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authorMaciej W. Rozycki <macro@linux-mips.org>2013-09-04 18:47:45 -0400
committerRalf Baechle <ralf@linux-mips.org>2013-09-05 14:38:28 -0400
commit8533966a6dba09d65a6764accdf44f3e96cddbfb (patch)
tree5f738205a2ab8783cba4cab256c0c10796637ec4 /arch
parentbf9621aaa0bb94dcd3b198ca14d3220310655eea (diff)
MIPS: DECstation HRT calibration bug fixes
This change corrects DECstation HRT calibration, by removing the following bugs: 1. Calibration period selection -- HZ / 10 has been chosen, however on DECstation computers, HZ never divides by 10, as the choice for HZ is among 128, 256 and 1024. The choice therefore results in a systematic calibration error, e.g. 6.25% for the usual choice of 128 for HZ: 128 / 10 * 10 = 120 (128 - 120) / 128 -> 6.25% The change therefore makes calibration use HZ / 8 that is always accurate for the HZ values available, getting rid of the systematic error. 2. Calibration starting point synchronisation -- the duration of a number of intervals between DS1287A periodic interrupt assertions is measured, however code does not ensure at the beginning that the interrupt has not been previously asserted. This results in a variable error of e.g. up to another 6.25% for the period of HZ / 8 (8.(3)% with the original HZ / 10 period) and the usual choice of 128 for HZ: 1 / 16 -> 6.25% 1 / 12 -> 8.(3)% The change therefore adds an initial call to ds1287_timer_state that clears any previous periodic interrupt pending. The same issue applies to both I/O ASIC counter and R4k CP0 timer calibration on DECstation systems as similar code is used in both cases and both pieces of code are covered by this fix. On an R3400 test system used this fix results in a change of the I/O ASIC clock frequency reported from values like: I/O ASIC clock frequency 23185830Hz to: I/O ASIC clock frequency 24999288Hz removing the miscalculation by 6.25% from the systematic error and (for the individual sample provided) a further 1.00% from the variable error, accordingly. The nominal I/O ASIC clock frequency is 25MHz on this system. Here's another result, with the fix applied, from a system that has both HRTs available (using an R4400 at 60MHz nominal): MIPS counter frequency 59999328Hz I/O ASIC clock frequency 24999432Hz Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5807/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/dec/time.c5
-rw-r--r--arch/mips/kernel/csrc-ioasic.c6
2 files changed, 6 insertions, 5 deletions
diff --git a/arch/mips/dec/time.c b/arch/mips/dec/time.c
index ea57f39e6736..56ebc7f2bede 100644
--- a/arch/mips/dec/time.c
+++ b/arch/mips/dec/time.c
@@ -126,12 +126,13 @@ int rtc_mips_set_mmss(unsigned long nowtime)
126void __init plat_time_init(void) 126void __init plat_time_init(void)
127{ 127{
128 u32 start, end; 128 u32 start, end;
129 int i = HZ / 10; 129 int i = HZ / 8;
130 130
131 /* Set up the rate of periodic DS1287 interrupts. */ 131 /* Set up the rate of periodic DS1287 interrupts. */
132 ds1287_set_base_clock(HZ); 132 ds1287_set_base_clock(HZ);
133 133
134 if (cpu_has_counter) { 134 if (cpu_has_counter) {
135 ds1287_timer_state();
135 while (!ds1287_timer_state()) 136 while (!ds1287_timer_state())
136 ; 137 ;
137 138
@@ -143,7 +144,7 @@ void __init plat_time_init(void)
143 144
144 end = read_c0_count(); 145 end = read_c0_count();
145 146
146 mips_hpt_frequency = (end - start) * 10; 147 mips_hpt_frequency = (end - start) * 8;
147 printk(KERN_INFO "MIPS counter frequency %dHz\n", 148 printk(KERN_INFO "MIPS counter frequency %dHz\n",
148 mips_hpt_frequency); 149 mips_hpt_frequency);
149 } else if (IOASIC) 150 } else if (IOASIC)
diff --git a/arch/mips/kernel/csrc-ioasic.c b/arch/mips/kernel/csrc-ioasic.c
index 0654bff9b69c..87e88feb4a25 100644
--- a/arch/mips/kernel/csrc-ioasic.c
+++ b/arch/mips/kernel/csrc-ioasic.c
@@ -41,9 +41,9 @@ void __init dec_ioasic_clocksource_init(void)
41{ 41{
42 unsigned int freq; 42 unsigned int freq;
43 u32 start, end; 43 u32 start, end;
44 int i = HZ / 10; 44 int i = HZ / 8;
45
46 45
46 ds1287_timer_state();
47 while (!ds1287_timer_state()) 47 while (!ds1287_timer_state())
48 ; 48 ;
49 49
@@ -55,7 +55,7 @@ void __init dec_ioasic_clocksource_init(void)
55 55
56 end = dec_ioasic_hpt_read(&clocksource_dec); 56 end = dec_ioasic_hpt_read(&clocksource_dec);
57 57
58 freq = (end - start) * 10; 58 freq = (end - start) * 8;
59 printk(KERN_INFO "I/O ASIC clock frequency %dHz\n", freq); 59 printk(KERN_INFO "I/O ASIC clock frequency %dHz\n", freq);
60 60
61 clocksource_dec.rating = 200 + freq / 10000000; 61 clocksource_dec.rating = 200 + freq / 10000000;