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authorLiu Gang <Gang.Liu@freescale.com>2011-11-12 07:02:28 -0500
committerKumar Gala <galak@kernel.crashing.org>2011-11-24 03:01:34 -0500
commit6ec4bedbf153a8ef71aeba99a40efef556b57798 (patch)
tree761f559ad55b2c72f01ce9c59280f2168a677358 /arch
parent91610d830dbc90ebf01fd255873d8277bf72d040 (diff)
fsl-rio: Split rio driver into two parts, RapidIO endpoint and message unit
The Freescale PowerPC RapidIO controller consists of a RapidIO endpoint and a RapidIO message unit(RMU). Or use RapidIO message manager(RMan) to replace the RMU in DPAA architecture. Therefore, we should split the code into two function modules according to the hardware architecture. Add new struct for RMU module, and new initialization function to set up RMU module. This policy is very conducive to adding new module like RMan, or adding multi-ports or message units support. Signed-off-by: Lian Minghuan <Minghuan.Lian@freescale.com> Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Acked-by: Alexandre Bounine <alexandre.bounine@idt.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/sysdev/Makefile2
-rw-r--r--arch/powerpc/sysdev/fsl_rio.c1152
-rw-r--r--arch/powerpc/sysdev/fsl_rio.h78
-rw-r--r--arch/powerpc/sysdev/fsl_rmu.c1163
4 files changed, 1267 insertions, 1128 deletions
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 84e13253aec5..8dea5935b21f 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -20,7 +20,7 @@ obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
20obj-$(CONFIG_FSL_GTM) += fsl_gtm.o 20obj-$(CONFIG_FSL_GTM) += fsl_gtm.o
21obj-$(CONFIG_FSL_85XX_CACHE_SRAM) += fsl_85xx_l2ctlr.o fsl_85xx_cache_sram.o 21obj-$(CONFIG_FSL_85XX_CACHE_SRAM) += fsl_85xx_l2ctlr.o fsl_85xx_cache_sram.o
22obj-$(CONFIG_SIMPLE_GPIO) += simple_gpio.o 22obj-$(CONFIG_SIMPLE_GPIO) += simple_gpio.o
23obj-$(CONFIG_FSL_RIO) += fsl_rio.o 23obj-$(CONFIG_FSL_RIO) += fsl_rio.o fsl_rmu.o
24obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o 24obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
25obj-$(CONFIG_QUICC_ENGINE) += qe_lib/ 25obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
26obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/ 26obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index 22ffccd8bef5..9484484c82c3 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -10,7 +10,7 @@
10 * - Added Port-Write message handling 10 * - Added Port-Write message handling
11 * - Added Machine Check exception handling 11 * - Added Machine Check exception handling
12 * 12 *
13 * Copyright (C) 2007, 2008, 2010 Freescale Semiconductor, Inc. 13 * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
14 * Zhang Wei <wei.zhang@freescale.com> 14 * Zhang Wei <wei.zhang@freescale.com>
15 * 15 *
16 * Copyright 2005 MontaVista Software, Inc. 16 * Copyright 2005 MontaVista Software, Inc.
@@ -28,240 +28,34 @@
28#include <linux/dma-mapping.h> 28#include <linux/dma-mapping.h>
29#include <linux/interrupt.h> 29#include <linux/interrupt.h>
30#include <linux/device.h> 30#include <linux/device.h>
31#include <linux/rio.h>
32#include <linux/rio_drv.h>
33#include <linux/of_platform.h> 31#include <linux/of_platform.h>
34#include <linux/delay.h> 32#include <linux/delay.h>
35#include <linux/slab.h> 33#include <linux/slab.h>
36#include <linux/kfifo.h>
37 34
38#include <asm/io.h> 35#include <linux/io.h>
36#include <linux/uaccess.h>
39#include <asm/machdep.h> 37#include <asm/machdep.h>
40#include <asm/uaccess.h>
41 38
42#undef DEBUG_PW /* Port-Write debugging */ 39#include "fsl_rio.h"
43 40
44/* RapidIO definition irq, which read from OF-tree */ 41#undef DEBUG_PW /* Port-Write debugging */
45#define IRQ_RIO_BELL(m) (((struct rio_priv *)(m->priv))->bellirq)
46#define IRQ_RIO_TX(m) (((struct rio_priv *)(m->priv))->txirq)
47#define IRQ_RIO_RX(m) (((struct rio_priv *)(m->priv))->rxirq)
48#define IRQ_RIO_PW(m) (((struct rio_priv *)(m->priv))->pwirq)
49
50#define IPWSR_CLEAR 0x98
51#define OMSR_CLEAR 0x1cb3
52#define IMSR_CLEAR 0x491
53#define IDSR_CLEAR 0x91
54#define ODSR_CLEAR 0x1c00
55#define LTLEECSR_ENABLE_ALL 0xFFC000FC
56#define ESCSR_CLEAR 0x07120204
57#define IECSR_CLEAR 0x80000000
58 42
59#define RIO_PORT1_EDCSR 0x0640 43#define RIO_PORT1_EDCSR 0x0640
60#define RIO_PORT2_EDCSR 0x0680 44#define RIO_PORT2_EDCSR 0x0680
61#define RIO_PORT1_IECSR 0x10130 45#define RIO_PORT1_IECSR 0x10130
62#define RIO_PORT2_IECSR 0x101B0 46#define RIO_PORT2_IECSR 0x101B0
63#define RIO_IM0SR 0x13064
64#define RIO_IM1SR 0x13164
65#define RIO_OM0SR 0x13004
66#define RIO_OM1SR 0x13104
67 47
68#define RIO_ATMU_REGS_OFFSET 0x10c00 48#define RIO_ATMU_REGS_OFFSET 0x10c00
69#define RIO_P_MSG_REGS_OFFSET 0x11000
70#define RIO_S_MSG_REGS_OFFSET 0x13000
71#define RIO_GCCSR 0x13c 49#define RIO_GCCSR 0x13c
72#define RIO_ESCSR 0x158 50#define RIO_ESCSR 0x158
51#define ESCSR_CLEAR 0x07120204
73#define RIO_PORT2_ESCSR 0x178 52#define RIO_PORT2_ESCSR 0x178
74#define RIO_CCSR 0x15c 53#define RIO_CCSR 0x15c
75#define RIO_LTLEDCSR 0x0608
76#define RIO_LTLEDCSR_IER 0x80000000 54#define RIO_LTLEDCSR_IER 0x80000000
77#define RIO_LTLEDCSR_PRT 0x01000000 55#define RIO_LTLEDCSR_PRT 0x01000000
78#define RIO_LTLEECSR 0x060c 56#define IECSR_CLEAR 0x80000000
79#define RIO_EPWISR 0x10010
80#define RIO_ISR_AACR 0x10120 57#define RIO_ISR_AACR 0x10120
81#define RIO_ISR_AACR_AA 0x1 /* Accept All ID */ 58#define RIO_ISR_AACR_AA 0x1 /* Accept All ID */
82#define RIO_MAINT_WIN_SIZE 0x400000
83#define RIO_DBELL_WIN_SIZE 0x1000
84
85#define RIO_MSG_OMR_MUI 0x00000002
86#define RIO_MSG_OSR_TE 0x00000080
87#define RIO_MSG_OSR_QOI 0x00000020
88#define RIO_MSG_OSR_QFI 0x00000010
89#define RIO_MSG_OSR_MUB 0x00000004
90#define RIO_MSG_OSR_EOMI 0x00000002
91#define RIO_MSG_OSR_QEI 0x00000001
92
93#define RIO_MSG_IMR_MI 0x00000002
94#define RIO_MSG_ISR_TE 0x00000080
95#define RIO_MSG_ISR_QFI 0x00000010
96#define RIO_MSG_ISR_DIQI 0x00000001
97
98#define RIO_IPWMR_SEN 0x00100000
99#define RIO_IPWMR_QFIE 0x00000100
100#define RIO_IPWMR_EIE 0x00000020
101#define RIO_IPWMR_CQ 0x00000002
102#define RIO_IPWMR_PWE 0x00000001
103
104#define RIO_IPWSR_QF 0x00100000
105#define RIO_IPWSR_TE 0x00000080
106#define RIO_IPWSR_QFI 0x00000010
107#define RIO_IPWSR_PWD 0x00000008
108#define RIO_IPWSR_PWB 0x00000004
109
110/* EPWISR Error match value */
111#define RIO_EPWISR_PINT1 0x80000000
112#define RIO_EPWISR_PINT2 0x40000000
113#define RIO_EPWISR_MU 0x00000002
114#define RIO_EPWISR_PW 0x00000001
115
116#define RIO_MSG_DESC_SIZE 32
117#define RIO_MSG_BUFFER_SIZE 4096
118#define RIO_MIN_TX_RING_SIZE 2
119#define RIO_MAX_TX_RING_SIZE 2048
120#define RIO_MIN_RX_RING_SIZE 2
121#define RIO_MAX_RX_RING_SIZE 2048
122
123#define DOORBELL_DMR_DI 0x00000002
124#define DOORBELL_DSR_TE 0x00000080
125#define DOORBELL_DSR_QFI 0x00000010
126#define DOORBELL_DSR_DIQI 0x00000001
127#define DOORBELL_TID_OFFSET 0x02
128#define DOORBELL_SID_OFFSET 0x04
129#define DOORBELL_INFO_OFFSET 0x06
130
131#define DOORBELL_MESSAGE_SIZE 0x08
132#define DBELL_SID(x) (*(u16 *)(x + DOORBELL_SID_OFFSET))
133#define DBELL_TID(x) (*(u16 *)(x + DOORBELL_TID_OFFSET))
134#define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET))
135
136struct rio_atmu_regs {
137 u32 rowtar;
138 u32 rowtear;
139 u32 rowbar;
140 u32 pad2;
141 u32 rowar;
142 u32 pad3[3];
143};
144
145struct rio_msg_regs {
146 u32 omr; /* 0xD_3000 - Outbound message 0 mode register */
147 u32 osr; /* 0xD_3004 - Outbound message 0 status register */
148 u32 pad1;
149 u32 odqdpar; /* 0xD_300C - Outbound message 0 descriptor queue
150 dequeue pointer address register */
151 u32 pad2;
152 u32 osar; /* 0xD_3014 - Outbound message 0 source address
153 register */
154 u32 odpr; /* 0xD_3018 - Outbound message 0 destination port
155 register */
156 u32 odatr; /* 0xD_301C - Outbound message 0 destination attributes
157 Register*/
158 u32 odcr; /* 0xD_3020 - Outbound message 0 double-word count
159 register */
160 u32 pad3;
161 u32 odqepar; /* 0xD_3028 - Outbound message 0 descriptor queue
162 enqueue pointer address register */
163 u32 pad4[13];
164 u32 imr; /* 0xD_3060 - Inbound message 0 mode register */
165 u32 isr; /* 0xD_3064 - Inbound message 0 status register */
166 u32 pad5;
167 u32 ifqdpar; /* 0xD_306C - Inbound message 0 frame queue dequeue
168 pointer address register*/
169 u32 pad6;
170 u32 ifqepar; /* 0xD_3074 - Inbound message 0 frame queue enqueue
171 pointer address register */
172 u32 pad7[226];
173 u32 odmr; /* 0xD_3400 - Outbound doorbell mode register */
174 u32 odsr; /* 0xD_3404 - Outbound doorbell status register */
175 u32 res0[4];
176 u32 oddpr; /* 0xD_3418 - Outbound doorbell destination port
177 register */
178 u32 oddatr; /* 0xD_341c - Outbound doorbell destination attributes
179 register */
180 u32 res1[3];
181 u32 odretcr; /* 0xD_342C - Outbound doorbell retry error threshold
182 configuration register */
183 u32 res2[12];
184 u32 dmr; /* 0xD_3460 - Inbound doorbell mode register */
185 u32 dsr; /* 0xD_3464 - Inbound doorbell status register */
186 u32 pad8;
187 u32 dqdpar; /* 0xD_346C - Inbound doorbell queue dequeue Pointer
188 address register */
189 u32 pad9;
190 u32 dqepar; /* 0xD_3474 - Inbound doorbell Queue enqueue pointer
191 address register */
192 u32 pad10[26];
193 u32 pwmr; /* 0xD_34E0 - Inbound port-write mode register */
194 u32 pwsr; /* 0xD_34E4 - Inbound port-write status register */
195 u32 epwqbar; /* 0xD_34E8 - Extended Port-Write Queue Base Address
196 register */
197 u32 pwqbar; /* 0xD_34EC - Inbound port-write queue base address
198 register */
199};
200
201struct rio_tx_desc {
202 u32 res1;
203 u32 saddr;
204 u32 dport;
205 u32 dattr;
206 u32 res2;
207 u32 res3;
208 u32 dwcnt;
209 u32 res4;
210};
211
212struct rio_dbell_ring {
213 void *virt;
214 dma_addr_t phys;
215};
216
217struct rio_msg_tx_ring {
218 void *virt;
219 dma_addr_t phys;
220 void *virt_buffer[RIO_MAX_TX_RING_SIZE];
221 dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE];
222 int tx_slot;
223 int size;
224 void *dev_id;
225};
226
227struct rio_msg_rx_ring {
228 void *virt;
229 dma_addr_t phys;
230 void *virt_buffer[RIO_MAX_RX_RING_SIZE];
231 int rx_slot;
232 int size;
233 void *dev_id;
234};
235
236struct rio_port_write_msg {
237 void *virt;
238 dma_addr_t phys;
239 u32 msg_count;
240 u32 err_count;
241 u32 discard_count;
242};
243
244struct rio_priv {
245 struct device *dev;
246 void __iomem *regs_win;
247 struct rio_atmu_regs __iomem *atmu_regs;
248 struct rio_atmu_regs __iomem *maint_atmu_regs;
249 struct rio_atmu_regs __iomem *dbell_atmu_regs;
250 void __iomem *dbell_win;
251 void __iomem *maint_win;
252 struct rio_msg_regs __iomem *msg_regs;
253 struct rio_dbell_ring dbell_ring;
254 struct rio_msg_tx_ring msg_tx_ring;
255 struct rio_msg_rx_ring msg_rx_ring;
256 struct rio_port_write_msg port_write_msg;
257 int bellirq;
258 int txirq;
259 int rxirq;
260 int pwirq;
261 struct work_struct pw_work;
262 struct kfifo pw_fifo;
263 spinlock_t pw_fifo_lock;
264};
265 59
266#define __fsl_read_rio_config(x, addr, err, op) \ 60#define __fsl_read_rio_config(x, addr, err, op) \
267 __asm__ __volatile__( \ 61 __asm__ __volatile__( \
@@ -279,7 +73,7 @@ struct rio_priv {
279 : "=r" (err), "=r" (x) \ 73 : "=r" (err), "=r" (x) \
280 : "b" (addr), "i" (-EFAULT), "0" (err)) 74 : "b" (addr), "i" (-EFAULT), "0" (err))
281 75
282static void __iomem *rio_regs_win; 76void __iomem *rio_regs_win;
283 77
284#ifdef CONFIG_E500 78#ifdef CONFIG_E500
285int fsl_rio_mcheck_exception(struct pt_regs *regs) 79int fsl_rio_mcheck_exception(struct pt_regs *regs)
@@ -311,42 +105,6 @@ EXPORT_SYMBOL_GPL(fsl_rio_mcheck_exception);
311#endif 105#endif
312 106
313/** 107/**
314 * fsl_rio_doorbell_send - Send a MPC85xx doorbell message
315 * @mport: RapidIO master port info
316 * @index: ID of RapidIO interface
317 * @destid: Destination ID of target device
318 * @data: 16-bit info field of RapidIO doorbell message
319 *
320 * Sends a MPC85xx doorbell message. Returns %0 on success or
321 * %-EINVAL on failure.
322 */
323static int fsl_rio_doorbell_send(struct rio_mport *mport,
324 int index, u16 destid, u16 data)
325{
326 struct rio_priv *priv = mport->priv;
327 pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n",
328 index, destid, data);
329 switch (mport->phy_type) {
330 case RIO_PHY_PARALLEL:
331 out_be32(&priv->dbell_atmu_regs->rowtar, destid << 22);
332 out_be16(priv->dbell_win, data);
333 break;
334 case RIO_PHY_SERIAL:
335 /* In the serial version silicons, such as MPC8548, MPC8641,
336 * below operations is must be.
337 */
338 out_be32(&priv->msg_regs->odmr, 0x00000000);
339 out_be32(&priv->msg_regs->odretcr, 0x00000004);
340 out_be32(&priv->msg_regs->oddpr, destid << 16);
341 out_be32(&priv->msg_regs->oddatr, data);
342 out_be32(&priv->msg_regs->odmr, 0x00000001);
343 break;
344 }
345
346 return 0;
347}
348
349/**
350 * fsl_local_config_read - Generate a MPC85xx local config space read 108 * fsl_local_config_read - Generate a MPC85xx local config space read
351 * @mport: RapidIO master port info 109 * @mport: RapidIO master port info
352 * @index: ID of RapdiIO interface 110 * @index: ID of RapdiIO interface
@@ -362,7 +120,7 @@ static int fsl_local_config_read(struct rio_mport *mport,
362{ 120{
363 struct rio_priv *priv = mport->priv; 121 struct rio_priv *priv = mport->priv;
364 pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index, 122 pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index,
365 offset); 123 offset);
366 *data = in_be32(priv->regs_win + offset); 124 *data = in_be32(priv->regs_win + offset);
367 125
368 return 0; 126 return 0;
@@ -384,8 +142,8 @@ static int fsl_local_config_write(struct rio_mport *mport,
384{ 142{
385 struct rio_priv *priv = mport->priv; 143 struct rio_priv *priv = mport->priv;
386 pr_debug 144 pr_debug
387 ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n", 145 ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n",
388 index, offset, data); 146 index, offset, data);
389 out_be32(priv->regs_win + offset, data); 147 out_be32(priv->regs_win + offset, data);
390 148
391 return 0; 149 return 0;
@@ -413,7 +171,8 @@ fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
413 u32 rval, err = 0; 171 u32 rval, err = 0;
414 172
415 pr_debug 173 pr_debug
416 ("fsl_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n", 174 ("fsl_rio_config_read:"
175 " index %d destid %d hopcount %d offset %8.8x len %d\n",
417 index, destid, hopcount, offset, len); 176 index, destid, hopcount, offset, len);
418 177
419 /* 16MB maintenance window possible */ 178 /* 16MB maintenance window possible */
@@ -423,7 +182,7 @@ fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
423 182
424 out_be32(&priv->maint_atmu_regs->rowtar, 183 out_be32(&priv->maint_atmu_regs->rowtar,
425 (destid << 22) | (hopcount << 12) | (offset >> 12)); 184 (destid << 22) | (hopcount << 12) | (offset >> 12));
426 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10)); 185 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
427 186
428 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1)); 187 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
429 switch (len) { 188 switch (len) {
@@ -470,7 +229,8 @@ fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
470 struct rio_priv *priv = mport->priv; 229 struct rio_priv *priv = mport->priv;
471 u8 *data; 230 u8 *data;
472 pr_debug 231 pr_debug
473 ("fsl_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n", 232 ("fsl_rio_config_write:"
233 "index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
474 index, destid, hopcount, offset, len, val); 234 index, destid, hopcount, offset, len, val);
475 235
476 /* 16MB maintenance windows possible */ 236 /* 16MB maintenance windows possible */
@@ -480,7 +240,7 @@ fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
480 240
481 out_be32(&priv->maint_atmu_regs->rowtar, 241 out_be32(&priv->maint_atmu_regs->rowtar,
482 (destid << 22) | (hopcount << 12) | (offset >> 12)); 242 (destid << 22) | (hopcount << 12) | (offset >> 12));
483 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10)); 243 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
484 244
485 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1)); 245 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
486 switch (len) { 246 switch (len) {
@@ -500,590 +260,7 @@ fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
500 return 0; 260 return 0;
501} 261}
502 262
503/** 263void fsl_rio_port_error_handler(struct rio_mport *port, int offset)
504 * fsl_add_outb_message - Add message to the MPC85xx outbound message queue
505 * @mport: Master port with outbound message queue
506 * @rdev: Target of outbound message
507 * @mbox: Outbound mailbox
508 * @buffer: Message to add to outbound queue
509 * @len: Length of message
510 *
511 * Adds the @buffer message to the MPC85xx outbound message queue. Returns
512 * %0 on success or %-EINVAL on failure.
513 */
514static int
515fsl_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
516 void *buffer, size_t len)
517{
518 struct rio_priv *priv = mport->priv;
519 u32 omr;
520 struct rio_tx_desc *desc = (struct rio_tx_desc *)priv->msg_tx_ring.virt
521 + priv->msg_tx_ring.tx_slot;
522 int ret = 0;
523
524 pr_debug("RIO: fsl_add_outb_message(): destid %4.4x mbox %d buffer " \
525 "%8.8x len %8.8x\n", rdev->destid, mbox, (int)buffer, len);
526
527 if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
528 ret = -EINVAL;
529 goto out;
530 }
531
532 /* Copy and clear rest of buffer */
533 memcpy(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot], buffer,
534 len);
535 if (len < (RIO_MAX_MSG_SIZE - 4))
536 memset(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot]
537 + len, 0, RIO_MAX_MSG_SIZE - len);
538
539 switch (mport->phy_type) {
540 case RIO_PHY_PARALLEL:
541 /* Set mbox field for message */
542 desc->dport = mbox & 0x3;
543
544 /* Enable EOMI interrupt, set priority, and set destid */
545 desc->dattr = 0x28000000 | (rdev->destid << 2);
546 break;
547 case RIO_PHY_SERIAL:
548 /* Set mbox field for message, and set destid */
549 desc->dport = (rdev->destid << 16) | (mbox & 0x3);
550
551 /* Enable EOMI interrupt and priority */
552 desc->dattr = 0x28000000;
553 break;
554 }
555
556 /* Set transfer size aligned to next power of 2 (in double words) */
557 desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len);
558
559 /* Set snooping and source buffer address */
560 desc->saddr = 0x00000004
561 | priv->msg_tx_ring.phys_buffer[priv->msg_tx_ring.tx_slot];
562
563 /* Increment enqueue pointer */
564 omr = in_be32(&priv->msg_regs->omr);
565 out_be32(&priv->msg_regs->omr, omr | RIO_MSG_OMR_MUI);
566
567 /* Go to next descriptor */
568 if (++priv->msg_tx_ring.tx_slot == priv->msg_tx_ring.size)
569 priv->msg_tx_ring.tx_slot = 0;
570
571 out:
572 return ret;
573}
574
575/**
576 * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler
577 * @irq: Linux interrupt number
578 * @dev_instance: Pointer to interrupt-specific data
579 *
580 * Handles outbound message interrupts. Executes a register outbound
581 * mailbox event handler and acks the interrupt occurrence.
582 */
583static irqreturn_t
584fsl_rio_tx_handler(int irq, void *dev_instance)
585{
586 int osr;
587 struct rio_mport *port = (struct rio_mport *)dev_instance;
588 struct rio_priv *priv = port->priv;
589
590 osr = in_be32(&priv->msg_regs->osr);
591
592 if (osr & RIO_MSG_OSR_TE) {
593 pr_info("RIO: outbound message transmission error\n");
594 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_TE);
595 goto out;
596 }
597
598 if (osr & RIO_MSG_OSR_QOI) {
599 pr_info("RIO: outbound message queue overflow\n");
600 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_QOI);
601 goto out;
602 }
603
604 if (osr & RIO_MSG_OSR_EOMI) {
605 u32 dqp = in_be32(&priv->msg_regs->odqdpar);
606 int slot = (dqp - priv->msg_tx_ring.phys) >> 5;
607 port->outb_msg[0].mcback(port, priv->msg_tx_ring.dev_id, -1,
608 slot);
609
610 /* Ack the end-of-message interrupt */
611 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_EOMI);
612 }
613
614 out:
615 return IRQ_HANDLED;
616}
617
618/**
619 * fsl_open_outb_mbox - Initialize MPC85xx outbound mailbox
620 * @mport: Master port implementing the outbound message unit
621 * @dev_id: Device specific pointer to pass on event
622 * @mbox: Mailbox to open
623 * @entries: Number of entries in the outbound mailbox ring
624 *
625 * Initializes buffer ring, request the outbound message interrupt,
626 * and enables the outbound message unit. Returns %0 on success and
627 * %-EINVAL or %-ENOMEM on failure.
628 */
629static int
630fsl_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
631{
632 int i, j, rc = 0;
633 struct rio_priv *priv = mport->priv;
634
635 if ((entries < RIO_MIN_TX_RING_SIZE) ||
636 (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) {
637 rc = -EINVAL;
638 goto out;
639 }
640
641 /* Initialize shadow copy ring */
642 priv->msg_tx_ring.dev_id = dev_id;
643 priv->msg_tx_ring.size = entries;
644
645 for (i = 0; i < priv->msg_tx_ring.size; i++) {
646 priv->msg_tx_ring.virt_buffer[i] =
647 dma_alloc_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
648 &priv->msg_tx_ring.phys_buffer[i], GFP_KERNEL);
649 if (!priv->msg_tx_ring.virt_buffer[i]) {
650 rc = -ENOMEM;
651 for (j = 0; j < priv->msg_tx_ring.size; j++)
652 if (priv->msg_tx_ring.virt_buffer[j])
653 dma_free_coherent(priv->dev,
654 RIO_MSG_BUFFER_SIZE,
655 priv->msg_tx_ring.
656 virt_buffer[j],
657 priv->msg_tx_ring.
658 phys_buffer[j]);
659 goto out;
660 }
661 }
662
663 /* Initialize outbound message descriptor ring */
664 priv->msg_tx_ring.virt = dma_alloc_coherent(priv->dev,
665 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
666 &priv->msg_tx_ring.phys, GFP_KERNEL);
667 if (!priv->msg_tx_ring.virt) {
668 rc = -ENOMEM;
669 goto out_dma;
670 }
671 memset(priv->msg_tx_ring.virt, 0,
672 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE);
673 priv->msg_tx_ring.tx_slot = 0;
674
675 /* Point dequeue/enqueue pointers at first entry in ring */
676 out_be32(&priv->msg_regs->odqdpar, priv->msg_tx_ring.phys);
677 out_be32(&priv->msg_regs->odqepar, priv->msg_tx_ring.phys);
678
679 /* Configure for snooping */
680 out_be32(&priv->msg_regs->osar, 0x00000004);
681
682 /* Clear interrupt status */
683 out_be32(&priv->msg_regs->osr, 0x000000b3);
684
685 /* Hook up outbound message handler */
686 rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0,
687 "msg_tx", (void *)mport);
688 if (rc < 0)
689 goto out_irq;
690
691 /*
692 * Configure outbound message unit
693 * Snooping
694 * Interrupts (all enabled, except QEIE)
695 * Chaining mode
696 * Disable
697 */
698 out_be32(&priv->msg_regs->omr, 0x00100220);
699
700 /* Set number of entries */
701 out_be32(&priv->msg_regs->omr,
702 in_be32(&priv->msg_regs->omr) |
703 ((get_bitmask_order(entries) - 2) << 12));
704
705 /* Now enable the unit */
706 out_be32(&priv->msg_regs->omr, in_be32(&priv->msg_regs->omr) | 0x1);
707
708 out:
709 return rc;
710
711 out_irq:
712 dma_free_coherent(priv->dev,
713 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
714 priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
715
716 out_dma:
717 for (i = 0; i < priv->msg_tx_ring.size; i++)
718 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
719 priv->msg_tx_ring.virt_buffer[i],
720 priv->msg_tx_ring.phys_buffer[i]);
721
722 return rc;
723}
724
725/**
726 * fsl_close_outb_mbox - Shut down MPC85xx outbound mailbox
727 * @mport: Master port implementing the outbound message unit
728 * @mbox: Mailbox to close
729 *
730 * Disables the outbound message unit, free all buffers, and
731 * frees the outbound message interrupt.
732 */
733static void fsl_close_outb_mbox(struct rio_mport *mport, int mbox)
734{
735 struct rio_priv *priv = mport->priv;
736 /* Disable inbound message unit */
737 out_be32(&priv->msg_regs->omr, 0);
738
739 /* Free ring */
740 dma_free_coherent(priv->dev,
741 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
742 priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
743
744 /* Free interrupt */
745 free_irq(IRQ_RIO_TX(mport), (void *)mport);
746}
747
748/**
749 * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler
750 * @irq: Linux interrupt number
751 * @dev_instance: Pointer to interrupt-specific data
752 *
753 * Handles inbound message interrupts. Executes a registered inbound
754 * mailbox event handler and acks the interrupt occurrence.
755 */
756static irqreturn_t
757fsl_rio_rx_handler(int irq, void *dev_instance)
758{
759 int isr;
760 struct rio_mport *port = (struct rio_mport *)dev_instance;
761 struct rio_priv *priv = port->priv;
762
763 isr = in_be32(&priv->msg_regs->isr);
764
765 if (isr & RIO_MSG_ISR_TE) {
766 pr_info("RIO: inbound message reception error\n");
767 out_be32((void *)&priv->msg_regs->isr, RIO_MSG_ISR_TE);
768 goto out;
769 }
770
771 /* XXX Need to check/dispatch until queue empty */
772 if (isr & RIO_MSG_ISR_DIQI) {
773 /*
774 * We implement *only* mailbox 0, but can receive messages
775 * for any mailbox/letter to that mailbox destination. So,
776 * make the callback with an unknown/invalid mailbox number
777 * argument.
778 */
779 port->inb_msg[0].mcback(port, priv->msg_rx_ring.dev_id, -1, -1);
780
781 /* Ack the queueing interrupt */
782 out_be32(&priv->msg_regs->isr, RIO_MSG_ISR_DIQI);
783 }
784
785 out:
786 return IRQ_HANDLED;
787}
788
789/**
790 * fsl_open_inb_mbox - Initialize MPC85xx inbound mailbox
791 * @mport: Master port implementing the inbound message unit
792 * @dev_id: Device specific pointer to pass on event
793 * @mbox: Mailbox to open
794 * @entries: Number of entries in the inbound mailbox ring
795 *
796 * Initializes buffer ring, request the inbound message interrupt,
797 * and enables the inbound message unit. Returns %0 on success
798 * and %-EINVAL or %-ENOMEM on failure.
799 */
800static int
801fsl_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
802{
803 int i, rc = 0;
804 struct rio_priv *priv = mport->priv;
805
806 if ((entries < RIO_MIN_RX_RING_SIZE) ||
807 (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) {
808 rc = -EINVAL;
809 goto out;
810 }
811
812 /* Initialize client buffer ring */
813 priv->msg_rx_ring.dev_id = dev_id;
814 priv->msg_rx_ring.size = entries;
815 priv->msg_rx_ring.rx_slot = 0;
816 for (i = 0; i < priv->msg_rx_ring.size; i++)
817 priv->msg_rx_ring.virt_buffer[i] = NULL;
818
819 /* Initialize inbound message ring */
820 priv->msg_rx_ring.virt = dma_alloc_coherent(priv->dev,
821 priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
822 &priv->msg_rx_ring.phys, GFP_KERNEL);
823 if (!priv->msg_rx_ring.virt) {
824 rc = -ENOMEM;
825 goto out;
826 }
827
828 /* Point dequeue/enqueue pointers at first entry in ring */
829 out_be32(&priv->msg_regs->ifqdpar, (u32) priv->msg_rx_ring.phys);
830 out_be32(&priv->msg_regs->ifqepar, (u32) priv->msg_rx_ring.phys);
831
832 /* Clear interrupt status */
833 out_be32(&priv->msg_regs->isr, 0x00000091);
834
835 /* Hook up inbound message handler */
836 rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0,
837 "msg_rx", (void *)mport);
838 if (rc < 0) {
839 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
840 priv->msg_tx_ring.virt_buffer[i],
841 priv->msg_tx_ring.phys_buffer[i]);
842 goto out;
843 }
844
845 /*
846 * Configure inbound message unit:
847 * Snooping
848 * 4KB max message size
849 * Unmask all interrupt sources
850 * Disable
851 */
852 out_be32(&priv->msg_regs->imr, 0x001b0060);
853
854 /* Set number of queue entries */
855 setbits32(&priv->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12);
856
857 /* Now enable the unit */
858 setbits32(&priv->msg_regs->imr, 0x1);
859
860 out:
861 return rc;
862}
863
864/**
865 * fsl_close_inb_mbox - Shut down MPC85xx inbound mailbox
866 * @mport: Master port implementing the inbound message unit
867 * @mbox: Mailbox to close
868 *
869 * Disables the inbound message unit, free all buffers, and
870 * frees the inbound message interrupt.
871 */
872static void fsl_close_inb_mbox(struct rio_mport *mport, int mbox)
873{
874 struct rio_priv *priv = mport->priv;
875 /* Disable inbound message unit */
876 out_be32(&priv->msg_regs->imr, 0);
877
878 /* Free ring */
879 dma_free_coherent(priv->dev, priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
880 priv->msg_rx_ring.virt, priv->msg_rx_ring.phys);
881
882 /* Free interrupt */
883 free_irq(IRQ_RIO_RX(mport), (void *)mport);
884}
885
886/**
887 * fsl_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
888 * @mport: Master port implementing the inbound message unit
889 * @mbox: Inbound mailbox number
890 * @buf: Buffer to add to inbound queue
891 *
892 * Adds the @buf buffer to the MPC85xx inbound message queue. Returns
893 * %0 on success or %-EINVAL on failure.
894 */
895static int fsl_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
896{
897 int rc = 0;
898 struct rio_priv *priv = mport->priv;
899
900 pr_debug("RIO: fsl_add_inb_buffer(), msg_rx_ring.rx_slot %d\n",
901 priv->msg_rx_ring.rx_slot);
902
903 if (priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot]) {
904 printk(KERN_ERR
905 "RIO: error adding inbound buffer %d, buffer exists\n",
906 priv->msg_rx_ring.rx_slot);
907 rc = -EINVAL;
908 goto out;
909 }
910
911 priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot] = buf;
912 if (++priv->msg_rx_ring.rx_slot == priv->msg_rx_ring.size)
913 priv->msg_rx_ring.rx_slot = 0;
914
915 out:
916 return rc;
917}
918
919/**
920 * fsl_get_inb_message - Fetch inbound message from the MPC85xx message unit
921 * @mport: Master port implementing the inbound message unit
922 * @mbox: Inbound mailbox number
923 *
924 * Gets the next available inbound message from the inbound message queue.
925 * A pointer to the message is returned on success or NULL on failure.
926 */
927static void *fsl_get_inb_message(struct rio_mport *mport, int mbox)
928{
929 struct rio_priv *priv = mport->priv;
930 u32 phys_buf, virt_buf;
931 void *buf = NULL;
932 int buf_idx;
933
934 phys_buf = in_be32(&priv->msg_regs->ifqdpar);
935
936 /* If no more messages, then bail out */
937 if (phys_buf == in_be32(&priv->msg_regs->ifqepar))
938 goto out2;
939
940 virt_buf = (u32) priv->msg_rx_ring.virt + (phys_buf
941 - priv->msg_rx_ring.phys);
942 buf_idx = (phys_buf - priv->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
943 buf = priv->msg_rx_ring.virt_buffer[buf_idx];
944
945 if (!buf) {
946 printk(KERN_ERR
947 "RIO: inbound message copy failed, no buffers\n");
948 goto out1;
949 }
950
951 /* Copy max message size, caller is expected to allocate that big */
952 memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE);
953
954 /* Clear the available buffer */
955 priv->msg_rx_ring.virt_buffer[buf_idx] = NULL;
956
957 out1:
958 setbits32(&priv->msg_regs->imr, RIO_MSG_IMR_MI);
959
960 out2:
961 return buf;
962}
963
964/**
965 * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler
966 * @irq: Linux interrupt number
967 * @dev_instance: Pointer to interrupt-specific data
968 *
969 * Handles doorbell interrupts. Parses a list of registered
970 * doorbell event handlers and executes a matching event handler.
971 */
972static irqreturn_t
973fsl_rio_dbell_handler(int irq, void *dev_instance)
974{
975 int dsr;
976 struct rio_mport *port = (struct rio_mport *)dev_instance;
977 struct rio_priv *priv = port->priv;
978
979 dsr = in_be32(&priv->msg_regs->dsr);
980
981 if (dsr & DOORBELL_DSR_TE) {
982 pr_info("RIO: doorbell reception error\n");
983 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_TE);
984 goto out;
985 }
986
987 if (dsr & DOORBELL_DSR_QFI) {
988 pr_info("RIO: doorbell queue full\n");
989 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_QFI);
990 }
991
992 /* XXX Need to check/dispatch until queue empty */
993 if (dsr & DOORBELL_DSR_DIQI) {
994 u32 dmsg =
995 (u32) priv->dbell_ring.virt +
996 (in_be32(&priv->msg_regs->dqdpar) & 0xfff);
997 struct rio_dbell *dbell;
998 int found = 0;
999
1000 pr_debug
1001 ("RIO: processing doorbell, sid %2.2x tid %2.2x info %4.4x\n",
1002 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
1003
1004 list_for_each_entry(dbell, &port->dbells, node) {
1005 if ((dbell->res->start <= DBELL_INF(dmsg)) &&
1006 (dbell->res->end >= DBELL_INF(dmsg))) {
1007 found = 1;
1008 break;
1009 }
1010 }
1011 if (found) {
1012 dbell->dinb(port, dbell->dev_id, DBELL_SID(dmsg), DBELL_TID(dmsg),
1013 DBELL_INF(dmsg));
1014 } else {
1015 pr_debug
1016 ("RIO: spurious doorbell, sid %2.2x tid %2.2x info %4.4x\n",
1017 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
1018 }
1019 setbits32(&priv->msg_regs->dmr, DOORBELL_DMR_DI);
1020 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_DIQI);
1021 }
1022
1023 out:
1024 return IRQ_HANDLED;
1025}
1026
1027/**
1028 * fsl_rio_doorbell_init - MPC85xx doorbell interface init
1029 * @mport: Master port implementing the inbound doorbell unit
1030 *
1031 * Initializes doorbell unit hardware and inbound DMA buffer
1032 * ring. Called from fsl_rio_setup(). Returns %0 on success
1033 * or %-ENOMEM on failure.
1034 */
1035static int fsl_rio_doorbell_init(struct rio_mport *mport)
1036{
1037 struct rio_priv *priv = mport->priv;
1038 int rc = 0;
1039
1040 /* Map outbound doorbell window immediately after maintenance window */
1041 priv->dbell_win = ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE,
1042 RIO_DBELL_WIN_SIZE);
1043 if (!priv->dbell_win) {
1044 printk(KERN_ERR
1045 "RIO: unable to map outbound doorbell window\n");
1046 rc = -ENOMEM;
1047 goto out;
1048 }
1049
1050 /* Initialize inbound doorbells */
1051 priv->dbell_ring.virt = dma_alloc_coherent(priv->dev, 512 *
1052 DOORBELL_MESSAGE_SIZE, &priv->dbell_ring.phys, GFP_KERNEL);
1053 if (!priv->dbell_ring.virt) {
1054 printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n");
1055 rc = -ENOMEM;
1056 iounmap(priv->dbell_win);
1057 goto out;
1058 }
1059
1060 /* Point dequeue/enqueue pointers at first entry in ring */
1061 out_be32(&priv->msg_regs->dqdpar, (u32) priv->dbell_ring.phys);
1062 out_be32(&priv->msg_regs->dqepar, (u32) priv->dbell_ring.phys);
1063
1064 /* Clear interrupt status */
1065 out_be32(&priv->msg_regs->dsr, 0x00000091);
1066
1067 /* Hook up doorbell handler */
1068 rc = request_irq(IRQ_RIO_BELL(mport), fsl_rio_dbell_handler, 0,
1069 "dbell_rx", (void *)mport);
1070 if (rc < 0) {
1071 iounmap(priv->dbell_win);
1072 dma_free_coherent(priv->dev, 512 * DOORBELL_MESSAGE_SIZE,
1073 priv->dbell_ring.virt, priv->dbell_ring.phys);
1074 printk(KERN_ERR
1075 "MPC85xx RIO: unable to request inbound doorbell irq");
1076 goto out;
1077 }
1078
1079 /* Configure doorbells for snooping, 512 entries, and enable */
1080 out_be32(&priv->msg_regs->dmr, 0x00108161);
1081
1082 out:
1083 return rc;
1084}
1085
1086static void port_error_handler(struct rio_mport *port, int offset)
1087{ 264{
1088 /*XXX: Error recovery is not implemented, we just clear errors */ 265 /*XXX: Error recovery is not implemented, we just clear errors */
1089 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0); 266 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
@@ -1098,263 +275,6 @@ static void port_error_handler(struct rio_mport *port, int offset)
1098 out_be32((u32 *)(rio_regs_win + RIO_PORT2_ESCSR), ESCSR_CLEAR); 275 out_be32((u32 *)(rio_regs_win + RIO_PORT2_ESCSR), ESCSR_CLEAR);
1099 } 276 }
1100} 277}
1101
1102static void msg_unit_error_handler(struct rio_mport *port)
1103{
1104 struct rio_priv *priv = port->priv;
1105
1106 /*XXX: Error recovery is not implemented, we just clear errors */
1107 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
1108
1109 out_be32((u32 *)(rio_regs_win + RIO_IM0SR), IMSR_CLEAR);
1110 out_be32((u32 *)(rio_regs_win + RIO_IM1SR), IMSR_CLEAR);
1111 out_be32((u32 *)(rio_regs_win + RIO_OM0SR), OMSR_CLEAR);
1112 out_be32((u32 *)(rio_regs_win + RIO_OM1SR), OMSR_CLEAR);
1113
1114 out_be32(&priv->msg_regs->odsr, ODSR_CLEAR);
1115 out_be32(&priv->msg_regs->dsr, IDSR_CLEAR);
1116
1117 out_be32(&priv->msg_regs->pwsr, IPWSR_CLEAR);
1118}
1119
1120/**
1121 * fsl_rio_port_write_handler - MPC85xx port write interrupt handler
1122 * @irq: Linux interrupt number
1123 * @dev_instance: Pointer to interrupt-specific data
1124 *
1125 * Handles port write interrupts. Parses a list of registered
1126 * port write event handlers and executes a matching event handler.
1127 */
1128static irqreturn_t
1129fsl_rio_port_write_handler(int irq, void *dev_instance)
1130{
1131 u32 ipwmr, ipwsr;
1132 struct rio_mport *port = (struct rio_mport *)dev_instance;
1133 struct rio_priv *priv = port->priv;
1134 u32 epwisr, tmp;
1135
1136 epwisr = in_be32(priv->regs_win + RIO_EPWISR);
1137 if (!(epwisr & RIO_EPWISR_PW))
1138 goto pw_done;
1139
1140 ipwmr = in_be32(&priv->msg_regs->pwmr);
1141 ipwsr = in_be32(&priv->msg_regs->pwsr);
1142
1143#ifdef DEBUG_PW
1144 pr_debug("PW Int->IPWMR: 0x%08x IPWSR: 0x%08x (", ipwmr, ipwsr);
1145 if (ipwsr & RIO_IPWSR_QF)
1146 pr_debug(" QF");
1147 if (ipwsr & RIO_IPWSR_TE)
1148 pr_debug(" TE");
1149 if (ipwsr & RIO_IPWSR_QFI)
1150 pr_debug(" QFI");
1151 if (ipwsr & RIO_IPWSR_PWD)
1152 pr_debug(" PWD");
1153 if (ipwsr & RIO_IPWSR_PWB)
1154 pr_debug(" PWB");
1155 pr_debug(" )\n");
1156#endif
1157 /* Schedule deferred processing if PW was received */
1158 if (ipwsr & RIO_IPWSR_QFI) {
1159 /* Save PW message (if there is room in FIFO),
1160 * otherwise discard it.
1161 */
1162 if (kfifo_avail(&priv->pw_fifo) >= RIO_PW_MSG_SIZE) {
1163 priv->port_write_msg.msg_count++;
1164 kfifo_in(&priv->pw_fifo, priv->port_write_msg.virt,
1165 RIO_PW_MSG_SIZE);
1166 } else {
1167 priv->port_write_msg.discard_count++;
1168 pr_debug("RIO: ISR Discarded Port-Write Msg(s) (%d)\n",
1169 priv->port_write_msg.discard_count);
1170 }
1171 /* Clear interrupt and issue Clear Queue command. This allows
1172 * another port-write to be received.
1173 */
1174 out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_QFI);
1175 out_be32(&priv->msg_regs->pwmr, ipwmr | RIO_IPWMR_CQ);
1176
1177 schedule_work(&priv->pw_work);
1178 }
1179
1180 if ((ipwmr & RIO_IPWMR_EIE) && (ipwsr & RIO_IPWSR_TE)) {
1181 priv->port_write_msg.err_count++;
1182 pr_debug("RIO: Port-Write Transaction Err (%d)\n",
1183 priv->port_write_msg.err_count);
1184 /* Clear Transaction Error: port-write controller should be
1185 * disabled when clearing this error
1186 */
1187 out_be32(&priv->msg_regs->pwmr, ipwmr & ~RIO_IPWMR_PWE);
1188 out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_TE);
1189 out_be32(&priv->msg_regs->pwmr, ipwmr);
1190 }
1191
1192 if (ipwsr & RIO_IPWSR_PWD) {
1193 priv->port_write_msg.discard_count++;
1194 pr_debug("RIO: Port Discarded Port-Write Msg(s) (%d)\n",
1195 priv->port_write_msg.discard_count);
1196 out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_PWD);
1197 }
1198
1199pw_done:
1200 if (epwisr & RIO_EPWISR_PINT1) {
1201 tmp = in_be32(priv->regs_win + RIO_LTLEDCSR);
1202 pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
1203 port_error_handler(port, 0);
1204 }
1205
1206 if (epwisr & RIO_EPWISR_PINT2) {
1207 tmp = in_be32(priv->regs_win + RIO_LTLEDCSR);
1208 pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
1209 port_error_handler(port, 1);
1210 }
1211
1212 if (epwisr & RIO_EPWISR_MU) {
1213 tmp = in_be32(priv->regs_win + RIO_LTLEDCSR);
1214 pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
1215 msg_unit_error_handler(port);
1216 }
1217
1218 return IRQ_HANDLED;
1219}
1220
1221static void fsl_pw_dpc(struct work_struct *work)
1222{
1223 struct rio_priv *priv = container_of(work, struct rio_priv, pw_work);
1224 unsigned long flags;
1225 u32 msg_buffer[RIO_PW_MSG_SIZE/sizeof(u32)];
1226
1227 /*
1228 * Process port-write messages
1229 */
1230 spin_lock_irqsave(&priv->pw_fifo_lock, flags);
1231 while (kfifo_out(&priv->pw_fifo, (unsigned char *)msg_buffer,
1232 RIO_PW_MSG_SIZE)) {
1233 /* Process one message */
1234 spin_unlock_irqrestore(&priv->pw_fifo_lock, flags);
1235#ifdef DEBUG_PW
1236 {
1237 u32 i;
1238 pr_debug("%s : Port-Write Message:", __func__);
1239 for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); i++) {
1240 if ((i%4) == 0)
1241 pr_debug("\n0x%02x: 0x%08x", i*4,
1242 msg_buffer[i]);
1243 else
1244 pr_debug(" 0x%08x", msg_buffer[i]);
1245 }
1246 pr_debug("\n");
1247 }
1248#endif
1249 /* Pass the port-write message to RIO core for processing */
1250 rio_inb_pwrite_handler((union rio_pw_msg *)msg_buffer);
1251 spin_lock_irqsave(&priv->pw_fifo_lock, flags);
1252 }
1253 spin_unlock_irqrestore(&priv->pw_fifo_lock, flags);
1254}
1255
1256/**
1257 * fsl_rio_pw_enable - enable/disable port-write interface init
1258 * @mport: Master port implementing the port write unit
1259 * @enable: 1=enable; 0=disable port-write message handling
1260 */
1261static int fsl_rio_pw_enable(struct rio_mport *mport, int enable)
1262{
1263 struct rio_priv *priv = mport->priv;
1264 u32 rval;
1265
1266 rval = in_be32(&priv->msg_regs->pwmr);
1267
1268 if (enable)
1269 rval |= RIO_IPWMR_PWE;
1270 else
1271 rval &= ~RIO_IPWMR_PWE;
1272
1273 out_be32(&priv->msg_regs->pwmr, rval);
1274
1275 return 0;
1276}
1277
1278/**
1279 * fsl_rio_port_write_init - MPC85xx port write interface init
1280 * @mport: Master port implementing the port write unit
1281 *
1282 * Initializes port write unit hardware and DMA buffer
1283 * ring. Called from fsl_rio_setup(). Returns %0 on success
1284 * or %-ENOMEM on failure.
1285 */
1286static int fsl_rio_port_write_init(struct rio_mport *mport)
1287{
1288 struct rio_priv *priv = mport->priv;
1289 int rc = 0;
1290
1291 /* Following configurations require a disabled port write controller */
1292 out_be32(&priv->msg_regs->pwmr,
1293 in_be32(&priv->msg_regs->pwmr) & ~RIO_IPWMR_PWE);
1294
1295 /* Initialize port write */
1296 priv->port_write_msg.virt = dma_alloc_coherent(priv->dev,
1297 RIO_PW_MSG_SIZE,
1298 &priv->port_write_msg.phys, GFP_KERNEL);
1299 if (!priv->port_write_msg.virt) {
1300 pr_err("RIO: unable allocate port write queue\n");
1301 return -ENOMEM;
1302 }
1303
1304 priv->port_write_msg.err_count = 0;
1305 priv->port_write_msg.discard_count = 0;
1306
1307 /* Point dequeue/enqueue pointers at first entry */
1308 out_be32(&priv->msg_regs->epwqbar, 0);
1309 out_be32(&priv->msg_regs->pwqbar, (u32) priv->port_write_msg.phys);
1310
1311 pr_debug("EIPWQBAR: 0x%08x IPWQBAR: 0x%08x\n",
1312 in_be32(&priv->msg_regs->epwqbar),
1313 in_be32(&priv->msg_regs->pwqbar));
1314
1315 /* Clear interrupt status IPWSR */
1316 out_be32(&priv->msg_regs->pwsr,
1317 (RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD));
1318
1319 /* Configure port write contoller for snooping enable all reporting,
1320 clear queue full */
1321 out_be32(&priv->msg_regs->pwmr,
1322 RIO_IPWMR_SEN | RIO_IPWMR_QFIE | RIO_IPWMR_EIE | RIO_IPWMR_CQ);
1323
1324
1325 /* Hook up port-write handler */
1326 rc = request_irq(IRQ_RIO_PW(mport), fsl_rio_port_write_handler,
1327 IRQF_SHARED, "port-write", (void *)mport);
1328 if (rc < 0) {
1329 pr_err("MPC85xx RIO: unable to request inbound doorbell irq");
1330 goto err_out;
1331 }
1332 /* Enable Error Interrupt */
1333 out_be32((u32 *)(rio_regs_win + RIO_LTLEECSR), LTLEECSR_ENABLE_ALL);
1334
1335 INIT_WORK(&priv->pw_work, fsl_pw_dpc);
1336 spin_lock_init(&priv->pw_fifo_lock);
1337 if (kfifo_alloc(&priv->pw_fifo, RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) {
1338 pr_err("FIFO allocation failed\n");
1339 rc = -ENOMEM;
1340 goto err_out_irq;
1341 }
1342
1343 pr_debug("IPWMR: 0x%08x IPWSR: 0x%08x\n",
1344 in_be32(&priv->msg_regs->pwmr),
1345 in_be32(&priv->msg_regs->pwsr));
1346
1347 return rc;
1348
1349err_out_irq:
1350 free_irq(IRQ_RIO_PW(mport), (void *)mport);
1351err_out:
1352 dma_free_coherent(priv->dev, RIO_PW_MSG_SIZE,
1353 priv->port_write_msg.virt,
1354 priv->port_write_msg.phys);
1355 return rc;
1356}
1357
1358static inline void fsl_rio_info(struct device *dev, u32 ccsr) 278static inline void fsl_rio_info(struct device *dev, u32 ccsr)
1359{ 279{
1360 const char *str; 280 const char *str;
@@ -1429,7 +349,8 @@ int fsl_rio_setup(struct platform_device *dev)
1429 dev->dev.of_node->full_name); 349 dev->dev.of_node->full_name);
1430 return -EFAULT; 350 return -EFAULT;
1431 } 351 }
1432 dev_info(&dev->dev, "Of-device full name %s\n", dev->dev.of_node->full_name); 352 dev_info(&dev->dev, "Of-device full name %s\n",
353 dev->dev.of_node->full_name);
1433 dev_info(&dev->dev, "Regs: %pR\n", &regs); 354 dev_info(&dev->dev, "Regs: %pR\n", &regs);
1434 355
1435 dt_range = of_get_property(dev->dev.of_node, "ranges", &rlen); 356 dt_range = of_get_property(dev->dev.of_node, "ranges", &rlen);
@@ -1469,15 +390,7 @@ int fsl_rio_setup(struct platform_device *dev)
1469 ops->lcwrite = fsl_local_config_write; 390 ops->lcwrite = fsl_local_config_write;
1470 ops->cread = fsl_rio_config_read; 391 ops->cread = fsl_rio_config_read;
1471 ops->cwrite = fsl_rio_config_write; 392 ops->cwrite = fsl_rio_config_write;
1472 ops->dsend = fsl_rio_doorbell_send;
1473 ops->pwenable = fsl_rio_pw_enable; 393 ops->pwenable = fsl_rio_pw_enable;
1474 ops->open_outb_mbox = fsl_open_outb_mbox;
1475 ops->open_inb_mbox = fsl_open_inb_mbox;
1476 ops->close_outb_mbox = fsl_close_outb_mbox;
1477 ops->close_inb_mbox = fsl_close_inb_mbox;
1478 ops->add_outb_message = fsl_add_outb_message;
1479 ops->add_inb_buffer = fsl_add_inb_buffer;
1480 ops->get_inb_message = fsl_get_inb_message;
1481 394
1482 port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL); 395 port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
1483 if (!port) { 396 if (!port) {
@@ -1507,16 +420,8 @@ int fsl_rio_setup(struct platform_device *dev)
1507 goto err_res; 420 goto err_res;
1508 } 421 }
1509 422
1510 priv->pwirq = irq_of_parse_and_map(dev->dev.of_node, 0); 423 priv->pwirq = irq_of_parse_and_map(dev->dev.of_node, 0);
1511 priv->bellirq = irq_of_parse_and_map(dev->dev.of_node, 2); 424 dev_info(&dev->dev, "pwirq: %d\n", priv->pwirq);
1512 priv->txirq = irq_of_parse_and_map(dev->dev.of_node, 3);
1513 priv->rxirq = irq_of_parse_and_map(dev->dev.of_node, 4);
1514 dev_info(&dev->dev, "pwirq: %d, bellirq: %d, txirq: %d, rxirq %d\n",
1515 priv->pwirq, priv->bellirq, priv->txirq, priv->rxirq);
1516
1517 rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
1518 rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0);
1519 rio_init_mbox_res(&port->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0);
1520 strcpy(port->name, "RIO0 mport"); 425 strcpy(port->name, "RIO0 mport");
1521 426
1522 priv->dev = &dev->dev; 427 priv->dev = &dev->dev;
@@ -1538,7 +443,7 @@ int fsl_rio_setup(struct platform_device *dev)
1538 /* Checking the port training status */ 443 /* Checking the port training status */
1539 if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) { 444 if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) {
1540 dev_err(&dev->dev, "Port is not ready. " 445 dev_err(&dev->dev, "Port is not ready. "
1541 "Try to restart connection...\n"); 446 "Try to restart connection...\n");
1542 switch (port->phy_type) { 447 switch (port->phy_type) {
1543 case RIO_PHY_SERIAL: 448 case RIO_PHY_SERIAL:
1544 /* Disable ports */ 449 /* Disable ports */
@@ -1582,10 +487,6 @@ int fsl_rio_setup(struct platform_device *dev)
1582 priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win 487 priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
1583 + RIO_ATMU_REGS_OFFSET); 488 + RIO_ATMU_REGS_OFFSET);
1584 priv->maint_atmu_regs = priv->atmu_regs + 1; 489 priv->maint_atmu_regs = priv->atmu_regs + 1;
1585 priv->dbell_atmu_regs = priv->atmu_regs + 2;
1586 priv->msg_regs = (struct rio_msg_regs *)(priv->regs_win +
1587 ((port->phy_type == RIO_PHY_SERIAL) ?
1588 RIO_S_MSG_REGS_OFFSET : RIO_P_MSG_REGS_OFFSET));
1589 490
1590 /* Set to receive any dist ID for serial RapidIO controller. */ 491 /* Set to receive any dist ID for serial RapidIO controller. */
1591 if (port->phy_type == RIO_PHY_SERIAL) 492 if (port->phy_type == RIO_PHY_SERIAL)
@@ -1598,11 +499,8 @@ int fsl_rio_setup(struct platform_device *dev)
1598 499
1599 priv->maint_win = ioremap(law_start, RIO_MAINT_WIN_SIZE); 500 priv->maint_win = ioremap(law_start, RIO_MAINT_WIN_SIZE);
1600 501
1601 /* Configure outbound doorbell window */ 502 fsl_rio_setup_rmu(port, dev->dev.of_node);
1602 out_be32(&priv->dbell_atmu_regs->rowbar, 503
1603 (law_start + RIO_MAINT_WIN_SIZE) >> 12);
1604 out_be32(&priv->dbell_atmu_regs->rowar, 0x8004200b); /* 4k */
1605 fsl_rio_doorbell_init(port);
1606 fsl_rio_port_write_init(port); 504 fsl_rio_port_write_init(port);
1607 505
1608 return 0; 506 return 0;
diff --git a/arch/powerpc/sysdev/fsl_rio.h b/arch/powerpc/sysdev/fsl_rio.h
new file mode 100644
index 000000000000..f888a1effd43
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_rio.h
@@ -0,0 +1,78 @@
1/*
2 * Freescale MPC85xx/MPC86xx RapidIO support
3 *
4 * Copyright 2009 Sysgo AG
5 * Thomas Moll <thomas.moll@sysgo.com>
6 * - fixed maintenance access routines, check for aligned access
7 *
8 * Copyright 2009 Integrated Device Technology, Inc.
9 * Alex Bounine <alexandre.bounine@idt.com>
10 * - Added Port-Write message handling
11 * - Added Machine Check exception handling
12 *
13 * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
14 * Zhang Wei <wei.zhang@freescale.com>
15 * Lian Minghuan-B31939 <Minghuan.Lian@freescale.com>
16 * Liu Gang <Gang.Liu@freescale.com>
17 *
18 * Copyright 2005 MontaVista Software, Inc.
19 * Matt Porter <mporter@kernel.crashing.org>
20 *
21 * This program is free software; you can redistribute it and/or modify it
22 * under the terms of the GNU General Public License as published by the
23 * Free Software Foundation; either version 2 of the License, or (at your
24 * option) any later version.
25 */
26
27#ifndef __FSL_RIO_H
28#define __FSL_RIO_H
29
30#include <linux/rio.h>
31#include <linux/rio_drv.h>
32#include <linux/kfifo.h>
33
34#define RIO_REGS_WIN(mport) (((struct rio_priv *)(mport->priv))->regs_win)
35
36#define RIO_MAINT_WIN_SIZE 0x400000
37#define RIO_LTLEDCSR 0x0608
38
39struct rio_atmu_regs {
40 u32 rowtar;
41 u32 rowtear;
42 u32 rowbar;
43 u32 pad2;
44 u32 rowar;
45 u32 pad3[3];
46};
47
48struct rio_port_write_msg {
49 void *virt;
50 dma_addr_t phys;
51 u32 msg_count;
52 u32 err_count;
53 u32 discard_count;
54};
55
56struct rio_priv {
57 struct device *dev;
58 void __iomem *regs_win;
59 struct rio_atmu_regs __iomem *atmu_regs;
60 struct rio_atmu_regs __iomem *maint_atmu_regs;
61 void __iomem *maint_win;
62 struct rio_port_write_msg port_write_msg;
63 int pwirq;
64 struct work_struct pw_work;
65 struct kfifo pw_fifo;
66 spinlock_t pw_fifo_lock;
67 void *rmm_handle; /* RapidIO message manager(unit) Handle */
68};
69
70extern void __iomem *rio_regs_win;
71
72extern int fsl_rio_setup_rmu(struct rio_mport *mport,
73 struct device_node *node);
74extern int fsl_rio_port_write_init(struct rio_mport *mport);
75extern int fsl_rio_pw_enable(struct rio_mport *mport, int enable);
76extern void fsl_rio_port_error_handler(struct rio_mport *port, int offset);
77
78#endif
diff --git a/arch/powerpc/sysdev/fsl_rmu.c b/arch/powerpc/sysdev/fsl_rmu.c
new file mode 100644
index 000000000000..0a3e6cff1837
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_rmu.c
@@ -0,0 +1,1163 @@
1/*
2 * Freescale MPC85xx/MPC86xx RapidIO RMU support
3 *
4 * Copyright 2009 Sysgo AG
5 * Thomas Moll <thomas.moll@sysgo.com>
6 * - fixed maintenance access routines, check for aligned access
7 *
8 * Copyright 2009 Integrated Device Technology, Inc.
9 * Alex Bounine <alexandre.bounine@idt.com>
10 * - Added Port-Write message handling
11 * - Added Machine Check exception handling
12 *
13 * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
14 * Zhang Wei <wei.zhang@freescale.com>
15 * Lian Minghuan-B31939 <Minghuan.Lian@freescale.com>
16 * Liu Gang <Gang.Liu@freescale.com>
17 *
18 * Copyright 2005 MontaVista Software, Inc.
19 * Matt Porter <mporter@kernel.crashing.org>
20 *
21 * This program is free software; you can redistribute it and/or modify it
22 * under the terms of the GNU General Public License as published by the
23 * Free Software Foundation; either version 2 of the License, or (at your
24 * option) any later version.
25 */
26
27#include <linux/types.h>
28#include <linux/dma-mapping.h>
29#include <linux/interrupt.h>
30#include <linux/of_platform.h>
31#include <linux/slab.h>
32
33#include "fsl_rio.h"
34
35#define GET_RMM_HANDLE(mport) \
36 (((struct rio_priv *)(mport->priv))->rmm_handle)
37
38/* RapidIO definition irq, which read from OF-tree */
39#define IRQ_RIO_PW(m) (((struct rio_priv *)(m->priv))->pwirq)
40#define IRQ_RIO_BELL(m) (((struct fsl_rmu *)(GET_RMM_HANDLE(m)))->bellirq)
41#define IRQ_RIO_TX(m) (((struct fsl_rmu *)(GET_RMM_HANDLE(m)))->txirq)
42#define IRQ_RIO_RX(m) (((struct fsl_rmu *)(GET_RMM_HANDLE(m)))->rxirq)
43
44#define RIO_MIN_TX_RING_SIZE 2
45#define RIO_MAX_TX_RING_SIZE 2048
46#define RIO_MIN_RX_RING_SIZE 2
47#define RIO_MAX_RX_RING_SIZE 2048
48
49#define RIO_IPWMR_SEN 0x00100000
50#define RIO_IPWMR_QFIE 0x00000100
51#define RIO_IPWMR_EIE 0x00000020
52#define RIO_IPWMR_CQ 0x00000002
53#define RIO_IPWMR_PWE 0x00000001
54
55#define RIO_IPWSR_QF 0x00100000
56#define RIO_IPWSR_TE 0x00000080
57#define RIO_IPWSR_QFI 0x00000010
58#define RIO_IPWSR_PWD 0x00000008
59#define RIO_IPWSR_PWB 0x00000004
60
61#define RIO_EPWISR 0x10010
62/* EPWISR Error match value */
63#define RIO_EPWISR_PINT1 0x80000000
64#define RIO_EPWISR_PINT2 0x40000000
65#define RIO_EPWISR_MU 0x00000002
66#define RIO_EPWISR_PW 0x00000001
67
68#define IPWSR_CLEAR 0x98
69#define OMSR_CLEAR 0x1cb3
70#define IMSR_CLEAR 0x491
71#define IDSR_CLEAR 0x91
72#define ODSR_CLEAR 0x1c00
73#define LTLEECSR_ENABLE_ALL 0xFFC000FC
74#define RIO_LTLEECSR 0x060c
75
76#define RIO_IM0SR 0x13064
77#define RIO_IM1SR 0x13164
78#define RIO_OM0SR 0x13004
79#define RIO_OM1SR 0x13104
80
81#define RIO_P_MSG_REGS_OFFSET 0x11000
82#define RIO_S_MSG_REGS_OFFSET 0x13000
83
84#define RIO_DBELL_WIN_SIZE 0x1000
85
86#define RIO_MSG_OMR_MUI 0x00000002
87#define RIO_MSG_OSR_TE 0x00000080
88#define RIO_MSG_OSR_QOI 0x00000020
89#define RIO_MSG_OSR_QFI 0x00000010
90#define RIO_MSG_OSR_MUB 0x00000004
91#define RIO_MSG_OSR_EOMI 0x00000002
92#define RIO_MSG_OSR_QEI 0x00000001
93
94#define RIO_MSG_IMR_MI 0x00000002
95#define RIO_MSG_ISR_TE 0x00000080
96#define RIO_MSG_ISR_QFI 0x00000010
97#define RIO_MSG_ISR_DIQI 0x00000001
98
99#define RIO_MSG_DESC_SIZE 32
100#define RIO_MSG_BUFFER_SIZE 4096
101
102#define DOORBELL_DMR_DI 0x00000002
103#define DOORBELL_DSR_TE 0x00000080
104#define DOORBELL_DSR_QFI 0x00000010
105#define DOORBELL_DSR_DIQI 0x00000001
106#define DOORBELL_TID_OFFSET 0x02
107#define DOORBELL_SID_OFFSET 0x04
108#define DOORBELL_INFO_OFFSET 0x06
109
110#define DOORBELL_MESSAGE_SIZE 0x08
111#define DBELL_SID(x) (*(u16 *)(x + DOORBELL_SID_OFFSET))
112#define DBELL_TID(x) (*(u16 *)(x + DOORBELL_TID_OFFSET))
113#define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET))
114
115struct rio_msg_regs {
116 u32 omr; /* 0xD_3000 - Outbound message 0 mode register */
117 u32 osr; /* 0xD_3004 - Outbound message 0 status register */
118 u32 pad1;
119 u32 odqdpar; /* 0xD_300C - Outbound message 0 descriptor queue
120 dequeue pointer address register */
121 u32 pad2;
122 u32 osar; /* 0xD_3014 - Outbound message 0 source address
123 register */
124 u32 odpr; /* 0xD_3018 - Outbound message 0 destination port
125 register */
126 u32 odatr; /* 0xD_301C - Outbound message 0 destination attributes
127 Register*/
128 u32 odcr; /* 0xD_3020 - Outbound message 0 double-word count
129 register */
130 u32 pad3;
131 u32 odqepar; /* 0xD_3028 - Outbound message 0 descriptor queue
132 enqueue pointer address register */
133 u32 pad4[13];
134 u32 imr; /* 0xD_3060 - Inbound message 0 mode register */
135 u32 isr; /* 0xD_3064 - Inbound message 0 status register */
136 u32 pad5;
137 u32 ifqdpar; /* 0xD_306C - Inbound message 0 frame queue dequeue
138 pointer address register*/
139 u32 pad6;
140 u32 ifqepar; /* 0xD_3074 - Inbound message 0 frame queue enqueue
141 pointer address register */
142 u32 pad7[226];
143 u32 odmr; /* 0xD_3400 - Outbound doorbell mode register */
144 u32 odsr; /* 0xD_3404 - Outbound doorbell status register */
145 u32 res0[4];
146 u32 oddpr; /* 0xD_3418 - Outbound doorbell destination port
147 register */
148 u32 oddatr; /* 0xD_341c - Outbound doorbell destination attributes
149 register */
150 u32 res1[3];
151 u32 odretcr; /* 0xD_342C - Outbound doorbell retry error threshold
152 configuration register */
153 u32 res2[12];
154 u32 dmr; /* 0xD_3460 - Inbound doorbell mode register */
155 u32 dsr; /* 0xD_3464 - Inbound doorbell status register */
156 u32 pad8;
157 u32 dqdpar; /* 0xD_346C - Inbound doorbell queue dequeue Pointer
158 address register */
159 u32 pad9;
160 u32 dqepar; /* 0xD_3474 - Inbound doorbell Queue enqueue pointer
161 address register */
162 u32 pad10[26];
163 u32 pwmr; /* 0xD_34E0 - Inbound port-write mode register */
164 u32 pwsr; /* 0xD_34E4 - Inbound port-write status register */
165 u32 epwqbar; /* 0xD_34E8 - Extended Port-Write Queue Base Address
166 register */
167 u32 pwqbar; /* 0xD_34EC - Inbound port-write queue base address
168 register */
169};
170
171struct rio_tx_desc {
172 u32 res1;
173 u32 saddr;
174 u32 dport;
175 u32 dattr;
176 u32 res2;
177 u32 res3;
178 u32 dwcnt;
179 u32 res4;
180};
181
182struct rio_dbell_ring {
183 void *virt;
184 dma_addr_t phys;
185};
186
187struct rio_msg_tx_ring {
188 void *virt;
189 dma_addr_t phys;
190 void *virt_buffer[RIO_MAX_TX_RING_SIZE];
191 dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE];
192 int tx_slot;
193 int size;
194 void *dev_id;
195};
196
197struct rio_msg_rx_ring {
198 void *virt;
199 dma_addr_t phys;
200 void *virt_buffer[RIO_MAX_RX_RING_SIZE];
201 int rx_slot;
202 int size;
203 void *dev_id;
204};
205
206struct fsl_rmu {
207 struct rio_atmu_regs __iomem *dbell_atmu_regs;
208 void __iomem *dbell_win;
209 struct rio_msg_regs __iomem *msg_regs;
210 struct rio_dbell_ring dbell_ring;
211 struct rio_msg_tx_ring msg_tx_ring;
212 struct rio_msg_rx_ring msg_rx_ring;
213 int bellirq;
214 int txirq;
215 int rxirq;
216};
217
218/**
219 * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler
220 * @irq: Linux interrupt number
221 * @dev_instance: Pointer to interrupt-specific data
222 *
223 * Handles outbound message interrupts. Executes a register outbound
224 * mailbox event handler and acks the interrupt occurrence.
225 */
226static irqreturn_t
227fsl_rio_tx_handler(int irq, void *dev_instance)
228{
229 int osr;
230 struct rio_mport *port = (struct rio_mport *)dev_instance;
231 struct fsl_rmu *rmu = GET_RMM_HANDLE(port);
232
233 osr = in_be32(&rmu->msg_regs->osr);
234
235 if (osr & RIO_MSG_OSR_TE) {
236 pr_info("RIO: outbound message transmission error\n");
237 out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_TE);
238 goto out;
239 }
240
241 if (osr & RIO_MSG_OSR_QOI) {
242 pr_info("RIO: outbound message queue overflow\n");
243 out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_QOI);
244 goto out;
245 }
246
247 if (osr & RIO_MSG_OSR_EOMI) {
248 u32 dqp = in_be32(&rmu->msg_regs->odqdpar);
249 int slot = (dqp - rmu->msg_tx_ring.phys) >> 5;
250 port->outb_msg[0].mcback(port, rmu->msg_tx_ring.dev_id, -1,
251 slot);
252
253 /* Ack the end-of-message interrupt */
254 out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_EOMI);
255 }
256
257out:
258 return IRQ_HANDLED;
259}
260
261/**
262 * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler
263 * @irq: Linux interrupt number
264 * @dev_instance: Pointer to interrupt-specific data
265 *
266 * Handles inbound message interrupts. Executes a registered inbound
267 * mailbox event handler and acks the interrupt occurrence.
268 */
269static irqreturn_t
270fsl_rio_rx_handler(int irq, void *dev_instance)
271{
272 int isr;
273 struct rio_mport *port = (struct rio_mport *)dev_instance;
274 struct fsl_rmu *rmu = GET_RMM_HANDLE(port);
275
276 isr = in_be32(&rmu->msg_regs->isr);
277
278 if (isr & RIO_MSG_ISR_TE) {
279 pr_info("RIO: inbound message reception error\n");
280 out_be32((void *)&rmu->msg_regs->isr, RIO_MSG_ISR_TE);
281 goto out;
282 }
283
284 /* XXX Need to check/dispatch until queue empty */
285 if (isr & RIO_MSG_ISR_DIQI) {
286 /*
287 * We implement *only* mailbox 0, but can receive messages
288 * for any mailbox/letter to that mailbox destination. So,
289 * make the callback with an unknown/invalid mailbox number
290 * argument.
291 */
292 port->inb_msg[0].mcback(port, rmu->msg_rx_ring.dev_id, -1, -1);
293
294 /* Ack the queueing interrupt */
295 out_be32(&rmu->msg_regs->isr, RIO_MSG_ISR_DIQI);
296 }
297
298out:
299 return IRQ_HANDLED;
300}
301
302/**
303 * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler
304 * @irq: Linux interrupt number
305 * @dev_instance: Pointer to interrupt-specific data
306 *
307 * Handles doorbell interrupts. Parses a list of registered
308 * doorbell event handlers and executes a matching event handler.
309 */
310static irqreturn_t
311fsl_rio_dbell_handler(int irq, void *dev_instance)
312{
313 int dsr;
314 struct rio_mport *port = (struct rio_mport *)dev_instance;
315 struct fsl_rmu *rmu = GET_RMM_HANDLE(port);
316
317 dsr = in_be32(&rmu->msg_regs->dsr);
318
319 if (dsr & DOORBELL_DSR_TE) {
320 pr_info("RIO: doorbell reception error\n");
321 out_be32(&rmu->msg_regs->dsr, DOORBELL_DSR_TE);
322 goto out;
323 }
324
325 if (dsr & DOORBELL_DSR_QFI) {
326 pr_info("RIO: doorbell queue full\n");
327 out_be32(&rmu->msg_regs->dsr, DOORBELL_DSR_QFI);
328 }
329
330 /* XXX Need to check/dispatch until queue empty */
331 if (dsr & DOORBELL_DSR_DIQI) {
332 u32 dmsg =
333 (u32) rmu->dbell_ring.virt +
334 (in_be32(&rmu->msg_regs->dqdpar) & 0xfff);
335 struct rio_dbell *dbell;
336 int found = 0;
337
338 pr_debug
339 ("RIO: processing doorbell,"
340 " sid %2.2x tid %2.2x info %4.4x\n",
341 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
342
343 list_for_each_entry(dbell, &port->dbells, node) {
344 if ((dbell->res->start <= DBELL_INF(dmsg)) &&
345 (dbell->res->end >= DBELL_INF(dmsg))) {
346 found = 1;
347 break;
348 }
349 }
350 if (found) {
351 dbell->dinb(port, dbell->dev_id,
352 DBELL_SID(dmsg),
353 DBELL_TID(dmsg), DBELL_INF(dmsg));
354 } else {
355 pr_debug
356 ("RIO: spurious doorbell,"
357 " sid %2.2x tid %2.2x info %4.4x\n",
358 DBELL_SID(dmsg), DBELL_TID(dmsg),
359 DBELL_INF(dmsg));
360 }
361 setbits32(&rmu->msg_regs->dmr, DOORBELL_DMR_DI);
362 out_be32(&rmu->msg_regs->dsr, DOORBELL_DSR_DIQI);
363 }
364
365out:
366 return IRQ_HANDLED;
367}
368
369void msg_unit_error_handler(struct rio_mport *port)
370{
371 struct fsl_rmu *rmu = GET_RMM_HANDLE(port);
372
373 /*XXX: Error recovery is not implemented, we just clear errors */
374 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
375
376 out_be32((u32 *)(rio_regs_win + RIO_IM0SR), IMSR_CLEAR);
377 out_be32((u32 *)(rio_regs_win + RIO_IM1SR), IMSR_CLEAR);
378 out_be32((u32 *)(rio_regs_win + RIO_OM0SR), OMSR_CLEAR);
379 out_be32((u32 *)(rio_regs_win + RIO_OM1SR), OMSR_CLEAR);
380
381 out_be32(&rmu->msg_regs->odsr, ODSR_CLEAR);
382 out_be32(&rmu->msg_regs->dsr, IDSR_CLEAR);
383
384 out_be32(&rmu->msg_regs->pwsr, IPWSR_CLEAR);
385}
386
387/**
388 * fsl_rio_port_write_handler - MPC85xx port write interrupt handler
389 * @irq: Linux interrupt number
390 * @dev_instance: Pointer to interrupt-specific data
391 *
392 * Handles port write interrupts. Parses a list of registered
393 * port write event handlers and executes a matching event handler.
394 */
395static irqreturn_t
396fsl_rio_port_write_handler(int irq, void *dev_instance)
397{
398 u32 ipwmr, ipwsr;
399 struct rio_mport *port = (struct rio_mport *)dev_instance;
400 struct rio_priv *priv = port->priv;
401 struct fsl_rmu *rmu;
402 u32 epwisr, tmp;
403
404 rmu = GET_RMM_HANDLE(port);
405 epwisr = in_be32(priv->regs_win + RIO_EPWISR);
406 if (!(epwisr & RIO_EPWISR_PW))
407 goto pw_done;
408
409 ipwmr = in_be32(&rmu->msg_regs->pwmr);
410 ipwsr = in_be32(&rmu->msg_regs->pwsr);
411
412#ifdef DEBUG_PW
413 pr_debug("PW Int->IPWMR: 0x%08x IPWSR: 0x%08x (", ipwmr, ipwsr);
414 if (ipwsr & RIO_IPWSR_QF)
415 pr_debug(" QF");
416 if (ipwsr & RIO_IPWSR_TE)
417 pr_debug(" TE");
418 if (ipwsr & RIO_IPWSR_QFI)
419 pr_debug(" QFI");
420 if (ipwsr & RIO_IPWSR_PWD)
421 pr_debug(" PWD");
422 if (ipwsr & RIO_IPWSR_PWB)
423 pr_debug(" PWB");
424 pr_debug(" )\n");
425#endif
426 /* Schedule deferred processing if PW was received */
427 if (ipwsr & RIO_IPWSR_QFI) {
428 /* Save PW message (if there is room in FIFO),
429 * otherwise discard it.
430 */
431 if (kfifo_avail(&priv->pw_fifo) >= RIO_PW_MSG_SIZE) {
432 priv->port_write_msg.msg_count++;
433 kfifo_in(&priv->pw_fifo, priv->port_write_msg.virt,
434 RIO_PW_MSG_SIZE);
435 } else {
436 priv->port_write_msg.discard_count++;
437 pr_debug("RIO: ISR Discarded Port-Write Msg(s) (%d)\n",
438 priv->port_write_msg.discard_count);
439 }
440 /* Clear interrupt and issue Clear Queue command. This allows
441 * another port-write to be received.
442 */
443 out_be32(&rmu->msg_regs->pwsr, RIO_IPWSR_QFI);
444 out_be32(&rmu->msg_regs->pwmr, ipwmr | RIO_IPWMR_CQ);
445
446 schedule_work(&priv->pw_work);
447 }
448
449 if ((ipwmr & RIO_IPWMR_EIE) && (ipwsr & RIO_IPWSR_TE)) {
450 priv->port_write_msg.err_count++;
451 pr_debug("RIO: Port-Write Transaction Err (%d)\n",
452 priv->port_write_msg.err_count);
453 /* Clear Transaction Error: port-write controller should be
454 * disabled when clearing this error
455 */
456 out_be32(&rmu->msg_regs->pwmr, ipwmr & ~RIO_IPWMR_PWE);
457 out_be32(&rmu->msg_regs->pwsr, RIO_IPWSR_TE);
458 out_be32(&rmu->msg_regs->pwmr, ipwmr);
459 }
460
461 if (ipwsr & RIO_IPWSR_PWD) {
462 priv->port_write_msg.discard_count++;
463 pr_debug("RIO: Port Discarded Port-Write Msg(s) (%d)\n",
464 priv->port_write_msg.discard_count);
465 out_be32(&rmu->msg_regs->pwsr, RIO_IPWSR_PWD);
466 }
467
468pw_done:
469 if (epwisr & RIO_EPWISR_PINT1) {
470 tmp = in_be32(priv->regs_win + RIO_LTLEDCSR);
471 pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
472 fsl_rio_port_error_handler(port, 0);
473 }
474
475 if (epwisr & RIO_EPWISR_PINT2) {
476 tmp = in_be32(priv->regs_win + RIO_LTLEDCSR);
477 pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
478 fsl_rio_port_error_handler(port, 1);
479 }
480
481 if (epwisr & RIO_EPWISR_MU) {
482 tmp = in_be32(priv->regs_win + RIO_LTLEDCSR);
483 pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
484 msg_unit_error_handler(port);
485 }
486
487 return IRQ_HANDLED;
488}
489
490static void fsl_pw_dpc(struct work_struct *work)
491{
492 struct rio_priv *priv = container_of(work, struct rio_priv, pw_work);
493 unsigned long flags;
494 u32 msg_buffer[RIO_PW_MSG_SIZE/sizeof(u32)];
495
496 /*
497 * Process port-write messages
498 */
499 spin_lock_irqsave(&priv->pw_fifo_lock, flags);
500 while (kfifo_out(&priv->pw_fifo, (unsigned char *)msg_buffer,
501 RIO_PW_MSG_SIZE)) {
502 /* Process one message */
503 spin_unlock_irqrestore(&priv->pw_fifo_lock, flags);
504#ifdef DEBUG_PW
505 {
506 u32 i;
507 pr_debug("%s : Port-Write Message:", __func__);
508 for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); i++) {
509 if ((i%4) == 0)
510 pr_debug("\n0x%02x: 0x%08x", i*4,
511 msg_buffer[i]);
512 else
513 pr_debug(" 0x%08x", msg_buffer[i]);
514 }
515 pr_debug("\n");
516 }
517#endif
518 /* Pass the port-write message to RIO core for processing */
519 rio_inb_pwrite_handler((union rio_pw_msg *)msg_buffer);
520 spin_lock_irqsave(&priv->pw_fifo_lock, flags);
521 }
522 spin_unlock_irqrestore(&priv->pw_fifo_lock, flags);
523}
524
525/**
526 * fsl_rio_pw_enable - enable/disable port-write interface init
527 * @mport: Master port implementing the port write unit
528 * @enable: 1=enable; 0=disable port-write message handling
529 */
530int fsl_rio_pw_enable(struct rio_mport *mport, int enable)
531{
532 struct fsl_rmu *rmu;
533 u32 rval;
534
535 rmu = GET_RMM_HANDLE(mport);
536
537 rval = in_be32(&rmu->msg_regs->pwmr);
538
539 if (enable)
540 rval |= RIO_IPWMR_PWE;
541 else
542 rval &= ~RIO_IPWMR_PWE;
543
544 out_be32(&rmu->msg_regs->pwmr, rval);
545
546 return 0;
547}
548
549/**
550 * fsl_rio_port_write_init - MPC85xx port write interface init
551 * @mport: Master port implementing the port write unit
552 *
553 * Initializes port write unit hardware and DMA buffer
554 * ring. Called from fsl_rio_setup(). Returns %0 on success
555 * or %-ENOMEM on failure.
556 */
557
558int fsl_rio_port_write_init(struct rio_mport *mport)
559{
560 struct rio_priv *priv = mport->priv;
561 struct fsl_rmu *rmu;
562 int rc = 0;
563
564 rmu = GET_RMM_HANDLE(mport);
565
566 /* Following configurations require a disabled port write controller */
567 out_be32(&rmu->msg_regs->pwmr,
568 in_be32(&rmu->msg_regs->pwmr) & ~RIO_IPWMR_PWE);
569
570 /* Initialize port write */
571 priv->port_write_msg.virt = dma_alloc_coherent(priv->dev,
572 RIO_PW_MSG_SIZE,
573 &priv->port_write_msg.phys, GFP_KERNEL);
574 if (!priv->port_write_msg.virt) {
575 pr_err("RIO: unable allocate port write queue\n");
576 return -ENOMEM;
577 }
578
579 priv->port_write_msg.err_count = 0;
580 priv->port_write_msg.discard_count = 0;
581
582 /* Point dequeue/enqueue pointers at first entry */
583 out_be32(&rmu->msg_regs->epwqbar, 0);
584 out_be32(&rmu->msg_regs->pwqbar, (u32) priv->port_write_msg.phys);
585
586 pr_debug("EIPWQBAR: 0x%08x IPWQBAR: 0x%08x\n",
587 in_be32(&rmu->msg_regs->epwqbar),
588 in_be32(&rmu->msg_regs->pwqbar));
589
590 /* Clear interrupt status IPWSR */
591 out_be32(&rmu->msg_regs->pwsr,
592 (RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD));
593
594 /* Configure port write contoller for snooping enable all reporting,
595 clear queue full */
596 out_be32(&rmu->msg_regs->pwmr,
597 RIO_IPWMR_SEN | RIO_IPWMR_QFIE | RIO_IPWMR_EIE | RIO_IPWMR_CQ);
598
599
600 /* Hook up port-write handler */
601 rc = request_irq(IRQ_RIO_PW(mport), fsl_rio_port_write_handler,
602 IRQF_SHARED, "port-write", (void *)mport);
603 if (rc < 0) {
604 pr_err("MPC85xx RIO: unable to request inbound doorbell irq");
605 goto err_out;
606 }
607 /* Enable Error Interrupt */
608 out_be32((u32 *)(rio_regs_win + RIO_LTLEECSR), LTLEECSR_ENABLE_ALL);
609
610 INIT_WORK(&priv->pw_work, fsl_pw_dpc);
611 spin_lock_init(&priv->pw_fifo_lock);
612 if (kfifo_alloc(&priv->pw_fifo, RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) {
613 pr_err("FIFO allocation failed\n");
614 rc = -ENOMEM;
615 goto err_out_irq;
616 }
617
618 pr_debug("IPWMR: 0x%08x IPWSR: 0x%08x\n",
619 in_be32(&rmu->msg_regs->pwmr),
620 in_be32(&rmu->msg_regs->pwsr));
621
622 return rc;
623
624err_out_irq:
625 free_irq(IRQ_RIO_PW(mport), (void *)mport);
626err_out:
627 dma_free_coherent(priv->dev, RIO_PW_MSG_SIZE,
628 priv->port_write_msg.virt,
629 priv->port_write_msg.phys);
630 return rc;
631}
632
633/**
634 * fsl_rio_doorbell_send - Send a MPC85xx doorbell message
635 * @mport: RapidIO master port info
636 * @index: ID of RapidIO interface
637 * @destid: Destination ID of target device
638 * @data: 16-bit info field of RapidIO doorbell message
639 *
640 * Sends a MPC85xx doorbell message. Returns %0 on success or
641 * %-EINVAL on failure.
642 */
643static int fsl_rio_doorbell_send(struct rio_mport *mport,
644 int index, u16 destid, u16 data)
645{
646 struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
647
648 pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n",
649 index, destid, data);
650 switch (mport->phy_type) {
651 case RIO_PHY_PARALLEL:
652 out_be32(&rmu->dbell_atmu_regs->rowtar, destid << 22);
653 out_be16(rmu->dbell_win, data);
654 break;
655 case RIO_PHY_SERIAL:
656 /* In the serial version silicons, such as MPC8548, MPC8641,
657 * below operations is must be.
658 */
659 out_be32(&rmu->msg_regs->odmr, 0x00000000);
660 out_be32(&rmu->msg_regs->odretcr, 0x00000004);
661 out_be32(&rmu->msg_regs->oddpr, destid << 16);
662 out_be32(&rmu->msg_regs->oddatr, data);
663 out_be32(&rmu->msg_regs->odmr, 0x00000001);
664 break;
665 }
666
667 return 0;
668}
669
670/**
671 * fsl_add_outb_message - Add message to the MPC85xx outbound message queue
672 * @mport: Master port with outbound message queue
673 * @rdev: Target of outbound message
674 * @mbox: Outbound mailbox
675 * @buffer: Message to add to outbound queue
676 * @len: Length of message
677 *
678 * Adds the @buffer message to the MPC85xx outbound message queue. Returns
679 * %0 on success or %-EINVAL on failure.
680 */
681static int
682fsl_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
683 void *buffer, size_t len)
684{
685 struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
686 u32 omr;
687 struct rio_tx_desc *desc = (struct rio_tx_desc *)rmu->msg_tx_ring.virt
688 + rmu->msg_tx_ring.tx_slot;
689 int ret = 0;
690
691 pr_debug("RIO: fsl_add_outb_message(): destid %4.4x mbox %d buffer " \
692 "%8.8x len %8.8x\n", rdev->destid, mbox, (int)buffer, len);
693
694 if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
695 ret = -EINVAL;
696 goto out;
697 }
698
699 /* Copy and clear rest of buffer */
700 memcpy(rmu->msg_tx_ring.virt_buffer[rmu->msg_tx_ring.tx_slot], buffer,
701 len);
702 if (len < (RIO_MAX_MSG_SIZE - 4))
703 memset(rmu->msg_tx_ring.virt_buffer[rmu->msg_tx_ring.tx_slot]
704 + len, 0, RIO_MAX_MSG_SIZE - len);
705
706 switch (mport->phy_type) {
707 case RIO_PHY_PARALLEL:
708 /* Set mbox field for message */
709 desc->dport = mbox & 0x3;
710
711 /* Enable EOMI interrupt, set priority, and set destid */
712 desc->dattr = 0x28000000 | (rdev->destid << 2);
713 break;
714 case RIO_PHY_SERIAL:
715 /* Set mbox field for message, and set destid */
716 desc->dport = (rdev->destid << 16) | (mbox & 0x3);
717
718 /* Enable EOMI interrupt and priority */
719 desc->dattr = 0x28000000;
720 break;
721 }
722
723 /* Set transfer size aligned to next power of 2 (in double words) */
724 desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len);
725
726 /* Set snooping and source buffer address */
727 desc->saddr = 0x00000004
728 | rmu->msg_tx_ring.phys_buffer[rmu->msg_tx_ring.tx_slot];
729
730 /* Increment enqueue pointer */
731 omr = in_be32(&rmu->msg_regs->omr);
732 out_be32(&rmu->msg_regs->omr, omr | RIO_MSG_OMR_MUI);
733
734 /* Go to next descriptor */
735 if (++rmu->msg_tx_ring.tx_slot == rmu->msg_tx_ring.size)
736 rmu->msg_tx_ring.tx_slot = 0;
737
738out:
739 return ret;
740}
741
742/**
743 * fsl_open_outb_mbox - Initialize MPC85xx outbound mailbox
744 * @mport: Master port implementing the outbound message unit
745 * @dev_id: Device specific pointer to pass on event
746 * @mbox: Mailbox to open
747 * @entries: Number of entries in the outbound mailbox ring
748 *
749 * Initializes buffer ring, request the outbound message interrupt,
750 * and enables the outbound message unit. Returns %0 on success and
751 * %-EINVAL or %-ENOMEM on failure.
752 */
753static int
754fsl_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
755{
756 int i, j, rc = 0;
757 struct rio_priv *priv = mport->priv;
758 struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
759
760 if ((entries < RIO_MIN_TX_RING_SIZE) ||
761 (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) {
762 rc = -EINVAL;
763 goto out;
764 }
765
766 /* Initialize shadow copy ring */
767 rmu->msg_tx_ring.dev_id = dev_id;
768 rmu->msg_tx_ring.size = entries;
769
770 for (i = 0; i < rmu->msg_tx_ring.size; i++) {
771 rmu->msg_tx_ring.virt_buffer[i] =
772 dma_alloc_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
773 &rmu->msg_tx_ring.phys_buffer[i], GFP_KERNEL);
774 if (!rmu->msg_tx_ring.virt_buffer[i]) {
775 rc = -ENOMEM;
776 for (j = 0; j < rmu->msg_tx_ring.size; j++)
777 if (rmu->msg_tx_ring.virt_buffer[j])
778 dma_free_coherent(priv->dev,
779 RIO_MSG_BUFFER_SIZE,
780 rmu->msg_tx_ring.
781 virt_buffer[j],
782 rmu->msg_tx_ring.
783 phys_buffer[j]);
784 goto out;
785 }
786 }
787
788 /* Initialize outbound message descriptor ring */
789 rmu->msg_tx_ring.virt = dma_alloc_coherent(priv->dev,
790 rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
791 &rmu->msg_tx_ring.phys, GFP_KERNEL);
792 if (!rmu->msg_tx_ring.virt) {
793 rc = -ENOMEM;
794 goto out_dma;
795 }
796 memset(rmu->msg_tx_ring.virt, 0,
797 rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE);
798 rmu->msg_tx_ring.tx_slot = 0;
799
800 /* Point dequeue/enqueue pointers at first entry in ring */
801 out_be32(&rmu->msg_regs->odqdpar, rmu->msg_tx_ring.phys);
802 out_be32(&rmu->msg_regs->odqepar, rmu->msg_tx_ring.phys);
803
804 /* Configure for snooping */
805 out_be32(&rmu->msg_regs->osar, 0x00000004);
806
807 /* Clear interrupt status */
808 out_be32(&rmu->msg_regs->osr, 0x000000b3);
809
810 /* Hook up outbound message handler */
811 rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0,
812 "msg_tx", (void *)mport);
813 if (rc < 0)
814 goto out_irq;
815
816 /*
817 * Configure outbound message unit
818 * Snooping
819 * Interrupts (all enabled, except QEIE)
820 * Chaining mode
821 * Disable
822 */
823 out_be32(&rmu->msg_regs->omr, 0x00100220);
824
825 /* Set number of entries */
826 out_be32(&rmu->msg_regs->omr,
827 in_be32(&rmu->msg_regs->omr) |
828 ((get_bitmask_order(entries) - 2) << 12));
829
830 /* Now enable the unit */
831 out_be32(&rmu->msg_regs->omr, in_be32(&rmu->msg_regs->omr) | 0x1);
832
833out:
834 return rc;
835
836out_irq:
837 dma_free_coherent(priv->dev,
838 rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
839 rmu->msg_tx_ring.virt, rmu->msg_tx_ring.phys);
840
841out_dma:
842 for (i = 0; i < rmu->msg_tx_ring.size; i++)
843 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
844 rmu->msg_tx_ring.virt_buffer[i],
845 rmu->msg_tx_ring.phys_buffer[i]);
846
847 return rc;
848}
849
850/**
851 * fsl_close_outb_mbox - Shut down MPC85xx outbound mailbox
852 * @mport: Master port implementing the outbound message unit
853 * @mbox: Mailbox to close
854 *
855 * Disables the outbound message unit, free all buffers, and
856 * frees the outbound message interrupt.
857 */
858static void fsl_close_outb_mbox(struct rio_mport *mport, int mbox)
859{
860 struct rio_priv *priv = mport->priv;
861 struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
862
863 /* Disable inbound message unit */
864 out_be32(&rmu->msg_regs->omr, 0);
865
866 /* Free ring */
867 dma_free_coherent(priv->dev,
868 rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
869 rmu->msg_tx_ring.virt, rmu->msg_tx_ring.phys);
870
871 /* Free interrupt */
872 free_irq(IRQ_RIO_TX(mport), (void *)mport);
873}
874
875/**
876 * fsl_open_inb_mbox - Initialize MPC85xx inbound mailbox
877 * @mport: Master port implementing the inbound message unit
878 * @dev_id: Device specific pointer to pass on event
879 * @mbox: Mailbox to open
880 * @entries: Number of entries in the inbound mailbox ring
881 *
882 * Initializes buffer ring, request the inbound message interrupt,
883 * and enables the inbound message unit. Returns %0 on success
884 * and %-EINVAL or %-ENOMEM on failure.
885 */
886static int
887fsl_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
888{
889 int i, rc = 0;
890 struct rio_priv *priv = mport->priv;
891 struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
892
893 if ((entries < RIO_MIN_RX_RING_SIZE) ||
894 (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) {
895 rc = -EINVAL;
896 goto out;
897 }
898
899 /* Initialize client buffer ring */
900 rmu->msg_rx_ring.dev_id = dev_id;
901 rmu->msg_rx_ring.size = entries;
902 rmu->msg_rx_ring.rx_slot = 0;
903 for (i = 0; i < rmu->msg_rx_ring.size; i++)
904 rmu->msg_rx_ring.virt_buffer[i] = NULL;
905
906 /* Initialize inbound message ring */
907 rmu->msg_rx_ring.virt = dma_alloc_coherent(priv->dev,
908 rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
909 &rmu->msg_rx_ring.phys, GFP_KERNEL);
910 if (!rmu->msg_rx_ring.virt) {
911 rc = -ENOMEM;
912 goto out;
913 }
914
915 /* Point dequeue/enqueue pointers at first entry in ring */
916 out_be32(&rmu->msg_regs->ifqdpar, (u32) rmu->msg_rx_ring.phys);
917 out_be32(&rmu->msg_regs->ifqepar, (u32) rmu->msg_rx_ring.phys);
918
919 /* Clear interrupt status */
920 out_be32(&rmu->msg_regs->isr, 0x00000091);
921
922 /* Hook up inbound message handler */
923 rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0,
924 "msg_rx", (void *)mport);
925 if (rc < 0) {
926 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
927 rmu->msg_tx_ring.virt_buffer[i],
928 rmu->msg_tx_ring.phys_buffer[i]);
929 goto out;
930 }
931
932 /*
933 * Configure inbound message unit:
934 * Snooping
935 * 4KB max message size
936 * Unmask all interrupt sources
937 * Disable
938 */
939 out_be32(&rmu->msg_regs->imr, 0x001b0060);
940
941 /* Set number of queue entries */
942 setbits32(&rmu->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12);
943
944 /* Now enable the unit */
945 setbits32(&rmu->msg_regs->imr, 0x1);
946
947out:
948 return rc;
949}
950
951/**
952 * fsl_close_inb_mbox - Shut down MPC85xx inbound mailbox
953 * @mport: Master port implementing the inbound message unit
954 * @mbox: Mailbox to close
955 *
956 * Disables the inbound message unit, free all buffers, and
957 * frees the inbound message interrupt.
958 */
959static void fsl_close_inb_mbox(struct rio_mport *mport, int mbox)
960{
961 struct rio_priv *priv = mport->priv;
962 struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
963
964 /* Disable inbound message unit */
965 out_be32(&rmu->msg_regs->imr, 0);
966
967 /* Free ring */
968 dma_free_coherent(priv->dev, rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
969 rmu->msg_rx_ring.virt, rmu->msg_rx_ring.phys);
970
971 /* Free interrupt */
972 free_irq(IRQ_RIO_RX(mport), (void *)mport);
973}
974
975/**
976 * fsl_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
977 * @mport: Master port implementing the inbound message unit
978 * @mbox: Inbound mailbox number
979 * @buf: Buffer to add to inbound queue
980 *
981 * Adds the @buf buffer to the MPC85xx inbound message queue. Returns
982 * %0 on success or %-EINVAL on failure.
983 */
984static int fsl_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
985{
986 int rc = 0;
987 struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
988
989 pr_debug("RIO: fsl_add_inb_buffer(), msg_rx_ring.rx_slot %d\n",
990 rmu->msg_rx_ring.rx_slot);
991
992 if (rmu->msg_rx_ring.virt_buffer[rmu->msg_rx_ring.rx_slot]) {
993 printk(KERN_ERR
994 "RIO: error adding inbound buffer %d, buffer exists\n",
995 rmu->msg_rx_ring.rx_slot);
996 rc = -EINVAL;
997 goto out;
998 }
999
1000 rmu->msg_rx_ring.virt_buffer[rmu->msg_rx_ring.rx_slot] = buf;
1001 if (++rmu->msg_rx_ring.rx_slot == rmu->msg_rx_ring.size)
1002 rmu->msg_rx_ring.rx_slot = 0;
1003
1004out:
1005 return rc;
1006}
1007
1008/**
1009 * fsl_get_inb_message - Fetch inbound message from the MPC85xx message unit
1010 * @mport: Master port implementing the inbound message unit
1011 * @mbox: Inbound mailbox number
1012 *
1013 * Gets the next available inbound message from the inbound message queue.
1014 * A pointer to the message is returned on success or NULL on failure.
1015 */
1016static void *fsl_get_inb_message(struct rio_mport *mport, int mbox)
1017{
1018 struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
1019 u32 phys_buf, virt_buf;
1020 void *buf = NULL;
1021 int buf_idx;
1022
1023 phys_buf = in_be32(&rmu->msg_regs->ifqdpar);
1024
1025 /* If no more messages, then bail out */
1026 if (phys_buf == in_be32(&rmu->msg_regs->ifqepar))
1027 goto out2;
1028
1029 virt_buf = (u32) rmu->msg_rx_ring.virt + (phys_buf
1030 - rmu->msg_rx_ring.phys);
1031 buf_idx = (phys_buf - rmu->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
1032 buf = rmu->msg_rx_ring.virt_buffer[buf_idx];
1033
1034 if (!buf) {
1035 printk(KERN_ERR
1036 "RIO: inbound message copy failed, no buffers\n");
1037 goto out1;
1038 }
1039
1040 /* Copy max message size, caller is expected to allocate that big */
1041 memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE);
1042
1043 /* Clear the available buffer */
1044 rmu->msg_rx_ring.virt_buffer[buf_idx] = NULL;
1045
1046out1:
1047 setbits32(&rmu->msg_regs->imr, RIO_MSG_IMR_MI);
1048
1049out2:
1050 return buf;
1051}
1052
1053/**
1054 * fsl_rio_doorbell_init - MPC85xx doorbell interface init
1055 * @mport: Master port implementing the inbound doorbell unit
1056 *
1057 * Initializes doorbell unit hardware and inbound DMA buffer
1058 * ring. Called from fsl_rio_setup(). Returns %0 on success
1059 * or %-ENOMEM on failure.
1060 */
1061static int fsl_rio_doorbell_init(struct rio_mport *mport)
1062{
1063 struct rio_priv *priv = mport->priv;
1064 struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
1065 int rc = 0;
1066
1067 /* Map outbound doorbell window immediately after maintenance window */
1068 rmu->dbell_win = ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE,
1069 RIO_DBELL_WIN_SIZE);
1070 if (!rmu->dbell_win) {
1071 printk(KERN_ERR
1072 "RIO: unable to map outbound doorbell window\n");
1073 rc = -ENOMEM;
1074 goto out;
1075 }
1076
1077 /* Initialize inbound doorbells */
1078 rmu->dbell_ring.virt = dma_alloc_coherent(priv->dev, 512 *
1079 DOORBELL_MESSAGE_SIZE, &rmu->dbell_ring.phys, GFP_KERNEL);
1080 if (!rmu->dbell_ring.virt) {
1081 printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n");
1082 rc = -ENOMEM;
1083 iounmap(rmu->dbell_win);
1084 goto out;
1085 }
1086
1087 /* Point dequeue/enqueue pointers at first entry in ring */
1088 out_be32(&rmu->msg_regs->dqdpar, (u32) rmu->dbell_ring.phys);
1089 out_be32(&rmu->msg_regs->dqepar, (u32) rmu->dbell_ring.phys);
1090
1091 /* Clear interrupt status */
1092 out_be32(&rmu->msg_regs->dsr, 0x00000091);
1093
1094 /* Hook up doorbell handler */
1095 rc = request_irq(IRQ_RIO_BELL(mport), fsl_rio_dbell_handler, 0,
1096 "dbell_rx", (void *)mport);
1097 if (rc < 0) {
1098 iounmap(rmu->dbell_win);
1099 dma_free_coherent(priv->dev, 512 * DOORBELL_MESSAGE_SIZE,
1100 rmu->dbell_ring.virt, rmu->dbell_ring.phys);
1101 printk(KERN_ERR
1102 "MPC85xx RIO: unable to request inbound doorbell irq");
1103 goto out;
1104 }
1105
1106 /* Configure doorbells for snooping, 512 entries, and enable */
1107 out_be32(&rmu->msg_regs->dmr, 0x00108161);
1108
1109out:
1110 return rc;
1111}
1112
1113int fsl_rio_setup_rmu(struct rio_mport *mport, struct device_node *node)
1114{
1115 struct rio_priv *priv;
1116 struct fsl_rmu *rmu;
1117 struct rio_ops *ops;
1118
1119 if (!mport || !mport->priv || !node)
1120 return -1;
1121
1122 rmu = kzalloc(sizeof(struct fsl_rmu), GFP_KERNEL);
1123 if (!rmu)
1124 return -ENOMEM;
1125
1126 priv = mport->priv;
1127 priv->rmm_handle = rmu;
1128 rmu->dbell_atmu_regs = priv->atmu_regs + 2;
1129 rmu->msg_regs = (struct rio_msg_regs *)(priv->regs_win +
1130 ((mport->phy_type == RIO_PHY_SERIAL) ?
1131 RIO_S_MSG_REGS_OFFSET : RIO_P_MSG_REGS_OFFSET));
1132
1133 rmu->bellirq = irq_of_parse_and_map(node, 2);
1134 rmu->txirq = irq_of_parse_and_map(node, 3);
1135 rmu->rxirq = irq_of_parse_and_map(node, 4);
1136 dev_info(priv->dev, "bellirq: %d, txirq: %d, rxirq %d\n",
1137 rmu->bellirq, rmu->txirq, rmu->rxirq);
1138
1139 ops = mport->ops;
1140
1141 ops->dsend = fsl_rio_doorbell_send;
1142 ops->open_outb_mbox = fsl_open_outb_mbox;
1143 ops->open_inb_mbox = fsl_open_inb_mbox;
1144 ops->close_outb_mbox = fsl_close_outb_mbox;
1145 ops->close_inb_mbox = fsl_close_inb_mbox;
1146 ops->add_outb_message = fsl_add_outb_message;
1147 ops->add_inb_buffer = fsl_add_inb_buffer;
1148 ops->get_inb_message = fsl_get_inb_message;
1149
1150 rio_init_dbell_res(&mport->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
1151 rio_init_mbox_res(&mport->riores[RIO_INB_MBOX_RESOURCE], 0, 0);
1152 rio_init_mbox_res(&mport->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0);
1153
1154 /* Configure outbound doorbell window */
1155 out_be32(&rmu->dbell_atmu_regs->rowbar,
1156 (mport->iores.start + RIO_MAINT_WIN_SIZE) >> 12);
1157 /* 4k window size */
1158 out_be32(&rmu->dbell_atmu_regs->rowar, 0x8004200b);
1159
1160 fsl_rio_doorbell_init(mport);
1161
1162 return 0;
1163}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-21 13:31:53 -0500