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authorEric Miao <ycmiao@ycmiao-hp520.(none)>2008-12-17 03:50:43 -0500
committerEric Miao <eric.miao@marvell.com>2008-12-29 04:59:17 -0500
commit6e354846e807e037751fdc8faaee8ad492177113 (patch)
treeeb31ad176a03091ff02560d2623ed9952fa19dc6 /arch
parent7e4b19c95c8632b543bd510ec6c710bebb53b840 (diff)
[ARM] pxafb: add support for FBIOPAN_DISPLAY by dma braching
dma branching is enabled by extending the current setup_frame_dma() function to allow a 2nd set of frame/palette dma descriptors to be used. As a result, pxafb_dma_buff.dma_desc[], pxafb_dma_buff.pal_desc[] and pxafb_info.fdadr[] are doubled. This allows maximum re-use of the current dma setup code, although the pxafb_info.fdadr[xx] for FBRx register values looks a bit odd. Signed-off-by: Eric Miao <eric.miao@marvell.com> Signed-off-by: Eric Miao <ycmiao@ycmiao-hp520.(none)>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-pxa/include/mach/regs-lcd.h10
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/arm/mach-pxa/include/mach/regs-lcd.h b/arch/arm/mach-pxa/include/mach/regs-lcd.h
index f817878d256b..c15df557fa8a 100644
--- a/arch/arm/mach-pxa/include/mach/regs-lcd.h
+++ b/arch/arm/mach-pxa/include/mach/regs-lcd.h
@@ -12,13 +12,19 @@
12#define LCCR3 (0x00C) /* LCD Controller Control Register 3 */ 12#define LCCR3 (0x00C) /* LCD Controller Control Register 3 */
13#define LCCR4 (0x010) /* LCD Controller Control Register 4 */ 13#define LCCR4 (0x010) /* LCD Controller Control Register 4 */
14#define LCCR5 (0x014) /* LCD Controller Control Register 5 */ 14#define LCCR5 (0x014) /* LCD Controller Control Register 5 */
15#define DFBR0 (0x020) /* DMA Channel 0 Frame Branch Register */
16#define DFBR1 (0x024) /* DMA Channel 1 Frame Branch Register */
17#define LCSR (0x038) /* LCD Controller Status Register */ 15#define LCSR (0x038) /* LCD Controller Status Register */
18#define LIIDR (0x03C) /* LCD Controller Interrupt ID Register */ 16#define LIIDR (0x03C) /* LCD Controller Interrupt ID Register */
19#define TMEDRGBR (0x040) /* TMED RGB Seed Register */ 17#define TMEDRGBR (0x040) /* TMED RGB Seed Register */
20#define TMEDCR (0x044) /* TMED Control Register */ 18#define TMEDCR (0x044) /* TMED Control Register */
21 19
20#define FBR0 (0x020) /* DMA Channel 0 Frame Branch Register */
21#define FBR1 (0x024) /* DMA Channel 1 Frame Branch Register */
22#define FBR2 (0x028) /* DMA Channel 2 Frame Branch Register */
23#define FBR3 (0x02C) /* DMA Channel 2 Frame Branch Register */
24#define FBR4 (0x030) /* DMA Channel 2 Frame Branch Register */
25#define FBR5 (0x110) /* DMA Channel 2 Frame Branch Register */
26#define FBR6 (0x114) /* DMA Channel 2 Frame Branch Register */
27
22#define CMDCR (0x100) /* Command Control Register */ 28#define CMDCR (0x100) /* Command Control Register */
23#define PRSR (0x104) /* Panel Read Status Register */ 29#define PRSR (0x104) /* Panel Read Status Register */
24 30