diff options
author | Thara Gopinath <thara@ti.com> | 2010-02-24 14:05:50 -0500 |
---|---|---|
committer | Paul Walmsley <paul@pwsan.com> | 2010-02-24 14:05:50 -0500 |
commit | 4133a44e28cb65c380903ca69806eec039401f46 (patch) | |
tree | 1cf7d3862505d8abf192f4e8bb31fe6ea4da2da0 /arch | |
parent | 1e3d0d2ba9ce1f975ca59d9a1048175f1e9c01ac (diff) |
OMAP3 PM: Defining .pwrsts_logic_ret field for core power domain structure
This patch adds the flag .pwrsts_logic_ret info for the core power domain
in the associated powerdomain structure. This flag specifies the states
core domain logic can hit in event of the domain entering retention.
Signed-off-by: Thara Gopinath <thara@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-omap2/powerdomains34xx.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h index 186c0132466b..bd87112beea8 100644 --- a/arch/arm/mach-omap2/powerdomains34xx.h +++ b/arch/arm/mach-omap2/powerdomains34xx.h | |||
@@ -82,6 +82,7 @@ static struct powerdomain core_3xxx_pre_es3_1_pwrdm = { | |||
82 | CHIP_IS_OMAP3430ES2 | | 82 | CHIP_IS_OMAP3430ES2 | |
83 | CHIP_IS_OMAP3430ES3_0), | 83 | CHIP_IS_OMAP3430ES3_0), |
84 | .pwrsts = PWRSTS_OFF_RET_ON, | 84 | .pwrsts = PWRSTS_OFF_RET_ON, |
85 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | ||
85 | .banks = 2, | 86 | .banks = 2, |
86 | .pwrsts_mem_ret = { | 87 | .pwrsts_mem_ret = { |
87 | [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ | 88 | [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ |
@@ -98,6 +99,7 @@ static struct powerdomain core_3xxx_es3_1_pwrdm = { | |||
98 | .prcm_offs = CORE_MOD, | 99 | .prcm_offs = CORE_MOD, |
99 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1), | 100 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1), |
100 | .pwrsts = PWRSTS_OFF_RET_ON, | 101 | .pwrsts = PWRSTS_OFF_RET_ON, |
102 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | ||
101 | .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */ | 103 | .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */ |
102 | .banks = 2, | 104 | .banks = 2, |
103 | .pwrsts_mem_ret = { | 105 | .pwrsts_mem_ret = { |