diff options
author | Olof Johansson <olof@lixom.net> | 2015-01-23 17:56:49 -0500 |
---|---|---|
committer | Olof Johansson <olof@lixom.net> | 2015-01-23 17:56:49 -0500 |
commit | 2e568f56c3572d13e3654c42f520f6f731a42a3f (patch) | |
tree | 0a48fa85c3262a708482a0aa15c3d47d12e0d8b0 /arch | |
parent | ff3a45b6185d734e7eb3aee6f01d93ad773935e3 (diff) | |
parent | d035fdfa27ac124bc8f94c3d7dc82ad069802170 (diff) |
Merge tag 'tegra-for-3.20-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/arm64
Merge "arm64: Add initial Tegra support" from Thierry Reding:
This adds support for the Tegra132 SoC, which is essentially a Tegra124
with a dual Denver CPU complex instead of the quad-Cortex-A15. There is
not much here, only the Kconfig entries, but it will allow us to more
easily get subsequent patches in (many of which have already been sent
for review).
* tag 'tegra-for-3.20-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: Add Tegra132 support
soc: tegra: Add thermal reset (thermtrip) support to PMC
ARM: tegra: Add PMC thermtrip programming to Jetson TK1 device tree
of: Add descriptions of thermtrip properties to Tegra PMC bindings
soc/tegra: pmc: Add Tegra132 support
soc/tegra: fuse: Add Tegra132 support
soc/tegra: fuse: Constify tegra_fuse_info structures
soc/tegra: Add Tegra132 support
clocksource: Build Tegra timer on 32-bit ARM only
soc/tegra: pmc: restrict compilation of suspend-related support to ARM
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/boot/dts/tegra124-jetson-tk1.dts | 7 | ||||
-rw-r--r-- | arch/arm/mach-tegra/Kconfig | 4 | ||||
-rw-r--r-- | arch/arm64/Kconfig | 28 |
3 files changed, 39 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 4eb540be368f..dbfaba09703a 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts | |||
@@ -1673,6 +1673,13 @@ | |||
1673 | nvidia,core-pwr-off-time = <61036>; | 1673 | nvidia,core-pwr-off-time = <61036>; |
1674 | nvidia,core-power-req-active-high; | 1674 | nvidia,core-power-req-active-high; |
1675 | nvidia,sys-clock-req-active-high; | 1675 | nvidia,sys-clock-req-active-high; |
1676 | |||
1677 | i2c-thermtrip { | ||
1678 | nvidia,i2c-controller-id = <4>; | ||
1679 | nvidia,bus-addr = <0x40>; | ||
1680 | nvidia,reg-addr = <0x36>; | ||
1681 | nvidia,reg-data = <0x2>; | ||
1682 | }; | ||
1676 | }; | 1683 | }; |
1677 | 1684 | ||
1678 | /* Serial ATA */ | 1685 | /* Serial ATA */ |
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index d0be9a1ef6b8..5d1a318f1302 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig | |||
@@ -27,6 +27,7 @@ config ARCH_TEGRA_2x_SOC | |||
27 | select PINCTRL_TEGRA20 | 27 | select PINCTRL_TEGRA20 |
28 | select PL310_ERRATA_727915 if CACHE_L2X0 | 28 | select PL310_ERRATA_727915 if CACHE_L2X0 |
29 | select PL310_ERRATA_769419 if CACHE_L2X0 | 29 | select PL310_ERRATA_769419 if CACHE_L2X0 |
30 | select TEGRA_TIMER | ||
30 | help | 31 | help |
31 | Support for NVIDIA Tegra AP20 and T20 processors, based on the | 32 | Support for NVIDIA Tegra AP20 and T20 processors, based on the |
32 | ARM CortexA9MP CPU and the ARM PL310 L2 cache controller | 33 | ARM CortexA9MP CPU and the ARM PL310 L2 cache controller |
@@ -37,6 +38,7 @@ config ARCH_TEGRA_3x_SOC | |||
37 | select ARM_ERRATA_764369 if SMP | 38 | select ARM_ERRATA_764369 if SMP |
38 | select PINCTRL_TEGRA30 | 39 | select PINCTRL_TEGRA30 |
39 | select PL310_ERRATA_769419 if CACHE_L2X0 | 40 | select PL310_ERRATA_769419 if CACHE_L2X0 |
41 | select TEGRA_TIMER | ||
40 | help | 42 | help |
41 | Support for NVIDIA Tegra T30 processor family, based on the | 43 | Support for NVIDIA Tegra T30 processor family, based on the |
42 | ARM CortexA9MP CPU and the ARM PL310 L2 cache controller | 44 | ARM CortexA9MP CPU and the ARM PL310 L2 cache controller |
@@ -47,6 +49,7 @@ config ARCH_TEGRA_114_SOC | |||
47 | select ARM_L1_CACHE_SHIFT_6 | 49 | select ARM_L1_CACHE_SHIFT_6 |
48 | select HAVE_ARM_ARCH_TIMER | 50 | select HAVE_ARM_ARCH_TIMER |
49 | select PINCTRL_TEGRA114 | 51 | select PINCTRL_TEGRA114 |
52 | select TEGRA_TIMER | ||
50 | help | 53 | help |
51 | Support for NVIDIA Tegra T114 processor family, based on the | 54 | Support for NVIDIA Tegra T114 processor family, based on the |
52 | ARM CortexA15MP CPU | 55 | ARM CortexA15MP CPU |
@@ -56,6 +59,7 @@ config ARCH_TEGRA_124_SOC | |||
56 | select ARM_L1_CACHE_SHIFT_6 | 59 | select ARM_L1_CACHE_SHIFT_6 |
57 | select HAVE_ARM_ARCH_TIMER | 60 | select HAVE_ARM_ARCH_TIMER |
58 | select PINCTRL_TEGRA124 | 61 | select PINCTRL_TEGRA124 |
62 | select TEGRA_TIMER | ||
59 | help | 63 | help |
60 | Support for NVIDIA Tegra T124 processor family, based on the | 64 | Support for NVIDIA Tegra T124 processor family, based on the |
61 | ARM CortexA15MP CPU | 65 | ARM CortexA15MP CPU |
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 15e8e7469ffd..84850c6cab20 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig | |||
@@ -170,6 +170,34 @@ config ARCH_SEATTLE | |||
170 | help | 170 | help |
171 | This enables support for AMD Seattle SOC Family | 171 | This enables support for AMD Seattle SOC Family |
172 | 172 | ||
173 | config ARCH_TEGRA | ||
174 | bool "NVIDIA Tegra SoC Family" | ||
175 | select ARCH_HAS_RESET_CONTROLLER | ||
176 | select ARCH_REQUIRE_GPIOLIB | ||
177 | select CLKDEV_LOOKUP | ||
178 | select CLKSRC_MMIO | ||
179 | select CLKSRC_OF | ||
180 | select GENERIC_CLOCKEVENTS | ||
181 | select HAVE_CLK | ||
182 | select HAVE_SMP | ||
183 | select PINCTRL | ||
184 | select RESET_CONTROLLER | ||
185 | help | ||
186 | This enables support for the NVIDIA Tegra SoC family. | ||
187 | |||
188 | config ARCH_TEGRA_132_SOC | ||
189 | bool "NVIDIA Tegra132 SoC" | ||
190 | depends on ARCH_TEGRA | ||
191 | select PINCTRL_TEGRA124 | ||
192 | select USB_ARCH_HAS_EHCI if USB_SUPPORT | ||
193 | select USB_ULPI if USB_PHY | ||
194 | select USB_ULPI_VIEWPORT if USB_PHY | ||
195 | help | ||
196 | Enable support for NVIDIA Tegra132 SoC, based on the Denver | ||
197 | ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC, | ||
198 | but contains an NVIDIA Denver CPU complex in place of | ||
199 | Tegra124's "4+1" Cortex-A15 CPU complex. | ||
200 | |||
173 | config ARCH_THUNDER | 201 | config ARCH_THUNDER |
174 | bool "Cavium Inc. Thunder SoC Family" | 202 | bool "Cavium Inc. Thunder SoC Family" |
175 | help | 203 | help |