Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS fixes from Ralf Baechle:
 "Three fixes across arch/mips with the most complex one being the GIC
  interrupt fix - at nine lines still not monster.  I'm confident this
  are the final MIPS patches even if there should go for an rc8"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  MIPS: ralink: fix return value check in rt_timer_probe()
  MIPS: malta: Fix GIC interrupt offsets
  MIPS: Perf: Fix 74K cache map

3 files changed, 8 insertions, 7 deletions

diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index 45f1ffcf1a4b..24cdf64789c3 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -971,11 +971,11 @@ static const struct mips_perf_event mipsxx74Kcore_cache_map
 [C(LL)] = {
         [C(OP_READ)] = {
                 [C(RESULT_ACCESS)]      = { 0x1c, CNTR_ODD, P },
-                [C(RESULT_MISS)]        = { 0x1d, CNTR_EVEN | CNTR_ODD, P },
+                [C(RESULT_MISS)]        = { 0x1d, CNTR_EVEN, P },
         },
         [C(OP_WRITE)] = {
                 [C(RESULT_ACCESS)]      = { 0x1c, CNTR_ODD, P },
-                [C(RESULT_MISS)]        = { 0x1d, CNTR_EVEN | CNTR_ODD, P },
+                [C(RESULT_MISS)]        = { 0x1d, CNTR_EVEN, P },
         },
 },
 [C(ITLB)] = {
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index c69da3734699..5b28e81d94a0 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -473,7 +473,7 @@ static void __init fill_ipi_map(void)
 {
         int cpu;
 
-        for (cpu = 0; cpu < NR_CPUS; cpu++) {
+        for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
                 fill_ipi_map1(gic_resched_int_base, cpu, GIC_CPU_INT1);
                 fill_ipi_map1(gic_call_int_base, cpu, GIC_CPU_INT2);
         }
@@ -574,8 +574,9 @@ void __init arch_init_irq(void)
                 /* FIXME */
                 int i;
 #if defined(CONFIG_MIPS_MT_SMP)
-                gic_call_int_base = GIC_NUM_INTRS - NR_CPUS;
-                gic_resched_int_base = gic_call_int_base - NR_CPUS;
+                gic_call_int_base = GIC_NUM_INTRS -
+                        (NR_CPUS - nr_cpu_ids) * 2 - nr_cpu_ids;
+                gic_resched_int_base = gic_call_int_base - nr_cpu_ids;
                 fill_ipi_map();
 #endif
                 gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map,
@@ -599,7 +600,7 @@ void __init arch_init_irq(void)
                 printk("CPU%d: status register now %08x\n", smp_processor_id(), read_c0_status());
                 write_c0_status(0x1100dc00);
                 printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status());
-                for (i = 0; i < NR_CPUS; i++) {
+                for (i = 0; i < nr_cpu_ids; i++) {
                         arch_init_ipiirq(MIPS_GIC_IRQ_BASE +
                                          GIC_RESCHED_INT(i), &irq_resched);
                         arch_init_ipiirq(MIPS_GIC_IRQ_BASE +
diff --git a/arch/mips/ralink/timer.c b/arch/mips/ralink/timer.c
index e49241a2c39a..202785709441 100644
--- a/arch/mips/ralink/timer.c
+++ b/arch/mips/ralink/timer.c
@@ -126,7 +126,7 @@ static int rt_timer_probe(struct platform_device *pdev)
                 return -ENOENT;
         }
 
-        rt->membase = devm_request_and_ioremap(&pdev->dev, res);
+        rt->membase = devm_ioremap_resource(&pdev->dev, res);
         if (IS_ERR(rt->membase))
                 return PTR_ERR(rt->membase);