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authorLinus Torvalds <torvalds@linux-foundation.org>2014-11-21 18:44:07 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2014-11-21 18:44:07 -0500
commit13f5004c94785af107dd702d9fbbe160f1004064 (patch)
tree4aded04e423a06fd232e653cb5efefa98f342773 /arch
parenta64bb02f4a62a604d8dd62decb559b9c6adfb40c (diff)
parent68055915c1c22489f9658bd2b7391bb11b2cf4e4 (diff)
Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull perf fixes from Ingo Molnar: "Misc fixes: two Intel uncore driver fixes, a CPU-hotplug fix and a build dependencies fix" * 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: perf/x86/intel/uncore: Fix boot crash on SBOX PMU on Haswell-EP perf/x86/intel/uncore: Fix IRP uncore register offsets on Haswell EP perf: Fix corruption of sibling list with hotplug perf/x86: Fix embarrasing typo
Diffstat (limited to 'arch')
-rw-r--r--arch/x86/Kconfig2
-rw-r--r--arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c49
2 files changed, 46 insertions, 5 deletions
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index ded8a6774ac9..41a503c15862 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -144,7 +144,7 @@ config INSTRUCTION_DECODER
144 144
145config PERF_EVENTS_INTEL_UNCORE 145config PERF_EVENTS_INTEL_UNCORE
146 def_bool y 146 def_bool y
147 depends on PERF_EVENTS && SUP_SUP_INTEL && PCI 147 depends on PERF_EVENTS && CPU_SUP_INTEL && PCI
148 148
149config OUTPUT_FORMAT 149config OUTPUT_FORMAT
150 string 150 string
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c b/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
index adf138eac85c..f9ed429d6e4f 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
@@ -486,14 +486,17 @@ static struct attribute_group snbep_uncore_qpi_format_group = {
486 .attrs = snbep_uncore_qpi_formats_attr, 486 .attrs = snbep_uncore_qpi_formats_attr,
487}; 487};
488 488
489#define SNBEP_UNCORE_MSR_OPS_COMMON_INIT() \ 489#define __SNBEP_UNCORE_MSR_OPS_COMMON_INIT() \
490 .init_box = snbep_uncore_msr_init_box, \
491 .disable_box = snbep_uncore_msr_disable_box, \ 490 .disable_box = snbep_uncore_msr_disable_box, \
492 .enable_box = snbep_uncore_msr_enable_box, \ 491 .enable_box = snbep_uncore_msr_enable_box, \
493 .disable_event = snbep_uncore_msr_disable_event, \ 492 .disable_event = snbep_uncore_msr_disable_event, \
494 .enable_event = snbep_uncore_msr_enable_event, \ 493 .enable_event = snbep_uncore_msr_enable_event, \
495 .read_counter = uncore_msr_read_counter 494 .read_counter = uncore_msr_read_counter
496 495
496#define SNBEP_UNCORE_MSR_OPS_COMMON_INIT() \
497 __SNBEP_UNCORE_MSR_OPS_COMMON_INIT(), \
498 .init_box = snbep_uncore_msr_init_box \
499
497static struct intel_uncore_ops snbep_uncore_msr_ops = { 500static struct intel_uncore_ops snbep_uncore_msr_ops = {
498 SNBEP_UNCORE_MSR_OPS_COMMON_INIT(), 501 SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
499}; 502};
@@ -1919,6 +1922,30 @@ static struct intel_uncore_type hswep_uncore_cbox = {
1919 .format_group = &hswep_uncore_cbox_format_group, 1922 .format_group = &hswep_uncore_cbox_format_group,
1920}; 1923};
1921 1924
1925/*
1926 * Write SBOX Initialization register bit by bit to avoid spurious #GPs
1927 */
1928static void hswep_uncore_sbox_msr_init_box(struct intel_uncore_box *box)
1929{
1930 unsigned msr = uncore_msr_box_ctl(box);
1931
1932 if (msr) {
1933 u64 init = SNBEP_PMON_BOX_CTL_INT;
1934 u64 flags = 0;
1935 int i;
1936
1937 for_each_set_bit(i, (unsigned long *)&init, 64) {
1938 flags |= (1ULL << i);
1939 wrmsrl(msr, flags);
1940 }
1941 }
1942}
1943
1944static struct intel_uncore_ops hswep_uncore_sbox_msr_ops = {
1945 __SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
1946 .init_box = hswep_uncore_sbox_msr_init_box
1947};
1948
1922static struct attribute *hswep_uncore_sbox_formats_attr[] = { 1949static struct attribute *hswep_uncore_sbox_formats_attr[] = {
1923 &format_attr_event.attr, 1950 &format_attr_event.attr,
1924 &format_attr_umask.attr, 1951 &format_attr_umask.attr,
@@ -1944,7 +1971,7 @@ static struct intel_uncore_type hswep_uncore_sbox = {
1944 .event_mask = HSWEP_S_MSR_PMON_RAW_EVENT_MASK, 1971 .event_mask = HSWEP_S_MSR_PMON_RAW_EVENT_MASK,
1945 .box_ctl = HSWEP_S0_MSR_PMON_BOX_CTL, 1972 .box_ctl = HSWEP_S0_MSR_PMON_BOX_CTL,
1946 .msr_offset = HSWEP_SBOX_MSR_OFFSET, 1973 .msr_offset = HSWEP_SBOX_MSR_OFFSET,
1947 .ops = &snbep_uncore_msr_ops, 1974 .ops = &hswep_uncore_sbox_msr_ops,
1948 .format_group = &hswep_uncore_sbox_format_group, 1975 .format_group = &hswep_uncore_sbox_format_group,
1949}; 1976};
1950 1977
@@ -2025,13 +2052,27 @@ static struct intel_uncore_type hswep_uncore_imc = {
2025 SNBEP_UNCORE_PCI_COMMON_INIT(), 2052 SNBEP_UNCORE_PCI_COMMON_INIT(),
2026}; 2053};
2027 2054
2055static unsigned hswep_uncore_irp_ctrs[] = {0xa0, 0xa8, 0xb0, 0xb8};
2056
2057static u64 hswep_uncore_irp_read_counter(struct intel_uncore_box *box, struct perf_event *event)
2058{
2059 struct pci_dev *pdev = box->pci_dev;
2060 struct hw_perf_event *hwc = &event->hw;
2061 u64 count = 0;
2062
2063 pci_read_config_dword(pdev, hswep_uncore_irp_ctrs[hwc->idx], (u32 *)&count);
2064 pci_read_config_dword(pdev, hswep_uncore_irp_ctrs[hwc->idx] + 4, (u32 *)&count + 1);
2065
2066 return count;
2067}
2068
2028static struct intel_uncore_ops hswep_uncore_irp_ops = { 2069static struct intel_uncore_ops hswep_uncore_irp_ops = {
2029 .init_box = snbep_uncore_pci_init_box, 2070 .init_box = snbep_uncore_pci_init_box,
2030 .disable_box = snbep_uncore_pci_disable_box, 2071 .disable_box = snbep_uncore_pci_disable_box,
2031 .enable_box = snbep_uncore_pci_enable_box, 2072 .enable_box = snbep_uncore_pci_enable_box,
2032 .disable_event = ivbep_uncore_irp_disable_event, 2073 .disable_event = ivbep_uncore_irp_disable_event,
2033 .enable_event = ivbep_uncore_irp_enable_event, 2074 .enable_event = ivbep_uncore_irp_enable_event,
2034 .read_counter = ivbep_uncore_irp_read_counter, 2075 .read_counter = hswep_uncore_irp_read_counter,
2035}; 2076};
2036 2077
2037static struct intel_uncore_type hswep_uncore_irp = { 2078static struct intel_uncore_type hswep_uncore_irp = {