diff options
| author | Markos Chandras <markos.chandras@imgtec.com> | 2015-01-06 06:09:24 -0500 |
|---|---|---|
| committer | Markos Chandras <markos.chandras@imgtec.com> | 2015-02-17 10:37:22 -0500 |
| commit | 0038df2240ff01c666e5b55120ef9c3f15c281a4 (patch) | |
| tree | 6e243ae11c00a0f0ed31572a8f0f30ba03851308 /arch | |
| parent | fa998ebbc02d11aa33a621e6f41cb15ce87e6b9e (diff) | |
MIPS: asm: atomic: Update ISA constraints for MIPS R6 support
MIPS R6 changed the opcodes for LL/SC instructions so we need to
set the correct ISA level.
Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/include/asm/atomic.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h index 3a44c2f17e53..26d436336f2e 100644 --- a/arch/mips/include/asm/atomic.h +++ b/arch/mips/include/asm/atomic.h | |||
| @@ -61,7 +61,7 @@ static __inline__ void atomic_##op(int i, atomic_t * v) \ | |||
| 61 | \ | 61 | \ |
| 62 | do { \ | 62 | do { \ |
| 63 | __asm__ __volatile__( \ | 63 | __asm__ __volatile__( \ |
| 64 | " .set arch=r4000 \n" \ | 64 | " .set "MIPS_ISA_LEVEL" \n" \ |
| 65 | " ll %0, %1 # atomic_" #op "\n" \ | 65 | " ll %0, %1 # atomic_" #op "\n" \ |
| 66 | " " #asm_op " %0, %2 \n" \ | 66 | " " #asm_op " %0, %2 \n" \ |
| 67 | " sc %0, %1 \n" \ | 67 | " sc %0, %1 \n" \ |
| @@ -104,7 +104,7 @@ static __inline__ int atomic_##op##_return(int i, atomic_t * v) \ | |||
| 104 | \ | 104 | \ |
| 105 | do { \ | 105 | do { \ |
| 106 | __asm__ __volatile__( \ | 106 | __asm__ __volatile__( \ |
| 107 | " .set arch=r4000 \n" \ | 107 | " .set "MIPS_ISA_LEVEL" \n" \ |
| 108 | " ll %1, %2 # atomic_" #op "_return \n" \ | 108 | " ll %1, %2 # atomic_" #op "_return \n" \ |
| 109 | " " #asm_op " %0, %1, %3 \n" \ | 109 | " " #asm_op " %0, %1, %3 \n" \ |
| 110 | " sc %0, %2 \n" \ | 110 | " sc %0, %2 \n" \ |
| @@ -178,7 +178,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) | |||
| 178 | int temp; | 178 | int temp; |
| 179 | 179 | ||
| 180 | __asm__ __volatile__( | 180 | __asm__ __volatile__( |
| 181 | " .set arch=r4000 \n" | 181 | " .set "MIPS_ISA_LEVEL" \n" |
| 182 | "1: ll %1, %2 # atomic_sub_if_positive\n" | 182 | "1: ll %1, %2 # atomic_sub_if_positive\n" |
| 183 | " subu %0, %1, %3 \n" | 183 | " subu %0, %1, %3 \n" |
| 184 | " bltz %0, 1f \n" | 184 | " bltz %0, 1f \n" |
| @@ -340,7 +340,7 @@ static __inline__ void atomic64_##op(long i, atomic64_t * v) \ | |||
| 340 | \ | 340 | \ |
| 341 | do { \ | 341 | do { \ |
| 342 | __asm__ __volatile__( \ | 342 | __asm__ __volatile__( \ |
| 343 | " .set arch=r4000 \n" \ | 343 | " .set "MIPS_ISA_LEVEL" \n" \ |
| 344 | " lld %0, %1 # atomic64_" #op "\n" \ | 344 | " lld %0, %1 # atomic64_" #op "\n" \ |
| 345 | " " #asm_op " %0, %2 \n" \ | 345 | " " #asm_op " %0, %2 \n" \ |
| 346 | " scd %0, %1 \n" \ | 346 | " scd %0, %1 \n" \ |
| @@ -383,7 +383,7 @@ static __inline__ long atomic64_##op##_return(long i, atomic64_t * v) \ | |||
| 383 | \ | 383 | \ |
| 384 | do { \ | 384 | do { \ |
| 385 | __asm__ __volatile__( \ | 385 | __asm__ __volatile__( \ |
| 386 | " .set arch=r4000 \n" \ | 386 | " .set "MIPS_ISA_LEVEL" \n" \ |
| 387 | " lld %1, %2 # atomic64_" #op "_return\n" \ | 387 | " lld %1, %2 # atomic64_" #op "_return\n" \ |
| 388 | " " #asm_op " %0, %1, %3 \n" \ | 388 | " " #asm_op " %0, %1, %3 \n" \ |
| 389 | " scd %0, %2 \n" \ | 389 | " scd %0, %2 \n" \ |
| @@ -459,7 +459,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) | |||
| 459 | long temp; | 459 | long temp; |
| 460 | 460 | ||
| 461 | __asm__ __volatile__( | 461 | __asm__ __volatile__( |
| 462 | " .set arch=r4000 \n" | 462 | " .set "MIPS_ISA_LEVEL" \n" |
| 463 | "1: lld %1, %2 # atomic64_sub_if_positive\n" | 463 | "1: lld %1, %2 # atomic64_sub_if_positive\n" |
| 464 | " dsubu %0, %1, %3 \n" | 464 | " dsubu %0, %1, %3 \n" |
| 465 | " bltz %0, 1f \n" | 465 | " bltz %0, 1f \n" |