diff options
author | Ingo Molnar <mingo@elte.hu> | 2009-09-21 06:20:38 -0400 |
---|---|---|
committer | Ingo Molnar <mingo@elte.hu> | 2009-09-21 08:34:11 -0400 |
commit | 57c0c15b5244320065374ad2c54f4fbec77a6428 (patch) | |
tree | 35369d817f5925aca09b083bba47c437b91386d9 /arch | |
parent | cdd6c482c9ff9c55475ee7392ec8f672eddb7be6 (diff) |
perf: Tidy up after the big rename
- provide compatibility Kconfig entry for existing PERF_COUNTERS .config's
- provide courtesy copy of old perf_counter.h, for user-space projects
- small indentation fixups
- fix up MAINTAINERS
- fix small x86 printout fallout
- fix up small PowerPC comment fallout (use 'counter' as in register)
Reviewed-by: Arjan van de Ven <arjan@linux.intel.com>
Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/powerpc/include/asm/paca.h | 2 | ||||
-rw-r--r-- | arch/powerpc/kernel/perf_event.c | 12 | ||||
-rw-r--r-- | arch/x86/kernel/cpu/perf_event.c | 14 |
3 files changed, 14 insertions, 14 deletions
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h index 154f405b642f..7d8514ceceae 100644 --- a/arch/powerpc/include/asm/paca.h +++ b/arch/powerpc/include/asm/paca.h | |||
@@ -122,7 +122,7 @@ struct paca_struct { | |||
122 | u8 soft_enabled; /* irq soft-enable flag */ | 122 | u8 soft_enabled; /* irq soft-enable flag */ |
123 | u8 hard_enabled; /* set if irqs are enabled in MSR */ | 123 | u8 hard_enabled; /* set if irqs are enabled in MSR */ |
124 | u8 io_sync; /* writel() needs spin_unlock sync */ | 124 | u8 io_sync; /* writel() needs spin_unlock sync */ |
125 | u8 perf_event_pending; /* PM interrupt while soft-disabled */ | 125 | u8 perf_event_pending; /* PM interrupt while soft-disabled */ |
126 | 126 | ||
127 | /* Stuff for accurate time accounting */ | 127 | /* Stuff for accurate time accounting */ |
128 | u64 user_time; /* accumulated usermode TB ticks */ | 128 | u64 user_time; /* accumulated usermode TB ticks */ |
diff --git a/arch/powerpc/kernel/perf_event.c b/arch/powerpc/kernel/perf_event.c index c98321fcb459..197b7d958796 100644 --- a/arch/powerpc/kernel/perf_event.c +++ b/arch/powerpc/kernel/perf_event.c | |||
@@ -41,7 +41,7 @@ DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); | |||
41 | struct power_pmu *ppmu; | 41 | struct power_pmu *ppmu; |
42 | 42 | ||
43 | /* | 43 | /* |
44 | * Normally, to ignore kernel events we set the FCS (freeze events | 44 | * Normally, to ignore kernel events we set the FCS (freeze counters |
45 | * in supervisor mode) bit in MMCR0, but if the kernel runs with the | 45 | * in supervisor mode) bit in MMCR0, but if the kernel runs with the |
46 | * hypervisor bit set in the MSR, or if we are running on a processor | 46 | * hypervisor bit set in the MSR, or if we are running on a processor |
47 | * where the hypervisor bit is forced to 1 (as on Apple G5 processors), | 47 | * where the hypervisor bit is forced to 1 (as on Apple G5 processors), |
@@ -159,7 +159,7 @@ void perf_event_print_debug(void) | |||
159 | } | 159 | } |
160 | 160 | ||
161 | /* | 161 | /* |
162 | * Read one performance monitor event (PMC). | 162 | * Read one performance monitor counter (PMC). |
163 | */ | 163 | */ |
164 | static unsigned long read_pmc(int idx) | 164 | static unsigned long read_pmc(int idx) |
165 | { | 165 | { |
@@ -409,7 +409,7 @@ static void power_pmu_read(struct perf_event *event) | |||
409 | val = read_pmc(event->hw.idx); | 409 | val = read_pmc(event->hw.idx); |
410 | } while (atomic64_cmpxchg(&event->hw.prev_count, prev, val) != prev); | 410 | } while (atomic64_cmpxchg(&event->hw.prev_count, prev, val) != prev); |
411 | 411 | ||
412 | /* The events are only 32 bits wide */ | 412 | /* The counters are only 32 bits wide */ |
413 | delta = (val - prev) & 0xfffffffful; | 413 | delta = (val - prev) & 0xfffffffful; |
414 | atomic64_add(delta, &event->count); | 414 | atomic64_add(delta, &event->count); |
415 | atomic64_sub(delta, &event->hw.period_left); | 415 | atomic64_sub(delta, &event->hw.period_left); |
@@ -543,7 +543,7 @@ void hw_perf_disable(void) | |||
543 | } | 543 | } |
544 | 544 | ||
545 | /* | 545 | /* |
546 | * Set the 'freeze events' bit. | 546 | * Set the 'freeze counters' bit. |
547 | * The barrier is to make sure the mtspr has been | 547 | * The barrier is to make sure the mtspr has been |
548 | * executed and the PMU has frozen the events | 548 | * executed and the PMU has frozen the events |
549 | * before we return. | 549 | * before we return. |
@@ -1124,7 +1124,7 @@ const struct pmu *hw_perf_event_init(struct perf_event *event) | |||
1124 | } | 1124 | } |
1125 | 1125 | ||
1126 | /* | 1126 | /* |
1127 | * A event has overflowed; update its count and record | 1127 | * A counter has overflowed; update its count and record |
1128 | * things if requested. Note that interrupts are hard-disabled | 1128 | * things if requested. Note that interrupts are hard-disabled |
1129 | * here so there is no possibility of being interrupted. | 1129 | * here so there is no possibility of being interrupted. |
1130 | */ | 1130 | */ |
@@ -1271,7 +1271,7 @@ static void perf_event_interrupt(struct pt_regs *regs) | |||
1271 | 1271 | ||
1272 | /* | 1272 | /* |
1273 | * Reset MMCR0 to its normal value. This will set PMXE and | 1273 | * Reset MMCR0 to its normal value. This will set PMXE and |
1274 | * clear FC (freeze events) and PMAO (perf mon alert occurred) | 1274 | * clear FC (freeze counters) and PMAO (perf mon alert occurred) |
1275 | * and thus allow interrupts to occur again. | 1275 | * and thus allow interrupts to occur again. |
1276 | * XXX might want to use MSR.PM to keep the events frozen until | 1276 | * XXX might want to use MSR.PM to keep the events frozen until |
1277 | * we get back out of this interrupt. | 1277 | * we get back out of this interrupt. |
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c index 0d03629fb1a5..a3c7adb06b78 100644 --- a/arch/x86/kernel/cpu/perf_event.c +++ b/arch/x86/kernel/cpu/perf_event.c | |||
@@ -2081,13 +2081,13 @@ void __init init_hw_perf_events(void) | |||
2081 | perf_events_lapic_init(); | 2081 | perf_events_lapic_init(); |
2082 | register_die_notifier(&perf_event_nmi_notifier); | 2082 | register_die_notifier(&perf_event_nmi_notifier); |
2083 | 2083 | ||
2084 | pr_info("... version: %d\n", x86_pmu.version); | 2084 | pr_info("... version: %d\n", x86_pmu.version); |
2085 | pr_info("... bit width: %d\n", x86_pmu.event_bits); | 2085 | pr_info("... bit width: %d\n", x86_pmu.event_bits); |
2086 | pr_info("... generic events: %d\n", x86_pmu.num_events); | 2086 | pr_info("... generic registers: %d\n", x86_pmu.num_events); |
2087 | pr_info("... value mask: %016Lx\n", x86_pmu.event_mask); | 2087 | pr_info("... value mask: %016Lx\n", x86_pmu.event_mask); |
2088 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); | 2088 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
2089 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_events_fixed); | 2089 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_events_fixed); |
2090 | pr_info("... event mask: %016Lx\n", perf_event_mask); | 2090 | pr_info("... event mask: %016Lx\n", perf_event_mask); |
2091 | } | 2091 | } |
2092 | 2092 | ||
2093 | static inline void x86_pmu_read(struct perf_event *event) | 2093 | static inline void x86_pmu_read(struct perf_event *event) |