diff options
author | Eric Bénard <eric@eukrea.com> | 2010-10-12 13:26:34 -0400 |
---|---|---|
committer | Sascha Hauer <s.hauer@pengutronix.de> | 2010-10-19 12:44:58 -0400 |
commit | e482b3bee66d627356904746c217f8f1bf891e60 (patch) | |
tree | 9c6fa60278728972b160a95a014c24e4d7d92697 /arch | |
parent | 6136a6ddc9db50d909344bb7e6f45dbe631f2e29 (diff) |
mx25: fix clock's calculation
* get_rate_arm : when 400MHz clock is selected (cctl & 1<<14),
ARM clock is 400MHz (MPLL * 3 / 4) and not 800MHz
* get_rate_per : peripherals's clock is derived from AHB and not
from IPG (ref manual : figure 5-1)
* can2_clk : use the correct ID
* without this patch, peripherals getting their clock from PER
clocks work fine because of the 2 errors which fix themselves
(ARM clock x 2 and per clock actually based on IPG which is AHB/2)
but flexcan can't work as it gets its clock from IPG and thus
calculates its bitrate using a reference value which is twice
what it really is.
Signed-off-by: Eric Bénard <eric@eukrea.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-mx25/clock.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c index 2179713873c2..9e4a5578c2fb 100644 --- a/arch/arm/mach-mx25/clock.c +++ b/arch/arm/mach-mx25/clock.c | |||
@@ -72,7 +72,7 @@ unsigned long get_rate_arm(struct clk *clk) | |||
72 | unsigned long rate = get_rate_mpll(); | 72 | unsigned long rate = get_rate_mpll(); |
73 | 73 | ||
74 | if (cctl & (1 << 14)) | 74 | if (cctl & (1 << 14)) |
75 | rate = (rate * 3) >> 1; | 75 | rate = (rate * 3) >> 2; |
76 | 76 | ||
77 | return rate / ((cctl >> 30) + 1); | 77 | return rate / ((cctl >> 30) + 1); |
78 | } | 78 | } |
@@ -99,7 +99,7 @@ static unsigned long get_rate_per(int per) | |||
99 | if (readl(CRM_BASE + 0x64) & (1 << per)) | 99 | if (readl(CRM_BASE + 0x64) & (1 << per)) |
100 | fref = get_rate_upll(); | 100 | fref = get_rate_upll(); |
101 | else | 101 | else |
102 | fref = get_rate_ipg(NULL); | 102 | fref = get_rate_ahb(NULL); |
103 | 103 | ||
104 | return fref / (val + 1); | 104 | return fref / (val + 1); |
105 | } | 105 | } |
@@ -261,7 +261,7 @@ DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGCR1, 14, get_rate_esdhc2, NULL, | |||
261 | DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL); | 261 | DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL); |
262 | DEFINE_CLOCK(csi_clk, 0, CCM_CGCR1, 4, get_rate_csi, NULL, &csi_per_clk); | 262 | DEFINE_CLOCK(csi_clk, 0, CCM_CGCR1, 4, get_rate_csi, NULL, &csi_per_clk); |
263 | DEFINE_CLOCK(can1_clk, 0, CCM_CGCR1, 2, get_rate_ipg, NULL, NULL); | 263 | DEFINE_CLOCK(can1_clk, 0, CCM_CGCR1, 2, get_rate_ipg, NULL, NULL); |
264 | DEFINE_CLOCK(can2_clk, 0, CCM_CGCR1, 3, get_rate_ipg, NULL, NULL); | 264 | DEFINE_CLOCK(can2_clk, 1, CCM_CGCR1, 3, get_rate_ipg, NULL, NULL); |
265 | 265 | ||
266 | #define _REGISTER_CLOCK(d, n, c) \ | 266 | #define _REGISTER_CLOCK(d, n, c) \ |
267 | { \ | 267 | { \ |