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authorUwe Kleine-König <u.kleine-koenig@pengutronix.de>2010-02-05 11:40:28 -0500
committerUwe Kleine-König <u.kleine-koenig@pengutronix.de>2010-02-24 04:06:51 -0500
commit897359d596ca406aaa9f9687b439b4498b579d7f (patch)
tree1fc49c2334b823c7318efd2ac25c6036cfd64069 /arch
parent3636a145321573f2f735e3ae69f87e0fb166abec (diff)
arm/mx2: define seperate gpio port descriptions for imx21 and imx27
As the gpio ports have different addresses on imx21 and imx27 there are two different port descriptions needed if not relying on the overloaded cpp macro IO_ADDRESS. So some cpp magic is added to minimize code duplication. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-mx2/devices.c72
1 files changed, 44 insertions, 28 deletions
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c
index cda4aced7a39..a4b809b82fa3 100644
--- a/arch/arm/mach-mx2/devices.c
+++ b/arch/arm/mach-mx2/devices.c
@@ -432,36 +432,52 @@ DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
432DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1); 432DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
433 433
434/* GPIO port description */ 434/* GPIO port description */
435static struct mxc_gpio_port imx_gpio_ports[] = { 435#define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
436 { 436 { \
437 .chip.label = "gpio-0", 437 .chip.label = "gpio-" #n, \
438 .irq = MX2x_INT_GPIO, 438 .irq = _irq, \
439 .base = IO_ADDRESS(MX2x_GPIO_BASE_ADDR), 439 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
440 .virtual_irq_start = MXC_GPIO_IRQ_START, 440 n * 0x100), \
441 }, { 441 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
442 .chip.label = "gpio-1", 442 }
443 .base = IO_ADDRESS(MX2x_GPIO_BASE_ADDR + 0x100), 443
444 .virtual_irq_start = MXC_GPIO_IRQ_START + 32, 444#define DEFINE_MXC_GPIO_PORT(SOC, n) \
445 }, { 445 { \
446 .chip.label = "gpio-2", 446 .chip.label = "gpio-" #n, \
447 .base = IO_ADDRESS(MX2x_GPIO_BASE_ADDR + 0x200), 447 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
448 .virtual_irq_start = MXC_GPIO_IRQ_START + 64, 448 n * 0x100), \
449 }, { 449 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
450 .chip.label = "gpio-3",
451 .base = IO_ADDRESS(MX2x_GPIO_BASE_ADDR + 0x300),
452 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
453 }, {
454 .chip.label = "gpio-4",
455 .base = IO_ADDRESS(MX2x_GPIO_BASE_ADDR + 0x400),
456 .virtual_irq_start = MXC_GPIO_IRQ_START + 128,
457 }, {
458 .chip.label = "gpio-5",
459 .base = IO_ADDRESS(MX2x_GPIO_BASE_ADDR + 0x500),
460 .virtual_irq_start = MXC_GPIO_IRQ_START + 160,
461 } 450 }
462}; 451
452#define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \
453 static struct mxc_gpio_port pfx ## _gpio_ports[] = { \
454 DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \
455 DEFINE_MXC_GPIO_PORT(SOC, 1), \
456 DEFINE_MXC_GPIO_PORT(SOC, 2), \
457 DEFINE_MXC_GPIO_PORT(SOC, 3), \
458 DEFINE_MXC_GPIO_PORT(SOC, 4), \
459 DEFINE_MXC_GPIO_PORT(SOC, 5), \
460 }
461
462#ifdef CONFIG_MACH_MX21
463DEFINE_MXC_GPIO_PORTS(MX21, imx21);
464#endif
465
466#ifdef CONFIG_MACH_MX27
467DEFINE_MXC_GPIO_PORTS(MX27, imx27);
468#endif
463 469
464int __init mxc_register_gpios(void) 470int __init mxc_register_gpios(void)
465{ 471{
466 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); 472#ifdef CONFIG_MACH_MX21
473 if (cpu_is_mx21())
474 return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
475 else
476#endif
477#ifdef CONFIG_MACH_MX27
478 if (cpu_is_mx27())
479 return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
480 else
481#endif
482 return 0;
467} 483}