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authorManuel Lauss <mano@roarinelk.homelinux.net>2009-03-31 12:51:27 -0400
committerRalf Baechle <ralf@linux-mips.org>2009-05-14 08:50:24 -0400
commitb7863ee144a99ff54fee90d851e24d73f38af661 (patch)
tree0b51504a6b833b7241e60b444998eb866839aca3 /arch
parentbcf11801e77946533767bbb368130220e241d824 (diff)
MIPS: Alchemy: Fix AU1100 interrupt numbers off-by-one
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index 62f91f50b5b5..87a16598ebc3 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -715,7 +715,7 @@ enum soc_au1500_ints {
715#ifdef CONFIG_SOC_AU1100 715#ifdef CONFIG_SOC_AU1100
716enum soc_au1100_ints { 716enum soc_au1100_ints {
717 AU1100_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, 717 AU1100_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
718 AU1100_UART0_INT, 718 AU1100_UART0_INT = AU1100_FIRST_INT,
719 AU1100_UART1_INT, 719 AU1100_UART1_INT,
720 AU1100_SD_INT, 720 AU1100_SD_INT,
721 AU1100_UART3_INT, 721 AU1100_UART3_INT,