Blackfin arch: Make L2 SRAM cacheable

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>

4 files changed, 26 insertions, 3 deletions

diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index 554ac5827c1d..10c97efbd91f 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -772,6 +772,13 @@ config BFIN_WT
 
 endchoice
 
+config BFIN_L2_CACHEABLE
+        bool "Cache L2 SRAM"
+        depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || BF561)
+        default n
+        help
+          Select to make L2 SRAM cacheable in L1 data and instruction cache.
+
 config MPU
         bool "Enable the memory protection unit (EXPERIMENTAL)"
         default n
diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h
index 05d6f05fb748..9e8b4035fcec 100644
--- a/arch/blackfin/include/asm/cplb.h
+++ b/arch/blackfin/include/asm/cplb.h
@@ -55,7 +55,13 @@
 #endif
 
 #define L1_DMEMORY       (CPLB_LOCK | CPLB_COMMON)
-#define L2_MEMORY        (CPLB_COMMON)
+#ifdef CONFIG_BFIN_L2_CACHEABLE
+#define L2_IMEMORY        (SDRAM_IGENERIC)
+#define L2_DMEMORY        (SDRAM_DGENERIC)
+#else
+#define L2_IMEMORY        (CPLB_COMMON)
+#define L2_DMEMORY        (CPLB_COMMON)
+#endif
 #define SDRAM_DNON_CHBL  (CPLB_COMMON)
 #define SDRAM_EBIU       (CPLB_COMMON)
 #define SDRAM_OOPS       (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbinit.c b/arch/blackfin/kernel/cplb-mpu/cplbinit.c
index d4257d0ad6a8..55af729f8495 100644
--- a/arch/blackfin/kernel/cplb-mpu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-mpu/cplbinit.c
@@ -83,8 +83,18 @@ void __init generate_cplb_tables(void)
         dcplb_tbl[i_d].addr = L1_DATA_A_START;
         dcplb_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
 #endif
+#if L1_CODE_LENGTH > 0
         icplb_tbl[i_i].addr = L1_CODE_START;
         icplb_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
+#endif
+
+        /* Cover L2 memory */
+#if L2_LENGTH > 0
+        dcplb_tbl[i_d].addr = L2_START;
+        dcplb_tbl[i_d++].data = L2_DMEMORY | PAGE_SIZE_1MB;
+        icplb_tbl[i_i].addr = L2_START;
+        icplb_tbl[i_i++].data = L2_IMEMORY | PAGE_SIZE_1MB;
+#endif
 
         first_mask_dcplb = i_d;
         first_switched_dcplb = i_d + (1 << page_mask_order);
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
index 2c45c16c3520..301252e84441 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
@@ -168,8 +168,8 @@ static struct cplb_desc cplb_data[] = {
                 .end = L2_START + L2_LENGTH,
                 .psize = SIZE_1M,
                 .attr = SWITCH_T | I_CPLB | D_CPLB,
-                .i_conf = L2_MEMORY,
-                .d_conf = L2_MEMORY,
+                .i_conf = L2_IMEMORY,
+                .d_conf = L2_DMEMORY,
                 .valid = (L2_LENGTH > 0),
                 .name = "L2 Memory",
         },