diff options
author | Tony Lindgren <tony@atomide.com> | 2010-01-19 17:42:08 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-01-19 18:11:56 -0500 |
commit | 2045124ffd1a5e46d157349016a2c50f19c8c91d (patch) | |
tree | e305146e3f9054baead6ccb6d8bddb22c845161a /arch | |
parent | 1f667c690be3ab71036c436d8391105eee23f65b (diff) |
ARM: 5888/1: arm: Update comments in cacheflush.h and remove unnecessary V6 and V7 comments
The comments in cacheflush.h should follow what's in
struct cpu_cache_fns. The comments for V6 and V7 are
unnecessary.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/include/asm/cacheflush.h | 20 | ||||
-rw-r--r-- | arch/arm/mm/proc-v6.S | 2 | ||||
-rw-r--r-- | arch/arm/mm/proc-v7.S | 2 |
3 files changed, 17 insertions, 7 deletions
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index 730aefcfbee3..c77d2fa1f6e5 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h | |||
@@ -154,16 +154,16 @@ | |||
154 | * Please note that the implementation of these, and the required | 154 | * Please note that the implementation of these, and the required |
155 | * effects are cache-type (VIVT/VIPT/PIPT) specific. | 155 | * effects are cache-type (VIVT/VIPT/PIPT) specific. |
156 | * | 156 | * |
157 | * flush_cache_kern_all() | 157 | * flush_kern_all() |
158 | * | 158 | * |
159 | * Unconditionally clean and invalidate the entire cache. | 159 | * Unconditionally clean and invalidate the entire cache. |
160 | * | 160 | * |
161 | * flush_cache_user_mm(mm) | 161 | * flush_user_all() |
162 | * | 162 | * |
163 | * Clean and invalidate all user space cache entries | 163 | * Clean and invalidate all user space cache entries |
164 | * before a change of page tables. | 164 | * before a change of page tables. |
165 | * | 165 | * |
166 | * flush_cache_user_range(start, end, flags) | 166 | * flush_user_range(start, end, flags) |
167 | * | 167 | * |
168 | * Clean and invalidate a range of cache entries in the | 168 | * Clean and invalidate a range of cache entries in the |
169 | * specified address space before a change of page tables. | 169 | * specified address space before a change of page tables. |
@@ -179,6 +179,20 @@ | |||
179 | * - start - virtual start address | 179 | * - start - virtual start address |
180 | * - end - virtual end address | 180 | * - end - virtual end address |
181 | * | 181 | * |
182 | * coherent_user_range(start, end) | ||
183 | * | ||
184 | * Ensure coherency between the Icache and the Dcache in the | ||
185 | * region described by start, end. If you have non-snooping | ||
186 | * Harvard caches, you need to implement this function. | ||
187 | * - start - virtual start address | ||
188 | * - end - virtual end address | ||
189 | * | ||
190 | * flush_kern_dcache_area(kaddr, size) | ||
191 | * | ||
192 | * Ensure that the data held in page is written back. | ||
193 | * - kaddr - page address | ||
194 | * - size - region size | ||
195 | * | ||
182 | * DMA Cache Coherency | 196 | * DMA Cache Coherency |
183 | * =================== | 197 | * =================== |
184 | * | 198 | * |
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 395cc90c6613..7a5337ed7d68 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S | |||
@@ -59,8 +59,6 @@ ENTRY(cpu_v6_proc_fin) | |||
59 | * to what would be the reset vector. | 59 | * to what would be the reset vector. |
60 | * | 60 | * |
61 | * - loc - location to jump to for soft reset | 61 | * - loc - location to jump to for soft reset |
62 | * | ||
63 | * It is assumed that: | ||
64 | */ | 62 | */ |
65 | .align 5 | 63 | .align 5 |
66 | ENTRY(cpu_v6_reset) | 64 | ENTRY(cpu_v6_reset) |
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index d2a80747c6fe..7aaf88a3b7aa 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S | |||
@@ -63,8 +63,6 @@ ENDPROC(cpu_v7_proc_fin) | |||
63 | * to what would be the reset vector. | 63 | * to what would be the reset vector. |
64 | * | 64 | * |
65 | * - loc - location to jump to for soft reset | 65 | * - loc - location to jump to for soft reset |
66 | * | ||
67 | * It is assumed that: | ||
68 | */ | 66 | */ |
69 | .align 5 | 67 | .align 5 |
70 | ENTRY(cpu_v7_reset) | 68 | ENTRY(cpu_v7_reset) |