Merge branch 'master' into sh/smp

Conflicts:
	arch/sh/mm/cache-sh4.c

160 files changed, 8744 insertions, 847 deletions

diff --git a/arch/arm/configs/rx51_defconfig b/arch/arm/configs/rx51_defconfig
index eb2cb31825c0..f238df66efd4 100644
--- a/arch/arm/configs/rx51_defconfig
+++ b/arch/arm/configs/rx51_defconfig
@@ -282,7 +282,7 @@ CONFIG_ALIGNMENT_TRAP=y
 #
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="init=/sbin/preinit ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs rootflags=bulk_read,no_chk_data_crc rw console=ttyMTD,log console=tty0"
+CONFIG_CMDLINE="init=/sbin/preinit ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs rootflags=bulk_read,no_chk_data_crc rw console=ttyMTD,log console=tty0 console=ttyS2,115200n8"
 # CONFIG_XIP_KERNEL is not set
 # CONFIG_KEXEC is not set
 
@@ -1354,7 +1354,7 @@ CONFIG_USB_OTG_UTILS=y
 # CONFIG_USB_GPIO_VBUS is not set
 # CONFIG_ISP1301_OMAP is not set
 CONFIG_TWL4030_USB=y
-CONFIG_MMC=m
+CONFIG_MMC=y
 # CONFIG_MMC_DEBUG is not set
 # CONFIG_MMC_UNSAFE_RESUME is not set
 
@@ -1449,7 +1449,8 @@ CONFIG_RTC_DRV_TWL4030=m
 # on-CPU RTC drivers
 #
 # CONFIG_DMADEVICES is not set
-# CONFIG_REGULATOR is not set
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_TWL4030=y
 # CONFIG_UIO is not set
 # CONFIG_STAGING is not set
 
diff --git a/arch/arm/include/asm/device.h b/arch/arm/include/asm/device.h
index c61642b40603..9f390ce335cb 100644
--- a/arch/arm/include/asm/device.h
+++ b/arch/arm/include/asm/device.h
@@ -12,4 +12,7 @@ struct dev_archdata {
 #endif
 };
 
+struct pdev_archdata {
+};
+
 #endif
diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h
index ee1304f22f94..5ccce0a9b03c 100644
--- a/arch/arm/include/asm/setup.h
+++ b/arch/arm/include/asm/setup.h
@@ -201,7 +201,8 @@ static struct tagtable __tagtable_##fn __tag = { tag, fn }
 struct membank {
         unsigned long start;
         unsigned long size;
-        int           node;
+        unsigned short node;
+        unsigned short highmem;
 };
 
 struct meminfo {
diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h
index ce63048d45eb..8a947d42a6f1 100644
--- a/arch/arm/mach-ixp4xx/include/mach/io.h
+++ b/arch/arm/mach-ixp4xx/include/mach/io.h
@@ -17,7 +17,7 @@
 
 #include <mach/hardware.h>
 
-#define IO_SPACE_LIMIT 0xffff0000
+#define IO_SPACE_LIMIT 0x0000ffff
 
 extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
 extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c
index 4704405165a1..b48581e7dedd 100644
--- a/arch/arm/mach-mx3/mx31moboard-devboard.c
+++ b/arch/arm/mach-mx3/mx31moboard-devboard.c
@@ -63,7 +63,7 @@ static struct imxuart_platform_data uart_pdata = {
 
 static int devboard_sdhc2_get_ro(struct device *dev)
 {
-        return gpio_get_value(SDHC2_WP);
+        return !gpio_get_value(SDHC2_WP);
 }
 
 static int devboard_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c
index 641c3d6153ae..901fb0166c0e 100644
--- a/arch/arm/mach-mx3/mx31moboard-marxbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c
@@ -67,7 +67,7 @@ static unsigned int marxbot_pins[] = {
 
 static int marxbot_sdhc2_get_ro(struct device *dev)
 {
-        return gpio_get_value(SDHC2_WP);
+        return !gpio_get_value(SDHC2_WP);
 }
 
 static int marxbot_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
diff --git a/arch/arm/mach-mx3/mx31moboard.c b/arch/arm/mach-mx3/mx31moboard.c
index a17f2e411609..2a2da4739ecf 100644
--- a/arch/arm/mach-mx3/mx31moboard.c
+++ b/arch/arm/mach-mx3/mx31moboard.c
@@ -94,7 +94,7 @@ static struct imxi2c_platform_data moboard_i2c1_pdata = {
 
 static int moboard_sdhc1_get_ro(struct device *dev)
 {
-        return gpio_get_value(SDHC1_WP);
+        return !gpio_get_value(SDHC1_WP);
 }
 
 static int moboard_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
diff --git a/arch/arm/mach-mx3/pcm037_eet.c b/arch/arm/mach-mx3/pcm037_eet.c
index fe52fb1bb8b7..8d386000fc40 100644
--- a/arch/arm/mach-mx3/pcm037_eet.c
+++ b/arch/arm/mach-mx3/pcm037_eet.c
@@ -24,15 +24,6 @@
 #include "devices.h"
 
 static unsigned int pcm037_eet_pins[] = {
-        /* SPI #1 */
-        MX31_PIN_CSPI1_MISO__MISO,
-        MX31_PIN_CSPI1_MOSI__MOSI,
-        MX31_PIN_CSPI1_SCLK__SCLK,
-        MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
-        MX31_PIN_CSPI1_SS0__SS0,
-        MX31_PIN_CSPI1_SS1__SS1,
-        MX31_PIN_CSPI1_SS2__SS2,
-
         /* Reserve and hardwire GPIO 57 high - S6E63D6 chipselect */
         IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_GPIO),
         /* GPIO keys */
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 9c3fdcdf76c3..8ec2a132904d 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -141,7 +141,7 @@ static inline void board_smc91x_init(void)
 
 static void __init omap_2430sdp_init_irq(void)
 {
-        omap2_init_common_hw(NULL);
+        omap2_init_common_hw(NULL, NULL);
         omap_init_irq();
         omap_gpio_init();
 }
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 496a90e4ea7a..ac262cd74503 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -169,7 +169,7 @@ static struct platform_device *sdp3430_devices[] __initdata = {
 
 static void __init omap_3430sdp_init_irq(void)
 {
-        omap2_init_common_hw(hyb18m512160af6_sdrc_params);
+        omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL);
         omap_init_irq();
         omap_gpio_init();
 }
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 57e477bd89c6..b0c7402248f7 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -59,7 +59,7 @@ static void __init gic_init_irq(void)
 
 static void __init omap_4430sdp_init_irq(void)
 {
-        omap2_init_common_hw(NULL);
+        omap2_init_common_hw(NULL, NULL);
 #ifdef CONFIG_OMAP_32K_TIMER
         omap2_gp_clockevent_set_gptimer(1);
 #endif
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 06dfba888b0c..dcfc20d03894 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -250,7 +250,7 @@ out:
 
 static void __init omap_apollon_init_irq(void)
 {
-        omap2_init_common_hw(NULL);
+        omap2_init_common_hw(NULL, NULL);
         omap_init_irq();
         omap_gpio_init();
         apollon_init_smc91x();
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 3492162a65c3..fd00aa03690c 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -33,7 +33,7 @@
 
 static void __init omap_generic_init_irq(void)
 {
-        omap2_init_common_hw(NULL);
+        omap2_init_common_hw(NULL, NULL);
         omap_init_irq();
 }
 
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index e7d017cdc438..7b1d61d5bb2c 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -270,7 +270,7 @@ static void __init h4_init_flash(void)
 
 static void __init omap_h4_init_irq(void)
 {
-        omap2_init_common_hw(NULL);
+        omap2_init_common_hw(NULL, NULL);
         omap_init_irq();
         omap_gpio_init();
         h4_init_flash();
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index d8bc0a7dcb8d..ea383f88cb1b 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -270,7 +270,7 @@ static inline void __init ldp_init_smsc911x(void)
 
 static void __init omap_ldp_init_irq(void)
 {
-        omap2_init_common_hw(NULL);
+        omap2_init_common_hw(NULL, NULL);
         omap_init_irq();
         omap_gpio_init();
         ldp_init_smsc911x();
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 991ac9c38032..e00ba128cece 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -282,7 +282,8 @@ static int __init omap3_beagle_i2c_init(void)
 
 static void __init omap3_beagle_init_irq(void)
 {
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
+        omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
+                             mt46h32m32lf6_sdrc_params);
         omap_init_irq();
 #ifdef CONFIG_OMAP_32K_TIMER
         omap2_gp_clockevent_set_gptimer(12);
@@ -408,6 +409,10 @@ static void __init omap3_beagle_init(void)
 
         usb_musb_init();
         omap3beagle_flash_init();
+
+        /* Ensure SDRC pins are mux'd for self-refresh */
+        omap_cfg_reg(H16_34XX_SDRC_CKE0);
+        omap_cfg_reg(H17_34XX_SDRC_CKE1);
 }
 
 static void __init omap3_beagle_map_io(void)
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index cf3dd771a678..c4b144647dc5 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -280,7 +280,7 @@ struct spi_board_info omap3evm_spi_board_info[] = {
 
 static void __init omap3_evm_init_irq(void)
 {
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
+        omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL);
         omap_init_irq();
         omap_gpio_init();
         omap3evm_init_smc911x();
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index e32aa23ce962..864ee3d021f7 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -40,6 +40,7 @@
 #include <mach/mcspi.h>
 #include <mach/usb.h>
 #include <mach/keypad.h>
+#include <mach/mux.h>
 
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "mmc-twl4030.h"
@@ -310,7 +311,8 @@ static int __init omap3pandora_i2c_init(void)
 
 static void __init omap3pandora_init_irq(void)
 {
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
+        omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
+                             mt46h32m32lf6_sdrc_params);
         omap_init_irq();
         omap_gpio_init();
 }
@@ -397,6 +399,10 @@ static void __init omap3pandora_init(void)
         omap3pandora_ads7846_init();
         pandora_keys_gpio_init();
         usb_musb_init();
+
+        /* Ensure SDRC pins are mux'd for self-refresh */
+        omap_cfg_reg(H16_34XX_SDRC_CKE0);
+        omap_cfg_reg(H17_34XX_SDRC_CKE1);
 }
 
 static void __init omap3pandora_map_io(void)
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index dff5528fbfb5..6bce23004aa4 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -44,6 +44,7 @@
 #include <mach/gpmc.h>
 #include <mach/hardware.h>
 #include <mach/nand.h>
+#include <mach/mux.h>
 #include <mach/usb.h>
 
 #include "sdram-micron-mt46h32m32lf-6.h"
@@ -51,6 +52,7 @@
 
 #define OVERO_GPIO_BT_XGATE     15
 #define OVERO_GPIO_W2W_NRESET   16
+#define OVERO_GPIO_PENDOWN      114
 #define OVERO_GPIO_BT_NRESET    164
 #define OVERO_GPIO_USBH_CPEN    168
 #define OVERO_GPIO_USBH_NRESET  183
@@ -146,7 +148,7 @@ static struct platform_device overo_smsc911x_device = {
         .name           = "smsc911x",
         .id             = -1,
         .num_resources  = ARRAY_SIZE(overo_smsc911x_resources),
-        .resource       = &overo_smsc911x_resources,
+        .resource       = overo_smsc911x_resources,
         .dev            = {
                 .platform_data = &overo_smsc911x_config,
         },
@@ -360,7 +362,8 @@ static int __init overo_i2c_init(void)
 
 static void __init overo_init_irq(void)
 {
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
+        omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
+                             mt46h32m32lf6_sdrc_params);
         omap_init_irq();
         omap_gpio_init();
 }
@@ -395,6 +398,10 @@ static void __init overo_init(void)
         overo_ads7846_init();
         overo_init_smsc911x();
 
+        /* Ensure SDRC pins are mux'd for self-refresh */
+        omap_cfg_reg(H16_34XX_SDRC_CKE0);
+        omap_cfg_reg(H17_34XX_SDRC_CKE1);
+
         if ((gpio_request(OVERO_GPIO_W2W_NRESET,
                           "OVERO_GPIO_W2W_NRESET") == 0) &&
             (gpio_direction_output(OVERO_GPIO_W2W_NRESET, 1) == 0)) {
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 9a0bf6744a05..56d931a425f7 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -278,6 +278,10 @@ static struct twl4030_gpio_platform_data rx51_gpio_data = {
         .setup                  = rx51_twlgpio_setup,
 };
 
+static struct twl4030_usb_data rx51_usb_data = {
+        .usb_mode               = T2_USB_MODE_ULPI,
+};
+
 static struct twl4030_platform_data rx51_twldata = {
         .irq_base               = TWL4030_IRQ_BASE,
         .irq_end                = TWL4030_IRQ_END,
@@ -286,6 +290,7 @@ static struct twl4030_platform_data rx51_twldata = {
         .gpio                   = &rx51_gpio_data,
         .keypad                 = &rx51_kp_data,
         .madc                   = &rx51_madc_data,
+        .usb                    = &rx51_usb_data,
 
         .vaux1                  = &rx51_vaux1,
         .vaux2                  = &rx51_vaux2,
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 374ff63c3eb2..1c9e07fe8266 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -61,7 +61,7 @@ static struct omap_board_config_kernel rx51_config[] = {
 
 static void __init rx51_init_irq(void)
 {
-        omap2_init_common_hw(NULL);
+        omap2_init_common_hw(NULL, NULL);
         omap_init_irq();
         omap_gpio_init();
 }
@@ -75,6 +75,10 @@ static void __init rx51_init(void)
         omap_serial_init();
         usb_musb_init();
         rx51_peripherals_init();
+
+        /* Ensure SDRC pins are mux'd for self-refresh */
+        omap_cfg_reg(H16_34XX_SDRC_CKE0);
+        omap_cfg_reg(H17_34XX_SDRC_CKE1);
 }
 
 static void __init rx51_map_io(void)
diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c
index bcc0f7632dea..427b7b8b1237 100644
--- a/arch/arm/mach-omap2/board-zoom2.c
+++ b/arch/arm/mach-omap2/board-zoom2.c
@@ -25,7 +25,7 @@
 
 static void __init omap_zoom2_init_irq(void)
 {
-        omap2_init_common_hw(NULL);
+        omap2_init_common_hw(NULL, NULL);
         omap_init_irq();
         omap_gpio_init();
 }
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index b0665f161c03..456e2ad5f621 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -27,6 +27,7 @@
 #include <mach/clock.h>
 #include <mach/clockdomain.h>
 #include <mach/cpu.h>
+#include <mach/prcm.h>
 #include <asm/div64.h>
 
 #include <mach/sdrc.h>
@@ -38,8 +39,6 @@
 #include "cm-regbits-24xx.h"
 #include "cm-regbits-34xx.h"
 
-#define MAX_CLOCK_ENABLE_WAIT           100000
-
 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
 #define DPLL_MIN_MULTIPLIER             1
 #define DPLL_MIN_DIVIDER                1
@@ -274,83 +273,97 @@ unsigned long omap2_fixed_divisor_recalc(struct clk *clk)
 }
 
 /**
- * omap2_wait_clock_ready - wait for clock to enable
- * @reg: physical address of clock IDLEST register
- * @mask: value to mask against to determine if the clock is active
- * @name: name of the clock (for printk)
+ * omap2_clk_dflt_find_companion - find companion clock to @clk
+ * @clk: struct clk * to find the companion clock of
+ * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
+ * @other_bit: u8 ** to return the companion clock bit shift in
+ *
+ * Note: We don't need special code here for INVERT_ENABLE for the
+ * time being since INVERT_ENABLE only applies to clocks enabled by
+ * CM_CLKEN_PLL
  *
- * Returns 1 if the clock enabled in time, or 0 if it failed to enable
- * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
+ * Convert CM_ICLKEN* <-> CM_FCLKEN*.  This conversion assumes it's
+ * just a matter of XORing the bits.
+ *
+ * Some clocks don't have companion clocks.  For example, modules with
+ * only an interface clock (such as MAILBOXES) don't have a companion
+ * clock.  Right now, this code relies on the hardware exporting a bit
+ * in the correct companion register that indicates that the
+ * nonexistent 'companion clock' is active.  Future patches will
+ * associate this type of code with per-module data structures to
+ * avoid this issue, and remove the casts.  No return value.
  */
-int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
+void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
+                                   u8 *other_bit)
 {
-        int i = 0;
-        int ena = 0;
+        u32 r;
 
         /*
-         * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
-         * 34xx reverses this, just to keep us on our toes
+         * Convert CM_ICLKEN* <-> CM_FCLKEN*.  This conversion assumes
+         * it's just a matter of XORing the bits.
          */
-        if (cpu_mask & (RATE_IN_242X | RATE_IN_243X))
-                ena = mask;
-        else if (cpu_mask & RATE_IN_343X)
-                ena = 0;
-
-        /* Wait for lock */
-        while (((__raw_readl(reg) & mask) != ena) &&
-               (i++ < MAX_CLOCK_ENABLE_WAIT)) {
-                udelay(1);
-        }
-
-        if (i <= MAX_CLOCK_ENABLE_WAIT)
-                pr_debug("Clock %s stable after %d loops\n", name, i);
-        else
-                printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
-                       name, MAX_CLOCK_ENABLE_WAIT);
-
-
-        return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
-};
+        r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN));
 
+        *other_reg = (__force void __iomem *)r;
+        *other_bit = clk->enable_bit;
+}
 
-/*
- * Note: We don't need special code here for INVERT_ENABLE
- * for the time being since INVERT_ENABLE only applies to clocks enabled by
- * CM_CLKEN_PLL
+/**
+ * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk
+ * @clk: struct clk * to find IDLEST info for
+ * @idlest_reg: void __iomem ** to return the CM_IDLEST va in
+ * @idlest_bit: u8 ** to return the CM_IDLEST bit shift in
+ *
+ * Return the CM_IDLEST register address and bit shift corresponding
+ * to the module that "owns" this clock.  This default code assumes
+ * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that
+ * the IDLEST register address ID corresponds to the CM_*CLKEN
+ * register address ID (e.g., that CM_FCLKEN2 corresponds to
+ * CM_IDLEST2).  This is not true for all modules.  No return value.
  */
-static void omap2_clk_wait_ready(struct clk *clk)
+void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
+                                u8 *idlest_bit)
 {
-        void __iomem *reg, *other_reg, *st_reg;
-        u32 bit;
+        u32 r;
 
-        /*
-         * REVISIT: This code is pretty ugly.  It would be nice to generalize
-         * it and pull it into struct clk itself somehow.
-         */
-        reg = clk->enable_reg;
+        r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
+        *idlest_reg = (__force void __iomem *)r;
+        *idlest_bit = clk->enable_bit;
+}
 
-        /*
-         * Convert CM_ICLKEN* <-> CM_FCLKEN*.  This conversion assumes
-         * it's just a matter of XORing the bits.
-         */
-        other_reg = (void __iomem *)((u32)reg ^ (CM_FCLKEN ^ CM_ICLKEN));
+/**
+ * omap2_module_wait_ready - wait for an OMAP module to leave IDLE
+ * @clk: struct clk * belonging to the module
+ *
+ * If the necessary clocks for the OMAP hardware IP block that
+ * corresponds to clock @clk are enabled, then wait for the module to
+ * indicate readiness (i.e., to leave IDLE).  This code does not
+ * belong in the clock code and will be moved in the medium term to
+ * module-dependent code.  No return value.
+ */
+static void omap2_module_wait_ready(struct clk *clk)
+{
+        void __iomem *companion_reg, *idlest_reg;
+        u8 other_bit, idlest_bit;
+
+        /* Not all modules have multiple clocks that their IDLEST depends on */
+        if (clk->ops->find_companion) {
+                clk->ops->find_companion(clk, &companion_reg, &other_bit);
+                if (!(__raw_readl(companion_reg) & (1 << other_bit)))
+                        return;
+        }
 
-        /* Check if both functional and interface clocks
-         * are running. */
-        bit = 1 << clk->enable_bit;
-        if (!(__raw_readl(other_reg) & bit))
-                return;
-        st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
+        clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit);
 
-        omap2_wait_clock_ready(st_reg, bit, clk->name);
+        omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), clk->name);
 }
 
-static int omap2_dflt_clk_enable(struct clk *clk)
+int omap2_dflt_clk_enable(struct clk *clk)
 {
         u32 v;
 
         if (unlikely(clk->enable_reg == NULL)) {
-                printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
+                pr_err("clock.c: Enable for %s without enable code\n",
                        clk->name);
                 return 0; /* REVISIT: -EINVAL */
         }
@@ -363,26 +376,13 @@ static int omap2_dflt_clk_enable(struct clk *clk)
         __raw_writel(v, clk->enable_reg);
         v = __raw_readl(clk->enable_reg); /* OCP barrier */
 
-        return 0;
-}
+        if (clk->ops->find_idlest)
+                omap2_module_wait_ready(clk);
 
-static int omap2_dflt_clk_enable_wait(struct clk *clk)
-{
-        int ret;
-
-        if (!clk->enable_reg) {
-                printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
-                       clk->name);
-                return 0; /* REVISIT: -EINVAL */
-        }
-
-        ret = omap2_dflt_clk_enable(clk);
-        if (ret == 0)
-                omap2_clk_wait_ready(clk);
-        return ret;
+        return 0;
 }
 
-static void omap2_dflt_clk_disable(struct clk *clk)
+void omap2_dflt_clk_disable(struct clk *clk)
 {
         u32 v;
 
@@ -406,8 +406,10 @@ static void omap2_dflt_clk_disable(struct clk *clk)
 }
 
 const struct clkops clkops_omap2_dflt_wait = {
-        .enable         = omap2_dflt_clk_enable_wait,
+        .enable         = omap2_dflt_clk_enable,
         .disable        = omap2_dflt_clk_disable,
+        .find_companion = omap2_clk_dflt_find_companion,
+        .find_idlest    = omap2_clk_dflt_find_idlest,
 };
 
 const struct clkops clkops_omap2_dflt = {
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 2679ddfa6424..9ae7540f8af2 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -65,6 +65,12 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
 u32 omap2_get_dpll_rate(struct clk *clk);
 int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
 void omap2_clk_prepare_for_reboot(void);
+int omap2_dflt_clk_enable(struct clk *clk);
+void omap2_dflt_clk_disable(struct clk *clk);
+void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
+                                   u8 *other_bit);
+void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
+                                u8 *idlest_bit);
 
 extern const struct clkops clkops_omap2_dflt_wait;
 extern const struct clkops clkops_omap2_dflt;
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index 44de0271fc2f..bc5d3ac66611 100644
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -30,6 +30,7 @@
 
 #include <mach/clock.h>
 #include <mach/sram.h>
+#include <mach/prcm.h>
 #include <asm/div64.h>
 #include <asm/clkdev.h>
 
@@ -43,6 +44,18 @@
 static const struct clkops clkops_oscck;
 static const struct clkops clkops_fixed;
 
+static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
+                                           void __iomem **idlest_reg,
+                                           u8 *idlest_bit);
+
+/* 2430 I2CHS has non-standard IDLEST register */
+static const struct clkops clkops_omap2430_i2chs_wait = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+        .find_idlest    = omap2430_clk_i2chs_find_idlest,
+        .find_companion = omap2_clk_dflt_find_companion,
+};
+
 #include "clock24xx.h"
 
 struct omap_clk {
@@ -240,6 +253,26 @@ static void __iomem *prcm_clksrc_ctrl;
  *-------------------------------------------------------------------------*/
 
 /**
+ * omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS
+ * @clk: struct clk * being enabled
+ * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
+ * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
+ *
+ * OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the
+ * CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE.  This custom function
+ * passes back the correct CM_IDLEST register address for I2CHS
+ * modules.  No return value.
+ */
+static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
+                                           void __iomem **idlest_reg,
+                                           u8 *idlest_bit)
+{
+        *idlest_reg = OMAP_CM_REGADDR(CORE_MOD, CM_IDLEST);
+        *idlest_bit = clk->enable_bit;
+}
+
+
+/**
  * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
  * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")
  *
@@ -325,8 +358,8 @@ static int omap2_clk_fixed_enable(struct clk *clk)
         else if (clk == &apll54_ck)
                 cval = OMAP24XX_ST_54M_APLL;
 
-        omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
-                            clk->name);
+        omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
+                             clk->name);
 
         /*
          * REVISIT: Should we return an error code if omap2_wait_clock_ready()
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index 458f00cdcbea..d19cf7a7d8db 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -2337,7 +2337,7 @@ static struct clk i2c2_fck = {
 
 static struct clk i2chs2_fck = {
         .name           = "i2c_fck",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2430_i2chs_wait,
         .id             = 2,
         .parent         = &func_96m_ck,
         .clkdm_name     = "core_l4_clkdm",
@@ -2370,7 +2370,7 @@ static struct clk i2c1_fck = {
 
 static struct clk i2chs1_fck = {
         .name           = "i2c_fck",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2430_i2chs_wait,
         .id             = 1,
         .parent         = &func_96m_ck,
         .clkdm_name     = "core_l4_clkdm",
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 045da923e75b..cd7819cc0c9e 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -2,7 +2,7 @@
  * OMAP3-specific clock framework functions
  *
  * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2008 Nokia Corporation
+ * Copyright (C) 2007-2009 Nokia Corporation
  *
  * Written by Paul Walmsley
  * Testing and integration fixes by Jouni Högander
@@ -41,6 +41,37 @@
 
 static const struct clkops clkops_noncore_dpll_ops;
 
+static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
+                                            void __iomem **idlest_reg,
+                                            u8 *idlest_bit);
+static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
+                                            void __iomem **idlest_reg,
+                                            u8 *idlest_bit);
+static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
+                                                    void __iomem **idlest_reg,
+                                                    u8 *idlest_bit);
+
+static const struct clkops clkops_omap3430es2_ssi_wait = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+        .find_idlest    = omap3430es2_clk_ssi_find_idlest,
+        .find_companion = omap2_clk_dflt_find_companion,
+};
+
+static const struct clkops clkops_omap3430es2_hsotgusb_wait = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+        .find_idlest    = omap3430es2_clk_hsotgusb_find_idlest,
+        .find_companion = omap2_clk_dflt_find_companion,
+};
+
+static const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+        .find_idlest    = omap3430es2_clk_dss_usbhost_find_idlest,
+        .find_companion = omap2_clk_dflt_find_companion,
+};
+
 #include "clock34xx.h"
 
 struct omap_clk {
@@ -157,10 +188,13 @@ static struct omap_clk omap34xx_clks[] = {
         CLK(NULL,       "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
         CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_343X),
         CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_343X),
-        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck,   CK_343X),
-        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck,   CK_343X),
+        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1,   CK_3430ES1),
+        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2,   CK_3430ES2),
+        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1,   CK_3430ES1),
+        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es2,   CK_3430ES2),
         CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_343X),
-        CLK("musb_hdrc",        "ick",  &hsotgusb_ick,  CK_343X),
+        CLK("musb_hdrc",        "ick",  &hsotgusb_ick_3430es1,  CK_3430ES1),
+        CLK("musb_hdrc",        "ick",  &hsotgusb_ick_3430es2,  CK_3430ES2),
         CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_343X),
         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_343X),
         CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_343X),
@@ -193,18 +227,21 @@ static struct omap_clk omap34xx_clks[] = {
         CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_343X),
         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_343X),
         CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_343X),
-        CLK(NULL,       "ssi_ick",      &ssi_ick,       CK_343X),
+        CLK(NULL,       "ssi_ick",      &ssi_ick_3430es1,       CK_3430ES1),
+        CLK(NULL,       "ssi_ick",      &ssi_ick_3430es2,       CK_3430ES2),
         CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_3430ES1),
         CLK(NULL,       "security_l4_ick2", &security_l4_ick2, CK_343X),
         CLK(NULL,       "aes1_ick",     &aes1_ick,      CK_343X),
         CLK("omap_rng", "ick",          &rng_ick,       CK_343X),
         CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_343X),
         CLK(NULL,       "des1_ick",     &des1_ick,      CK_343X),
-        CLK("omapfb",   "dss1_fck",     &dss1_alwon_fck, CK_343X),
+        CLK("omapfb",   "dss1_fck",     &dss1_alwon_fck_3430es1, CK_3430ES1),
+        CLK("omapfb",   "dss1_fck",     &dss1_alwon_fck_3430es2, CK_3430ES2),
         CLK("omapfb",   "tv_fck",       &dss_tv_fck,    CK_343X),
         CLK("omapfb",   "video_fck",    &dss_96m_fck,   CK_343X),
         CLK("omapfb",   "dss2_fck",     &dss2_alwon_fck, CK_343X),
-        CLK("omapfb",   "ick",          &dss_ick,       CK_343X),
+        CLK("omapfb",   "ick",          &dss_ick_3430es1,       CK_3430ES1),
+        CLK("omapfb",   "ick",          &dss_ick_3430es2,       CK_3430ES2),
         CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_343X),
         CLK(NULL,       "cam_ick",      &cam_ick,       CK_343X),
         CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_343X),
@@ -301,6 +338,73 @@ static struct omap_clk omap34xx_clks[] = {
 #define SDRC_MPURATE_LOOPS              96
 
 /**
+ * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
+ * @clk: struct clk * being enabled
+ * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
+ * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
+ *
+ * The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift
+ * from the CM_{I,F}CLKEN bit.  Pass back the correct info via
+ * @idlest_reg and @idlest_bit.  No return value.
+ */
+static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
+                                            void __iomem **idlest_reg,
+                                            u8 *idlest_bit)
+{
+        u32 r;
+
+        r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
+        *idlest_reg = (__force void __iomem *)r;
+        *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT;
+}
+
+/**
+ * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
+ * @clk: struct clk * being enabled
+ * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
+ * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
+ *
+ * Some OMAP modules on OMAP3 ES2+ chips have both initiator and
+ * target IDLEST bits.  For our purposes, we are concerned with the
+ * target IDLEST bits, which exist at a different bit position than
+ * the *CLKEN bit position for these modules (DSS and USBHOST) (The
+ * default find_idlest code assumes that they are at the same
+ * position.)  No return value.
+ */
+static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
+                                                    void __iomem **idlest_reg,
+                                                    u8 *idlest_bit)
+{
+        u32 r;
+
+        r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
+        *idlest_reg = (__force void __iomem *)r;
+        /* USBHOST_IDLE has same shift */
+        *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT;
+}
+
+/**
+ * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
+ * @clk: struct clk * being enabled
+ * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
+ * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
+ *
+ * The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different
+ * shift from the CM_{I,F}CLKEN bit.  Pass back the correct info via
+ * @idlest_reg and @idlest_bit.  No return value.
+ */
+static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
+                                                 void __iomem **idlest_reg,
+                                                 u8 *idlest_bit)
+{
+        u32 r;
+
+        r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
+        *idlest_reg = (__force void __iomem *)r;
+        *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT;
+}
+
+/**
  * omap3_dpll_recalc - recalculate DPLL rate
  * @clk: DPLL struct clk
  *
@@ -725,7 +829,9 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
         u32 unlock_dll = 0;
         u32 c;
         unsigned long validrate, sdrcrate, mpurate;
-        struct omap_sdrc_params *sp;
+        struct omap_sdrc_params *sdrc_cs0;
+        struct omap_sdrc_params *sdrc_cs1;
+        int ret;
 
         if (!clk || !rate)
                 return -EINVAL;
@@ -743,8 +849,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
         else
                 sdrcrate >>= ((clk->rate / rate) >> 1);
 
-        sp = omap2_sdrc_get_params(sdrcrate);
-        if (!sp)
+        ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
+        if (ret)
                 return -EINVAL;
 
         if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
@@ -765,12 +871,29 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 
         pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
                  validrate);
-        pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
-                 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
-
-        omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
-                                  sp->actim_ctrlb, new_div, unlock_dll, c,
-                                  sp->mr, rate > clk->rate);
+        pr_debug("clock: SDRC CS0 timing params used:"
+                 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
+                 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
+                 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
+        if (sdrc_cs1)
+                pr_debug("clock: SDRC CS1 timing params used: "
+                 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
+                 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
+                 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
+
+        if (sdrc_cs1)
+                omap3_configure_core_dpll(
+                                  new_div, unlock_dll, c, rate > clk->rate,
+                                  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
+                                  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
+                                  sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
+                                  sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
+        else
+                omap3_configure_core_dpll(
+                                  new_div, unlock_dll, c, rate > clk->rate,
+                                  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
+                                  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
+                                  0, 0, 0, 0);
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index e433aec4efdd..57cc2725b923 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -1568,7 +1568,7 @@ static const struct clksel ssi_ssr_clksel[] = {
         { .parent = NULL }
 };
 
-static struct clk ssi_ssr_fck = {
+static struct clk ssi_ssr_fck_3430es1 = {
         .name           = "ssi_ssr_fck",
         .ops            = &clkops_omap2_dflt,
         .init           = &omap2_init_clksel_parent,
@@ -1581,10 +1581,31 @@ static struct clk ssi_ssr_fck = {
         .recalc         = &omap2_clksel_recalc,
 };
 
-static struct clk ssi_sst_fck = {
+static struct clk ssi_ssr_fck_3430es2 = {
+        .name           = "ssi_ssr_fck",
+        .ops            = &clkops_omap3430es2_ssi_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
+        .clksel         = ssi_ssr_clksel,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk ssi_sst_fck_3430es1 = {
         .name           = "ssi_sst_fck",
         .ops            = &clkops_null,
-        .parent         = &ssi_ssr_fck,
+        .parent         = &ssi_ssr_fck_3430es1,
+        .fixed_div      = 2,
+        .recalc         = &omap2_fixed_divisor_recalc,
+};
+
+static struct clk ssi_sst_fck_3430es2 = {
+        .name           = "ssi_sst_fck",
+        .ops            = &clkops_null,
+        .parent         = &ssi_ssr_fck_3430es2,
         .fixed_div      = 2,
         .recalc         = &omap2_fixed_divisor_recalc,
 };
@@ -1606,9 +1627,19 @@ static struct clk core_l3_ick = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk hsotgusb_ick = {
+static struct clk hsotgusb_ick_3430es1 = {
         .name           = "hsotgusb_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &core_l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
+        .clkdm_name     = "core_l3_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk hsotgusb_ick_3430es2 = {
+        .name           = "hsotgusb_ick",
+        .ops            = &clkops_omap3430es2_hsotgusb_wait,
         .parent         = &core_l3_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
@@ -1947,7 +1978,7 @@ static struct clk ssi_l4_ick = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk ssi_ick = {
+static struct clk ssi_ick_3430es1 = {
         .name           = "ssi_ick",
         .ops            = &clkops_omap2_dflt,
         .parent         = &ssi_l4_ick,
@@ -1957,6 +1988,16 @@ static struct clk ssi_ick = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk ssi_ick_3430es2 = {
+        .name           = "ssi_ick",
+        .ops            = &clkops_omap3430es2_ssi_wait,
+        .parent         = &ssi_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
  * but l4_ick makes more sense to me */
 
@@ -2024,7 +2065,7 @@ static struct clk des1_ick = {
 };
 
 /* DSS */
-static struct clk dss1_alwon_fck = {
+static struct clk dss1_alwon_fck_3430es1 = {
         .name           = "dss1_alwon_fck",
         .ops            = &clkops_omap2_dflt,
         .parent         = &dpll4_m4x2_ck,
@@ -2034,6 +2075,16 @@ static struct clk dss1_alwon_fck = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk dss1_alwon_fck_3430es2 = {
+        .name           = "dss1_alwon_fck",
+        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
+        .parent         = &dpll4_m4x2_ck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk dss_tv_fck = {
         .name           = "dss_tv_fck",
         .ops            = &clkops_omap2_dflt,
@@ -2067,7 +2118,7 @@ static struct clk dss2_alwon_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk dss_ick = {
+static struct clk dss_ick_3430es1 = {
         /* Handles both L3 and L4 clocks */
         .name           = "dss_ick",
         .ops            = &clkops_omap2_dflt,
@@ -2079,6 +2130,18 @@ static struct clk dss_ick = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk dss_ick_3430es2 = {
+        /* Handles both L3 and L4 clocks */
+        .name           = "dss_ick",
+        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
+        .parent         = &l4_ick,
+        .init           = &omap2_init_clk_clkdm,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
 /* CAM */
 
 static struct clk cam_mclk = {
@@ -2118,7 +2181,7 @@ static struct clk csi2_96m_fck = {
 
 static struct clk usbhost_120m_fck = {
         .name           = "usbhost_120m_fck",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_dflt,
         .parent         = &dpll5_m2_ck,
         .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
@@ -2129,7 +2192,7 @@ static struct clk usbhost_120m_fck = {
 
 static struct clk usbhost_48m_fck = {
         .name           = "usbhost_48m_fck",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
         .parent         = &omap_48m_fck,
         .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
@@ -2141,7 +2204,7 @@ static struct clk usbhost_48m_fck = {
 static struct clk usbhost_ick = {
         /* Handles both L3 and L4 clocks */
         .name           = "usbhost_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
         .parent         = &l4_ick,
         .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index 1d3c93bf86d3..f3c91a1ca391 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -29,9 +29,9 @@
  * These registers appear once per CM module.
  */
 
-#define OMAP3430_CM_REVISION            OMAP_CM_REGADDR(OCP_MOD, 0x0000)
-#define OMAP3430_CM_SYSCONFIG           OMAP_CM_REGADDR(OCP_MOD, 0x0010)
-#define OMAP3430_CM_POLCTRL             OMAP_CM_REGADDR(OCP_MOD, 0x009c)
+#define OMAP3430_CM_REVISION            OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
+#define OMAP3430_CM_SYSCONFIG           OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
+#define OMAP3430_CM_POLCTRL             OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
 
 #define OMAP3_CM_CLKOUT_CTRL_OFFSET     0x0070
 #define OMAP3430_CM_CLKOUT_CTRL         OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 3a86b0f66031..e9b9bcb19b4e 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -276,14 +276,15 @@ static int __init _omap2_init_reprogram_sdrc(void)
         return v;
 }
 
-void __init omap2_init_common_hw(struct omap_sdrc_params *sp)
+void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
+                                 struct omap_sdrc_params *sdrc_cs1)
 {
         omap2_mux_init();
 #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
         pwrdm_init(powerdomains_omap);
         clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
         omap2_clk_init();
-        omap2_sdrc_init(sp);
+        omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
         _omap2_init_reprogram_sdrc();
 #endif
         gpmc_init();
diff --git a/arch/arm/mach-omap2/mmc-twl4030.c b/arch/arm/mach-omap2/mmc-twl4030.c
index 1541fd4c8d0f..3c04c2f1b23f 100644
--- a/arch/arm/mach-omap2/mmc-twl4030.c
+++ b/arch/arm/mach-omap2/mmc-twl4030.c
@@ -119,6 +119,7 @@ static int twl_mmc_late_init(struct device *dev)
                                 if (i != 0)
                                         break;
                                 ret = PTR_ERR(reg);
+                                hsmmc[i].vcc = NULL;
                                 goto err;
                         }
                         hsmmc[i].vcc = reg;
@@ -165,8 +166,13 @@ done:
 static void twl_mmc_cleanup(struct device *dev)
 {
         struct omap_mmc_platform_data *mmc = dev->platform_data;
+        int i;
 
         gpio_free(mmc->slots[0].switch_pin);
+        for(i = 0; i < ARRAY_SIZE(hsmmc); i++) {
+                regulator_put(hsmmc[i].vcc);
+                regulator_put(hsmmc[i].vcc_aux);
+        }
 }
 
 #ifdef CONFIG_PM
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 026c4fc883a7..43d6b92b65f2 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -486,6 +486,12 @@ MUX_CFG_34XX("H19_34XX_GPIO164_OUT", 0x19c,
                 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
 MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6,
                 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
+
+/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
+MUX_CFG_34XX("H16_34XX_SDRC_CKE0", 0x262,
+                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
+MUX_CFG_34XX("H17_34XX_SDRC_CKE1", 0x264,
+                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
 };
 
 #define OMAP34XX_PINS_SZ        ARRAY_SIZE(omap34xx_pins)
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index f7b3baf76678..21201cd4117b 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -11,9 +11,6 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PM_H
 #define __ARCH_ARM_MACH_OMAP2_PM_H
 
-extern int omap2_pm_init(void);
-extern int omap3_pm_init(void);
-
 #ifdef CONFIG_PM_DEBUG
 extern void omap2_pm_dump(int mode, int resume, unsigned int us);
 extern int omap2_pm_debug;
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index db1025562fb0..528dbdc26e23 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -470,7 +470,7 @@ static void __init prcm_setup_regs(void)
                           WKUP_MOD, PM_WKEN);
 }
 
-int __init omap2_pm_init(void)
+static int __init omap2_pm_init(void)
 {
         u32 l;
 
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 841d4c5ed8be..488d595d8e4b 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -39,7 +39,9 @@
 struct power_state {
         struct powerdomain *pwrdm;
         u32 next_state;
+#ifdef CONFIG_SUSPEND
         u32 saved_state;
+#endif
         struct list_head node;
 };
 
@@ -293,6 +295,9 @@ out:
         local_irq_enable();
 }
 
+#ifdef CONFIG_SUSPEND
+static suspend_state_t suspend_state;
+
 static int omap3_pm_prepare(void)
 {
         disable_hlt();
@@ -321,7 +326,6 @@ static int omap3_pm_suspend(void)
 restore:
         /* Restore next_pwrsts */
         list_for_each_entry(pwrst, &pwrst_list, node) {
-                set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
                 if (state > pwrst->next_state) {
                         printk(KERN_INFO "Powerdomain (%s) didn't enter "
@@ -329,6 +333,7 @@ restore:
                                pwrst->pwrdm->name, pwrst->next_state);
                         ret = -1;
                 }
+                set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
         }
         if (ret)
                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
@@ -339,11 +344,11 @@ restore:
         return ret;
 }
 
-static int omap3_pm_enter(suspend_state_t state)
+static int omap3_pm_enter(suspend_state_t unused)
 {
         int ret = 0;
 
-        switch (state) {
+        switch (suspend_state) {
         case PM_SUSPEND_STANDBY:
         case PM_SUSPEND_MEM:
                 ret = omap3_pm_suspend();
@@ -360,12 +365,30 @@ static void omap3_pm_finish(void)
         enable_hlt();
 }
 
+/* Hooks to enable / disable UART interrupts during suspend */
+static int omap3_pm_begin(suspend_state_t state)
+{
+        suspend_state = state;
+        omap_uart_enable_irqs(0);
+        return 0;
+}
+
+static void omap3_pm_end(void)
+{
+        suspend_state = PM_SUSPEND_ON;
+        omap_uart_enable_irqs(1);
+        return;
+}
+
 static struct platform_suspend_ops omap_pm_ops = {
+        .begin          = omap3_pm_begin,
+        .end            = omap3_pm_end,
         .prepare        = omap3_pm_prepare,
         .enter          = omap3_pm_enter,
         .finish         = omap3_pm_finish,
         .valid          = suspend_valid_only_mem,
 };
+#endif /* CONFIG_SUSPEND */
 
 
 /**
@@ -613,6 +636,24 @@ static void __init prcm_setup_regs(void)
         /* Clear any pending PRCM interrupts */
         prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 
+        /* Don't attach IVA interrupts */
+        prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
+        prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
+        prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
+        prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
+
+        /* Clear any pending 'reset' flags */
+        prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
+        prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
+        prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
+        prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
+        prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
+        prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
+        prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
+
+        /* Clear any pending PRCM interrupts */
+        prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+
         omap3_iva_idle();
         omap3_d2d_idle();
 }
@@ -652,7 +693,7 @@ static int __init clkdms_setup(struct clockdomain *clkdm)
         return 0;
 }
 
-int __init omap3_pm_init(void)
+static int __init omap3_pm_init(void)
 {
         struct power_state *pwrst, *tmp;
         int ret;
@@ -692,7 +733,9 @@ int __init omap3_pm_init(void)
         _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
                                          omap34xx_cpu_suspend_sz);
 
+#ifdef CONFIG_SUSPEND
         suspend_set_ops(&omap_pm_ops);
+#endif /* CONFIG_SUSPEND */
 
         pm_idle = omap3_pm_idle;
 
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index f945156d5585..ced555a4cd1a 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -17,6 +17,7 @@
 #include <linux/init.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/delay.h>
 
 #include <mach/common.h>
 #include <mach/prcm.h>
@@ -28,6 +29,8 @@
 static void __iomem *prm_base;
 static void __iomem *cm_base;
 
+#define MAX_MODULE_ENABLE_WAIT          100000
+
 u32 omap_prcm_get_reset_sources(void)
 {
         /* XXX This presumably needs modification for 34XX */
@@ -120,6 +123,46 @@ u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
 }
 EXPORT_SYMBOL(cm_rmw_mod_reg_bits);
 
+/**
+ * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
+ * @reg: physical address of module IDLEST register
+ * @mask: value to mask against to determine if the module is active
+ * @name: name of the clock (for printk)
+ *
+ * Returns 1 if the module indicated readiness in time, or 0 if it
+ * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
+ */
+int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name)
+{
+        int i = 0;
+        int ena = 0;
+
+        /*
+         * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
+         * 34xx reverses this, just to keep us on our toes
+         */
+        if (cpu_is_omap24xx())
+                ena = mask;
+        else if (cpu_is_omap34xx())
+                ena = 0;
+        else
+                BUG();
+
+        /* Wait for lock */
+        while (((__raw_readl(reg) & mask) != ena) &&
+               (i++ < MAX_MODULE_ENABLE_WAIT))
+                udelay(1);
+
+        if (i < MAX_MODULE_ENABLE_WAIT)
+                pr_debug("cm: Module associated with clock %s ready after %d "
+                         "loops\n", name, i);
+        else
+                pr_err("cm: Module associated with clock %s didn't enable in "
+                       "%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
+
+        return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
+};
+
 void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
 {
         prm_base = omap2_globals->prm;
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
index 2045441e8385..9e3bd4fa7810 100644
--- a/arch/arm/mach-omap2/sdrc.c
+++ b/arch/arm/mach-omap2/sdrc.c
@@ -32,7 +32,7 @@
 #include <mach/sdrc.h>
 #include "sdrc.h"
 
-static struct omap_sdrc_params *sdrc_init_params;
+static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
 
 void __iomem *omap2_sdrc_base;
 void __iomem *omap2_sms_base;
@@ -45,33 +45,49 @@ void __iomem *omap2_sms_base;
 /**
  * omap2_sdrc_get_params - return SDRC register values for a given clock rate
  * @r: SDRC clock rate (in Hz)
+ * @sdrc_cs0: chip select 0 ram timings **
+ * @sdrc_cs1: chip select 1 ram timings **
  *
  * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
- * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL, and SDRC_MR registers, for a given
- * SDRC clock rate 'r'.  These parameters control various timing
- * delays in the SDRAM controller that are expressed in terms of the
- * number of SDRC clock cycles to wait; hence the clock rate
- * dependency. Note that sdrc_init_params must be sorted rate
- * descending.  Also assumes that both chip-selects use the same
- * timing parameters.  Returns a struct omap_sdrc_params * upon
- * success, or NULL upon failure.
+ *  SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01]
+ *  structs,for a given SDRC clock rate 'r'.
+ * These parameters control various timing delays in the SDRAM controller
+ *  that are expressed in terms of the number of SDRC clock cycles to
+ *  wait; hence the clock rate dependency.
+ *
+ * Supports 2 different timing parameters for both chip selects.
+ *
+ * Note 1: the sdrc_init_params_cs[01] must be sorted rate descending.
+ * Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size
+ *  as sdrc_init_params_cs_0.
+ *
+ * Fills in the struct omap_sdrc_params * for each chip select.
+ * Returns 0 upon success or -1 upon failure.
  */
-struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r)
+int omap2_sdrc_get_params(unsigned long r,
+                          struct omap_sdrc_params **sdrc_cs0,
+                          struct omap_sdrc_params **sdrc_cs1)
 {
-        struct omap_sdrc_params *sp;
+        struct omap_sdrc_params *sp0, *sp1;
 
-        if (!sdrc_init_params)
-                return NULL;
+        if (!sdrc_init_params_cs0)
+                return -1;
 
-        sp = sdrc_init_params;
+        sp0 = sdrc_init_params_cs0;
+        sp1 = sdrc_init_params_cs1;
 
-        while (sp->rate && sp->rate != r)
-                sp++;
+        while (sp0->rate && sp0->rate != r) {
+                sp0++;
+                if (sdrc_init_params_cs1)
+                        sp1++;
+        }
 
-        if (!sp->rate)
-                return NULL;
+        if (!sp0->rate)
+                return -1;
 
-        return sp;
+        *sdrc_cs0 = sp0;
+        *sdrc_cs1 = sp1;
+        return 0;
 }
 
 
@@ -83,13 +99,15 @@ void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
 
 /**
  * omap2_sdrc_init - initialize SMS, SDRC devices on boot
- * @sp: pointer to a null-terminated list of struct omap_sdrc_params
+ * @sdrc_cs[01]: pointers to a null-terminated list of struct omap_sdrc_params
+ *  Support for 2 chip selects timings
  *
  * Turn on smart idle modes for SDRAM scheduler and controller.
  * Program a known-good configuration for the SDRC to deal with buggy
  * bootloaders.
  */
-void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
+void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
+                            struct omap_sdrc_params *sdrc_cs1)
 {
         u32 l;
 
@@ -103,11 +121,15 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
         l |= (0x2 << 3);
         sdrc_write_reg(l, SDRC_SYSCONFIG);
 
-        sdrc_init_params = sp;
+        sdrc_init_params_cs0 = sdrc_cs0;
+        sdrc_init_params_cs1 = sdrc_cs1;
 
         /* XXX Enable SRFRONIDLEREQ here also? */
+        /*
+         * PWDENA should not be set due to 34xx erratum 1.150 - PWDENA
+         * can cause random memory corruption
+         */
         l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
-                (1 << SDRC_POWER_PWDENA_SHIFT) |
                 (1 << SDRC_POWER_PAGEPOLICY_SHIFT);
         sdrc_write_reg(l, SDRC_POWER);
 }
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index b094c15bfe47..a7421a50410b 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -54,6 +54,7 @@ struct omap_uart_state {
 
         struct plat_serial8250_port *p;
         struct list_head node;
+        struct platform_device pdev;
 
 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
         int context_valid;
@@ -68,10 +69,9 @@ struct omap_uart_state {
 #endif
 };
 
-static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS];
 static LIST_HEAD(uart_list);
 
-static struct plat_serial8250_port serial_platform_data[] = {
+static struct plat_serial8250_port serial_platform_data0[] = {
         {
                 .membase        = IO_ADDRESS(OMAP_UART1_BASE),
                 .mapbase        = OMAP_UART1_BASE,
@@ -81,6 +81,12 @@ static struct plat_serial8250_port serial_platform_data[] = {
                 .regshift       = 2,
                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
         }, {
+                .flags          = 0
+        }
+};
+
+static struct plat_serial8250_port serial_platform_data1[] = {
+        {
                 .membase        = IO_ADDRESS(OMAP_UART2_BASE),
                 .mapbase        = OMAP_UART2_BASE,
                 .irq            = 73,
@@ -89,6 +95,12 @@ static struct plat_serial8250_port serial_platform_data[] = {
                 .regshift       = 2,
                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
         }, {
+                .flags          = 0
+        }
+};
+
+static struct plat_serial8250_port serial_platform_data2[] = {
+        {
                 .membase        = IO_ADDRESS(OMAP_UART3_BASE),
                 .mapbase        = OMAP_UART3_BASE,
                 .irq            = 74,
@@ -217,6 +229,40 @@ static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
         clk_disable(uart->fck);
 }
 
+static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
+{
+        /* Set wake-enable bit */
+        if (uart->wk_en && uart->wk_mask) {
+                u32 v = __raw_readl(uart->wk_en);
+                v |= uart->wk_mask;
+                __raw_writel(v, uart->wk_en);
+        }
+
+        /* Ensure IOPAD wake-enables are set */
+        if (cpu_is_omap34xx() && uart->padconf) {
+                u16 v = omap_ctrl_readw(uart->padconf);
+                v |= OMAP3_PADCONF_WAKEUPENABLE0;
+                omap_ctrl_writew(v, uart->padconf);
+        }
+}
+
+static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
+{
+        /* Clear wake-enable bit */
+        if (uart->wk_en && uart->wk_mask) {
+                u32 v = __raw_readl(uart->wk_en);
+                v &= ~uart->wk_mask;
+                __raw_writel(v, uart->wk_en);
+        }
+
+        /* Ensure IOPAD wake-enables are cleared */
+        if (cpu_is_omap34xx() && uart->padconf) {
+                u16 v = omap_ctrl_readw(uart->padconf);
+                v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
+                omap_ctrl_writew(v, uart->padconf);
+        }
+}
+
 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
                                           int enable)
 {
@@ -246,6 +292,11 @@ static void omap_uart_block_sleep(struct omap_uart_state *uart)
 
 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
 {
+        if (device_may_wakeup(&uart->pdev.dev))
+                omap_uart_enable_wakeup(uart);
+        else
+                omap_uart_disable_wakeup(uart);
+
         if (!uart->clocked)
                 return;
 
@@ -292,7 +343,6 @@ void omap_uart_resume_idle(int num)
                         /* Check for normal UART wakeup */
                         if (__raw_readl(uart->wk_st) & uart->wk_mask)
                                 omap_uart_block_sleep(uart);
-
                         return;
                 }
         }
@@ -346,16 +396,13 @@ static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
         return IRQ_NONE;
 }
 
-static u32 sleep_timeout = DEFAULT_TIMEOUT;
-
 static void omap_uart_idle_init(struct omap_uart_state *uart)
 {
-        u32 v;
         struct plat_serial8250_port *p = uart->p;
         int ret;
 
         uart->can_sleep = 0;
-        uart->timeout = sleep_timeout;
+        uart->timeout = DEFAULT_TIMEOUT;
         setup_timer(&uart->timer, omap_uart_idle_timer,
                     (unsigned long) uart);
         mod_timer(&uart->timer, jiffies + uart->timeout);
@@ -413,76 +460,101 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
                 uart->padconf = 0;
         }
 
-        /* Set wake-enable bit */
-        if (uart->wk_en && uart->wk_mask) {
-                v = __raw_readl(uart->wk_en);
-                v |= uart->wk_mask;
-                __raw_writel(v, uart->wk_en);
-        }
-
-        /* Ensure IOPAD wake-enables are set */
-        if (cpu_is_omap34xx() && uart->padconf) {
-                u16 v;
-
-                v = omap_ctrl_readw(uart->padconf);
-                v |= OMAP3_PADCONF_WAKEUPENABLE0;
-                omap_ctrl_writew(v, uart->padconf);
-        }
-
         p->flags |= UPF_SHARE_IRQ;
         ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
                           "serial idle", (void *)uart);
         WARN_ON(ret);
 }
 
-static ssize_t sleep_timeout_show(struct kobject *kobj,
-                                  struct kobj_attribute *attr,
+void omap_uart_enable_irqs(int enable)
+{
+        int ret;
+        struct omap_uart_state *uart;
+
+        list_for_each_entry(uart, &uart_list, node) {
+                if (enable)
+                        ret = request_irq(uart->p->irq, omap_uart_interrupt,
+                                IRQF_SHARED, "serial idle", (void *)uart);
+                else
+                        free_irq(uart->p->irq, (void *)uart);
+        }
+}
+
+static ssize_t sleep_timeout_show(struct device *dev,
+                                  struct device_attribute *attr,
                                   char *buf)
 {
-        return sprintf(buf, "%u\n", sleep_timeout / HZ);
+        struct platform_device *pdev = container_of(dev,
+                                        struct platform_device, dev);
+        struct omap_uart_state *uart = container_of(pdev,
+                                        struct omap_uart_state, pdev);
+
+        return sprintf(buf, "%u\n", uart->timeout / HZ);
 }
 
-static ssize_t sleep_timeout_store(struct kobject *kobj,
-                                   struct kobj_attribute *attr,
+static ssize_t sleep_timeout_store(struct device *dev,
+                                   struct device_attribute *attr,
                                    const char *buf, size_t n)
 {
-        struct omap_uart_state *uart;
+        struct platform_device *pdev = container_of(dev,
+                                        struct platform_device, dev);
+        struct omap_uart_state *uart = container_of(pdev,
+                                        struct omap_uart_state, pdev);
         unsigned int value;
 
         if (sscanf(buf, "%u", &value) != 1) {
                 printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
                 return -EINVAL;
         }
-        sleep_timeout = value * HZ;
-        list_for_each_entry(uart, &uart_list, node) {
-                uart->timeout = sleep_timeout;
-                if (uart->timeout)
-                        mod_timer(&uart->timer, jiffies + uart->timeout);
-                else
-                        /* A zero value means disable timeout feature */
-                        omap_uart_block_sleep(uart);
-        }
+
+        uart->timeout = value * HZ;
+        if (uart->timeout)
+                mod_timer(&uart->timer, jiffies + uart->timeout);
+        else
+                /* A zero value means disable timeout feature */
+                omap_uart_block_sleep(uart);
+
         return n;
 }
 
-static struct kobj_attribute sleep_timeout_attr =
-        __ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
-
+DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
+#define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
 #else
 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
+#define DEV_CREATE_FILE(dev, attr)
 #endif /* CONFIG_PM */
 
-static struct platform_device serial_device = {
-        .name                   = "serial8250",
-        .id                     = PLAT8250_DEV_PLATFORM,
-        .dev                    = {
-                .platform_data  = serial_platform_data,
+static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS] = {
+        {
+                .pdev = {
+                        .name                   = "serial8250",
+                        .id                     = PLAT8250_DEV_PLATFORM,
+                        .dev                    = {
+                                .platform_data  = serial_platform_data0,
+                        },
+                },
+        }, {
+                .pdev = {
+                        .name                   = "serial8250",
+                        .id                     = PLAT8250_DEV_PLATFORM1,
+                        .dev                    = {
+                                .platform_data  = serial_platform_data1,
+                        },
+                },
+        }, {
+                .pdev = {
+                        .name                   = "serial8250",
+                        .id                     = PLAT8250_DEV_PLATFORM2,
+                        .dev                    = {
+                                .platform_data  = serial_platform_data2,
+                        },
+                },
         },
 };
 
 void __init omap_serial_init(void)
 {
-        int i, err;
+        int i;
         const struct omap_uart_config *info;
         char name[16];
 
@@ -496,14 +568,12 @@ void __init omap_serial_init(void)
 
         if (info == NULL)
                 return;
-        if (cpu_is_omap44xx()) {
-                for (i = 0; i < OMAP_MAX_NR_PORTS; i++)
-                        serial_platform_data[i].irq += 32;
-        }
 
         for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
-                struct plat_serial8250_port *p = serial_platform_data + i;
                 struct omap_uart_state *uart = &omap_uart[i];
+                struct platform_device *pdev = &uart->pdev;
+                struct device *dev = &pdev->dev;
+                struct plat_serial8250_port *p = dev->platform_data;
 
                 if (!(info->enabled_uarts & (1 << i))) {
                         p->membase = NULL;
@@ -531,20 +601,21 @@ void __init omap_serial_init(void)
                 uart->num = i;
                 p->private_data = uart;
                 uart->p = p;
-                list_add(&uart->node, &uart_list);
+                list_add_tail(&uart->node, &uart_list);
+
+                if (cpu_is_omap44xx())
+                        p->irq += 32;
 
                 omap_uart_enable_clocks(uart);
                 omap_uart_reset(uart);
                 omap_uart_idle_init(uart);
-        }
-
-        err = platform_device_register(&serial_device);
-
-#ifdef CONFIG_PM
-        if (!err)
-                err = sysfs_create_file(&serial_device.dev.kobj,
-                                        &sleep_timeout_attr.attr);
-#endif
 
+                if (WARN_ON(platform_device_register(pdev)))
+                        continue;
+                if ((cpu_is_omap34xx() && uart->padconf) ||
+                    (uart->wk_en && uart->wk_mask)) {
+                        device_init_wakeup(dev, true);
+                        DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
+                }
+        }
 }
-
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index f41f8d96ddba..82aa4a3d160c 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -36,7 +36,7 @@
 
         .text
 
-/* r4 parameters */
+/* r1 parameters */
 #define SDRC_NO_UNLOCK_DLL              0x0
 #define SDRC_UNLOCK_DLL                 0x1
 
@@ -58,7 +58,6 @@
 
 /* SDRC_POWER bit settings */
 #define SRFRONIDLEREQ_MASK              0x40
-#define PWDENA_MASK                     0x4
 
 /* CM_IDLEST1_CORE bit settings */
 #define ST_SDRC_MASK                    0x2
@@ -71,41 +70,72 @@
 
 /*
  * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
- * r0 = new SDRC_RFR_CTRL register contents
- * r1 = new SDRC_ACTIM_CTRLA register contents
- * r2 = new SDRC_ACTIM_CTRLB register contents
- * r3 = new M2 divider setting (only 1 and 2 supported right now)
- * r4 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
+ *
+ * Params passed in registers:
+ *  r0 = new M2 divider setting (only 1 and 2 supported right now)
+ *  r1 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
  *      SDRC rates < 83MHz
- * r5 = number of MPU cycles to wait for SDRC to stabilize after
+ *  r2 = number of MPU cycles to wait for SDRC to stabilize after
  *      reprogramming the SDRC when switching to a slower MPU speed
- * r6 = new SDRC_MR_0 register value
- * r7 = increasing SDRC rate? (1 = yes, 0 = no)
+ *  r3 = increasing SDRC rate? (1 = yes, 0 = no)
+ *
+ * Params passed via the stack. The needed params will be copied in SRAM
+ *  before use by the code in SRAM (SDRAM is not accessible during SDRC
+ *  reconfiguration):
+ *  new SDRC_RFR_CTRL_0 register contents
+ *  new SDRC_ACTIM_CTRL_A_0 register contents
+ *  new SDRC_ACTIM_CTRL_B_0 register contents
+ *  new SDRC_MR_0 register value
+ *  new SDRC_RFR_CTRL_1 register contents
+ *  new SDRC_ACTIM_CTRL_A_1 register contents
+ *  new SDRC_ACTIM_CTRL_B_1 register contents
+ *  new SDRC_MR_1 register value
  *
+ * If the param SDRC_RFR_CTRL_1 is 0, the parameters
+ *  are not programmed into the SDRC CS1 registers
  */
 ENTRY(omap3_sram_configure_core_dpll)
         stmfd   sp!, {r1-r12, lr}       @ store regs to stack
-        ldr     r4, [sp, #52]           @ pull extra args off the stack
-        ldr     r5, [sp, #56]           @ load extra args from the stack
-        ldr     r6, [sp, #60]           @ load extra args from the stack
-        ldr     r7, [sp, #64]           @ load extra args from the stack
+
+                                        @ pull the extra args off the stack
+                                        @  and store them in SRAM
+        ldr     r4, [sp, #52]
+        str     r4, omap_sdrc_rfr_ctrl_0_val
+        ldr     r4, [sp, #56]
+        str     r4, omap_sdrc_actim_ctrl_a_0_val
+        ldr     r4, [sp, #60]
+        str     r4, omap_sdrc_actim_ctrl_b_0_val
+        ldr     r4, [sp, #64]
+        str     r4, omap_sdrc_mr_0_val
+        ldr     r4, [sp, #68]
+        str     r4, omap_sdrc_rfr_ctrl_1_val
+        cmp     r4, #0                  @ if SDRC_RFR_CTRL_1 is 0,
+        beq     skip_cs1_params         @  do not use cs1 params
+        ldr     r4, [sp, #72]
+        str     r4, omap_sdrc_actim_ctrl_a_1_val
+        ldr     r4, [sp, #76]
+        str     r4, omap_sdrc_actim_ctrl_b_1_val
+        ldr     r4, [sp, #80]
+        str     r4, omap_sdrc_mr_1_val
+skip_cs1_params:
         dsb                             @ flush buffered writes to interconnect
-        cmp     r7, #1                  @ if increasing SDRC clk rate,
+
+        cmp     r3, #1                  @ if increasing SDRC clk rate,
         bleq    configure_sdrc          @ program the SDRC regs early (for RFR)
-        cmp     r4, #SDRC_UNLOCK_DLL    @ set the intended DLL state
+        cmp     r1, #SDRC_UNLOCK_DLL    @ set the intended DLL state
         bleq    unlock_dll
         blne    lock_dll
         bl      sdram_in_selfrefresh    @ put SDRAM in self refresh, idle SDRC
         bl      configure_core_dpll     @ change the DPLL3 M2 divider
+        mov     r12, r2
+        bl      wait_clk_stable         @ wait for SDRC to stabilize
         bl      enable_sdrc             @ take SDRC out of idle
-        cmp     r4, #SDRC_UNLOCK_DLL    @ wait for DLL status to change
+        cmp     r1, #SDRC_UNLOCK_DLL    @ wait for DLL status to change
         bleq    wait_dll_unlock
         blne    wait_dll_lock
-        cmp     r7, #1                  @ if increasing SDRC clk rate,
+        cmp     r3, #1                  @ if increasing SDRC clk rate,
         beq     return_to_sdram         @ return to SDRAM code, otherwise,
         bl      configure_sdrc          @ reprogram SDRC regs now
-        mov     r12, r5
-        bl      wait_clk_stable         @ wait for SDRC to stabilize
 return_to_sdram:
         isb                             @ prevent speculative exec past here
         mov     r0, #0                  @ return value
@@ -113,7 +143,7 @@ return_to_sdram:
 unlock_dll:
         ldr     r11, omap3_sdrc_dlla_ctrl
         ldr     r12, [r11]
-        and     r12, r12, #FIXEDDELAY_MASK
+        bic     r12, r12, #FIXEDDELAY_MASK
         orr     r12, r12, #FIXEDDELAY_DEFAULT
         orr     r12, r12, #DLLIDLE_MASK
         str     r12, [r11]              @ (no OCP barrier needed)
@@ -129,7 +159,6 @@ sdram_in_selfrefresh:
         ldr     r12, [r11]              @ read the contents of SDRC_POWER
         mov     r9, r12                 @ keep a copy of SDRC_POWER bits
         orr     r12, r12, #SRFRONIDLEREQ_MASK   @ enable self refresh on idle
-        bic     r12, r12, #PWDENA_MASK  @ clear PWDENA
         str     r12, [r11]              @ write back to SDRC_POWER register
         ldr     r12, [r11]              @ posted-write barrier for SDRC
 idle_sdrc:
@@ -149,7 +178,7 @@ configure_core_dpll:
         ldr     r12, [r11]
         ldr     r10, core_m2_mask_val   @ modify m2 for core dpll
         and     r12, r12, r10
-        orr     r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
+        orr     r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
         str     r12, [r11]
         ldr     r12, [r11]              @ posted-write barrier for CM
         bx      lr
@@ -187,15 +216,34 @@ wait_dll_unlock:
         bne     wait_dll_unlock
         bx      lr
 configure_sdrc:
-        ldr     r11, omap3_sdrc_rfr_ctrl
-        str     r0, [r11]
-        ldr     r11, omap3_sdrc_actim_ctrla
-        str     r1, [r11]
-        ldr     r11, omap3_sdrc_actim_ctrlb
-        str     r2, [r11]
+        ldr     r12, omap_sdrc_rfr_ctrl_0_val   @ fetch value from SRAM
+        ldr     r11, omap3_sdrc_rfr_ctrl_0      @ fetch addr from SRAM
+        str     r12, [r11]                      @ store
+        ldr     r12, omap_sdrc_actim_ctrl_a_0_val
+        ldr     r11, omap3_sdrc_actim_ctrl_a_0
+        str     r12, [r11]
+        ldr     r12, omap_sdrc_actim_ctrl_b_0_val
+        ldr     r11, omap3_sdrc_actim_ctrl_b_0
+        str     r12, [r11]
+        ldr     r12, omap_sdrc_mr_0_val
         ldr     r11, omap3_sdrc_mr_0
-        str     r6, [r11]
-        ldr     r6, [r11]               @ posted-write barrier for SDRC
+        str     r12, [r11]
+        ldr     r12, omap_sdrc_rfr_ctrl_1_val
+        cmp     r12, #0                 @ if SDRC_RFR_CTRL_1 is 0,
+        beq     skip_cs1_prog           @  do not program cs1 params
+        ldr     r11, omap3_sdrc_rfr_ctrl_1
+        str     r12, [r11]
+        ldr     r12, omap_sdrc_actim_ctrl_a_1_val
+        ldr     r11, omap3_sdrc_actim_ctrl_a_1
+        str     r12, [r11]
+        ldr     r12, omap_sdrc_actim_ctrl_b_1_val
+        ldr     r11, omap3_sdrc_actim_ctrl_b_1
+        str     r12, [r11]
+        ldr     r12, omap_sdrc_mr_1_val
+        ldr     r11, omap3_sdrc_mr_1
+        str     r12, [r11]
+skip_cs1_prog:
+        ldr     r12, [r11]              @ posted-write barrier for SDRC
         bx      lr
 
 omap3_sdrc_power:
@@ -206,14 +254,40 @@ omap3_cm_idlest1_core:
         .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
 omap3_cm_iclken1_core:
         .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
-omap3_sdrc_rfr_ctrl:
+
+omap3_sdrc_rfr_ctrl_0:
         .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
-omap3_sdrc_actim_ctrla:
+omap3_sdrc_rfr_ctrl_1:
+        .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
+omap3_sdrc_actim_ctrl_a_0:
         .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
-omap3_sdrc_actim_ctrlb:
+omap3_sdrc_actim_ctrl_a_1:
+        .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
+omap3_sdrc_actim_ctrl_b_0:
         .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
+omap3_sdrc_actim_ctrl_b_1:
+        .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
 omap3_sdrc_mr_0:
         .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
+omap3_sdrc_mr_1:
+        .word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
+omap_sdrc_rfr_ctrl_0_val:
+        .word 0xDEADBEEF
+omap_sdrc_rfr_ctrl_1_val:
+        .word 0xDEADBEEF
+omap_sdrc_actim_ctrl_a_0_val:
+        .word 0xDEADBEEF
+omap_sdrc_actim_ctrl_a_1_val:
+        .word 0xDEADBEEF
+omap_sdrc_actim_ctrl_b_0_val:
+        .word 0xDEADBEEF
+omap_sdrc_actim_ctrl_b_1_val:
+        .word 0xDEADBEEF
+omap_sdrc_mr_0_val:
+        .word 0xDEADBEEF
+omap_sdrc_mr_1_val:
+        .word 0xDEADBEEF
+
 omap3_sdrc_dlla_status:
         .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
 omap3_sdrc_dlla_ctrl:
@@ -223,3 +297,4 @@ core_m2_mask_val:
 
 ENTRY(omap3_sram_configure_core_dpll_sz)
         .word   . - omap3_sram_configure_core_dpll
+
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 7936085dd758..2e9b8ccd8ec2 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -510,7 +510,7 @@ static struct db_chip db_chips[] __initdata = {
         }
 };
 
-static void u300_init_check_chip(void)
+static void __init u300_init_check_chip(void)
 {
 
         u16 val;
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 8277802ec859..3a7279c1ce5e 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -120,6 +120,32 @@ void show_mem(void)
         printk("%d pages swap cached\n", cached);
 }
 
+static void __init find_node_limits(int node, struct meminfo *mi,
+        unsigned long *min, unsigned long *max_low, unsigned long *max_high)
+{
+        int i;
+
+        *min = -1UL;
+        *max_low = *max_high = 0;
+
+        for_each_nodebank(i, mi, node) {
+                struct membank *bank = &mi->bank[i];
+                unsigned long start, end;
+
+                start = bank_pfn_start(bank);
+                end = bank_pfn_end(bank);
+
+                if (*min > start)
+                        *min = start;
+                if (*max_high < end)
+                        *max_high = end;
+                if (bank->highmem)
+                        continue;
+                if (*max_low < end)
+                        *max_low = end;
+        }
+}
+
 /*
  * FIXME: We really want to avoid allocating the bootmap bitmap
  * over the top of the initrd.  Hopefully, this is located towards
@@ -210,41 +236,25 @@ static inline void map_memory_bank(struct membank *bank)
 #endif
 }
 
-static unsigned long __init bootmem_init_node(int node, struct meminfo *mi)
+static void __init bootmem_init_node(int node, struct meminfo *mi,
+        unsigned long start_pfn, unsigned long end_pfn)
 {
-        unsigned long start_pfn, end_pfn, boot_pfn;
+        unsigned long boot_pfn;
         unsigned int boot_pages;
         pg_data_t *pgdat;
         int i;
 
-        start_pfn = -1UL;
-        end_pfn = 0;
-
         /*
-         * Calculate the pfn range, and map the memory banks for this node.
+         * Map the memory banks for this node.
          */
         for_each_nodebank(i, mi, node) {
                 struct membank *bank = &mi->bank[i];
-                unsigned long start, end;
 
-                start = bank_pfn_start(bank);
-                end = bank_pfn_end(bank);
-
-                if (start_pfn > start)
-                        start_pfn = start;
-                if (end_pfn < end)
-                        end_pfn = end;
-
-                map_memory_bank(bank);
+                if (!bank->highmem)
+                        map_memory_bank(bank);
         }
 
         /*
-         * If there is no memory in this node, ignore it.
-         */
-        if (end_pfn == 0)
-                return end_pfn;
-
-        /*
          * Allocate the bootmem bitmap page.
          */
         boot_pages = bootmem_bootmap_pages(end_pfn - start_pfn);
@@ -260,7 +270,8 @@ static unsigned long __init bootmem_init_node(int node, struct meminfo *mi)
 
         for_each_nodebank(i, mi, node) {
                 struct membank *bank = &mi->bank[i];
-                free_bootmem_node(pgdat, bank_phys_start(bank), bank_phys_size(bank));
+                if (!bank->highmem)
+                        free_bootmem_node(pgdat, bank_phys_start(bank), bank_phys_size(bank));
                 memory_present(node, bank_pfn_start(bank), bank_pfn_end(bank));
         }
 
@@ -269,8 +280,6 @@ static unsigned long __init bootmem_init_node(int node, struct meminfo *mi)
          */
         reserve_bootmem_node(pgdat, boot_pfn << PAGE_SHIFT,
                              boot_pages << PAGE_SHIFT, BOOTMEM_DEFAULT);
-
-        return end_pfn;
 }
 
 static void __init bootmem_reserve_initrd(int node)
@@ -297,33 +306,39 @@ static void __init bootmem_reserve_initrd(int node)
 static void __init bootmem_free_node(int node, struct meminfo *mi)
 {
         unsigned long zone_size[MAX_NR_ZONES], zhole_size[MAX_NR_ZONES];
-        unsigned long start_pfn, end_pfn;
-        pg_data_t *pgdat = NODE_DATA(node);
+        unsigned long min, max_low, max_high;
         int i;
 
-        start_pfn = pgdat->bdata->node_min_pfn;
-        end_pfn = pgdat->bdata->node_low_pfn;
+        find_node_limits(node, mi, &min, &max_low, &max_high);
 
         /*
          * initialise the zones within this node.
          */
         memset(zone_size, 0, sizeof(zone_size));
-        memset(zhole_size, 0, sizeof(zhole_size));
 
         /*
          * The size of this node has already been determined.  If we need
          * to do anything fancy with the allocation of this memory to the
          * zones, now is the time to do it.
          */
-        zone_size[0] = end_pfn - start_pfn;
+        zone_size[0] = max_low - min;
+#ifdef CONFIG_HIGHMEM
+        zone_size[ZONE_HIGHMEM] = max_high - max_low;
+#endif
 
         /*
          * For each bank in this node, calculate the size of the holes.
          *  holes = node_size - sum(bank_sizes_in_node)
          */
-        zhole_size[0] = zone_size[0];
-        for_each_nodebank(i, mi, node)
-                zhole_size[0] -= bank_pfn_size(&mi->bank[i]);
+        memcpy(zhole_size, zone_size, sizeof(zhole_size));
+        for_each_nodebank(i, mi, node) {
+                int idx = 0;
+#ifdef CONFIG_HIGHMEM
+                if (mi->bank[i].highmem)
+                        idx = ZONE_HIGHMEM;
+#endif
+                zhole_size[idx] -= bank_pfn_size(&mi->bank[i]);
+        }
 
         /*
          * Adjust the sizes according to any special requirements for
@@ -331,13 +346,13 @@ static void __init bootmem_free_node(int node, struct meminfo *mi)
          */
         arch_adjust_zones(node, zone_size, zhole_size);
 
-        free_area_init_node(node, zone_size, start_pfn, zhole_size);
+        free_area_init_node(node, zone_size, min, zhole_size);
 }
 
 void __init bootmem_init(void)
 {
         struct meminfo *mi = &meminfo;
-        unsigned long memend_pfn = 0;
+        unsigned long min, max_low, max_high;
         int node, initrd_node;
 
         /*
@@ -345,11 +360,29 @@ void __init bootmem_init(void)
          */
         initrd_node = check_initrd(mi);
 
+        max_low = max_high = 0;
+
         /*
          * Run through each node initialising the bootmem allocator.
          */
         for_each_node(node) {
-                unsigned long end_pfn = bootmem_init_node(node, mi);
+                unsigned long node_low, node_high;
+
+                find_node_limits(node, mi, &min, &node_low, &node_high);
+
+                if (node_low > max_low)
+                        max_low = node_low;
+                if (node_high > max_high)
+                        max_high = node_high;
+
+                /*
+                 * If there is no memory in this node, ignore it.
+                 * (We can't have nodes which have no lowmem)
+                 */
+                if (node_low == 0)
+                        continue;
+
+                bootmem_init_node(node, mi, min, node_low);
 
                 /*
                  * Reserve any special node zero regions.
@@ -362,12 +395,6 @@ void __init bootmem_init(void)
                  */
                 if (node == initrd_node)
                         bootmem_reserve_initrd(node);
-
-                /*
-                 * Remember the highest memory PFN.
-                 */
-                if (end_pfn > memend_pfn)
-                        memend_pfn = end_pfn;
         }
 
         /*
@@ -383,7 +410,7 @@ void __init bootmem_init(void)
         for_each_node(node)
                 bootmem_free_node(node, mi);
 
-        high_memory = __va((memend_pfn << PAGE_SHIFT) - 1) + 1;
+        high_memory = __va((max_low << PAGE_SHIFT) - 1) + 1;
 
         /*
          * This doesn't seem to be used by the Linux memory manager any
@@ -393,7 +420,8 @@ void __init bootmem_init(void)
          * Note: max_low_pfn and max_pfn reflect the number of _pages_ in
          * the system, not the maximum PFN.
          */
-        max_pfn = max_low_pfn = memend_pfn - PHYS_PFN_OFFSET;
+        max_low_pfn = max_low - PHYS_PFN_OFFSET;
+        max_pfn = max_high - PHYS_PFN_OFFSET;
 }
 
 static inline int free_area(unsigned long pfn, unsigned long end, char *s)
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 4722582b17b8..4426ee67ceca 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -687,13 +687,19 @@ __early_param("vmalloc=", early_vmalloc);
 
 static void __init sanity_check_meminfo(void)
 {
-        int i, j;
+        int i, j, highmem = 0;
 
         for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
                 struct membank *bank = &meminfo.bank[j];
                 *bank = meminfo.bank[i];
 
 #ifdef CONFIG_HIGHMEM
+                if (__va(bank->start) > VMALLOC_MIN ||
+                    __va(bank->start) < (void *)PAGE_OFFSET)
+                        highmem = 1;
+
+                bank->highmem = highmem;
+
                 /*
                  * Split those memory banks which are partially overlapping
                  * the vmalloc area greatly simplifying things later.
@@ -714,6 +720,7 @@ static void __init sanity_check_meminfo(void)
                                 i++;
                                 bank[1].size -= VMALLOC_MIN - __va(bank->start);
                                 bank[1].start = __pa(VMALLOC_MIN - 1) + 1;
+                                bank[1].highmem = highmem = 1;
                                 j++;
                         }
                         bank->size = VMALLOC_MIN - __va(bank->start);
diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c
index 843e8af64066..1868c0d8f9b5 100644
--- a/arch/arm/plat-omap/cpu-omap.c
+++ b/arch/arm/plat-omap/cpu-omap.c
@@ -78,10 +78,10 @@ static int omap_target(struct cpufreq_policy *policy,
 
         /* Ensure desired rate is within allowed range.  Some govenors
          * (ondemand) will just pass target_freq=0 to get the minimum. */
-        if (target_freq < policy->cpuinfo.min_freq)
-                target_freq = policy->cpuinfo.min_freq;
-        if (target_freq > policy->cpuinfo.max_freq)
-                target_freq = policy->cpuinfo.max_freq;
+        if (target_freq < policy->min)
+                target_freq = policy->min;
+        if (target_freq > policy->max)
+                target_freq = policy->max;
 
         freqs.old = omap_getspeed(0);
         freqs.new = clk_round_rate(mpu_clk, target_freq * 1000) / 1000;
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index be4eefda4767..9395898dd49a 100644
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -281,24 +281,27 @@ static int /* __init */ fpga_probe(struct platform_device *pdev)
         return 0;
 }
 
-static int fpga_suspend_late(struct platform_device *pdev, pm_message_t mesg)
+static int fpga_suspend_noirq(struct device *dev)
 {
         __raw_writew(~0, &fpga->leds);
         return 0;
 }
 
-static int fpga_resume_early(struct platform_device *pdev)
+static int fpga_resume_noirq(struct device *dev)
 {
         __raw_writew(~hw_led_state, &fpga->leds);
         return 0;
 }
 
+static struct dev_pm_ops fpga_dev_pm_ops = {
+        .suspend_noirq = fpga_suspend_noirq,
+        .resume_noirq = fpga_resume_noirq,
+};
 
 static struct platform_driver led_driver = {
         .driver.name    = "omap_dbg_led",
+        .driver.pm      = &fpga_dev_pm_ops,
         .probe          = fpga_probe,
-        .suspend_late   = fpga_suspend_late,
-        .resume_early   = fpga_resume_early,
 };
 
 static int __init fpga_init(void)
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 7677a4a1cef2..e3ac94f09006 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -946,7 +946,9 @@ void omap_start_dma(int lch)
 
                         cur_lch = next_lch;
                 } while (next_lch != -1);
-        } else if (cpu_class_is_omap2()) {
+        } else if (cpu_is_omap242x() ||
+                (cpu_is_omap243x() &&  omap_type() <= OMAP2430_REV_ES1_0)) {
+
                 /* Errata: Need to write lch even if not using chaining */
                 dma_write(lch, CLNK_CTRL(lch));
         }
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 26b387c12423..50b19a3027bc 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -476,14 +476,12 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
         __raw_writel(l, reg);
 }
 
-static int __omap_get_gpio_datain(int gpio)
+static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
 {
-        struct gpio_bank *bank;
         void __iomem *reg;
 
         if (check_gpio(gpio) < 0)
                 return -EINVAL;
-        bank = get_gpio_bank(gpio);
         reg = bank->base;
         switch (bank->method) {
 #ifdef CONFIG_ARCH_OMAP1
@@ -524,6 +522,53 @@ static int __omap_get_gpio_datain(int gpio)
                         & (1 << get_gpio_index(gpio))) != 0;
 }
 
+static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
+{
+        void __iomem *reg;
+
+        if (check_gpio(gpio) < 0)
+                return -EINVAL;
+        reg = bank->base;
+
+        switch (bank->method) {
+#ifdef CONFIG_ARCH_OMAP1
+        case METHOD_MPUIO:
+                reg += OMAP_MPUIO_OUTPUT;
+                break;
+#endif
+#ifdef CONFIG_ARCH_OMAP15XX
+        case METHOD_GPIO_1510:
+                reg += OMAP1510_GPIO_DATA_OUTPUT;
+                break;
+#endif
+#ifdef CONFIG_ARCH_OMAP16XX
+        case METHOD_GPIO_1610:
+                reg += OMAP1610_GPIO_DATAOUT;
+                break;
+#endif
+#ifdef CONFIG_ARCH_OMAP730
+        case METHOD_GPIO_730:
+                reg += OMAP730_GPIO_DATA_OUTPUT;
+                break;
+#endif
+#ifdef CONFIG_ARCH_OMAP850
+        case METHOD_GPIO_850:
+                reg += OMAP850_GPIO_DATA_OUTPUT;
+                break;
+#endif
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+                defined(CONFIG_ARCH_OMAP4)
+        case METHOD_GPIO_24XX:
+                reg += OMAP24XX_GPIO_DATAOUT;
+                break;
+#endif
+        default:
+                return -EINVAL;
+        }
+
+        return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
+}
+
 #define MOD_REG_BIT(reg, bit_mask, set) \
 do {    \
         int l = __raw_readl(base + reg); \
@@ -1189,6 +1234,7 @@ static void gpio_mask_irq(unsigned int irq)
         struct gpio_bank *bank = get_irq_chip_data(irq);
 
         _set_gpio_irqenable(bank, gpio, 0);
+        _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
 }
 
 static void gpio_unmask_irq(unsigned int irq)
@@ -1196,6 +1242,11 @@ static void gpio_unmask_irq(unsigned int irq)
         unsigned int gpio = irq - IH_GPIO_BASE;
         struct gpio_bank *bank = get_irq_chip_data(irq);
         unsigned int irq_mask = 1 << get_gpio_index(gpio);
+        struct irq_desc *desc = irq_to_desc(irq);
+        u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
+
+        if (trigger)
+                _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
 
         /* For level-triggered GPIOs, the clearing must be done after
          * the HW source is cleared, thus after the handler has run */
@@ -1264,8 +1315,9 @@ static struct irq_chip mpuio_irq_chip = {
 
 #include <linux/platform_device.h>
 
-static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
+static int omap_mpuio_suspend_noirq(struct device *dev)
 {
+        struct platform_device *pdev = to_platform_device(dev);
         struct gpio_bank        *bank = platform_get_drvdata(pdev);
         void __iomem            *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
         unsigned long           flags;
@@ -1278,8 +1330,9 @@ static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t me
         return 0;
 }
 
-static int omap_mpuio_resume_early(struct platform_device *pdev)
+static int omap_mpuio_resume_noirq(struct device *dev)
 {
+        struct platform_device *pdev = to_platform_device(dev);
         struct gpio_bank        *bank = platform_get_drvdata(pdev);
         void __iomem            *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
         unsigned long           flags;
@@ -1291,14 +1344,18 @@ static int omap_mpuio_resume_early(struct platform_device *pdev)
         return 0;
 }
 
+static struct dev_pm_ops omap_mpuio_dev_pm_ops = {
+        .suspend_noirq = omap_mpuio_suspend_noirq,
+        .resume_noirq = omap_mpuio_resume_noirq,
+};
+
 /* use platform_driver for this, now that there's no longer any
  * point to sys_device (other than not disturbing old code).
  */
 static struct platform_driver omap_mpuio_driver = {
-        .suspend_late   = omap_mpuio_suspend_late,
-        .resume_early   = omap_mpuio_resume_early,
         .driver         = {
                 .name   = "mpuio",
+                .pm     = &omap_mpuio_dev_pm_ops,
         },
 };
 
@@ -1350,9 +1407,49 @@ static int gpio_input(struct gpio_chip *chip, unsigned offset)
         return 0;
 }
 
+static int gpio_is_input(struct gpio_bank *bank, int mask)
+{
+        void __iomem *reg = bank->base;
+
+        switch (bank->method) {
+        case METHOD_MPUIO:
+                reg += OMAP_MPUIO_IO_CNTL;
+                break;
+        case METHOD_GPIO_1510:
+                reg += OMAP1510_GPIO_DIR_CONTROL;
+                break;
+        case METHOD_GPIO_1610:
+                reg += OMAP1610_GPIO_DIRECTION;
+                break;
+        case METHOD_GPIO_730:
+                reg += OMAP730_GPIO_DIR_CONTROL;
+                break;
+        case METHOD_GPIO_850:
+                reg += OMAP850_GPIO_DIR_CONTROL;
+                break;
+        case METHOD_GPIO_24XX:
+                reg += OMAP24XX_GPIO_OE;
+                break;
+        }
+        return __raw_readl(reg) & mask;
+}
+
 static int gpio_get(struct gpio_chip *chip, unsigned offset)
 {
-        return __omap_get_gpio_datain(chip->base + offset);
+        struct gpio_bank *bank;
+        void __iomem *reg;
+        int gpio;
+        u32 mask;
+
+        gpio = chip->base + offset;
+        bank = get_gpio_bank(gpio);
+        reg = bank->base;
+        mask = 1 << get_gpio_index(gpio);
+
+        if (gpio_is_input(bank, mask))
+                return _get_gpio_datain(bank, gpio);
+        else
+                return _get_gpio_dataout(bank, gpio);
 }
 
 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
@@ -1886,34 +1983,6 @@ arch_initcall(omap_gpio_sysinit);
 #include <linux/debugfs.h>
 #include <linux/seq_file.h>
 
-static int gpio_is_input(struct gpio_bank *bank, int mask)
-{
-        void __iomem *reg = bank->base;
-
-        switch (bank->method) {
-        case METHOD_MPUIO:
-                reg += OMAP_MPUIO_IO_CNTL;
-                break;
-        case METHOD_GPIO_1510:
-                reg += OMAP1510_GPIO_DIR_CONTROL;
-                break;
-        case METHOD_GPIO_1610:
-                reg += OMAP1610_GPIO_DIRECTION;
-                break;
-        case METHOD_GPIO_730:
-                reg += OMAP730_GPIO_DIR_CONTROL;
-                break;
-        case METHOD_GPIO_850:
-                reg += OMAP850_GPIO_DIR_CONTROL;
-                break;
-        case METHOD_GPIO_24XX:
-                reg += OMAP24XX_GPIO_OE;
-                break;
-        }
-        return __raw_readl(reg) & mask;
-}
-
-
 static int dbg_gpio_show(struct seq_file *s, void *unused)
 {
         unsigned        i, j, gpio;
diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h
index f9f65e1ba3f1..4b8b0d65cbf2 100644
--- a/arch/arm/plat-omap/include/mach/clock.h
+++ b/arch/arm/plat-omap/include/mach/clock.h
@@ -20,6 +20,8 @@ struct clockdomain;
 struct clkops {
         int                     (*enable)(struct clk *);
         void                    (*disable)(struct clk *);
+        void                    (*find_idlest)(struct clk *, void __iomem **, u8 *);
+        void                    (*find_companion)(struct clk *, void __iomem **, u8 *);
 };
 
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
diff --git a/arch/arm/plat-omap/include/mach/cpu.h b/arch/arm/plat-omap/include/mach/cpu.h
index 285eaa3a8275..11e73d9e8928 100644
--- a/arch/arm/plat-omap/include/mach/cpu.h
+++ b/arch/arm/plat-omap/include/mach/cpu.h
@@ -378,9 +378,6 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define cpu_class_is_omap2()    (cpu_is_omap24xx() || cpu_is_omap34xx() || \
                                 cpu_is_omap44xx())
 
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
-                        defined(CONFIG_ARCH_OMAP4)
-
 /* Various silicon revisions for omap2 */
 #define OMAP242X_CLASS          0x24200024
 #define OMAP2420_REV_ES1_0      0x24200024
@@ -436,5 +433,3 @@ IS_OMAP_TYPE(3430, 0x3430)
 
 int omap_chip_is(struct omap_chip_id oci);
 void omap2_check_revision(void);
-
-#endif    /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */
diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/mach/io.h
index 73f483d56ca6..21fb0efdda86 100644
--- a/arch/arm/plat-omap/include/mach/io.h
+++ b/arch/arm/plat-omap/include/mach/io.h
@@ -228,7 +228,8 @@ extern void omap1_map_common_io(void);
 extern void omap1_init_common_hw(void);
 
 extern void omap2_map_common_io(void);
-extern void omap2_init_common_hw(struct omap_sdrc_params *sp);
+extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
+                                 struct omap_sdrc_params *sdrc_cs1);
 
 #define __arch_ioremap(p,s,t)   omap_ioremap(p,s,t)
 #define __arch_iounmap(v)       omap_iounmap(v)
diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/mach/mux.h
index 85a621705766..80281c458baf 100644
--- a/arch/arm/plat-omap/include/mach/mux.h
+++ b/arch/arm/plat-omap/include/mach/mux.h
@@ -853,6 +853,10 @@ enum omap34xx_index {
         AE5_34XX_GPIO143,
         H19_34XX_GPIO164_OUT,
         J25_34XX_GPIO170,
+
+        /* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
+        H16_34XX_SDRC_CKE0,
+        H17_34XX_SDRC_CKE1,
 };
 
 struct omap_mux_cfg {
diff --git a/arch/arm/plat-omap/include/mach/prcm.h b/arch/arm/plat-omap/include/mach/prcm.h
index 24ac3c715912..cda2a70397b4 100644
--- a/arch/arm/plat-omap/include/mach/prcm.h
+++ b/arch/arm/plat-omap/include/mach/prcm.h
@@ -25,6 +25,7 @@
 
 u32 omap_prcm_get_reset_sources(void);
 void omap_prcm_arch_reset(char mode);
+int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name);
 
 #endif
 
diff --git a/arch/arm/plat-omap/include/mach/sdrc.h b/arch/arm/plat-omap/include/mach/sdrc.h
index adc73522491f..0be18e4ff182 100644
--- a/arch/arm/plat-omap/include/mach/sdrc.h
+++ b/arch/arm/plat-omap/include/mach/sdrc.h
@@ -30,6 +30,10 @@
 #define SDRC_ACTIM_CTRL_A_0     0x09c
 #define SDRC_ACTIM_CTRL_B_0     0x0a0
 #define SDRC_RFR_CTRL_0         0x0a4
+#define SDRC_MR_1               0x0B4
+#define SDRC_ACTIM_CTRL_A_1     0x0C4
+#define SDRC_ACTIM_CTRL_B_1     0x0C8
+#define SDRC_RFR_CTRL_1         0x0D4
 
 /*
  * These values represent the number of memory clock cycles between
@@ -102,8 +106,11 @@ struct omap_sdrc_params {
         u32 mr;
 };
 
-void __init omap2_sdrc_init(struct omap_sdrc_params *sp);
-struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r);
+void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
+                            struct omap_sdrc_params *sdrc_cs1);
+int omap2_sdrc_get_params(unsigned long r,
+                          struct omap_sdrc_params **sdrc_cs0,
+                          struct omap_sdrc_params **sdrc_cs1);
 
 #ifdef CONFIG_ARCH_OMAP2
 
diff --git a/arch/arm/plat-omap/include/mach/serial.h b/arch/arm/plat-omap/include/mach/serial.h
index 13abd02d1527..def0529c75eb 100644
--- a/arch/arm/plat-omap/include/mach/serial.h
+++ b/arch/arm/plat-omap/include/mach/serial.h
@@ -59,6 +59,7 @@ extern void omap_uart_check_wakeup(void);
 extern void omap_uart_prepare_suspend(void);
 extern void omap_uart_prepare_idle(int num);
 extern void omap_uart_resume_idle(int num);
+extern void omap_uart_enable_irqs(int enable);
 #endif
 
 #endif
diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h
index 4d53cc59d7a3..8974e3fc2691 100644
--- a/arch/arm/plat-omap/include/mach/sram.h
+++ b/arch/arm/plat-omap/include/mach/sram.h
@@ -21,11 +21,12 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
                                       u32 mem_type);
 extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 
-extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
-                                     u32 sdrc_actim_ctrla,
-                                     u32 sdrc_actim_ctrlb, u32 m2,
-                                     u32 unlock_dll, u32 f, u32 sdrc_mr,
-                                     u32 inc);
+extern u32 omap3_configure_core_dpll(
+                        u32 m2, u32 unlock_dll, u32 f, u32 inc,
+                        u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+                        u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+                        u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+                        u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
 
 /* Do not use these */
 extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
@@ -59,12 +60,12 @@ extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
                                                 u32 mem_type);
 extern unsigned long omap243x_sram_reprogram_sdrc_sz;
 
-
-extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
-                                          u32 sdrc_actim_ctrla,
-                                          u32 sdrc_actim_ctrlb, u32 m2,
-                                          u32 unlock_dll, u32 f, u32 sdrc_mr,
-                                          u32 inc);
+extern u32 omap3_sram_configure_core_dpll(
+                        u32 m2, u32 unlock_dll, u32 f, u32 inc,
+                        u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+                        u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+                        u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+                        u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
 extern unsigned long omap3_sram_configure_core_dpll_sz;
 
 #endif
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 4ea73804d21e..5eae7876979c 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -44,9 +44,9 @@
 #define OMAP2_SRAM_VA           0xe3000000
 #define OMAP2_SRAM_PUB_VA       (OMAP2_SRAM_VA + 0x800)
 #define OMAP3_SRAM_PA           0x40200000
-#define OMAP3_SRAM_VA           0xd7000000
+#define OMAP3_SRAM_VA           0xe3000000
 #define OMAP3_SRAM_PUB_PA       0x40208000
-#define OMAP3_SRAM_PUB_VA       0xd7008000
+#define OMAP3_SRAM_PUB_VA       (OMAP3_SRAM_VA + 0x8000)
 #define OMAP4_SRAM_PA           0x40200000              /*0x402f0000*/
 #define OMAP4_SRAM_VA           0xd7000000              /*0xd70f0000*/
 
@@ -373,20 +373,26 @@ static inline int omap243x_sram_init(void)
 
 #ifdef CONFIG_ARCH_OMAP3
 
-static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
-                                              u32 sdrc_actim_ctrla,
-                                              u32 sdrc_actim_ctrlb,
-                                              u32 m2, u32 unlock_dll,
-                                              u32 f, u32 sdrc_mr, u32 inc);
-u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
-                              u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
-                              u32 f, u32 sdrc_mr, u32 inc)
+static u32 (*_omap3_sram_configure_core_dpll)(
+                        u32 m2, u32 unlock_dll, u32 f, u32 inc,
+                        u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+                        u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+                        u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+                        u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
+
+u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
+                        u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+                        u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+                        u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+                        u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
 {
         BUG_ON(!_omap3_sram_configure_core_dpll);
-        return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
-                                               sdrc_actim_ctrla,
-                                               sdrc_actim_ctrlb, m2,
-                                               unlock_dll, f, sdrc_mr, inc);
+        return _omap3_sram_configure_core_dpll(
+                        m2, unlock_dll, f, inc,
+                        sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
+                        sdrc_actim_ctrl_b_0, sdrc_mr_0,
+                        sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
+                        sdrc_actim_ctrl_b_1, sdrc_mr_1);
 }
 
 /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
diff --git a/arch/arm/plat-s3c24xx/clock-dclk.c b/arch/arm/plat-s3c24xx/clock-dclk.c
index 5b75a797b5ab..0afb217a775e 100644
--- a/arch/arm/plat-s3c24xx/clock-dclk.c
+++ b/arch/arm/plat-s3c24xx/clock-dclk.c
@@ -129,7 +129,7 @@ static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
 
         /* calculate the MISCCR setting for the clock */
 
-        if (parent == &clk_xtal)
+        if (parent == &clk_mpll)
                 source = S3C2410_MISCCR_CLK0_MPLL;
         else if (parent == &clk_upll)
                 source = S3C2410_MISCCR_CLK0_UPLL;
diff --git a/arch/ia64/include/asm/device.h b/arch/ia64/include/asm/device.h
index 41ab85d66f33..d66d446b127c 100644
--- a/arch/ia64/include/asm/device.h
+++ b/arch/ia64/include/asm/device.h
@@ -15,4 +15,7 @@ struct dev_archdata {
 #endif
 };
 
+struct pdev_archdata {
+};
+
 #endif /* _ASM_IA64_DEVICE_H */
diff --git a/arch/microblaze/configs/mmu_defconfig b/arch/microblaze/configs/mmu_defconfig
index bd0b85ec38f5..09c32962b66f 100644
--- a/arch/microblaze/configs/mmu_defconfig
+++ b/arch/microblaze/configs/mmu_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.30-rc6
-# Fri May 22 10:02:33 2009
+# Linux kernel version: 2.6.31-rc6
+# Tue Aug 18 11:00:02 2009
 #
 CONFIG_MICROBLAZE=y
 # CONFIG_SWAP is not set
@@ -18,7 +18,11 @@ CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_CSUM=y
+# CONFIG_PCI is not set
+CONFIG_NO_DMA=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
 # General setup
@@ -59,8 +63,8 @@ CONFIG_INITRAMFS_ROOT_GID=0
 CONFIG_RD_GZIP=y
 # CONFIG_RD_BZIP2 is not set
 # CONFIG_RD_LZMA is not set
-CONFIG_INITRAMFS_COMPRESSION_NONE=y
-# CONFIG_INITRAMFS_COMPRESSION_GZIP is not set
+# CONFIG_INITRAMFS_COMPRESSION_NONE is not set
+CONFIG_INITRAMFS_COMPRESSION_GZIP=y
 # CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set
 # CONFIG_INITRAMFS_COMPRESSION_LZMA is not set
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -71,7 +75,6 @@ CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
 CONFIG_KALLSYMS_ALL=y
 CONFIG_KALLSYMS_EXTRA_PASS=y
-# CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_HOTPLUG is not set
 CONFIG_PRINTK=y
 CONFIG_BUG=y
@@ -84,13 +87,22 @@ CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 # CONFIG_SHMEM is not set
 CONFIG_AIO=y
+
+#
+# Performance Counters
+#
 CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
+
+#
+# GCOV-based kernel profiling
+#
 # CONFIG_SLOW_WORK is not set
 # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
@@ -102,7 +114,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
+CONFIG_LBDAF=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
 
@@ -194,9 +206,9 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
 CONFIG_VIRT_TO_BUS=y
-CONFIG_UNEVICTABLE_LRU=y
 CONFIG_HAVE_MLOCK=y
 CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 
 #
 # Exectuable file formats
@@ -262,6 +274,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
 # CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
 # CONFIG_DCB is not set
 
@@ -325,7 +338,6 @@ CONFIG_MISC_DEVICES=y
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
-CONFIG_COMPAT_NET_DEV_OPS=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -344,7 +356,7 @@ CONFIG_NET_ETHERNET=y
 # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
 # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
 # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
-# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
 CONFIG_NETDEV_1000=y
 CONFIG_NETDEV_10000=y
 
@@ -410,6 +422,11 @@ CONFIG_LEGACY_PTY_COUNT=256
 # CONFIG_TCG_TPM is not set
 # CONFIG_I2C is not set
 # CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
 CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
 # CONFIG_GPIOLIB is not set
 # CONFIG_W1 is not set
@@ -418,12 +435,6 @@ CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
 # CONFIG_THERMAL is not set
 # CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
-CONFIG_SSB_POSSIBLE=y
-
-#
-# Sonics Silicon Backplane
-#
-# CONFIG_SSB is not set
 
 #
 # Multifunction device drivers
@@ -433,22 +444,7 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_HTC_PASIC3 is not set
 # CONFIG_MFD_TMIO is not set
 # CONFIG_REGULATOR is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-# CONFIG_VIDEO_MEDIA is not set
-
-#
-# Multimedia drivers
-#
-# CONFIG_DAB is not set
+# CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
@@ -469,9 +465,12 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_NEW_LEDS is not set
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_RTC_CLASS is not set
-# CONFIG_DMADEVICES is not set
 # CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
 # CONFIG_STAGING is not set
 
 #
@@ -485,12 +484,15 @@ CONFIG_EXT2_FS=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
-CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
 # CONFIG_DNOTIFY is not set
 # CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
@@ -678,6 +680,7 @@ CONFIG_DEBUG_INFO=y
 # CONFIG_SYSCTL_SYSCALL_CHECK is not set
 # CONFIG_PAGE_POISONING is not set
 # CONFIG_SAMPLES is not set
+# CONFIG_KMEMCHECK is not set
 CONFIG_EARLY_PRINTK=y
 CONFIG_HEART_BEAT=y
 CONFIG_DEBUG_BOOTMEM=y
@@ -793,6 +796,5 @@ CONFIG_ZLIB_INFLATE=y
 CONFIG_DECOMPRESS_GZIP=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
 CONFIG_HAVE_LMB=y
 CONFIG_NLATTR=y
diff --git a/arch/microblaze/configs/nommu_defconfig b/arch/microblaze/configs/nommu_defconfig
index 4ef6af0a8f31..8b638615a972 100644
--- a/arch/microblaze/configs/nommu_defconfig
+++ b/arch/microblaze/configs/nommu_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.30-rc5
-# Mon May 11 09:01:02 2009
+# Linux kernel version: 2.6.31-rc6
+# Tue Aug 18 10:35:30 2009
 #
 CONFIG_MICROBLAZE=y
 # CONFIG_SWAP is not set
@@ -17,9 +17,12 @@ CONFIG_GENERIC_TIME=y
 # CONFIG_GENERIC_TIME_VSYSCALL is not set
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_CSUM=y
 # CONFIG_PCI is not set
-# CONFIG_NO_DMA is not set
+CONFIG_NO_DMA=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
 # General setup
@@ -64,7 +67,6 @@ CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
 CONFIG_KALLSYMS_ALL=y
 CONFIG_KALLSYMS_EXTRA_PASS=y
-# CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_HOTPLUG is not set
 CONFIG_PRINTK=y
 CONFIG_BUG=y
@@ -76,13 +78,23 @@ CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_AIO=y
+
+#
+# Performance Counters
+#
 CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
 # CONFIG_SLOW_WORK is not set
 # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
@@ -95,7 +107,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
+CONFIG_LBDAF=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
 
@@ -156,8 +168,16 @@ CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="console=ttyUL0,115200"
 # CONFIG_CMDLINE_FORCE is not set
 CONFIG_OF=y
-CONFIG_OF_DEVICE=y
 CONFIG_PROC_DEVICETREE=y
+
+#
+# Advanced setup
+#
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_KERNEL_START=0x90000000
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
@@ -169,7 +189,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
 CONFIG_VIRT_TO_BUS=y
-CONFIG_UNEVICTABLE_LRU=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 CONFIG_NOMMU_INITIAL_TRIM_EXCESS=1
 
 #
@@ -237,6 +257,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
 # CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
 # CONFIG_DCB is not set
 
@@ -254,7 +275,11 @@ CONFIG_WIRELESS=y
 CONFIG_WIRELESS_OLD_REGULATORY=y
 # CONFIG_WIRELESS_EXT is not set
 # CONFIG_LIB80211 is not set
-# CONFIG_MAC80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+CONFIG_MAC80211_DEFAULT_PS_VALUE=0
 # CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
@@ -353,6 +378,7 @@ CONFIG_MTD_UCLINUX=y
 # UBI - Unsorted block images
 #
 # CONFIG_MTD_UBI is not set
+CONFIG_OF_DEVICE=y
 # CONFIG_PARPORT is not set
 CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
@@ -364,6 +390,7 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
 # CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+# CONFIG_XILINX_SYSACE is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_ENCLOSURE_SERVICES is not set
 # CONFIG_C2PORT is not set
@@ -383,7 +410,6 @@ CONFIG_MISC_DEVICES=y
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
-CONFIG_COMPAT_NET_DEV_OPS=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -402,7 +428,7 @@ CONFIG_NET_ETHERNET=y
 # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
 # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
 # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
-# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
 CONFIG_NETDEV_1000=y
 CONFIG_NETDEV_10000=y
 
@@ -463,23 +489,25 @@ CONFIG_HW_RANDOM=y
 # CONFIG_HW_RANDOM_TIMERIOMEM is not set
 # CONFIG_RTC is not set
 # CONFIG_GEN_RTC is not set
+# CONFIG_XILINX_HWICAP is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
 # CONFIG_I2C is not set
 # CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
 # CONFIG_THERMAL is not set
 # CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
-CONFIG_SSB_POSSIBLE=y
-
-#
-# Sonics Silicon Backplane
-#
-# CONFIG_SSB is not set
 
 #
 # Multifunction device drivers
@@ -489,22 +517,7 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_HTC_PASIC3 is not set
 # CONFIG_MFD_TMIO is not set
 # CONFIG_REGULATOR is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-# CONFIG_VIDEO_MEDIA is not set
-
-#
-# Multimedia drivers
-#
-CONFIG_DAB=y
+# CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
@@ -520,9 +533,10 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y
 # CONFIG_DISPLAY_SUPPORT is not set
 # CONFIG_SOUND is not set
 CONFIG_USB_SUPPORT=y
-# CONFIG_USB_ARCH_HAS_HCD is not set
+CONFIG_USB_ARCH_HAS_HCD=y
 # CONFIG_USB_ARCH_HAS_OHCI is not set
 # CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB is not set
 # CONFIG_USB_OTG_WHITELIST is not set
 # CONFIG_USB_OTG_BLACKLIST_HUB is not set
 
@@ -543,9 +557,12 @@ CONFIG_USB_SUPPORT=y
 # CONFIG_NEW_LEDS is not set
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_RTC_CLASS is not set
-# CONFIG_DMADEVICES is not set
 # CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
 # CONFIG_STAGING is not set
 
 #
@@ -558,12 +575,15 @@ CONFIG_EXT2_FS=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 CONFIG_FS_POSIX_ACL=y
-CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
 # CONFIG_DNOTIFY is not set
 # CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
@@ -813,6 +833,5 @@ CONFIG_GENERIC_FIND_LAST_BIT=y
 CONFIG_ZLIB_INFLATE=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
 CONFIG_HAVE_LMB=y
 CONFIG_NLATTR=y
diff --git a/arch/microblaze/include/asm/device.h b/arch/microblaze/include/asm/device.h
index c042830793ed..30286db27c1c 100644
--- a/arch/microblaze/include/asm/device.h
+++ b/arch/microblaze/include/asm/device.h
@@ -16,6 +16,9 @@ struct dev_archdata {
         struct device_node      *of_node;
 };
 
+struct pdev_archdata {
+};
+
 #endif /* _ASM_MICROBLAZE_DEVICE_H */
 
 
diff --git a/arch/microblaze/include/asm/hardirq.h b/arch/microblaze/include/asm/hardirq.h
index 41e1e1aa36ac..cd1ac9aad56c 100644
--- a/arch/microblaze/include/asm/hardirq.h
+++ b/arch/microblaze/include/asm/hardirq.h
@@ -12,8 +12,6 @@
 /* should be defined in each interrupt controller driver */
 extern unsigned int get_irq(struct pt_regs *regs);
 
-#define ack_bad_irq ack_bad_irq
-void ack_bad_irq(unsigned int irq);
 #include <asm-generic/hardirq.h>
 
 #endif /* _ASM_MICROBLAZE_HARDIRQ_H */
diff --git a/arch/microblaze/kernel/intc.c b/arch/microblaze/kernel/intc.c
index b15605299a57..6eea6f92b84e 100644
--- a/arch/microblaze/kernel/intc.c
+++ b/arch/microblaze/kernel/intc.c
@@ -12,6 +12,7 @@
 #include <linux/irq.h>
 #include <asm/page.h>
 #include <linux/io.h>
+#include <linux/bug.h>
 
 #include <asm/prom.h>
 #include <asm/irq.h>
@@ -130,6 +131,7 @@ void __init init_IRQ(void)
                 if (intc)
                         break;
         }
+        BUG_ON(!intc);
 
         intc_baseaddr = *(int *) of_get_property(intc, "reg", NULL);
         intc_baseaddr = (unsigned long) ioremap(intc_baseaddr, PAGE_SIZE);
diff --git a/arch/microblaze/kernel/irq.c b/arch/microblaze/kernel/irq.c
index f688ee93e3b9..7d5ddd62d4d2 100644
--- a/arch/microblaze/kernel/irq.c
+++ b/arch/microblaze/kernel/irq.c
@@ -30,15 +30,6 @@ unsigned int irq_of_parse_and_map(struct device_node *dev, int index)
 }
 EXPORT_SYMBOL_GPL(irq_of_parse_and_map);
 
-/*
- * 'what should we do if we get a hw irq event on an illegal vector'.
- * each architecture has to answer this themselves.
- */
-void ack_bad_irq(unsigned int irq)
-{
-        printk(KERN_WARNING "unexpected IRQ trap at vector %02x\n", irq);
-}
-
 static u32 concurrent_irq;
 
 void do_IRQ(struct pt_regs *regs)
diff --git a/arch/microblaze/kernel/syscall_table.S b/arch/microblaze/kernel/syscall_table.S
index 216db817beb6..457216097dfd 100644
--- a/arch/microblaze/kernel/syscall_table.S
+++ b/arch/microblaze/kernel/syscall_table.S
@@ -313,7 +313,7 @@ ENTRY(sys_call_table)
         .long sys_fchmodat
         .long sys_faccessat
         .long sys_ni_syscall /* pselect6 */
-        .long sys_ni_syscall /* sys_ppoll */
+        .long sys_ppoll
         .long sys_unshare               /* 310 */
         .long sys_set_robust_list
         .long sys_get_robust_list
diff --git a/arch/microblaze/kernel/timer.c b/arch/microblaze/kernel/timer.c
index bdfa2f9f0c81..5499deae7fa6 100644
--- a/arch/microblaze/kernel/timer.c
+++ b/arch/microblaze/kernel/timer.c
@@ -22,6 +22,7 @@
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
 #include <linux/io.h>
+#include <linux/bug.h>
 #include <asm/cpuinfo.h>
 #include <asm/setup.h>
 #include <asm/prom.h>
@@ -234,6 +235,7 @@ void __init time_init(void)
                 if (timer)
                         break;
         }
+        BUG_ON(!timer);
 
         timer_baseaddr = *(int *) of_get_property(timer, "reg", NULL);
         timer_baseaddr = (unsigned long) ioremap(timer_baseaddr, PAGE_SIZE);
diff --git a/arch/microblaze/mm/init.c b/arch/microblaze/mm/init.c
index 8d92c4efe9a4..f207f1a94dbc 100644
--- a/arch/microblaze/mm/init.c
+++ b/arch/microblaze/mm/init.c
@@ -130,13 +130,13 @@ void __init setup_memory(void)
          * (in case the address isn't page-aligned).
          */
 #ifndef CONFIG_MMU
-        map_size = init_bootmem_node(NODE_DATA(0), PFN_UP(TOPHYS((u32)_end)),
+        map_size = init_bootmem_node(NODE_DATA(0), PFN_UP(TOPHYS((u32)klimit)),
                                         min_low_pfn, max_low_pfn);
 #else
         map_size = init_bootmem_node(&contig_page_data,
-                PFN_UP(TOPHYS((u32)_end)), min_low_pfn, max_low_pfn);
+                PFN_UP(TOPHYS((u32)klimit)), min_low_pfn, max_low_pfn);
 #endif
-        lmb_reserve(PFN_UP(TOPHYS((u32)_end)) << PAGE_SHIFT, map_size);
+        lmb_reserve(PFN_UP(TOPHYS((u32)klimit)) << PAGE_SHIFT, map_size);
 
         /* free bootmem is whole main memory */
         free_bootmem(memory_start, memory_size);
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index 96a14a426a7c..4320239cf4ef 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -32,10 +32,12 @@
 #define PAGE_SIZE       (1UL << PAGE_SHIFT)
 #define PAGE_MASK       (~((1 << PAGE_SHIFT) - 1))
 
+#ifdef CONFIG_HUGETLB_PAGE
 #define HPAGE_SHIFT     (PAGE_SHIFT + PAGE_SHIFT - 3)
 #define HPAGE_SIZE      ((1UL) << HPAGE_SHIFT)
 #define HPAGE_MASK      (~(HPAGE_SIZE - 1))
 #define HUGETLB_PAGE_ORDER      (HPAGE_SHIFT - PAGE_SHIFT)
+#endif /* CONFIG_HUGETLB_PAGE */
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/powerpc/include/asm/device.h b/arch/powerpc/include/asm/device.h
index 7d2277cef09a..e3e06e0f7fc0 100644
--- a/arch/powerpc/include/asm/device.h
+++ b/arch/powerpc/include/asm/device.h
@@ -30,4 +30,7 @@ dev_archdata_get_node(const struct dev_archdata *ad)
         return ad->of_node;
 }
 
+struct pdev_archdata {
+};
+
 #endif /* _ASM_POWERPC_DEVICE_H */
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index c4a955d25451..2f5352c06a0e 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -219,6 +219,8 @@ config CPU_SHX3
 config ARCH_SHMOBILE
         bool
         select ARCH_SUSPEND_POSSIBLE
+        select PM
+        select PM_RUNTIME
 
 if SUPERH32
 
@@ -396,6 +398,13 @@ config CPU_SUBTYPE_SH7724
         help
           Select SH7724 if you have an SH-MobileR2R CPU.
 
+config CPU_SUBTYPE_SH7757
+        bool "Support SH7757 processor"
+        select CPU_SH4A
+        select CPU_SHX2
+        help
+          Select SH7757 if you have a SH4A SH7757 CPU.
+
 config CPU_SUBTYPE_SH7763
         bool "Support SH7763 processor"
         select CPU_SH4A
@@ -758,12 +767,31 @@ config UBC_WAKEUP
 
           If unsure, say N.
 
-config CMDLINE_BOOL
-        bool "Default bootloader kernel arguments"
+choice
+        prompt "Kernel command line"
+        optional
+        default CMDLINE_OVERWRITE
+        help
+          Setting this option allows the kernel command line arguments
+          to be set.
+
+config CMDLINE_OVERWRITE
+        bool "Overwrite bootloader kernel arguments"
+        help
+          Given string will overwrite any arguments passed in by
+          a bootloader.
+
+config CMDLINE_EXTEND
+        bool "Extend bootloader kernel arguments"
+        help
+          Given string will be concatenated with arguments passed in
+          by a bootloader.
+
+endchoice
 
 config CMDLINE
-        string "Initial kernel command string"
-        depends on CMDLINE_BOOL
+        string "Kernel command line arguments string"
+        depends on CMDLINE_OVERWRITE || CMDLINE_EXTEND
         default "console=ttySC1,115200"
 
 endmenu
diff --git a/arch/sh/Kconfig.debug b/arch/sh/Kconfig.debug
index 741d20fab2e1..55907af1dc25 100644
--- a/arch/sh/Kconfig.debug
+++ b/arch/sh/Kconfig.debug
@@ -38,6 +38,7 @@ config EARLY_SCIF_CONSOLE_PORT
         default "0xffe00000" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7763 || \
                                 CPU_SUBTYPE_SH7722 || CPU_SUBTYPE_SH7366 || \
                                 CPU_SUBTYPE_SH7343
+        default "0xfe4c0000" if CPU_SUBTYPE_SH7757
         default "0xffeb0000" if CPU_SUBTYPE_SH7785
         default "0xffeb0000" if CPU_SUBTYPE_SH7786
         default "0xfffe8000" if CPU_SUBTYPE_SH7203
diff --git a/arch/sh/Makefile b/arch/sh/Makefile
index e26421bf9976..fc51a918b31a 100644
--- a/arch/sh/Makefile
+++ b/arch/sh/Makefile
@@ -137,6 +137,7 @@ machdir-$(CONFIG_SH_EDOSK7705)			+= mach-edosk7705
 machdir-$(CONFIG_SH_HIGHLANDER)                 += mach-highlander
 machdir-$(CONFIG_SH_MIGOR)                      += mach-migor
 machdir-$(CONFIG_SH_KFR2R09)                    += mach-kfr2r09
+machdir-$(CONFIG_SH_ECOVEC)                     += mach-ecovec24
 machdir-$(CONFIG_SH_SDK7780)                    += mach-sdk7780
 machdir-$(CONFIG_SH_X3PROTO)                    += mach-x3proto
 machdir-$(CONFIG_SH_SH7763RDP)                  += mach-sh7763rdp
diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig
index db04c85971ad..ee5bb200c715 100644
--- a/arch/sh/boards/Kconfig
+++ b/arch/sh/boards/Kconfig
@@ -171,6 +171,13 @@ config SH_SH7785LCR_29BIT_PHYSMAPS
           DIP switch(S2-5). If you set the DIP switch for S2-5 = ON,
           you can access all on-board device in 29bit address mode.
 
+config SH_SH7785LCR_PT
+        bool "SH7785LCR prototype board on 32-bit MMU mode"
+        depends on SH_SH7785LCR && 32BIT
+        default n
+        help
+          If you use prototype board, this option is enabled.
+
 config SH_URQUELL
         bool "Urquell"
         depends on CPU_SUBTYPE_SH7786
@@ -200,6 +207,13 @@ config SH_KFR2R09
         help
           "Kit For R2R for 2009" support.
 
+config SH_ECOVEC
+        bool "EcoVec"
+        depends on CPU_SUBTYPE_SH7724
+        select ARCH_REQUIRE_GPIOLIB
+        help
+          Renesas "R0P7724LC0011/21RL (EcoVec)" support.
+
 config SH_SH7763RDP
         bool "SH7763RDP"
         depends on CPU_SUBTYPE_SH7763
diff --git a/arch/sh/boards/board-ap325rxa.c b/arch/sh/boards/board-ap325rxa.c
index b9c88cc519e2..19eea4ab1ccc 100644
--- a/arch/sh/boards/board-ap325rxa.c
+++ b/arch/sh/boards/board-ap325rxa.c
@@ -227,6 +227,9 @@ static struct platform_device lcdc_device = {
         .dev            = {
                 .platform_data  = &lcdc_info,
         },
+        .archdata = {
+                .hwblk_id = HWBLK_LCDC,
+        },
 };
 
 static void camera_power(int val)
@@ -377,6 +380,9 @@ static struct platform_device ceu_device = {
         .dev            = {
                 .platform_data  = &sh_mobile_ceu_info,
         },
+        .archdata = {
+                .hwblk_id = HWBLK_CEU,
+        },
 };
 
 struct spi_gpio_platform_data sdcard_cn3_platform_data = {
diff --git a/arch/sh/boards/board-sh7785lcr.c b/arch/sh/boards/board-sh7785lcr.c
index 42410a15d255..726427c3522b 100644
--- a/arch/sh/boards/board-sh7785lcr.c
+++ b/arch/sh/boards/board-sh7785lcr.c
@@ -223,6 +223,19 @@ static struct platform_device sm501_device = {
         .resource       = sm501_resources,
 };
 
+static struct resource i2c_proto_resources[] = {
+        [0] = {
+                .start  = PCA9564_PROTO_32BIT_ADDR,
+                .end    = PCA9564_PROTO_32BIT_ADDR + PCA9564_SIZE - 1,
+                .flags  = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
+        },
+        [1] = {
+                .start  = 12,
+                .end    = 12,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
 static struct resource i2c_resources[] = {
         [0] = {
                 .start  = PCA9564_ADDR,
@@ -271,6 +284,11 @@ static int __init sh7785lcr_devices_setup(void)
         i2c_register_board_info(0, sh7785lcr_i2c_devices,
                                 ARRAY_SIZE(sh7785lcr_i2c_devices));
 
+        if (mach_is_sh7785lcr_pt()) {
+                i2c_device.resource = &i2c_proto_resources;
+                i2c_device.num_resources = ARRAY_SIZE(i2c_proto_resources);
+        }
+
         return platform_add_devices(sh7785lcr_devices,
                                     ARRAY_SIZE(sh7785lcr_devices));
 }
diff --git a/arch/sh/boards/mach-ecovec24/Makefile b/arch/sh/boards/mach-ecovec24/Makefile
new file mode 100644
index 000000000000..51f852151655
--- /dev/null
+++ b/arch/sh/boards/mach-ecovec24/Makefile
@@ -0,0 +1,9 @@
+#
+# Makefile for the R0P7724LC0011/21RL (EcoVec)
+#
+# This file is subject to the terms and conditions of the GNU General Public
+# License.  See the file "COPYING" in the main directory of this archive
+# for more details.
+#
+
+obj-y    := setup.o
\ No newline at end of file
diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c
new file mode 100644
index 000000000000..428d1187ce5c
--- /dev/null
+++ b/arch/sh/boards/mach-ecovec24/setup.c
@@ -0,0 +1,516 @@
+/*
+ * Copyright (C) 2009 Renesas Solutions Corp.
+ *
+ * Kuninori Morimoto <morimoto.kuninori@renesas.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/usb/r8a66597.h>
+#include <video/sh_mobile_lcdc.h>
+#include <media/sh_mobile_ceu.h>
+#include <asm/heartbeat.h>
+#include <asm/sh_eth.h>
+#include <cpu/sh7724.h>
+
+/*
+ *  Address      Interface        BusWidth
+ *-----------------------------------------
+ *  0x0000_0000  uboot            16bit
+ *  0x0004_0000  Linux romImage   16bit
+ *  0x0014_0000  MTD for Linux    16bit
+ *  0x0400_0000  Internal I/O     16/32bit
+ *  0x0800_0000  DRAM             32bit
+ *  0x1800_0000  MFI              16bit
+ */
+
+/* Heartbeat */
+static unsigned char led_pos[] = { 0, 1, 2, 3 };
+static struct heartbeat_data heartbeat_data = {
+        .regsize = 8,
+        .nr_bits = 4,
+        .bit_pos = led_pos,
+};
+
+static struct resource heartbeat_resources[] = {
+        [0] = {
+                .start  = 0xA405012C, /* PTG */
+                .end    = 0xA405012E - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device heartbeat_device = {
+        .name           = "heartbeat",
+        .id             = -1,
+        .dev = {
+                .platform_data = &heartbeat_data,
+        },
+        .num_resources  = ARRAY_SIZE(heartbeat_resources),
+        .resource       = heartbeat_resources,
+};
+
+/* MTD */
+static struct mtd_partition nor_flash_partitions[] = {
+        {
+                .name = "boot loader",
+                .offset = 0,
+                .size = (5 * 1024 * 1024),
+                .mask_flags = MTD_CAP_ROM,
+        }, {
+                .name = "free-area",
+                .offset = MTDPART_OFS_APPEND,
+                .size = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct physmap_flash_data nor_flash_data = {
+        .width          = 2,
+        .parts          = nor_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(nor_flash_partitions),
+};
+
+static struct resource nor_flash_resources[] = {
+        [0] = {
+                .name   = "NOR Flash",
+                .start  = 0x00000000,
+                .end    = 0x03ffffff,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device nor_flash_device = {
+        .name           = "physmap-flash",
+        .resource       = nor_flash_resources,
+        .num_resources  = ARRAY_SIZE(nor_flash_resources),
+        .dev            = {
+                .platform_data = &nor_flash_data,
+        },
+};
+
+/* SH Eth */
+#define SH_ETH_ADDR     (0xA4600000)
+#define SH_ETH_MAHR     (SH_ETH_ADDR + 0x1C0)
+#define SH_ETH_MALR     (SH_ETH_ADDR + 0x1C8)
+static struct resource sh_eth_resources[] = {
+        [0] = {
+                .start = SH_ETH_ADDR,
+                .end   = SH_ETH_ADDR + 0x1FC,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = 91,
+                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
+        },
+};
+
+struct sh_eth_plat_data sh_eth_plat = {
+        .phy = 0x1f, /* SMSC LAN8700 */
+        .edmac_endian = EDMAC_LITTLE_ENDIAN,
+};
+
+static struct platform_device sh_eth_device = {
+        .name = "sh-eth",
+        .id     = 0,
+        .dev = {
+                .platform_data = &sh_eth_plat,
+        },
+        .num_resources = ARRAY_SIZE(sh_eth_resources),
+        .resource = sh_eth_resources,
+};
+
+/* USB0 host */
+void usb0_port_power(int port, int power)
+{
+        gpio_set_value(GPIO_PTB4, power);
+}
+
+static struct r8a66597_platdata usb0_host_data = {
+        .on_chip = 1,
+        .port_power = usb0_port_power,
+};
+
+static struct resource usb0_host_resources[] = {
+        [0] = {
+                .start  = 0xa4d80000,
+                .end    = 0xa4d80124 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 65,
+                .end    = 65,
+                .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
+        },
+};
+
+static struct platform_device usb0_host_device = {
+        .name           = "r8a66597_hcd",
+        .id             = 0,
+        .dev = {
+                .dma_mask               = NULL,         /*  not use dma */
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &usb0_host_data,
+        },
+        .num_resources  = ARRAY_SIZE(usb0_host_resources),
+        .resource       = usb0_host_resources,
+};
+
+/*
+ * USB1
+ *
+ * CN5 can use both host/function,
+ * and we can determine it by checking PTB[3]
+ *
+ * This time only USB1 host is supported.
+ */
+void usb1_port_power(int port, int power)
+{
+        if (!gpio_get_value(GPIO_PTB3)) {
+                printk(KERN_ERR "USB1 function is not supported\n");
+                return;
+        }
+
+        gpio_set_value(GPIO_PTB5, power);
+}
+
+static struct r8a66597_platdata usb1_host_data = {
+        .on_chip = 1,
+        .port_power = usb1_port_power,
+};
+
+static struct resource usb1_host_resources[] = {
+        [0] = {
+                .start  = 0xa4d90000,
+                .end    = 0xa4d90124 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 66,
+                .end    = 66,
+                .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
+        },
+};
+
+static struct platform_device usb1_host_device = {
+        .name           = "r8a66597_hcd",
+        .id             = 1,
+        .dev = {
+                .dma_mask               = NULL,         /*  not use dma */
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &usb1_host_data,
+        },
+        .num_resources  = ARRAY_SIZE(usb1_host_resources),
+        .resource       = usb1_host_resources,
+};
+
+/* LCDC */
+static struct sh_mobile_lcdc_info lcdc_info = {
+        .ch[0] = {
+                .interface_type = RGB18,
+                .chan = LCDC_CHAN_MAINLCD,
+                .bpp = 16,
+                .lcd_cfg = {
+                        .sync = 0, /* hsync and vsync are active low */
+                },
+                .lcd_size_cfg = { /* 7.0 inch */
+                        .width = 152,
+                        .height = 91,
+                },
+                .board_cfg = {
+                },
+        }
+};
+
+static struct resource lcdc_resources[] = {
+        [0] = {
+                .name   = "LCDC",
+                .start  = 0xfe940000,
+                .end    = 0xfe941fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 106,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device lcdc_device = {
+        .name           = "sh_mobile_lcdc_fb",
+        .num_resources  = ARRAY_SIZE(lcdc_resources),
+        .resource       = lcdc_resources,
+        .dev            = {
+                .platform_data  = &lcdc_info,
+        },
+        .archdata = {
+                .hwblk_id = HWBLK_LCDC,
+        },
+};
+
+/* CEU0 */
+static struct sh_mobile_ceu_info sh_mobile_ceu0_info = {
+        .flags = SH_CEU_FLAG_USE_8BIT_BUS,
+};
+
+static struct resource ceu0_resources[] = {
+        [0] = {
+                .name   = "CEU0",
+                .start  = 0xfe910000,
+                .end    = 0xfe91009f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 52,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                /* place holder for contiguous memory */
+        },
+};
+
+static struct platform_device ceu0_device = {
+        .name           = "sh_mobile_ceu",
+        .id             = 0, /* "ceu0" clock */
+        .num_resources  = ARRAY_SIZE(ceu0_resources),
+        .resource       = ceu0_resources,
+        .dev    = {
+                .platform_data  = &sh_mobile_ceu0_info,
+        },
+        .archdata = {
+                .hwblk_id = HWBLK_CEU0,
+        },
+};
+
+/* CEU1 */
+static struct sh_mobile_ceu_info sh_mobile_ceu1_info = {
+        .flags = SH_CEU_FLAG_USE_8BIT_BUS,
+};
+
+static struct resource ceu1_resources[] = {
+        [0] = {
+                .name   = "CEU1",
+                .start  = 0xfe914000,
+                .end    = 0xfe91409f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 63,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                /* place holder for contiguous memory */
+        },
+};
+
+static struct platform_device ceu1_device = {
+        .name           = "sh_mobile_ceu",
+        .id             = 1, /* "ceu1" clock */
+        .num_resources  = ARRAY_SIZE(ceu1_resources),
+        .resource       = ceu1_resources,
+        .dev    = {
+                .platform_data  = &sh_mobile_ceu1_info,
+        },
+        .archdata = {
+                .hwblk_id = HWBLK_CEU1,
+        },
+};
+
+static struct platform_device *ecovec_devices[] __initdata = {
+        &heartbeat_device,
+        &nor_flash_device,
+        &sh_eth_device,
+        &usb0_host_device,
+        &usb1_host_device, /* USB1 host support */
+        &lcdc_device,
+        &ceu0_device,
+        &ceu1_device,
+};
+
+#define PORT_HIZA 0xA4050158
+#define IODRIVEA  0xA405018A
+static int __init devices_setup(void)
+{
+        /* enable SCIFA0 */
+        gpio_request(GPIO_FN_SCIF0_TXD, NULL);
+        gpio_request(GPIO_FN_SCIF0_RXD, NULL);
+
+        /* enable debug LED */
+        gpio_request(GPIO_PTG0, NULL);
+        gpio_request(GPIO_PTG1, NULL);
+        gpio_request(GPIO_PTG2, NULL);
+        gpio_request(GPIO_PTG3, NULL);
+        gpio_direction_output(GPIO_PTG0, 0);
+        gpio_direction_output(GPIO_PTG1, 0);
+        gpio_direction_output(GPIO_PTG2, 0);
+        gpio_direction_output(GPIO_PTG3, 0);
+
+        /* enable SH-Eth */
+        gpio_request(GPIO_PTA1, NULL);
+        gpio_direction_output(GPIO_PTA1, 1);
+        mdelay(20);
+
+        gpio_request(GPIO_FN_RMII_RXD0,    NULL);
+        gpio_request(GPIO_FN_RMII_RXD1,    NULL);
+        gpio_request(GPIO_FN_RMII_TXD0,    NULL);
+        gpio_request(GPIO_FN_RMII_TXD1,    NULL);
+        gpio_request(GPIO_FN_RMII_REF_CLK, NULL);
+        gpio_request(GPIO_FN_RMII_TX_EN,   NULL);
+        gpio_request(GPIO_FN_RMII_RX_ER,   NULL);
+        gpio_request(GPIO_FN_RMII_CRS_DV,  NULL);
+        gpio_request(GPIO_FN_MDIO,         NULL);
+        gpio_request(GPIO_FN_MDC,          NULL);
+        gpio_request(GPIO_FN_LNKSTA,       NULL);
+
+        /* enable USB */
+        gpio_request(GPIO_PTB3,  NULL);
+        gpio_request(GPIO_PTB4,  NULL);
+        gpio_request(GPIO_PTB5,  NULL);
+        gpio_direction_input(GPIO_PTB3);
+        gpio_direction_output(GPIO_PTB4, 0);
+        gpio_direction_output(GPIO_PTB5, 0);
+        ctrl_outw(0x0600, 0xa40501d4);
+        ctrl_outw(0x0600, 0xa4050192);
+
+        /* enable LCDC */
+        gpio_request(GPIO_FN_LCDD23,   NULL);
+        gpio_request(GPIO_FN_LCDD22,   NULL);
+        gpio_request(GPIO_FN_LCDD21,   NULL);
+        gpio_request(GPIO_FN_LCDD20,   NULL);
+        gpio_request(GPIO_FN_LCDD19,   NULL);
+        gpio_request(GPIO_FN_LCDD18,   NULL);
+        gpio_request(GPIO_FN_LCDD17,   NULL);
+        gpio_request(GPIO_FN_LCDD16,   NULL);
+        gpio_request(GPIO_FN_LCDD15,   NULL);
+        gpio_request(GPIO_FN_LCDD14,   NULL);
+        gpio_request(GPIO_FN_LCDD13,   NULL);
+        gpio_request(GPIO_FN_LCDD12,   NULL);
+        gpio_request(GPIO_FN_LCDD11,   NULL);
+        gpio_request(GPIO_FN_LCDD10,   NULL);
+        gpio_request(GPIO_FN_LCDD9,    NULL);
+        gpio_request(GPIO_FN_LCDD8,    NULL);
+        gpio_request(GPIO_FN_LCDD7,    NULL);
+        gpio_request(GPIO_FN_LCDD6,    NULL);
+        gpio_request(GPIO_FN_LCDD5,    NULL);
+        gpio_request(GPIO_FN_LCDD4,    NULL);
+        gpio_request(GPIO_FN_LCDD3,    NULL);
+        gpio_request(GPIO_FN_LCDD2,    NULL);
+        gpio_request(GPIO_FN_LCDD1,    NULL);
+        gpio_request(GPIO_FN_LCDD0,    NULL);
+        gpio_request(GPIO_FN_LCDDISP,  NULL);
+        gpio_request(GPIO_FN_LCDHSYN,  NULL);
+        gpio_request(GPIO_FN_LCDDCK,   NULL);
+        gpio_request(GPIO_FN_LCDVSYN,  NULL);
+        gpio_request(GPIO_FN_LCDDON,   NULL);
+        gpio_request(GPIO_FN_LCDLCLK,  NULL);
+        ctrl_outw((ctrl_inw(PORT_HIZA) & ~0x0001), PORT_HIZA);
+
+        gpio_request(GPIO_PTE6, NULL);
+        gpio_request(GPIO_PTU1, NULL);
+        gpio_request(GPIO_PTR1, NULL);
+        gpio_request(GPIO_PTA2, NULL);
+        gpio_direction_input(GPIO_PTE6);
+        gpio_direction_output(GPIO_PTU1, 0);
+        gpio_direction_output(GPIO_PTR1, 0);
+        gpio_direction_output(GPIO_PTA2, 0);
+
+        /* I/O buffer drive ability is low */
+        ctrl_outw((ctrl_inw(IODRIVEA) & ~0x00c0) | 0x0040 , IODRIVEA);
+
+        if (gpio_get_value(GPIO_PTE6)) {
+                /* DVI */
+                lcdc_info.clock_source                  = LCDC_CLK_EXTERNAL;
+                lcdc_info.ch[0].clock_divider           = 1,
+                lcdc_info.ch[0].lcd_cfg.name            = "DVI";
+                lcdc_info.ch[0].lcd_cfg.xres            = 1280;
+                lcdc_info.ch[0].lcd_cfg.yres            = 720;
+                lcdc_info.ch[0].lcd_cfg.left_margin     = 220;
+                lcdc_info.ch[0].lcd_cfg.right_margin    = 110;
+                lcdc_info.ch[0].lcd_cfg.hsync_len       = 40;
+                lcdc_info.ch[0].lcd_cfg.upper_margin    = 20;
+                lcdc_info.ch[0].lcd_cfg.lower_margin    = 5;
+                lcdc_info.ch[0].lcd_cfg.vsync_len       = 5;
+
+                gpio_set_value(GPIO_PTA2, 1);
+                gpio_set_value(GPIO_PTU1, 1);
+        } else {
+                /* Panel */
+
+                lcdc_info.clock_source                  = LCDC_CLK_PERIPHERAL;
+                lcdc_info.ch[0].clock_divider           = 2,
+                lcdc_info.ch[0].lcd_cfg.name            = "Panel";
+                lcdc_info.ch[0].lcd_cfg.xres            = 800;
+                lcdc_info.ch[0].lcd_cfg.yres            = 480;
+                lcdc_info.ch[0].lcd_cfg.left_margin     = 220;
+                lcdc_info.ch[0].lcd_cfg.right_margin    = 110;
+                lcdc_info.ch[0].lcd_cfg.hsync_len       = 70;
+                lcdc_info.ch[0].lcd_cfg.upper_margin    = 20;
+                lcdc_info.ch[0].lcd_cfg.lower_margin    = 5;
+                lcdc_info.ch[0].lcd_cfg.vsync_len       = 5;
+
+                gpio_set_value(GPIO_PTR1, 1);
+
+                /* FIXME
+                 *
+                 * LCDDON control is needed for Panel,
+                 * but current sh_mobile_lcdc driver doesn't control it.
+                 * It is temporary correspondence
+                 */
+                gpio_request(GPIO_PTF4, NULL);
+                gpio_direction_output(GPIO_PTF4, 1);
+        }
+
+        /* enable CEU0 */
+        gpio_request(GPIO_FN_VIO0_D15, NULL);
+        gpio_request(GPIO_FN_VIO0_D14, NULL);
+        gpio_request(GPIO_FN_VIO0_D13, NULL);
+        gpio_request(GPIO_FN_VIO0_D12, NULL);
+        gpio_request(GPIO_FN_VIO0_D11, NULL);
+        gpio_request(GPIO_FN_VIO0_D10, NULL);
+        gpio_request(GPIO_FN_VIO0_D9,  NULL);
+        gpio_request(GPIO_FN_VIO0_D8,  NULL);
+        gpio_request(GPIO_FN_VIO0_D7,  NULL);
+        gpio_request(GPIO_FN_VIO0_D6,  NULL);
+        gpio_request(GPIO_FN_VIO0_D5,  NULL);
+        gpio_request(GPIO_FN_VIO0_D4,  NULL);
+        gpio_request(GPIO_FN_VIO0_D3,  NULL);
+        gpio_request(GPIO_FN_VIO0_D2,  NULL);
+        gpio_request(GPIO_FN_VIO0_D1,  NULL);
+        gpio_request(GPIO_FN_VIO0_D0,  NULL);
+        gpio_request(GPIO_FN_VIO0_VD,  NULL);
+        gpio_request(GPIO_FN_VIO0_CLK, NULL);
+        gpio_request(GPIO_FN_VIO0_FLD, NULL);
+        gpio_request(GPIO_FN_VIO0_HD,  NULL);
+        platform_resource_setup_memory(&ceu0_device, "ceu0", 4 << 20);
+
+        /* enable CEU1 */
+        gpio_request(GPIO_FN_VIO1_D7,  NULL);
+        gpio_request(GPIO_FN_VIO1_D6,  NULL);
+        gpio_request(GPIO_FN_VIO1_D5,  NULL);
+        gpio_request(GPIO_FN_VIO1_D4,  NULL);
+        gpio_request(GPIO_FN_VIO1_D3,  NULL);
+        gpio_request(GPIO_FN_VIO1_D2,  NULL);
+        gpio_request(GPIO_FN_VIO1_D1,  NULL);
+        gpio_request(GPIO_FN_VIO1_D0,  NULL);
+        gpio_request(GPIO_FN_VIO1_FLD, NULL);
+        gpio_request(GPIO_FN_VIO1_HD,  NULL);
+        gpio_request(GPIO_FN_VIO1_VD,  NULL);
+        gpio_request(GPIO_FN_VIO1_CLK, NULL);
+        platform_resource_setup_memory(&ceu1_device, "ceu1", 4 << 20);
+
+        return platform_add_devices(ecovec_devices,
+                                    ARRAY_SIZE(ecovec_devices));
+}
+device_initcall(devices_setup);
+
+static struct sh_machine_vector mv_ecovec __initmv = {
+        .mv_name        = "R0P7724 (EcoVec)",
+};
diff --git a/arch/sh/boards/mach-kfr2r09/setup.c b/arch/sh/boards/mach-kfr2r09/setup.c
index bdb10c29ef18..7155be0d1154 100644
--- a/arch/sh/boards/mach-kfr2r09/setup.c
+++ b/arch/sh/boards/mach-kfr2r09/setup.c
@@ -16,6 +16,8 @@
 #include <linux/clk.h>
 #include <linux/gpio.h>
 #include <linux/input.h>
+#include <linux/i2c.h>
+#include <linux/usb/r8a66597.h>
 #include <video/sh_mobile_lcdc.h>
 #include <asm/clock.h>
 #include <asm/machvec.h>
@@ -113,6 +115,9 @@ static struct platform_device kfr2r09_sh_keysc_device = {
         .dev    = {
                 .platform_data  = &kfr2r09_sh_keysc_info,
         },
+        .archdata = {
+                .hwblk_id = HWBLK_KEYSC,
+        },
 };
 
 static struct sh_mobile_lcdc_info kfr2r09_sh_lcdc_info = {
@@ -173,6 +178,38 @@ static struct platform_device kfr2r09_sh_lcdc_device = {
         .dev    = {
                 .platform_data  = &kfr2r09_sh_lcdc_info,
         },
+        .archdata = {
+                .hwblk_id = HWBLK_LCDC,
+        },
+};
+
+static struct r8a66597_platdata kfr2r09_usb0_gadget_data = {
+        .on_chip = 1,
+};
+
+static struct resource kfr2r09_usb0_gadget_resources[] = {
+        [0] = {
+                .start  = 0x04d80000,
+                .end    = 0x04d80123,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 65,
+                .end    = 65,
+                .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
+        },
+};
+
+static struct platform_device kfr2r09_usb0_gadget_device = {
+        .name           = "r8a66597_udc",
+        .id             = 0,
+        .dev = {
+                .dma_mask               = NULL,         /*  not use dma */
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data  = &kfr2r09_usb0_gadget_data,
+        },
+        .num_resources  = ARRAY_SIZE(kfr2r09_usb0_gadget_resources),
+        .resource       = kfr2r09_usb0_gadget_resources,
 };
 
 static struct platform_device *kfr2r09_devices[] __initdata = {
@@ -186,6 +223,81 @@ static struct platform_device *kfr2r09_devices[] __initdata = {
 #define BSC_CS0WCR 0xfec10024
 #define BSC_CS4BCR 0xfec10010
 #define BSC_CS4WCR 0xfec10030
+#define PORT_MSELCRB 0xa4050182
+
+#ifdef CONFIG_I2C
+static int kfr2r09_usb0_gadget_i2c_setup(void)
+{
+        struct i2c_adapter *a;
+        struct i2c_msg msg;
+        unsigned char buf[2];
+        int ret;
+
+        a = i2c_get_adapter(0);
+        if (!a)
+                return -ENODEV;
+
+        /* set bit 1 (the second bit) of chip at 0x09, register 0x13 */
+        buf[0] = 0x13;
+        msg.addr = 0x09;
+        msg.buf = buf;
+        msg.len = 1;
+        msg.flags = 0;
+        ret = i2c_transfer(a, &msg, 1);
+        if (ret != 1)
+                return -ENODEV;
+
+        buf[0] = 0;
+        msg.addr = 0x09;
+        msg.buf = buf;
+        msg.len = 1;
+        msg.flags = I2C_M_RD;
+        ret = i2c_transfer(a, &msg, 1);
+        if (ret != 1)
+                return -ENODEV;
+
+        buf[1] = buf[0] | (1 << 1);
+        buf[0] = 0x13;
+        msg.addr = 0x09;
+        msg.buf = buf;
+        msg.len = 2;
+        msg.flags = 0;
+        ret = i2c_transfer(a, &msg, 1);
+        if (ret != 1)
+                return -ENODEV;
+
+        return 0;
+}
+#else
+static int kfr2r09_usb0_gadget_i2c_setup(void)
+{
+        return -ENODEV;
+}
+#endif
+
+static int kfr2r09_usb0_gadget_setup(void)
+{
+        int plugged_in;
+
+        gpio_request(GPIO_PTN4, NULL); /* USB_DET */
+        gpio_direction_input(GPIO_PTN4);
+        plugged_in = gpio_get_value(GPIO_PTN4);
+        if (!plugged_in)
+                return -ENODEV; /* no cable plugged in */
+
+        if (kfr2r09_usb0_gadget_i2c_setup() != 0)
+                return -ENODEV; /* unable to configure using i2c */
+
+        ctrl_outw((ctrl_inw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB);
+        gpio_request(GPIO_FN_PDSTATUS, NULL); /* R-standby disables USB clock */
+        gpio_request(GPIO_PTV6, NULL); /* USBCLK_ON */
+        gpio_direction_output(GPIO_PTV6, 1); /* USBCLK_ON = H */
+        msleep(20); /* wait 20ms to let the clock settle */
+        clk_enable(clk_get(NULL, "usb0"));
+        ctrl_outw(0x0600, 0xa40501d4);
+
+        return 0;
+}
 
 static int __init kfr2r09_devices_setup(void)
 {
@@ -245,6 +357,10 @@ static int __init kfr2r09_devices_setup(void)
         gpio_request(GPIO_PTU0, NULL); /* LEDSTDBY/ */
         gpio_direction_output(GPIO_PTU0, 1);
 
+        /* setup USB function */
+        if (kfr2r09_usb0_gadget_setup() == 0)
+                platform_device_register(&kfr2r09_usb0_gadget_device);
+
         return platform_add_devices(kfr2r09_devices,
                                     ARRAY_SIZE(kfr2r09_devices));
 }
diff --git a/arch/sh/boards/mach-migor/setup.c b/arch/sh/boards/mach-migor/setup.c
index f9b2e4df35b9..be8f0d94f6f1 100644
--- a/arch/sh/boards/mach-migor/setup.c
+++ b/arch/sh/boards/mach-migor/setup.c
@@ -98,6 +98,9 @@ static struct platform_device sh_keysc_device = {
         .dev    = {
                 .platform_data  = &sh_keysc_info,
         },
+        .archdata = {
+                .hwblk_id = HWBLK_KEYSC,
+        },
 };
 
 static struct mtd_partition migor_nor_flash_partitions[] =
@@ -292,6 +295,9 @@ static struct platform_device migor_lcdc_device = {
         .dev    = {
                 .platform_data  = &sh_mobile_lcdc_info,
         },
+        .archdata = {
+                .hwblk_id = HWBLK_LCDC,
+        },
 };
 
 static struct clk *camera_clk;
@@ -379,6 +385,9 @@ static struct platform_device migor_ceu_device = {
         .dev    = {
                 .platform_data  = &sh_mobile_ceu_info,
         },
+        .archdata = {
+                .hwblk_id = HWBLK_CEU,
+        },
 };
 
 struct spi_gpio_platform_data sdcard_cn9_platform_data = {
diff --git a/arch/sh/boards/mach-se/7722/setup.c b/arch/sh/boards/mach-se/7722/setup.c
index af84904ed86f..36374078e521 100644
--- a/arch/sh/boards/mach-se/7722/setup.c
+++ b/arch/sh/boards/mach-se/7722/setup.c
@@ -22,6 +22,7 @@
 #include <asm/io.h>
 #include <asm/heartbeat.h>
 #include <asm/sh_keysc.h>
+#include <cpu/sh7722.h>
 
 /* Heartbeat */
 static struct heartbeat_data heartbeat_data = {
@@ -137,6 +138,9 @@ static struct platform_device sh_keysc_device = {
         .dev    = {
                 .platform_data  = &sh_keysc_info,
         },
+        .archdata = {
+                .hwblk_id = HWBLK_KEYSC,
+        },
 };
 
 static struct platform_device *se7722_devices[] __initdata = {
diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c
index 9162081504ef..1876c8306c85 100644
--- a/arch/sh/boards/mach-se/7724/setup.c
+++ b/arch/sh/boards/mach-se/7724/setup.c
@@ -182,6 +182,9 @@ static struct platform_device lcdc_device = {
         .dev            = {
                 .platform_data  = &lcdc_info,
         },
+        .archdata = {
+                .hwblk_id = HWBLK_LCDC,
+        },
 };
 
 /* CEU0 */
@@ -213,6 +216,9 @@ static struct platform_device ceu0_device = {
         .dev    = {
                 .platform_data  = &sh_mobile_ceu0_info,
         },
+        .archdata = {
+                .hwblk_id = HWBLK_CEU0,
+        },
 };
 
 /* CEU1 */
@@ -244,6 +250,9 @@ static struct platform_device ceu1_device = {
         .dev    = {
                 .platform_data  = &sh_mobile_ceu1_info,
         },
+        .archdata = {
+                .hwblk_id = HWBLK_CEU1,
+        },
 };
 
 /* KEYSC in SoC (Needs SW33-2 set to ON) */
@@ -282,6 +291,9 @@ static struct platform_device keysc_device = {
         .dev    = {
                 .platform_data  = &keysc_info,
         },
+        .archdata = {
+                .hwblk_id = HWBLK_KEYSC,
+        },
 };
 
 /* SH Eth */
@@ -310,6 +322,9 @@ static struct platform_device sh_eth_device = {
         },
         .num_resources = ARRAY_SIZE(sh_eth_resources),
         .resource = sh_eth_resources,
+        .archdata = {
+                .hwblk_id = HWBLK_ETHER,
+        },
 };
 
 static struct r8a66597_platdata sh7724_usb0_host_data = {
@@ -319,7 +334,7 @@ static struct r8a66597_platdata sh7724_usb0_host_data = {
 static struct resource sh7724_usb0_host_resources[] = {
         [0] = {
                 .start  = 0xa4d80000,
-                .end    = 0xa4d800ff,
+                .end    = 0xa4d80124 - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -339,6 +354,38 @@ static struct platform_device sh7724_usb0_host_device = {
         },
         .num_resources  = ARRAY_SIZE(sh7724_usb0_host_resources),
         .resource       = sh7724_usb0_host_resources,
+        .archdata = {
+                .hwblk_id = HWBLK_USB0,
+        },
+};
+
+static struct r8a66597_platdata sh7724_usb1_gadget_data = {
+        .on_chip = 1,
+};
+
+static struct resource sh7724_usb1_gadget_resources[] = {
+        [0] = {
+                .start  = 0xa4d90000,
+                .end    = 0xa4d90123,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 66,
+                .end    = 66,
+                .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
+        },
+};
+
+static struct platform_device sh7724_usb1_gadget_device = {
+        .name           = "r8a66597_udc",
+        .id             = 1, /* USB1 */
+        .dev = {
+                .dma_mask               = NULL,         /*  not use dma */
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &sh7724_usb1_gadget_data,
+        },
+        .num_resources  = ARRAY_SIZE(sh7724_usb1_gadget_resources),
+        .resource       = sh7724_usb1_gadget_resources,
 };
 
 static struct platform_device *ms7724se_devices[] __initdata = {
@@ -351,6 +398,7 @@ static struct platform_device *ms7724se_devices[] __initdata = {
         &keysc_device,
         &sh_eth_device,
         &sh7724_usb0_host_device,
+        &sh7724_usb1_gadget_device,
 };
 
 #define EEPROM_OP   0xBA206000
@@ -459,6 +507,9 @@ static int __init devices_setup(void)
         /* enable USB0 port */
         ctrl_outw(0x0600, 0xa40501d4);
 
+        /* enable USB1 port */
+        ctrl_outw(0x0600, 0xa4050192);
+
         /* enable IRQ 0,1,2 */
         gpio_request(GPIO_FN_INTC_IRQ0, NULL);
         gpio_request(GPIO_FN_INTC_IRQ1, NULL);
diff --git a/arch/sh/boot/compressed/head_32.S b/arch/sh/boot/compressed/head_32.S
index 06ac31f3be88..02a30935f0b9 100644
--- a/arch/sh/boot/compressed/head_32.S
+++ b/arch/sh/boot/compressed/head_32.S
@@ -22,7 +22,7 @@ startup:
         bt      clear_bss
         sub     r0, r2
         mov.l   bss_start_addr, r0
-        mov     #0xe0, r1
+        mov     #0xffffffe0, r1
         and     r1, r0                  ! align cache line
         mov.l   text_start_addr, r3
         mov     r0, r1
diff --git a/arch/sh/configs/ecovec24_defconfig b/arch/sh/configs/ecovec24_defconfig
new file mode 100644
index 000000000000..2050a76683c3
--- /dev/null
+++ b/arch/sh/configs/ecovec24_defconfig
@@ -0,0 +1,1558 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.31-rc7
+# Wed Aug 26 09:09:07 2009
+#
+CONFIG_SUPERH=y
+CONFIG_SUPERH32=y
+# CONFIG_SUPERH64 is not set
+CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_IRQ_PER_CPU=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_SYS_SUPPORTS_CMT=y
+CONFIG_SYS_SUPPORTS_TMU=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_NO_VIRT_TO_BUS=y
+CONFIG_ARCH_HAS_DEFAULT_IDLE=y
+CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_BZIP2 is not set
+# CONFIG_KERNEL_LZMA is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+# CONFIG_KALLSYMS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_HAVE_PERF_COUNTERS=y
+
+#
+# Performance Counters
+#
+# CONFIG_PERF_COUNTERS is not set
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_COMPAT_BRK=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_IOREMAP_PROT=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# System type
+#
+CONFIG_CPU_SH4=y
+CONFIG_CPU_SH4A=y
+CONFIG_CPU_SHX2=y
+CONFIG_ARCH_SHMOBILE=y
+# CONFIG_CPU_SUBTYPE_SH7619 is not set
+# CONFIG_CPU_SUBTYPE_SH7201 is not set
+# CONFIG_CPU_SUBTYPE_SH7203 is not set
+# CONFIG_CPU_SUBTYPE_SH7206 is not set
+# CONFIG_CPU_SUBTYPE_SH7263 is not set
+# CONFIG_CPU_SUBTYPE_MXG is not set
+# CONFIG_CPU_SUBTYPE_SH7705 is not set
+# CONFIG_CPU_SUBTYPE_SH7706 is not set
+# CONFIG_CPU_SUBTYPE_SH7707 is not set
+# CONFIG_CPU_SUBTYPE_SH7708 is not set
+# CONFIG_CPU_SUBTYPE_SH7709 is not set
+# CONFIG_CPU_SUBTYPE_SH7710 is not set
+# CONFIG_CPU_SUBTYPE_SH7712 is not set
+# CONFIG_CPU_SUBTYPE_SH7720 is not set
+# CONFIG_CPU_SUBTYPE_SH7721 is not set
+# CONFIG_CPU_SUBTYPE_SH7750 is not set
+# CONFIG_CPU_SUBTYPE_SH7091 is not set
+# CONFIG_CPU_SUBTYPE_SH7750R is not set
+# CONFIG_CPU_SUBTYPE_SH7750S is not set
+# CONFIG_CPU_SUBTYPE_SH7751 is not set
+# CONFIG_CPU_SUBTYPE_SH7751R is not set
+# CONFIG_CPU_SUBTYPE_SH7760 is not set
+# CONFIG_CPU_SUBTYPE_SH4_202 is not set
+# CONFIG_CPU_SUBTYPE_SH7723 is not set
+CONFIG_CPU_SUBTYPE_SH7724=y
+# CONFIG_CPU_SUBTYPE_SH7757 is not set
+# CONFIG_CPU_SUBTYPE_SH7763 is not set
+# CONFIG_CPU_SUBTYPE_SH7770 is not set
+# CONFIG_CPU_SUBTYPE_SH7780 is not set
+# CONFIG_CPU_SUBTYPE_SH7785 is not set
+# CONFIG_CPU_SUBTYPE_SH7786 is not set
+# CONFIG_CPU_SUBTYPE_SHX3 is not set
+# CONFIG_CPU_SUBTYPE_SH7343 is not set
+# CONFIG_CPU_SUBTYPE_SH7722 is not set
+# CONFIG_CPU_SUBTYPE_SH7366 is not set
+
+#
+# Memory management options
+#
+CONFIG_QUICKLIST=y
+CONFIG_MMU=y
+CONFIG_PAGE_OFFSET=0x80000000
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_MEMORY_START=0x08000000
+CONFIG_MEMORY_SIZE=0x08000000
+CONFIG_29BIT=y
+# CONFIG_X2TLB is not set
+CONFIG_VSYSCALL=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+CONFIG_MAX_ACTIVE_REGIONS=1
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_SPARSEMEM_STATIC=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_NR_QUICK=2
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+
+#
+# Cache configuration
+#
+CONFIG_CACHE_WRITEBACK=y
+# CONFIG_CACHE_WRITETHROUGH is not set
+# CONFIG_CACHE_OFF is not set
+
+#
+# Processor features
+#
+CONFIG_CPU_LITTLE_ENDIAN=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_SH_FPU=y
+# CONFIG_SH_STORE_QUEUES is not set
+CONFIG_CPU_HAS_INTEVT=y
+CONFIG_CPU_HAS_SR_RB=y
+CONFIG_CPU_HAS_FPU=y
+
+#
+# Board support
+#
+# CONFIG_SH_7724_SOLUTION_ENGINE is not set
+# CONFIG_SH_KFR2R09 is not set
+CONFIG_SH_ECOVEC=y
+
+#
+# Timer and clock configuration
+#
+CONFIG_SH_TIMER_TMU=y
+# CONFIG_SH_TIMER_CMT is not set
+CONFIG_SH_PCLK_FREQ=33333333
+CONFIG_SH_CLK_CPG=y
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+
+#
+# DMA support
+#
+# CONFIG_SH_DMA is not set
+
+#
+# Companion Chips
+#
+
+#
+# Additional SuperH Device Drivers
+#
+CONFIG_HEARTBEAT=y
+# CONFIG_PUSH_SWITCH is not set
+
+#
+# Kernel features
+#
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
+# CONFIG_KEXEC is not set
+# CONFIG_CRASH_DUMP is not set
+CONFIG_SECCOMP=y
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_GUSA=y
+# CONFIG_SPARSE_IRQ is not set
+
+#
+# Boot options
+#
+CONFIG_ZERO_PAGE_OFFSET=0x00001000
+CONFIG_BOOT_LINK_OFFSET=0x00800000
+CONFIG_ENTRY_OFFSET=0x00001000
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="console=tty0, console=ttySC0,115200 root=/dev/nfs ip=dhcp mem=120M memchunk.vpu=4m"
+
+#
+# Bus options
+#
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options (EXPERIMENTAL)
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_HIBERNATION is not set
+CONFIG_PM_RUNTIME=y
+# CONFIG_CPU_IDLE is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_MULTIPLE_TABLES is not set
+# CONFIG_IP_ROUTE_MULTIPATH is not set
+# CONFIG_IP_ROUTE_VERBOSE is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+CONFIG_MAC80211_DEFAULT_PS_VALUE=0
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=4
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+CONFIG_SMSC_PHY=y
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+CONFIG_MDIO_BITBANG=y
+# CONFIG_MDIO_GPIO is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_STNIC is not set
+CONFIG_SH_ETH=y
+# CONFIG_SMC91X is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+CONFIG_KEYBOARD_SH_KEYSC=y
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=6
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE is not set
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_SH_MOBILE=y
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_GPIO is not set
+# CONFIG_SPI_SH_SCI is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_REGULATOR is not set
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+CONFIG_VIDEO_ALLOW_V4L1=y
+CONFIG_VIDEO_V4L1_COMPAT=y
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=y
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=y
+CONFIG_MEDIA_TUNER_TDA8290=y
+CONFIG_MEDIA_TUNER_TDA9887=y
+CONFIG_MEDIA_TUNER_TEA5761=y
+CONFIG_MEDIA_TUNER_TEA5767=y
+CONFIG_MEDIA_TUNER_MT20XX=y
+CONFIG_MEDIA_TUNER_XC2028=y
+CONFIG_MEDIA_TUNER_XC5000=y
+CONFIG_MEDIA_TUNER_MC44S803=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEO_V4L1=y
+CONFIG_VIDEOBUF_GEN=y
+CONFIG_VIDEOBUF_DMA_CONTIG=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_CPIA is not set
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+CONFIG_SOC_CAMERA=y
+# CONFIG_SOC_CAMERA_MT9M001 is not set
+# CONFIG_SOC_CAMERA_MT9M111 is not set
+# CONFIG_SOC_CAMERA_MT9T031 is not set
+# CONFIG_SOC_CAMERA_MT9V022 is not set
+# CONFIG_SOC_CAMERA_TW9910 is not set
+# CONFIG_SOC_CAMERA_PLATFORM is not set
+# CONFIG_SOC_CAMERA_OV772X is not set
+CONFIG_VIDEO_SH_MOBILE_CEU=y
+# CONFIG_V4L_USB_DRIVERS is not set
+CONFIG_RADIO_ADAPTERS=y
+# CONFIG_USB_DSBR is not set
+# CONFIG_USB_SI470X is not set
+# CONFIG_USB_MR800 is not set
+# CONFIG_RADIO_TEA5764 is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+# CONFIG_FB_CFB_FILLRECT is not set
+# CONFIG_FB_CFB_COPYAREA is not set
+# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_SH_MOBILE_LCDC=y
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+# CONFIG_LOGO_LINUX_CLUT224 is not set
+# CONFIG_LOGO_SUPERH_MONO is not set
+# CONFIG_LOGO_SUPERH_VGA16 is not set
+CONFIG_LOGO_SUPERH_CLUT224=y
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+CONFIG_USB_R8A66597_HCD=y
+# CONFIG_USB_HWA_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_SPI=y
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+CONFIG_RTC_DRV_PCF8563=y
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_SH is not set
+# CONFIG_RTC_DRV_GENERIC is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+CONFIG_UIO=y
+# CONFIG_UIO_PDRV is not set
+CONFIG_UIO_PDRV_GENIRQ=y
+# CONFIG_UIO_SMX is not set
+# CONFIG_UIO_SERCOS3 is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLBFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_UBIFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+# CONFIG_NFSD_V4 is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+CONFIG_NLS_CODEPAGE_932=y
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FTRACE_SYSCALLS=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_SH_STANDARD_BIOS is not set
+# CONFIG_EARLY_SCIF_CONSOLE is not set
+# CONFIG_DWARF_UNWINDER is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+CONFIG_CRC7=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
+CONFIG_NLATTR=y
+CONFIG_GENERIC_ATOMIC64=y
diff --git a/arch/sh/configs/kfr2r09-romimage_defconfig b/arch/sh/configs/kfr2r09-romimage_defconfig
new file mode 100644
index 000000000000..c0f9263e1387
--- /dev/null
+++ b/arch/sh/configs/kfr2r09-romimage_defconfig
@@ -0,0 +1,774 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.31-rc6
+# Thu Aug 20 15:09:16 2009
+#
+CONFIG_SUPERH=y
+CONFIG_SUPERH32=y
+# CONFIG_SUPERH64 is not set
+CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_IRQ_PER_CPU=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_SYS_SUPPORTS_CMT=y
+CONFIG_SYS_SUPPORTS_TMU=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_NO_VIRT_TO_BUS=y
+CONFIG_ARCH_HAS_DEFAULT_IDLE=y
+CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_BZIP2 is not set
+# CONFIG_KERNEL_LZMA is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INITRAMFS_ROOT_UID=0
+CONFIG_INITRAMFS_ROOT_GID=0
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_INITRAMFS_COMPRESSION_NONE is not set
+CONFIG_INITRAMFS_COMPRESSION_GZIP=y
+# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set
+# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+# CONFIG_KALLSYMS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_HAVE_PERF_COUNTERS=y
+
+#
+# Performance Counters
+#
+# CONFIG_PERF_COUNTERS is not set
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_COMPAT_BRK=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_IOREMAP_PROT=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+# CONFIG_MODULES is not set
+# CONFIG_BLOCK is not set
+# CONFIG_FREEZER is not set
+
+#
+# System type
+#
+CONFIG_CPU_SH4=y
+CONFIG_CPU_SH4A=y
+CONFIG_CPU_SHX2=y
+CONFIG_ARCH_SHMOBILE=y
+# CONFIG_CPU_SUBTYPE_SH7619 is not set
+# CONFIG_CPU_SUBTYPE_SH7201 is not set
+# CONFIG_CPU_SUBTYPE_SH7203 is not set
+# CONFIG_CPU_SUBTYPE_SH7206 is not set
+# CONFIG_CPU_SUBTYPE_SH7263 is not set
+# CONFIG_CPU_SUBTYPE_MXG is not set
+# CONFIG_CPU_SUBTYPE_SH7705 is not set
+# CONFIG_CPU_SUBTYPE_SH7706 is not set
+# CONFIG_CPU_SUBTYPE_SH7707 is not set
+# CONFIG_CPU_SUBTYPE_SH7708 is not set
+# CONFIG_CPU_SUBTYPE_SH7709 is not set
+# CONFIG_CPU_SUBTYPE_SH7710 is not set
+# CONFIG_CPU_SUBTYPE_SH7712 is not set
+# CONFIG_CPU_SUBTYPE_SH7720 is not set
+# CONFIG_CPU_SUBTYPE_SH7721 is not set
+# CONFIG_CPU_SUBTYPE_SH7750 is not set
+# CONFIG_CPU_SUBTYPE_SH7091 is not set
+# CONFIG_CPU_SUBTYPE_SH7750R is not set
+# CONFIG_CPU_SUBTYPE_SH7750S is not set
+# CONFIG_CPU_SUBTYPE_SH7751 is not set
+# CONFIG_CPU_SUBTYPE_SH7751R is not set
+# CONFIG_CPU_SUBTYPE_SH7760 is not set
+# CONFIG_CPU_SUBTYPE_SH4_202 is not set
+# CONFIG_CPU_SUBTYPE_SH7723 is not set
+CONFIG_CPU_SUBTYPE_SH7724=y
+# CONFIG_CPU_SUBTYPE_SH7763 is not set
+# CONFIG_CPU_SUBTYPE_SH7770 is not set
+# CONFIG_CPU_SUBTYPE_SH7780 is not set
+# CONFIG_CPU_SUBTYPE_SH7785 is not set
+# CONFIG_CPU_SUBTYPE_SH7786 is not set
+# CONFIG_CPU_SUBTYPE_SHX3 is not set
+# CONFIG_CPU_SUBTYPE_SH7343 is not set
+# CONFIG_CPU_SUBTYPE_SH7722 is not set
+# CONFIG_CPU_SUBTYPE_SH7366 is not set
+
+#
+# Memory management options
+#
+CONFIG_QUICKLIST=y
+CONFIG_MMU=y
+CONFIG_PAGE_OFFSET=0x80000000
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_MEMORY_START=0x08000000
+CONFIG_MEMORY_SIZE=0x08000000
+CONFIG_29BIT=y
+# CONFIG_X2TLB is not set
+CONFIG_VSYSCALL=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+CONFIG_MAX_ACTIVE_REGIONS=1
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_SPARSEMEM_STATIC=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_NR_QUICK=2
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+
+#
+# Cache configuration
+#
+CONFIG_CACHE_WRITEBACK=y
+# CONFIG_CACHE_WRITETHROUGH is not set
+# CONFIG_CACHE_OFF is not set
+
+#
+# Processor features
+#
+CONFIG_CPU_LITTLE_ENDIAN=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_SH_FPU=y
+# CONFIG_SH_STORE_QUEUES is not set
+CONFIG_CPU_HAS_INTEVT=y
+CONFIG_CPU_HAS_SR_RB=y
+CONFIG_CPU_HAS_FPU=y
+
+#
+# Board support
+#
+# CONFIG_SH_7724_SOLUTION_ENGINE is not set
+CONFIG_SH_KFR2R09=y
+# CONFIG_SH_ECOVEC is not set
+
+#
+# Timer and clock configuration
+#
+# CONFIG_SH_TIMER_TMU is not set
+CONFIG_SH_TIMER_CMT=y
+CONFIG_SH_PCLK_FREQ=33333333
+CONFIG_SH_CLK_CPG=y
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+
+#
+# DMA support
+#
+# CONFIG_SH_DMA is not set
+
+#
+# Companion Chips
+#
+
+#
+# Additional SuperH Device Drivers
+#
+# CONFIG_HEARTBEAT is not set
+# CONFIG_PUSH_SWITCH is not set
+
+#
+# Kernel features
+#
+CONFIG_HZ_100=y
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=100
+# CONFIG_SCHED_HRTICK is not set
+CONFIG_KEXEC=y
+# CONFIG_CRASH_DUMP is not set
+# CONFIG_SECCOMP is not set
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_GUSA=y
+# CONFIG_SPARSE_IRQ is not set
+
+#
+# Boot options
+#
+CONFIG_ZERO_PAGE_OFFSET=0x00001000
+CONFIG_BOOT_LINK_OFFSET=0x00800000
+CONFIG_ENTRY_OFFSET=0x00001000
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="console=ttySC1,115200 quiet"
+
+#
+# Bus options
+#
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options (EXPERIMENTAL)
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+# CONFIG_SUSPEND is not set
+# CONFIG_CPU_IDLE is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+
+#
+# SCSI device support
+#
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_NETDEVICES is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=6
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_R3964 is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_CHARDEV is not set
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE is not set
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_SH_MOBILE=y
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+CONFIG_USB_GADGET_R8A66597=y
+CONFIG_USB_R8A66597=y
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+CONFIG_USB_CDC_COMPOSITE=y
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_FILE_LOCKING=y
+# CONFIG_FSNOTIFY is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLBFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+# CONFIG_MISC_FILESYSTEMS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FTRACE_SYSCALLS=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_SH_STANDARD_BIOS is not set
+# CONFIG_EARLY_SCIF_CONSOLE is not set
+# CONFIG_DWARF_UNWINDER is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+# CONFIG_CRC32 is not set
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
+CONFIG_NLATTR=y
+CONFIG_GENERIC_ATOMIC64=y
diff --git a/arch/sh/configs/kfr2r09_defconfig b/arch/sh/configs/kfr2r09_defconfig
index 90e575c34d58..cef61319d2f4 100644
--- a/arch/sh/configs/kfr2r09_defconfig
+++ b/arch/sh/configs/kfr2r09_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.31-rc3
-# Thu Jul 23 17:45:09 2009
+# Linux kernel version: 2.6.31-rc6
+# Thu Aug 20 21:58:52 2009
 #
 CONFIG_SUPERH=y
 CONFIG_SUPERH32=y
@@ -38,6 +38,7 @@ CONFIG_CONSTRUCTORS=y
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
 CONFIG_LOCALVERSION=""
 # CONFIG_LOCALVERSION_AUTO is not set
@@ -132,7 +133,12 @@ CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 CONFIG_BASE_SMALL=0
-# CONFIG_MODULES is not set
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_BLOCK=y
 CONFIG_LBDAF=y
 # CONFIG_BLK_DEV_BSG is not set
@@ -255,6 +261,7 @@ CONFIG_CPU_HAS_FPU=y
 #
 # CONFIG_SH_7724_SOLUTION_ENGINE is not set
 CONFIG_SH_KFR2R09=y
+# CONFIG_SH_ECOVEC is not set
 
 #
 # Timer and clock configuration
@@ -301,8 +308,8 @@ CONFIG_KEXEC=y
 # CONFIG_CRASH_DUMP is not set
 # CONFIG_SECCOMP is not set
 # CONFIG_PREEMPT_NONE is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-# CONFIG_PREEMPT is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
 CONFIG_GUSA=y
 # CONFIG_SPARSE_IRQ is not set
 
@@ -313,7 +320,7 @@ CONFIG_ZERO_PAGE_OFFSET=0x00001000
 CONFIG_BOOT_LINK_OFFSET=0x00800000
 CONFIG_ENTRY_OFFSET=0x00001000
 CONFIG_CMDLINE_BOOL=y
-CONFIG_CMDLINE="console=ttySC1,115200"
+CONFIG_CMDLINE="console=tty0 console=ttySC1,115200"
 
 #
 # Bus options
@@ -427,6 +434,7 @@ CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 CONFIG_MTD_CONCAT=y
 CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_REDBOOT_PARTS is not set
 CONFIG_MTD_CMDLINE_PARTS=y
 # CONFIG_MTD_AR7_PARTS is not set
@@ -639,6 +647,7 @@ CONFIG_I2C_SH_MOBILE=y
 # Other I2C/SMBus bus drivers
 #
 # CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
 
 #
 # Miscellaneous I2C Chip support
@@ -715,7 +724,35 @@ CONFIG_SSB_POSSIBLE=y
 #
 # CONFIG_VGASTATE is not set
 # CONFIG_VIDEO_OUTPUT_CONTROL is not set
-# CONFIG_FB is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+# CONFIG_FB_CFB_FILLRECT is not set
+# CONFIG_FB_CFB_COPYAREA is not set
+# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_SH_MOBILE_LCDC=y
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
@@ -727,15 +764,157 @@ CONFIG_SSB_POSSIBLE=y
 # Console display driver support
 #
 CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FONTS=y
+# CONFIG_FONT_8x8 is not set
+# CONFIG_FONT_8x16 is not set
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+CONFIG_FONT_MINI_4x6=y
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+# CONFIG_LOGO_LINUX_CLUT224 is not set
+# CONFIG_LOGO_SUPERH_MONO is not set
+CONFIG_LOGO_SUPERH_VGA16=y
+# CONFIG_LOGO_SUPERH_CLUT224 is not set
 # CONFIG_SOUND is not set
 # CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_MMC is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+CONFIG_USB_GADGET_R8A66597=y
+CONFIG_USB_R8A66597=y
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+CONFIG_USB_CDC_COMPOSITE=y
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
 # CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
 # CONFIG_ACCESSIBILITY is not set
 CONFIG_RTC_LIB=y
-# CONFIG_RTC_CLASS is not set
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_SH=y
+# CONFIG_RTC_DRV_GENERIC is not set
 # CONFIG_DMADEVICES is not set
 # CONFIG_AUXDISPLAY is not set
 CONFIG_UIO=y
@@ -763,8 +942,10 @@ CONFIG_UIO_PDRV_GENIRQ=y
 # CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
 CONFIG_FILE_LOCKING=y
-# CONFIG_FSNOTIFY is not set
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
 # CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
@@ -829,7 +1010,7 @@ CONFIG_DEBUG_FS=y
 # CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_LATENCYTOP is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
 CONFIG_HAVE_FUNCTION_TRACER=y
 CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
 CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
@@ -844,6 +1025,7 @@ CONFIG_TRACING_SUPPORT=y
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_SH_STANDARD_BIOS is not set
 # CONFIG_EARLY_SCIF_CONSOLE is not set
+# CONFIG_DWARF_UNWINDER is not set
 
 #
 # Security options
@@ -862,10 +1044,10 @@ CONFIG_BITREVERSE=y
 CONFIG_GENERIC_FIND_LAST_BIT=y
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
-CONFIG_CRC_T10DIF=y
-CONFIG_CRC_ITU_T=y
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
-CONFIG_CRC7=y
+# CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_DECOMPRESS_GZIP=y
diff --git a/arch/sh/configs/snapgear_defconfig b/arch/sh/configs/snapgear_defconfig
index ca3c88a88021..2be2d75adbb7 100644
--- a/arch/sh/configs/snapgear_defconfig
+++ b/arch/sh/configs/snapgear_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.30
-# Thu Jun 18 13:11:58 2009
+# Linux kernel version: 2.6.31-rc6
+# Thu Aug 20 15:03:04 2009
 #
 CONFIG_SUPERH=y
 CONFIG_SUPERH32=y
@@ -14,6 +14,7 @@ CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_IRQ_PER_CPU=y
 # CONFIG_GENERIC_GPIO is not set
 CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
@@ -28,7 +29,9 @@ CONFIG_HAVE_LATENCYTOP_SUPPORT=y
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_ARCH_NO_VIRT_TO_BUS=y
 CONFIG_ARCH_HAS_DEFAULT_IDLE=y
+CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
 # General setup
@@ -38,6 +41,12 @@ CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_BZIP2 is not set
+# CONFIG_KERNEL_LZMA is not set
 # CONFIG_SWAP is not set
 # CONFIG_SYSVIPC is not set
 # CONFIG_POSIX_MQUEUE is not set
@@ -86,10 +95,12 @@ CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_AIO=y
+CONFIG_HAVE_PERF_COUNTERS=y
 
 #
 # Performance Counters
 #
+# CONFIG_PERF_COUNTERS is not set
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_PCI_QUIRKS=y
 # CONFIG_STRIP_ASM_SYMS is not set
@@ -106,6 +117,10 @@ CONFIG_HAVE_KRETPROBES=y
 CONFIG_HAVE_ARCH_TRACEHOOK=y
 CONFIG_HAVE_CLK=y
 CONFIG_HAVE_DMA_API_DEBUG=y
+
+#
+# GCOV-based kernel profiling
+#
 # CONFIG_SLOW_WORK is not set
 CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 CONFIG_SLABINFO=y
@@ -113,7 +128,7 @@ CONFIG_RT_MUTEXES=y
 CONFIG_BASE_SMALL=0
 # CONFIG_MODULES is not set
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
+CONFIG_LBDAF=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
 
@@ -534,7 +549,11 @@ CONFIG_HAVE_IDE=y
 #
 
 #
-# Enable only one of the two stacks, unless you know what you are doing
+# You can enable one or both FireWire driver stacks.
+#
+
+#
+# See the help texts for more information.
 #
 # CONFIG_FIREWIRE is not set
 # CONFIG_IEEE1394 is not set
@@ -686,6 +705,11 @@ CONFIG_LEGACY_PTY_COUNT=256
 CONFIG_DEVPORT=y
 # CONFIG_I2C is not set
 # CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
@@ -732,7 +756,44 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_INFINIBAND is not set
 CONFIG_RTC_LIB=y
-# CONFIG_RTC_CLASS is not set
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_DS1286 is not set
+CONFIG_RTC_DRV_DS1302=y
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_SH is not set
+# CONFIG_RTC_DRV_GENERIC is not set
 # CONFIG_DMADEVICES is not set
 # CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
@@ -754,6 +815,7 @@ CONFIG_EXT2_FS=y
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
 CONFIG_FILE_LOCKING=y
@@ -856,8 +918,11 @@ CONFIG_FRAME_WARN=1024
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_LATENCYTOP is not set
 CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
 CONFIG_HAVE_DYNAMIC_FTRACE=y
 CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FTRACE_SYSCALLS=y
 CONFIG_TRACING_SUPPORT=y
 # CONFIG_FTRACE is not set
 # CONFIG_DMA_API_DEBUG is not set
@@ -865,6 +930,7 @@ CONFIG_TRACING_SUPPORT=y
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_SH_STANDARD_BIOS is not set
 # CONFIG_EARLY_SCIF_CONSOLE is not set
+# CONFIG_DWARF_UNWINDER is not set
 
 #
 # Security options
@@ -893,5 +959,6 @@ CONFIG_DECOMPRESS_GZIP=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
 CONFIG_NLATTR=y
 CONFIG_GENERIC_ATOMIC64=y
diff --git a/arch/sh/drivers/dma/Kconfig b/arch/sh/drivers/dma/Kconfig
index 63e9dd30b41c..b91fa8dbf047 100644
--- a/arch/sh/drivers/dma/Kconfig
+++ b/arch/sh/drivers/dma/Kconfig
@@ -27,12 +27,12 @@ config NR_ONCHIP_DMA_CHANNELS
         default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R || \
                        CPU_SUBTYPE_SH7760
         default "12" if CPU_SUBTYPE_SH7723 || CPU_SUBTYPE_SH7780  || \
-                        CPU_SUBTYPE_SH7785
+                        CPU_SUBTYPE_SH7785 || CPU_SUBTYPE_SH7724
         default "6"
         help
           This allows you to specify the number of channels that the on-chip
-          DMAC supports. This will be 4 for SH7091/SH7750/SH7751 and 8 for the
-          SH7750R/SH7751R.
+          DMAC supports. This will be 4 for SH7750/SH7751/Sh7750S/SH7091 and 8 for the
+          SH7750R/SH7751R/SH7760, 12 for the SH7723/SH7780/SH7785/SH7724, default is 6.
 
 config NR_DMA_CHANNELS_BOOL
         depends on SH_DMA
diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c
index 9a1c423ad167..c481df639022 100644
--- a/arch/sh/drivers/pci/pci.c
+++ b/arch/sh/drivers/pci/pci.c
@@ -295,6 +295,8 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
                                vma->vm_page_prot);
 }
 
+#ifndef CONFIG_GENERIC_IOMAP
+
 static void __iomem *ioport_map_pci(struct pci_dev *dev,
                                     unsigned long port, unsigned int nr)
 {
@@ -346,6 +348,8 @@ void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
 }
 EXPORT_SYMBOL(pci_iounmap);
 
+#endif /* CONFIG_GENERIC_IOMAP */
+
 #ifdef CONFIG_HOTPLUG
 EXPORT_SYMBOL(pcibios_resource_to_bus);
 EXPORT_SYMBOL(pcibios_bus_to_resource);
diff --git a/arch/sh/include/asm/Kbuild b/arch/sh/include/asm/Kbuild
index 43910cdf78a5..e121c30f797d 100644
--- a/arch/sh/include/asm/Kbuild
+++ b/arch/sh/include/asm/Kbuild
@@ -1,6 +1,6 @@
 include include/asm-generic/Kbuild.asm
 
-header-y += cpu-features.h
+header-y += cachectl.h cpu-features.h
 
 unifdef-y += unistd_32.h
 unifdef-y += unistd_64.h
diff --git a/arch/sh/include/asm/bug.h b/arch/sh/include/asm/bug.h
index c01718040166..d02c01b3e6b9 100644
--- a/arch/sh/include/asm/bug.h
+++ b/arch/sh/include/asm/bug.h
@@ -2,6 +2,7 @@
 #define __ASM_SH_BUG_H
 
 #define TRAPA_BUG_OPCODE        0xc33e  /* trapa #0x3e */
+#define BUGFLAG_UNWINDER        (1 << 1)
 
 #ifdef CONFIG_GENERIC_BUG
 #define HAVE_ARCH_BUG
@@ -72,6 +73,36 @@ do {							\
         unlikely(__ret_warn_on);                                \
 })
 
+#define UNWINDER_BUG()                                  \
+do {                                                    \
+        __asm__ __volatile__ (                          \
+                "1:\t.short %O0\n"                      \
+                _EMIT_BUG_ENTRY                         \
+                 :                                      \
+                 : "n" (TRAPA_BUG_OPCODE),              \
+                   "i" (__FILE__),                      \
+                   "i" (__LINE__),                      \
+                   "i" (BUGFLAG_UNWINDER),              \
+                   "i" (sizeof(struct bug_entry)));     \
+} while (0)
+
+#define UNWINDER_BUG_ON(x) ({                                   \
+        int __ret_unwinder_on = !!(x);                          \
+        if (__builtin_constant_p(__ret_unwinder_on)) {          \
+                if (__ret_unwinder_on)                          \
+                        UNWINDER_BUG();                         \
+        } else {                                                \
+                if (unlikely(__ret_unwinder_on))                \
+                        UNWINDER_BUG();                         \
+        }                                                       \
+        unlikely(__ret_unwinder_on);                            \
+})
+
+#else
+
+#define UNWINDER_BUG    BUG
+#define UNWINDER_BUG_ON BUG_ON
+
 #endif /* CONFIG_GENERIC_BUG */
 
 #include <asm-generic/bug.h>
diff --git a/arch/sh/include/asm/cachectl.h b/arch/sh/include/asm/cachectl.h
new file mode 100644
index 000000000000..6ffb4b7a212e
--- /dev/null
+++ b/arch/sh/include/asm/cachectl.h
@@ -0,0 +1,19 @@
+#ifndef _SH_CACHECTL_H
+#define _SH_CACHECTL_H
+
+/* Definitions for the cacheflush system call.  */
+
+#define CACHEFLUSH_D_INVAL      0x1     /* invalidate (without write back) */
+#define CACHEFLUSH_D_WB         0x2     /* write back (without invalidate) */
+#define CACHEFLUSH_D_PURGE      0x3     /* writeback and invalidate */
+
+#define CACHEFLUSH_I            0x4
+
+/*
+ * Options for cacheflush system call
+ */
+#define ICACHE  CACHEFLUSH_I            /* flush instruction cache */
+#define DCACHE  CACHEFLUSH_D_PURGE      /* writeback and flush data cache */
+#define BCACHE  (ICACHE|DCACHE)         /* flush both caches */
+
+#endif /* _SH_CACHECTL_H */
diff --git a/arch/sh/include/asm/device.h b/arch/sh/include/asm/device.h
index 8688a88303ee..b16debfe8c1e 100644
--- a/arch/sh/include/asm/device.h
+++ b/arch/sh/include/asm/device.h
@@ -3,7 +3,9 @@
  *
  * This file is released under the GPLv2
  */
-#include <asm-generic/device.h>
+
+struct dev_archdata {
+};
 
 struct platform_device;
 /* allocate contiguous memory chunk and fill in struct resource */
@@ -12,3 +14,15 @@ int platform_resource_setup_memory(struct platform_device *pdev,
 
 void plat_early_device_setup(void);
 
+#define PDEV_ARCHDATA_FLAG_INIT 0
+#define PDEV_ARCHDATA_FLAG_IDLE 1
+#define PDEV_ARCHDATA_FLAG_SUSP 2
+
+struct pdev_archdata {
+        int hwblk_id;
+#ifdef CONFIG_PM_RUNTIME
+        unsigned long flags;
+        struct list_head entry;
+        struct mutex mutex;
+#endif
+};
diff --git a/arch/sh/include/asm/dwarf.h b/arch/sh/include/asm/dwarf.h
index d3d3837c5e1b..ced6795891a6 100644
--- a/arch/sh/include/asm/dwarf.h
+++ b/arch/sh/include/asm/dwarf.h
@@ -200,7 +200,7 @@
  */
 static __always_inline unsigned long dwarf_read_arch_reg(unsigned int reg)
 {
-        unsigned long value;
+        unsigned long value = 0;
 
         switch (reg) {
         case 14:
@@ -265,10 +265,7 @@ struct dwarf_frame {
 
         unsigned long pc;
 
-        struct dwarf_reg *regs;
-        unsigned int num_regs;  /* how many regs are allocated? */
-
-        unsigned int depth;     /* what level are we in the callstack? */
+        struct list_head reg_list;
 
         unsigned long cfa;
 
@@ -292,20 +289,15 @@ struct dwarf_frame {
  *      @flags: Describes how to calculate the value of this register
  */
 struct dwarf_reg {
+        struct list_head link;
+
+        unsigned int number;
+
         unsigned long addr;
         unsigned long flags;
 #define DWARF_REG_OFFSET        (1 << 0)
-};
-
-/**
- *      dwarf_stack - a DWARF stack contains a collection of DWARF frames
- *      @depth: the number of frames in the stack
- *      @level: an array of DWARF frames, indexed by stack level
- *
- */
-struct dwarf_stack {
-        unsigned int depth;
-        struct dwarf_frame **level;
+#define DWARF_VAL_OFFSET        (1 << 1)
+#define DWARF_UNDEFINED         (1 << 2)
 };
 
 /*
@@ -370,17 +362,16 @@ static inline unsigned int DW_CFA_operand(unsigned long insn)
 #define DW_EXT_HI       0xffffffff
 #define DW_EXT_DWARF64  DW_EXT_HI
 
-extern void dwarf_unwinder_init(void);
-
 extern struct dwarf_frame *dwarf_unwind_stack(unsigned long,
                                               struct dwarf_frame *);
-#endif /* __ASSEMBLY__ */
+#endif /* !__ASSEMBLY__ */
 
 #define CFI_STARTPROC   .cfi_startproc
 #define CFI_ENDPROC     .cfi_endproc
 #define CFI_DEF_CFA     .cfi_def_cfa
 #define CFI_REGISTER    .cfi_register
 #define CFI_REL_OFFSET  .cfi_rel_offset
+#define CFI_UNDEFINED   .cfi_undefined
 
 #else
 
@@ -394,6 +385,7 @@ extern struct dwarf_frame *dwarf_unwind_stack(unsigned long,
 #define CFI_DEF_CFA     CFI_IGNORE
 #define CFI_REGISTER    CFI_IGNORE
 #define CFI_REL_OFFSET  CFI_IGNORE
+#define CFI_UNDEFINED   CFI_IGNORE
 
 #ifndef __ASSEMBLY__
 static inline void dwarf_unwinder_init(void)
diff --git a/arch/sh/include/asm/entry-macros.S b/arch/sh/include/asm/entry-macros.S
index 64fd0de24daf..cc43a55e1fcf 100644
--- a/arch/sh/include/asm/entry-macros.S
+++ b/arch/sh/include/asm/entry-macros.S
@@ -7,7 +7,7 @@
         .endm
 
         .macro  sti
-        mov     #0xf0, r11
+        mov     #0xfffffff0, r11
         extu.b  r11, r11
         not     r11, r11
         stc     sr, r10
diff --git a/arch/sh/include/asm/ftrace.h b/arch/sh/include/asm/ftrace.h
index 7e0bcc4d4a96..12f3a31f20af 100644
--- a/arch/sh/include/asm/ftrace.h
+++ b/arch/sh/include/asm/ftrace.h
@@ -4,6 +4,7 @@
 #ifdef CONFIG_FUNCTION_TRACER
 
 #define MCOUNT_INSN_SIZE        4 /* sizeof mcount call */
+#define FTRACE_SYSCALL_MAX      NR_syscalls
 
 #ifndef __ASSEMBLY__
 extern void mcount(void);
diff --git a/arch/sh/include/asm/hwblk.h b/arch/sh/include/asm/hwblk.h
index c01d72cb6757..5d3ccae4202b 100644
--- a/arch/sh/include/asm/hwblk.h
+++ b/arch/sh/include/asm/hwblk.h
@@ -5,7 +5,9 @@
 #include <asm/io.h>
 
 #define HWBLK_CNT_USAGE 0
-#define HWBLK_CNT_NR 1
+#define HWBLK_CNT_IDLE 1
+#define HWBLK_CNT_DEVICES 2
+#define HWBLK_CNT_NR 3
 
 #define HWBLK_AREA_FLAG_PARENT (1 << 0) /* valid parent */
 
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index 25348141674b..5be45ea4dfec 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -92,8 +92,12 @@
 
 static inline void ctrl_delay(void)
 {
-#ifdef P2SEG
+#ifdef CONFIG_CPU_SH4
+        __raw_readw(CCN_PVR);
+#elif defined(P2SEG)
         __raw_readw(P2SEG);
+#else
+#error "Need a dummy address for delay"
 #endif
 }
 
@@ -146,6 +150,7 @@ __BUILD_MEMORY_STRING(q, u64)
 #define readl_relaxed(a)        readl(a)
 #define readq_relaxed(a)        readq(a)
 
+#ifndef CONFIG_GENERIC_IOMAP
 /* Simple MMIO */
 #define ioread8(a)              __raw_readb(a)
 #define ioread16(a)             __raw_readw(a)
@@ -166,6 +171,15 @@ __BUILD_MEMORY_STRING(q, u64)
 #define iowrite8_rep(a, s, c)   __raw_writesb((a), (s), (c))
 #define iowrite16_rep(a, s, c)  __raw_writesw((a), (s), (c))
 #define iowrite32_rep(a, s, c)  __raw_writesl((a), (s), (c))
+#endif
+
+#define mmio_insb(p,d,c)        __raw_readsb(p,d,c)
+#define mmio_insw(p,d,c)        __raw_readsw(p,d,c)
+#define mmio_insl(p,d,c)        __raw_readsl(p,d,c)
+
+#define mmio_outsb(p,s,c)       __raw_writesb(p,s,c)
+#define mmio_outsw(p,s,c)       __raw_writesw(p,s,c)
+#define mmio_outsl(p,s,c)       __raw_writesl(p,s,c)
 
 /* synco on SH-4A, otherwise a nop */
 #define mmiowb()                wmb()
diff --git a/arch/sh/include/asm/pgtable_32.h b/arch/sh/include/asm/pgtable_32.h
index 0db19db913c7..4c4429cda56d 100644
--- a/arch/sh/include/asm/pgtable_32.h
+++ b/arch/sh/include/asm/pgtable_32.h
@@ -87,6 +87,14 @@
 #define _PAGE_PCC_ATR8  0x60000000      /* Attribute Memory space, 8 bit bus */
 #define _PAGE_PCC_ATR16 0x60000001      /* Attribute Memory space, 6 bit bus */
 
+#ifndef CONFIG_X2TLB
+/* copy the ptea attributes */
+static inline unsigned long copy_ptea_attributes(unsigned long x)
+{
+        return  ((x >> 28) & 0xe) | (x & 0x1);
+}
+#endif
+
 /* Mask which drops unused bits from the PTEL value */
 #if defined(CONFIG_CPU_SH3)
 #define _PAGE_CLEAR_FLAGS       (_PAGE_PROTNONE | _PAGE_ACCESSED| \
diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h
index db1a4f3a755f..017e0c1807b2 100644
--- a/arch/sh/include/asm/processor.h
+++ b/arch/sh/include/asm/processor.h
@@ -32,7 +32,7 @@ enum cpu_type {
 
         /* SH-4A types */
         CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
-        CPU_SH7723, CPU_SH7724, CPU_SHX3,
+        CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SHX3,
 
         /* SH4AL-DSP types */
         CPU_SH7343, CPU_SH7722, CPU_SH7366,
diff --git a/arch/sh/include/asm/system.h b/arch/sh/include/asm/system.h
index bf7c4cbde372..6b272238a46e 100644
--- a/arch/sh/include/asm/system.h
+++ b/arch/sh/include/asm/system.h
@@ -169,6 +169,11 @@ BUILD_TRAP_HANDLER(breakpoint);
 BUILD_TRAP_HANDLER(singlestep);
 BUILD_TRAP_HANDLER(fpu_error);
 BUILD_TRAP_HANDLER(fpu_state_restore);
+BUILD_TRAP_HANDLER(unwinder);
+
+#ifdef CONFIG_BUG
+extern void handle_BUG(struct pt_regs *);
+#endif
 
 #define arch_align_stack(x) (x)
 
diff --git a/arch/sh/include/asm/system_32.h b/arch/sh/include/asm/system_32.h
index 5ddd2359f3ef..607d413f6168 100644
--- a/arch/sh/include/asm/system_32.h
+++ b/arch/sh/include/asm/system_32.h
@@ -14,12 +14,12 @@ do {									\
                         (u32 *)&tsk->thread.dsp_status;                 \
         __asm__ __volatile__ (                                          \
                 ".balign 4\n\t"                                         \
+                "movs.l @r2+, a0\n\t"                                   \
                 "movs.l @r2+, a1\n\t"                                   \
                 "movs.l @r2+, a0g\n\t"                                  \
                 "movs.l @r2+, a1g\n\t"                                  \
                 "movs.l @r2+, m0\n\t"                                   \
                 "movs.l @r2+, m1\n\t"                                   \
-                "movs.l @r2+, a0\n\t"                                   \
                 "movs.l @r2+, x0\n\t"                                   \
                 "movs.l @r2+, x1\n\t"                                   \
                 "movs.l @r2+, y0\n\t"                                   \
@@ -39,20 +39,20 @@ do {									\
                                                                         \
         __asm__ __volatile__ (                                          \
                 ".balign 4\n\t"                                         \
-                "stc.l  mod, @-r2\n\t"                          \
+                "stc.l  mod, @-r2\n\t"                                  \
                 "stc.l  re, @-r2\n\t"                                   \
                 "stc.l  rs, @-r2\n\t"                                   \
-                "sts.l  dsr, @-r2\n\t"                          \
-                "sts.l  y1, @-r2\n\t"                                   \
-                "sts.l  y0, @-r2\n\t"                                   \
-                "sts.l  x1, @-r2\n\t"                                   \
-                "sts.l  x0, @-r2\n\t"                                   \
-                "sts.l  a0, @-r2\n\t"                                   \
-                ".word  0xf653          ! movs.l        a1, @-r2\n\t"   \
-                ".word  0xf6f3          ! movs.l        a0g, @-r2\n\t"  \
-                ".word  0xf6d3          ! movs.l        a1g, @-r2\n\t"  \
-                ".word  0xf6c3          ! movs.l        m0, @-r2\n\t"   \
-                ".word  0xf6e3          ! movs.l        m1, @-r2\n\t"   \
+                "sts.l  dsr, @-r2\n\t"                                  \
+                "movs.l y1, @-r2\n\t"                                   \
+                "movs.l y0, @-r2\n\t"                                   \
+                "movs.l x1, @-r2\n\t"                                   \
+                "movs.l x0, @-r2\n\t"                                   \
+                "movs.l m1, @-r2\n\t"                                   \
+                "movs.l m0, @-r2\n\t"                                   \
+                "movs.l a1g, @-r2\n\t"                                  \
+                "movs.l a0g, @-r2\n\t"                                  \
+                "movs.l a1, @-r2\n\t"                                   \
+                "movs.l a0, @-r2\n\t"                                   \
                 : : "r" (__ts2));                                       \
 } while (0)
 
@@ -214,7 +214,7 @@ static inline reg_size_t register_align(void *val)
 }
 
 int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
-                            struct mem_access *ma);
+                            struct mem_access *ma, int);
 
 asmlinkage void do_address_error(struct pt_regs *regs,
                                  unsigned long writeaccess,
diff --git a/arch/sh/include/asm/unistd_32.h b/arch/sh/include/asm/unistd_32.h
index 61d6ad93d786..925dd40d9d55 100644
--- a/arch/sh/include/asm/unistd_32.h
+++ b/arch/sh/include/asm/unistd_32.h
@@ -132,7 +132,7 @@
 #define __NR_clone              120
 #define __NR_setdomainname      121
 #define __NR_uname              122
-#define __NR_modify_ldt         123
+#define __NR_cacheflush         123
 #define __NR_adjtimex           124
 #define __NR_mprotect           125
 #define __NR_sigprocmask        126
diff --git a/arch/sh/include/asm/unistd_64.h b/arch/sh/include/asm/unistd_64.h
index a751699afda3..2b84bc916bc5 100644
--- a/arch/sh/include/asm/unistd_64.h
+++ b/arch/sh/include/asm/unistd_64.h
@@ -137,7 +137,7 @@
 #define __NR_clone              120
 #define __NR_setdomainname      121
 #define __NR_uname              122
-#define __NR_modify_ldt         123
+#define __NR_cacheflush         123
 #define __NR_adjtimex           124
 #define __NR_mprotect           125
 #define __NR_sigprocmask        126
diff --git a/arch/sh/include/asm/unwinder.h b/arch/sh/include/asm/unwinder.h
index 3dc551453e28..1e65c07b3e18 100644
--- a/arch/sh/include/asm/unwinder.h
+++ b/arch/sh/include/asm/unwinder.h
@@ -22,4 +22,10 @@ extern void stack_reader_dump(struct task_struct *, struct pt_regs *,
                               unsigned long *, const struct stacktrace_ops *,
                               void *);
 
+/*
+ * Used by fault handling code to signal to the unwinder code that it
+ * should switch to a different unwinder.
+ */
+extern int unwinder_faulted;
+
 #endif /* _LINUX_UNWINDER_H */
diff --git a/arch/sh/include/asm/watchdog.h b/arch/sh/include/asm/watchdog.h
index f024fed00a72..2fe7cee9e43a 100644
--- a/arch/sh/include/asm/watchdog.h
+++ b/arch/sh/include/asm/watchdog.h
@@ -13,10 +13,18 @@
 #ifdef __KERNEL__
 
 #include <linux/types.h>
+#include <linux/io.h>
+
+#define WTCNT_HIGH      0x5a
+#define WTCSR_HIGH      0xa5
+
+#define WTCSR_CKS2      0x04
+#define WTCSR_CKS1      0x02
+#define WTCSR_CKS0      0x01
+
 #include <cpu/watchdog.h>
-#include <asm/io.h>
 
-/* 
+/*
  * See cpu-sh2/watchdog.h for explanation of this stupidity..
  */
 #ifndef WTCNT_R
@@ -27,13 +35,6 @@
 #  define WTCSR_R       WTCSR
 #endif
 
-#define WTCNT_HIGH      0x5a
-#define WTCSR_HIGH      0xa5
-
-#define WTCSR_CKS2      0x04
-#define WTCSR_CKS1      0x02
-#define WTCSR_CKS0      0x01
-
 /*
  * CKS0-2 supports a number of clock division ratios. At the time the watchdog
  * is enabled, it defaults to a 41 usec overflow period .. we overload this to
diff --git a/arch/sh/include/cpu-sh4/cpu/freq.h b/arch/sh/include/cpu-sh4/cpu/freq.h
index ccf1d999db6d..e1e90960ee9a 100644
--- a/arch/sh/include/cpu-sh4/cpu/freq.h
+++ b/arch/sh/include/cpu-sh4/cpu/freq.h
@@ -22,6 +22,10 @@
 #define MSTPCR0                 0xa4150030
 #define MSTPCR1                 0xa4150034
 #define MSTPCR2                 0xa4150038
+#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
+#define FRQCR                   0xffc80000
+#define OSCCR                   0xffc80018
+#define PLLCR                   0xffc80024
 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
       defined(CONFIG_CPU_SUBTYPE_SH7780)
 #define FRQCR                   0xffc80000
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7757.h b/arch/sh/include/cpu-sh4/cpu/sh7757.h
new file mode 100644
index 000000000000..f4d267efad71
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/sh7757.h
@@ -0,0 +1,243 @@
+#ifndef __ASM_SH7757_H__
+#define __ASM_SH7757_H__
+
+enum {
+        /* PTA */
+        GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4,
+        GPIO_PTA3, GPIO_PTA2, GPIO_PTA1, GPIO_PTA0,
+
+        /* PTB */
+        GPIO_PTB7, GPIO_PTB6, GPIO_PTB5, GPIO_PTB4,
+        GPIO_PTB3, GPIO_PTB2, GPIO_PTB1, GPIO_PTB0,
+
+        /* PTC */
+        GPIO_PTC7, GPIO_PTC6, GPIO_PTC5, GPIO_PTC4,
+        GPIO_PTC3, GPIO_PTC2, GPIO_PTC1, GPIO_PTC0,
+
+        /* PTD */
+        GPIO_PTD7, GPIO_PTD6, GPIO_PTD5, GPIO_PTD4,
+        GPIO_PTD3, GPIO_PTD2, GPIO_PTD1, GPIO_PTD0,
+
+        /* PTE */
+        GPIO_PTE7, GPIO_PTE6, GPIO_PTE5, GPIO_PTE4,
+        GPIO_PTE3, GPIO_PTE2, GPIO_PTE1, GPIO_PTE0,
+
+        /* PTF */
+        GPIO_PTF7, GPIO_PTF6, GPIO_PTF5, GPIO_PTF4,
+        GPIO_PTF3, GPIO_PTF2, GPIO_PTF1, GPIO_PTF0,
+
+        /* PTG */
+        GPIO_PTG7, GPIO_PTG6, GPIO_PTG5, GPIO_PTG4,
+        GPIO_PTG3, GPIO_PTG2, GPIO_PTG1, GPIO_PTG0,
+
+        /* PTH */
+        GPIO_PTH7, GPIO_PTH6, GPIO_PTH5, GPIO_PTH4,
+        GPIO_PTH3, GPIO_PTH2, GPIO_PTH1, GPIO_PTH0,
+
+        /* PTI */
+        GPIO_PTI7, GPIO_PTI6, GPIO_PTI5, GPIO_PTI4,
+        GPIO_PTI3, GPIO_PTI2, GPIO_PTI1, GPIO_PTI0,
+
+        /* PTJ */
+        GPIO_PTJ7, GPIO_PTJ6, GPIO_PTJ5, GPIO_PTJ4,
+        GPIO_PTJ3, GPIO_PTJ2, GPIO_PTJ1, GPIO_PTJ0,
+
+        /* PTK */
+        GPIO_PTK7, GPIO_PTK6, GPIO_PTK5, GPIO_PTK4,
+        GPIO_PTK3, GPIO_PTK2, GPIO_PTK1, GPIO_PTK0,
+
+        /* PTL */
+        GPIO_PTL7, GPIO_PTL6, GPIO_PTL5, GPIO_PTL4,
+        GPIO_PTL3, GPIO_PTL2, GPIO_PTL1, GPIO_PTL0,
+
+        /* PTM */
+                   GPIO_PTM6, GPIO_PTM5, GPIO_PTM4,
+        GPIO_PTM3, GPIO_PTM2, GPIO_PTM1, GPIO_PTM0,
+
+        /* PTN */
+        GPIO_PTN7, GPIO_PTN6, GPIO_PTN5, GPIO_PTN4,
+        GPIO_PTN3, GPIO_PTN2, GPIO_PTN1, GPIO_PTN0,
+
+        /* PTO */
+        GPIO_PTO7, GPIO_PTO6, GPIO_PTO5, GPIO_PTO4,
+        GPIO_PTO3, GPIO_PTO2, GPIO_PTO1, GPIO_PTO0,
+
+        /* PTP */
+                   GPIO_PTP6, GPIO_PTP5, GPIO_PTP4,
+        GPIO_PTP3, GPIO_PTP2, GPIO_PTP1, GPIO_PTP0,
+
+        /* PTQ */
+                   GPIO_PTQ6, GPIO_PTQ5, GPIO_PTQ4,
+        GPIO_PTQ3, GPIO_PTQ2, GPIO_PTQ1, GPIO_PTQ0,
+
+        /* PTR */
+        GPIO_PTR7, GPIO_PTR6, GPIO_PTR5, GPIO_PTR4,
+        GPIO_PTR3, GPIO_PTR2, GPIO_PTR1, GPIO_PTR0,
+
+        /* PTS */
+        GPIO_PTS7, GPIO_PTS6, GPIO_PTS5, GPIO_PTS4,
+        GPIO_PTS3, GPIO_PTS2, GPIO_PTS1, GPIO_PTS0,
+
+        /* PTT */
+                              GPIO_PTT5, GPIO_PTT4,
+        GPIO_PTT3, GPIO_PTT2, GPIO_PTT1, GPIO_PTT0,
+
+        /* PTU */
+        GPIO_PTU7, GPIO_PTU6, GPIO_PTU5, GPIO_PTU4,
+        GPIO_PTU3, GPIO_PTU2, GPIO_PTU1, GPIO_PTU0,
+
+        /* PTV */
+        GPIO_PTV7, GPIO_PTV6, GPIO_PTV5, GPIO_PTV4,
+        GPIO_PTV3, GPIO_PTV2, GPIO_PTV1, GPIO_PTV0,
+
+        /* PTW */
+        GPIO_PTW7, GPIO_PTW6, GPIO_PTW5, GPIO_PTW4,
+        GPIO_PTW3, GPIO_PTW2, GPIO_PTW1, GPIO_PTW0,
+
+        /* PTX */
+        GPIO_PTX7, GPIO_PTX6, GPIO_PTX5, GPIO_PTX4,
+        GPIO_PTX3, GPIO_PTX2, GPIO_PTX1, GPIO_PTX0,
+
+        /* PTY */
+        GPIO_PTY7, GPIO_PTY6, GPIO_PTY5, GPIO_PTY4,
+        GPIO_PTY3, GPIO_PTY2, GPIO_PTY1, GPIO_PTY0,
+
+        /* PTZ */
+        GPIO_PTZ7, GPIO_PTZ6, GPIO_PTZ5, GPIO_PTZ4,
+        GPIO_PTZ3, GPIO_PTZ2, GPIO_PTZ1, GPIO_PTZ0,
+
+
+        /* PTA (mobule: LBSC, CPG, LPC) */
+        GPIO_FN_BS,     GPIO_FN_RDWR,   GPIO_FN_WE1,    GPIO_FN_RDY,
+        GPIO_FN_MD10,   GPIO_FN_MD9,    GPIO_FN_MD8,
+        GPIO_FN_LGPIO7, GPIO_FN_LGPIO6, GPIO_FN_LGPIO5, GPIO_FN_LGPIO4,
+        GPIO_FN_LGPIO3, GPIO_FN_LGPIO2, GPIO_FN_LGPIO1, GPIO_FN_LGPIO0,
+
+        /* PTB (mobule: LBSC, EtherC, SIM, LPC) */
+        GPIO_FN_D15,    GPIO_FN_D14,    GPIO_FN_D13,    GPIO_FN_D12,
+        GPIO_FN_D11,    GPIO_FN_D10,    GPIO_FN_D9,     GPIO_FN_D8,
+        GPIO_FN_ET0_MDC,                GPIO_FN_ET0_MDIO,
+        GPIO_FN_ET1_MDC,                GPIO_FN_ET1_MDIO,
+        GPIO_FN_SIM_D,  GPIO_FN_SIM_CLK,                GPIO_FN_SIM_RST,
+        GPIO_FN_WPSZ1,  GPIO_FN_WPSZ0,  GPIO_FN_FWID,   GPIO_FN_FLSHSZ,
+        GPIO_FN_LPC_SPIEN,              GPIO_FN_BASEL,
+
+        /* PTC (mobule: SD) */
+        GPIO_FN_SD_WP,  GPIO_FN_SD_CD,  GPIO_FN_SD_CLK, GPIO_FN_SD_CMD,
+        GPIO_FN_SD_D3,  GPIO_FN_SD_D2,  GPIO_FN_SD_D1,  GPIO_FN_SD_D0,
+
+        /* PTD (mobule: INTC, SPI0, LBSC, CPG, ADC) */
+        GPIO_FN_IRQ7,   GPIO_FN_IRQ6,   GPIO_FN_IRQ5,   GPIO_FN_IRQ4,
+        GPIO_FN_IRQ3,   GPIO_FN_IRQ2,   GPIO_FN_IRQ1,   GPIO_FN_IRQ0,
+        GPIO_FN_MD6,    GPIO_FN_MD5,    GPIO_FN_MD3,    GPIO_FN_MD2,
+        GPIO_FN_MD1,    GPIO_FN_MD0,    GPIO_FN_ADTRG1, GPIO_FN_ADTRG0,
+
+        /* PTE (mobule: EtherC) */
+        GPIO_FN_ET0_CRS_DV,             GPIO_FN_ET0_TXD1,
+        GPIO_FN_ET0_TXD0,               GPIO_FN_ET0_TX_EN,
+        GPIO_FN_ET0_REF_CLK,            GPIO_FN_ET0_RXD1,
+        GPIO_FN_ET0_RXD0,               GPIO_FN_ET0_RX_ER,
+
+        /* PTF (mobule: EtherC) */
+        GPIO_FN_ET1_CRS_DV,             GPIO_FN_ET1_TXD1,
+        GPIO_FN_ET1_TXD0,               GPIO_FN_ET1_TX_EN,
+        GPIO_FN_ET1_REF_CLK,            GPIO_FN_ET1_RXD1,
+        GPIO_FN_ET1_RXD0,               GPIO_FN_ET1_RX_ER,
+
+        /* PTG (mobule: SYSTEM, PWMX, LPC) */
+        GPIO_FN_STATUS0,                GPIO_FN_STATUS1,
+        GPIO_FN_PWX0,   GPIO_FN_PWX1,   GPIO_FN_PWX2,   GPIO_FN_PWX3,
+        GPIO_FN_SERIRQ, GPIO_FN_CLKRUN, GPIO_FN_LPCPD,  GPIO_FN_LDRQ,
+
+        /* PTH (mobule: TMU, SCIF234, SPI1, SPI0) */
+        GPIO_FN_TCLK,   GPIO_FN_RXD4,   GPIO_FN_TXD4,
+        GPIO_FN_SP1_MOSI,               GPIO_FN_SP1_MISO,
+        GPIO_FN_SP1_SCK,                GPIO_FN_SP1_SCK_FB,
+        GPIO_FN_SP1_SS0,                GPIO_FN_SP1_SS1,
+        GPIO_FN_SP0_SS1,
+
+        /* PTI (mobule: INTC) */
+        GPIO_FN_IRQ15,  GPIO_FN_IRQ14,  GPIO_FN_IRQ13,  GPIO_FN_IRQ12,
+        GPIO_FN_IRQ11,  GPIO_FN_IRQ10,  GPIO_FN_IRQ9,   GPIO_FN_IRQ8,
+
+        /* PTJ (mobule: SCIF234, SERMUX) */
+        GPIO_FN_RXD3,   GPIO_FN_TXD3,   GPIO_FN_RXD2,   GPIO_FN_TXD2,
+        GPIO_FN_COM1_TXD,               GPIO_FN_COM1_RXD,
+        GPIO_FN_COM1_RTS,               GPIO_FN_COM1_CTS,
+
+        /* PTK (mobule: SERMUX) */
+        GPIO_FN_COM2_TXD,               GPIO_FN_COM2_RXD,
+        GPIO_FN_COM2_RTS,               GPIO_FN_COM2_CTS,
+        GPIO_FN_COM2_DTR,               GPIO_FN_COM2_DSR,
+        GPIO_FN_COM2_DCD,               GPIO_FN_COM2_RI,
+
+        /* PTL (mobule: SERMUX) */
+        GPIO_FN_RAC_TXD,                GPIO_FN_RAC_RXD,
+        GPIO_FN_RAC_RTS,                GPIO_FN_RAC_CTS,
+        GPIO_FN_RAC_DTR,                GPIO_FN_RAC_DSR,
+        GPIO_FN_RAC_DCD,                GPIO_FN_RAC_RI,
+
+        /* PTM (mobule: IIC, LPC) */
+        GPIO_FN_SDA6,   GPIO_FN_SCL6,   GPIO_FN_SDA7,   GPIO_FN_SCL7,
+        GPIO_FN_WP,     GPIO_FN_FMS0,   GPIO_FN_FMS1,
+
+        /* PTN (mobule: SCIF234, EVC) */
+        GPIO_FN_SCK2,   GPIO_FN_RTS4,   GPIO_FN_RTS3,   GPIO_FN_RTS2,
+        GPIO_FN_CTS4,   GPIO_FN_CTS3,   GPIO_FN_CTS2,
+        GPIO_FN_EVENT7, GPIO_FN_EVENT6, GPIO_FN_EVENT5, GPIO_FN_EVENT4,
+        GPIO_FN_EVENT3, GPIO_FN_EVENT2, GPIO_FN_EVENT1, GPIO_FN_EVENT0,
+
+        /* PTO (mobule: SGPIO) */
+        GPIO_FN_SGPIO0_CLK,             GPIO_FN_SGPIO0_LOAD,
+        GPIO_FN_SGPIO0_DI,              GPIO_FN_SGPIO0_DO,
+        GPIO_FN_SGPIO1_CLK,             GPIO_FN_SGPIO1_LOAD,
+        GPIO_FN_SGPIO1_DI,              GPIO_FN_SGPIO1_DO,
+
+        /* PTP (mobule: JMC, SCIF234) */
+        GPIO_FN_JMCTCK, GPIO_FN_JMCTMS, GPIO_FN_JMCTDO, GPIO_FN_JMCTDI,
+        GPIO_FN_JMCRST, GPIO_FN_SCK4,   GPIO_FN_SCK3,
+
+        /* PTQ (mobule: LPC) */
+        GPIO_FN_LAD3,   GPIO_FN_LAD2,   GPIO_FN_LAD1,   GPIO_FN_LAD0,
+        GPIO_FN_LFRAME, GPIO_FN_LRESET, GPIO_FN_LCLK,
+
+        /* PTR (mobule: GRA, IIC) */
+        GPIO_FN_DDC3,   GPIO_FN_DDC2,
+        GPIO_FN_SDA8,   GPIO_FN_SCL8,   GPIO_FN_SDA2,   GPIO_FN_SCL2,
+        GPIO_FN_SDA1,   GPIO_FN_SCL1,   GPIO_FN_SDA0,   GPIO_FN_SCL0,
+
+        /* PTS (mobule: GRA, IIC) */
+        GPIO_FN_DDC1,   GPIO_FN_DDC0,
+        GPIO_FN_SDA9,   GPIO_FN_SCL9,   GPIO_FN_SDA5,   GPIO_FN_SCL5,
+        GPIO_FN_SDA4,   GPIO_FN_SCL4,   GPIO_FN_SDA3,   GPIO_FN_SCL3,
+
+        /* PTT (mobule: SYSTEM, PWMX) */
+        GPIO_FN_AUDSYNC,                GPIO_FN_AUDCK,
+        GPIO_FN_AUDATA3,                GPIO_FN_AUDATA2,
+        GPIO_FN_AUDATA1,                GPIO_FN_AUDATA0,
+        GPIO_FN_PWX7,   GPIO_FN_PWX6,   GPIO_FN_PWX5,   GPIO_FN_PWX4,
+
+        /* PTU (mobule: LBSC, DMAC) */
+        GPIO_FN_CS6,    GPIO_FN_CS5,    GPIO_FN_CS4,    GPIO_FN_CS0,
+        GPIO_FN_RD,     GPIO_FN_WE0,    GPIO_FN_A25,    GPIO_FN_A24,
+        GPIO_FN_DREQ0,  GPIO_FN_DACK0,
+
+        /* PTV (mobule: LBSC, DMAC) */
+        GPIO_FN_A23,    GPIO_FN_A22,    GPIO_FN_A21,    GPIO_FN_A20,
+        GPIO_FN_A19,    GPIO_FN_A18,    GPIO_FN_A17,    GPIO_FN_A16,
+        GPIO_FN_TEND0,  GPIO_FN_DREQ1,  GPIO_FN_DACK1,  GPIO_FN_TEND1,
+
+        /* PTW (mobule: LBSC) */
+        GPIO_FN_A15,    GPIO_FN_A14,    GPIO_FN_A13,    GPIO_FN_A12,
+        GPIO_FN_A11,    GPIO_FN_A10,    GPIO_FN_A9,     GPIO_FN_A8,
+
+        /* PTX (mobule: LBSC) */
+        GPIO_FN_A7,     GPIO_FN_A6,     GPIO_FN_A5,     GPIO_FN_A4,
+        GPIO_FN_A3,     GPIO_FN_A2,     GPIO_FN_A1,     GPIO_FN_A0,
+
+        /* PTY (mobule: LBSC) */
+        GPIO_FN_D7,     GPIO_FN_D6,     GPIO_FN_D5,     GPIO_FN_D4,
+        GPIO_FN_D3,     GPIO_FN_D2,     GPIO_FN_D1,     GPIO_FN_D0,
+};
+
+#endif /* __ASM_SH7757_H__ */
diff --git a/arch/sh/include/mach-common/mach/sh7785lcr.h b/arch/sh/include/mach-common/mach/sh7785lcr.h
index 90011d435f30..1292ae5c21b3 100644
--- a/arch/sh/include/mach-common/mach/sh7785lcr.h
+++ b/arch/sh/include/mach-common/mach/sh7785lcr.h
@@ -35,6 +35,8 @@
 #define PCA9564_ADDR            0x06000000      /* I2C */
 #define PCA9564_SIZE            0x00000100
 
+#define PCA9564_PROTO_32BIT_ADDR        0x14000000
+
 #define SM107_MEM_ADDR          0x10000000
 #define SM107_MEM_SIZE          0x00e00000
 #define SM107_REG_ADDR          0x13e00000
diff --git a/arch/sh/include/mach-kfr2r09/mach/partner-jet-setup.txt b/arch/sh/include/mach-kfr2r09/mach/partner-jet-setup.txt
index 25801d495c5f..a19ac31c8cde 100644
--- a/arch/sh/include/mach-kfr2r09/mach/partner-jet-setup.txt
+++ b/arch/sh/include/mach-kfr2r09/mach/partner-jet-setup.txt
@@ -16,6 +16,12 @@ LIST "--------------------------------"
 LIST "disable watchdog"
 EW 0xa4520004, 0xa507
 
+LIST "invalidate instruction cache"
+ED 0xff00001c, 0x00000800
+
+LIST "invalidate TLBs"
+ED 0xff000010, 0x00000004
+
 LIST "select mode for cs5 + cs6"
 ED 0xff800020, 0xa5a50001
 ED 0xfec10000, 0x0000001b
diff --git a/arch/sh/include/mach-kfr2r09/mach/romimage.h b/arch/sh/include/mach-kfr2r09/mach/romimage.h
index f5aa8e16770c..39ee79443569 100644
--- a/arch/sh/include/mach-kfr2r09/mach/romimage.h
+++ b/arch/sh/include/mach-kfr2r09/mach/romimage.h
@@ -73,3 +73,16 @@
 .endm
 
 #include "partner-jet-setup.txt"
+
+        /* execute icbi after enabling cache */
+        mov.l   1f, r0
+        icbi    @r0
+
+        /* jump to cached area */
+        mova    2f, r0
+        jmp     @r0
+         nop
+
+        .align 2
+1:      .long 0xa8000000
+2:
diff --git a/arch/sh/kernel/cpu/irq/ipr.c b/arch/sh/kernel/cpu/irq/ipr.c
index 808d99a48efb..c1508a90fc6a 100644
--- a/arch/sh/kernel/cpu/irq/ipr.c
+++ b/arch/sh/kernel/cpu/irq/ipr.c
@@ -35,6 +35,7 @@ static void disable_ipr_irq(unsigned int irq)
         unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx];
         /* Set the priority in IPR to 0 */
         __raw_writew(__raw_readw(addr) & (0xffff ^ (0xf << p->shift)), addr);
+        (void)__raw_readw(addr);        /* Read back to flush write posting */
 }
 
 static void enable_ipr_irq(unsigned int irq)
diff --git a/arch/sh/kernel/cpu/sh3/entry.S b/arch/sh/kernel/cpu/sh3/entry.S
index f94f25e666cc..aebd33d18ff7 100644
--- a/arch/sh/kernel/cpu/sh3/entry.S
+++ b/arch/sh/kernel/cpu/sh3/entry.S
@@ -265,7 +265,7 @@ restore_all:
         !
         ! Calculate new SR value
         mov     k3, k2                  ! original SR value
-        mov     #0xf0, k1
+        mov     #0xfffffff0, k1
         extu.b  k1, k1
         not     k1, k1
         and     k1, k2                  ! Mask original SR value
@@ -516,6 +516,8 @@ ENTRY(handle_interrupt)
         bsr     save_regs       ! needs original pr value in k3
          mov    #-1, k2         ! default vector kept in k2
 
+        setup_frame_reg
+
         stc     sr, r0  ! get status register
         shlr2   r0
         and     #0x3c, r0
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index 695026a3f02d..d36f0c45f55f 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -144,8 +144,15 @@ int __init detect_cpu_and_cache_system(void)
                 }
                 break;
         case 0x300b:
-                boot_cpu_data.type = CPU_SH7724;
-                boot_cpu_data.flags |= CPU_HAS_L2_CACHE;
+                switch (prr) {
+                case 0x20:
+                        boot_cpu_data.type = CPU_SH7724;
+                        boot_cpu_data.flags |= CPU_HAS_L2_CACHE;
+                        break;
+                case 0x50:
+                        boot_cpu_data.type = CPU_SH7757;
+                        break;
+                }
                 break;
         case 0x4000:    /* 1st cut */
         case 0x4001:    /* 2nd cut */
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index 12cddf4c721d..490d5dc9e372 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -3,6 +3,7 @@
 #
 
 # CPU subtype setup
+obj-$(CONFIG_CPU_SUBTYPE_SH7757)        += setup-sh7757.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7763)        += setup-sh7763.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7770)        += setup-sh7770.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7780)        += setup-sh7780.o
@@ -19,6 +20,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SHX3)		+= setup-shx3.o
 smp-$(CONFIG_CPU_SHX3)                  := smp-shx3.o
 
 # Primary on-chip clocks (common)
+clock-$(CONFIG_CPU_SUBTYPE_SH7757)      := clock-sh7757.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7763)      := clock-sh7763.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7770)      := clock-sh7770.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7780)      := clock-sh7780.o
@@ -35,6 +37,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SHX3)	:= clock-shx3.o
 pinmux-$(CONFIG_CPU_SUBTYPE_SH7722)     := pinmux-sh7722.o
 pinmux-$(CONFIG_CPU_SUBTYPE_SH7723)     := pinmux-sh7723.o
 pinmux-$(CONFIG_CPU_SUBTYPE_SH7724)     := pinmux-sh7724.o
+pinmux-$(CONFIG_CPU_SUBTYPE_SH7757)     := pinmux-sh7757.o
 pinmux-$(CONFIG_CPU_SUBTYPE_SH7785)     := pinmux-sh7785.o
 pinmux-$(CONFIG_CPU_SUBTYPE_SH7786)     := pinmux-sh7786.o
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index 5b1bbbe63b1b..ea38b554dc05 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -164,11 +164,11 @@ static struct clk mstp_clks[] = {
         SH_HWBLK_CLK("2dg0", -1, B_CLK, HWBLK_2DG, 0),
         SH_HWBLK_CLK("siu0", -1, B_CLK, HWBLK_SIU, 0),
         SH_HWBLK_CLK("vou0", -1, B_CLK, HWBLK_VOU, 0),
-        SH_HWBLK_CLK("jpu0", -1, B_CLK, HWBLK_JPU, CLK_ENABLE_ON_INIT),
+        SH_HWBLK_CLK("jpu0", -1, B_CLK, HWBLK_JPU, 0),
         SH_HWBLK_CLK("beu0", -1, B_CLK, HWBLK_BEU, 0),
         SH_HWBLK_CLK("ceu0", -1, B_CLK, HWBLK_CEU, 0),
-        SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU, CLK_ENABLE_ON_INIT),
-        SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, CLK_ENABLE_ON_INIT),
+        SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU, 0),
+        SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, 0),
         SH_HWBLK_CLK("lcdc0", -1, P_CLK, HWBLK_LCDC, 0),
 };
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
index e5c63911403c..20a31c2255a8 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
@@ -190,12 +190,12 @@ static struct clk mstp_clks[] = {
         SH_HWBLK_CLK("usb0", -1, B_CLK, HWBLK_USB, 0),
         SH_HWBLK_CLK("2dg0", -1, B_CLK, HWBLK_2DG, 0),
         SH_HWBLK_CLK("siu0", -1, B_CLK, HWBLK_SIU, 0),
-        SH_HWBLK_CLK("veu1", -1, B_CLK, HWBLK_VEU2H1, CLK_ENABLE_ON_INIT),
+        SH_HWBLK_CLK("veu1", -1, B_CLK, HWBLK_VEU2H1, 0),
         SH_HWBLK_CLK("vou0", -1, B_CLK, HWBLK_VOU, 0),
         SH_HWBLK_CLK("beu0", -1, B_CLK, HWBLK_BEU, 0),
         SH_HWBLK_CLK("ceu0", -1, B_CLK, HWBLK_CEU, 0),
-        SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU2H0, CLK_ENABLE_ON_INIT),
-        SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, CLK_ENABLE_ON_INIT),
+        SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU2H0, 0),
+        SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, 0),
         SH_HWBLK_CLK("lcdc0", -1, B_CLK, HWBLK_LCDC, 0),
 };
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
index 627588dfddf0..dfe9192be63e 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
@@ -204,17 +204,17 @@ static struct clk mstp_clks[] = {
         SH_HWBLK_CLK("2dg0", -1, B_CLK, HWBLK_2DG, 0),
         SH_HWBLK_CLK("sdhi0", -1, B_CLK, HWBLK_SDHI0, 0),
         SH_HWBLK_CLK("sdhi1", -1, B_CLK, HWBLK_SDHI1, 0),
-        SH_HWBLK_CLK("veu1", -1, B_CLK, HWBLK_VEU1, CLK_ENABLE_ON_INIT),
+        SH_HWBLK_CLK("veu1", -1, B_CLK, HWBLK_VEU1, 0),
         SH_HWBLK_CLK("ceu1", -1, B_CLK, HWBLK_CEU1, 0),
         SH_HWBLK_CLK("beu1", -1, B_CLK, HWBLK_BEU1, 0),
         SH_HWBLK_CLK("2ddmac0", -1, SH_CLK, HWBLK_2DDMAC, 0),
         SH_HWBLK_CLK("spu0", -1, B_CLK, HWBLK_SPU, 0),
-        SH_HWBLK_CLK("jpu0", -1, B_CLK, HWBLK_JPU, CLK_ENABLE_ON_INIT),
+        SH_HWBLK_CLK("jpu0", -1, B_CLK, HWBLK_JPU, 0),
         SH_HWBLK_CLK("vou0", -1, B_CLK, HWBLK_VOU, 0),
         SH_HWBLK_CLK("beu0", -1, B_CLK, HWBLK_BEU0, 0),
         SH_HWBLK_CLK("ceu0", -1, B_CLK, HWBLK_CEU0, 0),
-        SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU0, CLK_ENABLE_ON_INIT),
-        SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, CLK_ENABLE_ON_INIT),
+        SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU0, 0),
+        SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, 0),
         SH_HWBLK_CLK("lcdc0", -1, B_CLK, HWBLK_LCDC, 0),
 };
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
new file mode 100644
index 000000000000..ddc235ca9664
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
@@ -0,0 +1,130 @@
+/*
+ * arch/sh/kernel/cpu/sh4/clock-sh7757.c
+ *
+ * SH7757 support for the clock framework
+ *
+ *  Copyright (C) 2009  Renesas Solutions Corp.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <asm/clock.h>
+#include <asm/freq.h>
+
+static int ifc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1,
+                              16, 1, 1, 32, 1, 1, 1, 1 };
+static int sfc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1,
+                              16, 1, 1, 32, 1, 1, 1, 1 };
+static int bfc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1,
+                              16, 1, 1, 32, 1, 1, 1, 1 };
+static int p1fc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1,
+                               16, 1, 1, 32, 1, 1, 1, 1 };
+
+static void master_clk_init(struct clk *clk)
+{
+        clk->rate = CONFIG_SH_PCLK_FREQ * 16;
+}
+
+static struct clk_ops sh7757_master_clk_ops = {
+        .init           = master_clk_init,
+};
+
+static void module_clk_recalc(struct clk *clk)
+{
+        int idx = ctrl_inl(FRQCR) & 0x0000000f;
+        clk->rate = clk->parent->rate / p1fc_divisors[idx];
+}
+
+static struct clk_ops sh7757_module_clk_ops = {
+        .recalc         = module_clk_recalc,
+};
+
+static void bus_clk_recalc(struct clk *clk)
+{
+        int idx = (ctrl_inl(FRQCR) >> 8) & 0x0000000f;
+        clk->rate = clk->parent->rate / bfc_divisors[idx];
+}
+
+static struct clk_ops sh7757_bus_clk_ops = {
+        .recalc         = bus_clk_recalc,
+};
+
+static void cpu_clk_recalc(struct clk *clk)
+{
+        int idx = (ctrl_inl(FRQCR) >> 20) & 0x0000000f;
+        clk->rate = clk->parent->rate / ifc_divisors[idx];
+}
+
+static struct clk_ops sh7757_cpu_clk_ops = {
+        .recalc         = cpu_clk_recalc,
+};
+
+static struct clk_ops *sh7757_clk_ops[] = {
+        &sh7757_master_clk_ops,
+        &sh7757_module_clk_ops,
+        &sh7757_bus_clk_ops,
+        &sh7757_cpu_clk_ops,
+};
+
+void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+{
+        if (idx < ARRAY_SIZE(sh7757_clk_ops))
+                *ops = sh7757_clk_ops[idx];
+}
+
+static void shyway_clk_recalc(struct clk *clk)
+{
+        int idx = (ctrl_inl(FRQCR) >> 12) & 0x0000000f;
+        clk->rate = clk->parent->rate / sfc_divisors[idx];
+}
+
+static struct clk_ops sh7757_shyway_clk_ops = {
+        .recalc         = shyway_clk_recalc,
+};
+
+static struct clk sh7757_shyway_clk = {
+        .name           = "shyway_clk",
+        .flags          = CLK_ENABLE_ON_INIT,
+        .ops            = &sh7757_shyway_clk_ops,
+};
+
+/*
+ * Additional sh7757-specific on-chip clocks that aren't already part of the
+ * clock framework
+ */
+static struct clk *sh7757_onchip_clocks[] = {
+        &sh7757_shyway_clk,
+};
+
+static int __init sh7757_clk_init(void)
+{
+        struct clk *clk = clk_get(NULL, "master_clk");
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(sh7757_onchip_clocks); i++) {
+                struct clk *clkp = sh7757_onchip_clocks[i];
+
+                clkp->parent = clk;
+                clk_register(clkp);
+                clk_enable(clkp);
+        }
+
+        /*
+         * Now that we have the rest of the clocks registered, we need to
+         * force the parent clock to propagate so that these clocks will
+         * automatically figure out their rate. We cheat by handing the
+         * parent clock its current rate and forcing child propagation.
+         */
+        clk_set_rate(clk, clk_get_rate(clk));
+
+        clk_put(clk);
+
+        return 0;
+}
+
+arch_initcall(sh7757_clk_init);
+
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
new file mode 100644
index 000000000000..ed23b155c097
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
@@ -0,0 +1,2019 @@
+/*
+ * SH7757 (A0 step) Pinmux
+ *
+ *  Copyright (C) 2009  Renesas Solutions Corp.
+ *
+ *  Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * Based on SH7757 Pinmux
+ *  Copyright (C) 2008  Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <cpu/sh7757.h>
+
+enum {
+        PINMUX_RESERVED = 0,
+
+        PINMUX_DATA_BEGIN,
+        PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
+        PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA,
+        PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
+        PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA,
+        PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
+        PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA,
+        PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
+        PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA,
+        PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
+        PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA,
+        PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
+        PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA,
+        PTG7_DATA, PTG6_DATA, PTG5_DATA, PTG4_DATA,
+        PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA,
+        PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
+        PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA,
+        PTI7_DATA, PTI6_DATA, PTI5_DATA, PTI4_DATA,
+        PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA,
+        PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA,
+        PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA,
+        PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
+        PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA,
+        PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
+        PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA,
+        PTM6_DATA, PTM5_DATA, PTM4_DATA,
+        PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA,
+        PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
+        PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA,
+        PTO7_DATA, PTO6_DATA, PTO5_DATA, PTO4_DATA,
+        PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA,
+        PTP6_DATA, PTP5_DATA, PTP4_DATA,
+        PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA,
+        PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
+        PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA,
+        PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
+        PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA,
+        PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA,
+        PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA,
+        PTT5_DATA, PTT4_DATA,
+        PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA,
+        PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
+        PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA,
+        PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
+        PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA,
+        PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
+        PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA,
+        PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
+        PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA,
+        PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
+        PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA,
+        PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
+        PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA,
+        PINMUX_DATA_END,
+
+        PINMUX_INPUT_BEGIN,
+        PTA7_IN, PTA6_IN, PTA5_IN, PTA4_IN,
+        PTA3_IN, PTA2_IN, PTA1_IN, PTA0_IN,
+        PTB7_IN, PTB6_IN, PTB5_IN, PTB4_IN,
+        PTB3_IN, PTB2_IN, PTB1_IN, PTB0_IN,
+        PTC7_IN, PTC6_IN, PTC5_IN, PTC4_IN,
+        PTC3_IN, PTC2_IN, PTC1_IN, PTC0_IN,
+        PTD7_IN, PTD6_IN, PTD5_IN, PTD4_IN,
+        PTD3_IN, PTD2_IN, PTD1_IN, PTD0_IN,
+        PTE7_IN, PTE6_IN, PTE5_IN, PTE4_IN,
+        PTE3_IN, PTE2_IN, PTE1_IN, PTE0_IN,
+        PTF7_IN, PTF6_IN, PTF5_IN, PTF4_IN,
+        PTF3_IN, PTF2_IN, PTF1_IN, PTF0_IN,
+        PTG7_IN, PTG6_IN, PTG5_IN, PTG4_IN,
+        PTG3_IN, PTG2_IN, PTG1_IN, PTG0_IN,
+        PTH7_IN, PTH6_IN, PTH5_IN, PTH4_IN,
+        PTH3_IN, PTH2_IN, PTH1_IN, PTH0_IN,
+        PTI7_IN, PTI6_IN, PTI5_IN, PTI4_IN,
+        PTI3_IN, PTI2_IN, PTI1_IN, PTI0_IN,
+        PTJ7_IN, PTJ6_IN, PTJ5_IN, PTJ4_IN,
+        PTJ3_IN, PTJ2_IN, PTJ1_IN, PTJ0_IN,
+        PTK7_IN, PTK6_IN, PTK5_IN, PTK4_IN,
+        PTK3_IN, PTK2_IN, PTK1_IN, PTK0_IN,
+        PTL7_IN, PTL6_IN, PTL5_IN, PTL4_IN,
+        PTL3_IN, PTL2_IN, PTL1_IN, PTL0_IN,
+        PTM6_IN, PTM5_IN, PTM4_IN,
+        PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN,
+        PTN7_IN, PTN6_IN, PTN5_IN, PTN4_IN,
+        PTN3_IN, PTN2_IN, PTN1_IN, PTN0_IN,
+        PTO7_IN, PTO6_IN, PTO5_IN, PTO4_IN,
+        PTO3_IN, PTO2_IN, PTO1_IN, PTO0_IN,
+        PTP6_IN, PTP5_IN, PTP4_IN,
+        PTP3_IN, PTP2_IN, PTP1_IN, PTP0_IN,
+        PTQ6_IN, PTQ5_IN, PTQ4_IN,
+        PTQ3_IN, PTQ2_IN, PTQ1_IN, PTQ0_IN,
+        PTR7_IN, PTR6_IN, PTR5_IN, PTR4_IN,
+        PTR3_IN, PTR2_IN, PTR1_IN, PTR0_IN,
+        PTS7_IN, PTS6_IN, PTS5_IN, PTS4_IN,
+        PTS3_IN, PTS2_IN, PTS1_IN, PTS0_IN,
+        PTT5_IN, PTT4_IN,
+        PTT3_IN, PTT2_IN, PTT1_IN, PTT0_IN,
+        PTU7_IN, PTU6_IN, PTU5_IN, PTU4_IN,
+        PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN,
+        PTV7_IN, PTV6_IN, PTV5_IN, PTV4_IN,
+        PTV3_IN, PTV2_IN, PTV1_IN, PTV0_IN,
+        PTW7_IN, PTW6_IN, PTW5_IN, PTW4_IN,
+        PTW3_IN, PTW2_IN, PTW1_IN, PTW0_IN,
+        PTX7_IN, PTX6_IN, PTX5_IN, PTX4_IN,
+        PTX3_IN, PTX2_IN, PTX1_IN, PTX0_IN,
+        PTY7_IN, PTY6_IN, PTY5_IN, PTY4_IN,
+        PTY3_IN, PTY2_IN, PTY1_IN, PTY0_IN,
+        PTZ7_IN, PTZ6_IN, PTZ5_IN, PTZ4_IN,
+        PTZ3_IN, PTZ2_IN, PTZ1_IN, PTZ0_IN,
+        PINMUX_INPUT_END,
+
+        PINMUX_INPUT_PULLUP_BEGIN,
+        PTU7_IN_PU, PTU6_IN_PU, PTU5_IN_PU, PTU4_IN_PU,
+        PTU3_IN_PU, PTU2_IN_PU, PTU1_IN_PU, PTU0_IN_PU,
+        PTV7_IN_PU, PTV6_IN_PU, PTV5_IN_PU, PTV4_IN_PU,
+        PTV3_IN_PU, PTV2_IN_PU, PTV1_IN_PU, PTV0_IN_PU,
+        PTW7_IN_PU, PTW6_IN_PU, PTW5_IN_PU, PTW4_IN_PU,
+        PTW3_IN_PU, PTW2_IN_PU, PTW1_IN_PU, PTW0_IN_PU,
+        PTX7_IN_PU, PTX6_IN_PU, PTX5_IN_PU, PTX4_IN_PU,
+        PTX3_IN_PU, PTX2_IN_PU, PTX1_IN_PU, PTX0_IN_PU,
+        PTY7_IN_PU, PTY6_IN_PU, PTY5_IN_PU, PTY4_IN_PU,
+        PTY3_IN_PU, PTY2_IN_PU, PTY1_IN_PU, PTY0_IN_PU,
+        PINMUX_INPUT_PULLUP_END,
+
+        PINMUX_OUTPUT_BEGIN,
+        PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT,
+        PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT,
+        PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT,
+        PTB3_OUT, PTB2_OUT, PTB1_OUT, PTB0_OUT,
+        PTC7_OUT, PTC6_OUT, PTC5_OUT, PTC4_OUT,
+        PTC3_OUT, PTC2_OUT, PTC1_OUT, PTC0_OUT,
+        PTD7_OUT, PTD6_OUT, PTD5_OUT, PTD4_OUT,
+        PTD3_OUT, PTD2_OUT, PTD1_OUT, PTD0_OUT,
+        PTE7_OUT, PTE6_OUT, PTE5_OUT, PTE4_OUT,
+        PTE3_OUT, PTE2_OUT, PTE1_OUT, PTE0_OUT,
+        PTF7_OUT, PTF6_OUT, PTF5_OUT, PTF4_OUT,
+        PTF3_OUT, PTF2_OUT, PTF1_OUT, PTF0_OUT,
+        PTG7_OUT, PTG6_OUT, PTG5_OUT, PTG4_OUT,
+        PTG3_OUT, PTG2_OUT, PTG1_OUT, PTG0_OUT,
+        PTH7_OUT, PTH6_OUT, PTH5_OUT, PTH4_OUT,
+        PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT,
+        PTI7_OUT, PTI6_OUT, PTI5_OUT, PTI4_OUT,
+        PTI3_OUT, PTI2_OUT, PTI1_OUT, PTI0_OUT,
+        PTJ7_OUT, PTJ6_OUT, PTJ5_OUT, PTJ4_OUT,
+        PTJ3_OUT, PTJ2_OUT, PTJ1_OUT, PTJ0_OUT,
+        PTK7_OUT, PTK6_OUT, PTK5_OUT, PTK4_OUT,
+        PTK3_OUT, PTK2_OUT, PTK1_OUT, PTK0_OUT,
+        PTL7_OUT, PTL6_OUT, PTL5_OUT, PTL4_OUT,
+        PTL3_OUT, PTL2_OUT, PTL1_OUT, PTL0_OUT,
+        PTM6_OUT, PTM5_OUT, PTM4_OUT,
+        PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT,
+        PTN7_OUT, PTN6_OUT, PTN5_OUT, PTN4_OUT,
+        PTN3_OUT, PTN2_OUT, PTN1_OUT, PTN0_OUT,
+        PTO7_OUT, PTO6_OUT, PTO5_OUT, PTO4_OUT,
+        PTO3_OUT, PTO2_OUT, PTO1_OUT, PTO0_OUT,
+        PTP6_OUT, PTP5_OUT, PTP4_OUT,
+        PTP3_OUT, PTP2_OUT, PTP1_OUT, PTP0_OUT,
+        PTQ6_OUT, PTQ5_OUT, PTQ4_OUT,
+        PTQ3_OUT, PTQ2_OUT, PTQ1_OUT, PTQ0_OUT,
+        PTR7_OUT, PTR6_OUT, PTR5_OUT, PTR4_OUT,
+        PTR3_OUT, PTR2_OUT, PTR1_OUT, PTR0_OUT,
+        PTS7_OUT, PTS6_OUT, PTS5_OUT, PTS4_OUT,
+        PTS3_OUT, PTS2_OUT, PTS1_OUT, PTS0_OUT,
+        PTT5_OUT, PTT4_OUT,
+        PTT3_OUT, PTT2_OUT, PTT1_OUT, PTT0_OUT,
+        PTU7_OUT, PTU6_OUT, PTU5_OUT, PTU4_OUT,
+        PTU3_OUT, PTU2_OUT, PTU1_OUT, PTU0_OUT,
+        PTV7_OUT, PTV6_OUT, PTV5_OUT, PTV4_OUT,
+        PTV3_OUT, PTV2_OUT, PTV1_OUT, PTV0_OUT,
+        PTW7_OUT, PTW6_OUT, PTW5_OUT, PTW4_OUT,
+        PTW3_OUT, PTW2_OUT, PTW1_OUT, PTW0_OUT,
+        PTX7_OUT, PTX6_OUT, PTX5_OUT, PTX4_OUT,
+        PTX3_OUT, PTX2_OUT, PTX1_OUT, PTX0_OUT,
+        PTY7_OUT, PTY6_OUT, PTY5_OUT, PTY4_OUT,
+        PTY3_OUT, PTY2_OUT, PTY1_OUT, PTY0_OUT,
+        PTZ7_OUT, PTZ6_OUT, PTZ5_OUT, PTZ4_OUT,
+        PTZ3_OUT, PTZ2_OUT, PTZ1_OUT, PTZ0_OUT,
+        PINMUX_OUTPUT_END,
+
+        PINMUX_FUNCTION_BEGIN,
+        PTA7_FN, PTA6_FN, PTA5_FN, PTA4_FN,
+        PTA3_FN, PTA2_FN, PTA1_FN, PTA0_FN,
+        PTB7_FN, PTB6_FN, PTB5_FN, PTB4_FN,
+        PTB3_FN, PTB2_FN, PTB1_FN, PTB0_FN,
+        PTC7_FN, PTC6_FN, PTC5_FN, PTC4_FN,
+        PTC3_FN, PTC2_FN, PTC1_FN, PTC0_FN,
+        PTD7_FN, PTD6_FN, PTD5_FN, PTD4_FN,
+        PTD3_FN, PTD2_FN, PTD1_FN, PTD0_FN,
+        PTE7_FN, PTE6_FN, PTE5_FN, PTE4_FN,
+        PTE3_FN, PTE2_FN, PTE1_FN, PTE0_FN,
+        PTF7_FN, PTF6_FN, PTF5_FN, PTF4_FN,
+        PTF3_FN, PTF2_FN, PTF1_FN, PTF0_FN,
+        PTG7_FN, PTG6_FN, PTG5_FN, PTG4_FN,
+        PTG3_FN, PTG2_FN, PTG1_FN, PTG0_FN,
+        PTH7_FN, PTH6_FN, PTH5_FN, PTH4_FN,
+        PTH3_FN, PTH2_FN, PTH1_FN, PTH0_FN,
+        PTI7_FN, PTI6_FN, PTI5_FN, PTI4_FN,
+        PTI3_FN, PTI2_FN, PTI1_FN, PTI0_FN,
+        PTJ7_FN, PTJ6_FN, PTJ5_FN, PTJ4_FN,
+        PTJ3_FN, PTJ2_FN, PTJ1_FN, PTJ0_FN,
+        PTK7_FN, PTK6_FN, PTK5_FN, PTK4_FN,
+        PTK3_FN, PTK2_FN, PTK1_FN, PTK0_FN,
+        PTL7_FN, PTL6_FN, PTL5_FN, PTL4_FN,
+        PTL3_FN, PTL2_FN, PTL1_FN, PTL0_FN,
+        PTM6_FN, PTM5_FN, PTM4_FN,
+        PTM3_FN, PTM2_FN, PTM1_FN, PTM0_FN,
+        PTN7_FN, PTN6_FN, PTN5_FN, PTN4_FN,
+        PTN3_FN, PTN2_FN, PTN1_FN, PTN0_FN,
+        PTO7_FN, PTO6_FN, PTO5_FN, PTO4_FN,
+        PTO3_FN, PTO2_FN, PTO1_FN, PTO0_FN,
+        PTP6_FN, PTP5_FN, PTP4_FN,
+        PTP3_FN, PTP2_FN, PTP1_FN, PTP0_FN,
+        PTQ6_FN, PTQ5_FN, PTQ4_FN,
+        PTQ3_FN, PTQ2_FN, PTQ1_FN, PTQ0_FN,
+        PTR7_FN, PTR6_FN, PTR5_FN, PTR4_FN,
+        PTR3_FN, PTR2_FN, PTR1_FN, PTR0_FN,
+        PTS7_FN, PTS6_FN, PTS5_FN, PTS4_FN,
+        PTS3_FN, PTS2_FN, PTS1_FN, PTS0_FN,
+        PTT5_FN, PTT4_FN,
+        PTT3_FN, PTT2_FN, PTT1_FN, PTT0_FN,
+        PTU7_FN, PTU6_FN, PTU5_FN, PTU4_FN,
+        PTU3_FN, PTU2_FN, PTU1_FN, PTU0_FN,
+        PTV7_FN, PTV6_FN, PTV5_FN, PTV4_FN,
+        PTV3_FN, PTV2_FN, PTV1_FN, PTV0_FN,
+        PTW7_FN, PTW6_FN, PTW5_FN, PTW4_FN,
+        PTW3_FN, PTW2_FN, PTW1_FN, PTW0_FN,
+        PTX7_FN, PTX6_FN, PTX5_FN, PTX4_FN,
+        PTX3_FN, PTX2_FN, PTX1_FN, PTX0_FN,
+        PTY7_FN, PTY6_FN, PTY5_FN, PTY4_FN,
+        PTY3_FN, PTY2_FN, PTY1_FN, PTY0_FN,
+        PTZ7_FN, PTZ6_FN, PTZ5_FN, PTZ4_FN,
+        PTZ3_FN, PTZ2_FN, PTZ1_FN, PTZ0_FN,
+
+        PS0_15_FN1, PS0_15_FN3,
+        PS0_14_FN1, PS0_14_FN3,
+        PS0_13_FN1, PS0_13_FN3,
+        PS0_12_FN1, PS0_12_FN3,
+        PS0_7_FN1, PS0_7_FN2,
+        PS0_6_FN1, PS0_6_FN2,
+        PS0_5_FN1, PS0_5_FN2,
+        PS0_4_FN1, PS0_4_FN2,
+        PS0_3_FN1, PS0_3_FN2,
+        PS0_2_FN1, PS0_2_FN2,
+        PS0_1_FN1, PS0_1_FN2,
+
+        PS1_7_FN1, PS1_7_FN3,
+        PS1_6_FN1, PS1_6_FN3,
+
+        PS2_13_FN1, PS2_13_FN3,
+        PS2_12_FN1, PS2_12_FN3,
+        PS2_1_FN1, PS2_1_FN2,
+        PS2_0_FN1, PS2_0_FN2,
+
+        PS4_15_FN1, PS4_15_FN2,
+        PS4_14_FN1, PS4_14_FN2,
+        PS4_13_FN1, PS4_13_FN2,
+        PS4_12_FN1, PS4_12_FN2,
+        PS4_11_FN1, PS4_11_FN2,
+        PS4_10_FN1, PS4_10_FN2,
+        PS4_9_FN1, PS4_9_FN2,
+        PS4_3_FN1, PS4_3_FN2,
+        PS4_2_FN1, PS4_2_FN2,
+        PS4_1_FN1, PS4_1_FN2,
+        PS4_0_FN1, PS4_0_FN2,
+
+        PS5_9_FN1, PS5_9_FN2,
+        PS5_8_FN1, PS5_8_FN2,
+        PS5_7_FN1, PS5_7_FN2,
+        PS5_6_FN1, PS5_6_FN2,
+        PS5_5_FN1, PS5_5_FN2,
+        PS5_4_FN1, PS5_4_FN2,
+
+        /* AN15 to 8 : EVENT15 to 8 */
+        PS6_7_FN_AN, PS6_7_FN_EV,
+        PS6_6_FN_AN, PS6_6_FN_EV,
+        PS6_5_FN_AN, PS6_5_FN_EV,
+        PS6_4_FN_AN, PS6_4_FN_EV,
+        PS6_3_FN_AN, PS6_3_FN_EV,
+        PS6_2_FN_AN, PS6_2_FN_EV,
+        PS6_1_FN_AN, PS6_1_FN_EV,
+        PS6_0_FN_AN, PS6_0_FN_EV,
+
+        PINMUX_FUNCTION_END,
+
+        PINMUX_MARK_BEGIN,
+        /* PTA (mobule: LBSC, CPG, LPC) */
+        BS_MARK,        RDWR_MARK,      WE1_MARK,       RDY_MARK,
+        MD10_MARK,      MD9_MARK,       MD8_MARK,
+        LGPIO7_MARK,    LGPIO6_MARK,    LGPIO5_MARK,    LGPIO4_MARK,
+        LGPIO3_MARK,    LGPIO2_MARK,    LGPIO1_MARK,    LGPIO0_MARK,
+
+        /* PTB (mobule: LBSC, EtherC, SIM, LPC) */
+        D15_MARK,       D14_MARK,       D13_MARK,       D12_MARK,
+        D11_MARK,       D10_MARK,       D9_MARK,        D8_MARK,
+        ET0_MDC_MARK,   ET0_MDIO_MARK,  ET1_MDC_MARK,   ET1_MDIO_MARK,
+        SIM_D_MARK,     SIM_CLK_MARK,   SIM_RST_MARK,
+        WPSZ1_MARK,     WPSZ0_MARK,     FWID_MARK,      FLSHSZ_MARK,
+        LPC_SPIEN_MARK, BASEL_MARK,
+
+        /* PTC (mobule: SD) */
+        SD_WP_MARK,     SD_CD_MARK,     SD_CLK_MARK,    SD_CMD_MARK,
+        SD_D3_MARK,     SD_D2_MARK,     SD_D1_MARK,     SD_D0_MARK,
+
+        /* PTD (mobule: INTC, SPI0, LBSC, CPG, ADC) */
+        IRQ7_MARK,      IRQ6_MARK,      IRQ5_MARK,      IRQ4_MARK,
+        IRQ3_MARK,      IRQ2_MARK,      IRQ1_MARK,      IRQ0_MARK,
+        MD6_MARK,       MD5_MARK,       MD3_MARK,       MD2_MARK,
+        MD1_MARK,       MD0_MARK,       ADTRG1_MARK,    ADTRG0_MARK,
+
+        /* PTE (mobule: EtherC) */
+        ET0_CRS_DV_MARK,        ET0_TXD1_MARK,
+        ET0_TXD0_MARK,          ET0_TX_EN_MARK,
+        ET0_REF_CLK_MARK,       ET0_RXD1_MARK,
+        ET0_RXD0_MARK,          ET0_RX_ER_MARK,
+
+        /* PTF (mobule: EtherC) */
+        ET1_CRS_DV_MARK,        ET1_TXD1_MARK,
+        ET1_TXD0_MARK,          ET1_TX_EN_MARK,
+        ET1_REF_CLK_MARK,       ET1_RXD1_MARK,
+        ET1_RXD0_MARK,          ET1_RX_ER_MARK,
+
+        /* PTG (mobule: SYSTEM, PWMX, LPC) */
+        STATUS0_MARK,   STATUS1_MARK,
+        PWX0_MARK,      PWX1_MARK,      PWX2_MARK,      PWX3_MARK,
+        SERIRQ_MARK,    CLKRUN_MARK,    LPCPD_MARK,     LDRQ_MARK,
+
+        /* PTH (mobule: TMU, SCIF234, SPI1, SPI0) */
+        TCLK_MARK,      RXD4_MARK,      TXD4_MARK,
+        SP1_MOSI_MARK,  SP1_MISO_MARK,  SP1_SCK_MARK,   SP1_SCK_FB_MARK,
+        SP1_SS0_MARK,   SP1_SS1_MARK,   SP0_SS1_MARK,
+
+        /* PTI (mobule: INTC) */
+        IRQ15_MARK,     IRQ14_MARK,     IRQ13_MARK,     IRQ12_MARK,
+        IRQ11_MARK,     IRQ10_MARK,     IRQ9_MARK,      IRQ8_MARK,
+
+        /* PTJ (mobule: SCIF234, SERMUX) */
+        RXD3_MARK,      TXD3_MARK,      RXD2_MARK,      TXD2_MARK,
+        COM1_TXD_MARK,  COM1_RXD_MARK,  COM1_RTS_MARK,  COM1_CTS_MARK,
+
+        /* PTK (mobule: SERMUX) */
+        COM2_TXD_MARK,  COM2_RXD_MARK,  COM2_RTS_MARK,  COM2_CTS_MARK,
+        COM2_DTR_MARK,  COM2_DSR_MARK,  COM2_DCD_MARK,  COM2_RI_MARK,
+
+        /* PTL (mobule: SERMUX) */
+        RAC_TXD_MARK,   RAC_RXD_MARK,   RAC_RTS_MARK,   RAC_CTS_MARK,
+        RAC_DTR_MARK,   RAC_DSR_MARK,   RAC_DCD_MARK,   RAC_RI_MARK,
+
+        /* PTM (mobule: IIC, LPC) */
+        SDA6_MARK,      SCL6_MARK,      SDA7_MARK,      SCL7_MARK,
+        WP_MARK,        FMS0_MARK,      FMS1_MARK,
+
+        /* PTN (mobule: SCIF234, EVC) */
+        SCK2_MARK,      RTS4_MARK,      RTS3_MARK,      RTS2_MARK,
+        CTS4_MARK,      CTS3_MARK,      CTS2_MARK,
+        EVENT7_MARK,    EVENT6_MARK,    EVENT5_MARK,    EVENT4_MARK,
+        EVENT3_MARK,    EVENT2_MARK,    EVENT1_MARK,    EVENT0_MARK,
+
+        /* PTO (mobule: SGPIO) */
+        SGPIO0_CLK_MARK,        SGPIO0_LOAD_MARK,
+        SGPIO0_DI_MARK,         SGPIO0_DO_MARK,
+        SGPIO1_CLK_MARK,        SGPIO1_LOAD_MARK,
+        SGPIO1_DI_MARK,         SGPIO1_DO_MARK,
+
+        /* PTP (mobule: JMC, SCIF234) */
+        JMCTCK_MARK,    JMCTMS_MARK,    JMCTDO_MARK,    JMCTDI_MARK,
+        JMCRST_MARK,    SCK4_MARK,      SCK3_MARK,
+
+        /* PTQ (mobule: LPC) */
+        LAD3_MARK,      LAD2_MARK,      LAD1_MARK,      LAD0_MARK,
+        LFRAME_MARK,    LRESET_MARK,    LCLK_MARK,
+
+        /* PTR (mobule: GRA, IIC) */
+        DDC3_MARK,      DDC2_MARK,
+        SDA8_MARK,      SCL8_MARK,      SDA2_MARK,      SCL2_MARK,
+        SDA1_MARK,      SCL1_MARK,      SDA0_MARK,      SCL0_MARK,
+
+        /* PTS (mobule: GRA, IIC) */
+        DDC1_MARK,      DDC0_MARK,
+        SDA9_MARK,      SCL9_MARK,      SDA5_MARK,      SCL5_MARK,
+        SDA4_MARK,      SCL4_MARK,      SDA3_MARK,      SCL3_MARK,
+
+        /* PTT (mobule: SYSTEM, PWMX) */
+        AUDSYNC_MARK,           AUDCK_MARK,
+        AUDATA3_MARK,           AUDATA2_MARK,
+        AUDATA1_MARK,           AUDATA0_MARK,
+        PWX7_MARK,      PWX6_MARK,      PWX5_MARK,      PWX4_MARK,
+
+        /* PTU (mobule: LBSC, DMAC) */
+        CS6_MARK,       CS5_MARK,       CS4_MARK,       CS0_MARK,
+        RD_MARK,        WE0_MARK,       A25_MARK,       A24_MARK,
+        DREQ0_MARK,     DACK0_MARK,
+
+        /* PTV (mobule: LBSC, DMAC) */
+        A23_MARK,       A22_MARK,       A21_MARK,       A20_MARK,
+        A19_MARK,       A18_MARK,       A17_MARK,       A16_MARK,
+        TEND0_MARK,     DREQ1_MARK,     DACK1_MARK,     TEND1_MARK,
+
+        /* PTW (mobule: LBSC) */
+        A15_MARK,       A14_MARK,       A13_MARK,       A12_MARK,
+        A11_MARK,       A10_MARK,       A9_MARK,        A8_MARK,
+
+        /* PTX (mobule: LBSC) */
+        A7_MARK,        A6_MARK,        A5_MARK,        A4_MARK,
+        A3_MARK,        A2_MARK,        A1_MARK,        A0_MARK,
+
+        /* PTY (mobule: LBSC) */
+        D7_MARK,        D6_MARK,        D5_MARK,        D4_MARK,
+        D3_MARK,        D2_MARK,        D1_MARK,        D0_MARK,
+        PINMUX_MARK_END,
+};
+
+static pinmux_enum_t pinmux_data[] = {
+        /* PTA GPIO */
+        PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT),
+        PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT),
+        PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT),
+        PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT),
+        PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT),
+        PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT),
+        PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT),
+        PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT),
+
+        /* PTB GPIO */
+        PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT),
+        PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT),
+        PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT),
+        PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT),
+        PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT),
+        PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT),
+        PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT),
+        PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT),
+
+        /* PTC GPIO */
+        PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT),
+        PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT),
+        PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT),
+        PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT),
+        PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT),
+        PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT),
+        PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT),
+        PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT),
+
+        /* PTD GPIO */
+        PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT),
+        PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT),
+        PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT),
+        PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT),
+        PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT),
+        PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT),
+        PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT),
+        PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT),
+
+        /* PTE GPIO */
+        PINMUX_DATA(PTE5_DATA, PTE5_IN, PTE5_OUT),
+        PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT),
+        PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT),
+        PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT),
+        PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT),
+        PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT),
+
+        /* PTF GPIO */
+        PINMUX_DATA(PTF7_DATA, PTF7_IN, PTF7_OUT),
+        PINMUX_DATA(PTF6_DATA, PTF6_IN, PTF6_OUT),
+        PINMUX_DATA(PTF5_DATA, PTF5_IN, PTF5_OUT),
+        PINMUX_DATA(PTF4_DATA, PTF4_IN, PTF4_OUT),
+        PINMUX_DATA(PTF3_DATA, PTF3_IN, PTF3_OUT),
+        PINMUX_DATA(PTF2_DATA, PTF2_IN, PTF2_OUT),
+        PINMUX_DATA(PTF1_DATA, PTF1_IN, PTF1_OUT),
+        PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT),
+
+        /* PTG GPIO */
+        PINMUX_DATA(PTG7_DATA, PTG7_IN, PTG7_OUT),
+        PINMUX_DATA(PTG6_DATA, PTG6_IN, PTG6_OUT),
+        PINMUX_DATA(PTG5_DATA, PTG5_IN, PTG5_OUT),
+        PINMUX_DATA(PTG4_DATA, PTG4_IN, PTG4_OUT),
+        PINMUX_DATA(PTG3_DATA, PTG3_IN, PTG3_OUT),
+        PINMUX_DATA(PTG2_DATA, PTG2_IN, PTG2_OUT),
+        PINMUX_DATA(PTG1_DATA, PTG1_IN, PTG1_OUT),
+        PINMUX_DATA(PTG0_DATA, PTG0_IN, PTG0_OUT),
+
+        /* PTH GPIO */
+        PINMUX_DATA(PTH7_DATA, PTH7_IN, PTH7_OUT),
+        PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT),
+        PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT),
+        PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT),
+        PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT),
+        PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT),
+        PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT),
+        PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT),
+
+        /* PTI GPIO */
+        PINMUX_DATA(PTI7_DATA, PTI7_IN, PTI7_OUT),
+        PINMUX_DATA(PTI6_DATA, PTI6_IN, PTI6_OUT),
+        PINMUX_DATA(PTI5_DATA, PTI5_IN, PTI5_OUT),
+        PINMUX_DATA(PTI4_DATA, PTI4_IN, PTI4_OUT),
+        PINMUX_DATA(PTI3_DATA, PTI3_IN, PTI3_OUT),
+        PINMUX_DATA(PTI2_DATA, PTI2_IN, PTI2_OUT),
+        PINMUX_DATA(PTI1_DATA, PTI1_IN, PTI1_OUT),
+        PINMUX_DATA(PTI0_DATA, PTI0_IN, PTI0_OUT),
+
+        /* PTJ GPIO */
+        PINMUX_DATA(PTJ7_DATA, PTJ7_IN, PTJ7_OUT),
+        PINMUX_DATA(PTJ6_DATA, PTJ6_IN, PTJ6_OUT),
+        PINMUX_DATA(PTJ5_DATA, PTJ5_IN, PTJ5_OUT),
+        PINMUX_DATA(PTJ4_DATA, PTJ4_IN, PTJ4_OUT),
+        PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT),
+        PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT),
+        PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT),
+        PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT),
+
+        /* PTK GPIO */
+        PINMUX_DATA(PTK7_DATA, PTK7_IN, PTK7_OUT),
+        PINMUX_DATA(PTK6_DATA, PTK6_IN, PTK6_OUT),
+        PINMUX_DATA(PTK5_DATA, PTK5_IN, PTK5_OUT),
+        PINMUX_DATA(PTK4_DATA, PTK4_IN, PTK4_OUT),
+        PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT),
+        PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT),
+        PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT),
+        PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT),
+
+        /* PTL GPIO */
+        PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT),
+        PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT),
+        PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT),
+        PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT),
+        PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT),
+        PINMUX_DATA(PTL2_DATA, PTL2_IN, PTL2_OUT),
+        PINMUX_DATA(PTL1_DATA, PTL1_IN, PTL1_OUT),
+        PINMUX_DATA(PTL0_DATA, PTL0_IN, PTL0_OUT),
+
+        /* PTM GPIO */
+        PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT),
+        PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT),
+        PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT),
+        PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT),
+        PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT),
+        PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT),
+        PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT),
+
+        /* PTN GPIO */
+        PINMUX_DATA(PTN7_DATA, PTN7_IN, PTN7_OUT),
+        PINMUX_DATA(PTN6_DATA, PTN6_IN, PTN6_OUT),
+        PINMUX_DATA(PTN5_DATA, PTN5_IN, PTN5_OUT),
+        PINMUX_DATA(PTN4_DATA, PTN4_IN, PTN4_OUT),
+        PINMUX_DATA(PTN3_DATA, PTN3_IN, PTN3_OUT),
+        PINMUX_DATA(PTN2_DATA, PTN2_IN, PTN2_OUT),
+        PINMUX_DATA(PTN1_DATA, PTN1_IN, PTN1_OUT),
+        PINMUX_DATA(PTN0_DATA, PTN0_IN, PTN0_OUT),
+
+        /* PTO GPIO */
+        PINMUX_DATA(PTO7_DATA, PTO7_IN, PTO7_OUT),
+        PINMUX_DATA(PTO6_DATA, PTO6_IN, PTO6_OUT),
+        PINMUX_DATA(PTO5_DATA, PTO5_IN, PTO5_OUT),
+        PINMUX_DATA(PTO4_DATA, PTO4_IN, PTO4_OUT),
+        PINMUX_DATA(PTO3_DATA, PTO3_IN, PTO3_OUT),
+        PINMUX_DATA(PTO2_DATA, PTO2_IN, PTO2_OUT),
+        PINMUX_DATA(PTO1_DATA, PTO1_IN, PTO1_OUT),
+        PINMUX_DATA(PTO0_DATA, PTO0_IN, PTO0_OUT),
+
+        /* PTQ GPIO */
+        PINMUX_DATA(PTQ6_DATA, PTQ6_IN, PTQ6_OUT),
+        PINMUX_DATA(PTQ5_DATA, PTQ5_IN, PTQ5_OUT),
+        PINMUX_DATA(PTQ4_DATA, PTQ4_IN, PTQ4_OUT),
+        PINMUX_DATA(PTQ3_DATA, PTQ3_IN, PTQ3_OUT),
+        PINMUX_DATA(PTQ2_DATA, PTQ2_IN, PTQ2_OUT),
+        PINMUX_DATA(PTQ1_DATA, PTQ1_IN, PTQ1_OUT),
+        PINMUX_DATA(PTQ0_DATA, PTQ0_IN, PTQ0_OUT),
+
+        /* PTR GPIO */
+        PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT),
+        PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT),
+        PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT),
+        PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT),
+        PINMUX_DATA(PTR3_DATA, PTR3_IN, PTR3_OUT),
+        PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_OUT),
+        PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT),
+        PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT),
+
+        /* PTS GPIO */
+        PINMUX_DATA(PTS7_DATA, PTS7_IN, PTS7_OUT),
+        PINMUX_DATA(PTS6_DATA, PTS6_IN, PTS6_OUT),
+        PINMUX_DATA(PTS5_DATA, PTS5_IN, PTS5_OUT),
+        PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT),
+        PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT),
+        PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT),
+        PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT),
+        PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT),
+
+        /* PTT GPIO */
+        PINMUX_DATA(PTT5_DATA, PTT5_IN, PTT5_OUT),
+        PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT),
+        PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT),
+        PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT),
+        PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT),
+        PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT),
+
+        /* PTU GPIO */
+        PINMUX_DATA(PTU7_DATA, PTU7_IN, PTU7_OUT),
+        PINMUX_DATA(PTU6_DATA, PTU6_IN, PTU6_OUT),
+        PINMUX_DATA(PTU5_DATA, PTU5_IN, PTU5_OUT),
+        PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT),
+        PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT),
+        PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT),
+        PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT),
+        PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT),
+
+        /* PTV GPIO */
+        PINMUX_DATA(PTV7_DATA, PTV7_IN, PTV7_OUT),
+        PINMUX_DATA(PTV6_DATA, PTV6_IN, PTV6_OUT),
+        PINMUX_DATA(PTV5_DATA, PTV5_IN, PTV5_OUT),
+        PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT),
+        PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT),
+        PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT),
+        PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT),
+        PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT),
+
+        /* PTW GPIO */
+        PINMUX_DATA(PTW7_DATA, PTW7_IN, PTW7_OUT),
+        PINMUX_DATA(PTW6_DATA, PTW6_IN, PTW6_OUT),
+        PINMUX_DATA(PTW5_DATA, PTW5_IN, PTW5_OUT),
+        PINMUX_DATA(PTW4_DATA, PTW4_IN, PTW4_OUT),
+        PINMUX_DATA(PTW3_DATA, PTW3_IN, PTW3_OUT),
+        PINMUX_DATA(PTW2_DATA, PTW2_IN, PTW2_OUT),
+        PINMUX_DATA(PTW1_DATA, PTW1_IN, PTW1_OUT),
+        PINMUX_DATA(PTW0_DATA, PTW0_IN, PTW0_OUT),
+
+        /* PTX GPIO */
+        PINMUX_DATA(PTX7_DATA, PTX7_IN, PTX7_OUT),
+        PINMUX_DATA(PTX6_DATA, PTX6_IN, PTX6_OUT),
+        PINMUX_DATA(PTX5_DATA, PTX5_IN, PTX5_OUT),
+        PINMUX_DATA(PTX4_DATA, PTX4_IN, PTX4_OUT),
+        PINMUX_DATA(PTX3_DATA, PTX3_IN, PTX3_OUT),
+        PINMUX_DATA(PTX2_DATA, PTX2_IN, PTX2_OUT),
+        PINMUX_DATA(PTX1_DATA, PTX1_IN, PTX1_OUT),
+        PINMUX_DATA(PTX0_DATA, PTX0_IN, PTX0_OUT),
+
+        /* PTY GPIO */
+        PINMUX_DATA(PTY7_DATA, PTY7_IN, PTY7_OUT),
+        PINMUX_DATA(PTY6_DATA, PTY6_IN, PTY6_OUT),
+        PINMUX_DATA(PTY5_DATA, PTY5_IN, PTY5_OUT),
+        PINMUX_DATA(PTY4_DATA, PTY4_IN, PTY4_OUT),
+        PINMUX_DATA(PTY3_DATA, PTY3_IN, PTY3_OUT),
+        PINMUX_DATA(PTY2_DATA, PTY2_IN, PTY2_OUT),
+        PINMUX_DATA(PTY1_DATA, PTY1_IN, PTY1_OUT),
+        PINMUX_DATA(PTY0_DATA, PTY0_IN, PTY0_OUT),
+
+        /* PTZ GPIO */
+        PINMUX_DATA(PTZ7_DATA, PTZ7_IN, PTZ7_OUT),
+        PINMUX_DATA(PTZ6_DATA, PTZ6_IN, PTZ6_OUT),
+        PINMUX_DATA(PTZ5_DATA, PTZ5_IN, PTZ5_OUT),
+        PINMUX_DATA(PTZ4_DATA, PTZ4_IN, PTZ4_OUT),
+        PINMUX_DATA(PTZ3_DATA, PTZ3_IN, PTZ3_OUT),
+        PINMUX_DATA(PTZ2_DATA, PTZ2_IN, PTZ2_OUT),
+        PINMUX_DATA(PTZ1_DATA, PTZ1_IN, PTZ1_OUT),
+        PINMUX_DATA(PTZ0_DATA, PTZ0_IN, PTZ0_OUT),
+
+        /* PTA FN */
+        PINMUX_DATA(BS_MARK, PS0_15_FN1, PTA7_FN),
+        PINMUX_DATA(LGPIO7_MARK, PS0_15_FN3, PTA7_FN),
+        PINMUX_DATA(RDWR_MARK, PS0_14_FN1, PTA6_FN),
+        PINMUX_DATA(LGPIO6_MARK, PS0_14_FN3, PTA6_FN),
+        PINMUX_DATA(WE1_MARK, PS0_13_FN1, PTA5_FN),
+        PINMUX_DATA(LGPIO5_MARK, PS0_13_FN3, PTA5_FN),
+        PINMUX_DATA(RDY_MARK, PS0_12_FN1, PTA4_FN),
+        PINMUX_DATA(LGPIO4_MARK, PS0_12_FN3, PTA4_FN),
+        PINMUX_DATA(LGPIO3_MARK, PTA3_FN),
+        PINMUX_DATA(LGPIO2_MARK, PTA2_FN),
+        PINMUX_DATA(LGPIO1_MARK, PTA1_FN),
+        PINMUX_DATA(LGPIO0_MARK, PTA0_FN),
+
+        /* PTB FN */
+        PINMUX_DATA(D15_MARK, PS0_7_FN1, PTB7_FN),
+        PINMUX_DATA(ET0_MDC_MARK, PS0_7_FN2, PTB7_FN),
+        PINMUX_DATA(D14_MARK, PS0_6_FN1, PTB6_FN),
+        PINMUX_DATA(ET0_MDIO_MARK, PS0_6_FN2, PTB6_FN),
+        PINMUX_DATA(D13_MARK, PS0_5_FN1, PTB5_FN),
+        PINMUX_DATA(ET1_MDC_MARK, PS0_5_FN2, PTB5_FN),
+        PINMUX_DATA(D12_MARK, PS0_4_FN1, PTB4_FN),
+        PINMUX_DATA(ET1_MDIO_MARK, PS0_4_FN2, PTB4_FN),
+        PINMUX_DATA(D11_MARK, PS0_3_FN1, PTB3_FN),
+        PINMUX_DATA(SIM_D_MARK, PS0_3_FN2, PTB3_FN),
+        PINMUX_DATA(D10_MARK, PS0_2_FN1, PTB2_FN),
+        PINMUX_DATA(SIM_CLK_MARK, PS0_2_FN2, PTB2_FN),
+        PINMUX_DATA(D9_MARK, PS0_1_FN1, PTB1_FN),
+        PINMUX_DATA(SIM_RST_MARK, PS0_1_FN2, PTB1_FN),
+        PINMUX_DATA(D8_MARK, PTB0_FN),
+
+        /* PTC FN */
+        PINMUX_DATA(SD_WP_MARK, PTC7_FN),
+        PINMUX_DATA(SD_CD_MARK, PTC6_FN),
+        PINMUX_DATA(SD_CLK_MARK, PTC5_FN),
+        PINMUX_DATA(SD_CMD_MARK, PTC4_FN),
+        PINMUX_DATA(SD_D3_MARK, PTC3_FN),
+        PINMUX_DATA(SD_D2_MARK, PTC2_FN),
+        PINMUX_DATA(SD_D1_MARK, PTC1_FN),
+        PINMUX_DATA(SD_D0_MARK, PTC0_FN),
+
+        /* PTD FN */
+        PINMUX_DATA(IRQ7_MARK, PS1_7_FN1, PTD7_FN),
+        PINMUX_DATA(ADTRG1_MARK, PS1_7_FN3, PTD7_FN),
+        PINMUX_DATA(IRQ6_MARK, PS1_6_FN1, PTD6_FN),
+        PINMUX_DATA(ADTRG0_MARK, PS1_6_FN3, PTD6_FN),
+        PINMUX_DATA(IRQ5_MARK, PTD5_FN),
+        PINMUX_DATA(IRQ4_MARK, PTD4_FN),
+        PINMUX_DATA(IRQ3_MARK, PTD3_FN),
+        PINMUX_DATA(IRQ2_MARK, PTD2_FN),
+        PINMUX_DATA(IRQ1_MARK, PTD1_FN),
+        PINMUX_DATA(IRQ0_MARK, PTD0_FN),
+
+        /* PTE FN */
+        PINMUX_DATA(ET0_CRS_DV_MARK, PTE7_FN),
+        PINMUX_DATA(ET0_TXD1_MARK, PTE6_FN),
+        PINMUX_DATA(ET0_TXD0_MARK, PTE5_FN),
+        PINMUX_DATA(ET0_TX_EN_MARK, PTE4_FN),
+        PINMUX_DATA(ET0_REF_CLK_MARK, PTE3_FN),
+        PINMUX_DATA(ET0_RXD1_MARK, PTE2_FN),
+        PINMUX_DATA(ET0_RXD0_MARK, PTE1_FN),
+        PINMUX_DATA(ET0_RX_ER_MARK, PTE0_FN),
+
+        /* PTF FN */
+        PINMUX_DATA(ET1_CRS_DV_MARK, PTF7_FN),
+        PINMUX_DATA(ET1_TXD1_MARK, PTF6_FN),
+        PINMUX_DATA(ET1_TXD0_MARK, PTF5_FN),
+        PINMUX_DATA(ET1_TX_EN_MARK, PTF4_FN),
+        PINMUX_DATA(ET1_REF_CLK_MARK, PTF3_FN),
+        PINMUX_DATA(ET1_RXD1_MARK, PTF2_FN),
+        PINMUX_DATA(ET1_RXD0_MARK, PTF1_FN),
+        PINMUX_DATA(ET1_RX_ER_MARK, PTF0_FN),
+
+        /* PTG FN */
+        PINMUX_DATA(PWX0_MARK, PTG7_FN),
+        PINMUX_DATA(PWX1_MARK, PTG6_FN),
+        PINMUX_DATA(STATUS0_MARK, PS2_13_FN1, PTG5_FN),
+        PINMUX_DATA(PWX2_MARK, PS2_13_FN3, PTG5_FN),
+        PINMUX_DATA(STATUS1_MARK, PS2_12_FN1, PTG4_FN),
+        PINMUX_DATA(PWX3_MARK, PS2_12_FN3, PTG4_FN),
+        PINMUX_DATA(SERIRQ_MARK, PTG3_FN),
+        PINMUX_DATA(CLKRUN_MARK, PTG2_FN),
+        PINMUX_DATA(LPCPD_MARK, PTG1_FN),
+        PINMUX_DATA(LDRQ_MARK, PTG0_FN),
+
+        /* PTH FN */
+        PINMUX_DATA(SP1_MOSI_MARK, PTH7_FN),
+        PINMUX_DATA(SP1_MISO_MARK, PTH6_FN),
+        PINMUX_DATA(SP1_SCK_MARK, PTH5_FN),
+        PINMUX_DATA(SP1_SCK_FB_MARK, PTH4_FN),
+        PINMUX_DATA(SP1_SS0_MARK, PTH3_FN),
+        PINMUX_DATA(TCLK_MARK, PTH2_FN),
+        PINMUX_DATA(RXD4_MARK, PS2_1_FN1, PTH1_FN),
+        PINMUX_DATA(SP1_SS1_MARK, PS2_1_FN2, PTH1_FN),
+        PINMUX_DATA(TXD4_MARK, PS2_0_FN1, PTH0_FN),
+        PINMUX_DATA(SP0_SS1_MARK, PS2_0_FN2, PTH0_FN),
+
+        /* PTI FN */
+        PINMUX_DATA(IRQ15_MARK, PTI7_FN),
+        PINMUX_DATA(IRQ14_MARK, PTI6_FN),
+        PINMUX_DATA(IRQ13_MARK, PTI5_FN),
+        PINMUX_DATA(IRQ12_MARK, PTI4_FN),
+        PINMUX_DATA(IRQ11_MARK, PTI3_FN),
+        PINMUX_DATA(IRQ10_MARK, PTI2_FN),
+        PINMUX_DATA(IRQ9_MARK, PTI1_FN),
+        PINMUX_DATA(IRQ8_MARK, PTI0_FN),
+
+        /* PTJ FN */
+        PINMUX_DATA(RXD3_MARK, PTJ7_FN),
+        PINMUX_DATA(TXD3_MARK, PTJ6_FN),
+        PINMUX_DATA(RXD2_MARK, PTJ5_FN),
+        PINMUX_DATA(TXD2_MARK, PTJ4_FN),
+        PINMUX_DATA(COM1_TXD_MARK, PTJ3_FN),
+        PINMUX_DATA(COM1_RXD_MARK, PTJ2_FN),
+        PINMUX_DATA(COM1_RTS_MARK, PTJ1_FN),
+        PINMUX_DATA(COM1_CTS_MARK, PTJ0_FN),
+
+        /* PTK FN */
+        PINMUX_DATA(COM2_TXD_MARK, PTK7_FN),
+        PINMUX_DATA(COM2_RXD_MARK, PTK6_FN),
+        PINMUX_DATA(COM2_RTS_MARK, PTK5_FN),
+        PINMUX_DATA(COM2_CTS_MARK, PTK4_FN),
+        PINMUX_DATA(COM2_DTR_MARK, PTK3_FN),
+        PINMUX_DATA(COM2_DSR_MARK, PTK2_FN),
+        PINMUX_DATA(COM2_DCD_MARK, PTK1_FN),
+        PINMUX_DATA(COM2_RI_MARK, PTK0_FN),
+
+        /* PTL FN */
+        PINMUX_DATA(RAC_TXD_MARK, PTL7_FN),
+        PINMUX_DATA(RAC_RXD_MARK, PTL6_FN),
+        PINMUX_DATA(RAC_RTS_MARK, PTL5_FN),
+        PINMUX_DATA(RAC_CTS_MARK, PTL4_FN),
+        PINMUX_DATA(RAC_DTR_MARK, PTL3_FN),
+        PINMUX_DATA(RAC_DSR_MARK, PTL2_FN),
+        PINMUX_DATA(RAC_DCD_MARK, PTL1_FN),
+        PINMUX_DATA(RAC_RI_MARK, PTL0_FN),
+
+        /* PTM FN */
+        PINMUX_DATA(WP_MARK, PTM6_FN),
+        PINMUX_DATA(FMS0_MARK, PTM5_FN),
+        PINMUX_DATA(FMS1_MARK, PTM4_FN),
+        PINMUX_DATA(SDA6_MARK, PTM3_FN),
+        PINMUX_DATA(SCL6_MARK, PTM2_FN),
+        PINMUX_DATA(SDA7_MARK, PTM1_FN),
+        PINMUX_DATA(SCL7_MARK, PTM0_FN),
+
+        /* PTN FN */
+        PINMUX_DATA(SCK2_MARK, PS4_15_FN1, PTN7_FN),
+        PINMUX_DATA(EVENT7_MARK, PS4_15_FN2, PTN7_FN),
+        PINMUX_DATA(RTS4_MARK, PS4_14_FN1, PTN6_FN),
+        PINMUX_DATA(EVENT6_MARK, PS4_14_FN2, PTN6_FN),
+        PINMUX_DATA(RTS3_MARK, PS4_13_FN1, PTN5_FN),
+        PINMUX_DATA(EVENT5_MARK, PS4_13_FN2, PTN5_FN),
+        PINMUX_DATA(RTS2_MARK, PS4_12_FN1, PTN4_FN),
+        PINMUX_DATA(EVENT4_MARK, PS4_12_FN2, PTN4_FN),
+        PINMUX_DATA(CTS4_MARK, PS4_11_FN1, PTN3_FN),
+        PINMUX_DATA(EVENT3_MARK, PS4_11_FN2, PTN3_FN),
+        PINMUX_DATA(CTS3_MARK, PS4_10_FN1, PTN2_FN),
+        PINMUX_DATA(EVENT2_MARK, PS4_10_FN2, PTN2_FN),
+        PINMUX_DATA(CTS2_MARK, PS4_9_FN1, PTN1_FN),
+        PINMUX_DATA(EVENT1_MARK, PS4_9_FN2, PTN1_FN),
+        PINMUX_DATA(EVENT0_MARK, PTN0_FN),
+
+        /* PTO FN */
+        PINMUX_DATA(SGPIO0_CLK_MARK, PTO7_FN),
+        PINMUX_DATA(SGPIO0_LOAD_MARK, PTO6_FN),
+        PINMUX_DATA(SGPIO0_DI_MARK, PTO5_FN),
+        PINMUX_DATA(SGPIO0_DO_MARK, PTO4_FN),
+        PINMUX_DATA(SGPIO1_CLK_MARK, PTO3_FN),
+        PINMUX_DATA(SGPIO1_LOAD_MARK, PTO2_FN),
+        PINMUX_DATA(SGPIO1_DI_MARK, PTO1_FN),
+        PINMUX_DATA(SGPIO1_DO_MARK, PTO0_FN),
+
+        /* PTP FN */
+        PINMUX_DATA(JMCTCK_MARK, PTP6_FN),
+        PINMUX_DATA(JMCTMS_MARK, PTP5_FN),
+        PINMUX_DATA(JMCTDO_MARK, PTP4_FN),
+        PINMUX_DATA(JMCTDI_MARK, PTP3_FN),
+        PINMUX_DATA(JMCRST_MARK, PTP2_FN),
+        PINMUX_DATA(SCK4_MARK, PTP1_FN),
+        PINMUX_DATA(SCK3_MARK, PTP0_FN),
+
+        /* PTQ FN */
+        PINMUX_DATA(LAD3_MARK, PTQ6_FN),
+        PINMUX_DATA(LAD2_MARK, PTQ5_FN),
+        PINMUX_DATA(LAD1_MARK, PTQ4_FN),
+        PINMUX_DATA(LAD0_MARK, PTQ3_FN),
+        PINMUX_DATA(LFRAME_MARK, PTQ2_FN),
+        PINMUX_DATA(SCK4_MARK, PTQ1_FN),
+        PINMUX_DATA(SCK3_MARK, PTQ0_FN),
+
+        /* PTR FN */
+        PINMUX_DATA(SDA8_MARK, PTR7_FN),        /* DDC3? */
+        PINMUX_DATA(SCL8_MARK, PTR6_FN),        /* DDC2? */
+        PINMUX_DATA(SDA2_MARK, PTR5_FN),
+        PINMUX_DATA(SCL2_MARK, PTR4_FN),
+        PINMUX_DATA(SDA1_MARK, PTR3_FN),
+        PINMUX_DATA(SCL1_MARK, PTR2_FN),
+        PINMUX_DATA(SDA0_MARK, PTR1_FN),
+        PINMUX_DATA(SCL0_MARK, PTR0_FN),
+
+        /* PTS FN */
+        PINMUX_DATA(SDA9_MARK, PTS7_FN),        /* DDC1? */
+        PINMUX_DATA(SCL9_MARK, PTS6_FN),        /* DDC0? */
+        PINMUX_DATA(SDA5_MARK, PTS5_FN),
+        PINMUX_DATA(SCL5_MARK, PTS4_FN),
+        PINMUX_DATA(SDA4_MARK, PTS3_FN),
+        PINMUX_DATA(SCL4_MARK, PTS2_FN),
+        PINMUX_DATA(SDA3_MARK, PTS1_FN),
+        PINMUX_DATA(SCL3_MARK, PTS0_FN),
+
+        /* PTT FN */
+        PINMUX_DATA(AUDSYNC_MARK, PTS5_FN),
+        PINMUX_DATA(AUDCK_MARK, PTS4_FN),
+        PINMUX_DATA(AUDATA3_MARK, PS4_3_FN1, PTS3_FN),
+        PINMUX_DATA(PWX7_MARK, PS4_3_FN2, PTS3_FN),
+        PINMUX_DATA(AUDATA2_MARK, PS4_2_FN1, PTS2_FN),
+        PINMUX_DATA(PWX6_MARK, PS4_2_FN2, PTS2_FN),
+        PINMUX_DATA(AUDATA1_MARK, PS4_1_FN1, PTS1_FN),
+        PINMUX_DATA(PWX5_MARK, PS4_1_FN2, PTS1_FN),
+        PINMUX_DATA(AUDATA0_MARK, PS4_0_FN1, PTS0_FN),
+        PINMUX_DATA(PWX4_MARK, PS4_0_FN2, PTS0_FN),
+
+        /* PTU FN */
+        PINMUX_DATA(CS6_MARK, PTU7_FN),
+        PINMUX_DATA(CS5_MARK, PTU6_FN),
+        PINMUX_DATA(CS4_MARK, PTU5_FN),
+        PINMUX_DATA(CS0_MARK, PTU4_FN),
+        PINMUX_DATA(RD_MARK, PTU3_FN),
+        PINMUX_DATA(WE0_MARK, PTU2_FN),
+        PINMUX_DATA(A25_MARK, PS5_9_FN1, PTU1_FN),
+        PINMUX_DATA(DREQ0_MARK, PS5_9_FN2, PTU1_FN),
+        PINMUX_DATA(A24_MARK, PS5_8_FN1, PTU0_FN),
+        PINMUX_DATA(DACK0_MARK, PS5_8_FN2, PTU0_FN),
+
+        /* PTV FN */
+        PINMUX_DATA(A23_MARK, PS5_7_FN1, PTV7_FN),
+        PINMUX_DATA(TEND0_MARK, PS5_7_FN2, PTV7_FN),
+        PINMUX_DATA(A22_MARK, PS5_6_FN1, PTV6_FN),
+        PINMUX_DATA(DREQ1_MARK, PS5_6_FN2, PTV6_FN),
+        PINMUX_DATA(A21_MARK, PS5_5_FN1, PTV5_FN),
+        PINMUX_DATA(DACK1_MARK, PS5_5_FN2, PTV5_FN),
+        PINMUX_DATA(A20_MARK, PS5_4_FN1, PTV4_FN),
+        PINMUX_DATA(TEND1_MARK, PS5_4_FN2, PTV4_FN),
+        PINMUX_DATA(A19_MARK, PTV3_FN),
+        PINMUX_DATA(A18_MARK, PTV2_FN),
+        PINMUX_DATA(A17_MARK, PTV1_FN),
+        PINMUX_DATA(A16_MARK, PTV0_FN),
+
+        /* PTW FN */
+        PINMUX_DATA(A15_MARK, PTW7_FN),
+        PINMUX_DATA(A14_MARK, PTW6_FN),
+        PINMUX_DATA(A13_MARK, PTW5_FN),
+        PINMUX_DATA(A12_MARK, PTW4_FN),
+        PINMUX_DATA(A11_MARK, PTW3_FN),
+        PINMUX_DATA(A10_MARK, PTW2_FN),
+        PINMUX_DATA(A9_MARK, PTW1_FN),
+        PINMUX_DATA(A8_MARK, PTW0_FN),
+
+        /* PTX FN */
+        PINMUX_DATA(A7_MARK, PTX7_FN),
+        PINMUX_DATA(A6_MARK, PTX6_FN),
+        PINMUX_DATA(A5_MARK, PTX5_FN),
+        PINMUX_DATA(A4_MARK, PTX4_FN),
+        PINMUX_DATA(A3_MARK, PTX3_FN),
+        PINMUX_DATA(A2_MARK, PTX2_FN),
+        PINMUX_DATA(A1_MARK, PTX1_FN),
+        PINMUX_DATA(A0_MARK, PTX0_FN),
+
+        /* PTY FN */
+        PINMUX_DATA(D7_MARK, PTY7_FN),
+        PINMUX_DATA(D6_MARK, PTY6_FN),
+        PINMUX_DATA(D5_MARK, PTY5_FN),
+        PINMUX_DATA(D4_MARK, PTY4_FN),
+        PINMUX_DATA(D3_MARK, PTY3_FN),
+        PINMUX_DATA(D2_MARK, PTY2_FN),
+        PINMUX_DATA(D1_MARK, PTY1_FN),
+        PINMUX_DATA(D0_MARK, PTY0_FN),
+};
+
+static struct pinmux_gpio pinmux_gpios[] = {
+        /* PTA */
+        PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
+        PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
+        PINMUX_GPIO(GPIO_PTA5, PTA5_DATA),
+        PINMUX_GPIO(GPIO_PTA4, PTA4_DATA),
+        PINMUX_GPIO(GPIO_PTA3, PTA3_DATA),
+        PINMUX_GPIO(GPIO_PTA2, PTA2_DATA),
+        PINMUX_GPIO(GPIO_PTA1, PTA1_DATA),
+        PINMUX_GPIO(GPIO_PTA0, PTA0_DATA),
+
+        /* PTB */
+        PINMUX_GPIO(GPIO_PTB7, PTB7_DATA),
+        PINMUX_GPIO(GPIO_PTB6, PTB6_DATA),
+        PINMUX_GPIO(GPIO_PTB5, PTB5_DATA),
+        PINMUX_GPIO(GPIO_PTB4, PTB4_DATA),
+        PINMUX_GPIO(GPIO_PTB3, PTB3_DATA),
+        PINMUX_GPIO(GPIO_PTB2, PTB2_DATA),
+        PINMUX_GPIO(GPIO_PTB1, PTB1_DATA),
+        PINMUX_GPIO(GPIO_PTB0, PTB0_DATA),
+
+        /* PTC */
+        PINMUX_GPIO(GPIO_PTC7, PTC7_DATA),
+        PINMUX_GPIO(GPIO_PTC6, PTC6_DATA),
+        PINMUX_GPIO(GPIO_PTC5, PTC5_DATA),
+        PINMUX_GPIO(GPIO_PTC4, PTC4_DATA),
+        PINMUX_GPIO(GPIO_PTC3, PTC3_DATA),
+        PINMUX_GPIO(GPIO_PTC2, PTC2_DATA),
+        PINMUX_GPIO(GPIO_PTC1, PTC1_DATA),
+        PINMUX_GPIO(GPIO_PTC0, PTC0_DATA),
+
+        /* PTD */
+        PINMUX_GPIO(GPIO_PTD7, PTD7_DATA),
+        PINMUX_GPIO(GPIO_PTD6, PTD6_DATA),
+        PINMUX_GPIO(GPIO_PTD5, PTD5_DATA),
+        PINMUX_GPIO(GPIO_PTD4, PTD4_DATA),
+        PINMUX_GPIO(GPIO_PTD3, PTD3_DATA),
+        PINMUX_GPIO(GPIO_PTD2, PTD2_DATA),
+        PINMUX_GPIO(GPIO_PTD1, PTD1_DATA),
+        PINMUX_GPIO(GPIO_PTD0, PTD0_DATA),
+
+        /* PTE */
+        PINMUX_GPIO(GPIO_PTE7, PTE7_DATA),
+        PINMUX_GPIO(GPIO_PTE6, PTE6_DATA),
+        PINMUX_GPIO(GPIO_PTE5, PTE5_DATA),
+        PINMUX_GPIO(GPIO_PTE4, PTE4_DATA),
+        PINMUX_GPIO(GPIO_PTE3, PTE3_DATA),
+        PINMUX_GPIO(GPIO_PTE2, PTE2_DATA),
+        PINMUX_GPIO(GPIO_PTE1, PTE1_DATA),
+        PINMUX_GPIO(GPIO_PTE0, PTE0_DATA),
+
+        /* PTF */
+        PINMUX_GPIO(GPIO_PTF7, PTF7_DATA),
+        PINMUX_GPIO(GPIO_PTF6, PTF6_DATA),
+        PINMUX_GPIO(GPIO_PTF5, PTF5_DATA),
+        PINMUX_GPIO(GPIO_PTF4, PTF4_DATA),
+        PINMUX_GPIO(GPIO_PTF3, PTF3_DATA),
+        PINMUX_GPIO(GPIO_PTF2, PTF2_DATA),
+        PINMUX_GPIO(GPIO_PTF1, PTF1_DATA),
+        PINMUX_GPIO(GPIO_PTF0, PTF0_DATA),
+
+        /* PTG */
+        PINMUX_GPIO(GPIO_PTG7, PTG7_DATA),
+        PINMUX_GPIO(GPIO_PTG6, PTG6_DATA),
+        PINMUX_GPIO(GPIO_PTG5, PTG5_DATA),
+        PINMUX_GPIO(GPIO_PTG4, PTG4_DATA),
+        PINMUX_GPIO(GPIO_PTG3, PTG3_DATA),
+        PINMUX_GPIO(GPIO_PTG2, PTG2_DATA),
+        PINMUX_GPIO(GPIO_PTG1, PTG1_DATA),
+        PINMUX_GPIO(GPIO_PTG0, PTG0_DATA),
+
+        /* PTH */
+        PINMUX_GPIO(GPIO_PTH7, PTH7_DATA),
+        PINMUX_GPIO(GPIO_PTH6, PTH6_DATA),
+        PINMUX_GPIO(GPIO_PTH5, PTH5_DATA),
+        PINMUX_GPIO(GPIO_PTH4, PTH4_DATA),
+        PINMUX_GPIO(GPIO_PTH3, PTH3_DATA),
+        PINMUX_GPIO(GPIO_PTH2, PTH2_DATA),
+        PINMUX_GPIO(GPIO_PTH1, PTH1_DATA),
+        PINMUX_GPIO(GPIO_PTH0, PTH0_DATA),
+
+        /* PTI */
+        PINMUX_GPIO(GPIO_PTI7, PTI7_DATA),
+        PINMUX_GPIO(GPIO_PTI6, PTI6_DATA),
+        PINMUX_GPIO(GPIO_PTI5, PTI5_DATA),
+        PINMUX_GPIO(GPIO_PTI4, PTI4_DATA),
+        PINMUX_GPIO(GPIO_PTI3, PTI3_DATA),
+        PINMUX_GPIO(GPIO_PTI2, PTI2_DATA),
+        PINMUX_GPIO(GPIO_PTI1, PTI1_DATA),
+        PINMUX_GPIO(GPIO_PTI0, PTI0_DATA),
+
+        /* PTJ */
+        PINMUX_GPIO(GPIO_PTJ7, PTJ7_DATA),
+        PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA),
+        PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA),
+        PINMUX_GPIO(GPIO_PTJ4, PTJ4_DATA),
+        PINMUX_GPIO(GPIO_PTJ3, PTJ3_DATA),
+        PINMUX_GPIO(GPIO_PTJ2, PTJ2_DATA),
+        PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA),
+        PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA),
+
+        /* PTK */
+        PINMUX_GPIO(GPIO_PTK7, PTK7_DATA),
+        PINMUX_GPIO(GPIO_PTK6, PTK6_DATA),
+        PINMUX_GPIO(GPIO_PTK5, PTK5_DATA),
+        PINMUX_GPIO(GPIO_PTK4, PTK4_DATA),
+        PINMUX_GPIO(GPIO_PTK3, PTK3_DATA),
+        PINMUX_GPIO(GPIO_PTK2, PTK2_DATA),
+        PINMUX_GPIO(GPIO_PTK1, PTK1_DATA),
+        PINMUX_GPIO(GPIO_PTK0, PTK0_DATA),
+
+        /* PTL */
+        PINMUX_GPIO(GPIO_PTL7, PTL7_DATA),
+        PINMUX_GPIO(GPIO_PTL6, PTL6_DATA),
+        PINMUX_GPIO(GPIO_PTL5, PTL5_DATA),
+        PINMUX_GPIO(GPIO_PTL4, PTL4_DATA),
+        PINMUX_GPIO(GPIO_PTL3, PTL3_DATA),
+        PINMUX_GPIO(GPIO_PTL2, PTL2_DATA),
+        PINMUX_GPIO(GPIO_PTL1, PTL1_DATA),
+        PINMUX_GPIO(GPIO_PTL0, PTL0_DATA),
+
+        /* PTM */
+        PINMUX_GPIO(GPIO_PTM6, PTM6_DATA),
+        PINMUX_GPIO(GPIO_PTM5, PTM5_DATA),
+        PINMUX_GPIO(GPIO_PTM4, PTM4_DATA),
+        PINMUX_GPIO(GPIO_PTM3, PTM3_DATA),
+        PINMUX_GPIO(GPIO_PTM2, PTM2_DATA),
+        PINMUX_GPIO(GPIO_PTM1, PTM1_DATA),
+        PINMUX_GPIO(GPIO_PTM0, PTM0_DATA),
+
+        /* PTN */
+        PINMUX_GPIO(GPIO_PTN7, PTN7_DATA),
+        PINMUX_GPIO(GPIO_PTN6, PTN6_DATA),
+        PINMUX_GPIO(GPIO_PTN5, PTN5_DATA),
+        PINMUX_GPIO(GPIO_PTN4, PTN4_DATA),
+        PINMUX_GPIO(GPIO_PTN3, PTN3_DATA),
+        PINMUX_GPIO(GPIO_PTN2, PTN2_DATA),
+        PINMUX_GPIO(GPIO_PTN1, PTN1_DATA),
+        PINMUX_GPIO(GPIO_PTN0, PTN0_DATA),
+
+        /* PTO */
+        PINMUX_GPIO(GPIO_PTO7, PTO7_DATA),
+        PINMUX_GPIO(GPIO_PTO6, PTO6_DATA),
+        PINMUX_GPIO(GPIO_PTO5, PTO5_DATA),
+        PINMUX_GPIO(GPIO_PTO4, PTO4_DATA),
+        PINMUX_GPIO(GPIO_PTO3, PTO3_DATA),
+        PINMUX_GPIO(GPIO_PTO2, PTO2_DATA),
+        PINMUX_GPIO(GPIO_PTO1, PTO1_DATA),
+        PINMUX_GPIO(GPIO_PTO0, PTO0_DATA),
+
+        /* PTP */
+        PINMUX_GPIO(GPIO_PTP6, PTP6_DATA),
+        PINMUX_GPIO(GPIO_PTP5, PTP5_DATA),
+        PINMUX_GPIO(GPIO_PTP4, PTP4_DATA),
+        PINMUX_GPIO(GPIO_PTP3, PTP3_DATA),
+        PINMUX_GPIO(GPIO_PTP2, PTP2_DATA),
+        PINMUX_GPIO(GPIO_PTP1, PTP1_DATA),
+        PINMUX_GPIO(GPIO_PTP0, PTP0_DATA),
+
+        /* PTQ */
+        PINMUX_GPIO(GPIO_PTQ6, PTQ6_DATA),
+        PINMUX_GPIO(GPIO_PTQ5, PTQ5_DATA),
+        PINMUX_GPIO(GPIO_PTQ4, PTQ4_DATA),
+        PINMUX_GPIO(GPIO_PTQ3, PTQ3_DATA),
+        PINMUX_GPIO(GPIO_PTQ2, PTQ2_DATA),
+        PINMUX_GPIO(GPIO_PTQ1, PTQ1_DATA),
+        PINMUX_GPIO(GPIO_PTQ0, PTQ0_DATA),
+
+        /* PTR */
+        PINMUX_GPIO(GPIO_PTR7, PTR7_DATA),
+        PINMUX_GPIO(GPIO_PTR6, PTR6_DATA),
+        PINMUX_GPIO(GPIO_PTR5, PTR5_DATA),
+        PINMUX_GPIO(GPIO_PTR4, PTR4_DATA),
+        PINMUX_GPIO(GPIO_PTR3, PTR3_DATA),
+        PINMUX_GPIO(GPIO_PTR2, PTR2_DATA),
+        PINMUX_GPIO(GPIO_PTR1, PTR1_DATA),
+        PINMUX_GPIO(GPIO_PTR0, PTR0_DATA),
+
+        /* PTS */
+        PINMUX_GPIO(GPIO_PTS7, PTS7_DATA),
+        PINMUX_GPIO(GPIO_PTS6, PTS6_DATA),
+        PINMUX_GPIO(GPIO_PTS5, PTS5_DATA),
+        PINMUX_GPIO(GPIO_PTS4, PTS4_DATA),
+        PINMUX_GPIO(GPIO_PTS3, PTS3_DATA),
+        PINMUX_GPIO(GPIO_PTS2, PTS2_DATA),
+        PINMUX_GPIO(GPIO_PTS1, PTS1_DATA),
+        PINMUX_GPIO(GPIO_PTS0, PTS0_DATA),
+
+        /* PTT */
+        PINMUX_GPIO(GPIO_PTT5, PTT5_DATA),
+        PINMUX_GPIO(GPIO_PTT4, PTT4_DATA),
+        PINMUX_GPIO(GPIO_PTT3, PTT3_DATA),
+        PINMUX_GPIO(GPIO_PTT2, PTT2_DATA),
+        PINMUX_GPIO(GPIO_PTT1, PTT1_DATA),
+        PINMUX_GPIO(GPIO_PTT0, PTT0_DATA),
+
+        /* PTU */
+        PINMUX_GPIO(GPIO_PTU7, PTU7_DATA),
+        PINMUX_GPIO(GPIO_PTU6, PTU6_DATA),
+        PINMUX_GPIO(GPIO_PTU5, PTU5_DATA),
+        PINMUX_GPIO(GPIO_PTU4, PTU4_DATA),
+        PINMUX_GPIO(GPIO_PTU3, PTU3_DATA),
+        PINMUX_GPIO(GPIO_PTU2, PTU2_DATA),
+        PINMUX_GPIO(GPIO_PTU1, PTU1_DATA),
+        PINMUX_GPIO(GPIO_PTU0, PTU0_DATA),
+
+        /* PTV */
+        PINMUX_GPIO(GPIO_PTV7, PTV7_DATA),
+        PINMUX_GPIO(GPIO_PTV6, PTV6_DATA),
+        PINMUX_GPIO(GPIO_PTV5, PTV5_DATA),
+        PINMUX_GPIO(GPIO_PTV4, PTV4_DATA),
+        PINMUX_GPIO(GPIO_PTV3, PTV3_DATA),
+        PINMUX_GPIO(GPIO_PTV2, PTV2_DATA),
+        PINMUX_GPIO(GPIO_PTV1, PTV1_DATA),
+        PINMUX_GPIO(GPIO_PTV0, PTV0_DATA),
+
+        /* PTW */
+        PINMUX_GPIO(GPIO_PTW7, PTW7_DATA),
+        PINMUX_GPIO(GPIO_PTW6, PTW6_DATA),
+        PINMUX_GPIO(GPIO_PTW5, PTW5_DATA),
+        PINMUX_GPIO(GPIO_PTW4, PTW4_DATA),
+        PINMUX_GPIO(GPIO_PTW3, PTW3_DATA),
+        PINMUX_GPIO(GPIO_PTW2, PTW2_DATA),
+        PINMUX_GPIO(GPIO_PTW1, PTW1_DATA),
+        PINMUX_GPIO(GPIO_PTW0, PTW0_DATA),
+
+        /* PTX */
+        PINMUX_GPIO(GPIO_PTX7, PTX7_DATA),
+        PINMUX_GPIO(GPIO_PTX6, PTX6_DATA),
+        PINMUX_GPIO(GPIO_PTX5, PTX5_DATA),
+        PINMUX_GPIO(GPIO_PTX4, PTX4_DATA),
+        PINMUX_GPIO(GPIO_PTX3, PTX3_DATA),
+        PINMUX_GPIO(GPIO_PTX2, PTX2_DATA),
+        PINMUX_GPIO(GPIO_PTX1, PTX1_DATA),
+        PINMUX_GPIO(GPIO_PTX0, PTX0_DATA),
+
+        /* PTY */
+        PINMUX_GPIO(GPIO_PTY7, PTY7_DATA),
+        PINMUX_GPIO(GPIO_PTY6, PTY6_DATA),
+        PINMUX_GPIO(GPIO_PTY5, PTY5_DATA),
+        PINMUX_GPIO(GPIO_PTY4, PTY4_DATA),
+        PINMUX_GPIO(GPIO_PTY3, PTY3_DATA),
+        PINMUX_GPIO(GPIO_PTY2, PTY2_DATA),
+        PINMUX_GPIO(GPIO_PTY1, PTY1_DATA),
+        PINMUX_GPIO(GPIO_PTY0, PTY0_DATA),
+
+        /* PTZ */
+        PINMUX_GPIO(GPIO_PTZ7, PTZ7_DATA),
+        PINMUX_GPIO(GPIO_PTZ6, PTZ6_DATA),
+        PINMUX_GPIO(GPIO_PTZ5, PTZ5_DATA),
+        PINMUX_GPIO(GPIO_PTZ4, PTZ4_DATA),
+        PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA),
+        PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
+        PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
+        PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA),
+
+        /* PTA (mobule: LBSC, CPG, LPC) */
+        PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
+        PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK),
+        PINMUX_GPIO(GPIO_FN_WE1, WE1_MARK),
+        PINMUX_GPIO(GPIO_FN_RDY, RDY_MARK),
+        PINMUX_GPIO(GPIO_FN_MD10, MD10_MARK),
+        PINMUX_GPIO(GPIO_FN_MD9, MD9_MARK),
+        PINMUX_GPIO(GPIO_FN_MD8, MD8_MARK),
+        PINMUX_GPIO(GPIO_FN_LGPIO7, LGPIO7_MARK),
+        PINMUX_GPIO(GPIO_FN_LGPIO6, LGPIO6_MARK),
+        PINMUX_GPIO(GPIO_FN_LGPIO5, LGPIO5_MARK),
+        PINMUX_GPIO(GPIO_FN_LGPIO4, LGPIO4_MARK),
+        PINMUX_GPIO(GPIO_FN_LGPIO3, LGPIO3_MARK),
+        PINMUX_GPIO(GPIO_FN_LGPIO2, LGPIO2_MARK),
+        PINMUX_GPIO(GPIO_FN_LGPIO1, LGPIO1_MARK),
+        PINMUX_GPIO(GPIO_FN_LGPIO0, LGPIO0_MARK),
+
+        /* PTB (mobule: LBSC, EtherC, SIM, LPC) */
+        PINMUX_GPIO(GPIO_FN_D15, D15_MARK),
+        PINMUX_GPIO(GPIO_FN_D14, D14_MARK),
+        PINMUX_GPIO(GPIO_FN_D13, D13_MARK),
+        PINMUX_GPIO(GPIO_FN_D12, D12_MARK),
+        PINMUX_GPIO(GPIO_FN_D11, D11_MARK),
+        PINMUX_GPIO(GPIO_FN_D10, D10_MARK),
+        PINMUX_GPIO(GPIO_FN_D9, D9_MARK),
+        PINMUX_GPIO(GPIO_FN_D8, D8_MARK),
+        PINMUX_GPIO(GPIO_FN_ET0_MDC, ET0_MDC_MARK),
+        PINMUX_GPIO(GPIO_FN_ET0_MDIO, ET0_MDIO_MARK),
+        PINMUX_GPIO(GPIO_FN_ET1_MDC, ET1_MDC_MARK),
+        PINMUX_GPIO(GPIO_FN_ET1_MDIO, ET1_MDIO_MARK),
+        PINMUX_GPIO(GPIO_FN_WPSZ1, WPSZ1_MARK),
+        PINMUX_GPIO(GPIO_FN_WPSZ0, WPSZ0_MARK),
+        PINMUX_GPIO(GPIO_FN_FWID, FWID_MARK),
+        PINMUX_GPIO(GPIO_FN_FLSHSZ, FLSHSZ_MARK),
+        PINMUX_GPIO(GPIO_FN_LPC_SPIEN, LPC_SPIEN_MARK),
+        PINMUX_GPIO(GPIO_FN_BASEL, BASEL_MARK),
+
+        /* PTC (mobule: SD) */
+        PINMUX_GPIO(GPIO_FN_SD_WP, SD_WP_MARK),
+        PINMUX_GPIO(GPIO_FN_SD_CD, SD_CD_MARK),
+        PINMUX_GPIO(GPIO_FN_SD_CLK, SD_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_SD_CMD, SD_CMD_MARK),
+        PINMUX_GPIO(GPIO_FN_SD_D3, SD_D3_MARK),
+        PINMUX_GPIO(GPIO_FN_SD_D2, SD_D2_MARK),
+        PINMUX_GPIO(GPIO_FN_SD_D1, SD_D1_MARK),
+        PINMUX_GPIO(GPIO_FN_SD_D0, SD_D0_MARK),
+
+        /* PTD (mobule: INTC, SPI0, LBSC, CPG, ADC) */
+        PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK),
+        PINMUX_GPIO(GPIO_FN_MD6, MD6_MARK),
+        PINMUX_GPIO(GPIO_FN_MD5, MD5_MARK),
+        PINMUX_GPIO(GPIO_FN_MD3, MD3_MARK),
+        PINMUX_GPIO(GPIO_FN_MD2, MD2_MARK),
+        PINMUX_GPIO(GPIO_FN_MD1, MD1_MARK),
+        PINMUX_GPIO(GPIO_FN_MD0, MD0_MARK),
+        PINMUX_GPIO(GPIO_FN_ADTRG1, ADTRG1_MARK),
+        PINMUX_GPIO(GPIO_FN_ADTRG0, ADTRG0_MARK),
+
+        /* PTE (mobule: EtherC) */
+        PINMUX_GPIO(GPIO_FN_ET0_CRS_DV, ET0_CRS_DV_MARK),
+        PINMUX_GPIO(GPIO_FN_ET0_TXD1, ET0_TXD1_MARK),
+        PINMUX_GPIO(GPIO_FN_ET0_TXD0, ET0_TXD0_MARK),
+        PINMUX_GPIO(GPIO_FN_ET0_TX_EN, ET0_TX_EN_MARK),
+        PINMUX_GPIO(GPIO_FN_ET0_REF_CLK, ET0_REF_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_ET0_RXD1, ET0_RXD1_MARK),
+        PINMUX_GPIO(GPIO_FN_ET0_RXD0, ET0_RXD0_MARK),
+        PINMUX_GPIO(GPIO_FN_ET0_RX_ER, ET0_RX_ER_MARK),
+
+        /* PTF (mobule: EtherC) */
+        PINMUX_GPIO(GPIO_FN_ET1_CRS_DV, ET1_CRS_DV_MARK),
+        PINMUX_GPIO(GPIO_FN_ET1_TXD1, ET1_TXD1_MARK),
+        PINMUX_GPIO(GPIO_FN_ET1_TXD0, ET1_TXD0_MARK),
+        PINMUX_GPIO(GPIO_FN_ET1_TX_EN, ET1_TX_EN_MARK),
+        PINMUX_GPIO(GPIO_FN_ET1_REF_CLK, ET1_REF_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_ET1_RXD1, ET1_RXD1_MARK),
+        PINMUX_GPIO(GPIO_FN_ET1_RXD0, ET1_RXD0_MARK),
+        PINMUX_GPIO(GPIO_FN_ET1_RX_ER, ET1_RX_ER_MARK),
+
+        /* PTG (mobule: SYSTEM, PWMX, LPC) */
+        PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
+        PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK),
+        PINMUX_GPIO(GPIO_FN_PWX0, PWX0_MARK),
+        PINMUX_GPIO(GPIO_FN_PWX1, PWX1_MARK),
+        PINMUX_GPIO(GPIO_FN_PWX2, PWX2_MARK),
+        PINMUX_GPIO(GPIO_FN_PWX3, PWX3_MARK),
+        PINMUX_GPIO(GPIO_FN_SERIRQ, SERIRQ_MARK),
+        PINMUX_GPIO(GPIO_FN_CLKRUN, CLKRUN_MARK),
+        PINMUX_GPIO(GPIO_FN_LPCPD, LPCPD_MARK),
+        PINMUX_GPIO(GPIO_FN_LDRQ, LDRQ_MARK),
+
+        /* PTH (mobule: TMU, SCIF234, SPI1, SPI0) */
+        PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK),
+        PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK),
+        PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK),
+        PINMUX_GPIO(GPIO_FN_SP1_MOSI, SP1_MOSI_MARK),
+        PINMUX_GPIO(GPIO_FN_SP1_MISO, SP1_MISO_MARK),
+        PINMUX_GPIO(GPIO_FN_SP1_SCK, SP1_SCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SP1_SCK_FB, SP1_SCK_FB_MARK),
+        PINMUX_GPIO(GPIO_FN_SP1_SS0, SP1_SS0_MARK),
+        PINMUX_GPIO(GPIO_FN_SP1_SS1, SP1_SS1_MARK),
+        PINMUX_GPIO(GPIO_FN_SP0_SS1, SP0_SS1_MARK),
+
+        /* PTI (mobule: INTC) */
+        PINMUX_GPIO(GPIO_FN_IRQ15, IRQ15_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ14, IRQ14_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ13, IRQ13_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ12, IRQ12_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ11, IRQ11_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ10, IRQ10_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ9, IRQ9_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ8, IRQ8_MARK),
+
+        /* PTJ (mobule: SCIF234, SERMUX) */
+        PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
+        PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK),
+        PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
+        PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK),
+        PINMUX_GPIO(GPIO_FN_COM1_TXD, COM1_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_COM1_RXD, COM1_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_COM1_RTS, COM1_RTS_MARK),
+        PINMUX_GPIO(GPIO_FN_COM1_CTS, COM1_CTS_MARK),
+
+        /* PTK (mobule: SERMUX) */
+        PINMUX_GPIO(GPIO_FN_COM2_TXD, COM2_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_COM2_RXD, COM2_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_COM2_RTS, COM2_RTS_MARK),
+        PINMUX_GPIO(GPIO_FN_COM2_CTS, COM2_CTS_MARK),
+        PINMUX_GPIO(GPIO_FN_COM2_DTR, COM2_DTR_MARK),
+        PINMUX_GPIO(GPIO_FN_COM2_DSR, COM2_DSR_MARK),
+        PINMUX_GPIO(GPIO_FN_COM2_DCD, COM2_DCD_MARK),
+        PINMUX_GPIO(GPIO_FN_COM2_RI, COM2_RI_MARK),
+
+        /* PTL (mobule: SERMUX) */
+        PINMUX_GPIO(GPIO_FN_RAC_TXD, RAC_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_RAC_RXD, RAC_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_RAC_RTS, RAC_RTS_MARK),
+        PINMUX_GPIO(GPIO_FN_RAC_CTS, RAC_CTS_MARK),
+        PINMUX_GPIO(GPIO_FN_RAC_DTR, RAC_DTR_MARK),
+        PINMUX_GPIO(GPIO_FN_RAC_DSR, RAC_DSR_MARK),
+        PINMUX_GPIO(GPIO_FN_RAC_DCD, RAC_DCD_MARK),
+        PINMUX_GPIO(GPIO_FN_RAC_RI, RAC_RI_MARK),
+
+        /* PTM (mobule: IIC, LPC) */
+        PINMUX_GPIO(GPIO_FN_SDA6, SDA6_MARK),
+        PINMUX_GPIO(GPIO_FN_SCL6, SCL6_MARK),
+        PINMUX_GPIO(GPIO_FN_SDA7, SDA7_MARK),
+        PINMUX_GPIO(GPIO_FN_SCL7, SCL7_MARK),
+        PINMUX_GPIO(GPIO_FN_WP, WP_MARK),
+        PINMUX_GPIO(GPIO_FN_FMS0, FMS0_MARK),
+        PINMUX_GPIO(GPIO_FN_FMS1, FMS1_MARK),
+
+        /* PTN (mobule: SCIF234, EVC) */
+        PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK),
+        PINMUX_GPIO(GPIO_FN_RTS4, RTS4_MARK),
+        PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK),
+        PINMUX_GPIO(GPIO_FN_RTS2, RTS2_MARK),
+        PINMUX_GPIO(GPIO_FN_CTS4, CTS4_MARK),
+        PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK),
+        PINMUX_GPIO(GPIO_FN_CTS2, CTS2_MARK),
+        PINMUX_GPIO(GPIO_FN_EVENT7, EVENT7_MARK),
+        PINMUX_GPIO(GPIO_FN_EVENT6, EVENT6_MARK),
+        PINMUX_GPIO(GPIO_FN_EVENT5, EVENT5_MARK),
+        PINMUX_GPIO(GPIO_FN_EVENT4, EVENT4_MARK),
+        PINMUX_GPIO(GPIO_FN_EVENT3, EVENT3_MARK),
+        PINMUX_GPIO(GPIO_FN_EVENT2, EVENT2_MARK),
+        PINMUX_GPIO(GPIO_FN_EVENT1, EVENT1_MARK),
+        PINMUX_GPIO(GPIO_FN_EVENT0, EVENT0_MARK),
+
+        /* PTO (mobule: SGPIO) */
+        PINMUX_GPIO(GPIO_FN_SGPIO0_CLK, SGPIO0_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_SGPIO0_LOAD, SGPIO0_LOAD_MARK),
+        PINMUX_GPIO(GPIO_FN_SGPIO0_DI, SGPIO0_DI_MARK),
+        PINMUX_GPIO(GPIO_FN_SGPIO0_DO, SGPIO0_DO_MARK),
+        PINMUX_GPIO(GPIO_FN_SGPIO1_CLK, SGPIO1_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_SGPIO1_LOAD, SGPIO1_LOAD_MARK),
+        PINMUX_GPIO(GPIO_FN_SGPIO1_DI, SGPIO1_DI_MARK),
+        PINMUX_GPIO(GPIO_FN_SGPIO1_DO, SGPIO1_DO_MARK),
+
+        /* PTP (mobule: JMC, SCIF234) */
+        PINMUX_GPIO(GPIO_FN_JMCTCK, JMCTCK_MARK),
+        PINMUX_GPIO(GPIO_FN_JMCTMS, JMCTMS_MARK),
+        PINMUX_GPIO(GPIO_FN_JMCTDO, JMCTDO_MARK),
+        PINMUX_GPIO(GPIO_FN_JMCTDI, JMCTDI_MARK),
+        PINMUX_GPIO(GPIO_FN_JMCRST, JMCRST_MARK),
+        PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK),
+        PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
+
+        /* PTQ (mobule: LPC) */
+        PINMUX_GPIO(GPIO_FN_LAD3, LAD3_MARK),
+        PINMUX_GPIO(GPIO_FN_LAD2, LAD2_MARK),
+        PINMUX_GPIO(GPIO_FN_LAD1, LAD1_MARK),
+        PINMUX_GPIO(GPIO_FN_LAD0, LAD0_MARK),
+        PINMUX_GPIO(GPIO_FN_LFRAME, LFRAME_MARK),
+        PINMUX_GPIO(GPIO_FN_LRESET, LRESET_MARK),
+        PINMUX_GPIO(GPIO_FN_LCLK, LCLK_MARK),
+
+        /* PTR (mobule: GRA, IIC) */
+        PINMUX_GPIO(GPIO_FN_DDC3, DDC3_MARK),
+        PINMUX_GPIO(GPIO_FN_DDC2, DDC2_MARK),
+        PINMUX_GPIO(GPIO_FN_SDA8, SDA8_MARK),
+        PINMUX_GPIO(GPIO_FN_SCL8, SCL8_MARK),
+        PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK),
+        PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK),
+        PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK),
+        PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK),
+        PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK),
+        PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK),
+
+        /* PTS (mobule: GRA, IIC) */
+        PINMUX_GPIO(GPIO_FN_DDC1, DDC1_MARK),
+        PINMUX_GPIO(GPIO_FN_DDC0, DDC0_MARK),
+        PINMUX_GPIO(GPIO_FN_SDA9, SDA9_MARK),
+        PINMUX_GPIO(GPIO_FN_SCL9, SCL9_MARK),
+        PINMUX_GPIO(GPIO_FN_SDA5, SDA5_MARK),
+        PINMUX_GPIO(GPIO_FN_SCL5, SCL5_MARK),
+        PINMUX_GPIO(GPIO_FN_SDA4, SDA4_MARK),
+        PINMUX_GPIO(GPIO_FN_SCL4, SCL4_MARK),
+        PINMUX_GPIO(GPIO_FN_SDA3, SDA3_MARK),
+        PINMUX_GPIO(GPIO_FN_SCL3, SCL3_MARK),
+
+        /* PTT (mobule: SYSTEM, PWMX) */
+        PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK),
+        PINMUX_GPIO(GPIO_FN_PWX7, PWX7_MARK),
+        PINMUX_GPIO(GPIO_FN_PWX6, PWX6_MARK),
+        PINMUX_GPIO(GPIO_FN_PWX5, PWX5_MARK),
+        PINMUX_GPIO(GPIO_FN_PWX4, PWX4_MARK),
+
+        /* PTU (mobule: LBSC, DMAC) */
+        PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK),
+        PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK),
+        PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
+        PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK),
+        PINMUX_GPIO(GPIO_FN_RD, RD_MARK),
+        PINMUX_GPIO(GPIO_FN_WE0, WE0_MARK),
+        PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
+        PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
+        PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
+        PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
+
+        /* PTV (mobule: LBSC, DMAC) */
+        PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
+        PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
+        PINMUX_GPIO(GPIO_FN_A21, A21_MARK),
+        PINMUX_GPIO(GPIO_FN_A20, A20_MARK),
+        PINMUX_GPIO(GPIO_FN_A19, A19_MARK),
+        PINMUX_GPIO(GPIO_FN_A18, A18_MARK),
+        PINMUX_GPIO(GPIO_FN_A17, A17_MARK),
+        PINMUX_GPIO(GPIO_FN_A16, A16_MARK),
+        PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK),
+        PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
+        PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
+        PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK),
+
+        /* PTW (mobule: LBSC) */
+        PINMUX_GPIO(GPIO_FN_A16, A16_MARK),
+        PINMUX_GPIO(GPIO_FN_A15, A15_MARK),
+        PINMUX_GPIO(GPIO_FN_A14, A14_MARK),
+        PINMUX_GPIO(GPIO_FN_A13, A13_MARK),
+        PINMUX_GPIO(GPIO_FN_A12, A12_MARK),
+        PINMUX_GPIO(GPIO_FN_A11, A11_MARK),
+        PINMUX_GPIO(GPIO_FN_A10, A10_MARK),
+        PINMUX_GPIO(GPIO_FN_A9, A9_MARK),
+        PINMUX_GPIO(GPIO_FN_A8, A8_MARK),
+
+        /* PTX (mobule: LBSC) */
+        PINMUX_GPIO(GPIO_FN_A7, A7_MARK),
+        PINMUX_GPIO(GPIO_FN_A6, A6_MARK),
+        PINMUX_GPIO(GPIO_FN_A5, A5_MARK),
+        PINMUX_GPIO(GPIO_FN_A4, A4_MARK),
+        PINMUX_GPIO(GPIO_FN_A3, A3_MARK),
+        PINMUX_GPIO(GPIO_FN_A2, A2_MARK),
+        PINMUX_GPIO(GPIO_FN_A1, A1_MARK),
+        PINMUX_GPIO(GPIO_FN_A0, A0_MARK),
+
+        /* PTY (mobule: LBSC) */
+        PINMUX_GPIO(GPIO_FN_D7, D7_MARK),
+        PINMUX_GPIO(GPIO_FN_D6, D6_MARK),
+        PINMUX_GPIO(GPIO_FN_D5, D5_MARK),
+        PINMUX_GPIO(GPIO_FN_D4, D4_MARK),
+        PINMUX_GPIO(GPIO_FN_D3, D3_MARK),
+        PINMUX_GPIO(GPIO_FN_D2, D2_MARK),
+        PINMUX_GPIO(GPIO_FN_D1, D1_MARK),
+        PINMUX_GPIO(GPIO_FN_D0, D0_MARK),
+ };
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+        { PINMUX_CFG_REG("PACR", 0xffec0000, 16, 2) {
+                PTA7_FN, PTA7_OUT, PTA7_IN, 0,
+                PTA6_FN, PTA6_OUT, PTA6_IN, 0,
+                PTA5_FN, PTA5_OUT, PTA5_IN, 0,
+                PTA4_FN, PTA4_OUT, PTA4_IN, 0,
+                PTA3_FN, PTA3_OUT, PTA3_IN, 0,
+                PTA2_FN, PTA2_OUT, PTA2_IN, 0,
+                PTA1_FN, PTA1_OUT, PTA1_IN, 0,
+                PTA0_FN, PTA0_OUT, PTA0_IN, 0 }
+        },
+        { PINMUX_CFG_REG("PBCR", 0xffec0002, 16, 2) {
+                PTB7_FN, PTB7_OUT, PTB7_IN, 0,
+                PTB6_FN, PTB6_OUT, PTB6_IN, 0,
+                PTB5_FN, PTB5_OUT, PTB5_IN, 0,
+                PTB4_FN, PTB4_OUT, PTB4_IN, 0,
+                PTB3_FN, PTB3_OUT, PTB3_IN, 0,
+                PTB2_FN, PTB2_OUT, PTB2_IN, 0,
+                PTB1_FN, PTB1_OUT, PTB1_IN, 0,
+                PTB0_FN, PTB0_OUT, PTB0_IN, 0 }
+        },
+        { PINMUX_CFG_REG("PCCR", 0xffec0004, 16, 2) {
+                PTC7_FN, PTC7_OUT, PTC7_IN, 0,
+                PTC6_FN, PTC6_OUT, PTC6_IN, 0,
+                PTC5_FN, PTC5_OUT, PTC5_IN, 0,
+                PTC4_FN, PTC4_OUT, PTC4_IN, 0,
+                PTC3_FN, PTC3_OUT, PTC3_IN, 0,
+                PTC2_FN, PTC2_OUT, PTC2_IN, 0,
+                PTC1_FN, PTC1_OUT, PTC1_IN, 0,
+                PTC0_FN, PTC0_OUT, PTC0_IN, 0 }
+        },
+        { PINMUX_CFG_REG("PDCR", 0xffec0006, 16, 2) {
+                PTD7_FN, PTD7_OUT, PTD7_IN, 0,
+                PTD6_FN, PTD6_OUT, PTD6_IN, 0,
+                PTD5_FN, PTD5_OUT, PTD5_IN, 0,
+                PTD4_FN, PTD4_OUT, PTD4_IN, 0,
+                PTD3_FN, PTD3_OUT, PTD3_IN, 0,
+                PTD2_FN, PTD2_OUT, PTD2_IN, 0,
+                PTD1_FN, PTD1_OUT, PTD1_IN, 0,
+                PTD0_FN, PTD0_OUT, PTD0_IN, 0 }
+        },
+        { PINMUX_CFG_REG("PECR", 0xffec0008, 16, 2) {
+                PTE7_FN, PTE7_OUT, PTE7_IN, 0,
+                PTE6_FN, PTE6_OUT, PTE6_IN, 0,
+                PTE5_FN, PTE5_OUT, PTE5_IN, 0,
+                PTE4_FN, PTE4_OUT, PTE4_IN, 0,
+                PTE3_FN, PTE3_OUT, PTE3_IN, 0,
+                PTE2_FN, PTE2_OUT, PTE2_IN, 0,
+                PTE1_FN, PTE1_OUT, PTE1_IN, 0,
+                PTE0_FN, PTE0_OUT, PTE0_IN, 0 }
+        },
+        { PINMUX_CFG_REG("PFCR", 0xffec000a, 16, 2) {
+                PTF7_FN, PTF7_OUT, PTF7_IN, 0,
+                PTF6_FN, PTF6_OUT, PTF6_IN, 0,
+                PTF5_FN, PTF5_OUT, PTF5_IN, 0,
+                PTF4_FN, PTF4_OUT, PTF4_IN, 0,
+                PTF3_FN, PTF3_OUT, PTF3_IN, 0,
+                PTF2_FN, PTF2_OUT, PTF2_IN, 0,
+                PTF1_FN, PTF1_OUT, PTF1_IN, 0,
+                PTF0_FN, PTF0_OUT, PTF0_IN, 0 }
+        },
+        { PINMUX_CFG_REG("PGCR", 0xffec000c, 16, 2) {
+                PTG7_FN, PTG7_OUT, PTG7_IN, 0,
+                PTG6_FN, PTG6_OUT, PTG6_IN, 0,
+                PTG5_FN, PTG5_OUT, PTG5_IN, 0,
+                PTG4_FN, PTG4_OUT, PTG4_IN, 0,
+                PTG3_FN, PTG3_OUT, PTG3_IN, 0,
+                PTG2_FN, PTG2_OUT, PTG2_IN, 0,
+                PTG1_FN, PTG1_OUT, PTG1_IN, 0,
+                PTG0_FN, PTG0_OUT, PTG0_IN, 0 }
+        },
+        { PINMUX_CFG_REG("PHCR", 0xffec000e, 16, 2) {
+                PTH7_FN, PTH7_OUT, PTH7_IN, 0,
+                PTH6_FN, PTH6_OUT, PTH6_IN, 0,
+                PTH5_FN, PTH5_OUT, PTH5_IN, 0,
+                PTH4_FN, PTH4_OUT, PTH4_IN, 0,
+                PTH3_FN, PTH3_OUT, PTH3_IN, 0,
+                PTH2_FN, PTH2_OUT, PTH2_IN, 0,
+                PTH1_FN, PTH1_OUT, PTH1_IN, 0,
+                PTH0_FN, PTH0_OUT, PTH0_IN, 0 }
+        },
+        { PINMUX_CFG_REG("PICR", 0xffec0010, 16, 2) {
+                PTI7_FN, PTI7_OUT, PTI7_IN, 0,
+                PTI6_FN, PTI6_OUT, PTI6_IN, 0,
+                PTI5_FN, PTI5_OUT, PTI5_IN, 0,
+                PTI4_FN, PTI4_OUT, PTI4_IN, 0,
+                PTI3_FN, PTI3_OUT, PTI3_IN, 0,
+                PTI2_FN, PTI2_OUT, PTI2_IN, 0,
+                PTI1_FN, PTI1_OUT, PTI1_IN, 0,
+                PTI0_FN, PTI0_OUT, PTI0_IN, 0 }
+        },
+        { PINMUX_CFG_REG("PJCR", 0xffec0012, 16, 2) {
+                PTJ7_FN, PTJ7_OUT, PTJ7_IN, 0,
+                PTJ6_FN, PTJ6_OUT, PTJ6_IN, 0,
+                PTJ5_FN, PTJ5_OUT, PTJ5_IN, 0,
+                PTJ4_FN, PTJ4_OUT, PTJ4_IN, 0,
+                PTJ3_FN, PTJ3_OUT, PTJ3_IN, 0,
+                PTJ2_FN, PTJ2_OUT, PTJ2_IN, 0,
+                PTJ1_FN, PTJ1_OUT, PTJ1_IN, 0,
+                PTJ0_FN, PTJ0_OUT, PTJ0_IN, 0 }
+        },
+        { PINMUX_CFG_REG("PKCR", 0xffec0014, 16, 2) {
+                PTK7_FN, PTK7_OUT, PTK7_IN, 0,
+                PTK6_FN, PTK6_OUT, PTK6_IN, 0,
+                PTK5_FN, PTK5_OUT, PTK5_IN, 0,
+                PTK4_FN, PTK4_OUT, PTK4_IN, 0,
+                PTK3_FN, PTK3_OUT, PTK3_IN, 0,
+                PTK2_FN, PTK2_OUT, PTK2_IN, 0,
+                PTK1_FN, PTK1_OUT, PTK1_IN, 0,
+                PTK0_FN, PTK0_OUT, PTK0_IN, 0 }
+        },
+        { PINMUX_CFG_REG("PLCR", 0xffec0016, 16, 2) {
+                PTL7_FN, PTL7_OUT, PTL7_IN, 0,
+                PTL6_FN, PTL6_OUT, PTL6_IN, 0,
+                PTL5_FN, PTL5_OUT, PTL5_IN, 0,
+                PTL4_FN, PTL4_OUT, PTL4_IN, 0,
+                PTL3_FN, PTL3_OUT, PTL3_IN, 0,
+                PTL2_FN, PTL2_OUT, PTL2_IN, 0,
+                PTL1_FN, PTL1_OUT, PTL1_IN, 0,
+                PTL0_FN, PTL0_OUT, PTL0_IN, 0 }
+        },
+        { PINMUX_CFG_REG("PMCR", 0xffec0018, 16, 2) {
+                0, 0, 0, 0,     /* reserved: always set 1 */
+                PTM6_FN, PTM6_OUT, PTM6_IN, 0,
+                PTM5_FN, PTM5_OUT, PTM5_IN, 0,
+                PTM4_FN, PTM4_OUT, PTM4_IN, 0,
+                PTM3_FN, PTM3_OUT, PTM3_IN, 0,
+                PTM2_FN, PTM2_OUT, PTM2_IN, 0,
+                PTM1_FN, PTM1_OUT, PTM1_IN, 0,
+                PTM0_FN, PTM0_OUT, PTM0_IN, 0 }
+        },
+        { PINMUX_CFG_REG("PNCR", 0xffec001a, 16, 2) {
+                PTN7_FN, PTN7_OUT, PTN7_IN, 0,
+                PTN6_FN, PTN6_OUT, PTN6_IN, 0,
+                PTN5_FN, PTN5_OUT, PTN5_IN, 0,
+                PTN4_FN, PTN4_OUT, PTN4_IN, 0,
+                PTN3_FN, PTN3_OUT, PTN3_IN, 0,
+                PTN2_FN, PTN2_OUT, PTN2_IN, 0,
+                PTN1_FN, PTN1_OUT, PTN1_IN, 0,
+                PTN0_FN, PTN0_OUT, PTN0_IN, 0 }
+        },
+        { PINMUX_CFG_REG("POCR", 0xffec001c, 16, 2) {
+                PTO7_FN, PTO7_OUT, PTO7_IN, 0,
+                PTO6_FN, PTO6_OUT, PTO6_IN, 0,
+                PTO5_FN, PTO5_OUT, PTO5_IN, 0,
+                PTO4_FN, PTO4_OUT, PTO4_IN, 0,
+                PTO3_FN, PTO3_OUT, PTO3_IN, 0,
+                PTO2_FN, PTO2_OUT, PTO2_IN, 0,
+                PTO1_FN, PTO1_OUT, PTO1_IN, 0,
+                PTO0_FN, PTO0_OUT, PTO0_IN, 0 }
+        },
+        { PINMUX_CFG_REG("PPCR", 0xffec001e, 16, 2) {
+                0, 0, 0, 0,     /* reserved: always set 1 */
+                PTP6_FN, PTP6_OUT, PTP6_IN, 0,
+                PTP5_FN, PTP5_OUT, PTP5_IN, 0,
+                PTP4_FN, PTP4_OUT, PTP4_IN, 0,
+                PTP3_FN, PTP3_OUT, PTP3_IN, 0,
+                PTP2_FN, PTP2_OUT, PTP2_IN, 0,
+                PTP1_FN, PTP1_OUT, PTP1_IN, 0,
+                PTP0_FN, PTP0_OUT, PTP0_IN, 0 }
+        },
+        { PINMUX_CFG_REG("PQCR", 0xffec0020, 16, 2) {
+                0, 0, 0, 0,     /* reserved: always set 1 */
+                PTQ6_FN, PTQ6_OUT, PTQ6_IN, 0,
+                PTQ5_FN, PTQ5_OUT, PTQ5_IN, 0,
+                PTQ4_FN, PTQ4_OUT, PTQ4_IN, 0,
+                PTQ3_FN, PTQ3_OUT, PTQ3_IN, 0,
+                PTQ2_FN, PTQ2_OUT, PTQ2_IN, 0,
+                PTQ1_FN, PTQ1_OUT, PTQ1_IN, 0,
+                PTQ0_FN, PTQ0_OUT, PTQ0_IN, 0 }
+        },
+        { PINMUX_CFG_REG("PRCR", 0xffec0022, 16, 2) {
+                PTR7_FN, PTR7_OUT, PTR7_IN, 0,
+                PTR6_FN, PTR6_OUT, PTR6_IN, 0,
+                PTR5_FN, PTR5_OUT, PTR5_IN, 0,
+                PTR4_FN, PTR4_OUT, PTR4_IN, 0,
+                PTR3_FN, PTR3_OUT, PTR3_IN, 0,
+                PTR2_FN, PTR2_OUT, PTR2_IN, 0,
+                PTR1_FN, PTR1_OUT, PTR1_IN, 0,
+                PTR0_FN, PTR0_OUT, PTR0_IN, 0 }
+        },
+        { PINMUX_CFG_REG("PSCR", 0xffec0024, 16, 2) {
+                PTS7_FN, PTS7_OUT, PTS7_IN, 0,
+                PTS6_FN, PTS6_OUT, PTS6_IN, 0,
+                PTS5_FN, PTS5_OUT, PTS5_IN, 0,
+                PTS4_FN, PTS4_OUT, PTS4_IN, 0,
+                PTS3_FN, PTS3_OUT, PTS3_IN, 0,
+                PTS2_FN, PTS2_OUT, PTS2_IN, 0,
+                PTS1_FN, PTS1_OUT, PTS1_IN, 0,
+                PTS0_FN, PTS0_OUT, PTS0_IN, 0 }
+        },
+        { PINMUX_CFG_REG("PTCR", 0xffec0026, 16, 2) {
+                0, 0, 0, 0,     /* reserved: always set 1 */
+                0, 0, 0, 0,     /* reserved: always set 1 */
+                PTT5_FN, PTT5_OUT, PTT5_IN, 0,
+                PTT4_FN, PTT4_OUT, PTT4_IN, 0,
+                PTT3_FN, PTT3_OUT, PTT3_IN, 0,
+                PTT2_FN, PTT2_OUT, PTT2_IN, 0,
+                PTT1_FN, PTT1_OUT, PTT1_IN, 0,
+                PTT0_FN, PTT0_OUT, PTT0_IN, 0 }
+        },
+        { PINMUX_CFG_REG("PUCR", 0xffec0028, 16, 2) {
+                PTU7_FN, PTU7_OUT, PTU7_IN, PTU7_IN_PU,
+                PTU6_FN, PTU6_OUT, PTU6_IN, PTU6_IN_PU,
+                PTU5_FN, PTU5_OUT, PTU5_IN, PTU5_IN_PU,
+                PTU4_FN, PTU4_OUT, PTU4_IN, PTU4_IN_PU,
+                PTU3_FN, PTU3_OUT, PTU3_IN, PTU3_IN_PU,
+                PTU2_FN, PTU2_OUT, PTU2_IN, PTU2_IN_PU,
+                PTU1_FN, PTU1_OUT, PTU1_IN, PTU1_IN_PU,
+                PTU0_FN, PTU0_OUT, PTU0_IN, PTU0_IN_PU }
+        },
+        { PINMUX_CFG_REG("PVCR", 0xffec002a, 16, 2) {
+                PTV7_FN, PTV7_OUT, PTV7_IN, PTV7_IN_PU,
+                PTV6_FN, PTV6_OUT, PTV6_IN, PTV6_IN_PU,
+                PTV5_FN, PTV5_OUT, PTV5_IN, PTV5_IN_PU,
+                PTV4_FN, PTV4_OUT, PTV4_IN, PTV4_IN_PU,
+                PTV3_FN, PTV3_OUT, PTV3_IN, PTV3_IN_PU,
+                PTV2_FN, PTV2_OUT, PTV2_IN, PTV2_IN_PU,
+                PTV1_FN, PTV1_OUT, PTV1_IN, PTV1_IN_PU,
+                PTV0_FN, PTV0_OUT, PTV0_IN, PTV0_IN_PU }
+        },
+        { PINMUX_CFG_REG("PWCR", 0xffec002c, 16, 2) {
+                PTW7_FN, PTW7_OUT, PTW7_IN, PTW7_IN_PU,
+                PTW6_FN, PTW6_OUT, PTW6_IN, PTW6_IN_PU,
+                PTW5_FN, PTW5_OUT, PTW5_IN, PTW5_IN_PU,
+                PTW4_FN, PTW4_OUT, PTW4_IN, PTW4_IN_PU,
+                PTW3_FN, PTW3_OUT, PTW3_IN, PTW3_IN_PU,
+                PTW2_FN, PTW2_OUT, PTW2_IN, PTW2_IN_PU,
+                PTW1_FN, PTW1_OUT, PTW1_IN, PTW1_IN_PU,
+                PTW0_FN, PTW0_OUT, PTW0_IN, PTW0_IN_PU }
+        },
+        { PINMUX_CFG_REG("PXCR", 0xffec002e, 16, 2) {
+                PTX7_FN, PTX7_OUT, PTX7_IN, PTX7_IN_PU,
+                PTX6_FN, PTX6_OUT, PTX6_IN, PTX6_IN_PU,
+                PTX5_FN, PTX5_OUT, PTX5_IN, PTX5_IN_PU,
+                PTX4_FN, PTX4_OUT, PTX4_IN, PTX4_IN_PU,
+                PTX3_FN, PTX3_OUT, PTX3_IN, PTX3_IN_PU,
+                PTX2_FN, PTX2_OUT, PTX2_IN, PTX2_IN_PU,
+                PTX1_FN, PTX1_OUT, PTX1_IN, PTX1_IN_PU,
+                PTX0_FN, PTX0_OUT, PTX0_IN, PTX0_IN_PU }
+        },
+        { PINMUX_CFG_REG("PYCR", 0xffec0030, 16, 2) {
+                PTY7_FN, PTY7_OUT, PTY7_IN, PTY7_IN_PU,
+                PTY6_FN, PTY6_OUT, PTY6_IN, PTY6_IN_PU,
+                PTY5_FN, PTY5_OUT, PTY5_IN, PTY5_IN_PU,
+                PTY4_FN, PTY4_OUT, PTY4_IN, PTY4_IN_PU,
+                PTY3_FN, PTY3_OUT, PTY3_IN, PTY3_IN_PU,
+                PTY2_FN, PTY2_OUT, PTY2_IN, PTY2_IN_PU,
+                PTY1_FN, PTY1_OUT, PTY1_IN, PTY1_IN_PU,
+                PTY0_FN, PTY0_OUT, PTY0_IN, PTY0_IN_PU }
+        },
+        { PINMUX_CFG_REG("PZCR", 0xffec0032, 16, 2) {
+                0, PTZ7_OUT, PTZ7_IN, 0,
+                0, PTZ6_OUT, PTZ6_IN, 0,
+                0, PTZ5_OUT, PTZ5_IN, 0,
+                0, PTZ4_OUT, PTZ4_IN, 0,
+                0, PTZ3_OUT, PTZ3_IN, 0,
+                0, PTZ2_OUT, PTZ2_IN, 0,
+                0, PTZ1_OUT, PTZ1_IN, 0,
+                0, PTZ0_OUT, PTZ0_IN, 0 }
+        },
+
+        { PINMUX_CFG_REG("PSEL0", 0xffec0070, 16, 1) {
+                PS0_15_FN3, PS0_15_FN1,
+                PS0_14_FN3, PS0_14_FN1,
+                PS0_13_FN3, PS0_13_FN1,
+                PS0_12_FN3, PS0_12_FN1,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                PS0_7_FN2, PS0_7_FN1,
+                PS0_6_FN2, PS0_6_FN1,
+                PS0_5_FN2, PS0_5_FN1,
+                PS0_4_FN2, PS0_4_FN1,
+                PS0_3_FN2, PS0_3_FN1,
+                PS0_2_FN2, PS0_2_FN1,
+                PS0_1_FN2, PS0_1_FN1,
+                0, 0, }
+        },
+        { PINMUX_CFG_REG("PSEL1", 0xffec0072, 16, 1) {
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                PS1_7_FN1, PS1_7_FN3,
+                PS1_6_FN1, PS1_6_FN3,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0, }
+        },
+        { PINMUX_CFG_REG("PSEL2", 0xffec0074, 16, 1) {
+                0, 0,
+                0, 0,
+                PS2_13_FN3, PS2_13_FN1,
+                PS2_12_FN3, PS2_12_FN1,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                PS2_1_FN1, PS2_1_FN2,
+                PS2_0_FN1, PS2_0_FN2, }
+        },
+        { PINMUX_CFG_REG("PSEL4", 0xffec0078, 16, 1) {
+                PS4_15_FN2, PS4_15_FN1,
+                PS4_14_FN2, PS4_14_FN1,
+                PS4_13_FN2, PS4_13_FN1,
+                PS4_12_FN2, PS4_12_FN1,
+                PS4_11_FN2, PS4_11_FN1,
+                PS4_10_FN2, PS4_10_FN1,
+                PS4_9_FN2, PS4_9_FN1,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                PS4_3_FN2, PS4_3_FN1,
+                PS4_2_FN2, PS4_2_FN1,
+                PS4_1_FN2, PS4_1_FN1,
+                PS4_0_FN2, PS4_0_FN1, }
+        },
+        { PINMUX_CFG_REG("PSEL5", 0xffec007a, 16, 1) {
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                PS5_9_FN1, PS5_9_FN2,
+                PS5_8_FN1, PS5_8_FN2,
+                PS5_7_FN1, PS5_7_FN2,
+                PS5_6_FN1, PS5_6_FN2,
+                PS5_5_FN1, PS5_5_FN2,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0, }
+        },
+        { PINMUX_CFG_REG("PSEL6", 0xffec007c, 16, 1) {
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                PS6_7_FN_AN, PS6_7_FN_EV,
+                PS6_6_FN_AN, PS6_6_FN_EV,
+                PS6_5_FN_AN, PS6_5_FN_EV,
+                PS6_4_FN_AN, PS6_4_FN_EV,
+                PS6_3_FN_AN, PS6_3_FN_EV,
+                PS6_2_FN_AN, PS6_2_FN_EV,
+                PS6_1_FN_AN, PS6_1_FN_EV,
+                PS6_0_FN_AN, PS6_0_FN_EV, }
+        },
+        {}
+};
+
+static struct pinmux_data_reg pinmux_data_regs[] = {
+        { PINMUX_DATA_REG("PADR", 0xffec0034, 8) {
+                PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
+                PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
+        },
+        { PINMUX_DATA_REG("PBDR", 0xffec0036, 8) {
+                PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
+                PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA }
+        },
+        { PINMUX_DATA_REG("PCDR", 0xffec0038, 8) {
+                PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
+                PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA }
+        },
+        { PINMUX_DATA_REG("PDDR", 0xffec003a, 8) {
+                PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
+                PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA }
+        },
+        { PINMUX_DATA_REG("PEDR", 0xffec003c, 8) {
+                PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
+                PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA }
+        },
+        { PINMUX_DATA_REG("PFDR", 0xffec003e, 8) {
+                PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
+                PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA }
+        },
+        { PINMUX_DATA_REG("PGDR", 0xffec0040, 8) {
+                PTG7_DATA, PTG6_DATA, PTG5_DATA, PTG4_DATA,
+                PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA }
+        },
+        { PINMUX_DATA_REG("PHDR", 0xffec0042, 8) {
+                PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
+                PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA }
+        },
+        { PINMUX_DATA_REG("PIDR", 0xffec0044, 8) {
+                PTI7_DATA, PTI6_DATA, PTI5_DATA, PTI4_DATA,
+                PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA }
+        },
+        { PINMUX_DATA_REG("PJDR", 0xffec0046, 8) {
+                PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA,
+                PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA }
+        },
+        { PINMUX_DATA_REG("PKDR", 0xffec0048, 8) {
+                PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
+                PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA }
+        },
+        { PINMUX_DATA_REG("PLDR", 0xffec004a, 8) {
+                PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
+                PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA }
+        },
+        { PINMUX_DATA_REG("PMDR", 0xffec004c, 8) {
+                0, PTM6_DATA, PTM5_DATA, PTM4_DATA,
+                PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA }
+        },
+        { PINMUX_DATA_REG("PNDR", 0xffec004e, 8) {
+                PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
+                PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA }
+        },
+        { PINMUX_DATA_REG("PODR", 0xffec0050, 8) {
+                PTO7_DATA, PTO6_DATA, PTO5_DATA, PTO4_DATA,
+                PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA }
+        },
+        { PINMUX_DATA_REG("PPDR", 0xffec0052, 8) {
+                0, PTP6_DATA, PTP5_DATA, PTP4_DATA,
+                PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA }
+        },
+        { PINMUX_DATA_REG("PQDR", 0xffec0054, 8) {
+                0, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
+                PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA }
+        },
+        { PINMUX_DATA_REG("PRDR", 0xffec0056, 8) {
+                PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
+                PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA }
+        },
+        { PINMUX_DATA_REG("PSDR", 0xffec0058, 8) {
+                PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA,
+                PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA }
+        },
+        { PINMUX_DATA_REG("PTDR", 0xffec005a, 8) {
+                0, 0, PTT5_DATA, PTT4_DATA,
+                PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA }
+        },
+        { PINMUX_DATA_REG("PUDR", 0xffec005c, 8) {
+                PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
+                PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA }
+        },
+        { PINMUX_DATA_REG("PVDR", 0xffec005e, 8) {
+                PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
+                PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA }
+        },
+        { PINMUX_DATA_REG("PWDR", 0xffec0060, 8) {
+                PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
+                PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA }
+        },
+        { PINMUX_DATA_REG("PXDR", 0xffec0062, 8) {
+                PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
+                PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA }
+        },
+        { PINMUX_DATA_REG("PYDR", 0xffec0064, 8) {
+                PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
+                PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA }
+        },
+        { PINMUX_DATA_REG("PZDR", 0xffec0066, 8) {
+                PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
+                PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA }
+        },
+        { },
+};
+
+static struct pinmux_info sh7757_pinmux_info = {
+        .name = "sh7757_pfc",
+        .reserved_id = PINMUX_RESERVED,
+        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
+        .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
+        .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
+        .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
+        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
+        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+        .first_gpio = GPIO_PTA7,
+        .last_gpio = GPIO_FN_D0,
+
+        .gpios = pinmux_gpios,
+        .cfg_regs = pinmux_config_regs,
+        .data_regs = pinmux_data_regs,
+
+        .gpio_data = pinmux_data,
+        .gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
+
+static int __init plat_pinmux_setup(void)
+{
+        return register_pinmux(&sh7757_pinmux_info);
+}
+
+arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index 67b0d87fcb27..35097753456c 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -17,6 +17,7 @@
 #include <linux/sh_timer.h>
 #include <asm/clock.h>
 #include <asm/mmzone.h>
+#include <cpu/sh7722.h>
 
 static struct resource rtc_resources[] = {
         [0] = {
@@ -46,6 +47,9 @@ static struct platform_device rtc_device = {
         .id             = -1,
         .num_resources  = ARRAY_SIZE(rtc_resources),
         .resource       = rtc_resources,
+        .archdata = {
+                .hwblk_id = HWBLK_RTC,
+        },
 };
 
 static struct m66592_platdata usbf_platdata = {
@@ -76,6 +80,9 @@ static struct platform_device usbf_device = {
         },
         .num_resources  = ARRAY_SIZE(usbf_resources),
         .resource       = usbf_resources,
+        .archdata = {
+                .hwblk_id = HWBLK_USBF,
+        },
 };
 
 static struct resource iic_resources[] = {
@@ -97,6 +104,9 @@ static struct platform_device iic_device = {
         .id             = 0, /* "i2c0" clock */
         .num_resources  = ARRAY_SIZE(iic_resources),
         .resource       = iic_resources,
+        .archdata = {
+                .hwblk_id = HWBLK_IIC,
+        },
 };
 
 static struct uio_info vpu_platform_data = {
@@ -125,6 +135,9 @@ static struct platform_device vpu_device = {
         },
         .resource       = vpu_resources,
         .num_resources  = ARRAY_SIZE(vpu_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_VPU,
+        },
 };
 
 static struct uio_info veu_platform_data = {
@@ -153,6 +166,9 @@ static struct platform_device veu_device = {
         },
         .resource       = veu_resources,
         .num_resources  = ARRAY_SIZE(veu_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_VEU,
+        },
 };
 
 static struct uio_info jpu_platform_data = {
@@ -181,6 +197,9 @@ static struct platform_device jpu_device = {
         },
         .resource       = jpu_resources,
         .num_resources  = ARRAY_SIZE(jpu_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_JPU,
+        },
 };
 
 static struct sh_timer_config cmt_platform_data = {
@@ -213,6 +232,9 @@ static struct platform_device cmt_device = {
         },
         .resource       = cmt_resources,
         .num_resources  = ARRAY_SIZE(cmt_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_CMT,
+        },
 };
 
 static struct sh_timer_config tmu0_platform_data = {
@@ -244,6 +266,9 @@ static struct platform_device tmu0_device = {
         },
         .resource       = tmu0_resources,
         .num_resources  = ARRAY_SIZE(tmu0_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_TMU,
+        },
 };
 
 static struct sh_timer_config tmu1_platform_data = {
@@ -275,6 +300,9 @@ static struct platform_device tmu1_device = {
         },
         .resource       = tmu1_resources,
         .num_resources  = ARRAY_SIZE(tmu1_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_TMU,
+        },
 };
 
 static struct sh_timer_config tmu2_platform_data = {
@@ -305,6 +333,9 @@ static struct platform_device tmu2_device = {
         },
         .resource       = tmu2_resources,
         .num_resources  = ARRAY_SIZE(tmu2_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_TMU,
+        },
 };
 
 static struct plat_sci_port sci_platform_data[] = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index 26dc4d323252..4caa5a7ca86e 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -18,6 +18,7 @@
 #include <linux/io.h>
 #include <asm/clock.h>
 #include <asm/mmzone.h>
+#include <cpu/sh7723.h>
 
 static struct uio_info vpu_platform_data = {
         .name = "VPU5",
@@ -45,6 +46,9 @@ static struct platform_device vpu_device = {
         },
         .resource       = vpu_resources,
         .num_resources  = ARRAY_SIZE(vpu_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_VPU,
+        },
 };
 
 static struct uio_info veu0_platform_data = {
@@ -73,6 +77,9 @@ static struct platform_device veu0_device = {
         },
         .resource       = veu0_resources,
         .num_resources  = ARRAY_SIZE(veu0_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_VEU2H0,
+        },
 };
 
 static struct uio_info veu1_platform_data = {
@@ -101,6 +108,9 @@ static struct platform_device veu1_device = {
         },
         .resource       = veu1_resources,
         .num_resources  = ARRAY_SIZE(veu1_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_VEU2H1,
+        },
 };
 
 static struct sh_timer_config cmt_platform_data = {
@@ -133,6 +143,9 @@ static struct platform_device cmt_device = {
         },
         .resource       = cmt_resources,
         .num_resources  = ARRAY_SIZE(cmt_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_CMT,
+        },
 };
 
 static struct sh_timer_config tmu0_platform_data = {
@@ -164,6 +177,9 @@ static struct platform_device tmu0_device = {
         },
         .resource       = tmu0_resources,
         .num_resources  = ARRAY_SIZE(tmu0_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_TMU0,
+        },
 };
 
 static struct sh_timer_config tmu1_platform_data = {
@@ -195,6 +211,9 @@ static struct platform_device tmu1_device = {
         },
         .resource       = tmu1_resources,
         .num_resources  = ARRAY_SIZE(tmu1_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_TMU0,
+        },
 };
 
 static struct sh_timer_config tmu2_platform_data = {
@@ -225,6 +244,9 @@ static struct platform_device tmu2_device = {
         },
         .resource       = tmu2_resources,
         .num_resources  = ARRAY_SIZE(tmu2_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_TMU0,
+        },
 };
 
 static struct sh_timer_config tmu3_platform_data = {
@@ -255,6 +277,9 @@ static struct platform_device tmu3_device = {
         },
         .resource       = tmu3_resources,
         .num_resources  = ARRAY_SIZE(tmu3_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_TMU1,
+        },
 };
 
 static struct sh_timer_config tmu4_platform_data = {
@@ -285,6 +310,9 @@ static struct platform_device tmu4_device = {
         },
         .resource       = tmu4_resources,
         .num_resources  = ARRAY_SIZE(tmu4_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_TMU1,
+        },
 };
 
 static struct sh_timer_config tmu5_platform_data = {
@@ -315,6 +343,9 @@ static struct platform_device tmu5_device = {
         },
         .resource       = tmu5_resources,
         .num_resources  = ARRAY_SIZE(tmu5_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_TMU1,
+        },
 };
 
 static struct plat_sci_port sci_platform_data[] = {
@@ -395,6 +426,9 @@ static struct platform_device rtc_device = {
         .id             = -1,
         .num_resources  = ARRAY_SIZE(rtc_resources),
         .resource       = rtc_resources,
+        .archdata = {
+                .hwblk_id = HWBLK_RTC,
+        },
 };
 
 static struct r8a66597_platdata r8a66597_data = {
@@ -424,6 +458,9 @@ static struct platform_device sh7723_usb_host_device = {
         },
         .num_resources  = ARRAY_SIZE(sh7723_usb_host_resources),
         .resource       = sh7723_usb_host_resources,
+        .archdata = {
+                .hwblk_id = HWBLK_USB,
+        },
 };
 
 static struct resource iic_resources[] = {
@@ -445,6 +482,9 @@ static struct platform_device iic_device = {
         .id             = 0, /* "i2c0" clock */
         .num_resources  = ARRAY_SIZE(iic_resources),
         .resource       = iic_resources,
+        .archdata = {
+                .hwblk_id = HWBLK_IIC,
+        },
 };
 
 static struct platform_device *sh7723_devices[] __initdata = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index a04edaab9a29..f3851fd757ec 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -22,6 +22,7 @@
 #include <linux/io.h>
 #include <asm/clock.h>
 #include <asm/mmzone.h>
+#include <cpu/sh7724.h>
 
 /* Serial */
 static struct plat_sci_port sci_platform_data[] = {
@@ -103,6 +104,9 @@ static struct platform_device rtc_device = {
         .id             = -1,
         .num_resources  = ARRAY_SIZE(rtc_resources),
         .resource       = rtc_resources,
+        .archdata = {
+                .hwblk_id = HWBLK_RTC,
+        },
 };
 
 /* I2C0 */
@@ -125,6 +129,9 @@ static struct platform_device iic0_device = {
         .id             = 0, /* "i2c0" clock */
         .num_resources  = ARRAY_SIZE(iic0_resources),
         .resource       = iic0_resources,
+        .archdata = {
+                .hwblk_id = HWBLK_IIC0,
+        },
 };
 
 /* I2C1 */
@@ -147,6 +154,9 @@ static struct platform_device iic1_device = {
         .id             = 1, /* "i2c1" clock */
         .num_resources  = ARRAY_SIZE(iic1_resources),
         .resource       = iic1_resources,
+        .archdata = {
+                .hwblk_id = HWBLK_IIC1,
+        },
 };
 
 /* VPU */
@@ -176,6 +186,9 @@ static struct platform_device vpu_device = {
         },
         .resource       = vpu_resources,
         .num_resources  = ARRAY_SIZE(vpu_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_VPU,
+        },
 };
 
 /* VEU0 */
@@ -205,6 +218,9 @@ static struct platform_device veu0_device = {
         },
         .resource       = veu0_resources,
         .num_resources  = ARRAY_SIZE(veu0_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_VEU0,
+        },
 };
 
 /* VEU1 */
@@ -234,6 +250,9 @@ static struct platform_device veu1_device = {
         },
         .resource       = veu1_resources,
         .num_resources  = ARRAY_SIZE(veu1_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_VEU1,
+        },
 };
 
 static struct sh_timer_config cmt_platform_data = {
@@ -266,6 +285,9 @@ static struct platform_device cmt_device = {
         },
         .resource       = cmt_resources,
         .num_resources  = ARRAY_SIZE(cmt_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_CMT,
+        },
 };
 
 static struct sh_timer_config tmu0_platform_data = {
@@ -297,6 +319,9 @@ static struct platform_device tmu0_device = {
         },
         .resource       = tmu0_resources,
         .num_resources  = ARRAY_SIZE(tmu0_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_TMU0,
+        },
 };
 
 static struct sh_timer_config tmu1_platform_data = {
@@ -328,6 +353,9 @@ static struct platform_device tmu1_device = {
         },
         .resource       = tmu1_resources,
         .num_resources  = ARRAY_SIZE(tmu1_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_TMU0,
+        },
 };
 
 static struct sh_timer_config tmu2_platform_data = {
@@ -358,6 +386,9 @@ static struct platform_device tmu2_device = {
         },
         .resource       = tmu2_resources,
         .num_resources  = ARRAY_SIZE(tmu2_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_TMU0,
+        },
 };
 
 
@@ -389,6 +420,9 @@ static struct platform_device tmu3_device = {
         },
         .resource       = tmu3_resources,
         .num_resources  = ARRAY_SIZE(tmu3_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_TMU1,
+        },
 };
 
 static struct sh_timer_config tmu4_platform_data = {
@@ -419,6 +453,9 @@ static struct platform_device tmu4_device = {
         },
         .resource       = tmu4_resources,
         .num_resources  = ARRAY_SIZE(tmu4_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_TMU1,
+        },
 };
 
 static struct sh_timer_config tmu5_platform_data = {
@@ -449,6 +486,9 @@ static struct platform_device tmu5_device = {
         },
         .resource       = tmu5_resources,
         .num_resources  = ARRAY_SIZE(tmu5_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_TMU1,
+        },
 };
 
 /* JPU */
@@ -478,6 +518,9 @@ static struct platform_device jpu_device = {
         },
         .resource       = jpu_resources,
         .num_resources  = ARRAY_SIZE(jpu_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_JPU,
+        },
 };
 
 static struct platform_device *sh7724_devices[] __initdata = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
new file mode 100644
index 000000000000..c470e15f2e03
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
@@ -0,0 +1,513 @@
+/*
+ * SH7757 Setup
+ *
+ * Copyright (C) 2009  Renesas Solutions Corp.
+ *
+ *  based on setup-sh7785.c : Copyright (C) 2007  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/serial.h>
+#include <linux/serial_sci.h>
+#include <linux/io.h>
+#include <linux/mm.h>
+#include <linux/sh_timer.h>
+
+static struct sh_timer_config tmu0_platform_data = {
+        .name = "TMU0",
+        .channel_offset = 0x04,
+        .timer_bit = 0,
+        .clk = "peripheral_clk",
+        .clockevent_rating = 200,
+};
+
+static struct resource tmu0_resources[] = {
+        [0] = {
+                .name   = "TMU0",
+                .start  = 0xfe430008,
+                .end    = 0xfe430013,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 28,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu0_device = {
+        .name           = "sh_tmu",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &tmu0_platform_data,
+        },
+        .resource       = tmu0_resources,
+        .num_resources  = ARRAY_SIZE(tmu0_resources),
+};
+
+static struct sh_timer_config tmu1_platform_data = {
+        .name = "TMU1",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clk = "peripheral_clk",
+        .clocksource_rating = 200,
+};
+
+static struct resource tmu1_resources[] = {
+        [0] = {
+                .name   = "TMU1",
+                .start  = 0xfe430014,
+                .end    = 0xfe43001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 29,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu1_device = {
+        .name           = "sh_tmu",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &tmu1_platform_data,
+        },
+        .resource       = tmu1_resources,
+        .num_resources  = ARRAY_SIZE(tmu1_resources),
+};
+
+static struct plat_sci_port sci_platform_data[] = {
+        {
+                .mapbase        = 0xfe4b0000,           /* SCIF2 */
+                .flags          = UPF_BOOT_AUTOCONF,
+                .type           = PORT_SCIF,
+                .irqs           = { 40, 40, 40, 40 },
+        }, {
+                .mapbase        = 0xfe4c0000,           /* SCIF3 */
+                .flags          = UPF_BOOT_AUTOCONF,
+                .type           = PORT_SCIF,
+                .irqs           = { 76, 76, 76, 76 },
+        }, {
+                .mapbase        = 0xfe4d0000,           /* SCIF4 */
+                .flags          = UPF_BOOT_AUTOCONF,
+                .type           = PORT_SCIF,
+                .irqs           = { 104, 104, 104, 104 },
+        }, {
+                .flags = 0,
+        }
+};
+
+static struct platform_device sci_device = {
+        .name           = "sh-sci",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = sci_platform_data,
+        },
+};
+
+static struct platform_device *sh7757_devices[] __initdata = {
+        &tmu0_device,
+        &tmu1_device,
+        &sci_device,
+};
+
+static int __init sh7757_devices_setup(void)
+{
+        return platform_add_devices(sh7757_devices,
+                                    ARRAY_SIZE(sh7757_devices));
+}
+arch_initcall(sh7757_devices_setup);
+
+enum {
+        UNUSED = 0,
+
+        /* interrupt sources */
+
+        IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
+        IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
+        IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
+        IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
+
+        IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
+        IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
+        IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
+        IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
+        IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
+
+        SDHI,
+        DVC,
+        IRQ8, IRQ9, IRQ10,
+        WDT0,
+        TMU0, TMU1, TMU2, TMU2_TICPI,
+        HUDI,
+
+        ARC4,
+        DMAC0,
+        IRQ11,
+        SCIF2,
+        DMAC1_6,
+        USB0,
+        IRQ12,
+        JMC,
+        SPI1,
+        IRQ13, IRQ14,
+        USB1,
+        TMR01, TMR23, TMR45,
+        WDT1,
+        FRT,
+        LPC,
+        SCIF0, SCIF1, SCIF3,
+        PECI0I, PECI1I, PECI2I,
+        IRQ15,
+        ETHERC,
+        SPI0,
+        ADC1,
+        DMAC1_8,
+        SIM,
+        TMU3, TMU4, TMU5,
+        ADC0,
+        SCIF4,
+        IIC0_0, IIC0_1, IIC0_2, IIC0_3,
+        IIC1_0, IIC1_1, IIC1_2, IIC1_3,
+        IIC2_0, IIC2_1, IIC2_2, IIC2_3,
+        IIC3_0, IIC3_1, IIC3_2, IIC3_3,
+        IIC4_0, IIC4_1, IIC4_2, IIC4_3,
+        IIC5_0, IIC5_1, IIC5_2, IIC5_3,
+        IIC6_0, IIC6_1, IIC6_2, IIC6_3,
+        IIC7_0, IIC7_1, IIC7_2, IIC7_3,
+        IIC8_0, IIC8_1, IIC8_2, IIC8_3,
+        IIC9_0, IIC9_1, IIC9_2, IIC9_3,
+        PCIINTA,
+        PCIE,
+        SGPIO,
+
+        /* interrupt groups */
+
+        TMU012, TMU345,
+};
+
+static struct intc_vect vectors[] __initdata = {
+        INTC_VECT(SDHI, 0x480), INTC_VECT(SDHI, 0x04a0),
+        INTC_VECT(SDHI, 0x4c0),
+        INTC_VECT(DVC, 0x4e0),
+        INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520),
+        INTC_VECT(IRQ10, 0x540),
+        INTC_VECT(WDT0, 0x560),
+        INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
+        INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
+        INTC_VECT(HUDI, 0x600),
+        INTC_VECT(ARC4, 0x620),
+        INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660),
+        INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0),
+        INTC_VECT(DMAC0, 0x6c0),
+        INTC_VECT(IRQ11, 0x6e0),
+        INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720),
+        INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760),
+        INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0),
+        INTC_VECT(DMAC1_6, 0x7c0), INTC_VECT(DMAC1_6, 0x7e0),
+        INTC_VECT(USB0, 0x840),
+        INTC_VECT(IRQ12, 0x880),
+        INTC_VECT(JMC, 0x8a0),
+        INTC_VECT(SPI1, 0x8c0),
+        INTC_VECT(IRQ13, 0x8e0), INTC_VECT(IRQ14, 0x900),
+        INTC_VECT(USB1, 0x920),
+        INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20),
+        INTC_VECT(TMR45, 0xa40),
+        INTC_VECT(WDT1, 0xa60),
+        INTC_VECT(FRT, 0xa80),
+        INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0),
+        INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00),
+        INTC_VECT(LPC, 0xb20),
+        INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60),
+        INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0),
+        INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0),
+        INTC_VECT(PECI0I, 0xc00), INTC_VECT(PECI1I, 0xc20),
+        INTC_VECT(PECI2I, 0xc40),
+        INTC_VECT(IRQ15, 0xc60),
+        INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0),
+        INTC_VECT(SPI0, 0xcc0),
+        INTC_VECT(ADC1, 0xce0),
+        INTC_VECT(DMAC1_8, 0xd00), INTC_VECT(DMAC1_8, 0xd20),
+        INTC_VECT(DMAC1_8, 0xd40), INTC_VECT(DMAC1_8, 0xd60),
+        INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
+        INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
+        INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
+        INTC_VECT(TMU5, 0xe40),
+        INTC_VECT(ADC0, 0xe60),
+        INTC_VECT(SCIF4, 0xf00), INTC_VECT(SCIF4, 0xf20),
+        INTC_VECT(SCIF4, 0xf40), INTC_VECT(SCIF4, 0xf60),
+        INTC_VECT(IIC0_0, 0x1400), INTC_VECT(IIC0_1, 0x1420),
+        INTC_VECT(IIC0_2, 0x1440), INTC_VECT(IIC0_3, 0x1460),
+        INTC_VECT(IIC1_0, 0x1480), INTC_VECT(IIC1_1, 0x14e0),
+        INTC_VECT(IIC1_2, 0x1500), INTC_VECT(IIC1_3, 0x1520),
+        INTC_VECT(IIC2_0, 0x1540), INTC_VECT(IIC2_1, 0x1560),
+        INTC_VECT(IIC2_2, 0x1580), INTC_VECT(IIC2_3, 0x1600),
+        INTC_VECT(IIC3_0, 0x1620), INTC_VECT(IIC3_1, 0x1640),
+        INTC_VECT(IIC3_2, 0x16e0), INTC_VECT(IIC3_3, 0x1700),
+        INTC_VECT(IIC4_0, 0x17c0), INTC_VECT(IIC4_1, 0x1800),
+        INTC_VECT(IIC4_2, 0x1820), INTC_VECT(IIC4_3, 0x1840),
+        INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880),
+        INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0),
+        INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900),
+        INTC_VECT(IIC6_2, 0x1920), INTC_VECT(IIC6_3, 0x1980),
+        INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00),
+        INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40),
+        INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80),
+        INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40),
+        INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80),
+        INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20),
+        INTC_VECT(PCIINTA, 0x1ce0),
+        INTC_VECT(PCIE, 0x1e00),
+        INTC_VECT(SGPIO, 0x1f80),
+        INTC_VECT(SGPIO, 0x1fa0),
+};
+
+static struct intc_group groups[] __initdata = {
+        INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
+        INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
+};
+
+static struct intc_mask_reg mask_registers[] __initdata = {
+        { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
+          { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+
+        { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
+          { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
+            IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
+            IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
+            IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
+            IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
+            IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
+            IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
+            IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
+
+        { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
+          { 0, 0, 0, 0, 0, 0, 0, 0,
+            0, DMAC1_8, 0, PECI0I, LPC, FRT, WDT1, TMR45,
+            TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0,
+            HUDI, 0, WDT0, SCIF3, SCIF2, SDHI, TMU345, TMU012
+             } },
+
+        { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
+          { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC,
+            IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1,
+            ADC1, 0, DMAC1_6, ADC0, SPI0, SIM, PECI2I, PECI1I,
+            ARC4, 0, SPI1, JMC, 0, 0, 0, DVC
+             } },
+
+        { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */
+          { IIC4_1, IIC4_2, IIC5_0, 0, 0, 0, SGPIO, 0,
+            0, 0, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3,
+            IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1,
+            IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, PCIE, IIC2_2
+             } },
+
+        { 0xffd100d0, 0xff1400d4, 32, /* INT2MSKR3 / INT2MSKCR4 */
+          { 0, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, 0, 0,
+            IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2,
+            PCIINTA, 0, IIC4_0, 0, 0, 0, 0, IIC9_3,
+            IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1
+             } },
+};
+
+#define INTPRI          0xffd00010
+#define INT2PRI0        0xffd40000
+#define INT2PRI1        0xffd40004
+#define INT2PRI2        0xffd40008
+#define INT2PRI3        0xffd4000c
+#define INT2PRI4        0xffd40010
+#define INT2PRI5        0xffd40014
+#define INT2PRI6        0xffd40018
+#define INT2PRI7        0xffd4001c
+#define INT2PRI8        0xffd400a0
+#define INT2PRI9        0xffd400a4
+#define INT2PRI10       0xffd400a8
+#define INT2PRI11       0xffd400ac
+#define INT2PRI12       0xffd400b0
+#define INT2PRI13       0xffd400b4
+#define INT2PRI14       0xffd400b8
+#define INT2PRI15       0xffd400bc
+#define INT2PRI16       0xffd10000
+#define INT2PRI17       0xffd10004
+#define INT2PRI18       0xffd10008
+#define INT2PRI19       0xffd1000c
+#define INT2PRI20       0xffd10010
+#define INT2PRI21       0xffd10014
+#define INT2PRI22       0xffd10018
+#define INT2PRI23       0xffd1001c
+#define INT2PRI24       0xffd100a0
+#define INT2PRI25       0xffd100a4
+#define INT2PRI26       0xffd100a8
+#define INT2PRI27       0xffd100ac
+#define INT2PRI28       0xffd100b0
+#define INT2PRI29       0xffd100b4
+#define INT2PRI30       0xffd100b8
+#define INT2PRI31       0xffd100bc
+
+static struct intc_prio_reg prio_registers[] __initdata = {
+        { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3,
+                              IRQ4, IRQ5, IRQ6, IRQ7 } },
+
+        { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } },
+        { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } },
+        { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, WDT0, IRQ8 } },
+        { INT2PRI3, 0, 32, 8, { HUDI, DMAC0, ADC0, IRQ9 } },
+        { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } },
+        { INT2PRI5, 0, 32, 8, { TMR45, WDT1, FRT, LPC } },
+        { INT2PRI6, 0, 32, 8, { PECI0I, ETHERC, DMAC1_8, 0 } },
+        { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } },
+        { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } },
+        { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } },
+        { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2I, PECI1I } },
+        { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC1_6, IRQ14 } },
+        { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } },
+        { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } },
+
+        { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } },
+        { INT2PRI17, 0, 32, 8, { PCIE, 0, 0, IIC1_0 } },
+        { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } },
+        { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } },
+        { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } },
+        { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } },
+        { INT2PRI22, 0, 32, 8, { IIC9_2, 0, 0, 0 } },
+        { INT2PRI23, 0, 32, 8, { 0, SGPIO, IIC3_2, IIC5_1 } },
+        { INT2PRI24, 0, 32, 8, { 0, 0, 0, IIC1_1 } },
+        { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } },
+        { INT2PRI26, 0, 32, 8, { 0, 0, 0, IIC9_3 } },
+        { INT2PRI27, 0, 32, 8, { PCIINTA, IIC6_0, IIC4_0, IIC6_1 } },
+        { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, 0, IIC6_2 } },
+        { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } },
+        { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, 0 } },
+        { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } },
+};
+
+static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups,
+                         mask_registers, prio_registers, NULL);
+
+/* Support for external interrupt pins in IRQ mode */
+static struct intc_vect vectors_irq0123[] __initdata = {
+        INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
+        INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
+};
+
+static struct intc_vect vectors_irq4567[] __initdata = {
+        INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
+        INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
+};
+
+static struct intc_sense_reg sense_registers[] __initdata = {
+        { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
+                                            IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static struct intc_mask_reg ack_registers[] __initdata = {
+        { 0xffd00024, 0, 32, /* INTREQ */
+          { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7757-irq0123",
+                             vectors_irq0123, NULL, mask_registers,
+                             prio_registers, sense_registers, ack_registers);
+
+static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7757-irq4567",
+                             vectors_irq4567, NULL, mask_registers,
+                             prio_registers, sense_registers, ack_registers);
+
+/* External interrupt pins in IRL mode */
+static struct intc_vect vectors_irl0123[] __initdata = {
+        INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
+        INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
+        INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
+        INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
+        INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
+        INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
+        INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
+        INTC_VECT(IRL0_HHHL, 0x3c0),
+};
+
+static struct intc_vect vectors_irl4567[] __initdata = {
+        INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
+        INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
+        INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
+        INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
+        INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
+        INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
+        INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
+        INTC_VECT(IRL4_HHHL, 0xcc0),
+};
+
+static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7757-irl0123", vectors_irl0123,
+                         NULL, mask_registers, NULL, NULL);
+
+static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7757-irl4567", vectors_irl4567,
+                         NULL, mask_registers, NULL, NULL);
+
+#define INTC_ICR0       0xffd00000
+#define INTC_INTMSK0    0xffd00044
+#define INTC_INTMSK1    0xffd00048
+#define INTC_INTMSK2    0xffd40080
+#define INTC_INTMSKCLR1 0xffd00068
+#define INTC_INTMSKCLR2 0xffd40084
+
+void __init plat_irq_setup(void)
+{
+        /* disable IRQ3-0 + IRQ7-4 */
+        ctrl_outl(0xff000000, INTC_INTMSK0);
+
+        /* disable IRL3-0 + IRL7-4 */
+        ctrl_outl(0xc0000000, INTC_INTMSK1);
+        ctrl_outl(0xfffefffe, INTC_INTMSK2);
+
+        /* select IRL mode for IRL3-0 + IRL7-4 */
+        ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
+
+        /* disable holding function, ie enable "SH-4 Mode" */
+        ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
+
+        register_intc_controller(&intc_desc);
+}
+
+void __init plat_irq_setup_pins(int mode)
+{
+        switch (mode) {
+        case IRQ_MODE_IRQ7654:
+                /* select IRQ mode for IRL7-4 */
+                ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
+                register_intc_controller(&intc_desc_irq4567);
+                break;
+        case IRQ_MODE_IRQ3210:
+                /* select IRQ mode for IRL3-0 */
+                ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
+                register_intc_controller(&intc_desc_irq0123);
+                break;
+        case IRQ_MODE_IRL7654:
+                /* enable IRL7-4 but don't provide any masking */
+                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
+                ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
+                break;
+        case IRQ_MODE_IRL3210:
+                /* enable IRL0-3 but don't provide any masking */
+                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
+                ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
+                break;
+        case IRQ_MODE_IRL7654_MASK:
+                /* enable IRL7-4 and mask using cpu intc controller */
+                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
+                register_intc_controller(&intc_desc_irl4567);
+                break;
+        case IRQ_MODE_IRL3210_MASK:
+                /* enable IRL0-3 and mask using cpu intc controller */
+                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
+                register_intc_controller(&intc_desc_irl0123);
+                break;
+        default:
+                BUG();
+        }
+}
+
+void __init plat_mem_setup(void)
+{
+}
diff --git a/arch/sh/kernel/cpu/shmobile/Makefile b/arch/sh/kernel/cpu/shmobile/Makefile
index e8a5111e848a..a39f88ea1a85 100644
--- a/arch/sh/kernel/cpu/shmobile/Makefile
+++ b/arch/sh/kernel/cpu/shmobile/Makefile
@@ -5,3 +5,4 @@
 # Power Management & Sleep mode
 obj-$(CONFIG_PM)        += pm.o sleep.o
 obj-$(CONFIG_CPU_IDLE)  += cpuidle.o
+obj-$(CONFIG_PM_RUNTIME)        += pm_runtime.o
diff --git a/arch/sh/kernel/cpu/shmobile/pm_runtime.c b/arch/sh/kernel/cpu/shmobile/pm_runtime.c
new file mode 100644
index 000000000000..7c615b17e209
--- /dev/null
+++ b/arch/sh/kernel/cpu/shmobile/pm_runtime.c
@@ -0,0 +1,303 @@
+/*
+ * arch/sh/kernel/cpu/shmobile/pm_runtime.c
+ *
+ * Runtime PM support code for SuperH Mobile
+ *
+ *  Copyright (C) 2009 Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/pm_runtime.h>
+#include <linux/platform_device.h>
+#include <linux/mutex.h>
+#include <asm/hwblk.h>
+
+static DEFINE_SPINLOCK(hwblk_lock);
+static LIST_HEAD(hwblk_idle_list);
+static struct work_struct hwblk_work;
+
+extern struct hwblk_info *hwblk_info;
+
+static void platform_pm_runtime_not_idle(struct platform_device *pdev)
+{
+        unsigned long flags;
+
+        /* remove device from idle list */
+        spin_lock_irqsave(&hwblk_lock, flags);
+        if (test_bit(PDEV_ARCHDATA_FLAG_IDLE, &pdev->archdata.flags)) {
+                list_del(&pdev->archdata.entry);
+                __clear_bit(PDEV_ARCHDATA_FLAG_IDLE, &pdev->archdata.flags);
+        }
+        spin_unlock_irqrestore(&hwblk_lock, flags);
+}
+
+static int __platform_pm_runtime_resume(struct platform_device *pdev)
+{
+        struct device *d = &pdev->dev;
+        struct pdev_archdata *ad = &pdev->archdata;
+        int hwblk = ad->hwblk_id;
+        int ret = -ENOSYS;
+
+        dev_dbg(d, "__platform_pm_runtime_resume() [%d]\n", hwblk);
+
+        if (d->driver && d->driver->pm && d->driver->pm->runtime_resume) {
+                hwblk_enable(hwblk_info, hwblk);
+                ret = 0;
+
+                if (test_bit(PDEV_ARCHDATA_FLAG_SUSP, &ad->flags)) {
+                        ret = d->driver->pm->runtime_resume(d);
+                        if (!ret)
+                                clear_bit(PDEV_ARCHDATA_FLAG_SUSP, &ad->flags);
+                        else
+                                hwblk_disable(hwblk_info, hwblk);
+                }
+        }
+
+        dev_dbg(d, "__platform_pm_runtime_resume() [%d] - returns %d\n",
+                hwblk, ret);
+
+        return ret;
+}
+
+static int __platform_pm_runtime_suspend(struct platform_device *pdev)
+{
+        struct device *d = &pdev->dev;
+        struct pdev_archdata *ad = &pdev->archdata;
+        int hwblk = ad->hwblk_id;
+        int ret = -ENOSYS;
+
+        dev_dbg(d, "__platform_pm_runtime_suspend() [%d]\n", hwblk);
+
+        if (d->driver && d->driver->pm && d->driver->pm->runtime_suspend) {
+                BUG_ON(!test_bit(PDEV_ARCHDATA_FLAG_IDLE, &ad->flags));
+
+                hwblk_enable(hwblk_info, hwblk);
+                ret = d->driver->pm->runtime_suspend(d);
+                hwblk_disable(hwblk_info, hwblk);
+
+                if (!ret) {
+                        set_bit(PDEV_ARCHDATA_FLAG_SUSP, &ad->flags);
+                        platform_pm_runtime_not_idle(pdev);
+                        hwblk_cnt_dec(hwblk_info, hwblk, HWBLK_CNT_IDLE);
+                }
+        }
+
+        dev_dbg(d, "__platform_pm_runtime_suspend() [%d] - returns %d\n",
+                hwblk, ret);
+
+        return ret;
+}
+
+static void platform_pm_runtime_work(struct work_struct *work)
+{
+        struct platform_device *pdev;
+        unsigned long flags;
+        int ret;
+
+        /* go through the idle list and suspend one device at a time */
+        do {
+                spin_lock_irqsave(&hwblk_lock, flags);
+                if (list_empty(&hwblk_idle_list))
+                        pdev = NULL;
+                else
+                        pdev = list_first_entry(&hwblk_idle_list,
+                                                struct platform_device,
+                                                archdata.entry);
+                spin_unlock_irqrestore(&hwblk_lock, flags);
+
+                if (pdev) {
+                        mutex_lock(&pdev->archdata.mutex);
+                        ret = __platform_pm_runtime_suspend(pdev);
+
+                        /* at this point the platform device may be:
+                         * suspended: ret = 0, FLAG_SUSP set, clock stopped
+                         * failed: ret < 0, FLAG_IDLE set, clock stopped
+                         */
+                        mutex_unlock(&pdev->archdata.mutex);
+                } else {
+                        ret = -ENODEV;
+                }
+        } while (!ret);
+}
+
+/* this function gets called from cpuidle context when all devices in the
+ * main power domain are unused but some are counted as idle, ie the hwblk
+ * counter values are (HWBLK_CNT_USAGE == 0) && (HWBLK_CNT_IDLE != 0)
+ */
+void platform_pm_runtime_suspend_idle(void)
+{
+        queue_work(pm_wq, &hwblk_work);
+}
+
+int platform_pm_runtime_suspend(struct device *dev)
+{
+        struct platform_device *pdev = to_platform_device(dev);
+        struct pdev_archdata *ad = &pdev->archdata;
+        unsigned long flags;
+        int hwblk = ad->hwblk_id;
+        int ret = 0;
+
+        dev_dbg(dev, "platform_pm_runtime_suspend() [%d]\n", hwblk);
+
+        /* ignore off-chip platform devices */
+        if (!hwblk)
+                goto out;
+
+        /* interrupt context not allowed */
+        might_sleep();
+
+        /* catch misconfigured drivers not starting with resume */
+        if (test_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags)) {
+                ret = -EINVAL;
+                goto out;
+        }
+
+        /* serialize */
+        mutex_lock(&ad->mutex);
+
+        /* disable clock */
+        hwblk_disable(hwblk_info, hwblk);
+
+        /* put device on idle list */
+        spin_lock_irqsave(&hwblk_lock, flags);
+        list_add_tail(&pdev->archdata.entry, &hwblk_idle_list);
+        __set_bit(PDEV_ARCHDATA_FLAG_IDLE, &pdev->archdata.flags);
+        spin_unlock_irqrestore(&hwblk_lock, flags);
+
+        /* increase idle count */
+        hwblk_cnt_inc(hwblk_info, hwblk, HWBLK_CNT_IDLE);
+
+        /* at this point the platform device is:
+         * idle: ret = 0, FLAG_IDLE set, clock stopped
+         */
+        mutex_unlock(&ad->mutex);
+
+out:
+        dev_dbg(dev, "platform_pm_runtime_suspend() [%d] returns %d\n",
+                hwblk, ret);
+
+        return ret;
+}
+
+int platform_pm_runtime_resume(struct device *dev)
+{
+        struct platform_device *pdev = to_platform_device(dev);
+        struct pdev_archdata *ad = &pdev->archdata;
+        int hwblk = ad->hwblk_id;
+        int ret = 0;
+
+        dev_dbg(dev, "platform_pm_runtime_resume() [%d]\n", hwblk);
+
+        /* ignore off-chip platform devices */
+        if (!hwblk)
+                goto out;
+
+        /* interrupt context not allowed */
+        might_sleep();
+
+        /* serialize */
+        mutex_lock(&ad->mutex);
+
+        /* make sure device is removed from idle list */
+        platform_pm_runtime_not_idle(pdev);
+
+        /* decrease idle count */
+        if (!test_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags) &&
+            !test_bit(PDEV_ARCHDATA_FLAG_SUSP, &pdev->archdata.flags))
+                hwblk_cnt_dec(hwblk_info, hwblk, HWBLK_CNT_IDLE);
+
+        /* resume the device if needed */
+        ret = __platform_pm_runtime_resume(pdev);
+
+        /* the driver has been initialized now, so clear the init flag */
+        clear_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags);
+
+        /* at this point the platform device may be:
+         * resumed: ret = 0, flags = 0, clock started
+         * failed: ret < 0, FLAG_SUSP set, clock stopped
+         */
+        mutex_unlock(&ad->mutex);
+out:
+        dev_dbg(dev, "platform_pm_runtime_resume() [%d] returns %d\n",
+                hwblk, ret);
+
+        return ret;
+}
+
+int platform_pm_runtime_idle(struct device *dev)
+{
+        struct platform_device *pdev = to_platform_device(dev);
+        int hwblk = pdev->archdata.hwblk_id;
+        int ret = 0;
+
+        dev_dbg(dev, "platform_pm_runtime_idle() [%d]\n", hwblk);
+
+        /* ignore off-chip platform devices */
+        if (!hwblk)
+                goto out;
+
+        /* interrupt context not allowed, use pm_runtime_put()! */
+        might_sleep();
+
+        /* suspend synchronously to disable clocks immediately */
+        ret = pm_runtime_suspend(dev);
+out:
+        dev_dbg(dev, "platform_pm_runtime_idle() [%d] done!\n", hwblk);
+        return ret;
+}
+
+static int platform_bus_notify(struct notifier_block *nb,
+                               unsigned long action, void *data)
+{
+        struct device *dev = data;
+        struct platform_device *pdev = to_platform_device(dev);
+        int hwblk = pdev->archdata.hwblk_id;
+
+        /* ignore off-chip platform devices */
+        if (!hwblk)
+                return 0;
+
+        switch (action) {
+        case BUS_NOTIFY_ADD_DEVICE:
+                INIT_LIST_HEAD(&pdev->archdata.entry);
+                mutex_init(&pdev->archdata.mutex);
+                /* platform devices without drivers should be disabled */
+                hwblk_enable(hwblk_info, hwblk);
+                hwblk_disable(hwblk_info, hwblk);
+                /* make sure driver re-inits itself once */
+                __set_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags);
+                break;
+        /* TODO: add BUS_NOTIFY_BIND_DRIVER and increase idle count */
+        case BUS_NOTIFY_BOUND_DRIVER:
+                /* keep track of number of devices in use per hwblk */
+                hwblk_cnt_inc(hwblk_info, hwblk, HWBLK_CNT_DEVICES);
+                break;
+        case BUS_NOTIFY_UNBOUND_DRIVER:
+                /* keep track of number of devices in use per hwblk */
+                hwblk_cnt_dec(hwblk_info, hwblk, HWBLK_CNT_DEVICES);
+                /* make sure driver re-inits itself once */
+                __set_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags);
+                break;
+        case BUS_NOTIFY_DEL_DEVICE:
+                break;
+        }
+        return 0;
+}
+
+static struct notifier_block platform_bus_notifier = {
+        .notifier_call = platform_bus_notify
+};
+
+static int __init sh_pm_runtime_init(void)
+{
+        INIT_WORK(&hwblk_work, platform_pm_runtime_work);
+
+        bus_register_notifier(&platform_bus_type, &platform_bus_notifier);
+        return 0;
+}
+core_initcall(sh_pm_runtime_init);
diff --git a/arch/sh/kernel/dwarf.c b/arch/sh/kernel/dwarf.c
index 5fd6e604816d..bc4d8d75332b 100644
--- a/arch/sh/kernel/dwarf.c
+++ b/arch/sh/kernel/dwarf.c
@@ -11,12 +11,14 @@
  *
  * TODO:
  *      - DWARF64 doesn't work.
+ *      - Registers with DWARF_VAL_OFFSET rules aren't handled properly.
  */
 
 /* #define DEBUG */
 #include <linux/kernel.h>
 #include <linux/io.h>
 #include <linux/list.h>
+#include <linux/mempool.h>
 #include <linux/mm.h>
 #include <asm/dwarf.h>
 #include <asm/unwinder.h>
@@ -25,55 +27,89 @@
 #include <asm/dwarf.h>
 #include <asm/stacktrace.h>
 
+/* Reserve enough memory for two stack frames */
+#define DWARF_FRAME_MIN_REQ     2
+/* ... with 4 registers per frame. */
+#define DWARF_REG_MIN_REQ       (DWARF_FRAME_MIN_REQ * 4)
+
+static struct kmem_cache *dwarf_frame_cachep;
+static mempool_t *dwarf_frame_pool;
+
+static struct kmem_cache *dwarf_reg_cachep;
+static mempool_t *dwarf_reg_pool;
+
 static LIST_HEAD(dwarf_cie_list);
-DEFINE_SPINLOCK(dwarf_cie_lock);
+static DEFINE_SPINLOCK(dwarf_cie_lock);
 
 static LIST_HEAD(dwarf_fde_list);
-DEFINE_SPINLOCK(dwarf_fde_lock);
+static DEFINE_SPINLOCK(dwarf_fde_lock);
 
 static struct dwarf_cie *cached_cie;
 
-/*
- * Figure out whether we need to allocate some dwarf registers. If dwarf
- * registers have already been allocated then we may need to realloc
- * them. "reg" is a register number that we need to be able to access
- * after this call.
+/**
+ *      dwarf_frame_alloc_reg - allocate memory for a DWARF register
+ *      @frame: the DWARF frame whose list of registers we insert on
+ *      @reg_num: the register number
+ *
+ *      Allocate space for, and initialise, a dwarf reg from
+ *      dwarf_reg_pool and insert it onto the (unsorted) linked-list of
+ *      dwarf registers for @frame.
  *
- * Register numbers start at zero, therefore we need to allocate space
- * for "reg" + 1 registers.
+ *      Return the initialised DWARF reg.
  */
-static void dwarf_frame_alloc_regs(struct dwarf_frame *frame,
-                                   unsigned int reg)
+static struct dwarf_reg *dwarf_frame_alloc_reg(struct dwarf_frame *frame,
+                                               unsigned int reg_num)
 {
-        struct dwarf_reg *regs;
-        unsigned int num_regs = reg + 1;
-        size_t new_size;
-        size_t old_size;
-
-        new_size = num_regs * sizeof(*regs);
-        old_size = frame->num_regs * sizeof(*regs);
+        struct dwarf_reg *reg;
 
-        /* Fast path: don't allocate any regs if we've already got enough. */
-        if (frame->num_regs >= num_regs)
-                return;
-
-        regs = kzalloc(new_size, GFP_ATOMIC);
-        if (!regs) {
-                printk(KERN_WARNING "Unable to allocate DWARF registers\n");
+        reg = mempool_alloc(dwarf_reg_pool, GFP_ATOMIC);
+        if (!reg) {
+                printk(KERN_WARNING "Unable to allocate a DWARF register\n");
                 /*
                  * Let's just bomb hard here, we have no way to
                  * gracefully recover.
                  */
-                BUG();
+                UNWINDER_BUG();
+        }
+
+        reg->number = reg_num;
+        reg->addr = 0;
+        reg->flags = 0;
+
+        list_add(&reg->link, &frame->reg_list);
+
+        return reg;
+}
+
+static void dwarf_frame_free_regs(struct dwarf_frame *frame)
+{
+        struct dwarf_reg *reg, *n;
+
+        list_for_each_entry_safe(reg, n, &frame->reg_list, link) {
+                list_del(&reg->link);
+                mempool_free(reg, dwarf_reg_pool);
         }
+}
+
+/**
+ *      dwarf_frame_reg - return a DWARF register
+ *      @frame: the DWARF frame to search in for @reg_num
+ *      @reg_num: the register number to search for
+ *
+ *      Lookup and return the dwarf reg @reg_num for this frame. Return
+ *      NULL if @reg_num is an register invalid number.
+ */
+static struct dwarf_reg *dwarf_frame_reg(struct dwarf_frame *frame,
+                                         unsigned int reg_num)
+{
+        struct dwarf_reg *reg;
 
-        if (frame->regs) {
-                memcpy(regs, frame->regs, old_size);
-                kfree(frame->regs);
+        list_for_each_entry(reg, &frame->reg_list, link) {
+                if (reg->number == reg_num)
+                        return reg;
         }
 
-        frame->regs = regs;
-        frame->num_regs = num_regs;
+        return NULL;
 }
 
 /**
@@ -196,7 +232,7 @@ static int dwarf_read_encoded_value(char *addr, unsigned long *val,
                 break;
         default:
                 pr_debug("encoding=0x%x\n", (encoding & 0x70));
-                BUG();
+                UNWINDER_BUG();
         }
 
         if ((encoding & 0x07) == 0x00)
@@ -211,7 +247,7 @@ static int dwarf_read_encoded_value(char *addr, unsigned long *val,
                 break;
         default:
                 pr_debug("encoding=0x%x\n", encoding);
-                BUG();
+                UNWINDER_BUG();
         }
 
         return count;
@@ -264,7 +300,7 @@ static inline int dwarf_entry_len(char *addr, unsigned long *len)
  */
 static struct dwarf_cie *dwarf_lookup_cie(unsigned long cie_ptr)
 {
-        struct dwarf_cie *cie, *n;
+        struct dwarf_cie *cie;
         unsigned long flags;
 
         spin_lock_irqsave(&dwarf_cie_lock, flags);
@@ -278,7 +314,7 @@ static struct dwarf_cie *dwarf_lookup_cie(unsigned long cie_ptr)
                 goto out;
         }
 
-        list_for_each_entry_safe(cie, n, &dwarf_cie_list, link) {
+        list_for_each_entry(cie, &dwarf_cie_list, link) {
                 if (cie->cie_pointer == cie_ptr) {
                         cached_cie = cie;
                         break;
@@ -299,11 +335,12 @@ out:
  */
 struct dwarf_fde *dwarf_lookup_fde(unsigned long pc)
 {
+        struct dwarf_fde *fde;
         unsigned long flags;
-        struct dwarf_fde *fde, *n;
 
         spin_lock_irqsave(&dwarf_fde_lock, flags);
-        list_for_each_entry_safe(fde, n, &dwarf_fde_list, link) {
+
+        list_for_each_entry(fde, &dwarf_fde_list, link) {
                 unsigned long start, end;
 
                 start = fde->initial_location;
@@ -346,6 +383,7 @@ static int dwarf_cfa_execute_insns(unsigned char *insn_start,
         unsigned char insn;
         unsigned char *current_insn;
         unsigned int count, delta, reg, expr_len, offset;
+        struct dwarf_reg *regp;
 
         current_insn = insn_start;
 
@@ -368,9 +406,9 @@ static int dwarf_cfa_execute_insns(unsigned char *insn_start,
                         count = dwarf_read_uleb128(current_insn, &offset);
                         current_insn += count;
                         offset *= cie->data_alignment_factor;
-                        dwarf_frame_alloc_regs(frame, reg);
-                        frame->regs[reg].addr = offset;
-                        frame->regs[reg].flags |= DWARF_REG_OFFSET;
+                        regp = dwarf_frame_alloc_reg(frame, reg);
+                        regp->addr = offset;
+                        regp->flags |= DWARF_REG_OFFSET;
                         continue;
                         /* NOTREACHED */
                 case DW_CFA_restore:
@@ -414,6 +452,8 @@ static int dwarf_cfa_execute_insns(unsigned char *insn_start,
                 case DW_CFA_undefined:
                         count = dwarf_read_uleb128(current_insn, &reg);
                         current_insn += count;
+                        regp = dwarf_frame_alloc_reg(frame, reg);
+                        regp->flags |= DWARF_UNDEFINED;
                         break;
                 case DW_CFA_def_cfa:
                         count = dwarf_read_uleb128(current_insn,
@@ -452,17 +492,18 @@ static int dwarf_cfa_execute_insns(unsigned char *insn_start,
                         count = dwarf_read_leb128(current_insn, &offset);
                         current_insn += count;
                         offset *= cie->data_alignment_factor;
-                        dwarf_frame_alloc_regs(frame, reg);
-                        frame->regs[reg].flags |= DWARF_REG_OFFSET;
-                        frame->regs[reg].addr = offset;
+                        regp = dwarf_frame_alloc_reg(frame, reg);
+                        regp->flags |= DWARF_REG_OFFSET;
+                        regp->addr = offset;
                         break;
                 case DW_CFA_val_offset:
                         count = dwarf_read_uleb128(current_insn, &reg);
                         current_insn += count;
                         count = dwarf_read_leb128(current_insn, &offset);
                         offset *= cie->data_alignment_factor;
-                        frame->regs[reg].flags |= DWARF_REG_OFFSET;
-                        frame->regs[reg].addr = offset;
+                        regp = dwarf_frame_alloc_reg(frame, reg);
+                        regp->flags |= DWARF_VAL_OFFSET;
+                        regp->addr = offset;
                         break;
                 case DW_CFA_GNU_args_size:
                         count = dwarf_read_uleb128(current_insn, &offset);
@@ -473,12 +514,14 @@ static int dwarf_cfa_execute_insns(unsigned char *insn_start,
                         current_insn += count;
                         count = dwarf_read_uleb128(current_insn, &offset);
                         offset *= cie->data_alignment_factor;
-                        dwarf_frame_alloc_regs(frame, reg);
-                        frame->regs[reg].flags |= DWARF_REG_OFFSET;
-                        frame->regs[reg].addr = -offset;
+
+                        regp = dwarf_frame_alloc_reg(frame, reg);
+                        regp->flags |= DWARF_REG_OFFSET;
+                        regp->addr = -offset;
                         break;
                 default:
                         pr_debug("unhandled DWARF instruction 0x%x\n", insn);
+                        UNWINDER_BUG();
                         break;
                 }
         }
@@ -495,14 +538,14 @@ static int dwarf_cfa_execute_insns(unsigned char *insn_start,
  *      on the callstack. Each of the lower (older) stack frames are
  *      linked via the "prev" member.
  */
-struct dwarf_frame *dwarf_unwind_stack(unsigned long pc,
-                                       struct dwarf_frame *prev)
+struct dwarf_frame * dwarf_unwind_stack(unsigned long pc,
+                                        struct dwarf_frame *prev)
 {
         struct dwarf_frame *frame;
         struct dwarf_cie *cie;
         struct dwarf_fde *fde;
+        struct dwarf_reg *reg;
         unsigned long addr;
-        int i, offset;
 
         /*
          * If this is the first invocation of this recursive function we
@@ -515,11 +558,16 @@ struct dwarf_frame *dwarf_unwind_stack(unsigned long pc,
         if (!pc && !prev)
                 pc = (unsigned long)current_text_addr();
 
-        frame = kzalloc(sizeof(*frame), GFP_ATOMIC);
-        if (!frame)
-                return NULL;
+        frame = mempool_alloc(dwarf_frame_pool, GFP_ATOMIC);
+        if (!frame) {
+                printk(KERN_ERR "Unable to allocate a dwarf frame\n");
+                UNWINDER_BUG();
+        }
 
+        INIT_LIST_HEAD(&frame->reg_list);
+        frame->flags = 0;
         frame->prev = prev;
+        frame->return_addr = 0;
 
         fde = dwarf_lookup_fde(pc);
         if (!fde) {
@@ -539,7 +587,7 @@ struct dwarf_frame *dwarf_unwind_stack(unsigned long pc,
                  *      case above, which sucks because we could print a
                  *      warning here.
                  */
-                return NULL;
+                goto bail;
         }
 
         cie = dwarf_lookup_cie(fde->cie_pointer);
@@ -559,10 +607,11 @@ struct dwarf_frame *dwarf_unwind_stack(unsigned long pc,
         switch (frame->flags) {
         case DWARF_FRAME_CFA_REG_OFFSET:
                 if (prev) {
-                        BUG_ON(!prev->regs[frame->cfa_register].flags);
+                        reg = dwarf_frame_reg(prev, frame->cfa_register);
+                        UNWINDER_BUG_ON(!reg);
+                        UNWINDER_BUG_ON(reg->flags != DWARF_REG_OFFSET);
 
-                        addr = prev->cfa;
-                        addr += prev->regs[frame->cfa_register].addr;
+                        addr = prev->cfa + reg->addr;
                         frame->cfa = __raw_readl(addr);
 
                 } else {
@@ -579,27 +628,30 @@ struct dwarf_frame *dwarf_unwind_stack(unsigned long pc,
                 frame->cfa += frame->cfa_offset;
                 break;
         default:
-                BUG();
+                UNWINDER_BUG();
         }
 
-        /* If we haven't seen the return address reg, we're screwed. */
-        BUG_ON(!frame->regs[DWARF_ARCH_RA_REG].flags);
-
-        for (i = 0; i <= frame->num_regs; i++) {
-                struct dwarf_reg *reg = &frame->regs[i];
+        reg = dwarf_frame_reg(frame, DWARF_ARCH_RA_REG);
 
-                if (!reg->flags)
-                        continue;
+        /*
+         * If we haven't seen the return address register or the return
+         * address column is undefined then we must assume that this is
+         * the end of the callstack.
+         */
+        if (!reg || reg->flags == DWARF_UNDEFINED)
+                goto bail;
 
-                offset = reg->addr;
-                offset += frame->cfa;
-        }
+        UNWINDER_BUG_ON(reg->flags != DWARF_REG_OFFSET);
 
-        addr = frame->cfa + frame->regs[DWARF_ARCH_RA_REG].addr;
+        addr = frame->cfa + reg->addr;
         frame->return_addr = __raw_readl(addr);
 
-        frame->next = dwarf_unwind_stack(frame->return_addr, frame);
         return frame;
+
+bail:
+        dwarf_frame_free_regs(frame);
+        mempool_free(frame, dwarf_frame_pool);
+        return NULL;
 }
 
 static int dwarf_parse_cie(void *entry, void *p, unsigned long len,
@@ -624,7 +676,7 @@ static int dwarf_parse_cie(void *entry, void *p, unsigned long len,
         cie->cie_pointer = (unsigned long)entry;
 
         cie->version = *(char *)p++;
-        BUG_ON(cie->version != 1);
+        UNWINDER_BUG_ON(cie->version != 1);
 
         cie->augmentation = p;
         p += strlen(cie->augmentation) + 1;
@@ -654,7 +706,7 @@ static int dwarf_parse_cie(void *entry, void *p, unsigned long len,
                 count = dwarf_read_uleb128(p, &length);
                 p += count;
 
-                BUG_ON((unsigned char *)p > end);
+                UNWINDER_BUG_ON((unsigned char *)p > end);
 
                 cie->initial_instructions = p + length;
                 cie->augmentation++;
@@ -682,16 +734,16 @@ static int dwarf_parse_cie(void *entry, void *p, unsigned long len,
                          * routine in the CIE
                          * augmentation.
                          */
-                        BUG();
+                        UNWINDER_BUG();
                 } else if (*cie->augmentation == 'S') {
-                        BUG();
+                        UNWINDER_BUG();
                 } else {
                         /*
                          * Unknown augmentation. Assume
                          * 'z' augmentation.
                          */
                         p = cie->initial_instructions;
-                        BUG_ON(!p);
+                        UNWINDER_BUG_ON(!p);
                         break;
                 }
         }
@@ -708,7 +760,8 @@ static int dwarf_parse_cie(void *entry, void *p, unsigned long len,
 }
 
 static int dwarf_parse_fde(void *entry, u32 entry_type,
-                           void *start, unsigned long len)
+                           void *start, unsigned long len,
+                           unsigned char *end)
 {
         struct dwarf_fde *fde;
         struct dwarf_cie *cie;
@@ -755,7 +808,7 @@ static int dwarf_parse_fde(void *entry, u32 entry_type,
 
         /* Call frame instructions. */
         fde->instructions = p;
-        fde->end = start + len;
+        fde->end = end;
 
         /* Add to list. */
         spin_lock_irqsave(&dwarf_fde_lock, flags);
@@ -765,17 +818,33 @@ static int dwarf_parse_fde(void *entry, u32 entry_type,
         return 0;
 }
 
-static void dwarf_unwinder_dump(struct task_struct *task, struct pt_regs *regs,
+static void dwarf_unwinder_dump(struct task_struct *task,
+                                struct pt_regs *regs,
                                 unsigned long *sp,
-                                const struct stacktrace_ops *ops, void *data)
+                                const struct stacktrace_ops *ops,
+                                void *data)
 {
-        struct dwarf_frame *frame;
+        struct dwarf_frame *frame, *_frame;
+        unsigned long return_addr;
 
-        frame = dwarf_unwind_stack(0, NULL);
+        _frame = NULL;
+        return_addr = 0;
+
+        while (1) {
+                frame = dwarf_unwind_stack(return_addr, _frame);
+
+                if (_frame) {
+                        dwarf_frame_free_regs(_frame);
+                        mempool_free(_frame, dwarf_frame_pool);
+                }
+
+                _frame = frame;
+
+                if (!frame || !frame->return_addr)
+                        break;
 
-        while (frame && frame->return_addr) {
-                ops->address(data, frame->return_addr, 1);
-                frame = frame->next;
+                return_addr = frame->return_addr;
+                ops->address(data, return_addr, 1);
         }
 }
 
@@ -787,24 +856,22 @@ static struct unwinder dwarf_unwinder = {
 
 static void dwarf_unwinder_cleanup(void)
 {
-        struct dwarf_cie *cie, *m;
-        struct dwarf_fde *fde, *n;
-        unsigned long flags;
+        struct dwarf_cie *cie;
+        struct dwarf_fde *fde;
 
         /*
          * Deallocate all the memory allocated for the DWARF unwinder.
          * Traverse all the FDE/CIE lists and remove and free all the
          * memory associated with those data structures.
          */
-        spin_lock_irqsave(&dwarf_cie_lock, flags);
-        list_for_each_entry_safe(cie, m, &dwarf_cie_list, link)
+        list_for_each_entry(cie, &dwarf_cie_list, link)
                 kfree(cie);
-        spin_unlock_irqrestore(&dwarf_cie_lock, flags);
 
-        spin_lock_irqsave(&dwarf_fde_lock, flags);
-        list_for_each_entry_safe(fde, n, &dwarf_fde_list, link)
+        list_for_each_entry(fde, &dwarf_fde_list, link)
                 kfree(fde);
-        spin_unlock_irqrestore(&dwarf_fde_lock, flags);
+
+        kmem_cache_destroy(dwarf_reg_cachep);
+        kmem_cache_destroy(dwarf_frame_cachep);
 }
 
 /**
@@ -816,11 +883,11 @@ static void dwarf_unwinder_cleanup(void)
  *      easy to lookup the FDE for a given PC, so we build a list of FDE
  *      and CIE entries that make it easier.
  */
-void dwarf_unwinder_init(void)
+static int __init dwarf_unwinder_init(void)
 {
         u32 entry_type;
         void *p, *entry;
-        int count, err;
+        int count, err = 0;
         unsigned long len;
         unsigned int c_entries, f_entries;
         unsigned char *end;
@@ -831,6 +898,24 @@ void dwarf_unwinder_init(void)
         f_entries = 0;
         entry = &__start_eh_frame;
 
+        dwarf_frame_cachep = kmem_cache_create("dwarf_frames",
+                        sizeof(struct dwarf_frame), 0,
+                        SLAB_PANIC | SLAB_HWCACHE_ALIGN | SLAB_NOTRACK, NULL);
+
+        dwarf_reg_cachep = kmem_cache_create("dwarf_regs",
+                        sizeof(struct dwarf_reg), 0,
+                        SLAB_PANIC | SLAB_HWCACHE_ALIGN | SLAB_NOTRACK, NULL);
+
+        dwarf_frame_pool = mempool_create(DWARF_FRAME_MIN_REQ,
+                                          mempool_alloc_slab,
+                                          mempool_free_slab,
+                                          dwarf_frame_cachep);
+
+        dwarf_reg_pool = mempool_create(DWARF_REG_MIN_REQ,
+                                         mempool_alloc_slab,
+                                         mempool_free_slab,
+                                         dwarf_reg_cachep);
+
         while ((char *)entry < __stop_eh_frame) {
                 p = entry;
 
@@ -860,7 +945,7 @@ void dwarf_unwinder_init(void)
                         else
                                 c_entries++;
                 } else {
-                        err = dwarf_parse_fde(entry, entry_type, p, len);
+                        err = dwarf_parse_fde(entry, entry_type, p, len, end);
                         if (err < 0)
                                 goto out;
                         else
@@ -877,9 +962,11 @@ void dwarf_unwinder_init(void)
         if (err)
                 goto out;
 
-        return;
+        return 0;
 
 out:
         printk(KERN_ERR "Failed to initialise DWARF unwinder: %d\n", err);
         dwarf_unwinder_cleanup();
+        return -EINVAL;
 }
+early_initcall(dwarf_unwinder_init);
diff --git a/arch/sh/kernel/entry-common.S b/arch/sh/kernel/entry-common.S
index 700477601c6f..68d9223b145e 100644
--- a/arch/sh/kernel/entry-common.S
+++ b/arch/sh/kernel/entry-common.S
@@ -98,8 +98,9 @@ need_resched:
 
         mov     #OFF_SR, r0
         mov.l   @(r0,r15), r0           ! get status register
-        and     #0xf0, r0               ! interrupts off (exception path)?
-        cmp/eq  #0xf0, r0
+        shlr    r0
+        and     #(0xf0>>1), r0          ! interrupts off (exception path)?
+        cmp/eq  #(0xf0>>1), r0
         bt      noresched
         mov.l   3f, r0
         jsr     @r0                     ! call preempt_schedule_irq
diff --git a/arch/sh/kernel/ftrace.c b/arch/sh/kernel/ftrace.c
index 6647dfcb781d..a3dcc6d5d253 100644
--- a/arch/sh/kernel/ftrace.c
+++ b/arch/sh/kernel/ftrace.c
@@ -283,8 +283,6 @@ static struct syscall_metadata *find_syscall_meta(unsigned long *syscall)
         return NULL;
 }
 
-#define FTRACE_SYSCALL_MAX      (NR_syscalls - 1)
-
 struct syscall_metadata *syscall_nr_to_meta(int nr)
 {
         if (!syscalls_metadata || nr >= FTRACE_SYSCALL_MAX || nr < 0)
diff --git a/arch/sh/kernel/io.c b/arch/sh/kernel/io.c
index 4f85fffaa557..4770c241c679 100644
--- a/arch/sh/kernel/io.c
+++ b/arch/sh/kernel/io.c
@@ -1,12 +1,9 @@
 /*
- * linux/arch/sh/kernel/io.c
+ * arch/sh/kernel/io.c - Machine independent I/O functions.
  *
- * Copyright (C) 2000  Stuart Menefy
+ * Copyright (C) 2000 - 2009  Stuart Menefy
  * Copyright (C) 2005  Paul Mundt
  *
- * Provide real functions which expand to whatever the header file defined.
- * Also definitions of machine independent IO functions.
- *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
@@ -18,33 +15,87 @@
 
 /*
  * Copy data from IO memory space to "real" memory space.
- * This needs to be optimized.
  */
 void memcpy_fromio(void *to, const volatile void __iomem *from, unsigned long count)
 {
-        unsigned char *p = to;
-        while (count) {
-                count--;
-                *p = readb(from);
-                p++;
-                from++;
-        }
+        /*
+         * Would it be worthwhile doing byte and long transfers first
+         * to try and get aligned?
+         */
+#ifdef CONFIG_CPU_SH4
+        if ((count >= 0x20) &&
+             (((u32)to & 0x1f) == 0) && (((u32)from & 0x3) == 0)) {
+                int tmp2, tmp3, tmp4, tmp5, tmp6;
+
+                __asm__ __volatile__(
+                        "1:                     \n\t"
+                        "mov.l  @%7+, r0        \n\t"
+                        "mov.l  @%7+, %2        \n\t"
+                        "movca.l r0, @%0        \n\t"
+                        "mov.l  @%7+, %3        \n\t"
+                        "mov.l  @%7+, %4        \n\t"
+                        "mov.l  @%7+, %5        \n\t"
+                        "mov.l  @%7+, %6        \n\t"
+                        "mov.l  @%7+, r7        \n\t"
+                        "mov.l  @%7+, r0        \n\t"
+                        "mov.l  %2, @(0x04,%0)  \n\t"
+                        "mov    #0x20, %2       \n\t"
+                        "mov.l  %3, @(0x08,%0)  \n\t"
+                        "sub    %2, %1          \n\t"
+                        "mov.l  %4, @(0x0c,%0)  \n\t"
+                        "cmp/hi %1, %2          ! T if 32 > count       \n\t"
+                        "mov.l  %5, @(0x10,%0)  \n\t"
+                        "mov.l  %6, @(0x14,%0)  \n\t"
+                        "mov.l  r7, @(0x18,%0)  \n\t"
+                        "mov.l  r0, @(0x1c,%0)  \n\t"
+                        "bf.s   1b              \n\t"
+                        " add   #0x20, %0       \n\t"
+                        : "=&r" (to), "=&r" (count),
+                          "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4),
+                          "=&r" (tmp5), "=&r" (tmp6), "=&r" (from)
+                        : "7"(from), "0" (to), "1" (count)
+                        : "r0", "r7", "t", "memory");
+        }
+#endif
+
+        if ((((u32)to | (u32)from) & 0x3) == 0) {
+                for (; count > 3; count -= 4) {
+                        *(u32 *)to = *(volatile u32 *)from;
+                        to += 4;
+                        from += 4;
+                }
+        }
+
+        for (; count > 0; count--) {
+                *(u8 *)to = *(volatile u8 *)from;
+                to++;
+                from++;
+        }
+
+        mb();
 }
 EXPORT_SYMBOL(memcpy_fromio);
 
 /*
  * Copy data from "real" memory space to IO memory space.
- * This needs to be optimized.
  */
 void memcpy_toio(volatile void __iomem *to, const void *from, unsigned long count)
 {
-        const unsigned char *p = from;
-        while (count) {
-                count--;
-                writeb(*p, to);
-                p++;
-                to++;
-        }
+        if ((((u32)to | (u32)from) & 0x3) == 0) {
+                for ( ; count > 3; count -= 4) {
+                        *(volatile u32 *)to = *(u32 *)from;
+                        to += 4;
+                        from += 4;
+                }
+        }
+
+        for (; count > 0; count--) {
+                *(volatile u8 *)to = *(u8 *)from;
+                to++;
+                from++;
+        }
+
+        mb();
 }
 EXPORT_SYMBOL(memcpy_toio);
 
@@ -62,6 +113,8 @@ void memset_io(volatile void __iomem *dst, int c, unsigned long count)
 }
 EXPORT_SYMBOL(memset_io);
 
+#ifndef CONFIG_GENERIC_IOMAP
+
 void __iomem *ioport_map(unsigned long port, unsigned int nr)
 {
         void __iomem *ret;
@@ -79,3 +132,5 @@ void ioport_unmap(void __iomem *addr)
         sh_mv.mv_ioport_unmap(addr);
 }
 EXPORT_SYMBOL(ioport_unmap);
+
+#endif /* CONFIG_GENERIC_IOMAP */
diff --git a/arch/sh/kernel/io_generic.c b/arch/sh/kernel/io_generic.c
index 5a7f554d9ca1..4ff507239286 100644
--- a/arch/sh/kernel/io_generic.c
+++ b/arch/sh/kernel/io_generic.c
@@ -73,35 +73,19 @@ u32 generic_inl_p(unsigned long port)
 
 void generic_insb(unsigned long port, void *dst, unsigned long count)
 {
-        volatile u8 *port_addr;
-        u8 *buf = dst;
-
-        port_addr = (volatile u8 __force *)__ioport_map(port, 1);
-        while (count--)
-                *buf++ = *port_addr;
+        __raw_readsb(__ioport_map(port, 1), dst, count);
+        dummy_read();
 }
 
 void generic_insw(unsigned long port, void *dst, unsigned long count)
 {
-        volatile u16 *port_addr;
-        u16 *buf = dst;
-
-        port_addr = (volatile u16 __force *)__ioport_map(port, 2);
-        while (count--)
-                *buf++ = *port_addr;
-
+        __raw_readsw(__ioport_map(port, 2), dst, count);
         dummy_read();
 }
 
 void generic_insl(unsigned long port, void *dst, unsigned long count)
 {
-        volatile u32 *port_addr;
-        u32 *buf = dst;
-
-        port_addr = (volatile u32 __force *)__ioport_map(port, 4);
-        while (count--)
-                *buf++ = *port_addr;
-
+        __raw_readsl(__ioport_map(port, 4), dst, count);
         dummy_read();
 }
 
@@ -145,37 +129,19 @@ void generic_outl_p(u32 b, unsigned long port)
  */
 void generic_outsb(unsigned long port, const void *src, unsigned long count)
 {
-        volatile u8 *port_addr;
-        const u8 *buf = src;
-
-        port_addr = (volatile u8 __force *)__ioport_map(port, 1);
-
-        while (count--)
-                *port_addr = *buf++;
+        __raw_writesb(__ioport_map(port, 1), src, count);
+        dummy_read();
 }
 
 void generic_outsw(unsigned long port, const void *src, unsigned long count)
 {
-        volatile u16 *port_addr;
-        const u16 *buf = src;
-
-        port_addr = (volatile u16 __force *)__ioport_map(port, 2);
-
-        while (count--)
-                *port_addr = *buf++;
-
+        __raw_writesw(__ioport_map(port, 2), src, count);
         dummy_read();
 }
 
 void generic_outsl(unsigned long port, const void *src, unsigned long count)
 {
-        volatile u32 *port_addr;
-        const u32 *buf = src;
-
-        port_addr = (volatile u32 __force *)__ioport_map(port, 4);
-        while (count--)
-                *port_addr = *buf++;
-
+        __raw_writesl(__ioport_map(port, 4), src, count);
         dummy_read();
 }
 
diff --git a/arch/sh/kernel/io_trapped.c b/arch/sh/kernel/io_trapped.c
index e27a19e1f46e..69be603aa2d7 100644
--- a/arch/sh/kernel/io_trapped.c
+++ b/arch/sh/kernel/io_trapped.c
@@ -284,7 +284,8 @@ int handle_trapped_io(struct pt_regs *regs, unsigned long address)
                 return 0;
         }
 
-        tmp = handle_unaligned_access(instruction, regs, &trapped_io_access);
+        tmp = handle_unaligned_access(instruction, regs,
+                                      &trapped_io_access, 1);
         set_fs(oldfs);
         return tmp == 0;
 }
diff --git a/arch/sh/kernel/irq.c b/arch/sh/kernel/irq.c
index 2bb43dc74f22..d1053392e287 100644
--- a/arch/sh/kernel/irq.c
+++ b/arch/sh/kernel/irq.c
@@ -14,7 +14,6 @@
 #include <asm/processor.h>
 #include <asm/machvec.h>
 #include <asm/uaccess.h>
-#include <asm/dwarf.h>
 #include <asm/thread_info.h>
 #include <cpu/mmu_context.h>
 
@@ -115,7 +114,7 @@ asmlinkage int do_IRQ(unsigned int irq, struct pt_regs *regs)
 #endif
 
         irq_enter();
-        irq = irq_demux(intc_evt2irq(irq));
+        irq = irq_demux(evt2irq(irq));
 
 #ifdef CONFIG_IRQSTACKS
         curctx = (union irq_ctx *)current_thread_info();
@@ -262,9 +261,6 @@ void __init init_IRQ(void)
                 sh_mv.mv_init_irq();
 
         irq_ctx_init(smp_processor_id());
-
-        /* This needs to be early, but not too early.. */
-        dwarf_unwinder_init();
 }
 
 #ifdef CONFIG_SPARSE_IRQ
diff --git a/arch/sh/kernel/kgdb.c b/arch/sh/kernel/kgdb.c
index 305aad742aec..d29de7864f32 100644
--- a/arch/sh/kernel/kgdb.c
+++ b/arch/sh/kernel/kgdb.c
@@ -195,8 +195,6 @@ void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
         regs->gbr = gdb_regs[GDB_GBR];
         regs->mach = gdb_regs[GDB_MACH];
         regs->macl = gdb_regs[GDB_MACL];
-
-        __asm__ __volatile__ ("ldc %0, vbr" : : "r" (gdb_regs[GDB_VBR]));
 }
 
 void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
diff --git a/arch/sh/kernel/process_32.c b/arch/sh/kernel/process_32.c
index 9fee977f176b..0673c4746be3 100644
--- a/arch/sh/kernel/process_32.c
+++ b/arch/sh/kernel/process_32.c
@@ -32,15 +32,35 @@
 #include <asm/ubc.h>
 #include <asm/fpu.h>
 #include <asm/syscalls.h>
+#include <asm/watchdog.h>
 
 int ubc_usercnt = 0;
 
+#ifdef CONFIG_32BIT
+static void watchdog_trigger_immediate(void)
+{
+        sh_wdt_write_cnt(0xFF);
+        sh_wdt_write_csr(0xC2);
+}
+
+void machine_restart(char * __unused)
+{
+        local_irq_disable();
+
+        /* Use watchdog timer to trigger reset */
+        watchdog_trigger_immediate();
+
+        while (1)
+                cpu_sleep();
+}
+#else
 void machine_restart(char * __unused)
 {
         /* SR.BL=1 and invoke address error to let CPU reset (manual reset) */
         asm volatile("ldc %0, sr\n\t"
                      "mov.l @%1, %0" : : "r" (0x10000000), "r" (0x80000001));
 }
+#endif
 
 void machine_halt(void)
 {
diff --git a/arch/sh/kernel/ptrace_32.c b/arch/sh/kernel/ptrace_32.c
index c198eceaee94..f4f58e438a26 100644
--- a/arch/sh/kernel/ptrace_32.c
+++ b/arch/sh/kernel/ptrace_32.c
@@ -461,8 +461,10 @@ asmlinkage long do_syscall_trace_enter(struct pt_regs *regs)
                  */
                 ret = -1L;
 
+#ifdef CONFIG_FTRACE_SYSCALLS
         if (unlikely(test_thread_flag(TIF_SYSCALL_FTRACE)))
                 ftrace_syscall_enter(regs);
+#endif
 
         if (unlikely(current->audit_context))
                 audit_syscall_entry(audit_arch(), regs->regs[3],
@@ -480,8 +482,10 @@ asmlinkage void do_syscall_trace_leave(struct pt_regs *regs)
                 audit_syscall_exit(AUDITSC_RESULT(regs->regs[0]),
                                    regs->regs[0]);
 
+#ifdef CONFIG_FTRACE_SYSCALLS
         if (unlikely(test_thread_flag(TIF_SYSCALL_FTRACE)))
                 ftrace_syscall_exit(regs);
+#endif
 
         step = test_thread_flag(TIF_SINGLESTEP);
         if (step || test_thread_flag(TIF_SYSCALL_TRACE))
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index dc403e42bcab..f9d44f8e0df6 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -405,10 +405,14 @@ void __init setup_arch(char **cmdline_p)
         if (!memory_end)
                 memory_end = memory_start + __MEMORY_SIZE;
 
-#ifdef CONFIG_CMDLINE_BOOL
+#ifdef CONFIG_CMDLINE_OVERWRITE
         strlcpy(command_line, CONFIG_CMDLINE, sizeof(command_line));
 #else
         strlcpy(command_line, COMMAND_LINE, sizeof(command_line));
+#ifdef CONFIG_CMDLINE_EXTEND
+        strlcat(command_line, " ", sizeof(command_line));
+        strlcat(command_line, CONFIG_CMDLINE, sizeof(command_line));
+#endif
 #endif
 
         /* Save unparsed command line copy for /proc/cmdline */
@@ -482,7 +486,7 @@ static const char *cpu_name[] = {
         [CPU_SH7763]    = "SH7763",     [CPU_SH7770]    = "SH7770",
         [CPU_SH7780]    = "SH7780",     [CPU_SH7781]    = "SH7781",
         [CPU_SH7343]    = "SH7343",     [CPU_SH7785]    = "SH7785",
-        [CPU_SH7786]    = "SH7786",
+        [CPU_SH7786]    = "SH7786",     [CPU_SH7757]    = "SH7757",
         [CPU_SH7722]    = "SH7722",     [CPU_SHX3]      = "SH-X3",
         [CPU_SH5_101]   = "SH5-101",    [CPU_SH5_103]   = "SH5-103",
         [CPU_MXG]       = "MX-G",       [CPU_SH7723]    = "SH7723",
diff --git a/arch/sh/kernel/signal_32.c b/arch/sh/kernel/signal_32.c
index b5afbec1db59..6010750c90b4 100644
--- a/arch/sh/kernel/signal_32.c
+++ b/arch/sh/kernel/signal_32.c
@@ -41,6 +41,16 @@ struct fdpic_func_descriptor {
 };
 
 /*
+ * The following define adds a 64 byte gap between the signal
+ * stack frame and previous contents of the stack.  This allows
+ * frame unwinding in a function epilogue but only if a frame
+ * pointer is used in the function.  This is necessary because
+ * current gcc compilers (<4.3) do not generate unwind info on
+ * SH for function epilogues.
+ */
+#define UNWINDGUARD 64
+
+/*
  * Atomically swap in the new signal mask, and wait for a signal.
  */
 asmlinkage int
@@ -327,7 +337,7 @@ get_sigframe(struct k_sigaction *ka, unsigned long sp, size_t frame_size)
                         sp = current->sas_ss_sp + current->sas_ss_size;
         }
 
-        return (void __user *)((sp - frame_size) & -8ul);
+        return (void __user *)((sp - (frame_size+UNWINDGUARD)) & -8ul);
 }
 
 /* These symbols are defined with the addresses in the vsyscall page.
diff --git a/arch/sh/kernel/sys_sh.c b/arch/sh/kernel/sys_sh.c
index 90d00e47264d..8aa5d1ceaf14 100644
--- a/arch/sh/kernel/sys_sh.c
+++ b/arch/sh/kernel/sys_sh.c
@@ -25,6 +25,8 @@
 #include <asm/syscalls.h>
 #include <asm/uaccess.h>
 #include <asm/unistd.h>
+#include <asm/cacheflush.h>
+#include <asm/cachectl.h>
 
 static inline long
 do_mmap2(unsigned long addr, unsigned long len, unsigned long prot,
@@ -179,6 +181,47 @@ asmlinkage int sys_ipc(uint call, int first, int second,
         return -EINVAL;
 }
 
+/* sys_cacheflush -- flush (part of) the processor cache.  */
+asmlinkage int sys_cacheflush(unsigned long addr, unsigned long len, int op)
+{
+        struct vm_area_struct *vma;
+
+        if ((op <= 0) || (op > (CACHEFLUSH_D_PURGE|CACHEFLUSH_I)))
+                return -EINVAL;
+
+        /*
+         * Verify that the specified address region actually belongs
+         * to this process.
+         */
+        if (addr + len < addr)
+                return -EFAULT;
+
+        down_read(&current->mm->mmap_sem);
+        vma = find_vma (current->mm, addr);
+        if (vma == NULL || addr < vma->vm_start || addr + len > vma->vm_end) {
+                up_read(&current->mm->mmap_sem);
+                return -EFAULT;
+        }
+
+        switch (op & CACHEFLUSH_D_PURGE) {
+                case CACHEFLUSH_D_INVAL:
+                        __flush_invalidate_region((void *)addr, len);
+                        break;
+                case CACHEFLUSH_D_WB:
+                        __flush_wback_region((void *)addr, len);
+                        break;
+                case CACHEFLUSH_D_PURGE:
+                        __flush_purge_region((void *)addr, len);
+                        break;
+        }
+
+        if (op & CACHEFLUSH_I)
+                flush_cache_all();
+
+        up_read(&current->mm->mmap_sem);
+        return 0;
+}
+
 asmlinkage int sys_uname(struct old_utsname __user *name)
 {
         int err;
diff --git a/arch/sh/kernel/syscalls_32.S b/arch/sh/kernel/syscalls_32.S
index f9e21fa2f592..16ba225ede89 100644
--- a/arch/sh/kernel/syscalls_32.S
+++ b/arch/sh/kernel/syscalls_32.S
@@ -139,7 +139,7 @@ ENTRY(sys_call_table)
         .long sys_clone         /* 120 */
         .long sys_setdomainname
         .long sys_newuname
-        .long sys_ni_syscall    /* sys_modify_ldt */
+        .long sys_cacheflush    /* x86: sys_modify_ldt */
         .long sys_adjtimex
         .long sys_mprotect              /* 125 */
         .long sys_sigprocmask
diff --git a/arch/sh/kernel/syscalls_64.S b/arch/sh/kernel/syscalls_64.S
index bf420b616ae0..af6fb7410c21 100644
--- a/arch/sh/kernel/syscalls_64.S
+++ b/arch/sh/kernel/syscalls_64.S
@@ -143,7 +143,7 @@ sys_call_table:
         .long sys_clone                 /* 120 */
         .long sys_setdomainname
         .long sys_newuname
-        .long sys_ni_syscall    /* sys_modify_ldt */
+        .long sys_cacheflush    /* x86: sys_modify_ldt */
         .long sys_adjtimex
         .long sys_mprotect              /* 125 */
         .long sys_sigprocmask
diff --git a/arch/sh/kernel/traps.c b/arch/sh/kernel/traps.c
index b3e0067db358..f69bd968fcca 100644
--- a/arch/sh/kernel/traps.c
+++ b/arch/sh/kernel/traps.c
@@ -5,18 +5,32 @@
 #include <linux/signal.h>
 #include <linux/sched.h>
 #include <linux/uaccess.h>
+#include <asm/unwinder.h>
 #include <asm/system.h>
 
 #ifdef CONFIG_BUG
-static void handle_BUG(struct pt_regs *regs)
+void handle_BUG(struct pt_regs *regs)
 {
+        const struct bug_entry *bug;
+        unsigned long bugaddr = regs->pc;
         enum bug_trap_type tt;
-        tt = report_bug(regs->pc, regs);
+
+        if (!is_valid_bugaddr(bugaddr))
+                goto invalid;
+
+        bug = find_bug(bugaddr);
+
+        /* Switch unwinders when unwind_stack() is called */
+        if (bug->flags & BUGFLAG_UNWINDER)
+                unwinder_faulted = 1;
+
+        tt = report_bug(bugaddr, regs);
         if (tt == BUG_TRAP_TYPE_WARN) {
-                regs->pc += instruction_size(regs->pc);
+                regs->pc += instruction_size(bugaddr);
                 return;
         }
 
+invalid:
         die("Kernel BUG", regs, TRAPA_BUG_OPCODE & 0xff);
 }
 
@@ -28,8 +42,10 @@ int is_valid_bugaddr(unsigned long addr)
                 return 0;
         if (probe_kernel_address((insn_size_t *)addr, opcode))
                 return 0;
+        if (opcode == TRAPA_BUG_OPCODE)
+                return 1;
 
-        return opcode == TRAPA_BUG_OPCODE;
+        return 0;
 }
 #endif
 
diff --git a/arch/sh/kernel/traps_32.c b/arch/sh/kernel/traps_32.c
index 563426487c6b..583ace55b0dc 100644
--- a/arch/sh/kernel/traps_32.c
+++ b/arch/sh/kernel/traps_32.c
@@ -24,6 +24,7 @@
 #include <linux/kdebug.h>
 #include <linux/kexec.h>
 #include <linux/limits.h>
+#include <linux/proc_fs.h>
 #include <asm/system.h>
 #include <asm/uaccess.h>
 #include <asm/fpu.h>
@@ -44,6 +45,87 @@
 #define TRAP_ILLEGAL_SLOT_INST  13
 #endif
 
+static unsigned long se_user;
+static unsigned long se_sys;
+static unsigned long se_skipped;
+static unsigned long se_half;
+static unsigned long se_word;
+static unsigned long se_dword;
+static unsigned long se_multi;
+/* bitfield: 1: warn 2: fixup 4: signal -> combinations 2|4 && 1|2|4 are not
+   valid! */
+static int se_usermode = 3;
+/* 0: no warning 1: print a warning message */
+static int se_kernmode_warn = 1;
+
+#ifdef CONFIG_PROC_FS
+static const char *se_usermode_action[] = {
+        "ignored",
+        "warn",
+        "fixup",
+        "fixup+warn",
+        "signal",
+        "signal+warn"
+};
+
+static int
+proc_alignment_read(char *page, char **start, off_t off, int count, int *eof,
+                    void *data)
+{
+        char *p = page;
+        int len;
+
+        p += sprintf(p, "User:\t\t%lu\n", se_user);
+        p += sprintf(p, "System:\t\t%lu\n", se_sys);
+        p += sprintf(p, "Skipped:\t%lu\n", se_skipped);
+        p += sprintf(p, "Half:\t\t%lu\n", se_half);
+        p += sprintf(p, "Word:\t\t%lu\n", se_word);
+        p += sprintf(p, "DWord:\t\t%lu\n", se_dword);
+        p += sprintf(p, "Multi:\t\t%lu\n", se_multi);
+        p += sprintf(p, "User faults:\t%i (%s)\n", se_usermode,
+                        se_usermode_action[se_usermode]);
+        p += sprintf(p, "Kernel faults:\t%i (fixup%s)\n", se_kernmode_warn,
+                        se_kernmode_warn ? "+warn" : "");
+
+        len = (p - page) - off;
+        if (len < 0)
+                len = 0;
+
+        *eof = (len <= count) ? 1 : 0;
+        *start = page + off;
+
+        return len;
+}
+
+static int proc_alignment_write(struct file *file, const char __user *buffer,
+                                unsigned long count, void *data)
+{
+        char mode;
+
+        if (count > 0) {
+                if (get_user(mode, buffer))
+                        return -EFAULT;
+                if (mode >= '0' && mode <= '5')
+                        se_usermode = mode - '0';
+        }
+        return count;
+}
+
+static int proc_alignment_kern_write(struct file *file, const char __user *buffer,
+                                     unsigned long count, void *data)
+{
+        char mode;
+
+        if (count > 0) {
+                if (get_user(mode, buffer))
+                        return -EFAULT;
+                if (mode >= '0' && mode <= '1')
+                        se_kernmode_warn = mode - '0';
+        }
+        return count;
+}
+#endif
+
 static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
 {
         unsigned long p;
@@ -136,6 +218,7 @@ static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
                         regs->pc = fixup->fixup;
                         return;
                 }
+
                 die(str, regs, err);
         }
 }
@@ -193,6 +276,13 @@ static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs,
 
         count = 1<<(instruction&3);
 
+        switch (count) {
+        case 1: se_half  += 1; break;
+        case 2: se_word  += 1; break;
+        case 4: se_dword += 1; break;
+        case 8: se_multi += 1; break; /* ??? */
+        }
+
         ret = -EFAULT;
         switch (instruction>>12) {
         case 0: /* mov.[bwl] to/from memory via r0+rn */
@@ -358,15 +448,8 @@ static inline int handle_delayslot(struct pt_regs *regs,
 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
 
-/*
- * XXX: SH-2A needs this too, but it needs an overhaul thanks to mixed 32-bit
- * opcodes..
- */
-
-static int handle_unaligned_notify_count = 10;
-
 int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
-                            struct mem_access *ma)
+                            struct mem_access *ma, int expected)
 {
         u_int rm;
         int ret, index;
@@ -374,15 +457,13 @@ int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
         index = (instruction>>8)&15;    /* 0x0F00 */
         rm = regs->regs[index];
 
-        /* shout about the first ten userspace fixups */
-        if (user_mode(regs) && handle_unaligned_notify_count>0) {
-                handle_unaligned_notify_count--;
-
-                printk(KERN_NOTICE "Fixing up unaligned userspace access "
+        /* shout about fixups */
+        if (!expected && printk_ratelimit())
+                printk(KERN_NOTICE "Fixing up unaligned %s access "
                        "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
+                       user_mode(regs) ? "userspace" : "kernel",
                        current->comm, task_pid_nr(current),
                        (void *)regs->pc, instruction);
-        }
 
         ret = -EFAULT;
         switch (instruction&0xF000) {
@@ -538,6 +619,36 @@ asmlinkage void do_address_error(struct pt_regs *regs,
 
                 local_irq_enable();
 
+                se_user += 1;
+
+#ifndef CONFIG_CPU_SH2A
+                set_fs(USER_DS);
+                if (copy_from_user(&instruction, (u16 *)(regs->pc & ~1), 2)) {
+                        set_fs(oldfs);
+                        goto uspace_segv;
+                }
+                set_fs(oldfs);
+
+                /* shout about userspace fixups */
+                if (se_usermode & 1)
+                        printk(KERN_NOTICE "Unaligned userspace access "
+                               "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
+                               current->comm, current->pid, (void *)regs->pc,
+                               instruction);
+#endif
+
+                if (se_usermode & 2)
+                        goto fixup;
+
+                if (se_usermode & 4)
+                        goto uspace_segv;
+                else {
+                        /* ignore */
+                        regs->pc += instruction_size(instruction);
+                        return;
+                }
+
+fixup:
                 /* bad PC is not something we can fix */
                 if (regs->pc & 1) {
                         si_code = BUS_ADRALN;
@@ -545,17 +656,8 @@ asmlinkage void do_address_error(struct pt_regs *regs,
                 }
 
                 set_fs(USER_DS);
-                if (copy_from_user(&instruction, (void __user *)(regs->pc),
-                                   sizeof(instruction))) {
-                        /* Argh. Fault on the instruction itself.
-                           This should never happen non-SMP
-                        */
-                        set_fs(oldfs);
-                        goto uspace_segv;
-                }
-
                 tmp = handle_unaligned_access(instruction, regs,
-                                              &user_mem_access);
+                                              &user_mem_access, 0);
                 set_fs(oldfs);
 
                 if (tmp==0)
@@ -571,6 +673,14 @@ uspace_segv:
                 info.si_addr = (void __user *)address;
                 force_sig_info(SIGBUS, &info, current);
         } else {
+                se_sys += 1;
+
+                if (se_kernmode_warn)
+                        printk(KERN_NOTICE "Unaligned kernel access "
+                               "on behalf of \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
+                               current->comm, current->pid, (void *)regs->pc,
+                               instruction);
+
                 if (regs->pc & 1)
                         die("unaligned program counter", regs, error_code);
 
@@ -584,7 +694,8 @@ uspace_segv:
                         die("insn faulting in do_address_error", regs, 0);
                 }
 
-                handle_unaligned_access(instruction, regs, &user_mem_access);
+                handle_unaligned_access(instruction, regs,
+                                        &user_mem_access, 0);
                 set_fs(oldfs);
         }
 }
@@ -880,3 +991,38 @@ void dump_stack(void)
         show_stack(NULL, NULL);
 }
 EXPORT_SYMBOL(dump_stack);
+
+#ifdef CONFIG_PROC_FS
+/*
+ * This needs to be done after sysctl_init, otherwise sys/ will be
+ * overwritten.  Actually, this shouldn't be in sys/ at all since
+ * it isn't a sysctl, and it doesn't contain sysctl information.
+ * We now locate it in /proc/cpu/alignment instead.
+ */
+static int __init alignment_init(void)
+{
+        struct proc_dir_entry *dir, *res;
+
+        dir = proc_mkdir("cpu", NULL);
+        if (!dir)
+                return -ENOMEM;
+
+        res = create_proc_entry("alignment", S_IWUSR | S_IRUGO, dir);
+        if (!res)
+                return -ENOMEM;
+
+        res->read_proc = proc_alignment_read;
+        res->write_proc = proc_alignment_write;
+
+        res = create_proc_entry("kernel_alignment", S_IWUSR | S_IRUGO, dir);
+        if (!res)
+                return -ENOMEM;
+
+        res->read_proc = proc_alignment_read;
+        res->write_proc = proc_alignment_kern_write;
+
+        return 0;
+}
+
+fs_initcall(alignment_init);
+#endif
diff --git a/arch/sh/kernel/unwinder.c b/arch/sh/kernel/unwinder.c
index 2b30fa28b440..468889d958f4 100644
--- a/arch/sh/kernel/unwinder.c
+++ b/arch/sh/kernel/unwinder.c
@@ -11,6 +11,7 @@
 #include <linux/errno.h>
 #include <linux/list.h>
 #include <linux/spinlock.h>
+#include <linux/module.h>
 #include <asm/unwinder.h>
 #include <asm/atomic.h>
 
@@ -53,8 +54,6 @@ static struct list_head unwinder_list = {
 
 static DEFINE_SPINLOCK(unwinder_lock);
 
-static atomic_t unwinder_running = ATOMIC_INIT(0);
-
 /**
  * select_unwinder - Select the best registered stack unwinder.
  *
@@ -122,6 +121,8 @@ int unwinder_register(struct unwinder *u)
         return ret;
 }
 
+int unwinder_faulted = 0;
+
 /*
  * Unwind the call stack and pass information to the stacktrace_ops
  * functions. Also handle the case where we need to switch to a new
@@ -144,19 +145,20 @@ void unwind_stack(struct task_struct *task, struct pt_regs *regs,
          * Hopefully this will give us a semi-reliable stacktrace so we
          * can diagnose why curr_unwinder->dump() faulted.
          */
-        if (atomic_inc_return(&unwinder_running) != 1) {
+        if (unwinder_faulted) {
                 spin_lock_irqsave(&unwinder_lock, flags);
 
-                if (!list_is_singular(&unwinder_list)) {
+                /* Make sure no one beat us to changing the unwinder */
+                if (unwinder_faulted && !list_is_singular(&unwinder_list)) {
                         list_del(&curr_unwinder->list);
                         curr_unwinder = select_unwinder();
+
+                        unwinder_faulted = 0;
                 }
 
                 spin_unlock_irqrestore(&unwinder_lock, flags);
-                atomic_dec(&unwinder_running);
         }
 
         curr_unwinder->dump(task, regs, sp, ops, data);
-
-        atomic_dec(&unwinder_running);
 }
+EXPORT_SYMBOL_GPL(unwind_stack);
diff --git a/arch/sh/lib/__clear_user.S b/arch/sh/lib/__clear_user.S
index bee9817e055d..db1dca7aad14 100644
--- a/arch/sh/lib/__clear_user.S
+++ b/arch/sh/lib/__clear_user.S
@@ -11,7 +11,7 @@
 ENTRY(__clear_user)
         !
         mov     #0, r0
-        mov     #0xe0, r1       ! 0xffffffe0
+        mov     #0xffffffe0, r1
         !
         ! r4..(r4+31)&~32          -------- not aligned [ Area 0 ]
         ! (r4+31)&~32..(r4+r5)&~32 -------- aligned     [ Area 1 ]
diff --git a/arch/sh/lib/delay.c b/arch/sh/lib/delay.c
index f3ddd2133e6f..faa8f86c0db4 100644
--- a/arch/sh/lib/delay.c
+++ b/arch/sh/lib/delay.c
@@ -21,13 +21,14 @@ void __delay(unsigned long loops)
 
 inline void __const_udelay(unsigned long xloops)
 {
+        xloops *= 4;
         __asm__("dmulu.l        %0, %2\n\t"
                 "sts    mach, %0"
                 : "=r" (xloops)
                 : "0" (xloops),
-                  "r" (HZ * cpu_data[raw_smp_processor_id()].loops_per_jiffy)
+                  "r" (cpu_data[raw_smp_processor_id()].loops_per_jiffy * (HZ/4))
                 : "macl", "mach");
-        __delay(xloops);
+        __delay(++xloops);
 }
 
 void __udelay(unsigned long usecs)
diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig
index 2795618e4f07..64dc1ad59801 100644
--- a/arch/sh/mm/Kconfig
+++ b/arch/sh/mm/Kconfig
@@ -82,7 +82,7 @@ config 32BIT
 
 config PMB_ENABLE
         bool "Support 32-bit physical addressing through PMB"
-        depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785)
+        depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7757 || CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785)
         select 32BIT
         default y
         help
@@ -97,7 +97,7 @@ choice
 
 config PMB
         bool "PMB"
-        depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785)
+        depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7757 || CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785)
         select 32BIT
         help
           If you say Y here, physical addressing will be extended to
@@ -106,7 +106,8 @@ config PMB
 
 config PMB_FIXED
         bool "fixed PMB"
-        depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7780 || \
+        depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7757 || \
+                                           CPU_SUBTYPE_SH7780 || \
                                            CPU_SUBTYPE_SH7785)
         select 32BIT
         help
diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c
index 2775f84d9aa3..70fb906419dd 100644
--- a/arch/sh/mm/cache-sh4.c
+++ b/arch/sh/mm/cache-sh4.c
@@ -455,7 +455,49 @@ static void __flush_cache_4096(unsigned long addr, unsigned long phys,
  * Break the 1, 2 and 4 way variants of this out into separate functions to
  * avoid nearly all the overhead of having the conditional stuff in the function
  * bodies (+ the 1 and 2 way cases avoid saving any registers too).
+ *
+ * We want to eliminate unnecessary bus transactions, so this code uses
+ * a non-obvious technique.
+ *
+ * Loop over a cache way sized block of, one cache line at a time. For each
+ * line, use movca.a to cause the current cache line contents to be written
+ * back, but without reading anything from main memory. However this has the
+ * side effect that the cache is now caching that memory location. So follow
+ * this with a cache invalidate to mark the cache line invalid. And do all
+ * this with interrupts disabled, to avoid the cache line being accidently
+ * evicted while it is holding garbage.
+ *
+ * This also breaks in a number of circumstances:
+ * - if there are modifications to the region of memory just above
+ *   empty_zero_page (for example because a breakpoint has been placed
+ *   there), then these can be lost.
+ *
+ *   This is because the the memory address which the cache temporarily
+ *   caches in the above description is empty_zero_page. So the
+ *   movca.l hits the cache (it is assumed that it misses, or at least
+ *   isn't dirty), modifies the line and then invalidates it, losing the
+ *   required change.
+ *
+ * - If caches are disabled or configured in write-through mode, then
+ *   the movca.l writes garbage directly into memory.
  */
+static void __flush_dcache_segment_writethrough(unsigned long start,
+                                                unsigned long extent_per_way)
+{
+        unsigned long addr;
+        int i;
+
+        addr = CACHE_OC_ADDRESS_ARRAY | (start & cpu_data->dcache.entry_mask);
+
+        while (extent_per_way) {
+                for (i = 0; i < cpu_data->dcache.ways; i++)
+                        __raw_writel(0, addr + cpu_data->dcache.way_incr * i);
+
+                addr += cpu_data->dcache.linesz;
+                extent_per_way -= cpu_data->dcache.linesz;
+        }
+}
+
 static void __flush_dcache_segment_1way(unsigned long start,
                                         unsigned long extent_per_way)
 {
@@ -655,24 +697,30 @@ extern void __weak sh4__flush_region_init(void);
  */
 void __init sh4_cache_init(void)
 {
+        unsigned int wt_enabled = !!(__raw_readl(CCR) & CCR_CACHE_WT);
+
         printk("PVR=%08x CVR=%08x PRR=%08x\n",
                 ctrl_inl(CCN_PVR),
                 ctrl_inl(CCN_CVR),
                 ctrl_inl(CCN_PRR));
 
-        switch (boot_cpu_data.dcache.ways) {
-        case 1:
-                __flush_dcache_segment_fn = __flush_dcache_segment_1way;
-                break;
-        case 2:
-                __flush_dcache_segment_fn = __flush_dcache_segment_2way;
-                break;
-        case 4:
-                __flush_dcache_segment_fn = __flush_dcache_segment_4way;
-                break;
-        default:
-                panic("unknown number of cache ways\n");
-                break;
+        if (wt_enabled)
+                __flush_dcache_segment_fn = __flush_dcache_segment_writethrough;
+        else {
+                switch (boot_cpu_data.dcache.ways) {
+                case 1:
+                        __flush_dcache_segment_fn = __flush_dcache_segment_1way;
+                        break;
+                case 2:
+                        __flush_dcache_segment_fn = __flush_dcache_segment_2way;
+                        break;
+                case 4:
+                        __flush_dcache_segment_fn = __flush_dcache_segment_4way;
+                        break;
+                default:
+                        panic("unknown number of cache ways\n");
+                        break;
+                }
         }
 
         local_flush_icache_range        = sh4_flush_icache_range;
diff --git a/arch/sh/mm/ioremap_32.c b/arch/sh/mm/ioremap_32.c
index da2f4186f2cd..c3250614e3ae 100644
--- a/arch/sh/mm/ioremap_32.c
+++ b/arch/sh/mm/ioremap_32.c
@@ -57,14 +57,6 @@ void __iomem *__ioremap(unsigned long phys_addr, unsigned long size,
         if (is_pci_memory_fixed_range(phys_addr, size))
                 return (void __iomem *)phys_addr;
 
-#if !defined(CONFIG_PMB_FIXED)
-        /*
-         * Don't allow anybody to remap normal RAM that we're using..
-         */
-        if (phys_addr < virt_to_phys(high_memory))
-                return NULL;
-#endif
-
         /*
          * Mappings have to be page-aligned
          */
diff --git a/arch/sh/mm/tlb-sh4.c b/arch/sh/mm/tlb-sh4.c
index 7d3c63e707a5..8cf550e2570f 100644
--- a/arch/sh/mm/tlb-sh4.c
+++ b/arch/sh/mm/tlb-sh4.c
@@ -43,9 +43,12 @@ void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
          */
         ctrl_outl(pte.pte_high, MMU_PTEA);
 #else
-        if (cpu_data->flags & CPU_HAS_PTEA)
-                /* TODO: make this look less hacky */
-                ctrl_outl(((pteval >> 28) & 0xe) | (pteval & 0x1), MMU_PTEA);
+        if (cpu_data->flags & CPU_HAS_PTEA) {
+                /* The last 3 bits and the first one of pteval contains
+                 * the PTEA timing control and space attribute bits
+                 */
+                ctrl_outl(copy_ptea_attributes(pteval), MMU_PTEA);
+        }
 #endif
 
         /* Set PTEL register */
diff --git a/arch/sh/tools/mach-types b/arch/sh/tools/mach-types
index 09eef360dde1..6639b25d8d57 100644
--- a/arch/sh/tools/mach-types
+++ b/arch/sh/tools/mach-types
@@ -53,7 +53,9 @@ RSK7203			SH_RSK7203
 AP325RXA                SH_AP325RXA
 SH7763RDP               SH_SH7763RDP
 SH7785LCR               SH_SH7785LCR
+SH7785LCR_PT            SH_SH7785LCR_PT
 URQUELL                 SH_URQUELL
 ESPT                    SH_ESPT
 POLARIS                 SH_POLARIS
 KFR2R09                 SH_KFR2R09
+ECOVEC                  SH_ECOVEC
diff --git a/arch/sparc/include/asm/device.h b/arch/sparc/include/asm/device.h
index 3702e087df2c..f3b85b6b0b76 100644
--- a/arch/sparc/include/asm/device.h
+++ b/arch/sparc/include/asm/device.h
@@ -32,4 +32,7 @@ dev_archdata_get_node(const struct dev_archdata *ad)
         return ad->prom_node;
 }
 
+struct pdev_archdata {
+};
+
 #endif /* _ASM_SPARC_DEVICE_H */
diff --git a/arch/sparc/kernel/smp_64.c b/arch/sparc/kernel/smp_64.c
index fa44eaf8d897..3691907a43b4 100644
--- a/arch/sparc/kernel/smp_64.c
+++ b/arch/sparc/kernel/smp_64.c
@@ -1499,7 +1499,7 @@ void __init setup_per_cpu_areas(void)
         dyn_size = pcpur_size - static_size - PERCPU_MODULE_RESERVE;
 
 
-        ptrs_size = PFN_ALIGN(num_possible_cpus() * sizeof(pcpur_ptrs[0]));
+        ptrs_size = PFN_ALIGN(nr_cpu_ids * sizeof(pcpur_ptrs[0]));
         pcpur_ptrs = alloc_bootmem(ptrs_size);
 
         for_each_possible_cpu(cpu) {
@@ -1514,7 +1514,7 @@ void __init setup_per_cpu_areas(void)
 
         /* allocate address and map */
         vm.flags = VM_ALLOC;
-        vm.size = num_possible_cpus() * PCPU_CHUNK_SIZE;
+        vm.size = nr_cpu_ids * PCPU_CHUNK_SIZE;
         vm_area_register_early(&vm, PCPU_CHUNK_SIZE);
 
         for_each_possible_cpu(cpu) {
diff --git a/arch/x86/include/asm/device.h b/arch/x86/include/asm/device.h
index 4994a20acbcb..cee34e9ca45b 100644
--- a/arch/x86/include/asm/device.h
+++ b/arch/x86/include/asm/device.h
@@ -13,4 +13,7 @@ struct dma_map_ops *dma_ops;
 #endif
 };
 
+struct pdev_archdata {
+};
+
 #endif /* _ASM_X86_DEVICE_H */
diff --git a/arch/x86/include/asm/uv/uv_bau.h b/arch/x86/include/asm/uv/uv_bau.h
index bddd44f2f0ab..80e2984f521c 100644
--- a/arch/x86/include/asm/uv/uv_bau.h
+++ b/arch/x86/include/asm/uv/uv_bau.h
@@ -133,7 +133,7 @@ struct bau_msg_payload {
  * see table 4.2.3.0.1 in broacast_assist spec.
  */
 struct bau_msg_header {
-        unsigned int dest_subnodeid:6;  /* must be zero */
+        unsigned int dest_subnodeid:6;  /* must be 0x10, for the LB */
         /* bits 5:0 */
         unsigned int base_dest_nodeid:15; /* nasid>>1 (pnode) of */
         /* bits 20:6 */                   /* first bit in node_map */
diff --git a/arch/x86/kernel/apic/ipi.c b/arch/x86/kernel/apic/ipi.c
index dbf5445727a9..6ef00ba4c886 100644
--- a/arch/x86/kernel/apic/ipi.c
+++ b/arch/x86/kernel/apic/ipi.c
@@ -106,6 +106,9 @@ void default_send_IPI_mask_logical(const struct cpumask *cpumask, int vector)
         unsigned long mask = cpumask_bits(cpumask)[0];
         unsigned long flags;
 
+        if (WARN_ONCE(!mask, "empty IPI mask"))
+                return;
+
         local_irq_save(flags);
         WARN_ON(mask & ~cpumask_bits(cpu_online_mask)[0]);
         __default_send_IPI_dest_field(mask, vector, apic->dest_logical);
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index 832e908adcb5..601159374e87 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -46,7 +46,7 @@ static int early_get_nodeid(void)
         return node_id.s.node_id;
 }
 
-static int uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
+static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 {
         if (!strcmp(oem_id, "SGI")) {
                 if (!strcmp(oem_table_id, "UVL"))
@@ -253,7 +253,7 @@ static void uv_send_IPI_self(int vector)
         apic_write(APIC_SELF_IPI, vector);
 }
 
-struct apic apic_x2apic_uv_x = {
+struct apic __refdata apic_x2apic_uv_x = {
 
         .name                           = "UV large system",
         .probe                          = NULL,
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 1cfb623ce11c..01213048f62f 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -1226,8 +1226,13 @@ static void mce_init(void)
 }
 
 /* Add per CPU specific workarounds here */
-static void mce_cpu_quirks(struct cpuinfo_x86 *c)
+static int mce_cpu_quirks(struct cpuinfo_x86 *c)
 {
+        if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
+                pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
+                return -EOPNOTSUPP;
+        }
+
         /* This should be disabled by the BIOS, but isn't always */
         if (c->x86_vendor == X86_VENDOR_AMD) {
                 if (c->x86 == 15 && banks > 4) {
@@ -1273,11 +1278,20 @@ static void mce_cpu_quirks(struct cpuinfo_x86 *c)
                 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
                         monarch_timeout < 0)
                         monarch_timeout = USEC_PER_SEC;
+
+                /*
+                 * There are also broken BIOSes on some Pentium M and
+                 * earlier systems:
+                 */
+                if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
+                        mce_bootlog = 0;
         }
         if (monarch_timeout < 0)
                 monarch_timeout = 0;
         if (mce_bootlog != 0)
                 mce_panic_timeout = 30;
+
+        return 0;
 }
 
 static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c)
@@ -1338,11 +1352,10 @@ void __cpuinit mcheck_init(struct cpuinfo_x86 *c)
         if (!mce_available(c))
                 return;
 
-        if (mce_cap_init() < 0) {
+        if (mce_cap_init() < 0 || mce_cpu_quirks(c) < 0) {
                 mce_disabled = 1;
                 return;
         }
-        mce_cpu_quirks(c);
 
         machine_check_vector = do_machine_check;
 
diff --git a/arch/x86/kernel/cpu/mcheck/therm_throt.c b/arch/x86/kernel/cpu/mcheck/therm_throt.c
index 8bc64cfbe936..5957a93e5173 100644
--- a/arch/x86/kernel/cpu/mcheck/therm_throt.c
+++ b/arch/x86/kernel/cpu/mcheck/therm_throt.c
@@ -116,11 +116,14 @@ static int therm_throt_process(int curr)
                        cpu, __get_cpu_var(thermal_throttle_count));
 
                 add_taint(TAINT_MACHINE_CHECK);
-        } else if (was_throttled) {
+                return 1;
+        }
+        if (was_throttled) {
                 printk(KERN_INFO "CPU%d: Temperature/speed normal\n", cpu);
+                return 1;
         }
 
-        return 1;
+        return 0;
 }
 
 #ifdef CONFIG_SYSFS
diff --git a/arch/x86/kernel/setup_percpu.c b/arch/x86/kernel/setup_percpu.c
index 29a3eef7cf4a..07d81916f212 100644
--- a/arch/x86/kernel/setup_percpu.c
+++ b/arch/x86/kernel/setup_percpu.c
@@ -165,7 +165,7 @@ static ssize_t __init setup_pcpu_lpage(size_t static_size, bool chosen)
 
         if (!chosen) {
                 size_t vm_size = VMALLOC_END - VMALLOC_START;
-                size_t tot_size = num_possible_cpus() * PMD_SIZE;
+                size_t tot_size = nr_cpu_ids * PMD_SIZE;
 
                 /* on non-NUMA, embedding is better */
                 if (!pcpu_need_numa())
@@ -199,7 +199,7 @@ static ssize_t __init setup_pcpu_lpage(size_t static_size, bool chosen)
         dyn_size = pcpul_size - static_size - PERCPU_FIRST_CHUNK_RESERVE;
 
         /* allocate pointer array and alloc large pages */
-        map_size = PFN_ALIGN(num_possible_cpus() * sizeof(pcpul_map[0]));
+        map_size = PFN_ALIGN(nr_cpu_ids * sizeof(pcpul_map[0]));
         pcpul_map = alloc_bootmem(map_size);
 
         for_each_possible_cpu(cpu) {
@@ -228,7 +228,7 @@ static ssize_t __init setup_pcpu_lpage(size_t static_size, bool chosen)
 
         /* allocate address and map */
         pcpul_vm.flags = VM_ALLOC;
-        pcpul_vm.size = num_possible_cpus() * PMD_SIZE;
+        pcpul_vm.size = nr_cpu_ids * PMD_SIZE;
         vm_area_register_early(&pcpul_vm, PMD_SIZE);
 
         for_each_possible_cpu(cpu) {
@@ -250,8 +250,8 @@ static ssize_t __init setup_pcpu_lpage(size_t static_size, bool chosen)
                                      PMD_SIZE, pcpul_vm.addr, NULL);
 
         /* sort pcpul_map array for pcpu_lpage_remapped() */
-        for (i = 0; i < num_possible_cpus() - 1; i++)
-                for (j = i + 1; j < num_possible_cpus(); j++)
+        for (i = 0; i < nr_cpu_ids - 1; i++)
+                for (j = i + 1; j < nr_cpu_ids; j++)
                         if (pcpul_map[i].ptr > pcpul_map[j].ptr) {
                                 struct pcpul_ent tmp = pcpul_map[i];
                                 pcpul_map[i] = pcpul_map[j];
@@ -288,7 +288,7 @@ void *pcpu_lpage_remapped(void *kaddr)
 {
         void *pmd_addr = (void *)((unsigned long)kaddr & PMD_MASK);
         unsigned long offset = (unsigned long)kaddr & ~PMD_MASK;
-        int left = 0, right = num_possible_cpus() - 1;
+        int left = 0, right = nr_cpu_ids - 1;
         int pos;
 
         /* pcpul in use at all? */
@@ -377,7 +377,7 @@ static ssize_t __init setup_pcpu_4k(size_t static_size)
         pcpu4k_nr_static_pages = PFN_UP(static_size);
 
         /* unaligned allocations can't be freed, round up to page size */
-        pages_size = PFN_ALIGN(pcpu4k_nr_static_pages * num_possible_cpus()
+        pages_size = PFN_ALIGN(pcpu4k_nr_static_pages * nr_cpu_ids
                                * sizeof(pcpu4k_pages[0]));
         pcpu4k_pages = alloc_bootmem(pages_size);
 
diff --git a/arch/x86/kernel/tlb_uv.c b/arch/x86/kernel/tlb_uv.c
index 8ccabb8a2f6a..77b9689f8edb 100644
--- a/arch/x86/kernel/tlb_uv.c
+++ b/arch/x86/kernel/tlb_uv.c
@@ -744,6 +744,7 @@ uv_activation_descriptor_init(int node, int pnode)
                  * note that base_dest_nodeid is actually a nasid.
                  */
                 ad2->header.base_dest_nodeid = uv_partition_base_pnode << 1;
+                ad2->header.dest_subnodeid = 0x10; /* the LB */
                 ad2->header.command = UV_NET_ENDPOINT_INTD;
                 ad2->header.int_both = 1;
                 /*
diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c
index 821e97017e95..c814e144a3f0 100644
--- a/arch/x86/mm/tlb.c
+++ b/arch/x86/mm/tlb.c
@@ -183,18 +183,17 @@ static void flush_tlb_others_ipi(const struct cpumask *cpumask,
 
         f->flush_mm = mm;
         f->flush_va = va;
-        cpumask_andnot(to_cpumask(f->flush_cpumask),
-                       cpumask, cpumask_of(smp_processor_id()));
-
-        /*
-         * We have to send the IPI only to
-         * CPUs affected.
-         */
-        apic->send_IPI_mask(to_cpumask(f->flush_cpumask),
-                      INVALIDATE_TLB_VECTOR_START + sender);
+        if (cpumask_andnot(to_cpumask(f->flush_cpumask), cpumask, cpumask_of(smp_processor_id()))) {
+                /*
+                 * We have to send the IPI only to
+                 * CPUs affected.
+                 */
+                apic->send_IPI_mask(to_cpumask(f->flush_cpumask),
+                              INVALIDATE_TLB_VECTOR_START + sender);
 
-        while (!cpumask_empty(to_cpumask(f->flush_cpumask)))
-                cpu_relax();
+                while (!cpumask_empty(to_cpumask(f->flush_cpumask)))
+                        cpu_relax();
+        }
 
         f->flush_mm = NULL;
         f->flush_va = 0;