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authorLinus Torvalds <torvalds@linux-foundation.org>2008-05-11 00:14:05 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2008-05-11 00:14:05 -0400
commit5bb7ff795fffc9418e3039cac77b42adcaae1a57 (patch)
treec6dca94cc723a0079d04d254e0407e85c1980c66 /arch
parent3e1b83ab3912a6f583897635bee0a2e0cd1545f7 (diff)
parent1f2ee6496b1f71e9d5aa2448745e65fbafdc3bd5 (diff)
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: [ARM] 5033/1: Unbreak corgi_ssp by registering ssp drivers earlier. [ARM] Orion: clean up addr-map.c after window setting code purge [ARM] Orion: pass proper t_clk into mv643xx_eth [ARM] Orion: use mv643xx_eth driver mbus window handling [ARM] pxa: Fix RCSR handling [ARM] lubbock: fix compilation [ARM] 5032/1: Added cpufreq support for pxa27x CPU [ARM] 5031/1: Indentation correction in cpu-pxa.c. [ARM] 5028/1: pxafb: fix broken "backward compatibility way" in framebuffer [ARM] 4882/2: Correction for S3C2410 clkout generation [ARM] 5027/1: Fixed random memory corruption on pxa suspend cycle. [ARM] 5024/1: Fix some minor clk issues in the MMCI PL18x driver [ARM] 5023/1: Fix broken gpio interrupts on ep93xx ns9xxx: fix sparse warning ns9xxx: check for irq lockups ns9xxx: fix handle_prio_irq to unmask irqs with lower priority
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-ep93xx/core.c2
-rw-r--r--arch/arm/mach-ns9xxx/irq.c22
-rw-r--r--arch/arm/mach-orion5x/addr-map.c66
-rw-r--r--arch/arm/mach-orion5x/common.c9
-rw-r--r--arch/arm/mach-orion5x/common.h1
-rw-r--r--arch/arm/mach-pxa/Makefile12
-rw-r--r--arch/arm/mach-pxa/corgi.c4
-rw-r--r--arch/arm/mach-pxa/cpu-pxa.c310
-rw-r--r--arch/arm/mach-pxa/lubbock.c2
-rw-r--r--arch/arm/mach-pxa/pm.c10
-rw-r--r--arch/arm/mach-pxa/poodle.c2
-rw-r--r--arch/arm/mach-pxa/pxa25x.c11
-rw-r--r--arch/arm/mach-pxa/pxa27x.c11
-rw-r--r--arch/arm/mach-pxa/pxa3xx.c7
-rw-r--r--arch/arm/mach-pxa/spitz.c2
-rw-r--r--arch/arm/mach-pxa/spitz_pm.c3
-rw-r--r--arch/arm/mach-pxa/tosa.c2
-rw-r--r--arch/arm/mach-sa1100/pm.c8
-rw-r--r--arch/arm/plat-s3c24xx/clock.c4
19 files changed, 269 insertions, 219 deletions
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 8bc187240542..1d7bca6aa441 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -280,7 +280,7 @@ static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
280 const int port = gpio >> 3; 280 const int port = gpio >> 3;
281 const int port_mask = 1 << (gpio & 7); 281 const int port_mask = 1 << (gpio & 7);
282 282
283 gpio_direction_output(gpio, gpio_get_value(gpio)); 283 gpio_direction_input(gpio);
284 284
285 switch (type) { 285 switch (type) {
286 case IRQT_RISING: 286 case IRQT_RISING:
diff --git a/arch/arm/mach-ns9xxx/irq.c b/arch/arm/mach-ns9xxx/irq.c
index 36e5835e6097..ca85d24cf39f 100644
--- a/arch/arm/mach-ns9xxx/irq.c
+++ b/arch/arm/mach-ns9xxx/irq.c
@@ -62,7 +62,7 @@ static struct irq_chip ns9xxx_chip = {
62#if 0 62#if 0
63#define handle_irq handle_level_irq 63#define handle_irq handle_level_irq
64#else 64#else
65void handle_prio_irq(unsigned int irq, struct irq_desc *desc) 65static void handle_prio_irq(unsigned int irq, struct irq_desc *desc)
66{ 66{
67 unsigned int cpu = smp_processor_id(); 67 unsigned int cpu = smp_processor_id();
68 struct irqaction *action; 68 struct irqaction *action;
@@ -70,27 +70,35 @@ void handle_prio_irq(unsigned int irq, struct irq_desc *desc)
70 70
71 spin_lock(&desc->lock); 71 spin_lock(&desc->lock);
72 72
73 if (unlikely(desc->status & IRQ_INPROGRESS)) 73 BUG_ON(desc->status & IRQ_INPROGRESS);
74 goto out_unlock;
75 74
76 desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); 75 desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
77 kstat_cpu(cpu).irqs[irq]++; 76 kstat_cpu(cpu).irqs[irq]++;
78 77
79 action = desc->action; 78 action = desc->action;
80 if (unlikely(!action || (desc->status & IRQ_DISABLED))) 79 if (unlikely(!action || (desc->status & IRQ_DISABLED)))
81 goto out_unlock; 80 goto out_mask;
82 81
83 desc->status |= IRQ_INPROGRESS; 82 desc->status |= IRQ_INPROGRESS;
84 spin_unlock(&desc->lock); 83 spin_unlock(&desc->lock);
85 84
86 action_ret = handle_IRQ_event(irq, action); 85 action_ret = handle_IRQ_event(irq, action);
87 86
87 /* XXX: There is no direct way to access noirqdebug, so check
88 * unconditionally for spurious irqs...
89 * Maybe this function should go to kernel/irq/chip.c? */
90 note_interrupt(irq, desc, action_ret);
91
88 spin_lock(&desc->lock); 92 spin_lock(&desc->lock);
89 desc->status &= ~IRQ_INPROGRESS; 93 desc->status &= ~IRQ_INPROGRESS;
90 if (!(desc->status & IRQ_DISABLED) && desc->chip->ack)
91 desc->chip->ack(irq);
92 94
93out_unlock: 95 if (desc->status & IRQ_DISABLED)
96out_mask:
97 desc->chip->mask(irq);
98
99 /* ack unconditionally to unmask lower prio irqs */
100 desc->chip->ack(irq);
101
94 spin_unlock(&desc->lock); 102 spin_unlock(&desc->lock);
95} 103}
96#define handle_irq handle_prio_irq 104#define handle_irq handle_prio_irq
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index 9608503d67f5..e63fb05dc893 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -34,11 +34,7 @@
34 * Non-CPU Masters address decoding -- 34 * Non-CPU Masters address decoding --
35 * Unlike the CPU, we setup the access from Orion's master interfaces to DDR 35 * Unlike the CPU, we setup the access from Orion's master interfaces to DDR
36 * banks only (the typical use case). 36 * banks only (the typical use case).
37 * Setup access for each master to DDR is issued by common.c. 37 * Setup access for each master to DDR is issued by platform device setup.
38 *
39 * Note: although orion_setbits() and orion_clrbits() are not atomic
40 * no locking is necessary here since code in this file is only called
41 * at boot time when there is no concurrency issues.
42 */ 38 */
43 39
44/* 40/*
@@ -48,10 +44,6 @@
48#define TARGET_DEV_BUS 1 44#define TARGET_DEV_BUS 1
49#define TARGET_PCI 3 45#define TARGET_PCI 3
50#define TARGET_PCIE 4 46#define TARGET_PCIE 4
51#define ATTR_DDR_CS(n) (((n) ==0) ? 0xe : \
52 ((n) == 1) ? 0xd : \
53 ((n) == 2) ? 0xb : \
54 ((n) == 3) ? 0x7 : 0xf)
55#define ATTR_PCIE_MEM 0x59 47#define ATTR_PCIE_MEM 0x59
56#define ATTR_PCIE_IO 0x51 48#define ATTR_PCIE_IO 0x51
57#define ATTR_PCIE_WA 0x79 49#define ATTR_PCIE_WA 0x79
@@ -61,17 +53,12 @@
61#define ATTR_DEV_CS1 0x1d 53#define ATTR_DEV_CS1 0x1d
62#define ATTR_DEV_CS2 0x1b 54#define ATTR_DEV_CS2 0x1b
63#define ATTR_DEV_BOOT 0xf 55#define ATTR_DEV_BOOT 0xf
64#define WIN_EN 1
65 56
66/* 57/*
67 * Helpers to get DDR bank info 58 * Helpers to get DDR bank info
68 */ 59 */
69#define DDR_BASE_CS(n) ORION5X_DDR_REG(0x1500 + ((n) * 8)) 60#define DDR_BASE_CS(n) ORION5X_DDR_REG(0x1500 + ((n) << 3))
70#define DDR_SIZE_CS(n) ORION5X_DDR_REG(0x1504 + ((n) * 8)) 61#define DDR_SIZE_CS(n) ORION5X_DDR_REG(0x1504 + ((n) << 3))
71#define DDR_MAX_CS 4
72#define DDR_REG_TO_SIZE(reg) (((reg) | 0xffffff) + 1)
73#define DDR_REG_TO_BASE(reg) ((reg) & 0xff000000)
74#define DDR_BANK_EN 1
75 62
76/* 63/*
77 * CPU Address Decode Windows registers 64 * CPU Address Decode Windows registers
@@ -81,17 +68,6 @@
81#define CPU_WIN_REMAP_LO(n) ORION5X_BRIDGE_REG(0x008 | ((n) << 4)) 68#define CPU_WIN_REMAP_LO(n) ORION5X_BRIDGE_REG(0x008 | ((n) << 4))
82#define CPU_WIN_REMAP_HI(n) ORION5X_BRIDGE_REG(0x00c | ((n) << 4)) 69#define CPU_WIN_REMAP_HI(n) ORION5X_BRIDGE_REG(0x00c | ((n) << 4))
83 70
84/*
85 * Gigabit Ethernet Address Decode Windows registers
86 */
87#define ETH_WIN_BASE(win) ORION5X_ETH_REG(0x200 + ((win) * 8))
88#define ETH_WIN_SIZE(win) ORION5X_ETH_REG(0x204 + ((win) * 8))
89#define ETH_WIN_REMAP(win) ORION5X_ETH_REG(0x280 + ((win) * 4))
90#define ETH_WIN_EN ORION5X_ETH_REG(0x290)
91#define ETH_WIN_PROT ORION5X_ETH_REG(0x294)
92#define ETH_MAX_WIN 6
93#define ETH_MAX_REMAP_WIN 4
94
95 71
96struct mbus_dram_target_info orion5x_mbus_dram_info; 72struct mbus_dram_target_info orion5x_mbus_dram_info;
97 73
@@ -202,39 +178,3 @@ void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
202{ 178{
203 setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1); 179 setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1);
204} 180}
205
206void __init orion5x_setup_eth_wins(void)
207{
208 int i;
209
210 /*
211 * First, disable and clear windows
212 */
213 for (i = 0; i < ETH_MAX_WIN; i++) {
214 orion5x_write(ETH_WIN_BASE(i), 0);
215 orion5x_write(ETH_WIN_SIZE(i), 0);
216 orion5x_setbits(ETH_WIN_EN, 1 << i);
217 orion5x_clrbits(ETH_WIN_PROT, 0x3 << (i * 2));
218 if (i < ETH_MAX_REMAP_WIN)
219 orion5x_write(ETH_WIN_REMAP(i), 0);
220 }
221
222 /*
223 * Setup windows for DDR banks.
224 */
225 for (i = 0; i < DDR_MAX_CS; i++) {
226 u32 base, size;
227 size = orion5x_read(DDR_SIZE_CS(i));
228 base = orion5x_read(DDR_BASE_CS(i));
229 if (size & DDR_BANK_EN) {
230 base = DDR_REG_TO_BASE(base);
231 size = DDR_REG_TO_SIZE(size);
232 orion5x_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000);
233 orion5x_write(ETH_WIN_BASE(i), (base & 0xffff0000) |
234 (ATTR_DDR_CS(i) << 8) |
235 TARGET_DDR);
236 orion5x_clrbits(ETH_WIN_EN, 1 << i);
237 orion5x_setbits(ETH_WIN_PROT, 0x3 << (i * 2));
238 }
239 }
240}
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 0ecff5a61972..4f13fd037f04 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -190,6 +190,11 @@ static struct platform_device orion5x_ehci1 = {
190 * (The Orion and Discovery (MV643xx) families use the same Ethernet driver) 190 * (The Orion and Discovery (MV643xx) families use the same Ethernet driver)
191 ****************************************************************************/ 191 ****************************************************************************/
192 192
193struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = {
194 .dram = &orion5x_mbus_dram_info,
195 .t_clk = ORION5X_TCLK,
196};
197
193static struct resource orion5x_eth_shared_resources[] = { 198static struct resource orion5x_eth_shared_resources[] = {
194 { 199 {
195 .start = ORION5X_ETH_PHYS_BASE + 0x2000, 200 .start = ORION5X_ETH_PHYS_BASE + 0x2000,
@@ -201,6 +206,9 @@ static struct resource orion5x_eth_shared_resources[] = {
201static struct platform_device orion5x_eth_shared = { 206static struct platform_device orion5x_eth_shared = {
202 .name = MV643XX_ETH_SHARED_NAME, 207 .name = MV643XX_ETH_SHARED_NAME,
203 .id = 0, 208 .id = 0,
209 .dev = {
210 .platform_data = &orion5x_eth_shared_data,
211 },
204 .num_resources = 1, 212 .num_resources = 1,
205 .resource = orion5x_eth_shared_resources, 213 .resource = orion5x_eth_shared_resources,
206}; 214};
@@ -362,7 +370,6 @@ void __init orion5x_init(void)
362 * Setup Orion address map 370 * Setup Orion address map
363 */ 371 */
364 orion5x_setup_cpu_mbus_bridge(); 372 orion5x_setup_cpu_mbus_bridge();
365 orion5x_setup_eth_wins();
366 373
367 /* 374 /*
368 * Register devices. 375 * Register devices.
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index 14adf8d1a54a..bd0f05de6e18 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -22,7 +22,6 @@ void orion5x_setup_dev0_win(u32 base, u32 size);
22void orion5x_setup_dev1_win(u32 base, u32 size); 22void orion5x_setup_dev1_win(u32 base, u32 size);
23void orion5x_setup_dev2_win(u32 base, u32 size); 23void orion5x_setup_dev2_win(u32 base, u32 size);
24void orion5x_setup_pcie_wa_win(u32 base, u32 size); 24void orion5x_setup_pcie_wa_win(u32 base, u32 size);
25void orion5x_setup_eth_wins(void);
26 25
27/* 26/*
28 * Shared code used internally by other Orion core functions. 27 * Shared code used internally by other Orion core functions.
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 6a830853aa6a..0e6d05bb81aa 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -5,6 +5,13 @@
5# Common support (must be linked before board specific support) 5# Common support (must be linked before board specific support)
6obj-y += clock.o devices.o generic.o irq.o dma.o \ 6obj-y += clock.o devices.o generic.o irq.o dma.o \
7 time.o gpio.o 7 time.o gpio.o
8obj-$(CONFIG_PM) += pm.o sleep.o standby.o
9obj-$(CONFIG_CPU_FREQ) += cpu-pxa.o
10
11# Generic drivers that other drivers may depend upon
12obj-$(CONFIG_PXA_SSP) += ssp.o
13
14# SoC-specific code
8obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o pxa25x.o 15obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o pxa25x.o
9obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o pxa27x.o 16obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o pxa27x.o
10obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o pxa3xx.o smemc.o 17obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o pxa3xx.o smemc.o
@@ -48,11 +55,6 @@ led-$(CONFIG_MACH_TRIZEPS4) += leds-trizeps4.o
48 55
49obj-$(CONFIG_LEDS) += $(led-y) 56obj-$(CONFIG_LEDS) += $(led-y)
50 57
51# Misc features
52obj-$(CONFIG_PM) += pm.o sleep.o standby.o
53obj-$(CONFIG_CPU_FREQ) += cpu-pxa.o
54obj-$(CONFIG_PXA_SSP) += ssp.o
55
56ifeq ($(CONFIG_PCI),y) 58ifeq ($(CONFIG_PCI),y)
57obj-$(CONFIG_MACH_ARMCORE) += cm-x270-pci.o 59obj-$(CONFIG_MACH_ARMCORE) += cm-x270-pci.o
58endif 60endif
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 259ca821e464..b757dd756655 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -493,8 +493,6 @@ static struct platform_device *devices[] __initdata = {
493 493
494static void corgi_poweroff(void) 494static void corgi_poweroff(void)
495{ 495{
496 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
497
498 if (!machine_is_corgi()) 496 if (!machine_is_corgi())
499 /* Green LED off tells the bootloader to halt */ 497 /* Green LED off tells the bootloader to halt */
500 reset_scoop_gpio(&corgiscoop_device.dev, CORGI_SCP_LED_GREEN); 498 reset_scoop_gpio(&corgiscoop_device.dev, CORGI_SCP_LED_GREEN);
@@ -503,8 +501,6 @@ static void corgi_poweroff(void)
503 501
504static void corgi_restart(char mode) 502static void corgi_restart(char mode)
505{ 503{
506 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
507
508 if (!machine_is_corgi()) 504 if (!machine_is_corgi())
509 /* Green LED on tells the bootloader to reboot */ 505 /* Green LED on tells the bootloader to reboot */
510 set_scoop_gpio(&corgiscoop_device.dev, CORGI_SCP_LED_GREEN); 506 set_scoop_gpio(&corgiscoop_device.dev, CORGI_SCP_LED_GREEN);
diff --git a/arch/arm/mach-pxa/cpu-pxa.c b/arch/arm/mach-pxa/cpu-pxa.c
index 4b21479332ae..fb9ba1ab2826 100644
--- a/arch/arm/mach-pxa/cpu-pxa.c
+++ b/arch/arm/mach-pxa/cpu-pxa.c
@@ -49,125 +49,216 @@ MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
49#define freq_debug 0 49#define freq_debug 0
50#endif 50#endif
51 51
52static unsigned int pxa27x_maxfreq;
53module_param(pxa27x_maxfreq, uint, 0);
54MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz"
55 "(typically 624=>pxa270, 416=>pxa271, 520=>pxa272)");
56
52typedef struct { 57typedef struct {
53 unsigned int khz; 58 unsigned int khz;
54 unsigned int membus; 59 unsigned int membus;
55 unsigned int cccr; 60 unsigned int cccr;
56 unsigned int div2; 61 unsigned int div2;
62 unsigned int cclkcfg;
57} pxa_freqs_t; 63} pxa_freqs_t;
58 64
59/* Define the refresh period in mSec for the SDRAM and the number of rows */ 65/* Define the refresh period in mSec for the SDRAM and the number of rows */
60#define SDRAM_TREF 64 /* standard 64ms SDRAM */ 66#define SDRAM_TREF 64 /* standard 64ms SDRAM */
61#define SDRAM_ROWS 4096 /* 64MB=8192 32MB=4096 */ 67#define SDRAM_ROWS 4096 /* 64MB=8192 32MB=4096 */
62#define MDREFR_DRI(x) (((x) * SDRAM_TREF) / (SDRAM_ROWS * 32))
63
64#define CCLKCFG_TURBO 0x1
65#define CCLKCFG_FCS 0x2
66#define PXA25x_MIN_FREQ 99500
67#define PXA25x_MAX_FREQ 398100
68#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2)
69#define MDREFR_DRI_MASK 0xFFF
70 68
69#define CCLKCFG_TURBO 0x1
70#define CCLKCFG_FCS 0x2
71#define CCLKCFG_HALFTURBO 0x4
72#define CCLKCFG_FASTBUS 0x8
73#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2)
74#define MDREFR_DRI_MASK 0xFFF
71 75
76/*
77 * PXA255 definitions
78 */
72/* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */ 79/* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */
80#define CCLKCFG CCLKCFG_TURBO | CCLKCFG_FCS
81
73static pxa_freqs_t pxa255_run_freqs[] = 82static pxa_freqs_t pxa255_run_freqs[] =
74{ 83{
75 /* CPU MEMBUS CCCR DIV2*/ 84 /* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */
76 { 99500, 99500, 0x121, 1}, /* run= 99, turbo= 99, PXbus=50, SDRAM=50 */ 85 { 99500, 99500, 0x121, 1, CCLKCFG}, /* 99, 99, 50, 50 */
77 {132700, 132700, 0x123, 1}, /* run=133, turbo=133, PXbus=66, SDRAM=66 */ 86 {132700, 132700, 0x123, 1, CCLKCFG}, /* 133, 133, 66, 66 */
78 {199100, 99500, 0x141, 0}, /* run=199, turbo=199, PXbus=99, SDRAM=99 */ 87 {199100, 99500, 0x141, 0, CCLKCFG}, /* 199, 199, 99, 99 */
79 {265400, 132700, 0x143, 1}, /* run=265, turbo=265, PXbus=133, SDRAM=66 */ 88 {265400, 132700, 0x143, 1, CCLKCFG}, /* 265, 265, 133, 66 */
80 {331800, 165900, 0x145, 1}, /* run=331, turbo=331, PXbus=166, SDRAM=83 */ 89 {331800, 165900, 0x145, 1, CCLKCFG}, /* 331, 331, 166, 83 */
81 {398100, 99500, 0x161, 0}, /* run=398, turbo=398, PXbus=196, SDRAM=99 */ 90 {398100, 99500, 0x161, 0, CCLKCFG}, /* 398, 398, 196, 99 */
82 {0,}
83}; 91};
84#define NUM_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
85
86static struct cpufreq_frequency_table pxa255_run_freq_table[NUM_RUN_FREQS+1];
87 92
88/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */ 93/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
89static pxa_freqs_t pxa255_turbo_freqs[] = 94static pxa_freqs_t pxa255_turbo_freqs[] =
90{ 95{
91 /* CPU MEMBUS CCCR DIV2*/ 96 /* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */
92 { 99500, 99500, 0x121, 1}, /* run=99, turbo= 99, PXbus=50, SDRAM=50 */ 97 { 99500, 99500, 0x121, 1, CCLKCFG}, /* 99, 99, 50, 50 */
93 {199100, 99500, 0x221, 0}, /* run=99, turbo=199, PXbus=50, SDRAM=99 */ 98 {199100, 99500, 0x221, 0, CCLKCFG}, /* 99, 199, 50, 99 */
94 {298500, 99500, 0x321, 0}, /* run=99, turbo=287, PXbus=50, SDRAM=99 */ 99 {298500, 99500, 0x321, 0, CCLKCFG}, /* 99, 287, 50, 99 */
95 {298600, 99500, 0x1c1, 0}, /* run=199, turbo=287, PXbus=99, SDRAM=99 */ 100 {298600, 99500, 0x1c1, 0, CCLKCFG}, /* 199, 287, 99, 99 */
96 {398100, 99500, 0x241, 0}, /* run=199, turbo=398, PXbus=99, SDRAM=99 */ 101 {398100, 99500, 0x241, 0, CCLKCFG}, /* 199, 398, 99, 99 */
97 {0,} 102};
103
104#define NUM_PXA25x_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
105#define NUM_PXA25x_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)
106
107static struct cpufreq_frequency_table
108 pxa255_run_freq_table[NUM_PXA25x_RUN_FREQS+1];
109static struct cpufreq_frequency_table
110 pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1];
111
112/*
113 * PXA270 definitions
114 *
115 * For the PXA27x:
116 * Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG.
117 *
118 * A = 0 => memory controller clock from table 3-7,
119 * A = 1 => memory controller clock = system bus clock
120 * Run mode frequency = 13 MHz * L
121 * Turbo mode frequency = 13 MHz * L * N
122 * System bus frequency = 13 MHz * L / (B + 1)
123 *
124 * In CCCR:
125 * A = 1
126 * L = 16 oscillator to run mode ratio
127 * 2N = 6 2 * (turbo mode to run mode ratio)
128 *
129 * In CCLKCFG:
130 * B = 1 Fast bus mode
131 * HT = 0 Half-Turbo mode
132 * T = 1 Turbo mode
133 *
134 * For now, just support some of the combinations in table 3-7 of
135 * PXA27x Processor Family Developer's Manual to simplify frequency
136 * change sequences.
137 */
138#define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L)
139#define CCLKCFG2(B, HT, T) \
140 (CCLKCFG_FCS | \
141 ((B) ? CCLKCFG_FASTBUS : 0) | \
142 ((HT) ? CCLKCFG_HALFTURBO : 0) | \
143 ((T) ? CCLKCFG_TURBO : 0))
144
145static pxa_freqs_t pxa27x_freqs[] = {
146 {104000, 104000, PXA27x_CCCR(1, 8, 2), 0, CCLKCFG2(1, 0, 1)},
147 {156000, 104000, PXA27x_CCCR(1, 8, 6), 0, CCLKCFG2(1, 1, 1)},
148 {208000, 208000, PXA27x_CCCR(0, 16, 2), 1, CCLKCFG2(0, 0, 1)},
149 {312000, 208000, PXA27x_CCCR(1, 16, 3), 1, CCLKCFG2(1, 0, 1)},
150 {416000, 208000, PXA27x_CCCR(1, 16, 4), 1, CCLKCFG2(1, 0, 1)},
151 {520000, 208000, PXA27x_CCCR(1, 16, 5), 1, CCLKCFG2(1, 0, 1)},
152 {624000, 208000, PXA27x_CCCR(1, 16, 6), 1, CCLKCFG2(1, 0, 1)}
98}; 153};
99#define NUM_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)
100 154
101static struct cpufreq_frequency_table pxa255_turbo_freq_table[NUM_TURBO_FREQS+1]; 155#define NUM_PXA27x_FREQS ARRAY_SIZE(pxa27x_freqs)
156static struct cpufreq_frequency_table
157 pxa27x_freq_table[NUM_PXA27x_FREQS+1];
102 158
103extern unsigned get_clk_frequency_khz(int info); 159extern unsigned get_clk_frequency_khz(int info);
104 160
161static void find_freq_tables(struct cpufreq_policy *policy,
162 struct cpufreq_frequency_table **freq_table,
163 pxa_freqs_t **pxa_freqs)
164{
165 if (cpu_is_pxa25x()) {
166 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
167 *pxa_freqs = pxa255_run_freqs;
168 *freq_table = pxa255_run_freq_table;
169 } else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) {
170 *pxa_freqs = pxa255_turbo_freqs;
171 *freq_table = pxa255_turbo_freq_table;
172 } else {
173 printk("CPU PXA: Unknown policy found. "
174 "Using CPUFREQ_POLICY_PERFORMANCE\n");
175 *pxa_freqs = pxa255_run_freqs;
176 *freq_table = pxa255_run_freq_table;
177 }
178 }
179 if (cpu_is_pxa27x()) {
180 *pxa_freqs = pxa27x_freqs;
181 *freq_table = pxa27x_freq_table;
182 }
183}
184
185static void pxa27x_guess_max_freq(void)
186{
187 if (!pxa27x_maxfreq) {
188 pxa27x_maxfreq = 416000;
189 printk(KERN_INFO "PXA CPU 27x max frequency not defined "
190 "(pxa27x_maxfreq), assuming pxa271 with %dkHz maxfreq\n",
191 pxa27x_maxfreq);
192 } else {
193 pxa27x_maxfreq *= 1000;
194 }
195}
196
197static u32 mdrefr_dri(unsigned int freq)
198{
199 u32 dri = 0;
200
201 if (cpu_is_pxa25x())
202 dri = ((freq * SDRAM_TREF) / (SDRAM_ROWS * 32));
203 if (cpu_is_pxa27x())
204 dri = ((freq * SDRAM_TREF) / (SDRAM_ROWS - 31)) / 32;
205 return dri;
206}
207
105/* find a valid frequency point */ 208/* find a valid frequency point */
106static int pxa_verify_policy(struct cpufreq_policy *policy) 209static int pxa_verify_policy(struct cpufreq_policy *policy)
107{ 210{
108 struct cpufreq_frequency_table *pxa_freqs_table; 211 struct cpufreq_frequency_table *pxa_freqs_table;
212 pxa_freqs_t *pxa_freqs;
109 int ret; 213 int ret;
110 214
111 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) { 215 find_freq_tables(policy, &pxa_freqs_table, &pxa_freqs);
112 pxa_freqs_table = pxa255_run_freq_table;
113 } else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) {
114 pxa_freqs_table = pxa255_turbo_freq_table;
115 } else {
116 printk("CPU PXA: Unknown policy found. "
117 "Using CPUFREQ_POLICY_PERFORMANCE\n");
118 pxa_freqs_table = pxa255_run_freq_table;
119 }
120
121 ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table); 216 ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table);
122 217
123 if (freq_debug) 218 if (freq_debug)
124 pr_debug("Verified CPU policy: %dKhz min to %dKhz max\n", 219 pr_debug("Verified CPU policy: %dKhz min to %dKhz max\n",
125 policy->min, policy->max); 220 policy->min, policy->max);
126 221
127 return ret; 222 return ret;
128} 223}
129 224
225static unsigned int pxa_cpufreq_get(unsigned int cpu)
226{
227 return get_clk_frequency_khz(0);
228}
229
130static int pxa_set_target(struct cpufreq_policy *policy, 230static int pxa_set_target(struct cpufreq_policy *policy,
131 unsigned int target_freq, 231 unsigned int target_freq,
132 unsigned int relation) 232 unsigned int relation)
133{ 233{
134 struct cpufreq_frequency_table *pxa_freqs_table; 234 struct cpufreq_frequency_table *pxa_freqs_table;
135 pxa_freqs_t *pxa_freq_settings; 235 pxa_freqs_t *pxa_freq_settings;
136 struct cpufreq_freqs freqs; 236 struct cpufreq_freqs freqs;
137 unsigned int idx; 237 unsigned int idx;
138 unsigned long flags; 238 unsigned long flags;
139 unsigned int unused, preset_mdrefr, postset_mdrefr; 239 unsigned int new_freq_cpu, new_freq_mem;
140 void *ramstart = phys_to_virt(0xa0000000); 240 unsigned int unused, preset_mdrefr, postset_mdrefr, cclkcfg;
141 241
142 /* Get the current policy */ 242 /* Get the current policy */
143 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) { 243 find_freq_tables(policy, &pxa_freqs_table, &pxa_freq_settings);
144 pxa_freq_settings = pxa255_run_freqs;
145 pxa_freqs_table = pxa255_run_freq_table;
146 } else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) {
147 pxa_freq_settings = pxa255_turbo_freqs;
148 pxa_freqs_table = pxa255_turbo_freq_table;
149 } else {
150 printk("CPU PXA: Unknown policy found. "
151 "Using CPUFREQ_POLICY_PERFORMANCE\n");
152 pxa_freq_settings = pxa255_run_freqs;
153 pxa_freqs_table = pxa255_run_freq_table;
154 }
155 244
156 /* Lookup the next frequency */ 245 /* Lookup the next frequency */
157 if (cpufreq_frequency_table_target(policy, pxa_freqs_table, 246 if (cpufreq_frequency_table_target(policy, pxa_freqs_table,
158 target_freq, relation, &idx)) { 247 target_freq, relation, &idx)) {
159 return -EINVAL; 248 return -EINVAL;
160 } 249 }
161 250
251 new_freq_cpu = pxa_freq_settings[idx].khz;
252 new_freq_mem = pxa_freq_settings[idx].membus;
162 freqs.old = policy->cur; 253 freqs.old = policy->cur;
163 freqs.new = pxa_freq_settings[idx].khz; 254 freqs.new = new_freq_cpu;
164 freqs.cpu = policy->cpu; 255 freqs.cpu = policy->cpu;
165 256
166 if (freq_debug) 257 if (freq_debug)
167 pr_debug(KERN_INFO "Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n", 258 pr_debug(KERN_INFO "Changing CPU frequency to %d Mhz, "
168 freqs.new / 1000, (pxa_freq_settings[idx].div2) ? 259 "(SDRAM %d Mhz)\n",
169 (pxa_freq_settings[idx].membus / 2000) : 260 freqs.new / 1000, (pxa_freq_settings[idx].div2) ?
170 (pxa_freq_settings[idx].membus / 1000)); 261 (new_freq_mem / 2000) : (new_freq_mem / 1000));
171 262
172 /* 263 /*
173 * Tell everyone what we're about to do... 264 * Tell everyone what we're about to do...
@@ -177,16 +268,16 @@ static int pxa_set_target(struct cpufreq_policy *policy,
177 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); 268 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
178 269
179 /* Calculate the next MDREFR. If we're slowing down the SDRAM clock 270 /* Calculate the next MDREFR. If we're slowing down the SDRAM clock
180 * we need to preset the smaller DRI before the change. If we're speeding 271 * we need to preset the smaller DRI before the change. If we're
181 * up we need to set the larger DRI value after the change. 272 * speeding up we need to set the larger DRI value after the change.
182 */ 273 */
183 preset_mdrefr = postset_mdrefr = MDREFR; 274 preset_mdrefr = postset_mdrefr = MDREFR;
184 if ((MDREFR & MDREFR_DRI_MASK) > MDREFR_DRI(pxa_freq_settings[idx].membus)) { 275 if ((MDREFR & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) {
185 preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK) | 276 preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK);
186 MDREFR_DRI(pxa_freq_settings[idx].membus); 277 preset_mdrefr |= mdrefr_dri(new_freq_mem);
187 } 278 }
188 postset_mdrefr = (postset_mdrefr & ~MDREFR_DRI_MASK) | 279 postset_mdrefr =
189 MDREFR_DRI(pxa_freq_settings[idx].membus); 280 (postset_mdrefr & ~MDREFR_DRI_MASK) | mdrefr_dri(new_freq_mem);
190 281
191 /* If we're dividing the memory clock by two for the SDRAM clock, this 282 /* If we're dividing the memory clock by two for the SDRAM clock, this
192 * must be set prior to the change. Clearing the divide must be done 283 * must be set prior to the change. Clearing the divide must be done
@@ -201,26 +292,27 @@ static int pxa_set_target(struct cpufreq_policy *policy,
201 292
202 local_irq_save(flags); 293 local_irq_save(flags);
203 294
204 /* Set new the CCCR */ 295 /* Set new the CCCR and prepare CCLKCFG */
205 CCCR = pxa_freq_settings[idx].cccr; 296 CCCR = pxa_freq_settings[idx].cccr;
297 cclkcfg = pxa_freq_settings[idx].cclkcfg;
206 298
207 asm volatile(" \n\ 299 asm volatile(" \n\
208 ldr r4, [%1] /* load MDREFR */ \n\ 300 ldr r4, [%1] /* load MDREFR */ \n\
209 b 2f \n\ 301 b 2f \n\
210 .align 5 \n\ 302 .align 5 \n\
2111: \n\ 3031: \n\
212 str %4, [%1] /* preset the MDREFR */ \n\ 304 str %3, [%1] /* preset the MDREFR */ \n\
213 mcr p14, 0, %2, c6, c0, 0 /* set CCLKCFG[FCS] */ \n\ 305 mcr p14, 0, %2, c6, c0, 0 /* set CCLKCFG[FCS] */ \n\
214 str %5, [%1] /* postset the MDREFR */ \n\ 306 str %4, [%1] /* postset the MDREFR */ \n\
215 \n\ 307 \n\
216 b 3f \n\ 308 b 3f \n\
2172: b 1b \n\ 3092: b 1b \n\
2183: nop \n\ 3103: nop \n\
219 " 311 "
220 : "=&r" (unused) 312 : "=&r" (unused)
221 : "r" (&MDREFR), "r" (CCLKCFG_TURBO|CCLKCFG_FCS), "r" (ramstart), 313 : "r" (&MDREFR), "r" (cclkcfg),
222 "r" (preset_mdrefr), "r" (postset_mdrefr) 314 "r" (preset_mdrefr), "r" (postset_mdrefr)
223 : "r4", "r5"); 315 : "r4", "r5");
224 local_irq_restore(flags); 316 local_irq_restore(flags);
225 317
226 /* 318 /*
@@ -233,38 +325,57 @@ static int pxa_set_target(struct cpufreq_policy *policy,
233 return 0; 325 return 0;
234} 326}
235 327
236static unsigned int pxa_cpufreq_get(unsigned int cpu) 328static __init int pxa_cpufreq_init(struct cpufreq_policy *policy)
237{
238 return get_clk_frequency_khz(0);
239}
240
241static int pxa_cpufreq_init(struct cpufreq_policy *policy)
242{ 329{
243 int i; 330 int i;
331 unsigned int freq;
332
333 /* try to guess pxa27x cpu */
334 if (cpu_is_pxa27x())
335 pxa27x_guess_max_freq();
244 336
245 /* set default policy and cpuinfo */ 337 /* set default policy and cpuinfo */
246 policy->governor = CPUFREQ_DEFAULT_GOVERNOR; 338 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
247 policy->policy = CPUFREQ_POLICY_PERFORMANCE; 339 if (cpu_is_pxa25x())
248 policy->cpuinfo.max_freq = PXA25x_MAX_FREQ; 340 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
249 policy->cpuinfo.min_freq = PXA25x_MIN_FREQ;
250 policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */ 341 policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
251 policy->cur = get_clk_frequency_khz(0); /* current freq */ 342 policy->cur = get_clk_frequency_khz(0); /* current freq */
252 policy->min = policy->max = policy->cur; 343 policy->min = policy->max = policy->cur;
253 344
254 /* Generate the run cpufreq_frequency_table struct */ 345 /* Generate pxa25x the run cpufreq_frequency_table struct */
255 for (i = 0; i < NUM_RUN_FREQS; i++) { 346 for (i = 0; i < NUM_PXA25x_RUN_FREQS; i++) {
256 pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz; 347 pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz;
257 pxa255_run_freq_table[i].index = i; 348 pxa255_run_freq_table[i].index = i;
258 } 349 }
259
260 pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END; 350 pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;
261 /* Generate the turbo cpufreq_frequency_table struct */ 351
262 for (i = 0; i < NUM_TURBO_FREQS; i++) { 352 /* Generate pxa25x the turbo cpufreq_frequency_table struct */
263 pxa255_turbo_freq_table[i].frequency = pxa255_turbo_freqs[i].khz; 353 for (i = 0; i < NUM_PXA25x_TURBO_FREQS; i++) {
354 pxa255_turbo_freq_table[i].frequency =
355 pxa255_turbo_freqs[i].khz;
264 pxa255_turbo_freq_table[i].index = i; 356 pxa255_turbo_freq_table[i].index = i;
265 } 357 }
266 pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END; 358 pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;
267 359
360 /* Generate the pxa27x cpufreq_frequency_table struct */
361 for (i = 0; i < NUM_PXA27x_FREQS; i++) {
362 freq = pxa27x_freqs[i].khz;
363 if (freq > pxa27x_maxfreq)
364 break;
365 pxa27x_freq_table[i].frequency = freq;
366 pxa27x_freq_table[i].index = i;
367 }
368 pxa27x_freq_table[i].frequency = CPUFREQ_TABLE_END;
369
370 /*
371 * Set the policy's minimum and maximum frequencies from the tables
372 * just constructed. This sets cpuinfo.mxx_freq, min and max.
373 */
374 if (cpu_is_pxa25x())
375 cpufreq_frequency_table_cpuinfo(policy, pxa255_run_freq_table);
376 else if (cpu_is_pxa27x())
377 cpufreq_frequency_table_cpuinfo(policy, pxa27x_freq_table);
378
268 printk(KERN_INFO "PXA CPU frequency change support initialized\n"); 379 printk(KERN_INFO "PXA CPU frequency change support initialized\n");
269 380
270 return 0; 381 return 0;
@@ -275,26 +386,25 @@ static struct cpufreq_driver pxa_cpufreq_driver = {
275 .target = pxa_set_target, 386 .target = pxa_set_target,
276 .init = pxa_cpufreq_init, 387 .init = pxa_cpufreq_init,
277 .get = pxa_cpufreq_get, 388 .get = pxa_cpufreq_get,
278 .name = "PXA25x", 389 .name = "PXA2xx",
279}; 390};
280 391
281static int __init pxa_cpu_init(void) 392static int __init pxa_cpu_init(void)
282{ 393{
283 int ret = -ENODEV; 394 int ret = -ENODEV;
284 if (cpu_is_pxa25x()) 395 if (cpu_is_pxa25x() || cpu_is_pxa27x())
285 ret = cpufreq_register_driver(&pxa_cpufreq_driver); 396 ret = cpufreq_register_driver(&pxa_cpufreq_driver);
286 return ret; 397 return ret;
287} 398}
288 399
289static void __exit pxa_cpu_exit(void) 400static void __exit pxa_cpu_exit(void)
290{ 401{
291 if (cpu_is_pxa25x()) 402 cpufreq_unregister_driver(&pxa_cpufreq_driver);
292 cpufreq_unregister_driver(&pxa_cpufreq_driver);
293} 403}
294 404
295 405
296MODULE_AUTHOR ("Intrinsyc Software Inc."); 406MODULE_AUTHOR("Intrinsyc Software Inc.");
297MODULE_DESCRIPTION ("CPU frequency changing driver for the PXA architecture"); 407MODULE_DESCRIPTION("CPU frequency changing driver for the PXA architecture");
298MODULE_LICENSE("GPL"); 408MODULE_LICENSE("GPL");
299module_init(pxa_cpu_init); 409module_init(pxa_cpu_init);
300module_exit(pxa_cpu_exit); 410module_exit(pxa_cpu_exit);
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 0993f4d1a0bc..7b9bdd0c6665 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -396,7 +396,7 @@ static struct pxafb_mach_info sharp_lm8v31 = {
396 .cmap_inverse = 0, 396 .cmap_inverse = 0,
397 .cmap_static = 0, 397 .cmap_static = 0,
398 .lcd_conn = LCD_COLOR_DSTN_16BPP | LCD_PCLK_EDGE_FALL | 398 .lcd_conn = LCD_COLOR_DSTN_16BPP | LCD_PCLK_EDGE_FALL |
399 LCD_AC_BIAS_FREQ(255); 399 LCD_AC_BIAS_FREQ(255),
400}; 400};
401 401
402#define MMC_POLL_RATE msecs_to_jiffies(1000) 402#define MMC_POLL_RATE msecs_to_jiffies(1000)
diff --git a/arch/arm/mach-pxa/pm.c b/arch/arm/mach-pxa/pm.c
index ec1bbf333a3a..7d4debbdcca3 100644
--- a/arch/arm/mach-pxa/pm.c
+++ b/arch/arm/mach-pxa/pm.c
@@ -42,20 +42,17 @@ int pxa_pm_enter(suspend_state_t state)
42 if (state != PM_SUSPEND_STANDBY) { 42 if (state != PM_SUSPEND_STANDBY) {
43 pxa_cpu_pm_fns->save(sleep_save); 43 pxa_cpu_pm_fns->save(sleep_save);
44 /* before sleeping, calculate and save a checksum */ 44 /* before sleeping, calculate and save a checksum */
45 for (i = 0; i < pxa_cpu_pm_fns->save_size - 1; i++) 45 for (i = 0; i < pxa_cpu_pm_fns->save_count - 1; i++)
46 sleep_save_checksum += sleep_save[i]; 46 sleep_save_checksum += sleep_save[i];
47 } 47 }
48 48
49 /* Clear reset status */
50 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
51
52 /* *** go zzz *** */ 49 /* *** go zzz *** */
53 pxa_cpu_pm_fns->enter(state); 50 pxa_cpu_pm_fns->enter(state);
54 cpu_init(); 51 cpu_init();
55 52
56 if (state != PM_SUSPEND_STANDBY) { 53 if (state != PM_SUSPEND_STANDBY) {
57 /* after sleeping, validate the checksum */ 54 /* after sleeping, validate the checksum */
58 for (i = 0; i < pxa_cpu_pm_fns->save_size - 1; i++) 55 for (i = 0; i < pxa_cpu_pm_fns->save_count - 1; i++)
59 checksum += sleep_save[i]; 56 checksum += sleep_save[i];
60 57
61 /* if invalid, display message and wait for a hardware reset */ 58 /* if invalid, display message and wait for a hardware reset */
@@ -101,7 +98,8 @@ static int __init pxa_pm_init(void)
101 return -EINVAL; 98 return -EINVAL;
102 } 99 }
103 100
104 sleep_save = kmalloc(pxa_cpu_pm_fns->save_size, GFP_KERNEL); 101 sleep_save = kmalloc(pxa_cpu_pm_fns->save_count * sizeof(unsigned long),
102 GFP_KERNEL);
105 if (!sleep_save) { 103 if (!sleep_save) {
106 printk(KERN_ERR "failed to alloc memory for pm save\n"); 104 printk(KERN_ERR "failed to alloc memory for pm save\n");
107 return -ENOMEM; 105 return -ENOMEM;
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index ca5ac196b47b..0b30f25cff3c 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -326,13 +326,11 @@ static struct platform_device *devices[] __initdata = {
326 326
327static void poodle_poweroff(void) 327static void poodle_poweroff(void)
328{ 328{
329 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
330 arm_machine_restart('h'); 329 arm_machine_restart('h');
331} 330}
332 331
333static void poodle_restart(char mode) 332static void poodle_restart(char mode)
334{ 333{
335 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
336 arm_machine_restart('h'); 334 arm_machine_restart('h');
337} 335}
338 336
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index d9b5450aee5b..e5b417d14bb0 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -150,9 +150,7 @@ static struct clk pxa25x_clks[] = {
150 * More ones like CP and general purpose register values are preserved 150 * More ones like CP and general purpose register values are preserved
151 * with the stack pointer in sleep.S. 151 * with the stack pointer in sleep.S.
152 */ 152 */
153enum { SLEEP_SAVE_START = 0, 153enum { SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2,
154
155 SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2,
156 154
157 SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U, 155 SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
158 SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U, 156 SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
@@ -162,7 +160,7 @@ enum { SLEEP_SAVE_START = 0,
162 160
163 SLEEP_SAVE_CKEN, 161 SLEEP_SAVE_CKEN,
164 162
165 SLEEP_SAVE_SIZE 163 SLEEP_SAVE_COUNT
166}; 164};
167 165
168 166
@@ -200,6 +198,9 @@ static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
200 198
201static void pxa25x_cpu_pm_enter(suspend_state_t state) 199static void pxa25x_cpu_pm_enter(suspend_state_t state)
202{ 200{
201 /* Clear reset status */
202 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
203
203 switch (state) { 204 switch (state) {
204 case PM_SUSPEND_MEM: 205 case PM_SUSPEND_MEM:
205 /* set resume return address */ 206 /* set resume return address */
@@ -210,7 +211,7 @@ static void pxa25x_cpu_pm_enter(suspend_state_t state)
210} 211}
211 212
212static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = { 213static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
213 .save_size = SLEEP_SAVE_SIZE, 214 .save_count = SLEEP_SAVE_COUNT,
214 .valid = suspend_valid_only_mem, 215 .valid = suspend_valid_only_mem,
215 .save = pxa25x_cpu_pm_save, 216 .save = pxa25x_cpu_pm_save,
216 .restore = pxa25x_cpu_pm_restore, 217 .restore = pxa25x_cpu_pm_restore,
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 7a2449dd0fd4..7e945836e129 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -181,9 +181,7 @@ static struct clk pxa27x_clks[] = {
181 * More ones like CP and general purpose register values are preserved 181 * More ones like CP and general purpose register values are preserved
182 * with the stack pointer in sleep.S. 182 * with the stack pointer in sleep.S.
183 */ 183 */
184enum { SLEEP_SAVE_START = 0, 184enum { SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3,
185
186 SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3,
187 185
188 SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U, 186 SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
189 SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U, 187 SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
@@ -198,7 +196,7 @@ enum { SLEEP_SAVE_START = 0,
198 SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER, 196 SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER,
199 SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR, 197 SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR,
200 198
201 SLEEP_SAVE_SIZE 199 SLEEP_SAVE_COUNT
202}; 200};
203 201
204void pxa27x_cpu_pm_save(unsigned long *sleep_save) 202void pxa27x_cpu_pm_save(unsigned long *sleep_save)
@@ -251,6 +249,9 @@ void pxa27x_cpu_pm_enter(suspend_state_t state)
251 /* Clear edge-detect status register. */ 249 /* Clear edge-detect status register. */
252 PEDR = 0xDF12FE1B; 250 PEDR = 0xDF12FE1B;
253 251
252 /* Clear reset status */
253 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
254
254 switch (state) { 255 switch (state) {
255 case PM_SUSPEND_STANDBY: 256 case PM_SUSPEND_STANDBY:
256 pxa_cpu_standby(); 257 pxa_cpu_standby();
@@ -269,7 +270,7 @@ static int pxa27x_cpu_pm_valid(suspend_state_t state)
269} 270}
270 271
271static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = { 272static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
272 .save_size = SLEEP_SAVE_SIZE, 273 .save_count = SLEEP_SAVE_COUNT,
273 .save = pxa27x_cpu_pm_save, 274 .save = pxa27x_cpu_pm_save,
274 .restore = pxa27x_cpu_pm_restore, 275 .restore = pxa27x_cpu_pm_restore,
275 .valid = pxa27x_cpu_pm_valid, 276 .valid = pxa27x_cpu_pm_valid,
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index b6a6f5fcc77a..644550bfa330 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -256,12 +256,11 @@ static unsigned long wakeup_src;
256#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 256#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
257#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] 257#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
258 258
259enum { SLEEP_SAVE_START = 0, 259enum { SLEEP_SAVE_CKENA,
260 SLEEP_SAVE_CKENA,
261 SLEEP_SAVE_CKENB, 260 SLEEP_SAVE_CKENB,
262 SLEEP_SAVE_ACCR, 261 SLEEP_SAVE_ACCR,
263 262
264 SLEEP_SAVE_SIZE, 263 SLEEP_SAVE_COUNT,
265}; 264};
266 265
267static void pxa3xx_cpu_pm_save(unsigned long *sleep_save) 266static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
@@ -376,7 +375,7 @@ static int pxa3xx_cpu_pm_valid(suspend_state_t state)
376} 375}
377 376
378static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { 377static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
379 .save_size = SLEEP_SAVE_SIZE, 378 .save_count = SLEEP_SAVE_COUNT,
380 .save = pxa3xx_cpu_pm_save, 379 .save = pxa3xx_cpu_pm_save,
381 .restore = pxa3xx_cpu_pm_restore, 380 .restore = pxa3xx_cpu_pm_restore,
382 .valid = pxa3xx_cpu_pm_valid, 381 .valid = pxa3xx_cpu_pm_valid,
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 62a02c3927c5..e7d0fcd9b43f 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -529,8 +529,6 @@ static struct platform_device *devices[] __initdata = {
529 529
530static void spitz_poweroff(void) 530static void spitz_poweroff(void)
531{ 531{
532 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
533
534 pxa_gpio_mode(SPITZ_GPIO_ON_RESET | GPIO_OUT); 532 pxa_gpio_mode(SPITZ_GPIO_ON_RESET | GPIO_OUT);
535 GPSR(SPITZ_GPIO_ON_RESET) = GPIO_bit(SPITZ_GPIO_ON_RESET); 533 GPSR(SPITZ_GPIO_ON_RESET) = GPIO_bit(SPITZ_GPIO_ON_RESET);
536 534
diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c
index 7a7f5f947cc5..23f050feb208 100644
--- a/arch/arm/mach-pxa/spitz_pm.c
+++ b/arch/arm/mach-pxa/spitz_pm.c
@@ -119,9 +119,6 @@ static void spitz_presuspend(void)
119 /* nRESET_OUT Disable */ 119 /* nRESET_OUT Disable */
120 PSLR |= PSLR_SL_ROD; 120 PSLR |= PSLR_SL_ROD;
121 121
122 /* Clear reset status */
123 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
124
125 /* Stop 3.6MHz and drive HIGH to PCMCIA and CS */ 122 /* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
126 PCFR = PCFR_GPR_EN | PCFR_OPDE; 123 PCFR = PCFR_GPR_EN | PCFR_OPDE;
127} 124}
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 6458f6d371d9..c2cbd66db814 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -467,8 +467,6 @@ static struct platform_device *devices[] __initdata = {
467 467
468static void tosa_poweroff(void) 468static void tosa_poweroff(void)
469{ 469{
470 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
471
472 pxa_gpio_mode(TOSA_GPIO_ON_RESET | GPIO_OUT); 470 pxa_gpio_mode(TOSA_GPIO_ON_RESET | GPIO_OUT);
473 GPSR(TOSA_GPIO_ON_RESET) = GPIO_bit(TOSA_GPIO_ON_RESET); 471 GPSR(TOSA_GPIO_ON_RESET) = GPIO_bit(TOSA_GPIO_ON_RESET);
474 472
diff --git a/arch/arm/mach-sa1100/pm.c b/arch/arm/mach-sa1100/pm.c
index 246c573e7252..1693d447a224 100644
--- a/arch/arm/mach-sa1100/pm.c
+++ b/arch/arm/mach-sa1100/pm.c
@@ -43,20 +43,18 @@ extern void sa1100_cpu_resume(void);
43 * More ones like CP and general purpose register values are preserved 43 * More ones like CP and general purpose register values are preserved
44 * on the stack and then the stack pointer is stored last in sleep.S. 44 * on the stack and then the stack pointer is stored last in sleep.S.
45 */ 45 */
46enum { SLEEP_SAVE_SP = 0, 46enum { SLEEP_SAVE_GPDR, SLEEP_SAVE_GAFR,
47
48 SLEEP_SAVE_GPDR, SLEEP_SAVE_GAFR,
49 SLEEP_SAVE_PPDR, SLEEP_SAVE_PPSR, SLEEP_SAVE_PPAR, SLEEP_SAVE_PSDR, 47 SLEEP_SAVE_PPDR, SLEEP_SAVE_PPSR, SLEEP_SAVE_PPAR, SLEEP_SAVE_PSDR,
50 48
51 SLEEP_SAVE_Ser1SDCR0, 49 SLEEP_SAVE_Ser1SDCR0,
52 50
53 SLEEP_SAVE_SIZE 51 SLEEP_SAVE_COUNT
54}; 52};
55 53
56 54
57static int sa11x0_pm_enter(suspend_state_t state) 55static int sa11x0_pm_enter(suspend_state_t state)
58{ 56{
59 unsigned long gpio, sleep_save[SLEEP_SAVE_SIZE]; 57 unsigned long gpio, sleep_save[SLEEP_SAVE_COUNT];
60 58
61 gpio = GPLR; 59 gpio = GPLR;
62 60
diff --git a/arch/arm/plat-s3c24xx/clock.c b/arch/arm/plat-s3c24xx/clock.c
index d84167fb33b1..3ac8d8d781b3 100644
--- a/arch/arm/plat-s3c24xx/clock.c
+++ b/arch/arm/plat-s3c24xx/clock.c
@@ -411,7 +411,7 @@ static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
411 411
412 clk->parent = parent; 412 clk->parent = parent;
413 413
414 if (clk == &s3c24xx_dclk0) 414 if (clk == &s3c24xx_clkout0)
415 mask = S3C2410_MISCCR_CLK0_MASK; 415 mask = S3C2410_MISCCR_CLK0_MASK;
416 else { 416 else {
417 source <<= 4; 417 source <<= 4;
@@ -437,7 +437,7 @@ struct clk s3c24xx_dclk0 = {
437struct clk s3c24xx_dclk1 = { 437struct clk s3c24xx_dclk1 = {
438 .name = "dclk1", 438 .name = "dclk1",
439 .id = -1, 439 .id = -1,
440 .ctrlbit = S3C2410_DCLKCON_DCLK0EN, 440 .ctrlbit = S3C2410_DCLKCON_DCLK1EN,
441 .enable = s3c24xx_dclk_enable, 441 .enable = s3c24xx_dclk_enable,
442 .set_parent = s3c24xx_dclk_setparent, 442 .set_parent = s3c24xx_dclk_setparent,
443 .set_rate = s3c24xx_set_dclk_rate, 443 .set_rate = s3c24xx_set_dclk_rate,
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 20:09:44 -0500