Merge branch 'sh/g3-prep' into sh/for-2.6.33

418 files changed, 18603 insertions, 4676 deletions

diff --git a/arch/Kconfig b/arch/Kconfig
index d82875820a15..9d055b4f0585 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -135,9 +135,7 @@ config HAVE_DEFAULT_NO_SPIN_MUTEXES
 
 config HAVE_HW_BREAKPOINT
         bool
-        depends on HAVE_PERF_EVENTS
-        select ANON_INODES
-        select PERF_EVENTS
+        depends on PERF_EVENTS
 
 config HAVE_USER_RETURN_NOTIFIER
         bool
diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig
index 443448154f32..bd7261ea8f94 100644
--- a/arch/alpha/Kconfig
+++ b/arch/alpha/Kconfig
@@ -9,6 +9,7 @@ config ALPHA
         select HAVE_IDE
         select HAVE_OPROFILE
         select HAVE_SYSCALL_WRAPPERS
+        select HAVE_PERF_EVENTS
         help
           The Alpha is a 64-bit general-purpose processor designed and
           marketed by the Digital Equipment Corporation of blessed memory,
diff --git a/arch/alpha/boot/bootp.c b/arch/alpha/boot/bootp.c
index 3af21c789339..3c8d1b25c661 100644
--- a/arch/alpha/boot/bootp.c
+++ b/arch/alpha/boot/bootp.c
@@ -9,7 +9,7 @@
  */
 #include <linux/kernel.h>
 #include <linux/string.h>
-#include <linux/utsrelease.h>
+#include <generated/utsrelease.h>
 #include <linux/mm.h>
 
 #include <asm/system.h>
diff --git a/arch/alpha/boot/bootpz.c b/arch/alpha/boot/bootpz.c
index 1036b515e20c..ade3f129dc27 100644
--- a/arch/alpha/boot/bootpz.c
+++ b/arch/alpha/boot/bootpz.c
@@ -11,7 +11,7 @@
  */
 #include <linux/kernel.h>
 #include <linux/string.h>
-#include <linux/utsrelease.h>
+#include <generated/utsrelease.h>
 #include <linux/mm.h>
 
 #include <asm/system.h>
diff --git a/arch/alpha/boot/main.c b/arch/alpha/boot/main.c
index 89f3be071ae5..644b7db55438 100644
--- a/arch/alpha/boot/main.c
+++ b/arch/alpha/boot/main.c
@@ -7,7 +7,7 @@
  */
 #include <linux/kernel.h>
 #include <linux/string.h>
-#include <linux/utsrelease.h>
+#include <generated/utsrelease.h>
 #include <linux/mm.h>
 
 #include <asm/system.h>
diff --git a/arch/alpha/include/asm/asm-offsets.h b/arch/alpha/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/alpha/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/alpha/include/asm/bug.h b/arch/alpha/include/asm/bug.h
index 1720c8ad86fe..f091682e3cc8 100644
--- a/arch/alpha/include/asm/bug.h
+++ b/arch/alpha/include/asm/bug.h
@@ -13,7 +13,8 @@
                 "call_pal %0  # bugchk\n\t"                             \
                 ".long %1\n\t.8byte %2"                                 \
                 : : "i"(PAL_bugchk), "i"(__LINE__), "i"(__FILE__));     \
-        for ( ; ; ); } while (0)
+        unreachable();                                                  \
+  } while (0)
 
 #define HAVE_ARCH_BUG
 #endif
diff --git a/arch/alpha/include/asm/fcntl.h b/arch/alpha/include/asm/fcntl.h
index 21b1117a0c61..70145cbb21cb 100644
--- a/arch/alpha/include/asm/fcntl.h
+++ b/arch/alpha/include/asm/fcntl.h
@@ -16,7 +16,7 @@
 #define O_NOATIME       04000000
 #define O_CLOEXEC       010000000 /* set close_on_exec */
 /*
- * Before Linux 2.6.32 only O_DSYNC semantics were implemented, but using
+ * Before Linux 2.6.33 only O_DSYNC semantics were implemented, but using
  * the O_SYNC flag.  We continue to use the existing numerical value
  * for O_DSYNC semantics now, but using the correct symbolic name for it.
  * This new value is used to request true Posix O_SYNC semantics.  It is
diff --git a/arch/alpha/include/asm/perf_event.h b/arch/alpha/include/asm/perf_event.h
new file mode 100644
index 000000000000..3bef8522017c
--- /dev/null
+++ b/arch/alpha/include/asm/perf_event.h
@@ -0,0 +1,9 @@
+#ifndef __ASM_ALPHA_PERF_EVENT_H
+#define __ASM_ALPHA_PERF_EVENT_H
+
+/* Alpha only supports software events through this interface. */
+static inline void set_perf_event_pending(void) { }
+
+#define PERF_EVENT_INDEX_OFFSET 0
+
+#endif /* __ASM_ALPHA_PERF_EVENT_H */
diff --git a/arch/alpha/include/asm/unistd.h b/arch/alpha/include/asm/unistd.h
index 7f23665122df..804e5311c841 100644
--- a/arch/alpha/include/asm/unistd.h
+++ b/arch/alpha/include/asm/unistd.h
@@ -247,6 +247,7 @@
 #define __IGNORE_pause
 #define __IGNORE_time
 #define __IGNORE_utime
+#define __IGNORE_umount2
 
 /*
  * Linux-specific system calls begin at 300
@@ -434,10 +435,24 @@
 #define __NR_timerfd                    477
 #define __NR_eventfd                    478
 #define __NR_recvmmsg                   479
+#define __NR_fallocate                  480
+#define __NR_timerfd_create             481
+#define __NR_timerfd_settime            482
+#define __NR_timerfd_gettime            483
+#define __NR_signalfd4                  484
+#define __NR_eventfd2                   485
+#define __NR_epoll_create1              486
+#define __NR_dup3                       487
+#define __NR_pipe2                      488
+#define __NR_inotify_init1              489
+#define __NR_preadv                     490
+#define __NR_pwritev                    491
+#define __NR_rt_tgsigqueueinfo          492
+#define __NR_perf_event_open            493
 
 #ifdef __KERNEL__
 
-#define NR_SYSCALLS                     480
+#define NR_SYSCALLS                     494
 
 #define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_OLD_READDIR
diff --git a/arch/alpha/kernel/systbls.S b/arch/alpha/kernel/systbls.S
index cda6b8b3d573..09acb786e72b 100644
--- a/arch/alpha/kernel/systbls.S
+++ b/arch/alpha/kernel/systbls.S
@@ -495,9 +495,23 @@ sys_call_table:
         .quad sys_epoll_pwait
         .quad sys_utimensat                     /* 475 */
         .quad sys_signalfd
-        .quad sys_ni_syscall
+        .quad sys_ni_syscall                    /* sys_timerfd */
         .quad sys_eventfd
         .quad sys_recvmmsg
+        .quad sys_fallocate                             /* 480 */
+        .quad sys_timerfd_create
+        .quad sys_timerfd_settime
+        .quad sys_timerfd_gettime
+        .quad sys_signalfd4
+        .quad sys_eventfd2                              /* 485 */
+        .quad sys_epoll_create1
+        .quad sys_dup3
+        .quad sys_pipe2
+        .quad sys_inotify_init1
+        .quad sys_preadv                                /* 490 */
+        .quad sys_pwritev
+        .quad sys_rt_tgsigqueueinfo
+        .quad sys_perf_event_open
 
         .size sys_call_table, . - sys_call_table
         .type sys_call_table, @object
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index fa0cdab2e1d3..e9da08483b3c 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -242,15 +242,8 @@ all:	$(KBUILD_IMAGE)
 
 boot := arch/arm/boot
 
-#       Update machine arch and proc symlinks if something which affects
-#       them changed.  We use .arch to indicate when they were updated
-#       last, otherwise make uses the target directory mtime.
-
-archprepare: maketools
-
-PHONY += maketools FORCE
-maketools: include/linux/version.h FORCE
-        $(Q)$(MAKE) $(build)=arch/arm/tools include/asm-arm/mach-types.h
+archprepare:
+        $(Q)$(MAKE) $(build)=arch/arm/tools include/generated/mach-types.h
 
 # Convert bzImage to zImage
 bzImage: zImage
@@ -261,9 +254,6 @@ zImage Image xipImage bootpImage uImage: vmlinux
 zinstall install: vmlinux
         $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $@
 
-CLEAN_FILES += include/asm-arm/mach-types.h \
-               include/asm-arm/arch include/asm-arm/.arch
-
 # We use MRPROPER_FILES and CLEAN_FILES now
 archclean:
         $(Q)$(MAKE) $(clean)=$(boot)
diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c
index 5a375e5fef21..bc90364a96c7 100644
--- a/arch/arm/common/dmabounce.c
+++ b/arch/arm/common/dmabounce.c
@@ -308,15 +308,11 @@ static inline void unmap_single(struct device *dev, dma_addr_t dma_addr,
                         memcpy(ptr, buf->safe, size);
 
                         /*
-                         * DMA buffers must have the same cache properties
-                         * as if they were really used for DMA - which means
-                         * data must be written back to RAM.  Note that
-                         * we don't use dmac_flush_range() here for the
-                         * bidirectional case because we know the cache
-                         * lines will be coherent with the data written.
+                         * Since we may have written to a page cache page,
+                         * we need to ensure that the data will be coherent
+                         * with user mappings.
                          */
-                        dmac_clean_range(ptr, ptr + size);
-                        outer_clean_range(__pa(ptr), __pa(ptr) + size);
+                        __cpuc_flush_kernel_dcache_area(ptr, size);
                 }
                 free_safe_buffer(dev->archdata.dmabounce, buf);
         }
diff --git a/arch/arm/include/asm/asm-offsets.h b/arch/arm/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/arm/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 73eceb87e588..730aefcfbee3 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -211,7 +211,7 @@ struct cpu_cache_fns {
 
         void (*coherent_kern_range)(unsigned long, unsigned long);
         void (*coherent_user_range)(unsigned long, unsigned long);
-        void (*flush_kern_dcache_page)(void *);
+        void (*flush_kern_dcache_area)(void *, size_t);
 
         void (*dma_inv_range)(const void *, const void *);
         void (*dma_clean_range)(const void *, const void *);
@@ -236,7 +236,7 @@ extern struct cpu_cache_fns cpu_cache;
 #define __cpuc_flush_user_range         cpu_cache.flush_user_range
 #define __cpuc_coherent_kern_range      cpu_cache.coherent_kern_range
 #define __cpuc_coherent_user_range      cpu_cache.coherent_user_range
-#define __cpuc_flush_dcache_page        cpu_cache.flush_kern_dcache_page
+#define __cpuc_flush_dcache_area        cpu_cache.flush_kern_dcache_area
 
 /*
  * These are private to the dma-mapping API.  Do not use directly.
@@ -255,14 +255,14 @@ extern struct cpu_cache_fns cpu_cache;
 #define __cpuc_flush_user_range         __glue(_CACHE,_flush_user_cache_range)
 #define __cpuc_coherent_kern_range      __glue(_CACHE,_coherent_kern_range)
 #define __cpuc_coherent_user_range      __glue(_CACHE,_coherent_user_range)
-#define __cpuc_flush_dcache_page        __glue(_CACHE,_flush_kern_dcache_page)
+#define __cpuc_flush_dcache_area        __glue(_CACHE,_flush_kern_dcache_area)
 
 extern void __cpuc_flush_kern_all(void);
 extern void __cpuc_flush_user_all(void);
 extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
 extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
 extern void __cpuc_coherent_user_range(unsigned long, unsigned long);
-extern void __cpuc_flush_dcache_page(void *);
+extern void __cpuc_flush_dcache_area(void *, size_t);
 
 /*
  * These are private to the dma-mapping API.  Do not use directly.
@@ -448,7 +448,7 @@ static inline void flush_kernel_dcache_page(struct page *page)
 {
         /* highmem pages are always flushed upon kunmap already */
         if ((cache_is_vivt() || cache_is_vipt_aliasing()) && !PageHighMem(page))
-                __cpuc_flush_dcache_page(page_address(page));
+                __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
 }
 
 #define flush_dcache_mmap_lock(mapping) \
@@ -465,13 +465,6 @@ static inline void flush_kernel_dcache_page(struct page *page)
  */
 #define flush_icache_page(vma,page)     do { } while (0)
 
-static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt,
-        unsigned offset, size_t size)
-{
-        const void *start = (void __force *)virt + offset;
-        dmac_inv_range(start, start + size);
-}
-
 /*
  * flush_cache_vmap() is used when creating mappings (eg, via vmap,
  * vmalloc, ioremap etc) in kernel space for pages.  On non-VIPT
diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
new file mode 100644
index 000000000000..948178cc6ba8
--- /dev/null
+++ b/arch/arm/include/asm/mach-types.h
@@ -0,0 +1 @@
+#include <generated/mach-types.h>
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 8bf09ae5b347..f6c6196a51fa 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -52,6 +52,12 @@ config MACH_OPENRD_BASE
           Say 'Y' here if you want your kernel to support the
           Marvell OpenRD Base Board.
 
+config MACH_NETSPACE_V2
+        bool "LaCie Network Space v2 NAS Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          LaCie Network Space v2 NAS.
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 9f2f67b2b63d..d4d7f53b0fb9 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -8,5 +8,6 @@ obj-$(CONFIG_MACH_SHEEVAPLUG)		+= sheevaplug-setup.o
 obj-$(CONFIG_MACH_TS219)                += ts219-setup.o tsx1x-common.o
 obj-$(CONFIG_MACH_TS41X)                += ts41x-setup.o tsx1x-common.o
 obj-$(CONFIG_MACH_OPENRD_BASE)          += openrd_base-setup.o
+obj-$(CONFIG_MACH_NETSPACE_V2)          += netspace_v2-setup.o
 
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c
new file mode 100644
index 000000000000..9a064065bebe
--- /dev/null
+++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c
@@ -0,0 +1,325 @@
+/*
+ * arch/arm/mach-kirkwood/netspace_v2-setup.c
+ *
+ * LaCie Network Space v2 board setup
+ *
+ * Copyright (C) 2009 Simon Guinot <sguinot@lacie.com>
+ * Copyright (C) 2009 Benoît Canet <benoit.canet@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/i2c.h>
+#include <linux/i2c/at24.h>
+#include <linux/input.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/leds.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/kirkwood.h>
+#include <plat/time.h>
+#include "common.h"
+#include "mpp.h"
+
+/*****************************************************************************
+ * 512KB SPI Flash on Boot Device (MACRONIX MX25L4005)
+ ****************************************************************************/
+
+static struct mtd_partition netspace_v2_flash_parts[] = {
+        {
+                .name = "u-boot",
+                .size = MTDPART_SIZ_FULL,
+                .offset = 0,
+                .mask_flags = MTD_WRITEABLE, /* force read-only */
+        },
+};
+
+static const struct flash_platform_data netspace_v2_flash = {
+        .type           = "mx25l4005a",
+        .name           = "spi_flash",
+        .parts          = netspace_v2_flash_parts,
+        .nr_parts       = ARRAY_SIZE(netspace_v2_flash_parts),
+};
+
+static struct spi_board_info __initdata netspace_v2_spi_slave_info[] = {
+        {
+                .modalias       = "m25p80",
+                .platform_data  = &netspace_v2_flash,
+                .irq            = -1,
+                .max_speed_hz   = 20000000,
+                .bus_num        = 0,
+                .chip_select    = 0,
+        },
+};
+
+/*****************************************************************************
+ * Ethernet
+ ****************************************************************************/
+
+static struct mv643xx_eth_platform_data netspace_v2_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
+};
+
+/*****************************************************************************
+ * I2C devices
+ ****************************************************************************/
+
+static struct at24_platform_data at24c04 = {
+        .byte_len       = SZ_4K / 8,
+        .page_size      = 16,
+};
+
+/*
+ * i2c addr | chip         | description
+ * 0x50     | HT24LC04     | eeprom (512B)
+ */
+
+static struct i2c_board_info __initdata netspace_v2_i2c_info[] = {
+        {
+                I2C_BOARD_INFO("24c04", 0x50),
+                .platform_data  = &at24c04,
+        }
+};
+
+/*****************************************************************************
+ * SATA
+ ****************************************************************************/
+
+static struct mv_sata_platform_data netspace_v2_sata_data = {
+        .n_ports        = 2,
+};
+
+#define NETSPACE_V2_GPIO_SATA0_POWER    16
+#define NETSPACE_V2_GPIO_SATA1_POWER    17
+
+static void __init netspace_v2_sata_power_init(void)
+{
+        int err;
+
+        err = gpio_request(NETSPACE_V2_GPIO_SATA0_POWER, "SATA0 power");
+        if (err == 0) {
+                err = gpio_direction_output(NETSPACE_V2_GPIO_SATA0_POWER, 1);
+                if (err)
+                        gpio_free(NETSPACE_V2_GPIO_SATA0_POWER);
+        }
+        if (err)
+                pr_err("netspace_v2: failed to setup SATA0 power\n");
+}
+
+/*****************************************************************************
+ * GPIO keys
+ ****************************************************************************/
+
+#define NETSPACE_V2_PUSH_BUTTON         32
+
+static struct gpio_keys_button netspace_v2_buttons[] = {
+        [0] = {
+                .code           = KEY_POWER,
+                .gpio           = NETSPACE_V2_PUSH_BUTTON,
+                .desc           = "Power push button",
+                .active_low     = 0,
+        },
+};
+
+static struct gpio_keys_platform_data netspace_v2_button_data = {
+        .buttons        = netspace_v2_buttons,
+        .nbuttons       = ARRAY_SIZE(netspace_v2_buttons),
+};
+
+static struct platform_device netspace_v2_gpio_buttons = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &netspace_v2_button_data,
+        },
+};
+
+/*****************************************************************************
+ * GPIO LEDs
+ ****************************************************************************/
+
+/*
+ * The blue front LED is wired to a CPLD and can blink in relation with the
+ * SATA activity.
+ *
+ * The following array detail the different LED registers and the combination
+ * of their possible values:
+ *
+ *  cmd_led   |  slow_led  | /SATA active | LED state
+ *            |            |              |
+ *     1      |     0      |      x       |  off
+ *     -      |     1      |      x       |  on
+ *     0      |     0      |      1       |  on
+ *     0      |     0      |      0       |  blink (rate 300ms)
+ */
+
+#define NETSPACE_V2_GPIO_RED_LED        12
+#define NETSPACE_V2_GPIO_BLUE_LED_SLOW  29
+#define NETSPACE_V2_GPIO_BLUE_LED_CMD   30
+
+
+static struct gpio_led netspace_v2_gpio_led_pins[] = {
+        {
+                .name   = "ns_v2:red:fail",
+                .gpio   = NETSPACE_V2_GPIO_RED_LED,
+        },
+};
+
+static struct gpio_led_platform_data netspace_v2_gpio_leds_data = {
+        .num_leds       = ARRAY_SIZE(netspace_v2_gpio_led_pins),
+        .leds           = netspace_v2_gpio_led_pins,
+};
+
+static struct platform_device netspace_v2_gpio_leds = {
+        .name           = "leds-gpio",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &netspace_v2_gpio_leds_data,
+        },
+};
+
+static void __init netspace_v2_gpio_leds_init(void)
+{
+        platform_device_register(&netspace_v2_gpio_leds);
+
+        /*
+         * Configure the front blue LED to blink in relation with the SATA
+         * activity.
+         */
+        if (gpio_request(NETSPACE_V2_GPIO_BLUE_LED_SLOW,
+                         "SATA blue LED slow") != 0)
+                return;
+        if (gpio_direction_output(NETSPACE_V2_GPIO_BLUE_LED_SLOW, 0) != 0)
+                goto err_free_1;
+        if (gpio_request(NETSPACE_V2_GPIO_BLUE_LED_CMD,
+                         "SATA blue LED command") != 0)
+                goto err_free_1;
+        if (gpio_direction_output(NETSPACE_V2_GPIO_BLUE_LED_CMD, 0) != 0)
+                goto err_free_2;
+
+        return;
+
+err_free_2:
+        gpio_free(NETSPACE_V2_GPIO_BLUE_LED_CMD);
+err_free_1:
+        gpio_free(NETSPACE_V2_GPIO_BLUE_LED_SLOW);
+        pr_err("netspace_v2: failed to configure SATA blue LED\n");
+}
+
+/*****************************************************************************
+ * Timer
+ ****************************************************************************/
+
+static void netspace_v2_timer_init(void)
+{
+        kirkwood_tclk = 166666667;
+        orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
+}
+
+struct sys_timer netspace_v2_timer = {
+        .init = netspace_v2_timer_init,
+};
+
+/*****************************************************************************
+ * General Setup
+ ****************************************************************************/
+
+static unsigned int netspace_v2_mpp_config[] __initdata = {
+        MPP0_SPI_SCn,
+        MPP1_SPI_MOSI,
+        MPP2_SPI_SCK,
+        MPP3_SPI_MISO,
+        MPP4_NF_IO6,
+        MPP5_NF_IO7,
+        MPP6_SYSRST_OUTn,
+        MPP8_TW_SDA,
+        MPP9_TW_SCK,
+        MPP10_UART0_TXD,
+        MPP11_UART0_RXD,
+        MPP12_GPO,              /* Red led */
+        MPP14_GPIO,             /* USB fuse */
+        MPP16_GPIO,             /* SATA 0 power */
+        MPP18_NF_IO0,
+        MPP19_NF_IO1,
+        MPP20_SATA1_ACTn,
+        MPP21_SATA0_ACTn,
+        MPP24_GPIO,             /* USB mode select */
+        MPP25_GPIO,             /* Fan rotation fail */
+        MPP26_GPIO,             /* USB device vbus */
+        MPP28_GPIO,             /* USB enable host vbus */
+        MPP29_GPIO,             /* Blue led (slow register) */
+        MPP30_GPIO,             /* Blue led (command register) */
+        MPP31_GPIO,             /* Board power off */
+        MPP32_GPIO,             /* Power button (0 = Released, 1 = Pushed) */
+        0
+};
+
+#define NETSPACE_V2_GPIO_POWER_OFF      31
+
+static void netspace_v2_power_off(void)
+{
+        gpio_set_value(NETSPACE_V2_GPIO_POWER_OFF, 1);
+}
+
+static void __init netspace_v2_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_init();
+        kirkwood_mpp_conf(netspace_v2_mpp_config);
+
+        netspace_v2_sata_power_init();
+
+        kirkwood_ehci_init();
+        kirkwood_ge00_init(&netspace_v2_ge00_data);
+        kirkwood_sata_init(&netspace_v2_sata_data);
+        kirkwood_uart0_init();
+        spi_register_board_info(netspace_v2_spi_slave_info,
+                                ARRAY_SIZE(netspace_v2_spi_slave_info));
+        kirkwood_spi_init();
+        kirkwood_i2c_init();
+        i2c_register_board_info(0, netspace_v2_i2c_info,
+                                ARRAY_SIZE(netspace_v2_i2c_info));
+
+        netspace_v2_gpio_leds_init();
+        platform_device_register(&netspace_v2_gpio_buttons);
+
+        if (gpio_request(NETSPACE_V2_GPIO_POWER_OFF, "power-off") == 0 &&
+            gpio_direction_output(NETSPACE_V2_GPIO_POWER_OFF, 0) == 0)
+                pm_power_off = netspace_v2_power_off;
+        else
+                pr_err("netspace_v2: failed to configure power-off GPIO\n");
+}
+
+MACHINE_START(NETSPACE_V2, "LaCie Network Space v2")
+        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
+        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = netspace_v2_init,
+        .map_io         = kirkwood_map_io,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &netspace_v2_timer,
+MACHINE_END
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 76c11ee113e9..10eafa70a909 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -18,6 +18,7 @@ config ARCH_OMAP2430
 config ARCH_OMAP34XX
         bool "OMAP34xx Based System"
         depends on ARCH_OMAP3
+        select USB_ARCH_HAS_EHCI
 
 config ARCH_OMAP3430
         bool "OMAP3430 support"
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 1591aae64500..2626a9f8a73a 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -29,7 +29,7 @@
 #include <linux/gpio.h>
 
 #include <linux/i2c/at24.h>
-#include <linux/i2c/twl4030.h>
+#include <linux/i2c/twl.h>
 #include <linux/regulator/machine.h>
 
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 44239e3ec02e..117b8fd7e3a6 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -19,7 +19,7 @@
 #include <linux/interrupt.h>
 
 #include <linux/regulator/machine.h>
-#include <linux/i2c/twl4030.h>
+#include <linux/i2c/twl.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 18913e96e34d..34de17851572 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -26,7 +26,7 @@
 
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
-#include <linux/i2c/twl4030.h>
+#include <linux/i2c/twl.h>
 #include <linux/usb/otg.h>
 #include <linux/smsc911x.h>
 
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index c9e5ebb4d91d..fe3d22cb2457 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -34,7 +34,7 @@
 #include <linux/spi/ads7846.h>
 
 #include <linux/regulator/machine.h>
-#include <linux/i2c/twl4030.h>
+#include <linux/i2c/twl.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 17f3c91231db..acafdbc8aa16 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -16,7 +16,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/wl12xx.h>
 #include <linux/i2c.h>
-#include <linux/i2c/twl4030.h>
+#include <linux/i2c/twl.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/regulator/machine.h>
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index 258794db488f..8dd277c36661 100755
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -14,7 +14,7 @@
 #include <linux/input.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/gpio.h>
-#include <linux/i2c/twl4030.h>
+#include <linux/i2c/twl.h>
 #include <linux/regulator/machine.h>
 
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 39b797bc14d6..19805a7de06c 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -640,12 +640,9 @@ void __init omap_serial_early_init(void)
                 uart->num = i;
                 p->private_data = uart;
                 uart->p = p;
-                list_add_tail(&uart->node, &uart_list);
 
                 if (cpu_is_omap44xx())
                         p->irq += 32;
-
-                omap_uart_enable_clocks(uart);
         }
 }
 
@@ -673,9 +670,13 @@ void __init omap_serial_init_port(int port)
         pdev = &uart->pdev;
         dev = &pdev->dev;
 
+        omap_uart_enable_clocks(uart);
+
         omap_uart_reset(uart);
         omap_uart_idle_init(uart);
 
+        list_add_tail(&uart->node, &uart_list);
+
         if (WARN_ON(platform_device_register(pdev)))
                 return;
 
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index e6d8e10ae5d1..8a0837ea0294 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -110,6 +110,8 @@ config MACH_CM_X300
         bool "CompuLab CM-X300 modules"
         select PXA3xx
         select CPU_PXA300
+        select CPU_PXA310
+        select HAVE_PWM
 
 config ARCH_GUMSTIX
         bool "Gumstix XScale 255 boards"
@@ -240,7 +242,6 @@ config MACH_COLIBRI300
         select PXA3xx
         select CPU_PXA300
         select CPU_PXA310
-        select HAVE_PWM
 
 config MACH_COLIBRI320
         bool "Toradex Colibri PXA320"
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index 3395463bb5a6..8e10db148f1b 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -4,7 +4,6 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 
-#include <mach/hardware.h>
 #include <mach/udc.h>
 #include <mach/pxafb.h>
 #include <mach/mmc.h>
@@ -14,6 +13,7 @@
 #include <mach/pxa2xx_spi.h>
 #include <mach/camera.h>
 #include <mach/audio.h>
+#include <mach/hardware.h>
 #include <plat/i2c.h>
 #include <plat/pxa3xx_nand.h>
 
diff --git a/arch/arm/mach-s3c2410/include/mach/spi.h b/arch/arm/mach-s3c2410/include/mach/spi.h
index 193b39d654ed..4d9588373aa5 100644
--- a/arch/arm/mach-s3c2410/include/mach/spi.h
+++ b/arch/arm/mach-s3c2410/include/mach/spi.h
@@ -18,6 +18,8 @@ struct s3c2410_spi_info {
         unsigned int             num_cs;        /* total chipselects */
         int                      bus_num;       /* bus number to use. */
 
+        unsigned int             use_fiq:1;     /* use fiq */
+
         void (*gpio_setup)(struct s3c2410_spi_info *spi, int enable);
         void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol);
 };
diff --git a/arch/arm/mm/cache-fa.S b/arch/arm/mm/cache-fa.S
index b63a8f7b95cf..a89444a3c016 100644
--- a/arch/arm/mm/cache-fa.S
+++ b/arch/arm/mm/cache-fa.S
@@ -127,15 +127,16 @@ ENTRY(fa_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(kaddr)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure that the data held in the page kaddr is written back
  *      to the page in question.
  *
- *      - kaddr   - kernel address (guaranteed to be page aligned)
+ *      - addr  - kernel address
+ *      - size  - size of region
  */
-ENTRY(fa_flush_kern_dcache_page)
-        add     r1, r0, #PAGE_SZ
+ENTRY(fa_flush_kern_dcache_area)
+        add     r1, r0, r1
 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean & invalidate D line
         add     r0, r0, #CACHE_DLINESIZE
         cmp     r0, r1
@@ -213,7 +214,7 @@ ENTRY(fa_cache_fns)
         .long   fa_flush_user_cache_range
         .long   fa_coherent_kern_range
         .long   fa_coherent_user_range
-        .long   fa_flush_kern_dcache_page
+        .long   fa_flush_kern_dcache_area
         .long   fa_dma_inv_range
         .long   fa_dma_clean_range
         .long   fa_dma_flush_range
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 747f9a9021bb..cb8fc6573b1b 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -28,69 +28,120 @@
 static void __iomem *l2x0_base;
 static DEFINE_SPINLOCK(l2x0_lock);
 
-static inline void sync_writel(unsigned long val, unsigned long reg,
-                               unsigned long complete_mask)
+static inline void cache_wait(void __iomem *reg, unsigned long mask)
 {
-        unsigned long flags;
-
-        spin_lock_irqsave(&l2x0_lock, flags);
-        writel(val, l2x0_base + reg);
         /* wait for the operation to complete */
-        while (readl(l2x0_base + reg) & complete_mask)
+        while (readl(reg) & mask)
                 ;
-        spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
 static inline void cache_sync(void)
 {
-        sync_writel(0, L2X0_CACHE_SYNC, 1);
+        void __iomem *base = l2x0_base;
+        writel(0, base + L2X0_CACHE_SYNC);
+        cache_wait(base + L2X0_CACHE_SYNC, 1);
 }
 
 static inline void l2x0_inv_all(void)
 {
+        unsigned long flags;
+
         /* invalidate all ways */
-        sync_writel(0xff, L2X0_INV_WAY, 0xff);
+        spin_lock_irqsave(&l2x0_lock, flags);
+        writel(0xff, l2x0_base + L2X0_INV_WAY);
+        cache_wait(l2x0_base + L2X0_INV_WAY, 0xff);
         cache_sync();
+        spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
 static void l2x0_inv_range(unsigned long start, unsigned long end)
 {
-        unsigned long addr;
+        void __iomem *base = l2x0_base;
+        unsigned long flags;
 
+        spin_lock_irqsave(&l2x0_lock, flags);
         if (start & (CACHE_LINE_SIZE - 1)) {
                 start &= ~(CACHE_LINE_SIZE - 1);
-                sync_writel(start, L2X0_CLEAN_INV_LINE_PA, 1);
+                cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
+                writel(start, base + L2X0_CLEAN_INV_LINE_PA);
                 start += CACHE_LINE_SIZE;
         }
 
         if (end & (CACHE_LINE_SIZE - 1)) {
                 end &= ~(CACHE_LINE_SIZE - 1);
-                sync_writel(end, L2X0_CLEAN_INV_LINE_PA, 1);
+                cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
+                writel(end, base + L2X0_CLEAN_INV_LINE_PA);
         }
 
-        for (addr = start; addr < end; addr += CACHE_LINE_SIZE)
-                sync_writel(addr, L2X0_INV_LINE_PA, 1);
+        while (start < end) {
+                unsigned long blk_end = start + min(end - start, 4096UL);
+
+                while (start < blk_end) {
+                        cache_wait(base + L2X0_INV_LINE_PA, 1);
+                        writel(start, base + L2X0_INV_LINE_PA);
+                        start += CACHE_LINE_SIZE;
+                }
+
+                if (blk_end < end) {
+                        spin_unlock_irqrestore(&l2x0_lock, flags);
+                        spin_lock_irqsave(&l2x0_lock, flags);
+                }
+        }
+        cache_wait(base + L2X0_INV_LINE_PA, 1);
         cache_sync();
+        spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
 static void l2x0_clean_range(unsigned long start, unsigned long end)
 {
-        unsigned long addr;
+        void __iomem *base = l2x0_base;
+        unsigned long flags;
 
+        spin_lock_irqsave(&l2x0_lock, flags);
         start &= ~(CACHE_LINE_SIZE - 1);
-        for (addr = start; addr < end; addr += CACHE_LINE_SIZE)
-                sync_writel(addr, L2X0_CLEAN_LINE_PA, 1);
+        while (start < end) {
+                unsigned long blk_end = start + min(end - start, 4096UL);
+
+                while (start < blk_end) {
+                        cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
+                        writel(start, base + L2X0_CLEAN_LINE_PA);
+                        start += CACHE_LINE_SIZE;
+                }
+
+                if (blk_end < end) {
+                        spin_unlock_irqrestore(&l2x0_lock, flags);
+                        spin_lock_irqsave(&l2x0_lock, flags);
+                }
+        }
+        cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
         cache_sync();
+        spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
 static void l2x0_flush_range(unsigned long start, unsigned long end)
 {
-        unsigned long addr;
+        void __iomem *base = l2x0_base;
+        unsigned long flags;
 
+        spin_lock_irqsave(&l2x0_lock, flags);
         start &= ~(CACHE_LINE_SIZE - 1);
-        for (addr = start; addr < end; addr += CACHE_LINE_SIZE)
-                sync_writel(addr, L2X0_CLEAN_INV_LINE_PA, 1);
+        while (start < end) {
+                unsigned long blk_end = start + min(end - start, 4096UL);
+
+                while (start < blk_end) {
+                        cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
+                        writel(start, base + L2X0_CLEAN_INV_LINE_PA);
+                        start += CACHE_LINE_SIZE;
+                }
+
+                if (blk_end < end) {
+                        spin_unlock_irqrestore(&l2x0_lock, flags);
+                        spin_lock_irqsave(&l2x0_lock, flags);
+                }
+        }
+        cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
         cache_sync();
+        spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
 void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
diff --git a/arch/arm/mm/cache-v3.S b/arch/arm/mm/cache-v3.S
index 8a4abebc478a..2a482731ea36 100644
--- a/arch/arm/mm/cache-v3.S
+++ b/arch/arm/mm/cache-v3.S
@@ -72,14 +72,15 @@ ENTRY(v3_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *page, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - addr  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(v3_flush_kern_dcache_page)
+ENTRY(v3_flush_kern_dcache_area)
         /* FALLTHROUGH */
 
 /*
@@ -129,7 +130,7 @@ ENTRY(v3_cache_fns)
         .long   v3_flush_user_cache_range
         .long   v3_coherent_kern_range
         .long   v3_coherent_user_range
-        .long   v3_flush_kern_dcache_page
+        .long   v3_flush_kern_dcache_area
         .long   v3_dma_inv_range
         .long   v3_dma_clean_range
         .long   v3_dma_flush_range
diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S
index 3668611cb400..5c7da3e372e9 100644
--- a/arch/arm/mm/cache-v4.S
+++ b/arch/arm/mm/cache-v4.S
@@ -82,14 +82,15 @@ ENTRY(v4_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - addr  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(v4_flush_kern_dcache_page)
+ENTRY(v4_flush_kern_dcache_area)
         /* FALLTHROUGH */
 
 /*
@@ -141,7 +142,7 @@ ENTRY(v4_cache_fns)
         .long   v4_flush_user_cache_range
         .long   v4_coherent_kern_range
         .long   v4_coherent_user_range
-        .long   v4_flush_kern_dcache_page
+        .long   v4_flush_kern_dcache_area
         .long   v4_dma_inv_range
         .long   v4_dma_clean_range
         .long   v4_dma_flush_range
diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S
index 2ebc1b3bf856..3dbedf1ec0e7 100644
--- a/arch/arm/mm/cache-v4wb.S
+++ b/arch/arm/mm/cache-v4wb.S
@@ -114,15 +114,16 @@ ENTRY(v4wb_flush_user_cache_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - addr  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(v4wb_flush_kern_dcache_page)
-        add     r1, r0, #PAGE_SZ
+ENTRY(v4wb_flush_kern_dcache_area)
+        add     r1, r0, r1
         /* fall through */
 
 /*
@@ -224,7 +225,7 @@ ENTRY(v4wb_cache_fns)
         .long   v4wb_flush_user_cache_range
         .long   v4wb_coherent_kern_range
         .long   v4wb_coherent_user_range
-        .long   v4wb_flush_kern_dcache_page
+        .long   v4wb_flush_kern_dcache_area
         .long   v4wb_dma_inv_range
         .long   v4wb_dma_clean_range
         .long   v4wb_dma_flush_range
diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S
index c54fa2cc40e6..b3b7410270b4 100644
--- a/arch/arm/mm/cache-v4wt.S
+++ b/arch/arm/mm/cache-v4wt.S
@@ -117,17 +117,18 @@ ENTRY(v4wt_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - addr  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(v4wt_flush_kern_dcache_page)
+ENTRY(v4wt_flush_kern_dcache_area)
         mov     r2, #0
         mcr     p15, 0, r2, c7, c5, 0           @ invalidate I cache
-        add     r1, r0, #PAGE_SZ
+        add     r1, r0, r1
         /* fallthrough */
 
 /*
@@ -180,7 +181,7 @@ ENTRY(v4wt_cache_fns)
         .long   v4wt_flush_user_cache_range
         .long   v4wt_coherent_kern_range
         .long   v4wt_coherent_user_range
-        .long   v4wt_flush_kern_dcache_page
+        .long   v4wt_flush_kern_dcache_area
         .long   v4wt_dma_inv_range
         .long   v4wt_dma_clean_range
         .long   v4wt_dma_flush_range
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 295e25dd6381..4ba0a24ce6f5 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -159,15 +159,16 @@ ENDPROC(v6_coherent_user_range)
 ENDPROC(v6_coherent_kern_range)
 
 /*
- *      v6_flush_kern_dcache_page(kaddr)
+ *      v6_flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure that the data held in the page kaddr is written back
  *      to the page in question.
  *
- *      - kaddr   - kernel address (guaranteed to be page aligned)
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(v6_flush_kern_dcache_page)
-        add     r1, r0, #PAGE_SZ
+ENTRY(v6_flush_kern_dcache_area)
+        add     r1, r0, r1
 1:
 #ifdef HARVARD_CACHE
         mcr     p15, 0, r0, c7, c14, 1          @ clean & invalidate D line
@@ -271,7 +272,7 @@ ENTRY(v6_cache_fns)
         .long   v6_flush_user_cache_range
         .long   v6_coherent_kern_range
         .long   v6_coherent_user_range
-        .long   v6_flush_kern_dcache_page
+        .long   v6_flush_kern_dcache_area
         .long   v6_dma_inv_range
         .long   v6_dma_clean_range
         .long   v6_dma_flush_range
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index e1bd9759617f..9073db849fb4 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -186,16 +186,17 @@ ENDPROC(v7_coherent_kern_range)
 ENDPROC(v7_coherent_user_range)
 
 /*
- *      v7_flush_kern_dcache_page(kaddr)
+ *      v7_flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure that the data held in the page kaddr is written back
  *      to the page in question.
  *
- *      - kaddr   - kernel address (guaranteed to be page aligned)
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(v7_flush_kern_dcache_page)
+ENTRY(v7_flush_kern_dcache_area)
         dcache_line_size r2, r3
-        add     r1, r0, #PAGE_SZ
+        add     r1, r0, r1
 1:
         mcr     p15, 0, r0, c7, c14, 1          @ clean & invalidate D line / unified line
         add     r0, r0, r2
@@ -203,7 +204,7 @@ ENTRY(v7_flush_kern_dcache_page)
         blo     1b
         dsb
         mov     pc, lr
-ENDPROC(v7_flush_kern_dcache_page)
+ENDPROC(v7_flush_kern_dcache_area)
 
 /*
  *      v7_dma_inv_range(start,end)
@@ -279,7 +280,7 @@ ENTRY(v7_cache_fns)
         .long   v7_flush_user_cache_range
         .long   v7_coherent_kern_range
         .long   v7_coherent_user_range
-        .long   v7_flush_kern_dcache_page
+        .long   v7_flush_kern_dcache_area
         .long   v7_dma_inv_range
         .long   v7_dma_clean_range
         .long   v7_dma_flush_range
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 329594e760cd..6f3a4b7a3b82 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -131,7 +131,7 @@ void __flush_dcache_page(struct address_space *mapping, struct page *page)
          */
         if (addr)
 #endif
-                __cpuc_flush_dcache_page(addr);
+                __cpuc_flush_dcache_area(addr, PAGE_SIZE);
 
         /*
          * If this is a page cache page, and we have an aliasing VIPT cache,
@@ -258,5 +258,5 @@ void __flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned l
          * in this mapping of the page.  FIXME: this is overkill
          * since we actually ask for a write-back and invalidate.
          */
-        __cpuc_flush_dcache_page(page_address(page));
+        __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
 }
diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c
index 30f82fb5918c..2be1ec7c1b41 100644
--- a/arch/arm/mm/highmem.c
+++ b/arch/arm/mm/highmem.c
@@ -79,7 +79,7 @@ void kunmap_atomic(void *kvaddr, enum km_type type)
         unsigned int idx = type + KM_TYPE_NR * smp_processor_id();
 
         if (kvaddr >= (void *)FIXADDR_START) {
-                __cpuc_flush_dcache_page((void *)vaddr);
+                __cpuc_flush_dcache_area((void *)vaddr, PAGE_SIZE);
 #ifdef CONFIG_DEBUG_HIGHMEM
                 BUG_ON(vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx));
                 set_pte_ext(TOP_PTE(vaddr), __pte(0), 0);
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index 900811cc9130..374a8311bc84 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -61,7 +61,7 @@ void setup_mm_for_reboot(char mode)
 
 void flush_dcache_page(struct page *page)
 {
-        __cpuc_flush_dcache_page(page_address(page));
+        __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
 }
 EXPORT_SYMBOL(flush_dcache_page);
 
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index d9fb4b98c49f..8012e24282b2 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -231,17 +231,18 @@ ENTRY(arm1020_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - page  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(arm1020_flush_kern_dcache_page)
+ENTRY(arm1020_flush_kern_dcache_area)
         mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
-        add     r1, r0, #PAGE_SZ
+        add     r1, r0, r1
 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
         add     r0, r0, #CACHE_DLINESIZE
@@ -335,7 +336,7 @@ ENTRY(arm1020_cache_fns)
         .long   arm1020_flush_user_cache_range
         .long   arm1020_coherent_kern_range
         .long   arm1020_coherent_user_range
-        .long   arm1020_flush_kern_dcache_page
+        .long   arm1020_flush_kern_dcache_area
         .long   arm1020_dma_inv_range
         .long   arm1020_dma_clean_range
         .long   arm1020_dma_flush_range
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 7453b75dcea5..41fe25d234f5 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -225,17 +225,18 @@ ENTRY(arm1020e_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - page  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(arm1020e_flush_kern_dcache_page)
+ENTRY(arm1020e_flush_kern_dcache_area)
         mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
-        add     r1, r0, #PAGE_SZ
+        add     r1, r0, r1
 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
         add     r0, r0, #CACHE_DLINESIZE
         cmp     r0, r1
@@ -321,7 +322,7 @@ ENTRY(arm1020e_cache_fns)
         .long   arm1020e_flush_user_cache_range
         .long   arm1020e_coherent_kern_range
         .long   arm1020e_coherent_user_range
-        .long   arm1020e_flush_kern_dcache_page
+        .long   arm1020e_flush_kern_dcache_area
         .long   arm1020e_dma_inv_range
         .long   arm1020e_dma_clean_range
         .long   arm1020e_dma_flush_range
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index 8eb72d75a8b6..20a5b1b31a70 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -214,17 +214,18 @@ ENTRY(arm1022_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - page  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(arm1022_flush_kern_dcache_page)
+ENTRY(arm1022_flush_kern_dcache_area)
         mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
-        add     r1, r0, #PAGE_SZ
+        add     r1, r0, r1
 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
         add     r0, r0, #CACHE_DLINESIZE
         cmp     r0, r1
@@ -310,7 +311,7 @@ ENTRY(arm1022_cache_fns)
         .long   arm1022_flush_user_cache_range
         .long   arm1022_coherent_kern_range
         .long   arm1022_coherent_user_range
-        .long   arm1022_flush_kern_dcache_page
+        .long   arm1022_flush_kern_dcache_area
         .long   arm1022_dma_inv_range
         .long   arm1022_dma_clean_range
         .long   arm1022_dma_flush_range
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 3b59f0d67139..96aedb10fcc4 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -208,17 +208,18 @@ ENTRY(arm1026_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - page  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(arm1026_flush_kern_dcache_page)
+ENTRY(arm1026_flush_kern_dcache_area)
         mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
-        add     r1, r0, #PAGE_SZ
+        add     r1, r0, r1
 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
         add     r0, r0, #CACHE_DLINESIZE
         cmp     r0, r1
@@ -304,7 +305,7 @@ ENTRY(arm1026_cache_fns)
         .long   arm1026_flush_user_cache_range
         .long   arm1026_coherent_kern_range
         .long   arm1026_coherent_user_range
-        .long   arm1026_flush_kern_dcache_page
+        .long   arm1026_flush_kern_dcache_area
         .long   arm1026_dma_inv_range
         .long   arm1026_dma_clean_range
         .long   arm1026_dma_flush_range
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 2b7c197cc58d..471669e2d7cb 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -207,15 +207,16 @@ ENTRY(arm920_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - addr  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(arm920_flush_kern_dcache_page)
-        add     r1, r0, #PAGE_SZ
+ENTRY(arm920_flush_kern_dcache_area)
+        add     r1, r0, r1
 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
         add     r0, r0, #CACHE_DLINESIZE
         cmp     r0, r1
@@ -293,7 +294,7 @@ ENTRY(arm920_cache_fns)
         .long   arm920_flush_user_cache_range
         .long   arm920_coherent_kern_range
         .long   arm920_coherent_user_range
-        .long   arm920_flush_kern_dcache_page
+        .long   arm920_flush_kern_dcache_area
         .long   arm920_dma_inv_range
         .long   arm920_dma_clean_range
         .long   arm920_dma_flush_range
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index 06a1aa4e3398..ee111b00fa41 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -209,15 +209,16 @@ ENTRY(arm922_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - addr  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(arm922_flush_kern_dcache_page)
-        add     r1, r0, #PAGE_SZ
+ENTRY(arm922_flush_kern_dcache_area)
+        add     r1, r0, r1
 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
         add     r0, r0, #CACHE_DLINESIZE
         cmp     r0, r1
@@ -295,7 +296,7 @@ ENTRY(arm922_cache_fns)
         .long   arm922_flush_user_cache_range
         .long   arm922_coherent_kern_range
         .long   arm922_coherent_user_range
-        .long   arm922_flush_kern_dcache_page
+        .long   arm922_flush_kern_dcache_area
         .long   arm922_dma_inv_range
         .long   arm922_dma_clean_range
         .long   arm922_dma_flush_range
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index cb53435a85ae..8deb5bde58e4 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -251,15 +251,16 @@ ENTRY(arm925_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - addr  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(arm925_flush_kern_dcache_page)
-        add     r1, r0, #PAGE_SZ
+ENTRY(arm925_flush_kern_dcache_area)
+        add     r1, r0, r1
 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
         add     r0, r0, #CACHE_DLINESIZE
         cmp     r0, r1
@@ -346,7 +347,7 @@ ENTRY(arm925_cache_fns)
         .long   arm925_flush_user_cache_range
         .long   arm925_coherent_kern_range
         .long   arm925_coherent_user_range
-        .long   arm925_flush_kern_dcache_page
+        .long   arm925_flush_kern_dcache_area
         .long   arm925_dma_inv_range
         .long   arm925_dma_clean_range
         .long   arm925_dma_flush_range
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 1c4848704bb3..64db6e275a44 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -214,15 +214,16 @@ ENTRY(arm926_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - addr  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(arm926_flush_kern_dcache_page)
-        add     r1, r0, #PAGE_SZ
+ENTRY(arm926_flush_kern_dcache_area)
+        add     r1, r0, r1
 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
         add     r0, r0, #CACHE_DLINESIZE
         cmp     r0, r1
@@ -309,7 +310,7 @@ ENTRY(arm926_cache_fns)
         .long   arm926_flush_user_cache_range
         .long   arm926_coherent_kern_range
         .long   arm926_coherent_user_range
-        .long   arm926_flush_kern_dcache_page
+        .long   arm926_flush_kern_dcache_area
         .long   arm926_dma_inv_range
         .long   arm926_dma_clean_range
         .long   arm926_dma_flush_range
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index 5b0f8464c8f2..8196b9f401fb 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -141,14 +141,15 @@ ENTRY(arm940_coherent_user_range)
         /* FALLTHROUGH */
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - addr  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(arm940_flush_kern_dcache_page)
+ENTRY(arm940_flush_kern_dcache_area)
         mov     ip, #0
         mov     r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
 1:      orr     r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
@@ -238,7 +239,7 @@ ENTRY(arm940_cache_fns)
         .long   arm940_flush_user_cache_range
         .long   arm940_coherent_kern_range
         .long   arm940_coherent_user_range
-        .long   arm940_flush_kern_dcache_page
+        .long   arm940_flush_kern_dcache_area
         .long   arm940_dma_inv_range
         .long   arm940_dma_clean_range
         .long   arm940_dma_flush_range
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index 40c0449a139b..9a951239c86c 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -183,16 +183,17 @@ ENTRY(arm946_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - addr  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  * (same as arm926)
  */
-ENTRY(arm946_flush_kern_dcache_page)
-        add     r1, r0, #PAGE_SZ
+ENTRY(arm946_flush_kern_dcache_area)
+        add     r1, r0, r1
 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
         add     r0, r0, #CACHE_DLINESIZE
         cmp     r0, r1
@@ -280,7 +281,7 @@ ENTRY(arm946_cache_fns)
         .long   arm946_flush_user_cache_range
         .long   arm946_coherent_kern_range
         .long   arm946_coherent_user_range
-        .long   arm946_flush_kern_dcache_page
+        .long   arm946_flush_kern_dcache_area
         .long   arm946_dma_inv_range
         .long   arm946_dma_clean_range
         .long   arm946_dma_flush_range
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index d0d7795200fc..dbc39383e66a 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -226,16 +226,17 @@ ENTRY(feroceon_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - addr  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
         .align  5
-ENTRY(feroceon_flush_kern_dcache_page)
-        add     r1, r0, #PAGE_SZ
+ENTRY(feroceon_flush_kern_dcache_area)
+        add     r1, r0, r1
 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
         add     r0, r0, #CACHE_DLINESIZE
         cmp     r0, r1
@@ -246,7 +247,7 @@ ENTRY(feroceon_flush_kern_dcache_page)
         mov     pc, lr
 
         .align  5
-ENTRY(feroceon_range_flush_kern_dcache_page)
+ENTRY(feroceon_range_flush_kern_dcache_area)
         mrs     r2, cpsr
         add     r1, r0, #PAGE_SZ - CACHE_DLINESIZE      @ top addr is inclusive
         orr     r3, r2, #PSR_I_BIT
@@ -372,7 +373,7 @@ ENTRY(feroceon_cache_fns)
         .long   feroceon_flush_user_cache_range
         .long   feroceon_coherent_kern_range
         .long   feroceon_coherent_user_range
-        .long   feroceon_flush_kern_dcache_page
+        .long   feroceon_flush_kern_dcache_area
         .long   feroceon_dma_inv_range
         .long   feroceon_dma_clean_range
         .long   feroceon_dma_flush_range
@@ -383,7 +384,7 @@ ENTRY(feroceon_range_cache_fns)
         .long   feroceon_flush_user_cache_range
         .long   feroceon_coherent_kern_range
         .long   feroceon_coherent_user_range
-        .long   feroceon_range_flush_kern_dcache_page
+        .long   feroceon_range_flush_kern_dcache_area
         .long   feroceon_range_dma_inv_range
         .long   feroceon_range_dma_clean_range
         .long   feroceon_range_dma_flush_range
diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S
index 52b5fd74fbb3..9674d36cc97d 100644
--- a/arch/arm/mm/proc-mohawk.S
+++ b/arch/arm/mm/proc-mohawk.S
@@ -186,15 +186,16 @@ ENTRY(mohawk_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - addr  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(mohawk_flush_kern_dcache_page)
-        add     r1, r0, #PAGE_SZ
+ENTRY(mohawk_flush_kern_dcache_area)
+        add     r1, r0, r1
 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
         add     r0, r0, #CACHE_DLINESIZE
         cmp     r0, r1
@@ -273,7 +274,7 @@ ENTRY(mohawk_cache_fns)
         .long   mohawk_flush_user_cache_range
         .long   mohawk_coherent_kern_range
         .long   mohawk_coherent_user_range
-        .long   mohawk_flush_kern_dcache_page
+        .long   mohawk_flush_kern_dcache_area
         .long   mohawk_dma_inv_range
         .long   mohawk_dma_clean_range
         .long   mohawk_dma_flush_range
diff --git a/arch/arm/mm/proc-syms.c b/arch/arm/mm/proc-syms.c
index ac5c80062b70..3e6210b4d6d4 100644
--- a/arch/arm/mm/proc-syms.c
+++ b/arch/arm/mm/proc-syms.c
@@ -27,8 +27,7 @@ EXPORT_SYMBOL(__cpuc_flush_kern_all);
 EXPORT_SYMBOL(__cpuc_flush_user_all);
 EXPORT_SYMBOL(__cpuc_flush_user_range);
 EXPORT_SYMBOL(__cpuc_coherent_kern_range);
-EXPORT_SYMBOL(__cpuc_flush_dcache_page);
-EXPORT_SYMBOL(dmac_inv_range);  /* because of flush_ioremap_region() */
+EXPORT_SYMBOL(__cpuc_flush_dcache_area);
 #else
 EXPORT_SYMBOL(cpu_cache);
 #endif
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 5485c821101c..395cc90c6613 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -254,10 +254,9 @@ __pj4_v6_proc_info:
         .long   0x560f5810
         .long   0xff0ffff0
         .long   PMD_TYPE_SECT | \
-                PMD_SECT_BUFFERABLE | \
-                PMD_SECT_CACHEABLE | \
                 PMD_SECT_AP_WRITE | \
-                PMD_SECT_AP_READ
+                PMD_SECT_AP_READ | \
+                PMD_FLAGS
         .long   PMD_TYPE_SECT | \
                 PMD_SECT_XN | \
                 PMD_SECT_AP_WRITE | \
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index fab134e29826..96456f548798 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -226,15 +226,16 @@ ENTRY(xsc3_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache.
  *
- *      - addr  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(xsc3_flush_kern_dcache_page)
-        add     r1, r0, #PAGE_SZ
+ENTRY(xsc3_flush_kern_dcache_area)
+        add     r1, r0, r1
 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean/invalidate L1 D line
         add     r0, r0, #CACHELINESIZE
         cmp     r0, r1
@@ -309,7 +310,7 @@ ENTRY(xsc3_cache_fns)
         .long   xsc3_flush_user_cache_range
         .long   xsc3_coherent_kern_range
         .long   xsc3_coherent_user_range
-        .long   xsc3_flush_kern_dcache_page
+        .long   xsc3_flush_kern_dcache_area
         .long   xsc3_dma_inv_range
         .long   xsc3_dma_clean_range
         .long   xsc3_dma_flush_range
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index f056c283682d..93df47265f2d 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -284,15 +284,16 @@ ENTRY(xscale_coherent_user_range)
         mov     pc, lr
 
 /*
- *      flush_kern_dcache_page(void *page)
+ *      flush_kern_dcache_area(void *addr, size_t size)
  *
  *      Ensure no D cache aliasing occurs, either with itself or
  *      the I cache
  *
- *      - addr  - page aligned address
+ *      - addr  - kernel address
+ *      - size  - region size
  */
-ENTRY(xscale_flush_kern_dcache_page)
-        add     r1, r0, #PAGE_SZ
+ENTRY(xscale_flush_kern_dcache_area)
+        add     r1, r0, r1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
         mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
         add     r0, r0, #CACHELINESIZE
@@ -368,7 +369,7 @@ ENTRY(xscale_cache_fns)
         .long   xscale_flush_user_cache_range
         .long   xscale_coherent_kern_range
         .long   xscale_coherent_user_range
-        .long   xscale_flush_kern_dcache_page
+        .long   xscale_flush_kern_dcache_area
         .long   xscale_dma_inv_range
         .long   xscale_dma_clean_range
         .long   xscale_dma_flush_range
@@ -392,7 +393,7 @@ ENTRY(xscale_80200_A0_A1_cache_fns)
         .long   xscale_flush_user_cache_range
         .long   xscale_coherent_kern_range
         .long   xscale_coherent_user_range
-        .long   xscale_flush_kern_dcache_page
+        .long   xscale_flush_kern_dcache_area
         .long   xscale_dma_flush_range
         .long   xscale_dma_clean_range
         .long   xscale_dma_flush_range
diff --git a/arch/arm/tools/Makefile b/arch/arm/tools/Makefile
index 1dbaa29ac4d7..635cb1865e4d 100644
--- a/arch/arm/tools/Makefile
+++ b/arch/arm/tools/Makefile
@@ -4,7 +4,7 @@
 # Copyright (C) 2001 Russell King
 #
 
-include/asm-arm/mach-types.h: $(src)/gen-mach-types $(src)/mach-types
+include/generated/mach-types.h: $(src)/gen-mach-types $(src)/mach-types
         @echo '  Generating $@'
         @mkdir -p $(dir $@)
         $(Q)$(AWK) -f $^ > $@ || { rm -f $@; /bin/false; }
diff --git a/arch/arm/tools/gen-mach-types b/arch/arm/tools/gen-mach-types
index ce319ef64bc1..04fef71d7be9 100644
--- a/arch/arm/tools/gen-mach-types
+++ b/arch/arm/tools/gen-mach-types
@@ -1,6 +1,6 @@
 #!/bin/awk
 #
-# Awk script to generate include/asm-arm/mach-types.h
+# Awk script to generate include/generated/mach-types.h
 #
 BEGIN   { nr = 0 }
 /^#/    { next }
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 07b976da6174..c3a74ce24ef6 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -12,7 +12,7 @@
 #
 #   http://www.arm.linux.org.uk/developer/machines/?action=new
 #
-# Last update: Wed Nov 25 22:14:58 2009
+# Last update: Wed Dec 16 20:06:34 2009
 #
 # machine_is_xxx        CONFIG_xxxx             MACH_TYPE_xxx           number
 #
@@ -1776,6 +1776,7 @@ cybook3			MACH_CYBOOK3		CYBOOK3			1784
 wdg002                  MACH_WDG002             WDG002                  1785
 sg560adsl               MACH_SG560ADSL          SG560ADSL               1786
 nextio_n2800_ica        MACH_NEXTIO_N2800_ICA   NEXTIO_N2800_ICA        1787
+dove_db                 MACH_DOVE_DB            DOVE_DB                 1788
 marvell_newdb           MACH_MARVELL_NEWDB      MARVELL_NEWDB           1789
 vandihud                MACH_VANDIHUD           VANDIHUD                1790
 magx_e8                 MACH_MAGX_E8            MAGX_E8                 1791
@@ -2536,3 +2537,44 @@ c3ax03			MACH_C3AX03		C3AX03			2549
 mxt_td60                MACH_MXT_TD60           MXT_TD60                2550
 esyx                    MACH_ESYX               ESYX                    2551
 bulldog                 MACH_BULLDOG            BULLDOG                 2553
+derell_me2000           MACH_DERELL_ME2000      DERELL_ME2000           2554
+bcmring_base            MACH_BCMRING_BASE       BCMRING_BASE            2555
+bcmring_evm             MACH_BCMRING_EVM        BCMRING_EVM             2556
+bcmring_evm_jazz        MACH_BCMRING_EVM_JAZZ   BCMRING_EVM_JAZZ        2557
+bcmring_sp              MACH_BCMRING_SP         BCMRING_SP              2558
+bcmring_sv              MACH_BCMRING_SV         BCMRING_SV              2559
+bcmring_sv_jazz         MACH_BCMRING_SV_JAZZ    BCMRING_SV_JAZZ         2560
+bcmring_tablet          MACH_BCMRING_TABLET     BCMRING_TABLET          2561
+bcmring_vp              MACH_BCMRING_VP         BCMRING_VP              2562
+bcmring_evm_seikor      MACH_BCMRING_EVM_SEIKOR BCMRING_EVM_SEIKOR      2563
+bcmring_sp_wqvga        MACH_BCMRING_SP_WQVGA   BCMRING_SP_WQVGA        2564
+bcmring_custom          MACH_BCMRING_CUSTOM     BCMRING_CUSTOM          2565
+acer_s200               MACH_ACER_S200          ACER_S200               2566
+bt270                   MACH_BT270              BT270                   2567
+iseo                    MACH_ISEO               ISEO                    2568
+cezanne                 MACH_CEZANNE            CEZANNE                 2569
+lucca                   MACH_LUCCA              LUCCA                   2570
+supersmart              MACH_SUPERSMART         SUPERSMART              2571
+magnolia2               MACH_MAGNOLIA2          MAGNOLIA2               2573
+emxx                    MACH_EMXX               EMXX                    2574
+outlaw                  MACH_OUTLAW             OUTLAW                  2575
+riot_bei2               MACH_RIOT_BEI2          RIOT_BEI2               2576
+riot_vox                MACH_RIOT_VOX           RIOT_VOX                2577
+riot_x37                MACH_RIOT_X37           RIOT_X37                2578
+mega25mx                MACH_MEGA25MX           MEGA25MX                2579
+benzina2                MACH_BENZINA2           BENZINA2                2580
+ignite                  MACH_IGNITE             IGNITE                  2581
+foggia                  MACH_FOGGIA             FOGGIA                  2582
+arezzo                  MACH_AREZZO             AREZZO                  2583
+leica_skywalker         MACH_LEICA_SKYWALKER    LEICA_SKYWALKER         2584
+jacinto2_jamr           MACH_JACINTO2_JAMR      JACINTO2_JAMR           2585
+gts_nova                MACH_GTS_NOVA           GTS_NOVA                2586
+p3600                   MACH_P3600              P3600                   2587
+dlt2                    MACH_DLT2               DLT2                    2588
+df3120                  MACH_DF3120             DF3120                  2589
+ecucore_9g20            MACH_ECUCORE_9G20       ECUCORE_9G20            2590
+nautel_lpc3240          MACH_NAUTEL_LPC3240     NAUTEL_LPC3240          2591
+glacier                 MACH_GLACIER            GLACIER                 2592
+phrazer_bulldog         MACH_PHRAZER_BULLDOG    PHRAZER_BULLDOG         2593
+omap3_bulldog           MACH_OMAP3_BULLDOG      OMAP3_BULLDOG           2594
+pca101                  MACH_PCA101             PCA101                  2595
diff --git a/arch/avr32/include/asm/asm-offsets.h b/arch/avr32/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/avr32/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/blackfin/include/asm/asm-offsets.h b/arch/blackfin/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/blackfin/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/cris/arch-v32/kernel/head.S b/arch/cris/arch-v32/kernel/head.S
index 3db478eb5155..76266f80a5f1 100644
--- a/arch/cris/arch-v32/kernel/head.S
+++ b/arch/cris/arch-v32/kernel/head.S
@@ -10,7 +10,6 @@
  * The macros found in mmu_defs_asm.h uses the ## concatenation operator, so
  * -traditional must not be used when assembling this file.
  */
-#include <linux/autoconf.h>
 #include <arch/memmap.h>
 #include <hwregs/reg_rdwr.h>
 #include <hwregs/intr_vect.h>
diff --git a/arch/cris/include/asm/asm-offsets.h b/arch/cris/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/cris/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/cris/kernel/asm-offsets.c b/arch/cris/kernel/asm-offsets.c
index ddd6fbbe75de..dd7b8e983221 100644
--- a/arch/cris/kernel/asm-offsets.c
+++ b/arch/cris/kernel/asm-offsets.c
@@ -1,6 +1,5 @@
 #include <linux/sched.h>
 #include <asm/thread_info.h>
-#include <linux/autoconf.h>
 
 /*
  * Generate definitions needed by assembly language modules.
diff --git a/arch/cris/kernel/vmlinux.lds.S b/arch/cris/kernel/vmlinux.lds.S
index bbfda67d2907..d49d17d2a14f 100644
--- a/arch/cris/kernel/vmlinux.lds.S
+++ b/arch/cris/kernel/vmlinux.lds.S
@@ -8,7 +8,6 @@
  * the kernel has booted.
  */
 
-#include <linux/autoconf.h>
 #include <asm-generic/vmlinux.lds.h>
 #include <asm/page.h>
 
diff --git a/arch/frv/include/asm/asm-offsets.h b/arch/frv/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/frv/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/frv/kernel/setup.c b/arch/frv/kernel/setup.c
index 55e4fab7c0bc..75cf7f4b2fa8 100644
--- a/arch/frv/kernel/setup.c
+++ b/arch/frv/kernel/setup.c
@@ -10,7 +10,7 @@
  * 2 of the License, or (at your option) any later version.
  */
 
-#include <linux/utsrelease.h>
+#include <generated/utsrelease.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
 #include <linux/delay.h>
diff --git a/arch/h8300/include/asm/asm-offsets.h b/arch/h8300/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/h8300/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/ia64/Makefile b/arch/ia64/Makefile
index e7cbaa02cd0b..475e2725fbde 100644
--- a/arch/ia64/Makefile
+++ b/arch/ia64/Makefile
@@ -103,4 +103,4 @@ archprepare: make_nr_irqs_h FORCE
 PHONY += make_nr_irqs_h FORCE
 
 make_nr_irqs_h: FORCE
-        $(Q)$(MAKE) $(build)=arch/ia64/kernel include/asm-ia64/nr-irqs.h
+        $(Q)$(MAKE) $(build)=arch/ia64/kernel include/generated/nr-irqs.h
diff --git a/arch/ia64/include/asm/asm-offsets.h b/arch/ia64/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/ia64/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/ia64/include/asm/irq.h b/arch/ia64/include/asm/irq.h
index 5282546cdf82..91b920fd7d53 100644
--- a/arch/ia64/include/asm/irq.h
+++ b/arch/ia64/include/asm/irq.h
@@ -13,7 +13,7 @@
 
 #include <linux/types.h>
 #include <linux/cpumask.h>
-#include <asm-ia64/nr-irqs.h>
+#include <generated/nr-irqs.h>
 
 static __inline__ int
 irq_canonicalize (int irq)
diff --git a/arch/ia64/kernel/Makefile b/arch/ia64/kernel/Makefile
index 6b7edcab0cb5..2a75e937ae8d 100644
--- a/arch/ia64/kernel/Makefile
+++ b/arch/ia64/kernel/Makefile
@@ -81,17 +81,14 @@ define cmd_nr_irqs
 endef
 
 # We use internal kbuild rules to avoid the "is up to date" message from make
-arch/$(SRCARCH)/kernel/nr-irqs.s: $(srctree)/arch/$(SRCARCH)/kernel/nr-irqs.c \
-                                $(wildcard $(srctree)/include/asm-ia64/*/irq.h)
+arch/$(SRCARCH)/kernel/nr-irqs.s: arch/$(SRCARCH)/kernel/nr-irqs.c
         $(Q)mkdir -p $(dir $@)
         $(call if_changed_dep,cc_s_c)
 
-include/asm-ia64/nr-irqs.h: arch/$(SRCARCH)/kernel/nr-irqs.s
+include/generated/nr-irqs.h: arch/$(SRCARCH)/kernel/nr-irqs.s
         $(Q)mkdir -p $(dir $@)
         $(call cmd,nr_irqs)
 
-clean-files += $(objtree)/include/asm-ia64/nr-irqs.h
-
 #
 # native ivt.S, entry.S and fsys.S
 #
diff --git a/arch/ia64/kvm/asm-offsets.c b/arch/ia64/kvm/asm-offsets.c
index 0c3564a7a033..9324c875caf5 100644
--- a/arch/ia64/kvm/asm-offsets.c
+++ b/arch/ia64/kvm/asm-offsets.c
@@ -22,7 +22,6 @@
  *
  */
 
-#include <linux/autoconf.h>
 #include <linux/kvm_host.h>
 #include <linux/kbuild.h>
 
diff --git a/arch/m68k/include/asm/asm-offsets.h b/arch/m68k/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/m68k/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/m68k/kernel/head.S b/arch/m68k/kernel/head.S
index 86edb5fbcfc3..ef54128baa0b 100644
--- a/arch/m68k/kernel/head.S
+++ b/arch/m68k/kernel/head.S
@@ -196,7 +196,7 @@
  * for them and trying to understand what they mean.
  *
  * CONFIG_xxx:  These are the obvious machine configuration defines created
- * during configuration.  These are defined in include/linux/autoconf.h.
+ * during configuration.  These are defined in autoconf.h.
  *
  * CONSOLE:     There is support for head.S console in this file.  This
  * console can talk to a Mac frame buffer, but could easily be extrapolated
diff --git a/arch/microblaze/include/asm/asm-offsets.h b/arch/microblaze/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/microblaze/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index fd7620f025fa..9541171f1220 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -5,9 +5,12 @@ config MIPS
         select HAVE_IDE
         select HAVE_OPROFILE
         select HAVE_ARCH_KGDB
-        # Horrible source of confusion.  Die, die, die ...
-        select EMBEDDED
-        select RTC_LIB if !LEMOTE_FULOONG2E
+        select HAVE_FUNCTION_TRACER
+        select HAVE_FUNCTION_TRACE_MCOUNT_TEST
+        select HAVE_DYNAMIC_FTRACE
+        select HAVE_FTRACE_MCOUNT_RECORD
+        select HAVE_FUNCTION_GRAPH_TRACER
+        select RTC_LIB if !MACH_LOONGSON
 
 mainmenu "Linux/MIPS Kernel Configuration"
 
@@ -22,6 +25,7 @@ choice
 
 config MACH_ALCHEMY
         bool "Alchemy processor based machines"
+        select SYS_SUPPORTS_ZBOOT
 
 config AR7
         bool "Texas Instruments AR7"
@@ -36,6 +40,7 @@ config AR7
         select SYS_HAS_EARLY_PRINTK
         select SYS_SUPPORTS_32BIT_KERNEL
         select SYS_SUPPORTS_LITTLE_ENDIAN
+        select SYS_SUPPORTS_ZBOOT_UART16550
         select GENERIC_GPIO
         select GCD
         select VLYNQ
@@ -43,23 +48,6 @@ config AR7
           Support for the Texas Instruments AR7 System-on-a-Chip
           family: TNETD7100, 7200 and 7300.
 
-config BASLER_EXCITE
-        bool "Basler eXcite smart camera"
-        select CEVT_R4K
-        select CSRC_R4K
-        select DMA_COHERENT
-        select HW_HAS_PCI
-        select IRQ_CPU
-        select IRQ_CPU_RM7K
-        select IRQ_CPU_RM9K
-        select MIPS_RM9122
-        select SYS_HAS_CPU_RM9000
-        select SYS_SUPPORTS_32BIT_KERNEL
-        select SYS_SUPPORTS_BIG_ENDIAN
-        help
-          The eXcite is a smart camera platform manufactured by
-          Basler Vision Technologies AG.
-
 config BCM47XX
         bool "BCM47XX based boards"
         select CEVT_R4K
@@ -192,6 +180,7 @@ config LASAT
 
 config MACH_LOONGSON
         bool "Loongson family of machines"
+        select SYS_SUPPORTS_ZBOOT_UART16550
         help
           This enables the support of Loongson family of machines.
 
@@ -233,6 +222,7 @@ config MIPS_MALTA
         select SYS_SUPPORTS_MIPS_CMP
         select SYS_SUPPORTS_MULTITHREADING
         select SYS_SUPPORTS_SMARTMIPS
+        select SYS_SUPPORTS_ZBOOT
         help
           This enables support for the MIPS Technologies Malta evaluation
           board.
@@ -334,6 +324,24 @@ config PMC_YOSEMITE
           Yosemite is an evaluation board for the RM9000x2 processor
           manufactured by PMC-Sierra.
 
+config POWERTV
+        bool "Cisco PowerTV"
+        select BOOT_ELF32
+        select CEVT_R4K
+        select CPU_MIPSR2_IRQ_VI
+        select CPU_MIPSR2_IRQ_EI
+        select CSRC_POWERTV
+        select DMA_NONCOHERENT
+        select HW_HAS_PCI
+        select SYS_HAS_EARLY_PRINTK
+        select SYS_HAS_CPU_MIPS32_R2
+        select SYS_SUPPORTS_32BIT_KERNEL
+        select SYS_SUPPORTS_BIG_ENDIAN
+        select SYS_SUPPORTS_HIGHMEM
+        select USB_OHCI_LITTLE_ENDIAN
+        help
+          This enables support for the Cisco PowerTV Platform.
+
 config SGI_IP22
         bool "SGI IP22 (Indy/Indigo2)"
         select ARC
@@ -674,11 +682,11 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
 endchoice
 
 source "arch/mips/alchemy/Kconfig"
-source "arch/mips/basler/excite/Kconfig"
 source "arch/mips/bcm63xx/Kconfig"
 source "arch/mips/jazz/Kconfig"
 source "arch/mips/lasat/Kconfig"
 source "arch/mips/pmc-sierra/Kconfig"
+source "arch/mips/powertv/Kconfig"
 source "arch/mips/sgi-ip27/Kconfig"
 source "arch/mips/sibyte/Kconfig"
 source "arch/mips/txx9/Kconfig"
@@ -778,6 +786,9 @@ config CSRC_BCM1480
 config CSRC_IOASIC
         bool
 
+config CSRC_POWERTV
+        bool
+
 config CSRC_R4K_LIB
         bool
 
@@ -806,20 +817,6 @@ config DMA_NONCOHERENT
 config DMA_NEED_PCI_MAP_STATE
         bool
 
-config EARLY_PRINTK
-        bool "Early printk" if EMBEDDED && DEBUG_KERNEL
-        depends on SYS_HAS_EARLY_PRINTK
-        default y
-        help
-          This option enables special console drivers which allow the kernel
-          to print messages very early in the bootup process.
-
-          This is useful for kernel debugging when your machine crashes very
-          early before the console code is initialized. For normal operation,
-          it is not recommended because it looks ugly on some machines and
-          doesn't cooperate with an X server. You should normally say N here,
-          unless you want to debug such a crash.
-
 config SYS_HAS_EARLY_PRINTK
         bool
 
@@ -1069,6 +1066,21 @@ config CPU_LOONGSON2E
           The Loongson 2E processor implements the MIPS III instruction set
           with many extensions.
 
+          It has an internal FPGA northbridge, which is compatiable to
+          bonito64.
+
+config CPU_LOONGSON2F
+        bool "Loongson 2F"
+        depends on SYS_HAS_CPU_LOONGSON2F
+        select CPU_LOONGSON2
+        help
+          The Loongson 2F processor implements the MIPS III instruction set
+          with many extensions.
+
+          Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
+          have a similar programming interface with FPGA northbridge used in
+          Loongson2E.
+
 config CPU_MIPS32_R1
         bool "MIPS32 Release 1"
         depends on SYS_HAS_CPU_MIPS32_R1
@@ -1294,6 +1306,16 @@ config CPU_CAVIUM_OCTEON
 
 endchoice
 
+config SYS_SUPPORTS_ZBOOT
+        bool
+        select HAVE_KERNEL_GZIP
+        select HAVE_KERNEL_BZIP2
+        select HAVE_KERNEL_LZMA
+
+config SYS_SUPPORTS_ZBOOT_UART16550
+        bool
+        select SYS_SUPPORTS_ZBOOT
+
 config CPU_LOONGSON2
         bool
         select CPU_SUPPORTS_32BIT_KERNEL
@@ -1303,6 +1325,12 @@ config CPU_LOONGSON2
 config SYS_HAS_CPU_LOONGSON2E
         bool
 
+config SYS_HAS_CPU_LOONGSON2F
+        bool
+        select CPU_SUPPORTS_CPUFREQ
+        select CPU_SUPPORTS_ADDRWINCFG if 64BIT
+        select CPU_SUPPORTS_UNCACHED_ACCELERATED
+
 config SYS_HAS_CPU_MIPS32_R1
         bool
 
@@ -1411,8 +1439,17 @@ config CPU_SUPPORTS_32BIT_KERNEL
         bool
 config CPU_SUPPORTS_64BIT_KERNEL
         bool
+config CPU_SUPPORTS_CPUFREQ
+        bool
+config CPU_SUPPORTS_ADDRWINCFG
+        bool
 config CPU_SUPPORTS_HUGEPAGES
         bool
+config CPU_SUPPORTS_UNCACHED_ACCELERATED
+        bool
+config MIPS_PGD_C0_CONTEXT
+        bool
+        default y if 64BIT && CPU_MIPSR2
 
 #
 # Set to y for ptrace access to watch registers.
@@ -2024,15 +2061,6 @@ config STACKTRACE_SUPPORT
 
 source "init/Kconfig"
 
-config PROBE_INITRD_HEADER
-        bool "Probe initrd header created by addinitrd"
-        depends on BLK_DEV_INITRD
-        help
-          Probe initrd header at the last page of kernel image.
-          Say Y here if you are using arch/mips/boot/addinitrd.c to
-          add initrd or initramfs image to the kernel image.
-          Otherwise, say N.
-
 source "kernel/Kconfig.freezer"
 
 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
@@ -2104,6 +2132,7 @@ config MMU
 
 config I8253
         bool
+        select MIPS_EXTERNAL_TIMER
 
 config ZONE_DMA32
         bool
@@ -2180,6 +2209,8 @@ source "kernel/power/Kconfig"
 
 endmenu
 
+source "arch/mips/kernel/cpufreq/Kconfig"
+
 source "net/Kconfig"
 
 source "drivers/Kconfig"
diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug
index 364ca8938807..d2b88a0be519 100644
--- a/arch/mips/Kconfig.debug
+++ b/arch/mips/Kconfig.debug
@@ -6,15 +6,66 @@ config TRACE_IRQFLAGS_SUPPORT
 
 source "lib/Kconfig.debug"
 
+config EARLY_PRINTK
+        bool "Early printk" if EMBEDDED
+        depends on SYS_HAS_EARLY_PRINTK
+        default y
+        help
+          This option enables special console drivers which allow the kernel
+          to print messages very early in the bootup process.
+
+          This is useful for kernel debugging when your machine crashes very
+          early before the console code is initialized. For normal operation,
+          it is not recommended because it looks ugly on some machines and
+          doesn't cooperate with an X server. You should normally say N here,
+          unless you want to debug such a crash.
+
+config CMDLINE_BOOL
+        bool "Built-in kernel command line"
+        default n
+        help
+          For most systems, it is firmware or second stage bootloader that
+          by default specifies the kernel command line options.  However,
+          it might be necessary or advantageous to either override the
+          default kernel command line or add a few extra options to it.
+          For such cases, this option allows you to hardcode your own
+          command line options directly into the kernel.  For that, you
+          should choose 'Y' here, and fill in the extra boot arguments
+          in CONFIG_CMDLINE.
+
+          The built-in options will be concatenated to the default command
+          line if CMDLINE_OVERRIDE is set to 'N'. Otherwise, the default
+          command line will be ignored and replaced by the built-in string.
+
+          Most MIPS systems will normally expect 'N' here and rely upon
+          the command line from the firmware or the second-stage bootloader.
+
 config CMDLINE
         string "Default kernel command string"
+        depends on CMDLINE_BOOL
         default ""
         help
           On some platforms, there is currently no way for the boot loader to
-          pass arguments to the kernel. For these platforms, you can supply
-          some command-line options at build time by entering them here.  In
-          other cases you can specify kernel args so that you don't have
-          to set them up in board prom initialization routines.
+          pass arguments to the kernel.  For these platforms, and for the cases
+          when you want to add some extra options to the command line or ignore
+          the default command line, you can supply some command-line options at
+          build time by entering them here.  In other cases you can specify
+          kernel args so that you don't have to set them up in board prom
+          initialization routines.
+
+          For more information, see the CMDLINE_BOOL and CMDLINE_OVERRIDE
+          options.
+
+config CMDLINE_OVERRIDE
+        bool "Built-in command line overrides firware arguments"
+        default n
+        depends on CMDLINE_BOOL
+        help
+          By setting this option to 'Y' you will have your kernel ignore
+          command line arguments from firmware or second stage bootloader.
+          Instead, the built-in command line will be used exclusively.
+
+          Normally, you will choose 'N' here.
 
 config DEBUG_STACK_USAGE
         bool "Enable stack utilization instrumentation"
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 77f5021218d3..1893efd43fca 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -48,7 +48,16 @@ ifneq ($(SUBARCH),$(ARCH))
   endif
 endif
 
+ifndef CONFIG_FUNCTION_TRACER
 cflags-y := -ffunction-sections
+endif
+ifdef CONFIG_FUNCTION_GRAPH_TRACER
+  ifndef KBUILD_MCOUNT_RA_ADDRESS
+    ifeq ($(call cc-option-yn,-mmcount-ra-address), y)
+      cflags-y += -mmcount-ra-address -DKBUILD_MCOUNT_RA_ADDRESS
+    endif
+  endif
+endif
 cflags-y += $(call cc-option, -mno-check-zero-division)
 
 ifdef CONFIG_32BIT
@@ -69,6 +78,7 @@ endif
 
 all-$(CONFIG_BOOT_ELF32)        := $(vmlinux-32)
 all-$(CONFIG_BOOT_ELF64)        := $(vmlinux-64)
+all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlinuz
 
 #
 # GCC uses -G 0 -mabicalls -fpic as default.  We don't want PIC in the kernel
@@ -124,6 +134,8 @@ cflags-$(CONFIG_CPU_TX49XX)	+= -march=r4600 -Wa,--trap
 cflags-$(CONFIG_CPU_LOONGSON2)  += -Wa,--trap
 cflags-$(CONFIG_CPU_LOONGSON2E) += \
         $(call cc-option,-march=loongson2e,-march=r4600)
+cflags-$(CONFIG_CPU_LOONGSON2F) += \
+        $(call cc-option,-march=loongson2f,-march=r4600)
 
 cflags-$(CONFIG_CPU_MIPS32_R1)  += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
                         -Wa,-mips32 -Wa,--trap
@@ -324,6 +336,7 @@ core-$(CONFIG_MACH_LOONGSON) +=arch/mips/loongson/
 cflags-$(CONFIG_MACH_LOONGSON) += -I$(srctree)/arch/mips/include/asm/mach-loongson \
                     -mno-branch-likely
 load-$(CONFIG_LEMOTE_FULOONG2E) +=0xffffffff80100000
+load-$(CONFIG_LEMOTE_MACH2F) +=0xffffffff80200000
 
 #
 # MIPS Malta board
@@ -331,7 +344,7 @@ load-$(CONFIG_LEMOTE_FULOONG2E) +=0xffffffff80100000
 core-$(CONFIG_MIPS_MALTA)       += arch/mips/mti-malta/
 cflags-$(CONFIG_MIPS_MALTA)     += -I$(srctree)/arch/mips/include/asm/mach-malta
 load-$(CONFIG_MIPS_MALTA)       += 0xffffffff80100000
-all-$(CONFIG_MIPS_MALTA)        := vmlinux.bin
+all-$(CONFIG_MIPS_MALTA)        := vmlinuz.bin
 
 #
 # MIPS SIM
@@ -356,13 +369,6 @@ cflags-$(CONFIG_PMC_YOSEMITE)	+= -I$(srctree)/arch/mips/include/asm/mach-yosemit
 load-$(CONFIG_PMC_YOSEMITE)     += 0xffffffff80100000
 
 #
-# Basler eXcite
-#
-core-$(CONFIG_BASLER_EXCITE)    += arch/mips/basler/excite/
-cflags-$(CONFIG_BASLER_EXCITE)  += -I$(srctree)/arch/mips/include/asm/mach-excite
-load-$(CONFIG_BASLER_EXCITE)    += 0x80100000
-
-#
 # LASAT platforms
 #
 core-$(CONFIG_LASAT)            += arch/mips/lasat/
@@ -441,6 +447,13 @@ core-$(CONFIG_NEC_MARKEINS)	+= arch/mips/emma/markeins/
 load-$(CONFIG_NEC_MARKEINS)     += 0xffffffff88100000
 
 #
+# Cisco PowerTV Platform
+#
+core-$(CONFIG_POWERTV)          += arch/mips/powertv/
+cflags-$(CONFIG_POWERTV)        += -I$(srctree)/arch/mips/include/asm/mach-powertv
+load-$(CONFIG_POWERTV)          += 0xffffffff90800000
+
+#
 # SGI IP22 (Indy/Indigo2)
 #
 # Set the load address to >= 0xffffffff88069000 if you want to leave space for
@@ -581,7 +594,7 @@ load-$(CONFIG_SNI_RM)		+= 0xffffffff80600000
 else
 load-$(CONFIG_SNI_RM)           += 0xffffffff80030000
 endif
-all-$(CONFIG_SNI_RM)            := vmlinux.ecoff
+all-$(CONFIG_SNI_RM)            := vmlinuz.ecoff
 
 #
 # Common TXx9
@@ -699,9 +712,23 @@ vmlinux.64: vmlinux
         $(OBJCOPY) -O $(64bit-bfd) $(OBJCOPYFLAGS) $< $@
 
 makeboot =$(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) $(1)
+makezboot =$(Q)$(MAKE) $(build)=arch/mips/boot/compressed \
+           VMLINUX_LOAD_ADDRESS=$(load-y) 32bit-bfd=$(32bit-bfd) $(1)
 
 all:    $(all-y)
 
+vmlinuz: vmlinux FORCE
+        +@$(call makezboot,$@)
+
+vmlinuz.bin: vmlinux
+        +@$(call makezboot,$@)
+
+vmlinuz.ecoff: vmlinux
+        +@$(call makezboot,$@)
+
+vmlinuz.srec: vmlinux
+        +@$(call makezboot,$@)
+
 vmlinux.bin: $(vmlinux-32)
         +@$(call makeboot,$@)
 
@@ -726,11 +753,13 @@ endif
 
 install:
         $(Q)install -D -m 755 vmlinux $(INSTALL_PATH)/vmlinux-$(KERNELRELEASE)
+        $(Q)install -D -m 755 vmlinuz $(INSTALL_PATH)/vmlinuz-$(KERNELRELEASE)
         $(Q)install -D -m 644 .config $(INSTALL_PATH)/config-$(KERNELRELEASE)
         $(Q)install -D -m 644 System.map $(INSTALL_PATH)/System.map-$(KERNELRELEASE)
 
 archclean:
         @$(MAKE) $(clean)=arch/mips/boot
+        @$(MAKE) $(clean)=arch/mips/boot/compressed
         @$(MAKE) $(clean)=arch/mips/lasat
 
 define archhelp
@@ -738,10 +767,18 @@ define archhelp
         echo '  vmlinux.ecoff        - ECOFF boot image'
         echo '  vmlinux.bin          - Raw binary boot image'
         echo '  vmlinux.srec         - SREC boot image'
+        echo '  vmlinuz              - Compressed boot(zboot) image'
+        echo '  vmlinuz.ecoff        - ECOFF zboot image'
+        echo '  vmlinuz.bin          - Raw binary zboot image'
+        echo '  vmlinuz.srec         - SREC zboot image'
         echo
         echo '  These will be default as apropriate for a configured platform.'
 endef
 
 CLEAN_FILES += vmlinux.32 \
                vmlinux.64 \
-               vmlinux.ecoff
+               vmlinux.ecoff \
+               vmlinuz \
+               vmlinuz.ecoff \
+               vmlinuz.bin \
+               vmlinuz.srec
diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c
index 835f3f0319ca..85169c08d8dc 100644
--- a/arch/mips/ar7/platform.c
+++ b/arch/mips/ar7/platform.c
@@ -505,7 +505,7 @@ static int __init ar7_register_devices(void)
         int res;
         u32 *bootcr, val;
 #ifdef CONFIG_SERIAL_8250
-        static struct uart_port uart_port[2];
+        static struct uart_port uart_port[2] __initdata;
 
         memset(uart_port, 0, sizeof(struct uart_port) * 2);
 
diff --git a/arch/mips/basler/excite/Kconfig b/arch/mips/basler/excite/Kconfig
deleted file mode 100644
index ba506075608b..000000000000
--- a/arch/mips/basler/excite/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-config BASLER_EXCITE_PROTOTYPE
-        bool "Support for pre-release units"
-        depends on BASLER_EXCITE
-        default n
-        help
-          Pre-series (prototype) units are different from later ones in
-          some ways. Select this option if you have one of these. Please
-          note that a kernel built with this option selected will not be
-          able to run on normal units.
diff --git a/arch/mips/basler/excite/Makefile b/arch/mips/basler/excite/Makefile
deleted file mode 100644
index cff29cf46d03..000000000000
--- a/arch/mips/basler/excite/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Makefile for Basler eXcite
-#
-
-obj-$(CONFIG_BASLER_EXCITE)     += excite_irq.o excite_prom.o excite_setup.o \
-                                   excite_device.o excite_procfs.o
-
-obj-m                           += excite_iodev.o
diff --git a/arch/mips/basler/excite/excite_device.c b/arch/mips/basler/excite/excite_device.c
deleted file mode 100644
index e00bc2d7f301..000000000000
--- a/arch/mips/basler/excite/excite_device.c
+++ /dev/null
@@ -1,403 +0,0 @@
-/*
- *  Copyright (C) 2004 by Basler Vision Technologies AG
- *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/ioport.h>
-#include <linux/err.h>
-#include <linux/jiffies.h>
-#include <linux/sched.h>
-#include <asm/types.h>
-#include <asm/rm9k-ocd.h>
-
-#include <excite.h>
-#include <rm9k_eth.h>
-#include <rm9k_wdt.h>
-#include <rm9k_xicap.h>
-#include <excite_nandflash.h>
-
-#include "excite_iodev.h"
-
-#define RM9K_GE_UNIT    0
-#define XICAP_UNIT      0
-#define NAND_UNIT       0
-
-#define DLL_TIMEOUT     3               /* seconds */
-
-
-#define RINIT(__start__, __end__, __name__, __parent__) {       \
-        .name   = __name__ "_0",                                \
-        .start  = (__start__),                                  \
-        .end    = (__end__),                                    \
-        .flags  = 0,                                            \
-        .parent = (__parent__)                                  \
-}
-
-#define RINIT_IRQ(__irq__, __name__) {  \
-        .name   = __name__ "_0",        \
-        .start  = (__irq__),            \
-        .end    = (__irq__),            \
-        .flags  = IORESOURCE_IRQ,       \
-        .parent = NULL                  \
-}
-
-
-
-enum {
-        slice_xicap,
-        slice_eth
-};
-
-
-
-static struct resource
-        excite_ctr_resource __maybe_unused = {
-                .name           = "GPI counters",
-                .start          = 0,
-                .end            = 5,
-                .flags          = 0,
-                .parent         = NULL,
-                .sibling        = NULL,
-                .child          = NULL
-        },
-        excite_gpislice_resource __maybe_unused = {
-                .name           = "GPI slices",
-                .start          = 0,
-                .end            = 1,
-                .flags          = 0,
-                .parent         = NULL,
-                .sibling        = NULL,
-                .child          = NULL
-        },
-        excite_mdio_channel_resource __maybe_unused = {
-                .name           = "MDIO channels",
-                .start          = 0,
-                .end            = 1,
-                .flags          = 0,
-                .parent         = NULL,
-                .sibling        = NULL,
-                .child          = NULL
-        },
-        excite_fifomem_resource __maybe_unused = {
-                .name           = "FIFO memory",
-                .start          = 0,
-                .end            = 767,
-                .flags          = 0,
-                .parent         = NULL,
-                .sibling        = NULL,
-                .child          = NULL
-        },
-        excite_scram_resource __maybe_unused = {
-                .name           = "Scratch RAM",
-                .start          = EXCITE_PHYS_SCRAM,
-                .end            = EXCITE_PHYS_SCRAM + EXCITE_SIZE_SCRAM - 1,
-                .flags          = IORESOURCE_MEM,
-                .parent         = NULL,
-                .sibling        = NULL,
-                .child          = NULL
-        },
-        excite_fpga_resource __maybe_unused = {
-                .name           = "System FPGA",
-                .start          = EXCITE_PHYS_FPGA,
-                .end            = EXCITE_PHYS_FPGA + EXCITE_SIZE_FPGA - 1,
-                .flags          = IORESOURCE_MEM,
-                .parent         = NULL,
-                .sibling        = NULL,
-                .child          = NULL
-        },
-        excite_nand_resource __maybe_unused = {
-                .name           = "NAND flash control",
-                .start          = EXCITE_PHYS_NAND,
-                .end            = EXCITE_PHYS_NAND + EXCITE_SIZE_NAND - 1,
-                .flags          = IORESOURCE_MEM,
-                .parent         = NULL,
-                .sibling        = NULL,
-                .child          = NULL
-        },
-        excite_titan_resource __maybe_unused = {
-                .name           = "TITAN registers",
-                .start          = EXCITE_PHYS_TITAN,
-                .end            = EXCITE_PHYS_TITAN + EXCITE_SIZE_TITAN - 1,
-                .flags          = IORESOURCE_MEM,
-                .parent         = NULL,
-                .sibling        = NULL,
-                .child          = NULL
-        };
-
-
-
-static void adjust_resources(struct resource *res, unsigned int n)
-{
-        struct resource *p;
-        const unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM
-                                   | IORESOURCE_IRQ | IORESOURCE_DMA;
-
-        for (p = res; p < res + n; p++) {
-                const struct resource * const parent = p->parent;
-                if (parent) {
-                        p->start += parent->start;
-                        p->end   += parent->start;
-                        p->flags =  parent->flags & mask;
-                }
-        }
-}
-
-
-
-#if defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE)
-static struct resource xicap_rsrc[] = {
-        RINIT(0x4840, 0x486f, XICAP_RESOURCE_FIFO_RX, &excite_titan_resource),
-        RINIT(0x4940, 0x494b, XICAP_RESOURCE_FIFO_TX, &excite_titan_resource),
-        RINIT(0x5040, 0x5127, XICAP_RESOURCE_XDMA, &excite_titan_resource),
-        RINIT(0x1000, 0x112f, XICAP_RESOURCE_PKTPROC, &excite_titan_resource),
-        RINIT(0x1100, 0x110f, XICAP_RESOURCE_PKT_STREAM, &excite_fpga_resource),
-        RINIT(0x0800, 0x0bff, XICAP_RESOURCE_DMADESC, &excite_scram_resource),
-        RINIT(slice_xicap, slice_xicap, XICAP_RESOURCE_GPI_SLICE, &excite_gpislice_resource),
-        RINIT(0x0100, 0x02ff, XICAP_RESOURCE_FIFO_BLK, &excite_fifomem_resource),
-        RINIT_IRQ(TITAN_IRQ,  XICAP_RESOURCE_IRQ)
-};
-
-static struct platform_device xicap_pdev = {
-        .name           = XICAP_NAME,
-        .id             = XICAP_UNIT,
-        .num_resources  = ARRAY_SIZE(xicap_rsrc),
-        .resource       = xicap_rsrc
-};
-
-/*
- * Create a platform device for the GPI port that receives the
- * image data from the embedded camera.
- */
-static int __init xicap_devinit(void)
-{
-        unsigned long tend;
-        u32 reg;
-        int retval;
-
-        adjust_resources(xicap_rsrc, ARRAY_SIZE(xicap_rsrc));
-
-        /* Power up the slice and configure it. */
-        reg = titan_readl(CPTC1R);
-        reg &= ~(0x11100 << slice_xicap);
-        titan_writel(reg, CPTC1R);
-
-        /* Enable slice & DLL. */
-        reg= titan_readl(CPRR);
-        reg &= ~(0x00030003 << (slice_xicap * 2));
-        titan_writel(reg, CPRR);
-
-        /* Wait for DLLs to lock */
-        tend = jiffies + DLL_TIMEOUT * HZ;
-        while (time_before(jiffies, tend)) {
-                if (!(~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))))
-                        break;
-                yield();
-        }
-
-        if (~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))) {
-                printk(KERN_ERR "%s: DLL not locked after %u seconds\n",
-                       xicap_pdev.name, DLL_TIMEOUT);
-                retval = -ETIME;
-        } else {
-                /* Register platform device */
-                retval = platform_device_register(&xicap_pdev);
-        }
-
-        return retval;
-}
-
-device_initcall(xicap_devinit);
-#endif /* defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE) */
-
-
-
-#if defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE)
-static struct resource wdt_rsrc[] = {
-        RINIT(0, 0, WDT_RESOURCE_COUNTER, &excite_ctr_resource),
-        RINIT(0x0084, 0x008f, WDT_RESOURCE_REGS, &excite_titan_resource),
-        RINIT_IRQ(TITAN_IRQ,  WDT_RESOURCE_IRQ)
-};
-
-static struct platform_device wdt_pdev = {
-        .name           = WDT_NAME,
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(wdt_rsrc),
-        .resource       = wdt_rsrc
-};
-
-/*
- * Create a platform device for the GPI port that receives the
- * image data from the embedded camera.
- */
-static int __init wdt_devinit(void)
-{
-        adjust_resources(wdt_rsrc, ARRAY_SIZE(wdt_rsrc));
-        return platform_device_register(&wdt_pdev);
-}
-
-device_initcall(wdt_devinit);
-#endif /* defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE) */
-
-
-
-static struct resource excite_nandflash_rsrc[] = {
-        RINIT(0x2000, 0x201f, EXCITE_NANDFLASH_RESOURCE_REGS,  &excite_nand_resource)
-};
-
-static struct platform_device excite_nandflash_pdev = {
-        .name           = "excite_nand",
-        .id             = NAND_UNIT,
-        .num_resources  = ARRAY_SIZE(excite_nandflash_rsrc),
-        .resource       = excite_nandflash_rsrc
-};
-
-/*
- * Create a platform device for the access to the nand-flash
- * port
- */
-static int __init excite_nandflash_devinit(void)
-{
-        adjust_resources(excite_nandflash_rsrc, ARRAY_SIZE(excite_nandflash_rsrc));
-
-        /* nothing to be done here */
-
-        /* Register platform device */
-        return platform_device_register(&excite_nandflash_pdev);
-}
-
-device_initcall(excite_nandflash_devinit);
-
-
-
-static struct resource iodev_rsrc[] = {
-        RINIT_IRQ(FPGA1_IRQ,  IODEV_RESOURCE_IRQ)
-};
-
-static struct platform_device io_pdev = {
-        .name           = IODEV_NAME,
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(iodev_rsrc),
-        .resource       = iodev_rsrc
-};
-
-/*
- * Create a platform device for the external I/O ports.
- */
-static int __init io_devinit(void)
-{
-        adjust_resources(iodev_rsrc, ARRAY_SIZE(iodev_rsrc));
-        return platform_device_register(&io_pdev);
-}
-
-device_initcall(io_devinit);
-
-
-
-
-#if defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE)
-static struct resource rm9k_ge_rsrc[] = {
-        RINIT(0x2200, 0x27ff, RM9K_GE_RESOURCE_MAC, &excite_titan_resource),
-        RINIT(0x1800, 0x1fff, RM9K_GE_RESOURCE_MSTAT, &excite_titan_resource),
-        RINIT(0x2000, 0x212f, RM9K_GE_RESOURCE_PKTPROC, &excite_titan_resource),
-        RINIT(0x5140, 0x5227, RM9K_GE_RESOURCE_XDMA, &excite_titan_resource),
-        RINIT(0x4870, 0x489f, RM9K_GE_RESOURCE_FIFO_RX, &excite_titan_resource),
-        RINIT(0x494c, 0x4957, RM9K_GE_RESOURCE_FIFO_TX, &excite_titan_resource),
-        RINIT(0x0000, 0x007f, RM9K_GE_RESOURCE_FIFOMEM_RX, &excite_fifomem_resource),
-        RINIT(0x0080, 0x00ff, RM9K_GE_RESOURCE_FIFOMEM_TX, &excite_fifomem_resource),
-        RINIT(0x0180, 0x019f, RM9K_GE_RESOURCE_PHY, &excite_titan_resource),
-        RINIT(0x0000, 0x03ff, RM9K_GE_RESOURCE_DMADESC_RX, &excite_scram_resource),
-        RINIT(0x0400, 0x07ff, RM9K_GE_RESOURCE_DMADESC_TX, &excite_scram_resource),
-        RINIT(slice_eth, slice_eth, RM9K_GE_RESOURCE_GPI_SLICE, &excite_gpislice_resource),
-        RINIT(0, 0, RM9K_GE_RESOURCE_MDIO_CHANNEL, &excite_mdio_channel_resource),
-        RINIT_IRQ(TITAN_IRQ,  RM9K_GE_RESOURCE_IRQ_MAIN),
-        RINIT_IRQ(PHY_IRQ, RM9K_GE_RESOURCE_IRQ_PHY)
-};
-
-static struct platform_device rm9k_ge_pdev = {
-        .name           = RM9K_GE_NAME,
-        .id             = RM9K_GE_UNIT,
-        .num_resources  = ARRAY_SIZE(rm9k_ge_rsrc),
-        .resource       = rm9k_ge_rsrc
-};
-
-
-
-/*
- * Create a platform device for the Ethernet port.
- */
-static int __init rm9k_ge_devinit(void)
-{
-        u32 reg;
-
-        adjust_resources(rm9k_ge_rsrc, ARRAY_SIZE(rm9k_ge_rsrc));
-
-        /* Power up the slice and configure it. */
-        reg = titan_readl(CPTC1R);
-        reg &= ~(0x11000 << slice_eth);
-        reg |= 0x100 << slice_eth;
-        titan_writel(reg, CPTC1R);
-
-        /* Take the MAC out of reset, reset the DLLs. */
-        reg = titan_readl(CPRR);
-        reg &= ~(0x00030000 << (slice_eth * 2));
-        reg |= 0x3 << (slice_eth * 2);
-        titan_writel(reg, CPRR);
-
-        return platform_device_register(&rm9k_ge_pdev);
-}
-
-device_initcall(rm9k_ge_devinit);
-#endif /* defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE) */
-
-
-
-static int __init excite_setup_devs(void)
-{
-        int res;
-        u32 reg;
-
-        /* Enable xdma and fifo interrupts */
-        reg = titan_readl(0x0050);
-        titan_writel(reg | 0x18000000, 0x0050);
-
-        res = request_resource(&iomem_resource, &excite_titan_resource);
-        if (res)
-                return res;
-        res = request_resource(&iomem_resource, &excite_scram_resource);
-        if (res)
-                return res;
-        res = request_resource(&iomem_resource, &excite_fpga_resource);
-        if (res)
-                return res;
-        res = request_resource(&iomem_resource, &excite_nand_resource);
-        if (res)
-                return res;
-        excite_fpga_resource.flags = excite_fpga_resource.parent->flags &
-                                   ( IORESOURCE_IO | IORESOURCE_MEM
-                                   | IORESOURCE_IRQ | IORESOURCE_DMA);
-        excite_nand_resource.flags = excite_nand_resource.parent->flags &
-                                   ( IORESOURCE_IO | IORESOURCE_MEM
-                                   | IORESOURCE_IRQ | IORESOURCE_DMA);
-
-        return 0;
-}
-
-arch_initcall(excite_setup_devs);
-
diff --git a/arch/mips/basler/excite/excite_iodev.c b/arch/mips/basler/excite/excite_iodev.c
deleted file mode 100644
index 938b1d0b7652..000000000000
--- a/arch/mips/basler/excite/excite_iodev.c
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- *  Copyright (C) 2005 by Basler Vision Technologies AG
- *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/compiler.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/wait.h>
-#include <linux/poll.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/miscdevice.h>
-#include <linux/smp_lock.h>
-
-#include "excite_iodev.h"
-
-
-
-static const struct resource *iodev_get_resource(struct platform_device *, const char *, unsigned int);
-static int __init iodev_probe(struct platform_device *);
-static int __exit iodev_remove(struct platform_device *);
-static int iodev_open(struct inode *, struct file *);
-static int iodev_release(struct inode *, struct file *);
-static ssize_t iodev_read(struct file *, char __user *, size_t s, loff_t *);
-static unsigned int iodev_poll(struct file *, struct poll_table_struct *);
-static irqreturn_t iodev_irqhdl(int, void *);
-
-
-
-static const char iodev_name[] = "iodev";
-static unsigned int iodev_irq;
-static DECLARE_WAIT_QUEUE_HEAD(wq);
-
-
-
-static const struct file_operations fops =
-{
-        .owner          = THIS_MODULE,
-        .open           = iodev_open,
-        .release        = iodev_release,
-        .read           = iodev_read,
-        .poll           = iodev_poll
-};
-
-static struct miscdevice miscdev =
-{
-        .minor          = MISC_DYNAMIC_MINOR,
-        .name           = iodev_name,
-        .fops           = &fops
-};
-
-static struct platform_driver iodev_driver = {
-        .driver = {
-                .name           = iodev_name,
-                .owner          = THIS_MODULE,
-        },
-        .probe          = iodev_probe,
-        .remove         = __devexit_p(iodev_remove),
-};
-
-
-
-static const struct resource *
-iodev_get_resource(struct platform_device *pdv, const char *name,
-                     unsigned int type)
-{
-        char buf[80];
-        if (snprintf(buf, sizeof buf, "%s_0", name) >= sizeof buf)
-                return NULL;
-        return platform_get_resource_byname(pdv, type, buf);
-}
-
-
-
-/* No hotplugging on the platform bus - use __init */
-static int __init iodev_probe(struct platform_device *dev)
-{
-        const struct resource * const ri =
-                iodev_get_resource(dev, IODEV_RESOURCE_IRQ, IORESOURCE_IRQ);
-
-        if (unlikely(!ri))
-                return -ENXIO;
-
-        iodev_irq = ri->start;
-        return misc_register(&miscdev);
-}
-
-
-
-static int __exit iodev_remove(struct platform_device *dev)
-{
-        return misc_deregister(&miscdev);
-}
-
-static int iodev_open(struct inode *i, struct file *f)
-{
-        int ret;
-
-        ret = request_irq(iodev_irq, iodev_irqhdl, IRQF_DISABLED,
-                           iodev_name, &miscdev);
-
-        return ret;
-}
-
-static int iodev_release(struct inode *i, struct file *f)
-{
-        free_irq(iodev_irq, &miscdev);
-        return 0;
-}
-
-
-
-
-static ssize_t
-iodev_read(struct file *f, char __user *d, size_t s, loff_t *o)
-{
-        ssize_t ret;
-        DEFINE_WAIT(w);
-
-        prepare_to_wait(&wq, &w, TASK_INTERRUPTIBLE);
-        if (!signal_pending(current))
-                schedule();
-        ret = signal_pending(current) ? -ERESTARTSYS : 0;
-        finish_wait(&wq, &w);
-        return ret;
-}
-
-
-static unsigned int iodev_poll(struct file *f, struct poll_table_struct *p)
-{
-        poll_wait(f, &wq, p);
-        return POLLOUT | POLLWRNORM;
-}
-
-static irqreturn_t iodev_irqhdl(int irq, void *ctxt)
-{
-        wake_up(&wq);
-
-        return IRQ_HANDLED;
-}
-
-static int __init iodev_init_module(void)
-{
-        return platform_driver_register(&iodev_driver);
-}
-
-
-
-static void __exit iodev_cleanup_module(void)
-{
-        platform_driver_unregister(&iodev_driver);
-}
-
-module_init(iodev_init_module);
-module_exit(iodev_cleanup_module);
-
-
-
-MODULE_AUTHOR("Thomas Koeller <thomas.koeller@baslerweb.com>");
-MODULE_DESCRIPTION("Basler eXcite i/o interrupt handler");
-MODULE_VERSION("0.0");
-MODULE_LICENSE("GPL");
diff --git a/arch/mips/basler/excite/excite_iodev.h b/arch/mips/basler/excite/excite_iodev.h
deleted file mode 100644
index cbfbb5d2ee62..000000000000
--- a/arch/mips/basler/excite/excite_iodev.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef __EXCITE_IODEV_H__
-#define __EXCITE_IODEV_H__
-
-/* Device name */
-#define IODEV_NAME              "iodev"
-
-/* Resource names */
-#define IODEV_RESOURCE_IRQ      "excite_iodev_irq"
-
-#endif /* __EXCITE_IODEV_H__ */
diff --git a/arch/mips/basler/excite/excite_irq.c b/arch/mips/basler/excite/excite_irq.c
deleted file mode 100644
index 934e0a6b1011..000000000000
--- a/arch/mips/basler/excite/excite_irq.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- *  Copyright (C) by Basler Vision Technologies AG
- *  Author: Thomas Koeller <thomas.koeller@baslereb.com>
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/kernel_stat.h>
-#include <linux/module.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/timex.h>
-#include <linux/slab.h>
-#include <linux/random.h>
-#include <linux/bitops.h>
-#include <asm/bootinfo.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/irq_cpu.h>
-#include <asm/mipsregs.h>
-#include <asm/system.h>
-#include <asm/rm9k-ocd.h>
-
-#include <excite.h>
-
-extern asmlinkage void excite_handle_int(void);
-
-/*
- * Initialize the interrupt handler
- */
-void __init arch_init_irq(void)
-{
-        mips_cpu_irq_init();
-        rm7k_cpu_irq_init();
-        rm9k_cpu_irq_init();
-}
-
-asmlinkage void plat_irq_dispatch(void)
-{
-        const u32
-                interrupts = read_c0_cause() >> 8,
-                mask = ((read_c0_status() >> 8) & 0x000000ff) |
-                       (read_c0_intcontrol() & 0x0000ff00),
-                pending = interrupts & mask;
-        u32 msgintflags, msgintmask, msgint;
-
-        /* process timer interrupt */
-        if (pending & (1 << TIMER_IRQ)) {
-                do_IRQ(TIMER_IRQ);
-                return;
-        }
-
-        /* Process PCI interrupts */
-#if USB_IRQ < 10
-        msgintflags = ocd_readl(INTP0Status0 + (USB_MSGINT / 0x20 * 0x10));
-        msgintmask  = ocd_readl(INTP0Mask0 + (USB_MSGINT / 0x20 * 0x10));
-        msgint      = msgintflags & msgintmask & (0x1 << (USB_MSGINT % 0x20));
-        if ((pending & (1 << USB_IRQ)) && msgint) {
-#else
-        if (pending & (1 << USB_IRQ)) {
-#endif
-                do_IRQ(USB_IRQ);
-                return;
-        }
-
-        /* Process TITAN interrupts */
-        msgintflags = ocd_readl(INTP0Status0 + (TITAN_MSGINT / 0x20 * 0x10));
-        msgintmask  = ocd_readl(INTP0Mask0 + (TITAN_MSGINT / 0x20 * 0x10));
-        msgint      = msgintflags & msgintmask & (0x1 << (TITAN_MSGINT % 0x20));
-        if ((pending & (1 << TITAN_IRQ)) && msgint) {
-                ocd_writel(msgint, INTP0Clear0 + (TITAN_MSGINT / 0x20 * 0x10));
-                do_IRQ(TITAN_IRQ);
-                return;
-        }
-
-        /* Process FPGA line #0 interrupts */
-        msgintflags = ocd_readl(INTP0Status0 + (FPGA0_MSGINT / 0x20 * 0x10));
-        msgintmask  = ocd_readl(INTP0Mask0 + (FPGA0_MSGINT / 0x20 * 0x10));
-        msgint      = msgintflags & msgintmask & (0x1 << (FPGA0_MSGINT % 0x20));
-        if ((pending & (1 << FPGA0_IRQ)) && msgint) {
-                do_IRQ(FPGA0_IRQ);
-                return;
-        }
-
-        /* Process FPGA line #1 interrupts */
-        msgintflags = ocd_readl(INTP0Status0 + (FPGA1_MSGINT / 0x20 * 0x10));
-        msgintmask  = ocd_readl(INTP0Mask0 + (FPGA1_MSGINT / 0x20 * 0x10));
-        msgint      = msgintflags & msgintmask & (0x1 << (FPGA1_MSGINT % 0x20));
-        if ((pending & (1 << FPGA1_IRQ)) && msgint) {
-                do_IRQ(FPGA1_IRQ);
-                return;
-        }
-
-        /* Process PHY interrupts */
-        msgintflags = ocd_readl(INTP0Status0 + (PHY_MSGINT / 0x20 * 0x10));
-        msgintmask  = ocd_readl(INTP0Mask0 + (PHY_MSGINT / 0x20 * 0x10));
-        msgint      = msgintflags & msgintmask & (0x1 << (PHY_MSGINT % 0x20));
-        if ((pending & (1 << PHY_IRQ)) && msgint) {
-                do_IRQ(PHY_IRQ);
-                return;
-        }
-
-        /* Process spurious interrupts */
-        spurious_interrupt();
-}
diff --git a/arch/mips/basler/excite/excite_procfs.c b/arch/mips/basler/excite/excite_procfs.c
deleted file mode 100644
index 08923e6825b5..000000000000
--- a/arch/mips/basler/excite/excite_procfs.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- *  Copyright (C) 2004, 2005 by Basler Vision Technologies AG
- *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
- *
- *  Procfs support for Basler eXcite
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/module.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-#include <linux/stat.h>
-#include <asm/page.h>
-#include <asm/io.h>
-#include <asm/system.h>
-#include <asm/rm9k-ocd.h>
-
-#include <excite.h>
-
-static int excite_unit_id_proc_show(struct seq_file *m, void *v)
-{
-        seq_printf(m, "%06x", unit_id);
-        return 0;
-}
-
-static int excite_unit_id_proc_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, excite_unit_id_proc_show, NULL);
-}
-
-static const struct file_operations excite_unit_id_proc_fops = {
-        .owner          = THIS_MODULE,
-        .open           = excite_unit_id_proc_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-};
-
-static int
-excite_bootrom_read(char *page, char **start, off_t off, int count,
-                  int *eof, void *data)
-{
-        void __iomem * src;
-
-        if (off >= EXCITE_SIZE_BOOTROM) {
-                *eof = 1;
-                return 0;
-        }
-
-        if ((off + count) > EXCITE_SIZE_BOOTROM)
-                count = EXCITE_SIZE_BOOTROM - off;
-
-        src = ioremap(EXCITE_PHYS_BOOTROM + off, count);
-        if (src) {
-                memcpy_fromio(page, src, count);
-                iounmap(src);
-                *start = page;
-        } else {
-                count = -ENOMEM;
-        }
-
-        return count;
-}
-
-void excite_procfs_init(void)
-{
-        /* Create & populate /proc/excite */
-        struct proc_dir_entry * const pdir = proc_mkdir("excite", NULL);
-        if (pdir) {
-                struct proc_dir_entry * e;
-
-                e = proc_create("unit_id", S_IRUGO, pdir,
-                                &excite_unit_id_proc_fops);
-                if (e) e->size = 6;
-
-                e = create_proc_read_entry("bootrom", S_IRUGO, pdir,
-                                           excite_bootrom_read, NULL);
-                if (e) e->size = EXCITE_SIZE_BOOTROM;
-        }
-}
diff --git a/arch/mips/basler/excite/excite_prom.c b/arch/mips/basler/excite/excite_prom.c
deleted file mode 100644
index 68d8bc597e34..000000000000
--- a/arch/mips/basler/excite/excite_prom.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- *  Copyright (C) 2004, 2005 by Thomas Koeller (thomas.koeller@baslerweb.com)
- *  Based on the PMC-Sierra Yosemite board support by Ralf Baechle and
- *  Manish Lachwani.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/init.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/delay.h>
-#include <linux/smp.h>
-#include <linux/module.h>
-#include <asm/io.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-#include <asm/reboot.h>
-#include <asm/system.h>
-#include <asm/bootinfo.h>
-#include <asm/string.h>
-
-#include <excite.h>
-
-/* This struct is used by Redboot to pass arguments to the kernel */
-typedef struct
-{
-        char *name;
-        char *val;
-} t_env_var;
-
-struct parmblock {
-        t_env_var memsize;
-        t_env_var modetty0;
-        t_env_var ethaddr;
-        t_env_var env_end;
-        char *argv[2];
-        char text[0];
-};
-
-static unsigned int prom_argc;
-static const char ** prom_argv;
-static const t_env_var * prom_env;
-
-static void prom_halt(void) __attribute__((noreturn));
-static void prom_exit(void) __attribute__((noreturn));
-
-
-
-const char *get_system_type(void)
-{
-        return "Basler eXcite";
-}
-
-/*
- * Halt the system
- */
-static void prom_halt(void)
-{
-        printk(KERN_NOTICE "\n** System halted.\n");
-        while (1)
-                asm volatile (
-                        "\t.set\tmips3\n"
-                        "\twait\n"
-                        "\t.set\tmips0\n"
-                );
-}
-
-/*
- * Reset the CPU and re-enter Redboot
- */
-static void prom_exit(void)
-{
-        unsigned int i;
-        volatile unsigned char * const flg =
-                (volatile unsigned char *) (EXCITE_ADDR_FPGA + EXCITE_FPGA_DPR);
-
-        /* Clear the watchdog reset flag, set the reboot flag */
-        *flg &= ~0x01;
-        *flg |= 0x80;
-
-        for (i = 0; i < 10; i++) {
-                *(volatile unsigned char *)  (EXCITE_ADDR_FPGA + EXCITE_FPGA_SYSCTL) = 0x02;
-                iob();
-                mdelay(1000);
-        }
-
-        printk(KERN_NOTICE "Reset failed\n");
-        prom_halt();
-}
-
-static const char __init *prom_getenv(char *name)
-{
-        const t_env_var * p;
-        for (p = prom_env; p->name != NULL; p++)
-                if(strcmp(name, p->name) == 0)
-                        break;
-        return p->val;
-}
-
-/*
- * Init routine which accepts the variables from Redboot
- */
-void __init prom_init(void)
-{
-        const struct parmblock * const pb = (struct parmblock *) fw_arg2;
-
-        prom_argc = fw_arg0;
-        prom_argv = (const char **) fw_arg1;
-        prom_env = &pb->memsize;
-
-        /* Callbacks for halt, restart */
-        _machine_restart = (void (*)(char *)) prom_exit;
-        _machine_halt = prom_halt;
-
-#ifdef CONFIG_32BIT
-        /* copy command line */
-        strcpy(arcs_cmdline, prom_argv[1]);
-        memsize = simple_strtol(prom_getenv("memsize"), NULL, 16);
-        strcpy(modetty, prom_getenv("modetty0"));
-#endif /* CONFIG_32BIT */
-
-#ifdef CONFIG_64BIT
-#       error 64 bit support not implemented
-#endif /* CONFIG_64BIT */
-}
-
-/* This is called from free_initmem(), so we need to provide it */
-void __init prom_free_prom_memory(void)
-{
-        /* Nothing to do */
-}
diff --git a/arch/mips/basler/excite/excite_setup.c b/arch/mips/basler/excite/excite_setup.c
deleted file mode 100644
index d66b3b8edf2a..000000000000
--- a/arch/mips/basler/excite/excite_setup.c
+++ /dev/null
@@ -1,302 +0,0 @@
-/*
- *  Copyright (C) 2004, 2005 by Basler Vision Technologies AG
- *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
- *  Based on the PMC-Sierra Yosemite board support by Ralf Baechle and
- *  Manish Lachwani.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <linux/tty.h>
-#include <linux/serial_core.h>
-#include <linux/serial.h>
-#include <linux/serial_8250.h>
-#include <linux/ioport.h>
-#include <linux/spinlock.h>
-#include <asm/bootinfo.h>
-#include <asm/mipsregs.h>
-#include <asm/pgtable-32.h>
-#include <asm/io.h>
-#include <asm/time.h>
-#include <asm/rm9k-ocd.h>
-
-#include <excite.h>
-
-#define TITAN_UART_CLK  25000000
-
-#if 1
-/* normal serial port assignment */
-#define REGBASE_SER0    0x0208
-#define REGBASE_SER1    0x0238
-#define MASK_SER0       0x1
-#define MASK_SER1       0x2
-#else
-/* serial ports swapped */
-#define REGBASE_SER0    0x0238
-#define REGBASE_SER1    0x0208
-#define MASK_SER0       0x2
-#define MASK_SER1       0x1
-#endif
-
-unsigned long memsize;
-char modetty[30];
-unsigned int titan_irq = TITAN_IRQ;
-static void __iomem * ctl_regs;
-u32 unit_id;
-
-volatile void __iomem * const ocd_base = (void *) (EXCITE_ADDR_OCD);
-volatile void __iomem * const titan_base = (void *) (EXCITE_ADDR_TITAN);
-
-/* Protect access to shared GPI registers */
-DEFINE_SPINLOCK(titan_lock);
-int titan_irqflags;
-
-
-/*
- * The eXcite platform uses the alternate timer interrupt
- *
- * Fixme: At the time of this writing cevt-r4k.c doesn't yet know about how
- * to handle the alternate timer interrupt of the RM9000.
- */
-void __init plat_time_init(void)
-{
-        const u32 modebit5 = ocd_readl(0x00e4);
-        unsigned int mult = ((modebit5 >> 11) & 0x1f) + 2;
-        unsigned int div = ((modebit5 >> 16) & 0x1f) + 2;
-
-        if (div == 33)
-                div = 1;
-        mips_hpt_frequency = EXCITE_CPU_EXT_CLOCK * mult / div / 2;
-}
-
-static int __init excite_init_console(void)
-{
-#if defined(CONFIG_SERIAL_8250)
-        static __initdata char serr[] =
-                KERN_ERR "Serial port #%u setup failed\n";
-        struct uart_port up;
-
-        /* Take the DUART out of reset */
-        titan_writel(0x00ff1cff, CPRR);
-
-#if (CONFIG_SERIAL_8250_NR_UARTS > 1)
-        /* Enable both ports */
-        titan_writel(MASK_SER0 | MASK_SER1, UACFG);
-#else
-        /* Enable port #0 only */
-        titan_writel(MASK_SER0, UACFG);
-#endif
-
-        /*
-         * Set up serial port #0. Do not use autodetection; the result is
-         * not what we want.
-         */
-        memset(&up, 0, sizeof(up));
-        up.membase      = (char *) titan_addr(REGBASE_SER0);
-        up.irq          = TITAN_IRQ;
-        up.uartclk      = TITAN_UART_CLK;
-        up.regshift     = 0;
-        up.iotype       = UPIO_RM9000;
-        up.type         = PORT_RM9000;
-        up.flags        = UPF_SHARE_IRQ;
-        up.line         = 0;
-        if (early_serial_setup(&up))
-                printk(serr, up.line);
-
-#if CONFIG_SERIAL_8250_NR_UARTS > 1
-        /* And now for port #1. */
-        up.membase      = (char *) titan_addr(REGBASE_SER1);
-        up.line         = 1;
-        if (early_serial_setup(&up))
-                printk(serr, up.line);
-#endif /* CONFIG_SERIAL_8250_NR_UARTS > 1 */
-#else
-        /* Leave the DUART in reset */
-        titan_writel(0x00ff3cff, CPRR);
-#endif  /* defined(CONFIG_SERIAL_8250) */
-
-        return 0;
-}
-
-static int __init excite_platform_init(void)
-{
-        unsigned int i;
-        unsigned char buf[3];
-        u8 reg;
-        void __iomem * dpr;
-
-        /* BIU buffer allocations */
-        ocd_writel(8, CPURSLMT);        /* CPU */
-        titan_writel(4, CPGRWL);        /* GPI / Ethernet */
-
-        /* Map control registers located in FPGA */
-        ctl_regs = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_SYSCTL, 16);
-        if (!ctl_regs)
-                panic("eXcite: failed to map platform control registers\n");
-        memcpy_fromio(buf, ctl_regs + 2, ARRAY_SIZE(buf));
-        unit_id = buf[0] | (buf[1] << 8) | (buf[2] << 16);
-
-        /* Clear the reboot flag */
-        dpr = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_DPR, 1);
-        reg = __raw_readb(dpr);
-        __raw_writeb(reg & 0x7f, dpr);
-        iounmap(dpr);
-
-        /* Interrupt controller setup */
-        for (i = INTP0Status0; i < INTP0Status0 + 0x80; i += 0x10) {
-                ocd_writel(0x00000000, i + 0x04);
-                ocd_writel(0xffffffff, i + 0x0c);
-        }
-        ocd_writel(0x2, NMICONFIG);
-
-        ocd_writel(0x1 << (TITAN_MSGINT % 0x20),
-                   INTP0Mask0 + (0x10 * (TITAN_MSGINT / 0x20)));
-        ocd_writel((0x1 << (FPGA0_MSGINT % 0x20))
-                   | ocd_readl(INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20))),
-                   INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20)));
-        ocd_writel((0x1 << (FPGA1_MSGINT % 0x20))
-                   | ocd_readl(INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20))),
-                   INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20)));
-        ocd_writel((0x1 << (PHY_MSGINT % 0x20))
-                   | ocd_readl(INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20))),
-                   INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20)));
-#if USB_IRQ < 10
-        ocd_writel((0x1 << (USB_MSGINT % 0x20))
-                   | ocd_readl(INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20))),
-                   INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20)));
-#endif
-        /* Enable the packet FIFO, XDMA and XDMA arbiter */
-        titan_writel(0x00ff18ff, CPRR);
-
-        /*
-         * Set up the PADMUX. Power down all ethernet slices,
-         * they will be powered up and configured at device startup.
-         */
-        titan_writel(0x00878206, CPTC1R);
-        titan_writel(0x00001100, CPTC0R); /* latch PADMUX, enable WCIMODE */
-
-        /* Reset and enable the FIFO block */
-        titan_writel(0x00000001, SDRXFCIE);
-        titan_writel(0x00000001, SDTXFCIE);
-        titan_writel(0x00000100, SDRXFCIE);
-        titan_writel(0x00000000, SDTXFCIE);
-
-        /*
-         * Initialize the common interrupt shared by all components of
-         * the GPI/Ethernet subsystem.
-         */
-        titan_writel((EXCITE_PHYS_OCD >> 12), CPCFG0);
-        titan_writel(TITAN_MSGINT, CPCFG1);
-
-        /*
-         * XDMA configuration.
-         * In order for the XDMA to be sharable among multiple drivers,
-         * the setup must be done here in the platform. The reason is that
-         * this setup can only be done while the XDMA is in reset. If this
-         * were done in a driver, it would interrupt all other drivers
-         * using the XDMA.
-         */
-        titan_writel(0x80021dff, GXCFG);        /* XDMA reset */
-        titan_writel(0x00000000, CPXCISRA);
-        titan_writel(0x00000000, CPXCISRB);     /* clear pending interrupts */
-#if defined(CONFIG_HIGHMEM)
-#       error change for HIGHMEM support!
-#else
-        titan_writel(0x00000000, GXDMADRPFX);   /* buffer address prefix */
-#endif
-        titan_writel(0, GXDMA_DESCADR);
-
-        for (i = 0x5040; i <= 0x5300; i += 0x0040)
-                titan_writel(0x80080000, i);    /* reset channel */
-
-        titan_writel((0x1 << 29)                        /* no sparse tx descr. */
-                     | (0x1 << 28)                      /* no sparse rx descr. */
-                     | (0x1 << 23) | (0x1 << 24)        /* descriptor coherency */
-                     | (0x1 << 21) | (0x1 << 22)        /* data coherency */
-                     | (0x1 << 17)
-                     | 0x1dff,
-                     GXCFG);
-
-#if defined(CONFIG_SMP)
-#       error No SMP support
-#else
-        /* All interrupts go to core #0 only. */
-        titan_writel(0x1f007fff, CPDST0A);
-        titan_writel(0x00000000, CPDST0B);
-        titan_writel(0x0000ff3f, CPDST1A);
-        titan_writel(0x00000000, CPDST1B);
-        titan_writel(0x00ffffff, CPXDSTA);
-        titan_writel(0x00000000, CPXDSTB);
-#endif
-
-        /* Enable DUART interrupts, disable everything else. */
-        titan_writel(0x04000000, CPGIG0ER);
-        titan_writel(0x000000c0, CPGIG1ER);
-
-        excite_procfs_init();
-        return 0;
-}
-
-void __init plat_mem_setup(void)
-{
-        volatile u32 * const boot_ocd_base = (u32 *) 0xbf7fc000;
-
-        /* Announce RAM to system */
-        add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
-
-        /* Set up the peripheral address map */
-        *(boot_ocd_base + (LKB9 / sizeof(u32))) = 0;
-        *(boot_ocd_base + (LKB10 / sizeof(u32))) = 0;
-        *(boot_ocd_base + (LKB11 / sizeof(u32))) = 0;
-        *(boot_ocd_base + (LKB12 / sizeof(u32))) = 0;
-        wmb();
-        *(boot_ocd_base + (LKB0 / sizeof(u32))) = EXCITE_PHYS_OCD >> 4;
-        wmb();
-
-        ocd_writel((EXCITE_PHYS_TITAN >> 4) | 0x1UL, LKB5);
-        ocd_writel(((EXCITE_SIZE_TITAN >> 4) & 0x7fffff00) - 0x100, LKM5);
-        ocd_writel((EXCITE_PHYS_SCRAM >> 4) | 0x1UL, LKB13);
-        ocd_writel(((EXCITE_SIZE_SCRAM >> 4) & 0xffffff00) - 0x100, LKM13);
-
-        /* Local bus slot #0 */
-        ocd_writel(0x00040510, LDP0);
-        ocd_writel((EXCITE_PHYS_BOOTROM >> 4) | 0x1UL, LKB9);
-        ocd_writel(((EXCITE_SIZE_BOOTROM >> 4) & 0x03ffff00) - 0x100, LKM9);
-
-        /* Local bus slot #2 */
-        ocd_writel(0x00000330, LDP2);
-        ocd_writel((EXCITE_PHYS_FPGA >> 4) | 0x1, LKB11);
-        ocd_writel(((EXCITE_SIZE_FPGA >> 4) - 0x100) & 0x03ffff00, LKM11);
-
-        /* Local bus slot #3 */
-        ocd_writel(0x00123413, LDP3);
-        ocd_writel((EXCITE_PHYS_NAND >> 4) | 0x1, LKB12);
-        ocd_writel(((EXCITE_SIZE_NAND >> 4) - 0x100) & 0x03ffff00, LKM12);
-}
-
-
-
-console_initcall(excite_init_console);
-arch_initcall(excite_platform_init);
-
-EXPORT_SYMBOL(titan_lock);
-EXPORT_SYMBOL(titan_irqflags);
-EXPORT_SYMBOL(titan_irq);
-EXPORT_SYMBOL(ocd_base);
-EXPORT_SYMBOL(titan_base);
diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c
index fb284c3b2cff..c51405e57921 100644
--- a/arch/mips/bcm47xx/prom.c
+++ b/arch/mips/bcm47xx/prom.c
@@ -100,11 +100,11 @@ static __init void prom_init_console(void)
 
 static __init void prom_init_cmdline(void)
 {
-        static char buf[CL_SIZE] __initdata;
+        static char buf[COMMAND_LINE_SIZE] __initdata;
 
         /* Get the kernel command line from CFE */
-        if (cfe_getenv("LINUX_CMDLINE", buf, CL_SIZE) >= 0) {
-                buf[CL_SIZE-1] = 0;
+        if (cfe_getenv("LINUX_CMDLINE", buf, COMMAND_LINE_SIZE) >= 0) {
+                buf[COMMAND_LINE_SIZE - 1] = 0;
                 strcpy(arcs_cmdline, buf);
         }
 
@@ -112,13 +112,13 @@ static __init void prom_init_cmdline(void)
          * as CFE is not available anymore later in the boot process. */
         if ((strstr(arcs_cmdline, "console=")) == NULL) {
                 /* Try to read the default serial port used by CFE */
-                if ((cfe_getenv("BOOT_CONSOLE", buf, CL_SIZE) < 0)
+                if ((cfe_getenv("BOOT_CONSOLE", buf, COMMAND_LINE_SIZE) < 0)
                     || (strncmp("uart", buf, 4)))
                         /* Default to uart0 */
                         strcpy(buf, "uart0");
 
                 /* Compute the new command line */
-                snprintf(arcs_cmdline, CL_SIZE, "%s console=ttyS%c,115200",
+                snprintf(arcs_cmdline, COMMAND_LINE_SIZE, "%s console=ttyS%c,115200",
                          arcs_cmdline, buf[4]);
         }
 }
diff --git a/arch/mips/boot/Makefile b/arch/mips/boot/Makefile
index 2a209d74f0b4..094bc84765a3 100644
--- a/arch/mips/boot/Makefile
+++ b/arch/mips/boot/Makefile
@@ -25,7 +25,7 @@ strip-flags	= $(addprefix --remove-section=,$(drop-sections))
 
 VMLINUX = vmlinux
 
-all: vmlinux.ecoff vmlinux.srec addinitrd
+all: vmlinux.ecoff vmlinux.srec
 
 vmlinux.ecoff: $(obj)/elf2ecoff $(VMLINUX)
         $(obj)/elf2ecoff $(VMLINUX) vmlinux.ecoff $(E2EFLAGS)
@@ -39,11 +39,7 @@ vmlinux.bin: $(VMLINUX)
 vmlinux.srec: $(VMLINUX)
         $(OBJCOPY) -S -O srec $(strip-flags) $(VMLINUX) $(obj)/vmlinux.srec
 
-$(obj)/addinitrd: $(obj)/addinitrd.c
-        $(HOSTCC) -o $@ $^
-
-clean-files += addinitrd \
-               elf2ecoff \
+clean-files += elf2ecoff \
                vmlinux.bin \
                vmlinux.ecoff \
                vmlinux.srec
diff --git a/arch/mips/boot/addinitrd.c b/arch/mips/boot/addinitrd.c
deleted file mode 100644
index b5b3febc10cc..000000000000
--- a/arch/mips/boot/addinitrd.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * addinitrd - program to add a initrd image to an ecoff kernel
- *
- * (C) 1999 Thomas Bogendoerfer
- * minor modifications, cleanup: Guido Guenther <agx@sigxcpu.org>
- * further cleanup: Maciej W. Rozycki
- */
-
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <fcntl.h>
-#include <unistd.h>
-#include <stdio.h>
-#include <netinet/in.h>
-
-#include "ecoff.h"
-
-#define MIPS_PAGE_SIZE  4096
-#define MIPS_PAGE_MASK  (MIPS_PAGE_SIZE-1)
-
-#define swab16(x) \
-        ((unsigned short)( \
-                (((unsigned short)(x) & (unsigned short)0x00ffU) << 8) | \
-                (((unsigned short)(x) & (unsigned short)0xff00U) >> 8) ))
-
-#define swab32(x) \
-        ((unsigned int)( \
-                (((unsigned int)(x) & (unsigned int)0x000000ffUL) << 24) | \
-                (((unsigned int)(x) & (unsigned int)0x0000ff00UL) <<  8) | \
-                (((unsigned int)(x) & (unsigned int)0x00ff0000UL) >>  8) | \
-                (((unsigned int)(x) & (unsigned int)0xff000000UL) >> 24) ))
-
-#define SWAB(a) (swab ? swab32(a) : (a))
-
-void die(char *s)
-{
-        perror(s);
-        exit(1);
-}
-
-int main(int argc, char *argv[])
-{
-        int fd_vmlinux, fd_initrd, fd_outfile;
-        FILHDR efile;
-        AOUTHDR eaout;
-        SCNHDR esecs[3];
-        struct stat st;
-        char buf[1024];
-        unsigned long loadaddr;
-        unsigned long initrd_header[2];
-        int i, cnt;
-        int swab = 0;
-
-        if (argc != 4) {
-                printf("Usage: %s <vmlinux> <initrd> <outfile>\n", argv[0]);
-                exit(1);
-        }
-
-        if ((fd_vmlinux = open (argv[1], O_RDONLY)) < 0)
-                 die("open vmlinux");
-        if (read (fd_vmlinux, &efile, sizeof efile) != sizeof efile)
-                die("read file header");
-        if (read (fd_vmlinux, &eaout, sizeof eaout) != sizeof eaout)
-                die("read aout header");
-        if (read (fd_vmlinux, esecs, sizeof esecs) != sizeof esecs)
-                die("read section headers");
-        /*
-         * check whether the file is good for us
-         */
-        /* TBD */
-
-        /*
-         * check, if we have to swab words
-         */
-        if (ntohs(0xaa55) == 0xaa55) {
-                if (efile.f_magic == swab16(MIPSELMAGIC))
-                        swab = 1;
-        } else {
-                if (efile.f_magic == swab16(MIPSEBMAGIC))
-                        swab = 1;
-        }
-
-        /* make sure we have an empty data segment for the initrd */
-        if (eaout.dsize || esecs[1].s_size) {
-                fprintf(stderr, "Data segment not empty. Giving up!\n");
-                exit(1);
-        }
-        if ((fd_initrd = open (argv[2], O_RDONLY)) < 0)
-                die("open initrd");
-        if (fstat (fd_initrd, &st) < 0)
-                die("fstat initrd");
-        loadaddr = ((SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size)
-                        + MIPS_PAGE_SIZE-1) & ~MIPS_PAGE_MASK) - 8;
-        if (loadaddr < (SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size)))
-                loadaddr += MIPS_PAGE_SIZE;
-        initrd_header[0] = SWAB(0x494E5244);
-        initrd_header[1] = SWAB(st.st_size);
-        eaout.dsize = esecs[1].s_size = initrd_header[1] = SWAB(st.st_size+8);
-        eaout.data_start = esecs[1].s_vaddr = esecs[1].s_paddr = SWAB(loadaddr);
-
-        if ((fd_outfile = open (argv[3], O_RDWR|O_CREAT|O_TRUNC, 0666)) < 0)
-                die("open outfile");
-        if (write (fd_outfile, &efile, sizeof efile) != sizeof efile)
-                die("write file header");
-        if (write (fd_outfile, &eaout, sizeof eaout) != sizeof eaout)
-                die("write aout header");
-        if (write (fd_outfile, esecs, sizeof esecs) != sizeof esecs)
-                die("write section headers");
-        /* skip padding */
-        if(lseek(fd_vmlinux, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1)
-                die("lseek vmlinux");
-        if(lseek(fd_outfile, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1)
-                die("lseek outfile");
-        /* copy text segment */
-        cnt = SWAB(eaout.tsize);
-        while (cnt) {
-                if ((i = read (fd_vmlinux, buf, sizeof buf)) <= 0)
-                        die("read vmlinux");
-                if (write (fd_outfile, buf, i) != i)
-                        die("write vmlinux");
-                cnt -= i;
-        }
-        if (write (fd_outfile, initrd_header, sizeof initrd_header) != sizeof initrd_header)
-                die("write initrd header");
-        while ((i = read (fd_initrd, buf, sizeof buf)) > 0)
-                if (write (fd_outfile, buf, i) != i)
-                        die("write initrd");
-        close(fd_vmlinux);
-        close(fd_initrd);
-        return 0;
-}
diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile
new file mode 100644
index 000000000000..e27f40bbd4e5
--- /dev/null
+++ b/arch/mips/boot/compressed/Makefile
@@ -0,0 +1,100 @@
+#
+# This file is subject to the terms and conditions of the GNU General Public
+# License.
+#
+# Adapted for MIPS Pete Popov, Dan Malek
+#
+# Copyright (C) 1994 by Linus Torvalds
+# Adapted for PowerPC by Gary Thomas
+# modified by Cort (cort@cs.nmt.edu)
+#
+# Copyright (C) 2009 Lemote Inc. & DSLab, Lanzhou University
+# Author: Wu Zhangjin <wuzj@lemote.com>
+#
+
+# compressed kernel load addr: VMLINUZ_LOAD_ADDRESS > VMLINUX_LOAD_ADDRESS + VMLINUX_SIZE
+VMLINUX_SIZE := $(shell wc -c $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | cut -d' ' -f1)
+VMLINUX_SIZE := $(shell [ -n "$(VMLINUX_SIZE)" ] && echo $$(($(VMLINUX_SIZE) + (65536 - $(VMLINUX_SIZE) % 65536))))
+VMLINUZ_LOAD_ADDRESS := 0x$(shell [ -n "$(VMLINUX_SIZE)" ] && printf %x $$(($(VMLINUX_LOAD_ADDRESS) + $(VMLINUX_SIZE))))
+
+# set the default size of the mallocing area for decompressing
+BOOT_HEAP_SIZE := 0x400000
+
+# Disable Function Tracer
+KBUILD_CFLAGS := $(shell echo $(KBUILD_CFLAGS) | sed -e "s/-pg//")
+
+KBUILD_CFLAGS := $(LINUXINCLUDE) $(KBUILD_CFLAGS) -D__KERNEL__ \
+        -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) -D"VMLINUX_LOAD_ADDRESS_ULL=$(VMLINUX_LOAD_ADDRESS)ull" \
+
+KBUILD_AFLAGS := $(LINUXINCLUDE) $(KBUILD_AFLAGS) -D__ASSEMBLY__ \
+        -DKERNEL_ENTRY=0x$(shell $(NM) $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | grep " kernel_entry" | cut -f1 -d \ ) \
+        -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE)
+
+obj-y := $(obj)/head.o $(obj)/decompress.o $(obj)/dbg.o
+
+obj-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o
+
+OBJCOPYFLAGS_vmlinux.bin := $(OBJCOPYFLAGS) -O binary -R .comment -S
+$(obj)/vmlinux.bin: $(KBUILD_IMAGE)
+        $(call if_changed,objcopy)
+
+suffix_$(CONFIG_KERNEL_GZIP)  = gz
+suffix_$(CONFIG_KERNEL_BZIP2) = bz2
+suffix_$(CONFIG_KERNEL_LZMA)  = lzma
+tool_$(CONFIG_KERNEL_GZIP)    = gzip
+tool_$(CONFIG_KERNEL_BZIP2)   = bzip2
+tool_$(CONFIG_KERNEL_LZMA)    = lzma
+$(obj)/vmlinux.$(suffix_y): $(obj)/vmlinux.bin
+        $(call if_changed,$(tool_y))
+
+$(obj)/piggy.o: $(obj)/vmlinux.$(suffix_y) $(obj)/dummy.o
+        $(Q)$(OBJCOPY) $(OBJCOPYFLAGS) \
+                --add-section=.image=$< \
+                --set-section-flags=.image=contents,alloc,load,readonly,data \
+                $(obj)/dummy.o $@
+
+LDFLAGS_vmlinuz := $(LDFLAGS) -Ttext $(VMLINUZ_LOAD_ADDRESS) -T
+vmlinuz: $(src)/ld.script $(obj-y) $(obj)/piggy.o
+        $(call if_changed,ld)
+        $(Q)$(OBJCOPY) $(OBJCOPYFLAGS) -R .comment -R .stab -R .stabstr -R .initrd -R .sysmap $@
+
+#
+# Some DECstations need all possible sections of an ECOFF executable
+#
+ifdef CONFIG_MACH_DECSTATION
+  E2EFLAGS = -a
+else
+  E2EFLAGS =
+endif
+
+# elf2ecoff can only handle 32bit image
+
+ifdef CONFIG_32BIT
+        VMLINUZ = vmlinuz
+else
+        VMLINUZ = vmlinuz.32
+endif
+
+vmlinuz.32: vmlinuz
+        $(Q)$(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
+
+vmlinuz.ecoff: $(obj)/../elf2ecoff $(VMLINUZ)
+        $(Q)$(obj)/../elf2ecoff $(VMLINUZ) vmlinuz.ecoff $(E2EFLAGS)
+
+$(obj)/../elf2ecoff: $(src)/../elf2ecoff.c
+        $(Q)$(HOSTCC) -o $@ $^
+
+drop-sections   = .reginfo .mdebug .comment .note .pdr .options .MIPS.options
+strip-flags     = $(addprefix --remove-section=,$(drop-sections))
+
+OBJCOPYFLAGS_vmlinuz.bin := $(OBJCOPYFLAGS) -O binary $(strip-flags)
+vmlinuz.bin: vmlinuz
+        $(call if_changed,objcopy)
+
+OBJCOPYFLAGS_vmlinuz.srec := $(OBJCOPYFLAGS) -S -O srec $(strip-flags)
+vmlinuz.srec: vmlinuz
+        $(call if_changed,objcopy)
+
+clean:
+clean-files += *.o \
+               vmlinu*
diff --git a/arch/mips/boot/compressed/dbg.c b/arch/mips/boot/compressed/dbg.c
new file mode 100644
index 000000000000..ff4dc7a33a9f
--- /dev/null
+++ b/arch/mips/boot/compressed/dbg.c
@@ -0,0 +1,37 @@
+/*
+ * MIPS-specific debug support for pre-boot environment
+ *
+ * NOTE: putc() is board specific, if your board have a 16550 compatible uart,
+ * please select SYS_SUPPORTS_ZBOOT_UART16550 for your machine. othewise, you
+ * need to implement your own putc().
+ */
+
+#include <linux/init.h>
+#include <linux/types.h>
+
+void __attribute__ ((weak)) putc(char c)
+{
+}
+
+void puts(const char *s)
+{
+        char c;
+        while ((c = *s++) != '\0') {
+                putc(c);
+                if (c == '\n')
+                        putc('\r');
+        }
+}
+
+void puthex(unsigned long long val)
+{
+
+        unsigned char buf[10];
+        int i;
+        for (i = 7; i >= 0; i--) {
+                buf[i] = "0123456789ABCDEF"[val & 0x0F];
+                val >>= 4;
+        }
+        buf[8] = '\0';
+        puts(buf);
+}
diff --git a/arch/mips/boot/compressed/decompress.c b/arch/mips/boot/compressed/decompress.c
new file mode 100644
index 000000000000..67330c2f7318
--- /dev/null
+++ b/arch/mips/boot/compressed/decompress.c
@@ -0,0 +1,126 @@
+/*
+ * Misc. bootloader code for many machines.
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: Matt Porter <mporter@mvista.com> Derived from
+ * arch/ppc/boot/prep/misc.c
+ *
+ * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology
+ * Author: Wu Zhangjin <wuzj@lemote.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+
+#include <asm/addrspace.h>
+
+/* These two variables specify the free mem region
+ * that can be used for temporary malloc area
+ */
+unsigned long free_mem_ptr;
+unsigned long free_mem_end_ptr;
+char *zimage_start;
+
+/* The linker tells us where the image is. */
+extern unsigned char __image_begin, __image_end;
+extern unsigned char __ramdisk_begin, __ramdisk_end;
+unsigned long initrd_size;
+
+/* debug interfaces  */
+extern void puts(const char *s);
+extern void puthex(unsigned long long val);
+
+void error(char *x)
+{
+        puts("\n\n");
+        puts(x);
+        puts("\n\n -- System halted");
+
+        while (1)
+                ;       /* Halt */
+}
+
+/* activate the code for pre-boot environment */
+#define STATIC static
+
+#ifdef CONFIG_KERNEL_GZIP
+void *memcpy(void *dest, const void *src, size_t n)
+{
+        int i;
+        const char *s = src;
+        char *d = dest;
+
+        for (i = 0; i < n; i++)
+                d[i] = s[i];
+        return dest;
+}
+#include "../../../../lib/decompress_inflate.c"
+#endif
+
+#ifdef CONFIG_KERNEL_BZIP2
+void *memset(void *s, int c, size_t n)
+{
+        int i;
+        char *ss = s;
+
+        for (i = 0; i < n; i++)
+                ss[i] = c;
+        return s;
+}
+#include "../../../../lib/decompress_bunzip2.c"
+#endif
+
+#ifdef CONFIG_KERNEL_LZMA
+#include "../../../../lib/decompress_unlzma.c"
+#endif
+
+void decompress_kernel(unsigned long boot_heap_start)
+{
+        int zimage_size;
+
+        /*
+         * We link ourself to an arbitrary low address.  When we run, we
+         * relocate outself to that address.  __image_beign points to
+         * the part of the image where the zImage is. -- Tom
+         */
+        zimage_start = (char *)(unsigned long)(&__image_begin);
+        zimage_size = (unsigned long)(&__image_end) -
+            (unsigned long)(&__image_begin);
+
+        /*
+         * The zImage and initrd will be between start and _end, so they've
+         * already been moved once.  We're good to go now. -- Tom
+         */
+        puts("zimage at:     ");
+        puthex((unsigned long)zimage_start);
+        puts(" ");
+        puthex((unsigned long)(zimage_size + zimage_start));
+        puts("\n");
+
+        if (initrd_size) {
+                puts("initrd at:     ");
+                puthex((unsigned long)(&__ramdisk_begin));
+                puts(" ");
+                puthex((unsigned long)(&__ramdisk_end));
+                puts("\n");
+        }
+
+        /* this area are prepared for mallocing when decompressing */
+        free_mem_ptr = boot_heap_start;
+        free_mem_end_ptr = boot_heap_start + BOOT_HEAP_SIZE;
+
+        /* Display standard Linux/MIPS boot prompt for kernel args */
+        puts("Uncompressing Linux at load address ");
+        puthex(VMLINUX_LOAD_ADDRESS_ULL);
+        puts("\n");
+        /* Decompress the kernel with according algorithm */
+        decompress(zimage_start, zimage_size, 0, 0,
+                   (void *)VMLINUX_LOAD_ADDRESS_ULL, 0, error);
+        /* FIXME: is there a need to flush cache here? */
+        puts("Now, booting the kernel...\n");
+}
diff --git a/arch/mips/boot/compressed/dummy.c b/arch/mips/boot/compressed/dummy.c
new file mode 100644
index 000000000000..31dbf45bf99c
--- /dev/null
+++ b/arch/mips/boot/compressed/dummy.c
@@ -0,0 +1,4 @@
+int main(void)
+{
+        return 0;
+}
diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S
new file mode 100644
index 000000000000..4e65a8420bee
--- /dev/null
+++ b/arch/mips/boot/compressed/head.S
@@ -0,0 +1,56 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 1995 Waldorf Electronics
+ * Written by Ralf Baechle and Andreas Busse
+ * Copyright (C) 1995 - 1999 Ralf Baechle
+ * Copyright (C) 1996 Paul M. Antoine
+ * Modified for DECStation and hence R3000 support by Paul M. Antoine
+ * Further modifications by David S. Miller and Harald Koerfgen
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+
+#include <asm/asm.h>
+#include <asm/regdef.h>
+
+        .set noreorder
+        .cprestore
+        LEAF(start)
+start:
+        /* Save boot rom start args */
+        move    s0, a0
+        move    s1, a1
+        move    s2, a2
+        move    s3, a3
+
+        /* Clear BSS */
+        PTR_LA  a0, _edata
+        PTR_LA  a2, _end
+1:      sw      zero, 0(a0)
+        bne     a2, a0, 1b
+         addiu  a0, a0, 4
+
+        PTR_LA  a0, (.heap)          /* heap address */
+        PTR_LA  sp, (.stack + 8192)  /* stack address */
+
+        PTR_LA  ra, 2f
+        PTR_LA  k0, decompress_kernel
+        jr      k0
+         nop
+2:
+        move    a0, s0
+        move    a1, s1
+        move    a2, s2
+        move    a3, s3
+        PTR_LI  k0, KERNEL_ENTRY
+        jr      k0
+         nop
+3:
+        b       3b
+         nop
+        END(start)
+
+        .comm .heap,BOOT_HEAP_SIZE,4
+        .comm .stack,4096*2,4
diff --git a/arch/mips/boot/compressed/ld.script b/arch/mips/boot/compressed/ld.script
new file mode 100644
index 000000000000..29e9f4c0d5d8
--- /dev/null
+++ b/arch/mips/boot/compressed/ld.script
@@ -0,0 +1,150 @@
+OUTPUT_ARCH(mips)
+ENTRY(start)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  .init          : { *(.init)           } =0
+  .text      :
+  {
+    _ftext = . ;
+    *(.text)
+    *(.rodata)
+    *(.rodata1)
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+  } =0
+  .kstrtab : { *(.kstrtab) }
+
+  . = ALIGN(16);                /* Exception table */
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  __start___dbe_table = .;      /* Exception table for data bus errors */
+  __dbe_table : { *(__dbe_table) }
+  __stop___dbe_table = .;
+
+  __start___ksymtab = .;        /* Kernel symbol table */
+  __ksymtab : { *(__ksymtab) }
+  __stop___ksymtab = .;
+
+  _etext = .;
+
+  . = ALIGN(8192);
+  .data.init_task : { *(.data.init_task) }
+
+  /* Startup code */
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(16);
+  __setup_start = .;
+  .setup.init : { *(.setup.init) }
+  __setup_end = .;
+  __initcall_start = .;
+  .initcall.init : { *(.initcall.init) }
+  __initcall_end = .;
+  . = ALIGN(4096);      /* Align double page for init_task_union */
+  __init_end = .;
+
+  . = ALIGN(4096);
+  .data.page_aligned : { *(.data.idt) }
+
+  . = ALIGN(32);
+  .data.cacheline_aligned : { *(.data.cacheline_aligned) }
+
+  .fini      : { *(.fini)    } =0
+  .reginfo : { *(.reginfo) }
+  /* Adjust the address for the data segment.  We want to adjust up to
+     the same address within the page on the next page up.  It would
+     be more correct to do this:
+       . = .;
+     The current expression does not correctly handle the case of a
+     text segment ending precisely at the end of a page; it causes the
+     data segment to skip a page.  The above expression does not have
+     this problem, but it will currently (2/95) cause BFD to allocate
+     a single segment, combining both text and data, for this case.
+     This will prevent the text segment from being shared among
+     multiple executions of the program; I think that is more
+     important than losing a page of the virtual address space (note
+     that no actual memory is lost; the page which is skipped can not
+     be referenced).  */
+  . = .;
+  .data    :
+  {
+    _fdata = . ;
+    *(.data)
+
+   /* Put the compressed image here, so bss is on the end. */
+   __image_begin = .;
+   *(.image)
+   __image_end = .;
+   /* Align the initial ramdisk image (INITRD) on page boundaries. */
+   . = ALIGN(4096);
+   __ramdisk_begin = .;
+   *(.initrd)
+   __ramdisk_end = .;
+   . = ALIGN(4096);
+
+    CONSTRUCTORS
+  }
+  .data1   : { *(.data1) }
+  _gp = . + 0x8000;
+  .lit8 : { *(.lit8) }
+  .lit4 : { *(.lit4) }
+  .ctors         : { *(.ctors)   }
+  .dtors         : { *(.dtors)   }
+  .got           : { *(.got.plt) *(.got) }
+  .dynamic       : { *(.dynamic) }
+  /* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .sdata     : { *(.sdata) }
+  . = ALIGN(4);
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __bss_start = .;
+  _fbss = .;
+  .sbss      : { *(.sbss) *(.scommon) }
+  .bss       :
+  {
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   .  = ALIGN(4);
+  _end = . ;
+  PROVIDE (end = .);
+  }
+
+  /* Sections to be discarded */
+  /DISCARD/ :
+  {
+        *(.text.exit)
+        *(.data.exit)
+        *(.exitcall.exit)
+  }
+
+  /* This is the MIPS specific mdebug section.  */
+  .mdebug : { *(.mdebug) }
+  /* These are needed for ELF backends which have not yet been
+     converted to the new style linker.  */
+  .stab 0 : { *(.stab) }
+  .stabstr 0 : { *(.stabstr) }
+  /* DWARF debug sections.
+     Symbols in the .debug DWARF section are relative to the beginning of the
+     section so we begin .debug at 0.  It's not clear yet what needs to happen
+     for the others.   */
+  .debug          0 : { *(.debug) }
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  .line           0 : { *(.line) }
+  /* These must appear regardless of  .  */
+  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
+  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
+  .comment : { *(.comment) }
+  .note : { *(.note) }
+}
diff --git a/arch/mips/boot/compressed/uart-16550.c b/arch/mips/boot/compressed/uart-16550.c
new file mode 100644
index 000000000000..c9caaf4fbf60
--- /dev/null
+++ b/arch/mips/boot/compressed/uart-16550.c
@@ -0,0 +1,43 @@
+/*
+ * 16550 compatible uart based serial debug support for zboot
+ */
+
+#include <linux/types.h>
+#include <linux/serial_reg.h>
+#include <linux/init.h>
+
+#include <asm/addrspace.h>
+
+#if defined(CONFIG_MACH_LOONGSON) || defined(CONFIG_MIPS_MALTA)
+#define UART_BASE 0x1fd003f8
+#define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset))
+#endif
+
+#ifdef CONFIG_AR7
+#include <ar7.h>
+#define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset))
+#endif
+
+#ifndef PORT
+#error please define the serial port address for your own machine
+#endif
+
+static inline unsigned int serial_in(int offset)
+{
+        return *((char *)PORT(offset));
+}
+
+static inline void serial_out(int offset, int value)
+{
+        *((char *)PORT(offset)) = value;
+}
+
+void putc(char c)
+{
+        int timeout = 1024;
+
+        while (((serial_in(UART_LSR) & UART_LSR_THRE) == 0) && (timeout-- > 0))
+                ;
+
+        serial_out(UART_TX, c);
+}
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 139436280520..3e9876317e61 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -9,7 +9,7 @@
 # Copyright (C) 2005-2009 Cavium Networks
 #
 
-obj-y := setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o
+obj-y := cpu.o setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o
 obj-y += dma-octeon.o flash_setup.o
 obj-y += octeon-memcpy.o
 
diff --git a/arch/mips/cavium-octeon/cpu.c b/arch/mips/cavium-octeon/cpu.c
new file mode 100644
index 000000000000..b6df5387e855
--- /dev/null
+++ b/arch/mips/cavium-octeon/cpu.c
@@ -0,0 +1,52 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2009 Wind River Systems,
+ *   written by Ralf Baechle <ralf@linux-mips.org>
+ */
+#include <linux/init.h>
+#include <linux/irqflags.h>
+#include <linux/notifier.h>
+#include <linux/prefetch.h>
+#include <linux/sched.h>
+
+#include <asm/cop2.h>
+#include <asm/current.h>
+#include <asm/mipsregs.h>
+#include <asm/page.h>
+#include <asm/octeon/octeon.h>
+
+static int cnmips_cu2_call(struct notifier_block *nfb, unsigned long action,
+        void *data)
+{
+        unsigned long flags;
+        unsigned int status;
+
+        switch (action) {
+        case CU2_EXCEPTION:
+                prefetch(&current->thread.cp2);
+                local_irq_save(flags);
+                KSTK_STATUS(current) |= ST0_CU2;
+                status = read_c0_status();
+                write_c0_status(status | ST0_CU2);
+                octeon_cop2_restore(&(current->thread.cp2));
+                write_c0_status(status & ~ST0_CU2);
+                local_irq_restore(flags);
+
+                return NOTIFY_BAD;      /* Don't call default notifier */
+        }
+
+        return NOTIFY_OK;               /* Let default notifier send signals */
+}
+
+static struct notifier_block cnmips_cu2_notifier = {
+        .notifier_call = cnmips_cu2_call,
+};
+
+static int cnmips_cu2_setup(void)
+{
+        return register_cu2_notifier(&cnmips_cu2_notifier);
+}
+early_initcall(cnmips_cu2_setup);
diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c
index be711dd2d918..cfdb4c2ac5c3 100644
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -159,6 +159,94 @@ out:
 }
 device_initcall(octeon_rng_device_init);
 
+/* Octeon SMI/MDIO interface.  */
+static int __init octeon_mdiobus_device_init(void)
+{
+        struct platform_device *pd;
+        int ret = 0;
+
+        if (octeon_is_simulation())
+                return 0; /* No mdio in the simulator. */
+
+        /* The bus number is the platform_device id.  */
+        pd = platform_device_alloc("mdio-octeon", 0);
+        if (!pd) {
+                ret = -ENOMEM;
+                goto out;
+        }
+
+        ret = platform_device_add(pd);
+        if (ret)
+                goto fail;
+
+        return ret;
+fail:
+        platform_device_put(pd);
+
+out:
+        return ret;
+
+}
+device_initcall(octeon_mdiobus_device_init);
+
+/* Octeon mgmt port Ethernet interface.  */
+static int __init octeon_mgmt_device_init(void)
+{
+        struct platform_device *pd;
+        int ret = 0;
+        int port, num_ports;
+
+        struct resource mgmt_port_resource = {
+                .flags  = IORESOURCE_IRQ,
+                .start  = -1,
+                .end    = -1
+        };
+
+        if (!OCTEON_IS_MODEL(OCTEON_CN56XX) && !OCTEON_IS_MODEL(OCTEON_CN52XX))
+                return 0;
+
+        if (OCTEON_IS_MODEL(OCTEON_CN56XX))
+                num_ports = 1;
+        else
+                num_ports = 2;
+
+        for (port = 0; port < num_ports; port++) {
+                pd = platform_device_alloc("octeon_mgmt", port);
+                if (!pd) {
+                        ret = -ENOMEM;
+                        goto out;
+                }
+                switch (port) {
+                case 0:
+                        mgmt_port_resource.start = OCTEON_IRQ_MII0;
+                        break;
+                case 1:
+                        mgmt_port_resource.start = OCTEON_IRQ_MII1;
+                        break;
+                default:
+                        BUG();
+                }
+                mgmt_port_resource.end = mgmt_port_resource.start;
+
+                ret = platform_device_add_resources(pd, &mgmt_port_resource, 1);
+
+                if (ret)
+                        goto fail;
+
+                ret = platform_device_add(pd);
+                if (ret)
+                        goto fail;
+        }
+        return ret;
+fail:
+        platform_device_put(pd);
+
+out:
+        return ret;
+
+}
+device_initcall(octeon_mgmt_device_init);
+
 MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
 MODULE_LICENSE("GPL");
 MODULE_DESCRIPTION("Platform driver for Octeon SOC");
diff --git a/arch/mips/configs/ar7_defconfig b/arch/mips/configs/ar7_defconfig
index 35648302f7cc..5a5b6ba7514e 100644
--- a/arch/mips/configs/ar7_defconfig
+++ b/arch/mips/configs/ar7_defconfig
@@ -10,7 +10,6 @@ CONFIG_MIPS=y
 #
 # CONFIG_MACH_ALCHEMY is not set
 CONFIG_AR7=y
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
@@ -265,7 +264,6 @@ CONFIG_DEFAULT_DEADLINE=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="deadline"
-CONFIG_PROBE_INITRD_HEADER=y
 # CONFIG_FREEZER is not set
 
 #
@@ -1053,7 +1051,9 @@ CONFIG_TRACING_SUPPORT=y
 # CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+# CONFIG_CMDLINE_OVERRIDE is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/bcm47xx_defconfig b/arch/mips/configs/bcm47xx_defconfig
index 94b7d57f906d..267bd46120bc 100644
--- a/arch/mips/configs/bcm47xx_defconfig
+++ b/arch/mips/configs/bcm47xx_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 CONFIG_BCM47XX=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
@@ -1853,7 +1852,7 @@ CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 # CONFIG_SAMPLES is not set
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/bcm63xx_defconfig b/arch/mips/configs/bcm63xx_defconfig
index ea00c18d1f7b..7fee0273c829 100644
--- a/arch/mips/configs/bcm63xx_defconfig
+++ b/arch/mips/configs/bcm63xx_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 CONFIG_BCM63XX=y
 # CONFIG_MIPS_COBALT is not set
@@ -942,7 +941,9 @@ CONFIG_TRACING_SUPPORT=y
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="console=ttyS0,115200"
+# CONFIG_CMDLINE_OVERRIDE is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig
index 13d9eb4736c0..c2f06e38c854 100644
--- a/arch/mips/configs/bigsur_defconfig
+++ b/arch/mips/configs/bigsur_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
@@ -1237,7 +1236,7 @@ CONFIG_DEBUG_MUTEXES=y
 # CONFIG_BACKTRACE_SELF_TEST is not set
 # CONFIG_FAULT_INJECTION is not set
 # CONFIG_SAMPLES is not set
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
 # CONFIG_SB1XXX_CORELIS is not set
 # CONFIG_RUNTIME_DEBUG is not set
diff --git a/arch/mips/configs/capcella_defconfig b/arch/mips/configs/capcella_defconfig
index 185df23fd460..72b7e456916e 100644
--- a/arch/mips/configs/capcella_defconfig
+++ b/arch/mips/configs/capcella_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -783,7 +782,9 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_CROSSCOMPILE=y
+CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="mem=32M console=ttyVR0,38400"
+# CONFIG_CMDLINE_OVERRIDE is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/cavium-octeon_defconfig b/arch/mips/configs/cavium-octeon_defconfig
index 7afaa28a3768..c8507bc8e925 100644
--- a/arch/mips/configs/cavium-octeon_defconfig
+++ b/arch/mips/configs/cavium-octeon_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
@@ -269,7 +268,6 @@ CONFIG_DEFAULT_CFQ=y
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="cfq"
 CONFIG_CLASSIC_RCU=y
-# CONFIG_PROBE_INITRD_HEADER is not set
 # CONFIG_FREEZER is not set
 
 #
@@ -822,7 +820,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KGDB is not set
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
 # CONFIG_RUNTIME_DEBUG is not set
 
diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig
index 6c8cca8589ba..49e61312e006 100644
--- a/arch/mips/configs/cobalt_defconfig
+++ b/arch/mips/configs/cobalt_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 CONFIG_MIPS_COBALT=y
 # CONFIG_MACH_DECSTATION is not set
@@ -1126,7 +1125,7 @@ CONFIG_FRAME_WARN=1024
 # CONFIG_SLUB_STATS is not set
 # CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_SAMPLES is not set
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig
index dbdf3bb1a34a..68e90cd6b2d4 100644
--- a/arch/mips/configs/db1000_defconfig
+++ b/arch/mips/configs/db1000_defconfig
@@ -23,7 +23,6 @@ CONFIG_MIPS_DB1000=y
 # CONFIG_MIPS_DB1550 is not set
 # CONFIG_MIPS_DB1200 is not set
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -1090,7 +1089,7 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig
index fa6814475898..90812830e940 100644
--- a/arch/mips/configs/db1100_defconfig
+++ b/arch/mips/configs/db1100_defconfig
@@ -23,7 +23,6 @@ CONFIG_MIPS_DB1100=y
 # CONFIG_MIPS_DB1550 is not set
 # CONFIG_MIPS_DB1200 is not set
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -1090,7 +1089,7 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig
index d73f1de43b5d..dabf03032e06 100644
--- a/arch/mips/configs/db1200_defconfig
+++ b/arch/mips/configs/db1200_defconfig
@@ -23,7 +23,6 @@ CONFIG_MACH_ALCHEMY=y
 # CONFIG_MIPS_DB1550 is not set
 CONFIG_MIPS_DB1200=y
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -1172,7 +1171,9 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
+CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="mem=48M"
+# CONFIG_CMDLINE_OVERRIDE is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig
index ec3e028a5b2e..a15131373138 100644
--- a/arch/mips/configs/db1500_defconfig
+++ b/arch/mips/configs/db1500_defconfig
@@ -23,7 +23,6 @@ CONFIG_MIPS_DB1500=y
 # CONFIG_MIPS_DB1550 is not set
 # CONFIG_MIPS_DB1200 is not set
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -1390,7 +1389,7 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig
index 7631dae51be9..6b64339c0014 100644
--- a/arch/mips/configs/db1550_defconfig
+++ b/arch/mips/configs/db1550_defconfig
@@ -23,7 +23,6 @@ CONFIG_MACH_ALCHEMY=y
 CONFIG_MIPS_DB1550=y
 # CONFIG_MIPS_DB1200 is not set
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -1207,7 +1206,7 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig
index 9e65e6a2dcb3..cbb4d86f2912 100644
--- a/arch/mips/configs/decstation_defconfig
+++ b/arch/mips/configs/decstation_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MIPS_DB1550 is not set
 # CONFIG_MIPS_DB1200 is not set
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 CONFIG_MACH_DECSTATION=y
 # CONFIG_MACH_JAZZ is not set
@@ -882,7 +881,7 @@ CONFIG_MAGIC_SYSRQ=y
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/e55_defconfig b/arch/mips/configs/e55_defconfig
index 1bd84d42b14f..52968c46c806 100644
--- a/arch/mips/configs/e55_defconfig
+++ b/arch/mips/configs/e55_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -561,7 +560,9 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_CROSSCOMPILE=y
+CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="console=ttyVR0,19200 ide0=0x1f0,0x3f6,40 mem=8M"
+# CONFIG_CMDLINE_OVERRIDE is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/excite_defconfig b/arch/mips/configs/excite_defconfig
deleted file mode 100644
index 1995d43a2ed1..000000000000
--- a/arch/mips/configs/excite_defconfig
+++ /dev/null
@@ -1,1335 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.20
-# Tue Feb 20 21:47:31 2007
-#
-CONFIG_MIPS=y
-
-#
-# Machine selection
-#
-CONFIG_ZONE_DMA=y
-# CONFIG_MIPS_MTX1 is not set
-# CONFIG_MIPS_BOSPORUS is not set
-# CONFIG_MIPS_PB1000 is not set
-# CONFIG_MIPS_PB1100 is not set
-# CONFIG_MIPS_PB1500 is not set
-# CONFIG_MIPS_PB1550 is not set
-# CONFIG_MIPS_PB1200 is not set
-# CONFIG_MIPS_DB1000 is not set
-# CONFIG_MIPS_DB1100 is not set
-# CONFIG_MIPS_DB1500 is not set
-# CONFIG_MIPS_DB1550 is not set
-# CONFIG_MIPS_DB1200 is not set
-# CONFIG_MIPS_MIRAGE is not set
-CONFIG_BASLER_EXCITE=y
-# CONFIG_BASLER_EXCITE_PROTOTYPE is not set
-# CONFIG_MIPS_COBALT is not set
-# CONFIG_MACH_DECSTATION is not set
-# CONFIG_MACH_JAZZ is not set
-# CONFIG_MIPS_MALTA is not set
-# CONFIG_WR_PPMC is not set
-# CONFIG_MIPS_SIM is not set
-# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_JBS is not set
-# CONFIG_PNX8550_STB810 is not set
-# CONFIG_MACH_VR41XX is not set
-# CONFIG_PMC_YOSEMITE is not set
-# CONFIG_MARKEINS is not set
-# CONFIG_SGI_IP22 is not set
-# CONFIG_SGI_IP27 is not set
-# CONFIG_SGI_IP32 is not set
-# CONFIG_SIBYTE_BIGSUR is not set
-# CONFIG_SIBYTE_SWARM is not set
-# CONFIG_SIBYTE_SENTOSA is not set
-# CONFIG_SIBYTE_RHONE is not set
-# CONFIG_SIBYTE_CARMEL is not set
-# CONFIG_SIBYTE_LITTLESUR is not set
-# CONFIG_SIBYTE_CRHINE is not set
-# CONFIG_SIBYTE_CRHONE is not set
-# CONFIG_SNI_RM is not set
-# CONFIG_TOSHIBA_JMR3927 is not set
-# CONFIG_TOSHIBA_RBTX4927 is not set
-# CONFIG_TOSHIBA_RBTX4938 is not set
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_GENERIC_FIND_NEXT_BIT=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_TIME=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
-CONFIG_DMA_COHERENT=y
-CONFIG_CPU_BIG_ENDIAN=y
-# CONFIG_CPU_LITTLE_ENDIAN is not set
-CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-CONFIG_IRQ_CPU=y
-CONFIG_IRQ_CPU_RM7K=y
-CONFIG_IRQ_CPU_RM9K=y
-CONFIG_MIPS_RM9122=y
-CONFIG_SERIAL_RM9000=y
-CONFIG_GPI_RM9000=y
-CONFIG_WDT_RM9000=y
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-
-#
-# CPU selection
-#
-# CONFIG_CPU_MIPS32_R1 is not set
-# CONFIG_CPU_MIPS32_R2 is not set
-# CONFIG_CPU_MIPS64_R1 is not set
-# CONFIG_CPU_MIPS64_R2 is not set
-# CONFIG_CPU_R3000 is not set
-# CONFIG_CPU_TX39XX is not set
-# CONFIG_CPU_VR41XX is not set
-# CONFIG_CPU_R4300 is not set
-# CONFIG_CPU_R4X00 is not set
-# CONFIG_CPU_TX49XX is not set
-# CONFIG_CPU_R5000 is not set
-# CONFIG_CPU_R5432 is not set
-# CONFIG_CPU_R6000 is not set
-# CONFIG_CPU_NEVADA is not set
-# CONFIG_CPU_R8000 is not set
-# CONFIG_CPU_R10000 is not set
-# CONFIG_CPU_RM7000 is not set
-CONFIG_CPU_RM9000=y
-# CONFIG_CPU_SB1 is not set
-CONFIG_SYS_HAS_CPU_RM9000=y
-CONFIG_WEAK_ORDERING=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-
-#
-# Kernel type
-#
-CONFIG_32BIT=y
-# CONFIG_64BIT is not set
-CONFIG_PAGE_SIZE_4KB=y
-# CONFIG_PAGE_SIZE_8KB is not set
-# CONFIG_PAGE_SIZE_16KB is not set
-# CONFIG_PAGE_SIZE_64KB is not set
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_MIPS_MT_DISABLED=y
-# CONFIG_MIPS_MT_SMP is not set
-# CONFIG_MIPS_MT_SMTC is not set
-# CONFIG_MIPS_VPE_LOADER is not set
-# CONFIG_64BIT_PHYS_ADDR is not set
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_ARCH_FLATMEM_ENABLE=y
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-CONFIG_SPLIT_PTLOCK_CPUS=4
-# CONFIG_RESOURCES_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=1
-# CONFIG_HZ_48 is not set
-# CONFIG_HZ_100 is not set
-# CONFIG_HZ_128 is not set
-# CONFIG_HZ_250 is not set
-# CONFIG_HZ_256 is not set
-CONFIG_HZ_1000=y
-# CONFIG_HZ_1024 is not set
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_HZ=1000
-# CONFIG_PREEMPT_NONE is not set
-# CONFIG_PREEMPT_VOLUNTARY is not set
-CONFIG_PREEMPT=y
-CONFIG_PREEMPT_BKL=y
-# CONFIG_KEXEC is not set
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# Code maturity level options
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_LOCK_KERNEL=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_POSIX_MQUEUE=y
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
-# CONFIG_AUDIT is not set
-# CONFIG_IKCONFIG is not set
-CONFIG_SYSFS_DEPRECATED=y
-# CONFIG_RELAY is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-CONFIG_EMBEDDED=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SHMEM=y
-CONFIG_SLAB=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-# CONFIG_MODVERSIONS is not set
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
-
-#
-# Block layer
-#
-CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
-
-#
-# Bus options (PCI, PCMCIA, EISA, ISA, TC)
-#
-CONFIG_HW_HAS_PCI=y
-CONFIG_PCI=y
-CONFIG_MMU=y
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-# CONFIG_PCCARD is not set
-
-#
-# PCI Hotplug Support
-#
-# CONFIG_HOTPLUG_PCI is not set
-
-#
-# Executable file formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_MISC is not set
-CONFIG_TRAD_SIGNALS=y
-
-#
-# Power management options
-#
-CONFIG_PM=y
-# CONFIG_PM_LEGACY is not set
-# CONFIG_PM_DEBUG is not set
-# CONFIG_PM_SYSFS_DEPRECATED is not set
-
-#
-# Networking
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-# CONFIG_NETDEBUG is not set
-CONFIG_PACKET=y
-CONFIG_PACKET_MMAP=y
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-CONFIG_XFRM_MIGRATE=y
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IP_PNP_BOOTP is not set
-# CONFIG_IP_PNP_RARP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=m
-CONFIG_INET_XFRM_MODE_TUNNEL=m
-CONFIG_INET_XFRM_MODE_BEET=m
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-CONFIG_TCP_MD5SIG=y
-# CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
-CONFIG_NETWORK_SECMARK=y
-# CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-# CONFIG_IEEE80211 is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
-# CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
-# CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_CONCAT is not set
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-# CONFIG_RFD_FTL is not set
-# CONFIG_SSFDC is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-# CONFIG_MTD_CFI is not set
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
-
-#
-# Mapping drivers for chip access
-#
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PLATRAM is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_PMC551 is not set
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLOCK2MTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-
-#
-# NAND Flash Device Drivers
-#
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
-# CONFIG_MTD_NAND_ECC_SMC is not set
-CONFIG_MTD_NAND_IDS=y
-# CONFIG_MTD_NAND_DISKONCHIP is not set
-# CONFIG_MTD_NAND_BASLER_EXCITE is not set
-# CONFIG_MTD_NAND_CAFE is not set
-# CONFIG_MTD_NAND_NANDSIM is not set
-
-#
-# OneNAND Flash Device Drivers
-#
-# CONFIG_MTD_ONENAND is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-# CONFIG_PNPACPI is not set
-
-#
-# Block devices
-#
-# CONFIG_BLK_CPQ_DA is not set
-# CONFIG_BLK_CPQ_CISS_DA is not set
-# CONFIG_BLK_DEV_DAC960 is not set
-# CONFIG_BLK_DEV_UMEM is not set
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=m
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_SX8 is not set
-# CONFIG_BLK_DEV_UB is not set
-# CONFIG_BLK_DEV_RAM is not set
-# CONFIG_BLK_DEV_INITRD is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-
-#
-# Misc devices
-#
-CONFIG_SGI_IOC4=m
-# CONFIG_TIFM_CORE is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_TGT=m
-# CONFIG_SCSI_NETLINK is not set
-# CONFIG_SCSI_PROC_FS is not set
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-# CONFIG_CHR_DEV_ST is not set
-# CONFIG_CHR_DEV_OSST is not set
-# CONFIG_BLK_DEV_SR is not set
-# CONFIG_CHR_DEV_SG is not set
-# CONFIG_CHR_DEV_SCH is not set
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-# CONFIG_SCSI_MULTI_LUN is not set
-# CONFIG_SCSI_CONSTANTS is not set
-# CONFIG_SCSI_LOGGING is not set
-CONFIG_SCSI_SCAN_ASYNC=y
-
-#
-# SCSI Transports
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-CONFIG_SCSI_SAS_ATTRS=m
-CONFIG_SCSI_SAS_LIBSAS=m
-# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
-
-#
-# SCSI low-level drivers
-#
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
-# CONFIG_SCSI_3W_9XXX is not set
-# CONFIG_SCSI_ACARD is not set
-# CONFIG_SCSI_AACRAID is not set
-# CONFIG_SCSI_AIC7XXX is not set
-# CONFIG_SCSI_AIC7XXX_OLD is not set
-# CONFIG_SCSI_AIC79XX is not set
-CONFIG_SCSI_AIC94XX=m
-# CONFIG_AIC94XX_DEBUG is not set
-# CONFIG_SCSI_DPT_I2O is not set
-# CONFIG_SCSI_ARCMSR is not set
-# CONFIG_MEGARAID_NEWGEN is not set
-# CONFIG_MEGARAID_LEGACY is not set
-# CONFIG_MEGARAID_SAS is not set
-# CONFIG_SCSI_HPTIOP is not set
-# CONFIG_SCSI_DMX3191D is not set
-# CONFIG_SCSI_FUTURE_DOMAIN is not set
-# CONFIG_SCSI_IPS is not set
-# CONFIG_SCSI_INITIO is not set
-# CONFIG_SCSI_INIA100 is not set
-# CONFIG_SCSI_STEX is not set
-# CONFIG_SCSI_SYM53C8XX_2 is not set
-# CONFIG_SCSI_QLOGIC_1280 is not set
-# CONFIG_SCSI_QLA_FC is not set
-# CONFIG_SCSI_QLA_ISCSI is not set
-# CONFIG_SCSI_LPFC is not set
-# CONFIG_SCSI_DC395x is not set
-# CONFIG_SCSI_DC390T is not set
-# CONFIG_SCSI_NSP32 is not set
-# CONFIG_SCSI_DEBUG is not set
-# CONFIG_SCSI_SRP is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
-# CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-# CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-# CONFIG_FUSION_SPI is not set
-# CONFIG_FUSION_FC is not set
-# CONFIG_FUSION_SAS is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-# CONFIG_IEEE1394 is not set
-
-#
-# I2O device support
-#
-# CONFIG_I2O is not set
-
-#
-# Network device support
-#
-CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-
-#
-# ARCnet devices
-#
-# CONFIG_ARCNET is not set
-
-#
-# PHY device support
-#
-
-#
-# Ethernet (10 or 100Mbit)
-#
-# CONFIG_NET_ETHERNET is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-# CONFIG_ACENIC is not set
-# CONFIG_DL2K is not set
-# CONFIG_E1000 is not set
-# CONFIG_NS83820 is not set
-# CONFIG_HAMACHI is not set
-# CONFIG_YELLOWFIN is not set
-# CONFIG_R8169 is not set
-# CONFIG_SIS190 is not set
-# CONFIG_SKGE is not set
-# CONFIG_SKY2 is not set
-# CONFIG_SK98LIN is not set
-# CONFIG_TIGON3 is not set
-# CONFIG_BNX2 is not set
-CONFIG_QLA3XXX=m
-# CONFIG_ATL1 is not set
-
-#
-# Ethernet (10000 Mbit)
-#
-# CONFIG_CHELSIO_T1 is not set
-CONFIG_CHELSIO_T3=m
-# CONFIG_IXGB is not set
-# CONFIG_S2IO is not set
-# CONFIG_MYRI10GE is not set
-CONFIG_NETXEN_NIC=m
-
-#
-# Token Ring devices
-#
-# CONFIG_TR is not set
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# Wan interfaces
-#
-# CONFIG_WAN is not set
-# CONFIG_FDDI is not set
-# CONFIG_HIPPI is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_NET_FC is not set
-# CONFIG_SHAPER is not set
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
-# CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=m
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-# CONFIG_SERIO is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_NR_UARTS=2
-CONFIG_SERIAL_8250_RUNTIME_UARTS=2
-CONFIG_SERIAL_8250_EXTENDED=y
-# CONFIG_SERIAL_8250_MANY_PORTS is not set
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-# CONFIG_SERIAL_8250_DETECT_IRQ is not set
-# CONFIG_SERIAL_8250_RSA is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-# CONFIG_SERIAL_JSM is not set
-CONFIG_UNIX98_PTYS=y
-# CONFIG_LEGACY_PTYS is not set
-
-#
-# IPMI
-#
-# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-CONFIG_WATCHDOG=y
-# CONFIG_WATCHDOG_NOWAYOUT is not set
-
-#
-# Watchdog Device Drivers
-#
-# CONFIG_SOFT_WATCHDOG is not set
-CONFIG_WDT_RM9K_GPI=m
-
-#
-# PCI-based Watchdog Cards
-#
-# CONFIG_PCIPCWATCHDOG is not set
-# CONFIG_WDTPCI is not set
-
-#
-# USB-based Watchdog Cards
-#
-# CONFIG_USBPCWATCHDOG is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_RTC is not set
-# CONFIG_GEN_RTC is not set
-# CONFIG_DTLK is not set
-# CONFIG_R3964 is not set
-# CONFIG_APPLICOM is not set
-# CONFIG_DRM is not set
-# CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
-# CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
-# CONFIG_I2C is not set
-
-#
-# SPI support
-#
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-
-#
-# Dallas's 1-wire bus
-#
-# CONFIG_W1 is not set
-
-#
-# Hardware Monitoring support
-#
-# CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
-
-#
-# Multimedia devices
-#
-# CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
-# CONFIG_USB_DABUSB is not set
-
-#
-# Graphics support
-#
-# CONFIG_FIRMWARE_EDID is not set
-CONFIG_FB=y
-# CONFIG_FB_CFB_FILLRECT is not set
-# CONFIG_FB_CFB_COPYAREA is not set
-# CONFIG_FB_CFB_IMAGEBLIT is not set
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-# CONFIG_FB_BACKLIGHT is not set
-# CONFIG_FB_MODE_HELPERS is not set
-# CONFIG_FB_TILEBLITTING is not set
-# CONFIG_FB_CIRRUS is not set
-# CONFIG_FB_PM2 is not set
-# CONFIG_FB_CYBER2000 is not set
-# CONFIG_FB_ASILIANT is not set
-# CONFIG_FB_IMSTT is not set
-# CONFIG_FB_S1D13XXX is not set
-# CONFIG_FB_NVIDIA is not set
-# CONFIG_FB_RIVA is not set
-# CONFIG_FB_MATROX is not set
-# CONFIG_FB_RADEON is not set
-# CONFIG_FB_ATY128 is not set
-# CONFIG_FB_ATY is not set
-# CONFIG_FB_S3 is not set
-# CONFIG_FB_SAVAGE is not set
-# CONFIG_FB_SIS is not set
-# CONFIG_FB_NEOMAGIC is not set
-# CONFIG_FB_KYRO is not set
-# CONFIG_FB_3DFX is not set
-# CONFIG_FB_VOODOO1 is not set
-# CONFIG_FB_SMIVGX is not set
-# CONFIG_FB_TRIDENT is not set
-# CONFIG_FB_VIRTUAL is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=m
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-# CONFIG_FONTS is not set
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-
-#
-# Logo configuration
-#
-# CONFIG_LOGO is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Sound
-#
-# CONFIG_SOUND is not set
-
-#
-# HID Devices
-#
-CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
-
-#
-# USB support
-#
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-CONFIG_USB_ARCH_HAS_EHCI=y
-CONFIG_USB=y
-# CONFIG_USB_DEBUG is not set
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_OTG is not set
-
-#
-# USB Host Controller Drivers
-#
-CONFIG_USB_EHCI_HCD=y
-# CONFIG_USB_EHCI_SPLIT_ISO is not set
-# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
-# CONFIG_USB_EHCI_TT_NEWSCHED is not set
-# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set
-# CONFIG_USB_ISP116X_HCD is not set
-CONFIG_USB_OHCI_HCD=y
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-# CONFIG_USB_UHCI_HCD is not set
-# CONFIG_USB_SL811_HCD is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-
-#
-# may also be needed; see USB_STORAGE Help for more information
-#
-CONFIG_USB_STORAGE=y
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_DPCM is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Input Devices
-#
-CONFIG_USB_HID=m
-# CONFIG_USB_HIDINPUT_POWERBOOK is not set
-# CONFIG_HID_FF is not set
-# CONFIG_USB_HIDDEV is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# CONFIG_USB_AIPTEK is not set
-# CONFIG_USB_WACOM is not set
-# CONFIG_USB_ACECAD is not set
-# CONFIG_USB_KBTAB is not set
-# CONFIG_USB_POWERMATE is not set
-# CONFIG_USB_TOUCHSCREEN is not set
-# CONFIG_USB_YEALINK is not set
-# CONFIG_USB_XPAD is not set
-# CONFIG_USB_ATI_REMOTE is not set
-# CONFIG_USB_ATI_REMOTE2 is not set
-# CONFIG_USB_KEYSPAN_REMOTE is not set
-# CONFIG_USB_APPLETOUCH is not set
-# CONFIG_USB_GTCO is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MICROTEK is not set
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET_MII is not set
-# CONFIG_USB_USBNET is not set
-# CONFIG_USB_MON is not set
-
-#
-# USB port drivers
-#
-
-#
-# USB Serial Converter support
-#
-# CONFIG_USB_SERIAL is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_AUERSWALD is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_BERRY_CHARGE is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGET is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_SISUSBVGA is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_TEST is not set
-
-#
-# USB DSL modem support
-#
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
-# CONFIG_MMC is not set
-
-#
-# LED devices
-#
-# CONFIG_NEW_LEDS is not set
-
-#
-# LED drivers
-#
-
-#
-# LED Triggers
-#
-
-#
-# InfiniBand support
-#
-# CONFIG_INFINIBAND is not set
-
-#
-# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
-#
-
-#
-# Real Time Clock
-#
-# CONFIG_RTC_CLASS is not set
-
-#
-# DMA Engine support
-#
-# CONFIG_DMA_ENGINE is not set
-
-#
-# DMA Clients
-#
-
-#
-# DMA Devices
-#
-
-#
-# Auxiliary Display support
-#
-
-#
-# Virtualization
-#
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT2_FS_XIP is not set
-# CONFIG_EXT3_FS is not set
-# CONFIG_EXT4DEV_FS is not set
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-CONFIG_FS_POSIX_ACL=y
-# CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-# CONFIG_DNOTIFY is not set
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
-CONFIG_GENERIC_ACL=y
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-# CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-CONFIG_CONFIGFS_FS=m
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-# CONFIG_JFFS2_SUMMARY is not set
-# CONFIG_JFFS2_FS_XATTR is not set
-# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-CONFIG_JFFS2_ZLIB=y
-CONFIG_JFFS2_RTIME=y
-# CONFIG_JFFS2_RUBIN is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-# CONFIG_NFS_V3_ACL is not set
-# CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
-# CONFIG_NFSD is not set
-CONFIG_ROOT_NFS=y
-CONFIG_LOCKD=y
-CONFIG_LOCKD_V4=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=y
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-# CONFIG_SMB_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-# CONFIG_SGI_PARTITION is not set
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-
-#
-# Native Language Support
-#
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
-CONFIG_NLS_CODEPAGE_437=m
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-CONFIG_NLS_CODEPAGE_850=m
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-CONFIG_NLS_ISO8859_1=m
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-# CONFIG_NLS_UTF8 is not set
-
-#
-# Distributed Lock Manager
-#
-CONFIG_DLM=m
-CONFIG_DLM_TCP=y
-# CONFIG_DLM_SCTP is not set
-# CONFIG_DLM_DEBUG is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
-
-#
-# Kernel hacking
-#
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-# CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_MUST_CHECK=y
-# CONFIG_MAGIC_SYSRQ is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_KERNEL is not set
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_BLKCIPHER=m
-CONFIG_CRYPTO_HASH=m
-CONFIG_CRYPTO_MANAGER=m
-# CONFIG_CRYPTO_HMAC is not set
-CONFIG_CRYPTO_XCBC=m
-# CONFIG_CRYPTO_NULL is not set
-# CONFIG_CRYPTO_MD4 is not set
-CONFIG_CRYPTO_MD5=y
-# CONFIG_CRYPTO_SHA1 is not set
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_WP512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-CONFIG_CRYPTO_GF128MUL=m
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_LRW=m
-# CONFIG_CRYPTO_DES is not set
-CONFIG_CRYPTO_FCRYPT=m
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_AES is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_ARC4 is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_CRC32C is not set
-CONFIG_CRYPTO_CAMELLIA=m
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Hardware crypto devices
-#
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-# CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
-CONFIG_CRC32=y
-# CONFIG_LIBCRC32C is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_PLIST=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
diff --git a/arch/mips/configs/fuloong2e_defconfig b/arch/mips/configs/fuloong2e_defconfig
index 0197f0de6b3f..a09dd03aa8c8 100644
--- a/arch/mips/configs/fuloong2e_defconfig
+++ b/arch/mips/configs/fuloong2e_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.31-rc1
-# Thu Jul  2 22:37:00 2009
+# Linux kernel version: 2.6.32-rc4
+# Fri Oct 16 13:18:01 2009
 #
 CONFIG_MIPS=y
 
@@ -10,8 +10,8 @@ CONFIG_MIPS=y
 #
 # CONFIG_MACH_ALCHEMY is not set
 # CONFIG_AR7 is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
+# CONFIG_BCM63XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -105,6 +105,8 @@ CONFIG_CPU_LOONGSON2E=y
 # CONFIG_CPU_RM9000 is not set
 # CONFIG_CPU_SB1 is not set
 # CONFIG_CPU_CAVIUM_OCTEON is not set
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_SYS_SUPPORTS_ZBOOT_UART16550=y
 CONFIG_CPU_LOONGSON2=y
 CONFIG_SYS_HAS_CPU_LOONGSON2E=y
 CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
@@ -135,12 +137,16 @@ CONFIG_SYS_SUPPORTS_HIGHMEM=y
 CONFIG_ARCH_FLATMEM_ENABLE=y
 CONFIG_ARCH_POPULATES_NODE_MAP=y
 CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
+# CONFIG_FLATMEM_MANUAL is not set
 # CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM=y
+CONFIG_HAVE_MEMORY_PRESENT=y
 CONFIG_SPARSEMEM_STATIC=y
+
+#
+# Memory hotplug is currently incompatible with Software Suspend
+#
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 CONFIG_PHYS_ADDR_T_64BIT=y
@@ -148,6 +154,7 @@ CONFIG_ZONE_DMA_FLAG=0
 CONFIG_VIRT_TO_BUS=y
 CONFIG_HAVE_MLOCK=y
 CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
 CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 CONFIG_TICK_ONESHOT=y
 CONFIG_NO_HZ=y
@@ -180,6 +187,12 @@ CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
 CONFIG_LOCALVERSION="-fuloong2e"
 # CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_BZIP2 is not set
+# CONFIG_KERNEL_LZMA is not set
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
@@ -193,11 +206,12 @@ CONFIG_BSD_PROCESS_ACCT=y
 #
 # RCU Subsystem
 #
-CONFIG_CLASSIC_RCU=y
-# CONFIG_TREE_RCU is not set
-# CONFIG_PREEMPT_RCU is not set
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=64
+# CONFIG_RCU_FANOUT_EXACT is not set
 # CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_PREEMPT_RCU_TRACE is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
@@ -235,18 +249,16 @@ CONFIG_SHMEM=y
 CONFIG_AIO=y
 
 #
-# Performance Counters
+# Kernel Performance Events And Counters
 #
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_PCI_QUIRKS=y
-# CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_COMPAT_BRK is not set
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
 CONFIG_PROFILING=y
 CONFIG_TRACEPOINTS=y
-CONFIG_MARKERS=y
 CONFIG_OPROFILE=m
 CONFIG_HAVE_OPROFILE=y
 CONFIG_HAVE_SYSCALL_WRAPPERS=y
@@ -255,8 +267,8 @@ CONFIG_HAVE_SYSCALL_WRAPPERS=y
 # GCOV-based kernel profiling
 #
 # CONFIG_GCOV_KERNEL is not set
-# CONFIG_SLOW_WORK is not set
-# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLOW_WORK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 CONFIG_BASE_SMALL=0
@@ -283,7 +295,7 @@ CONFIG_IOSCHED_CFQ=y
 CONFIG_DEFAULT_CFQ=y
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="cfq"
-# CONFIG_FREEZER is not set
+CONFIG_FREEZER=y
 
 #
 # Bus options (PCI, PCMCIA, EISA, ISA, TC)
@@ -321,9 +333,14 @@ CONFIG_ARCH_HIBERNATION_POSSIBLE=y
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
 CONFIG_PM=y
 # CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
 # CONFIG_SUSPEND is not set
-# CONFIG_HIBERNATION is not set
+CONFIG_HIBERNATION_NVS=y
+CONFIG_HIBERNATION=y
+CONFIG_PM_STD_PARTITION="/dev/hda3"
+# CONFIG_PM_RUNTIME is not set
 CONFIG_NET=y
+CONFIG_COMPAT_NETLINK_MESSAGES=y
 
 #
 # Networking options
@@ -442,6 +459,7 @@ CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
 # CONFIG_IP_DCCP is not set
 # CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
@@ -473,6 +491,7 @@ CONFIG_NET_CLS_ROUTE=y
 # CONFIG_AF_RXRPC is not set
 CONFIG_WIRELESS=y
 # CONFIG_CFG80211 is not set
+CONFIG_CFG80211_DEFAULT_PS_VALUE=0
 CONFIG_WIRELESS_OLD_REGULATORY=y
 CONFIG_WIRELESS_EXT=y
 CONFIG_WIRELESS_EXT_SYSFS=y
@@ -481,7 +500,6 @@ CONFIG_WIRELESS_EXT_SYSFS=y
 #
 # CFG80211 needs to be enabled for MAC80211
 #
-CONFIG_MAC80211_DEFAULT_PS_VALUE=0
 # CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
 CONFIG_NET_9P=m
@@ -495,6 +513,7 @@ CONFIG_NET_9P=m
 # Generic Driver Options
 #
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=m
@@ -504,9 +523,9 @@ CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=m
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 # CONFIG_MTD_PARTITIONS is not set
-# CONFIG_MTD_TESTS is not set
 
 #
 # User Modules And Translation Layers
@@ -820,6 +839,7 @@ CONFIG_8139TOO=y
 # CONFIG_SUNDANCE is not set
 # CONFIG_TLAN is not set
 # CONFIG_KS8842 is not set
+# CONFIG_KS8851_MLL is not set
 # CONFIG_VIA_RHINE is not set
 # CONFIG_SC92031 is not set
 # CONFIG_ATL2 is not set
@@ -867,10 +887,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y
 # CONFIG_SFC is not set
 # CONFIG_BE2NET is not set
 # CONFIG_TR is not set
-
-#
-# Wireless LAN
-#
+CONFIG_WLAN=y
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
 
@@ -886,6 +903,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y
 # CONFIG_USB_PEGASUS is not set
 # CONFIG_USB_RTL8150 is not set
 # CONFIG_USB_USBNET is not set
+# CONFIG_USB_CDC_PHONET is not set
 # CONFIG_WAN is not set
 # CONFIG_FDDI is not set
 # CONFIG_HIPPI is not set
@@ -933,12 +951,16 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # Input Device Drivers
 #
 CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
 CONFIG_KEYBOARD_ATKBD=y
-# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_QT2160 is not set
 # CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
 # CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
 # CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
 CONFIG_INPUT_MOUSE=y
 CONFIG_MOUSE_PS2=y
 CONFIG_MOUSE_PS2_ALPS=y
@@ -946,6 +968,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y
 CONFIG_MOUSE_PS2_SYNAPTICS=y
 CONFIG_MOUSE_PS2_TRACKPOINT=y
 # CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_SENTELIC is not set
 # CONFIG_MOUSE_PS2_TOUCHKIT is not set
 CONFIG_MOUSE_SERIAL=y
 # CONFIG_MOUSE_APPLETOUCH is not set
@@ -1015,6 +1038,7 @@ CONFIG_RTC=y
 CONFIG_DEVPORT=y
 CONFIG_I2C=m
 CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
 CONFIG_I2C_CHARDEV=m
 CONFIG_I2C_HELPER_AUTO=y
 
@@ -1070,9 +1094,6 @@ CONFIG_I2C_VIAPRO=m
 # Miscellaneous I2C Chip support
 #
 # CONFIG_DS1682 is not set
-# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_PCF8575 is not set
-# CONFIG_SENSORS_PCA9539 is not set
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
@@ -1088,7 +1109,6 @@ CONFIG_I2C_VIAPRO=m
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
 # CONFIG_THERMAL is not set
-# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 CONFIG_SSB_POSSIBLE=y
 
@@ -1105,6 +1125,7 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_HTC_PASIC3 is not set
 # CONFIG_MFD_TMIO is not set
 # CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
 # CONFIG_MFD_WM8350_I2C is not set
 # CONFIG_MFD_PCF50633 is not set
 # CONFIG_AB3100_CORE is not set
@@ -1114,6 +1135,7 @@ CONFIG_SSB_POSSIBLE=y
 #
 # Graphics support
 #
+CONFIG_VGA_ARB=y
 # CONFIG_DRM is not set
 # CONFIG_VGASTATE is not set
 CONFIG_VIDEO_OUTPUT_CONTROL=m
@@ -1198,6 +1220,7 @@ CONFIG_FONT_8x16=y
 # CONFIG_LOGO is not set
 CONFIG_SOUND=y
 CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
 CONFIG_SND=m
 CONFIG_SND_TIMER=m
 CONFIG_SND_PCM=m
@@ -1304,7 +1327,6 @@ CONFIG_SND_USB=y
 CONFIG_AC97_BUS=m
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
 CONFIG_HIDRAW=y
 
 #
@@ -1356,6 +1378,7 @@ CONFIG_USB_EHCI_TT_NEWSCHED=y
 # CONFIG_USB_OXU210HP_HCD is not set
 # CONFIG_USB_ISP116X_HCD is not set
 CONFIG_USB_ISP1760_HCD=m
+# CONFIG_USB_ISP1362_HCD is not set
 CONFIG_USB_OHCI_HCD=y
 # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
 # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
@@ -1453,6 +1476,7 @@ CONFIG_UIO_CIF=m
 # CONFIG_UIO_SMX is not set
 # CONFIG_UIO_AEC is not set
 # CONFIG_UIO_SERCOS3 is not set
+# CONFIG_UIO_PCI_GENERIC is not set
 
 #
 # TI VLYNQ
@@ -1469,10 +1493,10 @@ CONFIG_EXT3_FS=y
 # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 # CONFIG_EXT3_FS_XATTR is not set
 CONFIG_EXT4_FS=m
-CONFIG_EXT4DEV_COMPAT=y
 CONFIG_EXT4_FS_XATTR=y
 CONFIG_EXT4_FS_POSIX_ACL=y
 CONFIG_EXT4_FS_SECURITY=y
+# CONFIG_EXT4_DEBUG is not set
 CONFIG_FS_XIP=y
 CONFIG_JBD=y
 # CONFIG_JBD_DEBUG is not set
@@ -1489,6 +1513,7 @@ CONFIG_FS_POSIX_ACL=y
 # CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
 CONFIG_FILE_LOCKING=y
 CONFIG_FSNOTIFY=y
 CONFIG_DNOTIFY=y
@@ -1557,7 +1582,6 @@ CONFIG_OMFS_FS=m
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-# CONFIG_NILFS2_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
@@ -1666,6 +1690,7 @@ CONFIG_ENABLE_WARN_DEPRECATED=y
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_FRAME_WARN=2048
 # CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
@@ -1678,13 +1703,14 @@ CONFIG_NOP_TRACER=y
 CONFIG_RING_BUFFER=y
 CONFIG_EVENT_TRACING=y
 CONFIG_CONTEXT_SWITCH_TRACER=y
+CONFIG_RING_BUFFER_ALLOW_SWAP=y
 CONFIG_TRACING=y
 CONFIG_TRACING_SUPPORT=y
 # CONFIG_FTRACE is not set
 # CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
@@ -1742,11 +1768,13 @@ CONFIG_CRYPTO_XTS=m
 #
 CONFIG_CRYPTO_HMAC=y
 # CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
 
 #
 # Digest
 #
 # CONFIG_CRYPTO_CRC32C is not set
+CONFIG_CRYPTO_GHASH=m
 # CONFIG_CRYPTO_MD4 is not set
 CONFIG_CRYPTO_MD5=m
 # CONFIG_CRYPTO_MICHAEL_MIC is not set
diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig
index f14d38ba6034..222d7eca2fe4 100644
--- a/arch/mips/configs/ip22_defconfig
+++ b/arch/mips/configs/ip22_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
@@ -1188,7 +1187,7 @@ CONFIG_DEBUG_MEMORY_INIT=y
 CONFIG_DYNAMIC_PRINTK_DEBUG=y
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig
index 1fc73aa7b509..ed84b4cb3c8d 100644
--- a/arch/mips/configs/ip27_defconfig
+++ b/arch/mips/configs/ip27_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -940,7 +939,7 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/ip28_defconfig b/arch/mips/configs/ip28_defconfig
index 539dccb0345d..dab2e5aaadaf 100644
--- a/arch/mips/configs/ip28_defconfig
+++ b/arch/mips/configs/ip28_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
@@ -816,7 +815,7 @@ CONFIG_MAGIC_SYSRQ=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 # CONFIG_SAMPLES is not set
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig
index d934bdefb393..1841c88d3d24 100644
--- a/arch/mips/configs/ip32_defconfig
+++ b/arch/mips/configs/ip32_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
@@ -1126,7 +1125,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_DYNAMIC_PRINTK_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/jazz_defconfig b/arch/mips/configs/jazz_defconfig
index d22df61833a8..14c2ab3b2674 100644
--- a/arch/mips/configs/jazz_defconfig
+++ b/arch/mips/configs/jazz_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MIPS_DB1550 is not set
 # CONFIG_MIPS_DB1200 is not set
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 CONFIG_MACH_JAZZ=y
@@ -1374,7 +1373,7 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig
index 5380f1f582d9..4d66c44cced8 100644
--- a/arch/mips/configs/jmr3927_defconfig
+++ b/arch/mips/configs/jmr3927_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
@@ -835,7 +834,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_DYNAMIC_PRINTK_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/lasat_defconfig b/arch/mips/configs/lasat_defconfig
index 044074db7e55..08d481e3d42a 100644
--- a/arch/mips/configs/lasat_defconfig
+++ b/arch/mips/configs/lasat_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -798,7 +797,7 @@ CONFIG_MAGIC_SYSRQ=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/lemote2f_defconfig b/arch/mips/configs/lemote2f_defconfig
new file mode 100644
index 000000000000..b71a0a4fb95f
--- /dev/null
+++ b/arch/mips/configs/lemote2f_defconfig
@@ -0,0 +1,1835 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32-rc6
+# Mon Nov  9 23:42:42 2009
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_AR7 is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_BCM63XX is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+CONFIG_MACH_LOONGSON=y
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_NEC_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_NXP_STB220 is not set
+# CONFIG_NXP_STB225 is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
+# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
+# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+# CONFIG_LEMOTE_FULOONG2E is not set
+CONFIG_LEMOTE_MACH2F=y
+CONFIG_CS5536=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_CEVT_R4K_LIB=y
+CONFIG_CEVT_R4K=y
+CONFIG_CSRC_R4K_LIB=y
+CONFIG_CSRC_R4K=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_I8259=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_BOOT_ELF32=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+
+#
+# CPU selection
+#
+# CONFIG_CPU_LOONGSON2E is not set
+CONFIG_CPU_LOONGSON2F=y
+# CONFIG_CPU_MIPS32_R1 is not set
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R5500 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+# CONFIG_CPU_CAVIUM_OCTEON is not set
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_SYS_SUPPORTS_ZBOOT_UART16550=y
+CONFIG_CPU_LOONGSON2=y
+CONFIG_SYS_HAS_CPU_LOONGSON2F=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
+
+#
+# Kernel type
+#
+# CONFIG_32BIT is not set
+CONFIG_64BIT=y
+# CONFIG_PAGE_SIZE_4KB is not set
+# CONFIG_PAGE_SIZE_8KB is not set
+CONFIG_PAGE_SIZE_16KB=y
+# CONFIG_PAGE_SIZE_32KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_BOARD_SCACHE=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+CONFIG_CPU_HAS_WB=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_FLATMEM_MANUAL is not set
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM=y
+CONFIG_HAVE_MEMORY_PRESENT=y
+CONFIG_SPARSEMEM_STATIC=y
+
+#
+# Memory hotplug is currently incompatible with Software Suspend
+#
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_128 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_256 is not set
+# CONFIG_HZ_1000 is not set
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=250
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+# CONFIG_KEXEC is not set
+# CONFIG_SECCOMP is not set
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+# CONFIG_KERNEL_GZIP is not set
+# CONFIG_KERNEL_BZIP2 is not set
+CONFIG_KERNEL_LZMA=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+CONFIG_AUDIT=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=64
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=15
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_PCI_QUIRKS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_SYSCALL_WRAPPERS=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLOCK_COMPAT=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_HW_HAS_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
+CONFIG_ISA=y
+CONFIG_MMU=y
+# CONFIG_PCCARD is not set
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_MIPS32_COMPAT=y
+CONFIG_COMPAT=y
+CONFIG_SYSVIPC_COMPAT=y
+CONFIG_MIPS32_O32=y
+CONFIG_MIPS32_N32=y
+CONFIG_BINFMT_ELF32=y
+
+#
+# Power management options
+#
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_HIBERNATION_NVS=y
+CONFIG_HIBERNATION=y
+CONFIG_PM_STD_PARTITION="/dev/hda3"
+# CONFIG_PM_RUNTIME is not set
+CONFIG_NET=y
+CONFIG_COMPAT_NETLINK_MESSAGES=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_BIC=y
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_TCP_CONG_WESTWOOD=m
+CONFIG_TCP_CONG_HTCP=m
+# CONFIG_TCP_CONG_HSTCP is not set
+# CONFIG_TCP_CONG_HYBLA is not set
+# CONFIG_TCP_CONG_VEGAS is not set
+# CONFIG_TCP_CONG_SCALABLE is not set
+# CONFIG_TCP_CONG_LP is not set
+# CONFIG_TCP_CONG_VENO is not set
+# CONFIG_TCP_CONG_YEAH is not set
+# CONFIG_TCP_CONG_ILLINOIS is not set
+CONFIG_DEFAULT_BIC=y
+# CONFIG_DEFAULT_CUBIC is not set
+# CONFIG_DEFAULT_HTCP is not set
+# CONFIG_DEFAULT_VEGAS is not set
+# CONFIG_DEFAULT_WESTWOOD is not set
+# CONFIG_DEFAULT_RENO is not set
+CONFIG_DEFAULT_TCP_CONG="bic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=m
+CONFIG_IPV6_PRIVACY=y
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+CONFIG_NETWORK_SECMARK=y
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NETFILTER_XTABLES is not set
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_NF_DEFRAG_IPV4 is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+
+#
+# IPv6: Netfilter Configuration
+#
+# CONFIG_IP6_NF_QUEUE is not set
+# CONFIG_IP6_NF_IPTABLES is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+# CONFIG_NET_SCH_CBQ is not set
+# CONFIG_NET_SCH_HTB is not set
+# CONFIG_NET_SCH_HFSC is not set
+# CONFIG_NET_SCH_PRIO is not set
+# CONFIG_NET_SCH_MULTIQ is not set
+# CONFIG_NET_SCH_RED is not set
+# CONFIG_NET_SCH_SFQ is not set
+# CONFIG_NET_SCH_TEQL is not set
+# CONFIG_NET_SCH_TBF is not set
+# CONFIG_NET_SCH_GRED is not set
+# CONFIG_NET_SCH_DSMARK is not set
+# CONFIG_NET_SCH_NETEM is not set
+# CONFIG_NET_SCH_DRR is not set
+# CONFIG_NET_SCH_INGRESS is not set
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+# CONFIG_NET_CLS_BASIC is not set
+# CONFIG_NET_CLS_TCINDEX is not set
+# CONFIG_NET_CLS_ROUTE4 is not set
+# CONFIG_NET_CLS_FW is not set
+# CONFIG_NET_CLS_U32 is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_FLOW is not set
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_STACK=32
+# CONFIG_NET_EMATCH_CMP is not set
+# CONFIG_NET_EMATCH_NBYTE is not set
+# CONFIG_NET_EMATCH_U32 is not set
+# CONFIG_NET_EMATCH_META is not set
+# CONFIG_NET_EMATCH_TEXT is not set
+CONFIG_NET_CLS_ACT=y
+# CONFIG_NET_ACT_POLICE is not set
+# CONFIG_NET_ACT_GACT is not set
+# CONFIG_NET_ACT_MIRRED is not set
+# CONFIG_NET_ACT_NAT is not set
+# CONFIG_NET_ACT_PEDIT is not set
+# CONFIG_NET_ACT_SIMP is not set
+# CONFIG_NET_ACT_SKBEDIT is not set
+CONFIG_NET_SCH_FIFO=y
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_FIB_RULES=y
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+CONFIG_CFG80211_DEFAULT_PS_VALUE=0
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+# CONFIG_WIMAX is not set
+CONFIG_RFKILL=m
+# CONFIG_RFKILL_INPUT is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+# CONFIG_PNP is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=8192
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_CB710_CORE is not set
+CONFIG_HAVE_IDE=y
+CONFIG_IDE=y
+
+#
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
+#
+CONFIG_IDE_XFER_MODE=y
+CONFIG_IDE_TIMINGS=y
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_IDE_GD=y
+CONFIG_IDE_GD_ATA=y
+# CONFIG_IDE_GD_ATAPI is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+CONFIG_IDE_TASK_IOCTL=y
+CONFIG_IDE_PROC_FS=y
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
+CONFIG_BLK_DEV_IDEDMA_SFF=y
+
+#
+# PCI IDE chipsets support
+#
+CONFIG_BLK_DEV_IDEPCI=y
+# CONFIG_IDEPCI_PCIBUS_ORDER is not set
+# CONFIG_BLK_DEV_OFFBOARD is not set
+CONFIG_BLK_DEV_GENERIC=y
+# CONFIG_BLK_DEV_OPTI621 is not set
+CONFIG_BLK_DEV_IDEDMA_PCI=y
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+CONFIG_BLK_DEV_AMD74XX=y
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_TRIFLEX is not set
+# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_JMICRON is not set
+# CONFIG_BLK_DEV_SC1200 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_IT8172 is not set
+# CONFIG_BLK_DEV_IT8213 is not set
+# CONFIG_BLK_DEV_IT821X is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIIMAGE is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_BLK_DEV_TC86C001 is not set
+
+#
+# Other IDE chipsets support
+#
+
+#
+# Note: most of these also require special kernel boot parameters
+#
+# CONFIG_BLK_DEV_4DRIVES is not set
+# CONFIG_BLK_DEV_ALI14XX is not set
+# CONFIG_BLK_DEV_DTC2278 is not set
+# CONFIG_BLK_DEV_HT6560B is not set
+# CONFIG_BLK_DEV_QD65XX is not set
+# CONFIG_BLK_DEV_UMC8672 is not set
+CONFIG_BLK_DEV_IDEDMA=y
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# You can enable one or both FireWire driver stacks.
+#
+
+#
+# See the help texts for more information.
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_IFB is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_DNET is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_AT1700 is not set
+# CONFIG_DEPCA is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_AC3200 is not set
+# CONFIG_APRICOT is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_TC35815 is not set
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_8139CP is not set
+CONFIG_8139TOO=y
+# CONFIG_8139TOO_PIO is not set
+CONFIG_8139TOO_TUNE_TWISTER=y
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_OLD_RX_RESET is not set
+# CONFIG_R6040 is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SMSC9420 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_SC92031 is not set
+# CONFIG_ATL2 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_IGBVF is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+CONFIG_R8169=y
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_CNIC is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_ATL1C is not set
+# CONFIG_JME is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+CONFIG_WLAN=y
+CONFIG_WLAN_PRE80211=y
+# CONFIG_STRIP is not set
+# CONFIG_WAVELAN is not set
+CONFIG_WLAN_80211=y
+# CONFIG_LIBERTAS is not set
+# CONFIG_ATMEL is not set
+# CONFIG_PRISM54 is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_HOSTAP is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_USB_HSO is not set
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+# CONFIG_MOUSE_PS2_ALPS is not set
+# CONFIG_MOUSE_PS2_LOGIPS2PP is not set
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+# CONFIG_MOUSE_PS2_TRACKPOINT is not set
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_SENTELIC is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_INPORT is not set
+# CONFIG_MOUSE_LOGIBM is not set
+# CONFIG_MOUSE_PC110PAD is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+CONFIG_SERIAL_NONSTANDARD=y
+# CONFIG_COMPUTONE is not set
+# CONFIG_ROCKETPORT is not set
+# CONFIG_CYCLADES is not set
+# CONFIG_DIGIEPCA is not set
+# CONFIG_MOXA_INTELLIO is not set
+# CONFIG_MOXA_SMARTIO is not set
+# CONFIG_ISI is not set
+# CONFIG_SYNCLINKMP is not set
+# CONFIG_SYNCLINK_GT is not set
+# CONFIG_N_HDLC is not set
+# CONFIG_RISCOM8 is not set
+# CONFIG_SPECIALIX is not set
+# CONFIG_STALDRV is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+CONFIG_SERIAL_8250_NR_UARTS=16
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_FOURPORT=y
+# CONFIG_SERIAL_8250_ACCENT is not set
+# CONFIG_SERIAL_8250_BOCA is not set
+# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set
+# CONFIG_SERIAL_8250_HUB6 is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=16
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+CONFIG_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_I5K_AMB is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+CONFIG_THERMAL=y
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_REGULATOR is not set
+CONFIG_MEDIA_SUPPORT=m
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_V4L2_COMMON=m
+CONFIG_VIDEO_ALLOW_V4L1=y
+CONFIG_VIDEO_V4L1_COMPAT=y
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=m
+
+#
+# Multimedia drivers
+#
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEO_V4L1=m
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_PMS is not set
+# CONFIG_VIDEO_CPIA is not set
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_VIDEO_STRADIS is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_GSPCA=m
+# CONFIG_USB_M5602 is not set
+# CONFIG_USB_STV06XX is not set
+# CONFIG_USB_GL860 is not set
+# CONFIG_USB_GSPCA_CONEX is not set
+# CONFIG_USB_GSPCA_ETOMS is not set
+# CONFIG_USB_GSPCA_FINEPIX is not set
+# CONFIG_USB_GSPCA_JEILINJ is not set
+# CONFIG_USB_GSPCA_MARS is not set
+# CONFIG_USB_GSPCA_MR97310A is not set
+# CONFIG_USB_GSPCA_OV519 is not set
+# CONFIG_USB_GSPCA_OV534 is not set
+# CONFIG_USB_GSPCA_PAC207 is not set
+# CONFIG_USB_GSPCA_PAC7311 is not set
+# CONFIG_USB_GSPCA_SN9C20X is not set
+# CONFIG_USB_GSPCA_SONIXB is not set
+# CONFIG_USB_GSPCA_SONIXJ is not set
+# CONFIG_USB_GSPCA_SPCA500 is not set
+# CONFIG_USB_GSPCA_SPCA501 is not set
+# CONFIG_USB_GSPCA_SPCA505 is not set
+# CONFIG_USB_GSPCA_SPCA506 is not set
+# CONFIG_USB_GSPCA_SPCA508 is not set
+# CONFIG_USB_GSPCA_SPCA561 is not set
+# CONFIG_USB_GSPCA_SQ905 is not set
+# CONFIG_USB_GSPCA_SQ905C is not set
+# CONFIG_USB_GSPCA_STK014 is not set
+# CONFIG_USB_GSPCA_SUNPLUS is not set
+# CONFIG_USB_GSPCA_T613 is not set
+# CONFIG_USB_GSPCA_TV8532 is not set
+# CONFIG_USB_GSPCA_VC032X is not set
+# CONFIG_USB_GSPCA_ZC3XX is not set
+# CONFIG_VIDEO_HDPVR is not set
+# CONFIG_USB_VICAM is not set
+# CONFIG_USB_IBMCAM is not set
+# CONFIG_USB_KONICAWC is not set
+# CONFIG_USB_QUICKCAM_MESSENGER is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_USB_OV511 is not set
+# CONFIG_USB_SE401 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_STV680 is not set
+# CONFIG_USB_ZC0301 is not set
+# CONFIG_USB_PWC is not set
+CONFIG_USB_PWC_INPUT_EVDEV=y
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_USB_S2255 is not set
+# CONFIG_RADIO_ADAPTERS is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+CONFIG_VGA_ARB=y
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
+# CONFIG_FB_DDC is not set
+CONFIG_FB_BOOT_VESA_SUPPORT=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+CONFIG_FB_SIS=y
+CONFIG_FB_SIS_300=y
+CONFIG_FB_SIS_315=y
+# CONFIG_FB_VIA is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_FONT_6x11=y
+CONFIG_FONT_7x14=y
+CONFIG_FONT_PEARL_8x8=y
+CONFIG_FONT_ACORN_8x8=y
+CONFIG_FONT_MINI_4x6=y
+CONFIG_FONT_SUN8x16=y
+CONFIG_FONT_SUN12x22=y
+CONFIG_FONT_10x18=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=m
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_HRTIMER is not set
+# CONFIG_SND_RTCTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_AC97_CODEC=m
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_PCI=y
+# CONFIG_SND_AD1889 is not set
+# CONFIG_SND_ALS300 is not set
+# CONFIG_SND_ALI5451 is not set
+# CONFIG_SND_ATIIXP is not set
+# CONFIG_SND_ATIIXP_MODEM is not set
+# CONFIG_SND_AU8810 is not set
+# CONFIG_SND_AU8820 is not set
+# CONFIG_SND_AU8830 is not set
+# CONFIG_SND_AW2 is not set
+# CONFIG_SND_AZT3328 is not set
+# CONFIG_SND_BT87X is not set
+# CONFIG_SND_CA0106 is not set
+# CONFIG_SND_CMIPCI is not set
+# CONFIG_SND_OXYGEN is not set
+# CONFIG_SND_CS4281 is not set
+# CONFIG_SND_CS46XX is not set
+CONFIG_SND_CS5535AUDIO=m
+# CONFIG_SND_CTXFI is not set
+# CONFIG_SND_DARLA20 is not set
+# CONFIG_SND_GINA20 is not set
+# CONFIG_SND_LAYLA20 is not set
+# CONFIG_SND_DARLA24 is not set
+# CONFIG_SND_GINA24 is not set
+# CONFIG_SND_LAYLA24 is not set
+# CONFIG_SND_MONA is not set
+# CONFIG_SND_MIA is not set
+# CONFIG_SND_ECHO3G is not set
+# CONFIG_SND_INDIGO is not set
+# CONFIG_SND_INDIGOIO is not set
+# CONFIG_SND_INDIGODJ is not set
+# CONFIG_SND_INDIGOIOX is not set
+# CONFIG_SND_INDIGODJX is not set
+# CONFIG_SND_EMU10K1 is not set
+# CONFIG_SND_EMU10K1X is not set
+# CONFIG_SND_ENS1370 is not set
+# CONFIG_SND_ENS1371 is not set
+# CONFIG_SND_ES1938 is not set
+# CONFIG_SND_ES1968 is not set
+# CONFIG_SND_FM801 is not set
+# CONFIG_SND_HDA_INTEL is not set
+# CONFIG_SND_HDSP is not set
+# CONFIG_SND_HDSPM is not set
+# CONFIG_SND_HIFIER is not set
+# CONFIG_SND_ICE1712 is not set
+# CONFIG_SND_ICE1724 is not set
+# CONFIG_SND_INTEL8X0 is not set
+# CONFIG_SND_INTEL8X0M is not set
+# CONFIG_SND_KORG1212 is not set
+# CONFIG_SND_LX6464ES is not set
+# CONFIG_SND_MAESTRO3 is not set
+# CONFIG_SND_MIXART is not set
+# CONFIG_SND_NM256 is not set
+# CONFIG_SND_PCXHR is not set
+# CONFIG_SND_RIPTIDE is not set
+# CONFIG_SND_RME32 is not set
+# CONFIG_SND_RME96 is not set
+# CONFIG_SND_RME9652 is not set
+# CONFIG_SND_SONICVIBES is not set
+# CONFIG_SND_TRIDENT is not set
+# CONFIG_SND_VIA82XX is not set
+# CONFIG_SND_VIA82XX_MODEM is not set
+# CONFIG_SND_VIRTUOSO is not set
+# CONFIG_SND_VX222 is not set
+# CONFIG_SND_YMFPCI is not set
+# CONFIG_SND_MIPS is not set
+# CONFIG_SND_USB is not set
+# CONFIG_SND_SOC is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=m
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HIDRAW=y
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+CONFIG_USB_HIDDEV=y
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+CONFIG_USB_SUSPEND=y
+# CONFIG_USB_OTG is not set
+CONFIG_USB_OTG_WHITELIST=y
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_XHCI_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_UHCI_HCD=m
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_WHCI_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+# CONFIG_USB_PRINTER is not set
+CONFIG_USB_WDM=m
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+CONFIG_USB_STORAGE_DATAFAB=m
+CONFIG_USB_STORAGE_FREECOM=m
+CONFIG_USB_STORAGE_ISD200=m
+CONFIG_USB_STORAGE_USBAT=m
+CONFIG_USB_STORAGE_SDDR09=m
+CONFIG_USB_STORAGE_SDDR55=m
+CONFIG_USB_STORAGE_JUMPSHOT=m
+CONFIG_USB_STORAGE_ALAUDA=m
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+# CONFIG_USB_EZUSB is not set
+CONFIG_USB_SERIAL_GENERIC=y
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_CP210X is not set
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_QUALCOMM is not set
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_SYMBOL is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OPTION is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_OPTICON is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_UWB is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+CONFIG_STAGING=y
+# CONFIG_STAGING_EXCLUDE_BUILD is not set
+# CONFIG_ET131X is not set
+# CONFIG_USB_IP_COMMON is not set
+# CONFIG_PRISM2_USB is not set
+# CONFIG_ECHO is not set
+# CONFIG_COMEDI is not set
+# CONFIG_ASUS_OLED is not set
+# CONFIG_ALTERA_PCIE_CHDMA is not set
+# CONFIG_RTL8187SE is not set
+# CONFIG_RTL8192SU is not set
+# CONFIG_RTL8192E is not set
+# CONFIG_INPUT_MIMIO is not set
+# CONFIG_TRANZPORT is not set
+
+#
+# Android
+#
+
+#
+# Qualcomm MSM Camera And Video
+#
+
+#
+# Camera Sensor Selection
+#
+# CONFIG_INPUT_GPIO is not set
+# CONFIG_DST is not set
+# CONFIG_POHMELFS is not set
+# CONFIG_B3DFG is not set
+# CONFIG_PLAN9AUTH is not set
+# CONFIG_LINE6_USB is not set
+# CONFIG_USB_SERIAL_QUATECH2 is not set
+# CONFIG_USB_SERIAL_QUATECH_USB2 is not set
+# CONFIG_VT6655 is not set
+# CONFIG_VT6656 is not set
+# CONFIG_FB_UDL is not set
+# CONFIG_VME_BUS is not set
+
+#
+# RAR Register Driver
+#
+# CONFIG_RAR_REGISTER is not set
+# CONFIG_IIO is not set
+CONFIG_FB_SM7XX=y
+CONFIG_FB_SM7XX_ACCEL=y
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=m
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=m
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=m
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=m
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf-8"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+CONFIG_STRIP_ASM_SYMS=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_CMDLINE_BOOL is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+CONFIG_CRC_T10DIF=y
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_AUDIT_GENERIC=y
+CONFIG_ZLIB_INFLATE=m
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig
index 3f01870b4d65..d3c601206db2 100644
--- a/arch/mips/configs/malta_defconfig
+++ b/arch/mips/configs/malta_defconfig
@@ -10,7 +10,6 @@ CONFIG_MIPS=y
 #
 CONFIG_ZONE_DMA=y
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
@@ -1591,7 +1590,7 @@ CONFIG_FRAME_WARN=1024
 # CONFIG_DYNAMIC_PRINTK_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/markeins_defconfig b/arch/mips/configs/markeins_defconfig
index d001f7e87418..6a325c02b63c 100644
--- a/arch/mips/configs/markeins_defconfig
+++ b/arch/mips/configs/markeins_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MIPS_DB1550 is not set
 # CONFIG_MIPS_DB1200 is not set
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -1366,7 +1365,9 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
+CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="console=ttyS0,115200 mem=192m ip=bootp root=/dev/nfs rw"
+# CONFIG_CMDLINE_OVERRIDE is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig
index 7358454deaa6..f77a34e0f938 100644
--- a/arch/mips/configs/mipssim_defconfig
+++ b/arch/mips/configs/mipssim_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
@@ -635,7 +634,9 @@ CONFIG_FORCED_INLINING=y
 # CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_FAULT_INJECTION is not set
 CONFIG_CROSSCOMPILE=y
+CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="nfsroot=192.168.192.169:/u1/mipsel,timeo=20 ip=dhcp"
+# CONFIG_CMDLINE_OVERRIDE is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
 # CONFIG_RUNTIME_DEBUG is not set
 
diff --git a/arch/mips/configs/mpc30x_defconfig b/arch/mips/configs/mpc30x_defconfig
index 8c720e51795b..17203056b22b 100644
--- a/arch/mips/configs/mpc30x_defconfig
+++ b/arch/mips/configs/mpc30x_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -817,7 +816,9 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_CROSSCOMPILE=y
+CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="mem=32M console=ttyVR0,19200 ide0=0x170,0x376,73"
+# CONFIG_CMDLINE_OVERRIDE is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/msp71xx_defconfig b/arch/mips/configs/msp71xx_defconfig
index ecbc030b7b6c..000d185ddf42 100644
--- a/arch/mips/configs/msp71xx_defconfig
+++ b/arch/mips/configs/msp71xx_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MIPS_DB1550 is not set
 # CONFIG_MIPS_DB1200 is not set
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -1412,7 +1411,7 @@ CONFIG_FORCED_INLINING=y
 # CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_FAULT_INJECTION is not set
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
 # CONFIG_RUNTIME_DEBUG is not set
 # CONFIG_MIPS_UNCACHED is not set
diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig
index 9477f040796d..144b94d9a6ad 100644
--- a/arch/mips/configs/mtx1_defconfig
+++ b/arch/mips/configs/mtx1_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 CONFIG_MACH_ALCHEMY=y
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -3018,7 +3017,7 @@ CONFIG_MAGIC_SYSRQ=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig
index be8091ef0a79..ddf67f639194 100644
--- a/arch/mips/configs/pb1100_defconfig
+++ b/arch/mips/configs/pb1100_defconfig
@@ -23,7 +23,6 @@ CONFIG_MIPS_PB1100=y
 # CONFIG_MIPS_DB1550 is not set
 # CONFIG_MIPS_DB1200 is not set
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -1083,7 +1082,7 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig
index e74ba794c789..5ec60836b645 100644
--- a/arch/mips/configs/pb1500_defconfig
+++ b/arch/mips/configs/pb1500_defconfig
@@ -23,7 +23,6 @@ CONFIG_MIPS_PB1500=y
 # CONFIG_MIPS_DB1550 is not set
 # CONFIG_MIPS_DB1200 is not set
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -1200,7 +1199,7 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig
index 1d896fd830da..6647642b5d97 100644
--- a/arch/mips/configs/pb1550_defconfig
+++ b/arch/mips/configs/pb1550_defconfig
@@ -23,7 +23,6 @@ CONFIG_MIPS_PB1550=y
 # CONFIG_MIPS_DB1550 is not set
 # CONFIG_MIPS_DB1200 is not set
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -1193,7 +1192,7 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/pnx8335-stb225_defconfig b/arch/mips/configs/pnx8335-stb225_defconfig
index fef4d31c2055..848344d588d1 100644
--- a/arch/mips/configs/pnx8335-stb225_defconfig
+++ b/arch/mips/configs/pnx8335-stb225_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
@@ -1034,7 +1033,7 @@ CONFIG_FRAME_WARN=1024
 # CONFIG_DEBUG_KERNEL is not set
 # CONFIG_SAMPLES is not set
 # CONFIG_KERNEL_TESTS is not set
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig
index e10c7116c3c2..9d721fdccb30 100644
--- a/arch/mips/configs/pnx8550-jbs_defconfig
+++ b/arch/mips/configs/pnx8550-jbs_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MIPS_DB1550 is not set
 # CONFIG_MIPS_DB1200 is not set
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -1215,7 +1214,9 @@ CONFIG_DEBUG_MUTEXES=y
 CONFIG_FORCED_INLINING=y
 # CONFIG_RCU_TORTURE_TEST is not set
 CONFIG_CROSSCOMPILE=y
+CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp"
+# CONFIG_CMDLINE_OVERRIDE is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
 # CONFIG_RUNTIME_DEBUG is not set
 
diff --git a/arch/mips/configs/pnx8550-stb810_defconfig b/arch/mips/configs/pnx8550-stb810_defconfig
index 5ed3c8dfa0a1..ab07ec08c6fa 100644
--- a/arch/mips/configs/pnx8550-stb810_defconfig
+++ b/arch/mips/configs/pnx8550-stb810_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MIPS_DB1550 is not set
 # CONFIG_MIPS_DB1200 is not set
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -1205,7 +1204,9 @@ CONFIG_DEBUG_SLAB=y
 CONFIG_FORCED_INLINING=y
 # CONFIG_RCU_TORTURE_TEST is not set
 CONFIG_CROSSCOMPILE=y
+CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp"
+# CONFIG_CMDLINE_OVERRIDE is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
 # CONFIG_RUNTIME_DEBUG is not set
 
diff --git a/arch/mips/configs/powertv_defconfig b/arch/mips/configs/powertv_defconfig
new file mode 100644
index 000000000000..7291633d81cc
--- /dev/null
+++ b/arch/mips/configs/powertv_defconfig
@@ -0,0 +1,1550 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.31-rc5
+# Fri Aug 28 14:49:33 2009
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_AR7 is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_LEMOTE_FULONG is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_NEC_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_NXP_STB220 is not set
+# CONFIG_NXP_STB225 is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+CONFIG_POWERTV=y
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
+# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
+# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
+# CONFIG_MIN_RUNTIME_RESOURCES is not set
+# CONFIG_BOOTLOADER_DRIVER is not set
+CONFIG_BOOTLOADER_FAMILY="R2"
+CONFIG_CSRC_POWERTV=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_CEVT_R4K_LIB=y
+CONFIG_CEVT_R4K=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+# CONFIG_EARLY_PRINTK is not set
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_CPU_BIG_ENDIAN=y
+# CONFIG_CPU_LITTLE_ENDIAN is not set
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_BOOT_ELF32=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+
+#
+# CPU selection
+#
+# CONFIG_CPU_LOONGSON2 is not set
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R5500 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+# CONFIG_CPU_CAVIUM_OCTEON is not set
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+
+#
+# Kernel type
+#
+CONFIG_32BIT=y
+# CONFIG_64BIT is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_32KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+CONFIG_CPU_HAS_LLSC=y
+CONFIG_CPU_MIPSR2_IRQ_VI=y
+CONFIG_CPU_MIPSR2_IRQ_EI=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+# CONFIG_HIGHMEM is not set
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_128 is not set
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_256 is not set
+CONFIG_HZ_1000=y
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=1000
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+# CONFIG_KEXEC is not set
+# CONFIG_SECCOMP is not set
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_RD_GZIP is not set
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_PCSPKR_PLATFORM is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+# CONFIG_EPOLL is not set
+# CONFIG_SIGNALFD is not set
+CONFIG_TIMERFD=y
+# CONFIG_EVENTFD is not set
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Performance Counters
+#
+# CONFIG_VM_EVENT_COUNTERS is not set
+CONFIG_PCI_QUIRKS=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_SLOW_WORK is not set
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+# CONFIG_PROBE_INITRD_HEADER is not set
+# CONFIG_FREEZER is not set
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_HW_HAS_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCI_LEGACY is not set
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
+CONFIG_MMU=y
+# CONFIG_PCCARD is not set
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_TRAD_SIGNALS=y
+
+#
+# Power management options
+#
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_PM is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_MULTIPLE_TABLES is not set
+# CONFIG_IP_ROUTE_MULTIPATH is not set
+# CONFIG_IP_ROUTE_VERBOSE is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=y
+CONFIG_IPV6_PRIVACY=y
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+CONFIG_INET6_AH=y
+CONFIG_INET6_ESP=y
+CONFIG_INET6_IPCOMP=y
+# CONFIG_IPV6_MIP6 is not set
+CONFIG_INET6_XFRM_TUNNEL=y
+CONFIG_INET6_TUNNEL=y
+# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET6_XFRM_MODE_BEET is not set
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+# CONFIG_IPV6_SIT is not set
+CONFIG_IPV6_TUNNEL=y
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+# CONFIG_BRIDGE_NETFILTER is not set
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NF_CONNTRACK is not set
+CONFIG_NETFILTER_XTABLES=y
+# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
+# CONFIG_NETFILTER_XT_TARGET_MARK is not set
+# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
+# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
+# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
+# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
+# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
+# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
+# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
+# CONFIG_NETFILTER_XT_MATCH_ESP is not set
+# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_HL is not set
+# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
+# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
+# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_MAC is not set
+# CONFIG_NETFILTER_XT_MATCH_MARK is not set
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
+# CONFIG_NETFILTER_XT_MATCH_POLICY is not set
+# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
+# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
+# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
+# CONFIG_NETFILTER_XT_MATCH_REALM is not set
+# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
+# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
+# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
+# CONFIG_NETFILTER_XT_MATCH_STRING is not set
+# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
+# CONFIG_NETFILTER_XT_MATCH_TIME is not set
+# CONFIG_NETFILTER_XT_MATCH_U32 is not set
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_NF_DEFRAG_IPV4 is not set
+# CONFIG_IP_NF_QUEUE is not set
+CONFIG_IP_NF_IPTABLES=y
+# CONFIG_IP_NF_MATCH_ADDRTYPE is not set
+# CONFIG_IP_NF_MATCH_AH is not set
+# CONFIG_IP_NF_MATCH_ECN is not set
+# CONFIG_IP_NF_MATCH_TTL is not set
+CONFIG_IP_NF_FILTER=y
+# CONFIG_IP_NF_TARGET_REJECT is not set
+# CONFIG_IP_NF_TARGET_LOG is not set
+# CONFIG_IP_NF_TARGET_ULOG is not set
+# CONFIG_IP_NF_MANGLE is not set
+# CONFIG_IP_NF_TARGET_TTL is not set
+# CONFIG_IP_NF_RAW is not set
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+# CONFIG_IP_NF_ARP_MANGLE is not set
+
+#
+# IPv6: Netfilter Configuration
+#
+# CONFIG_IP6_NF_QUEUE is not set
+CONFIG_IP6_NF_IPTABLES=y
+# CONFIG_IP6_NF_MATCH_AH is not set
+# CONFIG_IP6_NF_MATCH_EUI64 is not set
+# CONFIG_IP6_NF_MATCH_FRAG is not set
+# CONFIG_IP6_NF_MATCH_OPTS is not set
+# CONFIG_IP6_NF_MATCH_HL is not set
+# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set
+# CONFIG_IP6_NF_MATCH_MH is not set
+# CONFIG_IP6_NF_MATCH_RT is not set
+# CONFIG_IP6_NF_TARGET_HL is not set
+# CONFIG_IP6_NF_TARGET_LOG is not set
+CONFIG_IP6_NF_FILTER=y
+# CONFIG_IP6_NF_TARGET_REJECT is not set
+# CONFIG_IP6_NF_MANGLE is not set
+# CONFIG_IP6_NF_RAW is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_STP=y
+CONFIG_BRIDGE=y
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=y
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+# CONFIG_NET_SCH_CBQ is not set
+# CONFIG_NET_SCH_HTB is not set
+# CONFIG_NET_SCH_HFSC is not set
+# CONFIG_NET_SCH_PRIO is not set
+# CONFIG_NET_SCH_MULTIQ is not set
+# CONFIG_NET_SCH_RED is not set
+# CONFIG_NET_SCH_SFQ is not set
+# CONFIG_NET_SCH_TEQL is not set
+CONFIG_NET_SCH_TBF=y
+# CONFIG_NET_SCH_GRED is not set
+# CONFIG_NET_SCH_DSMARK is not set
+# CONFIG_NET_SCH_NETEM is not set
+# CONFIG_NET_SCH_DRR is not set
+
+#
+# Classification
+#
+# CONFIG_NET_CLS_BASIC is not set
+# CONFIG_NET_CLS_TCINDEX is not set
+# CONFIG_NET_CLS_ROUTE4 is not set
+# CONFIG_NET_CLS_FW is not set
+# CONFIG_NET_CLS_U32 is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_FLOW is not set
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+CONFIG_NET_SCH_FIFO=y
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=32768
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
+# CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_SVW is not set
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# You can enable one or both FireWire driver stacks.
+#
+
+#
+# See the help texts for more information.
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_DNET is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_ATL2 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_IGBVF is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_CNIC is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_ATL1C is not set
+# CONFIG_JME is not set
+CONFIG_NETDEV_10000=y
+# CONFIG_CHELSIO_T1 is not set
+CONFIG_CHELSIO_T3_DEPENDS=y
+# CONFIG_CHELSIO_T3 is not set
+# CONFIG_ENIC is not set
+# CONFIG_IXGBE is not set
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+# CONFIG_VXGE is not set
+# CONFIG_MYRI10GE is not set
+# CONFIG_NETXEN_NIC is not set
+# CONFIG_NIU is not set
+# CONFIG_MLX4_EN is not set
+# CONFIG_MLX4_CORE is not set
+# CONFIG_TEHUTI is not set
+# CONFIG_BNX2X is not set
+# CONFIG_QLGE is not set
+# CONFIG_SFC is not set
+# CONFIG_BE2NET is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+CONFIG_USB_RTL8150=y
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+CONFIG_USB_HIDDEV=y
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_XHCI_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_WHCI_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_CONSOLE=y
+# CONFIG_USB_EZUSB is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+CONFIG_USB_SERIAL_CP210X=y
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_QUALCOMM is not set
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_SYMBOL is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OPTION is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_OPTICON is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_UWB is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+# CONFIG_CUSE is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_KMEMCHECK is not set
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="rw dhash_entries=1024 ihash_entries=1024 ip=10.0.1.3:10.0.1.1:10.0.1.1:255.255.255.0:zeus:eth0: root=/dev/nfs nfsroot=/nfsroot/cramfs,wsize=512,rsize=512,tcp nokgdb console=ttyUSB0,115200 memsize=252M"
+# CONFIG_CMDLINE_OVERRIDE is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_RUNTIME_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/mips/configs/rb532_defconfig b/arch/mips/configs/rb532_defconfig
index f40c3a04739d..57a50483abdf 100644
--- a/arch/mips/configs/rb532_defconfig
+++ b/arch/mips/configs/rb532_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
@@ -1204,7 +1203,7 @@ CONFIG_FRAME_WARN=1024
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 # CONFIG_SAMPLES is not set
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/rbtx49xx_defconfig b/arch/mips/configs/rbtx49xx_defconfig
index 6c6a19aebe1f..21c2022d46ee 100644
--- a/arch/mips/configs/rbtx49xx_defconfig
+++ b/arch/mips/configs/rbtx49xx_defconfig
@@ -10,7 +10,6 @@ CONFIG_MIPS=y
 #
 # CONFIG_MACH_ALCHEMY is not set
 # CONFIG_AR7 is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM63XX is not set
 # CONFIG_MIPS_COBALT is not set
@@ -284,7 +283,6 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
-# CONFIG_PROBE_INITRD_HEADER is not set
 # CONFIG_FREEZER is not set
 
 #
@@ -1063,7 +1061,7 @@ CONFIG_TRACING_SUPPORT=y
 # CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig
index e53b8d096cfc..790362890033 100644
--- a/arch/mips/configs/rm200_defconfig
+++ b/arch/mips/configs/rm200_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MIPS_DB1550 is not set
 # CONFIG_MIPS_DB1200 is not set
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -1694,7 +1693,7 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig
index 7f38c0b956f3..7f07bf02b838 100644
--- a/arch/mips/configs/sb1250-swarm_defconfig
+++ b/arch/mips/configs/sb1250-swarm_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
@@ -961,7 +960,7 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 # CONFIG_SAMPLES is not set
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 # CONFIG_SB1XXX_CORELIS is not set
 
 #
diff --git a/arch/mips/configs/tb0219_defconfig b/arch/mips/configs/tb0219_defconfig
index b5059881bc7e..c54d1128f9a3 100644
--- a/arch/mips/configs/tb0219_defconfig
+++ b/arch/mips/configs/tb0219_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
@@ -892,7 +891,9 @@ CONFIG_FRAME_WARN=1024
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 # CONFIG_SAMPLES is not set
+CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="cca=3 mem=64M console=ttyVR0,115200 ip=any root=/dev/nfs"
+# CONFIG_CMDLINE_OVERRIDE is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig
index b06a716bf23f..e7c5cd32a2bd 100644
--- a/arch/mips/configs/tb0226_defconfig
+++ b/arch/mips/configs/tb0226_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
@@ -895,7 +894,9 @@ CONFIG_FRAME_WARN=1024
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 # CONFIG_SAMPLES is not set
+CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="cca=3 mem=32M console=ttyVR0,115200"
+# CONFIG_CMDLINE_OVERRIDE is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/tb0287_defconfig b/arch/mips/configs/tb0287_defconfig
index 46512cf7ce04..b50032ba4d01 100644
--- a/arch/mips/configs/tb0287_defconfig
+++ b/arch/mips/configs/tb0287_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
@@ -1077,7 +1076,9 @@ CONFIG_FRAME_WARN=1024
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 # CONFIG_SAMPLES is not set
+CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="cca=3 mem=64M console=ttyVR0,115200 ip=any root=/dev/nfs"
+# CONFIG_CMDLINE_OVERRIDE is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/workpad_defconfig b/arch/mips/configs/workpad_defconfig
index b437eb7f8672..c02ba08b69ab 100644
--- a/arch/mips/configs/workpad_defconfig
+++ b/arch/mips/configs/workpad_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
 # Machine selection
 #
 # CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -755,7 +754,9 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_CROSSCOMPILE=y
+CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="console=ttyVR0,19200 ide0=0x170,0x376,49 mem=16M"
+# CONFIG_CMDLINE_OVERRIDE is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/wrppmc_defconfig b/arch/mips/configs/wrppmc_defconfig
index 06acc7482e4c..a35bc41389e5 100644
--- a/arch/mips/configs/wrppmc_defconfig
+++ b/arch/mips/configs/wrppmc_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MIPS_DB1550 is not set
 # CONFIG_MIPS_DB1200 is not set
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -887,7 +886,9 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
+CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="console=ttyS0,115200n8"
+# CONFIG_CMDLINE_OVERRIDE is not set
 
 #
 # Security options
diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig
index 69feaf88b510..e3d68d651e7d 100644
--- a/arch/mips/configs/yosemite_defconfig
+++ b/arch/mips/configs/yosemite_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MIPS_DB1550 is not set
 # CONFIG_MIPS_DB1200 is not set
 # CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
@@ -824,7 +823,7 @@ CONFIG_DEBUG_MUTEXES=y
 CONFIG_FORCED_INLINING=y
 # CONFIG_RCU_TORTURE_TEST is not set
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
 # CONFIG_RUNTIME_DEBUG is not set
 
diff --git a/arch/mips/fw/arc/cmdline.c b/arch/mips/fw/arc/cmdline.c
index 4ca4eef934a5..5c8603c85f20 100644
--- a/arch/mips/fw/arc/cmdline.c
+++ b/arch/mips/fw/arc/cmdline.c
@@ -16,11 +16,6 @@
 
 #undef DEBUG_CMDLINE
 
-char * __init prom_getcmdline(void)
-{
-        return arcs_cmdline;
-}
-
 static char *ignored[] = {
         "ConsoleIn=",
         "ConsoleOut=",
diff --git a/arch/mips/include/asm/asm-offsets.h b/arch/mips/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/mips/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index f5dfaf6a1606..09eee09780f2 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -67,9 +67,9 @@
 #define MACH_LEMOTE_ML2F7      3
 #define MACH_LEMOTE_YL2F89     4
 #define MACH_DEXXON_GDIUM2F10  5
-#define MACH_LOONGSON_END      6
-
-#define CL_SIZE                 COMMAND_LINE_SIZE
+#define MACH_LEMOTE_NAS        6
+#define MACH_LEMOTE_LL2F       7
+#define MACH_LOONGSON_END      8
 
 extern char *system_type;
 const char *get_system_type(void);
@@ -107,7 +107,7 @@ extern void free_init_pages(const char *what,
 /*
  * Initial kernel command line, usually setup by prom_init()
  */
-extern char arcs_cmdline[CL_SIZE];
+extern char arcs_cmdline[COMMAND_LINE_SIZE];
 
 /*
  * Registers a0, a1, a3 and a4 as passed to the kernel entry by firmware
diff --git a/arch/mips/include/asm/clock.h b/arch/mips/include/asm/clock.h
new file mode 100644
index 000000000000..83894aa7932c
--- /dev/null
+++ b/arch/mips/include/asm/clock.h
@@ -0,0 +1,64 @@
+#ifndef __ASM_MIPS_CLOCK_H
+#define __ASM_MIPS_CLOCK_H
+
+#include <linux/kref.h>
+#include <linux/list.h>
+#include <linux/seq_file.h>
+#include <linux/clk.h>
+
+extern void (*cpu_wait) (void);
+
+struct clk;
+
+struct clk_ops {
+        void (*init) (struct clk *clk);
+        void (*enable) (struct clk *clk);
+        void (*disable) (struct clk *clk);
+        void (*recalc) (struct clk *clk);
+        int (*set_rate) (struct clk *clk, unsigned long rate, int algo_id);
+        long (*round_rate) (struct clk *clk, unsigned long rate);
+};
+
+struct clk {
+        struct list_head node;
+        const char *name;
+        int id;
+        struct module *owner;
+
+        struct clk *parent;
+        struct clk_ops *ops;
+
+        struct kref kref;
+
+        unsigned long rate;
+        unsigned long flags;
+};
+
+#define CLK_ALWAYS_ENABLED      (1 << 0)
+#define CLK_RATE_PROPAGATES     (1 << 1)
+
+/* Should be defined by processor-specific code */
+void arch_init_clk_ops(struct clk_ops **, int type);
+
+int clk_init(void);
+
+int __clk_enable(struct clk *);
+void __clk_disable(struct clk *);
+
+void clk_recalc_rate(struct clk *);
+
+int clk_register(struct clk *);
+void clk_unregister(struct clk *);
+
+/* the exported API, in addition to clk_set_rate */
+/**
+ * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter
+ * @clk: clock source
+ * @rate: desired clock rate in Hz
+ * @algo_id: algorithm id to be passed down to ops->set_rate
+ *
+ * Returns success (0) or negative errno.
+ */
+int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);
+
+#endif                          /* __ASM_MIPS_CLOCK_H */
diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h
new file mode 100644
index 000000000000..6b04c98b7fad
--- /dev/null
+++ b/arch/mips/include/asm/cop2.h
@@ -0,0 +1,23 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2009 Wind River Systems,
+ *   written by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_COP2_H
+#define __ASM_COP2_H
+
+enum cu2_ops {
+        CU2_EXCEPTION,
+        CU2_LWC2_OP,
+        CU2_LDC2_OP,
+        CU2_SWC2_OP,
+        CU2_SDC2_OP,
+};
+
+extern int register_cu2_notifier(struct notifier_block *nb);
+extern int cu2_notifier_call_chain(unsigned long val, void *v);
+
+#endif /* __ASM_COP2_H */
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 4b96d1a36056..cf373a95fe4a 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -154,6 +154,8 @@
 #define PRID_REV_VR4181A        0x0070  /* Same as VR4122 */
 #define PRID_REV_VR4130         0x0080
 #define PRID_REV_34K_V1_0_2     0x0022
+#define PRID_REV_LOONGSON2E     0x0002
+#define PRID_REV_LOONGSON2F     0x0003
 
 /*
  * Older processors used to encode processor version and revision in two
diff --git a/arch/mips/include/asm/fcntl.h b/arch/mips/include/asm/fcntl.h
index 7c6681aa2ab8..e482fe90fe88 100644
--- a/arch/mips/include/asm/fcntl.h
+++ b/arch/mips/include/asm/fcntl.h
@@ -19,7 +19,7 @@
 #define FASYNC          0x1000  /* fcntl, for BSD compatibility */
 #define O_LARGEFILE     0x2000  /* allow large file opens */
 /*
- * Before Linux 2.6.32 only O_DSYNC semantics were implemented, but using
+ * Before Linux 2.6.33 only O_DSYNC semantics were implemented, but using
  * the O_SYNC flag.  We continue to use the existing numerical value
  * for O_DSYNC semantics now, but using the correct symbolic name for it.
  * This new value is used to request true Posix O_SYNC semantics.  It is
diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h
index 8a3ef247659a..7fcef8ef3fab 100644
--- a/arch/mips/include/asm/fpu.h
+++ b/arch/mips/include/asm/fpu.h
@@ -28,15 +28,7 @@
 struct sigcontext;
 struct sigcontext32;
 
-extern asmlinkage int (*save_fp_context)(struct sigcontext __user *sc);
-extern asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc);
-
-extern asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc);
-extern asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc);
-
 extern void fpu_emulator_init_fpu(void);
-extern int fpu_emulator_save_context(struct sigcontext __user *sc);
-extern int fpu_emulator_restore_context(struct sigcontext __user *sc);
 extern void _init_fpu(void);
 extern void _save_fp(struct task_struct *);
 extern void _restore_fp(struct task_struct *);
diff --git a/arch/mips/include/asm/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h
index e5189572956c..aecada6f6117 100644
--- a/arch/mips/include/asm/fpu_emulator.h
+++ b/arch/mips/include/asm/fpu_emulator.h
@@ -25,17 +25,27 @@
 
 #include <asm/break.h>
 #include <asm/inst.h>
+#include <asm/local.h>
+
+#ifdef CONFIG_DEBUG_FS
 
 struct mips_fpu_emulator_stats {
-        unsigned int emulated;
-        unsigned int loads;
-        unsigned int stores;
-        unsigned int cp1ops;
-        unsigned int cp1xops;
-        unsigned int errors;
+        local_t emulated;
+        local_t loads;
+        local_t stores;
+        local_t cp1ops;
+        local_t cp1xops;
+        local_t errors;
 };
 
-extern struct mips_fpu_emulator_stats fpuemustats;
+DECLARE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
+
+#define MIPS_FPU_EMU_INC_STATS(M)                                       \
+        cpu_local_wrap(__local_inc(&__get_cpu_var(fpuemustats).M))
+
+#else
+#define MIPS_FPU_EMU_INC_STATS(M) do { } while (0)
+#endif /* CONFIG_DEBUG_FS */
 
 extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir,
         unsigned long cpc);
diff --git a/arch/mips/include/asm/ftrace.h b/arch/mips/include/asm/ftrace.h
index 40a8c178f10d..3986cd8704f3 100644
--- a/arch/mips/include/asm/ftrace.h
+++ b/arch/mips/include/asm/ftrace.h
@@ -1 +1,90 @@
-/* empty */
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive for
+ * more details.
+ *
+ * Copyright (C) 2009 DSLab, Lanzhou University, China
+ * Author: Wu Zhangjin <wuzj@lemote.com>
+ */
+
+#ifndef _ASM_MIPS_FTRACE_H
+#define _ASM_MIPS_FTRACE_H
+
+#ifdef CONFIG_FUNCTION_TRACER
+
+#define MCOUNT_ADDR ((unsigned long)(_mcount))
+#define MCOUNT_INSN_SIZE 4              /* sizeof mcount call */
+
+#ifndef __ASSEMBLY__
+extern void _mcount(void);
+#define mcount _mcount
+
+#define safe_load(load, src, dst, error)                \
+do {                                                    \
+        asm volatile (                                  \
+                "1: " load " %[" STR(dst) "], 0(%[" STR(src) "])\n"\
+                "   li %[" STR(error) "], 0\n"          \
+                "2:\n"                                  \
+                                                        \
+                ".section .fixup, \"ax\"\n"             \
+                "3: li %[" STR(error) "], 1\n"          \
+                "   j 2b\n"                             \
+                ".previous\n"                           \
+                                                        \
+                ".section\t__ex_table,\"a\"\n\t"        \
+                STR(PTR) "\t1b, 3b\n\t"                 \
+                ".previous\n"                           \
+                                                        \
+                : [dst] "=&r" (dst), [error] "=r" (error)\
+                : [src] "r" (src)                       \
+                : "memory"                              \
+        );                                              \
+} while (0)
+
+#define safe_store(store, src, dst, error)      \
+do {                                            \
+        asm volatile (                          \
+                "1: " store " %[" STR(src) "], 0(%[" STR(dst) "])\n"\
+                "   li %[" STR(error) "], 0\n"  \
+                "2:\n"                          \
+                                                \
+                ".section .fixup, \"ax\"\n"     \
+                "3: li %[" STR(error) "], 1\n"  \
+                "   j 2b\n"                     \
+                ".previous\n"                   \
+                                                \
+                ".section\t__ex_table,\"a\"\n\t"\
+                STR(PTR) "\t1b, 3b\n\t"         \
+                ".previous\n"                   \
+                                                \
+                : [error] "=r" (error)          \
+                : [dst] "r" (dst), [src] "r" (src)\
+                : "memory"                      \
+        );                                      \
+} while (0)
+
+#define safe_load_code(dst, src, error) \
+        safe_load(STR(lw), src, dst, error)
+#define safe_store_code(src, dst, error) \
+        safe_store(STR(sw), src, dst, error)
+
+#define safe_load_stack(dst, src, error) \
+        safe_load(STR(PTR_L), src, dst, error)
+
+#define safe_store_stack(src, dst, error) \
+        safe_store(STR(PTR_S), src, dst, error)
+
+
+#ifdef CONFIG_DYNAMIC_FTRACE
+static inline unsigned long ftrace_call_adjust(unsigned long addr)
+{
+        return addr;
+}
+
+struct dyn_arch_ftrace {
+};
+
+#endif /*  CONFIG_DYNAMIC_FTRACE */
+#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_FUNCTION_TRACER */
+#endif /* _ASM_MIPS_FTRACE_H */
diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h
index 09b08d05ff72..06960364c96b 100644
--- a/arch/mips/include/asm/irq.h
+++ b/arch/mips/include/asm/irq.h
@@ -113,36 +113,11 @@ do {									\
 
 #endif
 
-/*
- * do_IRQ handles all normal device IRQ's (the special
- * SMP cross-CPU interrupts have their own specific
- * handlers).
- *
- * Ideally there should be away to get this into kernel/irq/handle.c to
- * avoid the overhead of a call for just a tiny function ...
- */
-#define do_IRQ(irq)                                                     \
-do {                                                                    \
-        irq_enter();                                                    \
-        __DO_IRQ_SMTC_HOOK(irq);                                        \
-        generic_handle_irq(irq);                                        \
-        irq_exit();                                                     \
-} while (0)
+extern void do_IRQ(unsigned int irq);
 
 #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
-/*
- * To avoid inefficient and in some cases pathological re-checking of
- * IRQ affinity, we have this variant that skips the affinity check.
- */
-
 
-#define do_IRQ_no_affinity(irq)                                         \
-do {                                                                    \
-        irq_enter();                                                    \
-        __NO_AFFINITY_IRQ_SMTC_HOOK(irq);                               \
-        generic_handle_irq(irq);                                        \
-        irq_exit();                                                     \
-} while (0)
+extern void do_IRQ_no_affinity(unsigned int irq);
 
 #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
 
diff --git a/arch/mips/include/asm/mach-excite/cpu-feature-overrides.h b/arch/mips/include/asm/mach-excite/cpu-feature-overrides.h
deleted file mode 100644
index 107104c3cd12..000000000000
--- a/arch/mips/include/asm/mach-excite/cpu-feature-overrides.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2004 Thomas Koeller <thomas.koeller@baslerweb.com>
- * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
- */
-#ifndef __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
-#define __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
-
-/*
- * Basler eXcite has an RM9122 processor.
- */
-#define cpu_has_watch           1
-#define cpu_has_mips16          0
-#define cpu_has_divec           0
-#define cpu_has_vce             0
-#define cpu_has_cache_cdex_p    0
-#define cpu_has_cache_cdex_s    0
-#define cpu_has_prefetch        1
-#define cpu_has_mcheck          0
-#define cpu_has_ejtag           0
-
-#define cpu_has_llsc            1
-#define cpu_has_vtag_icache     0
-#define cpu_has_dc_aliases      0
-#define cpu_has_ic_fills_f_dc   0
-#define cpu_has_dsp             0
-#define cpu_icache_snoops_remote_store  0
-#define cpu_has_mipsmt          0
-#define cpu_has_userlocal       0
-
-#define cpu_has_nofpuex         0
-#define cpu_has_64bits          1
-
-#define cpu_has_mips32r1        0
-#define cpu_has_mips32r2        0
-#define cpu_has_mips64r1        0
-#define cpu_has_mips64r2        0
-
-#define cpu_has_inclusive_pcaches       0
-
-#define cpu_dcache_line_size()  32
-#define cpu_icache_line_size()  32
-#define cpu_scache_line_size()  32
-
-#endif /* __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-excite/excite.h b/arch/mips/include/asm/mach-excite/excite.h
deleted file mode 100644
index 4c29ba44992c..000000000000
--- a/arch/mips/include/asm/mach-excite/excite.h
+++ /dev/null
@@ -1,154 +0,0 @@
-#ifndef __EXCITE_H__
-#define __EXCITE_H__
-
-#include <linux/init.h>
-#include <asm/addrspace.h>
-#include <asm/types.h>
-
-#define EXCITE_CPU_EXT_CLOCK 100000000
-
-#if !defined(__ASSEMBLY__)
-void __init excite_kgdb_init(void);
-void excite_procfs_init(void);
-extern unsigned long memsize;
-extern char modetty[];
-extern u32 unit_id;
-#endif
-
-/* Base name for XICAP devices */
-#define XICAP_NAME      "xicap_gpi"
-
-/* OCD register offsets */
-#define LKB0            0x0038
-#define LKB5            0x0128
-#define LKM5            0x012C
-#define LKB7            0x0138
-#define LKM7            0x013c
-#define LKB8            0x0140
-#define LKM8            0x0144
-#define LKB9            0x0148
-#define LKM9            0x014c
-#define LKB10           0x0150
-#define LKM10           0x0154
-#define LKB11           0x0158
-#define LKM11           0x015c
-#define LKB12           0x0160
-#define LKM12           0x0164
-#define LKB13           0x0168
-#define LKM13           0x016c
-#define LDP0            0x0200
-#define LDP1            0x0210
-#define LDP2            0x0220
-#define LDP3            0x0230
-#define INTPIN0         0x0A40
-#define INTPIN1         0x0A44
-#define INTPIN2         0x0A48
-#define INTPIN3         0x0A4C
-#define INTPIN4         0x0A50
-#define INTPIN5         0x0A54
-#define INTPIN6         0x0A58
-#define INTPIN7         0x0A5C
-
-
-
-
-/* TITAN register offsets */
-#define CPRR            0x0004
-#define CPDSR           0x0008
-#define CPTC0R          0x000c
-#define CPTC1R          0x0010
-#define CPCFG0          0x0020
-#define CPCFG1          0x0024
-#define CPDST0A         0x0028
-#define CPDST0B         0x002c
-#define CPDST1A         0x0030
-#define CPDST1B         0x0034
-#define CPXDSTA         0x0038
-#define CPXDSTB         0x003c
-#define CPXCISRA        0x0048
-#define CPXCISRB        0x004c
-#define CPGIG0ER        0x0050
-#define CPGIG1ER        0x0054
-#define CPGRWL          0x0068
-#define CPURSLMT        0x00f8
-#define UACFG           0x0200
-#define UAINTS          0x0204
-#define SDRXFCIE        0x4828
-#define SDTXFCIE        0x4928
-#define INTP0Status0    0x1B00
-#define INTP0Mask0      0x1B04
-#define INTP0Set0       0x1B08
-#define INTP0Clear0     0x1B0C
-#define GXCFG           0x5000
-#define GXDMADRPFX      0x5018
-#define GXDMA_DESCADR   0x501c
-#define GXCH0TDESSTRT   0x5054
-
-/* IRQ definitions */
-#define NMICONFIG               0xac0
-#define TITAN_MSGINT    0xc4
-#define TITAN_IRQ       ((TITAN_MSGINT / 0x20) + 2)
-#define FPGA0_MSGINT    0x5a
-#define FPGA0_IRQ       ((FPGA0_MSGINT / 0x20) + 2)
-#define FPGA1_MSGINT    0x7b
-#define FPGA1_IRQ       ((FPGA1_MSGINT / 0x20) + 2)
-#define PHY_MSGINT      0x9c
-#define PHY_IRQ         ((PHY_MSGINT   / 0x20) + 2)
-
-#if defined(CONFIG_BASLER_EXCITE_PROTOTYPE)
-/* Pre-release units used interrupt pin #9 */
-#define USB_IRQ         11
-#else
-/* Re-designed units use interrupt pin #1 */
-#define USB_MSGINT      0x39
-#define USB_IRQ         ((USB_MSGINT / 0x20) + 2)
-#endif
-#define TIMER_IRQ       12
-
-
-/* Device address ranges */
-#define EXCITE_OFFS_OCD         0x1fffc000
-#define EXCITE_SIZE_OCD         (16 * 1024)
-#define EXCITE_PHYS_OCD         CPHYSADDR(EXCITE_OFFS_OCD)
-#define EXCITE_ADDR_OCD         CKSEG1ADDR(EXCITE_OFFS_OCD)
-
-#define EXCITE_OFFS_SCRAM       0x1fffa000
-#define EXCITE_SIZE_SCRAM       (8 << 10)
-#define EXCITE_PHYS_SCRAM       CPHYSADDR(EXCITE_OFFS_SCRAM)
-#define EXCITE_ADDR_SCRAM       CKSEG1ADDR(EXCITE_OFFS_SCRAM)
-
-#define EXCITE_OFFS_PCI_IO      0x1fff8000
-#define EXCITE_SIZE_PCI_IO      (8 << 10)
-#define EXCITE_PHYS_PCI_IO      CPHYSADDR(EXCITE_OFFS_PCI_IO)
-#define EXCITE_ADDR_PCI_IO      CKSEG1ADDR(EXCITE_OFFS_PCI_IO)
-
-#define EXCITE_OFFS_TITAN       0x1fff0000
-#define EXCITE_SIZE_TITAN       (32 << 10)
-#define EXCITE_PHYS_TITAN       CPHYSADDR(EXCITE_OFFS_TITAN)
-#define EXCITE_ADDR_TITAN       CKSEG1ADDR(EXCITE_OFFS_TITAN)
-
-#define EXCITE_OFFS_PCI_MEM     0x1ffe0000
-#define EXCITE_SIZE_PCI_MEM     (64 << 10)
-#define EXCITE_PHYS_PCI_MEM     CPHYSADDR(EXCITE_OFFS_PCI_MEM)
-#define EXCITE_ADDR_PCI_MEM     CKSEG1ADDR(EXCITE_OFFS_PCI_MEM)
-
-#define EXCITE_OFFS_FPGA        0x1ffdc000
-#define EXCITE_SIZE_FPGA        (16 << 10)
-#define EXCITE_PHYS_FPGA        CPHYSADDR(EXCITE_OFFS_FPGA)
-#define EXCITE_ADDR_FPGA        CKSEG1ADDR(EXCITE_OFFS_FPGA)
-
-#define EXCITE_OFFS_NAND        0x1ffd8000
-#define EXCITE_SIZE_NAND        (16 << 10)
-#define EXCITE_PHYS_NAND        CPHYSADDR(EXCITE_OFFS_NAND)
-#define EXCITE_ADDR_NAND        CKSEG1ADDR(EXCITE_OFFS_NAND)
-
-#define EXCITE_OFFS_BOOTROM     0x1f000000
-#define EXCITE_SIZE_BOOTROM     (8 << 20)
-#define EXCITE_PHYS_BOOTROM     CPHYSADDR(EXCITE_OFFS_BOOTROM)
-#define EXCITE_ADDR_BOOTROM     CKSEG1ADDR(EXCITE_OFFS_BOOTROM)
-
-/* FPGA address offsets */
-#define EXCITE_FPGA_DPR         0x0104  /* dual-ported ram */
-#define EXCITE_FPGA_SYSCTL      0x0200  /* system control register block */
-
-#endif /* __EXCITE_H__ */
diff --git a/arch/mips/include/asm/mach-excite/excite_fpga.h b/arch/mips/include/asm/mach-excite/excite_fpga.h
deleted file mode 100644
index 0a1ef69bece7..000000000000
--- a/arch/mips/include/asm/mach-excite/excite_fpga.h
+++ /dev/null
@@ -1,80 +0,0 @@
-#ifndef EXCITE_FPGA_H_INCLUDED
-#define EXCITE_FPGA_H_INCLUDED
-
-
-/**
- * Address alignment of the individual FPGA bytes.
- * The address arrangement of the individual bytes of the FPGA is two
- * byte aligned at the embedded MK2 platform.
- */
-#ifdef EXCITE_CCI_FPGA_MK2
-typedef unsigned char excite_cci_fpga_align_t __attribute__ ((aligned(2)));
-#else
-typedef unsigned char excite_cci_fpga_align_t;
-#endif
-
-
-/**
- * Size of Dual Ported RAM.
- */
-#define EXCITE_DPR_SIZE 263
-
-
-/**
- * Size of Reserved Status Fields in Dual Ported RAM.
- */
-#define EXCITE_DPR_STATUS_SIZE 7
-
-
-
-/**
- * FPGA.
- * Hardware register layout of the FPGA interface. The FPGA must accessed
- * byte wise solely.
- * @see EXCITE_CCI_DPR_MK2
- */
-typedef struct excite_fpga {
-
-        /**
-         * Dual Ported RAM.
-         */
-        excite_cci_fpga_align_t dpr[EXCITE_DPR_SIZE];
-
-        /**
-         * Status.
-         */
-        excite_cci_fpga_align_t status[EXCITE_DPR_STATUS_SIZE];
-
-#ifdef EXCITE_CCI_FPGA_MK2
-        /**
-         * RM9000 Interrupt.
-         * Write access initiates interrupt at the RM9000 (MIPS) processor of the eXcite.
-         */
-        excite_cci_fpga_align_t rm9k_int;
-#else
-        /**
-         * MK2 Interrupt.
-         * Write access initiates interrupt at the ARM processor of the MK2.
-         */
-        excite_cci_fpga_align_t mk2_int;
-
-        excite_cci_fpga_align_t gap[0x1000-0x10f];
-
-        /**
-         * IRQ Source/Acknowledge.
-         */
-        excite_cci_fpga_align_t rm9k_irq_src;
-
-        /**
-         * IRQ Mask.
-         * Set bits enable the related interrupt.
-         */
-        excite_cci_fpga_align_t rm9k_irq_mask;
-#endif
-
-
-} excite_fpga;
-
-
-
-#endif  /* ndef EXCITE_FPGA_H_INCLUDED */
diff --git a/arch/mips/include/asm/mach-excite/excite_nandflash.h b/arch/mips/include/asm/mach-excite/excite_nandflash.h
deleted file mode 100644
index c4cf6140622e..000000000000
--- a/arch/mips/include/asm/mach-excite/excite_nandflash.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __EXCITE_NANDFLASH_H__
-#define __EXCITE_NANDFLASH_H__
-
-/* Resource names */
-#define EXCITE_NANDFLASH_RESOURCE_REGS  "excite_nandflash_regs"
-
-#endif /* __EXCITE_NANDFLASH_H__ */
diff --git a/arch/mips/include/asm/mach-excite/rm9k_eth.h b/arch/mips/include/asm/mach-excite/rm9k_eth.h
deleted file mode 100644
index 94705a46f72e..000000000000
--- a/arch/mips/include/asm/mach-excite/rm9k_eth.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#if !defined(__RM9K_ETH_H__)
-#define __RM9K_ETH_H__
-
-#define RM9K_GE_NAME                    "rm9k_ge"
-
-/* Resource names */
-#define RM9K_GE_RESOURCE_MAC            "rm9k_ge_mac"
-#define RM9K_GE_RESOURCE_MSTAT          "rm9k_ge_mstat"
-#define RM9K_GE_RESOURCE_PKTPROC        "rm9k_ge_pktproc"
-#define RM9K_GE_RESOURCE_XDMA           "rm9k_ge_xdma"
-#define RM9K_GE_RESOURCE_FIFO_RX        "rm9k_ge_fifo_rx"
-#define RM9K_GE_RESOURCE_FIFO_TX        "rm9k_ge_fifo_tx"
-#define RM9K_GE_RESOURCE_FIFOMEM_RX     "rm9k_ge_fifo_memory_rx"
-#define RM9K_GE_RESOURCE_FIFOMEM_TX     "rm9k_ge_fifo_memory_tx"
-#define RM9K_GE_RESOURCE_PHY            "rm9k_ge_phy"
-#define RM9K_GE_RESOURCE_DMADESC_RX     "rm9k_ge_dmadesc_rx"
-#define RM9K_GE_RESOURCE_DMADESC_TX     "rm9k_ge_dmadesc_tx"
-#define RM9K_GE_RESOURCE_IRQ_MAIN       "rm9k_ge_irq_main"
-#define RM9K_GE_RESOURCE_IRQ_PHY        "rm9k_ge_irq_phy"
-#define RM9K_GE_RESOURCE_GPI_SLICE      "rm9k_ge_gpi_slice"
-#define RM9K_GE_RESOURCE_MDIO_CHANNEL   "rm9k_ge_mdio_channel"
-
-#endif /* !defined(__RM9K_ETH_H__) */
diff --git a/arch/mips/include/asm/mach-excite/rm9k_wdt.h b/arch/mips/include/asm/mach-excite/rm9k_wdt.h
deleted file mode 100644
index 3fa3c08d2da7..000000000000
--- a/arch/mips/include/asm/mach-excite/rm9k_wdt.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef __RM9K_WDT_H__
-#define __RM9K_WDT_H__
-
-/* Device name */
-#define WDT_NAME                "wdt_gpi"
-
-/* Resource names */
-#define WDT_RESOURCE_REGS       "excite_watchdog_regs"
-#define WDT_RESOURCE_IRQ        "excite_watchdog_irq"
-#define WDT_RESOURCE_COUNTER    "excite_watchdog_counter"
-
-#endif /* __RM9K_WDT_H__ */
diff --git a/arch/mips/include/asm/mach-excite/rm9k_xicap.h b/arch/mips/include/asm/mach-excite/rm9k_xicap.h
deleted file mode 100644
index 009577734a8d..000000000000
--- a/arch/mips/include/asm/mach-excite/rm9k_xicap.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef __EXCITE_XICAP_H__
-#define __EXCITE_XICAP_H__
-
-
-/* Resource names */
-#define XICAP_RESOURCE_FIFO_RX          "xicap_fifo_rx"
-#define XICAP_RESOURCE_FIFO_TX          "xicap_fifo_tx"
-#define XICAP_RESOURCE_XDMA             "xicap_xdma"
-#define XICAP_RESOURCE_DMADESC          "xicap_dmadesc"
-#define XICAP_RESOURCE_PKTPROC          "xicap_pktproc"
-#define XICAP_RESOURCE_IRQ              "xicap_irq"
-#define XICAP_RESOURCE_GPI_SLICE        "xicap_gpi_slice"
-#define XICAP_RESOURCE_FIFO_BLK         "xicap_fifo_blocks"
-#define XICAP_RESOURCE_PKT_STREAM       "xicap_pkt_stream"
-
-#endif /* __EXCITE_XICAP_H__ */
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h
new file mode 100644
index 000000000000..021f77ca59ec
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h
@@ -0,0 +1,305 @@
+/*
+ * The header file of cs5536 sourth bridge.
+ *
+ * Copyright (C) 2007 Lemote, Inc.
+ * Author : jlliu <liujl@lemote.com>
+ */
+
+#ifndef _CS5536_H
+#define _CS5536_H
+
+#include <linux/types.h>
+
+extern void _rdmsr(u32 msr, u32 *hi, u32 *lo);
+extern void _wrmsr(u32 msr, u32 hi, u32 lo);
+
+/*
+ * MSR module base
+ */
+#define CS5536_SB_MSR_BASE      (0x00000000)
+#define CS5536_GLIU_MSR_BASE    (0x10000000)
+#define CS5536_ILLEGAL_MSR_BASE (0x20000000)
+#define CS5536_USB_MSR_BASE     (0x40000000)
+#define CS5536_IDE_MSR_BASE     (0x60000000)
+#define CS5536_DIVIL_MSR_BASE   (0x80000000)
+#define CS5536_ACC_MSR_BASE     (0xa0000000)
+#define CS5536_UNUSED_MSR_BASE  (0xc0000000)
+#define CS5536_GLCP_MSR_BASE    (0xe0000000)
+
+#define SB_MSR_REG(offset)      (CS5536_SB_MSR_BASE     | (offset))
+#define GLIU_MSR_REG(offset)    (CS5536_GLIU_MSR_BASE   | (offset))
+#define ILLEGAL_MSR_REG(offset) (CS5536_ILLEGAL_MSR_BASE | (offset))
+#define USB_MSR_REG(offset)     (CS5536_USB_MSR_BASE    | (offset))
+#define IDE_MSR_REG(offset)     (CS5536_IDE_MSR_BASE    | (offset))
+#define DIVIL_MSR_REG(offset)   (CS5536_DIVIL_MSR_BASE  | (offset))
+#define ACC_MSR_REG(offset)     (CS5536_ACC_MSR_BASE    | (offset))
+#define UNUSED_MSR_REG(offset)  (CS5536_UNUSED_MSR_BASE | (offset))
+#define GLCP_MSR_REG(offset)    (CS5536_GLCP_MSR_BASE   | (offset))
+
+/*
+ * BAR SPACE OF VIRTUAL PCI :
+ * range for pci probe use, length is the actual size.
+ */
+/* IO space for all DIVIL modules */
+#define CS5536_IRQ_RANGE        0xffffffe0 /* USERD FOR PCI PROBE */
+#define CS5536_IRQ_LENGTH       0x20    /* THE REGS ACTUAL LENGTH */
+#define CS5536_SMB_RANGE        0xfffffff8
+#define CS5536_SMB_LENGTH       0x08
+#define CS5536_GPIO_RANGE       0xffffff00
+#define CS5536_GPIO_LENGTH      0x100
+#define CS5536_MFGPT_RANGE      0xffffffc0
+#define CS5536_MFGPT_LENGTH     0x40
+#define CS5536_ACPI_RANGE       0xffffffe0
+#define CS5536_ACPI_LENGTH      0x20
+#define CS5536_PMS_RANGE        0xffffff80
+#define CS5536_PMS_LENGTH       0x80
+/* IO space for IDE */
+#define CS5536_IDE_RANGE        0xfffffff0
+#define CS5536_IDE_LENGTH       0x10
+/* IO space for ACC */
+#define CS5536_ACC_RANGE        0xffffff80
+#define CS5536_ACC_LENGTH       0x80
+/* MEM space for ALL USB modules */
+#define CS5536_OHCI_RANGE       0xfffff000
+#define CS5536_OHCI_LENGTH      0x1000
+#define CS5536_EHCI_RANGE       0xfffff000
+#define CS5536_EHCI_LENGTH      0x1000
+
+/*
+ * PCI MSR ACCESS
+ */
+#define PCI_MSR_CTRL            0xF0
+#define PCI_MSR_ADDR            0xF4
+#define PCI_MSR_DATA_LO         0xF8
+#define PCI_MSR_DATA_HI         0xFC
+
+/**************** MSR *****************************/
+
+/*
+ * GLIU STANDARD MSR
+ */
+#define GLIU_CAP                0x00
+#define GLIU_CONFIG             0x01
+#define GLIU_SMI                0x02
+#define GLIU_ERROR              0x03
+#define GLIU_PM                 0x04
+#define GLIU_DIAG               0x05
+
+/*
+ * GLIU SPEC. MSR
+ */
+#define GLIU_P2D_BM0            0x20
+#define GLIU_P2D_BM1            0x21
+#define GLIU_P2D_BM2            0x22
+#define GLIU_P2D_BMK0           0x23
+#define GLIU_P2D_BMK1           0x24
+#define GLIU_P2D_BM3            0x25
+#define GLIU_P2D_BM4            0x26
+#define GLIU_COH                0x80
+#define GLIU_PAE                0x81
+#define GLIU_ARB                0x82
+#define GLIU_ASMI               0x83
+#define GLIU_AERR               0x84
+#define GLIU_DEBUG              0x85
+#define GLIU_PHY_CAP            0x86
+#define GLIU_NOUT_RESP          0x87
+#define GLIU_NOUT_WDATA         0x88
+#define GLIU_WHOAMI             0x8B
+#define GLIU_SLV_DIS            0x8C
+#define GLIU_IOD_BM0            0xE0
+#define GLIU_IOD_BM1            0xE1
+#define GLIU_IOD_BM2            0xE2
+#define GLIU_IOD_BM3            0xE3
+#define GLIU_IOD_BM4            0xE4
+#define GLIU_IOD_BM5            0xE5
+#define GLIU_IOD_BM6            0xE6
+#define GLIU_IOD_BM7            0xE7
+#define GLIU_IOD_BM8            0xE8
+#define GLIU_IOD_BM9            0xE9
+#define GLIU_IOD_SC0            0xEA
+#define GLIU_IOD_SC1            0xEB
+#define GLIU_IOD_SC2            0xEC
+#define GLIU_IOD_SC3            0xED
+#define GLIU_IOD_SC4            0xEE
+#define GLIU_IOD_SC5            0xEF
+#define GLIU_IOD_SC6            0xF0
+#define GLIU_IOD_SC7            0xF1
+
+/*
+ * SB STANDARD
+ */
+#define SB_CAP          0x00
+#define SB_CONFIG       0x01
+#define SB_SMI          0x02
+#define SB_ERROR        0x03
+#define SB_MAR_ERR_EN           0x00000001
+#define SB_TAR_ERR_EN           0x00000002
+#define SB_RSVD_BIT1            0x00000004
+#define SB_EXCEP_ERR_EN         0x00000008
+#define SB_SYSE_ERR_EN          0x00000010
+#define SB_PARE_ERR_EN          0x00000020
+#define SB_TAS_ERR_EN           0x00000040
+#define SB_MAR_ERR_FLAG         0x00010000
+#define SB_TAR_ERR_FLAG         0x00020000
+#define SB_RSVD_BIT2            0x00040000
+#define SB_EXCEP_ERR_FLAG       0x00080000
+#define SB_SYSE_ERR_FLAG        0x00100000
+#define SB_PARE_ERR_FLAG        0x00200000
+#define SB_TAS_ERR_FLAG         0x00400000
+#define SB_PM           0x04
+#define SB_DIAG         0x05
+
+/*
+ * SB SPEC.
+ */
+#define SB_CTRL         0x10
+#define SB_R0           0x20
+#define SB_R1           0x21
+#define SB_R2           0x22
+#define SB_R3           0x23
+#define SB_R4           0x24
+#define SB_R5           0x25
+#define SB_R6           0x26
+#define SB_R7           0x27
+#define SB_R8           0x28
+#define SB_R9           0x29
+#define SB_R10          0x2A
+#define SB_R11          0x2B
+#define SB_R12          0x2C
+#define SB_R13          0x2D
+#define SB_R14          0x2E
+#define SB_R15          0x2F
+
+/*
+ * GLCP STANDARD
+ */
+#define GLCP_CAP                0x00
+#define GLCP_CONFIG             0x01
+#define GLCP_SMI                0x02
+#define GLCP_ERROR              0x03
+#define GLCP_PM                 0x04
+#define GLCP_DIAG               0x05
+
+/*
+ * GLCP SPEC.
+ */
+#define GLCP_CLK_DIS_DELAY      0x08
+#define GLCP_PM_CLK_DISABLE     0x09
+#define GLCP_GLB_PM             0x0B
+#define GLCP_DBG_OUT            0x0C
+#define GLCP_RSVD1              0x0D
+#define GLCP_SOFT_COM           0x0E
+#define SOFT_BAR_SMB_FLAG       0x00000001
+#define SOFT_BAR_GPIO_FLAG      0x00000002
+#define SOFT_BAR_MFGPT_FLAG     0x00000004
+#define SOFT_BAR_IRQ_FLAG       0x00000008
+#define SOFT_BAR_PMS_FLAG       0x00000010
+#define SOFT_BAR_ACPI_FLAG      0x00000020
+#define SOFT_BAR_IDE_FLAG       0x00000400
+#define SOFT_BAR_ACC_FLAG       0x00000800
+#define SOFT_BAR_OHCI_FLAG      0x00001000
+#define SOFT_BAR_EHCI_FLAG      0x00002000
+#define GLCP_RSVD2              0x0F
+#define GLCP_CLK_OFF            0x10
+#define GLCP_CLK_ACTIVE         0x11
+#define GLCP_CLK_DISABLE        0x12
+#define GLCP_CLK4ACK            0x13
+#define GLCP_SYS_RST            0x14
+#define GLCP_RSVD3              0x15
+#define GLCP_DBG_CLK_CTRL       0x16
+#define GLCP_CHIP_REV_ID        0x17
+
+/* PIC */
+#define PIC_YSEL_LOW            0x20
+#define PIC_YSEL_LOW_USB_SHIFT          8
+#define PIC_YSEL_LOW_ACC_SHIFT          16
+#define PIC_YSEL_LOW_FLASH_SHIFT        24
+#define PIC_YSEL_HIGH           0x21
+#define PIC_ZSEL_LOW            0x22
+#define PIC_ZSEL_HIGH           0x23
+#define PIC_IRQM_PRIM           0x24
+#define PIC_IRQM_LPC            0x25
+#define PIC_XIRR_STS_LOW        0x26
+#define PIC_XIRR_STS_HIGH       0x27
+#define PCI_SHDW                0x34
+
+/*
+ * DIVIL STANDARD
+ */
+#define DIVIL_CAP               0x00
+#define DIVIL_CONFIG            0x01
+#define DIVIL_SMI               0x02
+#define DIVIL_ERROR             0x03
+#define DIVIL_PM                0x04
+#define DIVIL_DIAG              0x05
+
+/*
+ * DIVIL SPEC.
+ */
+#define DIVIL_LBAR_IRQ          0x08
+#define DIVIL_LBAR_KEL          0x09
+#define DIVIL_LBAR_SMB          0x0B
+#define DIVIL_LBAR_GPIO         0x0C
+#define DIVIL_LBAR_MFGPT        0x0D
+#define DIVIL_LBAR_ACPI         0x0E
+#define DIVIL_LBAR_PMS          0x0F
+#define DIVIL_LEG_IO            0x14
+#define DIVIL_BALL_OPTS         0x15
+#define DIVIL_SOFT_IRQ          0x16
+#define DIVIL_SOFT_RESET        0x17
+
+/* MFGPT */
+#define MFGPT_IRQ       0x28
+
+/*
+ * IDE STANDARD
+ */
+#define IDE_CAP         0x00
+#define IDE_CONFIG      0x01
+#define IDE_SMI         0x02
+#define IDE_ERROR       0x03
+#define IDE_PM          0x04
+#define IDE_DIAG        0x05
+
+/*
+ * IDE SPEC.
+ */
+#define IDE_IO_BAR      0x08
+#define IDE_CFG         0x10
+#define IDE_DTC         0x12
+#define IDE_CAST        0x13
+#define IDE_ETC         0x14
+#define IDE_INTERNAL_PM 0x15
+
+/*
+ * ACC STANDARD
+ */
+#define ACC_CAP         0x00
+#define ACC_CONFIG      0x01
+#define ACC_SMI         0x02
+#define ACC_ERROR       0x03
+#define ACC_PM          0x04
+#define ACC_DIAG        0x05
+
+/*
+ * USB STANDARD
+ */
+#define USB_CAP         0x00
+#define USB_CONFIG      0x01
+#define USB_SMI         0x02
+#define USB_ERROR       0x03
+#define USB_PM          0x04
+#define USB_DIAG        0x05
+
+/*
+ * USB SPEC.
+ */
+#define USB_OHCI        0x08
+#define USB_EHCI        0x09
+
+/****************** NATIVE ***************************/
+/* GPIO : I/O SPACE; REG : 32BITS */
+#define GPIOL_OUT_VAL           0x00
+#define GPIOL_OUT_EN            0x04
+
+#endif                          /* _CS5536_H */
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h
new file mode 100644
index 000000000000..4b493d6772c2
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h
@@ -0,0 +1,35 @@
+/*
+ * cs5536 mfgpt header file
+ */
+
+#ifndef _CS5536_MFGPT_H
+#define _CS5536_MFGPT_H
+
+#include <cs5536/cs5536.h>
+#include <cs5536/cs5536_pci.h>
+
+#ifdef CONFIG_CS5536_MFGPT
+extern void setup_mfgpt0_timer(void);
+extern void disable_mfgpt0_counter(void);
+extern void enable_mfgpt0_counter(void);
+#else
+static inline void __maybe_unused setup_mfgpt0_timer(void)
+{
+}
+static inline void __maybe_unused disable_mfgpt0_counter(void)
+{
+}
+static inline void __maybe_unused enable_mfgpt0_counter(void)
+{
+}
+#endif
+
+#define MFGPT_TICK_RATE 14318000
+#define COMPARE  ((MFGPT_TICK_RATE + HZ/2) / HZ)
+
+#define MFGPT_BASE      mfgpt_base
+#define MFGPT0_CMP2     (MFGPT_BASE + 2)
+#define MFGPT0_CNT      (MFGPT_BASE + 4)
+#define MFGPT0_SETUP    (MFGPT_BASE + 6)
+
+#endif /*!_CS5536_MFGPT_H */
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h
new file mode 100644
index 000000000000..0dca9c89ee7c
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h
@@ -0,0 +1,153 @@
+/*
+ * the definition file of cs5536 Virtual Support Module(VSM).
+ * pci configuration space can be accessed through the VSM, so
+ * there is no need of the MSR read/write now, except the spec.
+ * MSR registers which are not implemented yet.
+ *
+ * Copyright (C) 2007 Lemote Inc.
+ * Author : jlliu, liujl@lemote.com
+ */
+
+#ifndef _CS5536_PCI_H
+#define _CS5536_PCI_H
+
+#include <linux/types.h>
+#include <linux/pci_regs.h>
+
+extern void cs5536_pci_conf_write4(int function, int reg, u32 value);
+extern u32 cs5536_pci_conf_read4(int function, int reg);
+
+#define CS5536_ACC_INTR         9
+#define CS5536_IDE_INTR         14
+#define CS5536_USB_INTR         11
+#define CS5536_MFGPT_INTR       5
+#define CS5536_UART1_INTR       4
+#define CS5536_UART2_INTR       3
+
+/************** PCI BUS DEVICE FUNCTION ***************/
+
+/*
+ * PCI bus device function
+ */
+#define PCI_BUS_CS5536          0
+#define PCI_IDSEL_CS5536        14
+
+/********** STANDARD PCI-2.2 EXPANSION ****************/
+
+/*
+ * PCI configuration space
+ * we have to virtualize the PCI configure space head, so we should
+ * define the necessary IDs and some others.
+ */
+
+/* CONFIG of PCI VENDOR ID*/
+#define CFG_PCI_VENDOR_ID(mod_dev_id, sys_vendor_id) \
+        (((mod_dev_id) << 16) | (sys_vendor_id))
+
+/* VENDOR ID */
+#define CS5536_VENDOR_ID        0x1022
+
+/* DEVICE ID */
+#define CS5536_ISA_DEVICE_ID            0x2090
+#define CS5536_IDE_DEVICE_ID            0x209a
+#define CS5536_ACC_DEVICE_ID            0x2093
+#define CS5536_OHCI_DEVICE_ID           0x2094
+#define CS5536_EHCI_DEVICE_ID           0x2095
+
+/* CLASS CODE : CLASS SUB-CLASS INTERFACE */
+#define CS5536_ISA_CLASS_CODE           0x060100
+#define CS5536_IDE_CLASS_CODE           0x010180
+#define CS5536_ACC_CLASS_CODE           0x040100
+#define CS5536_OHCI_CLASS_CODE          0x0C0310
+#define CS5536_EHCI_CLASS_CODE          0x0C0320
+
+/* BHLC : BIST HEADER-TYPE LATENCY-TIMER CACHE-LINE-SIZE */
+
+#define CFG_PCI_CACHE_LINE_SIZE(header_type, latency_timer)     \
+        ((PCI_NONE_BIST << 24) | ((header_type) << 16) \
+                | ((latency_timer) << 8) | PCI_NORMAL_CACHE_LINE_SIZE);
+
+#define PCI_NONE_BIST                   0x00    /* RO not implemented yet. */
+#define PCI_BRIDGE_HEADER_TYPE          0x80    /* RO */
+#define PCI_NORMAL_HEADER_TYPE          0x00
+#define PCI_NORMAL_LATENCY_TIMER        0x00
+#define PCI_NORMAL_CACHE_LINE_SIZE      0x08    /* RW */
+
+/* BAR */
+#define PCI_BAR0_REG                    0x10
+#define PCI_BAR1_REG                    0x14
+#define PCI_BAR2_REG                    0x18
+#define PCI_BAR3_REG                    0x1c
+#define PCI_BAR4_REG                    0x20
+#define PCI_BAR5_REG                    0x24
+#define PCI_BAR_COUNT                   6
+#define PCI_BAR_RANGE_MASK              0xFFFFFFFF
+
+/* CARDBUS CIS POINTER */
+#define PCI_CARDBUS_CIS_POINTER         0x00000000
+
+/* SUBSYSTEM VENDOR ID  */
+#define CS5536_SUB_VENDOR_ID            CS5536_VENDOR_ID
+
+/* SUBSYSTEM ID */
+#define CS5536_ISA_SUB_ID               CS5536_ISA_DEVICE_ID
+#define CS5536_IDE_SUB_ID               CS5536_IDE_DEVICE_ID
+#define CS5536_ACC_SUB_ID               CS5536_ACC_DEVICE_ID
+#define CS5536_OHCI_SUB_ID              CS5536_OHCI_DEVICE_ID
+#define CS5536_EHCI_SUB_ID              CS5536_EHCI_DEVICE_ID
+
+/* EXPANSION ROM BAR */
+#define PCI_EXPANSION_ROM_BAR           0x00000000
+
+/* CAPABILITIES POINTER */
+#define PCI_CAPLIST_POINTER             0x00000000
+#define PCI_CAPLIST_USB_POINTER         0x40
+/* INTERRUPT */
+
+#define CFG_PCI_INTERRUPT_LINE(pin, mod_intr) \
+        ((PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | \
+                ((pin) << 8) | (mod_intr))
+
+#define PCI_MAX_LATENCY                 0x40
+#define PCI_MIN_GRANT                   0x00
+#define PCI_DEFAULT_PIN                 0x01
+
+/*********** EXPANSION PCI REG ************************/
+
+/*
+ * ISA EXPANSION
+ */
+#define PCI_UART1_INT_REG       0x50
+#define PCI_UART2_INT_REG       0x54
+#define PCI_ISA_FIXUP_REG       0x58
+
+/*
+ * IDE EXPANSION
+ */
+#define PCI_IDE_CFG_REG         0x40
+#define CS5536_IDE_FLASH_SIGNATURE      0xDEADBEEF
+#define PCI_IDE_DTC_REG         0x48
+#define PCI_IDE_CAST_REG        0x4C
+#define PCI_IDE_ETC_REG         0x50
+#define PCI_IDE_PM_REG          0x54
+#define PCI_IDE_INT_REG         0x60
+
+/*
+ * ACC EXPANSION
+ */
+#define PCI_ACC_INT_REG         0x50
+
+/*
+ * OHCI EXPANSION : INTTERUPT IS IMPLEMENTED BY THE OHCI
+ */
+#define PCI_OHCI_PM_REG         0x40
+#define PCI_OHCI_INT_REG        0x50
+
+/*
+ * EHCI EXPANSION
+ */
+#define PCI_EHCI_LEGSMIEN_REG   0x50
+#define PCI_EHCI_LEGSMISTS_REG  0x54
+#define PCI_EHCI_FLADJ_REG      0x60
+
+#endif                          /* _CS5536_PCI_H_ */
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h
new file mode 100644
index 000000000000..6305bea7e18e
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h
@@ -0,0 +1,31 @@
+/*
+ * the read/write interfaces for Virtual Support Module(VSM)
+ *
+ * Copyright (C) 2009 Lemote, Inc.
+ * Author: Wu Zhangjin <wuzj@lemote.com>
+ */
+
+#ifndef _CS5536_VSM_H
+#define _CS5536_VSM_H
+
+#include <linux/types.h>
+
+typedef void (*cs5536_pci_vsm_write)(int reg, u32 value);
+typedef u32 (*cs5536_pci_vsm_read)(int reg);
+
+#define DECLARE_CS5536_MODULE(name) \
+extern void pci_##name##_write_reg(int reg, u32 value); \
+extern u32 pci_##name##_read_reg(int reg);
+
+/* ide module */
+DECLARE_CS5536_MODULE(ide)
+/* acc module */
+DECLARE_CS5536_MODULE(acc)
+/* ohci module */
+DECLARE_CS5536_MODULE(ohci)
+/* isa module */
+DECLARE_CS5536_MODULE(isa)
+/* ehci module */
+DECLARE_CS5536_MODULE(ehci)
+
+#endif                          /* _CS5536_VSM_H */
diff --git a/arch/mips/include/asm/mach-loongson/dma-coherence.h b/arch/mips/include/asm/mach-loongson/dma-coherence.h
index 71a6851ba833..981c75f91a7d 100644
--- a/arch/mips/include/asm/mach-loongson/dma-coherence.h
+++ b/arch/mips/include/asm/mach-loongson/dma-coherence.h
@@ -28,7 +28,11 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
 static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
         dma_addr_t dma_addr)
 {
+#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT)
+        return (dma_addr > 0x8fffffff) ? dma_addr : (dma_addr & 0x0fffffff);
+#else
         return dma_addr & 0x7fffffff;
+#endif
 }
 
 static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h
index da70bcf2304e..ee8bc8376972 100644
--- a/arch/mips/include/asm/mach-loongson/loongson.h
+++ b/arch/mips/include/asm/mach-loongson/loongson.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology
+ * Copyright (C) 2009 Lemote, Inc.
  * Author: Wu Zhangjin <wuzj@lemote.com>
  *
  * This program is free software; you can redistribute  it and/or modify it
@@ -15,9 +15,6 @@
 #include <linux/io.h>
 #include <linux/init.h>
 
-/* there is an internal bonito64-compatiable northbridge in loongson2e/2f */
-#include <asm/mips-boards/bonito64.h>
-
 /* loongson internal northbridge initialization */
 extern void bonito_irq_init(void);
 
@@ -32,7 +29,19 @@ extern unsigned long memsize, highmemsize;
 /* loongson-specific command line, env and memory initialization */
 extern void __init prom_init_memory(void);
 extern void __init prom_init_cmdline(void);
+extern void __init prom_init_machtype(void);
 extern void __init prom_init_env(void);
+#ifdef CONFIG_LOONGSON_UART_BASE
+extern unsigned long _loongson_uart_base, loongson_uart_base;
+extern void prom_init_loongson_uart_base(void);
+#endif
+
+static inline void prom_init_uart_base(void)
+{
+#ifdef CONFIG_LOONGSON_UART_BASE
+        prom_init_loongson_uart_base();
+#endif
+}
 
 /* irq operation functions */
 extern void bonito_irqdispatch(void);
@@ -40,25 +49,276 @@ extern void __init bonito_irq_init(void);
 extern void __init set_irq_trigger_mode(void);
 extern void __init mach_init_irq(void);
 extern void mach_irq_dispatch(unsigned int pending);
+extern int mach_i8259_irq(void);
+
+/* We need this in some places... */
+#define delay() ({              \
+        int x;                          \
+        for (x = 0; x < 100000; x++)    \
+                __asm__ __volatile__(""); \
+})
+
+#define LOONGSON_REG(x) \
+        (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
+
+#define LOONGSON_IRQ_BASE       32
+#define LOONGSON2_PERFCNT_IRQ   (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
+
+#define LOONGSON_FLASH_BASE     0x1c000000
+#define LOONGSON_FLASH_SIZE     0x02000000      /* 32M */
+#define LOONGSON_FLASH_TOP      (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)
+
+#define LOONGSON_LIO0_BASE      0x1e000000
+#define LOONGSON_LIO0_SIZE      0x01C00000      /* 28M */
+#define LOONGSON_LIO0_TOP       (LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1)
+
+#define LOONGSON_BOOT_BASE      0x1fc00000
+#define LOONGSON_BOOT_SIZE      0x00100000      /* 1M */
+#define LOONGSON_BOOT_TOP       (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
+#define LOONGSON_REG_BASE       0x1fe00000
+#define LOONGSON_REG_SIZE       0x00100000      /* 256Bytes + 256Bytes + ??? */
+#define LOONGSON_REG_TOP        (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
+
+#define LOONGSON_LIO1_BASE      0x1ff00000
+#define LOONGSON_LIO1_SIZE      0x00100000      /* 1M */
+#define LOONGSON_LIO1_TOP       (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1)
+
+#define LOONGSON_PCILO0_BASE    0x10000000
+#define LOONGSON_PCILO1_BASE    0x14000000
+#define LOONGSON_PCILO2_BASE    0x18000000
+#define LOONGSON_PCILO_BASE     LOONGSON_PCILO0_BASE
+#define LOONGSON_PCILO_SIZE     0x0c000000      /* 64M * 3 */
+#define LOONGSON_PCILO_TOP      (LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1)
+
+#define LOONGSON_PCICFG_BASE    0x1fe80000
+#define LOONGSON_PCICFG_SIZE    0x00000800      /* 2K */
+#define LOONGSON_PCICFG_TOP     (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
+#define LOONGSON_PCIIO_BASE     0x1fd00000
+#define LOONGSON_PCIIO_SIZE     0x00100000      /* 1M */
+#define LOONGSON_PCIIO_TOP      (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1)
+
+/* Loongson Register Bases */
+
+#define LOONGSON_PCICONFIGBASE  0x00
+#define LOONGSON_REGBASE        0x100
 
 /* PCI Configuration Registers */
-#define LOONGSON_PCI_ISR4C  BONITO_PCI_REG(0x4c)
+
+#define LOONGSON_PCI_REG(x)     LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x))
+#define LOONGSON_PCIDID         LOONGSON_PCI_REG(0x00)
+#define LOONGSON_PCICMD         LOONGSON_PCI_REG(0x04)
+#define LOONGSON_PCICLASS       LOONGSON_PCI_REG(0x08)
+#define LOONGSON_PCILTIMER      LOONGSON_PCI_REG(0x0c)
+#define LOONGSON_PCIBASE0       LOONGSON_PCI_REG(0x10)
+#define LOONGSON_PCIBASE1       LOONGSON_PCI_REG(0x14)
+#define LOONGSON_PCIBASE2       LOONGSON_PCI_REG(0x18)
+#define LOONGSON_PCIBASE3       LOONGSON_PCI_REG(0x1c)
+#define LOONGSON_PCIBASE4       LOONGSON_PCI_REG(0x20)
+#define LOONGSON_PCIEXPRBASE    LOONGSON_PCI_REG(0x30)
+#define LOONGSON_PCIINT         LOONGSON_PCI_REG(0x3c)
+
+#define LOONGSON_PCI_ISR4C      LOONGSON_PCI_REG(0x4c)
+
+#define LOONGSON_PCICMD_PERR_CLR        0x80000000
+#define LOONGSON_PCICMD_SERR_CLR        0x40000000
+#define LOONGSON_PCICMD_MABORT_CLR      0x20000000
+#define LOONGSON_PCICMD_MTABORT_CLR     0x10000000
+#define LOONGSON_PCICMD_TABORT_CLR      0x08000000
+#define LOONGSON_PCICMD_MPERR_CLR       0x01000000
+#define LOONGSON_PCICMD_PERRRESPEN      0x00000040
+#define LOONGSON_PCICMD_ASTEPEN         0x00000080
+#define LOONGSON_PCICMD_SERREN          0x00000100
+#define LOONGSON_PCILTIMER_BUSLATENCY   0x0000ff00
+#define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT     8
+
+/* Loongson h/w Configuration */
+
+#define LOONGSON_GENCFG_OFFSET          0x4
+#define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET)
+
+#define LOONGSON_GENCFG_DEBUGMODE       0x00000001
+#define LOONGSON_GENCFG_SNOOPEN         0x00000002
+#define LOONGSON_GENCFG_CPUSELFRESET    0x00000004
+
+#define LOONGSON_GENCFG_FORCE_IRQA      0x00000008
+#define LOONGSON_GENCFG_IRQA_ISOUT      0x00000010
+#define LOONGSON_GENCFG_IRQA_FROM_INT1  0x00000020
+#define LOONGSON_GENCFG_BYTESWAP        0x00000040
+
+#define LOONGSON_GENCFG_UNCACHED        0x00000080
+#define LOONGSON_GENCFG_PREFETCHEN      0x00000100
+#define LOONGSON_GENCFG_WBEHINDEN       0x00000200
+#define LOONGSON_GENCFG_CACHEALG        0x00000c00
+#define LOONGSON_GENCFG_CACHEALG_SHIFT  10
+#define LOONGSON_GENCFG_PCIQUEUE        0x00001000
+#define LOONGSON_GENCFG_CACHESTOP       0x00002000
+#define LOONGSON_GENCFG_MSTRBYTESWAP    0x00004000
+#define LOONGSON_GENCFG_BUSERREN        0x00008000
+#define LOONGSON_GENCFG_NORETRYTIMEOUT  0x00010000
+#define LOONGSON_GENCFG_SHORTCOPYTIMEOUT        0x00020000
+
+/* PCI address map control */
+
+#define LOONGSON_PCIMAP                 LOONGSON_REG(LOONGSON_REGBASE + 0x10)
+#define LOONGSON_PCIMEMBASECFG          LOONGSON_REG(LOONGSON_REGBASE + 0x14)
+#define LOONGSON_PCIMAP_CFG             LOONGSON_REG(LOONGSON_REGBASE + 0x18)
+
+/* GPIO Regs - r/w */
+
+#define LOONGSON_GPIODATA               LOONGSON_REG(LOONGSON_REGBASE + 0x1c)
+#define LOONGSON_GPIOIE                 LOONGSON_REG(LOONGSON_REGBASE + 0x20)
+
+/* ICU Configuration Regs - r/w */
+
+#define LOONGSON_INTEDGE                LOONGSON_REG(LOONGSON_REGBASE + 0x24)
+#define LOONGSON_INTSTEER               LOONGSON_REG(LOONGSON_REGBASE + 0x28)
+#define LOONGSON_INTPOL                 LOONGSON_REG(LOONGSON_REGBASE + 0x2c)
+
+/* ICU Enable Regs - IntEn & IntISR are r/o. */
+
+#define LOONGSON_INTENSET               LOONGSON_REG(LOONGSON_REGBASE + 0x30)
+#define LOONGSON_INTENCLR               LOONGSON_REG(LOONGSON_REGBASE + 0x34)
+#define LOONGSON_INTEN                  LOONGSON_REG(LOONGSON_REGBASE + 0x38)
+#define LOONGSON_INTISR                 LOONGSON_REG(LOONGSON_REGBASE + 0x3c)
+
+/* ICU */
+#define LOONGSON_ICU_MBOXES             0x0000000f
+#define LOONGSON_ICU_MBOXES_SHIFT       0
+#define LOONGSON_ICU_DMARDY             0x00000010
+#define LOONGSON_ICU_DMAEMPTY           0x00000020
+#define LOONGSON_ICU_COPYRDY            0x00000040
+#define LOONGSON_ICU_COPYEMPTY          0x00000080
+#define LOONGSON_ICU_COPYERR            0x00000100
+#define LOONGSON_ICU_PCIIRQ             0x00000200
+#define LOONGSON_ICU_MASTERERR          0x00000400
+#define LOONGSON_ICU_SYSTEMERR          0x00000800
+#define LOONGSON_ICU_DRAMPERR           0x00001000
+#define LOONGSON_ICU_RETRYERR           0x00002000
+#define LOONGSON_ICU_GPIOS              0x01ff0000
+#define LOONGSON_ICU_GPIOS_SHIFT                16
+#define LOONGSON_ICU_GPINS              0x7e000000
+#define LOONGSON_ICU_GPINS_SHIFT                25
+#define LOONGSON_ICU_MBOX(N)            (1<<(LOONGSON_ICU_MBOXES_SHIFT+(N)))
+#define LOONGSON_ICU_GPIO(N)            (1<<(LOONGSON_ICU_GPIOS_SHIFT+(N)))
+#define LOONGSON_ICU_GPIN(N)            (1<<(LOONGSON_ICU_GPINS_SHIFT+(N)))
+
+/* PCI prefetch window base & mask */
+
+#define LOONGSON_MEM_WIN_BASE_L         LOONGSON_REG(LOONGSON_REGBASE + 0x40)
+#define LOONGSON_MEM_WIN_BASE_H         LOONGSON_REG(LOONGSON_REGBASE + 0x44)
+#define LOONGSON_MEM_WIN_MASK_L         LOONGSON_REG(LOONGSON_REGBASE + 0x48)
+#define LOONGSON_MEM_WIN_MASK_H         LOONGSON_REG(LOONGSON_REGBASE + 0x4c)
 
 /* PCI_Hit*_Sel_* */
 
-#define LOONGSON_PCI_HIT0_SEL_L     BONITO(BONITO_REGBASE + 0x50)
-#define LOONGSON_PCI_HIT0_SEL_H     BONITO(BONITO_REGBASE + 0x54)
-#define LOONGSON_PCI_HIT1_SEL_L     BONITO(BONITO_REGBASE + 0x58)
-#define LOONGSON_PCI_HIT1_SEL_H     BONITO(BONITO_REGBASE + 0x5c)
-#define LOONGSON_PCI_HIT2_SEL_L     BONITO(BONITO_REGBASE + 0x60)
-#define LOONGSON_PCI_HIT2_SEL_H     BONITO(BONITO_REGBASE + 0x64)
+#define LOONGSON_PCI_HIT0_SEL_L         LOONGSON_REG(LOONGSON_REGBASE + 0x50)
+#define LOONGSON_PCI_HIT0_SEL_H         LOONGSON_REG(LOONGSON_REGBASE + 0x54)
+#define LOONGSON_PCI_HIT1_SEL_L         LOONGSON_REG(LOONGSON_REGBASE + 0x58)
+#define LOONGSON_PCI_HIT1_SEL_H         LOONGSON_REG(LOONGSON_REGBASE + 0x5c)
+#define LOONGSON_PCI_HIT2_SEL_L         LOONGSON_REG(LOONGSON_REGBASE + 0x60)
+#define LOONGSON_PCI_HIT2_SEL_H         LOONGSON_REG(LOONGSON_REGBASE + 0x64)
 
 /* PXArb Config & Status */
 
-#define LOONGSON_PXARB_CFG      BONITO(BONITO_REGBASE + 0x68)
-#define LOONGSON_PXARB_STATUS       BONITO(BONITO_REGBASE + 0x6c)
+#define LOONGSON_PXARB_CFG              LOONGSON_REG(LOONGSON_REGBASE + 0x68)
+#define LOONGSON_PXARB_STATUS           LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
+
+/* pcimap */
+
+#define LOONGSON_PCIMAP_PCIMAP_LO0      0x0000003f
+#define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT        0
+#define LOONGSON_PCIMAP_PCIMAP_LO1      0x00000fc0
+#define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT        6
+#define LOONGSON_PCIMAP_PCIMAP_LO2      0x0003f000
+#define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT        12
+#define LOONGSON_PCIMAP_PCIMAP_2        0x00040000
+#define LOONGSON_PCIMAP_WIN(WIN, ADDR)  \
+        ((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
+
+#ifdef CONFIG_CPU_SUPPORTS_CPUFREQ
+#include <linux/cpufreq.h>
+extern void loongson2_cpu_wait(void);
+extern struct cpufreq_frequency_table loongson2_clockmod_table[];
+
+/* Chip Config */
+#define LOONGSON_CHIPCFG0               LOONGSON_REG(LOONGSON_REGBASE + 0x80)
+#endif
+
+/*
+ * address windows configuration module
+ *
+ * loongson2e do not have this module
+ */
+#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
+
+/* address window config module base address */
+#define LOONGSON_ADDRWINCFG_BASE                0x3ff00000ul
+#define LOONGSON_ADDRWINCFG_SIZE                0x180
+
+extern unsigned long _loongson_addrwincfg_base;
+#define LOONGSON_ADDRWINCFG(offset) \
+        (*(volatile u64 *)(_loongson_addrwincfg_base + (offset)))
+
+#define CPU_WIN0_BASE   LOONGSON_ADDRWINCFG(0x00)
+#define CPU_WIN1_BASE   LOONGSON_ADDRWINCFG(0x08)
+#define CPU_WIN2_BASE   LOONGSON_ADDRWINCFG(0x10)
+#define CPU_WIN3_BASE   LOONGSON_ADDRWINCFG(0x18)
+
+#define CPU_WIN0_MASK   LOONGSON_ADDRWINCFG(0x20)
+#define CPU_WIN1_MASK   LOONGSON_ADDRWINCFG(0x28)
+#define CPU_WIN2_MASK   LOONGSON_ADDRWINCFG(0x30)
+#define CPU_WIN3_MASK   LOONGSON_ADDRWINCFG(0x38)
+
+#define CPU_WIN0_MMAP   LOONGSON_ADDRWINCFG(0x40)
+#define CPU_WIN1_MMAP   LOONGSON_ADDRWINCFG(0x48)
+#define CPU_WIN2_MMAP   LOONGSON_ADDRWINCFG(0x50)
+#define CPU_WIN3_MMAP   LOONGSON_ADDRWINCFG(0x58)
+
+#define PCIDMA_WIN0_BASE        LOONGSON_ADDRWINCFG(0x60)
+#define PCIDMA_WIN1_BASE        LOONGSON_ADDRWINCFG(0x68)
+#define PCIDMA_WIN2_BASE        LOONGSON_ADDRWINCFG(0x70)
+#define PCIDMA_WIN3_BASE        LOONGSON_ADDRWINCFG(0x78)
+
+#define PCIDMA_WIN0_MASK        LOONGSON_ADDRWINCFG(0x80)
+#define PCIDMA_WIN1_MASK        LOONGSON_ADDRWINCFG(0x88)
+#define PCIDMA_WIN2_MASK        LOONGSON_ADDRWINCFG(0x90)
+#define PCIDMA_WIN3_MASK        LOONGSON_ADDRWINCFG(0x98)
+
+#define PCIDMA_WIN0_MMAP        LOONGSON_ADDRWINCFG(0xa0)
+#define PCIDMA_WIN1_MMAP        LOONGSON_ADDRWINCFG(0xa8)
+#define PCIDMA_WIN2_MMAP        LOONGSON_ADDRWINCFG(0xb0)
+#define PCIDMA_WIN3_MMAP        LOONGSON_ADDRWINCFG(0xb8)
+
+#define ADDRWIN_WIN0    0
+#define ADDRWIN_WIN1    1
+#define ADDRWIN_WIN2    2
+#define ADDRWIN_WIN3    3
+
+#define ADDRWIN_MAP_DST_DDR     0
+#define ADDRWIN_MAP_DST_PCI     1
+#define ADDRWIN_MAP_DST_LIO     1
+
+/*
+ * s: CPU, PCIDMA
+ * d: DDR, PCI, LIO
+ * win: 0, 1, 2, 3
+ * src: map source
+ * dst: map destination
+ * size: ~mask + 1
+ */
+#define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\
+        s##_WIN##w##_BASE = (src); \
+        s##_WIN##w##_MMAP = (src) | ADDRWIN_MAP_DST_##d; \
+        s##_WIN##w##_MASK = ~(size-1); \
+} while (0)
+
+#define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \
+        LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size)
+#define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \
+        LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size)
+#define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \
+        LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size)
 
-/* loongson2-specific perf counter IRQ */
-#define LOONGSON2_PERFCNT_IRQ   (MIPS_CPU_IRQ_BASE + 6)
+#endif  /* ! CONFIG_CPU_SUPPORTS_ADDRWINCFG */
 
 #endif /* __ASM_MACH_LOONGSON_LOONGSON_H */
diff --git a/arch/mips/include/asm/mach-loongson/machine.h b/arch/mips/include/asm/mach-loongson/machine.h
index 206ea2067916..acf8359cb135 100644
--- a/arch/mips/include/asm/mach-loongson/machine.h
+++ b/arch/mips/include/asm/mach-loongson/machine.h
@@ -13,10 +13,15 @@
 
 #ifdef CONFIG_LEMOTE_FULOONG2E
 
-#define LOONGSON_UART_BASE (BONITO_PCIIO_BASE + 0x3f8)
-
 #define LOONGSON_MACHTYPE MACH_LEMOTE_FL2E
 
 #endif
 
+/* use fuloong2f as the default machine of LEMOTE_MACH2F */
+#ifdef CONFIG_LEMOTE_MACH2F
+
+#define LOONGSON_MACHTYPE MACH_LEMOTE_FL2F
+
+#endif
+
 #endif /* __ASM_MACH_LOONGSON_MACHINE_H */
diff --git a/arch/mips/include/asm/mach-loongson/mem.h b/arch/mips/include/asm/mach-loongson/mem.h
index bd7b3cba7e35..e9960f341b96 100644
--- a/arch/mips/include/asm/mach-loongson/mem.h
+++ b/arch/mips/include/asm/mach-loongson/mem.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology
+ * Copyright (C) 2009 Lemote, Inc.
  * Author: Wu Zhangjin <wuzj@lemote.com>
  *
  * This program is free software; you can redistribute  it and/or modify it
@@ -12,19 +12,30 @@
 #define __ASM_MACH_LOONGSON_MEM_H
 
 /*
- * On Lemote Loongson 2e
+ * high memory space
  *
- * the high memory space starts from 512M.
- * the peripheral registers reside between 0x1000:0000 and 0x2000:0000.
+ * in loongson2e, starts from 512M
+ * in loongson2f, starts from 2G 256M
  */
+#ifdef CONFIG_CPU_LOONGSON2E
+#define LOONGSON_HIGHMEM_START  0x20000000
+#else
+#define LOONGSON_HIGHMEM_START  0x90000000
+#endif
 
-#ifdef CONFIG_LEMOTE_FULOONG2E
-
-#define LOONGSON_HIGHMEM_START  0x20000000
+/*
+ * the peripheral registers(MMIO):
+ *
+ * On the Lemote Loongson 2e system, reside between 0x1000:0000 and 0x2000:0000.
+ * On the Lemote Loongson 2f system, reside between 0x1000:0000 and 0x8000:0000.
+ */
 
 #define LOONGSON_MMIO_MEM_START 0x10000000
-#define LOONGSON_MMIO_MEM_END   0x20000000
 
+#ifdef CONFIG_CPU_LOONGSON2E
+#define LOONGSON_MMIO_MEM_END   0x20000000
+#else
+#define LOONGSON_MMIO_MEM_END   0x80000000
 #endif
 
 #endif /* __ASM_MACH_LOONGSON_MEM_H */
diff --git a/arch/mips/include/asm/mach-loongson/pci.h b/arch/mips/include/asm/mach-loongson/pci.h
index f1663ca81da0..a199a4f6de4e 100644
--- a/arch/mips/include/asm/mach-loongson/pci.h
+++ b/arch/mips/include/asm/mach-loongson/pci.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org>
+ * Copyright (c) 2009 Wu Zhangjin <wuzj@lemote.com>
  *
  * This program is free software; you can redistribute it
  * and/or modify it under the terms of the GNU General
@@ -22,16 +23,39 @@
 #ifndef __ASM_MACH_LOONGSON_PCI_H_
 #define __ASM_MACH_LOONGSON_PCI_H_
 
-extern struct pci_ops bonito64_pci_ops;
+extern struct pci_ops loongson_pci_ops;
 
-#ifdef CONFIG_LEMOTE_FULOONG2E
+/* this is an offset from mips_io_port_base */
+#define LOONGSON_PCI_IO_START   0x00004000UL
+
+#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
+
+/*
+ * we use address window2 to map cpu address space to pci space
+ * window2: cpu [1G, 2G] -> pci [1G, 2G]
+ * why not use window 0 & 1? because they are used by cpu when booting.
+ * window0: cpu [0, 256M] -> ddr [0, 256M]
+ * window1: cpu [256M, 512M] -> pci [256M, 512M]
+ */
+
+/* the smallest LOONGSON_CPU_MEM_SRC can be 512M */
+#define LOONGSON_CPU_MEM_SRC    0x40000000ul            /* 1G */
+#define LOONGSON_PCI_MEM_DST    LOONGSON_CPU_MEM_SRC
+
+#define LOONGSON_PCI_MEM_START  LOONGSON_PCI_MEM_DST
+#define LOONGSON_PCI_MEM_END    (0x80000000ul-1)        /* 2G */
+
+#define MMAP_CPUTOPCI_SIZE      (LOONGSON_PCI_MEM_END - \
+                                        LOONGSON_PCI_MEM_START + 1)
+
+#else   /* loongson2f/32bit & loongson2e */
 
 /* this pci memory space is mapped by pcimap in pci.c */
-#define LOONGSON_PCI_MEM_START  BONITO_PCILO1_BASE
-#define LOONGSON_PCI_MEM_END    (BONITO_PCILO1_BASE + 0x04000000 * 2)
+#define LOONGSON_PCI_MEM_START  LOONGSON_PCILO1_BASE
+#define LOONGSON_PCI_MEM_END    (LOONGSON_PCILO1_BASE + 0x04000000 * 2)
 /* this is an offset from mips_io_port_base */
 #define LOONGSON_PCI_IO_START   0x00004000UL
 
-#endif
+#endif  /* !CONFIG_CPU_SUPPORTS_ADDRWINCFG */
 
 #endif /* !__ASM_MACH_LOONGSON_PCI_H_ */
diff --git a/arch/mips/include/asm/mach-powertv/asic.h b/arch/mips/include/asm/mach-powertv/asic.h
new file mode 100644
index 000000000000..bcad43a93ebf
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/asic.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2009  Cisco Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef _ASM_MACH_POWERTV_ASIC_H
+#define _ASM_MACH_POWERTV_ASIC_H
+
+#include <linux/ioport.h>
+#include <asm/mach-powertv/asic_regs.h>
+
+#define DVR_CAPABLE     (1<<0)
+#define PCIE_CAPABLE    (1<<1)
+#define FFS_CAPABLE     (1<<2)
+#define DISPLAY_CAPABLE (1<<3)
+
+/* Platform Family types
+ * For compitability, the new value must be added in the end */
+enum family_type {
+        FAMILY_8500,
+        FAMILY_8500RNG,
+        FAMILY_4500,
+        FAMILY_1500,
+        FAMILY_8600,
+        FAMILY_4600,
+        FAMILY_4600VZA,
+        FAMILY_8600VZB,
+        FAMILY_1500VZE,
+        FAMILY_1500VZF,
+        FAMILIES
+};
+
+/* Register maps for each ASIC */
+extern const struct register_map calliope_register_map;
+extern const struct register_map cronus_register_map;
+extern const struct register_map zeus_register_map;
+
+extern struct resource dvr_cronus_resources[];
+extern struct resource dvr_zeus_resources[];
+extern struct resource non_dvr_calliope_resources[];
+extern struct resource non_dvr_cronus_resources[];
+extern struct resource non_dvr_cronuslite_resources[];
+extern struct resource non_dvr_vz_calliope_resources[];
+extern struct resource non_dvr_vze_calliope_resources[];
+extern struct resource non_dvr_vzf_calliope_resources[];
+extern struct resource non_dvr_zeus_resources[];
+
+extern void powertv_platform_init(void);
+extern void platform_alloc_bootmem(void);
+extern enum asic_type platform_get_asic(void);
+extern enum family_type platform_get_family(void);
+extern int platform_supports_dvr(void);
+extern int platform_supports_ffs(void);
+extern int platform_supports_pcie(void);
+extern int platform_supports_display(void);
+extern void configure_platform(void);
+extern void platform_configure_usb_ehci(void);
+extern void platform_unconfigure_usb_ehci(void);
+extern void platform_configure_usb_ohci(void);
+extern void platform_unconfigure_usb_ohci(void);
+
+/* Platform Resources */
+#define ASIC_RESOURCE_GET_EXISTS 1
+extern struct resource *asic_resource_get(const char *name);
+extern void platform_release_memory(void *baddr, int size);
+
+/* Reboot Cause */
+extern void set_reboot_cause(char code, unsigned int data, unsigned int data2);
+extern void set_locked_reboot_cause(char code, unsigned int data,
+        unsigned int data2);
+
+enum sys_reboot_type {
+        sys_unknown_reboot = 0x00,      /* Unknown reboot cause */
+        sys_davic_change = 0x01,        /* Reboot due to change in DAVIC
+                                         * mode */
+        sys_user_reboot = 0x02,         /* Reboot initiated by user */
+        sys_system_reboot = 0x03,       /* Reboot initiated by OS */
+        sys_trap_reboot = 0x04,         /* Reboot due to a CPU trap */
+        sys_silent_reboot = 0x05,       /* Silent reboot */
+        sys_boot_ldr_reboot = 0x06,     /* Bootloader reboot */
+        sys_power_up_reboot = 0x07,     /* Power on bootup.  Older
+                                         * drivers may report as
+                                         * userReboot. */
+        sys_code_change = 0x08,         /* Reboot to take code change.
+                                         * Older drivers may report as
+                                         * userReboot. */
+        sys_hardware_reset = 0x09,      /* HW watchdog or front-panel
+                                         * reset button reset.  Older
+                                         * drivers may report as
+                                         * userReboot. */
+        sys_watchdogInterrupt = 0x0A    /* Pre-watchdog interrupt */
+};
+
+#endif /* _ASM_MACH_POWERTV_ASIC_H */
diff --git a/arch/mips/include/asm/mach-powertv/asic_regs.h b/arch/mips/include/asm/mach-powertv/asic_regs.h
new file mode 100644
index 000000000000..9a65c93782f9
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/asic_regs.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (C) 2009  Cisco Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef __ASM_MACH_POWERTV_ASIC_H_
+#define __ASM_MACH_POWERTV_ASIC_H_
+#include <linux/io.h>
+
+/* ASIC types */
+enum asic_type {
+        ASIC_UNKNOWN,
+        ASIC_ZEUS,
+        ASIC_CALLIOPE,
+        ASIC_CRONUS,
+        ASIC_CRONUSLITE,
+        ASICS
+};
+
+/* hardcoded values read from Chip Version registers */
+#define CRONUS_10       0x0B4C1C20
+#define CRONUS_11       0x0B4C1C21
+#define CRONUSLITE_10   0x0B4C1C40
+
+#define NAND_FLASH_BASE 0x03000000
+#define ZEUS_IO_BASE    0x09000000
+#define CALLIOPE_IO_BASE        0x08000000
+#define CRONUS_IO_BASE  0x09000000
+#define ASIC_IO_SIZE    0x01000000
+
+/* Definitions for backward compatibility */
+#define UART1_INTSTAT   uart1_intstat
+#define UART1_INTEN     uart1_inten
+#define UART1_CONFIG1   uart1_config1
+#define UART1_CONFIG2   uart1_config2
+#define UART1_DIVISORHI uart1_divisorhi
+#define UART1_DIVISORLO uart1_divisorlo
+#define UART1_DATA      uart1_data
+#define UART1_STATUS    uart1_status
+
+/* ASIC register enumeration */
+struct register_map {
+        u32 eic_slow0_strt_add;
+        u32 eic_cfg_bits;
+        u32 eic_ready_status;
+
+        u32 chipver3;
+        u32 chipver2;
+        u32 chipver1;
+        u32 chipver0;
+
+        u32 uart1_intstat;
+        u32 uart1_inten;
+        u32 uart1_config1;
+        u32 uart1_config2;
+        u32 uart1_divisorhi;
+        u32 uart1_divisorlo;
+        u32 uart1_data;
+        u32 uart1_status;
+
+        u32 int_stat_3;
+        u32 int_stat_2;
+        u32 int_stat_1;
+        u32 int_stat_0;
+        u32 int_config;
+        u32 int_int_scan;
+        u32 ien_int_3;
+        u32 ien_int_2;
+        u32 ien_int_1;
+        u32 ien_int_0;
+        u32 int_level_3_3;
+        u32 int_level_3_2;
+        u32 int_level_3_1;
+        u32 int_level_3_0;
+        u32 int_level_2_3;
+        u32 int_level_2_2;
+        u32 int_level_2_1;
+        u32 int_level_2_0;
+        u32 int_level_1_3;
+        u32 int_level_1_2;
+        u32 int_level_1_1;
+        u32 int_level_1_0;
+        u32 int_level_0_3;
+        u32 int_level_0_2;
+        u32 int_level_0_1;
+        u32 int_level_0_0;
+        u32 int_docsis_en;
+
+        u32 mips_pll_setup;
+        u32 usb_fs;
+        u32 test_bus;
+        u32 crt_spare;
+        u32 usb2_ohci_int_mask;
+        u32 usb2_strap;
+        u32 ehci_hcapbase;
+        u32 ohci_hc_revision;
+        u32 bcm1_bs_lmi_steer;
+        u32 usb2_control;
+        u32 usb2_stbus_obc;
+        u32 usb2_stbus_mess_size;
+        u32 usb2_stbus_chunk_size;
+
+        u32 pcie_regs;
+        u32 tim_ch;
+        u32 tim_cl;
+        u32 gpio_dout;
+        u32 gpio_din;
+        u32 gpio_dir;
+        u32 watchdog;
+        u32 front_panel;
+
+        u32 register_maps;
+};
+
+extern enum asic_type asic;
+extern const struct register_map *register_map;
+extern unsigned long asic_phy_base;     /* Physical address of ASIC */
+extern unsigned long asic_base;         /* Virtual address of ASIC */
+
+/*
+ * Macros to interface to registers through their ioremapped address
+ * asic_reg_offset      Returns the offset of a given register from the start
+ *                      of the ASIC address space
+ * asic_reg_phys_addr   Returns the physical address of the given register
+ * asic_reg_addr        Returns the iomapped virtual address of the given
+ *                      register.
+ */
+#define asic_reg_offset(x)      (register_map->x)
+#define asic_reg_phys_addr(x)   (asic_phy_base + asic_reg_offset(x))
+#define asic_reg_addr(x) \
+        ((unsigned int *) (asic_base + asic_reg_offset(x)))
+
+/*
+ * The asic_reg macro is gone. It should be replaced by either asic_read or
+ * asic_write, as appropriate.
+ */
+
+#define asic_read(x)            readl(asic_reg_addr(x))
+#define asic_write(v, x)        writel(v, asic_reg_addr(x))
+
+extern void asic_irq_init(void);
+#endif
diff --git a/arch/mips/include/asm/mach-powertv/dma-coherence.h b/arch/mips/include/asm/mach-powertv/dma-coherence.h
new file mode 100644
index 000000000000..5b8d5ebeb838
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/dma-coherence.h
@@ -0,0 +1,119 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Version from mach-generic modified to support PowerTV port
+ * Portions Copyright (C) 2009  Cisco Systems, Inc.
+ * Copyright (C) 2006  Ralf Baechle <ralf@linux-mips.org>
+ *
+ */
+
+#ifndef __ASM_MACH_POWERTV_DMA_COHERENCE_H
+#define __ASM_MACH_POWERTV_DMA_COHERENCE_H
+
+#include <linux/sched.h>
+#include <linux/version.h>
+#include <linux/device.h>
+#include <asm/mach-powertv/asic.h>
+
+static inline bool is_kseg2(void *addr)
+{
+        return (unsigned long)addr >= KSEG2;
+}
+
+static inline unsigned long virt_to_phys_from_pte(void *addr)
+{
+        pgd_t *pgd;
+        pud_t *pud;
+        pmd_t *pmd;
+        pte_t *ptep, pte;
+
+        unsigned long virt_addr = (unsigned long)addr;
+        unsigned long phys_addr = 0UL;
+
+        /* get the page global directory. */
+        pgd = pgd_offset_k(virt_addr);
+
+        if (!pgd_none(*pgd)) {
+                /* get the page upper directory */
+                pud = pud_offset(pgd, virt_addr);
+                if (!pud_none(*pud)) {
+                        /* get the page middle directory */
+                        pmd = pmd_offset(pud, virt_addr);
+                        if (!pmd_none(*pmd)) {
+                                /* get a pointer to the page table entry */
+                                ptep = pte_offset(pmd, virt_addr);
+                                pte = *ptep;
+                                /* check for a valid page */
+                                if (pte_present(pte)) {
+                                        /* get the physical address the page is
+                                         * refering to */
+                                        phys_addr = (unsigned long)
+                                                page_to_phys(pte_page(pte));
+                                        /* add the offset within the page */
+                                        phys_addr |= (virt_addr & ~PAGE_MASK);
+                                }
+                        }
+                }
+        }
+
+        return phys_addr;
+}
+
+static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
+        size_t size)
+{
+        if (is_kseg2(addr))
+                return phys_to_bus(virt_to_phys_from_pte(addr));
+        else
+                return phys_to_bus(virt_to_phys(addr));
+}
+
+static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
+        struct page *page)
+{
+        return phys_to_bus(page_to_phys(page));
+}
+
+static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
+        dma_addr_t dma_addr)
+{
+        return bus_to_phys(dma_addr);
+}
+
+static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
+        size_t size, enum dma_data_direction direction)
+{
+}
+
+static inline int plat_dma_supported(struct device *dev, u64 mask)
+{
+        /*
+         * we fall back to GFP_DMA when the mask isn't all 1s,
+         * so we can't guarantee allocations that must be
+         * within a tighter range than GFP_DMA..
+         */
+        if (mask < DMA_BIT_MASK(24))
+                return 0;
+
+        return 1;
+}
+
+static inline void plat_extra_sync_for_device(struct device *dev)
+{
+        return;
+}
+
+static inline int plat_dma_mapping_error(struct device *dev,
+                                         dma_addr_t dma_addr)
+{
+        return 0;
+}
+
+static inline int plat_device_is_coherent(struct device *dev)
+{
+        return 0;
+}
+
+#endif /* __ASM_MACH_POWERTV_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-powertv/interrupts.h b/arch/mips/include/asm/mach-powertv/interrupts.h
new file mode 100644
index 000000000000..629a57413657
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/interrupts.h
@@ -0,0 +1,254 @@
+/*
+ * Copyright (C) 2009  Cisco Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef _ASM_MACH_POWERTV_INTERRUPTS_H_
+#define _ASM_MACH_POWERTV_INTERRUPTS_H_
+
+/*
+ * Defines for all of the interrupt lines
+ */
+
+/* Definitions for backward compatibility */
+#define kIrq_Uart1              irq_uart1
+
+#define ibase 0
+
+/*------------- Register: int_stat_3 */
+/* 126 unused (bit 31) */
+#define irq_asc2video           (ibase+126)     /* ASC 2 Video Interrupt */
+#define irq_asc1video           (ibase+125)     /* ASC 1 Video Interrupt */
+#define irq_comms_block_wd      (ibase+124)     /* ASC 1 Video Interrupt */
+#define irq_fdma_mailbox        (ibase+123)     /* FDMA Mailbox Output */
+#define irq_fdma_gp             (ibase+122)     /* FDMA GP Output */
+#define irq_mips_pic            (ibase+121)     /* MIPS Performance Counter
+                                                 * Interrupt */
+#define irq_mips_timer          (ibase+120)     /* MIPS Timer Interrupt */
+#define irq_memory_protect      (ibase+119)     /* Memory Protection Interrupt
+                                                 * -- Ored by glue logic inside
+                                                 *  SPARC ILC (see
+                                                 *  INT_MEM_PROT_STAT, below,
+                                                 *  for individual interrupts)
+                                                 */
+/* 118 unused (bit 22) */
+#define irq_sbag                (ibase+117)     /* SBAG Interrupt -- Ored by
+                                                 * glue logic inside SPARC ILC
+                                                 * (see INT_SBAG_STAT, below,
+                                                 * for individual interrupts) */
+#define irq_qam_b_fec           (ibase+116)     /* QAM  B FEC Interrupt */
+#define irq_qam_a_fec           (ibase+115)     /* QAM A FEC Interrupt */
+/* 114 unused   (bit 18) */
+#define irq_mailbox             (ibase+113)     /* Mailbox Debug Interrupt  --
+                                                 * Ored by glue logic inside
+                                                 * SPARC ILC (see
+                                                 * INT_MAILBOX_STAT, below, for
+                                                 * individual interrupts) */
+#define irq_fuse_stat1          (ibase+112)     /* Fuse Status 1 */
+#define irq_fuse_stat2          (ibase+111)     /* Fuse Status 2 */
+#define irq_fuse_stat3          (ibase+110)     /* Blitter Interrupt / Fuse
+                                                 * Status 3 */
+#define irq_blitter             (ibase+110)     /* Blitter Interrupt / Fuse
+                                                 * Status 3 */
+#define irq_avc1_pp0            (ibase+109)     /* AVC Decoder #1 PP0
+                                                 * Interrupt */
+#define irq_avc1_pp1            (ibase+108)     /* AVC Decoder #1 PP1
+                                                 * Interrupt */
+#define irq_avc1_mbe            (ibase+107)     /* AVC Decoder #1 MBE
+                                                 * Interrupt */
+#define irq_avc2_pp0            (ibase+106)     /* AVC Decoder #2 PP0
+                                                 * Interrupt */
+#define irq_avc2_pp1            (ibase+105)     /* AVC Decoder #2 PP1
+                                                 * Interrupt */
+#define irq_avc2_mbe            (ibase+104)     /* AVC Decoder #2 MBE
+                                                 * Interrupt */
+#define irq_zbug_spi            (ibase+103)     /* Zbug SPI Slave Interrupt */
+#define irq_qam_mod2            (ibase+102)     /* QAM Modulator 2 DMA
+                                                 * Interrupt */
+#define irq_ir_rx               (ibase+101)     /* IR RX 2 Interrupt */
+#define irq_aud_dsp2            (ibase+100)     /* Audio DSP #2 Interrupt */
+#define irq_aud_dsp1            (ibase+99)      /* Audio DSP #1 Interrupt */
+#define irq_docsis              (ibase+98)      /* DOCSIS Debug Interrupt */
+#define irq_sd_dvp1             (ibase+97)      /* SD DVP #1 Interrupt */
+#define irq_sd_dvp2             (ibase+96)      /* SD DVP #2 Interrupt */
+/*------------- Register: int_stat_2 */
+#define irq_hd_dvp              (ibase+95)      /* HD DVP Interrupt */
+#define kIrq_Prewatchdog        (ibase+94)      /* watchdog Pre-Interrupt */
+#define irq_timer2              (ibase+93)      /* Programmable Timer
+                                                 * Interrupt 2 */
+#define irq_1394                (ibase+92)      /* 1394 Firewire Interrupt */
+#define irq_usbohci             (ibase+91)      /* USB 2.0 OHCI Interrupt */
+#define irq_usbehci             (ibase+90)      /* USB 2.0 EHCI Interrupt */
+#define irq_pciexp              (ibase+89)      /* PCI Express 0 Interrupt */
+#define irq_pciexp0             (ibase+89)      /* PCI Express 0 Interrupt */
+#define irq_afe1                (ibase+88)      /* AFE 1 Interrupt */
+#define irq_sata                (ibase+87)      /* SATA 1 Interrupt */
+#define irq_sata1               (ibase+87)      /* SATA 1 Interrupt */
+#define irq_dtcp                (ibase+86)      /* DTCP Interrupt */
+#define irq_pciexp1             (ibase+85)      /* PCI Express 1 Interrupt */
+/* 84 unused    (bit 20) */
+/* 83 unused    (bit 19) */
+/* 82 unused    (bit 18) */
+#define irq_sata2               (ibase+81)      /* SATA2 Interrupt */
+#define irq_uart2               (ibase+80)      /* UART2 Interrupt */
+#define irq_legacy_usb          (ibase+79)      /* Legacy USB Host ISR (1.1
+                                                 * Host module) */
+#define irq_pod                 (ibase+78)      /* POD Interrupt */
+#define irq_slave_usb           (ibase+77)      /* Slave USB */
+#define irq_denc1               (ibase+76)      /* DENC #1 VTG Interrupt */
+#define irq_vbi_vtg             (ibase+75)      /* VBI VTG Interrupt */
+#define irq_afe2                (ibase+74)      /* AFE 2 Interrupt */
+#define irq_denc2               (ibase+73)      /* DENC #2 VTG Interrupt */
+#define irq_asc2                (ibase+72)      /* ASC #2 Interrupt */
+#define irq_asc1                (ibase+71)      /* ASC #1 Interrupt */
+#define irq_mod_dma             (ibase+70)      /* Modulator DMA Interrupt */
+#define irq_byte_eng1           (ibase+69)      /* Byte Engine Interrupt [1] */
+#define irq_byte_eng0           (ibase+68)      /* Byte Engine Interrupt [0] */
+/* 67 unused    (bit 03) */
+/* 66 unused    (bit 02) */
+/* 65 unused    (bit 01) */
+/* 64 unused    (bit 00) */
+/*------------- Register: int_stat_1 */
+/* 63 unused    (bit 31) */
+/* 62 unused    (bit 30) */
+/* 61 unused    (bit 29) */
+/* 60 unused    (bit 28) */
+/* 59 unused    (bit 27) */
+/* 58 unused    (bit 26) */
+/* 57 unused    (bit 25) */
+/* 56 unused    (bit 24) */
+#define irq_buf_dma_mem2mem     (ibase+55)      /* BufDMA Memory to Memory
+                                                 * Interrupt */
+#define irq_buf_dma_usbtransmit (ibase+54)      /* BufDMA USB Transmit
+                                                 * Interrupt */
+#define irq_buf_dma_qpskpodtransmit (ibase+53)  /* BufDMA QPSK/POD Tramsit
+                                                 * Interrupt */
+#define irq_buf_dma_transmit_error (ibase+52)   /* BufDMA Transmit Error
+                                                 * Interrupt */
+#define irq_buf_dma_usbrecv     (ibase+51)      /* BufDMA USB Receive
+                                                 * Interrupt */
+#define irq_buf_dma_qpskpodrecv (ibase+50)      /* BufDMA QPSK/POD Receive
+                                                 * Interrupt */
+#define irq_buf_dma_recv_error  (ibase+49)      /* BufDMA Receive Error
+                                                 * Interrupt */
+#define irq_qamdma_transmit_play (ibase+48)     /* QAMDMA Transmit/Play
+                                                 * Interrupt */
+#define irq_qamdma_transmit_error (ibase+47)    /* QAMDMA Transmit Error
+                                                 * Interrupt */
+#define irq_qamdma_recv2high    (ibase+46)      /* QAMDMA Receive 2 High
+                                                 * (Chans 63-32) */
+#define irq_qamdma_recv2low     (ibase+45)      /* QAMDMA Receive 2 Low
+                                                 * (Chans 31-0) */
+#define irq_qamdma_recv1high    (ibase+44)      /* QAMDMA Receive 1 High
+                                                 * (Chans 63-32) */
+#define irq_qamdma_recv1low     (ibase+43)      /* QAMDMA Receive 1 Low
+                                                 * (Chans 31-0) */
+#define irq_qamdma_recv_error   (ibase+42)      /* QAMDMA Receive Error
+                                                 * Interrupt */
+#define irq_mpegsplice          (ibase+41)      /* MPEG Splice Interrupt */
+#define irq_deinterlace_rdy     (ibase+40)      /* Deinterlacer Frame Ready
+                                                 * Interrupt */
+#define irq_ext_in0             (ibase+39)      /* External Interrupt irq_in0 */
+#define irq_gpio3               (ibase+38)      /* GP I/O IRQ 3 - From GP I/O
+                                                 * Module */
+#define irq_gpio2               (ibase+37)      /* GP I/O IRQ 2 - From GP I/O
+                                                 * Module (ABE_intN) */
+#define irq_pcrcmplt1           (ibase+36)      /* PCR Capture Complete  or
+                                                 * Discontinuity 1 */
+#define irq_pcrcmplt2           (ibase+35)      /* PCR Capture Complete or
+                                                 * Discontinuity 2 */
+#define irq_parse_peierr        (ibase+34)      /* PID Parser Error Detect
+                                                 * (PEI) */
+#define irq_parse_cont_err      (ibase+33)      /* PID Parser continuity error
+                                                 * detect */
+#define irq_ds1framer           (ibase+32)      /* DS1 Framer Interrupt */
+/*------------- Register: int_stat_0 */
+#define irq_gpio1               (ibase+31)      /* GP I/O IRQ 1 - From GP I/O
+                                                 * Module */
+#define irq_gpio0               (ibase+30)      /* GP I/O IRQ 0 - From GP I/O
+                                                 * Module */
+#define irq_qpsk_out_aloha      (ibase+29)      /* QPSK Output Slotted Aloha
+                                                 * (chan 3) Transmission
+                                                 * Completed OK */
+#define irq_qpsk_out_tdma       (ibase+28)      /* QPSK Output TDMA (chan 2)
+                                                 * Transmission Completed OK */
+#define irq_qpsk_out_reserve    (ibase+27)      /* QPSK Output Reservation
+                                                 * (chan 1) Transmission
+                                                 * Completed OK */
+#define irq_qpsk_out_aloha_err  (ibase+26)      /* QPSK Output Slotted Aloha
+                                                 * (chan 3)Transmission
+                                                 * completed with Errors. */
+#define irq_qpsk_out_tdma_err   (ibase+25)      /* QPSK Output TDMA (chan 2)
+                                                 * Transmission completed with
+                                                 * Errors. */
+#define irq_qpsk_out_rsrv_err   (ibase+24)      /* QPSK Output Reservation
+                                                 * (chan 1) Transmission
+                                                 * completed with Errors */
+#define irq_aloha_fail          (ibase+23)      /* Unsuccessful Resend of Aloha
+                                                 * for N times. Aloha retry
+                                                 * timeout for channel 3. */
+#define irq_timer1              (ibase+22)      /* Programmable Timer
+                                                 * Interrupt */
+#define irq_keyboard            (ibase+21)      /* Keyboard Module Interrupt */
+#define irq_i2c                 (ibase+20)      /* I2C Module Interrupt */
+#define irq_spi                 (ibase+19)      /* SPI Module Interrupt */
+#define irq_irblaster           (ibase+18)      /* IR Blaster Interrupt */
+#define irq_splice_detect       (ibase+17)      /* PID Key Change Interrupt or
+                                                 * Splice Detect Interrupt */
+#define irq_se_micro            (ibase+16)      /* Secure Micro I/F Module
+                                                 * Interrupt */
+#define irq_uart1               (ibase+15)      /* UART Interrupt */
+#define irq_irrecv              (ibase+14)      /* IR Receiver Interrupt */
+#define irq_host_int1           (ibase+13)      /* Host-to-Host Interrupt 1 */
+#define irq_host_int0           (ibase+12)      /* Host-to-Host Interrupt 0 */
+#define irq_qpsk_hecerr         (ibase+11)      /* QPSK HEC Error Interrupt */
+#define irq_qpsk_crcerr         (ibase+10)      /* QPSK AAL-5 CRC Error
+                                                 * Interrupt */
+/* 9 unused     (bit 09) */
+/* 8 unused     (bit 08) */
+#define irq_psicrcerr           (ibase+7)       /* QAM PSI CRC Error
+                                                 * Interrupt */
+#define irq_psilength_err       (ibase+6)       /* QAM PSI Length Error
+                                                 * Interrupt */
+#define irq_esfforward          (ibase+5)       /* ESF Interrupt Mark From
+                                                 * Forward Path Reference -
+                                                 * every 3ms when forward Mbits
+                                                 * and forward slot control
+                                                 * bytes are updated. */
+#define irq_esfreverse          (ibase+4)       /* ESF Interrupt Mark from
+                                                 * Reverse Path Reference -
+                                                 * delayed from forward mark by
+                                                 * the ranging delay plus a
+                                                 * fixed amount. When reverse
+                                                 * Mbits and reverse slot
+                                                 * control bytes are updated.
+                                                 * Occurs every 3ms for 3.0M and
+                                                 * 1.554 M upstream rates and
+                                                 * every 6 ms for 256K upstream
+                                                 * rate. */
+#define irq_aloha_timeout       (ibase+3)       /* Slotted-Aloha timeout on
+                                                 * Channel 1. */
+#define irq_reservation         (ibase+2)       /* Partial (or Incremental)
+                                                 * Reservation Message Completed
+                                                 * or Slotted aloha verify for
+                                                 * channel 1. */
+#define irq_aloha3              (ibase+1)       /* Slotted-Aloha Message Verify
+                                                 * Interrupt or Reservation
+                                                 * increment completed for
+                                                 * channel 3. */
+#define irq_mpeg_d              (ibase+0)       /* MPEG Decoder Interrupt */
+#endif  /* _ASM_MACH_POWERTV_INTERRUPTS_H_ */
+
diff --git a/arch/mips/include/asm/mach-powertv/ioremap.h b/arch/mips/include/asm/mach-powertv/ioremap.h
new file mode 100644
index 000000000000..e6276d5146e8
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/ioremap.h
@@ -0,0 +1,90 @@
+/*
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ *
+ * Portions Copyright (C)  Cisco Systems, Inc.
+ */
+#ifndef __ASM_MACH_POWERTV_IOREMAP_H
+#define __ASM_MACH_POWERTV_IOREMAP_H
+
+#include <linux/types.h>
+
+#define LOW_MEM_BOUNDARY_PHYS   0x20000000
+#define LOW_MEM_BOUNDARY_MASK   (~(LOW_MEM_BOUNDARY_PHYS - 1))
+
+/*
+ * The bus addresses are different than the physical addresses that
+ * the processor sees by an offset. This offset varies by ASIC
+ * version. Define a variable to hold the offset and some macros to
+ * make the conversion simpler. */
+extern unsigned long phys_to_bus_offset;
+
+#ifdef CONFIG_HIGHMEM
+#define MEM_GAP_PHYS            0x60000000
+/*
+ * TODO: We will use the hard code for conversion between physical and
+ * bus until the bootloader releases their device tree to us.
+ */
+#define phys_to_bus(x) (((x) < LOW_MEM_BOUNDARY_PHYS) ? \
+        ((x) + phys_to_bus_offset) : (x))
+#define bus_to_phys(x) (((x) < MEM_GAP_PHYS_ADDR) ? \
+        ((x) - phys_to_bus_offset) : (x))
+#else
+#define phys_to_bus(x) ((x) + phys_to_bus_offset)
+#define bus_to_phys(x) ((x) - phys_to_bus_offset)
+#endif
+
+/*
+ * Determine whether the address we are given is for an ASIC device
+ * Params:  addr    Address to check
+ * Returns: Zero if the address is not for ASIC devices, non-zero
+ *      if it is.
+ */
+static inline int asic_is_device_addr(phys_t addr)
+{
+        return !((phys_t)addr & (phys_t) LOW_MEM_BOUNDARY_MASK);
+}
+
+/*
+ * Determine whether the address we are given is external RAM mappable
+ * into KSEG1.
+ * Params:  addr    Address to check
+ * Returns: Zero if the address is not for external RAM and
+ */
+static inline int asic_is_lowmem_ram_addr(phys_t addr)
+{
+        /*
+         * The RAM always starts at the following address in the processor's
+         * physical address space
+         */
+        static const phys_t phys_ram_base = 0x10000000;
+        phys_t bus_ram_base;
+
+        bus_ram_base = phys_to_bus_offset + phys_ram_base;
+
+        return addr >= bus_ram_base &&
+                addr < (bus_ram_base + (LOW_MEM_BOUNDARY_PHYS - phys_ram_base));
+}
+
+/*
+ * Allow physical addresses to be fixed up to help peripherals located
+ * outside the low 32-bit range -- generic pass-through version.
+ */
+static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
+{
+        return phys_addr;
+}
+
+static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
+        unsigned long flags)
+{
+        return NULL;
+}
+
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+        return 0;
+}
+#endif /* __ASM_MACH_POWERTV_IOREMAP_H */
diff --git a/arch/mips/include/asm/mach-powertv/irq.h b/arch/mips/include/asm/mach-powertv/irq.h
new file mode 100644
index 000000000000..4bd5d0c61a91
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/irq.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2009  Cisco Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef _ASM_MACH_POWERTV_IRQ_H
+#define _ASM_MACH_POWERTV_IRQ_H
+#include <asm/mach-powertv/interrupts.h>
+
+#define MIPS_CPU_IRQ_BASE       ibase
+#define NR_IRQS                 127
+#endif
diff --git a/arch/mips/include/asm/mach-powertv/powertv-clock.h b/arch/mips/include/asm/mach-powertv/powertv-clock.h
new file mode 100644
index 000000000000..6f3e9a0fcf8c
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/powertv-clock.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2009  Cisco Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+/*
+ * Local definitions for the powertv PCI code
+ */
+
+#ifndef _POWERTV_PCI_POWERTV_PCI_H_
+#define _POWERTV_PCI_POWERTV_PCI_H_
+extern int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
+extern int asic_pcie_init(void);
+extern int asic_pcie_init(void);
+
+extern int log_level;
+#endif
diff --git a/arch/mips/include/asm/mach-excite/war.h b/arch/mips/include/asm/mach-powertv/war.h
index 1f82180c1598..7ac05ecc512b 100644
--- a/arch/mips/include/asm/mach-excite/war.h
+++ b/arch/mips/include/asm/mach-powertv/war.h
@@ -3,10 +3,13 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
+ * This version for the PowerTV platform copied from the Malta version.
+ *
  * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ * Portions copyright (C) 2009 Cisco Systems, Inc.
  */
-#ifndef __ASM_MIPS_MACH_EXCITE_WAR_H
-#define __ASM_MIPS_MACH_EXCITE_WAR_H
+#ifndef __ASM_MACH_POWERTV_WAR_H
+#define __ASM_MACH_POWERTV_WAR_H
 
 #define R4600_V1_INDEX_ICACHEOP_WAR     0
 #define R4600_V1_HIT_CACHEOP_WAR        0
@@ -14,12 +17,12 @@
 #define R5432_CP0_INTERRUPT_WAR         0
 #define BCM1250_M3_WAR                  0
 #define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
+#define MIPS4K_ICACHE_REFILL_WAR        1
+#define MIPS_CACHE_SYNC_WAR             1
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             1
-#define ICACHE_REFILLS_WORKAROUND_WAR   1
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   1
 #define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR 0
+#define MIPS34K_MISSED_ITLB_WAR         0
 
-#endif /* __ASM_MIPS_MACH_EXCITE_WAR_H */
+#endif /* __ASM_MACH_POWERTV_WAR_H */
diff --git a/arch/mips/include/asm/mips-boards/bonito64.h b/arch/mips/include/asm/mips-boards/bonito64.h
index a576ce044c3c..d14e2adc4be5 100644
--- a/arch/mips/include/asm/mips-boards/bonito64.h
+++ b/arch/mips/include/asm/mips-boards/bonito64.h
@@ -26,11 +26,6 @@
 /* offsets from base register */
 #define BONITO(x)       (x)
 
-#elif defined(CONFIG_LEMOTE_FULOONG2E)
-
-#define BONITO(x) (*(volatile u32 *)((char *)CKSEG1ADDR(BONITO_REG_BASE) + (x)))
-#define BONITO_IRQ_BASE   32
-
 #else
 
 /*
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index 6083db586500..145bb81ccaa5 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -24,6 +24,33 @@
 #endif /* SMTC */
 #include <asm-generic/mm_hooks.h>
 
+#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
+
+#define TLBMISS_HANDLER_SETUP_PGD(pgd)                          \
+        tlbmiss_handler_setup_pgd((unsigned long)(pgd))
+
+static inline void tlbmiss_handler_setup_pgd(unsigned long pgd)
+{
+        /* Check for swapper_pg_dir and convert to physical address. */
+        if ((pgd & CKSEG3) == CKSEG0)
+                pgd = CPHYSADDR(pgd);
+        write_c0_context(pgd << 11);
+}
+
+#define TLBMISS_HANDLER_SETUP()                                         \
+        do {                                                            \
+                TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir);              \
+                write_c0_xcontext((unsigned long) smp_processor_id() << 51); \
+        } while (0)
+
+
+static inline unsigned long get_current_pgd(void)
+{
+        return PHYS_TO_XKSEG_CACHED((read_c0_context() >> 11) & ~0xfffUL);
+}
+
+#else /* CONFIG_MIPS_PGD_C0_CONTEXT: using  pgd_current*/
+
 /*
  * For the fast tlb miss handlers, we keep a per cpu array of pointers
  * to the current pgd for each processor. Also, the proc. id is stuffed
@@ -46,7 +73,7 @@ extern unsigned long pgd_current[];
         back_to_back_c0_hazard();                                       \
         TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
 #endif
-
+#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
 
 #define ASID_INC        0x40
diff --git a/arch/mips/include/asm/octeon/cvmx-agl-defs.h b/arch/mips/include/asm/octeon/cvmx-agl-defs.h
new file mode 100644
index 000000000000..ec94b9ab7be1
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-agl-defs.h
@@ -0,0 +1,1194 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_AGL_DEFS_H__
+#define __CVMX_AGL_DEFS_H__
+
+#define CVMX_AGL_GMX_BAD_REG \
+         CVMX_ADD_IO_SEG(0x00011800E0000518ull)
+#define CVMX_AGL_GMX_BIST \
+         CVMX_ADD_IO_SEG(0x00011800E0000400ull)
+#define CVMX_AGL_GMX_DRV_CTL \
+         CVMX_ADD_IO_SEG(0x00011800E00007F0ull)
+#define CVMX_AGL_GMX_INF_MODE \
+         CVMX_ADD_IO_SEG(0x00011800E00007F8ull)
+#define CVMX_AGL_GMX_PRTX_CFG(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000010ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000180ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000188ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000190ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000198ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E00001A0ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E00001A8ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000108ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_ADR_CTL(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000100ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_DECISION(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000040ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_FRM_CHK(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000020ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_FRM_CTL(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000018ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_FRM_MAX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000030ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_FRM_MIN(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000028ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_IFG(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000058ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_INT_EN(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000008ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_INT_REG(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000000ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_JABBER(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000038ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000068ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_STATS_CTL(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000050ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000088ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000098ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E00000A8ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E00000B8ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000080ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E00000C0ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000090ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E00000A0ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E00000B0ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RXX_UDD_SKP(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000048ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_RX_BP_DROPX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000420ull + (((offset) & 1) * 8))
+#define CVMX_AGL_GMX_RX_BP_OFFX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000460ull + (((offset) & 1) * 8))
+#define CVMX_AGL_GMX_RX_BP_ONX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000440ull + (((offset) & 1) * 8))
+#define CVMX_AGL_GMX_RX_PRT_INFO \
+         CVMX_ADD_IO_SEG(0x00011800E00004E8ull)
+#define CVMX_AGL_GMX_RX_TX_STATUS \
+         CVMX_ADD_IO_SEG(0x00011800E00007E8ull)
+#define CVMX_AGL_GMX_SMACX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000230ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_STAT_BP \
+         CVMX_ADD_IO_SEG(0x00011800E0000520ull)
+#define CVMX_AGL_GMX_TXX_APPEND(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000218ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_CTL(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000270ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_MIN_PKT(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000240ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000248ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000238ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000258ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000260ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000250ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_STAT0(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000280ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_STAT1(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000288ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_STAT2(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000290ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_STAT3(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000298ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_STAT4(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E00002A0ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_STAT5(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E00002A8ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_STAT6(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E00002B0ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_STAT7(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E00002B8ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_STAT8(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E00002C0ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_STAT9(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E00002C8ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_STATS_CTL(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000268ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TXX_THRESH(offset) \
+         CVMX_ADD_IO_SEG(0x00011800E0000210ull + (((offset) & 1) * 2048))
+#define CVMX_AGL_GMX_TX_BP \
+         CVMX_ADD_IO_SEG(0x00011800E00004D0ull)
+#define CVMX_AGL_GMX_TX_COL_ATTEMPT \
+         CVMX_ADD_IO_SEG(0x00011800E0000498ull)
+#define CVMX_AGL_GMX_TX_IFG \
+         CVMX_ADD_IO_SEG(0x00011800E0000488ull)
+#define CVMX_AGL_GMX_TX_INT_EN \
+         CVMX_ADD_IO_SEG(0x00011800E0000508ull)
+#define CVMX_AGL_GMX_TX_INT_REG \
+         CVMX_ADD_IO_SEG(0x00011800E0000500ull)
+#define CVMX_AGL_GMX_TX_JAM \
+         CVMX_ADD_IO_SEG(0x00011800E0000490ull)
+#define CVMX_AGL_GMX_TX_LFSR \
+         CVMX_ADD_IO_SEG(0x00011800E00004F8ull)
+#define CVMX_AGL_GMX_TX_OVR_BP \
+         CVMX_ADD_IO_SEG(0x00011800E00004C8ull)
+#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC \
+         CVMX_ADD_IO_SEG(0x00011800E00004A0ull)
+#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE \
+         CVMX_ADD_IO_SEG(0x00011800E00004A8ull)
+
+union cvmx_agl_gmx_bad_reg {
+        uint64_t u64;
+        struct cvmx_agl_gmx_bad_reg_s {
+                uint64_t reserved_38_63:26;
+                uint64_t txpsh1:1;
+                uint64_t txpop1:1;
+                uint64_t ovrflw1:1;
+                uint64_t txpsh:1;
+                uint64_t txpop:1;
+                uint64_t ovrflw:1;
+                uint64_t reserved_27_31:5;
+                uint64_t statovr:1;
+                uint64_t reserved_23_25:3;
+                uint64_t loststat:1;
+                uint64_t reserved_4_21:18;
+                uint64_t out_ovr:2;
+                uint64_t reserved_0_1:2;
+        } s;
+        struct cvmx_agl_gmx_bad_reg_s cn52xx;
+        struct cvmx_agl_gmx_bad_reg_s cn52xxp1;
+        struct cvmx_agl_gmx_bad_reg_cn56xx {
+                uint64_t reserved_35_63:29;
+                uint64_t txpsh:1;
+                uint64_t txpop:1;
+                uint64_t ovrflw:1;
+                uint64_t reserved_27_31:5;
+                uint64_t statovr:1;
+                uint64_t reserved_23_25:3;
+                uint64_t loststat:1;
+                uint64_t reserved_3_21:19;
+                uint64_t out_ovr:1;
+                uint64_t reserved_0_1:2;
+        } cn56xx;
+        struct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1;
+};
+
+union cvmx_agl_gmx_bist {
+        uint64_t u64;
+        struct cvmx_agl_gmx_bist_s {
+                uint64_t reserved_10_63:54;
+                uint64_t status:10;
+        } s;
+        struct cvmx_agl_gmx_bist_s cn52xx;
+        struct cvmx_agl_gmx_bist_s cn52xxp1;
+        struct cvmx_agl_gmx_bist_s cn56xx;
+        struct cvmx_agl_gmx_bist_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_drv_ctl {
+        uint64_t u64;
+        struct cvmx_agl_gmx_drv_ctl_s {
+                uint64_t reserved_49_63:15;
+                uint64_t byp_en1:1;
+                uint64_t reserved_45_47:3;
+                uint64_t pctl1:5;
+                uint64_t reserved_37_39:3;
+                uint64_t nctl1:5;
+                uint64_t reserved_17_31:15;
+                uint64_t byp_en:1;
+                uint64_t reserved_13_15:3;
+                uint64_t pctl:5;
+                uint64_t reserved_5_7:3;
+                uint64_t nctl:5;
+        } s;
+        struct cvmx_agl_gmx_drv_ctl_s cn52xx;
+        struct cvmx_agl_gmx_drv_ctl_s cn52xxp1;
+        struct cvmx_agl_gmx_drv_ctl_cn56xx {
+                uint64_t reserved_17_63:47;
+                uint64_t byp_en:1;
+                uint64_t reserved_13_15:3;
+                uint64_t pctl:5;
+                uint64_t reserved_5_7:3;
+                uint64_t nctl:5;
+        } cn56xx;
+        struct cvmx_agl_gmx_drv_ctl_cn56xx cn56xxp1;
+};
+
+union cvmx_agl_gmx_inf_mode {
+        uint64_t u64;
+        struct cvmx_agl_gmx_inf_mode_s {
+                uint64_t reserved_2_63:62;
+                uint64_t en:1;
+                uint64_t reserved_0_0:1;
+        } s;
+        struct cvmx_agl_gmx_inf_mode_s cn52xx;
+        struct cvmx_agl_gmx_inf_mode_s cn52xxp1;
+        struct cvmx_agl_gmx_inf_mode_s cn56xx;
+        struct cvmx_agl_gmx_inf_mode_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_prtx_cfg {
+        uint64_t u64;
+        struct cvmx_agl_gmx_prtx_cfg_s {
+                uint64_t reserved_6_63:58;
+                uint64_t tx_en:1;
+                uint64_t rx_en:1;
+                uint64_t slottime:1;
+                uint64_t duplex:1;
+                uint64_t speed:1;
+                uint64_t en:1;
+        } s;
+        struct cvmx_agl_gmx_prtx_cfg_s cn52xx;
+        struct cvmx_agl_gmx_prtx_cfg_s cn52xxp1;
+        struct cvmx_agl_gmx_prtx_cfg_s cn56xx;
+        struct cvmx_agl_gmx_prtx_cfg_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_adr_cam0 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_adr_cam0_s {
+                uint64_t adr:64;
+        } s;
+        struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xx;
+        struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx;
+        struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_adr_cam1 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_adr_cam1_s {
+                uint64_t adr:64;
+        } s;
+        struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xx;
+        struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx;
+        struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_adr_cam2 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_adr_cam2_s {
+                uint64_t adr:64;
+        } s;
+        struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xx;
+        struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx;
+        struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_adr_cam3 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_adr_cam3_s {
+                uint64_t adr:64;
+        } s;
+        struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xx;
+        struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx;
+        struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_adr_cam4 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_adr_cam4_s {
+                uint64_t adr:64;
+        } s;
+        struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xx;
+        struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx;
+        struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_adr_cam5 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_adr_cam5_s {
+                uint64_t adr:64;
+        } s;
+        struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xx;
+        struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx;
+        struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_adr_cam_en {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_adr_cam_en_s {
+                uint64_t reserved_8_63:56;
+                uint64_t en:8;
+        } s;
+        struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xx;
+        struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx;
+        struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_adr_ctl {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_adr_ctl_s {
+                uint64_t reserved_4_63:60;
+                uint64_t cam_mode:1;
+                uint64_t mcst:2;
+                uint64_t bcst:1;
+        } s;
+        struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xx;
+        struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx;
+        struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_decision {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_decision_s {
+                uint64_t reserved_5_63:59;
+                uint64_t cnt:5;
+        } s;
+        struct cvmx_agl_gmx_rxx_decision_s cn52xx;
+        struct cvmx_agl_gmx_rxx_decision_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_decision_s cn56xx;
+        struct cvmx_agl_gmx_rxx_decision_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_frm_chk {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_frm_chk_s {
+                uint64_t reserved_9_63:55;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t lenerr:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t maxerr:1;
+                uint64_t reserved_1_1:1;
+                uint64_t minerr:1;
+        } s;
+        struct cvmx_agl_gmx_rxx_frm_chk_s cn52xx;
+        struct cvmx_agl_gmx_rxx_frm_chk_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_frm_chk_s cn56xx;
+        struct cvmx_agl_gmx_rxx_frm_chk_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_frm_ctl {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_frm_ctl_s {
+                uint64_t reserved_10_63:54;
+                uint64_t pre_align:1;
+                uint64_t pad_len:1;
+                uint64_t vlan_len:1;
+                uint64_t pre_free:1;
+                uint64_t ctl_smac:1;
+                uint64_t ctl_mcst:1;
+                uint64_t ctl_bck:1;
+                uint64_t ctl_drp:1;
+                uint64_t pre_strp:1;
+                uint64_t pre_chk:1;
+        } s;
+        struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xx;
+        struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xx;
+        struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_frm_max {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_frm_max_s {
+                uint64_t reserved_16_63:48;
+                uint64_t len:16;
+        } s;
+        struct cvmx_agl_gmx_rxx_frm_max_s cn52xx;
+        struct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_frm_max_s cn56xx;
+        struct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_frm_min {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_frm_min_s {
+                uint64_t reserved_16_63:48;
+                uint64_t len:16;
+        } s;
+        struct cvmx_agl_gmx_rxx_frm_min_s cn52xx;
+        struct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_frm_min_s cn56xx;
+        struct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_ifg {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_ifg_s {
+                uint64_t reserved_4_63:60;
+                uint64_t ifg:4;
+        } s;
+        struct cvmx_agl_gmx_rxx_ifg_s cn52xx;
+        struct cvmx_agl_gmx_rxx_ifg_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_ifg_s cn56xx;
+        struct cvmx_agl_gmx_rxx_ifg_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_int_en {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_int_en_s {
+                uint64_t reserved_20_63:44;
+                uint64_t pause_drp:1;
+                uint64_t reserved_16_18:3;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t reserved_9_9:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t lenerr:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t maxerr:1;
+                uint64_t reserved_1_1:1;
+                uint64_t minerr:1;
+        } s;
+        struct cvmx_agl_gmx_rxx_int_en_s cn52xx;
+        struct cvmx_agl_gmx_rxx_int_en_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_int_en_s cn56xx;
+        struct cvmx_agl_gmx_rxx_int_en_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_int_reg {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_int_reg_s {
+                uint64_t reserved_20_63:44;
+                uint64_t pause_drp:1;
+                uint64_t reserved_16_18:3;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t reserved_9_9:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t lenerr:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t maxerr:1;
+                uint64_t reserved_1_1:1;
+                uint64_t minerr:1;
+        } s;
+        struct cvmx_agl_gmx_rxx_int_reg_s cn52xx;
+        struct cvmx_agl_gmx_rxx_int_reg_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_int_reg_s cn56xx;
+        struct cvmx_agl_gmx_rxx_int_reg_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_jabber {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_jabber_s {
+                uint64_t reserved_16_63:48;
+                uint64_t cnt:16;
+        } s;
+        struct cvmx_agl_gmx_rxx_jabber_s cn52xx;
+        struct cvmx_agl_gmx_rxx_jabber_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_jabber_s cn56xx;
+        struct cvmx_agl_gmx_rxx_jabber_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_pause_drop_time {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_pause_drop_time_s {
+                uint64_t reserved_16_63:48;
+                uint64_t status:16;
+        } s;
+        struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xx;
+        struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx;
+        struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_stats_ctl {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_stats_ctl_s {
+                uint64_t reserved_1_63:63;
+                uint64_t rd_clr:1;
+        } s;
+        struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xx;
+        struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx;
+        struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_stats_octs {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_stats_octs_s {
+                uint64_t reserved_48_63:16;
+                uint64_t cnt:48;
+        } s;
+        struct cvmx_agl_gmx_rxx_stats_octs_s cn52xx;
+        struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx;
+        struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_stats_octs_ctl {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s {
+                uint64_t reserved_48_63:16;
+                uint64_t cnt:48;
+        } s;
+        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xx;
+        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx;
+        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_stats_octs_dmac {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s {
+                uint64_t reserved_48_63:16;
+                uint64_t cnt:48;
+        } s;
+        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xx;
+        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx;
+        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_stats_octs_drp {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_stats_octs_drp_s {
+                uint64_t reserved_48_63:16;
+                uint64_t cnt:48;
+        } s;
+        struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xx;
+        struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx;
+        struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_stats_pkts {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_stats_pkts_s {
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xx;
+        struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx;
+        struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_stats_pkts_bad {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s {
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xx;
+        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx;
+        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_stats_pkts_ctl {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s {
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xx;
+        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx;
+        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_stats_pkts_dmac {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s {
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xx;
+        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx;
+        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_stats_pkts_drp {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s {
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xx;
+        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx;
+        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rxx_udd_skp {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_udd_skp_s {
+                uint64_t reserved_9_63:55;
+                uint64_t fcssel:1;
+                uint64_t reserved_7_7:1;
+                uint64_t len:7;
+        } s;
+        struct cvmx_agl_gmx_rxx_udd_skp_s cn52xx;
+        struct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1;
+        struct cvmx_agl_gmx_rxx_udd_skp_s cn56xx;
+        struct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rx_bp_dropx {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rx_bp_dropx_s {
+                uint64_t reserved_6_63:58;
+                uint64_t mark:6;
+        } s;
+        struct cvmx_agl_gmx_rx_bp_dropx_s cn52xx;
+        struct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1;
+        struct cvmx_agl_gmx_rx_bp_dropx_s cn56xx;
+        struct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rx_bp_offx {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rx_bp_offx_s {
+                uint64_t reserved_6_63:58;
+                uint64_t mark:6;
+        } s;
+        struct cvmx_agl_gmx_rx_bp_offx_s cn52xx;
+        struct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1;
+        struct cvmx_agl_gmx_rx_bp_offx_s cn56xx;
+        struct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rx_bp_onx {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rx_bp_onx_s {
+                uint64_t reserved_9_63:55;
+                uint64_t mark:9;
+        } s;
+        struct cvmx_agl_gmx_rx_bp_onx_s cn52xx;
+        struct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1;
+        struct cvmx_agl_gmx_rx_bp_onx_s cn56xx;
+        struct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_rx_prt_info {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rx_prt_info_s {
+                uint64_t reserved_18_63:46;
+                uint64_t drop:2;
+                uint64_t reserved_2_15:14;
+                uint64_t commit:2;
+        } s;
+        struct cvmx_agl_gmx_rx_prt_info_s cn52xx;
+        struct cvmx_agl_gmx_rx_prt_info_s cn52xxp1;
+        struct cvmx_agl_gmx_rx_prt_info_cn56xx {
+                uint64_t reserved_17_63:47;
+                uint64_t drop:1;
+                uint64_t reserved_1_15:15;
+                uint64_t commit:1;
+        } cn56xx;
+        struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1;
+};
+
+union cvmx_agl_gmx_rx_tx_status {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rx_tx_status_s {
+                uint64_t reserved_6_63:58;
+                uint64_t tx:2;
+                uint64_t reserved_2_3:2;
+                uint64_t rx:2;
+        } s;
+        struct cvmx_agl_gmx_rx_tx_status_s cn52xx;
+        struct cvmx_agl_gmx_rx_tx_status_s cn52xxp1;
+        struct cvmx_agl_gmx_rx_tx_status_cn56xx {
+                uint64_t reserved_5_63:59;
+                uint64_t tx:1;
+                uint64_t reserved_1_3:3;
+                uint64_t rx:1;
+        } cn56xx;
+        struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1;
+};
+
+union cvmx_agl_gmx_smacx {
+        uint64_t u64;
+        struct cvmx_agl_gmx_smacx_s {
+                uint64_t reserved_48_63:16;
+                uint64_t smac:48;
+        } s;
+        struct cvmx_agl_gmx_smacx_s cn52xx;
+        struct cvmx_agl_gmx_smacx_s cn52xxp1;
+        struct cvmx_agl_gmx_smacx_s cn56xx;
+        struct cvmx_agl_gmx_smacx_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_stat_bp {
+        uint64_t u64;
+        struct cvmx_agl_gmx_stat_bp_s {
+                uint64_t reserved_17_63:47;
+                uint64_t bp:1;
+                uint64_t cnt:16;
+        } s;
+        struct cvmx_agl_gmx_stat_bp_s cn52xx;
+        struct cvmx_agl_gmx_stat_bp_s cn52xxp1;
+        struct cvmx_agl_gmx_stat_bp_s cn56xx;
+        struct cvmx_agl_gmx_stat_bp_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_append {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_append_s {
+                uint64_t reserved_4_63:60;
+                uint64_t force_fcs:1;
+                uint64_t fcs:1;
+                uint64_t pad:1;
+                uint64_t preamble:1;
+        } s;
+        struct cvmx_agl_gmx_txx_append_s cn52xx;
+        struct cvmx_agl_gmx_txx_append_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_append_s cn56xx;
+        struct cvmx_agl_gmx_txx_append_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_ctl {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_ctl_s {
+                uint64_t reserved_2_63:62;
+                uint64_t xsdef_en:1;
+                uint64_t xscol_en:1;
+        } s;
+        struct cvmx_agl_gmx_txx_ctl_s cn52xx;
+        struct cvmx_agl_gmx_txx_ctl_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_ctl_s cn56xx;
+        struct cvmx_agl_gmx_txx_ctl_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_min_pkt {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_min_pkt_s {
+                uint64_t reserved_8_63:56;
+                uint64_t min_size:8;
+        } s;
+        struct cvmx_agl_gmx_txx_min_pkt_s cn52xx;
+        struct cvmx_agl_gmx_txx_min_pkt_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_min_pkt_s cn56xx;
+        struct cvmx_agl_gmx_txx_min_pkt_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_pause_pkt_interval {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_pause_pkt_interval_s {
+                uint64_t reserved_16_63:48;
+                uint64_t interval:16;
+        } s;
+        struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xx;
+        struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx;
+        struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_pause_pkt_time {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_pause_pkt_time_s {
+                uint64_t reserved_16_63:48;
+                uint64_t time:16;
+        } s;
+        struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xx;
+        struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx;
+        struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_pause_togo {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_pause_togo_s {
+                uint64_t reserved_16_63:48;
+                uint64_t time:16;
+        } s;
+        struct cvmx_agl_gmx_txx_pause_togo_s cn52xx;
+        struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_pause_togo_s cn56xx;
+        struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_pause_zero {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_pause_zero_s {
+                uint64_t reserved_1_63:63;
+                uint64_t send:1;
+        } s;
+        struct cvmx_agl_gmx_txx_pause_zero_s cn52xx;
+        struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_pause_zero_s cn56xx;
+        struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_soft_pause {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_soft_pause_s {
+                uint64_t reserved_16_63:48;
+                uint64_t time:16;
+        } s;
+        struct cvmx_agl_gmx_txx_soft_pause_s cn52xx;
+        struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_soft_pause_s cn56xx;
+        struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_stat0 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stat0_s {
+                uint64_t xsdef:32;
+                uint64_t xscol:32;
+        } s;
+        struct cvmx_agl_gmx_txx_stat0_s cn52xx;
+        struct cvmx_agl_gmx_txx_stat0_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_stat0_s cn56xx;
+        struct cvmx_agl_gmx_txx_stat0_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_stat1 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stat1_s {
+                uint64_t scol:32;
+                uint64_t mcol:32;
+        } s;
+        struct cvmx_agl_gmx_txx_stat1_s cn52xx;
+        struct cvmx_agl_gmx_txx_stat1_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_stat1_s cn56xx;
+        struct cvmx_agl_gmx_txx_stat1_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_stat2 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stat2_s {
+                uint64_t reserved_48_63:16;
+                uint64_t octs:48;
+        } s;
+        struct cvmx_agl_gmx_txx_stat2_s cn52xx;
+        struct cvmx_agl_gmx_txx_stat2_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_stat2_s cn56xx;
+        struct cvmx_agl_gmx_txx_stat2_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_stat3 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stat3_s {
+                uint64_t reserved_32_63:32;
+                uint64_t pkts:32;
+        } s;
+        struct cvmx_agl_gmx_txx_stat3_s cn52xx;
+        struct cvmx_agl_gmx_txx_stat3_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_stat3_s cn56xx;
+        struct cvmx_agl_gmx_txx_stat3_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_stat4 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stat4_s {
+                uint64_t hist1:32;
+                uint64_t hist0:32;
+        } s;
+        struct cvmx_agl_gmx_txx_stat4_s cn52xx;
+        struct cvmx_agl_gmx_txx_stat4_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_stat4_s cn56xx;
+        struct cvmx_agl_gmx_txx_stat4_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_stat5 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stat5_s {
+                uint64_t hist3:32;
+                uint64_t hist2:32;
+        } s;
+        struct cvmx_agl_gmx_txx_stat5_s cn52xx;
+        struct cvmx_agl_gmx_txx_stat5_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_stat5_s cn56xx;
+        struct cvmx_agl_gmx_txx_stat5_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_stat6 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stat6_s {
+                uint64_t hist5:32;
+                uint64_t hist4:32;
+        } s;
+        struct cvmx_agl_gmx_txx_stat6_s cn52xx;
+        struct cvmx_agl_gmx_txx_stat6_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_stat6_s cn56xx;
+        struct cvmx_agl_gmx_txx_stat6_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_stat7 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stat7_s {
+                uint64_t hist7:32;
+                uint64_t hist6:32;
+        } s;
+        struct cvmx_agl_gmx_txx_stat7_s cn52xx;
+        struct cvmx_agl_gmx_txx_stat7_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_stat7_s cn56xx;
+        struct cvmx_agl_gmx_txx_stat7_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_stat8 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stat8_s {
+                uint64_t mcst:32;
+                uint64_t bcst:32;
+        } s;
+        struct cvmx_agl_gmx_txx_stat8_s cn52xx;
+        struct cvmx_agl_gmx_txx_stat8_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_stat8_s cn56xx;
+        struct cvmx_agl_gmx_txx_stat8_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_stat9 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stat9_s {
+                uint64_t undflw:32;
+                uint64_t ctl:32;
+        } s;
+        struct cvmx_agl_gmx_txx_stat9_s cn52xx;
+        struct cvmx_agl_gmx_txx_stat9_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_stat9_s cn56xx;
+        struct cvmx_agl_gmx_txx_stat9_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_stats_ctl {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stats_ctl_s {
+                uint64_t reserved_1_63:63;
+                uint64_t rd_clr:1;
+        } s;
+        struct cvmx_agl_gmx_txx_stats_ctl_s cn52xx;
+        struct cvmx_agl_gmx_txx_stats_ctl_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_stats_ctl_s cn56xx;
+        struct cvmx_agl_gmx_txx_stats_ctl_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_txx_thresh {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_thresh_s {
+                uint64_t reserved_6_63:58;
+                uint64_t cnt:6;
+        } s;
+        struct cvmx_agl_gmx_txx_thresh_s cn52xx;
+        struct cvmx_agl_gmx_txx_thresh_s cn52xxp1;
+        struct cvmx_agl_gmx_txx_thresh_s cn56xx;
+        struct cvmx_agl_gmx_txx_thresh_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_tx_bp {
+        uint64_t u64;
+        struct cvmx_agl_gmx_tx_bp_s {
+                uint64_t reserved_2_63:62;
+                uint64_t bp:2;
+        } s;
+        struct cvmx_agl_gmx_tx_bp_s cn52xx;
+        struct cvmx_agl_gmx_tx_bp_s cn52xxp1;
+        struct cvmx_agl_gmx_tx_bp_cn56xx {
+                uint64_t reserved_1_63:63;
+                uint64_t bp:1;
+        } cn56xx;
+        struct cvmx_agl_gmx_tx_bp_cn56xx cn56xxp1;
+};
+
+union cvmx_agl_gmx_tx_col_attempt {
+        uint64_t u64;
+        struct cvmx_agl_gmx_tx_col_attempt_s {
+                uint64_t reserved_5_63:59;
+                uint64_t limit:5;
+        } s;
+        struct cvmx_agl_gmx_tx_col_attempt_s cn52xx;
+        struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1;
+        struct cvmx_agl_gmx_tx_col_attempt_s cn56xx;
+        struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_tx_ifg {
+        uint64_t u64;
+        struct cvmx_agl_gmx_tx_ifg_s {
+                uint64_t reserved_8_63:56;
+                uint64_t ifg2:4;
+                uint64_t ifg1:4;
+        } s;
+        struct cvmx_agl_gmx_tx_ifg_s cn52xx;
+        struct cvmx_agl_gmx_tx_ifg_s cn52xxp1;
+        struct cvmx_agl_gmx_tx_ifg_s cn56xx;
+        struct cvmx_agl_gmx_tx_ifg_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_tx_int_en {
+        uint64_t u64;
+        struct cvmx_agl_gmx_tx_int_en_s {
+                uint64_t reserved_18_63:46;
+                uint64_t late_col:2;
+                uint64_t reserved_14_15:2;
+                uint64_t xsdef:2;
+                uint64_t reserved_10_11:2;
+                uint64_t xscol:2;
+                uint64_t reserved_4_7:4;
+                uint64_t undflw:2;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+        } s;
+        struct cvmx_agl_gmx_tx_int_en_s cn52xx;
+        struct cvmx_agl_gmx_tx_int_en_s cn52xxp1;
+        struct cvmx_agl_gmx_tx_int_en_cn56xx {
+                uint64_t reserved_17_63:47;
+                uint64_t late_col:1;
+                uint64_t reserved_13_15:3;
+                uint64_t xsdef:1;
+                uint64_t reserved_9_11:3;
+                uint64_t xscol:1;
+                uint64_t reserved_3_7:5;
+                uint64_t undflw:1;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+        } cn56xx;
+        struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1;
+};
+
+union cvmx_agl_gmx_tx_int_reg {
+        uint64_t u64;
+        struct cvmx_agl_gmx_tx_int_reg_s {
+                uint64_t reserved_18_63:46;
+                uint64_t late_col:2;
+                uint64_t reserved_14_15:2;
+                uint64_t xsdef:2;
+                uint64_t reserved_10_11:2;
+                uint64_t xscol:2;
+                uint64_t reserved_4_7:4;
+                uint64_t undflw:2;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+        } s;
+        struct cvmx_agl_gmx_tx_int_reg_s cn52xx;
+        struct cvmx_agl_gmx_tx_int_reg_s cn52xxp1;
+        struct cvmx_agl_gmx_tx_int_reg_cn56xx {
+                uint64_t reserved_17_63:47;
+                uint64_t late_col:1;
+                uint64_t reserved_13_15:3;
+                uint64_t xsdef:1;
+                uint64_t reserved_9_11:3;
+                uint64_t xscol:1;
+                uint64_t reserved_3_7:5;
+                uint64_t undflw:1;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+        } cn56xx;
+        struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1;
+};
+
+union cvmx_agl_gmx_tx_jam {
+        uint64_t u64;
+        struct cvmx_agl_gmx_tx_jam_s {
+                uint64_t reserved_8_63:56;
+                uint64_t jam:8;
+        } s;
+        struct cvmx_agl_gmx_tx_jam_s cn52xx;
+        struct cvmx_agl_gmx_tx_jam_s cn52xxp1;
+        struct cvmx_agl_gmx_tx_jam_s cn56xx;
+        struct cvmx_agl_gmx_tx_jam_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_tx_lfsr {
+        uint64_t u64;
+        struct cvmx_agl_gmx_tx_lfsr_s {
+                uint64_t reserved_16_63:48;
+                uint64_t lfsr:16;
+        } s;
+        struct cvmx_agl_gmx_tx_lfsr_s cn52xx;
+        struct cvmx_agl_gmx_tx_lfsr_s cn52xxp1;
+        struct cvmx_agl_gmx_tx_lfsr_s cn56xx;
+        struct cvmx_agl_gmx_tx_lfsr_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_tx_ovr_bp {
+        uint64_t u64;
+        struct cvmx_agl_gmx_tx_ovr_bp_s {
+                uint64_t reserved_10_63:54;
+                uint64_t en:2;
+                uint64_t reserved_6_7:2;
+                uint64_t bp:2;
+                uint64_t reserved_2_3:2;
+                uint64_t ign_full:2;
+        } s;
+        struct cvmx_agl_gmx_tx_ovr_bp_s cn52xx;
+        struct cvmx_agl_gmx_tx_ovr_bp_s cn52xxp1;
+        struct cvmx_agl_gmx_tx_ovr_bp_cn56xx {
+                uint64_t reserved_9_63:55;
+                uint64_t en:1;
+                uint64_t reserved_5_7:3;
+                uint64_t bp:1;
+                uint64_t reserved_1_3:3;
+                uint64_t ign_full:1;
+        } cn56xx;
+        struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1;
+};
+
+union cvmx_agl_gmx_tx_pause_pkt_dmac {
+        uint64_t u64;
+        struct cvmx_agl_gmx_tx_pause_pkt_dmac_s {
+                uint64_t reserved_48_63:16;
+                uint64_t dmac:48;
+        } s;
+        struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xx;
+        struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1;
+        struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx;
+        struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1;
+};
+
+union cvmx_agl_gmx_tx_pause_pkt_type {
+        uint64_t u64;
+        struct cvmx_agl_gmx_tx_pause_pkt_type_s {
+                uint64_t reserved_16_63:48;
+                uint64_t type:16;
+        } s;
+        struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xx;
+        struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1;
+        struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx;
+        struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-mixx-defs.h b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
new file mode 100644
index 000000000000..dab6dca492f9
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
@@ -0,0 +1,248 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_MIXX_DEFS_H__
+#define __CVMX_MIXX_DEFS_H__
+
+#define CVMX_MIXX_BIST(offset) \
+         CVMX_ADD_IO_SEG(0x0001070000100078ull + (((offset) & 1) * 2048))
+#define CVMX_MIXX_CTL(offset) \
+         CVMX_ADD_IO_SEG(0x0001070000100020ull + (((offset) & 1) * 2048))
+#define CVMX_MIXX_INTENA(offset) \
+         CVMX_ADD_IO_SEG(0x0001070000100050ull + (((offset) & 1) * 2048))
+#define CVMX_MIXX_IRCNT(offset) \
+         CVMX_ADD_IO_SEG(0x0001070000100030ull + (((offset) & 1) * 2048))
+#define CVMX_MIXX_IRHWM(offset) \
+         CVMX_ADD_IO_SEG(0x0001070000100028ull + (((offset) & 1) * 2048))
+#define CVMX_MIXX_IRING1(offset) \
+         CVMX_ADD_IO_SEG(0x0001070000100010ull + (((offset) & 1) * 2048))
+#define CVMX_MIXX_IRING2(offset) \
+         CVMX_ADD_IO_SEG(0x0001070000100018ull + (((offset) & 1) * 2048))
+#define CVMX_MIXX_ISR(offset) \
+         CVMX_ADD_IO_SEG(0x0001070000100048ull + (((offset) & 1) * 2048))
+#define CVMX_MIXX_ORCNT(offset) \
+         CVMX_ADD_IO_SEG(0x0001070000100040ull + (((offset) & 1) * 2048))
+#define CVMX_MIXX_ORHWM(offset) \
+         CVMX_ADD_IO_SEG(0x0001070000100038ull + (((offset) & 1) * 2048))
+#define CVMX_MIXX_ORING1(offset) \
+         CVMX_ADD_IO_SEG(0x0001070000100000ull + (((offset) & 1) * 2048))
+#define CVMX_MIXX_ORING2(offset) \
+         CVMX_ADD_IO_SEG(0x0001070000100008ull + (((offset) & 1) * 2048))
+#define CVMX_MIXX_REMCNT(offset) \
+         CVMX_ADD_IO_SEG(0x0001070000100058ull + (((offset) & 1) * 2048))
+
+union cvmx_mixx_bist {
+        uint64_t u64;
+        struct cvmx_mixx_bist_s {
+                uint64_t reserved_4_63:60;
+                uint64_t mrqdat:1;
+                uint64_t ipfdat:1;
+                uint64_t irfdat:1;
+                uint64_t orfdat:1;
+        } s;
+        struct cvmx_mixx_bist_s cn52xx;
+        struct cvmx_mixx_bist_s cn52xxp1;
+        struct cvmx_mixx_bist_s cn56xx;
+        struct cvmx_mixx_bist_s cn56xxp1;
+};
+
+union cvmx_mixx_ctl {
+        uint64_t u64;
+        struct cvmx_mixx_ctl_s {
+                uint64_t reserved_8_63:56;
+                uint64_t crc_strip:1;
+                uint64_t busy:1;
+                uint64_t en:1;
+                uint64_t reset:1;
+                uint64_t lendian:1;
+                uint64_t nbtarb:1;
+                uint64_t mrq_hwm:2;
+        } s;
+        struct cvmx_mixx_ctl_s cn52xx;
+        struct cvmx_mixx_ctl_s cn52xxp1;
+        struct cvmx_mixx_ctl_s cn56xx;
+        struct cvmx_mixx_ctl_s cn56xxp1;
+};
+
+union cvmx_mixx_intena {
+        uint64_t u64;
+        struct cvmx_mixx_intena_s {
+                uint64_t reserved_7_63:57;
+                uint64_t orunena:1;
+                uint64_t irunena:1;
+                uint64_t data_drpena:1;
+                uint64_t ithena:1;
+                uint64_t othena:1;
+                uint64_t ivfena:1;
+                uint64_t ovfena:1;
+        } s;
+        struct cvmx_mixx_intena_s cn52xx;
+        struct cvmx_mixx_intena_s cn52xxp1;
+        struct cvmx_mixx_intena_s cn56xx;
+        struct cvmx_mixx_intena_s cn56xxp1;
+};
+
+union cvmx_mixx_ircnt {
+        uint64_t u64;
+        struct cvmx_mixx_ircnt_s {
+                uint64_t reserved_20_63:44;
+                uint64_t ircnt:20;
+        } s;
+        struct cvmx_mixx_ircnt_s cn52xx;
+        struct cvmx_mixx_ircnt_s cn52xxp1;
+        struct cvmx_mixx_ircnt_s cn56xx;
+        struct cvmx_mixx_ircnt_s cn56xxp1;
+};
+
+union cvmx_mixx_irhwm {
+        uint64_t u64;
+        struct cvmx_mixx_irhwm_s {
+                uint64_t reserved_40_63:24;
+                uint64_t ibplwm:20;
+                uint64_t irhwm:20;
+        } s;
+        struct cvmx_mixx_irhwm_s cn52xx;
+        struct cvmx_mixx_irhwm_s cn52xxp1;
+        struct cvmx_mixx_irhwm_s cn56xx;
+        struct cvmx_mixx_irhwm_s cn56xxp1;
+};
+
+union cvmx_mixx_iring1 {
+        uint64_t u64;
+        struct cvmx_mixx_iring1_s {
+                uint64_t reserved_60_63:4;
+                uint64_t isize:20;
+                uint64_t reserved_36_39:4;
+                uint64_t ibase:33;
+                uint64_t reserved_0_2:3;
+        } s;
+        struct cvmx_mixx_iring1_s cn52xx;
+        struct cvmx_mixx_iring1_s cn52xxp1;
+        struct cvmx_mixx_iring1_s cn56xx;
+        struct cvmx_mixx_iring1_s cn56xxp1;
+};
+
+union cvmx_mixx_iring2 {
+        uint64_t u64;
+        struct cvmx_mixx_iring2_s {
+                uint64_t reserved_52_63:12;
+                uint64_t itlptr:20;
+                uint64_t reserved_20_31:12;
+                uint64_t idbell:20;
+        } s;
+        struct cvmx_mixx_iring2_s cn52xx;
+        struct cvmx_mixx_iring2_s cn52xxp1;
+        struct cvmx_mixx_iring2_s cn56xx;
+        struct cvmx_mixx_iring2_s cn56xxp1;
+};
+
+union cvmx_mixx_isr {
+        uint64_t u64;
+        struct cvmx_mixx_isr_s {
+                uint64_t reserved_7_63:57;
+                uint64_t orun:1;
+                uint64_t irun:1;
+                uint64_t data_drp:1;
+                uint64_t irthresh:1;
+                uint64_t orthresh:1;
+                uint64_t idblovf:1;
+                uint64_t odblovf:1;
+        } s;
+        struct cvmx_mixx_isr_s cn52xx;
+        struct cvmx_mixx_isr_s cn52xxp1;
+        struct cvmx_mixx_isr_s cn56xx;
+        struct cvmx_mixx_isr_s cn56xxp1;
+};
+
+union cvmx_mixx_orcnt {
+        uint64_t u64;
+        struct cvmx_mixx_orcnt_s {
+                uint64_t reserved_20_63:44;
+                uint64_t orcnt:20;
+        } s;
+        struct cvmx_mixx_orcnt_s cn52xx;
+        struct cvmx_mixx_orcnt_s cn52xxp1;
+        struct cvmx_mixx_orcnt_s cn56xx;
+        struct cvmx_mixx_orcnt_s cn56xxp1;
+};
+
+union cvmx_mixx_orhwm {
+        uint64_t u64;
+        struct cvmx_mixx_orhwm_s {
+                uint64_t reserved_20_63:44;
+                uint64_t orhwm:20;
+        } s;
+        struct cvmx_mixx_orhwm_s cn52xx;
+        struct cvmx_mixx_orhwm_s cn52xxp1;
+        struct cvmx_mixx_orhwm_s cn56xx;
+        struct cvmx_mixx_orhwm_s cn56xxp1;
+};
+
+union cvmx_mixx_oring1 {
+        uint64_t u64;
+        struct cvmx_mixx_oring1_s {
+                uint64_t reserved_60_63:4;
+                uint64_t osize:20;
+                uint64_t reserved_36_39:4;
+                uint64_t obase:33;
+                uint64_t reserved_0_2:3;
+        } s;
+        struct cvmx_mixx_oring1_s cn52xx;
+        struct cvmx_mixx_oring1_s cn52xxp1;
+        struct cvmx_mixx_oring1_s cn56xx;
+        struct cvmx_mixx_oring1_s cn56xxp1;
+};
+
+union cvmx_mixx_oring2 {
+        uint64_t u64;
+        struct cvmx_mixx_oring2_s {
+                uint64_t reserved_52_63:12;
+                uint64_t otlptr:20;
+                uint64_t reserved_20_31:12;
+                uint64_t odbell:20;
+        } s;
+        struct cvmx_mixx_oring2_s cn52xx;
+        struct cvmx_mixx_oring2_s cn52xxp1;
+        struct cvmx_mixx_oring2_s cn56xx;
+        struct cvmx_mixx_oring2_s cn56xxp1;
+};
+
+union cvmx_mixx_remcnt {
+        uint64_t u64;
+        struct cvmx_mixx_remcnt_s {
+                uint64_t reserved_52_63:12;
+                uint64_t iremcnt:20;
+                uint64_t reserved_20_31:12;
+                uint64_t oremcnt:20;
+        } s;
+        struct cvmx_mixx_remcnt_s cn52xx;
+        struct cvmx_mixx_remcnt_s cn52xxp1;
+        struct cvmx_mixx_remcnt_s cn56xx;
+        struct cvmx_mixx_remcnt_s cn56xxp1;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-smix-defs.h b/arch/mips/include/asm/octeon/cvmx-smix-defs.h
new file mode 100644
index 000000000000..9ae45fcbe3e3
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-smix-defs.h
@@ -0,0 +1,178 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_SMIX_DEFS_H__
+#define __CVMX_SMIX_DEFS_H__
+
+#define CVMX_SMIX_CLK(offset) \
+         CVMX_ADD_IO_SEG(0x0001180000001818ull + (((offset) & 1) * 256))
+#define CVMX_SMIX_CMD(offset) \
+         CVMX_ADD_IO_SEG(0x0001180000001800ull + (((offset) & 1) * 256))
+#define CVMX_SMIX_EN(offset) \
+         CVMX_ADD_IO_SEG(0x0001180000001820ull + (((offset) & 1) * 256))
+#define CVMX_SMIX_RD_DAT(offset) \
+         CVMX_ADD_IO_SEG(0x0001180000001810ull + (((offset) & 1) * 256))
+#define CVMX_SMIX_WR_DAT(offset) \
+         CVMX_ADD_IO_SEG(0x0001180000001808ull + (((offset) & 1) * 256))
+
+union cvmx_smix_clk {
+        uint64_t u64;
+        struct cvmx_smix_clk_s {
+                uint64_t reserved_25_63:39;
+                uint64_t mode:1;
+                uint64_t reserved_21_23:3;
+                uint64_t sample_hi:5;
+                uint64_t sample_mode:1;
+                uint64_t reserved_14_14:1;
+                uint64_t clk_idle:1;
+                uint64_t preamble:1;
+                uint64_t sample:4;
+                uint64_t phase:8;
+        } s;
+        struct cvmx_smix_clk_cn30xx {
+                uint64_t reserved_21_63:43;
+                uint64_t sample_hi:5;
+                uint64_t reserved_14_15:2;
+                uint64_t clk_idle:1;
+                uint64_t preamble:1;
+                uint64_t sample:4;
+                uint64_t phase:8;
+        } cn30xx;
+        struct cvmx_smix_clk_cn30xx cn31xx;
+        struct cvmx_smix_clk_cn30xx cn38xx;
+        struct cvmx_smix_clk_cn30xx cn38xxp2;
+        struct cvmx_smix_clk_cn50xx {
+                uint64_t reserved_25_63:39;
+                uint64_t mode:1;
+                uint64_t reserved_21_23:3;
+                uint64_t sample_hi:5;
+                uint64_t reserved_14_15:2;
+                uint64_t clk_idle:1;
+                uint64_t preamble:1;
+                uint64_t sample:4;
+                uint64_t phase:8;
+        } cn50xx;
+        struct cvmx_smix_clk_s cn52xx;
+        struct cvmx_smix_clk_cn50xx cn52xxp1;
+        struct cvmx_smix_clk_s cn56xx;
+        struct cvmx_smix_clk_cn50xx cn56xxp1;
+        struct cvmx_smix_clk_cn30xx cn58xx;
+        struct cvmx_smix_clk_cn30xx cn58xxp1;
+};
+
+union cvmx_smix_cmd {
+        uint64_t u64;
+        struct cvmx_smix_cmd_s {
+                uint64_t reserved_18_63:46;
+                uint64_t phy_op:2;
+                uint64_t reserved_13_15:3;
+                uint64_t phy_adr:5;
+                uint64_t reserved_5_7:3;
+                uint64_t reg_adr:5;
+        } s;
+        struct cvmx_smix_cmd_cn30xx {
+                uint64_t reserved_17_63:47;
+                uint64_t phy_op:1;
+                uint64_t reserved_13_15:3;
+                uint64_t phy_adr:5;
+                uint64_t reserved_5_7:3;
+                uint64_t reg_adr:5;
+        } cn30xx;
+        struct cvmx_smix_cmd_cn30xx cn31xx;
+        struct cvmx_smix_cmd_cn30xx cn38xx;
+        struct cvmx_smix_cmd_cn30xx cn38xxp2;
+        struct cvmx_smix_cmd_s cn50xx;
+        struct cvmx_smix_cmd_s cn52xx;
+        struct cvmx_smix_cmd_s cn52xxp1;
+        struct cvmx_smix_cmd_s cn56xx;
+        struct cvmx_smix_cmd_s cn56xxp1;
+        struct cvmx_smix_cmd_cn30xx cn58xx;
+        struct cvmx_smix_cmd_cn30xx cn58xxp1;
+};
+
+union cvmx_smix_en {
+        uint64_t u64;
+        struct cvmx_smix_en_s {
+                uint64_t reserved_1_63:63;
+                uint64_t en:1;
+        } s;
+        struct cvmx_smix_en_s cn30xx;
+        struct cvmx_smix_en_s cn31xx;
+        struct cvmx_smix_en_s cn38xx;
+        struct cvmx_smix_en_s cn38xxp2;
+        struct cvmx_smix_en_s cn50xx;
+        struct cvmx_smix_en_s cn52xx;
+        struct cvmx_smix_en_s cn52xxp1;
+        struct cvmx_smix_en_s cn56xx;
+        struct cvmx_smix_en_s cn56xxp1;
+        struct cvmx_smix_en_s cn58xx;
+        struct cvmx_smix_en_s cn58xxp1;
+};
+
+union cvmx_smix_rd_dat {
+        uint64_t u64;
+        struct cvmx_smix_rd_dat_s {
+                uint64_t reserved_18_63:46;
+                uint64_t pending:1;
+                uint64_t val:1;
+                uint64_t dat:16;
+        } s;
+        struct cvmx_smix_rd_dat_s cn30xx;
+        struct cvmx_smix_rd_dat_s cn31xx;
+        struct cvmx_smix_rd_dat_s cn38xx;
+        struct cvmx_smix_rd_dat_s cn38xxp2;
+        struct cvmx_smix_rd_dat_s cn50xx;
+        struct cvmx_smix_rd_dat_s cn52xx;
+        struct cvmx_smix_rd_dat_s cn52xxp1;
+        struct cvmx_smix_rd_dat_s cn56xx;
+        struct cvmx_smix_rd_dat_s cn56xxp1;
+        struct cvmx_smix_rd_dat_s cn58xx;
+        struct cvmx_smix_rd_dat_s cn58xxp1;
+};
+
+union cvmx_smix_wr_dat {
+        uint64_t u64;
+        struct cvmx_smix_wr_dat_s {
+                uint64_t reserved_18_63:46;
+                uint64_t pending:1;
+                uint64_t val:1;
+                uint64_t dat:16;
+        } s;
+        struct cvmx_smix_wr_dat_s cn30xx;
+        struct cvmx_smix_wr_dat_s cn31xx;
+        struct cvmx_smix_wr_dat_s cn38xx;
+        struct cvmx_smix_wr_dat_s cn38xxp2;
+        struct cvmx_smix_wr_dat_s cn50xx;
+        struct cvmx_smix_wr_dat_s cn52xx;
+        struct cvmx_smix_wr_dat_s cn52xxp1;
+        struct cvmx_smix_wr_dat_s cn56xx;
+        struct cvmx_smix_wr_dat_s cn56xxp1;
+        struct cvmx_smix_wr_dat_s cn58xx;
+        struct cvmx_smix_wr_dat_s cn58xxp1;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index cac9b1a206fc..4d0a8c61fc3e 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -47,6 +47,7 @@ struct octeon_cop2_state;
 extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state);
 extern void octeon_crypto_disable(struct octeon_cop2_state *state,
                                   unsigned long flags);
+extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task);
 
 extern void octeon_init_cvmcount(void);
 
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index d6eb6134abec..1854336e56a2 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -390,6 +390,19 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma,
 #include <asm-generic/pgtable.h>
 
 /*
+ * uncached accelerated TLB map for video memory access
+ */
+#ifdef CONFIG_CPU_SUPPORTS_UNCACHED_ACCELERATED
+#define __HAVE_PHYS_MEM_ACCESS_PROT
+
+struct file;
+pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
+                unsigned long size, pgprot_t vma_prot);
+int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn,
+                unsigned long size, pgprot_t *vma_prot);
+#endif
+
+/*
  * We provide our own get_unmapped area to cope with the virtual aliasing
  * constraints placed on us by the cache architecture.
  */
diff --git a/arch/mips/include/asm/sgialib.h b/arch/mips/include/asm/sgialib.h
index bfce5c786f1c..63741ca1e422 100644
--- a/arch/mips/include/asm/sgialib.h
+++ b/arch/mips/include/asm/sgialib.h
@@ -85,8 +85,7 @@ extern void prom_identify_arch(void);
 extern PCHAR ArcGetEnvironmentVariable(PCHAR name);
 extern LONG ArcSetEnvironmentVariable(PCHAR name, PCHAR value);
 
-/* ARCS command line acquisition and parsing. */
-extern char *prom_getcmdline(void);
+/* ARCS command line parsing. */
 extern void prom_init_cmdline(void);
 
 /* Acquiring info about the current time, etc. */
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index db0fa7b5aeaf..3b6da3330e32 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -51,9 +51,6 @@
                 LONG_S  v1, PT_ACX(sp)
 #else
                 mfhi    v1
-                LONG_S  v1, PT_HI(sp)
-                mflo    v1
-                LONG_S  v1, PT_LO(sp)
 #endif
 #ifdef CONFIG_32BIT
                 LONG_S  $8, PT_R8(sp)
@@ -62,10 +59,17 @@
                 LONG_S  $10, PT_R10(sp)
                 LONG_S  $11, PT_R11(sp)
                 LONG_S  $12, PT_R12(sp)
+#ifndef CONFIG_CPU_HAS_SMARTMIPS
+                LONG_S  v1, PT_HI(sp)
+                mflo    v1
+#endif
                 LONG_S  $13, PT_R13(sp)
                 LONG_S  $14, PT_R14(sp)
                 LONG_S  $15, PT_R15(sp)
                 LONG_S  $24, PT_R24(sp)
+#ifndef CONFIG_CPU_HAS_SMARTMIPS
+                LONG_S  v1, PT_LO(sp)
+#endif
                 .endm
 
                 .macro  SAVE_STATIC
@@ -83,15 +87,19 @@
 #ifdef CONFIG_SMP
 #ifdef CONFIG_MIPS_MT_SMTC
 #define PTEBASE_SHIFT   19      /* TCBIND */
+#define CPU_ID_REG CP0_TCBIND
+#define CPU_ID_MFC0 mfc0
+#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT)
+#define PTEBASE_SHIFT   48      /* XCONTEXT */
+#define CPU_ID_REG CP0_XCONTEXT
+#define CPU_ID_MFC0 MFC0
 #else
 #define PTEBASE_SHIFT   23      /* CONTEXT */
+#define CPU_ID_REG CP0_CONTEXT
+#define CPU_ID_MFC0 MFC0
 #endif
                 .macro  get_saved_sp    /* SMP variation */
-#ifdef CONFIG_MIPS_MT_SMTC
-                mfc0    k0, CP0_TCBIND
-#else
-                MFC0    k0, CP0_CONTEXT
-#endif
+                CPU_ID_MFC0     k0, CPU_ID_REG
 #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
                 lui     k1, %hi(kernelsp)
 #else
@@ -107,11 +115,7 @@
                 .endm
 
                 .macro  set_saved_sp stackp temp temp2
-#ifdef CONFIG_MIPS_MT_SMTC
-                mfc0    \temp, CP0_TCBIND
-#else
-                MFC0    \temp, CP0_CONTEXT
-#endif
+                CPU_ID_MFC0     \temp, CPU_ID_REG
                 LONG_SRL        \temp, PTEBASE_SHIFT
                 LONG_S  \stackp, kernelsp(\temp)
                 .endm
@@ -166,7 +170,6 @@
                 LONG_S  $0, PT_R0(sp)
                 mfc0    v1, CP0_STATUS
                 LONG_S  $2, PT_R2(sp)
-                LONG_S  v1, PT_STATUS(sp)
 #ifdef CONFIG_MIPS_MT_SMTC
                 /*
                  * Ideally, these instructions would be shuffled in
@@ -178,20 +181,21 @@
                 LONG_S  v1, PT_TCSTATUS(sp)
 #endif /* CONFIG_MIPS_MT_SMTC */
                 LONG_S  $4, PT_R4(sp)
-                mfc0    v1, CP0_CAUSE
                 LONG_S  $5, PT_R5(sp)
-                LONG_S  v1, PT_CAUSE(sp)
+                LONG_S  v1, PT_STATUS(sp)
+                mfc0    v1, CP0_CAUSE
                 LONG_S  $6, PT_R6(sp)
-                MFC0    v1, CP0_EPC
                 LONG_S  $7, PT_R7(sp)
+                LONG_S  v1, PT_CAUSE(sp)
+                MFC0    v1, CP0_EPC
 #ifdef CONFIG_64BIT
                 LONG_S  $8, PT_R8(sp)
                 LONG_S  $9, PT_R9(sp)
 #endif
-                LONG_S  v1, PT_EPC(sp)
                 LONG_S  $25, PT_R25(sp)
                 LONG_S  $28, PT_R28(sp)
                 LONG_S  $31, PT_R31(sp)
+                LONG_S  v1, PT_EPC(sp)
                 ori     $28, sp, _THREAD_MASK
                 xori    $28, _THREAD_MASK
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index eecd2a9f155c..9326af5186fe 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -2,14 +2,17 @@
 # Makefile for the Linux/MIPS kernel.
 #
 
-CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS)
-
 extra-y         := head.o init_task.o vmlinux.lds
 
 obj-y           += cpu-probe.o branch.o entry.o genex.o irq.o process.o \
                    ptrace.o reset.o setup.o signal.o syscall.o \
                    time.o topology.o traps.o unaligned.o watch.o
 
+ifdef CONFIG_FUNCTION_TRACER
+CFLAGS_REMOVE_ftrace.o = -pg
+CFLAGS_REMOVE_early_printk.o = -pg
+endif
+
 obj-$(CONFIG_CEVT_BCM1480)      += cevt-bcm1480.o
 obj-$(CONFIG_CEVT_R4K_LIB)      += cevt-r4k.o
 obj-$(CONFIG_MIPS_MT_SMTC)      += cevt-smtc.o
@@ -19,6 +22,7 @@ obj-$(CONFIG_CEVT_SB1250)	+= cevt-sb1250.o
 obj-$(CONFIG_CEVT_TXX9)         += cevt-txx9.o
 obj-$(CONFIG_CSRC_BCM1480)      += csrc-bcm1480.o
 obj-$(CONFIG_CSRC_IOASIC)       += csrc-ioasic.o
+obj-$(CONFIG_CSRC_POWERTV)      += csrc-powertv.o
 obj-$(CONFIG_CSRC_R4K_LIB)      += csrc-r4k.o
 obj-$(CONFIG_CSRC_SB1250)       += csrc-sb1250.o
 obj-$(CONFIG_SYNC_R4K)          += sync-r4k.o
@@ -26,6 +30,8 @@ obj-$(CONFIG_SYNC_R4K)		+= sync-r4k.o
 obj-$(CONFIG_STACKTRACE)        += stacktrace.o
 obj-$(CONFIG_MODULES)           += mips_ksyms.o module.o
 
+obj-$(CONFIG_FUNCTION_TRACER)   += mcount.o ftrace.o
+
 obj-$(CONFIG_CPU_LOONGSON2)     += r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_MIPS32)        += r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_MIPS64)        += r4k_fpu.o r4k_switch.o
@@ -92,4 +98,8 @@ CFLAGS_cpu-bugs64.o	= $(shell if $(CC) $(KBUILD_CFLAGS) -Wa,-mdaddi -c -o /dev/n
 
 obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT)   += 8250-platform.o
 
+obj-$(CONFIG_MIPS_CPUFREQ)      += cpufreq/
+
 EXTRA_CFLAGS += -Werror
+
+CPPFLAGS_vmlinux.lds            := $(KBUILD_CFLAGS)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 7a51866068a4..80e202eca056 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -16,6 +16,7 @@
 #include <linux/ptrace.h>
 #include <linux/smp.h>
 #include <linux/stddef.h>
+#include <linux/module.h>
 
 #include <asm/bugs.h>
 #include <asm/cpu.h>
@@ -32,6 +33,7 @@
  * the CPU very much.
  */
 void (*cpu_wait)(void);
+EXPORT_SYMBOL(cpu_wait);
 
 static void r3081_wait(void)
 {
diff --git a/arch/mips/kernel/cpufreq/Kconfig b/arch/mips/kernel/cpufreq/Kconfig
new file mode 100644
index 000000000000..58c601eee6fd
--- /dev/null
+++ b/arch/mips/kernel/cpufreq/Kconfig
@@ -0,0 +1,41 @@
+#
+# CPU Frequency scaling
+#
+
+config MIPS_EXTERNAL_TIMER
+        bool
+
+config MIPS_CPUFREQ
+        bool
+        default y
+        depends on CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
+
+if MIPS_CPUFREQ
+
+menu "CPU Frequency scaling"
+
+source "drivers/cpufreq/Kconfig"
+
+if CPU_FREQ
+
+comment "CPUFreq processor drivers"
+
+config LOONGSON2_CPUFREQ
+        tristate "Loongson2 CPUFreq Driver"
+        select CPU_FREQ_TABLE
+        depends on MIPS_CPUFREQ
+        help
+          This option adds a CPUFreq driver for loongson processors which
+          support software configurable cpu frequency.
+
+          Loongson2F and it's successors support this feature.
+
+          For details, take a look at <file:Documentation/cpu-freq/>.
+
+          If in doubt, say N.
+
+endif   # CPU_FREQ
+
+endmenu
+
+endif   # MIPS_CPUFREQ
diff --git a/arch/mips/kernel/cpufreq/Makefile b/arch/mips/kernel/cpufreq/Makefile
new file mode 100644
index 000000000000..c3479a432efe
--- /dev/null
+++ b/arch/mips/kernel/cpufreq/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for the Linux/MIPS cpufreq.
+#
+
+obj-$(CONFIG_LOONGSON2_CPUFREQ) += loongson2_cpufreq.o loongson2_clock.o
diff --git a/arch/mips/kernel/cpufreq/loongson2_clock.c b/arch/mips/kernel/cpufreq/loongson2_clock.c
new file mode 100644
index 000000000000..d7ca256e33ef
--- /dev/null
+++ b/arch/mips/kernel/cpufreq/loongson2_clock.c
@@ -0,0 +1,166 @@
+/*
+ * Copyright (C) 2006 - 2008 Lemote Inc. & Insititute of Computing Technology
+ * Author: Yanhua, yanh@lemote.com
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/cpufreq.h>
+#include <linux/platform_device.h>
+
+#include <asm/clock.h>
+
+#include <loongson.h>
+
+static LIST_HEAD(clock_list);
+static DEFINE_SPINLOCK(clock_lock);
+static DEFINE_MUTEX(clock_list_sem);
+
+/* Minimum CLK support */
+enum {
+        DC_ZERO, DC_25PT = 2, DC_37PT, DC_50PT, DC_62PT, DC_75PT,
+        DC_87PT, DC_DISABLE, DC_RESV
+};
+
+struct cpufreq_frequency_table loongson2_clockmod_table[] = {
+        {DC_RESV, CPUFREQ_ENTRY_INVALID},
+        {DC_ZERO, CPUFREQ_ENTRY_INVALID},
+        {DC_25PT, 0},
+        {DC_37PT, 0},
+        {DC_50PT, 0},
+        {DC_62PT, 0},
+        {DC_75PT, 0},
+        {DC_87PT, 0},
+        {DC_DISABLE, 0},
+        {DC_RESV, CPUFREQ_TABLE_END},
+};
+EXPORT_SYMBOL_GPL(loongson2_clockmod_table);
+
+static struct clk cpu_clk = {
+        .name = "cpu_clk",
+        .flags = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
+        .rate = 800000000,
+};
+
+struct clk *clk_get(struct device *dev, const char *id)
+{
+        return &cpu_clk;
+}
+EXPORT_SYMBOL(clk_get);
+
+static void propagate_rate(struct clk *clk)
+{
+        struct clk *clkp;
+
+        list_for_each_entry(clkp, &clock_list, node) {
+                if (likely(clkp->parent != clk))
+                        continue;
+                if (likely(clkp->ops && clkp->ops->recalc))
+                        clkp->ops->recalc(clkp);
+                if (unlikely(clkp->flags & CLK_RATE_PROPAGATES))
+                        propagate_rate(clkp);
+        }
+}
+
+int clk_enable(struct clk *clk)
+{
+        return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+        return (unsigned long)clk->rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+void clk_put(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_put);
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        return clk_set_rate_ex(clk, rate, 0);
+}
+EXPORT_SYMBOL_GPL(clk_set_rate);
+
+int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id)
+{
+        int ret = 0;
+        int regval;
+        int i;
+
+        if (likely(clk->ops && clk->ops->set_rate)) {
+                unsigned long flags;
+
+                spin_lock_irqsave(&clock_lock, flags);
+                ret = clk->ops->set_rate(clk, rate, algo_id);
+                spin_unlock_irqrestore(&clock_lock, flags);
+        }
+
+        if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
+                propagate_rate(clk);
+
+        for (i = 0; loongson2_clockmod_table[i].frequency != CPUFREQ_TABLE_END;
+             i++) {
+                if (loongson2_clockmod_table[i].frequency ==
+                    CPUFREQ_ENTRY_INVALID)
+                        continue;
+                if (rate == loongson2_clockmod_table[i].frequency)
+                        break;
+        }
+        if (rate != loongson2_clockmod_table[i].frequency)
+                return -ENOTSUPP;
+
+        clk->rate = rate;
+
+        regval = LOONGSON_CHIPCFG0;
+        regval = (regval & ~0x7) | (loongson2_clockmod_table[i].index - 1);
+        LOONGSON_CHIPCFG0 = regval;
+
+        return ret;
+}
+EXPORT_SYMBOL_GPL(clk_set_rate_ex);
+
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+        if (likely(clk->ops && clk->ops->round_rate)) {
+                unsigned long flags, rounded;
+
+                spin_lock_irqsave(&clock_lock, flags);
+                rounded = clk->ops->round_rate(clk, rate);
+                spin_unlock_irqrestore(&clock_lock, flags);
+
+                return rounded;
+        }
+
+        return rate;
+}
+EXPORT_SYMBOL_GPL(clk_round_rate);
+
+/*
+ * This is the simple version of Loongson-2 wait, Maybe we need do this in
+ * interrupt disabled content
+ */
+
+DEFINE_SPINLOCK(loongson2_wait_lock);
+void loongson2_cpu_wait(void)
+{
+        u32 cpu_freq;
+        unsigned long flags;
+
+        spin_lock_irqsave(&loongson2_wait_lock, flags);
+        cpu_freq = LOONGSON_CHIPCFG0;
+        LOONGSON_CHIPCFG0 &= ~0x7;      /* Put CPU into wait mode */
+        LOONGSON_CHIPCFG0 = cpu_freq;   /* Restore CPU state */
+        spin_unlock_irqrestore(&loongson2_wait_lock, flags);
+}
+EXPORT_SYMBOL_GPL(loongson2_cpu_wait);
diff --git a/arch/mips/kernel/cpufreq/loongson2_cpufreq.c b/arch/mips/kernel/cpufreq/loongson2_cpufreq.c
new file mode 100644
index 000000000000..2f6a0b147ab8
--- /dev/null
+++ b/arch/mips/kernel/cpufreq/loongson2_cpufreq.c
@@ -0,0 +1,227 @@
+/*
+ * Cpufreq driver for the loongson-2 processors
+ *
+ * The 2E revision of loongson processor not support this feature.
+ *
+ * Copyright (C) 2006 - 2008 Lemote Inc. & Insititute of Computing Technology
+ * Author: Yanhua, yanh@lemote.com
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/cpufreq.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/sched.h>        /* set_cpus_allowed() */
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+
+#include <asm/clock.h>
+
+#include <loongson.h>
+
+static uint nowait;
+
+static struct clk *cpuclk;
+
+static void (*saved_cpu_wait) (void);
+
+static int loongson2_cpu_freq_notifier(struct notifier_block *nb,
+                                        unsigned long val, void *data);
+
+static struct notifier_block loongson2_cpufreq_notifier_block = {
+        .notifier_call = loongson2_cpu_freq_notifier
+};
+
+static int loongson2_cpu_freq_notifier(struct notifier_block *nb,
+                                        unsigned long val, void *data)
+{
+        if (val == CPUFREQ_POSTCHANGE)
+                current_cpu_data.udelay_val = loops_per_jiffy;
+
+        return 0;
+}
+
+static unsigned int loongson2_cpufreq_get(unsigned int cpu)
+{
+        return clk_get_rate(cpuclk);
+}
+
+/*
+ * Here we notify other drivers of the proposed change and the final change.
+ */
+static int loongson2_cpufreq_target(struct cpufreq_policy *policy,
+                                     unsigned int target_freq,
+                                     unsigned int relation)
+{
+        unsigned int cpu = policy->cpu;
+        unsigned int newstate = 0;
+        cpumask_t cpus_allowed;
+        struct cpufreq_freqs freqs;
+        unsigned int freq;
+
+        if (!cpu_online(cpu))
+                return -ENODEV;
+
+        cpus_allowed = current->cpus_allowed;
+        set_cpus_allowed(current, cpumask_of_cpu(cpu));
+
+        if (cpufreq_frequency_table_target
+            (policy, &loongson2_clockmod_table[0], target_freq, relation,
+             &newstate))
+                return -EINVAL;
+
+        freq =
+            ((cpu_clock_freq / 1000) *
+             loongson2_clockmod_table[newstate].index) / 8;
+        if (freq < policy->min || freq > policy->max)
+                return -EINVAL;
+
+        pr_debug("cpufreq: requested frequency %u Hz\n", target_freq * 1000);
+
+        freqs.cpu = cpu;
+        freqs.old = loongson2_cpufreq_get(cpu);
+        freqs.new = freq;
+        freqs.flags = 0;
+
+        if (freqs.new == freqs.old)
+                return 0;
+
+        /* notifiers */
+        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
+        set_cpus_allowed(current, cpus_allowed);
+
+        /* setting the cpu frequency */
+        clk_set_rate(cpuclk, freq);
+
+        /* notifiers */
+        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+
+        pr_debug("cpufreq: set frequency %u kHz\n", freq);
+
+        return 0;
+}
+
+static int loongson2_cpufreq_cpu_init(struct cpufreq_policy *policy)
+{
+        int i;
+
+        if (!cpu_online(policy->cpu))
+                return -ENODEV;
+
+        cpuclk = clk_get(NULL, "cpu_clk");
+        if (IS_ERR(cpuclk)) {
+                printk(KERN_ERR "cpufreq: couldn't get CPU clk\n");
+                return PTR_ERR(cpuclk);
+        }
+
+        cpuclk->rate = cpu_clock_freq / 1000;
+        if (!cpuclk->rate)
+                return -EINVAL;
+
+        /* clock table init */
+        for (i = 2;
+             (loongson2_clockmod_table[i].frequency != CPUFREQ_TABLE_END);
+             i++)
+                loongson2_clockmod_table[i].frequency = (cpuclk->rate * i) / 8;
+
+        policy->cur = loongson2_cpufreq_get(policy->cpu);
+
+        cpufreq_frequency_table_get_attr(&loongson2_clockmod_table[0],
+                                         policy->cpu);
+
+        return cpufreq_frequency_table_cpuinfo(policy,
+                                            &loongson2_clockmod_table[0]);
+}
+
+static int loongson2_cpufreq_verify(struct cpufreq_policy *policy)
+{
+        return cpufreq_frequency_table_verify(policy,
+                                              &loongson2_clockmod_table[0]);
+}
+
+static int loongson2_cpufreq_exit(struct cpufreq_policy *policy)
+{
+        clk_put(cpuclk);
+        return 0;
+}
+
+static struct freq_attr *loongson2_table_attr[] = {
+        &cpufreq_freq_attr_scaling_available_freqs,
+        NULL,
+};
+
+static struct cpufreq_driver loongson2_cpufreq_driver = {
+        .owner = THIS_MODULE,
+        .name = "loongson2",
+        .init = loongson2_cpufreq_cpu_init,
+        .verify = loongson2_cpufreq_verify,
+        .target = loongson2_cpufreq_target,
+        .get = loongson2_cpufreq_get,
+        .exit = loongson2_cpufreq_exit,
+        .attr = loongson2_table_attr,
+};
+
+static struct platform_device_id platform_device_ids[] = {
+        {
+                .name = "loongson2_cpufreq",
+        },
+        {}
+};
+
+MODULE_DEVICE_TABLE(platform, platform_device_ids);
+
+static struct platform_driver platform_driver = {
+        .driver = {
+                .name = "loongson2_cpufreq",
+                .owner = THIS_MODULE,
+        },
+        .id_table = platform_device_ids,
+};
+
+static int __init cpufreq_init(void)
+{
+        int ret;
+
+        /* Register platform stuff */
+        ret = platform_driver_register(&platform_driver);
+        if (ret)
+                return ret;
+
+        pr_info("cpufreq: Loongson-2F CPU frequency driver.\n");
+
+        cpufreq_register_notifier(&loongson2_cpufreq_notifier_block,
+                                  CPUFREQ_TRANSITION_NOTIFIER);
+
+        ret = cpufreq_register_driver(&loongson2_cpufreq_driver);
+
+        if (!ret && !nowait) {
+                saved_cpu_wait = cpu_wait;
+                cpu_wait = loongson2_cpu_wait;
+        }
+
+        return ret;
+}
+
+static void __exit cpufreq_exit(void)
+{
+        if (!nowait && saved_cpu_wait)
+                cpu_wait = saved_cpu_wait;
+        cpufreq_unregister_driver(&loongson2_cpufreq_driver);
+        cpufreq_unregister_notifier(&loongson2_cpufreq_notifier_block,
+                                    CPUFREQ_TRANSITION_NOTIFIER);
+
+        platform_driver_unregister(&platform_driver);
+}
+
+module_init(cpufreq_init);
+module_exit(cpufreq_exit);
+
+module_param(nowait, uint, 0644);
+MODULE_PARM_DESC(nowait, "Disable Loongson-2F specific wait");
+
+MODULE_AUTHOR("Yanhua <yanh@lemote.com>");
+MODULE_DESCRIPTION("cpufreq driver for Loongson2F");
+MODULE_LICENSE("GPL");
diff --git a/arch/mips/kernel/csrc-powertv.c b/arch/mips/kernel/csrc-powertv.c
new file mode 100644
index 000000000000..a27c16c8690e
--- /dev/null
+++ b/arch/mips/kernel/csrc-powertv.c
@@ -0,0 +1,180 @@
+/*
+ * Copyright (C) 2008 Scientific-Atlanta, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+/*
+ * The file comes from kernel/csrc-r4k.c
+ */
+#include <linux/clocksource.h>
+#include <linux/init.h>
+
+#include <asm/time.h>                   /* Not included in linux/time.h */
+
+#include <asm/mach-powertv/asic_regs.h>
+#include "powertv-clock.h"
+
+/* MIPS PLL Register Definitions */
+#define PLL_GET_M(x)            (((x) >> 8) & 0x000000FF)
+#define PLL_GET_N(x)            (((x) >> 16) & 0x000000FF)
+#define PLL_GET_P(x)            (((x) >> 24) & 0x00000007)
+
+/*
+ * returns:  Clock frequency in kHz
+ */
+unsigned int __init mips_get_pll_freq(void)
+{
+        unsigned int pll_reg, m, n, p;
+        unsigned int fin = 54000; /* Base frequency in kHz */
+        unsigned int fout;
+
+        /* Read PLL register setting */
+        pll_reg = asic_read(mips_pll_setup);
+        m = PLL_GET_M(pll_reg);
+        n = PLL_GET_N(pll_reg);
+        p = PLL_GET_P(pll_reg);
+        pr_info("MIPS PLL Register:0x%x  M=%d  N=%d  P=%d\n", pll_reg, m, n, p);
+
+        /* Calculate clock frequency = (2 * N * 54MHz) / (M * (2**P)) */
+        fout = ((2 * n * fin) / (m * (0x01 << p)));
+
+        pr_info("MIPS Clock Freq=%d kHz\n", fout);
+
+        return fout;
+}
+
+static cycle_t c0_hpt_read(struct clocksource *cs)
+{
+        return read_c0_count();
+}
+
+static struct clocksource clocksource_mips = {
+        .name           = "powertv-counter",
+        .read           = c0_hpt_read,
+        .mask           = CLOCKSOURCE_MASK(32),
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static void __init powertv_c0_hpt_clocksource_init(void)
+{
+        unsigned int pll_freq = mips_get_pll_freq();
+
+        pr_info("CPU frequency %d.%02d MHz\n", pll_freq / 1000,
+                (pll_freq % 1000) * 100 / 1000);
+
+        mips_hpt_frequency = pll_freq / 2 * 1000;
+
+        clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
+
+        clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
+
+        clocksource_register(&clocksource_mips);
+}
+
+/**
+ * struct tim_c - free running counter
+ * @hi: High 16 bits of the counter
+ * @lo: Low 32 bits of the counter
+ *
+ * Lays out the structure of the free running counter in memory. This counter
+ * increments at a rate of 27 MHz/8 on all platforms.
+ */
+struct tim_c {
+        unsigned int hi;
+        unsigned int lo;
+};
+
+static struct tim_c *tim_c;
+
+static cycle_t tim_c_read(struct clocksource *cs)
+{
+        unsigned int hi;
+        unsigned int next_hi;
+        unsigned int lo;
+
+        hi = readl(&tim_c->hi);
+
+        for (;;) {
+                lo = readl(&tim_c->lo);
+                next_hi = readl(&tim_c->hi);
+                if (next_hi == hi)
+                        break;
+                hi = next_hi;
+        }
+
+pr_crit("%s: read %llx\n", __func__, ((u64) hi << 32) | lo);
+        return ((u64) hi << 32) | lo;
+}
+
+#define TIM_C_SIZE              48              /* # bits in the timer */
+
+static struct clocksource clocksource_tim_c = {
+        .name           = "powertv-tim_c",
+        .read           = tim_c_read,
+        .mask           = CLOCKSOURCE_MASK(TIM_C_SIZE),
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+/**
+ * powertv_tim_c_clocksource_init - set up a clock source for the TIM_C clock
+ *
+ * The hard part here is coming up with a constant k and shift s such that
+ * the 48-bit TIM_C value multiplied by k doesn't overflow and that value,
+ * when shifted right by s, yields the corresponding number of nanoseconds.
+ * We know that TIM_C counts at 27 MHz/8, so each cycle corresponds to
+ * 1 / (27,000,000/8) seconds. Multiply that by a billion and you get the
+ * number of nanoseconds. Since the TIM_C value has 48 bits and the math is
+ * done in 64 bits, avoiding an overflow means that k must be less than
+ * 64 - 48 = 16 bits.
+ */
+static void __init powertv_tim_c_clocksource_init(void)
+{
+        int                     prescale;
+        unsigned long           dividend;
+        unsigned long           k;
+        int                     s;
+        const int               max_k_bits = (64 - 48) - 1;
+        const unsigned long     billion = 1000000000;
+        const unsigned long     counts_per_second = 27000000 / 8;
+
+        prescale = BITS_PER_LONG - ilog2(billion) - 1;
+        dividend = billion << prescale;
+        k = dividend / counts_per_second;
+        s = ilog2(k) - max_k_bits;
+
+        if (s < 0)
+                s = prescale;
+
+        else {
+                k >>= s;
+                s += prescale;
+        }
+
+        clocksource_tim_c.mult = k;
+        clocksource_tim_c.shift = s;
+        clocksource_tim_c.rating = 200;
+
+        clocksource_register(&clocksource_tim_c);
+        tim_c = (struct tim_c *) asic_reg_addr(tim_ch);
+}
+
+/**
+ powertv_clocksource_init - initialize all clocksources
+ */
+void __init powertv_clocksource_init(void)
+{
+        powertv_c0_hpt_clocksource_init();
+        powertv_tim_c_clocksource_init();
+}
diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c
new file mode 100644
index 000000000000..68b067040d8b
--- /dev/null
+++ b/arch/mips/kernel/ftrace.c
@@ -0,0 +1,275 @@
+/*
+ * Code for replacing ftrace calls with jumps.
+ *
+ * Copyright (C) 2007-2008 Steven Rostedt <srostedt@redhat.com>
+ * Copyright (C) 2009 DSLab, Lanzhou University, China
+ * Author: Wu Zhangjin <wuzj@lemote.com>
+ *
+ * Thanks goes to Steven Rostedt for writing the original x86 version.
+ */
+
+#include <linux/uaccess.h>
+#include <linux/init.h>
+#include <linux/ftrace.h>
+
+#include <asm/cacheflush.h>
+#include <asm/asm.h>
+#include <asm/asm-offsets.h>
+
+#ifdef CONFIG_DYNAMIC_FTRACE
+
+#define JAL 0x0c000000          /* jump & link: ip --> ra, jump to target */
+#define ADDR_MASK 0x03ffffff    /*  op_code|addr : 31...26|25 ....0 */
+#define jump_insn_encode(op_code, addr) \
+        ((unsigned int)((op_code) | (((addr) >> 2) & ADDR_MASK)))
+
+static unsigned int ftrace_nop = 0x00000000;
+
+static int ftrace_modify_code(unsigned long ip, unsigned int new_code)
+{
+        int faulted;
+
+        /* *(unsigned int *)ip = new_code; */
+        safe_store_code(new_code, ip, faulted);
+
+        if (unlikely(faulted))
+                return -EFAULT;
+
+        flush_icache_range(ip, ip + 8);
+
+        return 0;
+}
+
+static int lui_v1;
+static int jal_mcount;
+
+int ftrace_make_nop(struct module *mod,
+                    struct dyn_ftrace *rec, unsigned long addr)
+{
+        unsigned int new;
+        int faulted;
+        unsigned long ip = rec->ip;
+
+        /* We have compiled module with -mlong-calls, but compiled the kernel
+         * without it, we need to cope with them respectively. */
+        if (ip & 0x40000000) {
+                /* record it for ftrace_make_call */
+                if (lui_v1 == 0) {
+                        /* lui_v1 = *(unsigned int *)ip; */
+                        safe_load_code(lui_v1, ip, faulted);
+
+                        if (unlikely(faulted))
+                                return -EFAULT;
+                }
+
+                /* lui v1, hi_16bit_of_mcount        --> b 1f (0x10000004)
+                 * addiu v1, v1, low_16bit_of_mcount
+                 * move at, ra
+                 * jalr v1
+                 * nop
+                 *                                   1f: (ip + 12)
+                 */
+                new = 0x10000004;
+        } else {
+                /* record/calculate it for ftrace_make_call */
+                if (jal_mcount == 0) {
+                        /* We can record it directly like this:
+                         *     jal_mcount = *(unsigned int *)ip;
+                         * Herein, jump over the first two nop instructions */
+                        jal_mcount = jump_insn_encode(JAL, (MCOUNT_ADDR + 8));
+                }
+
+                /* move at, ra
+                 * jalr v1              --> nop
+                 */
+                new = ftrace_nop;
+        }
+        return ftrace_modify_code(ip, new);
+}
+
+static int modified;    /* initialized as 0 by default */
+
+int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
+{
+        unsigned int new;
+        unsigned long ip = rec->ip;
+
+        /* We just need to remove the "b ftrace_stub" at the fist time! */
+        if (modified == 0) {
+                modified = 1;
+                ftrace_modify_code(addr, ftrace_nop);
+        }
+        /* ip, module: 0xc0000000, kernel: 0x80000000 */
+        new = (ip & 0x40000000) ? lui_v1 : jal_mcount;
+
+        return ftrace_modify_code(ip, new);
+}
+
+#define FTRACE_CALL_IP ((unsigned long)(&ftrace_call))
+
+int ftrace_update_ftrace_func(ftrace_func_t func)
+{
+        unsigned int new;
+
+        new = jump_insn_encode(JAL, (unsigned long)func);
+
+        return ftrace_modify_code(FTRACE_CALL_IP, new);
+}
+
+int __init ftrace_dyn_arch_init(void *data)
+{
+        /* The return code is retured via data */
+        *(unsigned long *)data = 0;
+
+        return 0;
+}
+#endif                          /* CONFIG_DYNAMIC_FTRACE */
+
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+
+#ifdef CONFIG_DYNAMIC_FTRACE
+
+extern void ftrace_graph_call(void);
+#define JMP     0x08000000      /* jump to target directly */
+#define CALL_FTRACE_GRAPH_CALLER \
+        jump_insn_encode(JMP, (unsigned long)(&ftrace_graph_caller))
+#define FTRACE_GRAPH_CALL_IP    ((unsigned long)(&ftrace_graph_call))
+
+int ftrace_enable_ftrace_graph_caller(void)
+{
+        return ftrace_modify_code(FTRACE_GRAPH_CALL_IP,
+                                  CALL_FTRACE_GRAPH_CALLER);
+}
+
+int ftrace_disable_ftrace_graph_caller(void)
+{
+        return ftrace_modify_code(FTRACE_GRAPH_CALL_IP, ftrace_nop);
+}
+
+#endif                          /* !CONFIG_DYNAMIC_FTRACE */
+
+#ifndef KBUILD_MCOUNT_RA_ADDRESS
+#define S_RA_SP (0xafbf << 16)  /* s{d,w} ra, offset(sp) */
+#define S_R_SP  (0xafb0 << 16)  /* s{d,w} R, offset(sp) */
+#define OFFSET_MASK     0xffff  /* stack offset range: 0 ~ PT_SIZE */
+
+unsigned long ftrace_get_parent_addr(unsigned long self_addr,
+                                     unsigned long parent,
+                                     unsigned long parent_addr,
+                                     unsigned long fp)
+{
+        unsigned long sp, ip, ra;
+        unsigned int code;
+        int faulted;
+
+        /* in module or kernel? */
+        if (self_addr & 0x40000000) {
+                /* module: move to the instruction "lui v1, HI_16BIT_OF_MCOUNT" */
+                ip = self_addr - 20;
+        } else {
+                /* kernel: move to the instruction "move ra, at" */
+                ip = self_addr - 12;
+        }
+
+        /* search the text until finding the non-store instruction or "s{d,w}
+         * ra, offset(sp)" instruction */
+        do {
+                ip -= 4;
+
+                /* get the code at "ip": code = *(unsigned int *)ip; */
+                safe_load_code(code, ip, faulted);
+
+                if (unlikely(faulted))
+                        return 0;
+
+                /* If we hit the non-store instruction before finding where the
+                 * ra is stored, then this is a leaf function and it does not
+                 * store the ra on the stack. */
+                if ((code & S_R_SP) != S_R_SP)
+                        return parent_addr;
+
+        } while (((code & S_RA_SP) != S_RA_SP));
+
+        sp = fp + (code & OFFSET_MASK);
+
+        /* ra = *(unsigned long *)sp; */
+        safe_load_stack(ra, sp, faulted);
+        if (unlikely(faulted))
+                return 0;
+
+        if (ra == parent)
+                return sp;
+        return 0;
+}
+
+#endif
+
+/*
+ * Hook the return address and push it in the stack of return addrs
+ * in current thread info.
+ */
+void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr,
+                           unsigned long fp)
+{
+        unsigned long old;
+        struct ftrace_graph_ent trace;
+        unsigned long return_hooker = (unsigned long)
+            &return_to_handler;
+        int faulted;
+
+        if (unlikely(atomic_read(&current->tracing_graph_pause)))
+                return;
+
+        /* "parent" is the stack address saved the return address of the caller
+         * of _mcount.
+         *
+         * if the gcc < 4.5, a leaf function does not save the return address
+         * in the stack address, so, we "emulate" one in _mcount's stack space,
+         * and hijack it directly, but for a non-leaf function, it save the
+         * return address to the its own stack space, we can not hijack it
+         * directly, but need to find the real stack address,
+         * ftrace_get_parent_addr() does it!
+         *
+         * if gcc>= 4.5, with the new -mmcount-ra-address option, for a
+         * non-leaf function, the location of the return address will be saved
+         * to $12 for us, and for a leaf function, only put a zero into $12. we
+         * do it in ftrace_graph_caller of mcount.S.
+         */
+
+        /* old = *parent; */
+        safe_load_stack(old, parent, faulted);
+        if (unlikely(faulted))
+                goto out;
+#ifndef KBUILD_MCOUNT_RA_ADDRESS
+        parent = (unsigned long *)ftrace_get_parent_addr(self_addr, old,
+                                                         (unsigned long)parent,
+                                                         fp);
+        /* If fails when getting the stack address of the non-leaf function's
+         * ra, stop function graph tracer and return */
+        if (parent == 0)
+                goto out;
+#endif
+        /* *parent = return_hooker; */
+        safe_store_stack(return_hooker, parent, faulted);
+        if (unlikely(faulted))
+                goto out;
+
+        if (ftrace_push_return_trace(old, self_addr, &trace.depth, fp) ==
+            -EBUSY) {
+                *parent = old;
+                return;
+        }
+
+        trace.func = self_addr;
+
+        /* Only trace if the calling function expects to */
+        if (!ftrace_graph_entry(&trace)) {
+                current->curr_ret_stack--;
+                *parent = old;
+        }
+        return;
+out:
+        ftrace_graph_stop();
+        WARN_ON(1);
+}
+#endif                          /* CONFIG_FUNCTION_GRAPH_TRACER */
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index 8b0b4181219f..981f86c26168 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -22,6 +22,7 @@
 #include <linux/seq_file.h>
 #include <linux/kallsyms.h>
 #include <linux/kgdb.h>
+#include <linux/ftrace.h>
 
 #include <asm/atomic.h>
 #include <asm/system.h>
@@ -150,3 +151,32 @@ void __init init_IRQ(void)
                 kgdb_early_setup = 1;
 #endif
 }
+
+/*
+ * do_IRQ handles all normal device IRQ's (the special
+ * SMP cross-CPU interrupts have their own specific
+ * handlers).
+ */
+void __irq_entry do_IRQ(unsigned int irq)
+{
+        irq_enter();
+        __DO_IRQ_SMTC_HOOK(irq);
+        generic_handle_irq(irq);
+        irq_exit();
+}
+
+#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
+/*
+ * To avoid inefficient and in some cases pathological re-checking of
+ * IRQ affinity, we have this variant that skips the affinity check.
+ */
+
+void __irq_entry do_IRQ_no_affinity(unsigned int irq)
+{
+        irq_enter();
+        __NO_AFFINITY_IRQ_SMTC_HOOK(irq);
+        generic_handle_irq(irq);
+        irq_exit();
+}
+
+#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
diff --git a/arch/mips/kernel/mcount.S b/arch/mips/kernel/mcount.S
new file mode 100644
index 000000000000..0a9cfdb271dd
--- /dev/null
+++ b/arch/mips/kernel/mcount.S
@@ -0,0 +1,189 @@
+/*
+ * MIPS specific _mcount support
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive for
+ * more details.
+ *
+ * Copyright (C) 2009 Lemote Inc. & DSLab, Lanzhou University, China
+ * Author: Wu Zhangjin <wuzj@lemote.com>
+ */
+
+#include <asm/regdef.h>
+#include <asm/stackframe.h>
+#include <asm/ftrace.h>
+
+        .text
+        .set noreorder
+        .set noat
+
+        .macro MCOUNT_SAVE_REGS
+        PTR_SUBU        sp, PT_SIZE
+        PTR_S   ra, PT_R31(sp)
+        PTR_S   AT, PT_R1(sp)
+        PTR_S   a0, PT_R4(sp)
+        PTR_S   a1, PT_R5(sp)
+        PTR_S   a2, PT_R6(sp)
+        PTR_S   a3, PT_R7(sp)
+#ifdef CONFIG_64BIT
+        PTR_S   a4, PT_R8(sp)
+        PTR_S   a5, PT_R9(sp)
+        PTR_S   a6, PT_R10(sp)
+        PTR_S   a7, PT_R11(sp)
+#endif
+        .endm
+
+        .macro MCOUNT_RESTORE_REGS
+        PTR_L   ra, PT_R31(sp)
+        PTR_L   AT, PT_R1(sp)
+        PTR_L   a0, PT_R4(sp)
+        PTR_L   a1, PT_R5(sp)
+        PTR_L   a2, PT_R6(sp)
+        PTR_L   a3, PT_R7(sp)
+#ifdef CONFIG_64BIT
+        PTR_L   a4, PT_R8(sp)
+        PTR_L   a5, PT_R9(sp)
+        PTR_L   a6, PT_R10(sp)
+        PTR_L   a7, PT_R11(sp)
+#endif
+#ifdef CONFIG_64BIT
+        PTR_ADDIU       sp, PT_SIZE
+#else
+        PTR_ADDIU       sp, (PT_SIZE + 8)
+#endif
+.endm
+
+        .macro RETURN_BACK
+        jr ra
+         move ra, AT
+        .endm
+
+#ifdef CONFIG_DYNAMIC_FTRACE
+
+NESTED(ftrace_caller, PT_SIZE, ra)
+        .globl _mcount
+_mcount:
+        b       ftrace_stub
+         nop
+        lw      t1, function_trace_stop
+        bnez    t1, ftrace_stub
+         nop
+
+        MCOUNT_SAVE_REGS
+#ifdef KBUILD_MCOUNT_RA_ADDRESS
+        PTR_S   t0, PT_R12(sp)  /* t0 saved the location of the return address(at) by -mmcount-ra-address */
+#endif
+
+        move    a0, ra          /* arg1: next ip, selfaddr */
+        .globl ftrace_call
+ftrace_call:
+        nop     /* a placeholder for the call to a real tracing function */
+         move   a1, AT          /* arg2: the caller's next ip, parent */
+
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+        .globl ftrace_graph_call
+ftrace_graph_call:
+        nop
+         nop
+#endif
+
+        MCOUNT_RESTORE_REGS
+        .globl ftrace_stub
+ftrace_stub:
+        RETURN_BACK
+        END(ftrace_caller)
+
+#else   /* ! CONFIG_DYNAMIC_FTRACE */
+
+NESTED(_mcount, PT_SIZE, ra)
+        lw      t1, function_trace_stop
+        bnez    t1, ftrace_stub
+         nop
+        PTR_LA  t1, ftrace_stub
+        PTR_L   t2, ftrace_trace_function /* Prepare t2 for (1) */
+        bne     t1, t2, static_trace
+         nop
+
+#ifdef  CONFIG_FUNCTION_GRAPH_TRACER
+        PTR_L   t3, ftrace_graph_return
+        bne     t1, t3, ftrace_graph_caller
+         nop
+        PTR_LA  t1, ftrace_graph_entry_stub
+        PTR_L   t3, ftrace_graph_entry
+        bne     t1, t3, ftrace_graph_caller
+         nop
+#endif
+        b       ftrace_stub
+         nop
+
+static_trace:
+        MCOUNT_SAVE_REGS
+
+        move    a0, ra          /* arg1: next ip, selfaddr */
+        jalr    t2              /* (1) call *ftrace_trace_function */
+         move   a1, AT          /* arg2: the caller's next ip, parent */
+
+        MCOUNT_RESTORE_REGS
+        .globl ftrace_stub
+ftrace_stub:
+        RETURN_BACK
+        END(_mcount)
+
+#endif  /* ! CONFIG_DYNAMIC_FTRACE */
+
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+
+NESTED(ftrace_graph_caller, PT_SIZE, ra)
+#ifdef CONFIG_DYNAMIC_FTRACE
+        PTR_L   a1, PT_R31(sp)  /* load the original ra from the stack */
+#ifdef KBUILD_MCOUNT_RA_ADDRESS
+        PTR_L   t0, PT_R12(sp)  /* load the original t0 from the stack */
+#endif
+#else
+        MCOUNT_SAVE_REGS
+        move    a1, ra          /* arg2: next ip, selfaddr */
+#endif
+
+#ifdef KBUILD_MCOUNT_RA_ADDRESS
+        bnez    t0, 1f          /* non-leaf func: t0 saved the location of the return address */
+         nop
+        PTR_LA  t0, PT_R1(sp)   /* leaf func: get the location of at(old ra) from our own stack */
+1:      move    a0, t0          /* arg1: the location of the return address */
+#else
+        PTR_LA  a0, PT_R1(sp)   /* arg1: &AT -> a0 */
+#endif
+        jal     prepare_ftrace_return
+#ifdef CONFIG_FRAME_POINTER
+         move   a2, fp          /* arg3: frame pointer */
+#else
+#ifdef CONFIG_64BIT
+         PTR_LA a2, PT_SIZE(sp)
+#else
+         PTR_LA a2, (PT_SIZE+8)(sp)
+#endif
+#endif
+
+        MCOUNT_RESTORE_REGS
+        RETURN_BACK
+        END(ftrace_graph_caller)
+
+        .align  2
+        .globl  return_to_handler
+return_to_handler:
+        PTR_SUBU        sp, PT_SIZE
+        PTR_S   v0, PT_R2(sp)
+
+        jal     ftrace_return_to_handler
+         PTR_S  v1, PT_R3(sp)
+
+        /* restore the real parent address: v0 -> ra */
+        move    ra, v0
+
+        PTR_L   v0, PT_R2(sp)
+        PTR_L   v1, PT_R3(sp)
+        jr      ra
+         PTR_ADDIU      sp, PT_SIZE
+#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
+
+        .set at
+        .set reorder
diff --git a/arch/mips/kernel/mips_ksyms.c b/arch/mips/kernel/mips_ksyms.c
index 225755d0c1f6..1d04807874db 100644
--- a/arch/mips/kernel/mips_ksyms.c
+++ b/arch/mips/kernel/mips_ksyms.c
@@ -13,6 +13,7 @@
 #include <asm/checksum.h>
 #include <asm/pgtable.h>
 #include <asm/uaccess.h>
+#include <asm/ftrace.h>
 
 extern void *__bzero(void *__s, size_t __count);
 extern long __strncpy_from_user_nocheck_asm(char *__to,
@@ -51,3 +52,7 @@ EXPORT_SYMBOL(csum_partial_copy_nocheck);
 EXPORT_SYMBOL(__csum_partial_copy_user);
 
 EXPORT_SYMBOL(invalid_pte_table);
+#ifdef CONFIG_FUNCTION_TRACER
+/* _mcount is defined in arch/mips/kernel/mcount.S */
+EXPORT_SYMBOL(_mcount);
+#endif
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 2b290d70083e..f9513f9e61d3 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -58,8 +58,12 @@ EXPORT_SYMBOL(mips_machtype);
 
 struct boot_mem_map boot_mem_map;
 
-static char command_line[CL_SIZE];
-       char arcs_cmdline[CL_SIZE]=CONFIG_CMDLINE;
+static char __initdata command_line[COMMAND_LINE_SIZE];
+char __initdata arcs_cmdline[COMMAND_LINE_SIZE];
+
+#ifdef CONFIG_CMDLINE_BOOL
+static char __initdata builtin_cmdline[COMMAND_LINE_SIZE] = CONFIG_CMDLINE;
+#endif
 
 /*
  * mips_io_port_base is the begin of the address space to which x86 style
@@ -166,26 +170,8 @@ static unsigned long __init init_initrd(void)
          * already set up initrd_start and initrd_end. In these cases
          * perfom sanity checks and use them if all looks good.
          */
-        if (!initrd_start || initrd_end <= initrd_start) {
-#ifdef CONFIG_PROBE_INITRD_HEADER
-                u32 *initrd_header;
-
-                /*
-                 * See if initrd has been added to the kernel image by
-                 * arch/mips/boot/addinitrd.c. In that case a header is
-                 * prepended to initrd and is made up by 8 bytes. The first
-                 * word is a magic number and the second one is the size of
-                 * initrd.  Initrd start must be page aligned in any cases.
-                 */
-                initrd_header = __va(PAGE_ALIGN(__pa_symbol(&_end) + 8)) - 8;
-                if (initrd_header[0] != 0x494E5244)
-                        goto disable;
-                initrd_start = (unsigned long)(initrd_header + 2);
-                initrd_end = initrd_start + initrd_header[1];
-#else
+        if (!initrd_start || initrd_end <= initrd_start)
                 goto disable;
-#endif
-        }
 
         if (initrd_start & ~PAGE_MASK) {
                 pr_err("initrd start must be page aligned\n");
@@ -476,8 +462,20 @@ static void __init arch_mem_init(char **cmdline_p)
         pr_info("Determined physical RAM map:\n");
         print_memory_map();
 
-        strlcpy(command_line, arcs_cmdline, sizeof(command_line));
-        strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
+#ifdef CONFIG_CMDLINE_BOOL
+#ifdef CONFIG_CMDLINE_OVERRIDE
+        strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE);
+#else
+        if (builtin_cmdline[0]) {
+                strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
+                strlcat(arcs_cmdline, builtin_cmdline, COMMAND_LINE_SIZE);
+        }
+        strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
+#endif
+#else
+        strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
+#endif
+        strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
 
         *cmdline_p = command_line;
 
diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index 6254041b942f..d0c68b5d717b 100644
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -35,6 +35,15 @@
 
 #include "signal-common.h"
 
+static int (*save_fp_context)(struct sigcontext __user *sc);
+static int (*restore_fp_context)(struct sigcontext __user *sc);
+
+extern asmlinkage int _save_fp_context(struct sigcontext __user *sc);
+extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc);
+
+extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc);
+extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc);
+
 /*
  * Horribly complicated - with the bloody RM9000 workarounds enabled
  * the signal trampolines is moving to the end of the structure so we can
@@ -709,3 +718,40 @@ asmlinkage void do_notify_resume(struct pt_regs *regs, void *unused,
                         key_replace_session_keyring();
         }
 }
+
+#ifdef CONFIG_SMP
+static int smp_save_fp_context(struct sigcontext __user *sc)
+{
+        return raw_cpu_has_fpu
+               ? _save_fp_context(sc)
+               : fpu_emulator_save_context(sc);
+}
+
+static int smp_restore_fp_context(struct sigcontext __user *sc)
+{
+        return raw_cpu_has_fpu
+               ? _restore_fp_context(sc)
+               : fpu_emulator_restore_context(sc);
+}
+#endif
+
+static int signal_setup(void)
+{
+#ifdef CONFIG_SMP
+        /* For now just do the cpu_has_fpu check when the functions are invoked */
+        save_fp_context = smp_save_fp_context;
+        restore_fp_context = smp_restore_fp_context;
+#else
+        if (cpu_has_fpu) {
+                save_fp_context = _save_fp_context;
+                restore_fp_context = _restore_fp_context;
+        } else {
+                save_fp_context = fpu_emulator_save_context;
+                restore_fp_context = fpu_emulator_restore_context;
+        }
+#endif
+
+        return 0;
+}
+
+arch_initcall(signal_setup);
diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c
index 2e74075ac0ca..03abaf048f09 100644
--- a/arch/mips/kernel/signal32.c
+++ b/arch/mips/kernel/signal32.c
@@ -35,6 +35,15 @@
 
 #include "signal-common.h"
 
+static int (*save_fp_context32)(struct sigcontext32 __user *sc);
+static int (*restore_fp_context32)(struct sigcontext32 __user *sc);
+
+extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc);
+extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc);
+
+extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc);
+extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc);
+
 /*
  * Including <asm/unistd.h> would give use the 64-bit syscall numbers ...
  */
@@ -828,3 +837,18 @@ SYSCALL_DEFINE5(32_waitid, int, which, compat_pid_t, pid,
         info.si_code |= __SI_CHLD;
         return copy_siginfo_to_user32(uinfo, &info);
 }
+
+static int signal32_init(void)
+{
+        if (cpu_has_fpu) {
+                save_fp_context32 = _save_fp_context32;
+                restore_fp_context32 = _restore_fp_context32;
+        } else {
+                save_fp_context32 = fpu_emulator_save_context32;
+                restore_fp_context32 = fpu_emulator_restore_context32;
+        }
+
+        return 0;
+}
+
+arch_initcall(signal32_init);
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index e72e6844d134..6cdca1956b77 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -32,6 +32,7 @@
 #include <linux/cpumask.h>
 #include <linux/cpu.h>
 #include <linux/err.h>
+#include <linux/ftrace.h>
 
 #include <asm/atomic.h>
 #include <asm/cpu.h>
@@ -130,7 +131,7 @@ asmlinkage __cpuinit void start_secondary(void)
 /*
  * Call into both interrupt handlers, as we share the IPI for them
  */
-void smp_call_function_interrupt(void)
+void __irq_entry smp_call_function_interrupt(void)
 {
         irq_enter();
         generic_smp_call_function_single_interrupt();
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index a38e3ee95515..23499b5bd9c3 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -25,6 +25,7 @@
 #include <linux/interrupt.h>
 #include <linux/kernel_stat.h>
 #include <linux/module.h>
+#include <linux/ftrace.h>
 
 #include <asm/cpu.h>
 #include <asm/processor.h>
@@ -939,23 +940,29 @@ static void ipi_call_interrupt(void)
 
 DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device);
 
-void ipi_decode(struct smtc_ipi *pipi)
+static void __irq_entry smtc_clock_tick_interrupt(void)
 {
         unsigned int cpu = smp_processor_id();
         struct clock_event_device *cd;
+        int irq = MIPS_CPU_IRQ_BASE + 1;
+
+        irq_enter();
+        kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq));
+        cd = &per_cpu(mips_clockevent_device, cpu);
+        cd->event_handler(cd);
+        irq_exit();
+}
+
+void ipi_decode(struct smtc_ipi *pipi)
+{
         void *arg_copy = pipi->arg;
         int type_copy = pipi->type;
-        int irq = MIPS_CPU_IRQ_BASE + 1;
 
         smtc_ipi_nq(&freeIPIq, pipi);
 
         switch (type_copy) {
         case SMTC_CLOCK_TICK:
-                irq_enter();
-                kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq));
-                cd = &per_cpu(mips_clockevent_device, cpu);
-                cd->event_handler(cd);
-                irq_exit();
+                smtc_clock_tick_interrupt();
                 break;
 
         case LINUX_SMP_IPI:
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 0a18b4c62afb..308e43460864 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -25,10 +25,12 @@
 #include <linux/ptrace.h>
 #include <linux/kgdb.h>
 #include <linux/kdebug.h>
+#include <linux/notifier.h>
 
 #include <asm/bootinfo.h>
 #include <asm/branch.h>
 #include <asm/break.h>
+#include <asm/cop2.h>
 #include <asm/cpu.h>
 #include <asm/dsp.h>
 #include <asm/fpu.h>
@@ -79,10 +81,6 @@ extern asmlinkage void handle_reserved(void);
 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
         struct mips_fpu_struct *ctx, int has_fpu);
 
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
-extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task);
-#endif
-
 void (*board_be_init)(void);
 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
 void (*board_nmi_handler_setup)(void);
@@ -857,6 +855,44 @@ static void mt_ase_fp_affinity(void)
 #endif /* CONFIG_MIPS_MT_FPAFF */
 }
 
+/*
+ * No lock; only written during early bootup by CPU 0.
+ */
+static RAW_NOTIFIER_HEAD(cu2_chain);
+
+int __ref register_cu2_notifier(struct notifier_block *nb)
+{
+        return raw_notifier_chain_register(&cu2_chain, nb);
+}
+
+int cu2_notifier_call_chain(unsigned long val, void *v)
+{
+        return raw_notifier_call_chain(&cu2_chain, val, v);
+}
+
+static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
+        void *data)
+{
+        struct pt_regs *regs = data;
+
+        switch (action) {
+        default:
+                die_if_kernel("Unhandled kernel unaligned access or invalid "
+                              "instruction", regs);
+                /* Fall through  */
+
+        case CU2_EXCEPTION:
+                force_sig(SIGILL, current);
+        }
+
+        return NOTIFY_OK;
+}
+
+static struct notifier_block default_cu2_notifier = {
+        .notifier_call  = default_cu2_call,
+        .priority       = 0x80000000,           /* Run last  */
+};
+
 asmlinkage void do_cpu(struct pt_regs *regs)
 {
         unsigned int __user *epc;
@@ -920,17 +956,9 @@ asmlinkage void do_cpu(struct pt_regs *regs)
                 return;
 
         case 2:
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
-                prefetch(&current->thread.cp2);
-                local_irq_save(flags);
-                KSTK_STATUS(current) |= ST0_CU2;
-                status = read_c0_status();
-                write_c0_status(status | ST0_CU2);
-                octeon_cop2_restore(&(current->thread.cp2));
-                write_c0_status(status & ~ST0_CU2);
-                local_irq_restore(flags);
-                return;
-#endif
+                raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
+                break;
+
         case 3:
                 break;
         }
@@ -1367,77 +1395,6 @@ void *set_vi_handler(int n, vi_handler_t addr)
         return set_vi_srs_handler(n, addr, 0);
 }
 
-/*
- * This is used by native signal handling
- */
-asmlinkage int (*save_fp_context)(struct sigcontext __user *sc);
-asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc);
-
-extern asmlinkage int _save_fp_context(struct sigcontext __user *sc);
-extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc);
-
-extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc);
-extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc);
-
-#ifdef CONFIG_SMP
-static int smp_save_fp_context(struct sigcontext __user *sc)
-{
-        return raw_cpu_has_fpu
-               ? _save_fp_context(sc)
-               : fpu_emulator_save_context(sc);
-}
-
-static int smp_restore_fp_context(struct sigcontext __user *sc)
-{
-        return raw_cpu_has_fpu
-               ? _restore_fp_context(sc)
-               : fpu_emulator_restore_context(sc);
-}
-#endif
-
-static inline void signal_init(void)
-{
-#ifdef CONFIG_SMP
-        /* For now just do the cpu_has_fpu check when the functions are invoked */
-        save_fp_context = smp_save_fp_context;
-        restore_fp_context = smp_restore_fp_context;
-#else
-        if (cpu_has_fpu) {
-                save_fp_context = _save_fp_context;
-                restore_fp_context = _restore_fp_context;
-        } else {
-                save_fp_context = fpu_emulator_save_context;
-                restore_fp_context = fpu_emulator_restore_context;
-        }
-#endif
-}
-
-#ifdef CONFIG_MIPS32_COMPAT
-
-/*
- * This is used by 32-bit signal stuff on the 64-bit kernel
- */
-asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc);
-asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc);
-
-extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc);
-extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc);
-
-extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc);
-extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc);
-
-static inline void signal32_init(void)
-{
-        if (cpu_has_fpu) {
-                save_fp_context32 = _save_fp_context32;
-                restore_fp_context32 = _restore_fp_context32;
-        } else {
-                save_fp_context32 = fpu_emulator_save_context32;
-                restore_fp_context32 = fpu_emulator_restore_context32;
-        }
-}
-#endif
-
 extern void cpu_cache_init(void);
 extern void tlb_init(void);
 extern void flush_tlb_handlers(void);
@@ -1751,13 +1708,10 @@ void __init trap_init(void)
         else
                 memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80);
 
-        signal_init();
-#ifdef CONFIG_MIPS32_COMPAT
-        signal32_init();
-#endif
-
         local_flush_icache_range(ebase, ebase + 0x400);
         flush_tlb_handlers();
 
         sort_extable(__start___dbe_table, __stop___dbe_table);
+
+        register_cu2_notifier(&default_cu2_notifier);
 }
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index 67bd626942ab..69b039ca8d83 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -81,6 +81,7 @@
 #include <asm/asm.h>
 #include <asm/branch.h>
 #include <asm/byteorder.h>
+#include <asm/cop2.h>
 #include <asm/inst.h>
 #include <asm/uaccess.h>
 #include <asm/system.h>
@@ -451,17 +452,27 @@ static void emulate_load_store_insn(struct pt_regs *regs,
                  */
                 goto sigbus;
 
+        /*
+         * COP2 is available to implementor for application specific use.
+         * It's up to applications to register a notifier chain and do
+         * whatever they have to do, including possible sending of signals.
+         */
         case lwc2_op:
+                cu2_notifier_call_chain(CU2_LWC2_OP, regs);
+                break;
+
         case ldc2_op:
+                cu2_notifier_call_chain(CU2_LDC2_OP, regs);
+                break;
+
         case swc2_op:
+                cu2_notifier_call_chain(CU2_SWC2_OP, regs);
+                break;
+
         case sdc2_op:
-                /*
-                 * These are the coprocessor 2 load/stores.  The current
-                 * implementations don't use cp2 and cp2 should always be
-                 * disabled in c0_status.  So send SIGILL.
-                 * (No longer true: The Sony Praystation uses cp2 for
-                 * 3D matrix operations.  Dunno if that thingy has a MMU ...)
-                 */
+                cu2_notifier_call_chain(CU2_SDC2_OP, regs);
+                break;
+
         default:
                 /*
                  * Pheeee...  We encountered an yet unknown instruction or
diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
index 162b29954baa..f25df73db923 100644
--- a/arch/mips/kernel/vmlinux.lds.S
+++ b/arch/mips/kernel/vmlinux.lds.S
@@ -46,6 +46,7 @@ SECTIONS
                 SCHED_TEXT
                 LOCK_TEXT
                 KPROBES_TEXT
+                IRQENTRY_TEXT
                 *(.text.*)
                 *(.fixup)
                 *(.gnu.warning)
diff --git a/arch/mips/lasat/picvue_proc.c b/arch/mips/lasat/picvue_proc.c
index 0bb6037afba3..8e388da1926f 100644
--- a/arch/mips/lasat/picvue_proc.c
+++ b/arch/mips/lasat/picvue_proc.c
@@ -4,12 +4,14 @@
  * Brian Murphy <brian.murphy@eicon.com>
  *
  */
+#include <linux/bug.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/errno.h>
 
 #include <linux/proc_fs.h>
+#include <linux/seq_file.h>
 #include <linux/interrupt.h>
 
 #include <linux/timer.h>
@@ -38,12 +40,9 @@ static void pvc_display(unsigned long data)
 
 static DECLARE_TASKLET(pvc_display_tasklet, &pvc_display, 0);
 
-static int pvc_proc_read_line(char *page, char **start,
-                             off_t off, int count,
-                             int *eof, void *data)
+static int pvc_line_proc_show(struct seq_file *m, void *v)
 {
-        char *origpage = page;
-        int lineno = *(int *)data;
+        int lineno = *(int *)m->private;
 
         if (lineno < 0 || lineno > PVC_NLINES) {
                 printk(KERN_WARNING "proc_read_line: invalid lineno %d\n", lineno);
@@ -51,45 +50,66 @@ static int pvc_proc_read_line(char *page, char **start,
         }
 
         mutex_lock(&pvc_mutex);
-        page += sprintf(page, "%s\n", pvc_lines[lineno]);
+        seq_printf(m, "%s\n", pvc_lines[lineno]);
         mutex_unlock(&pvc_mutex);
 
-        return page - origpage;
+        return 0;
 }
 
-static int pvc_proc_write_line(struct file *file, const char *buffer,
-                           unsigned long count, void *data)
+static int pvc_line_proc_open(struct inode *inode, struct file *file)
 {
-        int origcount = count;
-        int lineno = *(int *)data;
+        return single_open(file, pvc_line_proc_show, PDE(inode)->data);
+}
 
-        if (lineno < 0 || lineno > PVC_NLINES) {
-                printk(KERN_WARNING "proc_write_line: invalid lineno %d\n",
-                       lineno);
-                return origcount;
-        }
+static ssize_t pvc_line_proc_write(struct file *file, const char __user *buf,
+                                   size_t count, loff_t *pos)
+{
+        int lineno = *(int *)PDE(file->f_path.dentry->d_inode)->data;
+        char kbuf[PVC_LINELEN];
+        size_t len;
+
+        BUG_ON(lineno < 0 || lineno > PVC_NLINES);
 
-        if (count > PVC_LINELEN)
-                count = PVC_LINELEN;
+        len = min(count, sizeof(kbuf) - 1);
+        if (copy_from_user(kbuf, buf, len))
+                return -EFAULT;
+        kbuf[len] = '\0';
 
-        if (buffer[count-1] == '\n')
-                count--;
+        if (len > 0 && kbuf[len - 1] == '\n')
+                len--;
 
         mutex_lock(&pvc_mutex);
-        strncpy(pvc_lines[lineno], buffer, count);
-        pvc_lines[lineno][count] = '\0';
+        strncpy(pvc_lines[lineno], kbuf, len);
+        pvc_lines[lineno][len] = '\0';
         mutex_unlock(&pvc_mutex);
 
         tasklet_schedule(&pvc_display_tasklet);
 
-        return origcount;
+        return count;
 }
 
-static int pvc_proc_write_scroll(struct file *file, const char *buffer,
-                           unsigned long count, void *data)
+static const struct file_operations pvc_line_proc_fops = {
+        .owner          = THIS_MODULE,
+        .open           = pvc_line_proc_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+        .write          = pvc_line_proc_write,
+};
+
+static ssize_t pvc_scroll_proc_write(struct file *file, const char __user *buf,
+                                     size_t count, loff_t *pos)
 {
-        int origcount = count;
-        int cmd = simple_strtol(buffer, NULL, 10);
+        char kbuf[42];
+        size_t len;
+        int cmd;
+
+        len = min(count, sizeof(kbuf) - 1);
+        if (copy_from_user(kbuf, buf, len))
+                return -EFAULT;
+        kbuf[len] = '\0';
+
+        cmd = simple_strtol(kbuf, NULL, 10);
 
         mutex_lock(&pvc_mutex);
         if (scroll_interval != 0)
@@ -110,22 +130,31 @@ static int pvc_proc_write_scroll(struct file *file, const char *buffer,
         }
         mutex_unlock(&pvc_mutex);
 
-        return origcount;
+        return count;
 }
 
-static int pvc_proc_read_scroll(char *page, char **start,
-                             off_t off, int count,
-                             int *eof, void *data)
+static int pvc_scroll_proc_show(struct seq_file *m, void *v)
 {
-        char *origpage = page;
-
         mutex_lock(&pvc_mutex);
-        page += sprintf(page, "%d\n", scroll_dir * scroll_interval);
+        seq_printf(m, "%d\n", scroll_dir * scroll_interval);
         mutex_unlock(&pvc_mutex);
 
-        return page - origpage;
+        return 0;
 }
 
+static int pvc_scroll_proc_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, pvc_scroll_proc_show, NULL);
+}
+
+static const struct file_operations pvc_scroll_proc_fops = {
+        .owner          = THIS_MODULE,
+        .open           = pvc_scroll_proc_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+        .write          = pvc_scroll_proc_write,
+};
 
 void pvc_proc_timerfunc(unsigned long data)
 {
@@ -163,22 +192,16 @@ static int __init pvc_proc_init(void)
                 pvc_linedata[i] = i;
         }
         for (i = 0; i < PVC_NLINES; i++) {
-                proc_entry = create_proc_entry(pvc_linename[i], 0644,
-                                               pvc_display_dir);
+                proc_entry = proc_create_data(pvc_linename[i], 0644, pvc_display_dir,
+                                        &pvc_line_proc_fops, &pvc_linedata[i]);
                 if (proc_entry == NULL)
                         goto error;
-
-                proc_entry->read_proc = pvc_proc_read_line;
-                proc_entry->write_proc = pvc_proc_write_line;
-                proc_entry->data = &pvc_linedata[i];
         }
-        proc_entry = create_proc_entry("scroll", 0644, pvc_display_dir);
+        proc_entry = proc_create("scroll", 0644, pvc_display_dir,
+                                 &pvc_scroll_proc_fops);
         if (proc_entry == NULL)
                 goto error;
 
-        proc_entry->write_proc = pvc_proc_write_scroll;
-        proc_entry->read_proc = pvc_proc_read_scroll;
-
         init_timer(&timer);
         timer.function = pvc_proc_timerfunc;
 
diff --git a/arch/mips/lasat/prom.c b/arch/mips/lasat/prom.c
index 6acc6cb85f0a..20fde19a5fbf 100644
--- a/arch/mips/lasat/prom.c
+++ b/arch/mips/lasat/prom.c
@@ -100,8 +100,8 @@ void __init prom_init(void)
 
         /* Get the command line */
         if (argc > 0) {
-                strncpy(arcs_cmdline, argv[0], CL_SIZE-1);
-                arcs_cmdline[CL_SIZE-1] = '\0';
+                strncpy(arcs_cmdline, argv[0], COMMAND_LINE_SIZE-1);
+                arcs_cmdline[COMMAND_LINE_SIZE-1] = '\0';
         }
 
         /* Set the I/O base address */
diff --git a/arch/mips/lasat/sysctl.c b/arch/mips/lasat/sysctl.c
index 14b9a28a4aec..d87ffd04cb0a 100644
--- a/arch/mips/lasat/sysctl.c
+++ b/arch/mips/lasat/sysctl.c
@@ -204,7 +204,7 @@ static ctl_table lasat_table[] = {
                 .maxlen         = sizeof(int),
                 .mode           = 0644,
                 .proc_handler   = proc_lasat_prid,
-.       },
+        },
 #ifdef CONFIG_INET
         {
                 .procname       = "ipaddr",
diff --git a/arch/mips/loongson/Kconfig b/arch/mips/loongson/Kconfig
index d45092505fa1..3df1967dea08 100644
--- a/arch/mips/loongson/Kconfig
+++ b/arch/mips/loongson/Kconfig
@@ -1,31 +1,85 @@
 choice
-    prompt "Machine Type"
-    depends on MACH_LOONGSON
+        prompt "Machine Type"
+        depends on MACH_LOONGSON
 
 config LEMOTE_FULOONG2E
-    bool "Lemote Fuloong(2e) mini-PC"
-    select ARCH_SPARSEMEM_ENABLE
-    select CEVT_R4K
-    select CSRC_R4K
-    select SYS_HAS_CPU_LOONGSON2E
-    select DMA_NONCOHERENT
-    select BOOT_ELF32
-    select BOARD_SCACHE
-    select HW_HAS_PCI
-    select I8259
-    select ISA
-    select IRQ_CPU
-    select SYS_SUPPORTS_32BIT_KERNEL
-    select SYS_SUPPORTS_64BIT_KERNEL
-    select SYS_SUPPORTS_LITTLE_ENDIAN
-    select SYS_SUPPORTS_HIGHMEM
-    select SYS_HAS_EARLY_PRINTK
-    select GENERIC_HARDIRQS_NO__DO_IRQ
-    select GENERIC_ISA_DMA_SUPPORT_BROKEN
-    select CPU_HAS_WB
-    help
-      Lemote Fuloong(2e) mini-PC board based on the Chinese Loongson-2E CPU and
-      an FPGA northbridge
-
-      Lemote Fuloong(2e) mini PC have a VIA686B south bridge.
+        bool "Lemote Fuloong(2e) mini-PC"
+        select ARCH_SPARSEMEM_ENABLE
+        select CEVT_R4K
+        select CSRC_R4K
+        select SYS_HAS_CPU_LOONGSON2E
+        select DMA_NONCOHERENT
+        select BOOT_ELF32
+        select BOARD_SCACHE
+        select HW_HAS_PCI
+        select I8259
+        select ISA
+        select IRQ_CPU
+        select SYS_SUPPORTS_32BIT_KERNEL
+        select SYS_SUPPORTS_64BIT_KERNEL
+        select SYS_SUPPORTS_LITTLE_ENDIAN
+        select SYS_SUPPORTS_HIGHMEM
+        select SYS_HAS_EARLY_PRINTK
+        select GENERIC_HARDIRQS_NO__DO_IRQ
+        select GENERIC_ISA_DMA_SUPPORT_BROKEN
+        select CPU_HAS_WB
+        help
+          Lemote Fuloong(2e) mini-PC board based on the Chinese Loongson-2E CPU and
+          an FPGA northbridge
+
+          Lemote Fuloong(2e) mini PC have a VIA686B south bridge.
+
+config LEMOTE_MACH2F
+        bool "Lemote Loongson 2F family machines"
+        select ARCH_SPARSEMEM_ENABLE
+        select BOARD_SCACHE
+        select BOOT_ELF32
+        select CEVT_R4K if ! MIPS_EXTERNAL_TIMER
+        select CPU_HAS_WB
+        select CS5536
+        select CSRC_R4K if ! MIPS_EXTERNAL_TIMER
+        select DMA_NONCOHERENT
+        select GENERIC_HARDIRQS_NO__DO_IRQ
+        select GENERIC_ISA_DMA_SUPPORT_BROKEN
+        select HW_HAS_PCI
+        select I8259
+        select IRQ_CPU
+        select ISA
+        select SYS_HAS_CPU_LOONGSON2F
+        select SYS_HAS_EARLY_PRINTK
+        select SYS_SUPPORTS_32BIT_KERNEL
+        select SYS_SUPPORTS_64BIT_KERNEL
+        select SYS_SUPPORTS_HIGHMEM
+        select SYS_SUPPORTS_LITTLE_ENDIAN
+        help
+          Lemote Loongson 2F family machines utilize the 2F revision of
+          Loongson processor and the AMD CS5536 south bridge.
+
+          These family machines include fuloong2f mini PC, yeeloong2f notebook,
+          LingLoong allinone PC and so forth.
 endchoice
+
+config CS5536
+        bool
+
+config CS5536_MFGPT
+        bool "CS5536 MFGPT Timer"
+        depends on CS5536
+        select MIPS_EXTERNAL_TIMER
+        help
+          This option enables the mfgpt0 timer of AMD CS5536.
+
+          If you want to enable the Loongson2 CPUFreq Driver, Please enable
+          this option at first, otherwise, You will get wrong system time.
+
+          If unsure, say Yes.
+
+config LOONGSON_SUSPEND
+        bool
+        default y
+        depends on CPU_SUPPORTS_CPUFREQ && SUSPEND
+
+config LOONGSON_UART_BASE
+        bool
+        default y
+        depends on EARLY_PRINTK || SERIAL_8250
diff --git a/arch/mips/loongson/Makefile b/arch/mips/loongson/Makefile
index 39048c455d7d..2b76cb0fb07d 100644
--- a/arch/mips/loongson/Makefile
+++ b/arch/mips/loongson/Makefile
@@ -9,3 +9,9 @@ obj-$(CONFIG_MACH_LOONGSON) += common/
 #
 
 obj-$(CONFIG_LEMOTE_FULOONG2E)  += fuloong-2e/
+
+#
+# Lemote loongson2f family machines
+#
+
+obj-$(CONFIG_LEMOTE_MACH2F)  += lemote-2f/
diff --git a/arch/mips/loongson/common/Makefile b/arch/mips/loongson/common/Makefile
index 656b3cc0a2a6..7668c4de1151 100644
--- a/arch/mips/loongson/common/Makefile
+++ b/arch/mips/loongson/common/Makefile
@@ -3,9 +3,23 @@
 #
 
 obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \
-    pci.o bonito-irq.o mem.o machtype.o
+    pci.o bonito-irq.o mem.o machtype.o platform.o
 
 #
-# Early printk support
+# Serial port support
 #
 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
+obj-$(CONFIG_SERIAL_8250) += serial.o
+obj-$(CONFIG_LOONGSON_UART_BASE) += uart_base.o
+
+#
+# Enable CS5536 Virtual Support Module(VSM) to virtulize the PCI configure
+# space
+#
+obj-$(CONFIG_CS5536) += cs5536/
+
+#
+# Suspend Support
+#
+
+obj-$(CONFIG_LOONGSON_SUSPEND) += pm.o
diff --git a/arch/mips/loongson/common/bonito-irq.c b/arch/mips/loongson/common/bonito-irq.c
index 3e31e7ad713e..2dc2a4cc632a 100644
--- a/arch/mips/loongson/common/bonito-irq.c
+++ b/arch/mips/loongson/common/bonito-irq.c
@@ -12,18 +12,19 @@
  *  option) any later version.
  */
 #include <linux/interrupt.h>
+#include <linux/compiler.h>
 
 #include <loongson.h>
 
 static inline void bonito_irq_enable(unsigned int irq)
 {
-        BONITO_INTENSET = (1 << (irq - BONITO_IRQ_BASE));
+        LOONGSON_INTENSET = (1 << (irq - LOONGSON_IRQ_BASE));
         mmiowb();
 }
 
 static inline void bonito_irq_disable(unsigned int irq)
 {
-        BONITO_INTENCLR = (1 << (irq - BONITO_IRQ_BASE));
+        LOONGSON_INTENCLR = (1 << (irq - LOONGSON_IRQ_BASE));
         mmiowb();
 }
 
@@ -35,7 +36,7 @@ static struct irq_chip bonito_irq_type = {
         .unmask = bonito_irq_enable,
 };
 
-static struct irqaction dma_timeout_irqaction = {
+static struct irqaction __maybe_unused dma_timeout_irqaction = {
         .handler        = no_action,
         .name           = "dma_timeout",
 };
@@ -44,8 +45,10 @@ void bonito_irq_init(void)
 {
         u32 i;
 
-        for (i = BONITO_IRQ_BASE; i < BONITO_IRQ_BASE + 32; i++)
+        for (i = LOONGSON_IRQ_BASE; i < LOONGSON_IRQ_BASE + 32; i++)
                 set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq);
 
-        setup_irq(BONITO_IRQ_BASE + 10, &dma_timeout_irqaction);
+#ifdef CONFIG_CPU_LOONGSON2E
+        setup_irq(LOONGSON_IRQ_BASE + 10, &dma_timeout_irqaction);
+#endif
 }
diff --git a/arch/mips/loongson/common/cmdline.c b/arch/mips/loongson/common/cmdline.c
index 75f1b243ee4e..7ad47f227477 100644
--- a/arch/mips/loongson/common/cmdline.c
+++ b/arch/mips/loongson/common/cmdline.c
@@ -9,7 +9,7 @@
  * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
  * Author: Fuxin Zhang, zhangfx@lemote.com
  *
- * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
+ * Copyright (C) 2009 Lemote Inc.
  * Author: Wu Zhangjin, wuzj@lemote.com
  *
  * This program is free software; you can redistribute  it and/or modify it
@@ -49,4 +49,6 @@ void __init prom_init_cmdline(void)
                 strcat(arcs_cmdline, " console=ttyS0,115200");
         if ((strstr(arcs_cmdline, "root=")) == NULL)
                 strcat(arcs_cmdline, " root=/dev/hda1");
+
+        prom_init_machtype();
 }
diff --git a/arch/mips/loongson/common/cs5536/Makefile b/arch/mips/loongson/common/cs5536/Makefile
new file mode 100644
index 000000000000..510d4cdc2378
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/Makefile
@@ -0,0 +1,13 @@
+#
+# Makefile for CS5536 support.
+#
+
+obj-$(CONFIG_CS5536) += cs5536_pci.o cs5536_ide.o cs5536_acc.o cs5536_ohci.o \
+                        cs5536_isa.o cs5536_ehci.o
+
+#
+# Enable cs5536 mfgpt Timer
+#
+obj-$(CONFIG_CS5536_MFGPT) += cs5536_mfgpt.o
+
+EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/loongson/common/cs5536/cs5536_acc.c b/arch/mips/loongson/common/cs5536/cs5536_acc.c
new file mode 100644
index 000000000000..b49485f187e0
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_acc.c
@@ -0,0 +1,140 @@
+/*
+ * the ACC Virtual Support Module of AMD CS5536
+ *
+ * Copyright (C) 2007 Lemote, Inc.
+ * Author : jlliu, liujl@lemote.com
+ *
+ * Copyright (C) 2009 Lemote, Inc.
+ * Author: Wu Zhangjin, wuzj@lemote.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <cs5536/cs5536.h>
+#include <cs5536/cs5536_pci.h>
+
+void pci_acc_write_reg(int reg, u32 value)
+{
+        u32 hi = 0, lo = value;
+
+        switch (reg) {
+        case PCI_COMMAND:
+                _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
+                if (value & PCI_COMMAND_MASTER)
+                        lo |= (0x03 << 8);
+                else
+                        lo &= ~(0x03 << 8);
+                _wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo);
+                break;
+        case PCI_STATUS:
+                if (value & PCI_STATUS_PARITY) {
+                        _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+                        if (lo & SB_PARE_ERR_FLAG) {
+                                lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
+                                _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
+                        }
+                }
+                break;
+        case PCI_BAR0_REG:
+                if (value == PCI_BAR_RANGE_MASK) {
+                        _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+                        lo |= SOFT_BAR_ACC_FLAG;
+                        _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+                } else if (value & 0x01) {
+                        value &= 0xfffffffc;
+                        hi = 0xA0000000 | ((value & 0x000ff000) >> 12);
+                        lo = 0x000fff80 | ((value & 0x00000fff) << 20);
+                        _wrmsr(GLIU_MSR_REG(GLIU_IOD_BM1), hi, lo);
+                }
+                break;
+        case PCI_ACC_INT_REG:
+                _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
+                /* disable all the usb interrupt in PIC */
+                lo &= ~(0xf << PIC_YSEL_LOW_ACC_SHIFT);
+                if (value)      /* enable all the acc interrupt in PIC */
+                        lo |= (CS5536_ACC_INTR << PIC_YSEL_LOW_ACC_SHIFT);
+                _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
+                break;
+        default:
+                break;
+        }
+}
+
+u32 pci_acc_read_reg(int reg)
+{
+        u32 hi, lo;
+        u32 conf_data = 0;
+
+        switch (reg) {
+        case PCI_VENDOR_ID:
+                conf_data =
+                    CFG_PCI_VENDOR_ID(CS5536_ACC_DEVICE_ID, CS5536_VENDOR_ID);
+                break;
+        case PCI_COMMAND:
+                _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo);
+                if (((lo & 0xfff00000) || (hi & 0x000000ff))
+                    && ((hi & 0xf0000000) == 0xa0000000))
+                        conf_data |= PCI_COMMAND_IO;
+                _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
+                if ((lo & 0x300) == 0x300)
+                        conf_data |= PCI_COMMAND_MASTER;
+                break;
+        case PCI_STATUS:
+                conf_data |= PCI_STATUS_66MHZ;
+                conf_data |= PCI_STATUS_FAST_BACK;
+                _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+                if (lo & SB_PARE_ERR_FLAG)
+                        conf_data |= PCI_STATUS_PARITY;
+                conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
+                break;
+        case PCI_CLASS_REVISION:
+                _rdmsr(ACC_MSR_REG(ACC_CAP), &hi, &lo);
+                conf_data = lo & 0x000000ff;
+                conf_data |= (CS5536_ACC_CLASS_CODE << 8);
+                break;
+        case PCI_CACHE_LINE_SIZE:
+                conf_data =
+                    CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
+                                            PCI_NORMAL_LATENCY_TIMER);
+                break;
+        case PCI_BAR0_REG:
+                _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+                if (lo & SOFT_BAR_ACC_FLAG) {
+                        conf_data = CS5536_ACC_RANGE |
+                            PCI_BASE_ADDRESS_SPACE_IO;
+                        lo &= ~SOFT_BAR_ACC_FLAG;
+                        _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+                } else {
+                        _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo);
+                        conf_data = (hi & 0x000000ff) << 12;
+                        conf_data |= (lo & 0xfff00000) >> 20;
+                        conf_data |= 0x01;
+                        conf_data &= ~0x02;
+                }
+                break;
+        case PCI_CARDBUS_CIS:
+                conf_data = PCI_CARDBUS_CIS_POINTER;
+                break;
+        case PCI_SUBSYSTEM_VENDOR_ID:
+                conf_data =
+                    CFG_PCI_VENDOR_ID(CS5536_ACC_SUB_ID, CS5536_SUB_VENDOR_ID);
+                break;
+        case PCI_ROM_ADDRESS:
+                conf_data = PCI_EXPANSION_ROM_BAR;
+                break;
+        case PCI_CAPABILITY_LIST:
+                conf_data = PCI_CAPLIST_USB_POINTER;
+                break;
+        case PCI_INTERRUPT_LINE:
+                conf_data =
+                    CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_ACC_INTR);
+                break;
+        default:
+                break;
+        }
+
+        return conf_data;
+}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_ehci.c b/arch/mips/loongson/common/cs5536/cs5536_ehci.c
new file mode 100644
index 000000000000..74f9c59d36af
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_ehci.c
@@ -0,0 +1,158 @@
+/*
+ * the EHCI Virtual Support Module of AMD CS5536
+ *
+ * Copyright (C) 2007 Lemote, Inc.
+ * Author : jlliu, liujl@lemote.com
+ *
+ * Copyright (C) 2009 Lemote, Inc.
+ * Author: Wu Zhangjin, wuzj@lemote.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <cs5536/cs5536.h>
+#include <cs5536/cs5536_pci.h>
+
+void pci_ehci_write_reg(int reg, u32 value)
+{
+        u32 hi = 0, lo = value;
+
+        switch (reg) {
+        case PCI_COMMAND:
+                _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
+                if (value & PCI_COMMAND_MASTER)
+                        hi |= PCI_COMMAND_MASTER;
+                else
+                        hi &= ~PCI_COMMAND_MASTER;
+
+                if (value & PCI_COMMAND_MEMORY)
+                        hi |= PCI_COMMAND_MEMORY;
+                else
+                        hi &= ~PCI_COMMAND_MEMORY;
+                _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
+                break;
+        case PCI_STATUS:
+                if (value & PCI_STATUS_PARITY) {
+                        _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+                        if (lo & SB_PARE_ERR_FLAG) {
+                                lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
+                                _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
+                        }
+                }
+                break;
+        case PCI_BAR0_REG:
+                if (value == PCI_BAR_RANGE_MASK) {
+                        _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+                        lo |= SOFT_BAR_EHCI_FLAG;
+                        _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+                } else if ((value & 0x01) == 0x00) {
+                        _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
+
+                        value &= 0xfffffff0;
+                        hi = 0x40000000 | ((value & 0xff000000) >> 24);
+                        lo = 0x000fffff | ((value & 0x00fff000) << 8);
+                        _wrmsr(GLIU_MSR_REG(GLIU_P2D_BM4), hi, lo);
+                }
+                break;
+        case PCI_EHCI_LEGSMIEN_REG:
+                _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
+                hi &= 0x003f0000;
+                hi |= (value & 0x3f) << 16;
+                _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
+                break;
+        case PCI_EHCI_FLADJ_REG:
+                _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
+                hi &= ~0x00003f00;
+                hi |= value & 0x00003f00;
+                _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
+                break;
+        default:
+                break;
+        }
+}
+
+u32 pci_ehci_read_reg(int reg)
+{
+        u32 conf_data = 0;
+        u32 hi, lo;
+
+        switch (reg) {
+        case PCI_VENDOR_ID:
+                conf_data =
+                    CFG_PCI_VENDOR_ID(CS5536_EHCI_DEVICE_ID, CS5536_VENDOR_ID);
+                break;
+        case PCI_COMMAND:
+                _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
+                if (hi & PCI_COMMAND_MASTER)
+                        conf_data |= PCI_COMMAND_MASTER;
+                if (hi & PCI_COMMAND_MEMORY)
+                        conf_data |= PCI_COMMAND_MEMORY;
+                break;
+        case PCI_STATUS:
+                conf_data |= PCI_STATUS_66MHZ;
+                conf_data |= PCI_STATUS_FAST_BACK;
+                _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+                if (lo & SB_PARE_ERR_FLAG)
+                        conf_data |= PCI_STATUS_PARITY;
+                conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
+                break;
+        case PCI_CLASS_REVISION:
+                _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo);
+                conf_data = lo & 0x000000ff;
+                conf_data |= (CS5536_EHCI_CLASS_CODE << 8);
+                break;
+        case PCI_CACHE_LINE_SIZE:
+                conf_data =
+                    CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
+                                            PCI_NORMAL_LATENCY_TIMER);
+                break;
+        case PCI_BAR0_REG:
+                _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+                if (lo & SOFT_BAR_EHCI_FLAG) {
+                        conf_data = CS5536_EHCI_RANGE |
+                            PCI_BASE_ADDRESS_SPACE_MEMORY;
+                        lo &= ~SOFT_BAR_EHCI_FLAG;
+                        _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+                } else {
+                        _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
+                        conf_data = lo & 0xfffff000;
+                }
+                break;
+        case PCI_CARDBUS_CIS:
+                conf_data = PCI_CARDBUS_CIS_POINTER;
+                break;
+        case PCI_SUBSYSTEM_VENDOR_ID:
+                conf_data =
+                    CFG_PCI_VENDOR_ID(CS5536_EHCI_SUB_ID, CS5536_SUB_VENDOR_ID);
+                break;
+        case PCI_ROM_ADDRESS:
+                conf_data = PCI_EXPANSION_ROM_BAR;
+                break;
+        case PCI_CAPABILITY_LIST:
+                conf_data = PCI_CAPLIST_USB_POINTER;
+                break;
+        case PCI_INTERRUPT_LINE:
+                conf_data =
+                    CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR);
+                break;
+        case PCI_EHCI_LEGSMIEN_REG:
+                _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
+                conf_data = (hi & 0x003f0000) >> 16;
+                break;
+        case PCI_EHCI_LEGSMISTS_REG:
+                _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
+                conf_data = (hi & 0x3f000000) >> 24;
+                break;
+        case PCI_EHCI_FLADJ_REG:
+                _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
+                conf_data = hi & 0x00003f00;
+                break;
+        default:
+                break;
+        }
+
+        return conf_data;
+}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_ide.c b/arch/mips/loongson/common/cs5536/cs5536_ide.c
new file mode 100644
index 000000000000..3f61594b3884
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_ide.c
@@ -0,0 +1,179 @@
+/*
+ * the IDE Virtual Support Module of AMD CS5536
+ *
+ * Copyright (C) 2007 Lemote, Inc.
+ * Author : jlliu, liujl@lemote.com
+ *
+ * Copyright (C) 2009 Lemote, Inc.
+ * Author: Wu Zhangjin, wuzj@lemote.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <cs5536/cs5536.h>
+#include <cs5536/cs5536_pci.h>
+
+void pci_ide_write_reg(int reg, u32 value)
+{
+        u32 hi = 0, lo = value;
+
+        switch (reg) {
+        case PCI_COMMAND:
+                _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
+                if (value & PCI_COMMAND_MASTER)
+                        lo |= (0x03 << 4);
+                else
+                        lo &= ~(0x03 << 4);
+                _wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo);
+                break;
+        case PCI_STATUS:
+                if (value & PCI_STATUS_PARITY) {
+                        _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+                        if (lo & SB_PARE_ERR_FLAG) {
+                                lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
+                                _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
+                        }
+                }
+                break;
+        case PCI_CACHE_LINE_SIZE:
+                value &= 0x0000ff00;
+                _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
+                hi &= 0xffffff00;
+                hi |= (value >> 8);
+                _wrmsr(SB_MSR_REG(SB_CTRL), hi, lo);
+                break;
+        case PCI_BAR4_REG:
+                if (value == PCI_BAR_RANGE_MASK) {
+                        _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+                        lo |= SOFT_BAR_IDE_FLAG;
+                        _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+                } else if (value & 0x01) {
+                        lo = (value & 0xfffffff0) | 0x1;
+                        _wrmsr(IDE_MSR_REG(IDE_IO_BAR), hi, lo);
+
+                        value &= 0xfffffffc;
+                        hi = 0x60000000 | ((value & 0x000ff000) >> 12);
+                        lo = 0x000ffff0 | ((value & 0x00000fff) << 20);
+                        _wrmsr(GLIU_MSR_REG(GLIU_IOD_BM2), hi, lo);
+                }
+                break;
+        case PCI_IDE_CFG_REG:
+                if (value == CS5536_IDE_FLASH_SIGNATURE) {
+                        _rdmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), &hi, &lo);
+                        lo |= 0x01;
+                        _wrmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), hi, lo);
+                } else
+                        _wrmsr(IDE_MSR_REG(IDE_CFG), hi, lo);
+                break;
+        case PCI_IDE_DTC_REG:
+                _wrmsr(IDE_MSR_REG(IDE_DTC), hi, lo);
+                break;
+        case PCI_IDE_CAST_REG:
+                _wrmsr(IDE_MSR_REG(IDE_CAST), hi, lo);
+                break;
+        case PCI_IDE_ETC_REG:
+                _wrmsr(IDE_MSR_REG(IDE_ETC), hi, lo);
+                break;
+        case PCI_IDE_PM_REG:
+                _wrmsr(IDE_MSR_REG(IDE_INTERNAL_PM), hi, lo);
+                break;
+        default:
+                break;
+        }
+}
+
+u32 pci_ide_read_reg(int reg)
+{
+        u32 conf_data = 0;
+        u32 hi, lo;
+
+        switch (reg) {
+        case PCI_VENDOR_ID:
+                conf_data =
+                    CFG_PCI_VENDOR_ID(CS5536_IDE_DEVICE_ID, CS5536_VENDOR_ID);
+                break;
+        case PCI_COMMAND:
+                _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo);
+                if (lo & 0xfffffff0)
+                        conf_data |= PCI_COMMAND_IO;
+                _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
+                if ((lo & 0x30) == 0x30)
+                        conf_data |= PCI_COMMAND_MASTER;
+                break;
+        case PCI_STATUS:
+                conf_data |= PCI_STATUS_66MHZ;
+                conf_data |= PCI_STATUS_FAST_BACK;
+                _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+                if (lo & SB_PARE_ERR_FLAG)
+                        conf_data |= PCI_STATUS_PARITY;
+                conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
+                break;
+        case PCI_CLASS_REVISION:
+                _rdmsr(IDE_MSR_REG(IDE_CAP), &hi, &lo);
+                conf_data = lo & 0x000000ff;
+                conf_data |= (CS5536_IDE_CLASS_CODE << 8);
+                break;
+        case PCI_CACHE_LINE_SIZE:
+                _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
+                hi &= 0x000000f8;
+                conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, hi);
+                break;
+        case PCI_BAR4_REG:
+                _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+                if (lo & SOFT_BAR_IDE_FLAG) {
+                        conf_data = CS5536_IDE_RANGE |
+                            PCI_BASE_ADDRESS_SPACE_IO;
+                        lo &= ~SOFT_BAR_IDE_FLAG;
+                        _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+                } else {
+                        _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo);
+                        conf_data = lo & 0xfffffff0;
+                        conf_data |= 0x01;
+                        conf_data &= ~0x02;
+                }
+                break;
+        case PCI_CARDBUS_CIS:
+                conf_data = PCI_CARDBUS_CIS_POINTER;
+                break;
+        case PCI_SUBSYSTEM_VENDOR_ID:
+                conf_data =
+                    CFG_PCI_VENDOR_ID(CS5536_IDE_SUB_ID, CS5536_SUB_VENDOR_ID);
+                break;
+        case PCI_ROM_ADDRESS:
+                conf_data = PCI_EXPANSION_ROM_BAR;
+                break;
+        case PCI_CAPABILITY_LIST:
+                conf_data = PCI_CAPLIST_POINTER;
+                break;
+        case PCI_INTERRUPT_LINE:
+                conf_data =
+                    CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_IDE_INTR);
+                break;
+        case PCI_IDE_CFG_REG:
+                _rdmsr(IDE_MSR_REG(IDE_CFG), &hi, &lo);
+                conf_data = lo;
+                break;
+        case PCI_IDE_DTC_REG:
+                _rdmsr(IDE_MSR_REG(IDE_DTC), &hi, &lo);
+                conf_data = lo;
+                break;
+        case PCI_IDE_CAST_REG:
+                _rdmsr(IDE_MSR_REG(IDE_CAST), &hi, &lo);
+                conf_data = lo;
+                break;
+        case PCI_IDE_ETC_REG:
+                _rdmsr(IDE_MSR_REG(IDE_ETC), &hi, &lo);
+                conf_data = lo;
+        case PCI_IDE_PM_REG:
+                _rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM), &hi, &lo);
+                conf_data = lo;
+                break;
+        default:
+                break;
+        }
+
+        return conf_data;
+}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_isa.c b/arch/mips/loongson/common/cs5536/cs5536_isa.c
new file mode 100644
index 000000000000..b6f17f538e48
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_isa.c
@@ -0,0 +1,316 @@
+/*
+ * the ISA Virtual Support Module of AMD CS5536
+ *
+ * Copyright (C) 2007 Lemote, Inc.
+ * Author : jlliu, liujl@lemote.com
+ *
+ * Copyright (C) 2009 Lemote, Inc.
+ * Author: Wu Zhangjin, wuzj@lemote.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <cs5536/cs5536.h>
+#include <cs5536/cs5536_pci.h>
+
+/* common variables for PCI_ISA_READ/WRITE_BAR */
+static const u32 divil_msr_reg[6] = {
+        DIVIL_MSR_REG(DIVIL_LBAR_SMB), DIVIL_MSR_REG(DIVIL_LBAR_GPIO),
+        DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), DIVIL_MSR_REG(DIVIL_LBAR_IRQ),
+        DIVIL_MSR_REG(DIVIL_LBAR_PMS), DIVIL_MSR_REG(DIVIL_LBAR_ACPI),
+};
+
+static const u32 soft_bar_flag[6] = {
+        SOFT_BAR_SMB_FLAG, SOFT_BAR_GPIO_FLAG, SOFT_BAR_MFGPT_FLAG,
+        SOFT_BAR_IRQ_FLAG, SOFT_BAR_PMS_FLAG, SOFT_BAR_ACPI_FLAG,
+};
+
+static const u32 sb_msr_reg[6] = {
+        SB_MSR_REG(SB_R0), SB_MSR_REG(SB_R1), SB_MSR_REG(SB_R2),
+        SB_MSR_REG(SB_R3), SB_MSR_REG(SB_R4), SB_MSR_REG(SB_R5),
+};
+
+static const u32 bar_space_range[6] = {
+        CS5536_SMB_RANGE, CS5536_GPIO_RANGE, CS5536_MFGPT_RANGE,
+        CS5536_IRQ_RANGE, CS5536_PMS_RANGE, CS5536_ACPI_RANGE,
+};
+
+static const int bar_space_len[6] = {
+        CS5536_SMB_LENGTH, CS5536_GPIO_LENGTH, CS5536_MFGPT_LENGTH,
+        CS5536_IRQ_LENGTH, CS5536_PMS_LENGTH, CS5536_ACPI_LENGTH,
+};
+
+/*
+ * enable the divil module bar space.
+ *
+ * For all the DIVIL module LBAR, you should control the DIVIL LBAR reg
+ * and the RCONFx(0~5) reg to use the modules.
+ */
+static void divil_lbar_enable(void)
+{
+        u32 hi, lo;
+        int offset;
+
+        /*
+         * The DIVIL IRQ is not used yet. and make the RCONF0 reserved.
+         */
+
+        for (offset = DIVIL_LBAR_SMB; offset <= DIVIL_LBAR_PMS; offset++) {
+                _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo);
+                hi |= 0x01;
+                _wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), hi, lo);
+        }
+}
+
+/*
+ * disable the divil module bar space.
+ */
+static void divil_lbar_disable(void)
+{
+        u32 hi, lo;
+        int offset;
+
+        for (offset = DIVIL_LBAR_SMB; offset <= DIVIL_LBAR_PMS; offset++) {
+                _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo);
+                hi &= ~0x01;
+                _wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), hi, lo);
+        }
+}
+
+/*
+ * BAR write: write value to the n BAR
+ */
+
+void pci_isa_write_bar(int n, u32 value)
+{
+        u32 hi = 0, lo = value;
+
+        if (value == PCI_BAR_RANGE_MASK) {
+                _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+                lo |= soft_bar_flag[n];
+                _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+        } else if (value & 0x01) {
+                /* NATIVE reg */
+                hi = 0x0000f001;
+                lo &= bar_space_range[n];
+                _wrmsr(divil_msr_reg[n], hi, lo);
+
+                /* RCONFx is 4bytes in units for I/O space */
+                hi = ((value & 0x000ffffc) << 12) |
+                    ((bar_space_len[n] - 4) << 12) | 0x01;
+                lo = ((value & 0x000ffffc) << 12) | 0x01;
+                _wrmsr(sb_msr_reg[n], hi, lo);
+        }
+}
+
+/*
+ * BAR read: read the n BAR
+ */
+
+u32 pci_isa_read_bar(int n)
+{
+        u32 conf_data = 0;
+        u32 hi, lo;
+
+        _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+        if (lo & soft_bar_flag[n]) {
+                conf_data = bar_space_range[n] | PCI_BASE_ADDRESS_SPACE_IO;
+                lo &= ~soft_bar_flag[n];
+                _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+        } else {
+                _rdmsr(divil_msr_reg[n], &hi, &lo);
+                conf_data = lo & bar_space_range[n];
+                conf_data |= 0x01;
+                conf_data &= ~0x02;
+        }
+        return conf_data;
+}
+
+/*
+ * isa_write: ISA write transfer
+ *
+ * We assume that this is not a bus master transfer.
+ */
+void pci_isa_write_reg(int reg, u32 value)
+{
+        u32 hi = 0, lo = value;
+        u32 temp;
+
+        switch (reg) {
+        case PCI_COMMAND:
+                if (value & PCI_COMMAND_IO)
+                        divil_lbar_enable();
+                else
+                        divil_lbar_disable();
+                break;
+        case PCI_STATUS:
+                _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+                temp = lo & 0x0000ffff;
+                if ((value & PCI_STATUS_SIG_TARGET_ABORT) &&
+                    (lo & SB_TAS_ERR_EN))
+                        temp |= SB_TAS_ERR_FLAG;
+
+                if ((value & PCI_STATUS_REC_TARGET_ABORT) &&
+                    (lo & SB_TAR_ERR_EN))
+                        temp |= SB_TAR_ERR_FLAG;
+
+                if ((value & PCI_STATUS_REC_MASTER_ABORT)
+                    && (lo & SB_MAR_ERR_EN))
+                        temp |= SB_MAR_ERR_FLAG;
+
+                if ((value & PCI_STATUS_DETECTED_PARITY)
+                    && (lo & SB_PARE_ERR_EN))
+                        temp |= SB_PARE_ERR_FLAG;
+
+                lo = temp;
+                _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
+                break;
+        case PCI_CACHE_LINE_SIZE:
+                value &= 0x0000ff00;
+                _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
+                hi &= 0xffffff00;
+                hi |= (value >> 8);
+                _wrmsr(SB_MSR_REG(SB_CTRL), hi, lo);
+                break;
+        case PCI_BAR0_REG:
+                pci_isa_write_bar(0, value);
+                break;
+        case PCI_BAR1_REG:
+                pci_isa_write_bar(1, value);
+                break;
+        case PCI_BAR2_REG:
+                pci_isa_write_bar(2, value);
+                break;
+        case PCI_BAR3_REG:
+                pci_isa_write_bar(3, value);
+                break;
+        case PCI_BAR4_REG:
+                pci_isa_write_bar(4, value);
+                break;
+        case PCI_BAR5_REG:
+                pci_isa_write_bar(5, value);
+                break;
+        case PCI_UART1_INT_REG:
+                _rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo);
+                /* disable uart1 interrupt in PIC */
+                lo &= ~(0xf << 24);
+                if (value)      /* enable uart1 interrupt in PIC */
+                        lo |= (CS5536_UART1_INTR << 24);
+                _wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo);
+                break;
+        case PCI_UART2_INT_REG:
+                _rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo);
+                /* disable uart2 interrupt in PIC */
+                lo &= ~(0xf << 28);
+                if (value)      /* enable uart2 interrupt in PIC */
+                        lo |= (CS5536_UART2_INTR << 28);
+                _wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo);
+                break;
+        case PCI_ISA_FIXUP_REG:
+                if (value) {
+                        /* enable the TARGET ABORT/MASTER ABORT etc. */
+                        _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+                        lo |= 0x00000063;
+                        _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
+                }
+
+        default:
+                /* ALL OTHER PCI CONFIG SPACE HEADER IS NOT IMPLEMENTED. */
+                break;
+        }
+}
+
+/*
+ * isa_read: ISA read transfers
+ *
+ * We assume that this is not a bus master transfer.
+ */
+u32 pci_isa_read_reg(int reg)
+{
+        u32 conf_data = 0;
+        u32 hi, lo;
+
+        switch (reg) {
+        case PCI_VENDOR_ID:
+                conf_data =
+                    CFG_PCI_VENDOR_ID(CS5536_ISA_DEVICE_ID, CS5536_VENDOR_ID);
+                break;
+        case PCI_COMMAND:
+                /* we just check the first LBAR for the IO enable bit, */
+                /* maybe we should changed later. */
+                _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), &hi, &lo);
+                if (hi & 0x01)
+                        conf_data |= PCI_COMMAND_IO;
+                break;
+        case PCI_STATUS:
+                conf_data |= PCI_STATUS_66MHZ;
+                conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
+                conf_data |= PCI_STATUS_FAST_BACK;
+
+                _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+                if (lo & SB_TAS_ERR_FLAG)
+                        conf_data |= PCI_STATUS_SIG_TARGET_ABORT;
+                if (lo & SB_TAR_ERR_FLAG)
+                        conf_data |= PCI_STATUS_REC_TARGET_ABORT;
+                if (lo & SB_MAR_ERR_FLAG)
+                        conf_data |= PCI_STATUS_REC_MASTER_ABORT;
+                if (lo & SB_PARE_ERR_FLAG)
+                        conf_data |= PCI_STATUS_DETECTED_PARITY;
+                break;
+        case PCI_CLASS_REVISION:
+                _rdmsr(GLCP_MSR_REG(GLCP_CHIP_REV_ID), &hi, &lo);
+                conf_data = lo & 0x000000ff;
+                conf_data |= (CS5536_ISA_CLASS_CODE << 8);
+                break;
+        case PCI_CACHE_LINE_SIZE:
+                _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
+                hi &= 0x000000f8;
+                conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_BRIDGE_HEADER_TYPE, hi);
+                break;
+                /*
+                 * we only use the LBAR of DIVIL, no RCONF used.
+                 * all of them are IO space.
+                 */
+        case PCI_BAR0_REG:
+                return pci_isa_read_bar(0);
+                break;
+        case PCI_BAR1_REG:
+                return pci_isa_read_bar(1);
+                break;
+        case PCI_BAR2_REG:
+                return pci_isa_read_bar(2);
+                break;
+        case PCI_BAR3_REG:
+                break;
+        case PCI_BAR4_REG:
+                return pci_isa_read_bar(4);
+                break;
+        case PCI_BAR5_REG:
+                return pci_isa_read_bar(5);
+                break;
+        case PCI_CARDBUS_CIS:
+                conf_data = PCI_CARDBUS_CIS_POINTER;
+                break;
+        case PCI_SUBSYSTEM_VENDOR_ID:
+                conf_data =
+                    CFG_PCI_VENDOR_ID(CS5536_ISA_SUB_ID, CS5536_SUB_VENDOR_ID);
+                break;
+        case PCI_ROM_ADDRESS:
+                conf_data = PCI_EXPANSION_ROM_BAR;
+                break;
+        case PCI_CAPABILITY_LIST:
+                conf_data = PCI_CAPLIST_POINTER;
+                break;
+        case PCI_INTERRUPT_LINE:
+                /* no interrupt used here */
+                conf_data = CFG_PCI_INTERRUPT_LINE(0x00, 0x00);
+                break;
+        default:
+                break;
+        }
+
+        return conf_data;
+}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c b/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
new file mode 100644
index 000000000000..6cb44dbaeec2
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
@@ -0,0 +1,217 @@
+/*
+ * CS5536 General timer functions
+ *
+ * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
+ * Author: Yanhua, yanh@lemote.com
+ *
+ * Copyright (C) 2009 Lemote Inc.
+ * Author: Wu zhangjin, wuzj@lemote.com
+ *
+ * Reference: AMD Geode(TM) CS5536 Companion Device Data Book
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/jiffies.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/clockchips.h>
+
+#include <asm/time.h>
+
+#include <cs5536/cs5536_mfgpt.h>
+
+DEFINE_SPINLOCK(mfgpt_lock);
+EXPORT_SYMBOL(mfgpt_lock);
+
+static u32 mfgpt_base;
+
+/*
+ * Initialize the MFGPT timer.
+ *
+ * This is also called after resume to bring the MFGPT into operation again.
+ */
+
+/* disable counter */
+void disable_mfgpt0_counter(void)
+{
+        outw(inw(MFGPT0_SETUP) & 0x7fff, MFGPT0_SETUP);
+}
+EXPORT_SYMBOL(disable_mfgpt0_counter);
+
+/* enable counter, comparator2 to event mode, 14.318MHz clock */
+void enable_mfgpt0_counter(void)
+{
+        outw(0xe310, MFGPT0_SETUP);
+}
+EXPORT_SYMBOL(enable_mfgpt0_counter);
+
+static void init_mfgpt_timer(enum clock_event_mode mode,
+                             struct clock_event_device *evt)
+{
+        spin_lock(&mfgpt_lock);
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                outw(COMPARE, MFGPT0_CMP2);     /* set comparator2 */
+                outw(0, MFGPT0_CNT);    /* set counter to 0 */
+                enable_mfgpt0_counter();
+                break;
+
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_UNUSED:
+                if (evt->mode == CLOCK_EVT_MODE_PERIODIC ||
+                    evt->mode == CLOCK_EVT_MODE_ONESHOT)
+                        disable_mfgpt0_counter();
+                break;
+
+        case CLOCK_EVT_MODE_ONESHOT:
+                /* The oneshot mode have very high deviation, Not use it! */
+                break;
+
+        case CLOCK_EVT_MODE_RESUME:
+                /* Nothing to do here */
+                break;
+        }
+        spin_unlock(&mfgpt_lock);
+}
+
+static struct clock_event_device mfgpt_clockevent = {
+        .name = "mfgpt",
+        .features = CLOCK_EVT_FEAT_PERIODIC,
+        .set_mode = init_mfgpt_timer,
+        .irq = CS5536_MFGPT_INTR,
+};
+
+static irqreturn_t timer_interrupt(int irq, void *dev_id)
+{
+        u32 basehi;
+
+        /*
+         * get MFGPT base address
+         *
+         * NOTE: do not remove me, it's need for the value of mfgpt_base is
+         * variable
+         */
+        _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base);
+
+        /* ack */
+        outw(inw(MFGPT0_SETUP) | 0x4000, MFGPT0_SETUP);
+
+        mfgpt_clockevent.event_handler(&mfgpt_clockevent);
+
+        return IRQ_HANDLED;
+}
+
+static struct irqaction irq5 = {
+        .handler = timer_interrupt,
+        .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER,
+        .name = "timer"
+};
+
+/*
+ * Initialize the conversion factor and the min/max deltas of the clock event
+ * structure and register the clock event source with the framework.
+ */
+void __init setup_mfgpt0_timer(void)
+{
+        u32 basehi;
+        struct clock_event_device *cd = &mfgpt_clockevent;
+        unsigned int cpu = smp_processor_id();
+
+        cd->cpumask = cpumask_of(cpu);
+        clockevent_set_clock(cd, MFGPT_TICK_RATE);
+        cd->max_delta_ns = clockevent_delta2ns(0xffff, cd);
+        cd->min_delta_ns = clockevent_delta2ns(0xf, cd);
+
+        /* Enable MFGPT0 Comparator 2 Output to the Interrupt Mapper */
+        _wrmsr(DIVIL_MSR_REG(MFGPT_IRQ), 0, 0x100);
+
+        /* Enable Interrupt Gate 5 */
+        _wrmsr(DIVIL_MSR_REG(PIC_ZSEL_LOW), 0, 0x50000);
+
+        /* get MFGPT base address */
+        _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base);
+
+        clockevents_register_device(cd);
+
+        setup_irq(CS5536_MFGPT_INTR, &irq5);
+}
+
+/*
+ * Since the MFGPT overflows every tick, its not very useful
+ * to just read by itself. So use jiffies to emulate a free
+ * running counter:
+ */
+static cycle_t mfgpt_read(struct clocksource *cs)
+{
+        unsigned long flags;
+        int count;
+        u32 jifs;
+        static int old_count;
+        static u32 old_jifs;
+
+        spin_lock_irqsave(&mfgpt_lock, flags);
+        /*
+         * Although our caller may have the read side of xtime_lock,
+         * this is now a seqlock, and we are cheating in this routine
+         * by having side effects on state that we cannot undo if
+         * there is a collision on the seqlock and our caller has to
+         * retry.  (Namely, old_jifs and old_count.)  So we must treat
+         * jiffies as volatile despite the lock.  We read jiffies
+         * before latching the timer count to guarantee that although
+         * the jiffies value might be older than the count (that is,
+         * the counter may underflow between the last point where
+         * jiffies was incremented and the point where we latch the
+         * count), it cannot be newer.
+         */
+        jifs = jiffies;
+        /* read the count */
+        count = inw(MFGPT0_CNT);
+
+        /*
+         * It's possible for count to appear to go the wrong way for this
+         * reason:
+         *
+         *  The timer counter underflows, but we haven't handled the resulting
+         *  interrupt and incremented jiffies yet.
+         *
+         * Previous attempts to handle these cases intelligently were buggy, so
+         * we just do the simple thing now.
+         */
+        if (count < old_count && jifs == old_jifs)
+                count = old_count;
+
+        old_count = count;
+        old_jifs = jifs;
+
+        spin_unlock_irqrestore(&mfgpt_lock, flags);
+
+        return (cycle_t) (jifs * COMPARE) + count;
+}
+
+static struct clocksource clocksource_mfgpt = {
+        .name = "mfgpt",
+        .rating = 120, /* Functional for real use, but not desired */
+        .read = mfgpt_read,
+        .mask = CLOCKSOURCE_MASK(32),
+        .mult = 0,
+        .shift = 22,
+};
+
+int __init init_mfgpt_clocksource(void)
+{
+        if (num_possible_cpus() > 1)    /* MFGPT does not scale! */
+                return 0;
+
+        clocksource_mfgpt.mult = clocksource_hz2mult(MFGPT_TICK_RATE, 22);
+        return clocksource_register(&clocksource_mfgpt);
+}
+
+arch_initcall(init_mfgpt_clocksource);
diff --git a/arch/mips/loongson/common/cs5536/cs5536_ohci.c b/arch/mips/loongson/common/cs5536/cs5536_ohci.c
new file mode 100644
index 000000000000..8fdb02b6e90f
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_ohci.c
@@ -0,0 +1,147 @@
+/*
+ * the OHCI Virtual Support Module of AMD CS5536
+ *
+ * Copyright (C) 2007 Lemote, Inc.
+ * Author : jlliu, liujl@lemote.com
+ *
+ * Copyright (C) 2009 Lemote, Inc.
+ * Author: Wu Zhangjin, wuzj@lemote.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <cs5536/cs5536.h>
+#include <cs5536/cs5536_pci.h>
+
+void pci_ohci_write_reg(int reg, u32 value)
+{
+        u32 hi = 0, lo = value;
+
+        switch (reg) {
+        case PCI_COMMAND:
+                _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
+                if (value & PCI_COMMAND_MASTER)
+                        hi |= PCI_COMMAND_MASTER;
+                else
+                        hi &= ~PCI_COMMAND_MASTER;
+
+                if (value & PCI_COMMAND_MEMORY)
+                        hi |= PCI_COMMAND_MEMORY;
+                else
+                        hi &= ~PCI_COMMAND_MEMORY;
+                _wrmsr(USB_MSR_REG(USB_OHCI), hi, lo);
+                break;
+        case PCI_STATUS:
+                if (value & PCI_STATUS_PARITY) {
+                        _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+                        if (lo & SB_PARE_ERR_FLAG) {
+                                lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
+                                _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
+                        }
+                }
+                break;
+        case PCI_BAR0_REG:
+                if (value == PCI_BAR_RANGE_MASK) {
+                        _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+                        lo |= SOFT_BAR_OHCI_FLAG;
+                        _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+                } else if ((value & 0x01) == 0x00) {
+                        _wrmsr(USB_MSR_REG(USB_OHCI), hi, lo);
+
+                        value &= 0xfffffff0;
+                        hi = 0x40000000 | ((value & 0xff000000) >> 24);
+                        lo = 0x000fffff | ((value & 0x00fff000) << 8);
+                        _wrmsr(GLIU_MSR_REG(GLIU_P2D_BM3), hi, lo);
+                }
+                break;
+        case PCI_OHCI_INT_REG:
+                _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
+                lo &= ~(0xf << PIC_YSEL_LOW_USB_SHIFT);
+                if (value)      /* enable all the usb interrupt in PIC */
+                        lo |= (CS5536_USB_INTR << PIC_YSEL_LOW_USB_SHIFT);
+                _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
+                break;
+        default:
+                break;
+        }
+}
+
+u32 pci_ohci_read_reg(int reg)
+{
+        u32 conf_data = 0;
+        u32 hi, lo;
+
+        switch (reg) {
+        case PCI_VENDOR_ID:
+                conf_data =
+                    CFG_PCI_VENDOR_ID(CS5536_OHCI_DEVICE_ID, CS5536_VENDOR_ID);
+                break;
+        case PCI_COMMAND:
+                _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
+                if (hi & PCI_COMMAND_MASTER)
+                        conf_data |= PCI_COMMAND_MASTER;
+                if (hi & PCI_COMMAND_MEMORY)
+                        conf_data |= PCI_COMMAND_MEMORY;
+                break;
+        case PCI_STATUS:
+                conf_data |= PCI_STATUS_66MHZ;
+                conf_data |= PCI_STATUS_FAST_BACK;
+                _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
+                if (lo & SB_PARE_ERR_FLAG)
+                        conf_data |= PCI_STATUS_PARITY;
+                conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
+                break;
+        case PCI_CLASS_REVISION:
+                _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo);
+                conf_data = lo & 0x000000ff;
+                conf_data |= (CS5536_OHCI_CLASS_CODE << 8);
+                break;
+        case PCI_CACHE_LINE_SIZE:
+                conf_data =
+                    CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
+                                            PCI_NORMAL_LATENCY_TIMER);
+                break;
+        case PCI_BAR0_REG:
+                _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
+                if (lo & SOFT_BAR_OHCI_FLAG) {
+                        conf_data = CS5536_OHCI_RANGE |
+                            PCI_BASE_ADDRESS_SPACE_MEMORY;
+                        lo &= ~SOFT_BAR_OHCI_FLAG;
+                        _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
+                } else {
+                        _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
+                        conf_data = lo & 0xffffff00;
+                        conf_data &= ~0x0000000f;       /* 32bit mem */
+                }
+                break;
+        case PCI_CARDBUS_CIS:
+                conf_data = PCI_CARDBUS_CIS_POINTER;
+                break;
+        case PCI_SUBSYSTEM_VENDOR_ID:
+                conf_data =
+                    CFG_PCI_VENDOR_ID(CS5536_OHCI_SUB_ID, CS5536_SUB_VENDOR_ID);
+                break;
+        case PCI_ROM_ADDRESS:
+                conf_data = PCI_EXPANSION_ROM_BAR;
+                break;
+        case PCI_CAPABILITY_LIST:
+                conf_data = PCI_CAPLIST_USB_POINTER;
+                break;
+        case PCI_INTERRUPT_LINE:
+                conf_data =
+                    CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR);
+                break;
+        case PCI_OHCI_INT_REG:
+                _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
+                if ((lo & 0x00000f00) == CS5536_USB_INTR)
+                        conf_data = 1;
+                break;
+        default:
+                break;
+        }
+
+        return conf_data;
+}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_pci.c b/arch/mips/loongson/common/cs5536/cs5536_pci.c
new file mode 100644
index 000000000000..e23f3d7d2c1d
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_pci.c
@@ -0,0 +1,87 @@
+/*
+ * read/write operation to the PCI config space of CS5536
+ *
+ * Copyright (C) 2007 Lemote, Inc.
+ * Author : jlliu, liujl@lemote.com
+ *
+ * Copyright (C) 2009 Lemote, Inc.
+ * Author: Wu Zhangjin, wuzj@lemote.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ *      the Virtual Support Module(VSM) for virtulizing the PCI
+ *      configure space are defined in cs5536_modulename.c respectively,
+ *
+ *      after this virtulizing, user can access the PCI configure space
+ *      directly as a normal multi-function PCI device which follows
+ *      the PCI-2.2 spec.
+ */
+
+#include <linux/types.h>
+#include <cs5536/cs5536_vsm.h>
+
+enum {
+        CS5536_FUNC_START = -1,
+        CS5536_ISA_FUNC,
+        reserved_func,
+        CS5536_IDE_FUNC,
+        CS5536_ACC_FUNC,
+        CS5536_OHCI_FUNC,
+        CS5536_EHCI_FUNC,
+        CS5536_FUNC_END,
+};
+
+static const cs5536_pci_vsm_write vsm_conf_write[] = {
+        [CS5536_ISA_FUNC]       pci_isa_write_reg,
+        [reserved_func]         NULL,
+        [CS5536_IDE_FUNC]       pci_ide_write_reg,
+        [CS5536_ACC_FUNC]       pci_acc_write_reg,
+        [CS5536_OHCI_FUNC]      pci_ohci_write_reg,
+        [CS5536_EHCI_FUNC]      pci_ehci_write_reg,
+};
+
+static const cs5536_pci_vsm_read vsm_conf_read[] = {
+        [CS5536_ISA_FUNC]       pci_isa_read_reg,
+        [reserved_func]         NULL,
+        [CS5536_IDE_FUNC]       pci_ide_read_reg,
+        [CS5536_ACC_FUNC]       pci_acc_read_reg,
+        [CS5536_OHCI_FUNC]      pci_ohci_read_reg,
+        [CS5536_EHCI_FUNC]      pci_ehci_read_reg,
+};
+
+/*
+ * write to PCI config space and transfer it to MSR write.
+ */
+void cs5536_pci_conf_write4(int function, int reg, u32 value)
+{
+        if ((function <= CS5536_FUNC_START) || (function >= CS5536_FUNC_END))
+                return;
+        if ((reg < 0) || (reg > 0x100) || ((reg & 0x03) != 0))
+                return;
+
+        if (vsm_conf_write[function] != NULL)
+                vsm_conf_write[function](reg, value);
+}
+
+/*
+ * read PCI config space and transfer it to MSR access.
+ */
+u32 cs5536_pci_conf_read4(int function, int reg)
+{
+        u32 data = 0;
+
+        if ((function <= CS5536_FUNC_START) || (function >= CS5536_FUNC_END))
+                return 0;
+        if ((reg < 0) || ((reg & 0x03) != 0))
+                return 0;
+        if (reg > 0x100)
+                return 0xffffffff;
+
+        if (vsm_conf_read[function] != NULL)
+                data = vsm_conf_read[function](reg);
+
+        return data;
+}
diff --git a/arch/mips/loongson/common/early_printk.c b/arch/mips/loongson/common/early_printk.c
index bc73edc0cfd8..23e7a8f8897f 100644
--- a/arch/mips/loongson/common/early_printk.c
+++ b/arch/mips/loongson/common/early_printk.c
@@ -1,7 +1,7 @@
 /*  early printk support
  *
  *  Copyright (c) 2009 Philippe Vachon <philippe@cowpig.ca>
- *  Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
+ *  Copyright (c) 2009 Lemote Inc.
  *  Author: Wu Zhangjin, wuzj@lemote.com
  *
  *  This program is free software; you can redistribute  it and/or modify it
@@ -12,26 +12,29 @@
 #include <linux/serial_reg.h>
 
 #include <loongson.h>
-#include <machine.h>
 
 #define PORT(base, offset) (u8 *)(base + offset)
 
-static inline unsigned int serial_in(phys_addr_t base, int offset)
+static inline unsigned int serial_in(unsigned char *base, int offset)
 {
         return readb(PORT(base, offset));
 }
 
-static inline void serial_out(phys_addr_t base, int offset, int value)
+static inline void serial_out(unsigned char *base, int offset, int value)
 {
         writeb(value, PORT(base, offset));
 }
 
 void prom_putchar(char c)
 {
-        phys_addr_t uart_base =
-                (phys_addr_t) ioremap_nocache(LOONGSON_UART_BASE, 8);
+        int timeout;
+        unsigned char *uart_base;
 
-        while ((serial_in(uart_base, UART_LSR) & UART_LSR_THRE) == 0)
+        uart_base = (unsigned char *)_loongson_uart_base;
+        timeout = 1024;
+
+        while (((serial_in(uart_base, UART_LSR) & UART_LSR_THRE) == 0) &&
+                        (timeout-- > 0))
                 ;
 
         serial_out(uart_base, UART_TX, c);
diff --git a/arch/mips/loongson/common/env.c b/arch/mips/loongson/common/env.c
index b9ef50385541..196d947d929a 100644
--- a/arch/mips/loongson/common/env.c
+++ b/arch/mips/loongson/common/env.c
@@ -17,11 +17,14 @@
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
+#include <linux/module.h>
+
 #include <asm/bootinfo.h>
 
 #include <loongson.h>
 
 unsigned long bus_clock, cpu_clock_freq;
+EXPORT_SYMBOL(cpu_clock_freq);
 unsigned long memsize, highmemsize;
 
 /* pmon passes arguments in 32bit pointers */
diff --git a/arch/mips/loongson/common/init.c b/arch/mips/loongson/common/init.c
index 3abe927422a3..a2abd9355737 100644
--- a/arch/mips/loongson/common/init.c
+++ b/arch/mips/loongson/common/init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
+ * Copyright (C) 2009 Lemote Inc.
  * Author: Wu Zhangjin, wuzj@lemote.com
  *
  * This program is free software; you can redistribute  it and/or modify it
@@ -10,19 +10,28 @@
 
 #include <linux/bootmem.h>
 
-#include <asm/bootinfo.h>
-
 #include <loongson.h>
 
+/* Loongson CPU address windows config space base address */
+unsigned long __maybe_unused _loongson_addrwincfg_base;
+
 void __init prom_init(void)
 {
-    /* init base address of io space */
+        /* init base address of io space */
         set_io_port_base((unsigned long)
-                ioremap(BONITO_PCIIO_BASE, BONITO_PCIIO_SIZE));
+                ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE));
+
+#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
+        _loongson_addrwincfg_base = (unsigned long)
+                ioremap(LOONGSON_ADDRWINCFG_BASE, LOONGSON_ADDRWINCFG_SIZE);
+#endif
 
         prom_init_cmdline();
         prom_init_env();
         prom_init_memory();
+
+        /*init the uart base address */
+        prom_init_uart_base();
 }
 
 void __init prom_free_prom_memory(void)
diff --git a/arch/mips/loongson/common/irq.c b/arch/mips/loongson/common/irq.c
index b32b4a3e5137..20e732831978 100644
--- a/arch/mips/loongson/common/irq.c
+++ b/arch/mips/loongson/common/irq.c
@@ -20,21 +20,21 @@ void bonito_irqdispatch(void)
         int i;
 
         /* workaround the IO dma problem: let cpu looping to allow DMA finish */
-        int_status = BONITO_INTISR;
+        int_status = LOONGSON_INTISR;
         if (int_status & (1 << 10)) {
                 while (int_status & (1 << 10)) {
                         udelay(1);
-                        int_status = BONITO_INTISR;
+                        int_status = LOONGSON_INTISR;
                 }
         }
 
         /* Get pending sources, masked by current enables */
-        int_status = BONITO_INTISR & BONITO_INTEN;
+        int_status = LOONGSON_INTISR & LOONGSON_INTEN;
 
         if (int_status != 0) {
                 i = __ffs(int_status);
                 int_status &= ~(1 << i);
-                do_IRQ(BONITO_IRQ_BASE + i);
+                do_IRQ(LOONGSON_IRQ_BASE + i);
         }
 }
 
@@ -60,13 +60,13 @@ void __init arch_init_irq(void)
         set_irq_trigger_mode();
 
         /* no steer */
-        BONITO_INTSTEER = 0;
+        LOONGSON_INTSTEER = 0;
 
         /*
          * Mask out all interrupt by writing "1" to all bit position in
          * the interrupt reset reg.
          */
-        BONITO_INTENCLR = ~0;
+        LOONGSON_INTENCLR = ~0;
 
         /* machine specific irq init */
         mach_init_irq();
diff --git a/arch/mips/loongson/common/machtype.c b/arch/mips/loongson/common/machtype.c
index 7b348248de7d..0ed52b3f5314 100644
--- a/arch/mips/loongson/common/machtype.c
+++ b/arch/mips/loongson/common/machtype.c
@@ -15,6 +15,9 @@
 #include <loongson.h>
 #include <machine.h>
 
+/* please ensure the length of the machtype string is less than 50 */
+#define MACHTYPE_LEN 50
+
 static const char *system_types[] = {
         [MACH_LOONGSON_UNKNOWN]         "unknown loongson machine",
         [MACH_LEMOTE_FL2E]              "lemote-fuloong-2e-box",
@@ -22,29 +25,35 @@ static const char *system_types[] = {
         [MACH_LEMOTE_ML2F7]             "lemote-mengloong-2f-7inches",
         [MACH_LEMOTE_YL2F89]            "lemote-yeeloong-2f-8.9inches",
         [MACH_DEXXON_GDIUM2F10]         "dexxon-gidum-2f-10inches",
+        [MACH_LEMOTE_NAS]               "lemote-nas-2f",
+        [MACH_LEMOTE_LL2F]              "lemote-lynloong-2f",
         [MACH_LOONGSON_END]             NULL,
 };
 
 const char *get_system_type(void)
 {
-        if (mips_machtype == MACH_UNKNOWN)
-                mips_machtype = LOONGSON_MACHTYPE;
-
         return system_types[mips_machtype];
 }
 
-static __init int machtype_setup(char *str)
+void __init prom_init_machtype(void)
 {
+        char *p, str[MACHTYPE_LEN];
         int machtype = MACH_LEMOTE_FL2E;
 
-        if (!str)
-                return -EINVAL;
+        mips_machtype = LOONGSON_MACHTYPE;
+
+        p = strstr(arcs_cmdline, "machtype=");
+        if (!p)
+                return;
+        p += strlen("machtype=");
+        strncpy(str, p, MACHTYPE_LEN);
+        p = strstr(str, " ");
+        if (p)
+                *p = '\0';
 
         for (; system_types[machtype]; machtype++)
                 if (strstr(system_types[machtype], str)) {
                         mips_machtype = machtype;
                         break;
                 }
-        return 0;
 }
-__setup("machtype=", machtype_setup);
diff --git a/arch/mips/loongson/common/mem.c b/arch/mips/loongson/common/mem.c
index e94ef158f980..ceacd092b446 100644
--- a/arch/mips/loongson/common/mem.c
+++ b/arch/mips/loongson/common/mem.c
@@ -12,15 +12,40 @@
 
 #include <loongson.h>
 #include <mem.h>
+#include <pci.h>
 
 void __init prom_init_memory(void)
 {
     add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM);
+
+    add_memory_region(memsize << 20, LOONGSON_PCI_MEM_START - (memsize <<
+                            20), BOOT_MEM_RESERVED);
+#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
+        {
+                int bit;
+
+                bit = fls(memsize + highmemsize);
+                if (bit != ffs(memsize + highmemsize))
+                        bit += 20;
+                else
+                        bit = bit + 20 - 1;
+
+                /* set cpu window3 to map CPU to DDR: 2G -> 2G */
+                LOONGSON_ADDRWIN_CPUTODDR(ADDRWIN_WIN3, 0x80000000ul,
+                                          0x80000000ul, (1 << bit));
+                mmiowb();
+        }
+#endif /* !CONFIG_CPU_SUPPORTS_ADDRWINCFG */
+
 #ifdef CONFIG_64BIT
-    if (highmemsize > 0)
-        add_memory_region(LOONGSON_HIGHMEM_START,
-                highmemsize << 20, BOOT_MEM_RAM);
-#endif /* CONFIG_64BIT */
+        if (highmemsize > 0)
+                add_memory_region(LOONGSON_HIGHMEM_START,
+                                  highmemsize << 20, BOOT_MEM_RAM);
+
+        add_memory_region(LOONGSON_PCI_MEM_END + 1, LOONGSON_HIGHMEM_START -
+                          LOONGSON_PCI_MEM_END - 1, BOOT_MEM_RESERVED);
+
+#endif /* !CONFIG_64BIT */
 }
 
 /* override of arch/mips/mm/cache.c: __uncached_access */
@@ -33,3 +58,61 @@ int __uncached_access(struct file *file, unsigned long addr)
                 ((addr >= LOONGSON_MMIO_MEM_START) &&
                  (addr < LOONGSON_MMIO_MEM_END));
 }
+
+#ifdef CONFIG_CPU_SUPPORTS_UNCACHED_ACCELERATED
+
+#include <linux/pci.h>
+#include <linux/sched.h>
+#include <asm/current.h>
+
+static unsigned long uca_start, uca_end;
+
+pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
+                              unsigned long size, pgprot_t vma_prot)
+{
+        unsigned long offset = pfn << PAGE_SHIFT;
+        unsigned long end = offset + size;
+
+        if (__uncached_access(file, offset)) {
+                if (((uca_start && offset) >= uca_start) &&
+                    (end <= uca_end))
+                        return __pgprot((pgprot_val(vma_prot) &
+                                         ~_CACHE_MASK) |
+                                        _CACHE_UNCACHED_ACCELERATED);
+                else
+                        return pgprot_noncached(vma_prot);
+        }
+        return vma_prot;
+}
+
+static int __init find_vga_mem_init(void)
+{
+        struct pci_dev *dev = 0;
+        struct resource *r;
+        int idx;
+
+        if (uca_start)
+                return 0;
+
+        for_each_pci_dev(dev) {
+                if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {
+                        for (idx = 0; idx < PCI_NUM_RESOURCES; idx++) {
+                                r = &dev->resource[idx];
+                                if (!r->start && r->end)
+                                        continue;
+                                if (r->flags & IORESOURCE_IO)
+                                        continue;
+                                if (r->flags & IORESOURCE_MEM) {
+                                        uca_start = r->start;
+                                        uca_end = r->end;
+                                        return 0;
+                                }
+                        }
+                }
+        }
+
+        return 0;
+}
+
+late_initcall(find_vga_mem_init);
+#endif /* !CONFIG_CPU_SUPPORTS_UNCACHED_ACCELERATED */
diff --git a/arch/mips/loongson/common/pci.c b/arch/mips/loongson/common/pci.c
index a3a4abfb6c9a..31d8c5ecd16c 100644
--- a/arch/mips/loongson/common/pci.c
+++ b/arch/mips/loongson/common/pci.c
@@ -27,7 +27,7 @@ static struct resource loongson_pci_io_resource = {
 };
 
 static struct pci_controller  loongson_pci_controller = {
-        .pci_ops        = &bonito64_pci_ops,
+        .pci_ops        = &loongson_pci_ops,
         .io_resource    = &loongson_pci_io_resource,
         .mem_resource   = &loongson_pci_mem_resource,
         .mem_offset     = 0x00000000UL,
@@ -44,15 +44,15 @@ static void __init setup_pcimap(void)
          * pcimap: PCI_MAP2  PCI_Mem_Lo2 PCI_Mem_Lo1 PCI_Mem_Lo0
          *           [<2G]   [384M,448M] [320M,384M] [0M,64M]
          */
-        BONITO_PCIMAP = BONITO_PCIMAP_PCIMAP_2 |
-                BONITO_PCIMAP_WIN(2, BONITO_PCILO2_BASE) |
-                BONITO_PCIMAP_WIN(1, BONITO_PCILO1_BASE) |
-                BONITO_PCIMAP_WIN(0, 0);
+        LOONGSON_PCIMAP = LOONGSON_PCIMAP_PCIMAP_2 |
+                LOONGSON_PCIMAP_WIN(2, LOONGSON_PCILO2_BASE) |
+                LOONGSON_PCIMAP_WIN(1, LOONGSON_PCILO1_BASE) |
+                LOONGSON_PCIMAP_WIN(0, 0);
 
         /*
          * PCI-DMA to local mapping: [2G,2G+256M] -> [0M,256M]
          */
-        BONITO_PCIBASE0 = 0x80000000ul;   /* base: 2G -> mmap: 0M */
+        LOONGSON_PCIBASE0 = 0x80000000ul;   /* base: 2G -> mmap: 0M */
         /* size: 256M, burst transmission, pre-fetch enable, 64bit */
         LOONGSON_PCI_HIT0_SEL_L = 0xc000000cul;
         LOONGSON_PCI_HIT0_SEL_H = 0xfffffffful;
@@ -67,6 +67,14 @@ static void __init setup_pcimap(void)
         /* can not change gnt to break pci transfer when device's gnt not
         deassert for some broken device */
         LOONGSON_PXARB_CFG = 0x00fe0105ul;
+
+#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
+        /*
+         * set cpu addr window2 to map CPU address space to PCI address space
+         */
+        LOONGSON_ADDRWIN_CPUTOPCI(ADDRWIN_WIN2, LOONGSON_CPU_MEM_SRC,
+                LOONGSON_PCI_MEM_DST, MMAP_CPUTOPCI_SIZE);
+#endif
 }
 
 static int __init pcibios_init(void)
diff --git a/arch/mips/loongson/common/platform.c b/arch/mips/loongson/common/platform.c
new file mode 100644
index 000000000000..be81777eb94d
--- /dev/null
+++ b/arch/mips/loongson/common/platform.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2009 Lemote Inc.
+ * Author: Wu Zhangjin, wuzj@lemote.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/platform_device.h>
+
+static struct platform_device loongson2_cpufreq_device = {
+        .name = "loongson2_cpufreq",
+        .id = -1,
+};
+
+static int __init loongson2_cpufreq_init(void)
+{
+        struct cpuinfo_mips *c = &current_cpu_data;
+
+        /* Only 2F revision and it's successors support CPUFreq */
+        if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_LOONGSON2F)
+                return platform_device_register(&loongson2_cpufreq_device);
+
+        return -ENODEV;
+}
+
+arch_initcall(loongson2_cpufreq_init);
diff --git a/arch/mips/loongson/common/pm.c b/arch/mips/loongson/common/pm.c
new file mode 100644
index 000000000000..b625fec8a4d5
--- /dev/null
+++ b/arch/mips/loongson/common/pm.c
@@ -0,0 +1,161 @@
+/*
+ * loongson-specific suspend support
+ *
+ *  Copyright (C) 2009 Lemote Inc.
+ *  Author: Wu Zhangjin <wuzj@lemote.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/suspend.h>
+#include <linux/interrupt.h>
+#include <linux/pm.h>
+
+#include <asm/i8259.h>
+#include <asm/mipsregs.h>
+
+#include <loongson.h>
+
+static unsigned int __maybe_unused cached_master_mask;  /* i8259A */
+static unsigned int __maybe_unused cached_slave_mask;
+static unsigned int __maybe_unused cached_bonito_irq_mask; /* bonito */
+
+void arch_suspend_disable_irqs(void)
+{
+        /* disable all mips events */
+        local_irq_disable();
+
+#ifdef CONFIG_I8259
+        /* disable all events of i8259A */
+        cached_slave_mask = inb(PIC_SLAVE_IMR);
+        cached_master_mask = inb(PIC_MASTER_IMR);
+
+        outb(0xff, PIC_SLAVE_IMR);
+        inb(PIC_SLAVE_IMR);
+        outb(0xff, PIC_MASTER_IMR);
+        inb(PIC_MASTER_IMR);
+#endif
+        /* disable all events of bonito */
+        cached_bonito_irq_mask = LOONGSON_INTEN;
+        LOONGSON_INTENCLR = 0xffff;
+        (void)LOONGSON_INTENCLR;
+}
+
+void arch_suspend_enable_irqs(void)
+{
+        /* enable all mips events */
+        local_irq_enable();
+#ifdef CONFIG_I8259
+        /* only enable the cached events of i8259A */
+        outb(cached_slave_mask, PIC_SLAVE_IMR);
+        outb(cached_master_mask, PIC_MASTER_IMR);
+#endif
+        /* enable all cached events of bonito */
+        LOONGSON_INTENSET = cached_bonito_irq_mask;
+        (void)LOONGSON_INTENSET;
+}
+
+/*
+ * Setup the board-specific events for waking up loongson from wait mode
+ */
+void __weak setup_wakeup_events(void)
+{
+}
+
+/*
+ * Check wakeup events
+ */
+int __weak wakeup_loongson(void)
+{
+        return 1;
+}
+
+/*
+ * If the events are really what we want to wakeup the CPU, wake it up
+ * otherwise put the CPU asleep again.
+ */
+static void wait_for_wakeup_events(void)
+{
+        while (!wakeup_loongson())
+                LOONGSON_CHIPCFG0 &= ~0x7;
+}
+
+/*
+ * Stop all perf counters
+ *
+ * $24 is the control register of Loongson perf counter
+ */
+static inline void stop_perf_counters(void)
+{
+        __write_64bit_c0_register($24, 0, 0);
+}
+
+
+static void loongson_suspend_enter(void)
+{
+        static unsigned int cached_cpu_freq;
+
+        /* setup wakeup events via enabling the IRQs */
+        setup_wakeup_events();
+
+        stop_perf_counters();
+
+        cached_cpu_freq = LOONGSON_CHIPCFG0;
+
+        /* Put CPU into wait mode */
+        LOONGSON_CHIPCFG0 &= ~0x7;
+
+        /* wait for the given events to wakeup cpu from wait mode */
+        wait_for_wakeup_events();
+
+        LOONGSON_CHIPCFG0 = cached_cpu_freq;
+        mmiowb();
+}
+
+void __weak mach_suspend(void)
+{
+}
+
+void __weak mach_resume(void)
+{
+}
+
+static int loongson_pm_enter(suspend_state_t state)
+{
+        mach_suspend();
+
+        /* processor specific suspend */
+        loongson_suspend_enter();
+
+        mach_resume();
+
+        return 0;
+}
+
+static int loongson_pm_valid_state(suspend_state_t state)
+{
+        switch (state) {
+        case PM_SUSPEND_ON:
+        case PM_SUSPEND_STANDBY:
+        case PM_SUSPEND_MEM:
+                return 1;
+
+        default:
+                return 0;
+        }
+}
+
+static struct platform_suspend_ops loongson_pm_ops = {
+        .valid  = loongson_pm_valid_state,
+        .enter  = loongson_pm_enter,
+};
+
+static int __init loongson_pm_init(void)
+{
+        suspend_set_ops(&loongson_pm_ops);
+
+        return 0;
+}
+arch_initcall(loongson_pm_init);
diff --git a/arch/mips/loongson/common/reset.c b/arch/mips/loongson/common/reset.c
index 97e918251edd..d57f1719da95 100644
--- a/arch/mips/loongson/common/reset.c
+++ b/arch/mips/loongson/common/reset.c
@@ -22,7 +22,7 @@ static void loongson_restart(char *command)
         mach_prepare_reboot();
 
         /* reboot via jumping to boot base address */
-        ((void (*)(void))ioremap_nocache(BONITO_BOOT_BASE, 4)) ();
+        ((void (*)(void))ioremap_nocache(LOONGSON_BOOT_BASE, 4)) ();
 }
 
 static void loongson_halt(void)
diff --git a/arch/mips/loongson/common/serial.c b/arch/mips/loongson/common/serial.c
new file mode 100644
index 000000000000..23b66a5f88cb
--- /dev/null
+++ b/arch/mips/loongson/common/serial.c
@@ -0,0 +1,76 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
+ *
+ * Copyright (C) 2009 Lemote, Inc.
+ * Author: Yan hua (yanhua@lemote.com)
+ * Author: Wu Zhangjin (wuzj@lemote.com)
+ */
+
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/serial_8250.h>
+
+#include <asm/bootinfo.h>
+
+#include <loongson.h>
+#include <machine.h>
+
+#define PORT(int)                       \
+{                                                               \
+        .irq            = int,                                  \
+        .uartclk        = 1843200,                              \
+        .iotype         = UPIO_PORT,                            \
+        .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,    \
+        .regshift       = 0,                                    \
+}
+
+#define PORT_M(int)                             \
+{                                                               \
+        .irq            = MIPS_CPU_IRQ_BASE + (int),            \
+        .uartclk        = 3686400,                              \
+        .iotype         = UPIO_MEM,                             \
+        .membase        = (void __iomem *)NULL,                 \
+        .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,    \
+        .regshift       = 0,                                    \
+}
+
+static struct plat_serial8250_port uart8250_data[][2] = {
+        [MACH_LOONGSON_UNKNOWN]         {},
+        [MACH_LEMOTE_FL2E]              {PORT(4), {} },
+        [MACH_LEMOTE_FL2F]              {PORT(3), {} },
+        [MACH_LEMOTE_ML2F7]             {PORT_M(3), {} },
+        [MACH_LEMOTE_YL2F89]            {PORT_M(3), {} },
+        [MACH_DEXXON_GDIUM2F10]         {PORT_M(3), {} },
+        [MACH_LEMOTE_NAS]               {PORT_M(3), {} },
+        [MACH_LEMOTE_LL2F]              {PORT(3), {} },
+        [MACH_LOONGSON_END]             {},
+};
+
+static struct platform_device uart8250_device = {
+        .name = "serial8250",
+        .id = PLAT8250_DEV_PLATFORM,
+};
+
+static int __init serial_init(void)
+{
+        unsigned char iotype;
+
+        iotype = uart8250_data[mips_machtype][0].iotype;
+
+        if (UPIO_MEM == iotype)
+                uart8250_data[mips_machtype][0].membase =
+                        (void __iomem *)_loongson_uart_base;
+        else if (UPIO_PORT == iotype)
+                uart8250_data[mips_machtype][0].iobase =
+                    loongson_uart_base - LOONGSON_PCIIO_BASE;
+
+        uart8250_device.dev.platform_data = uart8250_data[mips_machtype];
+
+        return platform_device_register(&uart8250_device);
+}
+
+device_initcall(serial_init);
diff --git a/arch/mips/loongson/common/time.c b/arch/mips/loongson/common/time.c
index 6e08c8270abe..35f0b66a94f5 100644
--- a/arch/mips/loongson/common/time.c
+++ b/arch/mips/loongson/common/time.c
@@ -14,11 +14,14 @@
 #include <asm/time.h>
 
 #include <loongson.h>
+#include <cs5536/cs5536_mfgpt.h>
 
 void __init plat_time_init(void)
 {
         /* setup mips r4k timer */
         mips_hpt_frequency = cpu_clock_freq / 2;
+
+        setup_mfgpt0_timer();
 }
 
 void read_persistent_clock(struct timespec *ts)
diff --git a/arch/mips/loongson/common/uart_base.c b/arch/mips/loongson/common/uart_base.c
new file mode 100644
index 000000000000..78ff66ae749e
--- /dev/null
+++ b/arch/mips/loongson/common/uart_base.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2009 Lemote Inc.
+ * Author: Wu Zhangjin, wuzj@lemote.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/module.h>
+#include <asm/bootinfo.h>
+
+#include <loongson.h>
+
+/* ioremapped */
+unsigned long _loongson_uart_base;
+EXPORT_SYMBOL(_loongson_uart_base);
+/* raw */
+unsigned long loongson_uart_base;
+EXPORT_SYMBOL(loongson_uart_base);
+
+void prom_init_loongson_uart_base(void)
+{
+        switch (mips_machtype) {
+        case MACH_LEMOTE_FL2E:
+                loongson_uart_base = LOONGSON_PCIIO_BASE + 0x3f8;
+                break;
+        case MACH_LEMOTE_FL2F:
+        case MACH_LEMOTE_LL2F:
+                loongson_uart_base = LOONGSON_PCIIO_BASE + 0x2f8;
+                break;
+        case MACH_LEMOTE_ML2F7:
+        case MACH_LEMOTE_YL2F89:
+        case MACH_DEXXON_GDIUM2F10:
+        case MACH_LEMOTE_NAS:
+        default:
+                /* The CPU provided serial port */
+                loongson_uart_base = LOONGSON_LIO1_BASE + 0x3f8;
+                break;
+        }
+
+        _loongson_uart_base =
+                (unsigned long)ioremap_nocache(loongson_uart_base, 8);
+}
diff --git a/arch/mips/loongson/fuloong-2e/irq.c b/arch/mips/loongson/fuloong-2e/irq.c
index 7888cf69424a..320e9379bdd7 100644
--- a/arch/mips/loongson/fuloong-2e/irq.c
+++ b/arch/mips/loongson/fuloong-2e/irq.c
@@ -47,8 +47,8 @@ static struct irqaction cascade_irqaction = {
 void __init set_irq_trigger_mode(void)
 {
         /* most bonito irq should be level triggered */
-        BONITO_INTEDGE = BONITO_ICU_SYSTEMERR | BONITO_ICU_MASTERERR |
-            BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES;
+        LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR |
+            LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES;
 }
 
 void __init mach_init_irq(void)
diff --git a/arch/mips/loongson/fuloong-2e/reset.c b/arch/mips/loongson/fuloong-2e/reset.c
index 677fe186db95..fc16c677d476 100644
--- a/arch/mips/loongson/fuloong-2e/reset.c
+++ b/arch/mips/loongson/fuloong-2e/reset.c
@@ -14,8 +14,8 @@
 
 void mach_prepare_reboot(void)
 {
-        BONITO_BONGENCFG &= ~(1 << 2);
-        BONITO_BONGENCFG |= (1 << 2);
+        LOONGSON_GENCFG &= ~(1 << 2);
+        LOONGSON_GENCFG |= (1 << 2);
 }
 
 void mach_prepare_shutdown(void)
diff --git a/arch/mips/loongson/lemote-2f/Makefile b/arch/mips/loongson/lemote-2f/Makefile
new file mode 100644
index 000000000000..4d84b27dc41b
--- /dev/null
+++ b/arch/mips/loongson/lemote-2f/Makefile
@@ -0,0 +1,11 @@
+#
+# Makefile for lemote loongson2f family machines
+#
+
+obj-y += irq.o reset.o ec_kb3310b.o
+
+#
+# Suspend Support
+#
+
+obj-$(CONFIG_LOONGSON_SUSPEND) += pm.o
diff --git a/arch/mips/loongson/lemote-2f/ec_kb3310b.c b/arch/mips/loongson/lemote-2f/ec_kb3310b.c
new file mode 100644
index 000000000000..4d84111a2cd4
--- /dev/null
+++ b/arch/mips/loongson/lemote-2f/ec_kb3310b.c
@@ -0,0 +1,130 @@
+/*
+ * Basic KB3310B Embedded Controller support for the YeeLoong 2F netbook
+ *
+ *  Copyright (C) 2008 Lemote Inc.
+ *  Author: liujl <liujl@lemote.com>, 2008-04-20
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+
+#include "ec_kb3310b.h"
+
+static DEFINE_SPINLOCK(index_access_lock);
+static DEFINE_SPINLOCK(port_access_lock);
+
+unsigned char ec_read(unsigned short addr)
+{
+        unsigned char value;
+        unsigned long flags;
+
+        spin_lock_irqsave(&index_access_lock, flags);
+        outb((addr & 0xff00) >> 8, EC_IO_PORT_HIGH);
+        outb((addr & 0x00ff), EC_IO_PORT_LOW);
+        value = inb(EC_IO_PORT_DATA);
+        spin_unlock_irqrestore(&index_access_lock, flags);
+
+        return value;
+}
+EXPORT_SYMBOL_GPL(ec_read);
+
+void ec_write(unsigned short addr, unsigned char val)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&index_access_lock, flags);
+        outb((addr & 0xff00) >> 8, EC_IO_PORT_HIGH);
+        outb((addr & 0x00ff), EC_IO_PORT_LOW);
+        outb(val, EC_IO_PORT_DATA);
+        /*  flush the write action */
+        inb(EC_IO_PORT_DATA);
+        spin_unlock_irqrestore(&index_access_lock, flags);
+
+        return;
+}
+EXPORT_SYMBOL_GPL(ec_write);
+
+/*
+ * This function is used for EC command writes and corresponding status queries.
+ */
+int ec_query_seq(unsigned char cmd)
+{
+        int timeout;
+        unsigned char status;
+        unsigned long flags;
+        int ret = 0;
+
+        spin_lock_irqsave(&port_access_lock, flags);
+
+        /* make chip goto reset mode */
+        udelay(EC_REG_DELAY);
+        outb(cmd, EC_CMD_PORT);
+        udelay(EC_REG_DELAY);
+
+        /* check if the command is received by ec */
+        timeout = EC_CMD_TIMEOUT;
+        status = inb(EC_STS_PORT);
+        while (timeout-- && (status & (1 << 1))) {
+                status = inb(EC_STS_PORT);
+                udelay(EC_REG_DELAY);
+        }
+
+        if (timeout <= 0) {
+                printk(KERN_ERR "%s: deadable error : timeout...\n", __func__);
+                ret = -EINVAL;
+        } else
+                printk(KERN_INFO
+                           "(%x/%d)ec issued command %d status : 0x%x\n",
+                           timeout, EC_CMD_TIMEOUT - timeout, cmd, status);
+
+        spin_unlock_irqrestore(&port_access_lock, flags);
+
+        return ret;
+}
+EXPORT_SYMBOL_GPL(ec_query_seq);
+
+/*
+ * Send query command to EC to get the proper event number
+ */
+int ec_query_event_num(void)
+{
+        return ec_query_seq(CMD_GET_EVENT_NUM);
+}
+EXPORT_SYMBOL(ec_query_event_num);
+
+/*
+ * Get event number from EC
+ *
+ * NOTE: This routine must follow the query_event_num function in the
+ * interrupt.
+ */
+int ec_get_event_num(void)
+{
+        int timeout = 100;
+        unsigned char value;
+        unsigned char status;
+
+        udelay(EC_REG_DELAY);
+        status = inb(EC_STS_PORT);
+        udelay(EC_REG_DELAY);
+        while (timeout-- && !(status & (1 << 0))) {
+                status = inb(EC_STS_PORT);
+                udelay(EC_REG_DELAY);
+        }
+        if (timeout <= 0) {
+                pr_info("%s: get event number timeout.\n", __func__);
+
+                return -EINVAL;
+        }
+        value = inb(EC_DAT_PORT);
+        udelay(EC_REG_DELAY);
+
+        return value;
+}
+EXPORT_SYMBOL(ec_get_event_num);
diff --git a/arch/mips/loongson/lemote-2f/ec_kb3310b.h b/arch/mips/loongson/lemote-2f/ec_kb3310b.h
new file mode 100644
index 000000000000..1595a21b315b
--- /dev/null
+++ b/arch/mips/loongson/lemote-2f/ec_kb3310b.h
@@ -0,0 +1,188 @@
+/*
+ * KB3310B Embedded Controller
+ *
+ *  Copyright (C) 2008 Lemote Inc.
+ *  Author: liujl <liujl@lemote.com>, 2008-03-14
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _EC_KB3310B_H
+#define _EC_KB3310B_H
+
+extern unsigned char ec_read(unsigned short addr);
+extern void ec_write(unsigned short addr, unsigned char val);
+extern int ec_query_seq(unsigned char cmd);
+extern int ec_query_event_num(void);
+extern int ec_get_event_num(void);
+
+typedef int (*sci_handler) (int status);
+extern sci_handler yeeloong_report_lid_status;
+
+#define SCI_IRQ_NUM 0x0A
+
+/*
+ * The following registers are determined by the EC index configuration.
+ * 1, fill the PORT_HIGH as EC register high part.
+ * 2, fill the PORT_LOW as EC register low part.
+ * 3, fill the PORT_DATA as EC register write data or get the data from it.
+ */
+#define EC_IO_PORT_HIGH 0x0381
+#define EC_IO_PORT_LOW  0x0382
+#define EC_IO_PORT_DATA 0x0383
+
+/*
+ * EC delay time is 500us for register and status access
+ */
+#define EC_REG_DELAY    500     /* unit : us */
+#define EC_CMD_TIMEOUT  0x1000
+
+/*
+ * EC access port for SCI communication
+ */
+#define EC_CMD_PORT             0x66
+#define EC_STS_PORT             0x66
+#define EC_DAT_PORT             0x62
+#define CMD_INIT_IDLE_MODE      0xdd
+#define CMD_EXIT_IDLE_MODE      0xdf
+#define CMD_INIT_RESET_MODE     0xd8
+#define CMD_REBOOT_SYSTEM       0x8c
+#define CMD_GET_EVENT_NUM       0x84
+#define CMD_PROGRAM_PIECE       0xda
+
+/* temperature & fan registers */
+#define REG_TEMPERATURE_VALUE   0xF458
+#define REG_FAN_AUTO_MAN_SWITCH 0xF459
+#define BIT_FAN_AUTO            0
+#define BIT_FAN_MANUAL          1
+#define REG_FAN_CONTROL         0xF4D2
+#define BIT_FAN_CONTROL_ON      (1 << 0)
+#define BIT_FAN_CONTROL_OFF     (0 << 0)
+#define REG_FAN_STATUS          0xF4DA
+#define BIT_FAN_STATUS_ON       (1 << 0)
+#define BIT_FAN_STATUS_OFF      (0 << 0)
+#define REG_FAN_SPEED_HIGH      0xFE22
+#define REG_FAN_SPEED_LOW       0xFE23
+#define REG_FAN_SPEED_LEVEL     0xF4CC
+/* fan speed divider */
+#define FAN_SPEED_DIVIDER       480000  /* (60*1000*1000/62.5/2)*/
+
+/* battery registers */
+#define REG_BAT_DESIGN_CAP_HIGH         0xF77D
+#define REG_BAT_DESIGN_CAP_LOW          0xF77E
+#define REG_BAT_FULLCHG_CAP_HIGH        0xF780
+#define REG_BAT_FULLCHG_CAP_LOW         0xF781
+#define REG_BAT_DESIGN_VOL_HIGH         0xF782
+#define REG_BAT_DESIGN_VOL_LOW          0xF783
+#define REG_BAT_CURRENT_HIGH            0xF784
+#define REG_BAT_CURRENT_LOW             0xF785
+#define REG_BAT_VOLTAGE_HIGH            0xF786
+#define REG_BAT_VOLTAGE_LOW             0xF787
+#define REG_BAT_TEMPERATURE_HIGH        0xF788
+#define REG_BAT_TEMPERATURE_LOW         0xF789
+#define REG_BAT_RELATIVE_CAP_HIGH       0xF492
+#define REG_BAT_RELATIVE_CAP_LOW        0xF493
+#define REG_BAT_VENDOR                  0xF4C4
+#define FLAG_BAT_VENDOR_SANYO           0x01
+#define FLAG_BAT_VENDOR_SIMPLO          0x02
+#define REG_BAT_CELL_COUNT              0xF4C6
+#define FLAG_BAT_CELL_3S1P              0x03
+#define FLAG_BAT_CELL_3S2P              0x06
+#define REG_BAT_CHARGE                  0xF4A2
+#define FLAG_BAT_CHARGE_DISCHARGE       0x01
+#define FLAG_BAT_CHARGE_CHARGE          0x02
+#define FLAG_BAT_CHARGE_ACPOWER         0x00
+#define REG_BAT_STATUS                  0xF4B0
+#define BIT_BAT_STATUS_LOW              (1 << 5)
+#define BIT_BAT_STATUS_DESTROY          (1 << 2)
+#define BIT_BAT_STATUS_FULL             (1 << 1)
+#define BIT_BAT_STATUS_IN               (1 << 0)
+#define REG_BAT_CHARGE_STATUS           0xF4B1
+#define BIT_BAT_CHARGE_STATUS_OVERTEMP  (1 << 2)
+#define BIT_BAT_CHARGE_STATUS_PRECHG    (1 << 1)
+#define REG_BAT_STATE                   0xF482
+#define BIT_BAT_STATE_CHARGING          (1 << 1)
+#define BIT_BAT_STATE_DISCHARGING       (1 << 0)
+#define REG_BAT_POWER                   0xF440
+#define BIT_BAT_POWER_S3                (1 << 2)
+#define BIT_BAT_POWER_ON                (1 << 1)
+#define BIT_BAT_POWER_ACIN              (1 << 0)
+
+/* other registers */
+/* Audio: rd/wr */
+#define REG_AUDIO_VOLUME        0xF46C
+#define REG_AUDIO_MUTE          0xF4E7
+#define REG_AUDIO_BEEP          0xF4D0
+/* USB port power or not: rd/wr */
+#define REG_USB0_FLAG           0xF461
+#define REG_USB1_FLAG           0xF462
+#define REG_USB2_FLAG           0xF463
+#define BIT_USB_FLAG_ON         1
+#define BIT_USB_FLAG_OFF        0
+/* LID */
+#define REG_LID_DETECT          0xF4BD
+#define BIT_LID_DETECT_ON       1
+#define BIT_LID_DETECT_OFF      0
+/* CRT */
+#define REG_CRT_DETECT          0xF4AD
+#define BIT_CRT_DETECT_PLUG     1
+#define BIT_CRT_DETECT_UNPLUG   0
+/* LCD backlight brightness adjust: 9 levels */
+#define REG_DISPLAY_BRIGHTNESS  0xF4F5
+/* Black screen Status */
+#define BIT_DISPLAY_LCD_ON      1
+#define BIT_DISPLAY_LCD_OFF     0
+/* LCD backlight control: off/restore */
+#define REG_BACKLIGHT_CTRL      0xF7BD
+#define BIT_BACKLIGHT_ON        1
+#define BIT_BACKLIGHT_OFF       0
+/* Reset the machine auto-clear: rd/wr */
+#define REG_RESET               0xF4EC
+#define BIT_RESET_ON            1
+/* Light the led: rd/wr */
+#define REG_LED                 0xF4C8
+#define BIT_LED_RED_POWER       (1 << 0)
+#define BIT_LED_ORANGE_POWER    (1 << 1)
+#define BIT_LED_GREEN_CHARGE    (1 << 2)
+#define BIT_LED_RED_CHARGE      (1 << 3)
+#define BIT_LED_NUMLOCK         (1 << 4)
+/* Test led mode, all led on/off */
+#define REG_LED_TEST            0xF4C2
+#define BIT_LED_TEST_IN         1
+#define BIT_LED_TEST_OUT        0
+/* Camera on/off */
+#define REG_CAMERA_STATUS       0xF46A
+#define BIT_CAMERA_STATUS_ON    1
+#define BIT_CAMERA_STATUS_OFF   0
+#define REG_CAMERA_CONTROL      0xF7B7
+#define BIT_CAMERA_CONTROL_OFF  0
+#define BIT_CAMERA_CONTROL_ON   1
+/* Wlan Status */
+#define REG_WLAN                0xF4FA
+#define BIT_WLAN_ON             1
+#define BIT_WLAN_OFF            0
+#define REG_DISPLAY_LCD         0xF79F
+
+/* SCI Event Number from EC */
+enum {
+        EVENT_LID = 0x23,       /*  LID open/close */
+        EVENT_DISPLAY_TOGGLE,   /*  Fn+F3 for display switch */
+        EVENT_SLEEP,            /*  Fn+F1 for entering sleep mode */
+        EVENT_OVERTEMP,         /*  Over-temperature happened */
+        EVENT_CRT_DETECT,       /*  CRT is connected */
+        EVENT_CAMERA,           /*  Camera on/off */
+        EVENT_USB_OC2,          /*  USB2 Over Current occurred */
+        EVENT_USB_OC0,          /*  USB0 Over Current occurred */
+        EVENT_BLACK_SCREEN,     /*  Turn on/off backlight */
+        EVENT_AUDIO_MUTE,       /*  Mute on/off */
+        EVENT_DISPLAY_BRIGHTNESS,/* LCD backlight brightness adjust */
+        EVENT_AC_BAT,           /*  AC & Battery relative issue */
+        EVENT_AUDIO_VOLUME,     /*  Volume adjust */
+        EVENT_WLAN,             /*  Wlan on/off */
+        EVENT_END
+};
+
+#endif /* !_EC_KB3310B_H */
diff --git a/arch/mips/loongson/lemote-2f/irq.c b/arch/mips/loongson/lemote-2f/irq.c
new file mode 100644
index 000000000000..77d32f9cf31e
--- /dev/null
+++ b/arch/mips/loongson/lemote-2f/irq.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) 2007 Lemote Inc.
+ * Author: Fuxin Zhang, zhangfx@lemote.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/module.h>
+
+#include <asm/irq_cpu.h>
+#include <asm/i8259.h>
+#include <asm/mipsregs.h>
+
+#include <loongson.h>
+#include <machine.h>
+
+#define LOONGSON_TIMER_IRQ      (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */
+#define LOONGSON_PERFCNT_IRQ    (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
+#define LOONGSON_NORTH_BRIDGE_IRQ       (MIPS_CPU_IRQ_BASE + 6) /* bonito */
+#define LOONGSON_UART_IRQ       (MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */
+#define LOONGSON_SOUTH_BRIDGE_IRQ       (MIPS_CPU_IRQ_BASE + 2) /* i8259 */
+
+#define LOONGSON_INT_BIT_INT0           (1 << 11)
+#define LOONGSON_INT_BIT_INT1           (1 << 12)
+
+/*
+ * The generic i8259_irq() make the kernel hang on booting.  Since we cannot
+ * get the irq via the IRR directly, we access the ISR instead.
+ */
+int mach_i8259_irq(void)
+{
+        int irq, isr;
+
+        irq = -1;
+
+        if ((LOONGSON_INTISR & LOONGSON_INTEN) & LOONGSON_INT_BIT_INT0) {
+                spin_lock(&i8259A_lock);
+                isr = inb(PIC_MASTER_CMD) &
+                        ~inb(PIC_MASTER_IMR) & ~(1 << PIC_CASCADE_IR);
+                if (!isr)
+                        isr = (inb(PIC_SLAVE_CMD) & ~inb(PIC_SLAVE_IMR)) << 8;
+                irq = ffs(isr) - 1;
+                if (unlikely(irq == 7)) {
+                        /*
+                         * This may be a spurious interrupt.
+                         *
+                         * Read the interrupt status register (ISR). If the most
+                         * significant bit is not set then there is no valid
+                         * interrupt.
+                         */
+                        outb(0x0B, PIC_MASTER_ISR);     /* ISR register */
+                        if (~inb(PIC_MASTER_ISR) & 0x80)
+                                irq = -1;
+                }
+                spin_unlock(&i8259A_lock);
+        }
+
+        return irq;
+}
+EXPORT_SYMBOL(mach_i8259_irq);
+
+static void i8259_irqdispatch(void)
+{
+        int irq;
+
+        irq = mach_i8259_irq();
+        if (irq >= 0)
+                do_IRQ(irq);
+        else
+                spurious_interrupt();
+}
+
+void mach_irq_dispatch(unsigned int pending)
+{
+        if (pending & CAUSEF_IP7)
+                do_IRQ(LOONGSON_TIMER_IRQ);
+        else if (pending & CAUSEF_IP6) {        /* North Bridge, Perf counter */
+#ifdef CONFIG_OPROFILE
+                do_IRQ(LOONGSON2_PERFCNT_IRQ);
+#endif
+                bonito_irqdispatch();
+        } else if (pending & CAUSEF_IP3)        /* CPU UART */
+                do_IRQ(LOONGSON_UART_IRQ);
+        else if (pending & CAUSEF_IP2)  /* South Bridge */
+                i8259_irqdispatch();
+        else
+                spurious_interrupt();
+}
+
+void __init set_irq_trigger_mode(void)
+{
+        /* setup cs5536 as high level trigger */
+        LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1;
+        LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1);
+}
+
+static irqreturn_t ip6_action(int cpl, void *dev_id)
+{
+        return IRQ_HANDLED;
+}
+
+struct irqaction ip6_irqaction = {
+        .handler = ip6_action,
+        .name = "cascade",
+        .flags = IRQF_SHARED,
+};
+
+struct irqaction cascade_irqaction = {
+        .handler = no_action,
+        .name = "cascade",
+};
+
+void __init mach_init_irq(void)
+{
+        /* init all controller
+         *   0-15         ------> i8259 interrupt
+         *   16-23        ------> mips cpu interrupt
+         *   32-63        ------> bonito irq
+         */
+
+        /* Sets the first-level interrupt dispatcher. */
+        mips_cpu_irq_init();
+        init_i8259_irqs();
+        bonito_irq_init();
+
+        /* setup north bridge irq (bonito) */
+        setup_irq(LOONGSON_NORTH_BRIDGE_IRQ, &ip6_irqaction);
+        /* setup source bridge irq (i8259) */
+        setup_irq(LOONGSON_SOUTH_BRIDGE_IRQ, &cascade_irqaction);
+}
diff --git a/arch/mips/loongson/lemote-2f/pm.c b/arch/mips/loongson/lemote-2f/pm.c
new file mode 100644
index 000000000000..d7af2e616592
--- /dev/null
+++ b/arch/mips/loongson/lemote-2f/pm.c
@@ -0,0 +1,149 @@
+/*
+ *  Lemote loongson2f family machines' specific suspend support
+ *
+ *  Copyright (C) 2009 Lemote Inc.
+ *  Author: Wu Zhangjin <wuzj@lemote.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/suspend.h>
+#include <linux/interrupt.h>
+#include <linux/pm.h>
+#include <linux/i8042.h>
+#include <linux/module.h>
+
+#include <asm/i8259.h>
+#include <asm/mipsregs.h>
+#include <asm/bootinfo.h>
+
+#include <loongson.h>
+
+#include <cs5536/cs5536_mfgpt.h>
+#include "ec_kb3310b.h"
+
+#define I8042_KBD_IRQ           1
+#define I8042_CTR_KBDINT        0x01
+#define I8042_CTR_KBDDIS        0x10
+
+static unsigned char i8042_ctr;
+
+static int i8042_enable_kbd_port(void)
+{
+        if (i8042_command(&i8042_ctr, I8042_CMD_CTL_RCTR)) {
+                pr_err("i8042.c: Can't read CTR while enabling i8042 kbd port."
+                       "\n");
+                return -EIO;
+        }
+
+        i8042_ctr &= ~I8042_CTR_KBDDIS;
+        i8042_ctr |= I8042_CTR_KBDINT;
+
+        if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
+                i8042_ctr &= ~I8042_CTR_KBDINT;
+                i8042_ctr |= I8042_CTR_KBDDIS;
+                pr_err("i8042.c: Failed to enable KBD port.\n");
+
+                return -EIO;
+        }
+
+        return 0;
+}
+
+void setup_wakeup_events(void)
+{
+        int irq_mask;
+
+        switch (mips_machtype) {
+        case MACH_LEMOTE_ML2F7:
+        case MACH_LEMOTE_YL2F89:
+                /* open the keyboard irq in i8259A */
+                outb((0xff & ~(1 << I8042_KBD_IRQ)), PIC_MASTER_IMR);
+                irq_mask = inb(PIC_MASTER_IMR);
+
+                /* enable keyboard port */
+                i8042_enable_kbd_port();
+
+                /* Wakeup CPU via SCI lid open event */
+                outb(irq_mask & ~(1 << PIC_CASCADE_IR), PIC_MASTER_IMR);
+                inb(PIC_MASTER_IMR);
+                outb(0xff & ~(1 << (SCI_IRQ_NUM - 8)), PIC_SLAVE_IMR);
+                inb(PIC_SLAVE_IMR);
+
+                break;
+
+        default:
+                break;
+        }
+}
+
+static struct delayed_work lid_task;
+static int initialized;
+/* yeeloong_report_lid_status will be implemented in yeeloong_laptop.c */
+sci_handler yeeloong_report_lid_status;
+EXPORT_SYMBOL(yeeloong_report_lid_status);
+static void yeeloong_lid_update_task(struct work_struct *work)
+{
+        if (yeeloong_report_lid_status)
+                yeeloong_report_lid_status(BIT_LID_DETECT_ON);
+}
+
+int wakeup_loongson(void)
+{
+        int irq;
+
+        /* query the interrupt number */
+        irq = mach_i8259_irq();
+        if (irq < 0)
+                return 0;
+
+        printk(KERN_INFO "%s: irq = %d\n", __func__, irq);
+
+        if (irq == I8042_KBD_IRQ)
+                return 1;
+        else if (irq == SCI_IRQ_NUM) {
+                int ret, sci_event;
+                /* query the event number */
+                ret = ec_query_seq(CMD_GET_EVENT_NUM);
+                if (ret < 0)
+                        return 0;
+                sci_event = ec_get_event_num();
+                if (sci_event < 0)
+                        return 0;
+                if (sci_event == EVENT_LID) {
+                        int lid_status;
+                        /* check the LID status */
+                        lid_status = ec_read(REG_LID_DETECT);
+                        /* wakeup cpu when people open the LID */
+                        if (lid_status == BIT_LID_DETECT_ON) {
+                                /* If we call it directly here, the WARNING
+                                 * will be sent out by getnstimeofday
+                                 * via "WARN_ON(timekeeping_suspended);"
+                                 * because we can not schedule in suspend mode.
+                                 */
+                                if (initialized == 0) {
+                                        INIT_DELAYED_WORK(&lid_task,
+                                                yeeloong_lid_update_task);
+                                        initialized = 1;
+                                }
+                                schedule_delayed_work(&lid_task, 1);
+                                return 1;
+                        }
+                }
+        }
+
+        return 0;
+}
+
+void __weak mach_suspend(void)
+{
+        disable_mfgpt0_counter();
+}
+
+void __weak mach_resume(void)
+{
+        enable_mfgpt0_counter();
+}
diff --git a/arch/mips/loongson/lemote-2f/reset.c b/arch/mips/loongson/lemote-2f/reset.c
new file mode 100644
index 000000000000..51d1a60d5349
--- /dev/null
+++ b/arch/mips/loongson/lemote-2f/reset.c
@@ -0,0 +1,159 @@
+/* Board-specific reboot/shutdown routines
+ *
+ * Copyright (c) 2009 Philippe Vachon <philippe@cowpig.ca>
+ *
+ * Copyright (C) 2009 Lemote Inc.
+ * Author: Wu Zhangjin, wuzj@lemote.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/types.h>
+
+#include <asm/bootinfo.h>
+
+#include <loongson.h>
+
+#include <cs5536/cs5536.h>
+#include "ec_kb3310b.h"
+
+static void reset_cpu(void)
+{
+        /*
+         * reset cpu to full speed, this is needed when enabling cpu frequency
+         * scalling
+         */
+        LOONGSON_CHIPCFG0 |= 0x7;
+}
+
+/* reset support for fuloong2f */
+
+static void fl2f_reboot(void)
+{
+        reset_cpu();
+
+        /* send a reset signal to south bridge.
+         *
+         * NOTE: if enable "Power Management" in kernel, rtl8169 will not reset
+         * normally with this reset operation and it will not work in PMON, but
+         * you can type halt command and then reboot, seems the hardware reset
+         * logic not work normally.
+         */
+        {
+                u32 hi, lo;
+                _rdmsr(DIVIL_MSR_REG(DIVIL_SOFT_RESET), &hi, &lo);
+                lo |= 0x00000001;
+                _wrmsr(DIVIL_MSR_REG(DIVIL_SOFT_RESET), hi, lo);
+        }
+}
+
+static void fl2f_shutdown(void)
+{
+        u32 hi, lo, val;
+        int gpio_base;
+
+        /* get gpio base */
+        _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_GPIO), &hi, &lo);
+        gpio_base = lo & 0xff00;
+
+        /* make cs5536 gpio13 output enable */
+        val = inl(gpio_base + GPIOL_OUT_EN);
+        val &= ~(1 << (16 + 13));
+        val |= (1 << 13);
+        outl(val, gpio_base + GPIOL_OUT_EN);
+        mmiowb();
+        /* make cs5536 gpio13 output low level voltage. */
+        val = inl(gpio_base + GPIOL_OUT_VAL) & ~(1 << (13));
+        val |= (1 << (16 + 13));
+        outl(val, gpio_base + GPIOL_OUT_VAL);
+        mmiowb();
+}
+
+/* reset support for yeeloong2f and mengloong2f notebook */
+
+void ml2f_reboot(void)
+{
+        reset_cpu();
+
+        /* sending an reset signal to EC(embedded controller) */
+        ec_write(REG_RESET, BIT_RESET_ON);
+}
+
+#define yl2f89_reboot ml2f_reboot
+
+/* menglong(7inches) laptop has different shutdown logic from 8.9inches */
+#define EC_SHUTDOWN_IO_PORT_HIGH 0xff2d
+#define EC_SHUTDOWN_IO_PORT_LOW  0xff2e
+#define EC_SHUTDOWN_IO_PORT_DATA 0xff2f
+#define REG_SHUTDOWN_HIGH        0xFC
+#define REG_SHUTDOWN_LOW         0x29
+#define BIT_SHUTDOWN_ON          (1 << 1)
+
+static void ml2f_shutdown(void)
+{
+        u8 val;
+        u64 i;
+
+        outb(REG_SHUTDOWN_HIGH, EC_SHUTDOWN_IO_PORT_HIGH);
+        outb(REG_SHUTDOWN_LOW, EC_SHUTDOWN_IO_PORT_LOW);
+        mmiowb();
+        val = inb(EC_SHUTDOWN_IO_PORT_DATA);
+        outb(val & (~BIT_SHUTDOWN_ON), EC_SHUTDOWN_IO_PORT_DATA);
+        mmiowb();
+        /* need enough wait here... how many microseconds needs? */
+        for (i = 0; i < 0x10000; i++)
+                delay();
+        outb(val | BIT_SHUTDOWN_ON, EC_SHUTDOWN_IO_PORT_DATA);
+        mmiowb();
+}
+
+static void yl2f89_shutdown(void)
+{
+        /* cpu-gpio0 output low */
+        LOONGSON_GPIODATA &= ~0x00000001;
+        /* cpu-gpio0 as output */
+        LOONGSON_GPIOIE &= ~0x00000001;
+}
+
+void mach_prepare_reboot(void)
+{
+        switch (mips_machtype) {
+        case MACH_LEMOTE_FL2F:
+        case MACH_LEMOTE_NAS:
+        case MACH_LEMOTE_LL2F:
+                fl2f_reboot();
+                break;
+        case MACH_LEMOTE_ML2F7:
+                ml2f_reboot();
+                break;
+        case MACH_LEMOTE_YL2F89:
+                yl2f89_reboot();
+                break;
+        default:
+                break;
+        }
+}
+
+void mach_prepare_shutdown(void)
+{
+        switch (mips_machtype) {
+        case MACH_LEMOTE_FL2F:
+        case MACH_LEMOTE_NAS:
+        case MACH_LEMOTE_LL2F:
+                fl2f_shutdown();
+                break;
+        case MACH_LEMOTE_ML2F7:
+                ml2f_shutdown();
+                break;
+        case MACH_LEMOTE_YL2F89:
+                yl2f89_shutdown();
+                break;
+        default:
+                break;
+        }
+}
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 454b53924490..8f2f8e9d8b21 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -35,6 +35,7 @@
  * better performance by compiling with -msoft-float!
  */
 #include <linux/sched.h>
+#include <linux/module.h>
 #include <linux/debugfs.h>
 
 #include <asm/inst.h>
@@ -68,7 +69,9 @@ static int fpux_emu(struct pt_regs *,
 
 /* Further private data for which no space exists in mips_fpu_struct */
 
-struct mips_fpu_emulator_stats fpuemustats;
+#ifdef CONFIG_DEBUG_FS
+DEFINE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
+#endif
 
 /* Control registers */
 
@@ -209,7 +212,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
         unsigned int cond;
 
         if (get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) {
-                fpuemustats.errors++;
+                MIPS_FPU_EMU_INC_STATS(errors);
                 return SIGBUS;
         }
 
@@ -240,7 +243,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
                         return SIGILL;
                 }
                 if (get_user(ir, (mips_instruction __user *) emulpc)) {
-                        fpuemustats.errors++;
+                        MIPS_FPU_EMU_INC_STATS(errors);
                         return SIGBUS;
                 }
                 /* __compute_return_epc() will have updated cp0_epc */
@@ -253,16 +256,16 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
         }
 
       emul:
-        fpuemustats.emulated++;
+        MIPS_FPU_EMU_INC_STATS(emulated);
         switch (MIPSInst_OPCODE(ir)) {
         case ldc1_op:{
                 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
                         MIPSInst_SIMM(ir));
                 u64 val;
 
-                fpuemustats.loads++;
+                MIPS_FPU_EMU_INC_STATS(loads);
                 if (get_user(val, va)) {
-                        fpuemustats.errors++;
+                        MIPS_FPU_EMU_INC_STATS(errors);
                         return SIGBUS;
                 }
                 DITOREG(val, MIPSInst_RT(ir));
@@ -274,10 +277,10 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
                         MIPSInst_SIMM(ir));
                 u64 val;
 
-                fpuemustats.stores++;
+                MIPS_FPU_EMU_INC_STATS(stores);
                 DIFROMREG(val, MIPSInst_RT(ir));
                 if (put_user(val, va)) {
-                        fpuemustats.errors++;
+                        MIPS_FPU_EMU_INC_STATS(errors);
                         return SIGBUS;
                 }
                 break;
@@ -288,9 +291,9 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
                         MIPSInst_SIMM(ir));
                 u32 val;
 
-                fpuemustats.loads++;
+                MIPS_FPU_EMU_INC_STATS(loads);
                 if (get_user(val, va)) {
-                        fpuemustats.errors++;
+                        MIPS_FPU_EMU_INC_STATS(errors);
                         return SIGBUS;
                 }
                 SITOREG(val, MIPSInst_RT(ir));
@@ -302,10 +305,10 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
                         MIPSInst_SIMM(ir));
                 u32 val;
 
-                fpuemustats.stores++;
+                MIPS_FPU_EMU_INC_STATS(stores);
                 SIFROMREG(val, MIPSInst_RT(ir));
                 if (put_user(val, va)) {
-                        fpuemustats.errors++;
+                        MIPS_FPU_EMU_INC_STATS(errors);
                         return SIGBUS;
                 }
                 break;
@@ -429,7 +432,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
 
                                 if (get_user(ir,
                                     (mips_instruction __user *) xcp->cp0_epc)) {
-                                        fpuemustats.errors++;
+                                        MIPS_FPU_EMU_INC_STATS(errors);
                                         return SIGBUS;
                                 }
 
@@ -595,7 +598,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 {
         unsigned rcsr = 0;      /* resulting csr */
 
-        fpuemustats.cp1xops++;
+        MIPS_FPU_EMU_INC_STATS(cp1xops);
 
         switch (MIPSInst_FMA_FFMT(ir)) {
         case s_fmt:{            /* 0 */
@@ -610,9 +613,9 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
                                 xcp->regs[MIPSInst_FT(ir)]);
 
-                        fpuemustats.loads++;
+                        MIPS_FPU_EMU_INC_STATS(loads);
                         if (get_user(val, va)) {
-                                fpuemustats.errors++;
+                                MIPS_FPU_EMU_INC_STATS(errors);
                                 return SIGBUS;
                         }
                         SITOREG(val, MIPSInst_FD(ir));
@@ -622,11 +625,11 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
                                 xcp->regs[MIPSInst_FT(ir)]);
 
-                        fpuemustats.stores++;
+                        MIPS_FPU_EMU_INC_STATS(stores);
 
                         SIFROMREG(val, MIPSInst_FS(ir));
                         if (put_user(val, va)) {
-                                fpuemustats.errors++;
+                                MIPS_FPU_EMU_INC_STATS(errors);
                                 return SIGBUS;
                         }
                         break;
@@ -687,9 +690,9 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
                                 xcp->regs[MIPSInst_FT(ir)]);
 
-                        fpuemustats.loads++;
+                        MIPS_FPU_EMU_INC_STATS(loads);
                         if (get_user(val, va)) {
-                                fpuemustats.errors++;
+                                MIPS_FPU_EMU_INC_STATS(errors);
                                 return SIGBUS;
                         }
                         DITOREG(val, MIPSInst_FD(ir));
@@ -699,10 +702,10 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
                                 xcp->regs[MIPSInst_FT(ir)]);
 
-                        fpuemustats.stores++;
+                        MIPS_FPU_EMU_INC_STATS(stores);
                         DIFROMREG(val, MIPSInst_FS(ir));
                         if (put_user(val, va)) {
-                                fpuemustats.errors++;
+                                MIPS_FPU_EMU_INC_STATS(errors);
                                 return SIGBUS;
                         }
                         break;
@@ -769,7 +772,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 #endif
         } rv;                   /* resulting value */
 
-        fpuemustats.cp1ops++;
+        MIPS_FPU_EMU_INC_STATS(cp1ops);
         switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
         case s_fmt:{            /* 0 */
                 union {
@@ -1240,7 +1243,7 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                 prevepc = xcp->cp0_epc;
 
                 if (get_user(insn, (mips_instruction __user *) xcp->cp0_epc)) {
-                        fpuemustats.errors++;
+                        MIPS_FPU_EMU_INC_STATS(errors);
                         return SIGBUS;
                 }
                 if (insn == 0)
@@ -1276,33 +1279,50 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 }
 
 #ifdef CONFIG_DEBUG_FS
+
+static int fpuemu_stat_get(void *data, u64 *val)
+{
+        int cpu;
+        unsigned long sum = 0;
+        for_each_online_cpu(cpu) {
+                struct mips_fpu_emulator_stats *ps;
+                local_t *pv;
+                ps = &per_cpu(fpuemustats, cpu);
+                pv = (void *)ps + (unsigned long)data;
+                sum += local_read(pv);
+        }
+        *val = sum;
+        return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(fops_fpuemu_stat, fpuemu_stat_get, NULL, "%llu\n");
+
 extern struct dentry *mips_debugfs_dir;
 static int __init debugfs_fpuemu(void)
 {
         struct dentry *d, *dir;
-        int i;
-        static struct {
-                const char *name;
-                unsigned int *v;
-        } vars[] __initdata = {
-                { "emulated", &fpuemustats.emulated },
-                { "loads",    &fpuemustats.loads },
-                { "stores",   &fpuemustats.stores },
-                { "cp1ops",   &fpuemustats.cp1ops },
-                { "cp1xops",  &fpuemustats.cp1xops },
-                { "errors",   &fpuemustats.errors },
-        };
 
         if (!mips_debugfs_dir)
                 return -ENODEV;
         dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir);
         if (!dir)
                 return -ENOMEM;
-        for (i = 0; i < ARRAY_SIZE(vars); i++) {
-                d = debugfs_create_u32(vars[i].name, S_IRUGO, dir, vars[i].v);
-                if (!d)
-                        return -ENOMEM;
-        }
+
+#define FPU_STAT_CREATE(M)                                              \
+        do {                                                            \
+                d = debugfs_create_file(#M , S_IRUGO, dir,              \
+                        (void *)offsetof(struct mips_fpu_emulator_stats, M), \
+                        &fops_fpuemu_stat);                             \
+                if (!d)                                                 \
+                        return -ENOMEM;                                 \
+        } while (0)
+
+        FPU_STAT_CREATE(emulated);
+        FPU_STAT_CREATE(loads);
+        FPU_STAT_CREATE(stores);
+        FPU_STAT_CREATE(cp1ops);
+        FPU_STAT_CREATE(cp1xops);
+        FPU_STAT_CREATE(errors);
+
         return 0;
 }
 __initcall(debugfs_fpuemu);
diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c
index df7b9d928efc..36d975ae08f8 100644
--- a/arch/mips/math-emu/dsemul.c
+++ b/arch/mips/math-emu/dsemul.c
@@ -98,7 +98,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc)
         err |= __put_user(cpc, &fr->epc);
 
         if (unlikely(err)) {
-                fpuemustats.errors++;
+                MIPS_FPU_EMU_INC_STATS(errors);
                 return SIGBUS;
         }
 
@@ -136,7 +136,7 @@ int do_dsemulret(struct pt_regs *xcp)
         err |= __get_user(cookie, &fr->cookie);
 
         if (unlikely(err || (insn != BREAK_MATH) || (cookie != BD_COOKIE))) {
-                fpuemustats.errors++;
+                MIPS_FPU_EMU_INC_STATS(errors);
                 return 0;
         }
 
diff --git a/arch/mips/mipssim/Makefile b/arch/mips/mipssim/Makefile
index 57f43c1c7882..41b96571315e 100644
--- a/arch/mips/mipssim/Makefile
+++ b/arch/mips/mipssim/Makefile
@@ -17,8 +17,7 @@
 # 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 #
 
-obj-y := sim_platform.o sim_setup.o sim_mem.o sim_time.o sim_int.o \
-         sim_cmdline.o
+obj-y := sim_platform.o sim_setup.o sim_mem.o sim_time.o sim_int.o
 
 obj-$(CONFIG_EARLY_PRINTK) += sim_console.o
 obj-$(CONFIG_MIPS_MT_SMTC) += sim_smtc.o
diff --git a/arch/mips/mipssim/sim_setup.c b/arch/mips/mipssim/sim_setup.c
index 2877675c5f0d..0824f6af4777 100644
--- a/arch/mips/mipssim/sim_setup.c
+++ b/arch/mips/mipssim/sim_setup.c
@@ -61,7 +61,6 @@ void __init prom_init(void)
         set_io_port_base(0xbfd00000);
 
         pr_info("\nLINUX started...\n");
-        prom_init_cmdline();
         prom_meminit();
 
 #ifdef CONFIG_MIPS_MT_SMP
diff --git a/arch/mips/mm/cerr-sb1.c b/arch/mips/mm/cerr-sb1.c
index 1bd1f18ac23c..3571090ba178 100644
--- a/arch/mips/mm/cerr-sb1.c
+++ b/arch/mips/mm/cerr-sb1.c
@@ -567,13 +567,10 @@ static uint32_t extract_dc(unsigned short addr, int data)
                                 datalo = ((unsigned long long)datalohi << 32) | datalolo;
                                 ecc = dc_ecc(datalo);
                                 if (ecc != datahi) {
-                                        int bits = 0;
+                                        int bits;
                                         bad_ecc |= 1 << (3-offset);
                                         ecc ^= datahi;
-                                        while (ecc) {
-                                                if (ecc & 1) bits++;
-                                                ecc >>= 1;
-                                        }
+                                        bits = hweight8(ecc);
                                         res |= (bits == 1) ? CP0_CERRD_DATA_SBE : CP0_CERRD_DATA_DBE;
                                 }
                                 printk("  %02X-%016llX", datahi, datalo);
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 8d1f4f363049..9e8d00389eef 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -462,7 +462,9 @@ void __init_refok free_initmem(void)
                         __pa_symbol(&__init_end));
 }
 
+#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
 unsigned long pgd_current[NR_CPUS];
+#endif
 /*
  * On 64-bit we've got three-level pagetables with a slightly
  * different layout ...
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index bb1719a55d22..3d0baa4a842d 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -160,6 +160,12 @@ static u32 tlb_handler[128] __cpuinitdata;
 static struct uasm_label labels[128] __cpuinitdata;
 static struct uasm_reloc relocs[128] __cpuinitdata;
 
+#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
+/*
+ * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
+ * we cannot do r3000 under these circumstances.
+ */
+
 /*
  * The R3000 TLB handler is simple.
  */
@@ -199,6 +205,7 @@ static void __cpuinit build_r3000_tlb_refill_handler(void)
 
         dump_handler((u32 *)ebase, 32);
 }
+#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
 
 /*
  * The R4000 TLB handler is much more complicated. We have two
@@ -497,8 +504,9 @@ static void __cpuinit
 build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
                  unsigned int tmp, unsigned int ptr)
 {
+#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
         long pgdc = (long)pgd_current;
-
+#endif
         /*
          * The vmalloc handling is not in the hotpath.
          */
@@ -506,7 +514,15 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
         uasm_il_bltz(p, r, tmp, label_vmalloc);
         /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
 
-#ifdef CONFIG_SMP
+#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
+        /*
+         * &pgd << 11 stored in CONTEXT [23..63].
+         */
+        UASM_i_MFC0(p, ptr, C0_CONTEXT);
+        uasm_i_dins(p, ptr, 0, 0, 23); /* Clear lower 23 bits of context. */
+        uasm_i_ori(p, ptr, ptr, 0x540); /* 1 0  1 0 1  << 6  xkphys cached */
+        uasm_i_drotr(p, ptr, ptr, 11);
+#elif defined(CONFIG_SMP)
 # ifdef  CONFIG_MIPS_MT_SMTC
         /*
          * SMTC uses TCBind value as "CPU" index
@@ -520,7 +536,7 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
          */
         uasm_i_dmfc0(p, ptr, C0_CONTEXT);
         uasm_i_dsrl(p, ptr, ptr, 23);
-#endif
+# endif
         UASM_i_LA_mostly(p, tmp, pgdc);
         uasm_i_daddu(p, ptr, ptr, tmp);
         uasm_i_dmfc0(p, tmp, C0_BADVADDR);
@@ -1033,6 +1049,7 @@ build_pte_modifiable(u32 **p, struct uasm_reloc **r,
         iPTE_LW(p, pte, ptr);
 }
 
+#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
 /*
  * R3000 style TLB load/store/modify handlers.
  */
@@ -1184,6 +1201,7 @@ static void __cpuinit build_r3000_tlb_modify_handler(void)
 
         dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm));
 }
+#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
 
 /*
  * R4000 style TLB load/store/modify handlers.
@@ -1400,6 +1418,7 @@ void __cpuinit build_tlb_refill_handler(void)
         case CPU_TX3912:
         case CPU_TX3922:
         case CPU_TX3927:
+#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
                 build_r3000_tlb_refill_handler();
                 if (!run_once) {
                         build_r3000_tlb_load_handler();
@@ -1407,6 +1426,9 @@ void __cpuinit build_tlb_refill_handler(void)
                         build_r3000_tlb_modify_handler();
                         run_once++;
                 }
+#else
+                panic("No R3000 TLB refill handler");
+#endif
                 break;
 
         case CPU_R6000:
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index f467199676a8..0a165c5179a1 100644
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -60,11 +60,11 @@ enum opcode {
         insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
         insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0,
         insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
-        insn_dsrl32, insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr,
-        insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0,
+        insn_dsrl32, insn_drotr, insn_dsubu, insn_eret, insn_j, insn_jal,
+        insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0,
         insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd,
         insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw,
-        insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori
+        insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, insn_dins
 };
 
 struct insn {
@@ -104,6 +104,7 @@ static struct insn insn_table[] __cpuinitdata = {
         { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
         { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
         { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
+        { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
         { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
         { insn_eret,  M(cop0_op, cop_op, 0, 0, 0, eret_op),  0 },
         { insn_j,  M(j_op, 0, 0, 0, 0, 0),  JIMM },
@@ -132,6 +133,7 @@ static struct insn insn_table[] __cpuinitdata = {
         { insn_tlbwr,  M(cop0_op, cop_op, 0, 0, 0, tlbwr_op),  0 },
         { insn_xor,  M(spec_op, 0, 0, 0, 0, xor_op),  RS | RT | RD },
         { insn_xori,  M(xori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM },
+        { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
         { insn_invalid, 0, 0 }
 };
 
@@ -304,6 +306,12 @@ Ip_u2u1s3(op)						\
         build_insn(buf, insn##op, b, a, c);             \
 }
 
+#define I_u2u1msbu3(op)                                 \
+Ip_u2u1msbu3(op)                                        \
+{                                                       \
+        build_insn(buf, insn##op, b, a, c+d-1, c);      \
+}
+
 #define I_u1u2(op)                                      \
 Ip_u1u2(op)                                             \
 {                                                       \
@@ -349,6 +357,7 @@ I_u2u1u3(_dsll32)
 I_u2u1u3(_dsra)
 I_u2u1u3(_dsrl)
 I_u2u1u3(_dsrl32)
+I_u2u1u3(_drotr)
 I_u3u1u2(_dsubu)
 I_0(_eret)
 I_u1(_j)
@@ -377,6 +386,7 @@ I_0(_tlbwi)
 I_0(_tlbwr)
 I_u3u1u2(_xor)
 I_u2u1u3(_xori)
+I_u2u1msbu3(_dins);
 
 /* Handle labels. */
 void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
diff --git a/arch/mips/mm/uasm.h b/arch/mips/mm/uasm.h
index c6d1e3dd82d4..3d153edaa51e 100644
--- a/arch/mips/mm/uasm.h
+++ b/arch/mips/mm/uasm.h
@@ -34,6 +34,11 @@ uasm_i##op(u32 **buf, unsigned int a, signed int b, unsigned int c)
 void __cpuinit                                                          \
 uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c)
 
+#define Ip_u2u1msbu3(op)                                                \
+void __cpuinit                                                          \
+uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c,   \
+           unsigned int d)
+
 #define Ip_u1u2(op)                                                     \
 void __cpuinit uasm_i##op(u32 **buf, unsigned int a, unsigned int b)
 
@@ -65,6 +70,7 @@ Ip_u2u1u3(_dsll32);
 Ip_u2u1u3(_dsra);
 Ip_u2u1u3(_dsrl);
 Ip_u2u1u3(_dsrl32);
+Ip_u2u1u3(_drotr);
 Ip_u3u1u2(_dsubu);
 Ip_0(_eret);
 Ip_u1(_j);
@@ -93,6 +99,7 @@ Ip_0(_tlbwi);
 Ip_0(_tlbwr);
 Ip_u3u1u2(_xor);
 Ip_u2u1u3(_xori);
+Ip_u2u1msbu3(_dins);
 
 /* Handle labels. */
 struct uasm_label {
diff --git a/arch/mips/mti-malta/malta-memory.c b/arch/mips/mti-malta/malta-memory.c
index 9035c64bc5ed..b27419c84919 100644
--- a/arch/mips/mti-malta/malta-memory.c
+++ b/arch/mips/mti-malta/malta-memory.c
@@ -55,7 +55,7 @@ static struct prom_pmemblock * __init prom_getmdesc(void)
         char *memsize_str;
         unsigned int memsize;
         char *ptr;
-        static char cmdline[CL_SIZE] __initdata;
+        static char cmdline[COMMAND_LINE_SIZE] __initdata;
 
         /* otherwise look in the environment */
         memsize_str = prom_getenv("memsize");
diff --git a/arch/mips/nxp/pnx833x/common/interrupts.c b/arch/mips/nxp/pnx833x/common/interrupts.c
index 30533ba200e2..3a467c04f811 100644
--- a/arch/mips/nxp/pnx833x/common/interrupts.c
+++ b/arch/mips/nxp/pnx833x/common/interrupts.c
@@ -295,7 +295,7 @@ static int pnx833x_set_type_gpio_irq(unsigned int irq, unsigned int flow_type)
 }
 
 static struct irq_chip pnx833x_pic_irq_type = {
-        .typename = "PNX-PIC",
+        .name = "PNX-PIC",
         .startup = pnx833x_startup_pic_irq,
         .shutdown = pnx833x_shutdown_pic_irq,
         .enable = pnx833x_enable_pic_irq,
@@ -305,7 +305,7 @@ static struct irq_chip pnx833x_pic_irq_type = {
 };
 
 static struct irq_chip pnx833x_gpio_irq_type = {
-        .typename = "PNX-GPIO",
+        .name = "PNX-GPIO",
         .startup = pnx833x_startup_gpio_irq,
         .shutdown = pnx833x_disable_gpio_irq,
         .enable = pnx833x_enable_gpio_irq,
diff --git a/arch/mips/oprofile/op_model_loongson2.c b/arch/mips/oprofile/op_model_loongson2.c
index 575cd1473475..475ff46712ab 100644
--- a/arch/mips/oprofile/op_model_loongson2.c
+++ b/arch/mips/oprofile/op_model_loongson2.c
@@ -1,7 +1,7 @@
 /*
  * Loongson2 performance counter driver for oprofile
  *
- * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
+ * Copyright (C) 2009 Lemote Inc.
  * Author: Yanhua <yanh@lemote.com>
  * Author: Wu Zhangjin <wuzj@lemote.com>
  *
@@ -125,6 +125,9 @@ static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id)
          */
 
         /* Check whether the irq belongs to me */
+        enabled = read_c0_perfcnt() & LOONGSON2_PERFCNT_INT_EN;
+        if (!enabled)
+                return IRQ_NONE;
         enabled = reg.cnt1_enabled | reg.cnt2_enabled;
         if (!enabled)
                 return IRQ_NONE;
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 91bfe73a7f60..c9209ca6c8e7 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -22,13 +22,13 @@ obj-$(CONFIG_BCM63XX)		+= pci-bcm63xx.o fixup-bcm63xx.o \
 #
 # These are still pretty much in the old state, watch, go blind.
 #
-obj-$(CONFIG_BASLER_EXCITE)     += ops-titan.o pci-excite.o fixup-excite.o
 obj-$(CONFIG_LASAT)             += pci-lasat.o
 obj-$(CONFIG_MIPS_COBALT)       += fixup-cobalt.o
 obj-$(CONFIG_SOC_AU1500)        += fixup-au1000.o ops-au1000.o
 obj-$(CONFIG_SOC_AU1550)        += fixup-au1000.o ops-au1000.o
 obj-$(CONFIG_SOC_PNX8550)       += fixup-pnx8550.o ops-pnx8550.o
-obj-$(CONFIG_LEMOTE_FULOONG2E)  += fixup-fuloong2e.o ops-bonito64.o
+obj-$(CONFIG_LEMOTE_FULOONG2E)  += fixup-fuloong2e.o ops-loongson2.o
+obj-$(CONFIG_LEMOTE_MACH2F)     += fixup-lemote2f.o ops-loongson2.o
 obj-$(CONFIG_MIPS_MALTA)        += fixup-malta.o
 obj-$(CONFIG_PMC_MSP7120_GW)    += fixup-pmcmsp.o ops-pmcmsp.o
 obj-$(CONFIG_PMC_MSP7120_EVAL)  += fixup-pmcmsp.o ops-pmcmsp.o
diff --git a/arch/mips/pci/fixup-excite.c b/arch/mips/pci/fixup-excite.c
deleted file mode 100644
index cd64d9f177c4..000000000000
--- a/arch/mips/pci/fixup-excite.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- *  Copyright (C) 2004 by Basler Vision Technologies AG
- *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <excite.h>
-
-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
-        if (pin == 0)
-                return -1;
-
-        return USB_IRQ;         /* USB controller is the only PCI device */
-}
-
-/* Do platform specific device initialization at pci_enable_device() time */
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
-        return 0;
-}
diff --git a/arch/mips/pci/fixup-fuloong2e.c b/arch/mips/pci/fixup-fuloong2e.c
index 0c4c7a81213f..4f6d8da07f93 100644
--- a/arch/mips/pci/fixup-fuloong2e.c
+++ b/arch/mips/pci/fixup-fuloong2e.c
@@ -13,7 +13,8 @@
  */
 #include <linux/init.h>
 #include <linux/pci.h>
-#include <asm/mips-boards/bonito64.h>
+
+#include <loongson.h>
 
 /* South bridge slot number is set by the pci probe process */
 static u8 sb_slot = 5;
@@ -35,7 +36,7 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
                         break;
                 }
         } else {
-                irq = BONITO_IRQ_BASE + 25 + pin;
+                irq = LOONGSON_IRQ_BASE + 25 + pin;
         }
         return irq;
 
diff --git a/arch/mips/pci/fixup-lemote2f.c b/arch/mips/pci/fixup-lemote2f.c
new file mode 100644
index 000000000000..caf2edeb02f0
--- /dev/null
+++ b/arch/mips/pci/fixup-lemote2f.c
@@ -0,0 +1,160 @@
+/*
+ * Copyright (C) 2008 Lemote Technology
+ * Copyright (C) 2004 ICT CAS
+ * Author: Li xiaoyu, lixy@ict.ac.cn
+ *
+ * Copyright (C) 2007 Lemote, Inc.
+ * Author: Fuxin Zhang, zhangfx@lemote.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+#include <linux/init.h>
+#include <linux/pci.h>
+
+#include <loongson.h>
+#include <cs5536/cs5536.h>
+#include <cs5536/cs5536_pci.h>
+
+/* PCI interrupt pins
+ *
+ * These should not be changed, or you should consider loongson2f interrupt
+ * register and your pci card dispatch
+ */
+
+#define PCIA            4
+#define PCIB            5
+#define PCIC            6
+#define PCID            7
+
+/* all the pci device has the PCIA pin, check the datasheet. */
+static char irq_tab[][5] __initdata = {
+        /*      INTA    INTB    INTC    INTD */
+        {0, 0, 0, 0, 0},        /*  11: Unused */
+        {0, 0, 0, 0, 0},        /*  12: Unused */
+        {0, 0, 0, 0, 0},        /*  13: Unused */
+        {0, 0, 0, 0, 0},        /*  14: Unused */
+        {0, 0, 0, 0, 0},        /*  15: Unused */
+        {0, 0, 0, 0, 0},        /*  16: Unused */
+        {0, PCIA, 0, 0, 0},     /*  17: RTL8110-0 */
+        {0, PCIB, 0, 0, 0},     /*  18: RTL8110-1 */
+        {0, PCIC, 0, 0, 0},     /*  19: SiI3114 */
+        {0, PCID, 0, 0, 0},     /*  20: 3-ports nec usb */
+        {0, PCIA, PCIB, PCIC, PCID},    /*  21: PCI-SLOT */
+        {0, 0, 0, 0, 0},        /*  22: Unused */
+        {0, 0, 0, 0, 0},        /*  23: Unused */
+        {0, 0, 0, 0, 0},        /*  24: Unused */
+        {0, 0, 0, 0, 0},        /*  25: Unused */
+        {0, 0, 0, 0, 0},        /*  26: Unused */
+        {0, 0, 0, 0, 0},        /*  27: Unused */
+};
+
+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        int virq;
+
+        if ((PCI_SLOT(dev->devfn) != PCI_IDSEL_CS5536)
+            && (PCI_SLOT(dev->devfn) < 32)) {
+                virq = irq_tab[slot][pin];
+                printk(KERN_INFO "slot: %d, pin: %d, irq: %d\n", slot, pin,
+                       virq + LOONGSON_IRQ_BASE);
+                if (virq != 0)
+                        return LOONGSON_IRQ_BASE + virq;
+                else
+                        return 0;
+        } else if (PCI_SLOT(dev->devfn) == PCI_IDSEL_CS5536) {  /*  cs5536 */
+                switch (PCI_FUNC(dev->devfn)) {
+                case 2:
+                        pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
+                                              CS5536_IDE_INTR);
+                        return CS5536_IDE_INTR; /*  for IDE */
+                case 3:
+                        pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
+                                              CS5536_ACC_INTR);
+                        return CS5536_ACC_INTR; /*  for AUDIO */
+                case 4: /*  for OHCI */
+                case 5: /*  for EHCI */
+                case 6: /*  for UDC */
+                case 7: /*  for OTG */
+                        pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
+                                              CS5536_USB_INTR);
+                        return CS5536_USB_INTR;
+                }
+                return dev->irq;
+        } else {
+                printk(KERN_INFO " strange pci slot number.\n");
+                return 0;
+        }
+}
+
+/* Do platform specific device initialization at pci_enable_device() time */
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+        return 0;
+}
+
+/* CS5536 SPEC. fixup */
+static void __init loongson_cs5536_isa_fixup(struct pci_dev *pdev)
+{
+        /* the uart1 and uart2 interrupt in PIC is enabled as default */
+        pci_write_config_dword(pdev, PCI_UART1_INT_REG, 1);
+        pci_write_config_dword(pdev, PCI_UART2_INT_REG, 1);
+}
+
+static void __init loongson_cs5536_ide_fixup(struct pci_dev *pdev)
+{
+        /* setting the mutex pin as IDE function */
+        pci_write_config_dword(pdev, PCI_IDE_CFG_REG,
+                               CS5536_IDE_FLASH_SIGNATURE);
+}
+
+static void __init loongson_cs5536_acc_fixup(struct pci_dev *pdev)
+{
+        /* enable the AUDIO interrupt in PIC  */
+        pci_write_config_dword(pdev, PCI_ACC_INT_REG, 1);
+
+        pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xc0);
+}
+
+static void __init loongson_cs5536_ohci_fixup(struct pci_dev *pdev)
+{
+        /* enable the OHCI interrupt in PIC */
+        /* THE OHCI, EHCI, UDC, OTG are shared with interrupt in PIC */
+        pci_write_config_dword(pdev, PCI_OHCI_INT_REG, 1);
+}
+
+static void __init loongson_cs5536_ehci_fixup(struct pci_dev *pdev)
+{
+        u32 hi, lo;
+
+        /* Serial short detect enable */
+        _rdmsr(USB_MSR_REG(USB_CONFIG), &hi, &lo);
+        _wrmsr(USB_MSR_REG(USB_CONFIG), (1 << 1) | (1 << 2) | (1 << 3), lo);
+
+        /* setting the USB2.0 micro frame length */
+        pci_write_config_dword(pdev, PCI_EHCI_FLADJ_REG, 0x2000);
+}
+
+static void __init loongson_nec_fixup(struct pci_dev *pdev)
+{
+        unsigned int val;
+
+        pci_read_config_dword(pdev, 0xe0, &val);
+        /* Only 2 port be used */
+        pci_write_config_dword(pdev, 0xe0, (val & ~3) | 0x2);
+}
+
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA,
+                         loongson_cs5536_isa_fixup);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OHC,
+                         loongson_cs5536_ohci_fixup);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_EHC,
+                         loongson_cs5536_ehci_fixup);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_AUDIO,
+                         loongson_cs5536_acc_fixup);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_IDE,
+                         loongson_cs5536_ide_fixup);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
+                         loongson_nec_fixup);
diff --git a/arch/mips/pci/ops-bonito64.c b/arch/mips/pci/ops-bonito64.c
index 54e55e7a2431..1b3e03f20c54 100644
--- a/arch/mips/pci/ops-bonito64.c
+++ b/arch/mips/pci/ops-bonito64.c
@@ -29,13 +29,8 @@
 #define PCI_ACCESS_READ  0
 #define PCI_ACCESS_WRITE 1
 
-#ifdef CONFIG_LEMOTE_FULOONG2E
-#define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(BONITO_PCICFG_BASE | (offset))
-#define ID_SEL_BEGIN 11
-#else
 #define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(_pcictrl_bonito_pcicfg + (offset))
 #define ID_SEL_BEGIN 10
-#endif
 #define MAX_DEV_NUM (31 - ID_SEL_BEGIN)
 
 
@@ -77,10 +72,8 @@ static int bonito64_pcibios_config_access(unsigned char access_type,
         addrp = CFG_SPACE_REG(addr & 0xffff);
         if (access_type == PCI_ACCESS_WRITE) {
                 writel(cpu_to_le32(*data), addrp);
-#ifndef CONFIG_LEMOTE_FULOONG2E
                 /* Wait till done */
                 while (BONITO_PCIMSTAT & 0xF);
-#endif
         } else {
                 *data = le32_to_cpu(readl(addrp));
         }
diff --git a/arch/mips/pci/ops-loongson2.c b/arch/mips/pci/ops-loongson2.c
new file mode 100644
index 000000000000..aa5d3da27212
--- /dev/null
+++ b/arch/mips/pci/ops-loongson2.c
@@ -0,0 +1,208 @@
+/*
+ * fuloong2e specific PCI support.
+ *
+ * Copyright (C) 1999, 2000, 2004  MIPS Technologies, Inc.
+ *      All rights reserved.
+ *      Authors: Carsten Langgaard <carstenl@mips.com>
+ *               Maciej W. Rozycki <macro@mips.com>
+ *
+ * Copyright (C) 2009 Lemote Inc.
+ * Author: Wu Zhangjin <wuzj@lemote.com>
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ */
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <loongson.h>
+
+#ifdef CONFIG_CS5536
+#include <cs5536/cs5536_pci.h>
+#include <cs5536/cs5536.h>
+#endif
+
+#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_WRITE 1
+
+#define CFG_SPACE_REG(offset) \
+        (void *)CKSEG1ADDR(LOONGSON_PCICFG_BASE | (offset))
+#define ID_SEL_BEGIN 11
+#define MAX_DEV_NUM (31 - ID_SEL_BEGIN)
+
+
+static int loongson_pcibios_config_access(unsigned char access_type,
+                                      struct pci_bus *bus,
+                                      unsigned int devfn, int where,
+                                      u32 *data)
+{
+        u32 busnum = bus->number;
+        u32 addr, type;
+        u32 dummy;
+        void *addrp;
+        int device = PCI_SLOT(devfn);
+        int function = PCI_FUNC(devfn);
+        int reg = where & ~3;
+
+        if (busnum == 0) {
+                /* board-specific part,currently,only fuloong2f,yeeloong2f
+                 * use CS5536, fuloong2e use via686b, gdium has no
+                 * south bridge
+                 */
+#ifdef CONFIG_CS5536
+                /* cs5536_pci_conf_read4/write4() will call _rdmsr/_wrmsr() to
+                 * access the regsters PCI_MSR_ADDR, PCI_MSR_DATA_LO,
+                 * PCI_MSR_DATA_HI, which is bigger than PCI_MSR_CTRL, so, it
+                 * will not go this branch, but the others. so, no calling dead
+                 * loop here.
+                 */
+                if ((PCI_IDSEL_CS5536 == device) && (reg < PCI_MSR_CTRL)) {
+                        switch (access_type) {
+                        case PCI_ACCESS_READ:
+                                *data = cs5536_pci_conf_read4(function, reg);
+                                break;
+                        case PCI_ACCESS_WRITE:
+                                cs5536_pci_conf_write4(function, reg, *data);
+                                break;
+                        }
+                        return 0;
+                }
+#endif
+                /* Type 0 configuration for onboard PCI bus */
+                if (device > MAX_DEV_NUM)
+                        return -1;
+
+                addr = (1 << (device + ID_SEL_BEGIN)) | (function << 8) | reg;
+                type = 0;
+        } else {
+                /* Type 1 configuration for offboard PCI bus */
+                addr = (busnum << 16) | (device << 11) | (function << 8) | reg;
+                type = 0x10000;
+        }
+
+        /* Clear aborts */
+        LOONGSON_PCICMD |= LOONGSON_PCICMD_MABORT_CLR | \
+                                LOONGSON_PCICMD_MTABORT_CLR;
+
+        LOONGSON_PCIMAP_CFG = (addr >> 16) | type;
+
+        /* Flush Bonito register block */
+        dummy = LOONGSON_PCIMAP_CFG;
+        mmiowb();
+
+        addrp = CFG_SPACE_REG(addr & 0xffff);
+        if (access_type == PCI_ACCESS_WRITE)
+                writel(cpu_to_le32(*data), addrp);
+        else
+                *data = le32_to_cpu(readl(addrp));
+
+        /* Detect Master/Target abort */
+        if (LOONGSON_PCICMD & (LOONGSON_PCICMD_MABORT_CLR |
+                             LOONGSON_PCICMD_MTABORT_CLR)) {
+                /* Error occurred */
+
+                /* Clear bits */
+                LOONGSON_PCICMD |= (LOONGSON_PCICMD_MABORT_CLR |
+                                  LOONGSON_PCICMD_MTABORT_CLR);
+
+                return -1;
+        }
+
+        return 0;
+
+}
+
+
+/*
+ * We can't address 8 and 16 bit words directly.  Instead we have to
+ * read/write a 32bit word and mask/modify the data we actually want.
+ */
+static int loongson_pcibios_read(struct pci_bus *bus, unsigned int devfn,
+                             int where, int size, u32 *val)
+{
+        u32 data = 0;
+
+        if ((size == 2) && (where & 1))
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+        else if ((size == 4) && (where & 3))
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+
+        if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
+                                       &data))
+                return -1;
+
+        if (size == 1)
+                *val = (data >> ((where & 3) << 3)) & 0xff;
+        else if (size == 2)
+                *val = (data >> ((where & 3) << 3)) & 0xffff;
+        else
+                *val = data;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int loongson_pcibios_write(struct pci_bus *bus, unsigned int devfn,
+                              int where, int size, u32 val)
+{
+        u32 data = 0;
+
+        if ((size == 2) && (where & 1))
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+        else if ((size == 4) && (where & 3))
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+
+        if (size == 4)
+                data = val;
+        else {
+                if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
+                                        where, &data))
+                        return -1;
+
+                if (size == 1)
+                        data = (data & ~(0xff << ((where & 3) << 3))) |
+                                (val << ((where & 3) << 3));
+                else if (size == 2)
+                        data = (data & ~(0xffff << ((where & 3) << 3))) |
+                                (val << ((where & 3) << 3));
+        }
+
+        if (loongson_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where,
+                                       &data))
+                return -1;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+struct pci_ops loongson_pci_ops = {
+        .read = loongson_pcibios_read,
+        .write = loongson_pcibios_write
+};
+
+#ifdef CONFIG_CS5536
+void _rdmsr(u32 msr, u32 *hi, u32 *lo)
+{
+        struct pci_bus bus = {
+                .number = PCI_BUS_CS5536
+        };
+        u32 devfn = PCI_DEVFN(PCI_IDSEL_CS5536, 0);
+        loongson_pcibios_write(&bus, devfn, PCI_MSR_ADDR, 4, msr);
+        loongson_pcibios_read(&bus, devfn, PCI_MSR_DATA_LO, 4, lo);
+        loongson_pcibios_read(&bus, devfn, PCI_MSR_DATA_HI, 4, hi);
+}
+EXPORT_SYMBOL(_rdmsr);
+
+void _wrmsr(u32 msr, u32 hi, u32 lo)
+{
+        struct pci_bus bus = {
+                .number = PCI_BUS_CS5536
+        };
+        u32 devfn = PCI_DEVFN(PCI_IDSEL_CS5536, 0);
+        loongson_pcibios_write(&bus, devfn, PCI_MSR_ADDR, 4, msr);
+        loongson_pcibios_write(&bus, devfn, PCI_MSR_DATA_LO, 4, lo);
+        loongson_pcibios_write(&bus, devfn, PCI_MSR_DATA_HI, 4, hi);
+}
+EXPORT_SYMBOL(_wrmsr);
+#endif
diff --git a/arch/mips/pci/pci-excite.c b/arch/mips/pci/pci-excite.c
deleted file mode 100644
index 8a56876afcc6..000000000000
--- a/arch/mips/pci/pci-excite.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- *  Copyright (C) 2004 by Basler Vision Technologies AG
- *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
- *  Based on the PMC-Sierra Yosemite board support by Ralf Baechle.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/bitops.h>
-#include <asm/rm9k-ocd.h>
-#include <excite.h>
-
-
-extern struct pci_ops titan_pci_ops;
-
-
-static struct resource
-        mem_resource =  {
-                .name   = "PCI memory",
-                .start  = EXCITE_PHYS_PCI_MEM,
-                .end    = EXCITE_PHYS_PCI_MEM + EXCITE_SIZE_PCI_MEM - 1,
-                .flags  = IORESOURCE_MEM
-        },
-        io_resource = {
-                .name   = "PCI I/O",
-                .start  = EXCITE_PHYS_PCI_IO,
-                .end    = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1,
-                .flags  = IORESOURCE_IO
-        };
-
-
-static struct pci_controller bx_controller = {
-        .pci_ops        = &titan_pci_ops,
-        .mem_resource   = &mem_resource,
-        .mem_offset     = 0x00000000UL,
-        .io_resource    = &io_resource,
-        .io_offset      = 0x00000000UL
-};
-
-
-static char
-        iopage_failed[] __initdata   = "Cannot allocate PCI I/O page",
-        modebits_no_pci[] __initdata = "PCI is not configured in mode bits";
-
-#define RM9000x2_OCD_HTSC       0x0604
-#define RM9000x2_OCD_HTBHL      0x060c
-#define RM9000x2_OCD_PCIHRST    0x078c
-
-#define RM9K_OCD_MODEBIT1       0x00d4 /* (MODEBIT1) Mode Bit 1 */
-#define RM9K_OCD_CPHDCR         0x00f4 /* CPU-PCI/HT Data Control. */
-
-#define PCISC_FB2B              0x00000200
-#define PCISC_MWICG             0x00000010
-#define PCISC_EMC               0x00000004
-#define PCISC_ERMA              0x00000002
-
-
-
-static int __init basler_excite_pci_setup(void)
-{
-        const unsigned int fullbars = memsize / (256 << 20);
-        unsigned int i;
-
-        /* Check modebits to see if PCI is really enabled. */
-        if (!((ocd_readl(RM9K_OCD_MODEBIT1) >> (47-32)) & 0x1))
-                panic(modebits_no_pci);
-
-        if (NULL == request_mem_region(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO,
-                                       "Memory-mapped PCI I/O page"))
-                panic(iopage_failed);
-
-        /* Enable PCI 0 as master for config cycles */
-        ocd_writel(PCISC_EMC | PCISC_ERMA, RM9000x2_OCD_HTSC);
-
-
-        /* Set up latency timer */
-        ocd_writel(0x8008, RM9000x2_OCD_HTBHL);
-
-        /*  Setup host IO and Memory space */
-        ocd_writel((EXCITE_PHYS_PCI_IO >> 4) | 1, LKB7);
-        ocd_writel(((EXCITE_SIZE_PCI_IO >> 4) & 0x7fffff00) - 0x100, LKM7);
-        ocd_writel((EXCITE_PHYS_PCI_MEM >> 4) | 1, LKB8);
-        ocd_writel(((EXCITE_SIZE_PCI_MEM >> 4) & 0x7fffff00) - 0x100, LKM8);
-
-        /* Set up PCI BARs to map all installed memory */
-        for (i = 0; i < 6; i++) {
-                const unsigned int bar = 0x610 + i * 4;
-
-                if (i < fullbars) {
-                        ocd_writel(0x10000000 * i, bar);
-                        ocd_writel(0x01000000 * i, bar + 0x140);
-                        ocd_writel(0x0ffff029, bar + 0x100);
-                        continue;
-                }
-
-                if (i == fullbars) {
-                        int o;
-                        u32 mask;
-
-                        const unsigned long rem = memsize - i * 0x10000000;
-                        if (!rem) {
-                                ocd_writel(0x00000000, bar + 0x100);
-                                continue;
-                        }
-
-                        o = ffs(rem) - 1;
-                        if (rem & ~(0x1 << o))
-                                o++;
-                        mask = ((0x1 << o) & 0x0ffff000) - 0x1000;
-                        ocd_writel(0x10000000 * i, bar);
-                        ocd_writel(0x01000000 * i, bar + 0x140);
-                        ocd_writel(0x00000029 | mask, bar + 0x100);
-                        continue;
-                }
-
-                ocd_writel(0x00000000, bar + 0x100);
-        }
-
-        /* Finally, enable the PCI interrupt */
-#if USB_IRQ > 7
-        set_c0_intcontrol(1 << USB_IRQ);
-#else
-        set_c0_status(1 << (USB_IRQ + 8));
-#endif
-
-        ioport_resource.start = EXCITE_PHYS_PCI_IO;
-        ioport_resource.end = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1;
-        set_io_port_base((unsigned long) ioremap_nocache(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO));
-        register_pci_controller(&bx_controller);
-        return 0;
-}
-
-
-arch_initcall(basler_excite_pci_setup);
diff --git a/arch/mips/powertv/Kconfig b/arch/mips/powertv/Kconfig
new file mode 100644
index 000000000000..ff0e7e3e6954
--- /dev/null
+++ b/arch/mips/powertv/Kconfig
@@ -0,0 +1,21 @@
+source "arch/mips/powertv/asic/Kconfig"
+
+config BOOTLOADER_DRIVER
+        bool "PowerTV Bootloader Driver Support"
+        default n
+        depends on POWERTV
+        help
+          Use this option if you want to load bootloader driver.
+
+config BOOTLOADER_FAMILY
+        string "POWERTV Bootloader Family string"
+        default "85"
+        depends on POWERTV && !BOOTLOADER_DRIVER
+        help
+          This value should be specified when the bootloader driver is disabled
+          and must be exactly two characters long. Families supported are:
+            R1 - RNG-100  R2 - RNG-200
+            A1 - Class A  B1 - Class B
+            E1 - Class E  F1 - Class F
+            44 - 45xx     46 - 46xx
+            85 - 85xx     86 - 86xx
diff --git a/arch/mips/powertv/Makefile b/arch/mips/powertv/Makefile
new file mode 100644
index 000000000000..2c516718affe
--- /dev/null
+++ b/arch/mips/powertv/Makefile
@@ -0,0 +1,28 @@
+#
+# Carsten Langgaard, carstenl@mips.com
+# Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
+#
+# Carsten Langgaard, carstenl@mips.com
+# Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+# Portions copyright (C)  2009 Cisco Systems, Inc.
+#
+# This program is free software; you can distribute it and/or modify it
+# under the terms of the GNU General Public License (Version 2) as
+# published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+# for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+#
+# Makefile for the Cisco PowerTV-specific kernel interface routines
+# under Linux.
+#
+
+obj-y += cmdline.o init.o memory.o reset.o time.o powertv_setup.o asic/ pci/
+
+EXTRA_CFLAGS += -Wall -Werror
diff --git a/arch/mips/powertv/asic/Kconfig b/arch/mips/powertv/asic/Kconfig
new file mode 100644
index 000000000000..2016bfe94d66
--- /dev/null
+++ b/arch/mips/powertv/asic/Kconfig
@@ -0,0 +1,28 @@
+config MIN_RUNTIME_RESOURCES
+        bool "Support for minimum runtime resources"
+        default n
+        depends on POWERTV
+        help
+          Enables support for minimizing the number of (SA asic) runtime
+          resources that are preallocated by the kernel.
+
+config MIN_RUNTIME_DOCSIS
+        bool "Support for minimum DOCSIS resource"
+        default y
+        depends on MIN_RUNTIME_RESOURCES
+        help
+          Enables support for the preallocated DOCSIS resource.
+
+config MIN_RUNTIME_PMEM
+        bool "Support for minimum PMEM resource"
+        default y
+        depends on MIN_RUNTIME_RESOURCES
+        help
+          Enables support for the preallocated Memory resource.
+
+config MIN_RUNTIME_TFTP
+        bool "Support for minimum TFTP resource"
+        default y
+        depends on MIN_RUNTIME_RESOURCES
+        help
+          Enables support for the preallocated TFTP resource.
diff --git a/arch/mips/powertv/asic/Makefile b/arch/mips/powertv/asic/Makefile
new file mode 100644
index 000000000000..bebfdcff0443
--- /dev/null
+++ b/arch/mips/powertv/asic/Makefile
@@ -0,0 +1,23 @@
+#
+# Copyright (C) 2009  Scientific-Atlanta, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+obj-y += asic-calliope.o asic-cronus.o asic-zeus.o asic_devices.o asic_int.o \
+         irq_asic.o prealloc-calliope.o prealloc-cronus.o \
+         prealloc-cronuslite.o prealloc-zeus.o
+
+EXTRA_CFLAGS += -Wall -Werror
diff --git a/arch/mips/powertv/asic/asic-calliope.c b/arch/mips/powertv/asic/asic-calliope.c
new file mode 100644
index 000000000000..03d3884c6270
--- /dev/null
+++ b/arch/mips/powertv/asic/asic-calliope.c
@@ -0,0 +1,98 @@
+/*
+ * Locations of devices in the Calliope ASIC.
+ *
+ * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * Author:       Ken Eppinett
+ *               David Schleef <ds@schleef.org>
+ *
+ * Description:  Defines the platform resources for the SA settop.
+ */
+
+#include <asm/mach-powertv/asic.h>
+
+const struct register_map calliope_register_map = {
+        .eic_slow0_strt_add = 0x800000,
+        .eic_cfg_bits = 0x800038,
+        .eic_ready_status = 0x80004c,
+
+        .chipver3 = 0xA00800,
+        .chipver2 = 0xA00804,
+        .chipver1 = 0xA00808,
+        .chipver0 = 0xA0080c,
+
+        /* The registers of IRBlaster */
+        .uart1_intstat = 0xA01800,
+        .uart1_inten = 0xA01804,
+        .uart1_config1 = 0xA01808,
+        .uart1_config2 = 0xA0180C,
+        .uart1_divisorhi = 0xA01810,
+        .uart1_divisorlo = 0xA01814,
+        .uart1_data = 0xA01818,
+        .uart1_status = 0xA0181C,
+
+        .int_stat_3 = 0xA02800,
+        .int_stat_2 = 0xA02804,
+        .int_stat_1 = 0xA02808,
+        .int_stat_0 = 0xA0280c,
+        .int_config = 0xA02810,
+        .int_int_scan = 0xA02818,
+        .ien_int_3 = 0xA02830,
+        .ien_int_2 = 0xA02834,
+        .ien_int_1 = 0xA02838,
+        .ien_int_0 = 0xA0283c,
+        .int_level_3_3 = 0xA02880,
+        .int_level_3_2 = 0xA02884,
+        .int_level_3_1 = 0xA02888,
+        .int_level_3_0 = 0xA0288c,
+        .int_level_2_3 = 0xA02890,
+        .int_level_2_2 = 0xA02894,
+        .int_level_2_1 = 0xA02898,
+        .int_level_2_0 = 0xA0289c,
+        .int_level_1_3 = 0xA028a0,
+        .int_level_1_2 = 0xA028a4,
+        .int_level_1_1 = 0xA028a8,
+        .int_level_1_0 = 0xA028ac,
+        .int_level_0_3 = 0xA028b0,
+        .int_level_0_2 = 0xA028b4,
+        .int_level_0_1 = 0xA028b8,
+        .int_level_0_0 = 0xA028bc,
+        .int_docsis_en = 0xA028F4,
+
+        .mips_pll_setup = 0x980000,
+        .usb_fs = 0x980030,             /* -default 72800028- */
+        .test_bus = 0x9800CC,
+        .crt_spare = 0x9800d4,
+        .usb2_ohci_int_mask = 0x9A000c,
+        .usb2_strap = 0x9A0014,
+        .ehci_hcapbase = 0x9BFE00,
+        .ohci_hc_revision = 0x9BFC00,
+        .bcm1_bs_lmi_steer = 0x9E0004,
+        .usb2_control = 0x9E0054,
+        .usb2_stbus_obc = 0x9BFF00,
+        .usb2_stbus_mess_size = 0x9BFF04,
+        .usb2_stbus_chunk_size = 0x9BFF08,
+
+        .pcie_regs = 0x000000,          /* -doesn't exist- */
+        .tim_ch = 0xA02C10,
+        .tim_cl = 0xA02C14,
+        .gpio_dout = 0xA02c20,
+        .gpio_din = 0xA02c24,
+        .gpio_dir = 0xA02c2C,
+        .watchdog = 0xA02c30,
+        .front_panel = 0x000000,        /* -not used- */
+};
diff --git a/arch/mips/powertv/asic/asic-cronus.c b/arch/mips/powertv/asic/asic-cronus.c
new file mode 100644
index 000000000000..5f4589c9f83d
--- /dev/null
+++ b/arch/mips/powertv/asic/asic-cronus.c
@@ -0,0 +1,98 @@
+/*
+ * Locations of devices in the Cronus ASIC
+ *
+ * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * Author:       Ken Eppinett
+ *               David Schleef <ds@schleef.org>
+ *
+ * Description:  Defines the platform resources for the SA settop.
+ */
+
+#include <asm/mach-powertv/asic.h>
+
+const struct register_map cronus_register_map = {
+        .eic_slow0_strt_add = 0x000000,
+        .eic_cfg_bits = 0x000038,
+        .eic_ready_status = 0x00004C,
+
+        .chipver3 = 0x2A0800,
+        .chipver2 = 0x2A0804,
+        .chipver1 = 0x2A0808,
+        .chipver0 = 0x2A080C,
+
+        /* The registers of IRBlaster */
+        .uart1_intstat = 0x2A1800,
+        .uart1_inten = 0x2A1804,
+        .uart1_config1 = 0x2A1808,
+        .uart1_config2 = 0x2A180C,
+        .uart1_divisorhi = 0x2A1810,
+        .uart1_divisorlo = 0x2A1814,
+        .uart1_data = 0x2A1818,
+        .uart1_status = 0x2A181C,
+
+        .int_stat_3 = 0x2A2800,
+        .int_stat_2 = 0x2A2804,
+        .int_stat_1 = 0x2A2808,
+        .int_stat_0 = 0x2A280C,
+        .int_config = 0x2A2810,
+        .int_int_scan = 0x2A2818,
+        .ien_int_3 = 0x2A2830,
+        .ien_int_2 = 0x2A2834,
+        .ien_int_1 = 0x2A2838,
+        .ien_int_0 = 0x2A283C,
+        .int_level_3_3 = 0x2A2880,
+        .int_level_3_2 = 0x2A2884,
+        .int_level_3_1 = 0x2A2888,
+        .int_level_3_0 = 0x2A288C,
+        .int_level_2_3 = 0x2A2890,
+        .int_level_2_2 = 0x2A2894,
+        .int_level_2_1 = 0x2A2898,
+        .int_level_2_0 = 0x2A289C,
+        .int_level_1_3 = 0x2A28A0,
+        .int_level_1_2 = 0x2A28A4,
+        .int_level_1_1 = 0x2A28A8,
+        .int_level_1_0 = 0x2A28AC,
+        .int_level_0_3 = 0x2A28B0,
+        .int_level_0_2 = 0x2A28B4,
+        .int_level_0_1 = 0x2A28B8,
+        .int_level_0_0 = 0x2A28BC,
+        .int_docsis_en = 0x2A28F4,
+
+        .mips_pll_setup = 0x1C0000,
+        .usb_fs = 0x1C0018,
+        .test_bus = 0x1C00CC,
+        .crt_spare = 0x1c00d4,
+        .usb2_ohci_int_mask = 0x20000C,
+        .usb2_strap = 0x200014,
+        .ehci_hcapbase = 0x21FE00,
+        .ohci_hc_revision = 0x1E0000,
+        .bcm1_bs_lmi_steer = 0x2E0008,
+        .usb2_control = 0x2E004C,
+        .usb2_stbus_obc = 0x21FF00,
+        .usb2_stbus_mess_size = 0x21FF04,
+        .usb2_stbus_chunk_size = 0x21FF08,
+
+        .pcie_regs = 0x220000,
+        .tim_ch = 0x2A2C10,
+        .tim_cl = 0x2A2C14,
+        .gpio_dout = 0x2A2C20,
+        .gpio_din = 0x2A2C24,
+        .gpio_dir = 0x2A2C2C,
+        .watchdog = 0x2A2C30,
+        .front_panel = 0x2A3800,
+};
diff --git a/arch/mips/powertv/asic/asic-zeus.c b/arch/mips/powertv/asic/asic-zeus.c
new file mode 100644
index 000000000000..1469daab920e
--- /dev/null
+++ b/arch/mips/powertv/asic/asic-zeus.c
@@ -0,0 +1,98 @@
+/*
+ * Locations of devices in the Zeus ASIC
+ *
+ * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * Author:       Ken Eppinett
+ *               David Schleef <ds@schleef.org>
+ *
+ * Description:  Defines the platform resources for the SA settop.
+ */
+
+#include <asm/mach-powertv/asic.h>
+
+const struct register_map zeus_register_map = {
+        .eic_slow0_strt_add = 0x000000,
+        .eic_cfg_bits = 0x000038,
+        .eic_ready_status = 0x00004c,
+
+        .chipver3 = 0x280800,
+        .chipver2 = 0x280804,
+        .chipver1 = 0x280808,
+        .chipver0 = 0x28080c,
+
+        /* The registers of IRBlaster */
+        .uart1_intstat = 0x281800,
+        .uart1_inten = 0x281804,
+        .uart1_config1 = 0x281808,
+        .uart1_config2 = 0x28180C,
+        .uart1_divisorhi = 0x281810,
+        .uart1_divisorlo = 0x281814,
+        .uart1_data = 0x281818,
+        .uart1_status = 0x28181C,
+
+        .int_stat_3 = 0x282800,
+        .int_stat_2 = 0x282804,
+        .int_stat_1 = 0x282808,
+        .int_stat_0 = 0x28280c,
+        .int_config = 0x282810,
+        .int_int_scan = 0x282818,
+        .ien_int_3 = 0x282830,
+        .ien_int_2 = 0x282834,
+        .ien_int_1 = 0x282838,
+        .ien_int_0 = 0x28283c,
+        .int_level_3_3 = 0x282880,
+        .int_level_3_2 = 0x282884,
+        .int_level_3_1 = 0x282888,
+        .int_level_3_0 = 0x28288c,
+        .int_level_2_3 = 0x282890,
+        .int_level_2_2 = 0x282894,
+        .int_level_2_1 = 0x282898,
+        .int_level_2_0 = 0x28289c,
+        .int_level_1_3 = 0x2828a0,
+        .int_level_1_2 = 0x2828a4,
+        .int_level_1_1 = 0x2828a8,
+        .int_level_1_0 = 0x2828ac,
+        .int_level_0_3 = 0x2828b0,
+        .int_level_0_2 = 0x2828b4,
+        .int_level_0_1 = 0x2828b8,
+        .int_level_0_0 = 0x2828bc,
+        .int_docsis_en = 0x2828F4,
+
+        .mips_pll_setup = 0x1a0000,
+        .usb_fs = 0x1a0018,
+        .test_bus = 0x1a0238,
+        .crt_spare = 0x1a0090,
+        .usb2_ohci_int_mask = 0x1e000c,
+        .usb2_strap = 0x1e0014,
+        .ehci_hcapbase = 0x1FFE00,
+        .ohci_hc_revision = 0x1FFC00,
+        .bcm1_bs_lmi_steer = 0x2C0008,
+        .usb2_control = 0x2c01a0,
+        .usb2_stbus_obc = 0x1FFF00,
+        .usb2_stbus_mess_size = 0x1FFF04,
+        .usb2_stbus_chunk_size = 0x1FFF08,
+
+        .pcie_regs = 0x200000,
+        .tim_ch = 0x282C10,
+        .tim_cl = 0x282C14,
+        .gpio_dout = 0x282c20,
+        .gpio_din = 0x282c24,
+        .gpio_dir = 0x282c2C,
+        .watchdog = 0x282c30,
+        .front_panel = 0x283800,
+};
diff --git a/arch/mips/powertv/asic/asic_devices.c b/arch/mips/powertv/asic/asic_devices.c
new file mode 100644
index 000000000000..bae82880b6b5
--- /dev/null
+++ b/arch/mips/powertv/asic/asic_devices.c
@@ -0,0 +1,787 @@
+/*
+ *                   ASIC Device List Intialization
+ *
+ * Description:  Defines the platform resources for the SA settop.
+ *
+ * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * Author:       Ken Eppinett
+ *               David Schleef <ds@schleef.org>
+ *
+ * Description:  Defines the platform resources for the SA settop.
+ *
+ * NOTE: The bootloader allocates persistent memory at an address which is
+ * 16 MiB below the end of the highest address in KSEG0. All fixed
+ * address memory reservations must avoid this region.
+ */
+
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/resource.h>
+#include <linux/serial_reg.h>
+#include <linux/io.h>
+#include <linux/bootmem.h>
+#include <linux/mm.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <asm/page.h>
+#include <linux/swap.h>
+#include <linux/highmem.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/mach-powertv/asic.h>
+#include <asm/mach-powertv/asic_regs.h>
+#include <asm/mach-powertv/interrupts.h>
+
+#ifdef CONFIG_BOOTLOADER_DRIVER
+#include <asm/mach-powertv/kbldr.h>
+#endif
+#include <asm/bootinfo.h>
+
+#define BOOTLDRFAMILY(byte1, byte0) (((byte1) << 8) | (byte0))
+
+/*
+ * Forward Prototypes
+ */
+static void pmem_setup_resource(void);
+
+/*
+ * Global Variables
+ */
+enum asic_type asic;
+
+unsigned int platform_features;
+unsigned int platform_family;
+const struct register_map  *register_map;
+EXPORT_SYMBOL(register_map);                    /* Exported for testing */
+unsigned long asic_phy_base;
+unsigned long asic_base;
+EXPORT_SYMBOL(asic_base);                       /* Exported for testing */
+struct resource *gp_resources;
+static bool usb_configured;
+
+/*
+ * Don't recommend to use it directly, it is usually used by kernel internally.
+ * Portable code should be using interfaces such as ioremp, dma_map_single, etc.
+ */
+unsigned long phys_to_bus_offset;
+EXPORT_SYMBOL(phys_to_bus_offset);
+
+/*
+ *
+ * IO Resource Definition
+ *
+ */
+
+struct resource asic_resource = {
+        .name  = "ASIC Resource",
+        .start = 0,
+        .end   = ASIC_IO_SIZE,
+        .flags = IORESOURCE_MEM,
+};
+
+/*
+ *
+ * USB Host Resource Definition
+ *
+ */
+
+static struct resource ehci_resources[] = {
+        {
+                .parent = &asic_resource,
+                .start  = 0,
+                .end    = 0xff,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = irq_usbehci,
+                .end    = irq_usbehci,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 ehci_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device ehci_device = {
+        .name = "powertv-ehci",
+        .id = 0,
+        .num_resources = 2,
+        .resource = ehci_resources,
+        .dev = {
+                .dma_mask = &ehci_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+};
+
+static struct resource ohci_resources[] = {
+        {
+                .parent = &asic_resource,
+                .start  = 0,
+                .end    = 0xff,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = irq_usbohci,
+                .end    = irq_usbohci,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 ohci_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device ohci_device = {
+        .name = "powertv-ohci",
+        .id = 0,
+        .num_resources = 2,
+        .resource = ohci_resources,
+        .dev = {
+                .dma_mask = &ohci_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+};
+
+static struct platform_device *platform_devices[] = {
+        &ehci_device,
+        &ohci_device,
+};
+
+/*
+ *
+ * Platform Configuration and Device Initialization
+ *
+ */
+static void __init fs_update(int pe, int md, int sdiv, int disable_div_by_3)
+{
+        int en_prg, byp, pwr, nsb, val;
+        int sout;
+
+        sout = 1;
+        en_prg = 1;
+        byp = 0;
+        nsb = 1;
+        pwr = 1;
+
+        val = ((sdiv << 29) | (md << 24) | (pe<<8) | (sout<<3) | (byp<<2) |
+                (nsb<<1) | (disable_div_by_3<<5));
+
+        asic_write(val, usb_fs);
+        asic_write(val | (en_prg<<4), usb_fs);
+        asic_write(val | (en_prg<<4) | pwr, usb_fs);
+}
+
+/*
+ * Allow override of bootloader-specified model
+ */
+static char __initdata cmdline[COMMAND_LINE_SIZE];
+
+#define FORCEFAMILY_PARAM       "forcefamily"
+
+static __init int check_forcefamily(unsigned char forced_family[2])
+{
+        const char *p;
+
+        forced_family[0] = '\0';
+        forced_family[1] = '\0';
+
+        /* Check the command line for a forcefamily directive */
+        strncpy(cmdline, arcs_cmdline, COMMAND_LINE_SIZE - 1);
+        p = strstr(cmdline, FORCEFAMILY_PARAM);
+        if (p && (p != cmdline) && (*(p - 1) != ' '))
+                p = strstr(p, " " FORCEFAMILY_PARAM "=");
+
+        if (p) {
+                p += strlen(FORCEFAMILY_PARAM "=");
+
+                if (*p == '\0' || *(p + 1) == '\0' ||
+                        (*(p + 2) != '\0' && *(p + 2) != ' '))
+                        pr_err(FORCEFAMILY_PARAM " must be exactly two "
+                                "characters long, ignoring value\n");
+
+                else {
+                        forced_family[0] = *p;
+                        forced_family[1] = *(p + 1);
+                }
+        }
+
+        return 0;
+}
+
+/*
+ * platform_set_family - determine major platform family type.
+ *
+ * Returns family type; -1 if none
+ * Returns the family type; -1 if none
+ *
+ */
+static __init noinline void platform_set_family(void)
+{
+#define BOOTLDRFAMILY(byte1, byte0) (((byte1) << 8) | (byte0))
+
+        unsigned char forced_family[2];
+        unsigned short bootldr_family;
+
+        check_forcefamily(forced_family);
+
+        if (forced_family[0] != '\0' && forced_family[1] != '\0')
+                bootldr_family = BOOTLDRFAMILY(forced_family[0],
+                        forced_family[1]);
+        else {
+
+#ifdef CONFIG_BOOTLOADER_DRIVER
+                bootldr_family = (unsigned short) kbldr_GetSWFamily();
+#else
+#if defined(CONFIG_BOOTLOADER_FAMILY)
+                bootldr_family = (unsigned short) BOOTLDRFAMILY(
+                        CONFIG_BOOTLOADER_FAMILY[0],
+                        CONFIG_BOOTLOADER_FAMILY[1]);
+#else
+#error "Unknown Bootloader Family"
+#endif
+#endif
+        }
+
+        pr_info("Bootloader Family = 0x%04X\n", bootldr_family);
+
+        switch (bootldr_family) {
+        case BOOTLDRFAMILY('R', '1'):
+                platform_family = FAMILY_1500;
+                break;
+        case BOOTLDRFAMILY('4', '4'):
+                platform_family = FAMILY_4500;
+                break;
+        case BOOTLDRFAMILY('4', '6'):
+                platform_family = FAMILY_4600;
+                break;
+        case BOOTLDRFAMILY('A', '1'):
+                platform_family = FAMILY_4600VZA;
+                break;
+        case BOOTLDRFAMILY('8', '5'):
+                platform_family = FAMILY_8500;
+                break;
+        case BOOTLDRFAMILY('R', '2'):
+                platform_family = FAMILY_8500RNG;
+                break;
+        case BOOTLDRFAMILY('8', '6'):
+                platform_family = FAMILY_8600;
+                break;
+        case BOOTLDRFAMILY('B', '1'):
+                platform_family = FAMILY_8600VZB;
+                break;
+        case BOOTLDRFAMILY('E', '1'):
+                platform_family = FAMILY_1500VZE;
+                break;
+        case BOOTLDRFAMILY('F', '1'):
+                platform_family = FAMILY_1500VZF;
+                break;
+        default:
+                platform_family = -1;
+        }
+}
+
+unsigned int platform_get_family(void)
+{
+        return platform_family;
+}
+EXPORT_SYMBOL(platform_get_family);
+
+/*
+ * \brief usb_eye_configure() for optimizing the USB eye on Calliope.
+ *
+ * \param     unsigned int value saved to the register.
+ *
+ * \return    none
+ *
+ */
+static void __init usb_eye_configure(unsigned int value)
+{
+        asic_write(asic_read(crt_spare) | value, crt_spare);
+}
+
+/*
+ * platform_get_asic - determine the ASIC type.
+ *
+ * \param     none
+ *
+ * \return    ASIC type; ASIC_UNKNOWN if none
+ *
+ */
+enum asic_type platform_get_asic(void)
+{
+        return asic;
+}
+EXPORT_SYMBOL(platform_get_asic);
+
+/*
+ * platform_configure_usb - usb configuration based on platform type.
+ * @bcm1_usb2_ctl:      value for the BCM1_USB2_CTL register, which is
+ *                      quirky
+ */
+static void __init platform_configure_usb(void)
+{
+        u32 bcm1_usb2_ctl;
+
+        if (usb_configured)
+                return;
+
+        switch (asic) {
+        case ASIC_ZEUS:
+                fs_update(0x0000, 0x11, 0x02, 0);
+                bcm1_usb2_ctl = 0x803;
+                break;
+
+        case ASIC_CRONUS:
+        case ASIC_CRONUSLITE:
+                fs_update(0x0000, 0x11, 0x02, 0);
+                bcm1_usb2_ctl = 0x803;
+                break;
+
+        case ASIC_CALLIOPE:
+                fs_update(0x0000, 0x11, 0x02, 1);
+
+                switch (platform_family) {
+                case FAMILY_1500VZE:
+                        break;
+
+                case FAMILY_1500VZF:
+                        usb_eye_configure(0x003c0000);
+                        break;
+
+                default:
+                        usb_eye_configure(0x00300000);
+                        break;
+                }
+
+                bcm1_usb2_ctl = 0x803;
+                break;
+
+        default:
+                pr_err("Unknown ASIC type: %d\n", asic);
+                break;
+        }
+
+        /* turn on USB power */
+        asic_write(0, usb2_strap);
+        /* Enable all OHCI interrupts */
+        asic_write(bcm1_usb2_ctl, usb2_control);
+        /* USB2_STBUS_OBC store32/load32 */
+        asic_write(3, usb2_stbus_obc);
+        /* USB2_STBUS_MESS_SIZE 2 packets */
+        asic_write(1, usb2_stbus_mess_size);
+        /* USB2_STBUS_CHUNK_SIZE 2 packets */
+        asic_write(1, usb2_stbus_chunk_size);
+
+        usb_configured = true;
+}
+
+/*
+ * Set up the USB EHCI interface
+ */
+void platform_configure_usb_ehci()
+{
+        platform_configure_usb();
+}
+
+/*
+ * Set up the USB OHCI interface
+ */
+void platform_configure_usb_ohci()
+{
+        platform_configure_usb();
+}
+
+/*
+ * Shut the USB EHCI interface down--currently a NOP
+ */
+void platform_unconfigure_usb_ehci()
+{
+}
+
+/*
+ * Shut the USB OHCI interface down--currently a NOP
+ */
+void platform_unconfigure_usb_ohci()
+{
+}
+
+/**
+ * configure_platform - configuration based on platform type.
+ */
+void __init configure_platform(void)
+{
+        platform_set_family();
+
+        switch (platform_family) {
+        case FAMILY_1500:
+        case FAMILY_1500VZE:
+        case FAMILY_1500VZF:
+                platform_features = FFS_CAPABLE;
+                asic = ASIC_CALLIOPE;
+                asic_phy_base = CALLIOPE_IO_BASE;
+                register_map = &calliope_register_map;
+                asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
+                        ASIC_IO_SIZE);
+
+                if (platform_family == FAMILY_1500VZE) {
+                        gp_resources = non_dvr_vze_calliope_resources;
+                        pr_info("Platform: 1500/Vz Class E - "
+                                "CALLIOPE, NON_DVR_CAPABLE\n");
+                } else if (platform_family == FAMILY_1500VZF) {
+                        gp_resources = non_dvr_vzf_calliope_resources;
+                        pr_info("Platform: 1500/Vz Class F - "
+                                "CALLIOPE, NON_DVR_CAPABLE\n");
+                } else {
+                        gp_resources = non_dvr_calliope_resources;
+                        pr_info("Platform: 1500/RNG100 - CALLIOPE, "
+                                "NON_DVR_CAPABLE\n");
+                }
+                break;
+
+        case FAMILY_4500:
+                platform_features = FFS_CAPABLE | PCIE_CAPABLE |
+                        DISPLAY_CAPABLE;
+                asic = ASIC_ZEUS;
+                asic_phy_base = ZEUS_IO_BASE;
+                register_map = &zeus_register_map;
+                asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
+                        ASIC_IO_SIZE);
+                gp_resources = non_dvr_zeus_resources;
+
+                pr_info("Platform: 4500 - ZEUS, NON_DVR_CAPABLE\n");
+                break;
+
+        case FAMILY_4600:
+        {
+                unsigned int chipversion = 0;
+
+                /* The settop has PCIE but it isn't used, so don't advertise
+                 * it*/
+                platform_features = FFS_CAPABLE | DISPLAY_CAPABLE;
+                asic_phy_base = CRONUS_IO_BASE;   /* same as Cronus */
+                register_map = &cronus_register_map;   /* same as Cronus */
+                asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
+                        ASIC_IO_SIZE);
+                gp_resources = non_dvr_cronuslite_resources;
+
+                /* ASIC version will determine if this is a real CronusLite or
+                 * Castrati(Cronus) */
+                chipversion  = asic_read(chipver3) << 24;
+                chipversion |= asic_read(chipver2) << 16;
+                chipversion |= asic_read(chipver1) << 8;
+                chipversion |= asic_read(chipver0);
+
+                if ((chipversion == CRONUS_10) || (chipversion == CRONUS_11))
+                        asic = ASIC_CRONUS;
+                else
+                        asic = ASIC_CRONUSLITE;
+
+                pr_info("Platform: 4600 - %s, NON_DVR_CAPABLE, "
+                        "chipversion=0x%08X\n",
+                        (asic == ASIC_CRONUS) ? "CRONUS" : "CRONUS LITE",
+                        chipversion);
+                break;
+        }
+        case FAMILY_4600VZA:
+                platform_features = FFS_CAPABLE | DISPLAY_CAPABLE;
+                asic = ASIC_CRONUS;
+                asic_phy_base = CRONUS_IO_BASE;
+                register_map = &cronus_register_map;
+                asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
+                        ASIC_IO_SIZE);
+                gp_resources = non_dvr_cronus_resources;
+
+                pr_info("Platform: Vz Class A - CRONUS, NON_DVR_CAPABLE\n");
+                break;
+
+        case FAMILY_8500:
+        case FAMILY_8500RNG:
+                platform_features = DVR_CAPABLE | PCIE_CAPABLE |
+                        DISPLAY_CAPABLE;
+                asic = ASIC_ZEUS;
+                asic_phy_base = ZEUS_IO_BASE;
+                register_map = &zeus_register_map;
+                asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
+                        ASIC_IO_SIZE);
+                gp_resources = dvr_zeus_resources;
+
+                pr_info("Platform: 8500/RNG200 - ZEUS, DVR_CAPABLE\n");
+                break;
+
+        case FAMILY_8600:
+        case FAMILY_8600VZB:
+                platform_features = DVR_CAPABLE | PCIE_CAPABLE |
+                        DISPLAY_CAPABLE;
+                asic = ASIC_CRONUS;
+                asic_phy_base = CRONUS_IO_BASE;
+                register_map = &cronus_register_map;
+                asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
+                        ASIC_IO_SIZE);
+                gp_resources = dvr_cronus_resources;
+
+                pr_info("Platform: 8600/Vz Class B - CRONUS, "
+                        "DVR_CAPABLE\n");
+                break;
+
+        default:
+                pr_crit("Platform:  UNKNOWN PLATFORM\n");
+                break;
+        }
+
+        switch (asic) {
+        case ASIC_ZEUS:
+                phys_to_bus_offset = 0x30000000;
+                break;
+        case ASIC_CALLIOPE:
+                phys_to_bus_offset = 0x10000000;
+                break;
+        case ASIC_CRONUSLITE:
+                /* Fall through */
+        case ASIC_CRONUS:
+                /*
+                 * TODO: We suppose 0x10000000 aliases into 0x20000000-
+                 * 0x2XXXXXXX. If 0x10000000 aliases into 0x60000000-
+                 * 0x6XXXXXXX, the offset should be 0x50000000, not 0x10000000.
+                 */
+                phys_to_bus_offset = 0x10000000;
+                break;
+        default:
+                phys_to_bus_offset = 0x00000000;
+                break;
+        }
+}
+
+/**
+ * platform_devices_init - sets up USB device resourse.
+ */
+static int __init platform_devices_init(void)
+{
+        pr_notice("%s: ----- Initializing USB resources -----\n", __func__);
+
+        asic_resource.start = asic_phy_base;
+        asic_resource.end += asic_resource.start;
+
+        ehci_resources[0].start = asic_reg_phys_addr(ehci_hcapbase);
+        ehci_resources[0].end += ehci_resources[0].start;
+
+        ohci_resources[0].start = asic_reg_phys_addr(ohci_hc_revision);
+        ohci_resources[0].end += ohci_resources[0].start;
+
+        set_io_port_base(0);
+
+        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+
+        return 0;
+}
+
+arch_initcall(platform_devices_init);
+
+/*
+ *
+ * BOOTMEM ALLOCATION
+ *
+ */
+/*
+ * Allocates/reserves the Platform memory resources early in the boot process.
+ * This ignores any resources that are designated IORESOURCE_IO
+ */
+void __init platform_alloc_bootmem(void)
+{
+        int i;
+        int total = 0;
+
+        /* Get persistent memory data from command line before allocating
+         * resources. This need to happen before normal command line parsing
+         * has been done */
+        pmem_setup_resource();
+
+        /* Loop through looking for resources that want a particular address */
+        for (i = 0; gp_resources[i].flags != 0; i++) {
+                int size = gp_resources[i].end - gp_resources[i].start + 1;
+                if ((gp_resources[i].start != 0) &&
+                        ((gp_resources[i].flags & IORESOURCE_MEM) != 0)) {
+                        reserve_bootmem(bus_to_phys(gp_resources[i].start),
+                                size, 0);
+                        total += gp_resources[i].end -
+                                gp_resources[i].start + 1;
+                        pr_info("reserve resource %s at %08x (%u bytes)\n",
+                                gp_resources[i].name, gp_resources[i].start,
+                                gp_resources[i].end -
+                                        gp_resources[i].start + 1);
+                }
+        }
+
+        /* Loop through assigning addresses for those that are left */
+        for (i = 0; gp_resources[i].flags != 0; i++) {
+                int size = gp_resources[i].end - gp_resources[i].start + 1;
+                if ((gp_resources[i].start == 0) &&
+                        ((gp_resources[i].flags & IORESOURCE_MEM) != 0)) {
+                        void *mem = alloc_bootmem_pages(size);
+
+                        if (mem == NULL)
+                                pr_err("Unable to allocate bootmem pages "
+                                        "for %s\n", gp_resources[i].name);
+
+                        else {
+                                gp_resources[i].start =
+                                        phys_to_bus(virt_to_phys(mem));
+                                gp_resources[i].end =
+                                        gp_resources[i].start + size - 1;
+                                total += size;
+                                pr_info("allocate resource %s at %08x "
+                                                "(%u bytes)\n",
+                                        gp_resources[i].name,
+                                        gp_resources[i].start, size);
+                        }
+                }
+        }
+
+        pr_info("Total Platform driver memory allocation: 0x%08x\n", total);
+
+        /* indicate resources that are platform I/O related */
+        for (i = 0; gp_resources[i].flags != 0; i++) {
+                if ((gp_resources[i].start != 0) &&
+                        ((gp_resources[i].flags & IORESOURCE_IO) != 0)) {
+                        pr_info("reserved platform resource %s at %08x\n",
+                                gp_resources[i].name, gp_resources[i].start);
+                }
+        }
+}
+
+/*
+ *
+ * PERSISTENT MEMORY (PMEM) CONFIGURATION
+ *
+ */
+static unsigned long pmemaddr __initdata;
+
+static int __init early_param_pmemaddr(char *p)
+{
+        pmemaddr = (unsigned long)simple_strtoul(p, NULL, 0);
+        return 0;
+}
+early_param("pmemaddr", early_param_pmemaddr);
+
+static long pmemlen __initdata;
+
+static int __init early_param_pmemlen(char *p)
+{
+/* TODO: we can use this code when and if the bootloader ever changes this */
+#if 0
+        pmemlen = (unsigned long)simple_strtoul(p, NULL, 0);
+#else
+        pmemlen = 0x20000;
+#endif
+        return 0;
+}
+early_param("pmemlen", early_param_pmemlen);
+
+/*
+ * Set up persistent memory. If we were given values, we patch the array of
+ * resources. Otherwise, persistent memory may be allocated anywhere at all.
+ */
+static void __init pmem_setup_resource(void)
+{
+        struct resource *resource;
+        resource = asic_resource_get("DiagPersistentMemory");
+
+        if (resource && pmemaddr && pmemlen) {
+                /* The address provided by bootloader is in kseg0. Convert to
+                 * a bus address. */
+                resource->start = phys_to_bus(pmemaddr - 0x80000000);
+                resource->end = resource->start + pmemlen - 1;
+
+                pr_info("persistent memory: start=0x%x  end=0x%x\n",
+                        resource->start, resource->end);
+        }
+}
+
+/*
+ *
+ * RESOURCE ACCESS FUNCTIONS
+ *
+ */
+
+/**
+ * asic_resource_get - retrieves parameters for a platform resource.
+ * @name:       string to match resource
+ *
+ * Returns a pointer to a struct resource corresponding to the given name.
+ *
+ * CANNOT BE NAMED platform_resource_get, which would be the obvious choice,
+ * as this function name is already declared
+ */
+struct resource *asic_resource_get(const char *name)
+{
+        int i;
+
+        for (i = 0; gp_resources[i].flags != 0; i++) {
+                if (strcmp(gp_resources[i].name, name) == 0)
+                        return &gp_resources[i];
+        }
+
+        return NULL;
+}
+EXPORT_SYMBOL(asic_resource_get);
+
+/**
+ * platform_release_memory - release pre-allocated memory
+ * @ptr:        pointer to memory to release
+ * @size:       size of resource
+ *
+ * This must only be called for memory allocated or reserved via the boot
+ * memory allocator.
+ */
+void platform_release_memory(void *ptr, int size)
+{
+        unsigned long addr;
+        unsigned long end;
+
+        addr = ((unsigned long)ptr + (PAGE_SIZE - 1)) & PAGE_MASK;
+        end = ((unsigned long)ptr + size) & PAGE_MASK;
+
+        for (; addr < end; addr += PAGE_SIZE) {
+                ClearPageReserved(virt_to_page(__va(addr)));
+                init_page_count(virt_to_page(__va(addr)));
+                free_page((unsigned long)__va(addr));
+        }
+}
+EXPORT_SYMBOL(platform_release_memory);
+
+/*
+ *
+ * FEATURE AVAILABILITY FUNCTIONS
+ *
+ */
+int platform_supports_dvr(void)
+{
+        return (platform_features & DVR_CAPABLE) != 0;
+}
+
+int platform_supports_ffs(void)
+{
+        return (platform_features & FFS_CAPABLE) != 0;
+}
+
+int platform_supports_pcie(void)
+{
+        return (platform_features & PCIE_CAPABLE) != 0;
+}
+
+int platform_supports_display(void)
+{
+        return (platform_features & DISPLAY_CAPABLE) != 0;
+}
diff --git a/arch/mips/powertv/asic/asic_int.c b/arch/mips/powertv/asic/asic_int.c
new file mode 100644
index 000000000000..80b2eed21ac3
--- /dev/null
+++ b/arch/mips/powertv/asic/asic_int.c
@@ -0,0 +1,125 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
+ * Copyright (C) 2001 Ralf Baechle
+ * Portions copyright (C) 2009  Cisco Systems, Inc.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * Routines for generic manipulation of the interrupts found on the PowerTV
+ * platform.
+ *
+ * The interrupt controller is located in the South Bridge a PIIX4 device
+ * with two internal 82C95 interrupt controllers.
+ */
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/kernel_stat.h>
+#include <linux/kernel.h>
+#include <linux/random.h>
+
+#include <asm/irq_cpu.h>
+#include <linux/io.h>
+#include <asm/irq_regs.h>
+#include <asm/mips-boards/generic.h>
+
+#include <asm/mach-powertv/asic_regs.h>
+
+static DEFINE_SPINLOCK(asic_irq_lock);
+
+static inline int get_int(void)
+{
+        unsigned long flags;
+        int irq;
+
+        spin_lock_irqsave(&asic_irq_lock, flags);
+
+        irq = (asic_read(int_int_scan) >> 4) - 1;
+
+        if (irq == 0 || irq >= NR_IRQS)
+                irq = -1;
+
+        spin_unlock_irqrestore(&asic_irq_lock, flags);
+
+        return irq;
+}
+
+static void asic_irqdispatch(void)
+{
+        int irq;
+
+        irq = get_int();
+        if (irq < 0)
+                return;  /* interrupt has already been cleared */
+
+        do_IRQ(irq);
+}
+
+static inline int clz(unsigned long x)
+{
+        __asm__(
+        "       .set    push                                    \n"
+        "       .set    mips32                                  \n"
+        "       clz     %0, %1                                  \n"
+        "       .set    pop                                     \n"
+        : "=r" (x)
+        : "r" (x));
+
+        return x;
+}
+
+/*
+ * Version of ffs that only looks at bits 12..15.
+ */
+static inline unsigned int irq_ffs(unsigned int pending)
+{
+        return fls(pending) - 1 + CAUSEB_IP;
+}
+
+/*
+ * TODO: check how it works under EIC mode.
+ */
+asmlinkage void plat_irq_dispatch(void)
+{
+        unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
+        int irq;
+
+        irq = irq_ffs(pending);
+
+        if (irq == CAUSEF_IP3)
+                asic_irqdispatch();
+        else if (irq >= 0)
+                do_IRQ(irq);
+        else
+                spurious_interrupt();
+}
+
+void __init arch_init_irq(void)
+{
+        int i;
+
+        asic_irq_init();
+
+        /*
+         * Initialize interrupt exception vectors.
+         */
+        if (cpu_has_veic || cpu_has_vint) {
+                int nvec = cpu_has_veic ? 64 : 8;
+                for (i = 0; i < nvec; i++)
+                        set_vi_handler(i, asic_irqdispatch);
+        }
+}
diff --git a/arch/mips/powertv/asic/irq_asic.c b/arch/mips/powertv/asic/irq_asic.c
new file mode 100644
index 000000000000..b54d24499b06
--- /dev/null
+++ b/arch/mips/powertv/asic/irq_asic.c
@@ -0,0 +1,116 @@
+/*
+ * Portions copyright (C) 2005-2009 Scientific Atlanta
+ * Portions copyright (C) 2009 Cisco Systems, Inc.
+ *
+ * Modified from arch/mips/kernel/irq-rm7000.c:
+ * Copyright (C) 2003 Ralf Baechle
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+
+#include <asm/irq_cpu.h>
+#include <asm/mipsregs.h>
+#include <asm/system.h>
+
+#include <asm/mach-powertv/asic_regs.h>
+
+static inline void unmask_asic_irq(unsigned int irq)
+{
+        unsigned long enable_bit;
+
+        enable_bit = (1 << (irq & 0x1f));
+
+        switch (irq >> 5) {
+        case 0:
+                asic_write(asic_read(ien_int_0) | enable_bit, ien_int_0);
+                break;
+        case 1:
+                asic_write(asic_read(ien_int_1) | enable_bit, ien_int_1);
+                break;
+        case 2:
+                asic_write(asic_read(ien_int_2) | enable_bit, ien_int_2);
+                break;
+        case 3:
+                asic_write(asic_read(ien_int_3) | enable_bit, ien_int_3);
+                break;
+        default:
+                BUG();
+        }
+}
+
+static inline void mask_asic_irq(unsigned int irq)
+{
+        unsigned long disable_mask;
+
+        disable_mask = ~(1 << (irq & 0x1f));
+
+        switch (irq >> 5) {
+        case 0:
+                asic_write(asic_read(ien_int_0) & disable_mask, ien_int_0);
+                break;
+        case 1:
+                asic_write(asic_read(ien_int_1) & disable_mask, ien_int_1);
+                break;
+        case 2:
+                asic_write(asic_read(ien_int_2) & disable_mask, ien_int_2);
+                break;
+        case 3:
+                asic_write(asic_read(ien_int_3) & disable_mask, ien_int_3);
+                break;
+        default:
+                BUG();
+        }
+}
+
+static struct irq_chip asic_irq_chip = {
+        .name = "ASIC Level",
+        .ack = mask_asic_irq,
+        .mask = mask_asic_irq,
+        .mask_ack = mask_asic_irq,
+        .unmask = unmask_asic_irq,
+        .eoi = unmask_asic_irq,
+};
+
+void __init asic_irq_init(void)
+{
+        int i;
+
+        /* set priority to 0 */
+        write_c0_status(read_c0_status() & ~(0x0000fc00));
+
+        asic_write(0, ien_int_0);
+        asic_write(0, ien_int_1);
+        asic_write(0, ien_int_2);
+        asic_write(0, ien_int_3);
+
+        asic_write(0x0fffffff, int_level_3_3);
+        asic_write(0xffffffff, int_level_3_2);
+        asic_write(0xffffffff, int_level_3_1);
+        asic_write(0xffffffff, int_level_3_0);
+        asic_write(0xffffffff, int_level_2_3);
+        asic_write(0xffffffff, int_level_2_2);
+        asic_write(0xffffffff, int_level_2_1);
+        asic_write(0xffffffff, int_level_2_0);
+        asic_write(0xffffffff, int_level_1_3);
+        asic_write(0xffffffff, int_level_1_2);
+        asic_write(0xffffffff, int_level_1_1);
+        asic_write(0xffffffff, int_level_1_0);
+        asic_write(0xffffffff, int_level_0_3);
+        asic_write(0xffffffff, int_level_0_2);
+        asic_write(0xffffffff, int_level_0_1);
+        asic_write(0xffffffff, int_level_0_0);
+
+        asic_write(0xf, int_int_scan);
+
+        /*
+         * Initialize interrupt handlers.
+         */
+        for (i = 0; i < NR_IRQS; i++)
+                set_irq_chip_and_handler(i, &asic_irq_chip, handle_level_irq);
+}
diff --git a/arch/mips/powertv/asic/prealloc-calliope.c b/arch/mips/powertv/asic/prealloc-calliope.c
new file mode 100644
index 000000000000..cd5b76a1c951
--- /dev/null
+++ b/arch/mips/powertv/asic/prealloc-calliope.c
@@ -0,0 +1,620 @@
+/*
+ * Memory pre-allocations for Calliope boxes.
+ *
+ * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * Author:       Ken Eppinett
+ *               David Schleef <ds@schleef.org>
+ */
+
+#include <linux/init.h>
+#include <asm/mach-powertv/asic.h>
+
+/*
+ * NON_DVR_CAPABLE CALLIOPE RESOURCES
+ */
+struct resource non_dvr_calliope_resources[] __initdata =
+{
+        /*
+         * VIDEO / LX1
+         */
+        {
+                .name   = "ST231aImage",        /* Delta-Mu 1 image and ram */
+                .start  = 0x24000000,
+                .end    = 0x24200000 - 1,       /*2MiB */
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ST231aMonitor",   /*8KiB block ST231a monitor */
+                .start  = 0x24200000,
+                .end    = 0x24202000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "MediaMemory1",
+                .start  = 0x24202000,
+                .end    = 0x26700000 - 1, /*~36.9MiB (32MiB - (2MiB + 8KiB)) */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Sysaudio Driver
+         */
+        {
+                .name   = "DSP_Image_Buff",
+                .start  = 0x00000000,
+                .end    = 0x000FFFFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_CPU_PCM_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00009FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_AUX_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_Main_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * STAVEM driver/STAPI
+         */
+        {
+                .name   = "AVMEMPartition0",
+                .start  = 0x00000000,
+                .end    = 0x00600000 - 1,       /* 6 MB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * DOCSIS Subsystem
+         */
+        {
+                .name   = "Docsis",
+                .start  = 0x22000000,
+                .end    = 0x22700000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * GHW HAL Driver
+         */
+        {
+                .name   = "GraphicsHeap",
+                .start  = 0x22700000,
+                .end    = 0x23500000 - 1,       /* 14 MB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * multi com buffer area
+         */
+        {
+                .name   = "MulticomSHM",
+                .start  = 0x23700000,
+                .end    = 0x23720000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * DMA Ring buffer (don't need recording buffers)
+         */
+        {
+                .name   = "BMM_Buffer",
+                .start  = 0x00000000,
+                .end    = 0x000AA000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Display bins buffer for unit0
+         */
+        {
+                .name   = "DisplayBins0",
+                .start  = 0x00000000,
+                .end    = 0x00000FFF,           /* 4 KB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * AVFS: player HAL memory
+         *
+         *
+         */
+        {
+                .name   = "AvfsDmaMem",
+                .start  = 0x00000000,
+                .end    = 0x002c4c00 - 1,       /* 945K * 3 for playback */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * PMEM
+         */
+        {
+                .name   = "DiagPersistentMemory",
+                .start  = 0x00000000,
+                .end    = 0x10000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Smartcard
+         */
+        {
+                .name   = "SmartCardInfo",
+                .start  = 0x00000000,
+                .end    = 0x2800 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * NAND Flash
+         */
+        {
+                .name   = "NandFlash",
+                .start  = NAND_FLASH_BASE,
+                .end    = NAND_FLASH_BASE + 0x400 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         * Synopsys GMAC Memory Region
+         */
+        {
+                .name   = "GMAC",
+                .start  = 0x00000000,
+                .end    = 0x00010000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Add other resources here
+         *
+         */
+        { },
+};
+
+struct resource non_dvr_vz_calliope_resources[] __initdata =
+{
+        /*
+         * VIDEO / LX1
+         */
+        {
+                .name   = "ST231aImage",        /* Delta-Mu 1 image and ram */
+                .start  = 0x24000000,
+                .end    = 0x24200000 - 1, /*2 Meg */
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ST231aMonitor",      /* 8k block ST231a monitor */
+                .start  = 0x24200000,
+                .end    = 0x24202000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "MediaMemory1",
+                .start  = 0x22202000,
+                .end    = 0x22C20B85 - 1,       /* 10.12 Meg */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Sysaudio Driver
+         */
+        {
+                .name   = "DSP_Image_Buff",
+                .start  = 0x00000000,
+                .end    = 0x000FFFFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_CPU_PCM_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00009FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_AUX_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_Main_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * STAVEM driver/STAPI
+         */
+        {
+                .name   = "AVMEMPartition0",
+                .start  = 0x20300000,
+                .end    = 0x20620000-1,  /*3.125 MB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * GHW HAL Driver
+         */
+        {
+                .name   = "GraphicsHeap",
+                .start  = 0x20100000,
+                .end    = 0x20300000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * multi com buffer area
+         */
+        {
+                .name   = "MulticomSHM",
+                .start  = 0x23900000,
+                .end    = 0x23920000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * DMA Ring buffer
+         */
+        {
+                .name   = "BMM_Buffer",
+                .start  = 0x00000000,
+                .end    = 0x000AA000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Display bins buffer for unit0
+         */
+        {
+                .name   = "DisplayBins0",
+                .start  = 0x00000000,
+                .end    = 0x00000FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * PMEM
+         */
+        {
+                .name   = "DiagPersistentMemory",
+                .start  = 0x00000000,
+                .end    = 0x10000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Smartcard
+         */
+        {
+                .name   = "SmartCardInfo",
+                .start  = 0x00000000,
+                .end    = 0x2800 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * NAND Flash
+         */
+        {
+                .name   = "NandFlash",
+                .start  = NAND_FLASH_BASE,
+                .end    = NAND_FLASH_BASE+0x400 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         * Synopsys GMAC Memory Region
+         */
+        {
+                .name   = "GMAC",
+                .start  = 0x00000000,
+                .end    = 0x00010000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Add other resources here
+         */
+        { },
+};
+
+struct resource non_dvr_vze_calliope_resources[] __initdata =
+{
+        /*
+         * VIDEO / LX1
+         */
+        {
+                .name   = "ST231aImage",        /* Delta-Mu 1 image and ram */
+                .start  = 0x22000000,
+                .end    = 0x22200000 - 1,       /*2  Meg */
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ST231aMonitor",      /* 8k block ST231a monitor */
+                .start  = 0x22200000,
+                .end    = 0x22202000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "MediaMemory1",
+                .start  = 0x22202000,
+                .end    = 0x22C20B85 - 1,       /* 10.12 Meg */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Sysaudio Driver
+         */
+        {
+                .name   = "DSP_Image_Buff",
+                .start  = 0x00000000,
+                .end    = 0x000FFFFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_CPU_PCM_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00009FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_AUX_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_Main_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * STAVEM driver/STAPI
+         */
+        {
+                .name   = "AVMEMPartition0",
+                .start  = 0x20396000,
+                .end    = 0x206B6000 - 1,               /* 3.125 MB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * GHW HAL Driver
+         */
+        {
+                .name   = "GraphicsHeap",
+                .start  = 0x20100000,
+                .end    = 0x20396000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * multi com buffer area
+         */
+        {
+                .name   = "MulticomSHM",
+                .start  = 0x206B6000,
+                .end    = 0x206D6000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * DMA Ring buffer
+         */
+        {
+                .name   = "BMM_Buffer",
+                .start  = 0x00000000,
+                .end    = 0x000AA000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Display bins buffer for unit0
+         */
+        {
+                .name   = "DisplayBins0",
+                .start  = 0x00000000,
+                .end    = 0x00000FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * PMEM
+         */
+        {
+                .name   = "DiagPersistentMemory",
+                .start  = 0x00000000,
+                .end    = 0x10000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Smartcard
+         */
+        {
+                .name   = "SmartCardInfo",
+                .start  = 0x00000000,
+                .end    = 0x2800 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * NAND Flash
+         */
+        {
+                .name   = "NandFlash",
+                .start  = NAND_FLASH_BASE,
+                .end    = NAND_FLASH_BASE+0x400 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Synopsys GMAC Memory Region
+         */
+        {
+                .name   = "GMAC",
+                .start  = 0x00000000,
+                .end    = 0x00010000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Add other resources here
+         */
+        { },
+};
+
+struct resource non_dvr_vzf_calliope_resources[] __initdata =
+{
+        /*
+         * VIDEO / LX1
+         */
+        {
+                .name   = "ST231aImage",        /*Delta-Mu 1 image and ram */
+                .start  = 0x24000000,
+                .end    = 0x24200000 - 1,       /*2MiB */
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ST231aMonitor",      /*8KiB block ST231a monitor */
+                .start  = 0x24200000,
+                .end    = 0x24202000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "MediaMemory1",
+                .start  = 0x24202000,
+                /* ~19.4 (21.5MiB - (2MiB + 8KiB)) */
+                .end    = 0x25580000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Sysaudio Driver
+         */
+        {
+                .name   = "DSP_Image_Buff",
+                .start  = 0x00000000,
+                .end    = 0x000FFFFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_CPU_PCM_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00009FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_AUX_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_Main_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * STAVEM driver/STAPI
+         */
+        {
+                .name   = "AVMEMPartition0",
+                .start  = 0x00000000,
+                .end    = 0x00480000 - 1,  /* 4.5 MB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * GHW HAL Driver
+         */
+        {
+                .name   = "GraphicsHeap",
+                .start  = 0x22700000,
+                .end    = 0x23500000 - 1, /* 14 MB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * multi com buffer area
+         */
+        {
+                .name   = "MulticomSHM",
+                .start  = 0x23700000,
+                .end    = 0x23720000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * DMA Ring buffer (don't need recording buffers)
+         */
+        {
+                .name   = "BMM_Buffer",
+                .start  = 0x00000000,
+                .end    = 0x000AA000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Display bins buffer for unit0
+         */
+        {
+                .name   = "DisplayBins0",
+                .start  = 0x00000000,
+                .end    = 0x00000FFF,  /* 4 KB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Display bins buffer for unit1
+         */
+        {
+                .name   = "DisplayBins1",
+                .start  = 0x00000000,
+                .end    = 0x00000FFF,  /* 4 KB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * AVFS: player HAL memory
+         *
+         *
+         */
+        {
+                .name   = "AvfsDmaMem",
+                .start  = 0x00000000,
+                .end    = 0x002c4c00 - 1,  /* 945K * 3 for playback */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * PMEM
+         */
+        {
+                .name   = "DiagPersistentMemory",
+                .start  = 0x00000000,
+                .end    = 0x10000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Smartcard
+         */
+        {
+                .name   = "SmartCardInfo",
+                .start  = 0x00000000,
+                .end    = 0x2800 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * NAND Flash
+         */
+        {
+                .name   = "NandFlash",
+                .start  = NAND_FLASH_BASE,
+                .end    = NAND_FLASH_BASE + 0x400 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Synopsys GMAC Memory Region
+         */
+        {
+                .name   = "GMAC",
+                .start  = 0x00000000,
+                .end    = 0x00010000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Add other resources here
+         */
+        { },
+};
diff --git a/arch/mips/powertv/asic/prealloc-cronus.c b/arch/mips/powertv/asic/prealloc-cronus.c
new file mode 100644
index 000000000000..45a5c3ea718c
--- /dev/null
+++ b/arch/mips/powertv/asic/prealloc-cronus.c
@@ -0,0 +1,608 @@
+/*
+ * Memory pre-allocations for Cronus boxes.
+ *
+ * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * Author:       Ken Eppinett
+ *               David Schleef <ds@schleef.org>
+ */
+
+#include <linux/init.h>
+#include <asm/mach-powertv/asic.h>
+
+/*
+ * DVR_CAPABLE CRONUS RESOURCES
+ */
+struct resource dvr_cronus_resources[] __initdata =
+{
+        /*
+         *
+         * VIDEO1 / LX1
+         *
+         */
+        {
+                .name   = "ST231aImage",        /* Delta-Mu 1 image and ram */
+                .start  = 0x24000000,
+                .end    = 0x241FFFFF,           /* 2MiB */
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ST231aMonitor",      /* 8KiB block ST231a monitor */
+                .start  = 0x24200000,
+                .end    = 0x24201FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "MediaMemory1",
+                .start  = 0x24202000,
+                .end    = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * VIDEO2 / LX2
+         *
+         */
+        {
+                .name   = "ST231bImage",        /* Delta-Mu 2 image and ram */
+                .start  = 0x60000000,
+                .end    = 0x601FFFFF,           /* 2MiB */
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "ST231bMonitor",      /* 8KiB block ST231b monitor */
+                .start  = 0x60200000,
+                .end    = 0x60201FFF,
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "MediaMemory2",
+                .start  = 0x60202000,
+                .end    = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * Sysaudio Driver
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  DSP_Image_Buff - DSP code and data images (1MB)
+         *  ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB)
+         *  ADSC_AUX_Buff - ADSC AUX buffer (16KB)
+         *  ADSC_Main_Buff - ADSC Main buffer (16KB)
+         *
+         */
+        {
+                .name   = "DSP_Image_Buff",
+                .start  = 0x00000000,
+                .end    = 0x000FFFFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_CPU_PCM_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00009FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_AUX_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_Main_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * STAVEM driver/STAPI
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  This memory area is used for allocating buffers for Video decoding
+         *  purposes.  Allocation/De-allocation within this buffer is managed
+         *  by the STAVMEM driver of the STAPI.  They could be Decimated
+         *  Picture Buffers, Intermediate Buffers, as deemed necessary for
+         *  video decoding purposes, for any video decoders on Zeus.
+         *
+         */
+        {
+                .name   = "AVMEMPartition0",
+                .start  = 0x63580000,
+                .end    = 0x64180000 - 1,  /* 12 MB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * DOCSIS Subsystem
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "Docsis",
+                .start  = 0x62000000,
+                .end    = 0x62700000 - 1,       /* 7 MB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * GHW HAL Driver
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  GraphicsHeap - PowerTV Graphics Heap
+         *
+         */
+        {
+                .name   = "GraphicsHeap",
+                .start  = 0x62700000,
+                .end    = 0x63500000 - 1,       /* 14 MB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * multi com buffer area
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "MulticomSHM",
+                .start  = 0x26000000,
+                .end    = 0x26020000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * DMA Ring buffer
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "BMM_Buffer",
+                .start  = 0x00000000,
+                .end    = 0x00280000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Display bins buffer for unit0
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Display Bins for unit0
+         *
+         */
+        {
+                .name   = "DisplayBins0",
+                .start  = 0x00000000,
+                .end    = 0x00000FFF,           /* 4 KB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Display bins buffer
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Display Bins for unit1
+         *
+         */
+        {
+                .name   = "DisplayBins1",
+                .start  = 0x64AD4000,
+                .end    = 0x64AD5000 - 1,  /* 4 KB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * ITFS
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "ITFS",
+                .start  = 0x64180000,
+                /* 815,104 bytes each for 2 ITFS partitions. */
+                .end    = 0x6430DFFF,
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * AVFS
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "AvfsDmaMem",
+                .start  = 0x6430E000,
+                /* (945K * 8) = (128K *3) 5 playbacks / 3 server */
+                .end    = 0x64AD0000 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "AvfsFileSys",
+                .start  = 0x64AD0000,
+                .end    = 0x64AD1000 - 1,  /* 4K */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * PMEM
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Persistent memory for diagnostics.
+         *
+         */
+        {
+                .name   = "DiagPersistentMemory",
+                .start  = 0x00000000,
+                .end    = 0x10000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Smartcard
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Read and write buffers for Internal/External cards
+         *
+         */
+        {
+                .name   = "SmartCardInfo",
+                .start  = 0x64AD1000,
+                .end    = 0x64AD3800 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * KAVNET
+         *    NP Reset Vector - must be of the form xxCxxxxx
+         *         NP Image - must be video bank 1
+         *         NP IPC - must be video bank 2
+         */
+        {
+                .name   = "NP_Reset_Vector",
+                .start  = 0x27c00000,
+                .end    = 0x27c01000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "NP_Image",
+                .start  = 0x27020000,
+                .end    = 0x27060000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "NP_IPC",
+                .start  = 0x63500000,
+                .end    = 0x63580000 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         * Add other resources here
+         */
+        { },
+};
+
+/*
+ * NON_DVR_CAPABLE CRONUS RESOURCES
+ */
+struct resource non_dvr_cronus_resources[] __initdata =
+{
+        /*
+         *
+         * VIDEO1 / LX1
+         *
+         */
+        {
+                .name   = "ST231aImage",        /* Delta-Mu 1 image and ram */
+                .start  = 0x24000000,
+                .end    = 0x241FFFFF,           /* 2MiB */
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ST231aMonitor",      /* 8KiB block ST231a monitor */
+                .start  = 0x24200000,
+                .end    = 0x24201FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "MediaMemory1",
+                .start  = 0x24202000,
+                .end    = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * VIDEO2 / LX2
+         *
+         */
+        {
+                .name   = "ST231bImage",        /* Delta-Mu 2 image and ram */
+                .start  = 0x60000000,
+                .end    = 0x601FFFFF,           /* 2MiB */
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "ST231bMonitor",      /* 8KiB block ST231b monitor */
+                .start  = 0x60200000,
+                .end    = 0x60201FFF,
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "MediaMemory2",
+                .start  = 0x60202000,
+                .end    = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * Sysaudio Driver
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  DSP_Image_Buff - DSP code and data images (1MB)
+         *  ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB)
+         *  ADSC_AUX_Buff - ADSC AUX buffer (16KB)
+         *  ADSC_Main_Buff - ADSC Main buffer (16KB)
+         *
+         */
+        {
+                .name   = "DSP_Image_Buff",
+                .start  = 0x00000000,
+                .end    = 0x000FFFFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_CPU_PCM_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00009FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_AUX_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_Main_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * STAVEM driver/STAPI
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  This memory area is used for allocating buffers for Video decoding
+         *  purposes.  Allocation/De-allocation within this buffer is managed
+         *  by the STAVMEM driver of the STAPI.  They could be Decimated
+         *  Picture Buffers, Intermediate Buffers, as deemed necessary for
+         *  video decoding purposes, for any video decoders on Zeus.
+         *
+         */
+        {
+                .name   = "AVMEMPartition0",
+                .start  = 0x63580000,
+                .end    = 0x64180000 - 1,  /* 12 MB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * DOCSIS Subsystem
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "Docsis",
+                .start  = 0x62000000,
+                .end    = 0x62700000 - 1,       /* 7 MB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * GHW HAL Driver
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  GraphicsHeap - PowerTV Graphics Heap
+         *
+         */
+        {
+                .name   = "GraphicsHeap",
+                .start  = 0x62700000,
+                .end    = 0x63500000 - 1,       /* 14 MB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * multi com buffer area
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "MulticomSHM",
+                .start  = 0x26000000,
+                .end    = 0x26020000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * DMA Ring buffer
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "BMM_Buffer",
+                .start  = 0x00000000,
+                .end    = 0x000AA000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Display bins buffer for unit0
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Display Bins for unit0
+         *
+         */
+        {
+                .name   = "DisplayBins0",
+                .start  = 0x00000000,
+                .end    = 0x00000FFF,           /* 4 KB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Display bins buffer
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Display Bins for unit1
+         *
+         */
+        {
+                .name   = "DisplayBins1",
+                .start  = 0x64AD4000,
+                .end    = 0x64AD5000 - 1,  /* 4 KB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * AVFS: player HAL memory
+         *
+         *
+         */
+        {
+                .name   = "AvfsDmaMem",
+                .start  = 0x6430E000,
+                .end    = 0x645D2C00 - 1,  /* 945K * 3 for playback */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * PMEM
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Persistent memory for diagnostics.
+         *
+         */
+        {
+                .name   = "DiagPersistentMemory",
+                .start  = 0x00000000,
+                .end    = 0x10000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Smartcard
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Read and write buffers for Internal/External cards
+         *
+         */
+        {
+                .name   = "SmartCardInfo",
+                .start  = 0x64AD1000,
+                .end    = 0x64AD3800 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * KAVNET
+         *    NP Reset Vector - must be of the form xxCxxxxx
+         *         NP Image - must be video bank 1
+         *         NP IPC - must be video bank 2
+         */
+        {
+                .name   = "NP_Reset_Vector",
+                .start  = 0x27c00000,
+                .end    = 0x27c01000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "NP_Image",
+                .start  = 0x27020000,
+                .end    = 0x27060000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "NP_IPC",
+                .start  = 0x63500000,
+                .end    = 0x63580000 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        { },
+};
diff --git a/arch/mips/powertv/asic/prealloc-cronuslite.c b/arch/mips/powertv/asic/prealloc-cronuslite.c
new file mode 100644
index 000000000000..23a905613c04
--- /dev/null
+++ b/arch/mips/powertv/asic/prealloc-cronuslite.c
@@ -0,0 +1,290 @@
+/*
+ * Memory pre-allocations for Cronus Lite boxes.
+ *
+ * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * Author:       Ken Eppinett
+ *               David Schleef <ds@schleef.org>
+ */
+
+#include <linux/init.h>
+#include <asm/mach-powertv/asic.h>
+
+/*
+ * NON_DVR_CAPABLE CRONUSLITE RESOURCES
+ */
+struct resource non_dvr_cronuslite_resources[] __initdata =
+{
+        /*
+         *
+         * VIDEO2 / LX2
+         *
+         */
+        {
+                .name   = "ST231aImage",        /* Delta-Mu 2 image and ram */
+                .start  = 0x60000000,
+                .end    = 0x601FFFFF,           /* 2MiB */
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "ST231aMonitor",      /* 8KiB block ST231b monitor */
+                .start  = 0x60200000,
+                .end    = 0x60201FFF,
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "MediaMemory1",
+                .start  = 0x60202000,
+                .end    = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * Sysaudio Driver
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  DSP_Image_Buff - DSP code and data images (1MB)
+         *  ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB)
+         *  ADSC_AUX_Buff - ADSC AUX buffer (16KB)
+         *  ADSC_Main_Buff - ADSC Main buffer (16KB)
+         *
+         */
+        {
+                .name   = "DSP_Image_Buff",
+                .start  = 0x00000000,
+                .end    = 0x000FFFFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_CPU_PCM_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00009FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_AUX_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_Main_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * STAVEM driver/STAPI
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  This memory area is used for allocating buffers for Video decoding
+         *  purposes.  Allocation/De-allocation within this buffer is managed
+         *  by the STAVMEM driver of the STAPI.  They could be Decimated
+         *  Picture Buffers, Intermediate Buffers, as deemed necessary for
+         *  video decoding purposes, for any video decoders on Zeus.
+         *
+         */
+        {
+                .name   = "AVMEMPartition0",
+                .start  = 0x63580000,
+                .end    = 0x63B80000 - 1,  /* 6 MB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * DOCSIS Subsystem
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "Docsis",
+                .start  = 0x62000000,
+                .end    = 0x62700000 - 1,       /* 7 MB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * GHW HAL Driver
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  GraphicsHeap - PowerTV Graphics Heap
+         *
+         */
+        {
+                .name   = "GraphicsHeap",
+                .start  = 0x62700000,
+                .end    = 0x63500000 - 1,       /* 14 MB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * multi com buffer area
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "MulticomSHM",
+                .start  = 0x26000000,
+                .end    = 0x26020000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * DMA Ring buffer
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "BMM_Buffer",
+                .start  = 0x00000000,
+                .end    = 0x000AA000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Display bins buffer for unit0
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Display Bins for unit0
+         *
+         */
+        {
+                .name   = "DisplayBins0",
+                .start  = 0x00000000,
+                .end    = 0x00000FFF,           /* 4 KB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Display bins buffer
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Display Bins for unit1
+         *
+         */
+        {
+                .name   = "DisplayBins1",
+                .start  = 0x63B83000,
+                .end    = 0x63B84000 - 1,  /* 4 KB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * AVFS: player HAL memory
+         *
+         *
+         */
+        {
+                .name   = "AvfsDmaMem",
+                .start  = 0x63B84000,
+                .end    = 0x63E48C00 - 1,  /* 945K * 3 for playback */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * PMEM
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Persistent memory for diagnostics.
+         *
+         */
+        {
+                .name   = "DiagPersistentMemory",
+                .start  = 0x00000000,
+                .end    = 0x10000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Smartcard
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Read and write buffers for Internal/External cards
+         *
+         */
+        {
+                .name   = "SmartCardInfo",
+                .start  = 0x63B80000,
+                .end    = 0x63B82800 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * KAVNET
+         *    NP Reset Vector - must be of the form xxCxxxxx
+         *         NP Image - must be video bank 1
+         *         NP IPC - must be video bank 2
+         */
+        {
+                .name   = "NP_Reset_Vector",
+                .start  = 0x27c00000,
+                .end    = 0x27c01000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "NP_Image",
+                .start  = 0x27020000,
+                .end    = 0x27060000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "NP_IPC",
+                .start  = 0x63500000,
+                .end    = 0x63580000 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         * NAND Flash
+         */
+        {
+                .name   = "NandFlash",
+                .start  = NAND_FLASH_BASE,
+                .end    = NAND_FLASH_BASE + 0x400 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         * Add other resources here
+         */
+        { },
+};
diff --git a/arch/mips/powertv/asic/prealloc-zeus.c b/arch/mips/powertv/asic/prealloc-zeus.c
new file mode 100644
index 000000000000..018d4514dbe3
--- /dev/null
+++ b/arch/mips/powertv/asic/prealloc-zeus.c
@@ -0,0 +1,459 @@
+/*
+ * Memory pre-allocations for Zeus boxes.
+ *
+ * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * Author:       Ken Eppinett
+ *               David Schleef <ds@schleef.org>
+ */
+
+#include <linux/init.h>
+#include <asm/mach-powertv/asic.h>
+
+/*
+ * DVR_CAPABLE RESOURCES
+ */
+struct resource dvr_zeus_resources[] __initdata =
+{
+        /*
+         *
+         * VIDEO1 / LX1
+         *
+         */
+        {
+                .name   = "ST231aImage",        /* Delta-Mu 1 image and ram */
+                .start  = 0x20000000,
+                .end    = 0x201FFFFF,           /* 2MiB */
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "ST231aMonitor",      /* 8KiB block ST231a monitor */
+                .start  = 0x20200000,
+                .end    = 0x20201FFF,
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "MediaMemory1",
+                .start  = 0x20202000,
+                .end    = 0x21FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * VIDEO2 / LX2
+         *
+         */
+        {
+                .name   = "ST231bImage",        /* Delta-Mu 2 image and ram */
+                .start  = 0x30000000,
+                .end    = 0x301FFFFF,           /* 2MiB */
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "ST231bMonitor",      /* 8KiB block ST231b monitor */
+                .start  = 0x30200000,
+                .end    = 0x30201FFF,
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "MediaMemory2",
+                .start  = 0x30202000,
+                .end    = 0x31FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * Sysaudio Driver
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  DSP_Image_Buff - DSP code and data images (1MB)
+         *  ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB)
+         *  ADSC_AUX_Buff - ADSC AUX buffer (16KB)
+         *  ADSC_Main_Buff - ADSC Main buffer (16KB)
+         *
+         */
+        {
+                .name   = "DSP_Image_Buff",
+                .start  = 0x00000000,
+                .end    = 0x000FFFFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_CPU_PCM_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00009FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_AUX_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_Main_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * STAVEM driver/STAPI
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  This memory area is used for allocating buffers for Video decoding
+         *  purposes.  Allocation/De-allocation within this buffer is managed
+         *  by the STAVMEM driver of the STAPI.  They could be Decimated
+         *  Picture Buffers, Intermediate Buffers, as deemed necessary for
+         *  video decoding purposes, for any video decoders on Zeus.
+         *
+         */
+        {
+                .name   = "AVMEMPartition0",
+                .start  = 0x00000000,
+                .end    = 0x00c00000 - 1,       /* 12 MB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * DOCSIS Subsystem
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "Docsis",
+                .start  = 0x40100000,
+                .end    = 0x407fffff,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * GHW HAL Driver
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  GraphicsHeap - PowerTV Graphics Heap
+         *
+         */
+        {
+                .name   = "GraphicsHeap",
+                .start  = 0x46900000,
+                .end    = 0x47700000 - 1,       /* 14 MB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * multi com buffer area
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "MulticomSHM",
+                .start  = 0x47900000,
+                .end    = 0x47920000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * DMA Ring buffer
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "BMM_Buffer",
+                .start  = 0x00000000,
+                .end    = 0x00280000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Display bins buffer for unit0
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Display Bins for unit0
+         *
+         */
+        {
+                .name   = "DisplayBins0",
+                .start  = 0x00000000,
+                .end    = 0x00000FFF,   /* 4 KB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Display bins buffer
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Display Bins for unit1
+         *
+         */
+        {
+                .name   = "DisplayBins1",
+                .start  = 0x00000000,
+                .end    = 0x00000FFF,   /* 4 KB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * ITFS
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "ITFS",
+                .start  = 0x00000000,
+                /* 815,104 bytes each for 2 ITFS partitions. */
+                .end    = 0x0018DFFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * AVFS
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "AvfsDmaMem",
+                .start  = 0x00000000,
+                /* (945K * 8) = (128K * 3) 5 playbacks / 3 server */
+                .end    = 0x007c2000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "AvfsFileSys",
+                .start  = 0x00000000,
+                .end    = 0x00001000 - 1,  /* 4K */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * PMEM
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Persistent memory for diagnostics.
+         *
+         */
+        {
+                .name   = "DiagPersistentMemory",
+                .start  = 0x00000000,
+                .end    = 0x10000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Smartcard
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Read and write buffers for Internal/External cards
+         *
+         */
+        {
+                .name   = "SmartCardInfo",
+                .start  = 0x00000000,
+                .end    = 0x2800 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Add other resources here
+         */
+        { },
+};
+
+/*
+ * NON_DVR_CAPABLE ZEUS RESOURCES
+ */
+struct resource non_dvr_zeus_resources[] __initdata =
+{
+        /*
+         * VIDEO1 / LX1
+         */
+        {
+                .name   = "ST231aImage",        /* Delta-Mu 1 image and ram */
+                .start  = 0x20000000,
+                .end    = 0x201FFFFF,           /* 2MiB */
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "ST231aMonitor",      /* 8KiB block ST231a monitor */
+                .start  = 0x20200000,
+                .end    = 0x20201FFF,
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "MediaMemory1",
+                .start  = 0x20202000,
+                .end    = 0x21FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         * Sysaudio Driver
+         */
+        {
+                .name   = "DSP_Image_Buff",
+                .start  = 0x00000000,
+                .end    = 0x000FFFFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_CPU_PCM_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00009FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_AUX_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_Main_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * STAVEM driver/STAPI
+         */
+        {
+                .name   = "AVMEMPartition0",
+                .start  = 0x00000000,
+                .end    = 0x00600000 - 1,       /* 6 MB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * DOCSIS Subsystem
+         */
+        {
+                .name   = "Docsis",
+                .start  = 0x40100000,
+                .end    = 0x407fffff,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * GHW HAL Driver
+         */
+        {
+                .name   = "GraphicsHeap",
+                .start  = 0x46900000,
+                .end    = 0x47700000 - 1,       /* 14 MB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * multi com buffer area
+         */
+        {
+                .name   = "MulticomSHM",
+                .start  = 0x47900000,
+                .end    = 0x47920000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * DMA Ring buffer
+         */
+        {
+                .name   = "BMM_Buffer",
+                .start  = 0x00000000,
+                .end    = 0x00280000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Display bins buffer for unit0
+         */
+        {
+                .name   = "DisplayBins0",
+                .start  = 0x00000000,
+                .end    = 0x00000FFF,           /* 4 KB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * AVFS: player HAL memory
+         *
+         *
+         */
+        {
+                .name   = "AvfsDmaMem",
+                .start  = 0x00000000,
+                .end    = 0x002c4c00 - 1,       /* 945K * 3 for playback */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * PMEM
+         */
+        {
+                .name   = "DiagPersistentMemory",
+                .start  = 0x00000000,
+                .end    = 0x10000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * Smartcard
+         */
+        {
+                .name   = "SmartCardInfo",
+                .start  = 0x00000000,
+                .end    = 0x2800 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * NAND Flash
+         */
+        {
+                .name   = "NandFlash",
+                .start  = NAND_FLASH_BASE,
+                .end    = NAND_FLASH_BASE + 0x400 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         * Add other resources here
+         */
+        { },
+};
diff --git a/arch/mips/powertv/cmdline.c b/arch/mips/powertv/cmdline.c
new file mode 100644
index 000000000000..98d73cb0d452
--- /dev/null
+++ b/arch/mips/powertv/cmdline.c
@@ -0,0 +1,52 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
+ * Portions copyright (C) 2009 Cisco Systems, Inc.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * Kernel command line creation using the prom monitor (YAMON) argc/argv.
+ */
+#include <linux/init.h>
+#include <linux/string.h>
+
+#include <asm/bootinfo.h>
+
+#include "init.h"
+
+/*
+ * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
+ * This macro take care of sign extension.
+ */
+#define prom_argv(index) ((char *)(long)_prom_argv[(index)])
+
+char * __init prom_getcmdline(void)
+{
+        return &(arcs_cmdline[0]);
+}
+
+void  __init prom_init_cmdline(void)
+{
+        int len;
+
+        if (prom_argc != 1)
+                return;
+
+        len = strlen(arcs_cmdline);
+
+        arcs_cmdline[len] = ' ';
+
+        strlcpy(arcs_cmdline + len + 1, (char *)_prom_argv,
+                COMMAND_LINE_SIZE - len - 1);
+}
diff --git a/arch/mips/powertv/init.c b/arch/mips/powertv/init.c
new file mode 100644
index 000000000000..5f4e4c304e48
--- /dev/null
+++ b/arch/mips/powertv/init.c
@@ -0,0 +1,128 @@
+/*
+ * Copyright (C) 1999, 2000, 2004, 2005  MIPS Technologies, Inc.
+ *      All rights reserved.
+ *      Authors: Carsten Langgaard <carstenl@mips.com>
+ *               Maciej W. Rozycki <macro@mips.com>
+ * Portions copyright (C) 2009 Cisco Systems, Inc.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * PROM library initialisation code.
+ */
+#include <linux/init.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+
+#include <asm/bootinfo.h>
+#include <linux/io.h>
+#include <asm/system.h>
+#include <asm/cacheflush.h>
+#include <asm/traps.h>
+
+#include <asm/mips-boards/prom.h>
+#include <asm/mips-boards/generic.h>
+#include <asm/mach-powertv/asic.h>
+
+#include "init.h"
+
+int prom_argc;
+int *_prom_argv, *_prom_envp;
+unsigned long _prom_memsize;
+
+/*
+ * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
+ * This macro take care of sign extension, if running in 64-bit mode.
+ */
+#define prom_envp(index) ((char *)(long)_prom_envp[(index)])
+
+char *prom_getenv(char *envname)
+{
+        char *result = NULL;
+
+        if (_prom_envp != NULL) {
+                /*
+                 * Return a pointer to the given environment variable.
+                 * In 64-bit mode: we're using 64-bit pointers, but all pointers
+                 * in the PROM structures are only 32-bit, so we need some
+                 * workarounds, if we are running in 64-bit mode.
+                 */
+                int i, index = 0;
+
+                i = strlen(envname);
+
+                while (prom_envp(index)) {
+                        if (strncmp(envname, prom_envp(index), i) == 0) {
+                                result = prom_envp(index + 1);
+                                break;
+                        }
+                        index += 2;
+                }
+        }
+
+        return result;
+}
+
+/* TODO: Verify on linux-mips mailing list that the following two  */
+/* functions are correct                                           */
+/* TODO: Copy NMI and EJTAG exception vectors to memory from the   */
+/* BootROM exception vectors. Flush their cache entries. test it.  */
+
+static void __init mips_nmi_setup(void)
+{
+        void *base;
+#if defined(CONFIG_CPU_MIPS32_R1)
+        base = cpu_has_veic ?
+                (void *)(CAC_BASE + 0xa80) :
+                (void *)(CAC_BASE + 0x380);
+#elif defined(CONFIG_CPU_MIPS32_R2)
+        base = (void *)0xbfc00000;
+#else
+#error NMI exception handler address not defined
+#endif
+}
+
+static void __init mips_ejtag_setup(void)
+{
+        void *base;
+
+#if defined(CONFIG_CPU_MIPS32_R1)
+        base = cpu_has_veic ?
+                (void *)(CAC_BASE + 0xa00) :
+                (void *)(CAC_BASE + 0x300);
+#elif defined(CONFIG_CPU_MIPS32_R2)
+        base = (void *)0xbfc00480;
+#else
+#error EJTAG exception handler address not defined
+#endif
+}
+
+void __init prom_init(void)
+{
+        prom_argc = fw_arg0;
+        _prom_argv = (int *) fw_arg1;
+        _prom_envp = (int *) fw_arg2;
+        _prom_memsize = (unsigned long) fw_arg3;
+
+        board_nmi_handler_setup = mips_nmi_setup;
+        board_ejtag_handler_setup = mips_ejtag_setup;
+
+        pr_info("\nLINUX started...\n");
+        prom_init_cmdline();
+        configure_platform();
+        prom_meminit();
+
+#ifndef CONFIG_BOOTLOADER_DRIVER
+        pr_info("\nBootloader driver isn't loaded...\n");
+#endif
+}
diff --git a/arch/mips/powertv/init.h b/arch/mips/powertv/init.h
new file mode 100644
index 000000000000..7af6bf25008c
--- /dev/null
+++ b/arch/mips/powertv/init.h
@@ -0,0 +1,28 @@
+/*
+ * Definitions from powertv init.c file
+ *
+ * Copyright (C) 2009  Cisco Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ * Author: David VomLehn
+ */
+
+#ifndef _POWERTV_INIT_H
+#define _POWERTV_INIT_H
+extern int prom_argc;
+extern int *_prom_argv;
+extern unsigned long _prom_memsize;
+#endif
diff --git a/arch/mips/powertv/memory.c b/arch/mips/powertv/memory.c
new file mode 100644
index 000000000000..28d06605fff6
--- /dev/null
+++ b/arch/mips/powertv/memory.c
@@ -0,0 +1,186 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
+ * Portions copyright (C) 2009 Cisco Systems, Inc.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * Apparently originally from arch/mips/malta-memory.c. Modified to work
+ * with the PowerTV bootloader.
+ */
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/bootmem.h>
+#include <linux/pfn.h>
+#include <linux/string.h>
+
+#include <asm/bootinfo.h>
+#include <asm/page.h>
+#include <asm/sections.h>
+
+#include <asm/mips-boards/prom.h>
+
+#include "init.h"
+
+/* Memory constants */
+#define KIBIBYTE(n)             ((n) * 1024)    /* Number of kibibytes */
+#define MEBIBYTE(n)             ((n) * KIBIBYTE(1024)) /* Number of mebibytes */
+#define DEFAULT_MEMSIZE         MEBIBYTE(256)   /* If no memsize provided */
+#define LOW_MEM_MAX             MEBIBYTE(252)   /* Max usable low mem */
+#define RES_BOOTLDR_MEMSIZE     MEBIBYTE(1)     /* Memory reserved for bldr */
+#define BOOT_MEM_SIZE           KIBIBYTE(256)   /* Memory reserved for bldr */
+#define PHYS_MEM_START          0x10000000      /* Start of physical memory */
+
+unsigned long ptv_memsize;
+
+char __initdata cmdline[COMMAND_LINE_SIZE];
+
+void __init prom_meminit(void)
+{
+        char *memsize_str;
+        unsigned long memsize = 0;
+        unsigned int physend;
+        char *ptr;
+        int low_mem;
+        int high_mem;
+
+        /* Check the command line first for a memsize directive */
+        strcpy(cmdline, arcs_cmdline);
+        ptr = strstr(cmdline, "memsize=");
+        if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' '))
+                ptr = strstr(ptr, " memsize=");
+
+        if (ptr) {
+                memsize = memparse(ptr + 8, &ptr);
+        } else {
+                /* otherwise look in the environment */
+                memsize_str = prom_getenv("memsize");
+
+                if (memsize_str != NULL) {
+                        pr_info("prom memsize = %s\n", memsize_str);
+                        memsize = simple_strtol(memsize_str, NULL, 0);
+                }
+
+                if (memsize == 0) {
+                        if (_prom_memsize != 0) {
+                                memsize = _prom_memsize;
+                                pr_info("_prom_memsize = 0x%lx\n", memsize);
+                                /* add in memory that the bootloader doesn't
+                                 * report */
+                                memsize += BOOT_MEM_SIZE;
+                        } else {
+                                memsize = DEFAULT_MEMSIZE;
+                                pr_info("Memsize not passed by bootloader, "
+                                        "defaulting to 0x%lx\n", memsize);
+                        }
+                }
+        }
+
+        /* Store memsize for diagnostic purposes */
+        ptv_memsize = memsize;
+
+        physend = PFN_ALIGN(&_end) - 0x80000000;
+        if (memsize > LOW_MEM_MAX) {
+                low_mem = LOW_MEM_MAX;
+                high_mem = memsize - low_mem;
+        } else {
+                low_mem = memsize;
+                high_mem = 0;
+        }
+
+/*
+ * TODO: We will use the hard code for memory configuration until
+ * the bootloader releases their device tree to us.
+ */
+        /*
+         * Add the memory reserved for use by the bootloader to the
+         * memory map.
+         */
+        add_memory_region(PHYS_MEM_START, RES_BOOTLDR_MEMSIZE,
+                BOOT_MEM_RESERVED);
+#ifdef CONFIG_HIGHMEM_256_128
+        /*
+         * Add memory in low for general use by the kernel and its friends
+         * (like drivers, applications, etc).
+         */
+        add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE,
+                LOW_MEM_MAX - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM);
+        /*
+         * Add the memory reserved for reset vector.
+         */
+        add_memory_region(0x1fc00000, MEBIBYTE(4), BOOT_MEM_RESERVED);
+        /*
+         * Add the memory reserved.
+         */
+        add_memory_region(0x20000000, MEBIBYTE(1024 + 75), BOOT_MEM_RESERVED);
+        /*
+         * Add memory in high for general use by the kernel and its friends
+         * (like drivers, applications, etc).
+         *
+         * 75MB is reserved for devices which are using the memory in high.
+         */
+        add_memory_region(0x60000000 + MEBIBYTE(75), MEBIBYTE(128 - 75),
+                BOOT_MEM_RAM);
+#elif defined CONFIG_HIGHMEM_128_128
+        /*
+         * Add memory in low for general use by the kernel and its friends
+         * (like drivers, applications, etc).
+         */
+        add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE,
+                MEBIBYTE(128) - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM);
+        /*
+         * Add the memory reserved.
+         */
+        add_memory_region(PHYS_MEM_START + MEBIBYTE(128),
+                MEBIBYTE(128 + 1024 + 75), BOOT_MEM_RESERVED);
+        /*
+         * Add memory in high for general use by the kernel and its friends
+         * (like drivers, applications, etc).
+         *
+         * 75MB is reserved for devices which are using the memory in high.
+         */
+        add_memory_region(0x60000000 + MEBIBYTE(75), MEBIBYTE(128 - 75),
+                BOOT_MEM_RAM);
+#else
+        /* Add low memory regions for either:
+         *   - no-highmemory configuration case -OR-
+         *   - highmemory "HIGHMEM_LOWBANK_ONLY" case
+         */
+        /*
+         * Add memory for general use by the kernel and its friends
+         * (like drivers, applications, etc).
+         */
+        add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE,
+                low_mem - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM);
+        /*
+         * Add the memory reserved for reset vector.
+         */
+        add_memory_region(0x1fc00000, MEBIBYTE(4), BOOT_MEM_RESERVED);
+#endif
+}
+
+void __init prom_free_prom_memory(void)
+{
+        unsigned long addr;
+        int i;
+
+        for (i = 0; i < boot_mem_map.nr_map; i++) {
+                if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
+                        continue;
+
+                addr = boot_mem_map.map[i].addr;
+                free_init_pages("prom memory",
+                                addr, addr + boot_mem_map.map[i].size);
+        }
+}
diff --git a/arch/mips/powertv/pci/Makefile b/arch/mips/powertv/pci/Makefile
new file mode 100644
index 000000000000..f5c62462fc9d
--- /dev/null
+++ b/arch/mips/powertv/pci/Makefile
@@ -0,0 +1,21 @@
+#
+# Copyright (C) 2009  Scientific-Atlanta, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+obj-$(CONFIG_PCI)       += fixup-powertv.o
+
+EXTRA_CFLAGS += -Wall -Werror
diff --git a/arch/mips/powertv/pci/fixup-powertv.c b/arch/mips/powertv/pci/fixup-powertv.c
new file mode 100644
index 000000000000..726bc2e824b3
--- /dev/null
+++ b/arch/mips/powertv/pci/fixup-powertv.c
@@ -0,0 +1,36 @@
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <asm/mach-powertv/interrupts.h>
+#include "powertv-pci.h"
+
+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        return asic_pcie_map_irq(dev, slot, pin);
+}
+
+/* Do platform specific device initialization at pci_enable_device() time */
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+        return 0;
+}
+
+/*
+ * asic_pcie_map_irq
+ *
+ * Parameters:
+ * *dev - pointer to a pci_dev structure  (not used)
+ * slot - slot number  (not used)
+ * pin - pin number  (not used)
+ *
+ * Return Value:
+ * Returns: IRQ number (always the PCI Express IRQ number)
+ *
+ * Description:
+ * asic_pcie_map_irq will return the IRQ number of the PCI Express interrupt.
+ *
+ */
+int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        return irq_pciexp;
+}
+EXPORT_SYMBOL(asic_pcie_map_irq);
diff --git a/arch/mips/powertv/pci/powertv-pci.h b/arch/mips/powertv/pci/powertv-pci.h
new file mode 100644
index 000000000000..1b5886bbd759
--- /dev/null
+++ b/arch/mips/powertv/pci/powertv-pci.h
@@ -0,0 +1,31 @@
+/*
+ *                              powertv-pci.c
+ *
+ * Copyright (C) 2009  Cisco Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+/*
+ * Local definitions for the powertv PCI code
+ */
+
+#ifndef _POWERTV_PCI_POWERTV_PCI_H_
+#define _POWERTV_PCI_POWERTV_PCI_H_
+extern int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
+extern int asic_pcie_init(void);
+extern int asic_pcie_init(void);
+
+extern int log_level;
+#endif
diff --git a/arch/mips/powertv/powertv-clock.h b/arch/mips/powertv/powertv-clock.h
new file mode 100644
index 000000000000..d94c54311485
--- /dev/null
+++ b/arch/mips/powertv/powertv-clock.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2009  Cisco Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ * Author: David VomLehn
+ */
+
+#ifndef _POWERTV_POWERTV_CLOCK_H
+#define _POWERTV_POWERTV_CLOCK_H
+extern int powertv_clockevent_init(void);
+extern void powertv_clocksource_init(void);
+extern unsigned int mips_get_pll_freq(void);
+#endif
diff --git a/arch/mips/powertv/powertv_setup.c b/arch/mips/powertv/powertv_setup.c
new file mode 100644
index 000000000000..bd8ebf128f29
--- /dev/null
+++ b/arch/mips/powertv/powertv_setup.c
@@ -0,0 +1,351 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ * Portions copyright (C) 2009 Cisco Systems, Inc.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/pci.h>
+#include <linux/screen_info.h>
+#include <linux/notifier.h>
+#include <linux/etherdevice.h>
+#include <linux/if_ether.h>
+#include <linux/ctype.h>
+
+#include <linux/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+#include <asm/mips-boards/generic.h>
+#include <asm/mips-boards/prom.h>
+#include <asm/dma.h>
+#include <linux/time.h>
+#include <asm/traps.h>
+#include <asm/asm-offsets.h>
+#include "reset.h"
+
+#define VAL(n)          STR(n)
+
+/*
+ * Macros for loading addresses and storing registers:
+ * PTR_LA       Load the address into a register
+ * LONG_S       Store the full width of the given register.
+ * LONG_L       Load the full width of the given register
+ * PTR_ADDIU    Add a constant value to a register used as a pointer
+ * REG_SIZE     Number of 8-bit bytes in a full width register
+ */
+#ifdef CONFIG_64BIT
+#warning TODO: 64-bit code needs to be verified
+#define PTR_LA          "dla    "
+#define LONG_S          "sd     "
+#define LONG_L          "ld     "
+#define PTR_ADDIU       "daddiu "
+#define REG_SIZE        "8"             /* In bytes */
+#endif
+
+#ifdef CONFIG_32BIT
+#define PTR_LA          "la     "
+#define LONG_S          "sw     "
+#define LONG_L          "lw     "
+#define PTR_ADDIU       "addiu  "
+#define REG_SIZE        "4"             /* In bytes */
+#endif
+
+static struct pt_regs die_regs;
+static bool have_die_regs;
+
+static void register_panic_notifier(void);
+static int panic_handler(struct notifier_block *notifier_block,
+        unsigned long event, void *cause_string);
+
+const char *get_system_type(void)
+{
+        return "PowerTV";
+}
+
+void __init plat_mem_setup(void)
+{
+        panic_on_oops = 1;
+        register_panic_notifier();
+
+#if 0
+        mips_pcibios_init();
+#endif
+        mips_reboot_setup();
+}
+
+/*
+ * Install a panic notifier for platform-specific diagnostics
+ */
+static void register_panic_notifier()
+{
+        static struct notifier_block panic_notifier = {
+                .notifier_call = panic_handler,
+                .next = NULL,
+                .priority       = INT_MAX
+        };
+        atomic_notifier_chain_register(&panic_notifier_list, &panic_notifier);
+}
+
+static int panic_handler(struct notifier_block *notifier_block,
+        unsigned long event, void *cause_string)
+{
+        struct pt_regs  my_regs;
+
+        /* Save all of the registers */
+        {
+                unsigned long   at, v0, v1; /* Must be on the stack */
+
+                /* Start by saving $at and v0 on the stack. We use $at
+                 * ourselves, but it looks like the compiler may use v0 or v1
+                 * to load the address of the pt_regs structure. We'll come
+                 * back later to store the registers in the pt_regs
+                 * structure. */
+                __asm__ __volatile__ (
+                        ".set   noat\n"
+                        LONG_S          "$at, %[at]\n"
+                        LONG_S          "$2, %[v0]\n"
+                        LONG_S          "$3, %[v1]\n"
+                :
+                        [at] "=m" (at),
+                        [v0] "=m" (v0),
+                        [v1] "=m" (v1)
+                :
+                :       "at"
+                );
+
+                __asm__ __volatile__ (
+                        ".set   noat\n"
+                        "move           $at, %[pt_regs]\n"
+
+                        /* Argument registers */
+                        LONG_S          "$4, " VAL(PT_R4) "($at)\n"
+                        LONG_S          "$5, " VAL(PT_R5) "($at)\n"
+                        LONG_S          "$6, " VAL(PT_R6) "($at)\n"
+                        LONG_S          "$7, " VAL(PT_R7) "($at)\n"
+
+                        /* Temporary regs */
+                        LONG_S          "$8, " VAL(PT_R8) "($at)\n"
+                        LONG_S          "$9, " VAL(PT_R9) "($at)\n"
+                        LONG_S          "$10, " VAL(PT_R10) "($at)\n"
+                        LONG_S          "$11, " VAL(PT_R11) "($at)\n"
+                        LONG_S          "$12, " VAL(PT_R12) "($at)\n"
+                        LONG_S          "$13, " VAL(PT_R13) "($at)\n"
+                        LONG_S          "$14, " VAL(PT_R14) "($at)\n"
+                        LONG_S          "$15, " VAL(PT_R15) "($at)\n"
+
+                        /* "Saved" registers */
+                        LONG_S          "$16, " VAL(PT_R16) "($at)\n"
+                        LONG_S          "$17, " VAL(PT_R17) "($at)\n"
+                        LONG_S          "$18, " VAL(PT_R18) "($at)\n"
+                        LONG_S          "$19, " VAL(PT_R19) "($at)\n"
+                        LONG_S          "$20, " VAL(PT_R20) "($at)\n"
+                        LONG_S          "$21, " VAL(PT_R21) "($at)\n"
+                        LONG_S          "$22, " VAL(PT_R22) "($at)\n"
+                        LONG_S          "$23, " VAL(PT_R23) "($at)\n"
+
+                        /* Add'l temp regs */
+                        LONG_S          "$24, " VAL(PT_R24) "($at)\n"
+                        LONG_S          "$25, " VAL(PT_R25) "($at)\n"
+
+                        /* Kernel temp regs */
+                        LONG_S          "$26, " VAL(PT_R26) "($at)\n"
+                        LONG_S          "$27, " VAL(PT_R27) "($at)\n"
+
+                        /* Global pointer, stack pointer, frame pointer and
+                         * return address */
+                        LONG_S          "$gp, " VAL(PT_R28) "($at)\n"
+                        LONG_S          "$sp, " VAL(PT_R29) "($at)\n"
+                        LONG_S          "$fp, " VAL(PT_R30) "($at)\n"
+                        LONG_S          "$ra, " VAL(PT_R31) "($at)\n"
+
+                        /* Now we can get the $at and v0 registers back and
+                         * store them */
+                        LONG_L          "$8, %[at]\n"
+                        LONG_S          "$8, " VAL(PT_R1) "($at)\n"
+                        LONG_L          "$8, %[v0]\n"
+                        LONG_S          "$8, " VAL(PT_R2) "($at)\n"
+                        LONG_L          "$8, %[v1]\n"
+                        LONG_S          "$8, " VAL(PT_R3) "($at)\n"
+                :
+                :
+                        [at] "m" (at),
+                        [v0] "m" (v0),
+                        [v1] "m" (v1),
+                        [pt_regs] "r" (&my_regs)
+                :       "at", "t0"
+                );
+
+                /* Set the current EPC value to be the current location in this
+                 * function */
+                __asm__ __volatile__ (
+                        ".set   noat\n"
+                "1:\n"
+                        PTR_LA          "$at, 1b\n"
+                        LONG_S          "$at, %[cp0_epc]\n"
+                :
+                        [cp0_epc] "=m" (my_regs.cp0_epc)
+                :
+                :       "at"
+                );
+
+                my_regs.cp0_cause = read_c0_cause();
+                my_regs.cp0_status = read_c0_status();
+        }
+
+#ifdef CONFIG_DIAGNOSTICS
+        failure_report((char *) cause_string,
+                have_die_regs ? &die_regs : &my_regs);
+        have_die_regs = false;
+#else
+        pr_crit("I'm feeling a bit sleepy. hmmmmm... perhaps a nap would... "
+                "zzzz... \n");
+#endif
+
+        return NOTIFY_DONE;
+}
+
+/**
+ * Platform-specific handling of oops
+ * @str:        Pointer to the oops string
+ * @regs:       Pointer to the oops registers
+ * All we do here is to save the registers for subsequent printing through
+ * the panic notifier.
+ */
+void platform_die(const char *str, const struct pt_regs *regs)
+{
+        /* If we already have saved registers, don't overwrite them as they
+         * they apply to the initial fault */
+
+        if (!have_die_regs) {
+                have_die_regs = true;
+                die_regs = *regs;
+        }
+}
+
+/* Information about the RF MAC address, if one was supplied on the
+ * command line. */
+static bool have_rfmac;
+static u8 rfmac[ETH_ALEN];
+
+static int rfmac_param(char *p)
+{
+        u8      *q;
+        bool    is_high_nibble;
+        int     c;
+
+        /* Skip a leading "0x", if present */
+        if (*p == '0' && *(p+1) == 'x')
+                p += 2;
+
+        q = rfmac;
+        is_high_nibble = true;
+
+        for (c = (unsigned char) *p++;
+                isxdigit(c) && q - rfmac < ETH_ALEN;
+                c = (unsigned char) *p++) {
+                int     nibble;
+
+                nibble = (isdigit(c) ? (c - '0') :
+                        (isupper(c) ? c - 'A' + 10 : c - 'a' + 10));
+
+                if (is_high_nibble)
+                        *q = nibble << 4;
+                else
+                        *q++ |= nibble;
+
+                is_high_nibble = !is_high_nibble;
+        }
+
+        /* If we parsed all the way to the end of the parameter value and
+         * parsed all ETH_ALEN bytes, we have a usable RF MAC address */
+        have_rfmac = (c == '\0' && q - rfmac == ETH_ALEN);
+
+        return 0;
+}
+
+early_param("rfmac", rfmac_param);
+
+/*
+ * Generate an Ethernet MAC address that has a good chance of being unique.
+ * @addr:       Pointer to six-byte array containing the Ethernet address
+ * Generates an Ethernet MAC address that is highly likely to be unique for
+ * this particular system on a network with other systems of the same type.
+ *
+ * The problem we are solving is that, when random_ether_addr() is used to
+ * generate MAC addresses at startup, there isn't much entropy for the random
+ * number generator to use and the addresses it produces are fairly likely to
+ * be the same as those of other identical systems on the same local network.
+ * This is true even for relatively small numbers of systems (for the reason
+ * why, see the Wikipedia entry for "Birthday problem" at:
+ *      http://en.wikipedia.org/wiki/Birthday_problem
+ *
+ * The good news is that we already have a MAC address known to be unique, the
+ * RF MAC address. The bad news is that this address is already in use on the
+ * RF interface. Worse, the obvious trick, taking the RF MAC address and
+ * turning on the locally managed bit, has already been used for other devices.
+ * Still, this does give us something to work with.
+ *
+ * The approach we take is:
+ * 1.   If we can't get the RF MAC Address, just call random_ether_addr.
+ * 2.   Use the 24-bit NIC-specific bits of the RF MAC address as the last 24
+ *      bits of the new address. This is very likely to be unique, except for
+ *      the current box.
+ * 3.   To avoid using addresses already on the current box, we set the top
+ *      six bits of the address with a value different from any currently
+ *      registered Scientific Atlanta organizationally unique identifyer
+ *      (OUI). This avoids duplication with any addresses on the system that
+ *      were generated from valid Scientific Atlanta-registered address by
+ *      simply flipping the locally managed bit.
+ * 4.   We aren't generating a multicast address, so we leave the multicast
+ *      bit off. Since we aren't using a registered address, we have to set
+ *      the locally managed bit.
+ * 5.   We then randomly generate the remaining 16-bits. This does two
+ *      things:
+ *      a.      It allows us to call this function for more than one device
+ *              in this system
+ *      b.      It ensures that things will probably still work even if
+ *              some device on the device network has a locally managed
+ *              address that matches the top six bits from step 2.
+ */
+void platform_random_ether_addr(u8 addr[ETH_ALEN])
+{
+        const int num_random_bytes = 2;
+        const unsigned char non_sciatl_oui_bits = 0xc0u;
+        const unsigned char mac_addr_locally_managed = (1 << 1);
+
+        if (!have_rfmac) {
+                pr_warning("rfmac not available on command line; "
+                        "generating random MAC address\n");
+                random_ether_addr(addr);
+        }
+
+        else {
+                int     i;
+
+                /* Set the first byte to something that won't match a Scientific
+                 * Atlanta OUI, is locally managed, and isn't a multicast
+                 * address */
+                addr[0] = non_sciatl_oui_bits | mac_addr_locally_managed;
+
+                /* Get some bytes of random address information */
+                get_random_bytes(&addr[1], num_random_bytes);
+
+                /* Copy over the NIC-specific bits of the RF MAC address */
+                for (i = 1 + num_random_bytes; i < ETH_ALEN; i++)
+                        addr[i] = rfmac[i];
+        }
+}
diff --git a/arch/mips/powertv/reset.c b/arch/mips/powertv/reset.c
new file mode 100644
index 000000000000..494c652c984b
--- /dev/null
+++ b/arch/mips/powertv/reset.c
@@ -0,0 +1,65 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
+ * Portions copyright (C) 2009 Cisco Systems, Inc.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+#include <linux/pm.h>
+
+#include <linux/io.h>
+#include <asm/reboot.h>                 /* Not included by linux/reboot.h */
+
+#ifdef CONFIG_BOOTLOADER_DRIVER
+#include <asm/mach-powertv/kbldr.h>
+#endif
+
+#include <asm/mach-powertv/asic_regs.h>
+#include "reset.h"
+
+static void mips_machine_restart(char *command);
+static void mips_machine_halt(void);
+
+static void mips_machine_restart(char *command)
+{
+#ifdef CONFIG_BOOTLOADER_DRIVER
+        /*
+         * Call the bootloader's reset function to ensure
+         * that persistent data is flushed before hard reset
+         */
+        kbldr_SetCauseAndReset();
+#else
+        writel(0x1, asic_reg_addr(watchdog));
+#endif
+}
+
+static void mips_machine_halt(void)
+{
+#ifdef CONFIG_BOOTLOADER_DRIVER
+        /*
+         * Call the bootloader's reset function to ensure
+         * that persistent data is flushed before hard reset
+         */
+        kbldr_SetCauseAndReset();
+#else
+        writel(0x1, asic_reg_addr(watchdog));
+#endif
+}
+
+void mips_reboot_setup(void)
+{
+        _machine_restart = mips_machine_restart;
+        _machine_halt = mips_machine_halt;
+        pm_power_off = mips_machine_halt;
+}
diff --git a/arch/mips/powertv/reset.h b/arch/mips/powertv/reset.h
new file mode 100644
index 000000000000..888fd09e2620
--- /dev/null
+++ b/arch/mips/powertv/reset.h
@@ -0,0 +1,26 @@
+/*
+ * Definitions from powertv reset.c file
+ *
+ * Copyright (C) 2009  Cisco Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ * Author: David VomLehn
+ */
+
+#ifndef _POWERTV_POWERTV_RESET_H
+#define _POWERTV_POWERTV_RESET_H
+extern void mips_reboot_setup(void);
+#endif
diff --git a/arch/mips/mipssim/sim_cmdline.c b/arch/mips/powertv/time.c
index 74240e1ce5a5..1e0a5ef4c8c7 100644
--- a/arch/mips/mipssim/sim_cmdline.c
+++ b/arch/mips/powertv/time.c
@@ -1,5 +1,7 @@
 /*
- * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
+ * Portions copyright (C) 2009 Cisco Systems, Inc.
  *
  *  This program is free software; you can distribute it and/or modify it
  *  under the terms of the GNU General Public License (Version 2) as
@@ -14,19 +16,22 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  *
+ * Setting up the clock on the MIPS boards.
  */
+
 #include <linux/init.h>
-#include <linux/string.h>
-#include <asm/bootinfo.h>
+#include <asm/mach-powertv/interrupts.h>
+#include <asm/time.h>
 
-extern char arcs_cmdline[];
+#include "powertv-clock.h"
 
-char * __init prom_getcmdline(void)
+unsigned int __cpuinit get_c0_compare_int(void)
 {
-        return arcs_cmdline;
+        return irq_mips_timer;
 }
 
-void  __init prom_init_cmdline(void)
+void __init plat_time_init(void)
 {
-        /* XXX: Get boot line from environment? */
+        powertv_clocksource_init();
+        r4k_clockevent_init();
 }
diff --git a/arch/mips/rb532/prom.c b/arch/mips/rb532/prom.c
index ad5bd1097974..d7c26d00cfef 100644
--- a/arch/mips/rb532/prom.c
+++ b/arch/mips/rb532/prom.c
@@ -69,7 +69,7 @@ static inline unsigned long tag2ul(char *arg, const char *tag)
 
 void __init prom_setup_cmdline(void)
 {
-        static char cmd_line[CL_SIZE] __initdata;
+        static char cmd_line[COMMAND_LINE_SIZE] __initdata;
         char *cp, *board;
         int prom_argc;
         char **prom_argv, **prom_envp;
@@ -115,7 +115,7 @@ void __init prom_setup_cmdline(void)
                 strcpy(cp, arcs_cmdline);
                 cp += strlen(arcs_cmdline);
         }
-        cmd_line[CL_SIZE-1] = '\0';
+        cmd_line[COMMAND_LINE_SIZE - 1] = '\0';
 
         strcpy(arcs_cmdline, cmd_line);
 }
diff --git a/arch/mips/sgi-ip22/ip22-eisa.c b/arch/mips/sgi-ip22/ip22-eisa.c
index 1617241d2737..da44ccb20829 100644
--- a/arch/mips/sgi-ip22/ip22-eisa.c
+++ b/arch/mips/sgi-ip22/ip22-eisa.c
@@ -50,9 +50,9 @@
 
 static char __init *decode_eisa_sig(unsigned long addr)
 {
-        static char sig_str[EISA_SIG_LEN];
+        static char sig_str[EISA_SIG_LEN] __initdata;
         u8 sig[4];
-        u16 rev;
+        u16 rev;
         int i;
 
         for (i = 0; i < 4; i++) {
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index 0ecd5fe9486e..383f11d7f442 100644
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -13,6 +13,7 @@
 #include <linux/init.h>
 #include <linux/kernel_stat.h>
 #include <linux/interrupt.h>
+#include <linux/ftrace.h>
 
 #include <asm/irq_cpu.h>
 #include <asm/sgi/hpc3.h>
@@ -150,7 +151,7 @@ static void indy_local1_irqdispatch(void)
 
 extern void ip22_be_interrupt(int irq);
 
-static void indy_buserror_irq(void)
+static void __irq_entry indy_buserror_irq(void)
 {
         int irq = SGI_BUSERR_IRQ;
 
diff --git a/arch/mips/sgi-ip22/ip22-setup.c b/arch/mips/sgi-ip22/ip22-setup.c
index b9a931358e23..5deeb68b6c9c 100644
--- a/arch/mips/sgi-ip22/ip22-setup.c
+++ b/arch/mips/sgi-ip22/ip22-setup.c
@@ -67,7 +67,7 @@ void __init plat_mem_setup(void)
         cserial = ArcGetEnvironmentVariable("ConsoleOut");
 
         if ((ctype && *ctype == 'd') || (cserial && *cserial == 's')) {
-                static char options[8];
+                static char options[8] __initdata;
                 char *baud = ArcGetEnvironmentVariable("dbaud");
                 if (baud)
                         strcpy(options, baud);
diff --git a/arch/mips/sgi-ip22/ip22-time.c b/arch/mips/sgi-ip22/ip22-time.c
index c8f7d2328b24..603fc91c1030 100644
--- a/arch/mips/sgi-ip22/ip22-time.c
+++ b/arch/mips/sgi-ip22/ip22-time.c
@@ -16,6 +16,7 @@
 #include <linux/interrupt.h>
 #include <linux/kernel_stat.h>
 #include <linux/time.h>
+#include <linux/ftrace.h>
 
 #include <asm/cpu.h>
 #include <asm/mipsregs.h>
@@ -115,7 +116,7 @@ __init void plat_time_init(void)
 }
 
 /* Generic SGI handler for (spurious) 8254 interrupts */
-void indy_8254timer_irq(void)
+void __irq_entry indy_8254timer_irq(void)
 {
         int irq = SGI_8254_0_IRQ;
         ULONG cnt;
diff --git a/arch/mips/sgi-ip32/ip32-setup.c b/arch/mips/sgi-ip32/ip32-setup.c
index c5a5d4a31b4b..3abd1465ec02 100644
--- a/arch/mips/sgi-ip32/ip32-setup.c
+++ b/arch/mips/sgi-ip32/ip32-setup.c
@@ -90,7 +90,7 @@ void __init plat_mem_setup(void)
         {
                 char* con = ArcGetEnvironmentVariable("console");
                 if (con && *con == 'd') {
-                        static char options[8];
+                        static char options[8] __initdata;
                         char *baud = ArcGetEnvironmentVariable("dbaud");
                         if (baud)
                                 strcpy(options, baud);
diff --git a/arch/mips/sibyte/common/cfe.c b/arch/mips/sibyte/common/cfe.c
index eb5396cf81bb..6343011e9902 100644
--- a/arch/mips/sibyte/common/cfe.c
+++ b/arch/mips/sibyte/common/cfe.c
@@ -287,7 +287,7 @@ void __init prom_init(void)
          * boot console
          */
         cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
-        if (cfe_getenv("LINUX_CMDLINE", arcs_cmdline, CL_SIZE) < 0) {
+        if (cfe_getenv("LINUX_CMDLINE", arcs_cmdline, COMMAND_LINE_SIZE) < 0) {
                 if (argc >= 0) {
                         /* The loader should have set the command line */
                         /* too early for panic to do any good */
@@ -318,7 +318,7 @@ void __init prom_init(void)
 #endif /* CONFIG_BLK_DEV_INITRD */
 
         /* Not sure this is needed, but it's the safe way. */
-        arcs_cmdline[CL_SIZE-1] = 0;
+        arcs_cmdline[COMMAND_LINE_SIZE-1] = 0;
 
         prom_meminit();
 
diff --git a/arch/mips/sni/a20r.c b/arch/mips/sni/a20r.c
index 7dd76fb3b645..e6980892834a 100644
--- a/arch/mips/sni/a20r.c
+++ b/arch/mips/sni/a20r.c
@@ -188,7 +188,7 @@ static void end_a20r_irq(unsigned int irq)
 }
 
 static struct irq_chip a20r_irq_type = {
-        .typename       = "A20R",
+        .name           = "A20R",
         .ack            = mask_a20r_irq,
         .mask           = mask_a20r_irq,
         .mask_ack       = mask_a20r_irq,
diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c
index 74e6c67982fb..51e62bbaa23b 100644
--- a/arch/mips/sni/pcimt.c
+++ b/arch/mips/sni/pcimt.c
@@ -214,7 +214,7 @@ static void end_pcimt_irq(unsigned int irq)
 }
 
 static struct irq_chip pcimt_irq_type = {
-        .typename = "PCIMT",
+        .name = "PCIMT",
         .ack = disable_pcimt_irq,
         .mask = disable_pcimt_irq,
         .mask_ack = disable_pcimt_irq,
diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c
index 071a9573ac7f..f4699d35858b 100644
--- a/arch/mips/sni/pcit.c
+++ b/arch/mips/sni/pcit.c
@@ -176,7 +176,7 @@ void end_pcit_irq(unsigned int irq)
 }
 
 static struct irq_chip pcit_irq_type = {
-        .typename = "PCIT",
+        .name = "PCIT",
         .ack = disable_pcit_irq,
         .mask = disable_pcit_irq,
         .mask_ack = disable_pcit_irq,
diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c
index 5e687819cbc2..46f00691f448 100644
--- a/arch/mips/sni/rm200.c
+++ b/arch/mips/sni/rm200.c
@@ -449,7 +449,7 @@ void end_rm200_irq(unsigned int irq)
 }
 
 static struct irq_chip rm200_irq_type = {
-        .typename = "RM200",
+        .name = "RM200",
         .ack = disable_rm200_irq,
         .mask = disable_rm200_irq,
         .mask_ack = disable_rm200_irq,
diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c
index a49272ce7ef5..d16b462154c3 100644
--- a/arch/mips/sni/setup.c
+++ b/arch/mips/sni/setup.c
@@ -60,7 +60,7 @@ static void __init sni_console_setup(void)
         char *cdev;
         char *baud;
         int port;
-        static char options[8];
+        static char options[8] __initdata;
 
         cdev = prom_getenv("console_dev");
         if (strncmp(cdev, "tty", 3) == 0) {
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index d66802edebb2..06e801c7e258 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -160,7 +160,7 @@ static void __init prom_init_cmdline(void)
         int argc;
         int *argv32;
         int i;                  /* Always ignore the "-c" at argv[0] */
-        static char builtin[CL_SIZE] __initdata;
+        static char builtin[COMMAND_LINE_SIZE] __initdata;
 
         if (fw_arg0 >= CKSEG0 || fw_arg1 < CKSEG0) {
                 /*
@@ -315,7 +315,7 @@ static inline void txx9_cache_fixup(void)
 
 static void __init preprocess_cmdline(void)
 {
-        static char cmdline[CL_SIZE] __initdata;
+        static char cmdline[COMMAND_LINE_SIZE] __initdata;
         char *s;
 
         strcpy(cmdline, arcs_cmdline);
diff --git a/arch/mn10300/include/asm/asm-offsets.h b/arch/mn10300/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/mn10300/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/parisc/include/asm/asm-offsets.h b/arch/parisc/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/parisc/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/powerpc/boot/dts/katmai.dts b/arch/powerpc/boot/dts/katmai.dts
index 51eb6ed5da2d..8f345de960cd 100644
--- a/arch/powerpc/boot/dts/katmai.dts
+++ b/arch/powerpc/boot/dts/katmai.dts
@@ -108,12 +108,19 @@
                 dcr-reg = <0x00c 0x002>;
         };
 
+        MQ0: mq {
+                compatible = "ibm,mq-440spe";
+                dcr-reg = <0x040 0x020>;
+        };
+
         plb {
                 compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4";
                 #address-cells = <2>;
                 #size-cells = <1>;
                 /*        addr-child     addr-parent    size */
-                ranges = <0x4 0xe0000000 0x4 0xe0000000 0x20000000
+                ranges = <0x4 0x00100000 0x4 0x00100000 0x00001000
+                          0x4 0x00200000 0x4 0x00200000 0x00000400
+                          0x4 0xe0000000 0x4 0xe0000000 0x20000000
                           0xc 0x00000000 0xc 0x00000000 0x20000000
                           0xd 0x00000000 0xd 0x00000000 0x80000000
                           0xd 0x80000000 0xd 0x80000000 0x80000000
@@ -400,6 +407,49 @@
                                 0x0 0x0 0x0 0x3 &UIC3 0xa 0x4 /* swizzled int C */
                                 0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>;
                 };
+
+                I2O: i2o@400100000 {
+                        compatible = "ibm,i2o-440spe";
+                        reg = <0x00000004 0x00100000 0x100>;
+                        dcr-reg = <0x060 0x020>;
+                };
+
+                DMA0: dma0@400100100 {
+                        compatible = "ibm,dma-440spe";
+                        cell-index = <0>;
+                        reg = <0x00000004 0x00100100 0x100>;
+                        dcr-reg = <0x060 0x020>;
+                        interrupt-parent = <&DMA0>;
+                        interrupts = <0 1>;
+                        #interrupt-cells = <1>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <
+                                0 &UIC0 0x14 4
+                                1 &UIC1 0x16 4>;
+                };
+
+                DMA1: dma1@400100200 {
+                        compatible = "ibm,dma-440spe";
+                        cell-index = <1>;
+                        reg = <0x00000004 0x00100200 0x100>;
+                        dcr-reg = <0x060 0x020>;
+                        interrupt-parent = <&DMA1>;
+                        interrupts = <0 1>;
+                        #interrupt-cells = <1>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <
+                                0 &UIC0 0x16 4
+                                1 &UIC1 0x16 4>;
+                };
+
+                xor-accel@400200000 {
+                        compatible = "amcc,xor-accelerator";
+                        reg = <0x00000004 0x00200000 0x400>;
+                        interrupt-parent = <&UIC1>;
+                        interrupts = <0x1f 4>;
+                };
         };
 
         chosen {
diff --git a/arch/powerpc/boot/dts/mpc8315erdb.dts b/arch/powerpc/boot/dts/mpc8315erdb.dts
index 32e10f588c1d..8a3a4f3ef831 100644
--- a/arch/powerpc/boot/dts/mpc8315erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8315erdb.dts
@@ -204,6 +204,7 @@
                         interrupt-parent = <&ipic>;
                         tbi-handle = <&tbi0>;
                         phy-handle = < &phy0 >;
+                        fsl,magic-packet;
 
                         mdio@520 {
                                 #address-cells = <1>;
@@ -246,6 +247,7 @@
                         interrupt-parent = <&ipic>;
                         tbi-handle = <&tbi1>;
                         phy-handle = < &phy1 >;
+                        fsl,magic-packet;
 
                         mdio@520 {
                                 #address-cells = <1>;
@@ -309,6 +311,22 @@
                         interrupt-parent = <&ipic>;
                 };
 
+                gtm1: timer@500 {
+                        compatible = "fsl,mpc8315-gtm", "fsl,gtm";
+                        reg = <0x500 0x100>;
+                        interrupts = <90 8 78 8 84 8 72 8>;
+                        interrupt-parent = <&ipic>;
+                        clock-frequency = <133333333>;
+                };
+
+                timer@600 {
+                        compatible = "fsl,mpc8315-gtm", "fsl,gtm";
+                        reg = <0x600 0x100>;
+                        interrupts = <91 8 79 8 85 8 73 8>;
+                        interrupt-parent = <&ipic>;
+                        clock-frequency = <133333333>;
+                };
+
                 /* IPIC
                  * interrupts cell = <intr #, sense>
                  * sense values match linux IORESOURCE_IRQ_* defines:
@@ -337,6 +355,15 @@
                                       0x59 0x8>;
                         interrupt-parent = < &ipic >;
                 };
+
+                pmc: power@b00 {
+                        compatible = "fsl,mpc8315-pmc", "fsl,mpc8313-pmc",
+                                     "fsl,mpc8349-pmc";
+                        reg = <0xb00 0x100 0xa00 0x100>;
+                        interrupts = <80 8>;
+                        interrupt-parent = <&ipic>;
+                        fsl,mpc8313-wakeup-timer = <&gtm1>;
+                };
         };
 
         pci0: pci@e0008500 {
diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts b/arch/powerpc/boot/dts/mpc8349emitx.dts
index feeeb7f9d609..b53d1df11e2d 100644
--- a/arch/powerpc/boot/dts/mpc8349emitx.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitx.dts
@@ -63,6 +63,24 @@
                         reg = <0x200 0x100>;
                 };
 
+                gpio1: gpio-controller@c00 {
+                        #gpio-cells = <2>;
+                        compatible = "fsl,mpc8349-gpio";
+                        reg = <0xc00 0x100>;
+                        interrupts = <74 0x8>;
+                        interrupt-parent = <&ipic>;
+                        gpio-controller;
+                };
+
+                gpio2: gpio-controller@d00 {
+                        #gpio-cells = <2>;
+                        compatible = "fsl,mpc8349-gpio";
+                        reg = <0xd00 0x100>;
+                        interrupts = <75 0x8>;
+                        interrupt-parent = <&ipic>;
+                        gpio-controller;
+                };
+
                 i2c@3000 {
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -72,6 +90,12 @@
                         interrupts = <14 0x8>;
                         interrupt-parent = <&ipic>;
                         dfsrr;
+
+                        eeprom: at24@50 {
+                                compatible = "st-micro,24c256";
+                                reg = <0x50>;
+                        };
+
                 };
 
                 i2c@3100 {
@@ -91,6 +115,25 @@
                                 interrupt-parent = <&ipic>;
                         };
 
+                        pcf1: iexp@38 {
+                                #gpio-cells = <2>;
+                                compatible = "ti,pcf8574a";
+                                reg = <0x38>;
+                                gpio-controller;
+                        };
+
+                        pcf2: iexp@39 {
+                                #gpio-cells = <2>;
+                                compatible = "ti,pcf8574a";
+                                reg = <0x39>;
+                                gpio-controller;
+                        };
+
+                        spd: at24@51 {
+                                compatible = "at24,spd";
+                                reg = <0x51>;
+                        };
+
                         mcu_pio: mcu@a {
                                 #gpio-cells = <2>;
                                 compatible = "fsl,mc9s08qg8-mpc8349emitx",
@@ -275,6 +318,24 @@
                         reg = <0x700 0x100>;
                         device_type = "ipic";
                 };
+
+                gpio-leds {
+                        compatible = "gpio-leds";
+
+                        green {
+                                label = "Green";
+                                gpios = <&pcf1 0 1>;
+                                linux,default-trigger = "heartbeat";
+                        };
+
+                        yellow {
+                                label = "Yellow";
+                                gpios = <&pcf1 1 1>;
+                                /* linux,default-trigger = "heartbeat"; */
+                                default-state = "on";
+                        };
+                };
+
         };
 
         pci0: pci@e0008500 {
@@ -331,7 +392,26 @@
                 compatible = "fsl,mpc8349e-localbus",
                              "fsl,pq2pro-localbus";
                 reg = <0xe0005000 0xd8>;
-                ranges = <0x3 0x0 0xf0000000 0x210>;
+                ranges = <0x0 0x0 0xfe000000 0x1000000  /* flash */
+                          0x1 0x0 0xf8000000 0x20000    /* VSC 7385 */
+                          0x2 0x0 0xf9000000 0x200000   /* exp slot */
+                          0x3 0x0 0xf0000000 0x210>;    /* CF slot */
+
+                flash@0,0 {
+                        compatible = "cfi-flash";
+                        reg = <0x0      0x0 0x800000>;
+                        bank-width = <2>;
+                        device-width = <1>;
+                };
+
+                flash@0,800000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "cfi-flash";
+                        reg = <0x0 0x800000 0x800000>;
+                        bank-width = <2>;
+                        device-width = <1>;
+                };
 
                 pata@3,0 {
                         compatible = "fsl,mpc8349emitx-pata", "ata-generic";
diff --git a/arch/powerpc/boot/dts/warp.dts b/arch/powerpc/boot/dts/warp.dts
index 31605ee4afb6..e576ee85c42f 100644
--- a/arch/powerpc/boot/dts/warp.dts
+++ b/arch/powerpc/boot/dts/warp.dts
@@ -146,7 +146,7 @@
 
                                 fpga@2,4000 {
                                         compatible = "pika,fpga-sd";
-                                        reg = <0x00000002 0x00004000 0x00000A00>;
+                                        reg = <0x00000002 0x00004000 0x00004000>;
                                 };
 
                                 nor@0,0 {
diff --git a/arch/powerpc/boot/ugecon.c b/arch/powerpc/boot/ugecon.c
index 50609ea6ddf8..8f2a6b311534 100644
--- a/arch/powerpc/boot/ugecon.c
+++ b/arch/powerpc/boot/ugecon.c
@@ -86,7 +86,7 @@ static void ug_putc(char ch)
 
         while (!ug_is_txfifo_ready() && count--)
                 barrier();
-        if (count)
+        if (count >= 0)
                 ug_raw_putc(ch);
 }
 
diff --git a/arch/powerpc/configs/g5_defconfig b/arch/powerpc/configs/g5_defconfig
index fc905924c022..826a65d3f002 100644
--- a/arch/powerpc/configs/g5_defconfig
+++ b/arch/powerpc/configs/g5_defconfig
@@ -757,7 +757,7 @@ CONFIG_SUNGEM=y
 # CONFIG_B44 is not set
 # CONFIG_ATL2 is not set
 CONFIG_NETDEV_1000=y
-CONFIG_ACENIC=y
+CONFIG_ACENIC=m
 CONFIG_ACENIC_OMIT_TIGON_I=y
 # CONFIG_DL2K is not set
 CONFIG_E1000=y
@@ -794,8 +794,8 @@ CONFIG_NETDEV_10000=y
 # CONFIG_BNX2X is not set
 # CONFIG_QLGE is not set
 # CONFIG_SFC is not set
-CONFIG_TR=y
-CONFIG_IBMOL=y
+# CONFIG_TR is not set
+# CONFIG_IBMOL is not set
 # CONFIG_3C359 is not set
 # CONFIG_TMS380TR is not set
 
diff --git a/arch/powerpc/configs/iseries_defconfig b/arch/powerpc/configs/iseries_defconfig
index f925c555508e..76982c51a4c7 100644
--- a/arch/powerpc/configs/iseries_defconfig
+++ b/arch/powerpc/configs/iseries_defconfig
@@ -714,8 +714,8 @@ CONFIG_NETDEV_10000=y
 # CONFIG_BNX2X is not set
 # CONFIG_QLGE is not set
 # CONFIG_SFC is not set
-CONFIG_TR=y
-CONFIG_IBMOL=y
+# CONFIG_TR is not set
+# CONFIG_IBMOL is not set
 # CONFIG_3C359 is not set
 # CONFIG_TMS380TR is not set
 
diff --git a/arch/powerpc/configs/ppc64_defconfig b/arch/powerpc/configs/ppc64_defconfig
index 252401824575..7b3804a6e363 100644
--- a/arch/powerpc/configs/ppc64_defconfig
+++ b/arch/powerpc/configs/ppc64_defconfig
@@ -304,11 +304,11 @@ CONFIG_TICK_ONESHOT=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
+CONFIG_HZ_100=y
+# CONFIG_HZ_250 is not set
 # CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
-CONFIG_HZ=250
+CONFIG_HZ=100
 CONFIG_SCHED_HRTICK=y
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
@@ -980,7 +980,7 @@ CONFIG_E100=y
 # CONFIG_SC92031 is not set
 # CONFIG_ATL2 is not set
 CONFIG_NETDEV_1000=y
-CONFIG_ACENIC=y
+CONFIG_ACENIC=m
 CONFIG_ACENIC_OMIT_TIGON_I=y
 # CONFIG_DL2K is not set
 CONFIG_E1000=y
@@ -1023,8 +1023,8 @@ CONFIG_PASEMI_MAC=y
 # CONFIG_BNX2X is not set
 # CONFIG_QLGE is not set
 # CONFIG_SFC is not set
-CONFIG_TR=y
-CONFIG_IBMOL=y
+# CONFIG_TR is not set
+# CONFIG_IBMOL is not set
 # CONFIG_3C359 is not set
 # CONFIG_TMS380TR is not set
 
@@ -1863,7 +1863,7 @@ CONFIG_HFSPLUS_FS=m
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-CONFIG_CRAMFS=y
+CONFIG_CRAMFS=m
 # CONFIG_VXFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_OMFS_FS is not set
diff --git a/arch/powerpc/configs/ppc64e_defconfig b/arch/powerpc/configs/ppc64e_defconfig
index 18af46036258..8195f1650cbf 100644
--- a/arch/powerpc/configs/ppc64e_defconfig
+++ b/arch/powerpc/configs/ppc64e_defconfig
@@ -1008,8 +1008,8 @@ CONFIG_IXGB=m
 # CONFIG_QLGE is not set
 # CONFIG_SFC is not set
 # CONFIG_BE2NET is not set
-CONFIG_TR=y
-CONFIG_IBMOL=y
+# CONFIG_TR is not set
+# CONFIG_IBMOL is not set
 # CONFIG_3C359 is not set
 # CONFIG_TMS380TR is not set
 CONFIG_WLAN=y
diff --git a/arch/powerpc/configs/pseries_defconfig b/arch/powerpc/configs/pseries_defconfig
index c568329723b8..ca9ff9aad74a 100644
--- a/arch/powerpc/configs/pseries_defconfig
+++ b/arch/powerpc/configs/pseries_defconfig
@@ -230,11 +230,11 @@ CONFIG_TICK_ONESHOT=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
+CONFIG_HZ_100=y
+# CONFIG_HZ_250 is not set
 # CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
-CONFIG_HZ=250
+CONFIG_HZ=100
 CONFIG_SCHED_HRTICK=y
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
@@ -796,7 +796,7 @@ CONFIG_E100=y
 # CONFIG_NET_POCKET is not set
 # CONFIG_ATL2 is not set
 CONFIG_NETDEV_1000=y
-CONFIG_ACENIC=y
+CONFIG_ACENIC=m
 CONFIG_ACENIC_OMIT_TIGON_I=y
 # CONFIG_DL2K is not set
 CONFIG_E1000=y
@@ -834,8 +834,8 @@ CONFIG_S2IO=m
 # CONFIG_BNX2X is not set
 # CONFIG_QLGE is not set
 # CONFIG_SFC is not set
-CONFIG_TR=y
-CONFIG_IBMOL=y
+# CONFIG_TR is not set
+# CONFIG_IBMOL is not set
 # CONFIG_3C359 is not set
 # CONFIG_TMS380TR is not set
 
@@ -1494,7 +1494,7 @@ CONFIG_CONFIGFS_FS=m
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-CONFIG_CRAMFS=y
+CONFIG_CRAMFS=m
 # CONFIG_VXFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_OMFS_FS is not set
diff --git a/arch/powerpc/include/asm/asm-offsets.h b/arch/powerpc/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/powerpc/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/powerpc/include/asm/bug.h b/arch/powerpc/include/asm/bug.h
index 64e1fdca233e..2c15212e1700 100644
--- a/arch/powerpc/include/asm/bug.h
+++ b/arch/powerpc/include/asm/bug.h
@@ -68,7 +68,7 @@
                 _EMIT_BUG_ENTRY                                 \
                 : : "i" (__FILE__), "i" (__LINE__),             \
                     "i" (0), "i"  (sizeof(struct bug_entry)));  \
-        for(;;) ;                                               \
+        unreachable();                                          \
 } while (0)
 
 #define BUG_ON(x) do {                                          \
diff --git a/arch/powerpc/include/asm/gpio.h b/arch/powerpc/include/asm/gpio.h
index ea04632399d8..38762edb5e58 100644
--- a/arch/powerpc/include/asm/gpio.h
+++ b/arch/powerpc/include/asm/gpio.h
@@ -38,12 +38,9 @@ static inline int gpio_cansleep(unsigned int gpio)
         return __gpio_cansleep(gpio);
 }
 
-/*
- * Not implemented, yet.
- */
 static inline int gpio_to_irq(unsigned int gpio)
 {
-        return -ENOSYS;
+        return __gpio_to_irq(gpio);
 }
 
 static inline int irq_to_gpio(unsigned int irq)
diff --git a/arch/powerpc/kernel/align.c b/arch/powerpc/kernel/align.c
index 3839839f83c7..b876e989220b 100644
--- a/arch/powerpc/kernel/align.c
+++ b/arch/powerpc/kernel/align.c
@@ -642,10 +642,14 @@ static int emulate_spe(struct pt_regs *regs, unsigned int reg,
  */
 static int emulate_vsx(unsigned char __user *addr, unsigned int reg,
                        unsigned int areg, struct pt_regs *regs,
-                       unsigned int flags, unsigned int length)
+                       unsigned int flags, unsigned int length,
+                       unsigned int elsize)
 {
         char *ptr;
+        unsigned long *lptr;
         int ret = 0;
+        int sw = 0;
+        int i, j;
 
         flush_vsx_to_thread(current);
 
@@ -654,19 +658,35 @@ static int emulate_vsx(unsigned char __user *addr, unsigned int reg,
         else
                 ptr = (char *) &current->thread.vr[reg - 32];
 
-        if (flags & ST)
-                ret = __copy_to_user(addr, ptr, length);
-        else {
-                if (flags & SPLT){
-                        ret = __copy_from_user(ptr, addr, length);
-                        ptr += length;
+        lptr = (unsigned long *) ptr;
+
+        if (flags & SW)
+                sw = elsize-1;
+
+        for (j = 0; j < length; j += elsize) {
+                for (i = 0; i < elsize; ++i) {
+                        if (flags & ST)
+                                ret |= __put_user(ptr[i^sw], addr + i);
+                        else
+                                ret |= __get_user(ptr[i^sw], addr + i);
                 }
-                ret |= __copy_from_user(ptr, addr, length);
+                ptr  += elsize;
+                addr += elsize;
         }
-        if (flags & U)
-                regs->gpr[areg] = regs->dar;
-        if (ret)
+
+        if (!ret) {
+                if (flags & U)
+                        regs->gpr[areg] = regs->dar;
+
+                /* Splat load copies the same data to top and bottom 8 bytes */
+                if (flags & SPLT)
+                        lptr[1] = lptr[0];
+                /* For 8 byte loads, zero the top 8 bytes */
+                else if (!(flags & ST) && (8 == length))
+                        lptr[1] = 0;
+        } else
                 return -EFAULT;
+
         return 1;
 }
 #endif
@@ -767,16 +787,25 @@ int fix_alignment(struct pt_regs *regs)
 
 #ifdef CONFIG_VSX
         if ((instruction & 0xfc00003e) == 0x7c000018) {
-                /* Additional register addressing bit (64 VSX vs 32 FPR/GPR */
+                unsigned int elsize;
+
+                /* Additional register addressing bit (64 VSX vs 32 FPR/GPR) */
                 reg |= (instruction & 0x1) << 5;
                 /* Simple inline decoder instead of a table */
+                /* VSX has only 8 and 16 byte memory accesses */
+                nb = 8;
                 if (instruction & 0x200)
                         nb = 16;
-                else if (instruction & 0x080)
-                        nb = 8;
-                else
-                        nb = 4;
+
+                /* Vector stores in little-endian mode swap individual
+                   elements, so process them separately */
+                elsize = 4;
+                if (instruction & 0x80)
+                        elsize = 8;
+
                 flags = 0;
+                if (regs->msr & MSR_LE)
+                        flags |= SW;
                 if (instruction & 0x100)
                         flags |= ST;
                 if (instruction & 0x040)
@@ -787,7 +816,7 @@ int fix_alignment(struct pt_regs *regs)
                         nb = 8;
                 }
                 PPC_WARN_ALIGNMENT(vsx, regs);
-                return emulate_vsx(addr, reg, areg, regs, flags, nb);
+                return emulate_vsx(addr, reg, areg, regs, flags, nb, elsize);
         }
 #endif
         /* A size of 0 indicates an instruction we don't support, with
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index 50f867d657df..3ecdcec0a39e 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -340,7 +340,7 @@ static int __init htab_dt_scan_page_sizes(unsigned long node,
                         else
                                 def->tlbiel = 0;
 
-                        DBG(" %d: shift=%02x, sllp=%04x, avpnm=%08x, "
+                        DBG(" %d: shift=%02x, sllp=%04lx, avpnm=%08lx, "
                             "tlbiel=%d, penc=%d\n",
                             idx, shift, def->sllp, def->avpnm, def->tlbiel,
                             def->penc);
@@ -663,7 +663,7 @@ static void __init htab_initialize(void)
                 base = (unsigned long)__va(lmb.memory.region[i].base);
                 size = lmb.memory.region[i].size;
 
-                DBG("creating mapping for region: %lx..%lx (prot: %x)\n",
+                DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
                     base, size, prot);
 
 #ifdef CONFIG_U3_DART
@@ -879,7 +879,7 @@ static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
  */
 int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
 {
-        void *pgdir;
+        pgd_t *pgdir;
         unsigned long vsid;
         struct mm_struct *mm;
         pte_t *ptep;
@@ -1025,7 +1025,7 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
         else
 #endif /* CONFIG_PPC_HAS_HASH_64K */
         {
-                int spp = subpage_protection(pgdir, ea);
+                int spp = subpage_protection(mm, ea);
                 if (access & spp)
                         rc = -2;
                 else
@@ -1115,7 +1115,7 @@ void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize,
 {
         unsigned long hash, index, shift, hidx, slot;
 
-        DBG_LOW("flush_hash_page(va=%016x)\n", va);
+        DBG_LOW("flush_hash_page(va=%016lx)\n", va);
         pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
                 hash = hpt_hash(va, shift, ssize);
                 hidx = __rpte_to_hidx(pte, index);
@@ -1123,7 +1123,7 @@ void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize,
                         hash = ~hash;
                 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
                 slot += hidx & _PTEIDX_GROUP_IX;
-                DBG_LOW(" sub %d: hash=%x, hidx=%x\n", index, slot, hidx);
+                DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx);
                 ppc_md.hpte_invalidate(slot, va, psize, ssize, local);
         } pte_iterate_hashed_end();
 }
diff --git a/arch/powerpc/mm/mmu_context_nohash.c b/arch/powerpc/mm/mmu_context_nohash.c
index be4f34c30a0b..1044a634b6d0 100644
--- a/arch/powerpc/mm/mmu_context_nohash.c
+++ b/arch/powerpc/mm/mmu_context_nohash.c
@@ -353,7 +353,7 @@ static int __cpuinit mmu_context_cpu_notify(struct notifier_block *self,
                 read_lock(&tasklist_lock);
                 for_each_process(p) {
                         if (p->mm)
-                                cpu_mask_clear_cpu(cpu, mm_cpumask(p->mm));
+                                cpumask_clear_cpu(cpu, mm_cpumask(p->mm));
                 }
                 read_unlock(&tasklist_lock);
         break;
diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c
index 177e4038b43c..573b3bd1c45b 100644
--- a/arch/powerpc/mm/pgtable_32.c
+++ b/arch/powerpc/mm/pgtable_32.c
@@ -382,7 +382,7 @@ static int __change_page_attr(struct page *page, pgprot_t prot)
                 return 0;
         if (!get_pteptr(&init_mm, address, &kpte, &kpmd))
                 return -EINVAL;
-        set_pte_at(&init_mm, address, kpte, mk_pte(page, prot));
+        __set_pte_at(&init_mm, address, kpte, mk_pte(page, prot), 0);
         wmb();
 #ifdef CONFIG_PPC_STD_MMU
         flush_hash_pages(0, address, pmd_val(*kpmd), 1);
diff --git a/arch/powerpc/platforms/52xx/efika.c b/arch/powerpc/platforms/52xx/efika.c
index bcc69e1f77c1..45c0cb9b67e6 100644
--- a/arch/powerpc/platforms/52xx/efika.c
+++ b/arch/powerpc/platforms/52xx/efika.c
@@ -10,7 +10,7 @@
  */
 
 #include <linux/init.h>
-#include <linux/utsrelease.h>
+#include <generated/utsrelease.h>
 #include <linux/pci.h>
 #include <linux/of.h>
 #include <asm/prom.h>
diff --git a/arch/powerpc/platforms/83xx/suspend.c b/arch/powerpc/platforms/83xx/suspend.c
index d306f07b9aa1..43805348b81e 100644
--- a/arch/powerpc/platforms/83xx/suspend.c
+++ b/arch/powerpc/platforms/83xx/suspend.c
@@ -32,6 +32,7 @@
 #define PMCCR1_NEXT_STATE       0x0C /* Next state for power management */
 #define PMCCR1_NEXT_STATE_SHIFT 2
 #define PMCCR1_CURR_STATE       0x03 /* Current state for power management*/
+#define IMMR_SYSCR_OFFSET       0x100
 #define IMMR_RCW_OFFSET         0x900
 #define RCW_PCI_HOST            0x80000000
 
@@ -78,6 +79,22 @@ struct mpc83xx_clock {
         u32 sccr;
 };
 
+struct mpc83xx_syscr {
+        __be32 sgprl;
+        __be32 sgprh;
+        __be32 spridr;
+        __be32 :32;
+        __be32 spcr;
+        __be32 sicrl;
+        __be32 sicrh;
+};
+
+struct mpc83xx_saved {
+        u32 sicrl;
+        u32 sicrh;
+        u32 sccr;
+};
+
 struct pmc_type {
         int has_deep_sleep;
 };
@@ -87,6 +104,8 @@ static int has_deep_sleep, deep_sleeping;
 static int pmc_irq;
 static struct mpc83xx_pmc __iomem *pmc_regs;
 static struct mpc83xx_clock __iomem *clock_regs;
+static struct mpc83xx_syscr __iomem *syscr_regs;
+static struct mpc83xx_saved saved_regs;
 static int is_pci_agent, wake_from_pci;
 static phys_addr_t immrbase;
 static int pci_pm_state;
@@ -137,6 +156,20 @@ static irqreturn_t pmc_irq_handler(int irq, void *dev_id)
         return ret;
 }
 
+static void mpc83xx_suspend_restore_regs(void)
+{
+        out_be32(&syscr_regs->sicrl, saved_regs.sicrl);
+        out_be32(&syscr_regs->sicrh, saved_regs.sicrh);
+        out_be32(&clock_regs->sccr, saved_regs.sccr);
+}
+
+static void mpc83xx_suspend_save_regs(void)
+{
+        saved_regs.sicrl = in_be32(&syscr_regs->sicrl);
+        saved_regs.sicrh = in_be32(&syscr_regs->sicrh);
+        saved_regs.sccr = in_be32(&clock_regs->sccr);
+}
+
 static int mpc83xx_suspend_enter(suspend_state_t state)
 {
         int ret = -EAGAIN;
@@ -166,6 +199,8 @@ static int mpc83xx_suspend_enter(suspend_state_t state)
          */
 
         if (deep_sleeping) {
+                mpc83xx_suspend_save_regs();
+
                 out_be32(&pmc_regs->mask, PMCER_ALL);
 
                 out_be32(&pmc_regs->config1,
@@ -179,6 +214,8 @@ static int mpc83xx_suspend_enter(suspend_state_t state)
                          in_be32(&pmc_regs->config1) & ~PMCCR1_POWER_OFF);
 
                 out_be32(&pmc_regs->mask, PMCER_PMCI);
+
+                mpc83xx_suspend_restore_regs();
         } else {
                 out_be32(&pmc_regs->mask, PMCER_PMCI);
 
@@ -194,7 +231,7 @@ out:
         return ret;
 }
 
-static void mpc83xx_suspend_finish(void)
+static void mpc83xx_suspend_end(void)
 {
         deep_sleeping = 0;
 }
@@ -278,7 +315,7 @@ static struct platform_suspend_ops mpc83xx_suspend_ops = {
         .valid = mpc83xx_suspend_valid,
         .begin = mpc83xx_suspend_begin,
         .enter = mpc83xx_suspend_enter,
-        .finish = mpc83xx_suspend_finish,
+        .end = mpc83xx_suspend_end,
 };
 
 static int pmc_probe(struct of_device *ofdev,
@@ -333,12 +370,23 @@ static int pmc_probe(struct of_device *ofdev,
                 goto out_pmc;
         }
 
+        if (has_deep_sleep) {
+                syscr_regs = ioremap(immrbase + IMMR_SYSCR_OFFSET,
+                                     sizeof(*syscr_regs));
+                if (!syscr_regs) {
+                        ret = -ENOMEM;
+                        goto out_syscr;
+                }
+        }
+
         if (is_pci_agent)
                 mpc83xx_set_agent();
 
         suspend_set_ops(&mpc83xx_suspend_ops);
         return 0;
 
+out_syscr:
+        iounmap(clock_regs);
 out_pmc:
         iounmap(pmc_regs);
 out:
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index c5028a2e5a58..21f61b8c445b 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -86,7 +86,7 @@ static int mpc8568_fixup_125_clock(struct phy_device *phydev)
         scr = phy_read(phydev, MV88E1111_SCR);
 
         if (scr < 0)
-                return err;
+                return scr;
 
         err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008);
 
diff --git a/arch/powerpc/platforms/amigaone/setup.c b/arch/powerpc/platforms/amigaone/setup.c
index 9290a7a442d0..fb4eb0df054c 100644
--- a/arch/powerpc/platforms/amigaone/setup.c
+++ b/arch/powerpc/platforms/amigaone/setup.c
@@ -14,7 +14,7 @@
 
 #include <linux/kernel.h>
 #include <linux/seq_file.h>
-#include <linux/utsrelease.h>
+#include <generated/utsrelease.h>
 
 #include <asm/machdep.h>
 #include <asm/cputable.h>
diff --git a/arch/powerpc/platforms/cell/spufs/Makefile b/arch/powerpc/platforms/cell/spufs/Makefile
index b93f877ba504..b9d5d678aa44 100644
--- a/arch/powerpc/platforms/cell/spufs/Makefile
+++ b/arch/powerpc/platforms/cell/spufs/Makefile
@@ -13,10 +13,8 @@ SPU_CC		:= $(SPU_CROSS)gcc
 SPU_AS          := $(SPU_CROSS)gcc
 SPU_LD          := $(SPU_CROSS)ld
 SPU_OBJCOPY     := $(SPU_CROSS)objcopy
-SPU_CFLAGS      := -O2 -Wall -I$(srctree)/include \
-                   -I$(objtree)/include2 -D__KERNEL__
-SPU_AFLAGS      := -c -D__ASSEMBLY__ -I$(srctree)/include \
-                   -I$(objtree)/include2 -D__KERNEL__
+SPU_CFLAGS      := -O2 -Wall -I$(srctree)/include -D__KERNEL__
+SPU_AFLAGS      := -c -D__ASSEMBLY__ -I$(srctree)/include -D__KERNEL__
 SPU_LDFLAGS     := -N -Ttext=0x0
 
 $(obj)/switch.o: $(obj)/spu_save_dump.h $(obj)/spu_restore_dump.h
diff --git a/arch/powerpc/platforms/chrp/setup.c b/arch/powerpc/platforms/chrp/setup.c
index 52f3df3b4ca0..8f41685d8f42 100644
--- a/arch/powerpc/platforms/chrp/setup.c
+++ b/arch/powerpc/platforms/chrp/setup.c
@@ -23,7 +23,7 @@
 #include <linux/reboot.h>
 #include <linux/init.h>
 #include <linux/pci.h>
-#include <linux/utsrelease.h>
+#include <generated/utsrelease.h>
 #include <linux/adb.h>
 #include <linux/module.h>
 #include <linux/delay.h>
diff --git a/arch/powerpc/platforms/embedded6xx/flipper-pic.c b/arch/powerpc/platforms/embedded6xx/flipper-pic.c
index d5963285e3be..c278bd3a8fec 100644
--- a/arch/powerpc/platforms/embedded6xx/flipper-pic.c
+++ b/arch/powerpc/platforms/embedded6xx/flipper-pic.c
@@ -102,7 +102,7 @@ static int flipper_pic_map(struct irq_host *h, unsigned int virq,
                            irq_hw_number_t hwirq)
 {
         set_irq_chip_data(virq, h->host_data);
-        get_irq_desc(virq)->status |= IRQ_LEVEL;
+        irq_to_desc(virq)->status |= IRQ_LEVEL;
         set_irq_chip_and_handler(virq, &flipper_pic, handle_level_irq);
         return 0;
 }
diff --git a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c
index dd20bff33207..a771f91e215b 100644
--- a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c
+++ b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c
@@ -95,7 +95,7 @@ static int hlwd_pic_map(struct irq_host *h, unsigned int virq,
                            irq_hw_number_t hwirq)
 {
         set_irq_chip_data(virq, h->host_data);
-        get_irq_desc(virq)->status |= IRQ_LEVEL;
+        irq_to_desc(virq)->status |= IRQ_LEVEL;
         set_irq_chip_and_handler(virq, &hlwd_pic, handle_level_irq);
         return 0;
 }
@@ -132,9 +132,9 @@ static void hlwd_pic_irq_cascade(unsigned int cascade_virq,
         struct irq_host *irq_host = get_irq_data(cascade_virq);
         unsigned int virq;
 
-        spin_lock(&desc->lock);
+        raw_spin_lock(&desc->lock);
         desc->chip->mask(cascade_virq); /* IRQ_LEVEL */
-        spin_unlock(&desc->lock);
+        raw_spin_unlock(&desc->lock);
 
         virq = __hlwd_pic_get_irq(irq_host);
         if (virq != NO_IRQ)
@@ -142,11 +142,11 @@ static void hlwd_pic_irq_cascade(unsigned int cascade_virq,
         else
                 pr_err("spurious interrupt!\n");
 
-        spin_lock(&desc->lock);
+        raw_spin_lock(&desc->lock);
         desc->chip->ack(cascade_virq); /* IRQ_LEVEL */
         if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask)
                 desc->chip->unmask(cascade_virq);
-        spin_unlock(&desc->lock);
+        raw_spin_unlock(&desc->lock);
 }
 
 /*
diff --git a/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c b/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c
index edc956cc8b13..20a8ed91962e 100644
--- a/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c
+++ b/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c
@@ -120,7 +120,7 @@ static void ug_putc(char ch)
 
         while (!ug_is_txfifo_ready() && count--)
                 barrier();
-        if (count)
+        if (count >= 0)
                 ug_raw_putc(ch);
 }
 
diff --git a/arch/powerpc/platforms/iseries/mf.c b/arch/powerpc/platforms/iseries/mf.c
index 0d9343df35bc..6617915bcb1a 100644
--- a/arch/powerpc/platforms/iseries/mf.c
+++ b/arch/powerpc/platforms/iseries/mf.c
@@ -855,59 +855,58 @@ static int mf_get_boot_rtc(struct rtc_time *tm)
 }
 
 #ifdef CONFIG_PROC_FS
-
-static int proc_mf_dump_cmdline(char *page, char **start, off_t off,
-                int count, int *eof, void *data)
+static int mf_cmdline_proc_show(struct seq_file *m, void *v)
 {
-        int len;
-        char *p;
+        char *page, *p;
         struct vsp_cmd_data vsp_cmd;
         int rc;
         dma_addr_t dma_addr;
 
         /* The HV appears to return no more than 256 bytes of command line */
-        if (off >= 256)
-                return 0;
-        if ((off + count) > 256)
-                count = 256 - off;
+        page = kmalloc(256, GFP_KERNEL);
+        if (!page)
+                return -ENOMEM;
 
-        dma_addr = iseries_hv_map(page, off + count, DMA_FROM_DEVICE);
-        if (dma_addr == DMA_ERROR_CODE)
+        dma_addr = iseries_hv_map(page, 256, DMA_FROM_DEVICE);
+        if (dma_addr == DMA_ERROR_CODE) {
+                kfree(page);
                 return -ENOMEM;
-        memset(page, 0, off + count);
+        }
+        memset(page, 0, 256);
         memset(&vsp_cmd, 0, sizeof(vsp_cmd));
         vsp_cmd.cmd = 33;
         vsp_cmd.sub_data.kern.token = dma_addr;
         vsp_cmd.sub_data.kern.address_type = HvLpDma_AddressType_TceIndex;
-        vsp_cmd.sub_data.kern.side = (u64)data;
-        vsp_cmd.sub_data.kern.length = off + count;
+        vsp_cmd.sub_data.kern.side = (u64)m->private;
+        vsp_cmd.sub_data.kern.length = 256;
         mb();
         rc = signal_vsp_instruction(&vsp_cmd);
-        iseries_hv_unmap(dma_addr, off + count, DMA_FROM_DEVICE);
-        if (rc)
+        iseries_hv_unmap(dma_addr, 256, DMA_FROM_DEVICE);
+        if (rc) {
+                kfree(page);
                 return rc;
-        if (vsp_cmd.result_code != 0)
+        }
+        if (vsp_cmd.result_code != 0) {
+                kfree(page);
                 return -ENOMEM;
+        }
         p = page;
-        len = 0;
-        while (len < (off + count)) {
-                if ((*p == '\0') || (*p == '\n')) {
-                        if (*p == '\0')
-                                *p = '\n';
-                        p++;
-                        len++;
-                        *eof = 1;
+        while (p - page < 256) {
+                if (*p == '\0' || *p == '\n') {
+                        *p = '\n';
                         break;
                 }
                 p++;
-                len++;
-        }
 
-        if (len < off) {
-                *eof = 1;
-                len = 0;
         }
-        return len;
+        seq_write(m, page, p - page);
+        kfree(page);
+        return 0;
+}
+
+static int mf_cmdline_proc_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, mf_cmdline_proc_show, PDE(inode)->data);
 }
 
 #if 0
@@ -962,10 +961,8 @@ static int proc_mf_dump_vmlinux(char *page, char **start, off_t off,
 }
 #endif
 
-static int proc_mf_dump_side(char *page, char **start, off_t off,
-                int count, int *eof, void *data)
+static int mf_side_proc_show(struct seq_file *m, void *v)
 {
-        int len;
         char mf_current_side = ' ';
         struct vsp_cmd_data vsp_cmd;
 
@@ -989,21 +986,17 @@ static int proc_mf_dump_side(char *page, char **start, off_t off,
                 }
         }
 
-        len = sprintf(page, "%c\n", mf_current_side);
+        seq_printf(m, "%c\n", mf_current_side);
+        return 0;
+}
 
-        if (len <= (off + count))
-                *eof = 1;
-        *start = page + off;
-        len -= off;
-        if (len > count)
-                len = count;
-        if (len < 0)
-                len = 0;
-        return len;
+static int mf_side_proc_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, mf_side_proc_show, NULL);
 }
 
-static int proc_mf_change_side(struct file *file, const char __user *buffer,
-                unsigned long count, void *data)
+static ssize_t mf_side_proc_write(struct file *file, const char __user *buffer,
+                                  size_t count, loff_t *pos)
 {
         char side;
         u64 newSide;
@@ -1041,6 +1034,15 @@ static int proc_mf_change_side(struct file *file, const char __user *buffer,
         return count;
 }
 
+static const struct file_operations mf_side_proc_fops = {
+        .owner          = THIS_MODULE,
+        .open           = mf_side_proc_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+        .write          = mf_side_proc_write,
+};
+
 #if 0
 static void mf_getSrcHistory(char *buffer, int size)
 {
@@ -1087,8 +1089,7 @@ static void mf_getSrcHistory(char *buffer, int size)
 }
 #endif
 
-static int proc_mf_dump_src(char *page, char **start, off_t off,
-                int count, int *eof, void *data)
+static int mf_src_proc_show(struct seq_file *m, void *v)
 {
 #if 0
         int len;
@@ -1109,8 +1110,13 @@ static int proc_mf_dump_src(char *page, char **start, off_t off,
 #endif
 }
 
-static int proc_mf_change_src(struct file *file, const char __user *buffer,
-                unsigned long count, void *data)
+static int mf_src_proc_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, mf_src_proc_show, NULL);
+}
+
+static ssize_t mf_src_proc_write(struct file *file, const char __user *buffer,
+                                 size_t count, loff_t *pos)
 {
         char stkbuf[10];
 
@@ -1135,9 +1141,19 @@ static int proc_mf_change_src(struct file *file, const char __user *buffer,
         return count;
 }
 
-static int proc_mf_change_cmdline(struct file *file, const char __user *buffer,
-                unsigned long count, void *data)
+static const struct file_operations mf_src_proc_fops = {
+        .owner          = THIS_MODULE,
+        .open           = mf_src_proc_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+        .write          = mf_src_proc_write,
+};
+
+static ssize_t mf_cmdline_proc_write(struct file *file, const char __user *buffer,
+                                     size_t count, loff_t *pos)
 {
+        void *data = PDE(file->f_path.dentry->d_inode)->data;
         struct vsp_cmd_data vsp_cmd;
         dma_addr_t dma_addr;
         char *page;
@@ -1172,6 +1188,15 @@ out:
         return ret;
 }
 
+static const struct file_operations mf_cmdline_proc_fops = {
+        .owner          = THIS_MODULE,
+        .open           = mf_cmdline_proc_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+        .write          = mf_cmdline_proc_write,
+};
+
 static ssize_t proc_mf_change_vmlinux(struct file *file,
                                       const char __user *buf,
                                       size_t count, loff_t *ppos)
@@ -1246,12 +1271,10 @@ static int __init mf_proc_init(void)
                 if (!mf)
                         return 1;
 
-                ent = create_proc_entry("cmdline", S_IFREG|S_IRUSR|S_IWUSR, mf);
+                ent = proc_create_data("cmdline", S_IRUSR|S_IWUSR, mf,
+                                       &mf_cmdline_proc_fops, (void *)(long)i);
                 if (!ent)
                         return 1;
-                ent->data = (void *)(long)i;
-                ent->read_proc = proc_mf_dump_cmdline;
-                ent->write_proc = proc_mf_change_cmdline;
 
                 if (i == 3)     /* no vmlinux entry for 'D' */
                         continue;
@@ -1263,19 +1286,15 @@ static int __init mf_proc_init(void)
                         return 1;
         }
 
-        ent = create_proc_entry("side", S_IFREG|S_IRUSR|S_IWUSR, mf_proc_root);
+        ent = proc_create("side", S_IFREG|S_IRUSR|S_IWUSR, mf_proc_root,
+                          &mf_side_proc_fops);
         if (!ent)
                 return 1;
-        ent->data = (void *)0;
-        ent->read_proc = proc_mf_dump_side;
-        ent->write_proc = proc_mf_change_side;
 
-        ent = create_proc_entry("src", S_IFREG|S_IRUSR|S_IWUSR, mf_proc_root);
+        ent = proc_create("src", S_IFREG|S_IRUSR|S_IWUSR, mf_proc_root,
+                          &mf_src_proc_fops);
         if (!ent)
                 return 1;
-        ent->data = (void *)0;
-        ent->read_proc = proc_mf_dump_src;
-        ent->write_proc = proc_mf_change_src;
 
         return 0;
 }
diff --git a/arch/powerpc/platforms/iseries/viopath.c b/arch/powerpc/platforms/iseries/viopath.c
index 49ff4dc422b7..5aea94f30836 100644
--- a/arch/powerpc/platforms/iseries/viopath.c
+++ b/arch/powerpc/platforms/iseries/viopath.c
@@ -116,7 +116,7 @@ static int proc_viopath_show(struct seq_file *m, void *v)
         u16 vlanMap;
         dma_addr_t handle;
         HvLpEvent_Rc hvrc;
-        DECLARE_COMPLETION(done);
+        DECLARE_COMPLETION_ONSTACK(done);
         struct device_node *node;
         const char *sysid;
 
diff --git a/arch/powerpc/platforms/powermac/bootx_init.c b/arch/powerpc/platforms/powermac/bootx_init.c
index cf660916ae0b..9dd789a7370d 100644
--- a/arch/powerpc/platforms/powermac/bootx_init.c
+++ b/arch/powerpc/platforms/powermac/bootx_init.c
@@ -12,7 +12,7 @@
 #include <linux/kernel.h>
 #include <linux/string.h>
 #include <linux/init.h>
-#include <linux/utsrelease.h>
+#include <generated/utsrelease.h>
 #include <asm/sections.h>
 #include <asm/prom.h>
 #include <asm/page.h>
diff --git a/arch/powerpc/platforms/pseries/Kconfig b/arch/powerpc/platforms/pseries/Kconfig
index 27554c807fd5..c667f0f02c34 100644
--- a/arch/powerpc/platforms/pseries/Kconfig
+++ b/arch/powerpc/platforms/pseries/Kconfig
@@ -2,6 +2,8 @@ config PPC_PSERIES
         depends on PPC64 && PPC_BOOK3S
         bool "IBM pSeries & new (POWER5-based) iSeries"
         select MPIC
+        select PCI_MSI
+        select XICS
         select PPC_I8259
         select PPC_RTAS
         select PPC_RTAS_DAEMON
diff --git a/arch/powerpc/platforms/pseries/cmm.c b/arch/powerpc/platforms/pseries/cmm.c
index bcdcf0ccc8d7..a277f2e28dbc 100644
--- a/arch/powerpc/platforms/pseries/cmm.c
+++ b/arch/powerpc/platforms/pseries/cmm.c
@@ -38,19 +38,28 @@
 #include <asm/mmu.h>
 #include <asm/pgalloc.h>
 #include <asm/uaccess.h>
+#include <linux/memory.h>
 
 #include "plpar_wrappers.h"
 
 #define CMM_DRIVER_VERSION      "1.0.0"
 #define CMM_DEFAULT_DELAY       1
+#define CMM_HOTPLUG_DELAY       5
 #define CMM_DEBUG                       0
 #define CMM_DISABLE             0
 #define CMM_OOM_KB              1024
 #define CMM_MIN_MEM_MB          256
 #define KB2PAGES(_p)            ((_p)>>(PAGE_SHIFT-10))
 #define PAGES2KB(_p)            ((_p)<<(PAGE_SHIFT-10))
+/*
+ * The priority level tries to ensure that this notifier is called as
+ * late as possible to reduce thrashing in the shared memory pool.
+ */
+#define CMM_MEM_HOTPLUG_PRI     1
+#define CMM_MEM_ISOLATE_PRI     15
 
 static unsigned int delay = CMM_DEFAULT_DELAY;
+static unsigned int hotplug_delay = CMM_HOTPLUG_DELAY;
 static unsigned int oom_kb = CMM_OOM_KB;
 static unsigned int cmm_debug = CMM_DEBUG;
 static unsigned int cmm_disabled = CMM_DISABLE;
@@ -65,6 +74,10 @@ MODULE_VERSION(CMM_DRIVER_VERSION);
 module_param_named(delay, delay, uint, S_IRUGO | S_IWUSR);
 MODULE_PARM_DESC(delay, "Delay (in seconds) between polls to query hypervisor paging requests. "
                  "[Default=" __stringify(CMM_DEFAULT_DELAY) "]");
+module_param_named(hotplug_delay, hotplug_delay, uint, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(delay, "Delay (in seconds) after memory hotplug remove "
+                 "before loaning resumes. "
+                 "[Default=" __stringify(CMM_HOTPLUG_DELAY) "]");
 module_param_named(oom_kb, oom_kb, uint, S_IRUGO | S_IWUSR);
 MODULE_PARM_DESC(oom_kb, "Amount of memory in kb to free on OOM. "
                  "[Default=" __stringify(CMM_OOM_KB) "]");
@@ -92,6 +105,9 @@ static unsigned long oom_freed_pages;
 static struct cmm_page_array *cmm_page_list;
 static DEFINE_SPINLOCK(cmm_lock);
 
+static DEFINE_MUTEX(hotplug_mutex);
+static int hotplug_occurred; /* protected by the hotplug mutex */
+
 static struct task_struct *cmm_thread_ptr;
 
 /**
@@ -110,6 +126,17 @@ static long cmm_alloc_pages(long nr)
         cmm_dbg("Begin request for %ld pages\n", nr);
 
         while (nr) {
+                /* Exit if a hotplug operation is in progress or occurred */
+                if (mutex_trylock(&hotplug_mutex)) {
+                        if (hotplug_occurred) {
+                                mutex_unlock(&hotplug_mutex);
+                                break;
+                        }
+                        mutex_unlock(&hotplug_mutex);
+                } else {
+                        break;
+                }
+
                 addr = __get_free_page(GFP_NOIO | __GFP_NOWARN |
                                        __GFP_NORETRY | __GFP_NOMEMALLOC);
                 if (!addr)
@@ -119,8 +146,9 @@ static long cmm_alloc_pages(long nr)
                 if (!pa || pa->index >= CMM_NR_PAGES) {
                         /* Need a new page for the page list. */
                         spin_unlock(&cmm_lock);
-                        npa = (struct cmm_page_array *)__get_free_page(GFP_NOIO | __GFP_NOWARN |
-                                                                       __GFP_NORETRY | __GFP_NOMEMALLOC);
+                        npa = (struct cmm_page_array *)__get_free_page(
+                                        GFP_NOIO | __GFP_NOWARN |
+                                        __GFP_NORETRY | __GFP_NOMEMALLOC);
                         if (!npa) {
                                 pr_info("%s: Can not allocate new page list\n", __func__);
                                 free_page(addr);
@@ -282,9 +310,28 @@ static int cmm_thread(void *dummy)
         while (1) {
                 timeleft = msleep_interruptible(delay * 1000);
 
-                if (kthread_should_stop() || timeleft) {
-                        loaned_pages_target = loaned_pages;
+                if (kthread_should_stop() || timeleft)
                         break;
+
+                if (mutex_trylock(&hotplug_mutex)) {
+                        if (hotplug_occurred) {
+                                hotplug_occurred = 0;
+                                mutex_unlock(&hotplug_mutex);
+                                cmm_dbg("Hotplug operation has occurred, "
+                                                "loaning activity suspended "
+                                                "for %d seconds.\n",
+                                                hotplug_delay);
+                                timeleft = msleep_interruptible(hotplug_delay *
+                                                1000);
+                                if (kthread_should_stop() || timeleft)
+                                        break;
+                                continue;
+                        }
+                        mutex_unlock(&hotplug_mutex);
+                } else {
+                        cmm_dbg("Hotplug operation in progress, activity "
+                                        "suspended\n");
+                        continue;
                 }
 
                 cmm_get_mpp();
@@ -414,6 +461,193 @@ static struct notifier_block cmm_reboot_nb = {
 };
 
 /**
+ * cmm_count_pages - Count the number of pages loaned in a particular range.
+ *
+ * @arg: memory_isolate_notify structure with address range and count
+ *
+ * Return value:
+ *      0 on success
+ **/
+static unsigned long cmm_count_pages(void *arg)
+{
+        struct memory_isolate_notify *marg = arg;
+        struct cmm_page_array *pa;
+        unsigned long start = (unsigned long)pfn_to_kaddr(marg->start_pfn);
+        unsigned long end = start + (marg->nr_pages << PAGE_SHIFT);
+        unsigned long idx;
+
+        spin_lock(&cmm_lock);
+        pa = cmm_page_list;
+        while (pa) {
+                if ((unsigned long)pa >= start && (unsigned long)pa < end)
+                        marg->pages_found++;
+                for (idx = 0; idx < pa->index; idx++)
+                        if (pa->page[idx] >= start && pa->page[idx] < end)
+                                marg->pages_found++;
+                pa = pa->next;
+        }
+        spin_unlock(&cmm_lock);
+        return 0;
+}
+
+/**
+ * cmm_memory_isolate_cb - Handle memory isolation notifier calls
+ * @self:       notifier block struct
+ * @action:     action to take
+ * @arg:        struct memory_isolate_notify data for handler
+ *
+ * Return value:
+ *      NOTIFY_OK or notifier error based on subfunction return value
+ **/
+static int cmm_memory_isolate_cb(struct notifier_block *self,
+                                 unsigned long action, void *arg)
+{
+        int ret = 0;
+
+        if (action == MEM_ISOLATE_COUNT)
+                ret = cmm_count_pages(arg);
+
+        if (ret)
+                ret = notifier_from_errno(ret);
+        else
+                ret = NOTIFY_OK;
+
+        return ret;
+}
+
+static struct notifier_block cmm_mem_isolate_nb = {
+        .notifier_call = cmm_memory_isolate_cb,
+        .priority = CMM_MEM_ISOLATE_PRI
+};
+
+/**
+ * cmm_mem_going_offline - Unloan pages where memory is to be removed
+ * @arg: memory_notify structure with page range to be offlined
+ *
+ * Return value:
+ *      0 on success
+ **/
+static int cmm_mem_going_offline(void *arg)
+{
+        struct memory_notify *marg = arg;
+        unsigned long start_page = (unsigned long)pfn_to_kaddr(marg->start_pfn);
+        unsigned long end_page = start_page + (marg->nr_pages << PAGE_SHIFT);
+        struct cmm_page_array *pa_curr, *pa_last, *npa;
+        unsigned long idx;
+        unsigned long freed = 0;
+
+        cmm_dbg("Memory going offline, searching 0x%lx (%ld pages).\n",
+                        start_page, marg->nr_pages);
+        spin_lock(&cmm_lock);
+
+        /* Search the page list for pages in the range to be offlined */
+        pa_last = pa_curr = cmm_page_list;
+        while (pa_curr) {
+                for (idx = (pa_curr->index - 1); (idx + 1) > 0; idx--) {
+                        if ((pa_curr->page[idx] < start_page) ||
+                            (pa_curr->page[idx] >= end_page))
+                                continue;
+
+                        plpar_page_set_active(__pa(pa_curr->page[idx]));
+                        free_page(pa_curr->page[idx]);
+                        freed++;
+                        loaned_pages--;
+                        totalram_pages++;
+                        pa_curr->page[idx] = pa_last->page[--pa_last->index];
+                        if (pa_last->index == 0) {
+                                if (pa_curr == pa_last)
+                                        pa_curr = pa_last->next;
+                                pa_last = pa_last->next;
+                                free_page((unsigned long)cmm_page_list);
+                                cmm_page_list = pa_last;
+                                continue;
+                        }
+                }
+                pa_curr = pa_curr->next;
+        }
+
+        /* Search for page list structures in the range to be offlined */
+        pa_last = NULL;
+        pa_curr = cmm_page_list;
+        while (pa_curr) {
+                if (((unsigned long)pa_curr >= start_page) &&
+                                ((unsigned long)pa_curr < end_page)) {
+                        npa = (struct cmm_page_array *)__get_free_page(
+                                        GFP_NOIO | __GFP_NOWARN |
+                                        __GFP_NORETRY | __GFP_NOMEMALLOC);
+                        if (!npa) {
+                                spin_unlock(&cmm_lock);
+                                cmm_dbg("Failed to allocate memory for list "
+                                                "management. Memory hotplug "
+                                                "failed.\n");
+                                return ENOMEM;
+                        }
+                        memcpy(npa, pa_curr, PAGE_SIZE);
+                        if (pa_curr == cmm_page_list)
+                                cmm_page_list = npa;
+                        if (pa_last)
+                                pa_last->next = npa;
+                        free_page((unsigned long) pa_curr);
+                        freed++;
+                        pa_curr = npa;
+                }
+
+                pa_last = pa_curr;
+                pa_curr = pa_curr->next;
+        }
+
+        spin_unlock(&cmm_lock);
+        cmm_dbg("Released %ld pages in the search range.\n", freed);
+
+        return 0;
+}
+
+/**
+ * cmm_memory_cb - Handle memory hotplug notifier calls
+ * @self:       notifier block struct
+ * @action:     action to take
+ * @arg:        struct memory_notify data for handler
+ *
+ * Return value:
+ *      NOTIFY_OK or notifier error based on subfunction return value
+ *
+ **/
+static int cmm_memory_cb(struct notifier_block *self,
+                        unsigned long action, void *arg)
+{
+        int ret = 0;
+
+        switch (action) {
+        case MEM_GOING_OFFLINE:
+                mutex_lock(&hotplug_mutex);
+                hotplug_occurred = 1;
+                ret = cmm_mem_going_offline(arg);
+                break;
+        case MEM_OFFLINE:
+        case MEM_CANCEL_OFFLINE:
+                mutex_unlock(&hotplug_mutex);
+                cmm_dbg("Memory offline operation complete.\n");
+                break;
+        case MEM_GOING_ONLINE:
+        case MEM_ONLINE:
+        case MEM_CANCEL_ONLINE:
+                break;
+        }
+
+        if (ret)
+                ret = notifier_from_errno(ret);
+        else
+                ret = NOTIFY_OK;
+
+        return ret;
+}
+
+static struct notifier_block cmm_mem_nb = {
+        .notifier_call = cmm_memory_cb,
+        .priority = CMM_MEM_HOTPLUG_PRI
+};
+
+/**
  * cmm_init - Module initialization
  *
  * Return value:
@@ -435,18 +669,24 @@ static int cmm_init(void)
         if ((rc = cmm_sysfs_register(&cmm_sysdev)))
                 goto out_reboot_notifier;
 
+        if (register_memory_notifier(&cmm_mem_nb) ||
+            register_memory_isolate_notifier(&cmm_mem_isolate_nb))
+                goto out_unregister_notifier;
+
         if (cmm_disabled)
                 return rc;
 
         cmm_thread_ptr = kthread_run(cmm_thread, NULL, "cmmthread");
         if (IS_ERR(cmm_thread_ptr)) {
                 rc = PTR_ERR(cmm_thread_ptr);
-                goto out_unregister_sysfs;
+                goto out_unregister_notifier;
         }
 
         return rc;
 
-out_unregister_sysfs:
+out_unregister_notifier:
+        unregister_memory_notifier(&cmm_mem_nb);
+        unregister_memory_isolate_notifier(&cmm_mem_isolate_nb);
         cmm_unregister_sysfs(&cmm_sysdev);
 out_reboot_notifier:
         unregister_reboot_notifier(&cmm_reboot_nb);
@@ -467,6 +707,8 @@ static void cmm_exit(void)
                 kthread_stop(cmm_thread_ptr);
         unregister_oom_notifier(&cmm_oom_nb);
         unregister_reboot_notifier(&cmm_reboot_nb);
+        unregister_memory_notifier(&cmm_mem_nb);
+        unregister_memory_isolate_notifier(&cmm_mem_isolate_nb);
         cmm_free_pages(loaned_pages);
         cmm_unregister_sysfs(&cmm_sysdev);
 }
diff --git a/arch/powerpc/platforms/pseries/dlpar.c b/arch/powerpc/platforms/pseries/dlpar.c
index 12df9e8812a9..67b7a10f9fce 100644
--- a/arch/powerpc/platforms/pseries/dlpar.c
+++ b/arch/powerpc/platforms/pseries/dlpar.c
@@ -346,12 +346,14 @@ int dlpar_release_drc(u32 drc_index)
 
 static DEFINE_MUTEX(pseries_cpu_hotplug_mutex);
 
-void cpu_hotplug_driver_lock()
+void cpu_hotplug_driver_lock(void)
+__acquires(pseries_cpu_hotplug_mutex)
 {
         mutex_lock(&pseries_cpu_hotplug_mutex);
 }
 
-void cpu_hotplug_driver_unlock()
+void cpu_hotplug_driver_unlock(void)
+__releases(pseries_cpu_hotplug_mutex)
 {
         mutex_unlock(&pseries_cpu_hotplug_mutex);
 }
diff --git a/arch/powerpc/platforms/pseries/smp.c b/arch/powerpc/platforms/pseries/smp.c
index 8868c012268a..b4886635972c 100644
--- a/arch/powerpc/platforms/pseries/smp.c
+++ b/arch/powerpc/platforms/pseries/smp.c
@@ -144,8 +144,8 @@ static void __devinit smp_pSeries_kick_cpu(int nr)
                 hcpuid = get_hard_smp_processor_id(nr);
                 rc = plpar_hcall_norets(H_PROD, hcpuid);
                 if (rc != H_SUCCESS)
-                        panic("Error: Prod to wake up processor %d Ret= %ld\n",
-                                nr, rc);
+                        printk(KERN_ERR "Error: Prod to wake up processor %d\
+                                                Ret= %ld\n", nr, rc);
         }
 }
 
diff --git a/arch/powerpc/sysdev/cpm2_pic.c b/arch/powerpc/sysdev/cpm2_pic.c
index 971483f0dfac..1709ac5aac7c 100644
--- a/arch/powerpc/sysdev/cpm2_pic.c
+++ b/arch/powerpc/sysdev/cpm2_pic.c
@@ -143,13 +143,23 @@ static int cpm2_set_irq_type(unsigned int virq, unsigned int flow_type)
         struct irq_desc *desc = irq_to_desc(virq);
         unsigned int vold, vnew, edibit;
 
-        if (flow_type == IRQ_TYPE_NONE)
-                flow_type = IRQ_TYPE_LEVEL_LOW;
-
-        if (flow_type & IRQ_TYPE_EDGE_RISING) {
-                printk(KERN_ERR "CPM2 PIC: sense type 0x%x not supported\n",
-                        flow_type);
-                return -EINVAL;
+        /* Port C interrupts are either IRQ_TYPE_EDGE_FALLING or
+         * IRQ_TYPE_EDGE_BOTH (default).  All others are IRQ_TYPE_EDGE_FALLING
+         * or IRQ_TYPE_LEVEL_LOW (default)
+         */
+        if (src >= CPM2_IRQ_PORTC15 && src <= CPM2_IRQ_PORTC0) {
+                if (flow_type == IRQ_TYPE_NONE)
+                        flow_type = IRQ_TYPE_EDGE_BOTH;
+
+                if (flow_type != IRQ_TYPE_EDGE_BOTH &&
+                    flow_type != IRQ_TYPE_EDGE_FALLING)
+                        goto err_sense;
+        } else {
+                if (flow_type == IRQ_TYPE_NONE)
+                        flow_type = IRQ_TYPE_LEVEL_LOW;
+
+                if (flow_type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH))
+                        goto err_sense;
         }
 
         desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
@@ -181,6 +191,10 @@ static int cpm2_set_irq_type(unsigned int virq, unsigned int flow_type)
         if (vold != vnew)
                 out_be32(&cpm2_intctl->ic_siexr, vnew);
         return 0;
+
+err_sense:
+        pr_err("CPM2 PIC: sense type 0x%x not supported\n", flow_type);
+        return -EINVAL;
 }
 
 static struct irq_chip cpm2_pic = {
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 4e3a3e345ab3..e1a028c1f18d 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -464,8 +464,7 @@ static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
 {
         struct pci_controller *hose = pci_bus_to_host(bus);
         struct mpc83xx_pcie_priv *pcie = hose->dn->data;
-        u8 bus_no = bus->number - hose->first_busno;
-        u32 dev_base = bus_no << 24 | devfn << 16;
+        u32 dev_base = bus->number << 24 | devfn << 16;
         int ret;
 
         ret = mpc83xx_pcie_exclude_device(bus, devfn);
@@ -515,12 +514,17 @@ static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
 static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
                                      int offset, int len, u32 val)
 {
+        struct pci_controller *hose = pci_bus_to_host(bus);
         void __iomem *cfg_addr;
 
         cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
         if (!cfg_addr)
                 return PCIBIOS_DEVICE_NOT_FOUND;
 
+        /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
+        if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
+                val &= 0xffffff00;
+
         switch (len) {
         case 1:
                 out_8(cfg_addr, val);
diff --git a/arch/powerpc/sysdev/mpc8xxx_gpio.c b/arch/powerpc/sysdev/mpc8xxx_gpio.c
index 103eace36194..ee1c0e1cf4a7 100644
--- a/arch/powerpc/sysdev/mpc8xxx_gpio.c
+++ b/arch/powerpc/sysdev/mpc8xxx_gpio.c
@@ -54,6 +54,22 @@ static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
         mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
 }
 
+/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
+ * defined as output cannot be determined by reading GPDAT register,
+ * so we use shadow data register instead. The status of input pins
+ * is determined by reading GPDAT register.
+ */
+static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
+{
+        u32 val;
+        struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
+        struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
+
+        val = in_be32(mm->regs + GPIO_DAT) & ~in_be32(mm->regs + GPIO_DIR);
+
+        return (val | mpc8xxx_gc->data) & mpc8xxx_gpio2mask(gpio);
+}
+
 static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
 {
         struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
@@ -136,7 +152,10 @@ static void __init mpc8xxx_add_controller(struct device_node *np)
         gc->ngpio = MPC8XXX_GPIO_PINS;
         gc->direction_input = mpc8xxx_gpio_dir_in;
         gc->direction_output = mpc8xxx_gpio_dir_out;
-        gc->get = mpc8xxx_gpio_get;
+        if (of_device_is_compatible(np, "fsl,mpc8572-gpio"))
+                gc->get = mpc8572_gpio_get;
+        else
+                gc->get = mpc8xxx_gpio_get;
         gc->set = mpc8xxx_gpio_set;
 
         ret = of_mm_gpiochip_add(np, mm_gc);
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index aa9d06e5925b..470dc6c11d57 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -567,13 +567,11 @@ static void __init mpic_scan_ht_pics(struct mpic *mpic)
 #endif /* CONFIG_MPIC_U3_HT_IRQS */
 
 #ifdef CONFIG_SMP
-static int irq_choose_cpu(unsigned int virt_irq)
+static int irq_choose_cpu(const cpumask_t *mask)
 {
-        cpumask_t mask;
         int cpuid;
 
-        cpumask_copy(&mask, irq_to_desc(virt_irq)->affinity);
-        if (cpus_equal(mask, CPU_MASK_ALL)) {
+        if (cpumask_equal(mask, cpu_all_mask)) {
                 static int irq_rover;
                 static DEFINE_SPINLOCK(irq_rover_lock);
                 unsigned long flags;
@@ -594,20 +592,15 @@ static int irq_choose_cpu(unsigned int virt_irq)
 
                 spin_unlock_irqrestore(&irq_rover_lock, flags);
         } else {
-                cpumask_t tmp;
-
-                cpus_and(tmp, cpu_online_map, mask);
-
-                if (cpus_empty(tmp))
+                cpuid = cpumask_first_and(mask, cpu_online_mask);
+                if (cpuid >= nr_cpu_ids)
                         goto do_round_robin;
-
-                cpuid = first_cpu(tmp);
         }
 
         return get_hard_smp_processor_id(cpuid);
 }
 #else
-static int irq_choose_cpu(unsigned int virt_irq)
+static int irq_choose_cpu(const cpumask_t *mask)
 {
         return hard_smp_processor_id();
 }
@@ -816,7 +809,7 @@ int mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask)
         unsigned int src = mpic_irq_to_hw(irq);
 
         if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
-                int cpuid = irq_choose_cpu(irq);
+                int cpuid = irq_choose_cpu(cpumask);
 
                 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
         } else {
diff --git a/arch/powerpc/sysdev/mpic_msi.c b/arch/powerpc/sysdev/mpic_msi.c
index 1d44eee80fa1..0f67cd79d481 100644
--- a/arch/powerpc/sysdev/mpic_msi.c
+++ b/arch/powerpc/sysdev/mpic_msi.c
@@ -39,7 +39,12 @@ static int mpic_msi_reserve_u3_hwirqs(struct mpic *mpic)
 
         pr_debug("mpic: found U3, guessing msi allocator setup\n");
 
-        /* Reserve source numbers we know are reserved in the HW */
+        /* Reserve source numbers we know are reserved in the HW.
+         *
+         * This is a bit of a mix of U3 and U4 reserves but that's going
+         * to work fine, we have plenty enugh numbers left so let's just
+         * mark anything we don't like reserved.
+         */
         for (i = 0;   i < 8;   i++)
                 msi_bitmap_reserve_hwirq(&mpic->msi_bitmap, i);
 
@@ -49,6 +54,10 @@ static int mpic_msi_reserve_u3_hwirqs(struct mpic *mpic)
         for (i = 100; i < 105; i++)
                 msi_bitmap_reserve_hwirq(&mpic->msi_bitmap, i);
 
+        for (i = 124; i < mpic->irq_count; i++)
+                msi_bitmap_reserve_hwirq(&mpic->msi_bitmap, i);
+
+
         np = NULL;
         while ((np = of_find_all_nodes(np))) {
                 pr_debug("mpic: mapping hwirqs for %s\n", np->full_name);
diff --git a/arch/powerpc/sysdev/mpic_u3msi.c b/arch/powerpc/sysdev/mpic_u3msi.c
index d3caf23e6312..bcbfe79c704b 100644
--- a/arch/powerpc/sysdev/mpic_u3msi.c
+++ b/arch/powerpc/sysdev/mpic_u3msi.c
@@ -64,12 +64,12 @@ static u64 read_ht_magic_addr(struct pci_dev *pdev, unsigned int pos)
         return addr;
 }
 
-static u64 find_ht_magic_addr(struct pci_dev *pdev)
+static u64 find_ht_magic_addr(struct pci_dev *pdev, unsigned int hwirq)
 {
         struct pci_bus *bus;
         unsigned int pos;
 
-        for (bus = pdev->bus; bus; bus = bus->parent) {
+        for (bus = pdev->bus; bus && bus->self; bus = bus->parent) {
                 pos = pci_find_ht_capability(bus->self, HT_CAPTYPE_MSI_MAPPING);
                 if (pos)
                         return read_ht_magic_addr(bus->self, pos);
@@ -78,13 +78,41 @@ static u64 find_ht_magic_addr(struct pci_dev *pdev)
         return 0;
 }
 
+static u64 find_u4_magic_addr(struct pci_dev *pdev, unsigned int hwirq)
+{
+        struct pci_controller *hose = pci_bus_to_host(pdev->bus);
+
+        /* U4 PCIe MSIs need to write to the special register in
+         * the bridge that generates interrupts. There should be
+         * theorically a register at 0xf8005000 where you just write
+         * the MSI number and that triggers the right interrupt, but
+         * unfortunately, this is busted in HW, the bridge endian swaps
+         * the value and hits the wrong nibble in the register.
+         *
+         * So instead we use another register set which is used normally
+         * for converting HT interrupts to MPIC interrupts, which decodes
+         * the interrupt number as part of the low address bits
+         *
+         * This will not work if we ever use more than one legacy MSI in
+         * a block but we never do. For one MSI or multiple MSI-X where
+         * each interrupt address can be specified separately, it works
+         * just fine.
+         */
+        if (of_device_is_compatible(hose->dn, "u4-pcie") ||
+            of_device_is_compatible(hose->dn, "U4-pcie"))
+                return 0xf8004000 | (hwirq << 4);
+
+        return 0;
+}
+
 static int u3msi_msi_check_device(struct pci_dev *pdev, int nvec, int type)
 {
         if (type == PCI_CAP_ID_MSIX)
                 pr_debug("u3msi: MSI-X untested, trying anyway.\n");
 
         /* If we can't find a magic address then MSI ain't gonna work */
-        if (find_ht_magic_addr(pdev) == 0) {
+        if (find_ht_magic_addr(pdev, 0) == 0 &&
+            find_u4_magic_addr(pdev, 0) == 0) {
                 pr_debug("u3msi: no magic address found for %s\n",
                          pci_name(pdev));
                 return -ENXIO;
@@ -118,10 +146,6 @@ static int u3msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
         u64 addr;
         int hwirq;
 
-        addr = find_ht_magic_addr(pdev);
-        msg.address_lo = addr & 0xFFFFFFFF;
-        msg.address_hi = addr >> 32;
-
         list_for_each_entry(entry, &pdev->msi_list, list) {
                 hwirq = msi_bitmap_alloc_hwirqs(&msi_mpic->msi_bitmap, 1);
                 if (hwirq < 0) {
@@ -129,6 +153,12 @@ static int u3msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
                         return hwirq;
                 }
 
+                addr = find_ht_magic_addr(pdev, hwirq);
+                if (addr == 0)
+                        addr = find_u4_magic_addr(pdev, hwirq);
+                msg.address_lo = addr & 0xFFFFFFFF;
+                msg.address_hi = addr >> 32;
+
                 virq = irq_create_mapping(msi_mpic->irqhost, hwirq);
                 if (virq == NO_IRQ) {
                         pr_debug("u3msi: failed mapping hwirq 0x%x\n", hwirq);
@@ -143,6 +173,8 @@ static int u3msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
                 pr_debug("u3msi: allocated virq 0x%x (hw 0x%x) addr 0x%lx\n",
                           virq, hwirq, (unsigned long)addr);
 
+                printk("u3msi: allocated virq 0x%x (hw 0x%x) addr 0x%lx\n",
+                          virq, hwirq, (unsigned long)addr);
                 msg.data = hwirq;
                 write_msi_msg(virq, &msg);
 
diff --git a/arch/s390/crypto/aes_s390.c b/arch/s390/crypto/aes_s390.c
index 6118890c946d..6be4503201ac 100644
--- a/arch/s390/crypto/aes_s390.c
+++ b/arch/s390/crypto/aes_s390.c
@@ -174,7 +174,7 @@ static int fallback_init_cip(struct crypto_tfm *tfm)
         if (IS_ERR(sctx->fallback.cip)) {
                 pr_err("Allocating AES fallback algorithm %s failed\n",
                        name);
-                return PTR_ERR(sctx->fallback.blk);
+                return PTR_ERR(sctx->fallback.cip);
         }
 
         return 0;
diff --git a/arch/s390/hypfs/hypfs_diag.c b/arch/s390/hypfs/hypfs_diag.c
index 77df726180ba..2b92d501425f 100644
--- a/arch/s390/hypfs/hypfs_diag.c
+++ b/arch/s390/hypfs/hypfs_diag.c
@@ -164,7 +164,7 @@ static inline void part_hdr__part_name(enum diag204_format type, void *hdr,
                        LPAR_NAME_LEN);
         EBCASC(name, LPAR_NAME_LEN);
         name[LPAR_NAME_LEN] = 0;
-        strstrip(name);
+        strim(name);
 }
 
 struct cpu_info {
@@ -523,7 +523,7 @@ static int diag224_idx2name(int index, char *name)
         memcpy(name, diag224_cpu_names + ((index + 1) * CPU_NAME_LEN),
                 CPU_NAME_LEN);
         name[CPU_NAME_LEN] = 0;
-        strstrip(name);
+        strim(name);
         return 0;
 }
 
diff --git a/arch/s390/hypfs/hypfs_vm.c b/arch/s390/hypfs/hypfs_vm.c
index d01fc8f799f0..f0b0d31f0b48 100644
--- a/arch/s390/hypfs/hypfs_vm.c
+++ b/arch/s390/hypfs/hypfs_vm.c
@@ -124,7 +124,7 @@ static int hpyfs_vm_create_guest(struct super_block *sb,
         /* guest dir */
         memcpy(guest_name, data->guest_name, NAME_LEN);
         EBCASC(guest_name, NAME_LEN);
-        strstrip(guest_name);
+        strim(guest_name);
         guest_dir = hypfs_mkdir(sb, systems_dir, guest_name);
         if (IS_ERR(guest_dir))
                 return PTR_ERR(guest_dir);
diff --git a/arch/s390/include/asm/asm-offsets.h b/arch/s390/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/s390/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/s390/include/asm/unistd.h b/arch/s390/include/asm/unistd.h
index cb5232df151e..192a7203a14f 100644
--- a/arch/s390/include/asm/unistd.h
+++ b/arch/s390/include/asm/unistd.h
@@ -269,7 +269,8 @@
 #define __NR_pwritev            329
 #define __NR_rt_tgsigqueueinfo  330
 #define __NR_perf_event_open    331
-#define NR_syscalls 332
+#define __NR_recvmmsg           332
+#define NR_syscalls 333
 
 /* 
  * There are some system calls that are not present on 64 bit, some
diff --git a/arch/s390/kernel/compat_wrapper.S b/arch/s390/kernel/compat_wrapper.S
index 30de2d0e52bb..faeaccc7d7d9 100644
--- a/arch/s390/kernel/compat_wrapper.S
+++ b/arch/s390/kernel/compat_wrapper.S
@@ -1853,3 +1853,12 @@ sys32_execve_wrapper:
         llgtr   %r3,%r3                 # compat_uptr_t *
         llgtr   %r4,%r4                 # compat_uptr_t *
         jg      sys32_execve            # branch to system call
+
+        .globl  compat_sys_recvmmsg_wrapper
+compat_sys_recvmmsg_wrapper:
+        lgfr    %r2,%r2                 # int
+        llgtr   %r3,%r3                 # struct compat_mmsghdr *
+        llgfr   %r4,%r4                 # unsigned int
+        llgfr   %r5,%r5                 # unsigned int
+        llgtr   %r6,%r6                 # struct compat_timespec *
+        jg      compat_sys_recvmmsg
diff --git a/arch/s390/kernel/ipl.c b/arch/s390/kernel/ipl.c
index 4890ac6d7faa..4d73296fed74 100644
--- a/arch/s390/kernel/ipl.c
+++ b/arch/s390/kernel/ipl.c
@@ -221,7 +221,7 @@ static ssize_t sys_##_prefix##_##_name##_store(struct kobject *kobj,	\
                 const char *buf, size_t len)                            \
 {                                                                       \
         strncpy(_value, buf, sizeof(_value) - 1);                       \
-        strstrip(_value);                                               \
+        strim(_value);                                                  \
         return len;                                                     \
 }                                                                       \
 static struct kobj_attribute sys_##_prefix##_##_name##_attr =           \
@@ -472,7 +472,7 @@ static ssize_t ipl_ccw_loadparm_show(struct kobject *kobj,
                 return sprintf(page, "#unknown#\n");
         memcpy(loadparm, &sclp_ipl_info.loadparm, LOADPARM_LEN);
         EBCASC(loadparm, LOADPARM_LEN);
-        strstrip(loadparm);
+        strim(loadparm);
         return sprintf(page, "%s\n", loadparm);
 }
 
@@ -776,7 +776,7 @@ static void reipl_get_ascii_loadparm(char *loadparm,
         memcpy(loadparm, ibp->ipl_info.ccw.load_parm, LOADPARM_LEN);
         EBCASC(loadparm, LOADPARM_LEN);
         loadparm[LOADPARM_LEN] = 0;
-        strstrip(loadparm);
+        strim(loadparm);
 }
 
 static ssize_t reipl_generic_loadparm_show(struct ipl_parameter_block *ipb,
diff --git a/arch/s390/kernel/ptrace.c b/arch/s390/kernel/ptrace.c
index 653c6a178740..13815d39f7dd 100644
--- a/arch/s390/kernel/ptrace.c
+++ b/arch/s390/kernel/ptrace.c
@@ -959,7 +959,7 @@ static const struct user_regset s390_compat_regsets[] = {
                 .set = s390_fpregs_set,
         },
         [REGSET_GENERAL_EXTENDED] = {
-                .core_note_type = NT_PRXSTATUS,
+                .core_note_type = NT_S390_HIGH_GPRS,
                 .n = sizeof(s390_compat_regs_high) / sizeof(compat_long_t),
                 .size = sizeof(compat_long_t),
                 .align = sizeof(compat_long_t),
diff --git a/arch/s390/kernel/syscalls.S b/arch/s390/kernel/syscalls.S
index 30eca070d426..4f292c936872 100644
--- a/arch/s390/kernel/syscalls.S
+++ b/arch/s390/kernel/syscalls.S
@@ -340,3 +340,4 @@ SYSCALL(sys_preadv,sys_preadv,compat_sys_preadv_wrapper)
 SYSCALL(sys_pwritev,sys_pwritev,compat_sys_pwritev_wrapper)
 SYSCALL(sys_rt_tgsigqueueinfo,sys_rt_tgsigqueueinfo,compat_sys_rt_tgsigqueueinfo_wrapper) /* 330 */
 SYSCALL(sys_perf_event_open,sys_perf_event_open,sys_perf_event_open_wrapper)
+SYSCALL(sys_recvmmsg,sys_recvmmsg,compat_sys_recvmmsg_wrapper)
diff --git a/arch/s390/kernel/traps.c b/arch/s390/kernel/traps.c
index c2e42cc65ce7..6e7ad63854c0 100644
--- a/arch/s390/kernel/traps.c
+++ b/arch/s390/kernel/traps.c
@@ -18,7 +18,7 @@
 #include <linux/kernel.h>
 #include <linux/string.h>
 #include <linux/errno.h>
-#include <linux/ptrace.h>
+#include <linux/tracehook.h>
 #include <linux/timer.h>
 #include <linux/mm.h>
 #include <linux/smp.h>
@@ -382,7 +382,7 @@ void __kprobes do_single_step(struct pt_regs *regs)
                                         SIGTRAP) == NOTIFY_STOP){
                 return;
         }
-        if ((current->ptrace & PT_PTRACED) != 0)
+        if (tracehook_consider_fatal_signal(current, SIGTRAP))
                 force_sig(SIGTRAP, current);
 }
 
@@ -483,7 +483,7 @@ static void illegal_op(struct pt_regs * regs, long interruption_code)
                 if (get_user(*((__u16 *) opcode), (__u16 __user *) location))
                         return;
                 if (*((__u16 *) opcode) == S390_BREAKPOINT_U16) {
-                        if (current->ptrace & PT_PTRACED)
+                        if (tracehook_consider_fatal_signal(current, SIGTRAP))
                                 force_sig(SIGTRAP, current);
                         else
                                 signal = SIGILL;
diff --git a/arch/score/include/asm/asm-offsets.h b/arch/score/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/score/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/score/include/asm/cacheflush.h b/arch/score/include/asm/cacheflush.h
index caaba24036e3..1d545d0ce206 100644
--- a/arch/score/include/asm/cacheflush.h
+++ b/arch/score/include/asm/cacheflush.h
@@ -14,10 +14,12 @@ extern void flush_cache_sigtramp(unsigned long addr);
 extern void flush_icache_all(void);
 extern void flush_icache_range(unsigned long start, unsigned long end);
 extern void flush_dcache_range(unsigned long start, unsigned long end);
+extern void flush_dcache_page(struct page *page);
+
+#define PG_dcache_dirty         PG_arch_1
 
 #define flush_cache_dup_mm(mm)                  do {} while (0)
 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
-#define flush_dcache_page(page)                 do {} while (0)
 #define flush_dcache_mmap_lock(mapping)         do {} while (0)
 #define flush_dcache_mmap_unlock(mapping)       do {} while (0)
 #define flush_cache_vmap(start, end)            do {} while (0)
diff --git a/arch/score/include/asm/delay.h b/arch/score/include/asm/delay.h
index 6726ec199dc0..529e494712a5 100644
--- a/arch/score/include/asm/delay.h
+++ b/arch/score/include/asm/delay.h
@@ -1,6 +1,8 @@
 #ifndef _ASM_SCORE_DELAY_H
 #define _ASM_SCORE_DELAY_H
 
+#include <asm-generic/param.h>
+
 static inline void __delay(unsigned long loops)
 {
         /* 3 cycles per loop. */
diff --git a/arch/score/include/asm/page.h b/arch/score/include/asm/page.h
index d92a5a2d36d4..1e9ade8e77e6 100644
--- a/arch/score/include/asm/page.h
+++ b/arch/score/include/asm/page.h
@@ -74,7 +74,7 @@ extern unsigned long max_pfn;
 #define page_to_bus(page)       (page_to_phys(page))
 #define phys_to_page(paddr)     (pfn_to_page(phys_to_pfn(paddr)))
 
-#define pfn_valid(pfn)          ((pfn) >= min_low_pfn && (pfn) < max_mapnr)
+#define pfn_valid(pfn)          (((pfn) >= min_low_pfn) && ((pfn) < max_low_pfn))
 
 #define ARCH_PFN_OFFSET         (PAGE_OFFSET >> PAGE_SHIFT)
 
diff --git a/arch/score/kernel/setup.c b/arch/score/kernel/setup.c
index 6a2503c75c4e..6f898c057878 100644
--- a/arch/score/kernel/setup.c
+++ b/arch/score/kernel/setup.c
@@ -49,6 +49,7 @@ static void __init bootmem_init(void)
 
         min_low_pfn = PFN_UP(MEMORY_START);
         max_low_pfn = PFN_UP(MEMORY_START + MEMORY_SIZE);
+        max_mapnr = max_low_pfn - min_low_pfn;
 
         /* Initialize the boot-time allocator with low memory only. */
         bootmap_size = init_bootmem_node(NODE_DATA(0), start_pfn,
diff --git a/arch/score/mm/cache.c b/arch/score/mm/cache.c
index dbac9d9dfddd..b25e95743600 100644
--- a/arch/score/mm/cache.c
+++ b/arch/score/mm/cache.c
@@ -29,6 +29,7 @@
 #include <linux/mm.h>
 #include <linux/module.h>
 #include <linux/sched.h>
+#include <linux/fs.h>
 
 #include <asm/mmu_context.h>
 
@@ -51,6 +52,27 @@ static void flush_data_cache_page(unsigned long addr)
         }
 }
 
+void flush_dcache_page(struct page *page)
+{
+        struct address_space *mapping = page_mapping(page);
+        unsigned long addr;
+
+        if (PageHighMem(page))
+                return;
+        if (mapping && !mapping_mapped(mapping)) {
+                set_bit(PG_dcache_dirty, &(page)->flags);
+                return;
+        }
+
+        /*
+         * We could delay the flush for the !page_mapping case too.  But that
+         * case is for exec env/arg pages and those are %99 certainly going to
+         * get faulted into the tlb (and thus flushed) anyways.
+         */
+        addr = (unsigned long) page_address(page);
+        flush_data_cache_page(addr);
+}
+
 /* called by update_mmu_cache. */
 void __update_cache(struct vm_area_struct *vma, unsigned long address,
                 pte_t pte)
@@ -63,11 +85,11 @@ void __update_cache(struct vm_area_struct *vma, unsigned long address,
         if (unlikely(!pfn_valid(pfn)))
                 return;
         page = pfn_to_page(pfn);
-        if (page_mapping(page) && test_bit(PG_arch_1, &page->flags)) {
+        if (page_mapping(page) && test_bit(PG_dcache_dirty, &(page)->flags)) {
                 addr = (unsigned long) page_address(page);
                 if (exec)
                         flush_data_cache_page(addr);
-                clear_bit(PG_arch_1, &page->flags);
+                clear_bit(PG_dcache_dirty, &(page)->flags);
         }
 }
 
diff --git a/arch/score/mm/init.c b/arch/score/mm/init.c
index 4e3dcd0c4716..8c15b2c85d5a 100644
--- a/arch/score/mm/init.c
+++ b/arch/score/mm/init.c
@@ -83,7 +83,6 @@ void __init mem_init(void)
         unsigned long codesize, reservedpages, datasize, initsize;
         unsigned long tmp, ram = 0;
 
-        max_mapnr = max_low_pfn;
         high_memory = (void *) __va(max_low_pfn << PAGE_SHIFT);
         totalram_pages += free_all_bootmem();
         totalram_pages -= setup_zero_page();    /* Setup zeroed pages. */
@@ -101,10 +100,6 @@ void __init mem_init(void)
         datasize = (unsigned long) &_edata - (unsigned long) &_etext;
         initsize = (unsigned long) &__init_end - (unsigned long) &__init_begin;
 
-        kclist_add(&kcore_mem, __va(0), max_low_pfn << PAGE_SHIFT);
-        kclist_add(&kcore_vmalloc, (void *) VMALLOC_START,
-                        VMALLOC_END - VMALLOC_START);
-
         printk(KERN_INFO "Memory: %luk/%luk available (%ldk kernel code, "
                         "%ldk reserved, %ldk data, %ldk init, %ldk highmem)\n",
                         (unsigned long) nr_free_pages() << (PAGE_SHIFT-10),
diff --git a/arch/sh/Makefile b/arch/sh/Makefile
index ac17c5ac550e..db91925c79d1 100644
--- a/arch/sh/Makefile
+++ b/arch/sh/Makefile
@@ -205,10 +205,7 @@ libs-$(CONFIG_SUPERH64)		:= arch/sh/lib64/ $(libs-y)
 
 BOOT_TARGETS = uImage uImage.bz2 uImage.gz uImage.lzma uImage.srec uImage.bin \
                zImage vmlinux.srec romImage
-PHONY += maketools $(BOOT_TARGETS) FORCE
-
-maketools:  include/linux/version.h FORCE
-        $(Q)$(MAKE) $(build)=arch/sh/tools include/asm-sh/machtypes.h
+PHONY += $(BOOT_TARGETS)
 
 all: $(KBUILD_IMAGE)
 
@@ -217,7 +214,8 @@ $(BOOT_TARGETS): vmlinux
 
 compressed: zImage
 
-archprepare: maketools
+archprepare:
+        $(Q)$(MAKE) $(build)=arch/sh/tools include/generated/machtypes.h
 
 archclean:
         $(Q)$(MAKE) $(clean)=$(boot)
@@ -234,5 +232,3 @@ define archhelp
         @echo '  uImage.bz2                - Kernel-only image for U-Boot (bzip2)'
         @echo '  uImage.lzma               - Kernel-only image for U-Boot (lzma)'
 endef
-
-CLEAN_FILES += include/asm-sh/machtypes.h
diff --git a/arch/sh/drivers/pci/fixups-rts7751r2d.c b/arch/sh/drivers/pci/fixups-rts7751r2d.c
index 052b354236dc..7898f14d6641 100644
--- a/arch/sh/drivers/pci/fixups-rts7751r2d.c
+++ b/arch/sh/drivers/pci/fixups-rts7751r2d.c
@@ -15,7 +15,7 @@
 #include <mach/lboxre2.h>
 #include <mach/r2d.h>
 #include "pci-sh4.h"
-#include <asm/machtypes.h>
+#include <generated/machtypes.h>
 
 #define PCIMCR_MRSET_OFF        0xBFFFFFFF
 #define PCIMCR_RFSH_OFF         0xFFFFFFFB
diff --git a/arch/sh/include/asm/.gitignore b/arch/sh/include/asm/.gitignore
deleted file mode 100644
index 378db779fb6c..000000000000
--- a/arch/sh/include/asm/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-machtypes.h
diff --git a/arch/sh/include/asm/asm-offsets.h b/arch/sh/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/sh/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/sh/include/asm/machvec.h b/arch/sh/include/asm/machvec.h
index 84dd37761f56..9c30955630ff 100644
--- a/arch/sh/include/asm/machvec.h
+++ b/arch/sh/include/asm/machvec.h
@@ -12,7 +12,7 @@
 
 #include <linux/types.h>
 #include <linux/time.h>
-#include <asm/machtypes.h>
+#include <generated/machtypes.h>
 
 struct sh_machine_vector {
         void (*mv_setup)(char **cmdline_p);
diff --git a/arch/sh/tools/Makefile b/arch/sh/tools/Makefile
index 567516b58acc..558a56bcc7cf 100644
--- a/arch/sh/tools/Makefile
+++ b/arch/sh/tools/Makefile
@@ -10,7 +10,7 @@
 # Shamelessly cloned from ARM.
 #
 
-include/asm-sh/machtypes.h: $(src)/gen-mach-types $(src)/mach-types
+include/generated/machtypes.h: $(src)/gen-mach-types $(src)/mach-types
         @echo '  Generating $@'
-        $(Q)if [ ! -d include/asm-sh ]; then mkdir -p include/asm-sh; fi
+        $(Q)mkdir -p $(dir $@)
         $(Q)$(AWK) -f $^ > $@ || { rm -f $@; /bin/false; }
diff --git a/arch/sh/tools/gen-mach-types b/arch/sh/tools/gen-mach-types
index 65161e368353..f5ff7c5d8913 100644
--- a/arch/sh/tools/gen-mach-types
+++ b/arch/sh/tools/gen-mach-types
@@ -1,6 +1,6 @@
 #!/bin/awk
 #
-# Awk script to generate include/asm-sh/machtypes.h
+# Awk script to generate include/generated/machtypes.h
 # Heavily based on arch/arm/tools/gen-mach-types
 #
 BEGIN   { nr = 0 }
diff --git a/arch/sparc/include/asm/asm-offsets.h b/arch/sparc/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/sparc/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/sparc/include/asm/fcntl.h b/arch/sparc/include/asm/fcntl.h
index 3b9cfb39175e..38f37b333cc7 100644
--- a/arch/sparc/include/asm/fcntl.h
+++ b/arch/sparc/include/asm/fcntl.h
@@ -19,7 +19,7 @@
 #define O_NOATIME       0x200000
 #define O_CLOEXEC       0x400000
 /*
- * Before Linux 2.6.32 only O_DSYNC semantics were implemented, but using
+ * Before Linux 2.6.33 only O_DSYNC semantics were implemented, but using
  * the O_SYNC flag.  We continue to use the existing numerical value
  * for O_DSYNC semantics now, but using the correct symbolic name for it.
  * This new value is used to request true Posix O_SYNC semantics.  It is
diff --git a/arch/um/Makefile b/arch/um/Makefile
index fc633dbacf84..fab8121d2b32 100644
--- a/arch/um/Makefile
+++ b/arch/um/Makefile
@@ -149,6 +149,6 @@ $(SHARED_HEADERS)/user_constants.h: $(ARCH_DIR)/sys-$(SUBARCH)/user-offsets.s
 
 $(SHARED_HEADERS)/kern_constants.h:
         $(Q)mkdir -p $(dir $@)
-        $(Q)echo '#include "../../../../include/asm/asm-offsets.h"' >$@
+        $(Q)echo '#include "../../../../include/generated/asm-offsets.h"' >$@
 
 export SUBARCH USER_CFLAGS CFLAGS_NO_HARDENING OS HEADER_ARCH DEV_NULL_PATH
diff --git a/arch/um/include/asm/asm-offsets.h b/arch/um/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/um/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 3b2a5aca4edb..55298e891571 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -50,6 +50,8 @@ config X86
         select HAVE_KERNEL_BZIP2
         select HAVE_KERNEL_LZMA
         select HAVE_HW_BREAKPOINT
+        select PERF_EVENTS
+        select ANON_INODES
         select HAVE_ARCH_KMEMCHECK
         select HAVE_USER_RETURN_NOTIFIER
 
diff --git a/arch/x86/boot/header.S b/arch/x86/boot/header.S
index b31cc54b4641..93e689f4bd86 100644
--- a/arch/x86/boot/header.S
+++ b/arch/x86/boot/header.S
@@ -16,7 +16,7 @@
  */
 
 #include <asm/segment.h>
-#include <linux/utsrelease.h>
+#include <generated/utsrelease.h>
 #include <asm/boot.h>
 #include <asm/e820.h>
 #include <asm/page_types.h>
diff --git a/arch/x86/boot/version.c b/arch/x86/boot/version.c
index 2723d9b5ce43..2b15aa488ffb 100644
--- a/arch/x86/boot/version.c
+++ b/arch/x86/boot/version.c
@@ -13,8 +13,8 @@
  */
 
 #include "boot.h"
-#include <linux/utsrelease.h>
-#include <linux/compile.h>
+#include <generated/utsrelease.h>
+#include <generated/compile.h>
 
 const char kernel_version[] =
         UTS_RELEASE " (" LINUX_COMPILE_BY "@" LINUX_COMPILE_HOST ") "
diff --git a/arch/x86/include/asm/asm-offsets.h b/arch/x86/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/x86/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 613700f27a4a..637e1ec963c3 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -153,6 +153,7 @@
 #define X86_FEATURE_SSE5        (6*32+11) /* SSE-5 */
 #define X86_FEATURE_SKINIT      (6*32+12) /* SKINIT/STGI instructions */
 #define X86_FEATURE_WDT         (6*32+13) /* Watchdog timer */
+#define X86_FEATURE_NODEID_MSR  (6*32+19) /* NodeId MSR */
 
 /*
  * Auxiliary flags: Linux defined - For features scattered in various
diff --git a/arch/x86/include/asm/hw_irq.h b/arch/x86/include/asm/hw_irq.h
index 08c48a81841f..eeac829a0f44 100644
--- a/arch/x86/include/asm/hw_irq.h
+++ b/arch/x86/include/asm/hw_irq.h
@@ -103,7 +103,8 @@ extern int assign_irq_vector(int, struct irq_cfg *, const struct cpumask *);
 extern void send_cleanup_vector(struct irq_cfg *);
 
 struct irq_desc;
-extern unsigned int set_desc_affinity(struct irq_desc *, const struct cpumask *);
+extern unsigned int set_desc_affinity(struct irq_desc *, const struct cpumask *,
+                                      unsigned int *dest_id);
 extern int IO_APIC_get_PCI_irq_vector(int bus, int devfn, int pin, struct io_apic_irq_attr *irq_attr);
 extern void setup_ioapic_dest(void);
 
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 4ffe09b2ad75..1cd58cdbc03f 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -12,6 +12,7 @@
 #define MSR_FS_BASE             0xc0000100 /* 64bit FS base */
 #define MSR_GS_BASE             0xc0000101 /* 64bit GS base */
 #define MSR_KERNEL_GS_BASE      0xc0000102 /* SwapGS GS shadow */
+#define MSR_TSC_AUX             0xc0000103 /* Auxiliary TSC */
 
 /* EFER bits: */
 #define _EFER_SCE               0  /* SYSCALL/SYSRET */
@@ -123,6 +124,7 @@
 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
 #define FAM10H_MMIO_CONF_BASE_MASK      0xfffffff
 #define FAM10H_MMIO_CONF_BASE_SHIFT     20
+#define MSR_FAM10H_NODE_ID              0xc001100c
 
 /* K8 MSRs */
 #define MSR_K8_TOP_MEM1                 0xc001001a
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index 2d228fc9b4b7..c5bc4c2d33f5 100644
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -27,6 +27,18 @@ struct msr {
         };
 };
 
+struct msr_info {
+        u32 msr_no;
+        struct msr reg;
+        struct msr *msrs;
+        int err;
+};
+
+struct msr_regs_info {
+        u32 *regs;
+        int err;
+};
+
 static inline unsigned long long native_read_tscp(unsigned int *aux)
 {
         unsigned long low, high;
@@ -240,9 +252,9 @@ do {                                                            \
 #define checking_wrmsrl(msr, val) wrmsr_safe((msr), (u32)(val),         \
                                              (u32)((val) >> 32))
 
-#define write_tsc(val1, val2) wrmsr(0x10, (val1), (val2))
+#define write_tsc(val1, val2) wrmsr(MSR_IA32_TSC, (val1), (val2))
 
-#define write_rdtscp_aux(val) wrmsr(0xc0000103, (val), 0)
+#define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0)
 
 struct msr *msrs_alloc(void);
 void msrs_free(struct msr *msrs);
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 6f8ec1c37e0a..fc801bab1b3b 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -181,7 +181,7 @@ static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
                                 unsigned int *ecx, unsigned int *edx)
 {
         /* ecx is often an input as well as an output. */
-        asm("cpuid"
+        asm volatile("cpuid"
             : "=a" (*eax),
               "=b" (*ebx),
               "=c" (*ecx),
diff --git a/arch/x86/include/asm/stacktrace.h b/arch/x86/include/asm/stacktrace.h
index cf86a5e73815..35e89122a42f 100644
--- a/arch/x86/include/asm/stacktrace.h
+++ b/arch/x86/include/asm/stacktrace.h
@@ -5,6 +5,29 @@ extern int kstack_depth_to_print;
 
 int x86_is_stack_id(int id, char *name);
 
+struct thread_info;
+struct stacktrace_ops;
+
+typedef unsigned long (*walk_stack_t)(struct thread_info *tinfo,
+                                      unsigned long *stack,
+                                      unsigned long bp,
+                                      const struct stacktrace_ops *ops,
+                                      void *data,
+                                      unsigned long *end,
+                                      int *graph);
+
+extern unsigned long
+print_context_stack(struct thread_info *tinfo,
+                    unsigned long *stack, unsigned long bp,
+                    const struct stacktrace_ops *ops, void *data,
+                    unsigned long *end, int *graph);
+
+extern unsigned long
+print_context_stack_bp(struct thread_info *tinfo,
+                       unsigned long *stack, unsigned long bp,
+                       const struct stacktrace_ops *ops, void *data,
+                       unsigned long *end, int *graph);
+
 /* Generic stack tracer with callbacks */
 
 struct stacktrace_ops {
@@ -14,6 +37,7 @@ struct stacktrace_ops {
         void (*address)(void *data, unsigned long address, int reliable);
         /* On negative return stop dumping */
         int (*stack)(void *data, char *name);
+        walk_stack_t    walk_stack;
 };
 
 void dump_trace(struct task_struct *tsk, struct pt_regs *regs,
diff --git a/arch/x86/kernel/apic/apic_flat_64.c b/arch/x86/kernel/apic/apic_flat_64.c
index d0c99abc26c3..eacbd2b31d27 100644
--- a/arch/x86/kernel/apic/apic_flat_64.c
+++ b/arch/x86/kernel/apic/apic_flat_64.c
@@ -306,10 +306,7 @@ physflat_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
                 if (cpumask_test_cpu(cpu, cpu_online_mask))
                         break;
         }
-        if (cpu < nr_cpu_ids)
-                return per_cpu(x86_cpu_to_apicid, cpu);
-
-        return BAD_APICID;
+        return per_cpu(x86_cpu_to_apicid, cpu);
 }
 
 struct apic apic_physflat =  {
diff --git a/arch/x86/kernel/apic/bigsmp_32.c b/arch/x86/kernel/apic/bigsmp_32.c
index 38dcecfa5818..cb804c5091b9 100644
--- a/arch/x86/kernel/apic/bigsmp_32.c
+++ b/arch/x86/kernel/apic/bigsmp_32.c
@@ -131,10 +131,7 @@ static unsigned int bigsmp_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
                 if (cpumask_test_cpu(cpu, cpu_online_mask))
                         break;
         }
-        if (cpu < nr_cpu_ids)
-                return bigsmp_cpu_to_logical_apicid(cpu);
-
-        return BAD_APICID;
+        return bigsmp_cpu_to_logical_apicid(cpu);
 }
 
 static int bigsmp_phys_pkg_id(int cpuid_apic, int index_msb)
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 11a5851f1f50..de00c4619a55 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -2276,26 +2276,28 @@ static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq
 
 /*
  * Either sets desc->affinity to a valid value, and returns
- * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
+ * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
  * leaves desc->affinity untouched.
  */
 unsigned int
-set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
+set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask,
+                  unsigned int *dest_id)
 {
         struct irq_cfg *cfg;
         unsigned int irq;
 
         if (!cpumask_intersects(mask, cpu_online_mask))
-                return BAD_APICID;
+                return -1;
 
         irq = desc->irq;
         cfg = desc->chip_data;
         if (assign_irq_vector(irq, cfg, mask))
-                return BAD_APICID;
+                return -1;
 
         cpumask_copy(desc->affinity, mask);
 
-        return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
+        *dest_id = apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
+        return 0;
 }
 
 static int
@@ -2311,12 +2313,11 @@ set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
         cfg = desc->chip_data;
 
         spin_lock_irqsave(&ioapic_lock, flags);
-        dest = set_desc_affinity(desc, mask);
-        if (dest != BAD_APICID) {
+        ret = set_desc_affinity(desc, mask, &dest);
+        if (!ret) {
                 /* Only the high 8 bits are valid. */
                 dest = SET_APIC_LOGICAL_ID(dest);
                 __target_IO_APIC_irq(irq, dest, cfg);
-                ret = 0;
         }
         spin_unlock_irqrestore(&ioapic_lock, flags);
 
@@ -3351,8 +3352,7 @@ static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
         struct msi_msg msg;
         unsigned int dest;
 
-        dest = set_desc_affinity(desc, mask);
-        if (dest == BAD_APICID)
+        if (set_desc_affinity(desc, mask, &dest))
                 return -1;
 
         cfg = desc->chip_data;
@@ -3384,8 +3384,7 @@ ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
         if (get_irte(irq, &irte))
                 return -1;
 
-        dest = set_desc_affinity(desc, mask);
-        if (dest == BAD_APICID)
+        if (set_desc_affinity(desc, mask, &dest))
                 return -1;
 
         irte.vector = cfg->vector;
@@ -3567,8 +3566,7 @@ static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
         struct msi_msg msg;
         unsigned int dest;
 
-        dest = set_desc_affinity(desc, mask);
-        if (dest == BAD_APICID)
+        if (set_desc_affinity(desc, mask, &dest))
                 return -1;
 
         cfg = desc->chip_data;
@@ -3623,8 +3621,7 @@ static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
         struct msi_msg msg;
         unsigned int dest;
 
-        dest = set_desc_affinity(desc, mask);
-        if (dest == BAD_APICID)
+        if (set_desc_affinity(desc, mask, &dest))
                 return -1;
 
         cfg = desc->chip_data;
@@ -3730,8 +3727,7 @@ static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
         struct irq_cfg *cfg;
         unsigned int dest;
 
-        dest = set_desc_affinity(desc, mask);
-        if (dest == BAD_APICID)
+        if (set_desc_affinity(desc, mask, &dest))
                 return -1;
 
         cfg = desc->chip_data;
diff --git a/arch/x86/kernel/apic/x2apic_cluster.c b/arch/x86/kernel/apic/x2apic_cluster.c
index a5371ec36776..cf69c59f4910 100644
--- a/arch/x86/kernel/apic/x2apic_cluster.c
+++ b/arch/x86/kernel/apic/x2apic_cluster.c
@@ -148,10 +148,7 @@ x2apic_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
                         break;
         }
 
-        if (cpu < nr_cpu_ids)
-                return per_cpu(x86_cpu_to_logical_apicid, cpu);
-
-        return BAD_APICID;
+        return per_cpu(x86_cpu_to_logical_apicid, cpu);
 }
 
 static unsigned int x2apic_cluster_phys_get_apic_id(unsigned long x)
diff --git a/arch/x86/kernel/apic/x2apic_phys.c b/arch/x86/kernel/apic/x2apic_phys.c
index a8989aadc99a..8972f38c5ced 100644
--- a/arch/x86/kernel/apic/x2apic_phys.c
+++ b/arch/x86/kernel/apic/x2apic_phys.c
@@ -146,10 +146,7 @@ x2apic_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
                         break;
         }
 
-        if (cpu < nr_cpu_ids)
-                return per_cpu(x86_cpu_to_apicid, cpu);
-
-        return BAD_APICID;
+        return per_cpu(x86_cpu_to_apicid, cpu);
 }
 
 static unsigned int x2apic_phys_get_apic_id(unsigned long x)
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index b684bb303cbf..d56b0efb2057 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -225,10 +225,7 @@ uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
                 if (cpumask_test_cpu(cpu, cpu_online_mask))
                         break;
         }
-        if (cpu < nr_cpu_ids)
-                return per_cpu(x86_cpu_to_apicid, cpu);
-
-        return BAD_APICID;
+        return per_cpu(x86_cpu_to_apicid, cpu);
 }
 
 static unsigned int x2apic_get_apic_id(unsigned long x)
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 8dc3ea145c97..e485825130d2 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -254,59 +254,36 @@ static int __cpuinit nearby_node(int apicid)
 
 /*
  * Fixup core topology information for AMD multi-node processors.
- * Assumption 1: Number of cores in each internal node is the same.
- * Assumption 2: Mixed systems with both single-node and dual-node
- *               processors are not supported.
+ * Assumption: Number of cores in each internal node is the same.
  */
 #ifdef CONFIG_X86_HT
 static void __cpuinit amd_fixup_dcm(struct cpuinfo_x86 *c)
 {
-#ifdef CONFIG_PCI
-        u32 t, cpn;
-        u8 n, n_id;
+        unsigned long long value;
+        u32 nodes, cores_per_node;
         int cpu = smp_processor_id();
 
+        if (!cpu_has(c, X86_FEATURE_NODEID_MSR))
+                return;
+
         /* fixup topology information only once for a core */
         if (cpu_has(c, X86_FEATURE_AMD_DCM))
                 return;
 
-        /* check for multi-node processor on boot cpu */
-        t = read_pci_config(0, 24, 3, 0xe8);
-        if (!(t & (1 << 29)))
+        rdmsrl(MSR_FAM10H_NODE_ID, value);
+
+        nodes = ((value >> 3) & 7) + 1;
+        if (nodes == 1)
                 return;
 
         set_cpu_cap(c, X86_FEATURE_AMD_DCM);
+        cores_per_node = c->x86_max_cores / nodes;
 
-        /* cores per node: each internal node has half the number of cores */
-        cpn = c->x86_max_cores >> 1;
+        /* store NodeID, use llc_shared_map to store sibling info */
+        per_cpu(cpu_llc_id, cpu) = value & 7;
 
-        /* even-numbered NB_id of this dual-node processor */
-        n = c->phys_proc_id << 1;
-
-        /*
-         * determine internal node id and assign cores fifty-fifty to
-         * each node of the dual-node processor
-         */
-        t = read_pci_config(0, 24 + n, 3, 0xe8);
-        n = (t>>30) & 0x3;
-        if (n == 0) {
-                if (c->cpu_core_id < cpn)
-                        n_id = 0;
-                else
-                        n_id = 1;
-        } else {
-                if (c->cpu_core_id < cpn)
-                        n_id = 1;
-                else
-                        n_id = 0;
-        }
-
-        /* compute entire NodeID, use llc_shared_map to store sibling info */
-        per_cpu(cpu_llc_id, cpu) = (c->phys_proc_id << 1) + n_id;
-
-        /* fixup core id to be in range from 0 to cpn */
-        c->cpu_core_id = c->cpu_core_id % cpn;
-#endif
+        /* fixup core id to be in range from 0 to (cores_per_node - 1) */
+        c->cpu_core_id = c->cpu_core_id % cores_per_node;
 }
 #endif
 
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
index a9df9441a9a2..f125e5c551c0 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
@@ -1136,7 +1136,7 @@ static int powernowk8_target(struct cpufreq_policy *pol,
         if (!alloc_cpumask_var(&oldmask, GFP_KERNEL))
                 return -ENOMEM;
 
-        cpumask_copy(oldmask, tsk_cpumask(current));
+        cpumask_copy(oldmask, tsk_cpus_allowed(current));
         set_cpus_allowed_ptr(current, cpumask_of(pol->cpu));
 
         if (smp_processor_id() != pol->cpu) {
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 9c31e8b09d2c..879666f4d871 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -70,7 +70,6 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
         if (c->x86_power & (1 << 8)) {
                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
                 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
-                set_cpu_cap(c, X86_FEATURE_TSC_RELIABLE);
                 sched_clock_stable = 1;
         }
 
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index 45506d5dd8df..c223b7e895d9 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -2336,6 +2336,7 @@ static const struct stacktrace_ops backtrace_ops = {
         .warning_symbol         = backtrace_warning_symbol,
         .stack                  = backtrace_stack,
         .address                = backtrace_address,
+        .walk_stack             = print_context_stack_bp,
 };
 
 #include "../dumpstack.h"
diff --git a/arch/x86/kernel/cpuid.c b/arch/x86/kernel/cpuid.c
index 7ef24a796992..cb27fd6136c9 100644
--- a/arch/x86/kernel/cpuid.c
+++ b/arch/x86/kernel/cpuid.c
@@ -187,7 +187,8 @@ static int __init cpuid_init(void)
         int i, err = 0;
         i = 0;
 
-        if (register_chrdev(CPUID_MAJOR, "cpu/cpuid", &cpuid_fops)) {
+        if (__register_chrdev(CPUID_MAJOR, 0, NR_CPUS,
+                              "cpu/cpuid", &cpuid_fops)) {
                 printk(KERN_ERR "cpuid: unable to get major %d for cpuid\n",
                        CPUID_MAJOR);
                 err = -EBUSY;
@@ -216,7 +217,7 @@ out_class:
         }
         class_destroy(cpuid_class);
 out_chrdev:
-        unregister_chrdev(CPUID_MAJOR, "cpu/cpuid");
+        __unregister_chrdev(CPUID_MAJOR, 0, NR_CPUS, "cpu/cpuid");
 out:
         return err;
 }
diff --git a/arch/x86/kernel/dumpstack.c b/arch/x86/kernel/dumpstack.c
index 0a0aa1cec8f1..c56bc2873030 100644
--- a/arch/x86/kernel/dumpstack.c
+++ b/arch/x86/kernel/dumpstack.c
@@ -109,6 +109,30 @@ print_context_stack(struct thread_info *tinfo,
         }
         return bp;
 }
+EXPORT_SYMBOL_GPL(print_context_stack);
+
+unsigned long
+print_context_stack_bp(struct thread_info *tinfo,
+                       unsigned long *stack, unsigned long bp,
+                       const struct stacktrace_ops *ops, void *data,
+                       unsigned long *end, int *graph)
+{
+        struct stack_frame *frame = (struct stack_frame *)bp;
+        unsigned long *ret_addr = &frame->return_address;
+
+        while (valid_stack_ptr(tinfo, ret_addr, sizeof(*ret_addr), end)) {
+                unsigned long addr = *ret_addr;
+
+                if (__kernel_text_address(addr)) {
+                        ops->address(data, addr, 1);
+                        frame = frame->next_frame;
+                        ret_addr = &frame->return_address;
+                        print_ftrace_graph_addr(addr, data, ops, tinfo, graph);
+                }
+        }
+        return (unsigned long)frame;
+}
+EXPORT_SYMBOL_GPL(print_context_stack_bp);
 
 
 static void
@@ -141,10 +165,11 @@ static void print_trace_address(void *data, unsigned long addr, int reliable)
 }
 
 static const struct stacktrace_ops print_trace_ops = {
-        .warning = print_trace_warning,
-        .warning_symbol = print_trace_warning_symbol,
-        .stack = print_trace_stack,
-        .address = print_trace_address,
+        .warning                = print_trace_warning,
+        .warning_symbol         = print_trace_warning_symbol,
+        .stack                  = print_trace_stack,
+        .address                = print_trace_address,
+        .walk_stack             = print_context_stack,
 };
 
 void
diff --git a/arch/x86/kernel/dumpstack.h b/arch/x86/kernel/dumpstack.h
index 81086c227ab7..4fd1420faffa 100644
--- a/arch/x86/kernel/dumpstack.h
+++ b/arch/x86/kernel/dumpstack.h
@@ -14,12 +14,6 @@
 #define get_bp(bp) asm("movq %%rbp, %0" : "=r" (bp) :)
 #endif
 
-extern unsigned long
-print_context_stack(struct thread_info *tinfo,
-                unsigned long *stack, unsigned long bp,
-                const struct stacktrace_ops *ops, void *data,
-                unsigned long *end, int *graph);
-
 extern void
 show_trace_log_lvl(struct task_struct *task, struct pt_regs *regs,
                 unsigned long *stack, unsigned long bp, char *log_lvl);
diff --git a/arch/x86/kernel/dumpstack_32.c b/arch/x86/kernel/dumpstack_32.c
index e0ed4c7abb62..ae775ca47b25 100644
--- a/arch/x86/kernel/dumpstack_32.c
+++ b/arch/x86/kernel/dumpstack_32.c
@@ -58,7 +58,7 @@ void dump_trace(struct task_struct *task, struct pt_regs *regs,
 
                 context = (struct thread_info *)
                         ((unsigned long)stack & (~(THREAD_SIZE - 1)));
-                bp = print_context_stack(context, stack, bp, ops, data, NULL, &graph);
+                bp = ops->walk_stack(context, stack, bp, ops, data, NULL, &graph);
 
                 stack = (unsigned long *)context->previous_esp;
                 if (!stack)
diff --git a/arch/x86/kernel/dumpstack_64.c b/arch/x86/kernel/dumpstack_64.c
index b13af53883aa..0ad9597073f5 100644
--- a/arch/x86/kernel/dumpstack_64.c
+++ b/arch/x86/kernel/dumpstack_64.c
@@ -188,8 +188,8 @@ void dump_trace(struct task_struct *task, struct pt_regs *regs,
                         if (ops->stack(data, id) < 0)
                                 break;
 
-                        bp = print_context_stack(tinfo, stack, bp, ops,
-                                                 data, estack_end, &graph);
+                        bp = ops->walk_stack(tinfo, stack, bp, ops,
+                                             data, estack_end, &graph);
                         ops->stack(data, "<EOE>");
                         /*
                          * We link to the next stack via the
diff --git a/arch/x86/kernel/e820.c b/arch/x86/kernel/e820.c
index f50447d961c0..05ed7ab2ca48 100644
--- a/arch/x86/kernel/e820.c
+++ b/arch/x86/kernel/e820.c
@@ -724,7 +724,7 @@ core_initcall(e820_mark_nvs_memory);
 /*
  * Early reserved memory areas.
  */
-#define MAX_EARLY_RES 20
+#define MAX_EARLY_RES 32
 
 struct early_res {
         u64 start, end;
diff --git a/arch/x86/kernel/microcode_core.c b/arch/x86/kernel/microcode_core.c
index 844c02c65fcb..0c8632433090 100644
--- a/arch/x86/kernel/microcode_core.c
+++ b/arch/x86/kernel/microcode_core.c
@@ -394,7 +394,7 @@ static enum ucode_state microcode_update_cpu(int cpu)
         struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
         enum ucode_state ustate;
 
-        if (uci->valid && uci->mc)
+        if (uci->valid)
                 ustate = microcode_resume_cpu(cpu);
         else
                 ustate = microcode_init_cpu(cpu);
diff --git a/arch/x86/kernel/msr.c b/arch/x86/kernel/msr.c
index 572b07eee3f4..4bd93c9b2b27 100644
--- a/arch/x86/kernel/msr.c
+++ b/arch/x86/kernel/msr.c
@@ -246,7 +246,7 @@ static int __init msr_init(void)
         int i, err = 0;
         i = 0;
 
-        if (register_chrdev(MSR_MAJOR, "cpu/msr", &msr_fops)) {
+        if (__register_chrdev(MSR_MAJOR, 0, NR_CPUS, "cpu/msr", &msr_fops)) {
                 printk(KERN_ERR "msr: unable to get major %d for msr\n",
                        MSR_MAJOR);
                 err = -EBUSY;
@@ -274,7 +274,7 @@ out_class:
                 msr_device_destroy(i);
         class_destroy(msr_class);
 out_chrdev:
-        unregister_chrdev(MSR_MAJOR, "cpu/msr");
+        __unregister_chrdev(MSR_MAJOR, 0, NR_CPUS, "cpu/msr");
 out:
         return err;
 }
diff --git a/arch/x86/kernel/ptrace.c b/arch/x86/kernel/ptrace.c
index 2779321046bd..017d937639fe 100644
--- a/arch/x86/kernel/ptrace.c
+++ b/arch/x86/kernel/ptrace.c
@@ -509,14 +509,14 @@ static int genregs_get(struct task_struct *target,
 {
         if (kbuf) {
                 unsigned long *k = kbuf;
-                while (count > 0) {
+                while (count >= sizeof(*k)) {
                         *k++ = getreg(target, pos);
                         count -= sizeof(*k);
                         pos += sizeof(*k);
                 }
         } else {
                 unsigned long __user *u = ubuf;
-                while (count > 0) {
+                while (count >= sizeof(*u)) {
                         if (__put_user(getreg(target, pos), u++))
                                 return -EFAULT;
                         count -= sizeof(*u);
@@ -535,14 +535,14 @@ static int genregs_set(struct task_struct *target,
         int ret = 0;
         if (kbuf) {
                 const unsigned long *k = kbuf;
-                while (count > 0 && !ret) {
+                while (count >= sizeof(*k) && !ret) {
                         ret = putreg(target, pos, *k++);
                         count -= sizeof(*k);
                         pos += sizeof(*k);
                 }
         } else {
                 const unsigned long  __user *u = ubuf;
-                while (count > 0 && !ret) {
+                while (count >= sizeof(*u) && !ret) {
                         unsigned long word;
                         ret = __get_user(word, u++);
                         if (ret)
@@ -1458,14 +1458,14 @@ static int genregs32_get(struct task_struct *target,
 {
         if (kbuf) {
                 compat_ulong_t *k = kbuf;
-                while (count > 0) {
+                while (count >= sizeof(*k)) {
                         getreg32(target, pos, k++);
                         count -= sizeof(*k);
                         pos += sizeof(*k);
                 }
         } else {
                 compat_ulong_t __user *u = ubuf;
-                while (count > 0) {
+                while (count >= sizeof(*u)) {
                         compat_ulong_t word;
                         getreg32(target, pos, &word);
                         if (__put_user(word, u++))
@@ -1486,14 +1486,14 @@ static int genregs32_set(struct task_struct *target,
         int ret = 0;
         if (kbuf) {
                 const compat_ulong_t *k = kbuf;
-                while (count > 0 && !ret) {
+                while (count >= sizeof(*k) && !ret) {
                         ret = putreg32(target, pos, *k++);
                         count -= sizeof(*k);
                         pos += sizeof(*k);
                 }
         } else {
                 const compat_ulong_t __user *u = ubuf;
-                while (count > 0 && !ret) {
+                while (count >= sizeof(*u) && !ret) {
                         compat_ulong_t word;
                         ret = __get_user(word, u++);
                         if (ret)
diff --git a/arch/x86/kernel/stacktrace.c b/arch/x86/kernel/stacktrace.c
index c3eb207181fe..922eefbb3f6c 100644
--- a/arch/x86/kernel/stacktrace.c
+++ b/arch/x86/kernel/stacktrace.c
@@ -53,17 +53,19 @@ save_stack_address_nosched(void *data, unsigned long addr, int reliable)
 }
 
 static const struct stacktrace_ops save_stack_ops = {
-        .warning = save_stack_warning,
-        .warning_symbol = save_stack_warning_symbol,
-        .stack = save_stack_stack,
-        .address = save_stack_address,
+        .warning        = save_stack_warning,
+        .warning_symbol = save_stack_warning_symbol,
+        .stack          = save_stack_stack,
+        .address        = save_stack_address,
+        .walk_stack     = print_context_stack,
 };
 
 static const struct stacktrace_ops save_stack_ops_nosched = {
-        .warning = save_stack_warning,
-        .warning_symbol = save_stack_warning_symbol,
-        .stack = save_stack_stack,
-        .address = save_stack_address_nosched,
+        .warning        = save_stack_warning,
+        .warning_symbol = save_stack_warning_symbol,
+        .stack          = save_stack_stack,
+        .address        = save_stack_address_nosched,
+        .walk_stack     = print_context_stack,
 };
 
 /*
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index cd982f48e23e..597683aa5ba0 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -763,6 +763,7 @@ void mark_tsc_unstable(char *reason)
 {
         if (!tsc_unstable) {
                 tsc_unstable = 1;
+                sched_clock_stable = 0;
                 printk(KERN_INFO "Marking TSC unstable due to %s\n", reason);
                 /* Change only the rating, when not registered */
                 if (clocksource_tsc.mult)
diff --git a/arch/x86/kernel/uv_irq.c b/arch/x86/kernel/uv_irq.c
index 61d805df4c91..ece73d8e3240 100644
--- a/arch/x86/kernel/uv_irq.c
+++ b/arch/x86/kernel/uv_irq.c
@@ -215,8 +215,7 @@ static int uv_set_irq_affinity(unsigned int irq, const struct cpumask *mask)
         unsigned long mmr_offset;
         unsigned mmr_pnode;
 
-        dest = set_desc_affinity(desc, mask);
-        if (dest == BAD_APICID)
+        if (set_desc_affinity(desc, mask, &dest))
                 return -1;
 
         mmr_value = 0;
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 45b20e486c2f..cffd754f3039 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -14,7 +14,7 @@ $(obj)/inat.o: $(obj)/inat-tables.c
 
 clean-files := inat-tables.c
 
-obj-$(CONFIG_SMP) := msr.o
+obj-$(CONFIG_SMP) += msr-smp.o
 
 lib-y := delay.o
 lib-y += thunk_$(BITS).o
@@ -22,7 +22,7 @@ lib-y += usercopy_$(BITS).o getuser.o putuser.o
 lib-y += memcpy_$(BITS).o
 lib-$(CONFIG_KPROBES) += insn.o inat.o
 
-obj-y += msr-reg.o msr-reg-export.o
+obj-y += msr.o msr-reg.o msr-reg-export.o
 
 ifeq ($(CONFIG_X86_32),y)
         obj-y += atomic64_32.o
diff --git a/arch/x86/lib/msr-smp.c b/arch/x86/lib/msr-smp.c
new file mode 100644
index 000000000000..a6b1b86d2253
--- /dev/null
+++ b/arch/x86/lib/msr-smp.c
@@ -0,0 +1,204 @@
+#include <linux/module.h>
+#include <linux/preempt.h>
+#include <linux/smp.h>
+#include <asm/msr.h>
+
+static void __rdmsr_on_cpu(void *info)
+{
+        struct msr_info *rv = info;
+        struct msr *reg;
+        int this_cpu = raw_smp_processor_id();
+
+        if (rv->msrs)
+                reg = per_cpu_ptr(rv->msrs, this_cpu);
+        else
+                reg = &rv->reg;
+
+        rdmsr(rv->msr_no, reg->l, reg->h);
+}
+
+static void __wrmsr_on_cpu(void *info)
+{
+        struct msr_info *rv = info;
+        struct msr *reg;
+        int this_cpu = raw_smp_processor_id();
+
+        if (rv->msrs)
+                reg = per_cpu_ptr(rv->msrs, this_cpu);
+        else
+                reg = &rv->reg;
+
+        wrmsr(rv->msr_no, reg->l, reg->h);
+}
+
+int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
+{
+        int err;
+        struct msr_info rv;
+
+        memset(&rv, 0, sizeof(rv));
+
+        rv.msr_no = msr_no;
+        err = smp_call_function_single(cpu, __rdmsr_on_cpu, &rv, 1);
+        *l = rv.reg.l;
+        *h = rv.reg.h;
+
+        return err;
+}
+EXPORT_SYMBOL(rdmsr_on_cpu);
+
+int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
+{
+        int err;
+        struct msr_info rv;
+
+        memset(&rv, 0, sizeof(rv));
+
+        rv.msr_no = msr_no;
+        rv.reg.l = l;
+        rv.reg.h = h;
+        err = smp_call_function_single(cpu, __wrmsr_on_cpu, &rv, 1);
+
+        return err;
+}
+EXPORT_SYMBOL(wrmsr_on_cpu);
+
+static void __rwmsr_on_cpus(const struct cpumask *mask, u32 msr_no,
+                            struct msr *msrs,
+                            void (*msr_func) (void *info))
+{
+        struct msr_info rv;
+        int this_cpu;
+
+        memset(&rv, 0, sizeof(rv));
+
+        rv.msrs   = msrs;
+        rv.msr_no = msr_no;
+
+        this_cpu = get_cpu();
+
+        if (cpumask_test_cpu(this_cpu, mask))
+                msr_func(&rv);
+
+        smp_call_function_many(mask, msr_func, &rv, 1);
+        put_cpu();
+}
+
+/* rdmsr on a bunch of CPUs
+ *
+ * @mask:       which CPUs
+ * @msr_no:     which MSR
+ * @msrs:       array of MSR values
+ *
+ */
+void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs)
+{
+        __rwmsr_on_cpus(mask, msr_no, msrs, __rdmsr_on_cpu);
+}
+EXPORT_SYMBOL(rdmsr_on_cpus);
+
+/*
+ * wrmsr on a bunch of CPUs
+ *
+ * @mask:       which CPUs
+ * @msr_no:     which MSR
+ * @msrs:       array of MSR values
+ *
+ */
+void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs)
+{
+        __rwmsr_on_cpus(mask, msr_no, msrs, __wrmsr_on_cpu);
+}
+EXPORT_SYMBOL(wrmsr_on_cpus);
+
+/* These "safe" variants are slower and should be used when the target MSR
+   may not actually exist. */
+static void __rdmsr_safe_on_cpu(void *info)
+{
+        struct msr_info *rv = info;
+
+        rv->err = rdmsr_safe(rv->msr_no, &rv->reg.l, &rv->reg.h);
+}
+
+static void __wrmsr_safe_on_cpu(void *info)
+{
+        struct msr_info *rv = info;
+
+        rv->err = wrmsr_safe(rv->msr_no, rv->reg.l, rv->reg.h);
+}
+
+int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
+{
+        int err;
+        struct msr_info rv;
+
+        memset(&rv, 0, sizeof(rv));
+
+        rv.msr_no = msr_no;
+        err = smp_call_function_single(cpu, __rdmsr_safe_on_cpu, &rv, 1);
+        *l = rv.reg.l;
+        *h = rv.reg.h;
+
+        return err ? err : rv.err;
+}
+EXPORT_SYMBOL(rdmsr_safe_on_cpu);
+
+int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
+{
+        int err;
+        struct msr_info rv;
+
+        memset(&rv, 0, sizeof(rv));
+
+        rv.msr_no = msr_no;
+        rv.reg.l = l;
+        rv.reg.h = h;
+        err = smp_call_function_single(cpu, __wrmsr_safe_on_cpu, &rv, 1);
+
+        return err ? err : rv.err;
+}
+EXPORT_SYMBOL(wrmsr_safe_on_cpu);
+
+/*
+ * These variants are significantly slower, but allows control over
+ * the entire 32-bit GPR set.
+ */
+static void __rdmsr_safe_regs_on_cpu(void *info)
+{
+        struct msr_regs_info *rv = info;
+
+        rv->err = rdmsr_safe_regs(rv->regs);
+}
+
+static void __wrmsr_safe_regs_on_cpu(void *info)
+{
+        struct msr_regs_info *rv = info;
+
+        rv->err = wrmsr_safe_regs(rv->regs);
+}
+
+int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 *regs)
+{
+        int err;
+        struct msr_regs_info rv;
+
+        rv.regs   = regs;
+        rv.err    = -EIO;
+        err = smp_call_function_single(cpu, __rdmsr_safe_regs_on_cpu, &rv, 1);
+
+        return err ? err : rv.err;
+}
+EXPORT_SYMBOL(rdmsr_safe_regs_on_cpu);
+
+int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 *regs)
+{
+        int err;
+        struct msr_regs_info rv;
+
+        rv.regs = regs;
+        rv.err  = -EIO;
+        err = smp_call_function_single(cpu, __wrmsr_safe_regs_on_cpu, &rv, 1);
+
+        return err ? err : rv.err;
+}
+EXPORT_SYMBOL(wrmsr_safe_regs_on_cpu);
diff --git a/arch/x86/lib/msr.c b/arch/x86/lib/msr.c
index 872834177937..8f8eebdca7d4 100644
--- a/arch/x86/lib/msr.c
+++ b/arch/x86/lib/msr.c
@@ -1,123 +1,7 @@
 #include <linux/module.h>
 #include <linux/preempt.h>
-#include <linux/smp.h>
 #include <asm/msr.h>
 
-struct msr_info {
-        u32 msr_no;
-        struct msr reg;
-        struct msr *msrs;
-        int err;
-};
-
-static void __rdmsr_on_cpu(void *info)
-{
-        struct msr_info *rv = info;
-        struct msr *reg;
-        int this_cpu = raw_smp_processor_id();
-
-        if (rv->msrs)
-                reg = per_cpu_ptr(rv->msrs, this_cpu);
-        else
-                reg = &rv->reg;
-
-        rdmsr(rv->msr_no, reg->l, reg->h);
-}
-
-static void __wrmsr_on_cpu(void *info)
-{
-        struct msr_info *rv = info;
-        struct msr *reg;
-        int this_cpu = raw_smp_processor_id();
-
-        if (rv->msrs)
-                reg = per_cpu_ptr(rv->msrs, this_cpu);
-        else
-                reg = &rv->reg;
-
-        wrmsr(rv->msr_no, reg->l, reg->h);
-}
-
-int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
-{
-        int err;
-        struct msr_info rv;
-
-        memset(&rv, 0, sizeof(rv));
-
-        rv.msr_no = msr_no;
-        err = smp_call_function_single(cpu, __rdmsr_on_cpu, &rv, 1);
-        *l = rv.reg.l;
-        *h = rv.reg.h;
-
-        return err;
-}
-EXPORT_SYMBOL(rdmsr_on_cpu);
-
-int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
-{
-        int err;
-        struct msr_info rv;
-
-        memset(&rv, 0, sizeof(rv));
-
-        rv.msr_no = msr_no;
-        rv.reg.l = l;
-        rv.reg.h = h;
-        err = smp_call_function_single(cpu, __wrmsr_on_cpu, &rv, 1);
-
-        return err;
-}
-EXPORT_SYMBOL(wrmsr_on_cpu);
-
-static void __rwmsr_on_cpus(const struct cpumask *mask, u32 msr_no,
-                            struct msr *msrs,
-                            void (*msr_func) (void *info))
-{
-        struct msr_info rv;
-        int this_cpu;
-
-        memset(&rv, 0, sizeof(rv));
-
-        rv.msrs   = msrs;
-        rv.msr_no = msr_no;
-
-        this_cpu = get_cpu();
-
-        if (cpumask_test_cpu(this_cpu, mask))
-                msr_func(&rv);
-
-        smp_call_function_many(mask, msr_func, &rv, 1);
-        put_cpu();
-}
-
-/* rdmsr on a bunch of CPUs
- *
- * @mask:       which CPUs
- * @msr_no:     which MSR
- * @msrs:       array of MSR values
- *
- */
-void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs)
-{
-        __rwmsr_on_cpus(mask, msr_no, msrs, __rdmsr_on_cpu);
-}
-EXPORT_SYMBOL(rdmsr_on_cpus);
-
-/*
- * wrmsr on a bunch of CPUs
- *
- * @mask:       which CPUs
- * @msr_no:     which MSR
- * @msrs:       array of MSR values
- *
- */
-void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs)
-{
-        __rwmsr_on_cpus(mask, msr_no, msrs, __wrmsr_on_cpu);
-}
-EXPORT_SYMBOL(wrmsr_on_cpus);
-
 struct msr *msrs_alloc(void)
 {
         struct msr *msrs = NULL;
@@ -137,100 +21,3 @@ void msrs_free(struct msr *msrs)
         free_percpu(msrs);
 }
 EXPORT_SYMBOL(msrs_free);
-
-/* These "safe" variants are slower and should be used when the target MSR
-   may not actually exist. */
-static void __rdmsr_safe_on_cpu(void *info)
-{
-        struct msr_info *rv = info;
-
-        rv->err = rdmsr_safe(rv->msr_no, &rv->reg.l, &rv->reg.h);
-}
-
-static void __wrmsr_safe_on_cpu(void *info)
-{
-        struct msr_info *rv = info;
-
-        rv->err = wrmsr_safe(rv->msr_no, rv->reg.l, rv->reg.h);
-}
-
-int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
-{
-        int err;
-        struct msr_info rv;
-
-        memset(&rv, 0, sizeof(rv));
-
-        rv.msr_no = msr_no;
-        err = smp_call_function_single(cpu, __rdmsr_safe_on_cpu, &rv, 1);
-        *l = rv.reg.l;
-        *h = rv.reg.h;
-
-        return err ? err : rv.err;
-}
-EXPORT_SYMBOL(rdmsr_safe_on_cpu);
-
-int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
-{
-        int err;
-        struct msr_info rv;
-
-        memset(&rv, 0, sizeof(rv));
-
-        rv.msr_no = msr_no;
-        rv.reg.l = l;
-        rv.reg.h = h;
-        err = smp_call_function_single(cpu, __wrmsr_safe_on_cpu, &rv, 1);
-
-        return err ? err : rv.err;
-}
-EXPORT_SYMBOL(wrmsr_safe_on_cpu);
-
-/*
- * These variants are significantly slower, but allows control over
- * the entire 32-bit GPR set.
- */
-struct msr_regs_info {
-        u32 *regs;
-        int err;
-};
-
-static void __rdmsr_safe_regs_on_cpu(void *info)
-{
-        struct msr_regs_info *rv = info;
-
-        rv->err = rdmsr_safe_regs(rv->regs);
-}
-
-static void __wrmsr_safe_regs_on_cpu(void *info)
-{
-        struct msr_regs_info *rv = info;
-
-        rv->err = wrmsr_safe_regs(rv->regs);
-}
-
-int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 *regs)
-{
-        int err;
-        struct msr_regs_info rv;
-
-        rv.regs   = regs;
-        rv.err    = -EIO;
-        err = smp_call_function_single(cpu, __rdmsr_safe_regs_on_cpu, &rv, 1);
-
-        return err ? err : rv.err;
-}
-EXPORT_SYMBOL(rdmsr_safe_regs_on_cpu);
-
-int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 *regs)
-{
-        int err;
-        struct msr_regs_info rv;
-
-        rv.regs = regs;
-        rv.err  = -EIO;
-        err = smp_call_function_single(cpu, __wrmsr_safe_regs_on_cpu, &rv, 1);
-
-        return err ? err : rv.err;
-}
-EXPORT_SYMBOL(wrmsr_safe_regs_on_cpu);
diff --git a/arch/x86/mm/srat_32.c b/arch/x86/mm/srat_32.c
index 6f8aa33031c7..9324f13492d5 100644
--- a/arch/x86/mm/srat_32.c
+++ b/arch/x86/mm/srat_32.c
@@ -267,6 +267,8 @@ int __init get_memcfg_from_srat(void)
                 e820_register_active_regions(chunk->nid, chunk->start_pfn,
                                              min(chunk->end_pfn, max_pfn));
         }
+        /* for out of order entries in SRAT */
+        sort_node_map();
 
         for_each_online_node(nid) {
                 unsigned long start = node_start_pfn[nid];
diff --git a/arch/x86/mm/srat_64.c b/arch/x86/mm/srat_64.c
index d89075489664..a27124185fc1 100644
--- a/arch/x86/mm/srat_64.c
+++ b/arch/x86/mm/srat_64.c
@@ -317,7 +317,7 @@ static int __init nodes_cover_memory(const struct bootnode *nodes)
                 unsigned long s = nodes[i].start >> PAGE_SHIFT;
                 unsigned long e = nodes[i].end >> PAGE_SHIFT;
                 pxmram += e - s;
-                pxmram -= absent_pages_in_range(s, e);
+                pxmram -= __absent_pages_in_range(i, s, e);
                 if ((long)pxmram < 0)
                         pxmram = 0;
         }
@@ -373,6 +373,8 @@ int __init acpi_scan_nodes(unsigned long start, unsigned long end)
         for_each_node_mask(i, nodes_parsed)
                 e820_register_active_regions(i, nodes[i].start >> PAGE_SHIFT,
                                                 nodes[i].end >> PAGE_SHIFT);
+        /* for out of order entries in SRAT */
+        sort_node_map();
         if (!nodes_cover_memory(nodes)) {
                 bad_srat();
                 return -1;
diff --git a/arch/x86/oprofile/backtrace.c b/arch/x86/oprofile/backtrace.c
index 044897be021f..3855096c59b8 100644
--- a/arch/x86/oprofile/backtrace.c
+++ b/arch/x86/oprofile/backtrace.c
@@ -41,10 +41,11 @@ static void backtrace_address(void *data, unsigned long addr, int reliable)
 }
 
 static struct stacktrace_ops backtrace_ops = {
-        .warning = backtrace_warning,
-        .warning_symbol = backtrace_warning_symbol,
-        .stack = backtrace_stack,
-        .address = backtrace_address,
+        .warning        = backtrace_warning,
+        .warning_symbol = backtrace_warning_symbol,
+        .stack          = backtrace_stack,
+        .address        = backtrace_address,
+        .walk_stack     = print_context_stack,
 };
 
 struct frame_head {
diff --git a/arch/x86/tools/chkobjdump.awk b/arch/x86/tools/chkobjdump.awk
index 0d13cd9fdcff..5bbb5a33f220 100644
--- a/arch/x86/tools/chkobjdump.awk
+++ b/arch/x86/tools/chkobjdump.awk
@@ -9,7 +9,7 @@ BEGIN {
 }
 
 /^GNU/ {
-        split($4, ver, ".");
+        split($3, ver, ".");
         if (ver[1] > od_ver ||
             (ver[1] == od_ver && ver[2] >= od_sver)) {
                 exit 1;
diff --git a/arch/x86/tools/gen-insn-attr-x86.awk b/arch/x86/tools/gen-insn-attr-x86.awk
index 7a6850683c34..eaf11f52fc0b 100644
--- a/arch/x86/tools/gen-insn-attr-x86.awk
+++ b/arch/x86/tools/gen-insn-attr-x86.awk
@@ -6,8 +6,6 @@
 
 # Awk implementation sanity check
 function check_awk_implement() {
-        if (!match("abc", "[[:lower:]]+"))
-                return "Your awk doesn't support charactor-class."
         if (sprintf("%x", 0) != "0")
                 return "Your awk has a printf-format problem."
         return ""
@@ -44,12 +42,12 @@ BEGIN {
         delete gtable
         delete atable
 
-        opnd_expr = "^[[:alpha:]/]"
+        opnd_expr = "^[A-Za-z/]"
         ext_expr = "^\\("
         sep_expr = "^\\|$"
-        group_expr = "^Grp[[:alnum:]]+"
+        group_expr = "^Grp[0-9A-Za-z]+"
 
-        imm_expr = "^[IJAO][[:lower:]]"
+        imm_expr = "^[IJAO][a-z]"
         imm_flag["Ib"] = "INAT_MAKE_IMM(INAT_IMM_BYTE)"
         imm_flag["Jb"] = "INAT_MAKE_IMM(INAT_IMM_BYTE)"
         imm_flag["Iw"] = "INAT_MAKE_IMM(INAT_IMM_WORD)"
@@ -62,7 +60,7 @@ BEGIN {
         imm_flag["Ob"] = "INAT_MOFFSET"
         imm_flag["Ov"] = "INAT_MOFFSET"
 
-        modrm_expr = "^([CDEGMNPQRSUVW/][[:lower:]]+|NTA|T[012])"
+        modrm_expr = "^([CDEGMNPQRSUVW/][a-z]+|NTA|T[012])"
         force64_expr = "\\([df]64\\)"
         rex_expr = "^REX(\\.[XRWB]+)*"
         fpu_expr = "^ESC" # TODO
diff --git a/arch/xtensa/include/asm/asm-offsets.h b/arch/xtensa/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/xtensa/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>