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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-05-11 12:59:50 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-05-11 12:59:50 -0400
commitf2c60ed038dedcc43a0eb3ef4e0602741ba90384 (patch)
tree1d06b6c080e1c164d87b66f8cc4b13203378b85a /arch
parentcabca0cb0d0e8579428d8f8c3f606e2f01d26d14 (diff)
parent3f2d560e9029ec0b7edf8be0c32425f4bb57d582 (diff)
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (28 commits) [MIPS] Rework cobalt_board_id [MIPS] Use RTC_CMOS for Cobalt [MIPS] Use platform_device for Cobalt UART [MIPS] Separate Alchemy processor based boards config [MIPS] Fix build error in atomic64_cmpxchg [MIPS] Run checksyscalls for N32 and O32 ABI [MIPS] tlbex: use __maybe_unused [MIPS] excite: use __maybe_unused [MIPS] Add extern cobalt_board_id [MIPS] Remove unused CONFIG_TOSHIBA_BOARDS [MIPS] Rename tb0229_defconfig to tb0219_defconfig [MIPS] Update tb0229_defconfig; add CONFIG_GPIO_TB0219. [MIPS] Add minimum defconfig for RBHMA4200 [MIPS] SB1: Build fix. [MIPS] Drop __devinit tag from allocate_irqno() and free_irqno() [MIPS] clocksource: use CLOCKSOURCE_MASK() macro [MIPS] Remove LIMITED_DMA support [MIPS] Remove Momenco Jaguar ATX support [MIPS] Remove Momenco Ocelot G support [MIPS] FPU hazard handling ...
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/Kconfig212
-rw-r--r--arch/mips/Makefile42
-rw-r--r--arch/mips/au1000/Kconfig142
-rw-r--r--arch/mips/basler/excite/excite_device.c16
-rw-r--r--arch/mips/cobalt/Makefile2
-rw-r--r--arch/mips/cobalt/rtc.c63
-rw-r--r--arch/mips/cobalt/serial.c85
-rw-r--r--arch/mips/cobalt/setup.c31
-rw-r--r--arch/mips/configs/cobalt_defconfig49
-rw-r--r--arch/mips/configs/db1000_defconfig1
-rw-r--r--arch/mips/configs/db1100_defconfig1
-rw-r--r--arch/mips/configs/db1200_defconfig1
-rw-r--r--arch/mips/configs/db1500_defconfig1
-rw-r--r--arch/mips/configs/db1550_defconfig1
-rw-r--r--arch/mips/configs/jaguar-atx_defconfig897
-rw-r--r--arch/mips/configs/jmr3927_defconfig1
-rw-r--r--arch/mips/configs/pb1100_defconfig1
-rw-r--r--arch/mips/configs/pb1500_defconfig1
-rw-r--r--arch/mips/configs/pb1550_defconfig1
-rw-r--r--arch/mips/configs/rbhma4200_defconfig (renamed from arch/mips/configs/ocelot_g_defconfig)379
-rw-r--r--arch/mips/configs/rbhma4500_defconfig1
-rw-r--r--arch/mips/configs/tb0219_defconfig (renamed from arch/mips/configs/tb0229_defconfig)24
-rw-r--r--arch/mips/kernel/early_printk.c11
-rw-r--r--arch/mips/kernel/irq-msc01.c10
-rw-r--r--arch/mips/kernel/irq.c4
-rw-r--r--arch/mips/kernel/time.c2
-rw-r--r--arch/mips/kernel/traps.c8
-rw-r--r--arch/mips/lib/Makefile2
-rw-r--r--arch/mips/lib/ucmpdi2.c19
-rw-r--r--arch/mips/mips-boards/malta/malta_int.c21
-rw-r--r--arch/mips/mm/highmem.c2
-rw-r--r--arch/mips/mm/init.c3
-rw-r--r--arch/mips/mm/tlbex.c36
-rw-r--r--arch/mips/momentum/Kconfig6
-rw-r--r--arch/mips/momentum/jaguar_atx/Makefile12
-rw-r--r--arch/mips/momentum/jaguar_atx/dbg_io.c125
-rw-r--r--arch/mips/momentum/jaguar_atx/irq.c94
-rw-r--r--arch/mips/momentum/jaguar_atx/ja-console.c101
-rw-r--r--arch/mips/momentum/jaguar_atx/jaguar_atx_fpga.h54
-rw-r--r--arch/mips/momentum/jaguar_atx/platform.c208
-rw-r--r--arch/mips/momentum/jaguar_atx/prom.c210
-rw-r--r--arch/mips/momentum/jaguar_atx/reset.c56
-rw-r--r--arch/mips/momentum/jaguar_atx/setup.c475
-rw-r--r--arch/mips/momentum/ocelot_g/Makefile6
-rw-r--r--arch/mips/momentum/ocelot_g/dbg_io.c121
-rw-r--r--arch/mips/momentum/ocelot_g/gt-irq.c212
-rw-r--r--arch/mips/momentum/ocelot_g/irq.c101
-rw-r--r--arch/mips/momentum/ocelot_g/ocelot_pld.h30
-rw-r--r--arch/mips/momentum/ocelot_g/prom.c84
-rw-r--r--arch/mips/momentum/ocelot_g/reset.c47
-rw-r--r--arch/mips/momentum/ocelot_g/setup.c267
-rw-r--r--arch/mips/pci/Makefile2
-rw-r--r--arch/mips/pci/fixup-cobalt.c25
-rw-r--r--arch/mips/pci/fixup-jaguar.c43
-rw-r--r--arch/mips/pci/fixup-ocelot-g.c37
-rw-r--r--arch/mips/pci/pci-ocelot-g.c97
56 files changed, 636 insertions, 3847 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 16ecea3c0813..0f09412e1b7f 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -15,121 +15,8 @@ choice
15 prompt "System type" 15 prompt "System type"
16 default SGI_IP22 16 default SGI_IP22
17 17
18config MIPS_MTX1 18config MACH_ALCHEMY
19 bool "4G Systems MTX-1 board" 19 bool "Alchemy processor based machines"
20 select DMA_NONCOHERENT
21 select HW_HAS_PCI
22 select RESOURCES_64BIT if PCI
23 select SOC_AU1500
24 select SYS_HAS_CPU_MIPS32_R1
25 select SYS_SUPPORTS_LITTLE_ENDIAN
26
27config MIPS_BOSPORUS
28 bool "AMD Alchemy Bosporus board"
29 select SOC_AU1500
30 select DMA_NONCOHERENT
31 select SYS_HAS_CPU_MIPS32_R1
32 select SYS_SUPPORTS_LITTLE_ENDIAN
33
34config MIPS_PB1000
35 bool "AMD Alchemy PB1000 board"
36 select SOC_AU1000
37 select DMA_NONCOHERENT
38 select HW_HAS_PCI
39 select RESOURCES_64BIT if PCI
40 select SWAP_IO_SPACE
41 select SYS_HAS_CPU_MIPS32_R1
42 select SYS_SUPPORTS_LITTLE_ENDIAN
43
44config MIPS_PB1100
45 bool "AMD Alchemy PB1100 board"
46 select SOC_AU1100
47 select DMA_NONCOHERENT
48 select HW_HAS_PCI
49 select RESOURCES_64BIT if PCI
50 select SWAP_IO_SPACE
51 select SYS_HAS_CPU_MIPS32_R1
52 select SYS_SUPPORTS_LITTLE_ENDIAN
53
54config MIPS_PB1500
55 bool "AMD Alchemy PB1500 board"
56 select SOC_AU1500
57 select DMA_NONCOHERENT
58 select HW_HAS_PCI
59 select RESOURCES_64BIT if PCI
60 select SYS_HAS_CPU_MIPS32_R1
61 select SYS_SUPPORTS_LITTLE_ENDIAN
62
63config MIPS_PB1550
64 bool "AMD Alchemy PB1550 board"
65 select SOC_AU1550
66 select DMA_NONCOHERENT
67 select HW_HAS_PCI
68 select MIPS_DISABLE_OBSOLETE_IDE
69 select RESOURCES_64BIT if PCI
70 select SYS_HAS_CPU_MIPS32_R1
71 select SYS_SUPPORTS_LITTLE_ENDIAN
72
73config MIPS_PB1200
74 bool "AMD Alchemy PB1200 board"
75 select SOC_AU1200
76 select DMA_NONCOHERENT
77 select MIPS_DISABLE_OBSOLETE_IDE
78 select RESOURCES_64BIT if PCI
79 select SYS_HAS_CPU_MIPS32_R1
80 select SYS_SUPPORTS_LITTLE_ENDIAN
81
82config MIPS_DB1000
83 bool "AMD Alchemy DB1000 board"
84 select SOC_AU1000
85 select DMA_NONCOHERENT
86 select HW_HAS_PCI
87 select RESOURCES_64BIT if PCI
88 select SYS_HAS_CPU_MIPS32_R1
89 select SYS_SUPPORTS_LITTLE_ENDIAN
90
91config MIPS_DB1100
92 bool "AMD Alchemy DB1100 board"
93 select SOC_AU1100
94 select DMA_NONCOHERENT
95 select SYS_HAS_CPU_MIPS32_R1
96 select SYS_SUPPORTS_LITTLE_ENDIAN
97
98config MIPS_DB1500
99 bool "AMD Alchemy DB1500 board"
100 select SOC_AU1500
101 select DMA_NONCOHERENT
102 select HW_HAS_PCI
103 select MIPS_DISABLE_OBSOLETE_IDE
104 select RESOURCES_64BIT if PCI
105 select SYS_HAS_CPU_MIPS32_R1
106 select SYS_SUPPORTS_BIG_ENDIAN
107 select SYS_SUPPORTS_LITTLE_ENDIAN
108
109config MIPS_DB1550
110 bool "AMD Alchemy DB1550 board"
111 select SOC_AU1550
112 select HW_HAS_PCI
113 select DMA_NONCOHERENT
114 select MIPS_DISABLE_OBSOLETE_IDE
115 select RESOURCES_64BIT if PCI
116 select SYS_HAS_CPU_MIPS32_R1
117 select SYS_SUPPORTS_LITTLE_ENDIAN
118
119config MIPS_DB1200
120 bool "AMD Alchemy DB1200 board"
121 select SOC_AU1200
122 select DMA_COHERENT
123 select MIPS_DISABLE_OBSOLETE_IDE
124 select SYS_HAS_CPU_MIPS32_R1
125 select SYS_SUPPORTS_LITTLE_ENDIAN
126
127config MIPS_MIRAGE
128 bool "AMD Alchemy Mirage board"
129 select DMA_NONCOHERENT
130 select SOC_AU1500
131 select SYS_HAS_CPU_MIPS32_R1
132 select SYS_SUPPORTS_LITTLE_ENDIAN
133 20
134config BASLER_EXCITE 21config BASLER_EXCITE
135 bool "Basler eXcite smart camera" 22 bool "Basler eXcite smart camera"
@@ -369,28 +256,6 @@ config MIPS_SIM
369 This option enables support for MIPS Technologies MIPSsim software 256 This option enables support for MIPS Technologies MIPSsim software
370 emulator. 257 emulator.
371 258
372config MOMENCO_JAGUAR_ATX
373 bool "Momentum Jaguar board"
374 select BOOT_ELF32
375 select DMA_NONCOHERENT
376 select HW_HAS_PCI
377 select IRQ_CPU
378 select IRQ_CPU_RM7K
379 select IRQ_MV64340
380 select LIMITED_DMA
381 select PCI_MARVELL
382 select RM7000_CPU_SCACHE
383 select SWAP_IO_SPACE
384 select SYS_HAS_CPU_RM9000
385 select SYS_HAS_EARLY_PRINTK
386 select SYS_SUPPORTS_32BIT_KERNEL
387 select SYS_SUPPORTS_64BIT_KERNEL
388 select SYS_SUPPORTS_BIG_ENDIAN
389 select SYS_SUPPORTS_KGDB
390 help
391 The Jaguar ATX is a MIPS-based Single Board Computer (SBC) made by
392 Momentum Computer <http://www.momenco.com/>.
393
394config MOMENCO_OCELOT 259config MOMENCO_OCELOT
395 bool "Momentum Ocelot board" 260 bool "Momentum Ocelot board"
396 select DMA_NONCOHERENT 261 select DMA_NONCOHERENT
@@ -446,29 +311,6 @@ config MOMENCO_OCELOT_C
446 The Ocelot is a MIPS-based Single Board Computer (SBC) made by 311 The Ocelot is a MIPS-based Single Board Computer (SBC) made by
447 Momentum Computer <http://www.momenco.com/>. 312 Momentum Computer <http://www.momenco.com/>.
448 313
449config MOMENCO_OCELOT_G
450 bool "Momentum Ocelot-G board"
451 select DMA_NONCOHERENT
452 select HW_HAS_PCI
453 select IRQ_CPU
454 select IRQ_CPU_RM7K
455 select PCI_MARVELL
456 select RM7000_CPU_SCACHE
457 select SWAP_IO_SPACE
458 select SYS_HAS_CPU_RM7000
459 select SYS_SUPPORTS_32BIT_KERNEL
460 select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
461 select SYS_SUPPORTS_BIG_ENDIAN
462 help
463 The Ocelot is a MIPS-based Single Board Computer (SBC) made by
464 Momentum Computer <http://www.momenco.com/>.
465
466config MIPS_XXS1500
467 bool "MyCable XXS1500 board"
468 select DMA_NONCOHERENT
469 select SOC_AU1500
470 select SYS_SUPPORTS_LITTLE_ENDIAN
471
472config PNX8550_JBS 314config PNX8550_JBS
473 bool "Philips PNX8550 based JBS board" 315 bool "Philips PNX8550 based JBS board"
474 select PNX8550 316 select PNX8550
@@ -775,7 +617,6 @@ config TOSHIBA_JMR3927
775 select SYS_SUPPORTS_32BIT_KERNEL 617 select SYS_SUPPORTS_32BIT_KERNEL
776 select SYS_SUPPORTS_LITTLE_ENDIAN 618 select SYS_SUPPORTS_LITTLE_ENDIAN
777 select SYS_SUPPORTS_BIG_ENDIAN 619 select SYS_SUPPORTS_BIG_ENDIAN
778 select TOSHIBA_BOARDS
779 select GENERIC_HARDIRQS_NO__DO_IRQ 620 select GENERIC_HARDIRQS_NO__DO_IRQ
780 621
781config TOSHIBA_RBTX4927 622config TOSHIBA_RBTX4927
@@ -791,7 +632,6 @@ config TOSHIBA_RBTX4927
791 select SYS_SUPPORTS_LITTLE_ENDIAN 632 select SYS_SUPPORTS_LITTLE_ENDIAN
792 select SYS_SUPPORTS_BIG_ENDIAN 633 select SYS_SUPPORTS_BIG_ENDIAN
793 select SYS_SUPPORTS_KGDB 634 select SYS_SUPPORTS_KGDB
794 select TOSHIBA_BOARDS
795 select GENERIC_HARDIRQS_NO__DO_IRQ 635 select GENERIC_HARDIRQS_NO__DO_IRQ
796 help 636 help
797 This Toshiba board is based on the TX4927 processor. Say Y here to 637 This Toshiba board is based on the TX4927 processor. Say Y here to
@@ -811,7 +651,6 @@ config TOSHIBA_RBTX4938
811 select SYS_SUPPORTS_LITTLE_ENDIAN 651 select SYS_SUPPORTS_LITTLE_ENDIAN
812 select SYS_SUPPORTS_BIG_ENDIAN 652 select SYS_SUPPORTS_BIG_ENDIAN
813 select SYS_SUPPORTS_KGDB 653 select SYS_SUPPORTS_KGDB
814 select TOSHIBA_BOARDS
815 select GENERIC_HARDIRQS_NO__DO_IRQ 654 select GENERIC_HARDIRQS_NO__DO_IRQ
816 help 655 help
817 This Toshiba board is based on the TX4938 processor. Say Y here to 656 This Toshiba board is based on the TX4938 processor. Say Y here to
@@ -819,11 +658,11 @@ config TOSHIBA_RBTX4938
819 658
820endchoice 659endchoice
821 660
661source "arch/mips/au1000/Kconfig"
822source "arch/mips/ddb5xxx/Kconfig" 662source "arch/mips/ddb5xxx/Kconfig"
823source "arch/mips/gt64120/ev64120/Kconfig" 663source "arch/mips/gt64120/ev64120/Kconfig"
824source "arch/mips/jazz/Kconfig" 664source "arch/mips/jazz/Kconfig"
825source "arch/mips/lasat/Kconfig" 665source "arch/mips/lasat/Kconfig"
826source "arch/mips/momentum/Kconfig"
827source "arch/mips/pmc-sierra/Kconfig" 666source "arch/mips/pmc-sierra/Kconfig"
828source "arch/mips/sgi-ip27/Kconfig" 667source "arch/mips/sgi-ip27/Kconfig"
829source "arch/mips/sibyte/Kconfig" 668source "arch/mips/sibyte/Kconfig"
@@ -923,11 +762,6 @@ config GENERIC_ISA_DMA
923config I8259 762config I8259
924 bool 763 bool
925 764
926config LIMITED_DMA
927 bool
928 select HIGHMEM
929 select SYS_SUPPORTS_HIGHMEM
930
931config MIPS_BONITO64 765config MIPS_BONITO64
932 bool 766 bool
933 767
@@ -1013,33 +847,6 @@ config MIPS_RM9122
1013config PCI_MARVELL 847config PCI_MARVELL
1014 bool 848 bool
1015 849
1016config SOC_AU1000
1017 bool
1018 select SOC_AU1X00
1019
1020config SOC_AU1100
1021 bool
1022 select SOC_AU1X00
1023
1024config SOC_AU1500
1025 bool
1026 select SOC_AU1X00
1027
1028config SOC_AU1550
1029 bool
1030 select SOC_AU1X00
1031
1032config SOC_AU1200
1033 bool
1034 select SOC_AU1X00
1035
1036config SOC_AU1X00
1037 bool
1038 select SYS_HAS_CPU_MIPS32_R1
1039 select SYS_SUPPORTS_32BIT_KERNEL
1040 select SYS_SUPPORTS_APM_EMULATION
1041 select SYS_SUPPORTS_KGDB
1042
1043config SERIAL_RM9000 850config SERIAL_RM9000
1044 bool 851 bool
1045 852
@@ -1081,9 +888,9 @@ config WDT_RM9000
1081choice 888choice
1082 prompt "Galileo Chip Clock" 889 prompt "Galileo Chip Clock"
1083 #default SYSCLK_83 if MIPS_EV64120 890 #default SYSCLK_83 if MIPS_EV64120
1084 depends on MIPS_EV64120 || MOMENCO_OCELOT || MOMENCO_OCELOT_G 891 depends on MIPS_EV64120 || MOMENCO_OCELOT
1085 default SYSCLK_83 if MIPS_EV64120 892 default SYSCLK_83 if MIPS_EV64120
1086 default SYSCLK_100 if MOMENCO_OCELOT || MOMENCO_OCELOT_G 893 default SYSCLK_100 if MOMENCO_OCELOT
1087 894
1088config SYSCLK_75 895config SYSCLK_75
1089 bool "75" if MIPS_EV64120 896 bool "75" if MIPS_EV64120
@@ -1092,7 +899,7 @@ config SYSCLK_83
1092 bool "83.3" if MIPS_EV64120 899 bool "83.3" if MIPS_EV64120
1093 900
1094config SYSCLK_100 901config SYSCLK_100
1095 bool "100" if MIPS_EV64120 || MOMENCO_OCELOT || MOMENCO_OCELOT_G 902 bool "100" if MIPS_EV64120 || MOMENCO_OCELOT
1096 903
1097endchoice 904endchoice
1098 905
@@ -1131,9 +938,6 @@ config ARC64
1131config BOOT_ELF64 938config BOOT_ELF64
1132 bool 939 bool
1133 940
1134config TOSHIBA_BOARDS
1135 bool
1136
1137menu "CPU selection" 941menu "CPU selection"
1138 942
1139choice 943choice
@@ -1557,6 +1361,7 @@ config MIPS_MT_SMP
1557 bool "Use 1 TC on each available VPE for SMP" 1361 bool "Use 1 TC on each available VPE for SMP"
1558 depends on SYS_SUPPORTS_MULTITHREADING 1362 depends on SYS_SUPPORTS_MULTITHREADING
1559 select CPU_MIPSR2_IRQ_VI 1363 select CPU_MIPSR2_IRQ_VI
1364 select CPU_MIPSR2_IRQ_EI
1560 select CPU_MIPSR2_SRS 1365 select CPU_MIPSR2_SRS
1561 select MIPS_MT 1366 select MIPS_MT
1562 select NR_CPUS_DEFAULT_2 1367 select NR_CPUS_DEFAULT_2
@@ -1572,6 +1377,7 @@ config MIPS_MT_SMTC
1572 #depends on CPU_MIPS64_R2 # once there is hardware ... 1377 #depends on CPU_MIPS64_R2 # once there is hardware ...
1573 depends on SYS_SUPPORTS_MULTITHREADING 1378 depends on SYS_SUPPORTS_MULTITHREADING
1574 select CPU_MIPSR2_IRQ_VI 1379 select CPU_MIPSR2_IRQ_VI
1380 select CPU_MIPSR2_IRQ_EI
1575 select CPU_MIPSR2_SRS 1381 select CPU_MIPSR2_SRS
1576 select MIPS_MT 1382 select MIPS_MT
1577 select NR_CPUS_DEFAULT_8 1383 select NR_CPUS_DEFAULT_8
@@ -1584,6 +1390,8 @@ config MIPS_MT_SMTC
1584config MIPS_VPE_LOADER 1390config MIPS_VPE_LOADER
1585 bool "VPE loader support." 1391 bool "VPE loader support."
1586 depends on SYS_SUPPORTS_MULTITHREADING 1392 depends on SYS_SUPPORTS_MULTITHREADING
1393 select CPU_MIPSR2_IRQ_VI
1394 select CPU_MIPSR2_IRQ_EI
1587 select MIPS_MT 1395 select MIPS_MT
1588 help 1396 help
1589 Includes a loader for loading an elf relocatable object 1397 Includes a loader for loading an elf relocatable object
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 4892db88a86a..f450066b6241 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -343,15 +343,6 @@ cflags-$(CONFIG_MOMENCO_OCELOT) += -Iinclude/asm-mips/mach-ocelot
343load-$(CONFIG_MOMENCO_OCELOT) += 0xffffffff80100000 343load-$(CONFIG_MOMENCO_OCELOT) += 0xffffffff80100000
344 344
345# 345#
346# Momentum Ocelot-G board
347#
348# The Ocelot-G setup.o must be linked early - it does the ioremap() for the
349# mips_io_port_base.
350#
351core-$(CONFIG_MOMENCO_OCELOT_G) += arch/mips/momentum/ocelot_g/
352load-$(CONFIG_MOMENCO_OCELOT_G) += 0xffffffff80100000
353
354#
355# Momentum Ocelot-C and -CS boards 346# Momentum Ocelot-C and -CS boards
356# 347#
357# The Ocelot-C[S] setup.o must be linked early - it does the ioremap() for the 348# The Ocelot-C[S] setup.o must be linked early - it does the ioremap() for the
@@ -388,17 +379,6 @@ cflags-$(CONFIG_BASLER_EXCITE) += -Iinclude/asm-mips/mach-excite
388load-$(CONFIG_BASLER_EXCITE) += 0x80100000 379load-$(CONFIG_BASLER_EXCITE) += 0x80100000
389 380
390# 381#
391# Momentum Jaguar ATX
392#
393core-$(CONFIG_MOMENCO_JAGUAR_ATX) += arch/mips/momentum/jaguar_atx/
394cflags-$(CONFIG_MOMENCO_JAGUAR_ATX) += -Iinclude/asm-mips/mach-ja
395#ifdef CONFIG_JAGUAR_DMALOW
396#load-$(CONFIG_MOMENCO_JAGUAR_ATX) += 0xffffffff88000000
397#else
398load-$(CONFIG_MOMENCO_JAGUAR_ATX) += 0xffffffff80100000
399#endif
400
401#
402# NEC DDB 382# NEC DDB
403# 383#
404core-$(CONFIG_DDB5XXX_COMMON) += arch/mips/ddb5xxx/common/ 384core-$(CONFIG_DDB5XXX_COMMON) += arch/mips/ddb5xxx/common/
@@ -729,3 +709,25 @@ archclean:
729CLEAN_FILES += vmlinux.32 \ 709CLEAN_FILES += vmlinux.32 \
730 vmlinux.64 \ 710 vmlinux.64 \
731 vmlinux.ecoff 711 vmlinux.ecoff
712
713quiet_cmd_syscalls_n32 = CALL-N32 $<
714 cmd_syscalls_n32 = $(CONFIG_SHELL) $< $(CC) $(c_flags) -mabi=n32
715
716quiet_cmd_syscalls_o32 = CALL-O32 $<
717 cmd_syscalls_o32 = $(CONFIG_SHELL) $< $(CC) $(c_flags) -mabi=32
718
719PHONY += missing-syscalls-n32 missing-syscalls-o32
720
721missing-syscalls-n32: scripts/checksyscalls.sh FORCE
722 $(call cmd,syscalls_n32)
723
724missing-syscalls-o32: scripts/checksyscalls.sh FORCE
725 $(call cmd,syscalls_o32)
726
727archprepare:
728ifdef CONFIG_MIPS32_N32
729 $(Q)$(MAKE) $(build)=arch/mips missing-syscalls-n32
730endif
731ifdef CONFIG_MIPS32_O32
732 $(Q)$(MAKE) $(build)=arch/mips missing-syscalls-o32
733endif
diff --git a/arch/mips/au1000/Kconfig b/arch/mips/au1000/Kconfig
new file mode 100644
index 000000000000..abea88098253
--- /dev/null
+++ b/arch/mips/au1000/Kconfig
@@ -0,0 +1,142 @@
1choice
2 prompt "Machine type"
3 depends on MACH_ALCHEMY
4 default MIPS_DB1000
5
6config MIPS_MTX1
7 bool "4G Systems MTX-1 board"
8 select DMA_NONCOHERENT
9 select HW_HAS_PCI
10 select RESOURCES_64BIT if PCI
11 select SOC_AU1500
12 select SYS_SUPPORTS_LITTLE_ENDIAN
13
14config MIPS_BOSPORUS
15 bool "Alchemy Bosporus board"
16 select SOC_AU1500
17 select DMA_NONCOHERENT
18 select SYS_SUPPORTS_LITTLE_ENDIAN
19
20config MIPS_DB1000
21 bool "Alchemy DB1000 board"
22 select SOC_AU1000
23 select DMA_NONCOHERENT
24 select HW_HAS_PCI
25 select RESOURCES_64BIT if PCI
26 select SYS_SUPPORTS_LITTLE_ENDIAN
27
28config MIPS_DB1100
29 bool "Alchemy DB1100 board"
30 select SOC_AU1100
31 select DMA_NONCOHERENT
32 select SYS_SUPPORTS_LITTLE_ENDIAN
33
34config MIPS_DB1200
35 bool "Alchemy DB1200 board"
36 select SOC_AU1200
37 select DMA_COHERENT
38 select MIPS_DISABLE_OBSOLETE_IDE
39 select SYS_SUPPORTS_LITTLE_ENDIAN
40
41config MIPS_DB1500
42 bool "Alchemy DB1500 board"
43 select SOC_AU1500
44 select DMA_NONCOHERENT
45 select HW_HAS_PCI
46 select MIPS_DISABLE_OBSOLETE_IDE
47 select RESOURCES_64BIT if PCI
48 select SYS_SUPPORTS_BIG_ENDIAN
49 select SYS_SUPPORTS_LITTLE_ENDIAN
50
51config MIPS_DB1550
52 bool "Alchemy DB1550 board"
53 select SOC_AU1550
54 select HW_HAS_PCI
55 select DMA_NONCOHERENT
56 select MIPS_DISABLE_OBSOLETE_IDE
57 select RESOURCES_64BIT if PCI
58 select SYS_SUPPORTS_LITTLE_ENDIAN
59
60config MIPS_MIRAGE
61 bool "Alchemy Mirage board"
62 select DMA_NONCOHERENT
63 select SOC_AU1500
64 select SYS_SUPPORTS_LITTLE_ENDIAN
65
66config MIPS_PB1000
67 bool "Alchemy PB1000 board"
68 select SOC_AU1000
69 select DMA_NONCOHERENT
70 select HW_HAS_PCI
71 select RESOURCES_64BIT if PCI
72 select SWAP_IO_SPACE
73 select SYS_SUPPORTS_LITTLE_ENDIAN
74
75config MIPS_PB1100
76 bool "Alchemy PB1100 board"
77 select SOC_AU1100
78 select DMA_NONCOHERENT
79 select HW_HAS_PCI
80 select RESOURCES_64BIT if PCI
81 select SWAP_IO_SPACE
82 select SYS_SUPPORTS_LITTLE_ENDIAN
83
84config MIPS_PB1200
85 bool "Alchemy PB1200 board"
86 select SOC_AU1200
87 select DMA_NONCOHERENT
88 select MIPS_DISABLE_OBSOLETE_IDE
89 select RESOURCES_64BIT if PCI
90 select SYS_SUPPORTS_LITTLE_ENDIAN
91
92config MIPS_PB1500
93 bool "Alchemy PB1500 board"
94 select SOC_AU1500
95 select DMA_NONCOHERENT
96 select HW_HAS_PCI
97 select RESOURCES_64BIT if PCI
98 select SYS_SUPPORTS_LITTLE_ENDIAN
99
100config MIPS_PB1550
101 bool "Alchemy PB1550 board"
102 select SOC_AU1550
103 select DMA_NONCOHERENT
104 select HW_HAS_PCI
105 select MIPS_DISABLE_OBSOLETE_IDE
106 select RESOURCES_64BIT if PCI
107 select SYS_SUPPORTS_LITTLE_ENDIAN
108
109config MIPS_XXS1500
110 bool "MyCable XXS1500 board"
111 select DMA_NONCOHERENT
112 select SOC_AU1500
113 select SYS_SUPPORTS_LITTLE_ENDIAN
114
115endchoice
116
117config SOC_AU1000
118 bool
119 select SOC_AU1X00
120
121config SOC_AU1100
122 bool
123 select SOC_AU1X00
124
125config SOC_AU1500
126 bool
127 select SOC_AU1X00
128
129config SOC_AU1550
130 bool
131 select SOC_AU1X00
132
133config SOC_AU1200
134 bool
135 select SOC_AU1X00
136
137config SOC_AU1X00
138 bool
139 select SYS_HAS_CPU_MIPS32_R1
140 select SYS_SUPPORTS_32BIT_KERNEL
141 select SYS_SUPPORTS_APM_EMULATION
142 select SYS_SUPPORTS_KGDB
diff --git a/arch/mips/basler/excite/excite_device.c b/arch/mips/basler/excite/excite_device.c
index cc1ce77eab4a..e00bc2d7f301 100644
--- a/arch/mips/basler/excite/excite_device.c
+++ b/arch/mips/basler/excite/excite_device.c
@@ -68,7 +68,7 @@ enum {
68 68
69 69
70static struct resource 70static struct resource
71 excite_ctr_resource __attribute__((unused)) = { 71 excite_ctr_resource __maybe_unused = {
72 .name = "GPI counters", 72 .name = "GPI counters",
73 .start = 0, 73 .start = 0,
74 .end = 5, 74 .end = 5,
@@ -77,7 +77,7 @@ static struct resource
77 .sibling = NULL, 77 .sibling = NULL,
78 .child = NULL 78 .child = NULL
79 }, 79 },
80 excite_gpislice_resource __attribute__((unused)) = { 80 excite_gpislice_resource __maybe_unused = {
81 .name = "GPI slices", 81 .name = "GPI slices",
82 .start = 0, 82 .start = 0,
83 .end = 1, 83 .end = 1,
@@ -86,7 +86,7 @@ static struct resource
86 .sibling = NULL, 86 .sibling = NULL,
87 .child = NULL 87 .child = NULL
88 }, 88 },
89 excite_mdio_channel_resource __attribute__((unused)) = { 89 excite_mdio_channel_resource __maybe_unused = {
90 .name = "MDIO channels", 90 .name = "MDIO channels",
91 .start = 0, 91 .start = 0,
92 .end = 1, 92 .end = 1,
@@ -95,7 +95,7 @@ static struct resource
95 .sibling = NULL, 95 .sibling = NULL,
96 .child = NULL 96 .child = NULL
97 }, 97 },
98 excite_fifomem_resource __attribute__((unused)) = { 98 excite_fifomem_resource __maybe_unused = {
99 .name = "FIFO memory", 99 .name = "FIFO memory",
100 .start = 0, 100 .start = 0,
101 .end = 767, 101 .end = 767,
@@ -104,7 +104,7 @@ static struct resource
104 .sibling = NULL, 104 .sibling = NULL,
105 .child = NULL 105 .child = NULL
106 }, 106 },
107 excite_scram_resource __attribute__((unused)) = { 107 excite_scram_resource __maybe_unused = {
108 .name = "Scratch RAM", 108 .name = "Scratch RAM",
109 .start = EXCITE_PHYS_SCRAM, 109 .start = EXCITE_PHYS_SCRAM,
110 .end = EXCITE_PHYS_SCRAM + EXCITE_SIZE_SCRAM - 1, 110 .end = EXCITE_PHYS_SCRAM + EXCITE_SIZE_SCRAM - 1,
@@ -113,7 +113,7 @@ static struct resource
113 .sibling = NULL, 113 .sibling = NULL,
114 .child = NULL 114 .child = NULL
115 }, 115 },
116 excite_fpga_resource __attribute__((unused)) = { 116 excite_fpga_resource __maybe_unused = {
117 .name = "System FPGA", 117 .name = "System FPGA",
118 .start = EXCITE_PHYS_FPGA, 118 .start = EXCITE_PHYS_FPGA,
119 .end = EXCITE_PHYS_FPGA + EXCITE_SIZE_FPGA - 1, 119 .end = EXCITE_PHYS_FPGA + EXCITE_SIZE_FPGA - 1,
@@ -122,7 +122,7 @@ static struct resource
122 .sibling = NULL, 122 .sibling = NULL,
123 .child = NULL 123 .child = NULL
124 }, 124 },
125 excite_nand_resource __attribute__((unused)) = { 125 excite_nand_resource __maybe_unused = {
126 .name = "NAND flash control", 126 .name = "NAND flash control",
127 .start = EXCITE_PHYS_NAND, 127 .start = EXCITE_PHYS_NAND,
128 .end = EXCITE_PHYS_NAND + EXCITE_SIZE_NAND - 1, 128 .end = EXCITE_PHYS_NAND + EXCITE_SIZE_NAND - 1,
@@ -131,7 +131,7 @@ static struct resource
131 .sibling = NULL, 131 .sibling = NULL,
132 .child = NULL 132 .child = NULL
133 }, 133 },
134 excite_titan_resource __attribute__((unused)) = { 134 excite_titan_resource __maybe_unused = {
135 .name = "TITAN registers", 135 .name = "TITAN registers",
136 .start = EXCITE_PHYS_TITAN, 136 .start = EXCITE_PHYS_TITAN,
137 .end = EXCITE_PHYS_TITAN + EXCITE_SIZE_TITAN - 1, 137 .end = EXCITE_PHYS_TITAN + EXCITE_SIZE_TITAN - 1,
diff --git a/arch/mips/cobalt/Makefile b/arch/mips/cobalt/Makefile
index 9565b2104dcd..c292f80a8c74 100644
--- a/arch/mips/cobalt/Makefile
+++ b/arch/mips/cobalt/Makefile
@@ -2,7 +2,7 @@
2# Makefile for the Cobalt micro systems family specific parts of the kernel 2# Makefile for the Cobalt micro systems family specific parts of the kernel
3# 3#
4 4
5obj-y := irq.o reset.o setup.o buttons.o 5obj-y := buttons.o irq.o reset.o rtc.o serial.o setup.o
6 6
7obj-$(CONFIG_PCI) += pci.o 7obj-$(CONFIG_PCI) += pci.o
8obj-$(CONFIG_EARLY_PRINTK) += console.o 8obj-$(CONFIG_EARLY_PRINTK) += console.o
diff --git a/arch/mips/cobalt/rtc.c b/arch/mips/cobalt/rtc.c
new file mode 100644
index 000000000000..284daefc5c55
--- /dev/null
+++ b/arch/mips/cobalt/rtc.c
@@ -0,0 +1,63 @@
1/*
2 * Registration of Cobalt RTC platform device.
3 *
4 * Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/errno.h>
21#include <linux/init.h>
22#include <linux/ioport.h>
23#include <linux/platform_device.h>
24
25static struct resource cobalt_rtc_resource[] __initdata = {
26 {
27 .start = 0x70,
28 .end = 0x77,
29 .flags = IORESOURCE_IO,
30 },
31 {
32 .start = 8,
33 .end = 8,
34 .flags = IORESOURCE_IRQ,
35 },
36};
37
38static __init int cobalt_rtc_add(void)
39{
40 struct platform_device *pdev;
41 int retval;
42
43 pdev = platform_device_alloc("rtc_cmos", -1);
44 if (!pdev)
45 return -ENOMEM;
46
47 retval = platform_device_add_resources(pdev, cobalt_rtc_resource,
48 ARRAY_SIZE(cobalt_rtc_resource));
49 if (retval)
50 goto err_free_device;
51
52 retval = platform_device_add(pdev);
53 if (retval)
54 goto err_free_device;
55
56 return 0;
57
58err_free_device:
59 platform_device_put(pdev);
60
61 return retval;
62}
63device_initcall(cobalt_rtc_add);
diff --git a/arch/mips/cobalt/serial.c b/arch/mips/cobalt/serial.c
new file mode 100644
index 000000000000..c27116599a5f
--- /dev/null
+++ b/arch/mips/cobalt/serial.c
@@ -0,0 +1,85 @@
1/*
2 * Registration of Cobalt UART platform device.
3 *
4 * Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/errno.h>
21#include <linux/init.h>
22#include <linux/ioport.h>
23#include <linux/platform_device.h>
24#include <linux/serial_8250.h>
25
26#include <cobalt.h>
27
28static struct resource cobalt_uart_resource[] __initdata = {
29 {
30 .start = 0x1c800000,
31 .end = 0x1c800007,
32 .flags = IORESOURCE_MEM,
33 },
34 {
35 .start = COBALT_SERIAL_IRQ,
36 .end = COBALT_SERIAL_IRQ,
37 .flags = IORESOURCE_IRQ,
38 },
39};
40
41static struct plat_serial8250_port cobalt_serial8250_port[] = {
42 {
43 .irq = COBALT_SERIAL_IRQ,
44 .uartclk = 18432000,
45 .iotype = UPIO_MEM,
46 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
47 .mapbase = 0x1c800000,
48 },
49 {},
50};
51
52static __init int cobalt_uart_add(void)
53{
54 struct platform_device *pdev;
55 int retval;
56
57 /*
58 * Cobalt Qube1 and RAQ1 have no UART.
59 */
60 if (cobalt_board_id <= COBALT_BRD_ID_RAQ1)
61 return 0;
62
63 pdev = platform_device_alloc("serial8250", -1);
64 if (!pdev)
65 return -ENOMEM;
66
67 pdev->id = PLAT8250_DEV_PLATFORM;
68 pdev->dev.platform_data = cobalt_serial8250_port;
69
70 retval = platform_device_add_resources(pdev, cobalt_uart_resource, ARRAY_SIZE(cobalt_uart_resource));
71 if (retval)
72 goto err_free_device;
73
74 retval = platform_device_add(pdev);
75 if (retval)
76 goto err_free_device;
77
78 return 0;
79
80err_free_device:
81 platform_device_put(pdev);
82
83 return retval;
84}
85device_initcall(cobalt_uart_add);
diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c
index d0dd81790f74..7abe45e78425 100644
--- a/arch/mips/cobalt/setup.c
+++ b/arch/mips/cobalt/setup.c
@@ -10,11 +10,8 @@
10 * 10 *
11 */ 11 */
12#include <linux/interrupt.h> 12#include <linux/interrupt.h>
13#include <linux/pci.h>
14#include <linux/init.h> 13#include <linux/init.h>
15#include <linux/pm.h> 14#include <linux/pm.h>
16#include <linux/serial.h>
17#include <linux/serial_core.h>
18 15
19#include <asm/bootinfo.h> 16#include <asm/bootinfo.h>
20#include <asm/time.h> 17#include <asm/time.h>
@@ -27,9 +24,6 @@
27extern void cobalt_machine_restart(char *command); 24extern void cobalt_machine_restart(char *command);
28extern void cobalt_machine_halt(void); 25extern void cobalt_machine_halt(void);
29extern void cobalt_machine_power_off(void); 26extern void cobalt_machine_power_off(void);
30extern void cobalt_early_console(void);
31
32int cobalt_board_id;
33 27
34const char *get_system_type(void) 28const char *get_system_type(void)
35{ 29{
@@ -95,8 +89,6 @@ static struct resource cobalt_reserved_resources[] = {
95 89
96void __init plat_mem_setup(void) 90void __init plat_mem_setup(void)
97{ 91{
98 static struct uart_port uart;
99 unsigned int devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0);
100 int i; 92 int i;
101 93
102 _machine_restart = cobalt_machine_restart; 94 _machine_restart = cobalt_machine_restart;
@@ -111,29 +103,6 @@ void __init plat_mem_setup(void)
111 /* These resources have been reserved by VIA SuperI/O chip. */ 103 /* These resources have been reserved by VIA SuperI/O chip. */
112 for (i = 0; i < ARRAY_SIZE(cobalt_reserved_resources); i++) 104 for (i = 0; i < ARRAY_SIZE(cobalt_reserved_resources); i++)
113 request_resource(&ioport_resource, cobalt_reserved_resources + i); 105 request_resource(&ioport_resource, cobalt_reserved_resources + i);
114
115 /* Read the cobalt id register out of the PCI config space */
116 PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3));
117 cobalt_board_id = GT_READ(GT_PCI0_CFGDATA_OFS);
118 cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8);
119 cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id);
120
121 printk("Cobalt board ID: %d\n", cobalt_board_id);
122
123 if (cobalt_board_id > COBALT_BRD_ID_RAQ1) {
124#ifdef CONFIG_SERIAL_8250
125 uart.line = 0;
126 uart.type = PORT_UNKNOWN;
127 uart.uartclk = 18432000;
128 uart.irq = COBALT_SERIAL_IRQ;
129 uart.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF |
130 UPF_SKIP_TEST;
131 uart.iotype = UPIO_MEM;
132 uart.mapbase = 0x1c800000;
133
134 early_serial_setup(&uart);
135#endif
136 }
137} 106}
138 107
139/* 108/*
diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig
index ba593b510b76..631b2138ad68 100644
--- a/arch/mips/configs/cobalt_defconfig
+++ b/arch/mips/configs/cobalt_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.20 3# Linux kernel version: 2.6.21-rc7
4# Tue Feb 20 21:47:24 2007 4# Wed Apr 18 14:25:45 2007
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7 7
@@ -62,7 +62,6 @@ CONFIG_MIPS_COBALT=y
62# CONFIG_TOSHIBA_JMR3927 is not set 62# CONFIG_TOSHIBA_JMR3927 is not set
63# CONFIG_TOSHIBA_RBTX4927 is not set 63# CONFIG_TOSHIBA_RBTX4927 is not set
64# CONFIG_TOSHIBA_RBTX4938 is not set 64# CONFIG_TOSHIBA_RBTX4938 is not set
65CONFIG_EARLY_PRINTK=y
66CONFIG_RWSEM_GENERIC_SPINLOCK=y 65CONFIG_RWSEM_GENERIC_SPINLOCK=y
67# CONFIG_ARCH_HAS_ILOG2_U32 is not set 66# CONFIG_ARCH_HAS_ILOG2_U32 is not set
68# CONFIG_ARCH_HAS_ILOG2_U64 is not set 67# CONFIG_ARCH_HAS_ILOG2_U64 is not set
@@ -74,12 +73,14 @@ CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
74CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y 73CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
75CONFIG_DMA_NONCOHERENT=y 74CONFIG_DMA_NONCOHERENT=y
76CONFIG_DMA_NEED_PCI_MAP_STATE=y 75CONFIG_DMA_NEED_PCI_MAP_STATE=y
76CONFIG_EARLY_PRINTK=y
77CONFIG_SYS_HAS_EARLY_PRINTK=y
77CONFIG_I8259=y 78CONFIG_I8259=y
78# CONFIG_CPU_BIG_ENDIAN is not set 79# CONFIG_CPU_BIG_ENDIAN is not set
79CONFIG_CPU_LITTLE_ENDIAN=y 80CONFIG_CPU_LITTLE_ENDIAN=y
80CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y 81CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
81CONFIG_IRQ_CPU=y 82CONFIG_IRQ_CPU=y
82CONFIG_MIPS_GT64111=y 83CONFIG_PCI_GT64XXX_PCI0=y
83CONFIG_MIPS_L1_CACHE_SHIFT=5 84CONFIG_MIPS_L1_CACHE_SHIFT=5
84 85
85# 86#
@@ -179,6 +180,7 @@ CONFIG_SYSVIPC_SYSCTL=y
179# CONFIG_IKCONFIG is not set 180# CONFIG_IKCONFIG is not set
180CONFIG_SYSFS_DEPRECATED=y 181CONFIG_SYSFS_DEPRECATED=y
181CONFIG_RELAY=y 182CONFIG_RELAY=y
183# CONFIG_BLK_DEV_INITRD is not set
182# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 184# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
183CONFIG_SYSCTL=y 185CONFIG_SYSCTL=y
184CONFIG_EMBEDDED=y 186CONFIG_EMBEDDED=y
@@ -477,7 +479,6 @@ CONFIG_BLK_DEV_LOOP=y
477# CONFIG_BLK_DEV_NBD is not set 479# CONFIG_BLK_DEV_NBD is not set
478# CONFIG_BLK_DEV_SX8 is not set 480# CONFIG_BLK_DEV_SX8 is not set
479# CONFIG_BLK_DEV_RAM is not set 481# CONFIG_BLK_DEV_RAM is not set
480# CONFIG_BLK_DEV_INITRD is not set
481CONFIG_CDROM_PKTCDVD=y 482CONFIG_CDROM_PKTCDVD=y
482CONFIG_CDROM_PKTCDVD_BUFFERS=8 483CONFIG_CDROM_PKTCDVD_BUFFERS=8
483# CONFIG_CDROM_PKTCDVD_WCACHE is not set 484# CONFIG_CDROM_PKTCDVD_WCACHE is not set
@@ -518,7 +519,7 @@ CONFIG_BLK_DEV_IDEPCI=y
518# CONFIG_BLK_DEV_OPTI621 is not set 519# CONFIG_BLK_DEV_OPTI621 is not set
519CONFIG_BLK_DEV_IDEDMA_PCI=y 520CONFIG_BLK_DEV_IDEDMA_PCI=y
520# CONFIG_BLK_DEV_IDEDMA_FORCED is not set 521# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
521# CONFIG_IDEDMA_PCI_AUTO is not set 522# CONFIG_IDEDMA_ONLYDISK is not set
522# CONFIG_BLK_DEV_AEC62XX is not set 523# CONFIG_BLK_DEV_AEC62XX is not set
523# CONFIG_BLK_DEV_ALI15X3 is not set 524# CONFIG_BLK_DEV_ALI15X3 is not set
524# CONFIG_BLK_DEV_AMD74XX is not set 525# CONFIG_BLK_DEV_AMD74XX is not set
@@ -546,7 +547,6 @@ CONFIG_BLK_DEV_TC86C001=y
546# CONFIG_IDE_ARM is not set 547# CONFIG_IDE_ARM is not set
547CONFIG_BLK_DEV_IDEDMA=y 548CONFIG_BLK_DEV_IDEDMA=y
548# CONFIG_IDEDMA_IVB is not set 549# CONFIG_IDEDMA_IVB is not set
549# CONFIG_IDEDMA_AUTO is not set
550# CONFIG_BLK_DEV_HD is not set 550# CONFIG_BLK_DEV_HD is not set
551 551
552# 552#
@@ -779,7 +779,8 @@ CONFIG_LEGACY_PTY_COUNT=256
779# 779#
780# CONFIG_WATCHDOG is not set 780# CONFIG_WATCHDOG is not set
781# CONFIG_HW_RANDOM is not set 781# CONFIG_HW_RANDOM is not set
782CONFIG_RTC=y 782# CONFIG_RTC is not set
783# CONFIG_GEN_RTC is not set
783CONFIG_COBALT_LCD=y 784CONFIG_COBALT_LCD=y
784# CONFIG_DTLK is not set 785# CONFIG_DTLK is not set
785# CONFIG_R3964 is not set 786# CONFIG_R3964 is not set
@@ -815,6 +816,11 @@ CONFIG_COBALT_LCD=y
815# CONFIG_HWMON_VID is not set 816# CONFIG_HWMON_VID is not set
816 817
817# 818#
819# Multifunction device drivers
820#
821# CONFIG_MFD_SM501 is not set
822
823#
818# Multimedia devices 824# Multimedia devices
819# 825#
820# CONFIG_VIDEO_DEV is not set 826# CONFIG_VIDEO_DEV is not set
@@ -827,7 +833,7 @@ CONFIG_COBALT_LCD=y
827# 833#
828# Graphics support 834# Graphics support
829# 835#
830# CONFIG_FIRMWARE_EDID is not set 836# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
831# CONFIG_FB is not set 837# CONFIG_FB is not set
832 838
833# 839#
@@ -835,7 +841,6 @@ CONFIG_COBALT_LCD=y
835# 841#
836# CONFIG_VGA_CONSOLE is not set 842# CONFIG_VGA_CONSOLE is not set
837CONFIG_DUMMY_CONSOLE=y 843CONFIG_DUMMY_CONSOLE=y
838# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
839 844
840# 845#
841# Sound 846# Sound
@@ -894,7 +899,29 @@ CONFIG_USB_ARCH_HAS_EHCI=y
894# 899#
895# Real Time Clock 900# Real Time Clock
896# 901#
897# CONFIG_RTC_CLASS is not set 902CONFIG_RTC_LIB=y
903CONFIG_RTC_CLASS=y
904CONFIG_RTC_HCTOSYS=y
905CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
906# CONFIG_RTC_DEBUG is not set
907
908#
909# RTC interfaces
910#
911CONFIG_RTC_INTF_SYSFS=y
912CONFIG_RTC_INTF_PROC=y
913CONFIG_RTC_INTF_DEV=y
914# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
915
916#
917# RTC drivers
918#
919CONFIG_RTC_DRV_CMOS=y
920# CONFIG_RTC_DRV_DS1553 is not set
921# CONFIG_RTC_DRV_DS1742 is not set
922# CONFIG_RTC_DRV_M48T86 is not set
923# CONFIG_RTC_DRV_TEST is not set
924# CONFIG_RTC_DRV_V3020 is not set
898 925
899# 926#
900# DMA Engine support 927# DMA Engine support
diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig
index 0db6a8b37301..10f6af43753d 100644
--- a/arch/mips/configs/db1000_defconfig
+++ b/arch/mips/configs/db1000_defconfig
@@ -9,6 +9,7 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11CONFIG_ZONE_DMA=y 11CONFIG_ZONE_DMA=y
12CONFIG_MACH_ALCHEMY=y
12# CONFIG_MIPS_MTX1 is not set 13# CONFIG_MIPS_MTX1 is not set
13# CONFIG_MIPS_BOSPORUS is not set 14# CONFIG_MIPS_BOSPORUS is not set
14# CONFIG_MIPS_PB1000 is not set 15# CONFIG_MIPS_PB1000 is not set
diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig
index 162add97c5ef..4b0862927748 100644
--- a/arch/mips/configs/db1100_defconfig
+++ b/arch/mips/configs/db1100_defconfig
@@ -9,6 +9,7 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11CONFIG_ZONE_DMA=y 11CONFIG_ZONE_DMA=y
12CONFIG_MACH_ALCHEMY=y
12# CONFIG_MIPS_MTX1 is not set 13# CONFIG_MIPS_MTX1 is not set
13# CONFIG_MIPS_BOSPORUS is not set 14# CONFIG_MIPS_BOSPORUS is not set
14# CONFIG_MIPS_PB1000 is not set 15# CONFIG_MIPS_PB1000 is not set
diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig
index 82801ec43e6a..820659e810dc 100644
--- a/arch/mips/configs/db1200_defconfig
+++ b/arch/mips/configs/db1200_defconfig
@@ -9,6 +9,7 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11CONFIG_ZONE_DMA=y 11CONFIG_ZONE_DMA=y
12CONFIG_MACH_ALCHEMY=y
12# CONFIG_MIPS_MTX1 is not set 13# CONFIG_MIPS_MTX1 is not set
13# CONFIG_MIPS_BOSPORUS is not set 14# CONFIG_MIPS_BOSPORUS is not set
14# CONFIG_MIPS_PB1000 is not set 15# CONFIG_MIPS_PB1000 is not set
diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig
index 545f23094e13..4050b9b91bcb 100644
--- a/arch/mips/configs/db1500_defconfig
+++ b/arch/mips/configs/db1500_defconfig
@@ -9,6 +9,7 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11CONFIG_ZONE_DMA=y 11CONFIG_ZONE_DMA=y
12CONFIG_MACH_ALCHEMY=y
12# CONFIG_MIPS_MTX1 is not set 13# CONFIG_MIPS_MTX1 is not set
13# CONFIG_MIPS_BOSPORUS is not set 14# CONFIG_MIPS_BOSPORUS is not set
14# CONFIG_MIPS_PB1000 is not set 15# CONFIG_MIPS_PB1000 is not set
diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig
index 5bd3b4328e57..7b3519058ab8 100644
--- a/arch/mips/configs/db1550_defconfig
+++ b/arch/mips/configs/db1550_defconfig
@@ -9,6 +9,7 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11CONFIG_ZONE_DMA=y 11CONFIG_ZONE_DMA=y
12CONFIG_MACH_ALCHEMY=y
12# CONFIG_MIPS_MTX1 is not set 13# CONFIG_MIPS_MTX1 is not set
13# CONFIG_MIPS_BOSPORUS is not set 14# CONFIG_MIPS_BOSPORUS is not set
14# CONFIG_MIPS_PB1000 is not set 15# CONFIG_MIPS_PB1000 is not set
diff --git a/arch/mips/configs/jaguar-atx_defconfig b/arch/mips/configs/jaguar-atx_defconfig
deleted file mode 100644
index 083104daa2ca..000000000000
--- a/arch/mips/configs/jaguar-atx_defconfig
+++ /dev/null
@@ -1,897 +0,0 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.20
4# Tue Feb 20 21:47:33 2007
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11CONFIG_ZONE_DMA=y
12# CONFIG_MIPS_MTX1 is not set
13# CONFIG_MIPS_BOSPORUS is not set
14# CONFIG_MIPS_PB1000 is not set
15# CONFIG_MIPS_PB1100 is not set
16# CONFIG_MIPS_PB1500 is not set
17# CONFIG_MIPS_PB1550 is not set
18# CONFIG_MIPS_PB1200 is not set
19# CONFIG_MIPS_DB1000 is not set
20# CONFIG_MIPS_DB1100 is not set
21# CONFIG_MIPS_DB1500 is not set
22# CONFIG_MIPS_DB1550 is not set
23# CONFIG_MIPS_DB1200 is not set
24# CONFIG_MIPS_MIRAGE is not set
25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set
34# CONFIG_WR_PPMC is not set
35# CONFIG_MIPS_SIM is not set
36CONFIG_MOMENCO_JAGUAR_ATX=y
37# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set
43# CONFIG_PNX8550_STB810 is not set
44# CONFIG_DDB5477 is not set
45# CONFIG_MACH_VR41XX is not set
46# CONFIG_PMC_YOSEMITE is not set
47# CONFIG_QEMU is not set
48# CONFIG_MARKEINS is not set
49# CONFIG_SGI_IP22 is not set
50# CONFIG_SGI_IP27 is not set
51# CONFIG_SGI_IP32 is not set
52# CONFIG_SIBYTE_BIGSUR is not set
53# CONFIG_SIBYTE_SWARM is not set
54# CONFIG_SIBYTE_SENTOSA is not set
55# CONFIG_SIBYTE_RHONE is not set
56# CONFIG_SIBYTE_CARMEL is not set
57# CONFIG_SIBYTE_PTSWARM is not set
58# CONFIG_SIBYTE_LITTLESUR is not set
59# CONFIG_SIBYTE_CRHINE is not set
60# CONFIG_SIBYTE_CRHONE is not set
61# CONFIG_SNI_RM is not set
62# CONFIG_TOSHIBA_JMR3927 is not set
63# CONFIG_TOSHIBA_RBTX4927 is not set
64# CONFIG_TOSHIBA_RBTX4938 is not set
65CONFIG_JAGUAR_DMALOW=y
66CONFIG_RWSEM_GENERIC_SPINLOCK=y
67# CONFIG_ARCH_HAS_ILOG2_U32 is not set
68# CONFIG_ARCH_HAS_ILOG2_U64 is not set
69CONFIG_GENERIC_FIND_NEXT_BIT=y
70CONFIG_GENERIC_HWEIGHT=y
71CONFIG_GENERIC_CALIBRATE_DELAY=y
72CONFIG_GENERIC_TIME=y
73CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
74# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
75CONFIG_DMA_NONCOHERENT=y
76CONFIG_DMA_NEED_PCI_MAP_STATE=y
77CONFIG_LIMITED_DMA=y
78CONFIG_CPU_BIG_ENDIAN=y
79# CONFIG_CPU_LITTLE_ENDIAN is not set
80CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
81CONFIG_IRQ_CPU=y
82CONFIG_IRQ_CPU_RM7K=y
83CONFIG_IRQ_MV64340=y
84CONFIG_PCI_MARVELL=y
85CONFIG_SWAP_IO_SPACE=y
86CONFIG_BOOT_ELF32=y
87CONFIG_MIPS_L1_CACHE_SHIFT=5
88
89#
90# CPU selection
91#
92# CONFIG_CPU_MIPS32_R1 is not set
93# CONFIG_CPU_MIPS32_R2 is not set
94# CONFIG_CPU_MIPS64_R1 is not set
95# CONFIG_CPU_MIPS64_R2 is not set
96# CONFIG_CPU_R3000 is not set
97# CONFIG_CPU_TX39XX is not set
98# CONFIG_CPU_VR41XX is not set
99# CONFIG_CPU_R4300 is not set
100# CONFIG_CPU_R4X00 is not set
101# CONFIG_CPU_TX49XX is not set
102# CONFIG_CPU_R5000 is not set
103# CONFIG_CPU_R5432 is not set
104# CONFIG_CPU_R6000 is not set
105# CONFIG_CPU_NEVADA is not set
106# CONFIG_CPU_R8000 is not set
107# CONFIG_CPU_R10000 is not set
108# CONFIG_CPU_RM7000 is not set
109CONFIG_CPU_RM9000=y
110# CONFIG_CPU_SB1 is not set
111CONFIG_SYS_HAS_CPU_RM9000=y
112CONFIG_WEAK_ORDERING=y
113CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
114CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
115CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
116CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
117
118#
119# Kernel type
120#
121CONFIG_32BIT=y
122# CONFIG_64BIT is not set
123CONFIG_PAGE_SIZE_4KB=y
124# CONFIG_PAGE_SIZE_8KB is not set
125# CONFIG_PAGE_SIZE_16KB is not set
126# CONFIG_PAGE_SIZE_64KB is not set
127CONFIG_BOARD_SCACHE=y
128CONFIG_RM7000_CPU_SCACHE=y
129CONFIG_CPU_HAS_PREFETCH=y
130CONFIG_MIPS_MT_DISABLED=y
131# CONFIG_MIPS_MT_SMP is not set
132# CONFIG_MIPS_MT_SMTC is not set
133# CONFIG_MIPS_VPE_LOADER is not set
134# CONFIG_64BIT_PHYS_ADDR is not set
135CONFIG_CPU_HAS_LLSC=y
136CONFIG_CPU_HAS_SYNC=y
137CONFIG_GENERIC_HARDIRQS=y
138CONFIG_GENERIC_IRQ_PROBE=y
139CONFIG_HIGHMEM=y
140CONFIG_CPU_SUPPORTS_HIGHMEM=y
141CONFIG_SYS_SUPPORTS_HIGHMEM=y
142CONFIG_ARCH_FLATMEM_ENABLE=y
143CONFIG_FLATMEM=y
144CONFIG_FLAT_NODE_MEM_MAP=y
145# CONFIG_SPARSEMEM_STATIC is not set
146CONFIG_SPLIT_PTLOCK_CPUS=4
147# CONFIG_RESOURCES_64BIT is not set
148CONFIG_ZONE_DMA_FLAG=1
149# CONFIG_HZ_48 is not set
150# CONFIG_HZ_100 is not set
151# CONFIG_HZ_128 is not set
152# CONFIG_HZ_250 is not set
153# CONFIG_HZ_256 is not set
154CONFIG_HZ_1000=y
155# CONFIG_HZ_1024 is not set
156CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
157CONFIG_HZ=1000
158CONFIG_PREEMPT_NONE=y
159# CONFIG_PREEMPT_VOLUNTARY is not set
160# CONFIG_PREEMPT is not set
161CONFIG_LOCKDEP_SUPPORT=y
162CONFIG_STACKTRACE_SUPPORT=y
163CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
164
165#
166# Code maturity level options
167#
168# CONFIG_EXPERIMENTAL is not set
169CONFIG_BROKEN_ON_SMP=y
170CONFIG_INIT_ENV_ARG_LIMIT=32
171
172#
173# General setup
174#
175CONFIG_LOCALVERSION=""
176CONFIG_LOCALVERSION_AUTO=y
177CONFIG_SWAP=y
178CONFIG_SYSVIPC=y
179# CONFIG_IPC_NS is not set
180CONFIG_SYSVIPC_SYSCTL=y
181# CONFIG_BSD_PROCESS_ACCT is not set
182# CONFIG_TASKSTATS is not set
183# CONFIG_UTS_NS is not set
184# CONFIG_AUDIT is not set
185CONFIG_IKCONFIG=y
186CONFIG_IKCONFIG_PROC=y
187CONFIG_SYSFS_DEPRECATED=y
188CONFIG_RELAY=y
189CONFIG_SYSCTL=y
190CONFIG_EMBEDDED=y
191CONFIG_SYSCTL_SYSCALL=y
192CONFIG_KALLSYMS=y
193# CONFIG_KALLSYMS_EXTRA_PASS is not set
194CONFIG_HOTPLUG=y
195CONFIG_PRINTK=y
196CONFIG_BUG=y
197CONFIG_ELF_CORE=y
198CONFIG_BASE_FULL=y
199CONFIG_FUTEX=y
200CONFIG_EPOLL=y
201CONFIG_SHMEM=y
202CONFIG_SLAB=y
203CONFIG_VM_EVENT_COUNTERS=y
204CONFIG_RT_MUTEXES=y
205# CONFIG_TINY_SHMEM is not set
206CONFIG_BASE_SMALL=0
207# CONFIG_SLOB is not set
208
209#
210# Loadable module support
211#
212CONFIG_MODULES=y
213CONFIG_MODULE_UNLOAD=y
214# CONFIG_MODVERSIONS is not set
215CONFIG_MODULE_SRCVERSION_ALL=y
216CONFIG_KMOD=y
217
218#
219# Block layer
220#
221CONFIG_BLOCK=y
222# CONFIG_LBD is not set
223# CONFIG_BLK_DEV_IO_TRACE is not set
224# CONFIG_LSF is not set
225
226#
227# IO Schedulers
228#
229CONFIG_IOSCHED_NOOP=y
230CONFIG_IOSCHED_AS=y
231CONFIG_IOSCHED_DEADLINE=y
232CONFIG_IOSCHED_CFQ=y
233CONFIG_DEFAULT_AS=y
234# CONFIG_DEFAULT_DEADLINE is not set
235# CONFIG_DEFAULT_CFQ is not set
236# CONFIG_DEFAULT_NOOP is not set
237CONFIG_DEFAULT_IOSCHED="anticipatory"
238
239#
240# Bus options (PCI, PCMCIA, EISA, ISA, TC)
241#
242CONFIG_HW_HAS_PCI=y
243CONFIG_PCI=y
244CONFIG_MMU=y
245
246#
247# PCCARD (PCMCIA/CardBus) support
248#
249# CONFIG_PCCARD is not set
250
251#
252# PCI Hotplug Support
253#
254
255#
256# Executable file formats
257#
258CONFIG_BINFMT_ELF=y
259# CONFIG_BINFMT_MISC is not set
260CONFIG_TRAD_SIGNALS=y
261
262#
263# Power management options
264#
265CONFIG_PM=y
266# CONFIG_PM_LEGACY is not set
267# CONFIG_PM_DEBUG is not set
268# CONFIG_PM_SYSFS_DEPRECATED is not set
269
270#
271# Networking
272#
273CONFIG_NET=y
274
275#
276# Networking options
277#
278# CONFIG_NETDEBUG is not set
279# CONFIG_PACKET is not set
280CONFIG_UNIX=y
281CONFIG_XFRM=y
282CONFIG_XFRM_USER=m
283# CONFIG_NET_KEY is not set
284CONFIG_INET=y
285# CONFIG_IP_MULTICAST is not set
286# CONFIG_IP_ADVANCED_ROUTER is not set
287CONFIG_IP_FIB_HASH=y
288CONFIG_IP_PNP=y
289# CONFIG_IP_PNP_DHCP is not set
290CONFIG_IP_PNP_BOOTP=y
291# CONFIG_IP_PNP_RARP is not set
292# CONFIG_NET_IPIP is not set
293# CONFIG_NET_IPGRE is not set
294# CONFIG_SYN_COOKIES is not set
295# CONFIG_INET_AH is not set
296# CONFIG_INET_ESP is not set
297# CONFIG_INET_IPCOMP is not set
298# CONFIG_INET_XFRM_TUNNEL is not set
299CONFIG_INET_TUNNEL=m
300CONFIG_INET_XFRM_MODE_TRANSPORT=m
301CONFIG_INET_XFRM_MODE_TUNNEL=m
302CONFIG_INET_XFRM_MODE_BEET=m
303CONFIG_INET_DIAG=y
304CONFIG_INET_TCP_DIAG=y
305# CONFIG_TCP_CONG_ADVANCED is not set
306CONFIG_TCP_CONG_CUBIC=y
307CONFIG_DEFAULT_TCP_CONG="cubic"
308CONFIG_IPV6=m
309CONFIG_IPV6_PRIVACY=y
310CONFIG_IPV6_ROUTER_PREF=y
311CONFIG_INET6_AH=m
312CONFIG_INET6_ESP=m
313CONFIG_INET6_IPCOMP=m
314CONFIG_INET6_XFRM_TUNNEL=m
315CONFIG_INET6_TUNNEL=m
316CONFIG_INET6_XFRM_MODE_TRANSPORT=m
317CONFIG_INET6_XFRM_MODE_TUNNEL=m
318CONFIG_INET6_XFRM_MODE_BEET=m
319CONFIG_IPV6_SIT=m
320CONFIG_IPV6_TUNNEL=m
321CONFIG_NETWORK_SECMARK=y
322# CONFIG_NETFILTER is not set
323# CONFIG_BRIDGE is not set
324# CONFIG_VLAN_8021Q is not set
325# CONFIG_DECNET is not set
326# CONFIG_LLC2 is not set
327# CONFIG_IPX is not set
328# CONFIG_ATALK is not set
329
330#
331# QoS and/or fair queueing
332#
333# CONFIG_NET_SCHED is not set
334
335#
336# Network testing
337#
338# CONFIG_NET_PKTGEN is not set
339# CONFIG_HAMRADIO is not set
340# CONFIG_IRDA is not set
341# CONFIG_BT is not set
342CONFIG_IEEE80211=m
343# CONFIG_IEEE80211_DEBUG is not set
344CONFIG_IEEE80211_CRYPT_WEP=m
345CONFIG_IEEE80211_CRYPT_CCMP=m
346
347#
348# Device Drivers
349#
350
351#
352# Generic Driver Options
353#
354CONFIG_STANDALONE=y
355CONFIG_PREVENT_FIRMWARE_BUILD=y
356CONFIG_FW_LOADER=m
357# CONFIG_SYS_HYPERVISOR is not set
358
359#
360# Connector - unified userspace <-> kernelspace linker
361#
362CONFIG_CONNECTOR=m
363
364#
365# Memory Technology Devices (MTD)
366#
367# CONFIG_MTD is not set
368
369#
370# Parallel port support
371#
372# CONFIG_PARPORT is not set
373
374#
375# Plug and Play support
376#
377# CONFIG_PNPACPI is not set
378
379#
380# Block devices
381#
382# CONFIG_BLK_CPQ_DA is not set
383# CONFIG_BLK_CPQ_CISS_DA is not set
384# CONFIG_BLK_DEV_DAC960 is not set
385# CONFIG_BLK_DEV_COW_COMMON is not set
386# CONFIG_BLK_DEV_LOOP is not set
387# CONFIG_BLK_DEV_NBD is not set
388# CONFIG_BLK_DEV_SX8 is not set
389# CONFIG_BLK_DEV_RAM is not set
390# CONFIG_BLK_DEV_INITRD is not set
391CONFIG_CDROM_PKTCDVD=m
392CONFIG_CDROM_PKTCDVD_BUFFERS=8
393CONFIG_ATA_OVER_ETH=m
394
395#
396# Misc devices
397#
398CONFIG_SGI_IOC4=m
399
400#
401# ATA/ATAPI/MFM/RLL support
402#
403# CONFIG_IDE is not set
404
405#
406# SCSI device support
407#
408CONFIG_RAID_ATTRS=m
409# CONFIG_SCSI is not set
410# CONFIG_SCSI_NETLINK is not set
411
412#
413# Serial ATA (prod) and Parallel ATA (experimental) drivers
414#
415# CONFIG_ATA is not set
416
417#
418# Multi-device support (RAID and LVM)
419#
420# CONFIG_MD is not set
421
422#
423# Fusion MPT device support
424#
425# CONFIG_FUSION is not set
426
427#
428# IEEE 1394 (FireWire) support
429#
430# CONFIG_IEEE1394 is not set
431
432#
433# I2O device support
434#
435# CONFIG_I2O is not set
436
437#
438# Network device support
439#
440CONFIG_NETDEVICES=y
441# CONFIG_DUMMY is not set
442# CONFIG_BONDING is not set
443# CONFIG_EQUALIZER is not set
444# CONFIG_TUN is not set
445
446#
447# ARCnet devices
448#
449# CONFIG_ARCNET is not set
450
451#
452# PHY device support
453#
454CONFIG_PHYLIB=m
455
456#
457# MII PHY device drivers
458#
459CONFIG_MARVELL_PHY=m
460CONFIG_DAVICOM_PHY=m
461CONFIG_QSEMI_PHY=m
462CONFIG_LXT_PHY=m
463CONFIG_CICADA_PHY=m
464CONFIG_VITESSE_PHY=m
465CONFIG_SMSC_PHY=m
466# CONFIG_BROADCOM_PHY is not set
467# CONFIG_FIXED_PHY is not set
468
469#
470# Ethernet (10 or 100Mbit)
471#
472CONFIG_NET_ETHERNET=y
473CONFIG_MII=y
474# CONFIG_HAPPYMEAL is not set
475# CONFIG_SUNGEM is not set
476# CONFIG_CASSINI is not set
477# CONFIG_NET_VENDOR_3COM is not set
478# CONFIG_DM9000 is not set
479
480#
481# Tulip family network device support
482#
483# CONFIG_NET_TULIP is not set
484# CONFIG_HP100 is not set
485CONFIG_NET_PCI=y
486# CONFIG_PCNET32 is not set
487# CONFIG_AMD8111_ETH is not set
488# CONFIG_ADAPTEC_STARFIRE is not set
489# CONFIG_B44 is not set
490# CONFIG_FORCEDETH is not set
491# CONFIG_DGRS is not set
492CONFIG_EEPRO100=y
493# CONFIG_E100 is not set
494# CONFIG_FEALNX is not set
495# CONFIG_NATSEMI is not set
496# CONFIG_NE2K_PCI is not set
497# CONFIG_8139TOO is not set
498# CONFIG_SIS900 is not set
499# CONFIG_EPIC100 is not set
500# CONFIG_SUNDANCE is not set
501# CONFIG_TLAN is not set
502# CONFIG_VIA_RHINE is not set
503
504#
505# Ethernet (1000 Mbit)
506#
507# CONFIG_ACENIC is not set
508# CONFIG_DL2K is not set
509# CONFIG_E1000 is not set
510# CONFIG_NS83820 is not set
511# CONFIG_HAMACHI is not set
512# CONFIG_R8169 is not set
513# CONFIG_SIS190 is not set
514# CONFIG_SKGE is not set
515# CONFIG_SKY2 is not set
516# CONFIG_SK98LIN is not set
517# CONFIG_VIA_VELOCITY is not set
518# CONFIG_TIGON3 is not set
519# CONFIG_BNX2 is not set
520CONFIG_MV643XX_ETH=y
521CONFIG_QLA3XXX=m
522
523#
524# Ethernet (10000 Mbit)
525#
526# CONFIG_CHELSIO_T1 is not set
527CONFIG_CHELSIO_T3=m
528# CONFIG_IXGB is not set
529# CONFIG_S2IO is not set
530# CONFIG_MYRI10GE is not set
531CONFIG_NETXEN_NIC=m
532
533#
534# Token Ring devices
535#
536# CONFIG_TR is not set
537
538#
539# Wireless LAN (non-hamradio)
540#
541# CONFIG_NET_RADIO is not set
542
543#
544# Wan interfaces
545#
546# CONFIG_WAN is not set
547# CONFIG_FDDI is not set
548# CONFIG_PPP is not set
549# CONFIG_SLIP is not set
550# CONFIG_NETPOLL is not set
551# CONFIG_NET_POLL_CONTROLLER is not set
552
553#
554# ISDN subsystem
555#
556# CONFIG_ISDN is not set
557
558#
559# Telephony Support
560#
561# CONFIG_PHONE is not set
562
563#
564# Input device support
565#
566# CONFIG_INPUT is not set
567
568#
569# Hardware I/O ports
570#
571# CONFIG_SERIO is not set
572# CONFIG_GAMEPORT is not set
573
574#
575# Character devices
576#
577# CONFIG_VT is not set
578# CONFIG_SERIAL_NONSTANDARD is not set
579
580#
581# Serial drivers
582#
583CONFIG_SERIAL_8250=y
584CONFIG_SERIAL_8250_CONSOLE=y
585CONFIG_SERIAL_8250_PCI=y
586CONFIG_SERIAL_8250_NR_UARTS=4
587CONFIG_SERIAL_8250_RUNTIME_UARTS=4
588# CONFIG_SERIAL_8250_EXTENDED is not set
589
590#
591# Non-8250 serial port support
592#
593CONFIG_SERIAL_CORE=y
594CONFIG_SERIAL_CORE_CONSOLE=y
595# CONFIG_SERIAL_JSM is not set
596CONFIG_UNIX98_PTYS=y
597CONFIG_LEGACY_PTYS=y
598CONFIG_LEGACY_PTY_COUNT=256
599
600#
601# IPMI
602#
603# CONFIG_IPMI_HANDLER is not set
604
605#
606# Watchdog Cards
607#
608# CONFIG_WATCHDOG is not set
609# CONFIG_HW_RANDOM is not set
610# CONFIG_RTC is not set
611# CONFIG_GEN_RTC is not set
612# CONFIG_DTLK is not set
613# CONFIG_R3964 is not set
614# CONFIG_APPLICOM is not set
615# CONFIG_DRM is not set
616# CONFIG_RAW_DRIVER is not set
617
618#
619# TPM devices
620#
621
622#
623# I2C support
624#
625# CONFIG_I2C is not set
626
627#
628# SPI support
629#
630# CONFIG_SPI is not set
631# CONFIG_SPI_MASTER is not set
632
633#
634# Dallas's 1-wire bus
635#
636# CONFIG_W1 is not set
637
638#
639# Hardware Monitoring support
640#
641# CONFIG_HWMON is not set
642# CONFIG_HWMON_VID is not set
643
644#
645# Multimedia devices
646#
647# CONFIG_VIDEO_DEV is not set
648
649#
650# Digital Video Broadcasting Devices
651#
652# CONFIG_DVB is not set
653
654#
655# Graphics support
656#
657# CONFIG_FIRMWARE_EDID is not set
658# CONFIG_FB is not set
659# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
660
661#
662# Sound
663#
664# CONFIG_SOUND is not set
665
666#
667# USB support
668#
669CONFIG_USB_ARCH_HAS_HCD=y
670CONFIG_USB_ARCH_HAS_OHCI=y
671CONFIG_USB_ARCH_HAS_EHCI=y
672# CONFIG_USB is not set
673
674#
675# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
676#
677
678#
679# USB Gadget Support
680#
681# CONFIG_USB_GADGET is not set
682
683#
684# MMC/SD Card support
685#
686# CONFIG_MMC is not set
687
688#
689# LED devices
690#
691# CONFIG_NEW_LEDS is not set
692
693#
694# LED drivers
695#
696
697#
698# LED Triggers
699#
700
701#
702# InfiniBand support
703#
704# CONFIG_INFINIBAND is not set
705
706#
707# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
708#
709
710#
711# Real Time Clock
712#
713
714#
715# DMA Engine support
716#
717# CONFIG_DMA_ENGINE is not set
718
719#
720# DMA Clients
721#
722
723#
724# DMA Devices
725#
726
727#
728# Auxiliary Display support
729#
730
731#
732# Virtualization
733#
734
735#
736# File systems
737#
738# CONFIG_EXT2_FS is not set
739# CONFIG_EXT3_FS is not set
740# CONFIG_REISERFS_FS is not set
741# CONFIG_JFS_FS is not set
742CONFIG_FS_POSIX_ACL=y
743# CONFIG_XFS_FS is not set
744# CONFIG_OCFS2_FS is not set
745# CONFIG_MINIX_FS is not set
746# CONFIG_ROMFS_FS is not set
747CONFIG_INOTIFY=y
748CONFIG_INOTIFY_USER=y
749# CONFIG_QUOTA is not set
750CONFIG_DNOTIFY=y
751# CONFIG_AUTOFS_FS is not set
752# CONFIG_AUTOFS4_FS is not set
753CONFIG_FUSE_FS=m
754CONFIG_GENERIC_ACL=y
755
756#
757# CD-ROM/DVD Filesystems
758#
759# CONFIG_ISO9660_FS is not set
760# CONFIG_UDF_FS is not set
761
762#
763# DOS/FAT/NT Filesystems
764#
765# CONFIG_MSDOS_FS is not set
766# CONFIG_VFAT_FS is not set
767# CONFIG_NTFS_FS is not set
768
769#
770# Pseudo filesystems
771#
772CONFIG_PROC_FS=y
773CONFIG_PROC_KCORE=y
774CONFIG_PROC_SYSCTL=y
775CONFIG_SYSFS=y
776CONFIG_TMPFS=y
777CONFIG_TMPFS_POSIX_ACL=y
778# CONFIG_HUGETLB_PAGE is not set
779CONFIG_RAMFS=y
780
781#
782# Miscellaneous filesystems
783#
784# CONFIG_HFSPLUS_FS is not set
785# CONFIG_CRAMFS is not set
786# CONFIG_VXFS_FS is not set
787# CONFIG_HPFS_FS is not set
788# CONFIG_QNX4FS_FS is not set
789# CONFIG_SYSV_FS is not set
790# CONFIG_UFS_FS is not set
791
792#
793# Network File Systems
794#
795CONFIG_NFS_FS=y
796# CONFIG_NFS_V3 is not set
797# CONFIG_NFS_DIRECTIO is not set
798# CONFIG_NFSD is not set
799CONFIG_ROOT_NFS=y
800CONFIG_LOCKD=y
801CONFIG_NFS_COMMON=y
802CONFIG_SUNRPC=y
803# CONFIG_SMB_FS is not set
804# CONFIG_CIFS is not set
805# CONFIG_NCP_FS is not set
806# CONFIG_CODA_FS is not set
807
808#
809# Partition Types
810#
811# CONFIG_PARTITION_ADVANCED is not set
812CONFIG_MSDOS_PARTITION=y
813
814#
815# Native Language Support
816#
817# CONFIG_NLS is not set
818
819#
820# Kernel hacking
821#
822CONFIG_TRACE_IRQFLAGS_SUPPORT=y
823# CONFIG_PRINTK_TIME is not set
824CONFIG_ENABLE_MUST_CHECK=y
825# CONFIG_MAGIC_SYSRQ is not set
826# CONFIG_UNUSED_SYMBOLS is not set
827# CONFIG_DEBUG_FS is not set
828# CONFIG_HEADERS_CHECK is not set
829# CONFIG_DEBUG_KERNEL is not set
830CONFIG_LOG_BUF_SHIFT=14
831CONFIG_CROSSCOMPILE=y
832CONFIG_CMDLINE=""
833CONFIG_SYS_SUPPORTS_KGDB=y
834
835#
836# Security options
837#
838CONFIG_KEYS=y
839CONFIG_KEYS_DEBUG_PROC_KEYS=y
840# CONFIG_SECURITY is not set
841
842#
843# Cryptographic options
844#
845CONFIG_CRYPTO=y
846CONFIG_CRYPTO_ALGAPI=y
847CONFIG_CRYPTO_BLKCIPHER=m
848CONFIG_CRYPTO_HASH=y
849CONFIG_CRYPTO_MANAGER=y
850CONFIG_CRYPTO_HMAC=y
851CONFIG_CRYPTO_NULL=m
852CONFIG_CRYPTO_MD4=m
853CONFIG_CRYPTO_MD5=m
854CONFIG_CRYPTO_SHA1=m
855CONFIG_CRYPTO_SHA256=m
856CONFIG_CRYPTO_SHA512=m
857CONFIG_CRYPTO_WP512=m
858CONFIG_CRYPTO_TGR192=m
859CONFIG_CRYPTO_ECB=m
860CONFIG_CRYPTO_CBC=m
861CONFIG_CRYPTO_PCBC=m
862CONFIG_CRYPTO_DES=m
863CONFIG_CRYPTO_FCRYPT=m
864CONFIG_CRYPTO_BLOWFISH=m
865CONFIG_CRYPTO_TWOFISH=m
866CONFIG_CRYPTO_TWOFISH_COMMON=m
867CONFIG_CRYPTO_SERPENT=m
868CONFIG_CRYPTO_AES=m
869CONFIG_CRYPTO_CAST5=m
870CONFIG_CRYPTO_CAST6=m
871CONFIG_CRYPTO_TEA=m
872CONFIG_CRYPTO_ARC4=m
873CONFIG_CRYPTO_KHAZAD=m
874CONFIG_CRYPTO_ANUBIS=m
875CONFIG_CRYPTO_DEFLATE=m
876CONFIG_CRYPTO_MICHAEL_MIC=m
877CONFIG_CRYPTO_CRC32C=m
878CONFIG_CRYPTO_CAMELLIA=m
879# CONFIG_CRYPTO_TEST is not set
880
881#
882# Hardware crypto devices
883#
884
885#
886# Library routines
887#
888CONFIG_BITREVERSE=m
889# CONFIG_CRC_CCITT is not set
890CONFIG_CRC16=m
891CONFIG_CRC32=m
892CONFIG_LIBCRC32C=m
893CONFIG_ZLIB_INFLATE=m
894CONFIG_ZLIB_DEFLATE=m
895CONFIG_PLIST=y
896CONFIG_HAS_IOMEM=y
897CONFIG_HAS_IOPORT=y
diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig
index 068e48ec7093..1b364cf69140 100644
--- a/arch/mips/configs/jmr3927_defconfig
+++ b/arch/mips/configs/jmr3927_defconfig
@@ -80,7 +80,6 @@ CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
80CONFIG_MIPS_TX3927=y 80CONFIG_MIPS_TX3927=y
81CONFIG_SWAP_IO_SPACE=y 81CONFIG_SWAP_IO_SPACE=y
82CONFIG_MIPS_L1_CACHE_SHIFT=5 82CONFIG_MIPS_L1_CACHE_SHIFT=5
83CONFIG_TOSHIBA_BOARDS=y
84 83
85# 84#
86# CPU selection 85# CPU selection
diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig
index 69678d99ae61..37d696c64541 100644
--- a/arch/mips/configs/pb1100_defconfig
+++ b/arch/mips/configs/pb1100_defconfig
@@ -9,6 +9,7 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11CONFIG_ZONE_DMA=y 11CONFIG_ZONE_DMA=y
12CONFIG_MACH_ALCHEMY=y
12# CONFIG_MIPS_MTX1 is not set 13# CONFIG_MIPS_MTX1 is not set
13# CONFIG_MIPS_BOSPORUS is not set 14# CONFIG_MIPS_BOSPORUS is not set
14# CONFIG_MIPS_PB1000 is not set 15# CONFIG_MIPS_PB1000 is not set
diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig
index 070672799dac..b11f0e8b6059 100644
--- a/arch/mips/configs/pb1500_defconfig
+++ b/arch/mips/configs/pb1500_defconfig
@@ -9,6 +9,7 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11CONFIG_ZONE_DMA=y 11CONFIG_ZONE_DMA=y
12CONFIG_MACH_ALCHEMY=y
12# CONFIG_MIPS_MTX1 is not set 13# CONFIG_MIPS_MTX1 is not set
13# CONFIG_MIPS_BOSPORUS is not set 14# CONFIG_MIPS_BOSPORUS is not set
14# CONFIG_MIPS_PB1000 is not set 15# CONFIG_MIPS_PB1000 is not set
diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig
index 354e49b7a5f1..2927f38f4907 100644
--- a/arch/mips/configs/pb1550_defconfig
+++ b/arch/mips/configs/pb1550_defconfig
@@ -9,6 +9,7 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11CONFIG_ZONE_DMA=y 11CONFIG_ZONE_DMA=y
12CONFIG_MACH_ALCHEMY=y
12# CONFIG_MIPS_MTX1 is not set 13# CONFIG_MIPS_MTX1 is not set
13# CONFIG_MIPS_BOSPORUS is not set 14# CONFIG_MIPS_BOSPORUS is not set
14# CONFIG_MIPS_PB1000 is not set 15# CONFIG_MIPS_PB1000 is not set
diff --git a/arch/mips/configs/ocelot_g_defconfig b/arch/mips/configs/rbhma4200_defconfig
index 7078e6b3ea11..35d64260917e 100644
--- a/arch/mips/configs/ocelot_g_defconfig
+++ b/arch/mips/configs/rbhma4200_defconfig
@@ -1,14 +1,13 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.20 3# Linux kernel version: 2.6.21
4# Tue Feb 20 21:47:36 2007 4# Wed May 9 23:44:19 2007
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7 7
8# 8#
9# Machine selection 9# Machine selection
10# 10#
11CONFIG_ZONE_DMA=y
12# CONFIG_MIPS_MTX1 is not set 11# CONFIG_MIPS_MTX1 is not set
13# CONFIG_MIPS_BOSPORUS is not set 12# CONFIG_MIPS_BOSPORUS is not set
14# CONFIG_MIPS_PB1000 is not set 13# CONFIG_MIPS_PB1000 is not set
@@ -33,11 +32,9 @@ CONFIG_ZONE_DMA=y
33# CONFIG_MIPS_SEAD is not set 32# CONFIG_MIPS_SEAD is not set
34# CONFIG_WR_PPMC is not set 33# CONFIG_WR_PPMC is not set
35# CONFIG_MIPS_SIM is not set 34# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 35# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set 36# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set 37# CONFIG_MOMENCO_OCELOT_C is not set
40CONFIG_MOMENCO_OCELOT_G=y
41# CONFIG_MIPS_XXS1500 is not set 38# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set 39# CONFIG_PNX8550_JBS is not set
43# CONFIG_PNX8550_STB810 is not set 40# CONFIG_PNX8550_STB810 is not set
@@ -60,8 +57,9 @@ CONFIG_MOMENCO_OCELOT_G=y
60# CONFIG_SIBYTE_CRHONE is not set 57# CONFIG_SIBYTE_CRHONE is not set
61# CONFIG_SNI_RM is not set 58# CONFIG_SNI_RM is not set
62# CONFIG_TOSHIBA_JMR3927 is not set 59# CONFIG_TOSHIBA_JMR3927 is not set
63# CONFIG_TOSHIBA_RBTX4927 is not set 60CONFIG_TOSHIBA_RBTX4927=y
64# CONFIG_TOSHIBA_RBTX4938 is not set 61# CONFIG_TOSHIBA_RBTX4938 is not set
62# CONFIG_TOSHIBA_FPCIB0 is not set
65CONFIG_RWSEM_GENERIC_SPINLOCK=y 63CONFIG_RWSEM_GENERIC_SPINLOCK=y
66# CONFIG_ARCH_HAS_ILOG2_U32 is not set 64# CONFIG_ARCH_HAS_ILOG2_U32 is not set
67# CONFIG_ARCH_HAS_ILOG2_U64 is not set 65# CONFIG_ARCH_HAS_ILOG2_U64 is not set
@@ -70,19 +68,15 @@ CONFIG_GENERIC_HWEIGHT=y
70CONFIG_GENERIC_CALIBRATE_DELAY=y 68CONFIG_GENERIC_CALIBRATE_DELAY=y
71CONFIG_GENERIC_TIME=y 69CONFIG_GENERIC_TIME=y
72CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 70CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
73# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set 71CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
74CONFIG_DMA_NONCOHERENT=y 72CONFIG_DMA_NONCOHERENT=y
75CONFIG_DMA_NEED_PCI_MAP_STATE=y 73CONFIG_DMA_NEED_PCI_MAP_STATE=y
74CONFIG_I8259=y
76CONFIG_CPU_BIG_ENDIAN=y 75CONFIG_CPU_BIG_ENDIAN=y
77# CONFIG_CPU_LITTLE_ENDIAN is not set 76# CONFIG_CPU_LITTLE_ENDIAN is not set
78CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y 77CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
79CONFIG_IRQ_CPU=y 78CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
80CONFIG_IRQ_CPU_RM7K=y
81CONFIG_PCI_MARVELL=y
82CONFIG_SWAP_IO_SPACE=y 79CONFIG_SWAP_IO_SPACE=y
83# CONFIG_SYSCLK_75 is not set
84# CONFIG_SYSCLK_83 is not set
85CONFIG_SYSCLK_100=y
86CONFIG_MIPS_L1_CACHE_SHIFT=5 80CONFIG_MIPS_L1_CACHE_SHIFT=5
87 81
88# 82#
@@ -97,18 +91,19 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
97# CONFIG_CPU_VR41XX is not set 91# CONFIG_CPU_VR41XX is not set
98# CONFIG_CPU_R4300 is not set 92# CONFIG_CPU_R4300 is not set
99# CONFIG_CPU_R4X00 is not set 93# CONFIG_CPU_R4X00 is not set
100# CONFIG_CPU_TX49XX is not set 94CONFIG_CPU_TX49XX=y
101# CONFIG_CPU_R5000 is not set 95# CONFIG_CPU_R5000 is not set
102# CONFIG_CPU_R5432 is not set 96# CONFIG_CPU_R5432 is not set
103# CONFIG_CPU_R6000 is not set 97# CONFIG_CPU_R6000 is not set
104# CONFIG_CPU_NEVADA is not set 98# CONFIG_CPU_NEVADA is not set
105# CONFIG_CPU_R8000 is not set 99# CONFIG_CPU_R8000 is not set
106# CONFIG_CPU_R10000 is not set 100# CONFIG_CPU_R10000 is not set
107CONFIG_CPU_RM7000=y 101# CONFIG_CPU_RM7000 is not set
108# CONFIG_CPU_RM9000 is not set 102# CONFIG_CPU_RM9000 is not set
109# CONFIG_CPU_SB1 is not set 103# CONFIG_CPU_SB1 is not set
110CONFIG_SYS_HAS_CPU_RM7000=y 104CONFIG_SYS_HAS_CPU_TX49XX=y
111CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y 105CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
106CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
112CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y 107CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
113CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y 108CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
114 109
@@ -121,19 +116,15 @@ CONFIG_PAGE_SIZE_4KB=y
121# CONFIG_PAGE_SIZE_8KB is not set 116# CONFIG_PAGE_SIZE_8KB is not set
122# CONFIG_PAGE_SIZE_16KB is not set 117# CONFIG_PAGE_SIZE_16KB is not set
123# CONFIG_PAGE_SIZE_64KB is not set 118# CONFIG_PAGE_SIZE_64KB is not set
124CONFIG_BOARD_SCACHE=y
125CONFIG_RM7000_CPU_SCACHE=y
126CONFIG_CPU_HAS_PREFETCH=y 119CONFIG_CPU_HAS_PREFETCH=y
127CONFIG_MIPS_MT_DISABLED=y 120CONFIG_MIPS_MT_DISABLED=y
128# CONFIG_MIPS_MT_SMP is not set 121# CONFIG_MIPS_MT_SMP is not set
129# CONFIG_MIPS_MT_SMTC is not set 122# CONFIG_MIPS_MT_SMTC is not set
130# CONFIG_MIPS_VPE_LOADER is not set 123# CONFIG_MIPS_VPE_LOADER is not set
131# CONFIG_64BIT_PHYS_ADDR is not set
132CONFIG_CPU_HAS_LLSC=y 124CONFIG_CPU_HAS_LLSC=y
133CONFIG_CPU_HAS_SYNC=y 125CONFIG_CPU_HAS_SYNC=y
134CONFIG_GENERIC_HARDIRQS=y 126CONFIG_GENERIC_HARDIRQS=y
135CONFIG_GENERIC_IRQ_PROBE=y 127CONFIG_GENERIC_IRQ_PROBE=y
136CONFIG_CPU_SUPPORTS_HIGHMEM=y
137CONFIG_ARCH_FLATMEM_ENABLE=y 128CONFIG_ARCH_FLATMEM_ENABLE=y
138CONFIG_SELECT_MEMORY_MODEL=y 129CONFIG_SELECT_MEMORY_MODEL=y
139CONFIG_FLATMEM_MANUAL=y 130CONFIG_FLATMEM_MANUAL=y
@@ -143,17 +134,17 @@ CONFIG_FLATMEM=y
143CONFIG_FLAT_NODE_MEM_MAP=y 134CONFIG_FLAT_NODE_MEM_MAP=y
144# CONFIG_SPARSEMEM_STATIC is not set 135# CONFIG_SPARSEMEM_STATIC is not set
145CONFIG_SPLIT_PTLOCK_CPUS=4 136CONFIG_SPLIT_PTLOCK_CPUS=4
146CONFIG_RESOURCES_64BIT=y 137# CONFIG_RESOURCES_64BIT is not set
147CONFIG_ZONE_DMA_FLAG=1 138CONFIG_ZONE_DMA_FLAG=0
148# CONFIG_HZ_48 is not set 139# CONFIG_HZ_48 is not set
149# CONFIG_HZ_100 is not set 140# CONFIG_HZ_100 is not set
150# CONFIG_HZ_128 is not set 141# CONFIG_HZ_128 is not set
151# CONFIG_HZ_250 is not set 142CONFIG_HZ_250=y
152# CONFIG_HZ_256 is not set 143# CONFIG_HZ_256 is not set
153CONFIG_HZ_1000=y 144# CONFIG_HZ_1000 is not set
154# CONFIG_HZ_1024 is not set 145# CONFIG_HZ_1024 is not set
155CONFIG_SYS_SUPPORTS_ARBIT_HZ=y 146CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
156CONFIG_HZ=1000 147CONFIG_HZ=250
157CONFIG_PREEMPT_NONE=y 148CONFIG_PREEMPT_NONE=y
158# CONFIG_PREEMPT_VOLUNTARY is not set 149# CONFIG_PREEMPT_VOLUNTARY is not set
159# CONFIG_PREEMPT is not set 150# CONFIG_PREEMPT is not set
@@ -183,34 +174,42 @@ CONFIG_SYSVIPC_SYSCTL=y
183# CONFIG_TASKSTATS is not set 174# CONFIG_TASKSTATS is not set
184# CONFIG_UTS_NS is not set 175# CONFIG_UTS_NS is not set
185# CONFIG_AUDIT is not set 176# CONFIG_AUDIT is not set
186# CONFIG_IKCONFIG is not set 177CONFIG_IKCONFIG=y
178CONFIG_IKCONFIG_PROC=y
179CONFIG_LOG_BUF_SHIFT=14
187CONFIG_SYSFS_DEPRECATED=y 180CONFIG_SYSFS_DEPRECATED=y
188CONFIG_RELAY=y 181# CONFIG_RELAY is not set
189# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 182CONFIG_BLK_DEV_INITRD=y
183CONFIG_INITRAMFS_SOURCE=""
184CONFIG_CC_OPTIMIZE_FOR_SIZE=y
190CONFIG_SYSCTL=y 185CONFIG_SYSCTL=y
191CONFIG_EMBEDDED=y 186CONFIG_EMBEDDED=y
192CONFIG_SYSCTL_SYSCALL=y 187CONFIG_SYSCTL_SYSCALL=y
193CONFIG_KALLSYMS=y 188CONFIG_KALLSYMS=y
194# CONFIG_KALLSYMS_EXTRA_PASS is not set 189# CONFIG_KALLSYMS_EXTRA_PASS is not set
195CONFIG_HOTPLUG=y 190# CONFIG_HOTPLUG is not set
196CONFIG_PRINTK=y 191CONFIG_PRINTK=y
197CONFIG_BUG=y 192CONFIG_BUG=y
198CONFIG_ELF_CORE=y 193CONFIG_ELF_CORE=y
199CONFIG_BASE_FULL=y 194CONFIG_BASE_FULL=y
200CONFIG_FUTEX=y 195# CONFIG_FUTEX is not set
201CONFIG_EPOLL=y 196# CONFIG_EPOLL is not set
202CONFIG_SHMEM=y 197CONFIG_SHMEM=y
203CONFIG_SLAB=y
204CONFIG_VM_EVENT_COUNTERS=y 198CONFIG_VM_EVENT_COUNTERS=y
205CONFIG_RT_MUTEXES=y 199CONFIG_SLAB=y
200# CONFIG_SLUB is not set
201# CONFIG_SLOB is not set
206# CONFIG_TINY_SHMEM is not set 202# CONFIG_TINY_SHMEM is not set
207CONFIG_BASE_SMALL=0 203CONFIG_BASE_SMALL=0
208# CONFIG_SLOB is not set
209 204
210# 205#
211# Loadable module support 206# Loadable module support
212# 207#
213# CONFIG_MODULES is not set 208CONFIG_MODULES=y
209# CONFIG_MODULE_UNLOAD is not set
210# CONFIG_MODVERSIONS is not set
211# CONFIG_MODULE_SRCVERSION_ALL is not set
212CONFIG_KMOD=y
214 213
215# 214#
216# Block layer 215# Block layer
@@ -218,7 +217,7 @@ CONFIG_BASE_SMALL=0
218CONFIG_BLOCK=y 217CONFIG_BLOCK=y
219# CONFIG_LBD is not set 218# CONFIG_LBD is not set
220# CONFIG_BLK_DEV_IO_TRACE is not set 219# CONFIG_BLK_DEV_IO_TRACE is not set
221CONFIG_LSF=y 220# CONFIG_LSF is not set
222 221
223# 222#
224# IO Schedulers 223# IO Schedulers
@@ -238,17 +237,12 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
238# 237#
239CONFIG_HW_HAS_PCI=y 238CONFIG_HW_HAS_PCI=y
240CONFIG_PCI=y 239CONFIG_PCI=y
240# CONFIG_ARCH_SUPPORTS_MSI is not set
241CONFIG_MMU=y 241CONFIG_MMU=y
242 242
243# 243#
244# PCCARD (PCMCIA/CardBus) support 244# PCCARD (PCMCIA/CardBus) support
245# 245#
246# CONFIG_PCCARD is not set
247
248#
249# PCI Hotplug Support
250#
251# CONFIG_HOTPLUG_PCI is not set
252 246
253# 247#
254# Executable file formats 248# Executable file formats
@@ -260,10 +254,7 @@ CONFIG_TRAD_SIGNALS=y
260# 254#
261# Power management options 255# Power management options
262# 256#
263CONFIG_PM=y 257# CONFIG_PM is not set
264# CONFIG_PM_LEGACY is not set
265# CONFIG_PM_DEBUG is not set
266# CONFIG_PM_SYSFS_DEPRECATED is not set
267 258
268# 259#
269# Networking 260# Networking
@@ -273,25 +264,21 @@ CONFIG_NET=y
273# 264#
274# Networking options 265# Networking options
275# 266#
276# CONFIG_NETDEBUG is not set 267CONFIG_PACKET=y
277# CONFIG_PACKET is not set 268# CONFIG_PACKET_MMAP is not set
278CONFIG_UNIX=y 269CONFIG_UNIX=y
279CONFIG_XFRM=y 270# CONFIG_NET_KEY is not set
280CONFIG_XFRM_USER=y
281# CONFIG_XFRM_SUB_POLICY is not set
282CONFIG_XFRM_MIGRATE=y
283CONFIG_NET_KEY=y
284CONFIG_NET_KEY_MIGRATE=y
285CONFIG_INET=y 271CONFIG_INET=y
286# CONFIG_IP_MULTICAST is not set 272CONFIG_IP_MULTICAST=y
287# CONFIG_IP_ADVANCED_ROUTER is not set 273# CONFIG_IP_ADVANCED_ROUTER is not set
288CONFIG_IP_FIB_HASH=y 274CONFIG_IP_FIB_HASH=y
289CONFIG_IP_PNP=y 275CONFIG_IP_PNP=y
290CONFIG_IP_PNP_DHCP=y 276# CONFIG_IP_PNP_DHCP is not set
291# CONFIG_IP_PNP_BOOTP is not set 277# CONFIG_IP_PNP_BOOTP is not set
292# CONFIG_IP_PNP_RARP is not set 278# CONFIG_IP_PNP_RARP is not set
293# CONFIG_NET_IPIP is not set 279# CONFIG_NET_IPIP is not set
294# CONFIG_NET_IPGRE is not set 280# CONFIG_NET_IPGRE is not set
281# CONFIG_IP_MROUTE is not set
295# CONFIG_ARPD is not set 282# CONFIG_ARPD is not set
296# CONFIG_SYN_COOKIES is not set 283# CONFIG_SYN_COOKIES is not set
297# CONFIG_INET_AH is not set 284# CONFIG_INET_AH is not set
@@ -299,19 +286,19 @@ CONFIG_IP_PNP_DHCP=y
299# CONFIG_INET_IPCOMP is not set 286# CONFIG_INET_IPCOMP is not set
300# CONFIG_INET_XFRM_TUNNEL is not set 287# CONFIG_INET_XFRM_TUNNEL is not set
301# CONFIG_INET_TUNNEL is not set 288# CONFIG_INET_TUNNEL is not set
302CONFIG_INET_XFRM_MODE_TRANSPORT=y 289# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
303CONFIG_INET_XFRM_MODE_TUNNEL=y 290# CONFIG_INET_XFRM_MODE_TUNNEL is not set
304CONFIG_INET_XFRM_MODE_BEET=y 291# CONFIG_INET_XFRM_MODE_BEET is not set
305CONFIG_INET_DIAG=y 292CONFIG_INET_DIAG=y
306CONFIG_INET_TCP_DIAG=y 293CONFIG_INET_TCP_DIAG=y
307# CONFIG_TCP_CONG_ADVANCED is not set 294# CONFIG_TCP_CONG_ADVANCED is not set
308CONFIG_TCP_CONG_CUBIC=y 295CONFIG_TCP_CONG_CUBIC=y
309CONFIG_DEFAULT_TCP_CONG="cubic" 296CONFIG_DEFAULT_TCP_CONG="cubic"
310CONFIG_TCP_MD5SIG=y 297# CONFIG_TCP_MD5SIG is not set
311# CONFIG_IPV6 is not set 298# CONFIG_IPV6 is not set
312# CONFIG_INET6_XFRM_TUNNEL is not set 299# CONFIG_INET6_XFRM_TUNNEL is not set
313# CONFIG_INET6_TUNNEL is not set 300# CONFIG_INET6_TUNNEL is not set
314CONFIG_NETWORK_SECMARK=y 301# CONFIG_NETWORK_SECMARK is not set
315# CONFIG_NETFILTER is not set 302# CONFIG_NETFILTER is not set
316 303
317# 304#
@@ -352,13 +339,16 @@ CONFIG_NETWORK_SECMARK=y
352# CONFIG_HAMRADIO is not set 339# CONFIG_HAMRADIO is not set
353# CONFIG_IRDA is not set 340# CONFIG_IRDA is not set
354# CONFIG_BT is not set 341# CONFIG_BT is not set
355CONFIG_IEEE80211=y 342# CONFIG_AF_RXRPC is not set
356# CONFIG_IEEE80211_DEBUG is not set 343
357CONFIG_IEEE80211_CRYPT_WEP=y 344#
358CONFIG_IEEE80211_CRYPT_CCMP=y 345# Wireless
359CONFIG_IEEE80211_SOFTMAC=y 346#
360# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set 347# CONFIG_CFG80211 is not set
361CONFIG_WIRELESS_EXT=y 348# CONFIG_WIRELESS_EXT is not set
349# CONFIG_MAC80211 is not set
350# CONFIG_IEEE80211 is not set
351# CONFIG_RFKILL is not set
362 352
363# 353#
364# Device Drivers 354# Device Drivers
@@ -369,18 +359,12 @@ CONFIG_WIRELESS_EXT=y
369# 359#
370CONFIG_STANDALONE=y 360CONFIG_STANDALONE=y
371CONFIG_PREVENT_FIRMWARE_BUILD=y 361CONFIG_PREVENT_FIRMWARE_BUILD=y
372CONFIG_FW_LOADER=y
373# CONFIG_SYS_HYPERVISOR is not set 362# CONFIG_SYS_HYPERVISOR is not set
374 363
375# 364#
376# Connector - unified userspace <-> kernelspace linker 365# Connector - unified userspace <-> kernelspace linker
377# 366#
378CONFIG_CONNECTOR=y 367# CONFIG_CONNECTOR is not set
379CONFIG_PROC_EVENTS=y
380
381#
382# Memory Technology Devices (MTD)
383#
384# CONFIG_MTD is not set 368# CONFIG_MTD is not set
385 369
386# 370#
@@ -401,21 +385,24 @@ CONFIG_PROC_EVENTS=y
401# CONFIG_BLK_DEV_DAC960 is not set 385# CONFIG_BLK_DEV_DAC960 is not set
402# CONFIG_BLK_DEV_UMEM is not set 386# CONFIG_BLK_DEV_UMEM is not set
403# CONFIG_BLK_DEV_COW_COMMON is not set 387# CONFIG_BLK_DEV_COW_COMMON is not set
404# CONFIG_BLK_DEV_LOOP is not set 388CONFIG_BLK_DEV_LOOP=y
389# CONFIG_BLK_DEV_CRYPTOLOOP is not set
405# CONFIG_BLK_DEV_NBD is not set 390# CONFIG_BLK_DEV_NBD is not set
406# CONFIG_BLK_DEV_SX8 is not set 391# CONFIG_BLK_DEV_SX8 is not set
407# CONFIG_BLK_DEV_RAM is not set 392CONFIG_BLK_DEV_RAM=y
408# CONFIG_BLK_DEV_INITRD is not set 393CONFIG_BLK_DEV_RAM_COUNT=16
409CONFIG_CDROM_PKTCDVD=y 394CONFIG_BLK_DEV_RAM_SIZE=8192
410CONFIG_CDROM_PKTCDVD_BUFFERS=8 395CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
411# CONFIG_CDROM_PKTCDVD_WCACHE is not set 396# CONFIG_CDROM_PKTCDVD is not set
412CONFIG_ATA_OVER_ETH=y 397# CONFIG_ATA_OVER_ETH is not set
413 398
414# 399#
415# Misc devices 400# Misc devices
416# 401#
417CONFIG_SGI_IOC4=y 402# CONFIG_PHANTOM is not set
403# CONFIG_SGI_IOC4 is not set
418# CONFIG_TIFM_CORE is not set 404# CONFIG_TIFM_CORE is not set
405# CONFIG_BLINK is not set
419 406
420# 407#
421# ATA/ATAPI/MFM/RLL support 408# ATA/ATAPI/MFM/RLL support
@@ -425,7 +412,7 @@ CONFIG_SGI_IOC4=y
425# 412#
426# SCSI device support 413# SCSI device support
427# 414#
428CONFIG_RAID_ATTRS=y 415# CONFIG_RAID_ATTRS is not set
429# CONFIG_SCSI is not set 416# CONFIG_SCSI is not set
430# CONFIG_SCSI_NETLINK is not set 417# CONFIG_SCSI_NETLINK is not set
431 418
@@ -471,27 +458,13 @@ CONFIG_NETDEVICES=y
471# 458#
472# PHY device support 459# PHY device support
473# 460#
474CONFIG_PHYLIB=y 461# CONFIG_PHYLIB is not set
475
476#
477# MII PHY device drivers
478#
479CONFIG_MARVELL_PHY=y
480CONFIG_DAVICOM_PHY=y
481CONFIG_QSEMI_PHY=y
482CONFIG_LXT_PHY=y
483CONFIG_CICADA_PHY=y
484CONFIG_VITESSE_PHY=y
485CONFIG_SMSC_PHY=y
486# CONFIG_BROADCOM_PHY is not set
487# CONFIG_FIXED_PHY is not set
488 462
489# 463#
490# Ethernet (10 or 100Mbit) 464# Ethernet (10 or 100Mbit)
491# 465#
492CONFIG_NET_ETHERNET=y 466CONFIG_NET_ETHERNET=y
493CONFIG_MII=y 467# CONFIG_MII is not set
494CONFIG_GALILEO_64240_ETH=y
495# CONFIG_HAPPYMEAL is not set 468# CONFIG_HAPPYMEAL is not set
496# CONFIG_SUNGEM is not set 469# CONFIG_SUNGEM is not set
497# CONFIG_CASSINI is not set 470# CONFIG_CASSINI is not set
@@ -503,6 +476,7 @@ CONFIG_GALILEO_64240_ETH=y
503# 476#
504# CONFIG_NET_TULIP is not set 477# CONFIG_NET_TULIP is not set
505# CONFIG_HP100 is not set 478# CONFIG_HP100 is not set
479CONFIG_NE2000=y
506# CONFIG_NET_PCI is not set 480# CONFIG_NET_PCI is not set
507 481
508# 482#
@@ -521,18 +495,18 @@ CONFIG_GALILEO_64240_ETH=y
521# CONFIG_SK98LIN is not set 495# CONFIG_SK98LIN is not set
522# CONFIG_TIGON3 is not set 496# CONFIG_TIGON3 is not set
523# CONFIG_BNX2 is not set 497# CONFIG_BNX2 is not set
524CONFIG_QLA3XXX=y 498# CONFIG_QLA3XXX is not set
525# CONFIG_ATL1 is not set 499# CONFIG_ATL1 is not set
526 500
527# 501#
528# Ethernet (10000 Mbit) 502# Ethernet (10000 Mbit)
529# 503#
530# CONFIG_CHELSIO_T1 is not set 504# CONFIG_CHELSIO_T1 is not set
531CONFIG_CHELSIO_T3=y 505# CONFIG_CHELSIO_T3 is not set
532# CONFIG_IXGB is not set 506# CONFIG_IXGB is not set
533# CONFIG_S2IO is not set 507# CONFIG_S2IO is not set
534# CONFIG_MYRI10GE is not set 508# CONFIG_MYRI10GE is not set
535CONFIG_NETXEN_NIC=y 509# CONFIG_NETXEN_NIC is not set
536 510
537# 511#
538# Token Ring devices 512# Token Ring devices
@@ -540,9 +514,10 @@ CONFIG_NETXEN_NIC=y
540# CONFIG_TR is not set 514# CONFIG_TR is not set
541 515
542# 516#
543# Wireless LAN (non-hamradio) 517# Wireless LAN
544# 518#
545# CONFIG_NET_RADIO is not set 519# CONFIG_WLAN_PRE80211 is not set
520# CONFIG_WLAN_80211 is not set
546 521
547# 522#
548# Wan interfaces 523# Wan interfaces
@@ -570,29 +545,7 @@ CONFIG_NETXEN_NIC=y
570# 545#
571# Input device support 546# Input device support
572# 547#
573CONFIG_INPUT=y 548# CONFIG_INPUT is not set
574# CONFIG_INPUT_FF_MEMLESS is not set
575
576#
577# Userland interfaces
578#
579CONFIG_INPUT_MOUSEDEV=y
580CONFIG_INPUT_MOUSEDEV_PSAUX=y
581CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
582CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
583# CONFIG_INPUT_JOYDEV is not set
584# CONFIG_INPUT_TSDEV is not set
585# CONFIG_INPUT_EVDEV is not set
586# CONFIG_INPUT_EVBUG is not set
587
588#
589# Input Device Drivers
590#
591# CONFIG_INPUT_KEYBOARD is not set
592# CONFIG_INPUT_MOUSE is not set
593# CONFIG_INPUT_JOYSTICK is not set
594# CONFIG_INPUT_TOUCHSCREEN is not set
595# CONFIG_INPUT_MISC is not set
596 549
597# 550#
598# Hardware I/O ports 551# Hardware I/O ports
@@ -601,34 +554,31 @@ CONFIG_SERIO=y
601# CONFIG_SERIO_I8042 is not set 554# CONFIG_SERIO_I8042 is not set
602CONFIG_SERIO_SERPORT=y 555CONFIG_SERIO_SERPORT=y
603# CONFIG_SERIO_PCIPS2 is not set 556# CONFIG_SERIO_PCIPS2 is not set
604# CONFIG_SERIO_LIBPS2 is not set 557CONFIG_SERIO_LIBPS2=y
605CONFIG_SERIO_RAW=y 558# CONFIG_SERIO_RAW is not set
606# CONFIG_GAMEPORT is not set 559# CONFIG_GAMEPORT is not set
607 560
608# 561#
609# Character devices 562# Character devices
610# 563#
611CONFIG_VT=y 564# CONFIG_VT is not set
612CONFIG_VT_CONSOLE=y
613CONFIG_HW_CONSOLE=y
614CONFIG_VT_HW_CONSOLE_BINDING=y
615# CONFIG_SERIAL_NONSTANDARD is not set 565# CONFIG_SERIAL_NONSTANDARD is not set
616 566
617# 567#
618# Serial drivers 568# Serial drivers
619# 569#
620CONFIG_SERIAL_8250=y 570# CONFIG_SERIAL_8250 is not set
621CONFIG_SERIAL_8250_CONSOLE=y
622CONFIG_SERIAL_8250_PCI=y
623CONFIG_SERIAL_8250_NR_UARTS=4
624CONFIG_SERIAL_8250_RUNTIME_UARTS=4
625# CONFIG_SERIAL_8250_EXTENDED is not set
626 571
627# 572#
628# Non-8250 serial port support 573# Non-8250 serial port support
629# 574#
630CONFIG_SERIAL_CORE=y 575CONFIG_SERIAL_CORE=y
631CONFIG_SERIAL_CORE_CONSOLE=y 576CONFIG_SERIAL_CORE_CONSOLE=y
577CONFIG_SERIAL_TXX9=y
578CONFIG_HAS_TXX9_SERIAL=y
579CONFIG_SERIAL_TXX9_NR_UARTS=6
580CONFIG_SERIAL_TXX9_CONSOLE=y
581CONFIG_SERIAL_TXX9_STDSERIAL=y
632# CONFIG_SERIAL_JSM is not set 582# CONFIG_SERIAL_JSM is not set
633CONFIG_UNIX98_PTYS=y 583CONFIG_UNIX98_PTYS=y
634CONFIG_LEGACY_PTYS=y 584CONFIG_LEGACY_PTYS=y
@@ -656,10 +606,7 @@ CONFIG_LEGACY_PTY_COUNT=256
656# TPM devices 606# TPM devices
657# 607#
658# CONFIG_TCG_TPM is not set 608# CONFIG_TCG_TPM is not set
659 609CONFIG_DEVPORT=y
660#
661# I2C support
662#
663# CONFIG_I2C is not set 610# CONFIG_I2C is not set
664 611
665# 612#
@@ -672,12 +619,12 @@ CONFIG_LEGACY_PTY_COUNT=256
672# Dallas's 1-wire bus 619# Dallas's 1-wire bus
673# 620#
674# CONFIG_W1 is not set 621# CONFIG_W1 is not set
622# CONFIG_HWMON is not set
675 623
676# 624#
677# Hardware Monitoring support 625# Multifunction device drivers
678# 626#
679# CONFIG_HWMON is not set 627# CONFIG_MFD_SM501 is not set
680# CONFIG_HWMON_VID is not set
681 628
682# 629#
683# Multimedia devices 630# Multimedia devices
@@ -692,15 +639,14 @@ CONFIG_LEGACY_PTY_COUNT=256
692# 639#
693# Graphics support 640# Graphics support
694# 641#
695# CONFIG_FIRMWARE_EDID is not set 642# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
696# CONFIG_FB is not set
697 643
698# 644#
699# Console display driver support 645# Display device support
700# 646#
701# CONFIG_VGA_CONSOLE is not set 647# CONFIG_DISPLAY_SUPPORT is not set
702CONFIG_DUMMY_CONSOLE=y 648# CONFIG_VGASTATE is not set
703# CONFIG_BACKLIGHT_LCD_SUPPORT is not set 649# CONFIG_FB is not set
704 650
705# 651#
706# Sound 652# Sound
@@ -708,11 +654,6 @@ CONFIG_DUMMY_CONSOLE=y
708# CONFIG_SOUND is not set 654# CONFIG_SOUND is not set
709 655
710# 656#
711# HID Devices
712#
713# CONFIG_HID is not set
714
715#
716# USB support 657# USB support
717# 658#
718CONFIG_USB_ARCH_HAS_HCD=y 659CONFIG_USB_ARCH_HAS_HCD=y
@@ -728,10 +669,6 @@ CONFIG_USB_ARCH_HAS_EHCI=y
728# USB Gadget Support 669# USB Gadget Support
729# 670#
730# CONFIG_USB_GADGET is not set 671# CONFIG_USB_GADGET is not set
731
732#
733# MMC/SD Card support
734#
735# CONFIG_MMC is not set 672# CONFIG_MMC is not set
736 673
737# 674#
@@ -759,7 +696,40 @@ CONFIG_USB_ARCH_HAS_EHCI=y
759# 696#
760# Real Time Clock 697# Real Time Clock
761# 698#
762# CONFIG_RTC_CLASS is not set 699CONFIG_RTC_LIB=y
700CONFIG_RTC_CLASS=y
701CONFIG_RTC_HCTOSYS=y
702CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
703# CONFIG_RTC_DEBUG is not set
704
705#
706# RTC interfaces
707#
708CONFIG_RTC_INTF_SYSFS=y
709CONFIG_RTC_INTF_PROC=y
710CONFIG_RTC_INTF_DEV=y
711# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
712# CONFIG_RTC_DRV_TEST is not set
713
714#
715# I2C RTC drivers
716#
717
718#
719# SPI RTC drivers
720#
721
722#
723# Platform RTC drivers
724#
725# CONFIG_RTC_DRV_DS1553 is not set
726CONFIG_RTC_DRV_DS1742=y
727# CONFIG_RTC_DRV_M48T86 is not set
728# CONFIG_RTC_DRV_V3020 is not set
729
730#
731# on-CPU RTC drivers
732#
763 733
764# 734#
765# DMA Engine support 735# DMA Engine support
@@ -785,9 +755,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y
785# 755#
786# File systems 756# File systems
787# 757#
788CONFIG_EXT2_FS=y 758# CONFIG_EXT2_FS is not set
789# CONFIG_EXT2_FS_XATTR is not set
790# CONFIG_EXT2_FS_XIP is not set
791# CONFIG_EXT3_FS is not set 759# CONFIG_EXT3_FS is not set
792# CONFIG_EXT4DEV_FS is not set 760# CONFIG_EXT4DEV_FS is not set
793# CONFIG_REISERFS_FS is not set 761# CONFIG_REISERFS_FS is not set
@@ -801,10 +769,10 @@ CONFIG_FS_POSIX_ACL=y
801CONFIG_INOTIFY=y 769CONFIG_INOTIFY=y
802CONFIG_INOTIFY_USER=y 770CONFIG_INOTIFY_USER=y
803# CONFIG_QUOTA is not set 771# CONFIG_QUOTA is not set
804CONFIG_DNOTIFY=y 772# CONFIG_DNOTIFY is not set
805# CONFIG_AUTOFS_FS is not set 773# CONFIG_AUTOFS_FS is not set
806# CONFIG_AUTOFS4_FS is not set 774# CONFIG_AUTOFS4_FS is not set
807CONFIG_FUSE_FS=y 775# CONFIG_FUSE_FS is not set
808CONFIG_GENERIC_ACL=y 776CONFIG_GENERIC_ACL=y
809 777
810# 778#
@@ -824,21 +792,20 @@ CONFIG_GENERIC_ACL=y
824# Pseudo filesystems 792# Pseudo filesystems
825# 793#
826CONFIG_PROC_FS=y 794CONFIG_PROC_FS=y
827CONFIG_PROC_KCORE=y 795# CONFIG_PROC_KCORE is not set
828CONFIG_PROC_SYSCTL=y 796CONFIG_PROC_SYSCTL=y
829CONFIG_SYSFS=y 797CONFIG_SYSFS=y
830CONFIG_TMPFS=y 798CONFIG_TMPFS=y
831CONFIG_TMPFS_POSIX_ACL=y 799CONFIG_TMPFS_POSIX_ACL=y
832# CONFIG_HUGETLB_PAGE is not set 800# CONFIG_HUGETLB_PAGE is not set
833CONFIG_RAMFS=y 801CONFIG_RAMFS=y
834CONFIG_CONFIGFS_FS=y 802# CONFIG_CONFIGFS_FS is not set
835 803
836# 804#
837# Miscellaneous filesystems 805# Miscellaneous filesystems
838# 806#
839# CONFIG_ADFS_FS is not set 807# CONFIG_ADFS_FS is not set
840# CONFIG_AFFS_FS is not set 808# CONFIG_AFFS_FS is not set
841# CONFIG_ECRYPT_FS is not set
842# CONFIG_HFS_FS is not set 809# CONFIG_HFS_FS is not set
843# CONFIG_HFSPLUS_FS is not set 810# CONFIG_HFSPLUS_FS is not set
844# CONFIG_BEFS_FS is not set 811# CONFIG_BEFS_FS is not set
@@ -855,17 +822,17 @@ CONFIG_CONFIGFS_FS=y
855# Network File Systems 822# Network File Systems
856# 823#
857CONFIG_NFS_FS=y 824CONFIG_NFS_FS=y
858# CONFIG_NFS_V3 is not set 825CONFIG_NFS_V3=y
826# CONFIG_NFS_V3_ACL is not set
859# CONFIG_NFS_V4 is not set 827# CONFIG_NFS_V4 is not set
860# CONFIG_NFS_DIRECTIO is not set 828# CONFIG_NFS_DIRECTIO is not set
861CONFIG_NFSD=y 829# CONFIG_NFSD is not set
862# CONFIG_NFSD_V3 is not set
863# CONFIG_NFSD_TCP is not set
864CONFIG_ROOT_NFS=y 830CONFIG_ROOT_NFS=y
865CONFIG_LOCKD=y 831CONFIG_LOCKD=y
866CONFIG_EXPORTFS=y 832CONFIG_LOCKD_V4=y
867CONFIG_NFS_COMMON=y 833CONFIG_NFS_COMMON=y
868CONFIG_SUNRPC=y 834CONFIG_SUNRPC=y
835# CONFIG_SUNRPC_BIND34 is not set
869# CONFIG_RPCSEC_GSS_KRB5 is not set 836# CONFIG_RPCSEC_GSS_KRB5 is not set
870# CONFIG_RPCSEC_GSS_SPKM3 is not set 837# CONFIG_RPCSEC_GSS_SPKM3 is not set
871# CONFIG_SMB_FS is not set 838# CONFIG_SMB_FS is not set
@@ -889,10 +856,7 @@ CONFIG_MSDOS_PARTITION=y
889# 856#
890# Distributed Lock Manager 857# Distributed Lock Manager
891# 858#
892CONFIG_DLM=y 859# CONFIG_DLM is not set
893CONFIG_DLM_TCP=y
894# CONFIG_DLM_SCTP is not set
895# CONFIG_DLM_DEBUG is not set
896 860
897# 861#
898# Profiling support 862# Profiling support
@@ -910,72 +874,29 @@ CONFIG_ENABLE_MUST_CHECK=y
910# CONFIG_DEBUG_FS is not set 874# CONFIG_DEBUG_FS is not set
911# CONFIG_HEADERS_CHECK is not set 875# CONFIG_HEADERS_CHECK is not set
912# CONFIG_DEBUG_KERNEL is not set 876# CONFIG_DEBUG_KERNEL is not set
913CONFIG_LOG_BUF_SHIFT=14
914CONFIG_CROSSCOMPILE=y 877CONFIG_CROSSCOMPILE=y
915CONFIG_CMDLINE="" 878CONFIG_CMDLINE=""
879CONFIG_SYS_SUPPORTS_KGDB=y
916 880
917# 881#
918# Security options 882# Security options
919# 883#
920CONFIG_KEYS=y 884# CONFIG_KEYS is not set
921CONFIG_KEYS_DEBUG_PROC_KEYS=y
922# CONFIG_SECURITY is not set 885# CONFIG_SECURITY is not set
923 886
924# 887#
925# Cryptographic options 888# Cryptographic options
926# 889#
927CONFIG_CRYPTO=y 890# CONFIG_CRYPTO is not set
928CONFIG_CRYPTO_ALGAPI=y
929CONFIG_CRYPTO_BLKCIPHER=y
930CONFIG_CRYPTO_HASH=y
931CONFIG_CRYPTO_MANAGER=y
932CONFIG_CRYPTO_HMAC=y
933CONFIG_CRYPTO_XCBC=y
934CONFIG_CRYPTO_NULL=y
935CONFIG_CRYPTO_MD4=y
936CONFIG_CRYPTO_MD5=y
937CONFIG_CRYPTO_SHA1=y
938CONFIG_CRYPTO_SHA256=y
939CONFIG_CRYPTO_SHA512=y
940CONFIG_CRYPTO_WP512=y
941CONFIG_CRYPTO_TGR192=y
942CONFIG_CRYPTO_GF128MUL=y
943CONFIG_CRYPTO_ECB=y
944CONFIG_CRYPTO_CBC=y
945CONFIG_CRYPTO_PCBC=y
946CONFIG_CRYPTO_LRW=y
947CONFIG_CRYPTO_DES=y
948CONFIG_CRYPTO_FCRYPT=y
949CONFIG_CRYPTO_BLOWFISH=y
950CONFIG_CRYPTO_TWOFISH=y
951CONFIG_CRYPTO_TWOFISH_COMMON=y
952CONFIG_CRYPTO_SERPENT=y
953CONFIG_CRYPTO_AES=y
954CONFIG_CRYPTO_CAST5=y
955CONFIG_CRYPTO_CAST6=y
956CONFIG_CRYPTO_TEA=y
957CONFIG_CRYPTO_ARC4=y
958CONFIG_CRYPTO_KHAZAD=y
959CONFIG_CRYPTO_ANUBIS=y
960CONFIG_CRYPTO_DEFLATE=y
961CONFIG_CRYPTO_MICHAEL_MIC=y
962CONFIG_CRYPTO_CRC32C=y
963CONFIG_CRYPTO_CAMELLIA=y
964
965#
966# Hardware crypto devices
967#
968 891
969# 892#
970# Library routines 893# Library routines
971# 894#
972CONFIG_BITREVERSE=y 895CONFIG_BITREVERSE=y
973# CONFIG_CRC_CCITT is not set 896# CONFIG_CRC_CCITT is not set
974CONFIG_CRC16=y 897# CONFIG_CRC16 is not set
975CONFIG_CRC32=y 898CONFIG_CRC32=y
976CONFIG_LIBCRC32C=y 899# CONFIG_LIBCRC32C is not set
977CONFIG_ZLIB_INFLATE=y
978CONFIG_ZLIB_DEFLATE=y
979CONFIG_PLIST=y
980CONFIG_HAS_IOMEM=y 900CONFIG_HAS_IOMEM=y
981CONFIG_HAS_IOPORT=y 901CONFIG_HAS_IOPORT=y
902CONFIG_HAS_DMA=y
diff --git a/arch/mips/configs/rbhma4500_defconfig b/arch/mips/configs/rbhma4500_defconfig
index 7d0f2174614e..41011f770a67 100644
--- a/arch/mips/configs/rbhma4500_defconfig
+++ b/arch/mips/configs/rbhma4500_defconfig
@@ -89,7 +89,6 @@ CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
89CONFIG_SWAP_IO_SPACE=y 89CONFIG_SWAP_IO_SPACE=y
90CONFIG_MIPS_L1_CACHE_SHIFT=5 90CONFIG_MIPS_L1_CACHE_SHIFT=5
91CONFIG_HAVE_STD_PC_SERIAL_PORT=y 91CONFIG_HAVE_STD_PC_SERIAL_PORT=y
92CONFIG_TOSHIBA_BOARDS=y
93 92
94# 93#
95# CPU selection 94# CPU selection
diff --git a/arch/mips/configs/tb0229_defconfig b/arch/mips/configs/tb0219_defconfig
index 1756d2bdf6b8..8b1675c07ec4 100644
--- a/arch/mips/configs/tb0229_defconfig
+++ b/arch/mips/configs/tb0219_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.20 3# Linux kernel version: 2.6.21-rc6
4# Tue Feb 20 21:47:41 2007 4# Sun Apr 15 01:06:01 2007
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7 7
@@ -66,10 +66,11 @@ CONFIG_MACH_VR41XX=y
66# CONFIG_IBM_WORKPAD is not set 66# CONFIG_IBM_WORKPAD is not set
67# CONFIG_NEC_CMBVR4133 is not set 67# CONFIG_NEC_CMBVR4133 is not set
68CONFIG_TANBAC_TB022X=y 68CONFIG_TANBAC_TB022X=y
69# CONFIG_TANBAC_TB0226 is not set
70# CONFIG_TANBAC_TB0287 is not set
71# CONFIG_VICTOR_MPC30X is not set 69# CONFIG_VICTOR_MPC30X is not set
72# CONFIG_ZAO_CAPCELLA is not set 70# CONFIG_ZAO_CAPCELLA is not set
71CONFIG_TANBAC_TB0219=y
72# CONFIG_TANBAC_TB0226 is not set
73# CONFIG_TANBAC_TB0287 is not set
73CONFIG_PCI_VR41XX=y 74CONFIG_PCI_VR41XX=y
74CONFIG_RWSEM_GENERIC_SPINLOCK=y 75CONFIG_RWSEM_GENERIC_SPINLOCK=y
75# CONFIG_ARCH_HAS_ILOG2_U32 is not set 76# CONFIG_ARCH_HAS_ILOG2_U32 is not set
@@ -184,6 +185,7 @@ CONFIG_SYSVIPC_SYSCTL=y
184# CONFIG_IKCONFIG is not set 185# CONFIG_IKCONFIG is not set
185CONFIG_SYSFS_DEPRECATED=y 186CONFIG_SYSFS_DEPRECATED=y
186# CONFIG_RELAY is not set 187# CONFIG_RELAY is not set
188# CONFIG_BLK_DEV_INITRD is not set
187# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 189# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
188CONFIG_SYSCTL=y 190CONFIG_SYSCTL=y
189CONFIG_EMBEDDED=y 191CONFIG_EMBEDDED=y
@@ -375,7 +377,7 @@ CONFIG_FIB_RULES=y
375# 377#
376CONFIG_STANDALONE=y 378CONFIG_STANDALONE=y
377CONFIG_PREVENT_FIRMWARE_BUILD=y 379CONFIG_PREVENT_FIRMWARE_BUILD=y
378# CONFIG_FW_LOADER is not set 380CONFIG_FW_LOADER=m
379# CONFIG_SYS_HYPERVISOR is not set 381# CONFIG_SYS_HYPERVISOR is not set
380 382
381# 383#
@@ -415,7 +417,6 @@ CONFIG_BLK_DEV_RAM=y
415CONFIG_BLK_DEV_RAM_COUNT=16 417CONFIG_BLK_DEV_RAM_COUNT=16
416CONFIG_BLK_DEV_RAM_SIZE=4096 418CONFIG_BLK_DEV_RAM_SIZE=4096
417CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 419CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
418# CONFIG_BLK_DEV_INITRD is not set
419# CONFIG_CDROM_PKTCDVD is not set 420# CONFIG_CDROM_PKTCDVD is not set
420# CONFIG_ATA_OVER_ETH is not set 421# CONFIG_ATA_OVER_ETH is not set
421 422
@@ -646,7 +647,7 @@ CONFIG_LEGACY_PTY_COUNT=256
646# CONFIG_DTLK is not set 647# CONFIG_DTLK is not set
647# CONFIG_R3964 is not set 648# CONFIG_R3964 is not set
648# CONFIG_APPLICOM is not set 649# CONFIG_APPLICOM is not set
649CONFIG_TANBAC_TB0219=y 650CONFIG_GPIO_TB0219=y
650# CONFIG_DRM is not set 651# CONFIG_DRM is not set
651CONFIG_GPIO_VR41XX=y 652CONFIG_GPIO_VR41XX=y
652# CONFIG_RAW_DRIVER is not set 653# CONFIG_RAW_DRIVER is not set
@@ -679,6 +680,11 @@ CONFIG_GPIO_VR41XX=y
679# CONFIG_HWMON_VID is not set 680# CONFIG_HWMON_VID is not set
680 681
681# 682#
683# Multifunction device drivers
684#
685# CONFIG_MFD_SM501 is not set
686
687#
682# Multimedia devices 688# Multimedia devices
683# 689#
684# CONFIG_VIDEO_DEV is not set 690# CONFIG_VIDEO_DEV is not set
@@ -692,7 +698,7 @@ CONFIG_GPIO_VR41XX=y
692# 698#
693# Graphics support 699# Graphics support
694# 700#
695# CONFIG_FIRMWARE_EDID is not set 701# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
696# CONFIG_FB is not set 702# CONFIG_FB is not set
697 703
698# 704#
@@ -700,7 +706,6 @@ CONFIG_GPIO_VR41XX=y
700# 706#
701# CONFIG_VGA_CONSOLE is not set 707# CONFIG_VGA_CONSOLE is not set
702CONFIG_DUMMY_CONSOLE=y 708CONFIG_DUMMY_CONSOLE=y
703# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
704 709
705# 710#
706# Sound 711# Sound
@@ -831,6 +836,7 @@ CONFIG_USB_MON=y
831# CONFIG_USB_SISUSBVGA is not set 836# CONFIG_USB_SISUSBVGA is not set
832# CONFIG_USB_LD is not set 837# CONFIG_USB_LD is not set
833# CONFIG_USB_TRANCEVIBRATOR is not set 838# CONFIG_USB_TRANCEVIBRATOR is not set
839# CONFIG_USB_IOWARRIOR is not set
834# CONFIG_USB_TEST is not set 840# CONFIG_USB_TEST is not set
835 841
836# 842#
diff --git a/arch/mips/kernel/early_printk.c b/arch/mips/kernel/early_printk.c
index 4fa54b230c09..9dccfa4752b2 100644
--- a/arch/mips/kernel/early_printk.c
+++ b/arch/mips/kernel/early_printk.c
@@ -12,7 +12,8 @@
12 12
13extern void prom_putchar(char); 13extern void prom_putchar(char);
14 14
15static void early_console_write(struct console *con, const char *s, unsigned n) 15static void __init
16early_console_write(struct console *con, const char *s, unsigned n)
16{ 17{
17 while (n-- && *s) { 18 while (n-- && *s) {
18 if (*s == '\n') 19 if (*s == '\n')
@@ -22,14 +23,20 @@ static void early_console_write(struct console *con, const char *s, unsigned n)
22 } 23 }
23} 24}
24 25
25static struct console early_console = { 26static struct console early_console __initdata = {
26 .name = "early", 27 .name = "early",
27 .write = early_console_write, 28 .write = early_console_write,
28 .flags = CON_PRINTBUFFER | CON_BOOT, 29 .flags = CON_PRINTBUFFER | CON_BOOT,
29 .index = -1 30 .index = -1
30}; 31};
31 32
33static int early_console_initialized __initdata;
34
32void __init setup_early_printk(void) 35void __init setup_early_printk(void)
33{ 36{
37 if (early_console_initialized)
38 return;
39 early_console_initialized = 1;
40
34 register_console(&early_console); 41 register_console(&early_console);
35} 42}
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c
index 2967537221e2..410868b5ea5f 100644
--- a/arch/mips/kernel/irq-msc01.c
+++ b/arch/mips/kernel/irq-msc01.c
@@ -132,11 +132,11 @@ struct irq_chip msc_edgeirq_type = {
132}; 132};
133 133
134 134
135void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq) 135void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqmap_t *imp, int nirq)
136{ 136{
137 extern void (*board_bind_eic_interrupt)(unsigned int irq, unsigned int regset); 137 extern void (*board_bind_eic_interrupt)(unsigned int irq, unsigned int regset);
138 138
139 _icctrl_msc = (unsigned long) ioremap (MIPS_MSC01_IC_REG_BASE, 0x40000); 139 _icctrl_msc = (unsigned long) ioremap (icubase, 0x40000);
140 140
141 /* Reset interrupt controller - initialises all registers to 0 */ 141 /* Reset interrupt controller - initialises all registers to 0 */
142 MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT); 142 MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT);
@@ -148,14 +148,14 @@ void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq)
148 148
149 switch (imp->im_type) { 149 switch (imp->im_type) {
150 case MSC01_IRQ_EDGE: 150 case MSC01_IRQ_EDGE:
151 set_irq_chip(base+n, &msc_edgeirq_type); 151 set_irq_chip(irqbase+n, &msc_edgeirq_type);
152 if (cpu_has_veic) 152 if (cpu_has_veic)
153 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); 153 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
154 else 154 else
155 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); 155 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
156 break; 156 break;
157 case MSC01_IRQ_LEVEL: 157 case MSC01_IRQ_LEVEL:
158 set_irq_chip(base+n, &msc_levelirq_type); 158 set_irq_chip(irqbase+n, &msc_levelirq_type);
159 if (cpu_has_veic) 159 if (cpu_has_veic)
160 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); 160 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
161 else 161 else
@@ -163,7 +163,7 @@ void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq)
163 } 163 }
164 } 164 }
165 165
166 irq_base = base; 166 irq_base = irqbase;
167 167
168 MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */ 168 MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */
169 169
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index 2fe4c868a801..aeded6c17de5 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -28,7 +28,7 @@
28 28
29static unsigned long irq_map[NR_IRQS / BITS_PER_LONG]; 29static unsigned long irq_map[NR_IRQS / BITS_PER_LONG];
30 30
31int __devinit allocate_irqno(void) 31int allocate_irqno(void)
32{ 32{
33 int irq; 33 int irq;
34 34
@@ -59,7 +59,7 @@ void __init alloc_legacy_irqno(void)
59 BUG_ON(test_and_set_bit(i, irq_map)); 59 BUG_ON(test_and_set_bit(i, irq_map));
60} 60}
61 61
62void __devinit free_irqno(unsigned int irq) 62void free_irqno(unsigned int irq)
63{ 63{
64 smp_mb__before_clear_bit(); 64 smp_mb__before_clear_bit();
65 clear_bit(irq, irq_map); 65 clear_bit(irq, irq_map);
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index e5e56bd498db..751b4a18b133 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -306,7 +306,7 @@ static unsigned int __init calibrate_hpt(void)
306 306
307struct clocksource clocksource_mips = { 307struct clocksource clocksource_mips = {
308 .name = "MIPS", 308 .name = "MIPS",
309 .mask = 0xffffffff, 309 .mask = CLOCKSOURCE_MASK(32),
310 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 310 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
311}; 311};
312 312
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index ff45a4b8fbaa..200de027f354 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -927,9 +927,9 @@ asmlinkage void do_reserved(struct pt_regs *regs)
927 (regs->cp0_cause & 0x7f) >> 2); 927 (regs->cp0_cause & 0x7f) >> 2);
928} 928}
929 929
930asmlinkage void do_default_vi(struct pt_regs *regs) 930static asmlinkage void do_default_vi(void)
931{ 931{
932 show_regs(regs); 932 show_regs(get_irq_regs());
933 panic("Caught unexpected vectored interrupt."); 933 panic("Caught unexpected vectored interrupt.");
934} 934}
935 935
@@ -1128,7 +1128,7 @@ void mips_srs_free(int set)
1128 clear_bit(set, &sr->sr_allocated); 1128 clear_bit(set, &sr->sr_allocated);
1129} 1129}
1130 1130
1131static void *set_vi_srs_handler(int n, void *addr, int srs) 1131static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1132{ 1132{
1133 unsigned long handler; 1133 unsigned long handler;
1134 unsigned long old_handler = vi_handlers[n]; 1134 unsigned long old_handler = vi_handlers[n];
@@ -1217,7 +1217,7 @@ static void *set_vi_srs_handler(int n, void *addr, int srs)
1217 return (void *)old_handler; 1217 return (void *)old_handler;
1218} 1218}
1219 1219
1220void *set_vi_handler(int n, void *addr) 1220void *set_vi_handler(int n, vi_handler_t addr)
1221{ 1221{
1222 return set_vi_srs_handler(n, addr, 0); 1222 return set_vi_srs_handler(n, addr, 0);
1223} 1223}
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index d7d3b14dcfb2..5dad13efba7e 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -9,4 +9,4 @@ obj-y += iomap.o
9obj-$(CONFIG_PCI) += iomap-pci.o 9obj-$(CONFIG_PCI) += iomap-pci.o
10 10
11# libgcc-style stuff needed in the kernel 11# libgcc-style stuff needed in the kernel
12lib-y += ashldi3.o ashrdi3.o lshrdi3.o 12lib-y += ashldi3.o ashrdi3.o lshrdi3.o ucmpdi2.o
diff --git a/arch/mips/lib/ucmpdi2.c b/arch/mips/lib/ucmpdi2.c
new file mode 100644
index 000000000000..e9ff258ef028
--- /dev/null
+++ b/arch/mips/lib/ucmpdi2.c
@@ -0,0 +1,19 @@
1#include <linux/module.h>
2
3#include "libgcc.h"
4
5word_type __ucmpdi2 (unsigned long a, unsigned long b)
6{
7 const DWunion au = {.ll = a};
8 const DWunion bu = {.ll = b};
9
10 if ((unsigned int) au.s.high < (unsigned int) bu.s.high)
11 return 0;
12 else if ((unsigned int) au.s.high > (unsigned int) bu.s.high)
13 return 2;
14 if ((unsigned int) au.s.low < (unsigned int) bu.s.low)
15 return 0;
16 else if ((unsigned int) au.s.low > (unsigned int) bu.s.low)
17 return 2;
18 return 1;
19}
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index 83d76025d61d..1cd830e3d933 100644
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -311,16 +311,21 @@ void __init arch_init_irq(void)
311 if (!cpu_has_veic) 311 if (!cpu_has_veic)
312 mips_cpu_irq_init(); 312 mips_cpu_irq_init();
313 313
314 switch(mips_revision_corid) { 314 switch(mips_revision_sconid) {
315 case MIPS_REVISION_CORID_CORE_MSC: 315 case MIPS_REVISION_SCON_SOCIT:
316 case MIPS_REVISION_CORID_CORE_FPGA2: 316 case MIPS_REVISION_SCON_ROCIT:
317 case MIPS_REVISION_CORID_CORE_FPGA3: 317 if (cpu_has_veic)
318 case MIPS_REVISION_CORID_CORE_24K: 318 init_msc_irqs (MIPS_MSC01_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
319 case MIPS_REVISION_CORID_CORE_EMUL_MSC: 319 else
320 init_msc_irqs (MIPS_MSC01_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
321 break;
322
323 case MIPS_REVISION_SCON_SOCITSC:
324 case MIPS_REVISION_SCON_SOCITSCP:
320 if (cpu_has_veic) 325 if (cpu_has_veic)
321 init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); 326 init_msc_irqs (MIPS_SOCITSC_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
322 else 327 else
323 init_msc_irqs (MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); 328 init_msc_irqs (MIPS_SOCITSC_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
324 } 329 }
325 330
326 if (cpu_has_veic) { 331 if (cpu_has_veic) {
diff --git a/arch/mips/mm/highmem.c b/arch/mips/mm/highmem.c
index 675502ada5a2..10dd2af2343b 100644
--- a/arch/mips/mm/highmem.c
+++ b/arch/mips/mm/highmem.c
@@ -80,7 +80,6 @@ void __kunmap_atomic(void *kvaddr, enum km_type type)
80 pagefault_enable(); 80 pagefault_enable();
81} 81}
82 82
83#ifndef CONFIG_LIMITED_DMA
84/* 83/*
85 * This is the same as kmap_atomic() but can map memory that doesn't 84 * This is the same as kmap_atomic() but can map memory that doesn't
86 * have a struct page associated with it. 85 * have a struct page associated with it.
@@ -99,7 +98,6 @@ void *kmap_atomic_pfn(unsigned long pfn, enum km_type type)
99 98
100 return (void*) vaddr; 99 return (void*) vaddr;
101} 100}
102#endif /* CONFIG_LIMITED_DMA */
103 101
104struct page *__kmap_atomic_to_page(void *ptr) 102struct page *__kmap_atomic_to_page(void *ptr)
105{ 103{
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 2d1c2c024822..4c80528deadd 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -424,9 +424,6 @@ void __init mem_init(void)
424 continue; 424 continue;
425 } 425 }
426 ClearPageReserved(page); 426 ClearPageReserved(page);
427#ifdef CONFIG_LIMITED_DMA
428 set_page_address(page, lowmem_page_address(page));
429#endif
430 init_page_count(page); 427 init_page_count(page);
431 __free_page(page); 428 __free_page(page);
432 totalhigh_pages++; 429 totalhigh_pages++;
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 492c518e7ba5..e7149290d1cb 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -35,24 +35,24 @@
35#include <asm/smp.h> 35#include <asm/smp.h>
36#include <asm/war.h> 36#include <asm/war.h>
37 37
38static __init int __attribute__((unused)) r45k_bvahwbug(void) 38static __init int __maybe_unused r45k_bvahwbug(void)
39{ 39{
40 /* XXX: We should probe for the presence of this bug, but we don't. */ 40 /* XXX: We should probe for the presence of this bug, but we don't. */
41 return 0; 41 return 0;
42} 42}
43 43
44static __init int __attribute__((unused)) r4k_250MHZhwbug(void) 44static __init int __maybe_unused r4k_250MHZhwbug(void)
45{ 45{
46 /* XXX: We should probe for the presence of this bug, but we don't. */ 46 /* XXX: We should probe for the presence of this bug, but we don't. */
47 return 0; 47 return 0;
48} 48}
49 49
50static __init int __attribute__((unused)) bcm1250_m3_war(void) 50static __init int __maybe_unused bcm1250_m3_war(void)
51{ 51{
52 return BCM1250_M3_WAR; 52 return BCM1250_M3_WAR;
53} 53}
54 54
55static __init int __attribute__((unused)) r10000_llsc_war(void) 55static __init int __maybe_unused r10000_llsc_war(void)
56{ 56{
57 return R10000_LLSC_WAR; 57 return R10000_LLSC_WAR;
58} 58}
@@ -511,18 +511,18 @@ L_LA(_r3000_write_probe_fail)
511#define i_ehb(buf) i_sll(buf, 0, 0, 3) 511#define i_ehb(buf) i_sll(buf, 0, 0, 3)
512 512
513#ifdef CONFIG_64BIT 513#ifdef CONFIG_64BIT
514static __init int __attribute__((unused)) in_compat_space_p(long addr) 514static __init int __maybe_unused in_compat_space_p(long addr)
515{ 515{
516 /* Is this address in 32bit compat space? */ 516 /* Is this address in 32bit compat space? */
517 return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L); 517 return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
518} 518}
519 519
520static __init int __attribute__((unused)) rel_highest(long val) 520static __init int __maybe_unused rel_highest(long val)
521{ 521{
522 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; 522 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
523} 523}
524 524
525static __init int __attribute__((unused)) rel_higher(long val) 525static __init int __maybe_unused rel_higher(long val)
526{ 526{
527 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; 527 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
528} 528}
@@ -556,8 +556,8 @@ static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr)
556 i_lui(buf, rs, rel_hi(addr)); 556 i_lui(buf, rs, rel_hi(addr));
557} 557}
558 558
559static __init void __attribute__((unused)) i_LA(u32 **buf, unsigned int rs, 559static __init void __maybe_unused i_LA(u32 **buf, unsigned int rs,
560 long addr) 560 long addr)
561{ 561{
562 i_LA_mostly(buf, rs, addr); 562 i_LA_mostly(buf, rs, addr);
563 if (rel_lo(addr)) 563 if (rel_lo(addr))
@@ -636,8 +636,8 @@ static __init void copy_handler(struct reloc *rel, struct label *lab,
636 move_labels(lab, first, end, off); 636 move_labels(lab, first, end, off);
637} 637}
638 638
639static __init int __attribute__((unused)) insn_has_bdelay(struct reloc *rel, 639static __init int __maybe_unused insn_has_bdelay(struct reloc *rel,
640 u32 *addr) 640 u32 *addr)
641{ 641{
642 for (; rel->lab != label_invalid; rel++) { 642 for (; rel->lab != label_invalid; rel++) {
643 if (rel->addr == addr 643 if (rel->addr == addr
@@ -650,15 +650,15 @@ static __init int __attribute__((unused)) insn_has_bdelay(struct reloc *rel,
650} 650}
651 651
652/* convenience functions for labeled branches */ 652/* convenience functions for labeled branches */
653static void __init __attribute__((unused)) 653static void __init __maybe_unused
654 il_bltz(u32 **p, struct reloc **r, unsigned int reg, enum label_id l) 654 il_bltz(u32 **p, struct reloc **r, unsigned int reg, enum label_id l)
655{ 655{
656 r_mips_pc16(r, *p, l); 656 r_mips_pc16(r, *p, l);
657 i_bltz(p, reg, 0); 657 i_bltz(p, reg, 0);
658} 658}
659 659
660static void __init __attribute__((unused)) il_b(u32 **p, struct reloc **r, 660static void __init __maybe_unused il_b(u32 **p, struct reloc **r,
661 enum label_id l) 661 enum label_id l)
662{ 662{
663 r_mips_pc16(r, *p, l); 663 r_mips_pc16(r, *p, l);
664 i_b(p, 0); 664 i_b(p, 0);
@@ -671,7 +671,7 @@ static void __init il_beqz(u32 **p, struct reloc **r, unsigned int reg,
671 i_beqz(p, reg, 0); 671 i_beqz(p, reg, 0);
672} 672}
673 673
674static void __init __attribute__((unused)) 674static void __init __maybe_unused
675il_beqzl(u32 **p, struct reloc **r, unsigned int reg, enum label_id l) 675il_beqzl(u32 **p, struct reloc **r, unsigned int reg, enum label_id l)
676{ 676{
677 r_mips_pc16(r, *p, l); 677 r_mips_pc16(r, *p, l);
@@ -692,7 +692,7 @@ static void __init il_bgezl(u32 **p, struct reloc **r, unsigned int reg,
692 i_bgezl(p, reg, 0); 692 i_bgezl(p, reg, 0);
693} 693}
694 694
695static void __init __attribute__((unused)) 695static void __init __maybe_unused
696il_bgez(u32 **p, struct reloc **r, unsigned int reg, enum label_id l) 696il_bgez(u32 **p, struct reloc **r, unsigned int reg, enum label_id l)
697{ 697{
698 r_mips_pc16(r, *p, l); 698 r_mips_pc16(r, *p, l);
@@ -810,7 +810,7 @@ static __initdata u32 final_handler[64];
810 * 810 *
811 * As if we MIPS hackers wouldn't know how to nop pipelines happy ... 811 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
812 */ 812 */
813static __init void __attribute__((unused)) build_tlb_probe_entry(u32 **p) 813static __init void __maybe_unused build_tlb_probe_entry(u32 **p)
814{ 814{
815 switch (current_cpu_data.cputype) { 815 switch (current_cpu_data.cputype) {
816 /* Found by experiment: R4600 v2.0 needs this, too. */ 816 /* Found by experiment: R4600 v2.0 needs this, too. */
@@ -1098,7 +1098,7 @@ build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r,
1098 * TMP and PTR are scratch. 1098 * TMP and PTR are scratch.
1099 * TMP will be clobbered, PTR will hold the pgd entry. 1099 * TMP will be clobbered, PTR will hold the pgd entry.
1100 */ 1100 */
1101static __init void __attribute__((unused)) 1101static __init void __maybe_unused
1102build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) 1102build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
1103{ 1103{
1104 long pgdc = (long)pgd_current; 1104 long pgdc = (long)pgd_current;
diff --git a/arch/mips/momentum/Kconfig b/arch/mips/momentum/Kconfig
deleted file mode 100644
index 70a61cf7174d..000000000000
--- a/arch/mips/momentum/Kconfig
+++ /dev/null
@@ -1,6 +0,0 @@
1config JAGUAR_DMALOW
2 bool "Low DMA Mode"
3 depends on MOMENCO_JAGUAR_ATX
4 help
5 Select to Y if jump JP5 is set on your board, N otherwise. Normally
6 the jumper is set, so if you feel unsafe, just say Y.
diff --git a/arch/mips/momentum/jaguar_atx/Makefile b/arch/mips/momentum/jaguar_atx/Makefile
deleted file mode 100644
index 2e8cebd49bc0..000000000000
--- a/arch/mips/momentum/jaguar_atx/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
1#
2# Makefile for Momentum Computer's Jaguar-ATX board.
3#
4# Note! Dependencies are done automagically by 'make dep', which also
5# removes any old dependencies. DON'T put your own dependencies here
6# unless it's something special (ie not a .c file).
7#
8
9obj-y += irq.o platform.o prom.o reset.o setup.o
10
11obj-$(CONFIG_SERIAL_8250_CONSOLE) += ja-console.o
12obj-$(CONFIG_REMOTE_DEBUG) += dbg_io.o
diff --git a/arch/mips/momentum/jaguar_atx/dbg_io.c b/arch/mips/momentum/jaguar_atx/dbg_io.c
deleted file mode 100644
index b85a6521f72d..000000000000
--- a/arch/mips/momentum/jaguar_atx/dbg_io.c
+++ /dev/null
@@ -1,125 +0,0 @@
1
2#if defined(CONFIG_REMOTE_DEBUG)
3
4#include <asm/serial.h> /* For the serial port location and base baud */
5
6/* --- CONFIG --- */
7
8typedef unsigned char uint8;
9typedef unsigned int uint32;
10
11/* --- END OF CONFIG --- */
12
13#define UART16550_BAUD_2400 2400
14#define UART16550_BAUD_4800 4800
15#define UART16550_BAUD_9600 9600
16#define UART16550_BAUD_19200 19200
17#define UART16550_BAUD_38400 38400
18#define UART16550_BAUD_57600 57600
19#define UART16550_BAUD_115200 115200
20
21#define UART16550_PARITY_NONE 0
22#define UART16550_PARITY_ODD 0x08
23#define UART16550_PARITY_EVEN 0x18
24#define UART16550_PARITY_MARK 0x28
25#define UART16550_PARITY_SPACE 0x38
26
27#define UART16550_DATA_5BIT 0x0
28#define UART16550_DATA_6BIT 0x1
29#define UART16550_DATA_7BIT 0x2
30#define UART16550_DATA_8BIT 0x3
31
32#define UART16550_STOP_1BIT 0x0
33#define UART16550_STOP_2BIT 0x4
34
35/* ----------------------------------------------------- */
36
37/* === CONFIG === */
38
39/* [jsun] we use the second serial port for kdb */
40#define BASE OCELOT_SERIAL1_BASE
41#define MAX_BAUD OCELOT_BASE_BAUD
42
43/* === END OF CONFIG === */
44
45#define REG_OFFSET 4
46
47/* register offset */
48#define OFS_RCV_BUFFER 0
49#define OFS_TRANS_HOLD 0
50#define OFS_SEND_BUFFER 0
51#define OFS_INTR_ENABLE (1*REG_OFFSET)
52#define OFS_INTR_ID (2*REG_OFFSET)
53#define OFS_DATA_FORMAT (3*REG_OFFSET)
54#define OFS_LINE_CONTROL (3*REG_OFFSET)
55#define OFS_MODEM_CONTROL (4*REG_OFFSET)
56#define OFS_RS232_OUTPUT (4*REG_OFFSET)
57#define OFS_LINE_STATUS (5*REG_OFFSET)
58#define OFS_MODEM_STATUS (6*REG_OFFSET)
59#define OFS_RS232_INPUT (6*REG_OFFSET)
60#define OFS_SCRATCH_PAD (7*REG_OFFSET)
61
62#define OFS_DIVISOR_LSB (0*REG_OFFSET)
63#define OFS_DIVISOR_MSB (1*REG_OFFSET)
64
65
66/* memory-mapped read/write of the port */
67#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
68#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
69
70void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
71{
72 /* disable interrupts */
73 UART16550_WRITE(OFS_INTR_ENABLE, 0);
74
75 /* set up baud rate */
76 {
77 uint32 divisor;
78
79 /* set DIAB bit */
80 UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
81
82 /* set divisor */
83 divisor = MAX_BAUD / baud;
84 UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
85 UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
86
87 /* clear DIAB bit */
88 UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
89 }
90
91 /* set data format */
92 UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
93}
94
95static int remoteDebugInitialized = 0;
96
97uint8 getDebugChar(void)
98{
99 if (!remoteDebugInitialized) {
100 remoteDebugInitialized = 1;
101 debugInit(UART16550_BAUD_38400,
102 UART16550_DATA_8BIT,
103 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
104 }
105
106 while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
107 return UART16550_READ(OFS_RCV_BUFFER);
108}
109
110
111int putDebugChar(uint8 byte)
112{
113 if (!remoteDebugInitialized) {
114 remoteDebugInitialized = 1;
115 debugInit(UART16550_BAUD_38400,
116 UART16550_DATA_8BIT,
117 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
118 }
119
120 while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
121 UART16550_WRITE(OFS_SEND_BUFFER, byte);
122 return 1;
123}
124
125#endif
diff --git a/arch/mips/momentum/jaguar_atx/irq.c b/arch/mips/momentum/jaguar_atx/irq.c
deleted file mode 100644
index f2b432585df2..000000000000
--- a/arch/mips/momentum/jaguar_atx/irq.c
+++ /dev/null
@@ -1,94 +0,0 @@
1/*
2 * Copyright (C) 2002 Momentum Computer, Inc.
3 * Author: Matthew Dharm, mdharm@momenco.com
4 *
5 * Based on work by:
6 * Copyright (C) 2000 RidgeRun, Inc.
7 * Author: RidgeRun, Inc.
8 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
9 *
10 * Copyright 2001 MontaVista Software Inc.
11 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
12 *
13 * Copyright (C) 2000, 01, 06 Ralf Baechle (ralf@linux-mips.org)
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
23 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
26 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * You should have received a copy of the GNU General Public License along
32 * with this program; if not, write to the Free Software Foundation, Inc.,
33 * 675 Mass Ave, Cambridge, MA 02139, USA.
34 */
35#include <linux/init.h>
36#include <linux/interrupt.h>
37#include <linux/signal.h>
38#include <linux/types.h>
39#include <asm/irq_cpu.h>
40#include <asm/mipsregs.h>
41#include <asm/time.h>
42
43asmlinkage void plat_irq_dispatch(void)
44{
45 unsigned int pending = read_c0_cause() & read_c0_status();
46
47 if (pending & STATUSF_IP0)
48 do_IRQ(0);
49 else if (pending & STATUSF_IP1)
50 do_IRQ(1);
51 else if (pending & STATUSF_IP2)
52 do_IRQ(2);
53 else if (pending & STATUSF_IP3)
54 do_IRQ(3);
55 else if (pending & STATUSF_IP4)
56 do_IRQ(4);
57 else if (pending & STATUSF_IP5)
58 do_IRQ(5);
59 else if (pending & STATUSF_IP6)
60 do_IRQ(6);
61 else if (pending & STATUSF_IP7)
62 ll_timer_interrupt(7);
63 else {
64 /*
65 * Now look at the extended interrupts
66 */
67 pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16;
68 if (pending & STATUSF_IP8)
69 ll_mv64340_irq();
70 }
71}
72
73static struct irqaction cascade_mv64340 = {
74 no_action, IRQF_DISABLED, CPU_MASK_NONE, "MV64340-Cascade", NULL, NULL
75};
76
77void __init arch_init_irq(void)
78{
79 /*
80 * Clear all of the interrupts while we change the able around a bit.
81 * int-handler is not on bootstrap
82 */
83 clear_c0_status(ST0_IM);
84
85 mips_cpu_irq_init();
86 rm7k_cpu_irq_init();
87
88 /* set up the cascading interrupts */
89 setup_irq(8, &cascade_mv64340);
90
91 mv64340_irq_init(16);
92
93 set_c0_status(ST0_IM);
94}
diff --git a/arch/mips/momentum/jaguar_atx/ja-console.c b/arch/mips/momentum/jaguar_atx/ja-console.c
deleted file mode 100644
index 2c30b4f56245..000000000000
--- a/arch/mips/momentum/jaguar_atx/ja-console.c
+++ /dev/null
@@ -1,101 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2001, 2002, 2004 Ralf Baechle
7 */
8#include <linux/init.h>
9#include <linux/console.h>
10#include <linux/kdev_t.h>
11#include <linux/major.h>
12#include <linux/termios.h>
13#include <linux/sched.h>
14#include <linux/tty.h>
15
16#include <linux/serial.h>
17#include <linux/serial_core.h>
18#include <asm/serial.h>
19
20/* SUPERIO uart register map */
21struct ja_uartregs {
22 union {
23 volatile u8 pad0[3];
24 volatile u8 rbr; /* read only, DLAB == 0 */
25 volatile u8 pad1[3];
26 volatile u8 thr; /* write only, DLAB == 0 */
27 volatile u8 pad2[3];
28 volatile u8 dll; /* DLAB == 1 */
29 } u1;
30 union {
31 volatile u8 pad0[3];
32 volatile u8 ier; /* DLAB == 0 */
33 volatile u8 pad1[3];
34 volatile u8 dlm; /* DLAB == 1 */
35 } u2;
36 union {
37 volatile u8 pad0[3];
38 volatile u8 iir; /* read only */
39 volatile u8 pad1[3];
40 volatile u8 fcr; /* write only */
41 } u3;
42 volatile u8 pad0[3];
43 volatile u8 iu_lcr;
44 volatile u8 pad1[3];
45 volatile u8 iu_mcr;
46 volatile u8 pad2[3];
47 volatile u8 iu_lsr;
48 volatile u8 pad3[3];
49 volatile u8 iu_msr;
50 volatile u8 pad4[3];
51 volatile u8 iu_scr;
52} ja_uregs_t;
53
54#define iu_rbr u1.rbr
55#define iu_thr u1.thr
56#define iu_dll u1.dll
57#define iu_ier u2.ier
58#define iu_dlm u2.dlm
59#define iu_iir u3.iir
60#define iu_fcr u3.fcr
61
62extern unsigned long uart_base;
63
64static inline struct ja_uartregs *console_uart(void)
65{
66 return (struct ja_uartregs *) (uart_base + 0x23UL);
67}
68
69void prom_putchar(char c)
70{
71 struct ja_uartregs *uart = console_uart();
72
73 while ((uart->iu_lsr & 0x20) == 0);
74 uart->iu_thr = c;
75}
76
77static void inline ja_console_probe(void)
78{
79 struct uart_port up;
80
81 /*
82 * Register to interrupt zero because we share the interrupt with
83 * the serial driver which we don't properly support yet.
84 */
85 memset(&up, 0, sizeof(up));
86 up.membase = (unsigned char *) uart_base + 0x23UL;
87 up.irq = JAGUAR_ATX_SERIAL1_IRQ;
88 up.uartclk = JAGUAR_ATX_UART_CLK;
89 up.regshift = 2;
90 up.iotype = UPIO_MEM;
91 up.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
92 up.line = 0;
93
94 if (early_serial_setup(&up))
95 printk(KERN_ERR "Early serial init of port 0 failed\n");
96}
97
98__init void ja_setup_console(void)
99{
100 ja_console_probe();
101}
diff --git a/arch/mips/momentum/jaguar_atx/jaguar_atx_fpga.h b/arch/mips/momentum/jaguar_atx/jaguar_atx_fpga.h
deleted file mode 100644
index 022f6974b76e..000000000000
--- a/arch/mips/momentum/jaguar_atx/jaguar_atx_fpga.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * Jaguar-ATX Board Register Definitions
3 *
4 * (C) 2002 Momentum Computer Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26#ifndef __JAGUAR_ATX_FPGA_H__
27#define __JAGUAR_ATX_FPGA_H__
28
29#define JAGUAR_ATX_REG_BOARDREV 0x0
30#define JAGUAR_ATX_REG_FPGA_REV 0x1
31#define JAGUAR_ATX_REG_FPGA_TYPE 0x2
32#define JAGUAR_ATX_REG_RESET_STATUS 0x3
33#define JAGUAR_ATX_REG_BOARD_STATUS 0x4
34#define JAGUAR_ATX_REG_RESERVED1 0x5
35#define JAGUAR_ATX_REG_SET 0x6
36#define JAGUAR_ATX_REG_CLR 0x7
37#define JAGUAR_ATX_REG_EEPROM_MODE 0x9
38#define JAGUAR_ATX_REG_RESERVED2 0xa
39#define JAGUAR_ATX_REG_RESERVED3 0xb
40#define JAGUAR_ATX_REG_RESERVED4 0xc
41#define JAGUAR_ATX_REG_PHY_INTSTAT 0xd
42#define JAGUAR_ATX_REG_RESERVED5 0xe
43#define JAGUAR_ATX_REG_RESERVED6 0xf
44
45#define JAGUAR_ATX_CS0_ADDR 0xfc000000L
46
47extern unsigned long ja_fpga_base;
48
49#define __FPGA_REG_TO_ADDR(reg) \
50 ((void *) ja_fpga_base + JAGUAR_ATX_REG_##reg)
51#define JAGUAR_FPGA_WRITE(x, reg) writeb(x, __FPGA_REG_TO_ADDR(reg))
52#define JAGUAR_FPGA_READ(reg) readb(__FPGA_REG_TO_ADDR(reg))
53
54#endif
diff --git a/arch/mips/momentum/jaguar_atx/platform.c b/arch/mips/momentum/jaguar_atx/platform.c
deleted file mode 100644
index 561844878a90..000000000000
--- a/arch/mips/momentum/jaguar_atx/platform.c
+++ /dev/null
@@ -1,208 +0,0 @@
1#include <linux/delay.h>
2#include <linux/if_ether.h>
3#include <linux/ioport.h>
4#include <linux/mv643xx.h>
5#include <linux/platform_device.h>
6
7#include "jaguar_atx_fpga.h"
8
9#if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE)
10
11static struct resource mv643xx_eth_shared_resources[] = {
12 [0] = {
13 .name = "ethernet shared base",
14 .start = 0xf1000000 + MV643XX_ETH_SHARED_REGS,
15 .end = 0xf1000000 + MV643XX_ETH_SHARED_REGS +
16 MV643XX_ETH_SHARED_REGS_SIZE - 1,
17 .flags = IORESOURCE_MEM,
18 },
19};
20
21static struct platform_device mv643xx_eth_shared_device = {
22 .name = MV643XX_ETH_SHARED_NAME,
23 .id = 0,
24 .num_resources = ARRAY_SIZE(mv643xx_eth_shared_resources),
25 .resource = mv643xx_eth_shared_resources,
26};
27
28#define MV_SRAM_BASE 0xfe000000UL
29#define MV_SRAM_SIZE (256 * 1024)
30
31#define MV_SRAM_RXRING_SIZE (MV_SRAM_SIZE / 4)
32#define MV_SRAM_TXRING_SIZE (MV_SRAM_SIZE / 4)
33
34#define MV_SRAM_BASE_ETH0 MV_SRAM_BASE
35#define MV_SRAM_BASE_ETH1 (MV_SRAM_BASE + (MV_SRAM_SIZE / 2))
36
37#define MV64x60_IRQ_ETH_0 48
38#define MV64x60_IRQ_ETH_1 49
39#define MV64x60_IRQ_ETH_2 50
40
41static struct resource mv64x60_eth0_resources[] = {
42 [0] = {
43 .name = "eth0 irq",
44 .start = MV64x60_IRQ_ETH_0,
45 .end = MV64x60_IRQ_ETH_0,
46 .flags = IORESOURCE_IRQ,
47 },
48};
49
50static struct mv643xx_eth_platform_data eth0_pd = {
51 .port_number = 0,
52
53 .tx_sram_addr = MV_SRAM_BASE_ETH0,
54 .tx_sram_size = MV_SRAM_TXRING_SIZE,
55 .tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
56
57 .rx_sram_addr = MV_SRAM_BASE_ETH0 + MV_SRAM_TXRING_SIZE,
58 .rx_sram_size = MV_SRAM_RXRING_SIZE,
59 .rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
60};
61
62static struct platform_device eth0_device = {
63 .name = MV643XX_ETH_NAME,
64 .id = 0,
65 .num_resources = ARRAY_SIZE(mv64x60_eth0_resources),
66 .resource = mv64x60_eth0_resources,
67 .dev = {
68 .platform_data = &eth0_pd,
69 },
70};
71
72static struct resource mv64x60_eth1_resources[] = {
73 [0] = {
74 .name = "eth1 irq",
75 .start = MV64x60_IRQ_ETH_1,
76 .end = MV64x60_IRQ_ETH_1,
77 .flags = IORESOURCE_IRQ,
78 },
79};
80
81static struct mv643xx_eth_platform_data eth1_pd = {
82 .port_number = 1,
83
84 .tx_sram_addr = MV_SRAM_BASE_ETH1,
85 .tx_sram_size = MV_SRAM_TXRING_SIZE,
86 .tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
87
88 .rx_sram_addr = MV_SRAM_BASE_ETH1 + MV_SRAM_TXRING_SIZE,
89 .rx_sram_size = MV_SRAM_RXRING_SIZE,
90 .rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
91};
92
93static struct platform_device eth1_device = {
94 .name = MV643XX_ETH_NAME,
95 .id = 1,
96 .num_resources = ARRAY_SIZE(mv64x60_eth1_resources),
97 .resource = mv64x60_eth1_resources,
98 .dev = {
99 .platform_data = &eth1_pd,
100 },
101};
102
103static struct resource mv64x60_eth2_resources[] = {
104 [0] = {
105 .name = "eth2 irq",
106 .start = MV64x60_IRQ_ETH_2,
107 .end = MV64x60_IRQ_ETH_2,
108 .flags = IORESOURCE_IRQ,
109 },
110};
111
112static struct mv643xx_eth_platform_data eth2_pd = {
113 .port_number = 2,
114};
115
116static struct platform_device eth2_device = {
117 .name = MV643XX_ETH_NAME,
118 .id = 2,
119 .num_resources = ARRAY_SIZE(mv64x60_eth2_resources),
120 .resource = mv64x60_eth2_resources,
121 .dev = {
122 .platform_data = &eth2_pd,
123 },
124};
125
126static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
127 &mv643xx_eth_shared_device,
128 &eth0_device,
129 &eth1_device,
130 &eth2_device,
131};
132
133static u8 __init exchange_bit(u8 val, u8 cs)
134{
135 /* place the data */
136 JAGUAR_FPGA_WRITE((val << 2) | cs, EEPROM_MODE);
137 udelay(1);
138
139 /* turn the clock on */
140 JAGUAR_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE);
141 udelay(1);
142
143 /* turn the clock off and read-strobe */
144 JAGUAR_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
145
146 /* return the data */
147 return (JAGUAR_FPGA_READ(EEPROM_MODE) >> 3) & 0x1;
148}
149
150static void __init get_mac(char dest[6])
151{
152 u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
153 int i,j;
154
155 for (i = 0; i < 12; i++)
156 exchange_bit(read_opcode[i], 1);
157
158 for (j = 0; j < 6; j++) {
159 dest[j] = 0;
160 for (i = 0; i < 8; i++) {
161 dest[j] <<= 1;
162 dest[j] |= exchange_bit(0, 1);
163 }
164 }
165
166 /* turn off CS */
167 exchange_bit(0,0);
168}
169
170/*
171 * Copy and increment ethernet MAC address by a small value.
172 *
173 * This is useful for systems where the only one MAC address is stored in
174 * non-volatile memory for multiple ports.
175 */
176static inline void eth_mac_add(unsigned char *dst, unsigned char *src,
177 unsigned int add)
178{
179 int i;
180
181 BUG_ON(add >= 256);
182
183 for (i = ETH_ALEN; i >= 0; i--) {
184 dst[i] = src[i] + add;
185 add = dst[i] < src[i]; /* compute carry */
186 }
187
188 WARN_ON(add);
189}
190
191static int __init mv643xx_eth_add_pds(void)
192{
193 unsigned char mac[ETH_ALEN];
194 int ret;
195
196 get_mac(mac);
197 eth_mac_add(eth0_pd.mac_addr, mac, 0);
198 eth_mac_add(eth1_pd.mac_addr, mac, 1);
199 eth_mac_add(eth2_pd.mac_addr, mac, 2);
200 ret = platform_add_devices(mv643xx_eth_pd_devs,
201 ARRAY_SIZE(mv643xx_eth_pd_devs));
202
203 return ret;
204}
205
206device_initcall(mv643xx_eth_add_pds);
207
208#endif /* defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE) */
diff --git a/arch/mips/momentum/jaguar_atx/prom.c b/arch/mips/momentum/jaguar_atx/prom.c
deleted file mode 100644
index 5dd154ee58f6..000000000000
--- a/arch/mips/momentum/jaguar_atx/prom.c
+++ /dev/null
@@ -1,210 +0,0 @@
1/*
2 * Copyright 2002 Momentum Computer Inc.
3 * Author: Matthew Dharm <mdharm@momenco.com>
4 *
5 * Louis Hamilton, Red Hat, Inc.
6 * hamilton@redhat.com [MIPS64 modifications]
7 *
8 * Based on Ocelot Linux port, which is
9 * Copyright 2001 MontaVista Software Inc.
10 * Author: jsun@mvista.com or jsun@junsun.net
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * Added changes for SMP - Manish Lachwani (lachwani@pmc-sierra.com)
18 */
19#include <linux/init.h>
20#include <linux/mm.h>
21#include <linux/sched.h>
22#include <linux/bootmem.h>
23#include <linux/mv643xx.h>
24
25#include <asm/addrspace.h>
26#include <asm/bootinfo.h>
27#include <asm/pmon.h>
28
29#include "jaguar_atx_fpga.h"
30
31extern void ja_setup_console(void);
32
33struct callvectors *debug_vectors;
34
35extern unsigned long cpu_clock;
36
37const char *get_system_type(void)
38{
39 return "Momentum Jaguar-ATX";
40}
41
42#ifdef CONFIG_64BIT
43
44unsigned long signext(unsigned long addr)
45{
46 addr &= 0xffffffff;
47 return (unsigned long)((int)addr);
48}
49
50void *get_arg(unsigned long args, int arc)
51{
52 unsigned long ul;
53 unsigned char *puc, uc;
54
55 args += (arc * 4);
56 ul = (unsigned long)signext(args);
57 puc = (unsigned char *)ul;
58 if (puc == 0)
59 return (void *)0;
60
61#ifdef CONFIG_CPU_LITTLE_ENDIAN
62 uc = *puc++;
63 l = (unsigned long)uc;
64 uc = *puc++;
65 ul |= (((unsigned long)uc) << 8);
66 uc = *puc++;
67 ul |= (((unsigned long)uc) << 16);
68 uc = *puc++;
69 ul |= (((unsigned long)uc) << 24);
70#else
71 uc = *puc++;
72 ul = ((unsigned long)uc) << 24;
73 uc = *puc++;
74 ul |= (((unsigned long)uc) << 16);
75 uc = *puc++;
76 ul |= (((unsigned long)uc) << 8);
77 uc = *puc++;
78 ul |= ((unsigned long)uc);
79#endif
80 ul = signext(ul);
81
82 return (void *)ul;
83}
84
85char *arg64(unsigned long addrin, int arg_index)
86{
87 unsigned long args;
88 char *p;
89
90 args = signext(addrin);
91 p = (char *)get_arg(args, arg_index);
92
93 return p;
94}
95#endif /* CONFIG_64BIT */
96
97/* PMON passes arguments in C main() style */
98void __init prom_init(void)
99{
100 int argc = fw_arg0;
101 char **arg = (char **) fw_arg1;
102 char **env = (char **) fw_arg2;
103 struct callvectors *cv = (struct callvectors *) fw_arg3;
104 int i;
105
106#ifdef CONFIG_SERIAL_8250_CONSOLE
107// ja_setup_console(); /* The very first thing. */
108#endif
109
110#ifdef CONFIG_64BIT
111 char *ptr;
112
113 printk("Mips64 Jaguar-ATX\n");
114 /* save the PROM vectors for debugging use */
115 debug_vectors = (struct callvectors *)signext((unsigned long)cv);
116
117 /* arg[0] is "g", the rest is boot parameters */
118 arcs_cmdline[0] = '\0';
119
120 for (i = 1; i < argc; i++) {
121 ptr = (char *)arg64((unsigned long)arg, i);
122 if ((strlen(arcs_cmdline) + strlen(ptr) + 1) >=
123 sizeof(arcs_cmdline))
124 break;
125 strcat(arcs_cmdline, ptr);
126 strcat(arcs_cmdline, " ");
127 }
128
129 i = 0;
130 while (1) {
131 ptr = (char *)arg64((unsigned long)env, i);
132 if (! ptr)
133 break;
134
135 if (strncmp("gtbase", ptr, strlen("gtbase")) == 0) {
136 marvell_base = simple_strtol(ptr + strlen("gtbase="),
137 NULL, 16);
138
139 if ((marvell_base & 0xffffffff00000000) == 0)
140 marvell_base |= 0xffffffff00000000;
141
142 printk("marvell_base set to 0x%016lx\n", marvell_base);
143 }
144 if (strncmp("cpuclock", ptr, strlen("cpuclock")) == 0) {
145 cpu_clock = simple_strtol(ptr + strlen("cpuclock="),
146 NULL, 10);
147 printk("cpu_clock set to %d\n", cpu_clock);
148 }
149 i++;
150 }
151 printk("arcs_cmdline: %s\n", arcs_cmdline);
152
153#else /* CONFIG_64BIT */
154 /* save the PROM vectors for debugging use */
155 debug_vectors = cv;
156
157 /* arg[0] is "g", the rest is boot parameters */
158 arcs_cmdline[0] = '\0';
159 for (i = 1; i < argc; i++) {
160 if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
161 >= sizeof(arcs_cmdline))
162 break;
163 strcat(arcs_cmdline, arg[i]);
164 strcat(arcs_cmdline, " ");
165 }
166
167 while (*env) {
168 if (strncmp("gtbase", *env, strlen("gtbase")) == 0) {
169 marvell_base = simple_strtol(*env + strlen("gtbase="),
170 NULL, 16);
171 }
172 if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0) {
173 cpu_clock = simple_strtol(*env + strlen("cpuclock="),
174 NULL, 10);
175 }
176 env++;
177 }
178#endif /* CONFIG_64BIT */
179 mips_machgroup = MACH_GROUP_MOMENCO;
180 mips_machtype = MACH_MOMENCO_JAGUAR_ATX;
181}
182
183void __init prom_free_prom_memory(void)
184{
185}
186
187void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
188{
189}
190
191int prom_boot_secondary(int cpu, unsigned long sp, unsigned long gp)
192{
193 /* Clear the semaphore */
194 *(volatile uint32_t *)(0xbb000a68) = 0x80000000;
195
196 return 1;
197}
198
199void prom_init_secondary(void)
200{
201 clear_c0_config(CONF_CM_CMASK);
202 set_c0_config(0x2);
203
204 clear_c0_status(ST0_IM);
205 set_c0_status(0x1ffff);
206}
207
208void prom_smp_finish(void)
209{
210}
diff --git a/arch/mips/momentum/jaguar_atx/reset.c b/arch/mips/momentum/jaguar_atx/reset.c
deleted file mode 100644
index c73b0897dc52..000000000000
--- a/arch/mips/momentum/jaguar_atx/reset.c
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Copyright (C) 1997, 2001 Ralf Baechle
8 * Copyright 2001 MontaVista Software Inc.
9 * Author: jsun@mvista.com or jsun@junsun.net
10 *
11 * Copyright (C) 2002 Momentum Computer Inc.
12 * Author: Matthew Dharm <mdharm@momenco.com>
13 *
14 * Louis Hamilton, Red Hat, Inc.
15 * hamilton@redhat.com [MIPS64 modifications]
16 */
17#include <linux/sched.h>
18#include <linux/mm.h>
19#include <asm/io.h>
20#include <asm/pgtable.h>
21#include <asm/processor.h>
22#include <asm/reboot.h>
23#include <asm/system.h>
24#include <linux/delay.h>
25
26void momenco_jaguar_restart(char *command)
27{
28 /* base address of timekeeper portion of part */
29#ifdef CONFIG_64BIT
30 void *nvram = (void*) 0xfffffffffc807000;
31#else
32 void *nvram = (void*) 0xfc807000;
33#endif
34 /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
35 writeb(0x84, nvram + 0xff7);
36
37 /* wait for the watchdog to go off */
38 mdelay(100+(1000/16));
39
40 /* if the watchdog fails for some reason, let people know */
41 printk(KERN_NOTICE "Watchdog reset failed\n");
42}
43
44void momenco_jaguar_halt(void)
45{
46 printk(KERN_NOTICE "\n** You can safely turn off the power\n");
47 while (1)
48 __asm__(".set\tmips3\n\t"
49 "wait\n\t"
50 ".set\tmips0");
51}
52
53void momenco_jaguar_power_off(void)
54{
55 momenco_jaguar_halt();
56}
diff --git a/arch/mips/momentum/jaguar_atx/setup.c b/arch/mips/momentum/jaguar_atx/setup.c
deleted file mode 100644
index 5a510142b978..000000000000
--- a/arch/mips/momentum/jaguar_atx/setup.c
+++ /dev/null
@@ -1,475 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Momentum Computer Jaguar-ATX board dependent boot routines
4 *
5 * Copyright (C) 1996, 1997, 2001, 04, 06 Ralf Baechle (ralf@linux-mips.org)
6 * Copyright (C) 2000 RidgeRun, Inc.
7 * Copyright (C) 2001 Red Hat, Inc.
8 * Copyright (C) 2002 Momentum Computer
9 *
10 * Author: Matthew Dharm, Momentum Computer
11 * mdharm@momenco.com
12 *
13 * Louis Hamilton, Red Hat, Inc.
14 * hamilton@redhat.com [MIPS64 modifications]
15 *
16 * Author: RidgeRun, Inc.
17 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
18 *
19 * Copyright 2001 MontaVista Software Inc.
20 * Author: jsun@mvista.com or jsun@junsun.net
21 *
22 * This program is free software; you can redistribute it and/or modify it
23 * under the terms of the GNU General Public License as published by the
24 * Free Software Foundation; either version 2 of the License, or (at your
25 * option) any later version.
26 *
27 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
28 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
30 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
31 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
32 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
33 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
34 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
36 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 * You should have received a copy of the GNU General Public License along
39 * with this program; if not, write to the Free Software Foundation, Inc.,
40 * 675 Mass Ave, Cambridge, MA 02139, USA.
41 */
42#include <linux/bcd.h>
43#include <linux/init.h>
44#include <linux/kernel.h>
45#include <linux/types.h>
46#include <linux/mm.h>
47#include <linux/bootmem.h>
48#include <linux/module.h>
49#include <linux/pci.h>
50#include <linux/swap.h>
51#include <linux/ioport.h>
52#include <linux/pm.h>
53#include <linux/sched.h>
54#include <linux/interrupt.h>
55#include <linux/timex.h>
56#include <linux/vmalloc.h>
57#include <linux/mv643xx.h>
58
59#include <asm/time.h>
60#include <asm/bootinfo.h>
61#include <asm/page.h>
62#include <asm/io.h>
63#include <asm/irq.h>
64#include <asm/processor.h>
65#include <asm/reboot.h>
66#include <asm/tlbflush.h>
67
68#include "jaguar_atx_fpga.h"
69
70extern unsigned long mv64340_sram_base;
71unsigned long cpu_clock;
72
73/* These functions are used for rebooting or halting the machine*/
74extern void momenco_jaguar_restart(char *command);
75extern void momenco_jaguar_halt(void);
76extern void momenco_jaguar_power_off(void);
77
78void momenco_time_init(void);
79
80static char reset_reason;
81
82static inline unsigned long ENTRYLO(unsigned long paddr)
83{
84 return ((paddr & PAGE_MASK) |
85 (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
86 _CACHE_UNCACHED)) >> 6;
87}
88
89void __init bus_error_init(void) { /* nothing */ }
90
91/*
92 * Load a few TLB entries for the MV64340 and perhiperals. The MV64340 is going
93 * to be hit on every IRQ anyway - there's absolutely no point in letting it be
94 * a random TLB entry, as it'll just cause needless churning of the TLB. And we
95 * use the other half for the serial port, which is just a PITA otherwise :)
96 *
97 * Device Physical Virtual
98 * MV64340 Internal Regs 0xf4000000 0xf4000000
99 * Ocelot-C[S] PLD (CS0) 0xfc000000 0xfc000000
100 * NVRAM (CS1) 0xfc800000 0xfc800000
101 * UARTs (CS2) 0xfd000000 0xfd000000
102 * Internal SRAM 0xfe000000 0xfe000000
103 * M-Systems DOC (CS3) 0xff000000 0xff000000
104 */
105
106static __init void wire_stupidity_into_tlb(void)
107{
108#ifdef CONFIG_32BIT
109 write_c0_wired(0);
110 local_flush_tlb_all();
111
112 /* marvell and extra space */
113 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000),
114 0xf4000000UL, PM_64K);
115 /* fpga, rtc, and uart */
116 add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000),
117 0xfc000000UL, PM_16M);
118// /* m-sys and internal SRAM */
119// add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000),
120// 0xfe000000UL, PM_16M);
121
122 marvell_base = 0xf4000000;
123 //mv64340_sram_base = 0xfe000000; /* Currently unused */
124#endif
125}
126
127unsigned long marvell_base = 0xf4000000L;
128unsigned long ja_fpga_base = JAGUAR_ATX_CS0_ADDR;
129unsigned long uart_base = 0xfd000000L;
130static unsigned char *rtc_base = (unsigned char*) 0xfc800000L;
131
132EXPORT_SYMBOL(marvell_base);
133
134static __init int per_cpu_mappings(void)
135{
136 marvell_base = (unsigned long) ioremap(0xf4000000, 0x10000);
137 ja_fpga_base = (unsigned long) ioremap(JAGUAR_ATX_CS0_ADDR, 0x1000);
138 uart_base = (unsigned long) ioremap(0xfd000000UL, 0x1000);
139 rtc_base = ioremap(0xfc000000UL, 0x8000);
140 // ioremap(0xfe000000, 32 << 20);
141 write_c0_wired(0);
142 local_flush_tlb_all();
143 ja_setup_console();
144
145 return 0;
146}
147arch_initcall(per_cpu_mappings);
148
149unsigned long m48t37y_get_time(void)
150{
151 unsigned int year, month, day, hour, min, sec;
152 unsigned long flags;
153
154 spin_lock_irqsave(&rtc_lock, flags);
155 /* stop the update */
156 rtc_base[0x7ff8] = 0x40;
157
158 year = BCD2BIN(rtc_base[0x7fff]);
159 year += BCD2BIN(rtc_base[0x7ff1]) * 100;
160
161 month = BCD2BIN(rtc_base[0x7ffe]);
162
163 day = BCD2BIN(rtc_base[0x7ffd]);
164
165 hour = BCD2BIN(rtc_base[0x7ffb]);
166 min = BCD2BIN(rtc_base[0x7ffa]);
167 sec = BCD2BIN(rtc_base[0x7ff9]);
168
169 /* start the update */
170 rtc_base[0x7ff8] = 0x00;
171 spin_unlock_irqrestore(&rtc_lock, flags);
172
173 return mktime(year, month, day, hour, min, sec);
174}
175
176int m48t37y_set_time(unsigned long sec)
177{
178 struct rtc_time tm;
179 unsigned long flags;
180
181 /* convert to a more useful format -- note months count from 0 */
182 to_tm(sec, &tm);
183 tm.tm_mon += 1;
184
185 spin_lock_irqsave(&rtc_lock, flags);
186 /* enable writing */
187 rtc_base[0x7ff8] = 0x80;
188
189 /* year */
190 rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100);
191 rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100);
192
193 /* month */
194 rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon);
195
196 /* day */
197 rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday);
198
199 /* hour/min/sec */
200 rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour);
201 rtc_base[0x7ffa] = BIN2BCD(tm.tm_min);
202 rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec);
203
204 /* day of week -- not really used, but let's keep it up-to-date */
205 rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1);
206
207 /* disable writing */
208 rtc_base[0x7ff8] = 0x00;
209 spin_unlock_irqrestore(&rtc_lock, flags);
210
211 return 0;
212}
213
214void __init plat_timer_setup(struct irqaction *irq)
215{
216 setup_irq(8, irq);
217}
218
219/*
220 * Ugly but the least of all evils. TLB initialization did flush the TLB so
221 * We need to setup mappings again before we can touch the RTC.
222 */
223void momenco_time_init(void)
224{
225 wire_stupidity_into_tlb();
226
227 mips_hpt_frequency = cpu_clock / 2;
228
229 rtc_mips_get_time = m48t37y_get_time;
230 rtc_mips_set_time = m48t37y_set_time;
231}
232
233static struct resource mv_pci_io_mem0_resource = {
234 .name = "MV64340 PCI0 IO MEM",
235 .flags = IORESOURCE_IO
236};
237
238static struct resource mv_pci_mem0_resource = {
239 .name = "MV64340 PCI0 MEM",
240 .flags = IORESOURCE_MEM
241};
242
243static struct mv_pci_controller mv_bus0_controller = {
244 .pcic = {
245 .pci_ops = &mv_pci_ops,
246 .mem_resource = &mv_pci_mem0_resource,
247 .io_resource = &mv_pci_io_mem0_resource,
248 },
249 .config_addr = MV64340_PCI_0_CONFIG_ADDR,
250 .config_vreg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG,
251};
252
253static uint32_t mv_io_base, mv_io_size;
254
255static void ja_pci0_init(void)
256{
257 uint32_t mem0_base, mem0_size;
258 uint32_t io_base, io_size;
259
260 io_base = MV_READ(MV64340_PCI_0_IO_BASE_ADDR) << 16;
261 io_size = (MV_READ(MV64340_PCI_0_IO_SIZE) + 1) << 16;
262 mem0_base = MV_READ(MV64340_PCI_0_MEMORY0_BASE_ADDR) << 16;
263 mem0_size = (MV_READ(MV64340_PCI_0_MEMORY0_SIZE) + 1) << 16;
264
265 mv_pci_io_mem0_resource.start = 0;
266 mv_pci_io_mem0_resource.end = io_size - 1;
267 mv_pci_mem0_resource.start = mem0_base;
268 mv_pci_mem0_resource.end = mem0_base + mem0_size - 1;
269 mv_bus0_controller.pcic.mem_offset = mem0_base;
270 mv_bus0_controller.pcic.io_offset = 0;
271
272 ioport_resource.end = io_size - 1;
273
274 register_pci_controller(&mv_bus0_controller.pcic);
275
276 mv_io_base = io_base;
277 mv_io_size = io_size;
278}
279
280static struct resource mv_pci_io_mem1_resource = {
281 .name = "MV64340 PCI1 IO MEM",
282 .flags = IORESOURCE_IO
283};
284
285static struct resource mv_pci_mem1_resource = {
286 .name = "MV64340 PCI1 MEM",
287 .flags = IORESOURCE_MEM
288};
289
290static struct mv_pci_controller mv_bus1_controller = {
291 .pcic = {
292 .pci_ops = &mv_pci_ops,
293 .mem_resource = &mv_pci_mem1_resource,
294 .io_resource = &mv_pci_io_mem1_resource,
295 },
296 .config_addr = MV64340_PCI_1_CONFIG_ADDR,
297 .config_vreg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG,
298};
299
300static __init void ja_pci1_init(void)
301{
302 uint32_t mem0_base, mem0_size;
303 uint32_t io_base, io_size;
304
305 io_base = MV_READ(MV64340_PCI_1_IO_BASE_ADDR) << 16;
306 io_size = (MV_READ(MV64340_PCI_1_IO_SIZE) + 1) << 16;
307 mem0_base = MV_READ(MV64340_PCI_1_MEMORY0_BASE_ADDR) << 16;
308 mem0_size = (MV_READ(MV64340_PCI_1_MEMORY0_SIZE) + 1) << 16;
309
310 /*
311 * Here we assume the I/O window of second bus to be contiguous with
312 * the first. A gap is no problem but would waste address space for
313 * remapping the port space.
314 */
315 mv_pci_io_mem1_resource.start = mv_io_size;
316 mv_pci_io_mem1_resource.end = mv_io_size + io_size - 1;
317 mv_pci_mem1_resource.start = mem0_base;
318 mv_pci_mem1_resource.end = mem0_base + mem0_size - 1;
319 mv_bus1_controller.pcic.mem_offset = mem0_base;
320 mv_bus1_controller.pcic.io_offset = 0;
321
322 ioport_resource.end = io_base + io_size -mv_io_base - 1;
323
324 register_pci_controller(&mv_bus1_controller.pcic);
325
326 mv_io_size = io_base + io_size - mv_io_base;
327}
328
329static __init int __init ja_pci_init(void)
330{
331 unsigned long io_v_base;
332 uint32_t enable;
333
334 enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE);
335
336 /*
337 * We require at least one enabled I/O or PCI memory window or we
338 * will ignore this PCI bus. We ignore PCI windows 1, 2 and 3.
339 */
340 if (enable & (0x01 << 9) || enable & (0x01 << 10))
341 ja_pci0_init();
342
343 if (enable & (0x01 << 14) || enable & (0x01 << 15))
344 ja_pci1_init();
345
346 if (mv_io_size) {
347 io_v_base = (unsigned long) ioremap(mv_io_base, mv_io_size);
348 if (!io_v_base)
349 panic("Could not ioremap I/O port range");
350
351 set_io_port_base(io_v_base);
352 }
353
354 return 0;
355}
356
357arch_initcall(ja_pci_init);
358
359void __init plat_mem_setup(void)
360{
361 unsigned int tmpword;
362
363 board_time_init = momenco_time_init;
364
365 _machine_restart = momenco_jaguar_restart;
366 _machine_halt = momenco_jaguar_halt;
367 pm_power_off = momenco_jaguar_power_off;
368
369 /*
370 * initrd_start = (unsigned long)jaguar_initrd_start;
371 * initrd_end = (unsigned long)jaguar_initrd_start + (ulong)jaguar_initrd_size;
372 * initrd_below_start_ok = 1;
373 */
374
375 wire_stupidity_into_tlb();
376
377 /*
378 * shut down ethernet ports, just to be sure our memory doesn't get
379 * corrupted by random ethernet traffic.
380 */
381 MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
382 MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
383 MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(2), 0xff << 8);
384 MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
385 MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
386 MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0xff << 8);
387 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
388 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
389 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(2)) & 0xff);
390 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
391 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
392 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(2)) & 0xff);
393 MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0),
394 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
395 MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1),
396 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
397 MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(2),
398 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(2)) & ~1);
399
400 /* Turn off the Bit-Error LED */
401 JAGUAR_FPGA_WRITE(0x80, CLR);
402
403 tmpword = JAGUAR_FPGA_READ(BOARDREV);
404 if (tmpword < 26)
405 printk("Momentum Jaguar-ATX: Board Assembly Rev. %c\n",
406 'A'+tmpword);
407 else
408 printk("Momentum Jaguar-ATX: Board Assembly Revision #0x%x\n",
409 tmpword);
410
411 tmpword = JAGUAR_FPGA_READ(FPGA_REV);
412 printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
413 tmpword = JAGUAR_FPGA_READ(RESET_STATUS);
414 printk("Reset reason: 0x%x\n", tmpword);
415 switch (tmpword) {
416 case 0x1:
417 printk(" - Power-up reset\n");
418 break;
419 case 0x2:
420 printk(" - Push-button reset\n");
421 break;
422 case 0x8:
423 printk(" - Watchdog reset\n");
424 break;
425 case 0x10:
426 printk(" - JTAG reset\n");
427 break;
428 default:
429 printk(" - Unknown reset cause\n");
430 }
431 reset_reason = tmpword;
432 JAGUAR_FPGA_WRITE(0xff, RESET_STATUS);
433
434 tmpword = JAGUAR_FPGA_READ(BOARD_STATUS);
435 printk("Board Status register: 0x%02x\n", tmpword);
436 printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
437 printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
438
439 /* 256MiB of RM9000x2 DDR */
440// add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM);
441
442 /* 128MiB of MV-64340 DDR */
443// add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM);
444
445 /* XXX Memory configuration should be picked up from PMON2k */
446#ifdef CONFIG_JAGUAR_DMALOW
447 printk("Jaguar ATX DMA-low mode set\n");
448 add_memory_region(0x00000000, 0x08000000, BOOT_MEM_RAM);
449 add_memory_region(0x08000000, 0x10000000, BOOT_MEM_RAM);
450#else
451 /* 128MiB of MV-64340 DDR RAM */
452 printk("Jaguar ATX DMA-low mode is not set\n");
453 add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM);
454#endif
455
456#ifdef GEMDEBUG_TRACEBUFFER
457 {
458 unsigned int tbControl;
459 tbControl =
460 0 << 26 | /* post trigger delay 0 */
461 0x2 << 16 | /* sequential trace mode */
462 // 0x0 << 16 | /* non-sequential trace mode */
463 // 0xf << 4 | /* watchpoints disabled */
464 2 << 2 | /* armed */
465 2 ; /* interrupt disabled */
466 printk ("setting tbControl = %08lx\n", tbControl);
467 write_32bit_cp0_set1_register($22, tbControl);
468 __asm__ __volatile__(".set noreorder\n\t" \
469 "nop; nop; nop; nop; nop; nop;\n\t" \
470 "nop; nop; nop; nop; nop; nop;\n\t" \
471 ".set reorder\n\t");
472
473 }
474#endif
475}
diff --git a/arch/mips/momentum/ocelot_g/Makefile b/arch/mips/momentum/ocelot_g/Makefile
deleted file mode 100644
index c0a0030d949d..000000000000
--- a/arch/mips/momentum/ocelot_g/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
1#
2# Makefile for Momentum Computer's Ocelot-G board.
3#
4
5obj-y += irq.o gt-irq.o prom.o reset.o setup.o
6obj-$(CONFIG_KGDB) += dbg_io.o
diff --git a/arch/mips/momentum/ocelot_g/dbg_io.c b/arch/mips/momentum/ocelot_g/dbg_io.c
deleted file mode 100644
index 32d6fb4ee679..000000000000
--- a/arch/mips/momentum/ocelot_g/dbg_io.c
+++ /dev/null
@@ -1,121 +0,0 @@
1
2#include <asm/serial.h> /* For the serial port location and base baud */
3
4/* --- CONFIG --- */
5
6typedef unsigned char uint8;
7typedef unsigned int uint32;
8
9/* --- END OF CONFIG --- */
10
11#define UART16550_BAUD_2400 2400
12#define UART16550_BAUD_4800 4800
13#define UART16550_BAUD_9600 9600
14#define UART16550_BAUD_19200 19200
15#define UART16550_BAUD_38400 38400
16#define UART16550_BAUD_57600 57600
17#define UART16550_BAUD_115200 115200
18
19#define UART16550_PARITY_NONE 0
20#define UART16550_PARITY_ODD 0x08
21#define UART16550_PARITY_EVEN 0x18
22#define UART16550_PARITY_MARK 0x28
23#define UART16550_PARITY_SPACE 0x38
24
25#define UART16550_DATA_5BIT 0x0
26#define UART16550_DATA_6BIT 0x1
27#define UART16550_DATA_7BIT 0x2
28#define UART16550_DATA_8BIT 0x3
29
30#define UART16550_STOP_1BIT 0x0
31#define UART16550_STOP_2BIT 0x4
32
33/* ----------------------------------------------------- */
34
35/* === CONFIG === */
36
37/* [jsun] we use the second serial port for kdb */
38#define BASE OCELOT_SERIAL1_BASE
39#define MAX_BAUD OCELOT_BASE_BAUD
40
41/* === END OF CONFIG === */
42
43#define REG_OFFSET 4
44
45/* register offset */
46#define OFS_RCV_BUFFER 0
47#define OFS_TRANS_HOLD 0
48#define OFS_SEND_BUFFER 0
49#define OFS_INTR_ENABLE (1*REG_OFFSET)
50#define OFS_INTR_ID (2*REG_OFFSET)
51#define OFS_DATA_FORMAT (3*REG_OFFSET)
52#define OFS_LINE_CONTROL (3*REG_OFFSET)
53#define OFS_MODEM_CONTROL (4*REG_OFFSET)
54#define OFS_RS232_OUTPUT (4*REG_OFFSET)
55#define OFS_LINE_STATUS (5*REG_OFFSET)
56#define OFS_MODEM_STATUS (6*REG_OFFSET)
57#define OFS_RS232_INPUT (6*REG_OFFSET)
58#define OFS_SCRATCH_PAD (7*REG_OFFSET)
59
60#define OFS_DIVISOR_LSB (0*REG_OFFSET)
61#define OFS_DIVISOR_MSB (1*REG_OFFSET)
62
63
64/* memory-mapped read/write of the port */
65#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
66#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
67
68void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
69{
70 /* disable interrupts */
71 UART16550_WRITE(OFS_INTR_ENABLE, 0);
72
73 /* set up baud rate */
74 {
75 uint32 divisor;
76
77 /* set DIAB bit */
78 UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
79
80 /* set divisor */
81 divisor = MAX_BAUD / baud;
82 UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
83 UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
84
85 /* clear DIAB bit */
86 UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
87 }
88
89 /* set data format */
90 UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
91}
92
93static int remoteDebugInitialized = 0;
94
95uint8 getDebugChar(void)
96{
97 if (!remoteDebugInitialized) {
98 remoteDebugInitialized = 1;
99 debugInit(UART16550_BAUD_38400,
100 UART16550_DATA_8BIT,
101 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
102 }
103
104 while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
105 return UART16550_READ(OFS_RCV_BUFFER);
106}
107
108
109int putDebugChar(uint8 byte)
110{
111 if (!remoteDebugInitialized) {
112 remoteDebugInitialized = 1;
113 debugInit(UART16550_BAUD_38400,
114 UART16550_DATA_8BIT,
115 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
116 }
117
118 while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
119 UART16550_WRITE(OFS_SEND_BUFFER, byte);
120 return 1;
121}
diff --git a/arch/mips/momentum/ocelot_g/gt-irq.c b/arch/mips/momentum/ocelot_g/gt-irq.c
deleted file mode 100644
index e5576bd50fa9..000000000000
--- a/arch/mips/momentum/ocelot_g/gt-irq.c
+++ /dev/null
@@ -1,212 +0,0 @@
1/*
2 *
3 * Copyright 2002 Momentum Computer
4 * Author: mdharm@momenco.com
5 *
6 * arch/mips/momentum/ocelot_g/gt_irq.c
7 * Interrupt routines for gt64240. Currently it only handles timer irq.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14#include <linux/module.h>
15#include <linux/interrupt.h>
16#include <linux/kernel.h>
17#include <linux/sched.h>
18#include <linux/kernel_stat.h>
19#include <asm/gt64240.h>
20#include <asm/io.h>
21
22unsigned long bus_clock;
23
24/*
25 * These are interrupt handlers for the GT on-chip interrupts. They
26 * all come in to the MIPS on a single interrupt line, and have to
27 * be handled and ack'ed differently than other MIPS interrupts.
28 */
29
30#if 0
31
32struct tq_struct irq_handlers[MAX_CAUSE_REGS][MAX_CAUSE_REG_WIDTH];
33void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr);
34
35/*
36 * Hooks IRQ handler to the system. When the system is interrupted
37 * the interrupt service routine is called.
38 *
39 * Inputs :
40 * int_cause - The interrupt cause number. In EVB64120 two parameters
41 * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
42 * bit_num - Indicates which bit number in the cause register
43 * isr_ptr - Pointer to the interrupt service routine
44 */
45void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr)
46{
47 irq_handlers[int_cause][bit_num].routine = isr_ptr;
48}
49
50
51/*
52 * Enables the IRQ on Galileo Chip
53 *
54 * Inputs :
55 * int_cause - The interrupt cause number. In EVB64120 two parameters
56 * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
57 * bit_num - Indicates which bit number in the cause register
58 *
59 * Outputs :
60 * 1 if successful, 0 if failure
61 */
62int enable_galileo_irq(int int_cause, int bit_num)
63{
64 if (int_cause == INT_CAUSE_MAIN)
65 SET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER, (1 << bit_num));
66 else if (int_cause == INT_CAUSE_HIGH)
67 SET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER,
68 (1 << bit_num));
69 else
70 return 0;
71
72 return 1;
73}
74
75/*
76 * Disables the IRQ on Galileo Chip
77 *
78 * Inputs :
79 * int_cause - The interrupt cause number. In EVB64120 two parameters
80 * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
81 * bit_num - Indicates which bit number in the cause register
82 *
83 * Outputs :
84 * 1 if successful, 0 if failure
85 */
86int disable_galileo_irq(int int_cause, int bit_num)
87{
88 if (int_cause == INT_CAUSE_MAIN)
89 RESET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER,
90 (1 << bit_num));
91 else if (int_cause == INT_CAUSE_HIGH)
92 RESET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER,
93 (1 << bit_num));
94 else
95 return 0;
96 return 1;
97}
98#endif /* 0 */
99
100/*
101 * Interrupt handler for interrupts coming from the Galileo chip via P0_INT#.
102 *
103 * We route the timer interrupt to P0_INT# (IRQ 6), and that's all this
104 * routine can handle, for now.
105 *
106 * In the future, we'll route more interrupts to this pin, and that's why
107 * we keep this particular structure in the function.
108 */
109
110static irqreturn_t gt64240_p0int_irq(int irq, void *dev)
111{
112 uint32_t irq_src, irq_src_mask;
113 int handled;
114
115 /* get the low interrupt cause register */
116 irq_src = MV_READ(LOW_INTERRUPT_CAUSE_REGISTER);
117
118 /* get the mask register for this pin */
119 irq_src_mask = MV_READ(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW);
120
121 /* mask off only the interrupts we're interested in */
122 irq_src = irq_src & irq_src_mask;
123
124 handled = IRQ_NONE;
125
126 /* Check for timer interrupt */
127 if (irq_src & 0x00000100) {
128 handled = IRQ_HANDLED;
129 irq_src &= ~0x00000100;
130
131 /* Clear any pending cause bits */
132 MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0);
133
134 /* handle the timer call */
135 do_timer(1);
136#ifndef CONFIG_SMP
137 update_process_times(user_mode(get_irq_regs()));
138#endif
139 }
140
141 if (irq_src) {
142 printk(KERN_INFO
143 "UNKNOWN P0_INT# interrupt received, irq_src=0x%x\n",
144 irq_src);
145 }
146
147 return handled;
148}
149
150/*
151 * Initializes timer using galileo's built in timer.
152 */
153
154/*
155 * This will ignore the standard MIPS timer interrupt handler
156 * that is passed in as *irq (=irq0 in ../kernel/time.c).
157 * We will do our own timer interrupt handling.
158 */
159void gt64240_time_init(void)
160{
161 static struct irqaction timer;
162
163 /* Stop the timer -- we'll use timer #0 */
164 MV_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x0);
165
166 /* Load timer value for 100 Hz */
167 MV_WRITE(TIMER_COUNTER0, bus_clock / 100);
168
169 /*
170 * Create the IRQ structure entry for the timer. Since we're too early
171 * in the boot process to use the "request_irq()" call, we'll hard-code
172 * the values to the correct interrupt line.
173 */
174 timer.handler = &gt64240_p0int_irq;
175 timer.flags = IRQF_SHARED | IRQF_DISABLED;
176 timer.name = "timer";
177 timer.dev_id = NULL;
178 timer.next = NULL;
179 timer.mask = CPU_MASK_NONE;
180 irq_desc[6].action = &timer;
181
182 enable_irq(6);
183
184 /* Clear any pending cause bits */
185 MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0);
186
187 /* Enable the interrupt for timer 0 */
188 MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_MASK, 0x1);
189
190 /* Enable the timer interrupt for GT-64240 pin P0_INT# */
191 MV_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0x100);
192
193 /* Configure and start the timer */
194 MV_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x3);
195}
196
197void gt64240_irq_init(void)
198{
199#if 0
200 int i, j;
201
202 /* Reset irq handlers pointers to NULL */
203 for (i = 0; i < MAX_CAUSE_REGS; i++) {
204 for (j = 0; j < MAX_CAUSE_REG_WIDTH; j++) {
205 irq_handlers[i][j].next = NULL;
206 irq_handlers[i][j].sync = 0;
207 irq_handlers[i][j].routine = NULL;
208 irq_handlers[i][j].data = NULL;
209 }
210 }
211#endif /* 0 */
212}
diff --git a/arch/mips/momentum/ocelot_g/irq.c b/arch/mips/momentum/ocelot_g/irq.c
deleted file mode 100644
index 273541fe7087..000000000000
--- a/arch/mips/momentum/ocelot_g/irq.c
+++ /dev/null
@@ -1,101 +0,0 @@
1/*
2 * Copyright (C) 2000 RidgeRun, Inc.
3 * Author: RidgeRun, Inc.
4 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
8 * Copyright (C) 2000, 01, 05 Ralf Baechle (ralf@linux-mips.org)
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 *
30 */
31#include <linux/errno.h>
32#include <linux/init.h>
33#include <linux/kernel_stat.h>
34#include <linux/module.h>
35#include <linux/signal.h>
36#include <linux/sched.h>
37#include <linux/types.h>
38#include <linux/interrupt.h>
39#include <linux/ioport.h>
40#include <linux/timex.h>
41#include <linux/slab.h>
42#include <linux/random.h>
43#include <linux/bitops.h>
44#include <asm/bootinfo.h>
45#include <asm/io.h>
46#include <asm/irq.h>
47#include <asm/irq_cpu.h>
48#include <asm/mipsregs.h>
49#include <asm/system.h>
50
51asmlinkage void plat_irq_dispatch(void)
52{
53 unsigned int pending = read_c0_cause() & read_c0_status();
54
55 if (pending & STATUSF_IP2)
56 do_IRQ(2);
57 else if (pending & STATUSF_IP3)
58 do_IRQ(3);
59 else if (pending & STATUSF_IP4)
60 do_IRQ(4);
61 else if (pending & STATUSF_IP5)
62 do_IRQ(5);
63 else if (pending & STATUSF_IP6)
64 do_IRQ(6);
65 else if (pending & STATUSF_IP7)
66 do_IRQ(7);
67 else {
68 /*
69 * Now look at the extended interrupts
70 */
71 pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16;
72
73 if (pending & STATUSF_IP8)
74 do_IRQ(8);
75 else if (pending & STATUSF_IP9)
76 do_IRQ(9);
77 else if (pending & STATUSF_IP10)
78 do_IRQ(10);
79 else if (pending & STATUSF_IP11)
80 do_IRQ(11);
81 else
82 spurious_interrupt();
83 }
84}
85
86extern void gt64240_irq_init(void);
87
88void __init arch_init_irq(void)
89{
90 /*
91 * Clear all of the interrupts while we change the able around a bit.
92 * int-handler is not on bootstrap
93 */
94 clear_c0_status(ST0_IM);
95 local_irq_disable();
96
97 mips_cpu_irq_init();
98 rm7k_cpu_irq_init();
99
100 gt64240_irq_init();
101}
diff --git a/arch/mips/momentum/ocelot_g/ocelot_pld.h b/arch/mips/momentum/ocelot_g/ocelot_pld.h
deleted file mode 100644
index 95e0534026d0..000000000000
--- a/arch/mips/momentum/ocelot_g/ocelot_pld.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Ocelot Board Register Definitions
3 *
4 * (C) 2001 Red Hat, Inc.
5 *
6 * GPL'd
7 */
8#ifndef __MOMENCO_OCELOT_PLD_H__
9#define __MOMENCO_OCELOT_PLD_H__
10
11#define OCELOT_CS0_ADDR (0xfc000000)
12
13#define OCELOT_REG_BOARDREV (0)
14#define OCELOT_REG_PLD1_ID (1)
15#define OCELOT_REG_PLD2_ID (2)
16#define OCELOT_REG_RESET_STATUS (3)
17#define OCELOT_REG_BOARD_STATUS (4)
18#define OCELOT_REG_CPCI_ID (5)
19#define OCELOT_REG_I2C_CTRL (8)
20#define OCELOT_REG_EEPROM_MODE (9)
21#define OCELOT_REG_INTMASK (10)
22#define OCELOT_REG_INTSTATUS (11)
23#define OCELOT_REG_INTSET (12)
24#define OCELOT_REG_INTCLR (13)
25
26#define __PLD_REG_TO_ADDR(reg) ((void *) OCELOT_CS0_ADDR + OCELOT_REG_##reg)
27#define OCELOT_PLD_WRITE(x, reg) writeb(x, __PLD_REG_TO_ADDR(reg))
28#define OCELOT_PLD_READ(reg) readb(__PLD_REG_TO_ADDR(reg))
29
30#endif /* __MOMENCO_OCELOT_PLD_H__ */
diff --git a/arch/mips/momentum/ocelot_g/prom.c b/arch/mips/momentum/ocelot_g/prom.c
deleted file mode 100644
index 836d0830720d..000000000000
--- a/arch/mips/momentum/ocelot_g/prom.c
+++ /dev/null
@@ -1,84 +0,0 @@
1/*
2 * Copyright 2002 Momentum Computer Inc.
3 * Author: Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on Ocelot Linux port, which is
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: jsun@mvista.com or jsun@junsun.net
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14#include <linux/init.h>
15#include <linux/mm.h>
16#include <linux/sched.h>
17#include <linux/bootmem.h>
18
19#include <asm/addrspace.h>
20#include <asm/bootinfo.h>
21#include <asm/pmon.h>
22#include <asm/gt64240.h>
23
24#include "ocelot_pld.h"
25
26struct callvectors* debug_vectors;
27
28extern unsigned long marvell_base;
29extern unsigned long bus_clock;
30
31#ifdef CONFIG_GALILEO_GT64240_ETH
32extern unsigned char prom_mac_addr_base[6];
33#endif
34
35const char *get_system_type(void)
36{
37 return "Momentum Ocelot";
38}
39
40void __init prom_init(void)
41{
42 int argc = fw_arg0;
43 char **arg = (char **) fw_arg1;
44 char **env = (char **) fw_arg2;
45 struct callvectors *cv = (struct callvectors *) fw_arg3;
46 int i;
47
48 /* save the PROM vectors for debugging use */
49 debug_vectors = cv;
50
51 /* arg[0] is "g", the rest is boot parameters */
52 arcs_cmdline[0] = '\0';
53 for (i = 1; i < argc; i++) {
54 if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
55 >= sizeof(arcs_cmdline))
56 break;
57 strcat(arcs_cmdline, arg[i]);
58 strcat(arcs_cmdline, " ");
59 }
60
61 mips_machgroup = MACH_GROUP_MOMENCO;
62 mips_machtype = MACH_MOMENCO_OCELOT_G;
63
64#ifdef CONFIG_GALILEO_GT64240_ETH
65 /* get the base MAC address for on-board ethernet ports */
66 memcpy(prom_mac_addr_base, (void*)0xfc807cf2, 6);
67#endif
68
69 while (*env) {
70 if (strncmp("gtbase", *env, strlen("gtbase")) == 0) {
71 marvell_base = simple_strtol(*env + strlen("gtbase="),
72 NULL, 16);
73 }
74 if (strncmp("busclock", *env, strlen("busclock")) == 0) {
75 bus_clock = simple_strtol(*env + strlen("busclock="),
76 NULL, 10);
77 }
78 env++;
79 }
80}
81
82void __init prom_free_prom_memory(void)
83{
84}
diff --git a/arch/mips/momentum/ocelot_g/reset.c b/arch/mips/momentum/ocelot_g/reset.c
deleted file mode 100644
index 3fd499adf4cf..000000000000
--- a/arch/mips/momentum/ocelot_g/reset.c
+++ /dev/null
@@ -1,47 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Copyright (C) 1997, 2001 Ralf Baechle
8 * Copyright 2001 MontaVista Software Inc.
9 * Author: jsun@mvista.com or jsun@junsun.net
10 */
11#include <linux/sched.h>
12#include <linux/mm.h>
13#include <asm/io.h>
14#include <asm/pgtable.h>
15#include <asm/processor.h>
16#include <asm/reboot.h>
17#include <asm/system.h>
18#include <linux/delay.h>
19
20void momenco_ocelot_restart(char *command)
21{
22 void *nvram = ioremap_nocache(0x2c807000, 0x1000);
23
24 if (!nvram) {
25 printk(KERN_NOTICE "ioremap of reset register failed\n");
26 return;
27 }
28 writeb(0x84, nvram + 0xff7); /* Ask the NVRAM/RTC/watchdog chip to
29 assert reset in 1/16 second */
30 mdelay(10+(1000/16));
31 iounmap(nvram);
32 printk(KERN_NOTICE "Watchdog reset failed\n");
33}
34
35void momenco_ocelot_halt(void)
36{
37 printk(KERN_NOTICE "\n** You can safely turn off the power\n");
38 while (1)
39 __asm__(".set\tmips3\n\t"
40 "wait\n\t"
41 ".set\tmips0");
42}
43
44void momenco_ocelot_power_off(void)
45{
46 momenco_ocelot_halt();
47}
diff --git a/arch/mips/momentum/ocelot_g/setup.c b/arch/mips/momentum/ocelot_g/setup.c
deleted file mode 100644
index 9db638a7982c..000000000000
--- a/arch/mips/momentum/ocelot_g/setup.c
+++ /dev/null
@@ -1,267 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Momentum Computer Ocelot-G (CP7000G) - board dependent boot routines
4 *
5 * Copyright (C) 1996, 1997, 2001 Ralf Baechle
6 * Copyright (C) 2000 RidgeRun, Inc.
7 * Copyright (C) 2001 Red Hat, Inc.
8 * Copyright (C) 2002 Momentum Computer
9 *
10 * Author: Matthew Dharm, Momentum Computer
11 * mdharm@momenco.com
12 *
13 * Author: RidgeRun, Inc.
14 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
15 *
16 * Copyright 2001 MontaVista Software Inc.
17 * Author: jsun@mvista.com or jsun@junsun.net
18 *
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2 of the License, or (at your
22 * option) any later version.
23 *
24 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
27 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
30 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
31 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * You should have received a copy of the GNU General Public License along
36 * with this program; if not, write to the Free Software Foundation, Inc.,
37 * 675 Mass Ave, Cambridge, MA 02139, USA.
38 *
39 */
40#include <linux/init.h>
41#include <linux/kernel.h>
42#include <linux/types.h>
43#include <linux/mm.h>
44#include <linux/swap.h>
45#include <linux/ioport.h>
46#include <linux/sched.h>
47#include <linux/interrupt.h>
48#include <linux/pci.h>
49#include <linux/pm.h>
50#include <linux/timex.h>
51#include <linux/vmalloc.h>
52
53#include <asm/time.h>
54#include <asm/bootinfo.h>
55#include <asm/page.h>
56#include <asm/io.h>
57#include <asm/gt64240.h>
58#include <asm/irq.h>
59#include <asm/pci.h>
60#include <asm/pgtable.h>
61#include <asm/processor.h>
62#include <asm/reboot.h>
63#include <linux/bootmem.h>
64
65#include "ocelot_pld.h"
66
67#ifdef CONFIG_GALILEO_GT64240_ETH
68extern unsigned char prom_mac_addr_base[6];
69#endif
70
71unsigned long marvell_base;
72
73/* These functions are used for rebooting or halting the machine*/
74extern void momenco_ocelot_restart(char *command);
75extern void momenco_ocelot_halt(void);
76extern void momenco_ocelot_power_off(void);
77
78extern void gt64240_time_init(void);
79extern void momenco_ocelot_irq_setup(void);
80
81static char reset_reason;
82
83static unsigned long ENTRYLO(unsigned long paddr)
84{
85 return ((paddr & PAGE_MASK) |
86 (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
87 _CACHE_UNCACHED)) >> 6;
88}
89
90/* setup code for a handoff from a version 2 PMON 2000 PROM */
91void PMON_v2_setup(void)
92{
93 /* A wired TLB entry for the GT64240 and the serial port. The
94 GT64240 is going to be hit on every IRQ anyway - there's
95 absolutely no point in letting it be a random TLB entry, as
96 it'll just cause needless churning of the TLB. And we use
97 the other half for the serial port, which is just a PITA
98 otherwise :)
99
100 Device Physical Virtual
101 GT64240 Internal Regs 0xf4000000 0xe0000000
102 UARTs (CS2) 0xfd000000 0xe0001000
103 */
104 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000),
105 0xf4000000, PM_64K);
106 add_wired_entry(ENTRYLO(0xfd000000), ENTRYLO(0xfd001000),
107 0xfd000000, PM_4K);
108
109 /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM
110 in the CS[012] region. We can't use ioremap() yet. The NVRAM
111 is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions.
112
113 Ocelot PLD (CS0) 0xfc000000 0xe0020000
114 NVRAM (CS1) 0xfc800000 0xe0030000
115 */
116 add_temporary_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfc010000),
117 0xfc000000, PM_64K);
118 add_temporary_entry(ENTRYLO(0xfc800000), ENTRYLO(0xfc810000),
119 0xfc800000, PM_64K);
120
121 marvell_base = 0xf4000000;
122}
123
124extern int rm7k_tcache_enabled;
125
126/*
127 * This runs in KSEG1. See the verbiage in rm7k.c::probe_scache()
128 */
129#define Page_Invalidate_T 0x16
130static void __init setup_l3cache(unsigned long size)
131{
132 int register i;
133
134 printk("Enabling L3 cache...");
135
136 /* Enable the L3 cache in the GT64120A's CPU Configuration register */
137 MV_WRITE(0, MV_READ(0) | (1<<14));
138
139 /* Enable the L3 cache in the CPU */
140 set_c0_config(1<<12 /* CONF_TE */);
141
142 /* Clear the cache */
143 write_c0_taglo(0);
144 write_c0_taghi(0);
145
146 for (i=0; i < size; i+= 4096) {
147 __asm__ __volatile__ (
148 ".set noreorder\n\t"
149 ".set mips3\n\t"
150 "cache %1, (%0)\n\t"
151 ".set mips0\n\t"
152 ".set reorder"
153 :
154 : "r" (KSEG0ADDR(i)),
155 "i" (Page_Invalidate_T));
156 }
157
158 /* Let the RM7000 MM code know that the tertiary cache is enabled */
159 rm7k_tcache_enabled = 1;
160
161 printk("Done\n");
162}
163
164void __init plat_timer_setup(struct irqaction *irq)
165{
166}
167
168void __init plat_mem_setup(void)
169{
170 void (*l3func)(unsigned long) = (void *) KSEG1ADDR(setup_l3cache);
171 unsigned int tmpword;
172
173 board_time_init = gt64240_time_init;
174
175 _machine_restart = momenco_ocelot_restart;
176 _machine_halt = momenco_ocelot_halt;
177 pm_power_off = momenco_ocelot_power_off;
178
179 /*
180 * initrd_start = (unsigned long)ocelot_initrd_start;
181 * initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size;
182 * initrd_below_start_ok = 1;
183 */
184
185 /* do handoff reconfiguration */
186 PMON_v2_setup();
187
188#ifdef CONFIG_GALILEO_GT64240_ETH
189 /* get the mac addr */
190 memcpy(prom_mac_addr_base, (void*)0xfc807cf2, 6);
191#endif
192
193 /* Turn off the Bit-Error LED */
194 OCELOT_PLD_WRITE(0x80, INTCLR);
195
196 tmpword = OCELOT_PLD_READ(BOARDREV);
197 if (tmpword < 26)
198 printk("Momenco Ocelot-G: Board Assembly Rev. %c\n", 'A'+tmpword);
199 else
200 printk("Momenco Ocelot-G: Board Assembly Revision #0x%x\n", tmpword);
201
202 tmpword = OCELOT_PLD_READ(PLD1_ID);
203 printk("PLD 1 ID: %d.%d\n", tmpword>>4, tmpword&15);
204 tmpword = OCELOT_PLD_READ(PLD2_ID);
205 printk("PLD 2 ID: %d.%d\n", tmpword>>4, tmpword&15);
206 tmpword = OCELOT_PLD_READ(RESET_STATUS);
207 printk("Reset reason: 0x%x\n", tmpword);
208 reset_reason = tmpword;
209 OCELOT_PLD_WRITE(0xff, RESET_STATUS);
210
211 tmpword = OCELOT_PLD_READ(BOARD_STATUS);
212 printk("Board Status register: 0x%02x\n", tmpword);
213 printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
214 printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
215 printk(" - Tulip PHY %s connected\n", (tmpword&0x10)?"is":"not");
216 printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1);
217 printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3)));
218
219 if (tmpword&12)
220 l3func((1<<(((tmpword&12) >> 2)+20)));
221
222 switch(tmpword &3) {
223 case 3:
224 /* 512MiB -- two banks of 256MiB */
225 add_memory_region( 0x0<<20, 0x100<<20, BOOT_MEM_RAM);
226/*
227 add_memory_region(0x100<<20, 0x100<<20, BOOT_MEM_RAM);
228*/
229 break;
230 case 2:
231 /* 256MiB -- two banks of 128MiB */
232 add_memory_region( 0x0<<20, 0x80<<20, BOOT_MEM_RAM);
233 add_memory_region(0x80<<20, 0x80<<20, BOOT_MEM_RAM);
234 break;
235 case 1:
236 /* 128MiB -- 64MiB per bank */
237 add_memory_region( 0x0<<20, 0x40<<20, BOOT_MEM_RAM);
238 add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM);
239 break;
240 case 0:
241 /* 64MiB */
242 add_memory_region( 0x0<<20, 0x40<<20, BOOT_MEM_RAM);
243 break;
244 }
245
246 /* FIXME: Fix up the DiskOnChip mapping */
247 MV_WRITE(0x468, 0xfef73);
248}
249
250/* This needs to be one of the first initcalls, because no I/O port access
251 can work before this */
252
253static int io_base_ioremap(void)
254{
255 /* we're mapping PCI accesses from 0xc0000000 to 0xf0000000 */
256 unsigned long io_remap_range;
257
258 io_remap_range = (unsigned long) ioremap(0xc0000000, 0x30000000);
259 if (!io_remap_range)
260 panic("Could not ioremap I/O port range");
261
262 set_io_port_base(io_remap_range - 0xc0000000);
263
264 return 0;
265}
266
267module_init(io_base_ioremap);
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index df487c063b1d..aba3dbf47eda 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -30,11 +30,9 @@ obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
30obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o 30obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o
31obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o 31obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o
32obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o 32obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o
33obj-$(CONFIG_MOMENCO_JAGUAR_ATX)+= fixup-jaguar.o
34obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o 33obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o
35obj-$(CONFIG_MOMENCO_OCELOT_3) += fixup-ocelot3.o 34obj-$(CONFIG_MOMENCO_OCELOT_3) += fixup-ocelot3.o
36obj-$(CONFIG_MOMENCO_OCELOT_C) += fixup-ocelot-c.o pci-ocelot-c.o 35obj-$(CONFIG_MOMENCO_OCELOT_C) += fixup-ocelot-c.o pci-ocelot-c.o
37obj-$(CONFIG_MOMENCO_OCELOT_G) += fixup-ocelot-g.o pci-ocelot-g.o
38obj-$(CONFIG_PMC_YOSEMITE) += fixup-yosemite.o ops-titan.o ops-titan-ht.o \ 36obj-$(CONFIG_PMC_YOSEMITE) += fixup-yosemite.o ops-titan.o ops-titan-ht.o \
39 pci-yosemite.o 37 pci-yosemite.o
40obj-$(CONFIG_SGI_IP27) += ops-bridge.o pci-ip27.o 38obj-$(CONFIG_SGI_IP27) += ops-bridge.o pci-ip27.o
diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c
index 7d5f6bbf7a9d..d57ffd7242ca 100644
--- a/arch/mips/pci/fixup-cobalt.c
+++ b/arch/mips/pci/fixup-cobalt.c
@@ -17,9 +17,7 @@
17#include <asm/io.h> 17#include <asm/io.h>
18#include <asm/gt64120.h> 18#include <asm/gt64120.h>
19 19
20#include <asm/mach-cobalt/cobalt.h> 20#include <cobalt.h>
21
22extern int cobalt_board_id;
23 21
24static void qube_raq_galileo_early_fixup(struct pci_dev *dev) 22static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
25{ 23{
@@ -115,6 +113,27 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev)
115DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111, 113DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
116 qube_raq_galileo_fixup); 114 qube_raq_galileo_fixup);
117 115
116int cobalt_board_id;
117
118static void qube_raq_via_board_id_fixup(struct pci_dev *dev)
119{
120 u8 id;
121 int retval;
122
123 retval = pci_read_config_byte(dev, VIA_COBALT_BRD_ID_REG, &id);
124 if (retval) {
125 panic("Cannot read board ID");
126 return;
127 }
128
129 cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(id);
130
131 printk(KERN_INFO "Cobalt board ID: %d\n", cobalt_board_id);
132}
133
134DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0,
135 qube_raq_via_board_id_fixup);
136
118static char irq_tab_qube1[] __initdata = { 137static char irq_tab_qube1[] __initdata = {
119 [COBALT_PCICONF_CPU] = 0, 138 [COBALT_PCICONF_CPU] = 0,
120 [COBALT_PCICONF_ETH0] = COBALT_QUBE1_ETH0_IRQ, 139 [COBALT_PCICONF_ETH0] = COBALT_QUBE1_ETH0_IRQ,
diff --git a/arch/mips/pci/fixup-jaguar.c b/arch/mips/pci/fixup-jaguar.c
deleted file mode 100644
index 6c5e1d47179c..000000000000
--- a/arch/mips/pci/fixup-jaguar.c
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Marvell MV64340 interrupt fixup code.
7 *
8 * Marvell wants an NDA for their docs so this was written without
9 * documentation. You've been warned.
10 *
11 * Copyright (C) 2004 Ralf Baechle (ralf@linux-mips.org)
12 */
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/pci.h>
16
17#include <asm/mipsregs.h>
18
19/*
20 * WARNING: Example of how _NOT_ to do it.
21 */
22int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
23{
24 int bus = dev->bus->number;
25
26 if (bus == 0 && slot == 1)
27 return 3; /* PCI-X A */
28 if (bus == 0 && slot == 2)
29 return 4; /* PCI-X B */
30 if (bus == 1 && slot == 1)
31 return 5; /* PCI A */
32 if (bus == 1 && slot == 2)
33 return 6; /* PCI B */
34
35return 0;
36 panic("Whooops in pcibios_map_irq");
37}
38
39/* Do platform specific device initialization at pci_enable_device() time */
40int pcibios_plat_dev_init(struct pci_dev *dev)
41{
42 return 0;
43}
diff --git a/arch/mips/pci/fixup-ocelot-g.c b/arch/mips/pci/fixup-ocelot-g.c
deleted file mode 100644
index d7a652e326c5..000000000000
--- a/arch/mips/pci/fixup-ocelot-g.c
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Copyright (C) 2004 Ralf Baechle (ralf@linux-mips.org)
8 */
9#include <linux/types.h>
10#include <linux/pci.h>
11#include <linux/kernel.h>
12#include <linux/init.h>
13
14int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
15{
16 int bus = dev->bus->number;
17
18 if (bus == 0 && slot == 1) /* Intel 82543 Gigabit MAC */
19 return 2; /* irq_nr is 2 for INT0 */
20
21 if (bus == 0 && slot == 2) /* Intel 82543 Gigabit MAC */
22 return 3; /* irq_nr is 3 for INT1 */
23
24 if (bus == 1 && slot == 3) /* Intel 21555 bridge */
25 return 5; /* irq_nr is 8 for INT6 */
26
27 if (bus == 1 && slot == 4) /* PMC Slot */
28 return 9; /* irq_nr is 9 for INT7 */
29
30 return -1;
31}
32
33/* Do platform specific device initialization at pci_enable_device() time */
34int pcibios_plat_dev_init(struct pci_dev *dev)
35{
36 return 0;
37}
diff --git a/arch/mips/pci/pci-ocelot-g.c b/arch/mips/pci/pci-ocelot-g.c
deleted file mode 100644
index 1e3430154fa0..000000000000
--- a/arch/mips/pci/pci-ocelot-g.c
+++ /dev/null
@@ -1,97 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
7 *
8 * This doesn't really fly - but I don't have a GT64240 system for testing.
9 */
10#include <linux/init.h>
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/pci.h>
14#include <asm/gt64240.h>
15
16/*
17 * We assume these address ranges have been programmed into the GT-64240 by
18 * the firmware. PMON in case of the Ocelot G does that. Note the size of
19 * the I/O range is completly stupid; I/O mappings are limited to at most
20 * 256 bytes by the PCI spec and deprecated; and just to make things worse
21 * apparently many devices don't decode more than 64k of I/O space.
22 */
23
24#define gt_io_size 0x20000000UL
25#define gt_io_base 0xe0000000UL
26
27static struct resource gt_pci_mem0_resource = {
28 .name = "MV64240 PCI0 MEM",
29 .start = 0xc0000000UL,
30 .end = 0xcfffffffUL,
31 .flags = IORESOURCE_MEM
32};
33
34static struct resource gt_pci_io_mem0_resource = {
35 .name = "MV64240 PCI0 IO MEM",
36 .start = 0xe0000000UL,
37 .end = 0xefffffffUL,
38 .flags = IORESOURCE_IO
39};
40
41static struct mv_pci_controller gt_bus0_controller = {
42 .pcic = {
43 .pci_ops = &mv_pci_ops,
44 .mem_resource = &gt_pci_mem0_resource,
45 .mem_offset = 0xc0000000UL,
46 .io_resource = &gt_pci_io_mem0_resource,
47 .io_offset = 0x00000000UL
48 },
49 .config_addr = PCI_0CONFIGURATION_ADDRESS,
50 .config_vreg = PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
51};
52
53static struct resource gt_pci_mem1_resource = {
54 .name = "MV64240 PCI1 MEM",
55 .start = 0xd0000000UL,
56 .end = 0xdfffffffUL,
57 .flags = IORESOURCE_MEM
58};
59
60static struct resource gt_pci_io_mem1_resource = {
61 .name = "MV64240 PCI1 IO MEM",
62 .start = 0xf0000000UL,
63 .end = 0xffffffffUL,
64 .flags = IORESOURCE_IO
65};
66
67static struct mv_pci_controller gt_bus1_controller = {
68 .pcic = {
69 .pci_ops = &mv_pci_ops,
70 .mem_resource = &gt_pci_mem1_resource,
71 .mem_offset = 0xd0000000UL,
72 .io_resource = &gt_pci_io_mem1_resource,
73 .io_offset = 0x10000000UL
74 },
75 .config_addr = PCI_1CONFIGURATION_ADDRESS,
76 .config_vreg = PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER,
77};
78
79static __init int __init ocelot_g_pci_init(void)
80{
81 unsigned long io_v_base;
82
83 if (gt_io_size) {
84 io_v_base = (unsigned long) ioremap(gt_io_base, gt_io_size);
85 if (!io_v_base)
86 panic("Could not ioremap I/O port range");
87
88 set_io_port_base(io_v_base);
89 }
90
91 register_pci_controller(&gt_bus0_controller.pcic);
92 register_pci_controller(&gt_bus1_controller.pcic);
93
94 return 0;
95}
96
97arch_initcall(ocelot_g_pci_init);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 19:46:20 -0500