diff options
author | Peter Ujfalusi <peter.ujfalusi@nokia.com> | 2006-06-26 19:16:06 -0400 |
---|---|---|
committer | Tony Lindgren <tony@atomide.com> | 2006-06-26 19:16:06 -0400 |
commit | eca9e56eb8dfcf2b8b966c1c49e4622196f0586d (patch) | |
tree | 09dfd83d3e56f1dfc52475f8e539b86b382d468b /arch | |
parent | e8cdf7bdf3efbb1e285fd82a86a3f8fae5ae2665 (diff) |
ARM: OMAP: DMA transfer parameter configuration fix
Fix for re-using OMAP DMA channel with different transfer parameters.
Bits in the CCR register need to be cleaned as well in some cases.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/plat-omap/dma.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 5dac4230360d..aa1cf79f9543 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c | |||
@@ -166,18 +166,24 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, | |||
166 | if (cpu_is_omap24xx() && dma_trigger) { | 166 | if (cpu_is_omap24xx() && dma_trigger) { |
167 | u32 val = OMAP_DMA_CCR_REG(lch); | 167 | u32 val = OMAP_DMA_CCR_REG(lch); |
168 | 168 | ||
169 | val &= ~(3 << 19); | ||
169 | if (dma_trigger > 63) | 170 | if (dma_trigger > 63) |
170 | val |= 1 << 20; | 171 | val |= 1 << 20; |
171 | if (dma_trigger > 31) | 172 | if (dma_trigger > 31) |
172 | val |= 1 << 19; | 173 | val |= 1 << 19; |
173 | 174 | ||
175 | val &= ~(0x1f); | ||
174 | val |= (dma_trigger & 0x1f); | 176 | val |= (dma_trigger & 0x1f); |
175 | 177 | ||
176 | if (sync_mode & OMAP_DMA_SYNC_FRAME) | 178 | if (sync_mode & OMAP_DMA_SYNC_FRAME) |
177 | val |= 1 << 5; | 179 | val |= 1 << 5; |
180 | else | ||
181 | val &= ~(1 << 5); | ||
178 | 182 | ||
179 | if (sync_mode & OMAP_DMA_SYNC_BLOCK) | 183 | if (sync_mode & OMAP_DMA_SYNC_BLOCK) |
180 | val |= 1 << 18; | 184 | val |= 1 << 18; |
185 | else | ||
186 | val &= ~(1 << 18); | ||
181 | 187 | ||
182 | if (src_or_dst_synch) | 188 | if (src_or_dst_synch) |
183 | val |= 1 << 24; /* source synch */ | 189 | val |= 1 << 24; /* source synch */ |