[X86] Add new Intel cache descriptors.

From http://www.intel.com/design/xeon/applnots/24161830.pdf

16MB of 16-way assoc 64 byte per cacheline L3 cache anyone? Yum.

Signed-off-by: Dave Jones <davej@redhat.com>

1 files changed, 11 insertions, 0 deletions

diff --git a/arch/i386/kernel/cpu/intel_cacheinfo.c b/arch/i386/kernel/cpu/intel_cacheinfo.c
index fbfd374aa336..af591c73345f 100644
--- a/arch/i386/kernel/cpu/intel_cacheinfo.c
+++ b/arch/i386/kernel/cpu/intel_cacheinfo.c
@@ -43,13 +43,23 @@ static struct _cache_table cache_table[] __cpuinitdata =
         { 0x2c, LVL_1_DATA, 32 },       /* 8-way set assoc, 64 byte line size */
         { 0x30, LVL_1_INST, 32 },       /* 8-way set assoc, 64 byte line size */
         { 0x39, LVL_2,      128 },      /* 4-way set assoc, sectored cache, 64 byte line size */
+        { 0x3a, LVL_2,      192 },      /* 6-way set assoc, sectored cache, 64 byte line size */
         { 0x3b, LVL_2,      128 },      /* 2-way set assoc, sectored cache, 64 byte line size */
         { 0x3c, LVL_2,      256 },      /* 4-way set assoc, sectored cache, 64 byte line size */
+        { 0x3d, LVL_2,      384 },      /* 6-way set assoc, sectored cache, 64 byte line size */
+        { 0x3e, LVL_2,      512 },      /* 4-way set assoc, sectored cache, 64 byte line size */
         { 0x41, LVL_2,      128 },      /* 4-way set assoc, 32 byte line size */
         { 0x42, LVL_2,      256 },      /* 4-way set assoc, 32 byte line size */
         { 0x43, LVL_2,      512 },      /* 4-way set assoc, 32 byte line size */
         { 0x44, LVL_2,      1024 },     /* 4-way set assoc, 32 byte line size */
         { 0x45, LVL_2,      2048 },     /* 4-way set assoc, 32 byte line size */
+        { 0x46, LVL_3,      4096 },     /* 4-way set assoc, 64 byte line size */
+        { 0x47, LVL_3,      8192 },     /* 8-way set assoc, 64 byte line size */
+        { 0x49, LVL_3,      4096 },     /* 16-way set assoc, 64 byte line size */
+        { 0x4a, LVL_3,      6144 },     /* 12-way set assoc, 64 byte line size */
+        { 0x4b, LVL_3,      8192 },     /* 16-way set assoc, 64 byte line size */
+        { 0x4c, LVL_3,     12288 },     /* 12-way set assoc, 64 byte line size */
+        { 0x4d, LVL_3,     16384 },     /* 16-way set assoc, 64 byte line size */
         { 0x60, LVL_1_DATA, 16 },       /* 8-way set assoc, sectored cache, 64 byte line size */
         { 0x66, LVL_1_DATA, 8 },        /* 4-way set assoc, sectored cache, 64 byte line size */
         { 0x67, LVL_1_DATA, 16 },       /* 4-way set assoc, sectored cache, 64 byte line size */
@@ -57,6 +67,7 @@ static struct _cache_table cache_table[] __cpuinitdata =
         { 0x70, LVL_TRACE,  12 },       /* 8-way set assoc */
         { 0x71, LVL_TRACE,  16 },       /* 8-way set assoc */
         { 0x72, LVL_TRACE,  32 },       /* 8-way set assoc */
+        { 0x73, LVL_TRACE,  64 },       /* 8-way set assoc */
         { 0x78, LVL_2,    1024 },       /* 4-way set assoc, 64 byte line size */
         { 0x79, LVL_2,     128 },       /* 8-way set assoc, sectored cache, 64 byte line size */
         { 0x7a, LVL_2,     256 },       /* 8-way set assoc, sectored cache, 64 byte line size */