aboutsummaryrefslogtreecommitdiffstats
path: root/arch
diff options
context:
space:
mode:
authorIngo Molnar <mingo@elte.hu>2009-09-21 06:02:48 -0400
committerIngo Molnar <mingo@elte.hu>2009-09-21 08:28:04 -0400
commitcdd6c482c9ff9c55475ee7392ec8f672eddb7be6 (patch)
tree81f98a3ab46c589792057fe2392c1e10f8ad7893 /arch
parentdfc65094d0313cc48969fa60bcf33d693aeb05a7 (diff)
perf: Do the big rename: Performance Counters -> Performance Events
Bye-bye Performance Counters, welcome Performance Events! In the past few months the perfcounters subsystem has grown out its initial role of counting hardware events, and has become (and is becoming) a much broader generic event enumeration, reporting, logging, monitoring, analysis facility. Naming its core object 'perf_counter' and naming the subsystem 'perfcounters' has become more and more of a misnomer. With pending code like hw-breakpoints support the 'counter' name is less and less appropriate. All in one, we've decided to rename the subsystem to 'performance events' and to propagate this rename through all fields, variables and API names. (in an ABI compatible fashion) The word 'event' is also a bit shorter than 'counter' - which makes it slightly more convenient to write/handle as well. Thanks goes to Stephane Eranian who first observed this misnomer and suggested a rename. User-space tooling and ABI compatibility is not affected - this patch should be function-invariant. (Also, defconfigs were not touched to keep the size down.) This patch has been generated via the following script: FILES=$(find * -type f | grep -vE 'oprofile|[^K]config') sed -i \ -e 's/PERF_EVENT_/PERF_RECORD_/g' \ -e 's/PERF_COUNTER/PERF_EVENT/g' \ -e 's/perf_counter/perf_event/g' \ -e 's/nb_counters/nb_events/g' \ -e 's/swcounter/swevent/g' \ -e 's/tpcounter_event/tp_event/g' \ $FILES for N in $(find . -name perf_counter.[ch]); do M=$(echo $N | sed 's/perf_counter/perf_event/g') mv $N $M done FILES=$(find . -name perf_event.*) sed -i \ -e 's/COUNTER_MASK/REG_MASK/g' \ -e 's/COUNTER/EVENT/g' \ -e 's/\<event\>/event_id/g' \ -e 's/counter/event/g' \ -e 's/Counter/Event/g' \ $FILES ... to keep it as correct as possible. This script can also be used by anyone who has pending perfcounters patches - it converts a Linux kernel tree over to the new naming. We tried to time this change to the point in time where the amount of pending patches is the smallest: the end of the merge window. Namespace clashes were fixed up in a preparatory patch - and some stylistic fallout will be fixed up in a subsequent patch. ( NOTE: 'counters' are still the proper terminology when we deal with hardware registers - and these sed scripts are a bit over-eager in renaming them. I've undone some of that, but in case there's something left where 'counter' would be better than 'event' we can undo that on an individual basis instead of touching an otherwise nicely automated patch. ) Suggested-by: Stephane Eranian <eranian@google.com> Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Acked-by: Paul Mackerras <paulus@samba.org> Reviewed-by: Arjan van de Ven <arjan@linux.intel.com> Cc: Mike Galbraith <efault@gmx.de> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: Steven Rostedt <rostedt@goodmis.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: David Howells <dhowells@redhat.com> Cc: Kyle McMartin <kyle@mcmartin.ca> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: <linux-arch@vger.kernel.org> LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/include/asm/unistd.h2
-rw-r--r--arch/arm/kernel/calls.S2
-rw-r--r--arch/blackfin/include/asm/unistd.h2
-rw-r--r--arch/blackfin/mach-common/entry.S2
-rw-r--r--arch/frv/Kconfig2
-rw-r--r--arch/frv/include/asm/perf_event.h (renamed from arch/frv/include/asm/perf_counter.h)10
-rw-r--r--arch/frv/include/asm/unistd.h2
-rw-r--r--arch/frv/kernel/entry.S2
-rw-r--r--arch/frv/lib/Makefile2
-rw-r--r--arch/frv/lib/perf_event.c (renamed from arch/frv/lib/perf_counter.c)8
-rw-r--r--arch/m68k/include/asm/unistd.h2
-rw-r--r--arch/m68k/kernel/entry.S2
-rw-r--r--arch/m68knommu/kernel/syscalltable.S2
-rw-r--r--arch/microblaze/include/asm/unistd.h2
-rw-r--r--arch/microblaze/kernel/syscall_table.S2
-rw-r--r--arch/mips/include/asm/unistd.h6
-rw-r--r--arch/mips/kernel/scall32-o32.S2
-rw-r--r--arch/mips/kernel/scall64-64.S2
-rw-r--r--arch/mips/kernel/scall64-n32.S2
-rw-r--r--arch/mips/kernel/scall64-o32.S2
-rw-r--r--arch/mn10300/include/asm/unistd.h2
-rw-r--r--arch/mn10300/kernel/entry.S2
-rw-r--r--arch/parisc/Kconfig2
-rw-r--r--arch/parisc/include/asm/perf_counter.h7
-rw-r--r--arch/parisc/include/asm/perf_event.h7
-rw-r--r--arch/parisc/include/asm/unistd.h4
-rw-r--r--arch/parisc/kernel/syscall_table.S2
-rw-r--r--arch/powerpc/Kconfig2
-rw-r--r--arch/powerpc/include/asm/hw_irq.h22
-rw-r--r--arch/powerpc/include/asm/paca.h2
-rw-r--r--arch/powerpc/include/asm/perf_event.h (renamed from arch/powerpc/include/asm/perf_counter.h)26
-rw-r--r--arch/powerpc/include/asm/systbl.h2
-rw-r--r--arch/powerpc/include/asm/unistd.h2
-rw-r--r--arch/powerpc/kernel/Makefile2
-rw-r--r--arch/powerpc/kernel/asm-offsets.c2
-rw-r--r--arch/powerpc/kernel/entry_64.S8
-rw-r--r--arch/powerpc/kernel/irq.c8
-rw-r--r--arch/powerpc/kernel/mpc7450-pmu.c2
-rw-r--r--arch/powerpc/kernel/perf_callchain.c2
-rw-r--r--arch/powerpc/kernel/perf_event.c (renamed from arch/powerpc/kernel/perf_counter.c)594
-rw-r--r--arch/powerpc/kernel/power4-pmu.c2
-rw-r--r--arch/powerpc/kernel/power5+-pmu.c2
-rw-r--r--arch/powerpc/kernel/power5-pmu.c2
-rw-r--r--arch/powerpc/kernel/power6-pmu.c2
-rw-r--r--arch/powerpc/kernel/power7-pmu.c2
-rw-r--r--arch/powerpc/kernel/ppc970-pmu.c2
-rw-r--r--arch/powerpc/kernel/time.c30
-rw-r--r--arch/powerpc/mm/fault.c8
-rw-r--r--arch/powerpc/platforms/Kconfig.cputype4
-rw-r--r--arch/s390/Kconfig2
-rw-r--r--arch/s390/include/asm/perf_counter.h10
-rw-r--r--arch/s390/include/asm/perf_event.h10
-rw-r--r--arch/s390/include/asm/unistd.h2
-rw-r--r--arch/s390/kernel/compat_wrapper.S8
-rw-r--r--arch/s390/kernel/syscalls.S2
-rw-r--r--arch/s390/mm/fault.c8
-rw-r--r--arch/sh/Kconfig2
-rw-r--r--arch/sh/include/asm/perf_counter.h9
-rw-r--r--arch/sh/include/asm/perf_event.h9
-rw-r--r--arch/sh/include/asm/unistd_32.h2
-rw-r--r--arch/sh/include/asm/unistd_64.h2
-rw-r--r--arch/sh/kernel/syscalls_32.S2
-rw-r--r--arch/sh/kernel/syscalls_64.S2
-rw-r--r--arch/sh/mm/fault_32.c8
-rw-r--r--arch/sh/mm/tlbflush_64.c8
-rw-r--r--arch/sparc/Kconfig4
-rw-r--r--arch/sparc/include/asm/perf_counter.h14
-rw-r--r--arch/sparc/include/asm/perf_event.h14
-rw-r--r--arch/sparc/include/asm/unistd.h2
-rw-r--r--arch/sparc/kernel/Makefile2
-rw-r--r--arch/sparc/kernel/nmi.c4
-rw-r--r--arch/sparc/kernel/pcr.c10
-rw-r--r--arch/sparc/kernel/perf_event.c (renamed from arch/sparc/kernel/perf_counter.c)178
-rw-r--r--arch/sparc/kernel/systbls_32.S2
-rw-r--r--arch/sparc/kernel/systbls_64.S4
-rw-r--r--arch/x86/Kconfig2
-rw-r--r--arch/x86/ia32/ia32entry.S2
-rw-r--r--arch/x86/include/asm/entry_arch.h2
-rw-r--r--arch/x86/include/asm/perf_event.h (renamed from arch/x86/include/asm/perf_counter.h)30
-rw-r--r--arch/x86/include/asm/unistd_32.h2
-rw-r--r--arch/x86/include/asm/unistd_64.h4
-rw-r--r--arch/x86/kernel/apic/apic.c6
-rw-r--r--arch/x86/kernel/cpu/Makefile2
-rw-r--r--arch/x86/kernel/cpu/common.c4
-rw-r--r--arch/x86/kernel/cpu/perf_event.c (renamed from arch/x86/kernel/cpu/perf_counter.c)504
-rw-r--r--arch/x86/kernel/cpu/perfctr-watchdog.c2
-rw-r--r--arch/x86/kernel/entry_64.S2
-rw-r--r--arch/x86/kernel/irqinit.c2
-rw-r--r--arch/x86/kernel/syscall_table_32.S2
-rw-r--r--arch/x86/mm/fault.c8
-rw-r--r--arch/x86/oprofile/op_model_ppro.c4
-rw-r--r--arch/x86/oprofile/op_x86_model.h2
92 files changed, 856 insertions, 856 deletions
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 9122c9ee18fb..89f7eade20af 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -390,7 +390,7 @@
390#define __NR_preadv (__NR_SYSCALL_BASE+361) 390#define __NR_preadv (__NR_SYSCALL_BASE+361)
391#define __NR_pwritev (__NR_SYSCALL_BASE+362) 391#define __NR_pwritev (__NR_SYSCALL_BASE+362)
392#define __NR_rt_tgsigqueueinfo (__NR_SYSCALL_BASE+363) 392#define __NR_rt_tgsigqueueinfo (__NR_SYSCALL_BASE+363)
393#define __NR_perf_counter_open (__NR_SYSCALL_BASE+364) 393#define __NR_perf_event_open (__NR_SYSCALL_BASE+364)
394 394
395/* 395/*
396 * The following SWIs are ARM private. 396 * The following SWIs are ARM private.
diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S
index ecfa98954d1d..fafce1b5c69f 100644
--- a/arch/arm/kernel/calls.S
+++ b/arch/arm/kernel/calls.S
@@ -373,7 +373,7 @@
373 CALL(sys_preadv) 373 CALL(sys_preadv)
374 CALL(sys_pwritev) 374 CALL(sys_pwritev)
375 CALL(sys_rt_tgsigqueueinfo) 375 CALL(sys_rt_tgsigqueueinfo)
376 CALL(sys_perf_counter_open) 376 CALL(sys_perf_event_open)
377#ifndef syscalls_counted 377#ifndef syscalls_counted
378.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls 378.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
379#define syscalls_counted 379#define syscalls_counted
diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h
index c8e7ee4768cd..02b1529dad57 100644
--- a/arch/blackfin/include/asm/unistd.h
+++ b/arch/blackfin/include/asm/unistd.h
@@ -381,7 +381,7 @@
381#define __NR_preadv 366 381#define __NR_preadv 366
382#define __NR_pwritev 367 382#define __NR_pwritev 367
383#define __NR_rt_tgsigqueueinfo 368 383#define __NR_rt_tgsigqueueinfo 368
384#define __NR_perf_counter_open 369 384#define __NR_perf_event_open 369
385 385
386#define __NR_syscall 370 386#define __NR_syscall 370
387#define NR_syscalls __NR_syscall 387#define NR_syscalls __NR_syscall
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index 01af24cde362..1e7cac23e25f 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -1620,7 +1620,7 @@ ENTRY(_sys_call_table)
1620 .long _sys_preadv 1620 .long _sys_preadv
1621 .long _sys_pwritev 1621 .long _sys_pwritev
1622 .long _sys_rt_tgsigqueueinfo 1622 .long _sys_rt_tgsigqueueinfo
1623 .long _sys_perf_counter_open 1623 .long _sys_perf_event_open
1624 1624
1625 .rept NR_syscalls-(.-_sys_call_table)/4 1625 .rept NR_syscalls-(.-_sys_call_table)/4
1626 .long _sys_ni_syscall 1626 .long _sys_ni_syscall
diff --git a/arch/frv/Kconfig b/arch/frv/Kconfig
index b86e19c9b5b0..4b5830bcbe2e 100644
--- a/arch/frv/Kconfig
+++ b/arch/frv/Kconfig
@@ -7,7 +7,7 @@ config FRV
7 default y 7 default y
8 select HAVE_IDE 8 select HAVE_IDE
9 select HAVE_ARCH_TRACEHOOK 9 select HAVE_ARCH_TRACEHOOK
10 select HAVE_PERF_COUNTERS 10 select HAVE_PERF_EVENTS
11 11
12config ZONE_DMA 12config ZONE_DMA
13 bool 13 bool
diff --git a/arch/frv/include/asm/perf_counter.h b/arch/frv/include/asm/perf_event.h
index ccf726e61b2e..a69e0155d146 100644
--- a/arch/frv/include/asm/perf_counter.h
+++ b/arch/frv/include/asm/perf_event.h
@@ -1,4 +1,4 @@
1/* FRV performance counter support 1/* FRV performance event support
2 * 2 *
3 * Copyright (C) 2009 Red Hat, Inc. All Rights Reserved. 3 * Copyright (C) 2009 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com) 4 * Written by David Howells (dhowells@redhat.com)
@@ -9,9 +9,9 @@
9 * 2 of the Licence, or (at your option) any later version. 9 * 2 of the Licence, or (at your option) any later version.
10 */ 10 */
11 11
12#ifndef _ASM_PERF_COUNTER_H 12#ifndef _ASM_PERF_EVENT_H
13#define _ASM_PERF_COUNTER_H 13#define _ASM_PERF_EVENT_H
14 14
15#define PERF_COUNTER_INDEX_OFFSET 0 15#define PERF_EVENT_INDEX_OFFSET 0
16 16
17#endif /* _ASM_PERF_COUNTER_H */ 17#endif /* _ASM_PERF_EVENT_H */
diff --git a/arch/frv/include/asm/unistd.h b/arch/frv/include/asm/unistd.h
index 4a8fb427ce0a..be6ef0f5cd42 100644
--- a/arch/frv/include/asm/unistd.h
+++ b/arch/frv/include/asm/unistd.h
@@ -342,7 +342,7 @@
342#define __NR_preadv 333 342#define __NR_preadv 333
343#define __NR_pwritev 334 343#define __NR_pwritev 334
344#define __NR_rt_tgsigqueueinfo 335 344#define __NR_rt_tgsigqueueinfo 335
345#define __NR_perf_counter_open 336 345#define __NR_perf_event_open 336
346 346
347#ifdef __KERNEL__ 347#ifdef __KERNEL__
348 348
diff --git a/arch/frv/kernel/entry.S b/arch/frv/kernel/entry.S
index fde1e446b440..189397ec012a 100644
--- a/arch/frv/kernel/entry.S
+++ b/arch/frv/kernel/entry.S
@@ -1525,6 +1525,6 @@ sys_call_table:
1525 .long sys_preadv 1525 .long sys_preadv
1526 .long sys_pwritev 1526 .long sys_pwritev
1527 .long sys_rt_tgsigqueueinfo /* 335 */ 1527 .long sys_rt_tgsigqueueinfo /* 335 */
1528 .long sys_perf_counter_open 1528 .long sys_perf_event_open
1529 1529
1530syscall_table_size = (. - sys_call_table) 1530syscall_table_size = (. - sys_call_table)
diff --git a/arch/frv/lib/Makefile b/arch/frv/lib/Makefile
index 0a377210c89b..f4709756d0d9 100644
--- a/arch/frv/lib/Makefile
+++ b/arch/frv/lib/Makefile
@@ -5,4 +5,4 @@
5lib-y := \ 5lib-y := \
6 __ashldi3.o __lshrdi3.o __muldi3.o __ashrdi3.o __negdi2.o __ucmpdi2.o \ 6 __ashldi3.o __lshrdi3.o __muldi3.o __ashrdi3.o __negdi2.o __ucmpdi2.o \
7 checksum.o memcpy.o memset.o atomic-ops.o atomic64-ops.o \ 7 checksum.o memcpy.o memset.o atomic-ops.o atomic64-ops.o \
8 outsl_ns.o outsl_sw.o insl_ns.o insl_sw.o cache.o perf_counter.o 8 outsl_ns.o outsl_sw.o insl_ns.o insl_sw.o cache.o perf_event.o
diff --git a/arch/frv/lib/perf_counter.c b/arch/frv/lib/perf_event.c
index 2000feecd571..9ac5acfd2e91 100644
--- a/arch/frv/lib/perf_counter.c
+++ b/arch/frv/lib/perf_event.c
@@ -1,4 +1,4 @@
1/* Performance counter handling 1/* Performance event handling
2 * 2 *
3 * Copyright (C) 2009 Red Hat, Inc. All Rights Reserved. 3 * Copyright (C) 2009 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com) 4 * Written by David Howells (dhowells@redhat.com)
@@ -9,11 +9,11 @@
9 * 2 of the Licence, or (at your option) any later version. 9 * 2 of the Licence, or (at your option) any later version.
10 */ 10 */
11 11
12#include <linux/perf_counter.h> 12#include <linux/perf_event.h>
13 13
14/* 14/*
15 * mark the performance counter as pending 15 * mark the performance event as pending
16 */ 16 */
17void set_perf_counter_pending(void) 17void set_perf_event_pending(void)
18{ 18{
19} 19}
diff --git a/arch/m68k/include/asm/unistd.h b/arch/m68k/include/asm/unistd.h
index 946d8691f2b0..48b87f5ced50 100644
--- a/arch/m68k/include/asm/unistd.h
+++ b/arch/m68k/include/asm/unistd.h
@@ -335,7 +335,7 @@
335#define __NR_preadv 329 335#define __NR_preadv 329
336#define __NR_pwritev 330 336#define __NR_pwritev 330
337#define __NR_rt_tgsigqueueinfo 331 337#define __NR_rt_tgsigqueueinfo 331
338#define __NR_perf_counter_open 332 338#define __NR_perf_event_open 332
339 339
340#ifdef __KERNEL__ 340#ifdef __KERNEL__
341 341
diff --git a/arch/m68k/kernel/entry.S b/arch/m68k/kernel/entry.S
index 922f52e7ed1a..c5b33634c980 100644
--- a/arch/m68k/kernel/entry.S
+++ b/arch/m68k/kernel/entry.S
@@ -756,5 +756,5 @@ sys_call_table:
756 .long sys_preadv 756 .long sys_preadv
757 .long sys_pwritev /* 330 */ 757 .long sys_pwritev /* 330 */
758 .long sys_rt_tgsigqueueinfo 758 .long sys_rt_tgsigqueueinfo
759 .long sys_perf_counter_open 759 .long sys_perf_event_open
760 760
diff --git a/arch/m68knommu/kernel/syscalltable.S b/arch/m68knommu/kernel/syscalltable.S
index 0ae123e08985..23535cc415ae 100644
--- a/arch/m68knommu/kernel/syscalltable.S
+++ b/arch/m68knommu/kernel/syscalltable.S
@@ -350,7 +350,7 @@ ENTRY(sys_call_table)
350 .long sys_preadv 350 .long sys_preadv
351 .long sys_pwritev /* 330 */ 351 .long sys_pwritev /* 330 */
352 .long sys_rt_tgsigqueueinfo 352 .long sys_rt_tgsigqueueinfo
353 .long sys_perf_counter_open 353 .long sys_perf_event_open
354 354
355 .rept NR_syscalls-(.-sys_call_table)/4 355 .rept NR_syscalls-(.-sys_call_table)/4
356 .long sys_ni_syscall 356 .long sys_ni_syscall
diff --git a/arch/microblaze/include/asm/unistd.h b/arch/microblaze/include/asm/unistd.h
index 0b852327c0e7..cb05a07e55e9 100644
--- a/arch/microblaze/include/asm/unistd.h
+++ b/arch/microblaze/include/asm/unistd.h
@@ -381,7 +381,7 @@
381#define __NR_preadv 363 /* new */ 381#define __NR_preadv 363 /* new */
382#define __NR_pwritev 364 /* new */ 382#define __NR_pwritev 364 /* new */
383#define __NR_rt_tgsigqueueinfo 365 /* new */ 383#define __NR_rt_tgsigqueueinfo 365 /* new */
384#define __NR_perf_counter_open 366 /* new */ 384#define __NR_perf_event_open 366 /* new */
385 385
386#define __NR_syscalls 367 386#define __NR_syscalls 367
387 387
diff --git a/arch/microblaze/kernel/syscall_table.S b/arch/microblaze/kernel/syscall_table.S
index 457216097dfd..ecec19155135 100644
--- a/arch/microblaze/kernel/syscall_table.S
+++ b/arch/microblaze/kernel/syscall_table.S
@@ -370,4 +370,4 @@ ENTRY(sys_call_table)
370 .long sys_ni_syscall 370 .long sys_ni_syscall
371 .long sys_ni_syscall 371 .long sys_ni_syscall
372 .long sys_rt_tgsigqueueinfo /* 365 */ 372 .long sys_rt_tgsigqueueinfo /* 365 */
373 .long sys_perf_counter_open 373 .long sys_perf_event_open
diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h
index e753a777949b..8c9dfa9e9018 100644
--- a/arch/mips/include/asm/unistd.h
+++ b/arch/mips/include/asm/unistd.h
@@ -353,7 +353,7 @@
353#define __NR_preadv (__NR_Linux + 330) 353#define __NR_preadv (__NR_Linux + 330)
354#define __NR_pwritev (__NR_Linux + 331) 354#define __NR_pwritev (__NR_Linux + 331)
355#define __NR_rt_tgsigqueueinfo (__NR_Linux + 332) 355#define __NR_rt_tgsigqueueinfo (__NR_Linux + 332)
356#define __NR_perf_counter_open (__NR_Linux + 333) 356#define __NR_perf_event_open (__NR_Linux + 333)
357#define __NR_accept4 (__NR_Linux + 334) 357#define __NR_accept4 (__NR_Linux + 334)
358 358
359/* 359/*
@@ -664,7 +664,7 @@
664#define __NR_preadv (__NR_Linux + 289) 664#define __NR_preadv (__NR_Linux + 289)
665#define __NR_pwritev (__NR_Linux + 290) 665#define __NR_pwritev (__NR_Linux + 290)
666#define __NR_rt_tgsigqueueinfo (__NR_Linux + 291) 666#define __NR_rt_tgsigqueueinfo (__NR_Linux + 291)
667#define __NR_perf_counter_open (__NR_Linux + 292) 667#define __NR_perf_event_open (__NR_Linux + 292)
668#define __NR_accept4 (__NR_Linux + 293) 668#define __NR_accept4 (__NR_Linux + 293)
669 669
670/* 670/*
@@ -979,7 +979,7 @@
979#define __NR_preadv (__NR_Linux + 293) 979#define __NR_preadv (__NR_Linux + 293)
980#define __NR_pwritev (__NR_Linux + 294) 980#define __NR_pwritev (__NR_Linux + 294)
981#define __NR_rt_tgsigqueueinfo (__NR_Linux + 295) 981#define __NR_rt_tgsigqueueinfo (__NR_Linux + 295)
982#define __NR_perf_counter_open (__NR_Linux + 296) 982#define __NR_perf_event_open (__NR_Linux + 296)
983#define __NR_accept4 (__NR_Linux + 297) 983#define __NR_accept4 (__NR_Linux + 297)
984 984
985/* 985/*
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index 7c2de4f091c4..fd2a9bb620d6 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -581,7 +581,7 @@ einval: li v0, -ENOSYS
581 sys sys_preadv 6 /* 4330 */ 581 sys sys_preadv 6 /* 4330 */
582 sys sys_pwritev 6 582 sys sys_pwritev 6
583 sys sys_rt_tgsigqueueinfo 4 583 sys sys_rt_tgsigqueueinfo 4
584 sys sys_perf_counter_open 5 584 sys sys_perf_event_open 5
585 sys sys_accept4 4 585 sys sys_accept4 4
586 .endm 586 .endm
587 587
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index b97b993846d6..18bf7f32c5e4 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -418,6 +418,6 @@ sys_call_table:
418 PTR sys_preadv 418 PTR sys_preadv
419 PTR sys_pwritev /* 5390 */ 419 PTR sys_pwritev /* 5390 */
420 PTR sys_rt_tgsigqueueinfo 420 PTR sys_rt_tgsigqueueinfo
421 PTR sys_perf_counter_open 421 PTR sys_perf_event_open
422 PTR sys_accept4 422 PTR sys_accept4
423 .size sys_call_table,.-sys_call_table 423 .size sys_call_table,.-sys_call_table
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index 1a6ae124635b..6ebc07976694 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -416,6 +416,6 @@ EXPORT(sysn32_call_table)
416 PTR sys_preadv 416 PTR sys_preadv
417 PTR sys_pwritev 417 PTR sys_pwritev
418 PTR compat_sys_rt_tgsigqueueinfo /* 5295 */ 418 PTR compat_sys_rt_tgsigqueueinfo /* 5295 */
419 PTR sys_perf_counter_open 419 PTR sys_perf_event_open
420 PTR sys_accept4 420 PTR sys_accept4
421 .size sysn32_call_table,.-sysn32_call_table 421 .size sysn32_call_table,.-sysn32_call_table
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index cd31087a651f..9bbf9775e0bd 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -536,6 +536,6 @@ sys_call_table:
536 PTR compat_sys_preadv /* 4330 */ 536 PTR compat_sys_preadv /* 4330 */
537 PTR compat_sys_pwritev 537 PTR compat_sys_pwritev
538 PTR compat_sys_rt_tgsigqueueinfo 538 PTR compat_sys_rt_tgsigqueueinfo
539 PTR sys_perf_counter_open 539 PTR sys_perf_event_open
540 PTR sys_accept4 540 PTR sys_accept4
541 .size sys_call_table,.-sys_call_table 541 .size sys_call_table,.-sys_call_table
diff --git a/arch/mn10300/include/asm/unistd.h b/arch/mn10300/include/asm/unistd.h
index fad68616af32..2a983931c11f 100644
--- a/arch/mn10300/include/asm/unistd.h
+++ b/arch/mn10300/include/asm/unistd.h
@@ -347,7 +347,7 @@
347#define __NR_preadv 334 347#define __NR_preadv 334
348#define __NR_pwritev 335 348#define __NR_pwritev 335
349#define __NR_rt_tgsigqueueinfo 336 349#define __NR_rt_tgsigqueueinfo 336
350#define __NR_perf_counter_open 337 350#define __NR_perf_event_open 337
351 351
352#ifdef __KERNEL__ 352#ifdef __KERNEL__
353 353
diff --git a/arch/mn10300/kernel/entry.S b/arch/mn10300/kernel/entry.S
index e0d2563af4f2..a94e7ea3faa6 100644
--- a/arch/mn10300/kernel/entry.S
+++ b/arch/mn10300/kernel/entry.S
@@ -723,7 +723,7 @@ ENTRY(sys_call_table)
723 .long sys_preadv 723 .long sys_preadv
724 .long sys_pwritev /* 335 */ 724 .long sys_pwritev /* 335 */
725 .long sys_rt_tgsigqueueinfo 725 .long sys_rt_tgsigqueueinfo
726 .long sys_perf_counter_open 726 .long sys_perf_event_open
727 727
728 728
729nr_syscalls=(.-sys_call_table)/4 729nr_syscalls=(.-sys_call_table)/4
diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig
index 06f8d5b5b0f9..f388dc68f605 100644
--- a/arch/parisc/Kconfig
+++ b/arch/parisc/Kconfig
@@ -16,7 +16,7 @@ config PARISC
16 select RTC_DRV_GENERIC 16 select RTC_DRV_GENERIC
17 select INIT_ALL_POSSIBLE 17 select INIT_ALL_POSSIBLE
18 select BUG 18 select BUG
19 select HAVE_PERF_COUNTERS 19 select HAVE_PERF_EVENTS
20 select GENERIC_ATOMIC64 if !64BIT 20 select GENERIC_ATOMIC64 if !64BIT
21 help 21 help
22 The PA-RISC microprocessor is designed by Hewlett-Packard and used 22 The PA-RISC microprocessor is designed by Hewlett-Packard and used
diff --git a/arch/parisc/include/asm/perf_counter.h b/arch/parisc/include/asm/perf_counter.h
deleted file mode 100644
index dc9e829f7013..000000000000
--- a/arch/parisc/include/asm/perf_counter.h
+++ /dev/null
@@ -1,7 +0,0 @@
1#ifndef __ASM_PARISC_PERF_COUNTER_H
2#define __ASM_PARISC_PERF_COUNTER_H
3
4/* parisc only supports software counters through this interface. */
5static inline void set_perf_counter_pending(void) { }
6
7#endif /* __ASM_PARISC_PERF_COUNTER_H */
diff --git a/arch/parisc/include/asm/perf_event.h b/arch/parisc/include/asm/perf_event.h
new file mode 100644
index 000000000000..cc146427d8f9
--- /dev/null
+++ b/arch/parisc/include/asm/perf_event.h
@@ -0,0 +1,7 @@
1#ifndef __ASM_PARISC_PERF_EVENT_H
2#define __ASM_PARISC_PERF_EVENT_H
3
4/* parisc only supports software events through this interface. */
5static inline void set_perf_event_pending(void) { }
6
7#endif /* __ASM_PARISC_PERF_EVENT_H */
diff --git a/arch/parisc/include/asm/unistd.h b/arch/parisc/include/asm/unistd.h
index f3d3b8b012c4..cda158318c62 100644
--- a/arch/parisc/include/asm/unistd.h
+++ b/arch/parisc/include/asm/unistd.h
@@ -810,9 +810,9 @@
810#define __NR_preadv (__NR_Linux + 315) 810#define __NR_preadv (__NR_Linux + 315)
811#define __NR_pwritev (__NR_Linux + 316) 811#define __NR_pwritev (__NR_Linux + 316)
812#define __NR_rt_tgsigqueueinfo (__NR_Linux + 317) 812#define __NR_rt_tgsigqueueinfo (__NR_Linux + 317)
813#define __NR_perf_counter_open (__NR_Linux + 318) 813#define __NR_perf_event_open (__NR_Linux + 318)
814 814
815#define __NR_Linux_syscalls (__NR_perf_counter_open + 1) 815#define __NR_Linux_syscalls (__NR_perf_event_open + 1)
816 816
817 817
818#define __IGNORE_select /* newselect */ 818#define __IGNORE_select /* newselect */
diff --git a/arch/parisc/kernel/syscall_table.S b/arch/parisc/kernel/syscall_table.S
index cf145eb026b3..843f423dec67 100644
--- a/arch/parisc/kernel/syscall_table.S
+++ b/arch/parisc/kernel/syscall_table.S
@@ -416,7 +416,7 @@
416 ENTRY_COMP(preadv) /* 315 */ 416 ENTRY_COMP(preadv) /* 315 */
417 ENTRY_COMP(pwritev) 417 ENTRY_COMP(pwritev)
418 ENTRY_COMP(rt_tgsigqueueinfo) 418 ENTRY_COMP(rt_tgsigqueueinfo)
419 ENTRY_SAME(perf_counter_open) 419 ENTRY_SAME(perf_event_open)
420 420
421 /* Nothing yet */ 421 /* Nothing yet */
422 422
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 8250902265c6..4fd479059d65 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -129,7 +129,7 @@ config PPC
129 select HAVE_OPROFILE 129 select HAVE_OPROFILE
130 select HAVE_SYSCALL_WRAPPERS if PPC64 130 select HAVE_SYSCALL_WRAPPERS if PPC64
131 select GENERIC_ATOMIC64 if PPC32 131 select GENERIC_ATOMIC64 if PPC32
132 select HAVE_PERF_COUNTERS 132 select HAVE_PERF_EVENTS
133 133
134config EARLY_PRINTK 134config EARLY_PRINTK
135 bool 135 bool
diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h
index e73d554538dd..abbc2aaaced5 100644
--- a/arch/powerpc/include/asm/hw_irq.h
+++ b/arch/powerpc/include/asm/hw_irq.h
@@ -135,43 +135,43 @@ static inline int irqs_disabled_flags(unsigned long flags)
135 */ 135 */
136struct irq_chip; 136struct irq_chip;
137 137
138#ifdef CONFIG_PERF_COUNTERS 138#ifdef CONFIG_PERF_EVENTS
139 139
140#ifdef CONFIG_PPC64 140#ifdef CONFIG_PPC64
141static inline unsigned long test_perf_counter_pending(void) 141static inline unsigned long test_perf_event_pending(void)
142{ 142{
143 unsigned long x; 143 unsigned long x;
144 144
145 asm volatile("lbz %0,%1(13)" 145 asm volatile("lbz %0,%1(13)"
146 : "=r" (x) 146 : "=r" (x)
147 : "i" (offsetof(struct paca_struct, perf_counter_pending))); 147 : "i" (offsetof(struct paca_struct, perf_event_pending)));
148 return x; 148 return x;
149} 149}
150 150
151static inline void set_perf_counter_pending(void) 151static inline void set_perf_event_pending(void)
152{ 152{
153 asm volatile("stb %0,%1(13)" : : 153 asm volatile("stb %0,%1(13)" : :
154 "r" (1), 154 "r" (1),
155 "i" (offsetof(struct paca_struct, perf_counter_pending))); 155 "i" (offsetof(struct paca_struct, perf_event_pending)));
156} 156}
157 157
158static inline void clear_perf_counter_pending(void) 158static inline void clear_perf_event_pending(void)
159{ 159{
160 asm volatile("stb %0,%1(13)" : : 160 asm volatile("stb %0,%1(13)" : :
161 "r" (0), 161 "r" (0),
162 "i" (offsetof(struct paca_struct, perf_counter_pending))); 162 "i" (offsetof(struct paca_struct, perf_event_pending)));
163} 163}
164#endif /* CONFIG_PPC64 */ 164#endif /* CONFIG_PPC64 */
165 165
166#else /* CONFIG_PERF_COUNTERS */ 166#else /* CONFIG_PERF_EVENTS */
167 167
168static inline unsigned long test_perf_counter_pending(void) 168static inline unsigned long test_perf_event_pending(void)
169{ 169{
170 return 0; 170 return 0;
171} 171}
172 172
173static inline void clear_perf_counter_pending(void) {} 173static inline void clear_perf_event_pending(void) {}
174#endif /* CONFIG_PERF_COUNTERS */ 174#endif /* CONFIG_PERF_EVENTS */
175 175
176#endif /* __KERNEL__ */ 176#endif /* __KERNEL__ */
177#endif /* _ASM_POWERPC_HW_IRQ_H */ 177#endif /* _ASM_POWERPC_HW_IRQ_H */
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index b634456ea893..154f405b642f 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -122,7 +122,7 @@ struct paca_struct {
122 u8 soft_enabled; /* irq soft-enable flag */ 122 u8 soft_enabled; /* irq soft-enable flag */
123 u8 hard_enabled; /* set if irqs are enabled in MSR */ 123 u8 hard_enabled; /* set if irqs are enabled in MSR */
124 u8 io_sync; /* writel() needs spin_unlock sync */ 124 u8 io_sync; /* writel() needs spin_unlock sync */
125 u8 perf_counter_pending; /* PM interrupt while soft-disabled */ 125 u8 perf_event_pending; /* PM interrupt while soft-disabled */
126 126
127 /* Stuff for accurate time accounting */ 127 /* Stuff for accurate time accounting */
128 u64 user_time; /* accumulated usermode TB ticks */ 128 u64 user_time; /* accumulated usermode TB ticks */
diff --git a/arch/powerpc/include/asm/perf_counter.h b/arch/powerpc/include/asm/perf_event.h
index 0ea0639fcf75..2499aaadaeb9 100644
--- a/arch/powerpc/include/asm/perf_counter.h
+++ b/arch/powerpc/include/asm/perf_event.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Performance counter support - PowerPC-specific definitions. 2 * Performance event support - PowerPC-specific definitions.
3 * 3 *
4 * Copyright 2008-2009 Paul Mackerras, IBM Corporation. 4 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
5 * 5 *
@@ -12,9 +12,9 @@
12 12
13#include <asm/hw_irq.h> 13#include <asm/hw_irq.h>
14 14
15#define MAX_HWCOUNTERS 8 15#define MAX_HWEVENTS 8
16#define MAX_EVENT_ALTERNATIVES 8 16#define MAX_EVENT_ALTERNATIVES 8
17#define MAX_LIMITED_HWCOUNTERS 2 17#define MAX_LIMITED_HWEVENTS 2
18 18
19/* 19/*
20 * This struct provides the constants and functions needed to 20 * This struct provides the constants and functions needed to
@@ -22,18 +22,18 @@
22 */ 22 */
23struct power_pmu { 23struct power_pmu {
24 const char *name; 24 const char *name;
25 int n_counter; 25 int n_event;
26 int max_alternatives; 26 int max_alternatives;
27 unsigned long add_fields; 27 unsigned long add_fields;
28 unsigned long test_adder; 28 unsigned long test_adder;
29 int (*compute_mmcr)(u64 events[], int n_ev, 29 int (*compute_mmcr)(u64 events[], int n_ev,
30 unsigned int hwc[], unsigned long mmcr[]); 30 unsigned int hwc[], unsigned long mmcr[]);
31 int (*get_constraint)(u64 event, unsigned long *mskp, 31 int (*get_constraint)(u64 event_id, unsigned long *mskp,
32 unsigned long *valp); 32 unsigned long *valp);
33 int (*get_alternatives)(u64 event, unsigned int flags, 33 int (*get_alternatives)(u64 event_id, unsigned int flags,
34 u64 alt[]); 34 u64 alt[]);
35 void (*disable_pmc)(unsigned int pmc, unsigned long mmcr[]); 35 void (*disable_pmc)(unsigned int pmc, unsigned long mmcr[]);
36 int (*limited_pmc_event)(u64 event); 36 int (*limited_pmc_event)(u64 event_id);
37 u32 flags; 37 u32 flags;
38 int n_generic; 38 int n_generic;
39 int *generic_events; 39 int *generic_events;
@@ -61,10 +61,10 @@ struct pt_regs;
61extern unsigned long perf_misc_flags(struct pt_regs *regs); 61extern unsigned long perf_misc_flags(struct pt_regs *regs);
62extern unsigned long perf_instruction_pointer(struct pt_regs *regs); 62extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
63 63
64#define PERF_COUNTER_INDEX_OFFSET 1 64#define PERF_EVENT_INDEX_OFFSET 1
65 65
66/* 66/*
67 * Only override the default definitions in include/linux/perf_counter.h 67 * Only override the default definitions in include/linux/perf_event.h
68 * if we have hardware PMU support. 68 * if we have hardware PMU support.
69 */ 69 */
70#ifdef CONFIG_PPC_PERF_CTRS 70#ifdef CONFIG_PPC_PERF_CTRS
@@ -73,14 +73,14 @@ extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
73 73
74/* 74/*
75 * The power_pmu.get_constraint function returns a 32/64-bit value and 75 * The power_pmu.get_constraint function returns a 32/64-bit value and
76 * a 32/64-bit mask that express the constraints between this event and 76 * a 32/64-bit mask that express the constraints between this event_id and
77 * other events. 77 * other events.
78 * 78 *
79 * The value and mask are divided up into (non-overlapping) bitfields 79 * The value and mask are divided up into (non-overlapping) bitfields
80 * of three different types: 80 * of three different types:
81 * 81 *
82 * Select field: this expresses the constraint that some set of bits 82 * Select field: this expresses the constraint that some set of bits
83 * in MMCR* needs to be set to a specific value for this event. For a 83 * in MMCR* needs to be set to a specific value for this event_id. For a
84 * select field, the mask contains 1s in every bit of the field, and 84 * select field, the mask contains 1s in every bit of the field, and
85 * the value contains a unique value for each possible setting of the 85 * the value contains a unique value for each possible setting of the
86 * MMCR* bits. The constraint checking code will ensure that two events 86 * MMCR* bits. The constraint checking code will ensure that two events
@@ -102,9 +102,9 @@ extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
102 * possible.) For N classes, the field is N+1 bits wide, and each class 102 * possible.) For N classes, the field is N+1 bits wide, and each class
103 * is assigned one bit from the least-significant N bits. The mask has 103 * is assigned one bit from the least-significant N bits. The mask has
104 * only the most-significant bit set, and the value has only the bit 104 * only the most-significant bit set, and the value has only the bit
105 * for the event's class set. The test_adder has the least significant 105 * for the event_id's class set. The test_adder has the least significant
106 * bit set in the field. 106 * bit set in the field.
107 * 107 *
108 * If an event is not subject to the constraint expressed by a particular 108 * If an event_id is not subject to the constraint expressed by a particular
109 * field, then it will have 0 in both the mask and value for that field. 109 * field, then it will have 0 in both the mask and value for that field.
110 */ 110 */
diff --git a/arch/powerpc/include/asm/systbl.h b/arch/powerpc/include/asm/systbl.h
index ed24bd92fe49..c7d671a7d9a1 100644
--- a/arch/powerpc/include/asm/systbl.h
+++ b/arch/powerpc/include/asm/systbl.h
@@ -322,7 +322,7 @@ SYSCALL_SPU(epoll_create1)
322SYSCALL_SPU(dup3) 322SYSCALL_SPU(dup3)
323SYSCALL_SPU(pipe2) 323SYSCALL_SPU(pipe2)
324SYSCALL(inotify_init1) 324SYSCALL(inotify_init1)
325SYSCALL_SPU(perf_counter_open) 325SYSCALL_SPU(perf_event_open)
326COMPAT_SYS_SPU(preadv) 326COMPAT_SYS_SPU(preadv)
327COMPAT_SYS_SPU(pwritev) 327COMPAT_SYS_SPU(pwritev)
328COMPAT_SYS(rt_tgsigqueueinfo) 328COMPAT_SYS(rt_tgsigqueueinfo)
diff --git a/arch/powerpc/include/asm/unistd.h b/arch/powerpc/include/asm/unistd.h
index cef080bfc607..f6ca76176766 100644
--- a/arch/powerpc/include/asm/unistd.h
+++ b/arch/powerpc/include/asm/unistd.h
@@ -341,7 +341,7 @@
341#define __NR_dup3 316 341#define __NR_dup3 316
342#define __NR_pipe2 317 342#define __NR_pipe2 317
343#define __NR_inotify_init1 318 343#define __NR_inotify_init1 318
344#define __NR_perf_counter_open 319 344#define __NR_perf_event_open 319
345#define __NR_preadv 320 345#define __NR_preadv 320
346#define __NR_pwritev 321 346#define __NR_pwritev 321
347#define __NR_rt_tgsigqueueinfo 322 347#define __NR_rt_tgsigqueueinfo 322
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 569f79ccd310..b23664a0b86c 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -97,7 +97,7 @@ obj64-$(CONFIG_AUDIT) += compat_audit.o
97 97
98obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o 98obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o
99obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o 99obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o
100obj-$(CONFIG_PPC_PERF_CTRS) += perf_counter.o perf_callchain.o 100obj-$(CONFIG_PPC_PERF_CTRS) += perf_event.o perf_callchain.o
101obj64-$(CONFIG_PPC_PERF_CTRS) += power4-pmu.o ppc970-pmu.o power5-pmu.o \ 101obj64-$(CONFIG_PPC_PERF_CTRS) += power4-pmu.o ppc970-pmu.o power5-pmu.o \
102 power5+-pmu.o power6-pmu.o power7-pmu.o 102 power5+-pmu.o power6-pmu.o power7-pmu.o
103obj32-$(CONFIG_PPC_PERF_CTRS) += mpc7450-pmu.o 103obj32-$(CONFIG_PPC_PERF_CTRS) += mpc7450-pmu.o
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index f0df285f0f87..0812b0f414bb 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -133,7 +133,7 @@ int main(void)
133 DEFINE(PACAKMSR, offsetof(struct paca_struct, kernel_msr)); 133 DEFINE(PACAKMSR, offsetof(struct paca_struct, kernel_msr));
134 DEFINE(PACASOFTIRQEN, offsetof(struct paca_struct, soft_enabled)); 134 DEFINE(PACASOFTIRQEN, offsetof(struct paca_struct, soft_enabled));
135 DEFINE(PACAHARDIRQEN, offsetof(struct paca_struct, hard_enabled)); 135 DEFINE(PACAHARDIRQEN, offsetof(struct paca_struct, hard_enabled));
136 DEFINE(PACAPERFPEND, offsetof(struct paca_struct, perf_counter_pending)); 136 DEFINE(PACAPERFPEND, offsetof(struct paca_struct, perf_event_pending));
137 DEFINE(PACACONTEXTID, offsetof(struct paca_struct, context.id)); 137 DEFINE(PACACONTEXTID, offsetof(struct paca_struct, context.id));
138#ifdef CONFIG_PPC_MM_SLICES 138#ifdef CONFIG_PPC_MM_SLICES
139 DEFINE(PACALOWSLICESPSIZE, offsetof(struct paca_struct, 139 DEFINE(PACALOWSLICESPSIZE, offsetof(struct paca_struct,
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 66bcda34a6bb..900e0eea0099 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -556,14 +556,14 @@ ALT_FW_FTR_SECTION_END_IFCLR(FW_FEATURE_ISERIES)
5562: 5562:
557 TRACE_AND_RESTORE_IRQ(r5); 557 TRACE_AND_RESTORE_IRQ(r5);
558 558
559#ifdef CONFIG_PERF_COUNTERS 559#ifdef CONFIG_PERF_EVENTS
560 /* check paca->perf_counter_pending if we're enabling ints */ 560 /* check paca->perf_event_pending if we're enabling ints */
561 lbz r3,PACAPERFPEND(r13) 561 lbz r3,PACAPERFPEND(r13)
562 and. r3,r3,r5 562 and. r3,r3,r5
563 beq 27f 563 beq 27f
564 bl .perf_counter_do_pending 564 bl .perf_event_do_pending
56527: 56527:
566#endif /* CONFIG_PERF_COUNTERS */ 566#endif /* CONFIG_PERF_EVENTS */
567 567
568 /* extract EE bit and use it to restore paca->hard_enabled */ 568 /* extract EE bit and use it to restore paca->hard_enabled */
569 ld r3,_MSR(r1) 569 ld r3,_MSR(r1)
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index f7f376ea7b17..e5d121177984 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -53,7 +53,7 @@
53#include <linux/bootmem.h> 53#include <linux/bootmem.h>
54#include <linux/pci.h> 54#include <linux/pci.h>
55#include <linux/debugfs.h> 55#include <linux/debugfs.h>
56#include <linux/perf_counter.h> 56#include <linux/perf_event.h>
57 57
58#include <asm/uaccess.h> 58#include <asm/uaccess.h>
59#include <asm/system.h> 59#include <asm/system.h>
@@ -138,9 +138,9 @@ notrace void raw_local_irq_restore(unsigned long en)
138 } 138 }
139#endif /* CONFIG_PPC_STD_MMU_64 */ 139#endif /* CONFIG_PPC_STD_MMU_64 */
140 140
141 if (test_perf_counter_pending()) { 141 if (test_perf_event_pending()) {
142 clear_perf_counter_pending(); 142 clear_perf_event_pending();
143 perf_counter_do_pending(); 143 perf_event_do_pending();
144 } 144 }
145 145
146 /* 146 /*
diff --git a/arch/powerpc/kernel/mpc7450-pmu.c b/arch/powerpc/kernel/mpc7450-pmu.c
index cc466d039af6..09d72028f317 100644
--- a/arch/powerpc/kernel/mpc7450-pmu.c
+++ b/arch/powerpc/kernel/mpc7450-pmu.c
@@ -9,7 +9,7 @@
9 * 2 of the License, or (at your option) any later version. 9 * 2 of the License, or (at your option) any later version.
10 */ 10 */
11#include <linux/string.h> 11#include <linux/string.h>
12#include <linux/perf_counter.h> 12#include <linux/perf_event.h>
13#include <asm/reg.h> 13#include <asm/reg.h>
14#include <asm/cputable.h> 14#include <asm/cputable.h>
15 15
diff --git a/arch/powerpc/kernel/perf_callchain.c b/arch/powerpc/kernel/perf_callchain.c
index f74b62c67511..0a03cf70d247 100644
--- a/arch/powerpc/kernel/perf_callchain.c
+++ b/arch/powerpc/kernel/perf_callchain.c
@@ -10,7 +10,7 @@
10 */ 10 */
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/sched.h> 12#include <linux/sched.h>
13#include <linux/perf_counter.h> 13#include <linux/perf_event.h>
14#include <linux/percpu.h> 14#include <linux/percpu.h>
15#include <linux/uaccess.h> 15#include <linux/uaccess.h>
16#include <linux/mm.h> 16#include <linux/mm.h>
diff --git a/arch/powerpc/kernel/perf_counter.c b/arch/powerpc/kernel/perf_event.c
index 5ccf9bca96c0..c98321fcb459 100644
--- a/arch/powerpc/kernel/perf_counter.c
+++ b/arch/powerpc/kernel/perf_event.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Performance counter support - powerpc architecture code 2 * Performance event support - powerpc architecture code
3 * 3 *
4 * Copyright 2008-2009 Paul Mackerras, IBM Corporation. 4 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
5 * 5 *
@@ -10,7 +10,7 @@
10 */ 10 */
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/sched.h> 12#include <linux/sched.h>
13#include <linux/perf_counter.h> 13#include <linux/perf_event.h>
14#include <linux/percpu.h> 14#include <linux/percpu.h>
15#include <linux/hardirq.h> 15#include <linux/hardirq.h>
16#include <asm/reg.h> 16#include <asm/reg.h>
@@ -19,35 +19,35 @@
19#include <asm/firmware.h> 19#include <asm/firmware.h>
20#include <asm/ptrace.h> 20#include <asm/ptrace.h>
21 21
22struct cpu_hw_counters { 22struct cpu_hw_events {
23 int n_counters; 23 int n_events;
24 int n_percpu; 24 int n_percpu;
25 int disabled; 25 int disabled;
26 int n_added; 26 int n_added;
27 int n_limited; 27 int n_limited;
28 u8 pmcs_enabled; 28 u8 pmcs_enabled;
29 struct perf_counter *counter[MAX_HWCOUNTERS]; 29 struct perf_event *event[MAX_HWEVENTS];
30 u64 events[MAX_HWCOUNTERS]; 30 u64 events[MAX_HWEVENTS];
31 unsigned int flags[MAX_HWCOUNTERS]; 31 unsigned int flags[MAX_HWEVENTS];
32 unsigned long mmcr[3]; 32 unsigned long mmcr[3];
33 struct perf_counter *limited_counter[MAX_LIMITED_HWCOUNTERS]; 33 struct perf_event *limited_event[MAX_LIMITED_HWEVENTS];
34 u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; 34 u8 limited_hwidx[MAX_LIMITED_HWEVENTS];
35 u64 alternatives[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES]; 35 u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
36 unsigned long amasks[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES]; 36 unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
37 unsigned long avalues[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES]; 37 unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
38}; 38};
39DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters); 39DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
40 40
41struct power_pmu *ppmu; 41struct power_pmu *ppmu;
42 42
43/* 43/*
44 * Normally, to ignore kernel events we set the FCS (freeze counters 44 * Normally, to ignore kernel events we set the FCS (freeze events
45 * in supervisor mode) bit in MMCR0, but if the kernel runs with the 45 * in supervisor mode) bit in MMCR0, but if the kernel runs with the
46 * hypervisor bit set in the MSR, or if we are running on a processor 46 * hypervisor bit set in the MSR, or if we are running on a processor
47 * where the hypervisor bit is forced to 1 (as on Apple G5 processors), 47 * where the hypervisor bit is forced to 1 (as on Apple G5 processors),
48 * then we need to use the FCHV bit to ignore kernel events. 48 * then we need to use the FCHV bit to ignore kernel events.
49 */ 49 */
50static unsigned int freeze_counters_kernel = MMCR0_FCS; 50static unsigned int freeze_events_kernel = MMCR0_FCS;
51 51
52/* 52/*
53 * 32-bit doesn't have MMCRA but does have an MMCR2, 53 * 32-bit doesn't have MMCRA but does have an MMCR2,
@@ -122,14 +122,14 @@ static inline u32 perf_get_misc_flags(struct pt_regs *regs)
122 122
123 if (ppmu->flags & PPMU_ALT_SIPR) { 123 if (ppmu->flags & PPMU_ALT_SIPR) {
124 if (mmcra & POWER6_MMCRA_SIHV) 124 if (mmcra & POWER6_MMCRA_SIHV)
125 return PERF_EVENT_MISC_HYPERVISOR; 125 return PERF_RECORD_MISC_HYPERVISOR;
126 return (mmcra & POWER6_MMCRA_SIPR) ? 126 return (mmcra & POWER6_MMCRA_SIPR) ?
127 PERF_EVENT_MISC_USER : PERF_EVENT_MISC_KERNEL; 127 PERF_RECORD_MISC_USER : PERF_RECORD_MISC_KERNEL;
128 } 128 }
129 if (mmcra & MMCRA_SIHV) 129 if (mmcra & MMCRA_SIHV)
130 return PERF_EVENT_MISC_HYPERVISOR; 130 return PERF_RECORD_MISC_HYPERVISOR;
131 return (mmcra & MMCRA_SIPR) ? PERF_EVENT_MISC_USER : 131 return (mmcra & MMCRA_SIPR) ? PERF_RECORD_MISC_USER :
132 PERF_EVENT_MISC_KERNEL; 132 PERF_RECORD_MISC_KERNEL;
133} 133}
134 134
135/* 135/*
@@ -152,14 +152,14 @@ static inline int perf_intr_is_nmi(struct pt_regs *regs)
152 152
153#endif /* CONFIG_PPC64 */ 153#endif /* CONFIG_PPC64 */
154 154
155static void perf_counter_interrupt(struct pt_regs *regs); 155static void perf_event_interrupt(struct pt_regs *regs);
156 156
157void perf_counter_print_debug(void) 157void perf_event_print_debug(void)
158{ 158{
159} 159}
160 160
161/* 161/*
162 * Read one performance monitor counter (PMC). 162 * Read one performance monitor event (PMC).
163 */ 163 */
164static unsigned long read_pmc(int idx) 164static unsigned long read_pmc(int idx)
165{ 165{
@@ -240,31 +240,31 @@ static void write_pmc(int idx, unsigned long val)
240 * Check if a set of events can all go on the PMU at once. 240 * Check if a set of events can all go on the PMU at once.
241 * If they can't, this will look at alternative codes for the events 241 * If they can't, this will look at alternative codes for the events
242 * and see if any combination of alternative codes is feasible. 242 * and see if any combination of alternative codes is feasible.
243 * The feasible set is returned in event[]. 243 * The feasible set is returned in event_id[].
244 */ 244 */
245static int power_check_constraints(struct cpu_hw_counters *cpuhw, 245static int power_check_constraints(struct cpu_hw_events *cpuhw,
246 u64 event[], unsigned int cflags[], 246 u64 event_id[], unsigned int cflags[],
247 int n_ev) 247 int n_ev)
248{ 248{
249 unsigned long mask, value, nv; 249 unsigned long mask, value, nv;
250 unsigned long smasks[MAX_HWCOUNTERS], svalues[MAX_HWCOUNTERS]; 250 unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS];
251 int n_alt[MAX_HWCOUNTERS], choice[MAX_HWCOUNTERS]; 251 int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS];
252 int i, j; 252 int i, j;
253 unsigned long addf = ppmu->add_fields; 253 unsigned long addf = ppmu->add_fields;
254 unsigned long tadd = ppmu->test_adder; 254 unsigned long tadd = ppmu->test_adder;
255 255
256 if (n_ev > ppmu->n_counter) 256 if (n_ev > ppmu->n_event)
257 return -1; 257 return -1;
258 258
259 /* First see if the events will go on as-is */ 259 /* First see if the events will go on as-is */
260 for (i = 0; i < n_ev; ++i) { 260 for (i = 0; i < n_ev; ++i) {
261 if ((cflags[i] & PPMU_LIMITED_PMC_REQD) 261 if ((cflags[i] & PPMU_LIMITED_PMC_REQD)
262 && !ppmu->limited_pmc_event(event[i])) { 262 && !ppmu->limited_pmc_event(event_id[i])) {
263 ppmu->get_alternatives(event[i], cflags[i], 263 ppmu->get_alternatives(event_id[i], cflags[i],
264 cpuhw->alternatives[i]); 264 cpuhw->alternatives[i]);
265 event[i] = cpuhw->alternatives[i][0]; 265 event_id[i] = cpuhw->alternatives[i][0];
266 } 266 }
267 if (ppmu->get_constraint(event[i], &cpuhw->amasks[i][0], 267 if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0],
268 &cpuhw->avalues[i][0])) 268 &cpuhw->avalues[i][0]))
269 return -1; 269 return -1;
270 } 270 }
@@ -287,7 +287,7 @@ static int power_check_constraints(struct cpu_hw_counters *cpuhw,
287 return -1; 287 return -1;
288 for (i = 0; i < n_ev; ++i) { 288 for (i = 0; i < n_ev; ++i) {
289 choice[i] = 0; 289 choice[i] = 0;
290 n_alt[i] = ppmu->get_alternatives(event[i], cflags[i], 290 n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i],
291 cpuhw->alternatives[i]); 291 cpuhw->alternatives[i]);
292 for (j = 1; j < n_alt[i]; ++j) 292 for (j = 1; j < n_alt[i]; ++j)
293 ppmu->get_constraint(cpuhw->alternatives[i][j], 293 ppmu->get_constraint(cpuhw->alternatives[i][j],
@@ -307,7 +307,7 @@ static int power_check_constraints(struct cpu_hw_counters *cpuhw,
307 j = choice[i]; 307 j = choice[i];
308 } 308 }
309 /* 309 /*
310 * See if any alternative k for event i, 310 * See if any alternative k for event_id i,
311 * where k > j, will satisfy the constraints. 311 * where k > j, will satisfy the constraints.
312 */ 312 */
313 while (++j < n_alt[i]) { 313 while (++j < n_alt[i]) {
@@ -321,16 +321,16 @@ static int power_check_constraints(struct cpu_hw_counters *cpuhw,
321 if (j >= n_alt[i]) { 321 if (j >= n_alt[i]) {
322 /* 322 /*
323 * No feasible alternative, backtrack 323 * No feasible alternative, backtrack
324 * to event i-1 and continue enumerating its 324 * to event_id i-1 and continue enumerating its
325 * alternatives from where we got up to. 325 * alternatives from where we got up to.
326 */ 326 */
327 if (--i < 0) 327 if (--i < 0)
328 return -1; 328 return -1;
329 } else { 329 } else {
330 /* 330 /*
331 * Found a feasible alternative for event i, 331 * Found a feasible alternative for event_id i,
332 * remember where we got up to with this event, 332 * remember where we got up to with this event_id,
333 * go on to the next event, and start with 333 * go on to the next event_id, and start with
334 * the first alternative for it. 334 * the first alternative for it.
335 */ 335 */
336 choice[i] = j; 336 choice[i] = j;
@@ -345,21 +345,21 @@ static int power_check_constraints(struct cpu_hw_counters *cpuhw,
345 345
346 /* OK, we have a feasible combination, tell the caller the solution */ 346 /* OK, we have a feasible combination, tell the caller the solution */
347 for (i = 0; i < n_ev; ++i) 347 for (i = 0; i < n_ev; ++i)
348 event[i] = cpuhw->alternatives[i][choice[i]]; 348 event_id[i] = cpuhw->alternatives[i][choice[i]];
349 return 0; 349 return 0;
350} 350}
351 351
352/* 352/*
353 * Check if newly-added counters have consistent settings for 353 * Check if newly-added events have consistent settings for
354 * exclude_{user,kernel,hv} with each other and any previously 354 * exclude_{user,kernel,hv} with each other and any previously
355 * added counters. 355 * added events.
356 */ 356 */
357static int check_excludes(struct perf_counter **ctrs, unsigned int cflags[], 357static int check_excludes(struct perf_event **ctrs, unsigned int cflags[],
358 int n_prev, int n_new) 358 int n_prev, int n_new)
359{ 359{
360 int eu = 0, ek = 0, eh = 0; 360 int eu = 0, ek = 0, eh = 0;
361 int i, n, first; 361 int i, n, first;
362 struct perf_counter *counter; 362 struct perf_event *event;
363 363
364 n = n_prev + n_new; 364 n = n_prev + n_new;
365 if (n <= 1) 365 if (n <= 1)
@@ -371,15 +371,15 @@ static int check_excludes(struct perf_counter **ctrs, unsigned int cflags[],
371 cflags[i] &= ~PPMU_LIMITED_PMC_REQD; 371 cflags[i] &= ~PPMU_LIMITED_PMC_REQD;
372 continue; 372 continue;
373 } 373 }
374 counter = ctrs[i]; 374 event = ctrs[i];
375 if (first) { 375 if (first) {
376 eu = counter->attr.exclude_user; 376 eu = event->attr.exclude_user;
377 ek = counter->attr.exclude_kernel; 377 ek = event->attr.exclude_kernel;
378 eh = counter->attr.exclude_hv; 378 eh = event->attr.exclude_hv;
379 first = 0; 379 first = 0;
380 } else if (counter->attr.exclude_user != eu || 380 } else if (event->attr.exclude_user != eu ||
381 counter->attr.exclude_kernel != ek || 381 event->attr.exclude_kernel != ek ||
382 counter->attr.exclude_hv != eh) { 382 event->attr.exclude_hv != eh) {
383 return -EAGAIN; 383 return -EAGAIN;
384 } 384 }
385 } 385 }
@@ -392,11 +392,11 @@ static int check_excludes(struct perf_counter **ctrs, unsigned int cflags[],
392 return 0; 392 return 0;
393} 393}
394 394
395static void power_pmu_read(struct perf_counter *counter) 395static void power_pmu_read(struct perf_event *event)
396{ 396{
397 s64 val, delta, prev; 397 s64 val, delta, prev;
398 398
399 if (!counter->hw.idx) 399 if (!event->hw.idx)
400 return; 400 return;
401 /* 401 /*
402 * Performance monitor interrupts come even when interrupts 402 * Performance monitor interrupts come even when interrupts
@@ -404,21 +404,21 @@ static void power_pmu_read(struct perf_counter *counter)
404 * Therefore we treat them like NMIs. 404 * Therefore we treat them like NMIs.
405 */ 405 */
406 do { 406 do {
407 prev = atomic64_read(&counter->hw.prev_count); 407 prev = atomic64_read(&event->hw.prev_count);
408 barrier(); 408 barrier();
409 val = read_pmc(counter->hw.idx); 409 val = read_pmc(event->hw.idx);
410 } while (atomic64_cmpxchg(&counter->hw.prev_count, prev, val) != prev); 410 } while (atomic64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
411 411
412 /* The counters are only 32 bits wide */ 412 /* The events are only 32 bits wide */
413 delta = (val - prev) & 0xfffffffful; 413 delta = (val - prev) & 0xfffffffful;
414 atomic64_add(delta, &counter->count); 414 atomic64_add(delta, &event->count);
415 atomic64_sub(delta, &counter->hw.period_left); 415 atomic64_sub(delta, &event->hw.period_left);
416} 416}
417 417
418/* 418/*
419 * On some machines, PMC5 and PMC6 can't be written, don't respect 419 * On some machines, PMC5 and PMC6 can't be written, don't respect
420 * the freeze conditions, and don't generate interrupts. This tells 420 * the freeze conditions, and don't generate interrupts. This tells
421 * us if `counter' is using such a PMC. 421 * us if `event' is using such a PMC.
422 */ 422 */
423static int is_limited_pmc(int pmcnum) 423static int is_limited_pmc(int pmcnum)
424{ 424{
@@ -426,53 +426,53 @@ static int is_limited_pmc(int pmcnum)
426 && (pmcnum == 5 || pmcnum == 6); 426 && (pmcnum == 5 || pmcnum == 6);
427} 427}
428 428
429static void freeze_limited_counters(struct cpu_hw_counters *cpuhw, 429static void freeze_limited_events(struct cpu_hw_events *cpuhw,
430 unsigned long pmc5, unsigned long pmc6) 430 unsigned long pmc5, unsigned long pmc6)
431{ 431{
432 struct perf_counter *counter; 432 struct perf_event *event;
433 u64 val, prev, delta; 433 u64 val, prev, delta;
434 int i; 434 int i;
435 435
436 for (i = 0; i < cpuhw->n_limited; ++i) { 436 for (i = 0; i < cpuhw->n_limited; ++i) {
437 counter = cpuhw->limited_counter[i]; 437 event = cpuhw->limited_event[i];
438 if (!counter->hw.idx) 438 if (!event->hw.idx)
439 continue; 439 continue;
440 val = (counter->hw.idx == 5) ? pmc5 : pmc6; 440 val = (event->hw.idx == 5) ? pmc5 : pmc6;
441 prev = atomic64_read(&counter->hw.prev_count); 441 prev = atomic64_read(&event->hw.prev_count);
442 counter->hw.idx = 0; 442 event->hw.idx = 0;
443 delta = (val - prev) & 0xfffffffful; 443 delta = (val - prev) & 0xfffffffful;
444 atomic64_add(delta, &counter->count); 444 atomic64_add(delta, &event->count);
445 } 445 }
446} 446}
447 447
448static void thaw_limited_counters(struct cpu_hw_counters *cpuhw, 448static void thaw_limited_events(struct cpu_hw_events *cpuhw,
449 unsigned long pmc5, unsigned long pmc6) 449 unsigned long pmc5, unsigned long pmc6)
450{ 450{
451 struct perf_counter *counter; 451 struct perf_event *event;
452 u64 val; 452 u64 val;
453 int i; 453 int i;
454 454
455 for (i = 0; i < cpuhw->n_limited; ++i) { 455 for (i = 0; i < cpuhw->n_limited; ++i) {
456 counter = cpuhw->limited_counter[i]; 456 event = cpuhw->limited_event[i];
457 counter->hw.idx = cpuhw->limited_hwidx[i]; 457 event->hw.idx = cpuhw->limited_hwidx[i];
458 val = (counter->hw.idx == 5) ? pmc5 : pmc6; 458 val = (event->hw.idx == 5) ? pmc5 : pmc6;
459 atomic64_set(&counter->hw.prev_count, val); 459 atomic64_set(&event->hw.prev_count, val);
460 perf_counter_update_userpage(counter); 460 perf_event_update_userpage(event);
461 } 461 }
462} 462}
463 463
464/* 464/*
465 * Since limited counters don't respect the freeze conditions, we 465 * Since limited events don't respect the freeze conditions, we
466 * have to read them immediately after freezing or unfreezing the 466 * have to read them immediately after freezing or unfreezing the
467 * other counters. We try to keep the values from the limited 467 * other events. We try to keep the values from the limited
468 * counters as consistent as possible by keeping the delay (in 468 * events as consistent as possible by keeping the delay (in
469 * cycles and instructions) between freezing/unfreezing and reading 469 * cycles and instructions) between freezing/unfreezing and reading
470 * the limited counters as small and consistent as possible. 470 * the limited events as small and consistent as possible.
471 * Therefore, if any limited counters are in use, we read them 471 * Therefore, if any limited events are in use, we read them
472 * both, and always in the same order, to minimize variability, 472 * both, and always in the same order, to minimize variability,
473 * and do it inside the same asm that writes MMCR0. 473 * and do it inside the same asm that writes MMCR0.
474 */ 474 */
475static void write_mmcr0(struct cpu_hw_counters *cpuhw, unsigned long mmcr0) 475static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0)
476{ 476{
477 unsigned long pmc5, pmc6; 477 unsigned long pmc5, pmc6;
478 478
@@ -485,7 +485,7 @@ static void write_mmcr0(struct cpu_hw_counters *cpuhw, unsigned long mmcr0)
485 * Write MMCR0, then read PMC5 and PMC6 immediately. 485 * Write MMCR0, then read PMC5 and PMC6 immediately.
486 * To ensure we don't get a performance monitor interrupt 486 * To ensure we don't get a performance monitor interrupt
487 * between writing MMCR0 and freezing/thawing the limited 487 * between writing MMCR0 and freezing/thawing the limited
488 * counters, we first write MMCR0 with the counter overflow 488 * events, we first write MMCR0 with the event overflow
489 * interrupt enable bits turned off. 489 * interrupt enable bits turned off.
490 */ 490 */
491 asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5" 491 asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5"
@@ -495,12 +495,12 @@ static void write_mmcr0(struct cpu_hw_counters *cpuhw, unsigned long mmcr0)
495 "i" (SPRN_PMC5), "i" (SPRN_PMC6)); 495 "i" (SPRN_PMC5), "i" (SPRN_PMC6));
496 496
497 if (mmcr0 & MMCR0_FC) 497 if (mmcr0 & MMCR0_FC)
498 freeze_limited_counters(cpuhw, pmc5, pmc6); 498 freeze_limited_events(cpuhw, pmc5, pmc6);
499 else 499 else
500 thaw_limited_counters(cpuhw, pmc5, pmc6); 500 thaw_limited_events(cpuhw, pmc5, pmc6);
501 501
502 /* 502 /*
503 * Write the full MMCR0 including the counter overflow interrupt 503 * Write the full MMCR0 including the event overflow interrupt
504 * enable bits, if necessary. 504 * enable bits, if necessary.
505 */ 505 */
506 if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE)) 506 if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE))
@@ -508,18 +508,18 @@ static void write_mmcr0(struct cpu_hw_counters *cpuhw, unsigned long mmcr0)
508} 508}
509 509
510/* 510/*
511 * Disable all counters to prevent PMU interrupts and to allow 511 * Disable all events to prevent PMU interrupts and to allow
512 * counters to be added or removed. 512 * events to be added or removed.
513 */ 513 */
514void hw_perf_disable(void) 514void hw_perf_disable(void)
515{ 515{
516 struct cpu_hw_counters *cpuhw; 516 struct cpu_hw_events *cpuhw;
517 unsigned long flags; 517 unsigned long flags;
518 518
519 if (!ppmu) 519 if (!ppmu)
520 return; 520 return;
521 local_irq_save(flags); 521 local_irq_save(flags);
522 cpuhw = &__get_cpu_var(cpu_hw_counters); 522 cpuhw = &__get_cpu_var(cpu_hw_events);
523 523
524 if (!cpuhw->disabled) { 524 if (!cpuhw->disabled) {
525 cpuhw->disabled = 1; 525 cpuhw->disabled = 1;
@@ -543,9 +543,9 @@ void hw_perf_disable(void)
543 } 543 }
544 544
545 /* 545 /*
546 * Set the 'freeze counters' bit. 546 * Set the 'freeze events' bit.
547 * The barrier is to make sure the mtspr has been 547 * The barrier is to make sure the mtspr has been
548 * executed and the PMU has frozen the counters 548 * executed and the PMU has frozen the events
549 * before we return. 549 * before we return.
550 */ 550 */
551 write_mmcr0(cpuhw, mfspr(SPRN_MMCR0) | MMCR0_FC); 551 write_mmcr0(cpuhw, mfspr(SPRN_MMCR0) | MMCR0_FC);
@@ -555,26 +555,26 @@ void hw_perf_disable(void)
555} 555}
556 556
557/* 557/*
558 * Re-enable all counters if disable == 0. 558 * Re-enable all events if disable == 0.
559 * If we were previously disabled and counters were added, then 559 * If we were previously disabled and events were added, then
560 * put the new config on the PMU. 560 * put the new config on the PMU.
561 */ 561 */
562void hw_perf_enable(void) 562void hw_perf_enable(void)
563{ 563{
564 struct perf_counter *counter; 564 struct perf_event *event;
565 struct cpu_hw_counters *cpuhw; 565 struct cpu_hw_events *cpuhw;
566 unsigned long flags; 566 unsigned long flags;
567 long i; 567 long i;
568 unsigned long val; 568 unsigned long val;
569 s64 left; 569 s64 left;
570 unsigned int hwc_index[MAX_HWCOUNTERS]; 570 unsigned int hwc_index[MAX_HWEVENTS];
571 int n_lim; 571 int n_lim;
572 int idx; 572 int idx;
573 573
574 if (!ppmu) 574 if (!ppmu)
575 return; 575 return;
576 local_irq_save(flags); 576 local_irq_save(flags);
577 cpuhw = &__get_cpu_var(cpu_hw_counters); 577 cpuhw = &__get_cpu_var(cpu_hw_events);
578 if (!cpuhw->disabled) { 578 if (!cpuhw->disabled) {
579 local_irq_restore(flags); 579 local_irq_restore(flags);
580 return; 580 return;
@@ -582,23 +582,23 @@ void hw_perf_enable(void)
582 cpuhw->disabled = 0; 582 cpuhw->disabled = 0;
583 583
584 /* 584 /*
585 * If we didn't change anything, or only removed counters, 585 * If we didn't change anything, or only removed events,
586 * no need to recalculate MMCR* settings and reset the PMCs. 586 * no need to recalculate MMCR* settings and reset the PMCs.
587 * Just reenable the PMU with the current MMCR* settings 587 * Just reenable the PMU with the current MMCR* settings
588 * (possibly updated for removal of counters). 588 * (possibly updated for removal of events).
589 */ 589 */
590 if (!cpuhw->n_added) { 590 if (!cpuhw->n_added) {
591 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); 591 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
592 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); 592 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
593 if (cpuhw->n_counters == 0) 593 if (cpuhw->n_events == 0)
594 ppc_set_pmu_inuse(0); 594 ppc_set_pmu_inuse(0);
595 goto out_enable; 595 goto out_enable;
596 } 596 }
597 597
598 /* 598 /*
599 * Compute MMCR* values for the new set of counters 599 * Compute MMCR* values for the new set of events
600 */ 600 */
601 if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_counters, hwc_index, 601 if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index,
602 cpuhw->mmcr)) { 602 cpuhw->mmcr)) {
603 /* shouldn't ever get here */ 603 /* shouldn't ever get here */
604 printk(KERN_ERR "oops compute_mmcr failed\n"); 604 printk(KERN_ERR "oops compute_mmcr failed\n");
@@ -607,22 +607,22 @@ void hw_perf_enable(void)
607 607
608 /* 608 /*
609 * Add in MMCR0 freeze bits corresponding to the 609 * Add in MMCR0 freeze bits corresponding to the
610 * attr.exclude_* bits for the first counter. 610 * attr.exclude_* bits for the first event.
611 * We have already checked that all counters have the 611 * We have already checked that all events have the
612 * same values for these bits as the first counter. 612 * same values for these bits as the first event.
613 */ 613 */
614 counter = cpuhw->counter[0]; 614 event = cpuhw->event[0];
615 if (counter->attr.exclude_user) 615 if (event->attr.exclude_user)
616 cpuhw->mmcr[0] |= MMCR0_FCP; 616 cpuhw->mmcr[0] |= MMCR0_FCP;
617 if (counter->attr.exclude_kernel) 617 if (event->attr.exclude_kernel)
618 cpuhw->mmcr[0] |= freeze_counters_kernel; 618 cpuhw->mmcr[0] |= freeze_events_kernel;
619 if (counter->attr.exclude_hv) 619 if (event->attr.exclude_hv)
620 cpuhw->mmcr[0] |= MMCR0_FCHV; 620 cpuhw->mmcr[0] |= MMCR0_FCHV;
621 621
622 /* 622 /*
623 * Write the new configuration to MMCR* with the freeze 623 * Write the new configuration to MMCR* with the freeze
624 * bit set and set the hardware counters to their initial values. 624 * bit set and set the hardware events to their initial values.
625 * Then unfreeze the counters. 625 * Then unfreeze the events.
626 */ 626 */
627 ppc_set_pmu_inuse(1); 627 ppc_set_pmu_inuse(1);
628 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); 628 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
@@ -631,43 +631,43 @@ void hw_perf_enable(void)
631 | MMCR0_FC); 631 | MMCR0_FC);
632 632
633 /* 633 /*
634 * Read off any pre-existing counters that need to move 634 * Read off any pre-existing events that need to move
635 * to another PMC. 635 * to another PMC.
636 */ 636 */
637 for (i = 0; i < cpuhw->n_counters; ++i) { 637 for (i = 0; i < cpuhw->n_events; ++i) {
638 counter = cpuhw->counter[i]; 638 event = cpuhw->event[i];
639 if (counter->hw.idx && counter->hw.idx != hwc_index[i] + 1) { 639 if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) {
640 power_pmu_read(counter); 640 power_pmu_read(event);
641 write_pmc(counter->hw.idx, 0); 641 write_pmc(event->hw.idx, 0);
642 counter->hw.idx = 0; 642 event->hw.idx = 0;
643 } 643 }
644 } 644 }
645 645
646 /* 646 /*
647 * Initialize the PMCs for all the new and moved counters. 647 * Initialize the PMCs for all the new and moved events.
648 */ 648 */
649 cpuhw->n_limited = n_lim = 0; 649 cpuhw->n_limited = n_lim = 0;
650 for (i = 0; i < cpuhw->n_counters; ++i) { 650 for (i = 0; i < cpuhw->n_events; ++i) {
651 counter = cpuhw->counter[i]; 651 event = cpuhw->event[i];
652 if (counter->hw.idx) 652 if (event->hw.idx)
653 continue; 653 continue;
654 idx = hwc_index[i] + 1; 654 idx = hwc_index[i] + 1;
655 if (is_limited_pmc(idx)) { 655 if (is_limited_pmc(idx)) {
656 cpuhw->limited_counter[n_lim] = counter; 656 cpuhw->limited_event[n_lim] = event;
657 cpuhw->limited_hwidx[n_lim] = idx; 657 cpuhw->limited_hwidx[n_lim] = idx;
658 ++n_lim; 658 ++n_lim;
659 continue; 659 continue;
660 } 660 }
661 val = 0; 661 val = 0;
662 if (counter->hw.sample_period) { 662 if (event->hw.sample_period) {
663 left = atomic64_read(&counter->hw.period_left); 663 left = atomic64_read(&event->hw.period_left);
664 if (left < 0x80000000L) 664 if (left < 0x80000000L)
665 val = 0x80000000L - left; 665 val = 0x80000000L - left;
666 } 666 }
667 atomic64_set(&counter->hw.prev_count, val); 667 atomic64_set(&event->hw.prev_count, val);
668 counter->hw.idx = idx; 668 event->hw.idx = idx;
669 write_pmc(idx, val); 669 write_pmc(idx, val);
670 perf_counter_update_userpage(counter); 670 perf_event_update_userpage(event);
671 } 671 }
672 cpuhw->n_limited = n_lim; 672 cpuhw->n_limited = n_lim;
673 cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE; 673 cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE;
@@ -688,85 +688,85 @@ void hw_perf_enable(void)
688 local_irq_restore(flags); 688 local_irq_restore(flags);
689} 689}
690 690
691static int collect_events(struct perf_counter *group, int max_count, 691static int collect_events(struct perf_event *group, int max_count,
692 struct perf_counter *ctrs[], u64 *events, 692 struct perf_event *ctrs[], u64 *events,
693 unsigned int *flags) 693 unsigned int *flags)
694{ 694{
695 int n = 0; 695 int n = 0;
696 struct perf_counter *counter; 696 struct perf_event *event;
697 697
698 if (!is_software_counter(group)) { 698 if (!is_software_event(group)) {
699 if (n >= max_count) 699 if (n >= max_count)
700 return -1; 700 return -1;
701 ctrs[n] = group; 701 ctrs[n] = group;
702 flags[n] = group->hw.counter_base; 702 flags[n] = group->hw.event_base;
703 events[n++] = group->hw.config; 703 events[n++] = group->hw.config;
704 } 704 }
705 list_for_each_entry(counter, &group->sibling_list, list_entry) { 705 list_for_each_entry(event, &group->sibling_list, list_entry) {
706 if (!is_software_counter(counter) && 706 if (!is_software_event(event) &&
707 counter->state != PERF_COUNTER_STATE_OFF) { 707 event->state != PERF_EVENT_STATE_OFF) {
708 if (n >= max_count) 708 if (n >= max_count)
709 return -1; 709 return -1;
710 ctrs[n] = counter; 710 ctrs[n] = event;
711 flags[n] = counter->hw.counter_base; 711 flags[n] = event->hw.event_base;
712 events[n++] = counter->hw.config; 712 events[n++] = event->hw.config;
713 } 713 }
714 } 714 }
715 return n; 715 return n;
716} 716}
717 717
718static void counter_sched_in(struct perf_counter *counter, int cpu) 718static void event_sched_in(struct perf_event *event, int cpu)
719{ 719{
720 counter->state = PERF_COUNTER_STATE_ACTIVE; 720 event->state = PERF_EVENT_STATE_ACTIVE;
721 counter->oncpu = cpu; 721 event->oncpu = cpu;
722 counter->tstamp_running += counter->ctx->time - counter->tstamp_stopped; 722 event->tstamp_running += event->ctx->time - event->tstamp_stopped;
723 if (is_software_counter(counter)) 723 if (is_software_event(event))
724 counter->pmu->enable(counter); 724 event->pmu->enable(event);
725} 725}
726 726
727/* 727/*
728 * Called to enable a whole group of counters. 728 * Called to enable a whole group of events.
729 * Returns 1 if the group was enabled, or -EAGAIN if it could not be. 729 * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
730 * Assumes the caller has disabled interrupts and has 730 * Assumes the caller has disabled interrupts and has
731 * frozen the PMU with hw_perf_save_disable. 731 * frozen the PMU with hw_perf_save_disable.
732 */ 732 */
733int hw_perf_group_sched_in(struct perf_counter *group_leader, 733int hw_perf_group_sched_in(struct perf_event *group_leader,
734 struct perf_cpu_context *cpuctx, 734 struct perf_cpu_context *cpuctx,
735 struct perf_counter_context *ctx, int cpu) 735 struct perf_event_context *ctx, int cpu)
736{ 736{
737 struct cpu_hw_counters *cpuhw; 737 struct cpu_hw_events *cpuhw;
738 long i, n, n0; 738 long i, n, n0;
739 struct perf_counter *sub; 739 struct perf_event *sub;
740 740
741 if (!ppmu) 741 if (!ppmu)
742 return 0; 742 return 0;
743 cpuhw = &__get_cpu_var(cpu_hw_counters); 743 cpuhw = &__get_cpu_var(cpu_hw_events);
744 n0 = cpuhw->n_counters; 744 n0 = cpuhw->n_events;
745 n = collect_events(group_leader, ppmu->n_counter - n0, 745 n = collect_events(group_leader, ppmu->n_event - n0,
746 &cpuhw->counter[n0], &cpuhw->events[n0], 746 &cpuhw->event[n0], &cpuhw->events[n0],
747 &cpuhw->flags[n0]); 747 &cpuhw->flags[n0]);
748 if (n < 0) 748 if (n < 0)
749 return -EAGAIN; 749 return -EAGAIN;
750 if (check_excludes(cpuhw->counter, cpuhw->flags, n0, n)) 750 if (check_excludes(cpuhw->event, cpuhw->flags, n0, n))
751 return -EAGAIN; 751 return -EAGAIN;
752 i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n + n0); 752 i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n + n0);
753 if (i < 0) 753 if (i < 0)
754 return -EAGAIN; 754 return -EAGAIN;
755 cpuhw->n_counters = n0 + n; 755 cpuhw->n_events = n0 + n;
756 cpuhw->n_added += n; 756 cpuhw->n_added += n;
757 757
758 /* 758 /*
759 * OK, this group can go on; update counter states etc., 759 * OK, this group can go on; update event states etc.,
760 * and enable any software counters 760 * and enable any software events
761 */ 761 */
762 for (i = n0; i < n0 + n; ++i) 762 for (i = n0; i < n0 + n; ++i)
763 cpuhw->counter[i]->hw.config = cpuhw->events[i]; 763 cpuhw->event[i]->hw.config = cpuhw->events[i];
764 cpuctx->active_oncpu += n; 764 cpuctx->active_oncpu += n;
765 n = 1; 765 n = 1;
766 counter_sched_in(group_leader, cpu); 766 event_sched_in(group_leader, cpu);
767 list_for_each_entry(sub, &group_leader->sibling_list, list_entry) { 767 list_for_each_entry(sub, &group_leader->sibling_list, list_entry) {
768 if (sub->state != PERF_COUNTER_STATE_OFF) { 768 if (sub->state != PERF_EVENT_STATE_OFF) {
769 counter_sched_in(sub, cpu); 769 event_sched_in(sub, cpu);
770 ++n; 770 ++n;
771 } 771 }
772 } 772 }
@@ -776,14 +776,14 @@ int hw_perf_group_sched_in(struct perf_counter *group_leader,
776} 776}
777 777
778/* 778/*
779 * Add a counter to the PMU. 779 * Add a event to the PMU.
780 * If all counters are not already frozen, then we disable and 780 * If all events are not already frozen, then we disable and
781 * re-enable the PMU in order to get hw_perf_enable to do the 781 * re-enable the PMU in order to get hw_perf_enable to do the
782 * actual work of reconfiguring the PMU. 782 * actual work of reconfiguring the PMU.
783 */ 783 */
784static int power_pmu_enable(struct perf_counter *counter) 784static int power_pmu_enable(struct perf_event *event)
785{ 785{
786 struct cpu_hw_counters *cpuhw; 786 struct cpu_hw_events *cpuhw;
787 unsigned long flags; 787 unsigned long flags;
788 int n0; 788 int n0;
789 int ret = -EAGAIN; 789 int ret = -EAGAIN;
@@ -792,23 +792,23 @@ static int power_pmu_enable(struct perf_counter *counter)
792 perf_disable(); 792 perf_disable();
793 793
794 /* 794 /*
795 * Add the counter to the list (if there is room) 795 * Add the event to the list (if there is room)
796 * and check whether the total set is still feasible. 796 * and check whether the total set is still feasible.
797 */ 797 */
798 cpuhw = &__get_cpu_var(cpu_hw_counters); 798 cpuhw = &__get_cpu_var(cpu_hw_events);
799 n0 = cpuhw->n_counters; 799 n0 = cpuhw->n_events;
800 if (n0 >= ppmu->n_counter) 800 if (n0 >= ppmu->n_event)
801 goto out; 801 goto out;
802 cpuhw->counter[n0] = counter; 802 cpuhw->event[n0] = event;
803 cpuhw->events[n0] = counter->hw.config; 803 cpuhw->events[n0] = event->hw.config;
804 cpuhw->flags[n0] = counter->hw.counter_base; 804 cpuhw->flags[n0] = event->hw.event_base;
805 if (check_excludes(cpuhw->counter, cpuhw->flags, n0, 1)) 805 if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1))
806 goto out; 806 goto out;
807 if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1)) 807 if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1))
808 goto out; 808 goto out;
809 809
810 counter->hw.config = cpuhw->events[n0]; 810 event->hw.config = cpuhw->events[n0];
811 ++cpuhw->n_counters; 811 ++cpuhw->n_events;
812 ++cpuhw->n_added; 812 ++cpuhw->n_added;
813 813
814 ret = 0; 814 ret = 0;
@@ -819,46 +819,46 @@ static int power_pmu_enable(struct perf_counter *counter)
819} 819}
820 820
821/* 821/*
822 * Remove a counter from the PMU. 822 * Remove a event from the PMU.
823 */ 823 */
824static void power_pmu_disable(struct perf_counter *counter) 824static void power_pmu_disable(struct perf_event *event)
825{ 825{
826 struct cpu_hw_counters *cpuhw; 826 struct cpu_hw_events *cpuhw;
827 long i; 827 long i;
828 unsigned long flags; 828 unsigned long flags;
829 829
830 local_irq_save(flags); 830 local_irq_save(flags);
831 perf_disable(); 831 perf_disable();
832 832
833 power_pmu_read(counter); 833 power_pmu_read(event);
834 834
835 cpuhw = &__get_cpu_var(cpu_hw_counters); 835 cpuhw = &__get_cpu_var(cpu_hw_events);
836 for (i = 0; i < cpuhw->n_counters; ++i) { 836 for (i = 0; i < cpuhw->n_events; ++i) {
837 if (counter == cpuhw->counter[i]) { 837 if (event == cpuhw->event[i]) {
838 while (++i < cpuhw->n_counters) 838 while (++i < cpuhw->n_events)
839 cpuhw->counter[i-1] = cpuhw->counter[i]; 839 cpuhw->event[i-1] = cpuhw->event[i];
840 --cpuhw->n_counters; 840 --cpuhw->n_events;
841 ppmu->disable_pmc(counter->hw.idx - 1, cpuhw->mmcr); 841 ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr);
842 if (counter->hw.idx) { 842 if (event->hw.idx) {
843 write_pmc(counter->hw.idx, 0); 843 write_pmc(event->hw.idx, 0);
844 counter->hw.idx = 0; 844 event->hw.idx = 0;
845 } 845 }
846 perf_counter_update_userpage(counter); 846 perf_event_update_userpage(event);
847 break; 847 break;
848 } 848 }
849 } 849 }
850 for (i = 0; i < cpuhw->n_limited; ++i) 850 for (i = 0; i < cpuhw->n_limited; ++i)
851 if (counter == cpuhw->limited_counter[i]) 851 if (event == cpuhw->limited_event[i])
852 break; 852 break;
853 if (i < cpuhw->n_limited) { 853 if (i < cpuhw->n_limited) {
854 while (++i < cpuhw->n_limited) { 854 while (++i < cpuhw->n_limited) {
855 cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i]; 855 cpuhw->limited_event[i-1] = cpuhw->limited_event[i];
856 cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i]; 856 cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i];
857 } 857 }
858 --cpuhw->n_limited; 858 --cpuhw->n_limited;
859 } 859 }
860 if (cpuhw->n_counters == 0) { 860 if (cpuhw->n_events == 0) {
861 /* disable exceptions if no counters are running */ 861 /* disable exceptions if no events are running */
862 cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE); 862 cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE);
863 } 863 }
864 864
@@ -867,28 +867,28 @@ static void power_pmu_disable(struct perf_counter *counter)
867} 867}
868 868
869/* 869/*
870 * Re-enable interrupts on a counter after they were throttled 870 * Re-enable interrupts on a event after they were throttled
871 * because they were coming too fast. 871 * because they were coming too fast.
872 */ 872 */
873static void power_pmu_unthrottle(struct perf_counter *counter) 873static void power_pmu_unthrottle(struct perf_event *event)
874{ 874{
875 s64 val, left; 875 s64 val, left;
876 unsigned long flags; 876 unsigned long flags;
877 877
878 if (!counter->hw.idx || !counter->hw.sample_period) 878 if (!event->hw.idx || !event->hw.sample_period)
879 return; 879 return;
880 local_irq_save(flags); 880 local_irq_save(flags);
881 perf_disable(); 881 perf_disable();
882 power_pmu_read(counter); 882 power_pmu_read(event);
883 left = counter->hw.sample_period; 883 left = event->hw.sample_period;
884 counter->hw.last_period = left; 884 event->hw.last_period = left;
885 val = 0; 885 val = 0;
886 if (left < 0x80000000L) 886 if (left < 0x80000000L)
887 val = 0x80000000L - left; 887 val = 0x80000000L - left;
888 write_pmc(counter->hw.idx, val); 888 write_pmc(event->hw.idx, val);
889 atomic64_set(&counter->hw.prev_count, val); 889 atomic64_set(&event->hw.prev_count, val);
890 atomic64_set(&counter->hw.period_left, left); 890 atomic64_set(&event->hw.period_left, left);
891 perf_counter_update_userpage(counter); 891 perf_event_update_userpage(event);
892 perf_enable(); 892 perf_enable();
893 local_irq_restore(flags); 893 local_irq_restore(flags);
894} 894}
@@ -901,29 +901,29 @@ struct pmu power_pmu = {
901}; 901};
902 902
903/* 903/*
904 * Return 1 if we might be able to put counter on a limited PMC, 904 * Return 1 if we might be able to put event on a limited PMC,
905 * or 0 if not. 905 * or 0 if not.
906 * A counter can only go on a limited PMC if it counts something 906 * A event can only go on a limited PMC if it counts something
907 * that a limited PMC can count, doesn't require interrupts, and 907 * that a limited PMC can count, doesn't require interrupts, and
908 * doesn't exclude any processor mode. 908 * doesn't exclude any processor mode.
909 */ 909 */
910static int can_go_on_limited_pmc(struct perf_counter *counter, u64 ev, 910static int can_go_on_limited_pmc(struct perf_event *event, u64 ev,
911 unsigned int flags) 911 unsigned int flags)
912{ 912{
913 int n; 913 int n;
914 u64 alt[MAX_EVENT_ALTERNATIVES]; 914 u64 alt[MAX_EVENT_ALTERNATIVES];
915 915
916 if (counter->attr.exclude_user 916 if (event->attr.exclude_user
917 || counter->attr.exclude_kernel 917 || event->attr.exclude_kernel
918 || counter->attr.exclude_hv 918 || event->attr.exclude_hv
919 || counter->attr.sample_period) 919 || event->attr.sample_period)
920 return 0; 920 return 0;
921 921
922 if (ppmu->limited_pmc_event(ev)) 922 if (ppmu->limited_pmc_event(ev))
923 return 1; 923 return 1;
924 924
925 /* 925 /*
926 * The requested event isn't on a limited PMC already; 926 * The requested event_id isn't on a limited PMC already;
927 * see if any alternative code goes on a limited PMC. 927 * see if any alternative code goes on a limited PMC.
928 */ 928 */
929 if (!ppmu->get_alternatives) 929 if (!ppmu->get_alternatives)
@@ -936,9 +936,9 @@ static int can_go_on_limited_pmc(struct perf_counter *counter, u64 ev,
936} 936}
937 937
938/* 938/*
939 * Find an alternative event that goes on a normal PMC, if possible, 939 * Find an alternative event_id that goes on a normal PMC, if possible,
940 * and return the event code, or 0 if there is no such alternative. 940 * and return the event_id code, or 0 if there is no such alternative.
941 * (Note: event code 0 is "don't count" on all machines.) 941 * (Note: event_id code 0 is "don't count" on all machines.)
942 */ 942 */
943static u64 normal_pmc_alternative(u64 ev, unsigned long flags) 943static u64 normal_pmc_alternative(u64 ev, unsigned long flags)
944{ 944{
@@ -952,26 +952,26 @@ static u64 normal_pmc_alternative(u64 ev, unsigned long flags)
952 return alt[0]; 952 return alt[0];
953} 953}
954 954
955/* Number of perf_counters counting hardware events */ 955/* Number of perf_events counting hardware events */
956static atomic_t num_counters; 956static atomic_t num_events;
957/* Used to avoid races in calling reserve/release_pmc_hardware */ 957/* Used to avoid races in calling reserve/release_pmc_hardware */
958static DEFINE_MUTEX(pmc_reserve_mutex); 958static DEFINE_MUTEX(pmc_reserve_mutex);
959 959
960/* 960/*
961 * Release the PMU if this is the last perf_counter. 961 * Release the PMU if this is the last perf_event.
962 */ 962 */
963static void hw_perf_counter_destroy(struct perf_counter *counter) 963static void hw_perf_event_destroy(struct perf_event *event)
964{ 964{
965 if (!atomic_add_unless(&num_counters, -1, 1)) { 965 if (!atomic_add_unless(&num_events, -1, 1)) {
966 mutex_lock(&pmc_reserve_mutex); 966 mutex_lock(&pmc_reserve_mutex);
967 if (atomic_dec_return(&num_counters) == 0) 967 if (atomic_dec_return(&num_events) == 0)
968 release_pmc_hardware(); 968 release_pmc_hardware();
969 mutex_unlock(&pmc_reserve_mutex); 969 mutex_unlock(&pmc_reserve_mutex);
970 } 970 }
971} 971}
972 972
973/* 973/*
974 * Translate a generic cache event config to a raw event code. 974 * Translate a generic cache event_id config to a raw event_id code.
975 */ 975 */
976static int hw_perf_cache_event(u64 config, u64 *eventp) 976static int hw_perf_cache_event(u64 config, u64 *eventp)
977{ 977{
@@ -1000,39 +1000,39 @@ static int hw_perf_cache_event(u64 config, u64 *eventp)
1000 return 0; 1000 return 0;
1001} 1001}
1002 1002
1003const struct pmu *hw_perf_counter_init(struct perf_counter *counter) 1003const struct pmu *hw_perf_event_init(struct perf_event *event)
1004{ 1004{
1005 u64 ev; 1005 u64 ev;
1006 unsigned long flags; 1006 unsigned long flags;
1007 struct perf_counter *ctrs[MAX_HWCOUNTERS]; 1007 struct perf_event *ctrs[MAX_HWEVENTS];
1008 u64 events[MAX_HWCOUNTERS]; 1008 u64 events[MAX_HWEVENTS];
1009 unsigned int cflags[MAX_HWCOUNTERS]; 1009 unsigned int cflags[MAX_HWEVENTS];
1010 int n; 1010 int n;
1011 int err; 1011 int err;
1012 struct cpu_hw_counters *cpuhw; 1012 struct cpu_hw_events *cpuhw;
1013 1013
1014 if (!ppmu) 1014 if (!ppmu)
1015 return ERR_PTR(-ENXIO); 1015 return ERR_PTR(-ENXIO);
1016 switch (counter->attr.type) { 1016 switch (event->attr.type) {
1017 case PERF_TYPE_HARDWARE: 1017 case PERF_TYPE_HARDWARE:
1018 ev = counter->attr.config; 1018 ev = event->attr.config;
1019 if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) 1019 if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0)
1020 return ERR_PTR(-EOPNOTSUPP); 1020 return ERR_PTR(-EOPNOTSUPP);
1021 ev = ppmu->generic_events[ev]; 1021 ev = ppmu->generic_events[ev];
1022 break; 1022 break;
1023 case PERF_TYPE_HW_CACHE: 1023 case PERF_TYPE_HW_CACHE:
1024 err = hw_perf_cache_event(counter->attr.config, &ev); 1024 err = hw_perf_cache_event(event->attr.config, &ev);
1025 if (err) 1025 if (err)
1026 return ERR_PTR(err); 1026 return ERR_PTR(err);
1027 break; 1027 break;
1028 case PERF_TYPE_RAW: 1028 case PERF_TYPE_RAW:
1029 ev = counter->attr.config; 1029 ev = event->attr.config;
1030 break; 1030 break;
1031 default: 1031 default:
1032 return ERR_PTR(-EINVAL); 1032 return ERR_PTR(-EINVAL);
1033 } 1033 }
1034 counter->hw.config_base = ev; 1034 event->hw.config_base = ev;
1035 counter->hw.idx = 0; 1035 event->hw.idx = 0;
1036 1036
1037 /* 1037 /*
1038 * If we are not running on a hypervisor, force the 1038 * If we are not running on a hypervisor, force the
@@ -1040,28 +1040,28 @@ const struct pmu *hw_perf_counter_init(struct perf_counter *counter)
1040 * the user set it to. 1040 * the user set it to.
1041 */ 1041 */
1042 if (!firmware_has_feature(FW_FEATURE_LPAR)) 1042 if (!firmware_has_feature(FW_FEATURE_LPAR))
1043 counter->attr.exclude_hv = 0; 1043 event->attr.exclude_hv = 0;
1044 1044
1045 /* 1045 /*
1046 * If this is a per-task counter, then we can use 1046 * If this is a per-task event, then we can use
1047 * PM_RUN_* events interchangeably with their non RUN_* 1047 * PM_RUN_* events interchangeably with their non RUN_*
1048 * equivalents, e.g. PM_RUN_CYC instead of PM_CYC. 1048 * equivalents, e.g. PM_RUN_CYC instead of PM_CYC.
1049 * XXX we should check if the task is an idle task. 1049 * XXX we should check if the task is an idle task.
1050 */ 1050 */
1051 flags = 0; 1051 flags = 0;
1052 if (counter->ctx->task) 1052 if (event->ctx->task)
1053 flags |= PPMU_ONLY_COUNT_RUN; 1053 flags |= PPMU_ONLY_COUNT_RUN;
1054 1054
1055 /* 1055 /*
1056 * If this machine has limited counters, check whether this 1056 * If this machine has limited events, check whether this
1057 * event could go on a limited counter. 1057 * event_id could go on a limited event.
1058 */ 1058 */
1059 if (ppmu->flags & PPMU_LIMITED_PMC5_6) { 1059 if (ppmu->flags & PPMU_LIMITED_PMC5_6) {
1060 if (can_go_on_limited_pmc(counter, ev, flags)) { 1060 if (can_go_on_limited_pmc(event, ev, flags)) {
1061 flags |= PPMU_LIMITED_PMC_OK; 1061 flags |= PPMU_LIMITED_PMC_OK;
1062 } else if (ppmu->limited_pmc_event(ev)) { 1062 } else if (ppmu->limited_pmc_event(ev)) {
1063 /* 1063 /*
1064 * The requested event is on a limited PMC, 1064 * The requested event_id is on a limited PMC,
1065 * but we can't use a limited PMC; see if any 1065 * but we can't use a limited PMC; see if any
1066 * alternative goes on a normal PMC. 1066 * alternative goes on a normal PMC.
1067 */ 1067 */
@@ -1073,50 +1073,50 @@ const struct pmu *hw_perf_counter_init(struct perf_counter *counter)
1073 1073
1074 /* 1074 /*
1075 * If this is in a group, check if it can go on with all the 1075 * If this is in a group, check if it can go on with all the
1076 * other hardware counters in the group. We assume the counter 1076 * other hardware events in the group. We assume the event
1077 * hasn't been linked into its leader's sibling list at this point. 1077 * hasn't been linked into its leader's sibling list at this point.
1078 */ 1078 */
1079 n = 0; 1079 n = 0;
1080 if (counter->group_leader != counter) { 1080 if (event->group_leader != event) {
1081 n = collect_events(counter->group_leader, ppmu->n_counter - 1, 1081 n = collect_events(event->group_leader, ppmu->n_event - 1,
1082 ctrs, events, cflags); 1082 ctrs, events, cflags);
1083 if (n < 0) 1083 if (n < 0)
1084 return ERR_PTR(-EINVAL); 1084 return ERR_PTR(-EINVAL);
1085 } 1085 }
1086 events[n] = ev; 1086 events[n] = ev;
1087 ctrs[n] = counter; 1087 ctrs[n] = event;
1088 cflags[n] = flags; 1088 cflags[n] = flags;
1089 if (check_excludes(ctrs, cflags, n, 1)) 1089 if (check_excludes(ctrs, cflags, n, 1))
1090 return ERR_PTR(-EINVAL); 1090 return ERR_PTR(-EINVAL);
1091 1091
1092 cpuhw = &get_cpu_var(cpu_hw_counters); 1092 cpuhw = &get_cpu_var(cpu_hw_events);
1093 err = power_check_constraints(cpuhw, events, cflags, n + 1); 1093 err = power_check_constraints(cpuhw, events, cflags, n + 1);
1094 put_cpu_var(cpu_hw_counters); 1094 put_cpu_var(cpu_hw_events);
1095 if (err) 1095 if (err)
1096 return ERR_PTR(-EINVAL); 1096 return ERR_PTR(-EINVAL);
1097 1097
1098 counter->hw.config = events[n]; 1098 event->hw.config = events[n];
1099 counter->hw.counter_base = cflags[n]; 1099 event->hw.event_base = cflags[n];
1100 counter->hw.last_period = counter->hw.sample_period; 1100 event->hw.last_period = event->hw.sample_period;
1101 atomic64_set(&counter->hw.period_left, counter->hw.last_period); 1101 atomic64_set(&event->hw.period_left, event->hw.last_period);
1102 1102
1103 /* 1103 /*
1104 * See if we need to reserve the PMU. 1104 * See if we need to reserve the PMU.
1105 * If no counters are currently in use, then we have to take a 1105 * If no events are currently in use, then we have to take a
1106 * mutex to ensure that we don't race with another task doing 1106 * mutex to ensure that we don't race with another task doing
1107 * reserve_pmc_hardware or release_pmc_hardware. 1107 * reserve_pmc_hardware or release_pmc_hardware.
1108 */ 1108 */
1109 err = 0; 1109 err = 0;
1110 if (!atomic_inc_not_zero(&num_counters)) { 1110 if (!atomic_inc_not_zero(&num_events)) {
1111 mutex_lock(&pmc_reserve_mutex); 1111 mutex_lock(&pmc_reserve_mutex);
1112 if (atomic_read(&num_counters) == 0 && 1112 if (atomic_read(&num_events) == 0 &&
1113 reserve_pmc_hardware(perf_counter_interrupt)) 1113 reserve_pmc_hardware(perf_event_interrupt))
1114 err = -EBUSY; 1114 err = -EBUSY;
1115 else 1115 else
1116 atomic_inc(&num_counters); 1116 atomic_inc(&num_events);
1117 mutex_unlock(&pmc_reserve_mutex); 1117 mutex_unlock(&pmc_reserve_mutex);
1118 } 1118 }
1119 counter->destroy = hw_perf_counter_destroy; 1119 event->destroy = hw_perf_event_destroy;
1120 1120
1121 if (err) 1121 if (err)
1122 return ERR_PTR(err); 1122 return ERR_PTR(err);
@@ -1124,28 +1124,28 @@ const struct pmu *hw_perf_counter_init(struct perf_counter *counter)
1124} 1124}
1125 1125
1126/* 1126/*
1127 * A counter has overflowed; update its count and record 1127 * A event has overflowed; update its count and record
1128 * things if requested. Note that interrupts are hard-disabled 1128 * things if requested. Note that interrupts are hard-disabled
1129 * here so there is no possibility of being interrupted. 1129 * here so there is no possibility of being interrupted.
1130 */ 1130 */
1131static void record_and_restart(struct perf_counter *counter, unsigned long val, 1131static void record_and_restart(struct perf_event *event, unsigned long val,
1132 struct pt_regs *regs, int nmi) 1132 struct pt_regs *regs, int nmi)
1133{ 1133{
1134 u64 period = counter->hw.sample_period; 1134 u64 period = event->hw.sample_period;
1135 s64 prev, delta, left; 1135 s64 prev, delta, left;
1136 int record = 0; 1136 int record = 0;
1137 1137
1138 /* we don't have to worry about interrupts here */ 1138 /* we don't have to worry about interrupts here */
1139 prev = atomic64_read(&counter->hw.prev_count); 1139 prev = atomic64_read(&event->hw.prev_count);
1140 delta = (val - prev) & 0xfffffffful; 1140 delta = (val - prev) & 0xfffffffful;
1141 atomic64_add(delta, &counter->count); 1141 atomic64_add(delta, &event->count);
1142 1142
1143 /* 1143 /*
1144 * See if the total period for this counter has expired, 1144 * See if the total period for this event has expired,
1145 * and update for the next period. 1145 * and update for the next period.
1146 */ 1146 */
1147 val = 0; 1147 val = 0;
1148 left = atomic64_read(&counter->hw.period_left) - delta; 1148 left = atomic64_read(&event->hw.period_left) - delta;
1149 if (period) { 1149 if (period) {
1150 if (left <= 0) { 1150 if (left <= 0) {
1151 left += period; 1151 left += period;
@@ -1163,18 +1163,18 @@ static void record_and_restart(struct perf_counter *counter, unsigned long val,
1163 if (record) { 1163 if (record) {
1164 struct perf_sample_data data = { 1164 struct perf_sample_data data = {
1165 .addr = 0, 1165 .addr = 0,
1166 .period = counter->hw.last_period, 1166 .period = event->hw.last_period,
1167 }; 1167 };
1168 1168
1169 if (counter->attr.sample_type & PERF_SAMPLE_ADDR) 1169 if (event->attr.sample_type & PERF_SAMPLE_ADDR)
1170 perf_get_data_addr(regs, &data.addr); 1170 perf_get_data_addr(regs, &data.addr);
1171 1171
1172 if (perf_counter_overflow(counter, nmi, &data, regs)) { 1172 if (perf_event_overflow(event, nmi, &data, regs)) {
1173 /* 1173 /*
1174 * Interrupts are coming too fast - throttle them 1174 * Interrupts are coming too fast - throttle them
1175 * by setting the counter to 0, so it will be 1175 * by setting the event to 0, so it will be
1176 * at least 2^30 cycles until the next interrupt 1176 * at least 2^30 cycles until the next interrupt
1177 * (assuming each counter counts at most 2 counts 1177 * (assuming each event counts at most 2 counts
1178 * per cycle). 1178 * per cycle).
1179 */ 1179 */
1180 val = 0; 1180 val = 0;
@@ -1182,15 +1182,15 @@ static void record_and_restart(struct perf_counter *counter, unsigned long val,
1182 } 1182 }
1183 } 1183 }
1184 1184
1185 write_pmc(counter->hw.idx, val); 1185 write_pmc(event->hw.idx, val);
1186 atomic64_set(&counter->hw.prev_count, val); 1186 atomic64_set(&event->hw.prev_count, val);
1187 atomic64_set(&counter->hw.period_left, left); 1187 atomic64_set(&event->hw.period_left, left);
1188 perf_counter_update_userpage(counter); 1188 perf_event_update_userpage(event);
1189} 1189}
1190 1190
1191/* 1191/*
1192 * Called from generic code to get the misc flags (i.e. processor mode) 1192 * Called from generic code to get the misc flags (i.e. processor mode)
1193 * for an event. 1193 * for an event_id.
1194 */ 1194 */
1195unsigned long perf_misc_flags(struct pt_regs *regs) 1195unsigned long perf_misc_flags(struct pt_regs *regs)
1196{ 1196{
@@ -1198,13 +1198,13 @@ unsigned long perf_misc_flags(struct pt_regs *regs)
1198 1198
1199 if (flags) 1199 if (flags)
1200 return flags; 1200 return flags;
1201 return user_mode(regs) ? PERF_EVENT_MISC_USER : 1201 return user_mode(regs) ? PERF_RECORD_MISC_USER :
1202 PERF_EVENT_MISC_KERNEL; 1202 PERF_RECORD_MISC_KERNEL;
1203} 1203}
1204 1204
1205/* 1205/*
1206 * Called from generic code to get the instruction pointer 1206 * Called from generic code to get the instruction pointer
1207 * for an event. 1207 * for an event_id.
1208 */ 1208 */
1209unsigned long perf_instruction_pointer(struct pt_regs *regs) 1209unsigned long perf_instruction_pointer(struct pt_regs *regs)
1210{ 1210{
@@ -1220,17 +1220,17 @@ unsigned long perf_instruction_pointer(struct pt_regs *regs)
1220/* 1220/*
1221 * Performance monitor interrupt stuff 1221 * Performance monitor interrupt stuff
1222 */ 1222 */
1223static void perf_counter_interrupt(struct pt_regs *regs) 1223static void perf_event_interrupt(struct pt_regs *regs)
1224{ 1224{
1225 int i; 1225 int i;
1226 struct cpu_hw_counters *cpuhw = &__get_cpu_var(cpu_hw_counters); 1226 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
1227 struct perf_counter *counter; 1227 struct perf_event *event;
1228 unsigned long val; 1228 unsigned long val;
1229 int found = 0; 1229 int found = 0;
1230 int nmi; 1230 int nmi;
1231 1231
1232 if (cpuhw->n_limited) 1232 if (cpuhw->n_limited)
1233 freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5), 1233 freeze_limited_events(cpuhw, mfspr(SPRN_PMC5),
1234 mfspr(SPRN_PMC6)); 1234 mfspr(SPRN_PMC6));
1235 1235
1236 perf_read_regs(regs); 1236 perf_read_regs(regs);
@@ -1241,26 +1241,26 @@ static void perf_counter_interrupt(struct pt_regs *regs)
1241 else 1241 else
1242 irq_enter(); 1242 irq_enter();
1243 1243
1244 for (i = 0; i < cpuhw->n_counters; ++i) { 1244 for (i = 0; i < cpuhw->n_events; ++i) {
1245 counter = cpuhw->counter[i]; 1245 event = cpuhw->event[i];
1246 if (!counter->hw.idx || is_limited_pmc(counter->hw.idx)) 1246 if (!event->hw.idx || is_limited_pmc(event->hw.idx))
1247 continue; 1247 continue;
1248 val = read_pmc(counter->hw.idx); 1248 val = read_pmc(event->hw.idx);
1249 if ((int)val < 0) { 1249 if ((int)val < 0) {
1250 /* counter has overflowed */ 1250 /* event has overflowed */
1251 found = 1; 1251 found = 1;
1252 record_and_restart(counter, val, regs, nmi); 1252 record_and_restart(event, val, regs, nmi);
1253 } 1253 }
1254 } 1254 }
1255 1255
1256 /* 1256 /*
1257 * In case we didn't find and reset the counter that caused 1257 * In case we didn't find and reset the event that caused
1258 * the interrupt, scan all counters and reset any that are 1258 * the interrupt, scan all events and reset any that are
1259 * negative, to avoid getting continual interrupts. 1259 * negative, to avoid getting continual interrupts.
1260 * Any that we processed in the previous loop will not be negative. 1260 * Any that we processed in the previous loop will not be negative.
1261 */ 1261 */
1262 if (!found) { 1262 if (!found) {
1263 for (i = 0; i < ppmu->n_counter; ++i) { 1263 for (i = 0; i < ppmu->n_event; ++i) {
1264 if (is_limited_pmc(i + 1)) 1264 if (is_limited_pmc(i + 1))
1265 continue; 1265 continue;
1266 val = read_pmc(i + 1); 1266 val = read_pmc(i + 1);
@@ -1271,9 +1271,9 @@ static void perf_counter_interrupt(struct pt_regs *regs)
1271 1271
1272 /* 1272 /*
1273 * Reset MMCR0 to its normal value. This will set PMXE and 1273 * Reset MMCR0 to its normal value. This will set PMXE and
1274 * clear FC (freeze counters) and PMAO (perf mon alert occurred) 1274 * clear FC (freeze events) and PMAO (perf mon alert occurred)
1275 * and thus allow interrupts to occur again. 1275 * and thus allow interrupts to occur again.
1276 * XXX might want to use MSR.PM to keep the counters frozen until 1276 * XXX might want to use MSR.PM to keep the events frozen until
1277 * we get back out of this interrupt. 1277 * we get back out of this interrupt.
1278 */ 1278 */
1279 write_mmcr0(cpuhw, cpuhw->mmcr[0]); 1279 write_mmcr0(cpuhw, cpuhw->mmcr[0]);
@@ -1284,9 +1284,9 @@ static void perf_counter_interrupt(struct pt_regs *regs)
1284 irq_exit(); 1284 irq_exit();
1285} 1285}
1286 1286
1287void hw_perf_counter_setup(int cpu) 1287void hw_perf_event_setup(int cpu)
1288{ 1288{
1289 struct cpu_hw_counters *cpuhw = &per_cpu(cpu_hw_counters, cpu); 1289 struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
1290 1290
1291 if (!ppmu) 1291 if (!ppmu)
1292 return; 1292 return;
@@ -1308,7 +1308,7 @@ int register_power_pmu(struct power_pmu *pmu)
1308 * Use FCHV to ignore kernel events if MSR.HV is set. 1308 * Use FCHV to ignore kernel events if MSR.HV is set.
1309 */ 1309 */
1310 if (mfmsr() & MSR_HV) 1310 if (mfmsr() & MSR_HV)
1311 freeze_counters_kernel = MMCR0_FCHV; 1311 freeze_events_kernel = MMCR0_FCHV;
1312#endif /* CONFIG_PPC64 */ 1312#endif /* CONFIG_PPC64 */
1313 1313
1314 return 0; 1314 return 0;
diff --git a/arch/powerpc/kernel/power4-pmu.c b/arch/powerpc/kernel/power4-pmu.c
index 3c90a3d9173e..2a361cdda635 100644
--- a/arch/powerpc/kernel/power4-pmu.c
+++ b/arch/powerpc/kernel/power4-pmu.c
@@ -9,7 +9,7 @@
9 * 2 of the License, or (at your option) any later version. 9 * 2 of the License, or (at your option) any later version.
10 */ 10 */
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/perf_counter.h> 12#include <linux/perf_event.h>
13#include <linux/string.h> 13#include <linux/string.h>
14#include <asm/reg.h> 14#include <asm/reg.h>
15#include <asm/cputable.h> 15#include <asm/cputable.h>
diff --git a/arch/powerpc/kernel/power5+-pmu.c b/arch/powerpc/kernel/power5+-pmu.c
index 31918af3e355..0f4c1c73a6ad 100644
--- a/arch/powerpc/kernel/power5+-pmu.c
+++ b/arch/powerpc/kernel/power5+-pmu.c
@@ -9,7 +9,7 @@
9 * 2 of the License, or (at your option) any later version. 9 * 2 of the License, or (at your option) any later version.
10 */ 10 */
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/perf_counter.h> 12#include <linux/perf_event.h>
13#include <linux/string.h> 13#include <linux/string.h>
14#include <asm/reg.h> 14#include <asm/reg.h>
15#include <asm/cputable.h> 15#include <asm/cputable.h>
diff --git a/arch/powerpc/kernel/power5-pmu.c b/arch/powerpc/kernel/power5-pmu.c
index 867f6f663963..c351b3a57fbb 100644
--- a/arch/powerpc/kernel/power5-pmu.c
+++ b/arch/powerpc/kernel/power5-pmu.c
@@ -9,7 +9,7 @@
9 * 2 of the License, or (at your option) any later version. 9 * 2 of the License, or (at your option) any later version.
10 */ 10 */
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/perf_counter.h> 12#include <linux/perf_event.h>
13#include <linux/string.h> 13#include <linux/string.h>
14#include <asm/reg.h> 14#include <asm/reg.h>
15#include <asm/cputable.h> 15#include <asm/cputable.h>
diff --git a/arch/powerpc/kernel/power6-pmu.c b/arch/powerpc/kernel/power6-pmu.c
index fa21890531da..ca399ba5034c 100644
--- a/arch/powerpc/kernel/power6-pmu.c
+++ b/arch/powerpc/kernel/power6-pmu.c
@@ -9,7 +9,7 @@
9 * 2 of the License, or (at your option) any later version. 9 * 2 of the License, or (at your option) any later version.
10 */ 10 */
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/perf_counter.h> 12#include <linux/perf_event.h>
13#include <linux/string.h> 13#include <linux/string.h>
14#include <asm/reg.h> 14#include <asm/reg.h>
15#include <asm/cputable.h> 15#include <asm/cputable.h>
diff --git a/arch/powerpc/kernel/power7-pmu.c b/arch/powerpc/kernel/power7-pmu.c
index 018d094d92f9..28a4daacdc02 100644
--- a/arch/powerpc/kernel/power7-pmu.c
+++ b/arch/powerpc/kernel/power7-pmu.c
@@ -9,7 +9,7 @@
9 * 2 of the License, or (at your option) any later version. 9 * 2 of the License, or (at your option) any later version.
10 */ 10 */
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/perf_counter.h> 12#include <linux/perf_event.h>
13#include <linux/string.h> 13#include <linux/string.h>
14#include <asm/reg.h> 14#include <asm/reg.h>
15#include <asm/cputable.h> 15#include <asm/cputable.h>
diff --git a/arch/powerpc/kernel/ppc970-pmu.c b/arch/powerpc/kernel/ppc970-pmu.c
index 75dccb71a043..479574413a93 100644
--- a/arch/powerpc/kernel/ppc970-pmu.c
+++ b/arch/powerpc/kernel/ppc970-pmu.c
@@ -9,7 +9,7 @@
9 * 2 of the License, or (at your option) any later version. 9 * 2 of the License, or (at your option) any later version.
10 */ 10 */
11#include <linux/string.h> 11#include <linux/string.h>
12#include <linux/perf_counter.h> 12#include <linux/perf_event.h>
13#include <asm/reg.h> 13#include <asm/reg.h>
14#include <asm/cputable.h> 14#include <asm/cputable.h>
15 15
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index 465e498bcb33..df45a7449a66 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -53,7 +53,7 @@
53#include <linux/posix-timers.h> 53#include <linux/posix-timers.h>
54#include <linux/irq.h> 54#include <linux/irq.h>
55#include <linux/delay.h> 55#include <linux/delay.h>
56#include <linux/perf_counter.h> 56#include <linux/perf_event.h>
57 57
58#include <asm/io.h> 58#include <asm/io.h>
59#include <asm/processor.h> 59#include <asm/processor.h>
@@ -527,25 +527,25 @@ void __init iSeries_time_init_early(void)
527} 527}
528#endif /* CONFIG_PPC_ISERIES */ 528#endif /* CONFIG_PPC_ISERIES */
529 529
530#if defined(CONFIG_PERF_COUNTERS) && defined(CONFIG_PPC32) 530#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_PPC32)
531DEFINE_PER_CPU(u8, perf_counter_pending); 531DEFINE_PER_CPU(u8, perf_event_pending);
532 532
533void set_perf_counter_pending(void) 533void set_perf_event_pending(void)
534{ 534{
535 get_cpu_var(perf_counter_pending) = 1; 535 get_cpu_var(perf_event_pending) = 1;
536 set_dec(1); 536 set_dec(1);
537 put_cpu_var(perf_counter_pending); 537 put_cpu_var(perf_event_pending);
538} 538}
539 539
540#define test_perf_counter_pending() __get_cpu_var(perf_counter_pending) 540#define test_perf_event_pending() __get_cpu_var(perf_event_pending)
541#define clear_perf_counter_pending() __get_cpu_var(perf_counter_pending) = 0 541#define clear_perf_event_pending() __get_cpu_var(perf_event_pending) = 0
542 542
543#else /* CONFIG_PERF_COUNTERS && CONFIG_PPC32 */ 543#else /* CONFIG_PERF_EVENTS && CONFIG_PPC32 */
544 544
545#define test_perf_counter_pending() 0 545#define test_perf_event_pending() 0
546#define clear_perf_counter_pending() 546#define clear_perf_event_pending()
547 547
548#endif /* CONFIG_PERF_COUNTERS && CONFIG_PPC32 */ 548#endif /* CONFIG_PERF_EVENTS && CONFIG_PPC32 */
549 549
550/* 550/*
551 * For iSeries shared processors, we have to let the hypervisor 551 * For iSeries shared processors, we have to let the hypervisor
@@ -573,9 +573,9 @@ void timer_interrupt(struct pt_regs * regs)
573 set_dec(DECREMENTER_MAX); 573 set_dec(DECREMENTER_MAX);
574 574
575#ifdef CONFIG_PPC32 575#ifdef CONFIG_PPC32
576 if (test_perf_counter_pending()) { 576 if (test_perf_event_pending()) {
577 clear_perf_counter_pending(); 577 clear_perf_event_pending();
578 perf_counter_do_pending(); 578 perf_event_do_pending();
579 } 579 }
580 if (atomic_read(&ppc_n_lost_interrupts) != 0) 580 if (atomic_read(&ppc_n_lost_interrupts) != 0)
581 do_IRQ(regs); 581 do_IRQ(regs);
diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index 830bef0a1131..e7dae82c1285 100644
--- a/arch/powerpc/mm/fault.c
+++ b/arch/powerpc/mm/fault.c
@@ -29,7 +29,7 @@
29#include <linux/module.h> 29#include <linux/module.h>
30#include <linux/kprobes.h> 30#include <linux/kprobes.h>
31#include <linux/kdebug.h> 31#include <linux/kdebug.h>
32#include <linux/perf_counter.h> 32#include <linux/perf_event.h>
33 33
34#include <asm/firmware.h> 34#include <asm/firmware.h>
35#include <asm/page.h> 35#include <asm/page.h>
@@ -171,7 +171,7 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned long address,
171 die("Weird page fault", regs, SIGSEGV); 171 die("Weird page fault", regs, SIGSEGV);
172 } 172 }
173 173
174 perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address); 174 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address);
175 175
176 /* When running in the kernel we expect faults to occur only to 176 /* When running in the kernel we expect faults to occur only to
177 * addresses in user space. All other faults represent errors in the 177 * addresses in user space. All other faults represent errors in the
@@ -312,7 +312,7 @@ good_area:
312 } 312 }
313 if (ret & VM_FAULT_MAJOR) { 313 if (ret & VM_FAULT_MAJOR) {
314 current->maj_flt++; 314 current->maj_flt++;
315 perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0, 315 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0,
316 regs, address); 316 regs, address);
317#ifdef CONFIG_PPC_SMLPAR 317#ifdef CONFIG_PPC_SMLPAR
318 if (firmware_has_feature(FW_FEATURE_CMO)) { 318 if (firmware_has_feature(FW_FEATURE_CMO)) {
@@ -323,7 +323,7 @@ good_area:
323#endif 323#endif
324 } else { 324 } else {
325 current->min_flt++; 325 current->min_flt++;
326 perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0, 326 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0,
327 regs, address); 327 regs, address);
328 } 328 }
329 up_read(&mm->mmap_sem); 329 up_read(&mm->mmap_sem);
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index 9efc8bda01b4..e382cae678b8 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -280,9 +280,9 @@ config PPC_HAVE_PMU_SUPPORT
280 280
281config PPC_PERF_CTRS 281config PPC_PERF_CTRS
282 def_bool y 282 def_bool y
283 depends on PERF_COUNTERS && PPC_HAVE_PMU_SUPPORT 283 depends on PERF_EVENTS && PPC_HAVE_PMU_SUPPORT
284 help 284 help
285 This enables the powerpc-specific perf_counter back-end. 285 This enables the powerpc-specific perf_event back-end.
286 286
287config SMP 287config SMP
288 depends on PPC_BOOK3S || PPC_BOOK3E || FSL_BOOKE 288 depends on PPC_BOOK3S || PPC_BOOK3E || FSL_BOOKE
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index 1c866efd217d..43c0acad7160 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -94,7 +94,7 @@ config S390
94 select HAVE_KVM if 64BIT 94 select HAVE_KVM if 64BIT
95 select HAVE_ARCH_TRACEHOOK 95 select HAVE_ARCH_TRACEHOOK
96 select INIT_ALL_POSSIBLE 96 select INIT_ALL_POSSIBLE
97 select HAVE_PERF_COUNTERS 97 select HAVE_PERF_EVENTS
98 98
99config SCHED_OMIT_FRAME_POINTER 99config SCHED_OMIT_FRAME_POINTER
100 bool 100 bool
diff --git a/arch/s390/include/asm/perf_counter.h b/arch/s390/include/asm/perf_counter.h
deleted file mode 100644
index 7015188c2cc2..000000000000
--- a/arch/s390/include/asm/perf_counter.h
+++ /dev/null
@@ -1,10 +0,0 @@
1/*
2 * Performance counter support - s390 specific definitions.
3 *
4 * Copyright 2009 Martin Schwidefsky, IBM Corporation.
5 */
6
7static inline void set_perf_counter_pending(void) {}
8static inline void clear_perf_counter_pending(void) {}
9
10#define PERF_COUNTER_INDEX_OFFSET 0
diff --git a/arch/s390/include/asm/perf_event.h b/arch/s390/include/asm/perf_event.h
new file mode 100644
index 000000000000..3840cbe77637
--- /dev/null
+++ b/arch/s390/include/asm/perf_event.h
@@ -0,0 +1,10 @@
1/*
2 * Performance event support - s390 specific definitions.
3 *
4 * Copyright 2009 Martin Schwidefsky, IBM Corporation.
5 */
6
7static inline void set_perf_event_pending(void) {}
8static inline void clear_perf_event_pending(void) {}
9
10#define PERF_EVENT_INDEX_OFFSET 0
diff --git a/arch/s390/include/asm/unistd.h b/arch/s390/include/asm/unistd.h
index c80602d7c880..cb5232df151e 100644
--- a/arch/s390/include/asm/unistd.h
+++ b/arch/s390/include/asm/unistd.h
@@ -268,7 +268,7 @@
268#define __NR_preadv 328 268#define __NR_preadv 328
269#define __NR_pwritev 329 269#define __NR_pwritev 329
270#define __NR_rt_tgsigqueueinfo 330 270#define __NR_rt_tgsigqueueinfo 330
271#define __NR_perf_counter_open 331 271#define __NR_perf_event_open 331
272#define NR_syscalls 332 272#define NR_syscalls 332
273 273
274/* 274/*
diff --git a/arch/s390/kernel/compat_wrapper.S b/arch/s390/kernel/compat_wrapper.S
index 88a83366819f..624790042d41 100644
--- a/arch/s390/kernel/compat_wrapper.S
+++ b/arch/s390/kernel/compat_wrapper.S
@@ -1832,11 +1832,11 @@ compat_sys_rt_tgsigqueueinfo_wrapper:
1832 llgtr %r5,%r5 # struct compat_siginfo * 1832 llgtr %r5,%r5 # struct compat_siginfo *
1833 jg compat_sys_rt_tgsigqueueinfo_wrapper # branch to system call 1833 jg compat_sys_rt_tgsigqueueinfo_wrapper # branch to system call
1834 1834
1835 .globl sys_perf_counter_open_wrapper 1835 .globl sys_perf_event_open_wrapper
1836sys_perf_counter_open_wrapper: 1836sys_perf_event_open_wrapper:
1837 llgtr %r2,%r2 # const struct perf_counter_attr * 1837 llgtr %r2,%r2 # const struct perf_event_attr *
1838 lgfr %r3,%r3 # pid_t 1838 lgfr %r3,%r3 # pid_t
1839 lgfr %r4,%r4 # int 1839 lgfr %r4,%r4 # int
1840 lgfr %r5,%r5 # int 1840 lgfr %r5,%r5 # int
1841 llgfr %r6,%r6 # unsigned long 1841 llgfr %r6,%r6 # unsigned long
1842 jg sys_perf_counter_open # branch to system call 1842 jg sys_perf_event_open # branch to system call
diff --git a/arch/s390/kernel/syscalls.S b/arch/s390/kernel/syscalls.S
index ad1acd200385..0b5083681e77 100644
--- a/arch/s390/kernel/syscalls.S
+++ b/arch/s390/kernel/syscalls.S
@@ -339,4 +339,4 @@ SYSCALL(sys_epoll_create1,sys_epoll_create1,sys_epoll_create1_wrapper)
339SYSCALL(sys_preadv,sys_preadv,compat_sys_preadv_wrapper) 339SYSCALL(sys_preadv,sys_preadv,compat_sys_preadv_wrapper)
340SYSCALL(sys_pwritev,sys_pwritev,compat_sys_pwritev_wrapper) 340SYSCALL(sys_pwritev,sys_pwritev,compat_sys_pwritev_wrapper)
341SYSCALL(sys_rt_tgsigqueueinfo,sys_rt_tgsigqueueinfo,compat_sys_rt_tgsigqueueinfo_wrapper) /* 330 */ 341SYSCALL(sys_rt_tgsigqueueinfo,sys_rt_tgsigqueueinfo,compat_sys_rt_tgsigqueueinfo_wrapper) /* 330 */
342SYSCALL(sys_perf_counter_open,sys_perf_counter_open,sys_perf_counter_open_wrapper) 342SYSCALL(sys_perf_event_open,sys_perf_event_open,sys_perf_event_open_wrapper)
diff --git a/arch/s390/mm/fault.c b/arch/s390/mm/fault.c
index 1abbadd497e1..6d507462967a 100644
--- a/arch/s390/mm/fault.c
+++ b/arch/s390/mm/fault.c
@@ -10,7 +10,7 @@
10 * Copyright (C) 1995 Linus Torvalds 10 * Copyright (C) 1995 Linus Torvalds
11 */ 11 */
12 12
13#include <linux/perf_counter.h> 13#include <linux/perf_event.h>
14#include <linux/signal.h> 14#include <linux/signal.h>
15#include <linux/sched.h> 15#include <linux/sched.h>
16#include <linux/kernel.h> 16#include <linux/kernel.h>
@@ -306,7 +306,7 @@ do_exception(struct pt_regs *regs, unsigned long error_code, int write)
306 * interrupts again and then search the VMAs 306 * interrupts again and then search the VMAs
307 */ 307 */
308 local_irq_enable(); 308 local_irq_enable();
309 perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address); 309 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address);
310 down_read(&mm->mmap_sem); 310 down_read(&mm->mmap_sem);
311 311
312 si_code = SEGV_MAPERR; 312 si_code = SEGV_MAPERR;
@@ -366,11 +366,11 @@ good_area:
366 } 366 }
367 if (fault & VM_FAULT_MAJOR) { 367 if (fault & VM_FAULT_MAJOR) {
368 tsk->maj_flt++; 368 tsk->maj_flt++;
369 perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0, 369 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0,
370 regs, address); 370 regs, address);
371 } else { 371 } else {
372 tsk->min_flt++; 372 tsk->min_flt++;
373 perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0, 373 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0,
374 regs, address); 374 regs, address);
375 } 375 }
376 up_read(&mm->mmap_sem); 376 up_read(&mm->mmap_sem);
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 4df3570fe511..b940424f8ccc 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -16,7 +16,7 @@ config SUPERH
16 select HAVE_IOREMAP_PROT if MMU 16 select HAVE_IOREMAP_PROT if MMU
17 select HAVE_ARCH_TRACEHOOK 17 select HAVE_ARCH_TRACEHOOK
18 select HAVE_DMA_API_DEBUG 18 select HAVE_DMA_API_DEBUG
19 select HAVE_PERF_COUNTERS 19 select HAVE_PERF_EVENTS
20 select HAVE_KERNEL_GZIP 20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_BZIP2 21 select HAVE_KERNEL_BZIP2
22 select HAVE_KERNEL_LZMA 22 select HAVE_KERNEL_LZMA
diff --git a/arch/sh/include/asm/perf_counter.h b/arch/sh/include/asm/perf_counter.h
deleted file mode 100644
index d8e6bb9c0ccc..000000000000
--- a/arch/sh/include/asm/perf_counter.h
+++ /dev/null
@@ -1,9 +0,0 @@
1#ifndef __ASM_SH_PERF_COUNTER_H
2#define __ASM_SH_PERF_COUNTER_H
3
4/* SH only supports software counters through this interface. */
5static inline void set_perf_counter_pending(void) {}
6
7#define PERF_COUNTER_INDEX_OFFSET 0
8
9#endif /* __ASM_SH_PERF_COUNTER_H */
diff --git a/arch/sh/include/asm/perf_event.h b/arch/sh/include/asm/perf_event.h
new file mode 100644
index 000000000000..11a302297ab7
--- /dev/null
+++ b/arch/sh/include/asm/perf_event.h
@@ -0,0 +1,9 @@
1#ifndef __ASM_SH_PERF_EVENT_H
2#define __ASM_SH_PERF_EVENT_H
3
4/* SH only supports software events through this interface. */
5static inline void set_perf_event_pending(void) {}
6
7#define PERF_EVENT_INDEX_OFFSET 0
8
9#endif /* __ASM_SH_PERF_EVENT_H */
diff --git a/arch/sh/include/asm/unistd_32.h b/arch/sh/include/asm/unistd_32.h
index 925dd40d9d55..f3fd1b9eb6b1 100644
--- a/arch/sh/include/asm/unistd_32.h
+++ b/arch/sh/include/asm/unistd_32.h
@@ -344,7 +344,7 @@
344#define __NR_preadv 333 344#define __NR_preadv 333
345#define __NR_pwritev 334 345#define __NR_pwritev 334
346#define __NR_rt_tgsigqueueinfo 335 346#define __NR_rt_tgsigqueueinfo 335
347#define __NR_perf_counter_open 336 347#define __NR_perf_event_open 336
348 348
349#define NR_syscalls 337 349#define NR_syscalls 337
350 350
diff --git a/arch/sh/include/asm/unistd_64.h b/arch/sh/include/asm/unistd_64.h
index 2b84bc916bc5..343ce8f073ea 100644
--- a/arch/sh/include/asm/unistd_64.h
+++ b/arch/sh/include/asm/unistd_64.h
@@ -384,7 +384,7 @@
384#define __NR_preadv 361 384#define __NR_preadv 361
385#define __NR_pwritev 362 385#define __NR_pwritev 362
386#define __NR_rt_tgsigqueueinfo 363 386#define __NR_rt_tgsigqueueinfo 363
387#define __NR_perf_counter_open 364 387#define __NR_perf_event_open 364
388 388
389#ifdef __KERNEL__ 389#ifdef __KERNEL__
390 390
diff --git a/arch/sh/kernel/syscalls_32.S b/arch/sh/kernel/syscalls_32.S
index 16ba225ede89..19fd11dd9871 100644
--- a/arch/sh/kernel/syscalls_32.S
+++ b/arch/sh/kernel/syscalls_32.S
@@ -352,4 +352,4 @@ ENTRY(sys_call_table)
352 .long sys_preadv 352 .long sys_preadv
353 .long sys_pwritev 353 .long sys_pwritev
354 .long sys_rt_tgsigqueueinfo /* 335 */ 354 .long sys_rt_tgsigqueueinfo /* 335 */
355 .long sys_perf_counter_open 355 .long sys_perf_event_open
diff --git a/arch/sh/kernel/syscalls_64.S b/arch/sh/kernel/syscalls_64.S
index af6fb7410c21..5bfde6c77498 100644
--- a/arch/sh/kernel/syscalls_64.S
+++ b/arch/sh/kernel/syscalls_64.S
@@ -390,4 +390,4 @@ sys_call_table:
390 .long sys_preadv 390 .long sys_preadv
391 .long sys_pwritev 391 .long sys_pwritev
392 .long sys_rt_tgsigqueueinfo 392 .long sys_rt_tgsigqueueinfo
393 .long sys_perf_counter_open 393 .long sys_perf_event_open
diff --git a/arch/sh/mm/fault_32.c b/arch/sh/mm/fault_32.c
index 781b413ff82d..47530104e0ad 100644
--- a/arch/sh/mm/fault_32.c
+++ b/arch/sh/mm/fault_32.c
@@ -15,7 +15,7 @@
15#include <linux/mm.h> 15#include <linux/mm.h>
16#include <linux/hardirq.h> 16#include <linux/hardirq.h>
17#include <linux/kprobes.h> 17#include <linux/kprobes.h>
18#include <linux/perf_counter.h> 18#include <linux/perf_event.h>
19#include <asm/io_trapped.h> 19#include <asm/io_trapped.h>
20#include <asm/system.h> 20#include <asm/system.h>
21#include <asm/mmu_context.h> 21#include <asm/mmu_context.h>
@@ -157,7 +157,7 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs,
157 if ((regs->sr & SR_IMASK) != SR_IMASK) 157 if ((regs->sr & SR_IMASK) != SR_IMASK)
158 local_irq_enable(); 158 local_irq_enable();
159 159
160 perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address); 160 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address);
161 161
162 /* 162 /*
163 * If we're in an interrupt, have no user context or are running 163 * If we're in an interrupt, have no user context or are running
@@ -208,11 +208,11 @@ survive:
208 } 208 }
209 if (fault & VM_FAULT_MAJOR) { 209 if (fault & VM_FAULT_MAJOR) {
210 tsk->maj_flt++; 210 tsk->maj_flt++;
211 perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0, 211 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0,
212 regs, address); 212 regs, address);
213 } else { 213 } else {
214 tsk->min_flt++; 214 tsk->min_flt++;
215 perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0, 215 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0,
216 regs, address); 216 regs, address);
217 } 217 }
218 218
diff --git a/arch/sh/mm/tlbflush_64.c b/arch/sh/mm/tlbflush_64.c
index 2dcc48528f7a..de0b0e881823 100644
--- a/arch/sh/mm/tlbflush_64.c
+++ b/arch/sh/mm/tlbflush_64.c
@@ -20,7 +20,7 @@
20#include <linux/mman.h> 20#include <linux/mman.h>
21#include <linux/mm.h> 21#include <linux/mm.h>
22#include <linux/smp.h> 22#include <linux/smp.h>
23#include <linux/perf_counter.h> 23#include <linux/perf_event.h>
24#include <linux/interrupt.h> 24#include <linux/interrupt.h>
25#include <asm/system.h> 25#include <asm/system.h>
26#include <asm/io.h> 26#include <asm/io.h>
@@ -116,7 +116,7 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long writeaccess,
116 /* Not an IO address, so reenable interrupts */ 116 /* Not an IO address, so reenable interrupts */
117 local_irq_enable(); 117 local_irq_enable();
118 118
119 perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address); 119 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address);
120 120
121 /* 121 /*
122 * If we're in an interrupt or have no user 122 * If we're in an interrupt or have no user
@@ -201,11 +201,11 @@ survive:
201 201
202 if (fault & VM_FAULT_MAJOR) { 202 if (fault & VM_FAULT_MAJOR) {
203 tsk->maj_flt++; 203 tsk->maj_flt++;
204 perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0, 204 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0,
205 regs, address); 205 regs, address);
206 } else { 206 } else {
207 tsk->min_flt++; 207 tsk->min_flt++;
208 perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0, 208 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0,
209 regs, address); 209 regs, address);
210 } 210 }
211 211
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index 86b82348b97c..97fca4695e0b 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -25,7 +25,7 @@ config SPARC
25 select ARCH_WANT_OPTIONAL_GPIOLIB 25 select ARCH_WANT_OPTIONAL_GPIOLIB
26 select RTC_CLASS 26 select RTC_CLASS
27 select RTC_DRV_M48T59 27 select RTC_DRV_M48T59
28 select HAVE_PERF_COUNTERS 28 select HAVE_PERF_EVENTS
29 select HAVE_DMA_ATTRS 29 select HAVE_DMA_ATTRS
30 select HAVE_DMA_API_DEBUG 30 select HAVE_DMA_API_DEBUG
31 31
@@ -47,7 +47,7 @@ config SPARC64
47 select RTC_DRV_BQ4802 47 select RTC_DRV_BQ4802
48 select RTC_DRV_SUN4V 48 select RTC_DRV_SUN4V
49 select RTC_DRV_STARFIRE 49 select RTC_DRV_STARFIRE
50 select HAVE_PERF_COUNTERS 50 select HAVE_PERF_EVENTS
51 51
52config ARCH_DEFCONFIG 52config ARCH_DEFCONFIG
53 string 53 string
diff --git a/arch/sparc/include/asm/perf_counter.h b/arch/sparc/include/asm/perf_counter.h
deleted file mode 100644
index 5d7a8ca0e491..000000000000
--- a/arch/sparc/include/asm/perf_counter.h
+++ /dev/null
@@ -1,14 +0,0 @@
1#ifndef __ASM_SPARC_PERF_COUNTER_H
2#define __ASM_SPARC_PERF_COUNTER_H
3
4extern void set_perf_counter_pending(void);
5
6#define PERF_COUNTER_INDEX_OFFSET 0
7
8#ifdef CONFIG_PERF_COUNTERS
9extern void init_hw_perf_counters(void);
10#else
11static inline void init_hw_perf_counters(void) { }
12#endif
13
14#endif
diff --git a/arch/sparc/include/asm/perf_event.h b/arch/sparc/include/asm/perf_event.h
new file mode 100644
index 000000000000..7e2669894ce8
--- /dev/null
+++ b/arch/sparc/include/asm/perf_event.h
@@ -0,0 +1,14 @@
1#ifndef __ASM_SPARC_PERF_EVENT_H
2#define __ASM_SPARC_PERF_EVENT_H
3
4extern void set_perf_event_pending(void);
5
6#define PERF_EVENT_INDEX_OFFSET 0
7
8#ifdef CONFIG_PERF_EVENTS
9extern void init_hw_perf_events(void);
10#else
11static inline void init_hw_perf_events(void) { }
12#endif
13
14#endif
diff --git a/arch/sparc/include/asm/unistd.h b/arch/sparc/include/asm/unistd.h
index 706df669f3b8..42f2316c3eaa 100644
--- a/arch/sparc/include/asm/unistd.h
+++ b/arch/sparc/include/asm/unistd.h
@@ -395,7 +395,7 @@
395#define __NR_preadv 324 395#define __NR_preadv 324
396#define __NR_pwritev 325 396#define __NR_pwritev 325
397#define __NR_rt_tgsigqueueinfo 326 397#define __NR_rt_tgsigqueueinfo 326
398#define __NR_perf_counter_open 327 398#define __NR_perf_event_open 327
399 399
400#define NR_SYSCALLS 328 400#define NR_SYSCALLS 328
401 401
diff --git a/arch/sparc/kernel/Makefile b/arch/sparc/kernel/Makefile
index 247cc620cee5..3a048fad7ee2 100644
--- a/arch/sparc/kernel/Makefile
+++ b/arch/sparc/kernel/Makefile
@@ -104,5 +104,5 @@ obj-$(CONFIG_AUDIT) += audit.o
104audit--$(CONFIG_AUDIT) := compat_audit.o 104audit--$(CONFIG_AUDIT) := compat_audit.o
105obj-$(CONFIG_COMPAT) += $(audit--y) 105obj-$(CONFIG_COMPAT) += $(audit--y)
106 106
107pc--$(CONFIG_PERF_COUNTERS) := perf_counter.o 107pc--$(CONFIG_PERF_EVENTS) := perf_event.o
108obj-$(CONFIG_SPARC64) += $(pc--y) 108obj-$(CONFIG_SPARC64) += $(pc--y)
diff --git a/arch/sparc/kernel/nmi.c b/arch/sparc/kernel/nmi.c
index 378eb53e0776..b129611590a4 100644
--- a/arch/sparc/kernel/nmi.c
+++ b/arch/sparc/kernel/nmi.c
@@ -19,7 +19,7 @@
19#include <linux/delay.h> 19#include <linux/delay.h>
20#include <linux/smp.h> 20#include <linux/smp.h>
21 21
22#include <asm/perf_counter.h> 22#include <asm/perf_event.h>
23#include <asm/ptrace.h> 23#include <asm/ptrace.h>
24#include <asm/local.h> 24#include <asm/local.h>
25#include <asm/pcr.h> 25#include <asm/pcr.h>
@@ -265,7 +265,7 @@ int __init nmi_init(void)
265 } 265 }
266 } 266 }
267 if (!err) 267 if (!err)
268 init_hw_perf_counters(); 268 init_hw_perf_events();
269 269
270 return err; 270 return err;
271} 271}
diff --git a/arch/sparc/kernel/pcr.c b/arch/sparc/kernel/pcr.c
index 68ff00107073..2d94e7a03af5 100644
--- a/arch/sparc/kernel/pcr.c
+++ b/arch/sparc/kernel/pcr.c
@@ -7,7 +7,7 @@
7#include <linux/init.h> 7#include <linux/init.h>
8#include <linux/irq.h> 8#include <linux/irq.h>
9 9
10#include <linux/perf_counter.h> 10#include <linux/perf_event.h>
11 11
12#include <asm/pil.h> 12#include <asm/pil.h>
13#include <asm/pcr.h> 13#include <asm/pcr.h>
@@ -15,7 +15,7 @@
15 15
16/* This code is shared between various users of the performance 16/* This code is shared between various users of the performance
17 * counters. Users will be oprofile, pseudo-NMI watchdog, and the 17 * counters. Users will be oprofile, pseudo-NMI watchdog, and the
18 * perf_counter support layer. 18 * perf_event support layer.
19 */ 19 */
20 20
21#define PCR_SUN4U_ENABLE (PCR_PIC_PRIV | PCR_STRACE | PCR_UTRACE) 21#define PCR_SUN4U_ENABLE (PCR_PIC_PRIV | PCR_STRACE | PCR_UTRACE)
@@ -42,14 +42,14 @@ void deferred_pcr_work_irq(int irq, struct pt_regs *regs)
42 42
43 old_regs = set_irq_regs(regs); 43 old_regs = set_irq_regs(regs);
44 irq_enter(); 44 irq_enter();
45#ifdef CONFIG_PERF_COUNTERS 45#ifdef CONFIG_PERF_EVENTS
46 perf_counter_do_pending(); 46 perf_event_do_pending();
47#endif 47#endif
48 irq_exit(); 48 irq_exit();
49 set_irq_regs(old_regs); 49 set_irq_regs(old_regs);
50} 50}
51 51
52void set_perf_counter_pending(void) 52void set_perf_event_pending(void)
53{ 53{
54 set_softint(1 << PIL_DEFERRED_PCR_WORK); 54 set_softint(1 << PIL_DEFERRED_PCR_WORK);
55} 55}
diff --git a/arch/sparc/kernel/perf_counter.c b/arch/sparc/kernel/perf_event.c
index b1265ce8a053..2d6a1b10c81d 100644
--- a/arch/sparc/kernel/perf_counter.c
+++ b/arch/sparc/kernel/perf_event.c
@@ -1,8 +1,8 @@
1/* Performance counter support for sparc64. 1/* Performance event support for sparc64.
2 * 2 *
3 * Copyright (C) 2009 David S. Miller <davem@davemloft.net> 3 * Copyright (C) 2009 David S. Miller <davem@davemloft.net>
4 * 4 *
5 * This code is based almost entirely upon the x86 perf counter 5 * This code is based almost entirely upon the x86 perf event
6 * code, which is: 6 * code, which is:
7 * 7 *
8 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> 8 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
@@ -12,7 +12,7 @@
12 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> 12 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
13 */ 13 */
14 14
15#include <linux/perf_counter.h> 15#include <linux/perf_event.h>
16#include <linux/kprobes.h> 16#include <linux/kprobes.h>
17#include <linux/kernel.h> 17#include <linux/kernel.h>
18#include <linux/kdebug.h> 18#include <linux/kdebug.h>
@@ -46,19 +46,19 @@
46 * normal code. 46 * normal code.
47 */ 47 */
48 48
49#define MAX_HWCOUNTERS 2 49#define MAX_HWEVENTS 2
50#define MAX_PERIOD ((1UL << 32) - 1) 50#define MAX_PERIOD ((1UL << 32) - 1)
51 51
52#define PIC_UPPER_INDEX 0 52#define PIC_UPPER_INDEX 0
53#define PIC_LOWER_INDEX 1 53#define PIC_LOWER_INDEX 1
54 54
55struct cpu_hw_counters { 55struct cpu_hw_events {
56 struct perf_counter *counters[MAX_HWCOUNTERS]; 56 struct perf_event *events[MAX_HWEVENTS];
57 unsigned long used_mask[BITS_TO_LONGS(MAX_HWCOUNTERS)]; 57 unsigned long used_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
58 unsigned long active_mask[BITS_TO_LONGS(MAX_HWCOUNTERS)]; 58 unsigned long active_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
59 int enabled; 59 int enabled;
60}; 60};
61DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = { .enabled = 1, }; 61DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { .enabled = 1, };
62 62
63struct perf_event_map { 63struct perf_event_map {
64 u16 encoding; 64 u16 encoding;
@@ -87,9 +87,9 @@ static const struct perf_event_map ultra3i_perfmon_event_map[] = {
87 [PERF_COUNT_HW_CACHE_MISSES] = { 0x0009, PIC_UPPER }, 87 [PERF_COUNT_HW_CACHE_MISSES] = { 0x0009, PIC_UPPER },
88}; 88};
89 89
90static const struct perf_event_map *ultra3i_event_map(int event) 90static const struct perf_event_map *ultra3i_event_map(int event_id)
91{ 91{
92 return &ultra3i_perfmon_event_map[event]; 92 return &ultra3i_perfmon_event_map[event_id];
93} 93}
94 94
95static const struct sparc_pmu ultra3i_pmu = { 95static const struct sparc_pmu ultra3i_pmu = {
@@ -111,9 +111,9 @@ static const struct perf_event_map niagara2_perfmon_event_map[] = {
111 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x0202, PIC_UPPER | PIC_LOWER }, 111 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x0202, PIC_UPPER | PIC_LOWER },
112}; 112};
113 113
114static const struct perf_event_map *niagara2_event_map(int event) 114static const struct perf_event_map *niagara2_event_map(int event_id)
115{ 115{
116 return &niagara2_perfmon_event_map[event]; 116 return &niagara2_perfmon_event_map[event_id];
117} 117}
118 118
119static const struct sparc_pmu niagara2_pmu = { 119static const struct sparc_pmu niagara2_pmu = {
@@ -130,13 +130,13 @@ static const struct sparc_pmu niagara2_pmu = {
130 130
131static const struct sparc_pmu *sparc_pmu __read_mostly; 131static const struct sparc_pmu *sparc_pmu __read_mostly;
132 132
133static u64 event_encoding(u64 event, int idx) 133static u64 event_encoding(u64 event_id, int idx)
134{ 134{
135 if (idx == PIC_UPPER_INDEX) 135 if (idx == PIC_UPPER_INDEX)
136 event <<= sparc_pmu->upper_shift; 136 event_id <<= sparc_pmu->upper_shift;
137 else 137 else
138 event <<= sparc_pmu->lower_shift; 138 event_id <<= sparc_pmu->lower_shift;
139 return event; 139 return event_id;
140} 140}
141 141
142static u64 mask_for_index(int idx) 142static u64 mask_for_index(int idx)
@@ -151,7 +151,7 @@ static u64 nop_for_index(int idx)
151 sparc_pmu->lower_nop, idx); 151 sparc_pmu->lower_nop, idx);
152} 152}
153 153
154static inline void sparc_pmu_enable_counter(struct hw_perf_counter *hwc, 154static inline void sparc_pmu_enable_event(struct hw_perf_event *hwc,
155 int idx) 155 int idx)
156{ 156{
157 u64 val, mask = mask_for_index(idx); 157 u64 val, mask = mask_for_index(idx);
@@ -160,7 +160,7 @@ static inline void sparc_pmu_enable_counter(struct hw_perf_counter *hwc,
160 pcr_ops->write((val & ~mask) | hwc->config); 160 pcr_ops->write((val & ~mask) | hwc->config);
161} 161}
162 162
163static inline void sparc_pmu_disable_counter(struct hw_perf_counter *hwc, 163static inline void sparc_pmu_disable_event(struct hw_perf_event *hwc,
164 int idx) 164 int idx)
165{ 165{
166 u64 mask = mask_for_index(idx); 166 u64 mask = mask_for_index(idx);
@@ -172,7 +172,7 @@ static inline void sparc_pmu_disable_counter(struct hw_perf_counter *hwc,
172 172
173void hw_perf_enable(void) 173void hw_perf_enable(void)
174{ 174{
175 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); 175 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
176 u64 val; 176 u64 val;
177 int i; 177 int i;
178 178
@@ -184,9 +184,9 @@ void hw_perf_enable(void)
184 184
185 val = pcr_ops->read(); 185 val = pcr_ops->read();
186 186
187 for (i = 0; i < MAX_HWCOUNTERS; i++) { 187 for (i = 0; i < MAX_HWEVENTS; i++) {
188 struct perf_counter *cp = cpuc->counters[i]; 188 struct perf_event *cp = cpuc->events[i];
189 struct hw_perf_counter *hwc; 189 struct hw_perf_event *hwc;
190 190
191 if (!cp) 191 if (!cp)
192 continue; 192 continue;
@@ -199,7 +199,7 @@ void hw_perf_enable(void)
199 199
200void hw_perf_disable(void) 200void hw_perf_disable(void)
201{ 201{
202 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); 202 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
203 u64 val; 203 u64 val;
204 204
205 if (!cpuc->enabled) 205 if (!cpuc->enabled)
@@ -241,8 +241,8 @@ static void write_pmc(int idx, u64 val)
241 write_pic(pic); 241 write_pic(pic);
242} 242}
243 243
244static int sparc_perf_counter_set_period(struct perf_counter *counter, 244static int sparc_perf_event_set_period(struct perf_event *event,
245 struct hw_perf_counter *hwc, int idx) 245 struct hw_perf_event *hwc, int idx)
246{ 246{
247 s64 left = atomic64_read(&hwc->period_left); 247 s64 left = atomic64_read(&hwc->period_left);
248 s64 period = hwc->sample_period; 248 s64 period = hwc->sample_period;
@@ -268,33 +268,33 @@ static int sparc_perf_counter_set_period(struct perf_counter *counter,
268 268
269 write_pmc(idx, (u64)(-left) & 0xffffffff); 269 write_pmc(idx, (u64)(-left) & 0xffffffff);
270 270
271 perf_counter_update_userpage(counter); 271 perf_event_update_userpage(event);
272 272
273 return ret; 273 return ret;
274} 274}
275 275
276static int sparc_pmu_enable(struct perf_counter *counter) 276static int sparc_pmu_enable(struct perf_event *event)
277{ 277{
278 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); 278 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
279 struct hw_perf_counter *hwc = &counter->hw; 279 struct hw_perf_event *hwc = &event->hw;
280 int idx = hwc->idx; 280 int idx = hwc->idx;
281 281
282 if (test_and_set_bit(idx, cpuc->used_mask)) 282 if (test_and_set_bit(idx, cpuc->used_mask))
283 return -EAGAIN; 283 return -EAGAIN;
284 284
285 sparc_pmu_disable_counter(hwc, idx); 285 sparc_pmu_disable_event(hwc, idx);
286 286
287 cpuc->counters[idx] = counter; 287 cpuc->events[idx] = event;
288 set_bit(idx, cpuc->active_mask); 288 set_bit(idx, cpuc->active_mask);
289 289
290 sparc_perf_counter_set_period(counter, hwc, idx); 290 sparc_perf_event_set_period(event, hwc, idx);
291 sparc_pmu_enable_counter(hwc, idx); 291 sparc_pmu_enable_event(hwc, idx);
292 perf_counter_update_userpage(counter); 292 perf_event_update_userpage(event);
293 return 0; 293 return 0;
294} 294}
295 295
296static u64 sparc_perf_counter_update(struct perf_counter *counter, 296static u64 sparc_perf_event_update(struct perf_event *event,
297 struct hw_perf_counter *hwc, int idx) 297 struct hw_perf_event *hwc, int idx)
298{ 298{
299 int shift = 64 - 32; 299 int shift = 64 - 32;
300 u64 prev_raw_count, new_raw_count; 300 u64 prev_raw_count, new_raw_count;
@@ -311,79 +311,79 @@ again:
311 delta = (new_raw_count << shift) - (prev_raw_count << shift); 311 delta = (new_raw_count << shift) - (prev_raw_count << shift);
312 delta >>= shift; 312 delta >>= shift;
313 313
314 atomic64_add(delta, &counter->count); 314 atomic64_add(delta, &event->count);
315 atomic64_sub(delta, &hwc->period_left); 315 atomic64_sub(delta, &hwc->period_left);
316 316
317 return new_raw_count; 317 return new_raw_count;
318} 318}
319 319
320static void sparc_pmu_disable(struct perf_counter *counter) 320static void sparc_pmu_disable(struct perf_event *event)
321{ 321{
322 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); 322 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
323 struct hw_perf_counter *hwc = &counter->hw; 323 struct hw_perf_event *hwc = &event->hw;
324 int idx = hwc->idx; 324 int idx = hwc->idx;
325 325
326 clear_bit(idx, cpuc->active_mask); 326 clear_bit(idx, cpuc->active_mask);
327 sparc_pmu_disable_counter(hwc, idx); 327 sparc_pmu_disable_event(hwc, idx);
328 328
329 barrier(); 329 barrier();
330 330
331 sparc_perf_counter_update(counter, hwc, idx); 331 sparc_perf_event_update(event, hwc, idx);
332 cpuc->counters[idx] = NULL; 332 cpuc->events[idx] = NULL;
333 clear_bit(idx, cpuc->used_mask); 333 clear_bit(idx, cpuc->used_mask);
334 334
335 perf_counter_update_userpage(counter); 335 perf_event_update_userpage(event);
336} 336}
337 337
338static void sparc_pmu_read(struct perf_counter *counter) 338static void sparc_pmu_read(struct perf_event *event)
339{ 339{
340 struct hw_perf_counter *hwc = &counter->hw; 340 struct hw_perf_event *hwc = &event->hw;
341 sparc_perf_counter_update(counter, hwc, hwc->idx); 341 sparc_perf_event_update(event, hwc, hwc->idx);
342} 342}
343 343
344static void sparc_pmu_unthrottle(struct perf_counter *counter) 344static void sparc_pmu_unthrottle(struct perf_event *event)
345{ 345{
346 struct hw_perf_counter *hwc = &counter->hw; 346 struct hw_perf_event *hwc = &event->hw;
347 sparc_pmu_enable_counter(hwc, hwc->idx); 347 sparc_pmu_enable_event(hwc, hwc->idx);
348} 348}
349 349
350static atomic_t active_counters = ATOMIC_INIT(0); 350static atomic_t active_events = ATOMIC_INIT(0);
351static DEFINE_MUTEX(pmc_grab_mutex); 351static DEFINE_MUTEX(pmc_grab_mutex);
352 352
353void perf_counter_grab_pmc(void) 353void perf_event_grab_pmc(void)
354{ 354{
355 if (atomic_inc_not_zero(&active_counters)) 355 if (atomic_inc_not_zero(&active_events))
356 return; 356 return;
357 357
358 mutex_lock(&pmc_grab_mutex); 358 mutex_lock(&pmc_grab_mutex);
359 if (atomic_read(&active_counters) == 0) { 359 if (atomic_read(&active_events) == 0) {
360 if (atomic_read(&nmi_active) > 0) { 360 if (atomic_read(&nmi_active) > 0) {
361 on_each_cpu(stop_nmi_watchdog, NULL, 1); 361 on_each_cpu(stop_nmi_watchdog, NULL, 1);
362 BUG_ON(atomic_read(&nmi_active) != 0); 362 BUG_ON(atomic_read(&nmi_active) != 0);
363 } 363 }
364 atomic_inc(&active_counters); 364 atomic_inc(&active_events);
365 } 365 }
366 mutex_unlock(&pmc_grab_mutex); 366 mutex_unlock(&pmc_grab_mutex);
367} 367}
368 368
369void perf_counter_release_pmc(void) 369void perf_event_release_pmc(void)
370{ 370{
371 if (atomic_dec_and_mutex_lock(&active_counters, &pmc_grab_mutex)) { 371 if (atomic_dec_and_mutex_lock(&active_events, &pmc_grab_mutex)) {
372 if (atomic_read(&nmi_active) == 0) 372 if (atomic_read(&nmi_active) == 0)
373 on_each_cpu(start_nmi_watchdog, NULL, 1); 373 on_each_cpu(start_nmi_watchdog, NULL, 1);
374 mutex_unlock(&pmc_grab_mutex); 374 mutex_unlock(&pmc_grab_mutex);
375 } 375 }
376} 376}
377 377
378static void hw_perf_counter_destroy(struct perf_counter *counter) 378static void hw_perf_event_destroy(struct perf_event *event)
379{ 379{
380 perf_counter_release_pmc(); 380 perf_event_release_pmc();
381} 381}
382 382
383static int __hw_perf_counter_init(struct perf_counter *counter) 383static int __hw_perf_event_init(struct perf_event *event)
384{ 384{
385 struct perf_counter_attr *attr = &counter->attr; 385 struct perf_event_attr *attr = &event->attr;
386 struct hw_perf_counter *hwc = &counter->hw; 386 struct hw_perf_event *hwc = &event->hw;
387 const struct perf_event_map *pmap; 387 const struct perf_event_map *pmap;
388 u64 enc; 388 u64 enc;
389 389
@@ -396,8 +396,8 @@ static int __hw_perf_counter_init(struct perf_counter *counter)
396 if (attr->config >= sparc_pmu->max_events) 396 if (attr->config >= sparc_pmu->max_events)
397 return -EINVAL; 397 return -EINVAL;
398 398
399 perf_counter_grab_pmc(); 399 perf_event_grab_pmc();
400 counter->destroy = hw_perf_counter_destroy; 400 event->destroy = hw_perf_event_destroy;
401 401
402 /* We save the enable bits in the config_base. So to 402 /* We save the enable bits in the config_base. So to
403 * turn off sampling just write 'config', and to enable 403 * turn off sampling just write 'config', and to enable
@@ -439,16 +439,16 @@ static const struct pmu pmu = {
439 .unthrottle = sparc_pmu_unthrottle, 439 .unthrottle = sparc_pmu_unthrottle,
440}; 440};
441 441
442const struct pmu *hw_perf_counter_init(struct perf_counter *counter) 442const struct pmu *hw_perf_event_init(struct perf_event *event)
443{ 443{
444 int err = __hw_perf_counter_init(counter); 444 int err = __hw_perf_event_init(event);
445 445
446 if (err) 446 if (err)
447 return ERR_PTR(err); 447 return ERR_PTR(err);
448 return &pmu; 448 return &pmu;
449} 449}
450 450
451void perf_counter_print_debug(void) 451void perf_event_print_debug(void)
452{ 452{
453 unsigned long flags; 453 unsigned long flags;
454 u64 pcr, pic; 454 u64 pcr, pic;
@@ -471,16 +471,16 @@ void perf_counter_print_debug(void)
471 local_irq_restore(flags); 471 local_irq_restore(flags);
472} 472}
473 473
474static int __kprobes perf_counter_nmi_handler(struct notifier_block *self, 474static int __kprobes perf_event_nmi_handler(struct notifier_block *self,
475 unsigned long cmd, void *__args) 475 unsigned long cmd, void *__args)
476{ 476{
477 struct die_args *args = __args; 477 struct die_args *args = __args;
478 struct perf_sample_data data; 478 struct perf_sample_data data;
479 struct cpu_hw_counters *cpuc; 479 struct cpu_hw_events *cpuc;
480 struct pt_regs *regs; 480 struct pt_regs *regs;
481 int idx; 481 int idx;
482 482
483 if (!atomic_read(&active_counters)) 483 if (!atomic_read(&active_events))
484 return NOTIFY_DONE; 484 return NOTIFY_DONE;
485 485
486 switch (cmd) { 486 switch (cmd) {
@@ -495,32 +495,32 @@ static int __kprobes perf_counter_nmi_handler(struct notifier_block *self,
495 495
496 data.addr = 0; 496 data.addr = 0;
497 497
498 cpuc = &__get_cpu_var(cpu_hw_counters); 498 cpuc = &__get_cpu_var(cpu_hw_events);
499 for (idx = 0; idx < MAX_HWCOUNTERS; idx++) { 499 for (idx = 0; idx < MAX_HWEVENTS; idx++) {
500 struct perf_counter *counter = cpuc->counters[idx]; 500 struct perf_event *event = cpuc->events[idx];
501 struct hw_perf_counter *hwc; 501 struct hw_perf_event *hwc;
502 u64 val; 502 u64 val;
503 503
504 if (!test_bit(idx, cpuc->active_mask)) 504 if (!test_bit(idx, cpuc->active_mask))
505 continue; 505 continue;
506 hwc = &counter->hw; 506 hwc = &event->hw;
507 val = sparc_perf_counter_update(counter, hwc, idx); 507 val = sparc_perf_event_update(event, hwc, idx);
508 if (val & (1ULL << 31)) 508 if (val & (1ULL << 31))
509 continue; 509 continue;
510 510
511 data.period = counter->hw.last_period; 511 data.period = event->hw.last_period;
512 if (!sparc_perf_counter_set_period(counter, hwc, idx)) 512 if (!sparc_perf_event_set_period(event, hwc, idx))
513 continue; 513 continue;
514 514
515 if (perf_counter_overflow(counter, 1, &data, regs)) 515 if (perf_event_overflow(event, 1, &data, regs))
516 sparc_pmu_disable_counter(hwc, idx); 516 sparc_pmu_disable_event(hwc, idx);
517 } 517 }
518 518
519 return NOTIFY_STOP; 519 return NOTIFY_STOP;
520} 520}
521 521
522static __read_mostly struct notifier_block perf_counter_nmi_notifier = { 522static __read_mostly struct notifier_block perf_event_nmi_notifier = {
523 .notifier_call = perf_counter_nmi_handler, 523 .notifier_call = perf_event_nmi_handler,
524}; 524};
525 525
526static bool __init supported_pmu(void) 526static bool __init supported_pmu(void)
@@ -536,9 +536,9 @@ static bool __init supported_pmu(void)
536 return false; 536 return false;
537} 537}
538 538
539void __init init_hw_perf_counters(void) 539void __init init_hw_perf_events(void)
540{ 540{
541 pr_info("Performance counters: "); 541 pr_info("Performance events: ");
542 542
543 if (!supported_pmu()) { 543 if (!supported_pmu()) {
544 pr_cont("No support for PMU type '%s'\n", sparc_pmu_type); 544 pr_cont("No support for PMU type '%s'\n", sparc_pmu_type);
@@ -547,10 +547,10 @@ void __init init_hw_perf_counters(void)
547 547
548 pr_cont("Supported PMU type is '%s'\n", sparc_pmu_type); 548 pr_cont("Supported PMU type is '%s'\n", sparc_pmu_type);
549 549
550 /* All sparc64 PMUs currently have 2 counters. But this simple 550 /* All sparc64 PMUs currently have 2 events. But this simple
551 * driver only supports one active counter at a time. 551 * driver only supports one active event at a time.
552 */ 552 */
553 perf_max_counters = 1; 553 perf_max_events = 1;
554 554
555 register_die_notifier(&perf_counter_nmi_notifier); 555 register_die_notifier(&perf_event_nmi_notifier);
556} 556}
diff --git a/arch/sparc/kernel/systbls_32.S b/arch/sparc/kernel/systbls_32.S
index 04181577cb65..0f1658d37490 100644
--- a/arch/sparc/kernel/systbls_32.S
+++ b/arch/sparc/kernel/systbls_32.S
@@ -82,5 +82,5 @@ sys_call_table:
82/*310*/ .long sys_utimensat, sys_signalfd, sys_timerfd_create, sys_eventfd, sys_fallocate 82/*310*/ .long sys_utimensat, sys_signalfd, sys_timerfd_create, sys_eventfd, sys_fallocate
83/*315*/ .long sys_timerfd_settime, sys_timerfd_gettime, sys_signalfd4, sys_eventfd2, sys_epoll_create1 83/*315*/ .long sys_timerfd_settime, sys_timerfd_gettime, sys_signalfd4, sys_eventfd2, sys_epoll_create1
84/*320*/ .long sys_dup3, sys_pipe2, sys_inotify_init1, sys_accept4, sys_preadv 84/*320*/ .long sys_dup3, sys_pipe2, sys_inotify_init1, sys_accept4, sys_preadv
85/*325*/ .long sys_pwritev, sys_rt_tgsigqueueinfo, sys_perf_counter_open 85/*325*/ .long sys_pwritev, sys_rt_tgsigqueueinfo, sys_perf_event_open
86 86
diff --git a/arch/sparc/kernel/systbls_64.S b/arch/sparc/kernel/systbls_64.S
index 91b06b7f7acf..009825f6e73c 100644
--- a/arch/sparc/kernel/systbls_64.S
+++ b/arch/sparc/kernel/systbls_64.S
@@ -83,7 +83,7 @@ sys_call_table32:
83/*310*/ .word compat_sys_utimensat, compat_sys_signalfd, sys_timerfd_create, sys_eventfd, compat_sys_fallocate 83/*310*/ .word compat_sys_utimensat, compat_sys_signalfd, sys_timerfd_create, sys_eventfd, compat_sys_fallocate
84 .word compat_sys_timerfd_settime, compat_sys_timerfd_gettime, compat_sys_signalfd4, sys_eventfd2, sys_epoll_create1 84 .word compat_sys_timerfd_settime, compat_sys_timerfd_gettime, compat_sys_signalfd4, sys_eventfd2, sys_epoll_create1
85/*320*/ .word sys_dup3, sys_pipe2, sys_inotify_init1, sys_accept4, compat_sys_preadv 85/*320*/ .word sys_dup3, sys_pipe2, sys_inotify_init1, sys_accept4, compat_sys_preadv
86 .word compat_sys_pwritev, compat_sys_rt_tgsigqueueinfo, sys_perf_counter_open 86 .word compat_sys_pwritev, compat_sys_rt_tgsigqueueinfo, sys_perf_event_open
87 87
88#endif /* CONFIG_COMPAT */ 88#endif /* CONFIG_COMPAT */
89 89
@@ -158,4 +158,4 @@ sys_call_table:
158/*310*/ .word sys_utimensat, sys_signalfd, sys_timerfd_create, sys_eventfd, sys_fallocate 158/*310*/ .word sys_utimensat, sys_signalfd, sys_timerfd_create, sys_eventfd, sys_fallocate
159 .word sys_timerfd_settime, sys_timerfd_gettime, sys_signalfd4, sys_eventfd2, sys_epoll_create1 159 .word sys_timerfd_settime, sys_timerfd_gettime, sys_signalfd4, sys_eventfd2, sys_epoll_create1
160/*320*/ .word sys_dup3, sys_pipe2, sys_inotify_init1, sys_accept4, sys_preadv 160/*320*/ .word sys_dup3, sys_pipe2, sys_inotify_init1, sys_accept4, sys_preadv
161 .word sys_pwritev, sys_rt_tgsigqueueinfo, sys_perf_counter_open 161 .word sys_pwritev, sys_rt_tgsigqueueinfo, sys_perf_event_open
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 51c59015b280..e4ff5d1280ca 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -24,7 +24,7 @@ config X86
24 select HAVE_UNSTABLE_SCHED_CLOCK 24 select HAVE_UNSTABLE_SCHED_CLOCK
25 select HAVE_IDE 25 select HAVE_IDE
26 select HAVE_OPROFILE 26 select HAVE_OPROFILE
27 select HAVE_PERF_COUNTERS if (!M386 && !M486) 27 select HAVE_PERF_EVENTS if (!M386 && !M486)
28 select HAVE_IOREMAP_PROT 28 select HAVE_IOREMAP_PROT
29 select HAVE_KPROBES 29 select HAVE_KPROBES
30 select ARCH_WANT_OPTIONAL_GPIOLIB 30 select ARCH_WANT_OPTIONAL_GPIOLIB
diff --git a/arch/x86/ia32/ia32entry.S b/arch/x86/ia32/ia32entry.S
index ba331bfd1112..74619c4f9fda 100644
--- a/arch/x86/ia32/ia32entry.S
+++ b/arch/x86/ia32/ia32entry.S
@@ -831,5 +831,5 @@ ia32_sys_call_table:
831 .quad compat_sys_preadv 831 .quad compat_sys_preadv
832 .quad compat_sys_pwritev 832 .quad compat_sys_pwritev
833 .quad compat_sys_rt_tgsigqueueinfo /* 335 */ 833 .quad compat_sys_rt_tgsigqueueinfo /* 335 */
834 .quad sys_perf_counter_open 834 .quad sys_perf_event_open
835ia32_syscall_end: 835ia32_syscall_end:
diff --git a/arch/x86/include/asm/entry_arch.h b/arch/x86/include/asm/entry_arch.h
index 5e3f2044f0d3..f5693c81a1db 100644
--- a/arch/x86/include/asm/entry_arch.h
+++ b/arch/x86/include/asm/entry_arch.h
@@ -49,7 +49,7 @@ BUILD_INTERRUPT(apic_timer_interrupt,LOCAL_TIMER_VECTOR)
49BUILD_INTERRUPT(error_interrupt,ERROR_APIC_VECTOR) 49BUILD_INTERRUPT(error_interrupt,ERROR_APIC_VECTOR)
50BUILD_INTERRUPT(spurious_interrupt,SPURIOUS_APIC_VECTOR) 50BUILD_INTERRUPT(spurious_interrupt,SPURIOUS_APIC_VECTOR)
51 51
52#ifdef CONFIG_PERF_COUNTERS 52#ifdef CONFIG_PERF_EVENTS
53BUILD_INTERRUPT(perf_pending_interrupt, LOCAL_PENDING_VECTOR) 53BUILD_INTERRUPT(perf_pending_interrupt, LOCAL_PENDING_VECTOR)
54#endif 54#endif
55 55
diff --git a/arch/x86/include/asm/perf_counter.h b/arch/x86/include/asm/perf_event.h
index e7b7c938ae27..ad7ce3fd5065 100644
--- a/arch/x86/include/asm/perf_counter.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -1,8 +1,8 @@
1#ifndef _ASM_X86_PERF_COUNTER_H 1#ifndef _ASM_X86_PERF_EVENT_H
2#define _ASM_X86_PERF_COUNTER_H 2#define _ASM_X86_PERF_EVENT_H
3 3
4/* 4/*
5 * Performance counter hw details: 5 * Performance event hw details:
6 */ 6 */
7 7
8#define X86_PMC_MAX_GENERIC 8 8#define X86_PMC_MAX_GENERIC 8
@@ -43,7 +43,7 @@
43union cpuid10_eax { 43union cpuid10_eax {
44 struct { 44 struct {
45 unsigned int version_id:8; 45 unsigned int version_id:8;
46 unsigned int num_counters:8; 46 unsigned int num_events:8;
47 unsigned int bit_width:8; 47 unsigned int bit_width:8;
48 unsigned int mask_length:8; 48 unsigned int mask_length:8;
49 } split; 49 } split;
@@ -52,7 +52,7 @@ union cpuid10_eax {
52 52
53union cpuid10_edx { 53union cpuid10_edx {
54 struct { 54 struct {
55 unsigned int num_counters_fixed:4; 55 unsigned int num_events_fixed:4;
56 unsigned int reserved:28; 56 unsigned int reserved:28;
57 } split; 57 } split;
58 unsigned int full; 58 unsigned int full;
@@ -60,7 +60,7 @@ union cpuid10_edx {
60 60
61 61
62/* 62/*
63 * Fixed-purpose performance counters: 63 * Fixed-purpose performance events:
64 */ 64 */
65 65
66/* 66/*
@@ -87,22 +87,22 @@ union cpuid10_edx {
87/* 87/*
88 * We model BTS tracing as another fixed-mode PMC. 88 * We model BTS tracing as another fixed-mode PMC.
89 * 89 *
90 * We choose a value in the middle of the fixed counter range, since lower 90 * We choose a value in the middle of the fixed event range, since lower
91 * values are used by actual fixed counters and higher values are used 91 * values are used by actual fixed events and higher values are used
92 * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr. 92 * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
93 */ 93 */
94#define X86_PMC_IDX_FIXED_BTS (X86_PMC_IDX_FIXED + 16) 94#define X86_PMC_IDX_FIXED_BTS (X86_PMC_IDX_FIXED + 16)
95 95
96 96
97#ifdef CONFIG_PERF_COUNTERS 97#ifdef CONFIG_PERF_EVENTS
98extern void init_hw_perf_counters(void); 98extern void init_hw_perf_events(void);
99extern void perf_counters_lapic_init(void); 99extern void perf_events_lapic_init(void);
100 100
101#define PERF_COUNTER_INDEX_OFFSET 0 101#define PERF_EVENT_INDEX_OFFSET 0
102 102
103#else 103#else
104static inline void init_hw_perf_counters(void) { } 104static inline void init_hw_perf_events(void) { }
105static inline void perf_counters_lapic_init(void) { } 105static inline void perf_events_lapic_init(void) { }
106#endif 106#endif
107 107
108#endif /* _ASM_X86_PERF_COUNTER_H */ 108#endif /* _ASM_X86_PERF_EVENT_H */
diff --git a/arch/x86/include/asm/unistd_32.h b/arch/x86/include/asm/unistd_32.h
index 8deaada61bc8..6fb3c209a7e3 100644
--- a/arch/x86/include/asm/unistd_32.h
+++ b/arch/x86/include/asm/unistd_32.h
@@ -341,7 +341,7 @@
341#define __NR_preadv 333 341#define __NR_preadv 333
342#define __NR_pwritev 334 342#define __NR_pwritev 334
343#define __NR_rt_tgsigqueueinfo 335 343#define __NR_rt_tgsigqueueinfo 335
344#define __NR_perf_counter_open 336 344#define __NR_perf_event_open 336
345 345
346#ifdef __KERNEL__ 346#ifdef __KERNEL__
347 347
diff --git a/arch/x86/include/asm/unistd_64.h b/arch/x86/include/asm/unistd_64.h
index b9f3c60de5f7..8d3ad0adbc68 100644
--- a/arch/x86/include/asm/unistd_64.h
+++ b/arch/x86/include/asm/unistd_64.h
@@ -659,8 +659,8 @@ __SYSCALL(__NR_preadv, sys_preadv)
659__SYSCALL(__NR_pwritev, sys_pwritev) 659__SYSCALL(__NR_pwritev, sys_pwritev)
660#define __NR_rt_tgsigqueueinfo 297 660#define __NR_rt_tgsigqueueinfo 297
661__SYSCALL(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo) 661__SYSCALL(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo)
662#define __NR_perf_counter_open 298 662#define __NR_perf_event_open 298
663__SYSCALL(__NR_perf_counter_open, sys_perf_counter_open) 663__SYSCALL(__NR_perf_event_open, sys_perf_event_open)
664 664
665#ifndef __NO_STUBS 665#ifndef __NO_STUBS
666#define __ARCH_WANT_OLD_READDIR 666#define __ARCH_WANT_OLD_READDIR
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index a34601f52987..754174d09deb 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -14,7 +14,7 @@
14 * Mikael Pettersson : PM converted to driver model. 14 * Mikael Pettersson : PM converted to driver model.
15 */ 15 */
16 16
17#include <linux/perf_counter.h> 17#include <linux/perf_event.h>
18#include <linux/kernel_stat.h> 18#include <linux/kernel_stat.h>
19#include <linux/mc146818rtc.h> 19#include <linux/mc146818rtc.h>
20#include <linux/acpi_pmtmr.h> 20#include <linux/acpi_pmtmr.h>
@@ -35,7 +35,7 @@
35#include <linux/smp.h> 35#include <linux/smp.h>
36#include <linux/mm.h> 36#include <linux/mm.h>
37 37
38#include <asm/perf_counter.h> 38#include <asm/perf_event.h>
39#include <asm/x86_init.h> 39#include <asm/x86_init.h>
40#include <asm/pgalloc.h> 40#include <asm/pgalloc.h>
41#include <asm/atomic.h> 41#include <asm/atomic.h>
@@ -1189,7 +1189,7 @@ void __cpuinit setup_local_APIC(void)
1189 apic_write(APIC_ESR, 0); 1189 apic_write(APIC_ESR, 0);
1190 } 1190 }
1191#endif 1191#endif
1192 perf_counters_lapic_init(); 1192 perf_events_lapic_init();
1193 1193
1194 preempt_disable(); 1194 preempt_disable();
1195 1195
diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile
index 8dd30638fe44..68537e957a9b 100644
--- a/arch/x86/kernel/cpu/Makefile
+++ b/arch/x86/kernel/cpu/Makefile
@@ -27,7 +27,7 @@ obj-$(CONFIG_CPU_SUP_CENTAUR) += centaur.o
27obj-$(CONFIG_CPU_SUP_TRANSMETA_32) += transmeta.o 27obj-$(CONFIG_CPU_SUP_TRANSMETA_32) += transmeta.o
28obj-$(CONFIG_CPU_SUP_UMC_32) += umc.o 28obj-$(CONFIG_CPU_SUP_UMC_32) += umc.o
29 29
30obj-$(CONFIG_PERF_COUNTERS) += perf_counter.o 30obj-$(CONFIG_PERF_EVENTS) += perf_event.o
31 31
32obj-$(CONFIG_X86_MCE) += mcheck/ 32obj-$(CONFIG_X86_MCE) += mcheck/
33obj-$(CONFIG_MTRR) += mtrr/ 33obj-$(CONFIG_MTRR) += mtrr/
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 2fea97eccf77..cc25c2b4a567 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -13,7 +13,7 @@
13#include <linux/io.h> 13#include <linux/io.h>
14 14
15#include <asm/stackprotector.h> 15#include <asm/stackprotector.h>
16#include <asm/perf_counter.h> 16#include <asm/perf_event.h>
17#include <asm/mmu_context.h> 17#include <asm/mmu_context.h>
18#include <asm/hypervisor.h> 18#include <asm/hypervisor.h>
19#include <asm/processor.h> 19#include <asm/processor.h>
@@ -869,7 +869,7 @@ void __init identify_boot_cpu(void)
869#else 869#else
870 vgetcpu_set_mode(); 870 vgetcpu_set_mode();
871#endif 871#endif
872 init_hw_perf_counters(); 872 init_hw_perf_events();
873} 873}
874 874
875void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) 875void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_event.c
index b1f115696c84..0d03629fb1a5 100644
--- a/arch/x86/kernel/cpu/perf_counter.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Performance counter x86 architecture code 2 * Performance events x86 architecture code
3 * 3 *
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> 4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar 5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
@@ -11,7 +11,7 @@
11 * For licencing details see kernel-base/COPYING 11 * For licencing details see kernel-base/COPYING
12 */ 12 */
13 13
14#include <linux/perf_counter.h> 14#include <linux/perf_event.h>
15#include <linux/capability.h> 15#include <linux/capability.h>
16#include <linux/notifier.h> 16#include <linux/notifier.h>
17#include <linux/hardirq.h> 17#include <linux/hardirq.h>
@@ -27,10 +27,10 @@
27#include <asm/stacktrace.h> 27#include <asm/stacktrace.h>
28#include <asm/nmi.h> 28#include <asm/nmi.h>
29 29
30static u64 perf_counter_mask __read_mostly; 30static u64 perf_event_mask __read_mostly;
31 31
32/* The maximal number of PEBS counters: */ 32/* The maximal number of PEBS events: */
33#define MAX_PEBS_COUNTERS 4 33#define MAX_PEBS_EVENTS 4
34 34
35/* The size of a BTS record in bytes: */ 35/* The size of a BTS record in bytes: */
36#define BTS_RECORD_SIZE 24 36#define BTS_RECORD_SIZE 24
@@ -65,11 +65,11 @@ struct debug_store {
65 u64 pebs_index; 65 u64 pebs_index;
66 u64 pebs_absolute_maximum; 66 u64 pebs_absolute_maximum;
67 u64 pebs_interrupt_threshold; 67 u64 pebs_interrupt_threshold;
68 u64 pebs_counter_reset[MAX_PEBS_COUNTERS]; 68 u64 pebs_event_reset[MAX_PEBS_EVENTS];
69}; 69};
70 70
71struct cpu_hw_counters { 71struct cpu_hw_events {
72 struct perf_counter *counters[X86_PMC_IDX_MAX]; 72 struct perf_event *events[X86_PMC_IDX_MAX];
73 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 73 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
74 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 74 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
75 unsigned long interrupts; 75 unsigned long interrupts;
@@ -86,17 +86,17 @@ struct x86_pmu {
86 int (*handle_irq)(struct pt_regs *); 86 int (*handle_irq)(struct pt_regs *);
87 void (*disable_all)(void); 87 void (*disable_all)(void);
88 void (*enable_all)(void); 88 void (*enable_all)(void);
89 void (*enable)(struct hw_perf_counter *, int); 89 void (*enable)(struct hw_perf_event *, int);
90 void (*disable)(struct hw_perf_counter *, int); 90 void (*disable)(struct hw_perf_event *, int);
91 unsigned eventsel; 91 unsigned eventsel;
92 unsigned perfctr; 92 unsigned perfctr;
93 u64 (*event_map)(int); 93 u64 (*event_map)(int);
94 u64 (*raw_event)(u64); 94 u64 (*raw_event)(u64);
95 int max_events; 95 int max_events;
96 int num_counters; 96 int num_events;
97 int num_counters_fixed; 97 int num_events_fixed;
98 int counter_bits; 98 int event_bits;
99 u64 counter_mask; 99 u64 event_mask;
100 int apic; 100 int apic;
101 u64 max_period; 101 u64 max_period;
102 u64 intel_ctrl; 102 u64 intel_ctrl;
@@ -106,7 +106,7 @@ struct x86_pmu {
106 106
107static struct x86_pmu x86_pmu __read_mostly; 107static struct x86_pmu x86_pmu __read_mostly;
108 108
109static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = { 109static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
110 .enabled = 1, 110 .enabled = 1,
111}; 111};
112 112
@@ -130,12 +130,12 @@ static u64 p6_pmu_event_map(int hw_event)
130} 130}
131 131
132/* 132/*
133 * Counter setting that is specified not to count anything. 133 * Event setting that is specified not to count anything.
134 * We use this to effectively disable a counter. 134 * We use this to effectively disable a counter.
135 * 135 *
136 * L2_RQSTS with 0 MESI unit mask. 136 * L2_RQSTS with 0 MESI unit mask.
137 */ 137 */
138#define P6_NOP_COUNTER 0x0000002EULL 138#define P6_NOP_EVENT 0x0000002EULL
139 139
140static u64 p6_pmu_raw_event(u64 hw_event) 140static u64 p6_pmu_raw_event(u64 hw_event)
141{ 141{
@@ -143,14 +143,14 @@ static u64 p6_pmu_raw_event(u64 hw_event)
143#define P6_EVNTSEL_UNIT_MASK 0x0000FF00ULL 143#define P6_EVNTSEL_UNIT_MASK 0x0000FF00ULL
144#define P6_EVNTSEL_EDGE_MASK 0x00040000ULL 144#define P6_EVNTSEL_EDGE_MASK 0x00040000ULL
145#define P6_EVNTSEL_INV_MASK 0x00800000ULL 145#define P6_EVNTSEL_INV_MASK 0x00800000ULL
146#define P6_EVNTSEL_COUNTER_MASK 0xFF000000ULL 146#define P6_EVNTSEL_REG_MASK 0xFF000000ULL
147 147
148#define P6_EVNTSEL_MASK \ 148#define P6_EVNTSEL_MASK \
149 (P6_EVNTSEL_EVENT_MASK | \ 149 (P6_EVNTSEL_EVENT_MASK | \
150 P6_EVNTSEL_UNIT_MASK | \ 150 P6_EVNTSEL_UNIT_MASK | \
151 P6_EVNTSEL_EDGE_MASK | \ 151 P6_EVNTSEL_EDGE_MASK | \
152 P6_EVNTSEL_INV_MASK | \ 152 P6_EVNTSEL_INV_MASK | \
153 P6_EVNTSEL_COUNTER_MASK) 153 P6_EVNTSEL_REG_MASK)
154 154
155 return hw_event & P6_EVNTSEL_MASK; 155 return hw_event & P6_EVNTSEL_MASK;
156} 156}
@@ -469,14 +469,14 @@ static u64 intel_pmu_raw_event(u64 hw_event)
469#define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL 469#define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL
470#define CORE_EVNTSEL_EDGE_MASK 0x00040000ULL 470#define CORE_EVNTSEL_EDGE_MASK 0x00040000ULL
471#define CORE_EVNTSEL_INV_MASK 0x00800000ULL 471#define CORE_EVNTSEL_INV_MASK 0x00800000ULL
472#define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL 472#define CORE_EVNTSEL_REG_MASK 0xFF000000ULL
473 473
474#define CORE_EVNTSEL_MASK \ 474#define CORE_EVNTSEL_MASK \
475 (CORE_EVNTSEL_EVENT_MASK | \ 475 (CORE_EVNTSEL_EVENT_MASK | \
476 CORE_EVNTSEL_UNIT_MASK | \ 476 CORE_EVNTSEL_UNIT_MASK | \
477 CORE_EVNTSEL_EDGE_MASK | \ 477 CORE_EVNTSEL_EDGE_MASK | \
478 CORE_EVNTSEL_INV_MASK | \ 478 CORE_EVNTSEL_INV_MASK | \
479 CORE_EVNTSEL_COUNTER_MASK) 479 CORE_EVNTSEL_REG_MASK)
480 480
481 return hw_event & CORE_EVNTSEL_MASK; 481 return hw_event & CORE_EVNTSEL_MASK;
482} 482}
@@ -596,28 +596,28 @@ static u64 amd_pmu_raw_event(u64 hw_event)
596#define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL 596#define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL
597#define K7_EVNTSEL_EDGE_MASK 0x000040000ULL 597#define K7_EVNTSEL_EDGE_MASK 0x000040000ULL
598#define K7_EVNTSEL_INV_MASK 0x000800000ULL 598#define K7_EVNTSEL_INV_MASK 0x000800000ULL
599#define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL 599#define K7_EVNTSEL_REG_MASK 0x0FF000000ULL
600 600
601#define K7_EVNTSEL_MASK \ 601#define K7_EVNTSEL_MASK \
602 (K7_EVNTSEL_EVENT_MASK | \ 602 (K7_EVNTSEL_EVENT_MASK | \
603 K7_EVNTSEL_UNIT_MASK | \ 603 K7_EVNTSEL_UNIT_MASK | \
604 K7_EVNTSEL_EDGE_MASK | \ 604 K7_EVNTSEL_EDGE_MASK | \
605 K7_EVNTSEL_INV_MASK | \ 605 K7_EVNTSEL_INV_MASK | \
606 K7_EVNTSEL_COUNTER_MASK) 606 K7_EVNTSEL_REG_MASK)
607 607
608 return hw_event & K7_EVNTSEL_MASK; 608 return hw_event & K7_EVNTSEL_MASK;
609} 609}
610 610
611/* 611/*
612 * Propagate counter elapsed time into the generic counter. 612 * Propagate event elapsed time into the generic event.
613 * Can only be executed on the CPU where the counter is active. 613 * Can only be executed on the CPU where the event is active.
614 * Returns the delta events processed. 614 * Returns the delta events processed.
615 */ 615 */
616static u64 616static u64
617x86_perf_counter_update(struct perf_counter *counter, 617x86_perf_event_update(struct perf_event *event,
618 struct hw_perf_counter *hwc, int idx) 618 struct hw_perf_event *hwc, int idx)
619{ 619{
620 int shift = 64 - x86_pmu.counter_bits; 620 int shift = 64 - x86_pmu.event_bits;
621 u64 prev_raw_count, new_raw_count; 621 u64 prev_raw_count, new_raw_count;
622 s64 delta; 622 s64 delta;
623 623
@@ -625,15 +625,15 @@ x86_perf_counter_update(struct perf_counter *counter,
625 return 0; 625 return 0;
626 626
627 /* 627 /*
628 * Careful: an NMI might modify the previous counter value. 628 * Careful: an NMI might modify the previous event value.
629 * 629 *
630 * Our tactic to handle this is to first atomically read and 630 * Our tactic to handle this is to first atomically read and
631 * exchange a new raw count - then add that new-prev delta 631 * exchange a new raw count - then add that new-prev delta
632 * count to the generic counter atomically: 632 * count to the generic event atomically:
633 */ 633 */
634again: 634again:
635 prev_raw_count = atomic64_read(&hwc->prev_count); 635 prev_raw_count = atomic64_read(&hwc->prev_count);
636 rdmsrl(hwc->counter_base + idx, new_raw_count); 636 rdmsrl(hwc->event_base + idx, new_raw_count);
637 637
638 if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count, 638 if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
639 new_raw_count) != prev_raw_count) 639 new_raw_count) != prev_raw_count)
@@ -642,7 +642,7 @@ again:
642 /* 642 /*
643 * Now we have the new raw value and have updated the prev 643 * Now we have the new raw value and have updated the prev
644 * timestamp already. We can now calculate the elapsed delta 644 * timestamp already. We can now calculate the elapsed delta
645 * (counter-)time and add that to the generic counter. 645 * (event-)time and add that to the generic event.
646 * 646 *
647 * Careful, not all hw sign-extends above the physical width 647 * Careful, not all hw sign-extends above the physical width
648 * of the count. 648 * of the count.
@@ -650,13 +650,13 @@ again:
650 delta = (new_raw_count << shift) - (prev_raw_count << shift); 650 delta = (new_raw_count << shift) - (prev_raw_count << shift);
651 delta >>= shift; 651 delta >>= shift;
652 652
653 atomic64_add(delta, &counter->count); 653 atomic64_add(delta, &event->count);
654 atomic64_sub(delta, &hwc->period_left); 654 atomic64_sub(delta, &hwc->period_left);
655 655
656 return new_raw_count; 656 return new_raw_count;
657} 657}
658 658
659static atomic_t active_counters; 659static atomic_t active_events;
660static DEFINE_MUTEX(pmc_reserve_mutex); 660static DEFINE_MUTEX(pmc_reserve_mutex);
661 661
662static bool reserve_pmc_hardware(void) 662static bool reserve_pmc_hardware(void)
@@ -667,12 +667,12 @@ static bool reserve_pmc_hardware(void)
667 if (nmi_watchdog == NMI_LOCAL_APIC) 667 if (nmi_watchdog == NMI_LOCAL_APIC)
668 disable_lapic_nmi_watchdog(); 668 disable_lapic_nmi_watchdog();
669 669
670 for (i = 0; i < x86_pmu.num_counters; i++) { 670 for (i = 0; i < x86_pmu.num_events; i++) {
671 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i)) 671 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
672 goto perfctr_fail; 672 goto perfctr_fail;
673 } 673 }
674 674
675 for (i = 0; i < x86_pmu.num_counters; i++) { 675 for (i = 0; i < x86_pmu.num_events; i++) {
676 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i)) 676 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
677 goto eventsel_fail; 677 goto eventsel_fail;
678 } 678 }
@@ -685,7 +685,7 @@ eventsel_fail:
685 for (i--; i >= 0; i--) 685 for (i--; i >= 0; i--)
686 release_evntsel_nmi(x86_pmu.eventsel + i); 686 release_evntsel_nmi(x86_pmu.eventsel + i);
687 687
688 i = x86_pmu.num_counters; 688 i = x86_pmu.num_events;
689 689
690perfctr_fail: 690perfctr_fail:
691 for (i--; i >= 0; i--) 691 for (i--; i >= 0; i--)
@@ -703,7 +703,7 @@ static void release_pmc_hardware(void)
703#ifdef CONFIG_X86_LOCAL_APIC 703#ifdef CONFIG_X86_LOCAL_APIC
704 int i; 704 int i;
705 705
706 for (i = 0; i < x86_pmu.num_counters; i++) { 706 for (i = 0; i < x86_pmu.num_events; i++) {
707 release_perfctr_nmi(x86_pmu.perfctr + i); 707 release_perfctr_nmi(x86_pmu.perfctr + i);
708 release_evntsel_nmi(x86_pmu.eventsel + i); 708 release_evntsel_nmi(x86_pmu.eventsel + i);
709 } 709 }
@@ -720,7 +720,7 @@ static inline bool bts_available(void)
720 720
721static inline void init_debug_store_on_cpu(int cpu) 721static inline void init_debug_store_on_cpu(int cpu)
722{ 722{
723 struct debug_store *ds = per_cpu(cpu_hw_counters, cpu).ds; 723 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
724 724
725 if (!ds) 725 if (!ds)
726 return; 726 return;
@@ -732,7 +732,7 @@ static inline void init_debug_store_on_cpu(int cpu)
732 732
733static inline void fini_debug_store_on_cpu(int cpu) 733static inline void fini_debug_store_on_cpu(int cpu)
734{ 734{
735 if (!per_cpu(cpu_hw_counters, cpu).ds) 735 if (!per_cpu(cpu_hw_events, cpu).ds)
736 return; 736 return;
737 737
738 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0); 738 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
@@ -751,12 +751,12 @@ static void release_bts_hardware(void)
751 fini_debug_store_on_cpu(cpu); 751 fini_debug_store_on_cpu(cpu);
752 752
753 for_each_possible_cpu(cpu) { 753 for_each_possible_cpu(cpu) {
754 struct debug_store *ds = per_cpu(cpu_hw_counters, cpu).ds; 754 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
755 755
756 if (!ds) 756 if (!ds)
757 continue; 757 continue;
758 758
759 per_cpu(cpu_hw_counters, cpu).ds = NULL; 759 per_cpu(cpu_hw_events, cpu).ds = NULL;
760 760
761 kfree((void *)(unsigned long)ds->bts_buffer_base); 761 kfree((void *)(unsigned long)ds->bts_buffer_base);
762 kfree(ds); 762 kfree(ds);
@@ -796,7 +796,7 @@ static int reserve_bts_hardware(void)
796 ds->bts_interrupt_threshold = 796 ds->bts_interrupt_threshold =
797 ds->bts_absolute_maximum - BTS_OVFL_TH; 797 ds->bts_absolute_maximum - BTS_OVFL_TH;
798 798
799 per_cpu(cpu_hw_counters, cpu).ds = ds; 799 per_cpu(cpu_hw_events, cpu).ds = ds;
800 err = 0; 800 err = 0;
801 } 801 }
802 802
@@ -812,9 +812,9 @@ static int reserve_bts_hardware(void)
812 return err; 812 return err;
813} 813}
814 814
815static void hw_perf_counter_destroy(struct perf_counter *counter) 815static void hw_perf_event_destroy(struct perf_event *event)
816{ 816{
817 if (atomic_dec_and_mutex_lock(&active_counters, &pmc_reserve_mutex)) { 817 if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
818 release_pmc_hardware(); 818 release_pmc_hardware();
819 release_bts_hardware(); 819 release_bts_hardware();
820 mutex_unlock(&pmc_reserve_mutex); 820 mutex_unlock(&pmc_reserve_mutex);
@@ -827,7 +827,7 @@ static inline int x86_pmu_initialized(void)
827} 827}
828 828
829static inline int 829static inline int
830set_ext_hw_attr(struct hw_perf_counter *hwc, struct perf_counter_attr *attr) 830set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
831{ 831{
832 unsigned int cache_type, cache_op, cache_result; 832 unsigned int cache_type, cache_op, cache_result;
833 u64 config, val; 833 u64 config, val;
@@ -880,7 +880,7 @@ static void intel_pmu_enable_bts(u64 config)
880 880
881static void intel_pmu_disable_bts(void) 881static void intel_pmu_disable_bts(void)
882{ 882{
883 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); 883 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
884 unsigned long debugctlmsr; 884 unsigned long debugctlmsr;
885 885
886 if (!cpuc->ds) 886 if (!cpuc->ds)
@@ -898,10 +898,10 @@ static void intel_pmu_disable_bts(void)
898/* 898/*
899 * Setup the hardware configuration for a given attr_type 899 * Setup the hardware configuration for a given attr_type
900 */ 900 */
901static int __hw_perf_counter_init(struct perf_counter *counter) 901static int __hw_perf_event_init(struct perf_event *event)
902{ 902{
903 struct perf_counter_attr *attr = &counter->attr; 903 struct perf_event_attr *attr = &event->attr;
904 struct hw_perf_counter *hwc = &counter->hw; 904 struct hw_perf_event *hwc = &event->hw;
905 u64 config; 905 u64 config;
906 int err; 906 int err;
907 907
@@ -909,22 +909,22 @@ static int __hw_perf_counter_init(struct perf_counter *counter)
909 return -ENODEV; 909 return -ENODEV;
910 910
911 err = 0; 911 err = 0;
912 if (!atomic_inc_not_zero(&active_counters)) { 912 if (!atomic_inc_not_zero(&active_events)) {
913 mutex_lock(&pmc_reserve_mutex); 913 mutex_lock(&pmc_reserve_mutex);
914 if (atomic_read(&active_counters) == 0) { 914 if (atomic_read(&active_events) == 0) {
915 if (!reserve_pmc_hardware()) 915 if (!reserve_pmc_hardware())
916 err = -EBUSY; 916 err = -EBUSY;
917 else 917 else
918 err = reserve_bts_hardware(); 918 err = reserve_bts_hardware();
919 } 919 }
920 if (!err) 920 if (!err)
921 atomic_inc(&active_counters); 921 atomic_inc(&active_events);
922 mutex_unlock(&pmc_reserve_mutex); 922 mutex_unlock(&pmc_reserve_mutex);
923 } 923 }
924 if (err) 924 if (err)
925 return err; 925 return err;
926 926
927 counter->destroy = hw_perf_counter_destroy; 927 event->destroy = hw_perf_event_destroy;
928 928
929 /* 929 /*
930 * Generate PMC IRQs: 930 * Generate PMC IRQs:
@@ -948,8 +948,8 @@ static int __hw_perf_counter_init(struct perf_counter *counter)
948 /* 948 /*
949 * If we have a PMU initialized but no APIC 949 * If we have a PMU initialized but no APIC
950 * interrupts, we cannot sample hardware 950 * interrupts, we cannot sample hardware
951 * counters (user-space has to fall back and 951 * events (user-space has to fall back and
952 * sample via a hrtimer based software counter): 952 * sample via a hrtimer based software event):
953 */ 953 */
954 if (!x86_pmu.apic) 954 if (!x86_pmu.apic)
955 return -EOPNOTSUPP; 955 return -EOPNOTSUPP;
@@ -1001,7 +1001,7 @@ static int __hw_perf_counter_init(struct perf_counter *counter)
1001 1001
1002static void p6_pmu_disable_all(void) 1002static void p6_pmu_disable_all(void)
1003{ 1003{
1004 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); 1004 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1005 u64 val; 1005 u64 val;
1006 1006
1007 if (!cpuc->enabled) 1007 if (!cpuc->enabled)
@@ -1018,7 +1018,7 @@ static void p6_pmu_disable_all(void)
1018 1018
1019static void intel_pmu_disable_all(void) 1019static void intel_pmu_disable_all(void)
1020{ 1020{
1021 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); 1021 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1022 1022
1023 if (!cpuc->enabled) 1023 if (!cpuc->enabled)
1024 return; 1024 return;
@@ -1034,7 +1034,7 @@ static void intel_pmu_disable_all(void)
1034 1034
1035static void amd_pmu_disable_all(void) 1035static void amd_pmu_disable_all(void)
1036{ 1036{
1037 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); 1037 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1038 int idx; 1038 int idx;
1039 1039
1040 if (!cpuc->enabled) 1040 if (!cpuc->enabled)
@@ -1043,12 +1043,12 @@ static void amd_pmu_disable_all(void)
1043 cpuc->enabled = 0; 1043 cpuc->enabled = 0;
1044 /* 1044 /*
1045 * ensure we write the disable before we start disabling the 1045 * ensure we write the disable before we start disabling the
1046 * counters proper, so that amd_pmu_enable_counter() does the 1046 * events proper, so that amd_pmu_enable_event() does the
1047 * right thing. 1047 * right thing.
1048 */ 1048 */
1049 barrier(); 1049 barrier();
1050 1050
1051 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 1051 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1052 u64 val; 1052 u64 val;
1053 1053
1054 if (!test_bit(idx, cpuc->active_mask)) 1054 if (!test_bit(idx, cpuc->active_mask))
@@ -1070,7 +1070,7 @@ void hw_perf_disable(void)
1070 1070
1071static void p6_pmu_enable_all(void) 1071static void p6_pmu_enable_all(void)
1072{ 1072{
1073 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); 1073 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1074 unsigned long val; 1074 unsigned long val;
1075 1075
1076 if (cpuc->enabled) 1076 if (cpuc->enabled)
@@ -1087,7 +1087,7 @@ static void p6_pmu_enable_all(void)
1087 1087
1088static void intel_pmu_enable_all(void) 1088static void intel_pmu_enable_all(void)
1089{ 1089{
1090 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); 1090 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1091 1091
1092 if (cpuc->enabled) 1092 if (cpuc->enabled)
1093 return; 1093 return;
@@ -1098,19 +1098,19 @@ static void intel_pmu_enable_all(void)
1098 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl); 1098 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
1099 1099
1100 if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { 1100 if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
1101 struct perf_counter *counter = 1101 struct perf_event *event =
1102 cpuc->counters[X86_PMC_IDX_FIXED_BTS]; 1102 cpuc->events[X86_PMC_IDX_FIXED_BTS];
1103 1103
1104 if (WARN_ON_ONCE(!counter)) 1104 if (WARN_ON_ONCE(!event))
1105 return; 1105 return;
1106 1106
1107 intel_pmu_enable_bts(counter->hw.config); 1107 intel_pmu_enable_bts(event->hw.config);
1108 } 1108 }
1109} 1109}
1110 1110
1111static void amd_pmu_enable_all(void) 1111static void amd_pmu_enable_all(void)
1112{ 1112{
1113 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); 1113 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1114 int idx; 1114 int idx;
1115 1115
1116 if (cpuc->enabled) 1116 if (cpuc->enabled)
@@ -1119,14 +1119,14 @@ static void amd_pmu_enable_all(void)
1119 cpuc->enabled = 1; 1119 cpuc->enabled = 1;
1120 barrier(); 1120 barrier();
1121 1121
1122 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 1122 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1123 struct perf_counter *counter = cpuc->counters[idx]; 1123 struct perf_event *event = cpuc->events[idx];
1124 u64 val; 1124 u64 val;
1125 1125
1126 if (!test_bit(idx, cpuc->active_mask)) 1126 if (!test_bit(idx, cpuc->active_mask))
1127 continue; 1127 continue;
1128 1128
1129 val = counter->hw.config; 1129 val = event->hw.config;
1130 val |= ARCH_PERFMON_EVENTSEL0_ENABLE; 1130 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
1131 wrmsrl(MSR_K7_EVNTSEL0 + idx, val); 1131 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
1132 } 1132 }
@@ -1153,19 +1153,19 @@ static inline void intel_pmu_ack_status(u64 ack)
1153 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); 1153 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1154} 1154}
1155 1155
1156static inline void x86_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) 1156static inline void x86_pmu_enable_event(struct hw_perf_event *hwc, int idx)
1157{ 1157{
1158 (void)checking_wrmsrl(hwc->config_base + idx, 1158 (void)checking_wrmsrl(hwc->config_base + idx,
1159 hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE); 1159 hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE);
1160} 1160}
1161 1161
1162static inline void x86_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) 1162static inline void x86_pmu_disable_event(struct hw_perf_event *hwc, int idx)
1163{ 1163{
1164 (void)checking_wrmsrl(hwc->config_base + idx, hwc->config); 1164 (void)checking_wrmsrl(hwc->config_base + idx, hwc->config);
1165} 1165}
1166 1166
1167static inline void 1167static inline void
1168intel_pmu_disable_fixed(struct hw_perf_counter *hwc, int __idx) 1168intel_pmu_disable_fixed(struct hw_perf_event *hwc, int __idx)
1169{ 1169{
1170 int idx = __idx - X86_PMC_IDX_FIXED; 1170 int idx = __idx - X86_PMC_IDX_FIXED;
1171 u64 ctrl_val, mask; 1171 u64 ctrl_val, mask;
@@ -1178,10 +1178,10 @@ intel_pmu_disable_fixed(struct hw_perf_counter *hwc, int __idx)
1178} 1178}
1179 1179
1180static inline void 1180static inline void
1181p6_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) 1181p6_pmu_disable_event(struct hw_perf_event *hwc, int idx)
1182{ 1182{
1183 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); 1183 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1184 u64 val = P6_NOP_COUNTER; 1184 u64 val = P6_NOP_EVENT;
1185 1185
1186 if (cpuc->enabled) 1186 if (cpuc->enabled)
1187 val |= ARCH_PERFMON_EVENTSEL0_ENABLE; 1187 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
@@ -1190,7 +1190,7 @@ p6_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
1190} 1190}
1191 1191
1192static inline void 1192static inline void
1193intel_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) 1193intel_pmu_disable_event(struct hw_perf_event *hwc, int idx)
1194{ 1194{
1195 if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) { 1195 if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) {
1196 intel_pmu_disable_bts(); 1196 intel_pmu_disable_bts();
@@ -1202,24 +1202,24 @@ intel_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
1202 return; 1202 return;
1203 } 1203 }
1204 1204
1205 x86_pmu_disable_counter(hwc, idx); 1205 x86_pmu_disable_event(hwc, idx);
1206} 1206}
1207 1207
1208static inline void 1208static inline void
1209amd_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) 1209amd_pmu_disable_event(struct hw_perf_event *hwc, int idx)
1210{ 1210{
1211 x86_pmu_disable_counter(hwc, idx); 1211 x86_pmu_disable_event(hwc, idx);
1212} 1212}
1213 1213
1214static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); 1214static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1215 1215
1216/* 1216/*
1217 * Set the next IRQ period, based on the hwc->period_left value. 1217 * Set the next IRQ period, based on the hwc->period_left value.
1218 * To be called with the counter disabled in hw: 1218 * To be called with the event disabled in hw:
1219 */ 1219 */
1220static int 1220static int
1221x86_perf_counter_set_period(struct perf_counter *counter, 1221x86_perf_event_set_period(struct perf_event *event,
1222 struct hw_perf_counter *hwc, int idx) 1222 struct hw_perf_event *hwc, int idx)
1223{ 1223{
1224 s64 left = atomic64_read(&hwc->period_left); 1224 s64 left = atomic64_read(&hwc->period_left);
1225 s64 period = hwc->sample_period; 1225 s64 period = hwc->sample_period;
@@ -1256,21 +1256,21 @@ x86_perf_counter_set_period(struct perf_counter *counter,
1256 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; 1256 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1257 1257
1258 /* 1258 /*
1259 * The hw counter starts counting from this counter offset, 1259 * The hw event starts counting from this event offset,
1260 * mark it to be able to extra future deltas: 1260 * mark it to be able to extra future deltas:
1261 */ 1261 */
1262 atomic64_set(&hwc->prev_count, (u64)-left); 1262 atomic64_set(&hwc->prev_count, (u64)-left);
1263 1263
1264 err = checking_wrmsrl(hwc->counter_base + idx, 1264 err = checking_wrmsrl(hwc->event_base + idx,
1265 (u64)(-left) & x86_pmu.counter_mask); 1265 (u64)(-left) & x86_pmu.event_mask);
1266 1266
1267 perf_counter_update_userpage(counter); 1267 perf_event_update_userpage(event);
1268 1268
1269 return ret; 1269 return ret;
1270} 1270}
1271 1271
1272static inline void 1272static inline void
1273intel_pmu_enable_fixed(struct hw_perf_counter *hwc, int __idx) 1273intel_pmu_enable_fixed(struct hw_perf_event *hwc, int __idx)
1274{ 1274{
1275 int idx = __idx - X86_PMC_IDX_FIXED; 1275 int idx = __idx - X86_PMC_IDX_FIXED;
1276 u64 ctrl_val, bits, mask; 1276 u64 ctrl_val, bits, mask;
@@ -1295,9 +1295,9 @@ intel_pmu_enable_fixed(struct hw_perf_counter *hwc, int __idx)
1295 err = checking_wrmsrl(hwc->config_base, ctrl_val); 1295 err = checking_wrmsrl(hwc->config_base, ctrl_val);
1296} 1296}
1297 1297
1298static void p6_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) 1298static void p6_pmu_enable_event(struct hw_perf_event *hwc, int idx)
1299{ 1299{
1300 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); 1300 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1301 u64 val; 1301 u64 val;
1302 1302
1303 val = hwc->config; 1303 val = hwc->config;
@@ -1308,10 +1308,10 @@ static void p6_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
1308} 1308}
1309 1309
1310 1310
1311static void intel_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) 1311static void intel_pmu_enable_event(struct hw_perf_event *hwc, int idx)
1312{ 1312{
1313 if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) { 1313 if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) {
1314 if (!__get_cpu_var(cpu_hw_counters).enabled) 1314 if (!__get_cpu_var(cpu_hw_events).enabled)
1315 return; 1315 return;
1316 1316
1317 intel_pmu_enable_bts(hwc->config); 1317 intel_pmu_enable_bts(hwc->config);
@@ -1323,19 +1323,19 @@ static void intel_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
1323 return; 1323 return;
1324 } 1324 }
1325 1325
1326 x86_pmu_enable_counter(hwc, idx); 1326 x86_pmu_enable_event(hwc, idx);
1327} 1327}
1328 1328
1329static void amd_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) 1329static void amd_pmu_enable_event(struct hw_perf_event *hwc, int idx)
1330{ 1330{
1331 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); 1331 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1332 1332
1333 if (cpuc->enabled) 1333 if (cpuc->enabled)
1334 x86_pmu_enable_counter(hwc, idx); 1334 x86_pmu_enable_event(hwc, idx);
1335} 1335}
1336 1336
1337static int 1337static int
1338fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc) 1338fixed_mode_idx(struct perf_event *event, struct hw_perf_event *hwc)
1339{ 1339{
1340 unsigned int hw_event; 1340 unsigned int hw_event;
1341 1341
@@ -1346,7 +1346,7 @@ fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc)
1346 (hwc->sample_period == 1))) 1346 (hwc->sample_period == 1)))
1347 return X86_PMC_IDX_FIXED_BTS; 1347 return X86_PMC_IDX_FIXED_BTS;
1348 1348
1349 if (!x86_pmu.num_counters_fixed) 1349 if (!x86_pmu.num_events_fixed)
1350 return -1; 1350 return -1;
1351 1351
1352 if (unlikely(hw_event == x86_pmu.event_map(PERF_COUNT_HW_INSTRUCTIONS))) 1352 if (unlikely(hw_event == x86_pmu.event_map(PERF_COUNT_HW_INSTRUCTIONS)))
@@ -1360,97 +1360,97 @@ fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc)
1360} 1360}
1361 1361
1362/* 1362/*
1363 * Find a PMC slot for the freshly enabled / scheduled in counter: 1363 * Find a PMC slot for the freshly enabled / scheduled in event:
1364 */ 1364 */
1365static int x86_pmu_enable(struct perf_counter *counter) 1365static int x86_pmu_enable(struct perf_event *event)
1366{ 1366{
1367 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); 1367 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1368 struct hw_perf_counter *hwc = &counter->hw; 1368 struct hw_perf_event *hwc = &event->hw;
1369 int idx; 1369 int idx;
1370 1370
1371 idx = fixed_mode_idx(counter, hwc); 1371 idx = fixed_mode_idx(event, hwc);
1372 if (idx == X86_PMC_IDX_FIXED_BTS) { 1372 if (idx == X86_PMC_IDX_FIXED_BTS) {
1373 /* BTS is already occupied. */ 1373 /* BTS is already occupied. */
1374 if (test_and_set_bit(idx, cpuc->used_mask)) 1374 if (test_and_set_bit(idx, cpuc->used_mask))
1375 return -EAGAIN; 1375 return -EAGAIN;
1376 1376
1377 hwc->config_base = 0; 1377 hwc->config_base = 0;
1378 hwc->counter_base = 0; 1378 hwc->event_base = 0;
1379 hwc->idx = idx; 1379 hwc->idx = idx;
1380 } else if (idx >= 0) { 1380 } else if (idx >= 0) {
1381 /* 1381 /*
1382 * Try to get the fixed counter, if that is already taken 1382 * Try to get the fixed event, if that is already taken
1383 * then try to get a generic counter: 1383 * then try to get a generic event:
1384 */ 1384 */
1385 if (test_and_set_bit(idx, cpuc->used_mask)) 1385 if (test_and_set_bit(idx, cpuc->used_mask))
1386 goto try_generic; 1386 goto try_generic;
1387 1387
1388 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; 1388 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
1389 /* 1389 /*
1390 * We set it so that counter_base + idx in wrmsr/rdmsr maps to 1390 * We set it so that event_base + idx in wrmsr/rdmsr maps to
1391 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2: 1391 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
1392 */ 1392 */
1393 hwc->counter_base = 1393 hwc->event_base =
1394 MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED; 1394 MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
1395 hwc->idx = idx; 1395 hwc->idx = idx;
1396 } else { 1396 } else {
1397 idx = hwc->idx; 1397 idx = hwc->idx;
1398 /* Try to get the previous generic counter again */ 1398 /* Try to get the previous generic event again */
1399 if (test_and_set_bit(idx, cpuc->used_mask)) { 1399 if (test_and_set_bit(idx, cpuc->used_mask)) {
1400try_generic: 1400try_generic:
1401 idx = find_first_zero_bit(cpuc->used_mask, 1401 idx = find_first_zero_bit(cpuc->used_mask,
1402 x86_pmu.num_counters); 1402 x86_pmu.num_events);
1403 if (idx == x86_pmu.num_counters) 1403 if (idx == x86_pmu.num_events)
1404 return -EAGAIN; 1404 return -EAGAIN;
1405 1405
1406 set_bit(idx, cpuc->used_mask); 1406 set_bit(idx, cpuc->used_mask);
1407 hwc->idx = idx; 1407 hwc->idx = idx;
1408 } 1408 }
1409 hwc->config_base = x86_pmu.eventsel; 1409 hwc->config_base = x86_pmu.eventsel;
1410 hwc->counter_base = x86_pmu.perfctr; 1410 hwc->event_base = x86_pmu.perfctr;
1411 } 1411 }
1412 1412
1413 perf_counters_lapic_init(); 1413 perf_events_lapic_init();
1414 1414
1415 x86_pmu.disable(hwc, idx); 1415 x86_pmu.disable(hwc, idx);
1416 1416
1417 cpuc->counters[idx] = counter; 1417 cpuc->events[idx] = event;
1418 set_bit(idx, cpuc->active_mask); 1418 set_bit(idx, cpuc->active_mask);
1419 1419
1420 x86_perf_counter_set_period(counter, hwc, idx); 1420 x86_perf_event_set_period(event, hwc, idx);
1421 x86_pmu.enable(hwc, idx); 1421 x86_pmu.enable(hwc, idx);
1422 1422
1423 perf_counter_update_userpage(counter); 1423 perf_event_update_userpage(event);
1424 1424
1425 return 0; 1425 return 0;
1426} 1426}
1427 1427
1428static void x86_pmu_unthrottle(struct perf_counter *counter) 1428static void x86_pmu_unthrottle(struct perf_event *event)
1429{ 1429{
1430 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); 1430 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1431 struct hw_perf_counter *hwc = &counter->hw; 1431 struct hw_perf_event *hwc = &event->hw;
1432 1432
1433 if (WARN_ON_ONCE(hwc->idx >= X86_PMC_IDX_MAX || 1433 if (WARN_ON_ONCE(hwc->idx >= X86_PMC_IDX_MAX ||
1434 cpuc->counters[hwc->idx] != counter)) 1434 cpuc->events[hwc->idx] != event))
1435 return; 1435 return;
1436 1436
1437 x86_pmu.enable(hwc, hwc->idx); 1437 x86_pmu.enable(hwc, hwc->idx);
1438} 1438}
1439 1439
1440void perf_counter_print_debug(void) 1440void perf_event_print_debug(void)
1441{ 1441{
1442 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; 1442 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1443 struct cpu_hw_counters *cpuc; 1443 struct cpu_hw_events *cpuc;
1444 unsigned long flags; 1444 unsigned long flags;
1445 int cpu, idx; 1445 int cpu, idx;
1446 1446
1447 if (!x86_pmu.num_counters) 1447 if (!x86_pmu.num_events)
1448 return; 1448 return;
1449 1449
1450 local_irq_save(flags); 1450 local_irq_save(flags);
1451 1451
1452 cpu = smp_processor_id(); 1452 cpu = smp_processor_id();
1453 cpuc = &per_cpu(cpu_hw_counters, cpu); 1453 cpuc = &per_cpu(cpu_hw_events, cpu);
1454 1454
1455 if (x86_pmu.version >= 2) { 1455 if (x86_pmu.version >= 2) {
1456 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); 1456 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
@@ -1466,7 +1466,7 @@ void perf_counter_print_debug(void)
1466 } 1466 }
1467 pr_info("CPU#%d: used: %016llx\n", cpu, *(u64 *)cpuc->used_mask); 1467 pr_info("CPU#%d: used: %016llx\n", cpu, *(u64 *)cpuc->used_mask);
1468 1468
1469 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 1469 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1470 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl); 1470 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1471 rdmsrl(x86_pmu.perfctr + idx, pmc_count); 1471 rdmsrl(x86_pmu.perfctr + idx, pmc_count);
1472 1472
@@ -1479,7 +1479,7 @@ void perf_counter_print_debug(void)
1479 pr_info("CPU#%d: gen-PMC%d left: %016llx\n", 1479 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1480 cpu, idx, prev_left); 1480 cpu, idx, prev_left);
1481 } 1481 }
1482 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { 1482 for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) {
1483 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); 1483 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1484 1484
1485 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", 1485 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
@@ -1488,7 +1488,7 @@ void perf_counter_print_debug(void)
1488 local_irq_restore(flags); 1488 local_irq_restore(flags);
1489} 1489}
1490 1490
1491static void intel_pmu_drain_bts_buffer(struct cpu_hw_counters *cpuc) 1491static void intel_pmu_drain_bts_buffer(struct cpu_hw_events *cpuc)
1492{ 1492{
1493 struct debug_store *ds = cpuc->ds; 1493 struct debug_store *ds = cpuc->ds;
1494 struct bts_record { 1494 struct bts_record {
@@ -1496,14 +1496,14 @@ static void intel_pmu_drain_bts_buffer(struct cpu_hw_counters *cpuc)
1496 u64 to; 1496 u64 to;
1497 u64 flags; 1497 u64 flags;
1498 }; 1498 };
1499 struct perf_counter *counter = cpuc->counters[X86_PMC_IDX_FIXED_BTS]; 1499 struct perf_event *event = cpuc->events[X86_PMC_IDX_FIXED_BTS];
1500 struct bts_record *at, *top; 1500 struct bts_record *at, *top;
1501 struct perf_output_handle handle; 1501 struct perf_output_handle handle;
1502 struct perf_event_header header; 1502 struct perf_event_header header;
1503 struct perf_sample_data data; 1503 struct perf_sample_data data;
1504 struct pt_regs regs; 1504 struct pt_regs regs;
1505 1505
1506 if (!counter) 1506 if (!event)
1507 return; 1507 return;
1508 1508
1509 if (!ds) 1509 if (!ds)
@@ -1518,7 +1518,7 @@ static void intel_pmu_drain_bts_buffer(struct cpu_hw_counters *cpuc)
1518 ds->bts_index = ds->bts_buffer_base; 1518 ds->bts_index = ds->bts_buffer_base;
1519 1519
1520 1520
1521 data.period = counter->hw.last_period; 1521 data.period = event->hw.last_period;
1522 data.addr = 0; 1522 data.addr = 0;
1523 regs.ip = 0; 1523 regs.ip = 0;
1524 1524
@@ -1527,9 +1527,9 @@ static void intel_pmu_drain_bts_buffer(struct cpu_hw_counters *cpuc)
1527 * We will overwrite the from and to address before we output 1527 * We will overwrite the from and to address before we output
1528 * the sample. 1528 * the sample.
1529 */ 1529 */
1530 perf_prepare_sample(&header, &data, counter, &regs); 1530 perf_prepare_sample(&header, &data, event, &regs);
1531 1531
1532 if (perf_output_begin(&handle, counter, 1532 if (perf_output_begin(&handle, event,
1533 header.size * (top - at), 1, 1)) 1533 header.size * (top - at), 1, 1))
1534 return; 1534 return;
1535 1535
@@ -1537,20 +1537,20 @@ static void intel_pmu_drain_bts_buffer(struct cpu_hw_counters *cpuc)
1537 data.ip = at->from; 1537 data.ip = at->from;
1538 data.addr = at->to; 1538 data.addr = at->to;
1539 1539
1540 perf_output_sample(&handle, &header, &data, counter); 1540 perf_output_sample(&handle, &header, &data, event);
1541 } 1541 }
1542 1542
1543 perf_output_end(&handle); 1543 perf_output_end(&handle);
1544 1544
1545 /* There's new data available. */ 1545 /* There's new data available. */
1546 counter->hw.interrupts++; 1546 event->hw.interrupts++;
1547 counter->pending_kill = POLL_IN; 1547 event->pending_kill = POLL_IN;
1548} 1548}
1549 1549
1550static void x86_pmu_disable(struct perf_counter *counter) 1550static void x86_pmu_disable(struct perf_event *event)
1551{ 1551{
1552 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); 1552 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1553 struct hw_perf_counter *hwc = &counter->hw; 1553 struct hw_perf_event *hwc = &event->hw;
1554 int idx = hwc->idx; 1554 int idx = hwc->idx;
1555 1555
1556 /* 1556 /*
@@ -1562,63 +1562,63 @@ static void x86_pmu_disable(struct perf_counter *counter)
1562 1562
1563 /* 1563 /*
1564 * Make sure the cleared pointer becomes visible before we 1564 * Make sure the cleared pointer becomes visible before we
1565 * (potentially) free the counter: 1565 * (potentially) free the event:
1566 */ 1566 */
1567 barrier(); 1567 barrier();
1568 1568
1569 /* 1569 /*
1570 * Drain the remaining delta count out of a counter 1570 * Drain the remaining delta count out of a event
1571 * that we are disabling: 1571 * that we are disabling:
1572 */ 1572 */
1573 x86_perf_counter_update(counter, hwc, idx); 1573 x86_perf_event_update(event, hwc, idx);
1574 1574
1575 /* Drain the remaining BTS records. */ 1575 /* Drain the remaining BTS records. */
1576 if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) 1576 if (unlikely(idx == X86_PMC_IDX_FIXED_BTS))
1577 intel_pmu_drain_bts_buffer(cpuc); 1577 intel_pmu_drain_bts_buffer(cpuc);
1578 1578
1579 cpuc->counters[idx] = NULL; 1579 cpuc->events[idx] = NULL;
1580 clear_bit(idx, cpuc->used_mask); 1580 clear_bit(idx, cpuc->used_mask);
1581 1581
1582 perf_counter_update_userpage(counter); 1582 perf_event_update_userpage(event);
1583} 1583}
1584 1584
1585/* 1585/*
1586 * Save and restart an expired counter. Called by NMI contexts, 1586 * Save and restart an expired event. Called by NMI contexts,
1587 * so it has to be careful about preempting normal counter ops: 1587 * so it has to be careful about preempting normal event ops:
1588 */ 1588 */
1589static int intel_pmu_save_and_restart(struct perf_counter *counter) 1589static int intel_pmu_save_and_restart(struct perf_event *event)
1590{ 1590{
1591 struct hw_perf_counter *hwc = &counter->hw; 1591 struct hw_perf_event *hwc = &event->hw;
1592 int idx = hwc->idx; 1592 int idx = hwc->idx;
1593 int ret; 1593 int ret;
1594 1594
1595 x86_perf_counter_update(counter, hwc, idx); 1595 x86_perf_event_update(event, hwc, idx);
1596 ret = x86_perf_counter_set_period(counter, hwc, idx); 1596 ret = x86_perf_event_set_period(event, hwc, idx);
1597 1597
1598 if (counter->state == PERF_COUNTER_STATE_ACTIVE) 1598 if (event->state == PERF_EVENT_STATE_ACTIVE)
1599 intel_pmu_enable_counter(hwc, idx); 1599 intel_pmu_enable_event(hwc, idx);
1600 1600
1601 return ret; 1601 return ret;
1602} 1602}
1603 1603
1604static void intel_pmu_reset(void) 1604static void intel_pmu_reset(void)
1605{ 1605{
1606 struct debug_store *ds = __get_cpu_var(cpu_hw_counters).ds; 1606 struct debug_store *ds = __get_cpu_var(cpu_hw_events).ds;
1607 unsigned long flags; 1607 unsigned long flags;
1608 int idx; 1608 int idx;
1609 1609
1610 if (!x86_pmu.num_counters) 1610 if (!x86_pmu.num_events)
1611 return; 1611 return;
1612 1612
1613 local_irq_save(flags); 1613 local_irq_save(flags);
1614 1614
1615 printk("clearing PMU state on CPU#%d\n", smp_processor_id()); 1615 printk("clearing PMU state on CPU#%d\n", smp_processor_id());
1616 1616
1617 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 1617 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1618 checking_wrmsrl(x86_pmu.eventsel + idx, 0ull); 1618 checking_wrmsrl(x86_pmu.eventsel + idx, 0ull);
1619 checking_wrmsrl(x86_pmu.perfctr + idx, 0ull); 1619 checking_wrmsrl(x86_pmu.perfctr + idx, 0ull);
1620 } 1620 }
1621 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { 1621 for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) {
1622 checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); 1622 checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
1623 } 1623 }
1624 if (ds) 1624 if (ds)
@@ -1630,38 +1630,38 @@ static void intel_pmu_reset(void)
1630static int p6_pmu_handle_irq(struct pt_regs *regs) 1630static int p6_pmu_handle_irq(struct pt_regs *regs)
1631{ 1631{
1632 struct perf_sample_data data; 1632 struct perf_sample_data data;
1633 struct cpu_hw_counters *cpuc; 1633 struct cpu_hw_events *cpuc;
1634 struct perf_counter *counter; 1634 struct perf_event *event;
1635 struct hw_perf_counter *hwc; 1635 struct hw_perf_event *hwc;
1636 int idx, handled = 0; 1636 int idx, handled = 0;
1637 u64 val; 1637 u64 val;
1638 1638
1639 data.addr = 0; 1639 data.addr = 0;
1640 1640
1641 cpuc = &__get_cpu_var(cpu_hw_counters); 1641 cpuc = &__get_cpu_var(cpu_hw_events);
1642 1642
1643 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 1643 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1644 if (!test_bit(idx, cpuc->active_mask)) 1644 if (!test_bit(idx, cpuc->active_mask))
1645 continue; 1645 continue;
1646 1646
1647 counter = cpuc->counters[idx]; 1647 event = cpuc->events[idx];
1648 hwc = &counter->hw; 1648 hwc = &event->hw;
1649 1649
1650 val = x86_perf_counter_update(counter, hwc, idx); 1650 val = x86_perf_event_update(event, hwc, idx);
1651 if (val & (1ULL << (x86_pmu.counter_bits - 1))) 1651 if (val & (1ULL << (x86_pmu.event_bits - 1)))
1652 continue; 1652 continue;
1653 1653
1654 /* 1654 /*
1655 * counter overflow 1655 * event overflow
1656 */ 1656 */
1657 handled = 1; 1657 handled = 1;
1658 data.period = counter->hw.last_period; 1658 data.period = event->hw.last_period;
1659 1659
1660 if (!x86_perf_counter_set_period(counter, hwc, idx)) 1660 if (!x86_perf_event_set_period(event, hwc, idx))
1661 continue; 1661 continue;
1662 1662
1663 if (perf_counter_overflow(counter, 1, &data, regs)) 1663 if (perf_event_overflow(event, 1, &data, regs))
1664 p6_pmu_disable_counter(hwc, idx); 1664 p6_pmu_disable_event(hwc, idx);
1665 } 1665 }
1666 1666
1667 if (handled) 1667 if (handled)
@@ -1677,13 +1677,13 @@ static int p6_pmu_handle_irq(struct pt_regs *regs)
1677static int intel_pmu_handle_irq(struct pt_regs *regs) 1677static int intel_pmu_handle_irq(struct pt_regs *regs)
1678{ 1678{
1679 struct perf_sample_data data; 1679 struct perf_sample_data data;
1680 struct cpu_hw_counters *cpuc; 1680 struct cpu_hw_events *cpuc;
1681 int bit, loops; 1681 int bit, loops;
1682 u64 ack, status; 1682 u64 ack, status;
1683 1683
1684 data.addr = 0; 1684 data.addr = 0;
1685 1685
1686 cpuc = &__get_cpu_var(cpu_hw_counters); 1686 cpuc = &__get_cpu_var(cpu_hw_events);
1687 1687
1688 perf_disable(); 1688 perf_disable();
1689 intel_pmu_drain_bts_buffer(cpuc); 1689 intel_pmu_drain_bts_buffer(cpuc);
@@ -1696,8 +1696,8 @@ static int intel_pmu_handle_irq(struct pt_regs *regs)
1696 loops = 0; 1696 loops = 0;
1697again: 1697again:
1698 if (++loops > 100) { 1698 if (++loops > 100) {
1699 WARN_ONCE(1, "perfcounters: irq loop stuck!\n"); 1699 WARN_ONCE(1, "perfevents: irq loop stuck!\n");
1700 perf_counter_print_debug(); 1700 perf_event_print_debug();
1701 intel_pmu_reset(); 1701 intel_pmu_reset();
1702 perf_enable(); 1702 perf_enable();
1703 return 1; 1703 return 1;
@@ -1706,19 +1706,19 @@ again:
1706 inc_irq_stat(apic_perf_irqs); 1706 inc_irq_stat(apic_perf_irqs);
1707 ack = status; 1707 ack = status;
1708 for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { 1708 for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
1709 struct perf_counter *counter = cpuc->counters[bit]; 1709 struct perf_event *event = cpuc->events[bit];
1710 1710
1711 clear_bit(bit, (unsigned long *) &status); 1711 clear_bit(bit, (unsigned long *) &status);
1712 if (!test_bit(bit, cpuc->active_mask)) 1712 if (!test_bit(bit, cpuc->active_mask))
1713 continue; 1713 continue;
1714 1714
1715 if (!intel_pmu_save_and_restart(counter)) 1715 if (!intel_pmu_save_and_restart(event))
1716 continue; 1716 continue;
1717 1717
1718 data.period = counter->hw.last_period; 1718 data.period = event->hw.last_period;
1719 1719
1720 if (perf_counter_overflow(counter, 1, &data, regs)) 1720 if (perf_event_overflow(event, 1, &data, regs))
1721 intel_pmu_disable_counter(&counter->hw, bit); 1721 intel_pmu_disable_event(&event->hw, bit);
1722 } 1722 }
1723 1723
1724 intel_pmu_ack_status(ack); 1724 intel_pmu_ack_status(ack);
@@ -1738,38 +1738,38 @@ again:
1738static int amd_pmu_handle_irq(struct pt_regs *regs) 1738static int amd_pmu_handle_irq(struct pt_regs *regs)
1739{ 1739{
1740 struct perf_sample_data data; 1740 struct perf_sample_data data;
1741 struct cpu_hw_counters *cpuc; 1741 struct cpu_hw_events *cpuc;
1742 struct perf_counter *counter; 1742 struct perf_event *event;
1743 struct hw_perf_counter *hwc; 1743 struct hw_perf_event *hwc;
1744 int idx, handled = 0; 1744 int idx, handled = 0;
1745 u64 val; 1745 u64 val;
1746 1746
1747 data.addr = 0; 1747 data.addr = 0;
1748 1748
1749 cpuc = &__get_cpu_var(cpu_hw_counters); 1749 cpuc = &__get_cpu_var(cpu_hw_events);
1750 1750
1751 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 1751 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1752 if (!test_bit(idx, cpuc->active_mask)) 1752 if (!test_bit(idx, cpuc->active_mask))
1753 continue; 1753 continue;
1754 1754
1755 counter = cpuc->counters[idx]; 1755 event = cpuc->events[idx];
1756 hwc = &counter->hw; 1756 hwc = &event->hw;
1757 1757
1758 val = x86_perf_counter_update(counter, hwc, idx); 1758 val = x86_perf_event_update(event, hwc, idx);
1759 if (val & (1ULL << (x86_pmu.counter_bits - 1))) 1759 if (val & (1ULL << (x86_pmu.event_bits - 1)))
1760 continue; 1760 continue;
1761 1761
1762 /* 1762 /*
1763 * counter overflow 1763 * event overflow
1764 */ 1764 */
1765 handled = 1; 1765 handled = 1;
1766 data.period = counter->hw.last_period; 1766 data.period = event->hw.last_period;
1767 1767
1768 if (!x86_perf_counter_set_period(counter, hwc, idx)) 1768 if (!x86_perf_event_set_period(event, hwc, idx))
1769 continue; 1769 continue;
1770 1770
1771 if (perf_counter_overflow(counter, 1, &data, regs)) 1771 if (perf_event_overflow(event, 1, &data, regs))
1772 amd_pmu_disable_counter(hwc, idx); 1772 amd_pmu_disable_event(hwc, idx);
1773 } 1773 }
1774 1774
1775 if (handled) 1775 if (handled)
@@ -1783,18 +1783,18 @@ void smp_perf_pending_interrupt(struct pt_regs *regs)
1783 irq_enter(); 1783 irq_enter();
1784 ack_APIC_irq(); 1784 ack_APIC_irq();
1785 inc_irq_stat(apic_pending_irqs); 1785 inc_irq_stat(apic_pending_irqs);
1786 perf_counter_do_pending(); 1786 perf_event_do_pending();
1787 irq_exit(); 1787 irq_exit();
1788} 1788}
1789 1789
1790void set_perf_counter_pending(void) 1790void set_perf_event_pending(void)
1791{ 1791{
1792#ifdef CONFIG_X86_LOCAL_APIC 1792#ifdef CONFIG_X86_LOCAL_APIC
1793 apic->send_IPI_self(LOCAL_PENDING_VECTOR); 1793 apic->send_IPI_self(LOCAL_PENDING_VECTOR);
1794#endif 1794#endif
1795} 1795}
1796 1796
1797void perf_counters_lapic_init(void) 1797void perf_events_lapic_init(void)
1798{ 1798{
1799#ifdef CONFIG_X86_LOCAL_APIC 1799#ifdef CONFIG_X86_LOCAL_APIC
1800 if (!x86_pmu.apic || !x86_pmu_initialized()) 1800 if (!x86_pmu.apic || !x86_pmu_initialized())
@@ -1808,13 +1808,13 @@ void perf_counters_lapic_init(void)
1808} 1808}
1809 1809
1810static int __kprobes 1810static int __kprobes
1811perf_counter_nmi_handler(struct notifier_block *self, 1811perf_event_nmi_handler(struct notifier_block *self,
1812 unsigned long cmd, void *__args) 1812 unsigned long cmd, void *__args)
1813{ 1813{
1814 struct die_args *args = __args; 1814 struct die_args *args = __args;
1815 struct pt_regs *regs; 1815 struct pt_regs *regs;
1816 1816
1817 if (!atomic_read(&active_counters)) 1817 if (!atomic_read(&active_events))
1818 return NOTIFY_DONE; 1818 return NOTIFY_DONE;
1819 1819
1820 switch (cmd) { 1820 switch (cmd) {
@@ -1833,7 +1833,7 @@ perf_counter_nmi_handler(struct notifier_block *self,
1833#endif 1833#endif
1834 /* 1834 /*
1835 * Can't rely on the handled return value to say it was our NMI, two 1835 * Can't rely on the handled return value to say it was our NMI, two
1836 * counters could trigger 'simultaneously' raising two back-to-back NMIs. 1836 * events could trigger 'simultaneously' raising two back-to-back NMIs.
1837 * 1837 *
1838 * If the first NMI handles both, the latter will be empty and daze 1838 * If the first NMI handles both, the latter will be empty and daze
1839 * the CPU. 1839 * the CPU.
@@ -1843,8 +1843,8 @@ perf_counter_nmi_handler(struct notifier_block *self,
1843 return NOTIFY_STOP; 1843 return NOTIFY_STOP;
1844} 1844}
1845 1845
1846static __read_mostly struct notifier_block perf_counter_nmi_notifier = { 1846static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1847 .notifier_call = perf_counter_nmi_handler, 1847 .notifier_call = perf_event_nmi_handler,
1848 .next = NULL, 1848 .next = NULL,
1849 .priority = 1 1849 .priority = 1
1850}; 1850};
@@ -1854,8 +1854,8 @@ static struct x86_pmu p6_pmu = {
1854 .handle_irq = p6_pmu_handle_irq, 1854 .handle_irq = p6_pmu_handle_irq,
1855 .disable_all = p6_pmu_disable_all, 1855 .disable_all = p6_pmu_disable_all,
1856 .enable_all = p6_pmu_enable_all, 1856 .enable_all = p6_pmu_enable_all,
1857 .enable = p6_pmu_enable_counter, 1857 .enable = p6_pmu_enable_event,
1858 .disable = p6_pmu_disable_counter, 1858 .disable = p6_pmu_disable_event,
1859 .eventsel = MSR_P6_EVNTSEL0, 1859 .eventsel = MSR_P6_EVNTSEL0,
1860 .perfctr = MSR_P6_PERFCTR0, 1860 .perfctr = MSR_P6_PERFCTR0,
1861 .event_map = p6_pmu_event_map, 1861 .event_map = p6_pmu_event_map,
@@ -1864,16 +1864,16 @@ static struct x86_pmu p6_pmu = {
1864 .apic = 1, 1864 .apic = 1,
1865 .max_period = (1ULL << 31) - 1, 1865 .max_period = (1ULL << 31) - 1,
1866 .version = 0, 1866 .version = 0,
1867 .num_counters = 2, 1867 .num_events = 2,
1868 /* 1868 /*
1869 * Counters have 40 bits implemented. However they are designed such 1869 * Events have 40 bits implemented. However they are designed such
1870 * that bits [32-39] are sign extensions of bit 31. As such the 1870 * that bits [32-39] are sign extensions of bit 31. As such the
1871 * effective width of a counter for P6-like PMU is 32 bits only. 1871 * effective width of a event for P6-like PMU is 32 bits only.
1872 * 1872 *
1873 * See IA-32 Intel Architecture Software developer manual Vol 3B 1873 * See IA-32 Intel Architecture Software developer manual Vol 3B
1874 */ 1874 */
1875 .counter_bits = 32, 1875 .event_bits = 32,
1876 .counter_mask = (1ULL << 32) - 1, 1876 .event_mask = (1ULL << 32) - 1,
1877}; 1877};
1878 1878
1879static struct x86_pmu intel_pmu = { 1879static struct x86_pmu intel_pmu = {
@@ -1881,8 +1881,8 @@ static struct x86_pmu intel_pmu = {
1881 .handle_irq = intel_pmu_handle_irq, 1881 .handle_irq = intel_pmu_handle_irq,
1882 .disable_all = intel_pmu_disable_all, 1882 .disable_all = intel_pmu_disable_all,
1883 .enable_all = intel_pmu_enable_all, 1883 .enable_all = intel_pmu_enable_all,
1884 .enable = intel_pmu_enable_counter, 1884 .enable = intel_pmu_enable_event,
1885 .disable = intel_pmu_disable_counter, 1885 .disable = intel_pmu_disable_event,
1886 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 1886 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1887 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 1887 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
1888 .event_map = intel_pmu_event_map, 1888 .event_map = intel_pmu_event_map,
@@ -1892,7 +1892,7 @@ static struct x86_pmu intel_pmu = {
1892 /* 1892 /*
1893 * Intel PMCs cannot be accessed sanely above 32 bit width, 1893 * Intel PMCs cannot be accessed sanely above 32 bit width,
1894 * so we install an artificial 1<<31 period regardless of 1894 * so we install an artificial 1<<31 period regardless of
1895 * the generic counter period: 1895 * the generic event period:
1896 */ 1896 */
1897 .max_period = (1ULL << 31) - 1, 1897 .max_period = (1ULL << 31) - 1,
1898 .enable_bts = intel_pmu_enable_bts, 1898 .enable_bts = intel_pmu_enable_bts,
@@ -1904,16 +1904,16 @@ static struct x86_pmu amd_pmu = {
1904 .handle_irq = amd_pmu_handle_irq, 1904 .handle_irq = amd_pmu_handle_irq,
1905 .disable_all = amd_pmu_disable_all, 1905 .disable_all = amd_pmu_disable_all,
1906 .enable_all = amd_pmu_enable_all, 1906 .enable_all = amd_pmu_enable_all,
1907 .enable = amd_pmu_enable_counter, 1907 .enable = amd_pmu_enable_event,
1908 .disable = amd_pmu_disable_counter, 1908 .disable = amd_pmu_disable_event,
1909 .eventsel = MSR_K7_EVNTSEL0, 1909 .eventsel = MSR_K7_EVNTSEL0,
1910 .perfctr = MSR_K7_PERFCTR0, 1910 .perfctr = MSR_K7_PERFCTR0,
1911 .event_map = amd_pmu_event_map, 1911 .event_map = amd_pmu_event_map,
1912 .raw_event = amd_pmu_raw_event, 1912 .raw_event = amd_pmu_raw_event,
1913 .max_events = ARRAY_SIZE(amd_perfmon_event_map), 1913 .max_events = ARRAY_SIZE(amd_perfmon_event_map),
1914 .num_counters = 4, 1914 .num_events = 4,
1915 .counter_bits = 48, 1915 .event_bits = 48,
1916 .counter_mask = (1ULL << 48) - 1, 1916 .event_mask = (1ULL << 48) - 1,
1917 .apic = 1, 1917 .apic = 1,
1918 /* use highest bit to detect overflow */ 1918 /* use highest bit to detect overflow */
1919 .max_period = (1ULL << 47) - 1, 1919 .max_period = (1ULL << 47) - 1,
@@ -1982,15 +1982,15 @@ static int intel_pmu_init(void)
1982 1982
1983 x86_pmu = intel_pmu; 1983 x86_pmu = intel_pmu;
1984 x86_pmu.version = version; 1984 x86_pmu.version = version;
1985 x86_pmu.num_counters = eax.split.num_counters; 1985 x86_pmu.num_events = eax.split.num_events;
1986 x86_pmu.counter_bits = eax.split.bit_width; 1986 x86_pmu.event_bits = eax.split.bit_width;
1987 x86_pmu.counter_mask = (1ULL << eax.split.bit_width) - 1; 1987 x86_pmu.event_mask = (1ULL << eax.split.bit_width) - 1;
1988 1988
1989 /* 1989 /*
1990 * Quirk: v2 perfmon does not report fixed-purpose counters, so 1990 * Quirk: v2 perfmon does not report fixed-purpose events, so
1991 * assume at least 3 counters: 1991 * assume at least 3 events:
1992 */ 1992 */
1993 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3); 1993 x86_pmu.num_events_fixed = max((int)edx.split.num_events_fixed, 3);
1994 1994
1995 /* 1995 /*
1996 * Install the hw-cache-events table: 1996 * Install the hw-cache-events table:
@@ -2037,11 +2037,11 @@ static int amd_pmu_init(void)
2037 return 0; 2037 return 0;
2038} 2038}
2039 2039
2040void __init init_hw_perf_counters(void) 2040void __init init_hw_perf_events(void)
2041{ 2041{
2042 int err; 2042 int err;
2043 2043
2044 pr_info("Performance Counters: "); 2044 pr_info("Performance Events: ");
2045 2045
2046 switch (boot_cpu_data.x86_vendor) { 2046 switch (boot_cpu_data.x86_vendor) {
2047 case X86_VENDOR_INTEL: 2047 case X86_VENDOR_INTEL:
@@ -2054,45 +2054,45 @@ void __init init_hw_perf_counters(void)
2054 return; 2054 return;
2055 } 2055 }
2056 if (err != 0) { 2056 if (err != 0) {
2057 pr_cont("no PMU driver, software counters only.\n"); 2057 pr_cont("no PMU driver, software events only.\n");
2058 return; 2058 return;
2059 } 2059 }
2060 2060
2061 pr_cont("%s PMU driver.\n", x86_pmu.name); 2061 pr_cont("%s PMU driver.\n", x86_pmu.name);
2062 2062
2063 if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) { 2063 if (x86_pmu.num_events > X86_PMC_MAX_GENERIC) {
2064 WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!", 2064 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
2065 x86_pmu.num_counters, X86_PMC_MAX_GENERIC); 2065 x86_pmu.num_events, X86_PMC_MAX_GENERIC);
2066 x86_pmu.num_counters = X86_PMC_MAX_GENERIC; 2066 x86_pmu.num_events = X86_PMC_MAX_GENERIC;
2067 } 2067 }
2068 perf_counter_mask = (1 << x86_pmu.num_counters) - 1; 2068 perf_event_mask = (1 << x86_pmu.num_events) - 1;
2069 perf_max_counters = x86_pmu.num_counters; 2069 perf_max_events = x86_pmu.num_events;
2070 2070
2071 if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) { 2071 if (x86_pmu.num_events_fixed > X86_PMC_MAX_FIXED) {
2072 WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!", 2072 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
2073 x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED); 2073 x86_pmu.num_events_fixed, X86_PMC_MAX_FIXED);
2074 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED; 2074 x86_pmu.num_events_fixed = X86_PMC_MAX_FIXED;
2075 } 2075 }
2076 2076
2077 perf_counter_mask |= 2077 perf_event_mask |=
2078 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED; 2078 ((1LL << x86_pmu.num_events_fixed)-1) << X86_PMC_IDX_FIXED;
2079 x86_pmu.intel_ctrl = perf_counter_mask; 2079 x86_pmu.intel_ctrl = perf_event_mask;
2080 2080
2081 perf_counters_lapic_init(); 2081 perf_events_lapic_init();
2082 register_die_notifier(&perf_counter_nmi_notifier); 2082 register_die_notifier(&perf_event_nmi_notifier);
2083 2083
2084 pr_info("... version: %d\n", x86_pmu.version); 2084 pr_info("... version: %d\n", x86_pmu.version);
2085 pr_info("... bit width: %d\n", x86_pmu.counter_bits); 2085 pr_info("... bit width: %d\n", x86_pmu.event_bits);
2086 pr_info("... generic counters: %d\n", x86_pmu.num_counters); 2086 pr_info("... generic events: %d\n", x86_pmu.num_events);
2087 pr_info("... value mask: %016Lx\n", x86_pmu.counter_mask); 2087 pr_info("... value mask: %016Lx\n", x86_pmu.event_mask);
2088 pr_info("... max period: %016Lx\n", x86_pmu.max_period); 2088 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
2089 pr_info("... fixed-purpose counters: %d\n", x86_pmu.num_counters_fixed); 2089 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_events_fixed);
2090 pr_info("... counter mask: %016Lx\n", perf_counter_mask); 2090 pr_info("... event mask: %016Lx\n", perf_event_mask);
2091} 2091}
2092 2092
2093static inline void x86_pmu_read(struct perf_counter *counter) 2093static inline void x86_pmu_read(struct perf_event *event)
2094{ 2094{
2095 x86_perf_counter_update(counter, &counter->hw, counter->hw.idx); 2095 x86_perf_event_update(event, &event->hw, event->hw.idx);
2096} 2096}
2097 2097
2098static const struct pmu pmu = { 2098static const struct pmu pmu = {
@@ -2102,14 +2102,14 @@ static const struct pmu pmu = {
2102 .unthrottle = x86_pmu_unthrottle, 2102 .unthrottle = x86_pmu_unthrottle,
2103}; 2103};
2104 2104
2105const struct pmu *hw_perf_counter_init(struct perf_counter *counter) 2105const struct pmu *hw_perf_event_init(struct perf_event *event)
2106{ 2106{
2107 int err; 2107 int err;
2108 2108
2109 err = __hw_perf_counter_init(counter); 2109 err = __hw_perf_event_init(event);
2110 if (err) { 2110 if (err) {
2111 if (counter->destroy) 2111 if (event->destroy)
2112 counter->destroy(counter); 2112 event->destroy(event);
2113 return ERR_PTR(err); 2113 return ERR_PTR(err);
2114 } 2114 }
2115 2115
@@ -2292,7 +2292,7 @@ struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
2292 return entry; 2292 return entry;
2293} 2293}
2294 2294
2295void hw_perf_counter_setup_online(int cpu) 2295void hw_perf_event_setup_online(int cpu)
2296{ 2296{
2297 init_debug_store_on_cpu(cpu); 2297 init_debug_store_on_cpu(cpu);
2298} 2298}
diff --git a/arch/x86/kernel/cpu/perfctr-watchdog.c b/arch/x86/kernel/cpu/perfctr-watchdog.c
index 392bea43b890..fab786f60ed6 100644
--- a/arch/x86/kernel/cpu/perfctr-watchdog.c
+++ b/arch/x86/kernel/cpu/perfctr-watchdog.c
@@ -20,7 +20,7 @@
20#include <linux/kprobes.h> 20#include <linux/kprobes.h>
21 21
22#include <asm/apic.h> 22#include <asm/apic.h>
23#include <asm/perf_counter.h> 23#include <asm/perf_event.h>
24 24
25struct nmi_watchdog_ctlblk { 25struct nmi_watchdog_ctlblk {
26 unsigned int cccr_msr; 26 unsigned int cccr_msr;
diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S
index d59fe323807e..681c3fda7391 100644
--- a/arch/x86/kernel/entry_64.S
+++ b/arch/x86/kernel/entry_64.S
@@ -1021,7 +1021,7 @@ apicinterrupt ERROR_APIC_VECTOR \
1021apicinterrupt SPURIOUS_APIC_VECTOR \ 1021apicinterrupt SPURIOUS_APIC_VECTOR \
1022 spurious_interrupt smp_spurious_interrupt 1022 spurious_interrupt smp_spurious_interrupt
1023 1023
1024#ifdef CONFIG_PERF_COUNTERS 1024#ifdef CONFIG_PERF_EVENTS
1025apicinterrupt LOCAL_PENDING_VECTOR \ 1025apicinterrupt LOCAL_PENDING_VECTOR \
1026 perf_pending_interrupt smp_perf_pending_interrupt 1026 perf_pending_interrupt smp_perf_pending_interrupt
1027#endif 1027#endif
diff --git a/arch/x86/kernel/irqinit.c b/arch/x86/kernel/irqinit.c
index 300883112e3d..40f30773fb29 100644
--- a/arch/x86/kernel/irqinit.c
+++ b/arch/x86/kernel/irqinit.c
@@ -208,7 +208,7 @@ static void __init apic_intr_init(void)
208 alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt); 208 alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
209 209
210 /* Performance monitoring interrupts: */ 210 /* Performance monitoring interrupts: */
211# ifdef CONFIG_PERF_COUNTERS 211# ifdef CONFIG_PERF_EVENTS
212 alloc_intr_gate(LOCAL_PENDING_VECTOR, perf_pending_interrupt); 212 alloc_intr_gate(LOCAL_PENDING_VECTOR, perf_pending_interrupt);
213# endif 213# endif
214 214
diff --git a/arch/x86/kernel/syscall_table_32.S b/arch/x86/kernel/syscall_table_32.S
index d51321ddafda..0157cd26d7cc 100644
--- a/arch/x86/kernel/syscall_table_32.S
+++ b/arch/x86/kernel/syscall_table_32.S
@@ -335,4 +335,4 @@ ENTRY(sys_call_table)
335 .long sys_preadv 335 .long sys_preadv
336 .long sys_pwritev 336 .long sys_pwritev
337 .long sys_rt_tgsigqueueinfo /* 335 */ 337 .long sys_rt_tgsigqueueinfo /* 335 */
338 .long sys_perf_counter_open 338 .long sys_perf_event_open
diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c
index 775a020990a5..82728f2c6d55 100644
--- a/arch/x86/mm/fault.c
+++ b/arch/x86/mm/fault.c
@@ -10,7 +10,7 @@
10#include <linux/bootmem.h> /* max_low_pfn */ 10#include <linux/bootmem.h> /* max_low_pfn */
11#include <linux/kprobes.h> /* __kprobes, ... */ 11#include <linux/kprobes.h> /* __kprobes, ... */
12#include <linux/mmiotrace.h> /* kmmio_handler, ... */ 12#include <linux/mmiotrace.h> /* kmmio_handler, ... */
13#include <linux/perf_counter.h> /* perf_swcounter_event */ 13#include <linux/perf_event.h> /* perf_sw_event */
14 14
15#include <asm/traps.h> /* dotraplinkage, ... */ 15#include <asm/traps.h> /* dotraplinkage, ... */
16#include <asm/pgalloc.h> /* pgd_*(), ... */ 16#include <asm/pgalloc.h> /* pgd_*(), ... */
@@ -1017,7 +1017,7 @@ do_page_fault(struct pt_regs *regs, unsigned long error_code)
1017 if (unlikely(error_code & PF_RSVD)) 1017 if (unlikely(error_code & PF_RSVD))
1018 pgtable_bad(regs, error_code, address); 1018 pgtable_bad(regs, error_code, address);
1019 1019
1020 perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address); 1020 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address);
1021 1021
1022 /* 1022 /*
1023 * If we're in an interrupt, have no user context or are running 1023 * If we're in an interrupt, have no user context or are running
@@ -1114,11 +1114,11 @@ good_area:
1114 1114
1115 if (fault & VM_FAULT_MAJOR) { 1115 if (fault & VM_FAULT_MAJOR) {
1116 tsk->maj_flt++; 1116 tsk->maj_flt++;
1117 perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0, 1117 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0,
1118 regs, address); 1118 regs, address);
1119 } else { 1119 } else {
1120 tsk->min_flt++; 1120 tsk->min_flt++;
1121 perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0, 1121 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0,
1122 regs, address); 1122 regs, address);
1123 } 1123 }
1124 1124
diff --git a/arch/x86/oprofile/op_model_ppro.c b/arch/x86/oprofile/op_model_ppro.c
index 4899215999de..8eb05878554c 100644
--- a/arch/x86/oprofile/op_model_ppro.c
+++ b/arch/x86/oprofile/op_model_ppro.c
@@ -234,11 +234,11 @@ static void arch_perfmon_setup_counters(void)
234 if (eax.split.version_id == 0 && current_cpu_data.x86 == 6 && 234 if (eax.split.version_id == 0 && current_cpu_data.x86 == 6 &&
235 current_cpu_data.x86_model == 15) { 235 current_cpu_data.x86_model == 15) {
236 eax.split.version_id = 2; 236 eax.split.version_id = 2;
237 eax.split.num_counters = 2; 237 eax.split.num_events = 2;
238 eax.split.bit_width = 40; 238 eax.split.bit_width = 40;
239 } 239 }
240 240
241 num_counters = eax.split.num_counters; 241 num_counters = eax.split.num_events;
242 242
243 op_arch_perfmon_spec.num_counters = num_counters; 243 op_arch_perfmon_spec.num_counters = num_counters;
244 op_arch_perfmon_spec.num_controls = num_counters; 244 op_arch_perfmon_spec.num_controls = num_counters;
diff --git a/arch/x86/oprofile/op_x86_model.h b/arch/x86/oprofile/op_x86_model.h
index b83776180c7f..7b8e75d16081 100644
--- a/arch/x86/oprofile/op_x86_model.h
+++ b/arch/x86/oprofile/op_x86_model.h
@@ -13,7 +13,7 @@
13#define OP_X86_MODEL_H 13#define OP_X86_MODEL_H
14 14
15#include <asm/types.h> 15#include <asm/types.h>
16#include <asm/perf_counter.h> 16#include <asm/perf_event.h>
17 17
18struct op_msr { 18struct op_msr {
19 unsigned long addr; 19 unsigned long addr;
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-20 10:27:55 -0400