Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (272 commits) Fix soc_common PCMCIA configuration ARM: 5827/1: SA1100: h3100/h3600: emit messages on failed gpio_request ARM: 5826/1: SA1100: h3100/h3600: always build htc-egpio driver ARM: 5825/1: SA1100: h3600: update defconfig ARM: 5824/1: SA1100: reuse h3600 PCMCIA driver on h3100 ARM: 5823/1: SA1100: h3100/h3600: add support for gpio-keys ARM: 5822/1: SA1100: h3100/h3600: clean up #includes ARM: 5821/1: SA1100: h3100/h3600: revise copyright boilerplates ARM: 5820/1: SA1100: h3100/h3600: split h3600.c ARM: 5819/1: SA1100: h3100/h3600: merge h3600.h and h3600_gpio.h into h3xxx.h ARM: 5818/1: SA1100: h3100/h3600: drop old GPIO definitions ARM: 5817/1: SA1100: h3100/h3600: configure all unused gpios as inputs ARM: 5816/1: SA1100: h3600: remove IRQ_GPIO_* definitions ARM: 5815/1: SA1100: h3100/h3600: remove now unused assign_h3600_egpio handlers ARM: 5814/1: SA1100: h3100/h3600: convert all users of assign_h3600_egpio to gpiolib ARM: 5813/1: SA1100: h3100/h3600: add htc-egpio driver ARM: 5812/1: SA1100: h3100/h3600: separate machine-specific LCD helpers ARM: 5811/2: pcmcia: convert sa1100_h3600 driver to gpiolib ARM: 5799/1: SA1100: h3600: stop setting direction for LCD pins ARM: 5798/1: SA1100: h3600: remove unused cruft from h3600.h ...
author: Linus Torvalds <torvalds@linux-foundation.org> 2009-12-08 11:12:43 -0500
committer: Linus Torvalds <torvalds@linux-foundation.org> 2009-12-08 11:12:43 -0500
commit: 79c9601c2e0dbbe69895d302de4d19f3a31fbd30 (patch)
tree: 78d4be2df851b2b4106adcfd736622a90cecf9e9 /arch
parent: 41440ffe21f29bdb985cab76b2d0b06d83e63b19 (diff)
parent: 3d14b5beba35250c548d3851a2b84fce742d8311 (diff)
418 files changed, 23600 insertions, 4911 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1c4119c60040..cf8a99f19dc4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -433,6 +433,17 @@ config ARCH_L7200
          If you have any questions or comments about the Linux kernel port
          to this board, send e-mail to <sjhill@cotw.com>.
+config ARCH_DOVE
+        bool "Marvell Dove"
+        select PCI
+        select GENERIC_GPIO
+        select ARCH_REQUIRE_GPIOLIB
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
+        select PLAT_ORION
+        help
+          Support for the Marvell Dove SoC 88AP510
 config ARCH_KIRKWOOD
        bool "Marvell Kirkwood"
        select CPU_FEROCEON
@@ -702,6 +713,16 @@ config ARCH_BCMRING
        help
          Support for Broadcom's BCMRing platform.
+config ARCH_U8500
+        bool "ST-Ericsson U8500 Series"
+        select CPU_V7
+        select ARM_AMBA
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
+        select COMMON_CLKDEV
+        help
+          Support for ST-Ericsson's Ux500 architecture
 endchoice
 source "arch/arm/mach-clps711x/Kconfig"
@@ -747,6 +768,9 @@ source "arch/arm/mach-orion5x/Kconfig"
 source "arch/arm/mach-kirkwood/Kconfig"
+source "arch/arm/mach-dove/Kconfig"
+source "arch/arm/plat-samsung/Kconfig"
 source "arch/arm/plat-s3c24xx/Kconfig"
 source "arch/arm/plat-s3c64xx/Kconfig"
 source "arch/arm/plat-s3c/Kconfig"
@@ -787,6 +811,7 @@ source "arch/arm/mach-at91/Kconfig"
 source "arch/arm/plat-mxc/Kconfig"
 source "arch/arm/mach-nomadik/Kconfig"
+source "arch/arm/plat-nomadik/Kconfig"
 source "arch/arm/mach-netx/Kconfig"
@@ -804,12 +829,16 @@ source "arch/arm/mach-w90x900/Kconfig"
 source "arch/arm/mach-bcmring/Kconfig"
+source "arch/arm/mach-ux500/Kconfig"
 # Definitions to make life easier
 config ARCH_ACORN
        bool
 config PLAT_IOP
        bool
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_TIME
 config PLAT_ORION
        bool
@@ -955,10 +984,10 @@ source "kernel/time/Kconfig"
 config SMP
        bool "Symmetric Multi-Processing (EXPERIMENTAL)"
        depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP ||\
-                 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4)
+                 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || ARCH_U8500)
        depends on GENERIC_CLOCKEVENTS
        select USE_GENERIC_SMP_HELPERS
-        select HAVE_ARM_SCU if (ARCH_REALVIEW || ARCH_OMAP4)
+        select HAVE_ARM_SCU if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500)
        help
          This enables support for systems with more than one CPU. If you have
          a system with only one CPU, like most personal computers, say N. If
@@ -1027,9 +1056,9 @@ config HOTPLUG_CPU
 config LOCAL_TIMERS
        bool "Use local timer interrupts"
        depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \
-                REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4)
+                REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || ARCH_U8500)
        default y
-        select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_OMAP4)
+        select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500)
        help
          Enable support for local timers on SMP platforms, rather then the
          legacy IPI broadcast method.  Local timers allows the system
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 1a6f70e52921..ff54c23d085e 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -83,6 +83,14 @@ config DEBUG_ICEDCC
          It does include a timeout to ensure that the system does not
          totally freeze when there is nothing connected to read.
+config OC_ETM
+        bool "On-chip ETM and ETB"
+        select ARM_AMBA
+        help
+          Enables the on-chip embedded trace macrocell and embedded trace
+          buffer driver that will allow you to collect traces of the
+          kernel code.
 config DEBUG_DC21285_PORT
        bool "Kernel low-level debugging messages via footbridge serial port"
        depends on DEBUG_LL && FOOTBRIDGE
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index a73caaf66763..fa0cdab2e1d3 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -122,6 +122,7 @@ machine-$(CONFIG_ARCH_AT91)		:= at91
 machine-$(CONFIG_ARCH_BCMRING)          := bcmring
 machine-$(CONFIG_ARCH_CLPS711X)         := clps711x
 machine-$(CONFIG_ARCH_DAVINCI)          := davinci
+machine-$(CONFIG_ARCH_DOVE)             := dove
 machine-$(CONFIG_ARCH_EBSA110)          := ebsa110
 machine-$(CONFIG_ARCH_EP93XX)           := ep93xx
 machine-$(CONFIG_ARCH_GEMINI)           := gemini
@@ -166,6 +167,7 @@ machine-$(CONFIG_ARCH_SHARK)		:= shark
 machine-$(CONFIG_ARCH_STMP378X)         := stmp378x
 machine-$(CONFIG_ARCH_STMP37XX)         := stmp37xx
 machine-$(CONFIG_ARCH_U300)             := u300
+machine-$(CONFIG_ARCH_U8500)            := ux500
 machine-$(CONFIG_ARCH_VERSATILE)        := versatile
 machine-$(CONFIG_ARCH_W90X900)          := w90x900
 machine-$(CONFIG_FOOTBRIDGE)            := footbridge
@@ -176,11 +178,12 @@ machine-$(CONFIG_ARCH_MXC91231)		:= mxc91231
 plat-$(CONFIG_ARCH_MXC)         := mxc
 plat-$(CONFIG_ARCH_OMAP)        := omap
 plat-$(CONFIG_PLAT_IOP)         := iop
+plat-$(CONFIG_PLAT_NOMADIK)     := nomadik
 plat-$(CONFIG_PLAT_ORION)       := orion
 plat-$(CONFIG_PLAT_PXA)         := pxa
-plat-$(CONFIG_PLAT_S3C24XX)     := s3c24xx s3c
+plat-$(CONFIG_PLAT_S3C24XX)     := s3c24xx s3c samsung
-plat-$(CONFIG_PLAT_S3C64XX)     := s3c64xx s3c
+plat-$(CONFIG_PLAT_S3C64XX)     := s3c64xx s3c samsung
-plat-$(CONFIG_PLAT_S5PC1XX)     := s5pc1xx s3c
+plat-$(CONFIG_PLAT_S5PC1XX)     := s5pc1xx s3c samsung
 plat-$(CONFIG_ARCH_STMP3XXX)    := stmp3xxx
 ifeq ($(CONFIG_ARCH_EBSA110),y)
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index fa6fbf45cf3b..d356af7cef82 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -743,6 +743,12 @@ proc_types:
                W(b)    __armv4_mmu_cache_off
                W(b)    __armv6_mmu_cache_flush
+                .word   0x560f5810              @ Marvell PJ4 ARMv6
+                .word   0xff0ffff0
+                W(b)    __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_off
+                W(b)    __armv6_mmu_cache_flush
                .word   0x000f0000              @ new CPU Id
                .word   0x000f0000
                W(b)    __armv7_mmu_cache_on
diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c
index 734ac9135998..5a375e5fef21 100644
--- a/arch/arm/common/dmabounce.c
+++ b/arch/arm/common/dmabounce.c
@@ -342,6 +342,22 @@ dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
 }
 EXPORT_SYMBOL(dma_map_single);
+/*
+ * see if a mapped address was really a "safe" buffer and if so, copy
+ * the data from the safe buffer back to the unsafe buffer and free up
+ * the safe buffer.  (basically return things back to the way they
+ * should be)
+ */
+void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
+                enum dma_data_direction dir)
+{
+        dev_dbg(dev, "%s(ptr=%p,size=%d,dir=%x)\n",
+                __func__, (void *) dma_addr, size, dir);
+        unmap_single(dev, dma_addr, size, dir);
+}
+EXPORT_SYMBOL(dma_unmap_single);
 dma_addr_t dma_map_page(struct device *dev, struct page *page,
                unsigned long offset, size_t size, enum dma_data_direction dir)
 {
@@ -366,8 +382,7 @@ EXPORT_SYMBOL(dma_map_page);
 * the safe buffer.  (basically return things back to the way they
 * should be)
 */
+void dma_unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
-void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
                enum dma_data_direction dir)
 {
        dev_dbg(dev, "%s(ptr=%p,size=%d,dir=%x)\n",
@@ -375,7 +390,7 @@ void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
        unmap_single(dev, dma_addr, size, dir);
 }
-EXPORT_SYMBOL(dma_unmap_single);
+EXPORT_SYMBOL(dma_unmap_page);
 int dmabounce_sync_for_cpu(struct device *dev, dma_addr_t addr,
                unsigned long off, size_t sz, enum dma_data_direction dir)
diff --git a/arch/arm/configs/at91rm9200dk_defconfig b/arch/arm/configs/at91rm9200dk_defconfig
index 238b218394e3..c97e1022ada1 100644
--- a/arch/arm/configs/at91rm9200dk_defconfig
+++ b/arch/arm/configs/at91rm9200dk_defconfig
@@ -120,6 +120,7 @@ CONFIG_ARCH_AT91RM9200DK=y
 # CONFIG_MACH_CARMEVA is not set
 # CONFIG_MACH_KB9200 is not set
 # CONFIG_MACH_ATEB9200 is not set
+CONFIG_MACH_ECO920=y
 #
 # AT91RM9200 Feature Selections
diff --git a/arch/arm/configs/cm_x300_defconfig b/arch/arm/configs/cm_x300_defconfig
index d18d21bb41e4..a0170867130e 100644
--- a/arch/arm/configs/cm_x300_defconfig
+++ b/arch/arm/configs/cm_x300_defconfig
@@ -1,15 +1,13 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.30-rc8
+# Linux kernel version: 2.6.32-rc4
-# Thu Jun  4 09:53:21 2009
+# Tue Oct 13 19:03:13 2009
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_GENERIC_GPIO=y
 CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_MMU=y
-# CONFIG_NO_IOPORT is not set
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_HAVE_LATENCYTOP_SUPPORT=y
@@ -18,14 +16,14 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+CONFIG_ARCH_HAS_CPUFREQ=y
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_ARCH_MTD_XIP=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 #
 # General setup
@@ -46,11 +44,12 @@ CONFIG_SYSVIPC_SYSCTL=y
 #
 # RCU Subsystem
 #
-CONFIG_CLASSIC_RCU=y
+CONFIG_TREE_RCU=y
-# CONFIG_TREE_RCU is not set
+# CONFIG_TREE_PREEMPT_RCU is not set
-# CONFIG_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
 # CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_PREEMPT_RCU_TRACE is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=18
@@ -83,7 +82,6 @@ CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
-# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
@@ -96,6 +94,10 @@ CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_AIO=y
+#
+# Kernel Performance Events And Counters
+#
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLUB_DEBUG=y
 CONFIG_COMPAT_BRK=y
@@ -103,13 +105,17 @@ CONFIG_COMPAT_BRK=y
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
 # CONFIG_PROFILING is not set
-# CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
 # CONFIG_KPROBES is not set
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_KRETPROBES=y
 CONFIG_HAVE_CLK=y
-# CONFIG_SLOW_WORK is not set
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_SLOW_WORK=y
 CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
@@ -117,11 +123,11 @@ CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
 # CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
+CONFIG_LBDAF=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
@@ -142,19 +148,22 @@ CONFIG_FREEZER=y
 #
 # System Type
 #
+CONFIG_MMU=y
 # CONFIG_ARCH_AAEC2000 is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_REALVIEW is not set
 # CONFIG_ARCH_VERSATILE is not set
 # CONFIG_ARCH_AT91 is not set
 # CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
 # CONFIG_ARCH_EBSA110 is not set
 # CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_GEMINI is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_NOMADIK is not set
 # CONFIG_ARCH_IOP13XX is not set
 # CONFIG_ARCH_IOP32X is not set
 # CONFIG_ARCH_IOP33X is not set
@@ -163,25 +172,27 @@ CONFIG_FREEZER=y
 # CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
 # CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
 # CONFIG_ARCH_LOKI is not set
 # CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_MXC is not set
 # CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
 # CONFIG_ARCH_PNX4008 is not set
 CONFIG_ARCH_PXA=y
-# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_MSM is not set
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
 # CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
 # CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_BCMRING is not set
-# CONFIG_ARCH_W90X900 is not set
 #
 # Intel PXA2xx/PXA3xx Implementations
@@ -191,16 +202,19 @@ CONFIG_ARCH_PXA=y
 # Supported PXA3xx Processor Variants
 #
 CONFIG_CPU_PXA300=y
-# CONFIG_CPU_PXA310 is not set
+CONFIG_CPU_PXA310=y
 # CONFIG_CPU_PXA320 is not set
 # CONFIG_CPU_PXA930 is not set
 # CONFIG_CPU_PXA935 is not set
+# CONFIG_CPU_PXA950 is not set
 # CONFIG_ARCH_GUMSTIX is not set
 # CONFIG_MACH_INTELMOTE2 is not set
+# CONFIG_MACH_STARGATE2 is not set
 # CONFIG_ARCH_LUBBOCK is not set
 # CONFIG_MACH_LOGICPD_PXA270 is not set
 # CONFIG_MACH_MAINSTONE is not set
 # CONFIG_MACH_MP900C is not set
+# CONFIG_MACH_BALLOON3 is not set
 # CONFIG_ARCH_PXA_IDP is not set
 # CONFIG_PXA_SHARPSL is not set
 # CONFIG_ARCH_VIPER is not set
@@ -218,6 +232,7 @@ CONFIG_CPU_PXA300=y
 # CONFIG_MACH_SAAR is not set
 # CONFIG_MACH_ARMCORE is not set
 CONFIG_MACH_CM_X300=y
+# CONFIG_MACH_H4700 is not set
 # CONFIG_MACH_MAGICIAN is not set
 # CONFIG_MACH_HIMALAYA is not set
 # CONFIG_MACH_MIOA701 is not set
@@ -225,8 +240,8 @@ CONFIG_MACH_CM_X300=y
 # CONFIG_ARCH_PXA_PALM is not set
 # CONFIG_MACH_CSB726 is not set
 # CONFIG_PXA_EZX is not set
+# CONFIG_MACH_XCEP is not set
 CONFIG_PXA3xx=y
-# CONFIG_PXA_PWM is not set
 CONFIG_PLAT_PXA=y
 #
@@ -236,7 +251,7 @@ CONFIG_CPU_32=y
 CONFIG_CPU_XSC3=y
 CONFIG_CPU_32v5=y
 CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_PABRT_LEGACY=y
 CONFIG_CPU_CACHE_VIVT=y
 CONFIG_CPU_TLB_V4WBI=y
 CONFIG_CPU_CP15=y
@@ -246,11 +261,12 @@ CONFIG_IO_36=y
 #
 # Processor Features
 #
-# CONFIG_ARM_THUMB is not set
+CONFIG_ARM_THUMB=y
 # CONFIG_CPU_DCACHE_DISABLE is not set
 # CONFIG_CPU_BPREDICT_DISABLE is not set
 CONFIG_OUTER_CACHE=y
 CONFIG_CACHE_XSC3L2=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
 CONFIG_IWMMXT=y
 CONFIG_COMMON_CLKDEV=y
@@ -272,11 +288,12 @@ CONFIG_VMSPLIT_3G=y
 # CONFIG_VMSPLIT_2G is not set
 # CONFIG_VMSPLIT_1G is not set
 CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
 CONFIG_HZ=100
 CONFIG_AEABI=y
 CONFIG_OABI_COMPAT=y
-# CONFIG_ARCH_HAS_HOLES_MEMORYMODEL is not set
 # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
 # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
 CONFIG_HIGHMEM=y
@@ -292,17 +309,19 @@ CONFIG_SPLIT_PTLOCK_CPUS=4096
 CONFIG_ZONE_DMA_FLAG=0
 CONFIG_BOUNCE=y
 CONFIG_VIRT_TO_BUS=y
-CONFIG_UNEVICTABLE_LRU=y
 CONFIG_HAVE_MLOCK=y
 CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
 #
 # Boot options
 #
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/mtdblock5 rootfstype=jffs2 console=ttyS2,38400"
+CONFIG_CMDLINE="root=/dev/mtdblock5 rootfstype=ubifs console=ttyS2,38400"
 # CONFIG_XIP_KERNEL is not set
 # CONFIG_KEXEC is not set
@@ -355,6 +374,7 @@ CONFIG_PM_SLEEP=y
 CONFIG_SUSPEND=y
 CONFIG_SUSPEND_FREEZER=y
 CONFIG_APM_EMULATION=y
+# CONFIG_PM_RUNTIME is not set
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
 CONFIG_NET=y
@@ -396,6 +416,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
 # CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
@@ -410,6 +431,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
 # CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
 # CONFIG_DCB is not set
@@ -433,22 +455,27 @@ CONFIG_BT_HIDP=m
 #
 # Bluetooth device drivers
 #
-# CONFIG_BT_HCIBTUSB is not set
+CONFIG_BT_HCIBTUSB=m
 # CONFIG_BT_HCIBTSDIO is not set
 # CONFIG_BT_HCIUART is not set
 # CONFIG_BT_HCIBCM203X is not set
 # CONFIG_BT_HCIBPA10X is not set
 # CONFIG_BT_HCIBFUSB is not set
 # CONFIG_BT_HCIVHCI is not set
+# CONFIG_BT_MRVL is not set
 # CONFIG_AF_RXRPC is not set
 CONFIG_WIRELESS=y
 # CONFIG_CFG80211 is not set
+CONFIG_CFG80211_DEFAULT_PS_VALUE=0
 # CONFIG_WIRELESS_OLD_REGULATORY is not set
 CONFIG_WIRELESS_EXT=y
 CONFIG_WIRELESS_EXT_SYSFS=y
 CONFIG_LIB80211=m
 # CONFIG_LIB80211_DEBUG is not set
-# CONFIG_MAC80211 is not set
+#
+# CFG80211 needs to be enabled for MAC80211
+#
 # CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
@@ -461,6 +488,7 @@ CONFIG_LIB80211=m
 # Generic Driver Options
 #
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=y
@@ -472,9 +500,9 @@ CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_REDBOOT_PARTS is not set
 # CONFIG_MTD_CMDLINE_PARTS is not set
 # CONFIG_MTD_AFS_PARTS is not set
@@ -521,6 +549,9 @@ CONFIG_MTD_CFI_I2=y
 #
 # Self-contained MTD device drivers
 #
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SST25L is not set
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
@@ -556,7 +587,15 @@ CONFIG_MTD_NAND_PXA3xx=y
 #
 # UBI - Unsorted block images
 #
-# CONFIG_MTD_UBI is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
 # CONFIG_PARPORT is not set
 CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
@@ -570,6 +609,7 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
 # CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
 # CONFIG_MISC_DEVICES is not set
 CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
@@ -593,10 +633,6 @@ CONFIG_BLK_DEV_SD=y
 # CONFIG_BLK_DEV_SR is not set
 # CONFIG_CHR_DEV_SG is not set
 # CONFIG_CHR_DEV_SCH is not set
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
 # CONFIG_SCSI_MULTI_LUN is not set
 # CONFIG_SCSI_CONSTANTS is not set
 # CONFIG_SCSI_LOGGING is not set
@@ -621,7 +657,6 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
-CONFIG_COMPAT_NET_DEV_OPS=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -636,6 +671,7 @@ CONFIG_MII=y
 CONFIG_DM9000=y
 CONFIG_DM9000_DEBUGLEVEL=0
 CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL=y
+# CONFIG_ENC28J60 is not set
 # CONFIG_ETHOC is not set
 # CONFIG_SMC911X is not set
 # CONFIG_SMSC911X is not set
@@ -648,20 +684,20 @@ CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL=y
 # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
 # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 # CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
+CONFIG_WLAN=y
-#
-# Wireless LAN
-#
 # CONFIG_WLAN_PRE80211 is not set
 CONFIG_WLAN_80211=y
 CONFIG_LIBERTAS=m
 # CONFIG_LIBERTAS_USB is not set
 CONFIG_LIBERTAS_SDIO=m
+# CONFIG_LIBERTAS_SPI is not set
 # CONFIG_LIBERTAS_DEBUG is not set
 # CONFIG_USB_ZD1201 is not set
-# CONFIG_USB_NET_RNDIS_WLAN is not set
 # CONFIG_HOSTAP is not set
 #
@@ -683,6 +719,7 @@ CONFIG_LIBERTAS_SDIO=m
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
 # CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
 #
 # Input device support
@@ -706,33 +743,51 @@ CONFIG_INPUT_EVDEV=y
 # Input Device Drivers
 #
 CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
 # CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_QT2160 is not set
 # CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
 # CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
 CONFIG_KEYBOARD_PXA27x=m
-# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
 # CONFIG_INPUT_TABLET is not set
 CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
 # CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
 # CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_DA9034 is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
 # CONFIG_TOUCHSCREEN_FUJITSU is not set
 # CONFIG_TOUCHSCREEN_GUNZE is not set
 # CONFIG_TOUCHSCREEN_ELO is not set
 # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
 # CONFIG_TOUCHSCREEN_MTOUCH is not set
 # CONFIG_TOUCHSCREEN_INEXIO is not set
 # CONFIG_TOUCHSCREEN_MK712 is not set
 # CONFIG_TOUCHSCREEN_PENMOUNT is not set
 # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
 # CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+CONFIG_TOUCHSCREEN_WM97XX=m
+# CONFIG_TOUCHSCREEN_WM9705 is not set
+CONFIG_TOUCHSCREEN_WM9712=y
+# CONFIG_TOUCHSCREEN_WM9713 is not set
+# CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE is not set
 # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
 # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
 # CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
 # CONFIG_INPUT_MISC is not set
 #
@@ -760,6 +815,7 @@ CONFIG_DEVKMEM=y
 #
 # Non-8250 serial port support
 #
+# CONFIG_SERIAL_MAX3100 is not set
 CONFIG_SERIAL_PXA=y
 CONFIG_SERIAL_PXA_CONSOLE=y
 CONFIG_SERIAL_CORE=y
@@ -774,6 +830,7 @@ CONFIG_UNIX98_PTYS=y
 # CONFIG_TCG_TPM is not set
 CONFIG_I2C=y
 CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
 # CONFIG_I2C_CHARDEV is not set
 CONFIG_I2C_HELPER_AUTO=y
@@ -784,6 +841,7 @@ CONFIG_I2C_HELPER_AUTO=y
 #
 # I2C system bus drivers (mostly embedded / system-on-chip)
 #
+# CONFIG_I2C_DESIGNWARE is not set
 # CONFIG_I2C_GPIO is not set
 # CONFIG_I2C_OCORES is not set
 CONFIG_I2C_PXA=y
@@ -807,19 +865,36 @@ CONFIG_I2C_PXA=y
 # Miscellaneous I2C Chip support
 #
 # CONFIG_DS1682 is not set
-# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_PCF8575 is not set
-# CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
 # CONFIG_I2C_DEBUG_CHIP is not set
-# CONFIG_SPI is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_GPIO=y
+# CONFIG_SPI_PXA2XX is not set
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+#
+# PPS support
+#
+# CONFIG_PPS is not set
 CONFIG_ARCH_REQUIRE_GPIOLIB=y
 CONFIG_GPIOLIB=y
 # CONFIG_DEBUG_GPIO is not set
-# CONFIG_GPIO_SYSFS is not set
+CONFIG_GPIO_SYSFS=y
 #
 # Memory mapped GPIO expanders:
@@ -839,11 +914,17 @@ CONFIG_GPIO_PCA953X=y
 #
 # SPI GPIO expanders:
 #
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+#
+# AC97 GPIO expanders:
+#
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
 # CONFIG_THERMAL is not set
-# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 CONFIG_SSB_POSSIBLE=y
@@ -860,32 +941,33 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_MFD_ASIC3 is not set
 # CONFIG_HTC_EGPIO is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_UCB1400_CORE is not set
 # CONFIG_TPS65010 is not set
 # CONFIG_TWL4030_CORE is not set
 # CONFIG_MFD_TMIO is not set
 # CONFIG_MFD_T7L66XB is not set
 # CONFIG_MFD_TC6387XB is not set
 # CONFIG_MFD_TC6393XB is not set
-# CONFIG_PMIC_DA903X is not set
+CONFIG_PMIC_DA903X=y
 # CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
 # CONFIG_MFD_WM8350_I2C is not set
 # CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
-#
+# CONFIG_AB3100_CORE is not set
-# Multimedia devices
+# CONFIG_EZX_PCAP is not set
-#
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
-#
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
-# Multimedia core support
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-#
+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
-# CONFIG_VIDEO_DEV is not set
+# CONFIG_REGULATOR_BQ24022 is not set
-# CONFIG_DVB_CORE is not set
+# CONFIG_REGULATOR_MAX1586 is not set
-# CONFIG_VIDEO_MEDIA is not set
+CONFIG_REGULATOR_DA903X=y
+# CONFIG_REGULATOR_LP3971 is not set
-#
+# CONFIG_REGULATOR_TPS65023 is not set
-# Multimedia drivers
+# CONFIG_REGULATOR_TPS6507X is not set
-#
+# CONFIG_MEDIA_SUPPORT is not set
-# CONFIG_DAB is not set
 #
 # Graphics support
@@ -925,7 +1007,17 @@ CONFIG_FB_PXA=y
 # CONFIG_FB_METRONOME is not set
 # CONFIG_FB_MB862XX is not set
 # CONFIG_FB_BROADSHEET is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_LMS283GF05 is not set
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_ILI9320 is not set
+CONFIG_LCD_TDO24M=y
+# CONFIG_LCD_VGG2432A4 is not set
+# CONFIG_LCD_PLATFORM is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=m
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_DA903X=m
 #
 # Display device support
@@ -956,38 +1048,48 @@ CONFIG_LOGO_LINUX_MONO=y
 CONFIG_LOGO_LINUX_VGA16=y
 CONFIG_LOGO_LINUX_CLUT224=y
 CONFIG_SOUND=m
-# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
 CONFIG_SND=m
 CONFIG_SND_TIMER=m
 CONFIG_SND_PCM=m
 CONFIG_SND_JACK=y
 # CONFIG_SND_SEQUENCER is not set
-# CONFIG_SND_MIXER_OSS is not set
+CONFIG_SND_OSSEMUL=y
-# CONFIG_SND_PCM_OSS is not set
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
 # CONFIG_SND_DYNAMIC_MINORS is not set
 CONFIG_SND_SUPPORT_OLD_API=y
 CONFIG_SND_VERBOSE_PROCFS=y
 # CONFIG_SND_VERBOSE_PRINTK is not set
 # CONFIG_SND_DEBUG is not set
-CONFIG_SND_DRIVERS=y
+CONFIG_SND_VMASTER=y
-# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
-# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
-# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
-# CONFIG_SND_MPU401 is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_AC97_CODEC=m
+# CONFIG_SND_DRIVERS is not set
 CONFIG_SND_ARM=y
 CONFIG_SND_PXA2XX_LIB=m
+CONFIG_SND_PXA2XX_LIB_AC97=y
 # CONFIG_SND_PXA2XX_AC97 is not set
-CONFIG_SND_USB=y
+# CONFIG_SND_SPI is not set
-# CONFIG_SND_USB_AUDIO is not set
+# CONFIG_SND_USB is not set
-# CONFIG_SND_USB_CAIAQ is not set
 CONFIG_SND_SOC=m
+CONFIG_SND_SOC_AC97_BUS=y
 CONFIG_SND_PXA2XX_SOC=m
+CONFIG_SND_PXA2XX_SOC_AC97=m
+CONFIG_SND_PXA2XX_SOC_EM_X270=m
 CONFIG_SND_SOC_I2C_AND_SPI=m
 # CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_WM9712=m
 # CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=m
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
-CONFIG_HID_DEBUG=y
 # CONFIG_HIDRAW is not set
 #
@@ -1006,10 +1108,12 @@ CONFIG_HID_BELKIN=y
 CONFIG_HID_CHERRY=y
 CONFIG_HID_CHICONY=y
 CONFIG_HID_CYPRESS=y
+CONFIG_HID_DRAGONRISE=y
 # CONFIG_DRAGONRISE_FF is not set
 CONFIG_HID_EZKEY=y
 CONFIG_HID_KYE=y
 CONFIG_HID_GYRATION=y
+CONFIG_HID_TWINHAN=y
 CONFIG_HID_KENSINGTON=y
 CONFIG_HID_LOGITECH=y
 # CONFIG_LOGITECH_FF is not set
@@ -1023,9 +1127,15 @@ CONFIG_HID_PETALYNX=y
 CONFIG_HID_SAMSUNG=y
 CONFIG_HID_SONY=y
 CONFIG_HID_SUNPLUS=y
+CONFIG_HID_GREENASIA=y
 # CONFIG_GREENASIA_FF is not set
+CONFIG_HID_SMARTJOYPLUS=y
+# CONFIG_SMARTJOYPLUS_FF is not set
 CONFIG_HID_TOPSEED=y
+CONFIG_HID_THRUSTMASTER=y
 # CONFIG_THRUSTMASTER_FF is not set
+CONFIG_HID_WACOM=m
+CONFIG_HID_ZEROPLUS=y
 # CONFIG_ZEROPLUS_FF is not set
 CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
@@ -1054,6 +1164,7 @@ CONFIG_USB_MON=y
 # CONFIG_USB_OXU210HP_HCD is not set
 # CONFIG_USB_ISP116X_HCD is not set
 # CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
 CONFIG_USB_OHCI_HCD=y
 # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
 # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
@@ -1151,8 +1262,9 @@ CONFIG_MMC_BLOCK_BOUNCE=y
 #
 CONFIG_MMC_PXA=m
 # CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_AT91 is not set
+# CONFIG_MMC_ATMELMCI is not set
 # CONFIG_MEMSTICK is not set
-# CONFIG_ACCESSIBILITY is not set
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
@@ -1162,8 +1274,10 @@ CONFIG_LEDS_CLASS=y
 # CONFIG_LEDS_PCA9532 is not set
 CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_GPIO_PLATFORM=y
-# CONFIG_LEDS_LP5521 is not set
+# CONFIG_LEDS_LP3944 is not set
 # CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_DA903X is not set
+# CONFIG_LEDS_DAC124S085 is not set
 # CONFIG_LEDS_BD2802 is not set
 #
@@ -1179,6 +1293,7 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 #
 # iptables trigger is under Netfilter config (LED target)
 #
+# CONFIG_ACCESSIBILITY is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_HCTOSYS=y
@@ -1210,10 +1325,19 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_S35390A is not set
 # CONFIG_RTC_DRV_FM3130 is not set
 # CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
 #
 # SPI RTC drivers
 #
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
 #
 # Platform RTC drivers
@@ -1233,12 +1357,15 @@ CONFIG_RTC_DRV_V3020=y
 #
 # on-CPU RTC drivers
 #
-CONFIG_RTC_DRV_SA1100=y
+# CONFIG_RTC_DRV_SA1100 is not set
-# CONFIG_RTC_DRV_PXA is not set
+CONFIG_RTC_DRV_PXA=y
 # CONFIG_DMADEVICES is not set
 # CONFIG_AUXDISPLAY is not set
-# CONFIG_REGULATOR is not set
 # CONFIG_UIO is not set
+#
+# TI VLYNQ
+#
 # CONFIG_STAGING is not set
 #
@@ -1256,10 +1383,13 @@ CONFIG_JBD=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 CONFIG_FS_POSIX_ACL=y
-CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
 CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -1319,6 +1449,12 @@ CONFIG_JFFS2_ZLIB=y
 # CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_XATTR is not set
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_DEBUG is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
@@ -1329,12 +1465,12 @@ CONFIG_JFFS2_RTIME=y
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-# CONFIG_NILFS2_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 CONFIG_NFS_V3_ACL=y
 CONFIG_NFS_V4=y
+# CONFIG_NFS_V4_1 is not set
 CONFIG_ROOT_NFS=y
 # CONFIG_NFSD is not set
 CONFIG_LOCKD=y
@@ -1378,7 +1514,7 @@ CONFIG_MSDOS_PARTITION=y
 # CONFIG_KARMA_PARTITION is not set
 # CONFIG_EFI_PARTITION is not set
 # CONFIG_SYSV68_PARTITION is not set
-CONFIG_NLS=m
+CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=m
 # CONFIG_NLS_CODEPAGE_737 is not set
@@ -1428,6 +1564,7 @@ CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
@@ -1441,6 +1578,7 @@ CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_OBJECTS is not set
 # CONFIG_SLUB_DEBUG_ON is not set
 # CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
 # CONFIG_DEBUG_RT_MUTEXES is not set
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
@@ -1460,32 +1598,20 @@ CONFIG_DEBUG_MEMORY_INIT=y
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
 # CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
 # CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
 # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
 # CONFIG_FAULT_INJECTION is not set
 # CONFIG_LATENCYTOP is not set
 CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_PAGE_POISONING is not set
 CONFIG_HAVE_FUNCTION_TRACER=y
 CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
-#
-# Tracers
-#
-# CONFIG_FUNCTION_TRACER is not set
-# CONFIG_IRQSOFF_TRACER is not set
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
-# CONFIG_EVENT_TRACER is not set
-# CONFIG_BOOT_TRACER is not set
-# CONFIG_TRACE_BRANCH_PROFILING is not set
-# CONFIG_STACK_TRACER is not set
-# CONFIG_KMEMTRACE is not set
-# CONFIG_WORKQUEUE_TRACER is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
@@ -1509,7 +1635,6 @@ CONFIG_CRYPTO=y
 #
 # Crypto core or helper
 #
-# CONFIG_CRYPTO_FIPS is not set
 CONFIG_CRYPTO_ALGAPI=y
 CONFIG_CRYPTO_ALGAPI2=y
 CONFIG_CRYPTO_AEAD2=y
@@ -1551,11 +1676,13 @@ CONFIG_CRYPTO_ECB=m
 #
 # CONFIG_CRYPTO_HMAC is not set
 # CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
 #
 # Digest
 #
 # CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
 # CONFIG_CRYPTO_MD4 is not set
 CONFIG_CRYPTO_MD5=y
 CONFIG_CRYPTO_MICHAEL_MIC=m
@@ -1591,9 +1718,9 @@ CONFIG_CRYPTO_DES=y
 #
 # Compression
 #
-# CONFIG_CRYPTO_DEFLATE is not set
+CONFIG_CRYPTO_DEFLATE=y
 # CONFIG_CRYPTO_ZLIB is not set
-# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_LZO=y
 #
 # Random Number Generation
@@ -1608,7 +1735,7 @@ CONFIG_CRYPTO_DES=y
 CONFIG_BITREVERSE=y
 CONFIG_GENERIC_FIND_LAST_BIT=y
 # CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
+CONFIG_CRC16=y
 CONFIG_CRC_T10DIF=y
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
@@ -1616,6 +1743,8 @@ CONFIG_CRC32=y
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
 CONFIG_DECOMPRESS_GZIP=y
 CONFIG_DECOMPRESS_BZIP2=y
 CONFIG_DECOMPRESS_LZMA=y
diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig
new file mode 100644
index 000000000000..b3a491675d59
--- /dev/null
+++ b/arch/arm/configs/dove_defconfig
@@ -0,0 +1,1620 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32-rc6
+# Tue Nov 24 13:53:37 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_PCI_QUIRKS=y
+CONFIG_COMPAT_BRK=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_FREEZER is not set
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+CONFIG_ARCH_DOVE=y
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_BCMRING is not set
+#
+# Marvell Dove Implementations
+#
+CONFIG_MACH_DOVE_DB=y
+CONFIG_PLAT_ORION=y
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_V6=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v6=y
+CONFIG_CPU_ABRT_EV6=y
+CONFIG_CPU_PABRT_V6=y
+CONFIG_CPU_CACHE_V6=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V6=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_OUTER_CACHE=y
+CONFIG_CACHE_TAUROS2=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
+# CONFIG_ARM_ERRATA_411920 is not set
+#
+# Bus support
+#
+CONFIG_PCI=y
+CONFIG_PCI_SYSCALL=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
+# CONFIG_PCCARD is not set
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+#
+# Floating point emulation
+#
+#
+# At least one emulation must be selected
+#
+# CONFIG_FPE_NWFPE is not set
+# CONFIG_FPE_FASTFPE is not set
+CONFIG_VFP=y
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+#
+# Device Drivers
+#
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_IMPA7 is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_DATAFLASH is not set
+CONFIG_MTD_M25P80=y
+CONFIG_M25PXX_USE_FAST_READ=y
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+#
+# UBI - Unsorted block images
+#
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=1
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_SATA_PMP=y
+# CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_SVW is not set
+# CONFIG_ATA_PIIX is not set
+CONFIG_SATA_MV=y
+# CONFIG_SATA_NV is not set
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATP867X is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RDC is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+#
+# IEEE 1394 (FireWire) support
+#
+#
+# You can enable one or both FireWire driver stacks.
+#
+#
+# See the help texts for more information.
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+CONFIG_PHYLIB=y
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+# CONFIG_NET_ETHERNET is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_IGBVF is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_CNIC is not set
+CONFIG_MV643XX_ETH=y
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_ATL1C is not set
+# CONFIG_JME is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+CONFIG_WLAN=y
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+CONFIG_INPUT_POLLDEV=y
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_QT2160 is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_INPUT_MOUSE=y
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+# CONFIG_SERIAL_8250_EXTENDED is not set
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=16
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+#
+# I2C Hardware Bus support
+#
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+CONFIG_I2C_MV64XXX=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+#
+# Graphics adapter I2C/DDC channel drivers
+#
+# CONFIG_I2C_VOODOO3 is not set
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_ORION=y
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+#
+# Memory mapped GPIO expanders:
+#
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+#
+# PCI GPIO expanders:
+#
+# CONFIG_GPIO_BT8XX is not set
+# CONFIG_GPIO_LANGWELL is not set
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+#
+# AC97 GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+#
+# Graphics support
+#
+CONFIG_VGA_ARB=y
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_XHCI_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_WHCI_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+# CONFIG_USB_GADGET is not set
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_UWB is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_MV=y
+CONFIG_DMADEVICES=y
+#
+# DMA Devices
+#
+CONFIG_MV_XOR=y
+CONFIG_DMA_ENGINE=y
+#
+# DMA Clients
+#
+# CONFIG_NET_DMA is not set
+# CONFIG_ASYNC_TX_DMA is not set
+# CONFIG_DMATEST is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+# CONFIG_ZISOFS is not set
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_UBIFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=y
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARM_UNWIND=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_GHASH is not set
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+CONFIG_CRYPTO_BLOWFISH=y
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+CONFIG_CRYPTO_TEA=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_TWOFISH_COMMON=y
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_ZLIB is not set
+CONFIG_CRYPTO_LZO=y
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_MV_CESA is not set
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+# CONFIG_BINARY_PRINTF is not set
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/ezx_defconfig b/arch/arm/configs/ezx_defconfig
index d5ee16e6abf3..492f29aba332 100644
--- a/arch/arm/configs/ezx_defconfig
+++ b/arch/arm/configs/ezx_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.26-rc3
+# Linux kernel version: 2.6.32-rc5
-# Mon Jul  7 17:52:21 2008
+# Mon Nov  2 13:18:50 2009
 #
 CONFIG_ARM=y
 CONFIG_HAVE_PWM=y
@@ -9,24 +9,22 @@ CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_GENERIC_GPIO=y
 CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_MMU=y
-# CONFIG_NO_IOPORT is not set
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
 CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+CONFIG_ARCH_HAS_CPUFREQ=y
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ARCH_SUPPORTS_AOUT=y
-CONFIG_ZONE_DMA=y
 CONFIG_ARCH_MTD_XIP=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 #
 # General setup
@@ -35,7 +33,7 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_LOCK_KERNEL=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_LOCALVERSION="-ezxdev"
+CONFIG_LOCALVERSION="-ezx200910312315"
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
@@ -44,56 +42,78 @@ CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CGROUPS is not set
 CONFIG_GROUP_SCHED=y
 CONFIG_FAIR_GROUP_SCHED=y
 # CONFIG_RT_GROUP_SCHED is not set
 CONFIG_USER_SCHED=y
 # CONFIG_CGROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
 # CONFIG_NAMESPACES is not set
-# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
-# CONFIG_COMPAT_BRK is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
+CONFIG_AIO=y
+#
+# Kernel Performance Events And Counters
+#
 CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_COMPAT_BRK is not set
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
 # CONFIG_PROFILING is not set
-# CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
 # CONFIG_KPROBES is not set
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_KRETPROBES=y
-# CONFIG_HAVE_DMA_ATTRS is not set
+CONFIG_HAVE_CLK=y
-CONFIG_PROC_PAGE_MONITOR=y
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_SLOW_WORK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
 # CONFIG_MODULE_FORCE_LOAD is not set
@@ -101,12 +121,10 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 # CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
+# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 #
 # IO Schedulers
@@ -120,25 +138,27 @@ CONFIG_DEFAULT_DEADLINE=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="deadline"
-CONFIG_CLASSIC_RCU=y
+CONFIG_FREEZER=y
 #
 # System Type
 #
+CONFIG_MMU=y
 # CONFIG_ARCH_AAEC2000 is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_REALVIEW is not set
 # CONFIG_ARCH_VERSATILE is not set
 # CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS7500 is not set
 # CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_GEMINI is not set
 # CONFIG_ARCH_EBSA110 is not set
 # CONFIG_ARCH_EP93XX is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_NOMADIK is not set
 # CONFIG_ARCH_IOP13XX is not set
 # CONFIG_ARCH_IOP32X is not set
 # CONFIG_ARCH_IOP33X is not set
@@ -146,39 +166,64 @@ CONFIG_CLASSIC_RCU=y
 # CONFIG_ARCH_IXP2000 is not set
 # CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
 # CONFIG_ARCH_KS8695 is not set
 # CONFIG_ARCH_NS9XXX is not set
-# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_W90X900 is not set
-# CONFIG_ARCH_ORION5X is not set
 # CONFIG_ARCH_PNX4008 is not set
 CONFIG_ARCH_PXA=y
+# CONFIG_ARCH_MSM is not set
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
 # CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_MSM7X00A is not set
+# CONFIG_ARCH_BCMRING is not set
 #
 # Intel PXA2xx/PXA3xx Implementations
 #
 # CONFIG_ARCH_GUMSTIX is not set
+# CONFIG_MACH_INTELMOTE2 is not set
+# CONFIG_MACH_STARGATE2 is not set
 # CONFIG_ARCH_LUBBOCK is not set
 # CONFIG_MACH_LOGICPD_PXA270 is not set
 # CONFIG_MACH_MAINSTONE is not set
+# CONFIG_MACH_MP900C is not set
+# CONFIG_MACH_BALLOON3 is not set
 # CONFIG_ARCH_PXA_IDP is not set
 # CONFIG_PXA_SHARPSL is not set
+# CONFIG_ARCH_VIPER is not set
 # CONFIG_ARCH_PXA_ESERIES is not set
-# CONFIG_MACH_TRIZEPS4 is not set
+# CONFIG_TRIZEPS_PXA is not set
+# CONFIG_MACH_H5000 is not set
 # CONFIG_MACH_EM_X270 is not set
+# CONFIG_MACH_EXEDA is not set
 # CONFIG_MACH_COLIBRI is not set
+# CONFIG_MACH_COLIBRI300 is not set
+# CONFIG_MACH_COLIBRI320 is not set
 # CONFIG_MACH_ZYLONITE is not set
 # CONFIG_MACH_LITTLETON is not set
+# CONFIG_MACH_TAVOREVB is not set
+# CONFIG_MACH_SAAR is not set
 # CONFIG_MACH_ARMCORE is not set
+# CONFIG_MACH_CM_X300 is not set
+# CONFIG_MACH_H4700 is not set
 # CONFIG_MACH_MAGICIAN is not set
+# CONFIG_MACH_HIMALAYA is not set
+# CONFIG_MACH_MIOA701 is not set
 # CONFIG_MACH_PCM027 is not set
+# CONFIG_ARCH_PXA_PALM is not set
+# CONFIG_MACH_CSB726 is not set
 CONFIG_PXA_EZX=y
 CONFIG_MACH_EZX_A780=y
 CONFIG_MACH_EZX_E680=y
@@ -186,17 +231,11 @@ CONFIG_MACH_EZX_A1200=y
 CONFIG_MACH_EZX_A910=y
 CONFIG_MACH_EZX_E6=y
 CONFIG_MACH_EZX_E2=y
+# CONFIG_MACH_XCEP is not set
 CONFIG_PXA27x=y
 CONFIG_PXA_SSP=y
-CONFIG_PXA_PWM=y
+CONFIG_PXA_HAVE_BOARD_IRQS=y
+CONFIG_PLAT_PXA=y
-#
-# Boot options
-#
-#
-# Power management
-#
 #
 # Processor Type
@@ -205,7 +244,7 @@ CONFIG_CPU_32=y
 CONFIG_CPU_XSCALE=y
 CONFIG_CPU_32v5=y
 CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_PABRT_LEGACY=y
 CONFIG_CPU_CACHE_VIVT=y
 CONFIG_CPU_TLB_V4WBI=y
 CONFIG_CPU_CP15=y
@@ -216,9 +255,10 @@ CONFIG_CPU_CP15_MMU=y
 #
 CONFIG_ARM_THUMB=y
 # CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_OUTER_CACHE is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
 CONFIG_IWMMXT=y
 CONFIG_XSCALE_PMU=y
+CONFIG_COMMON_CLKDEV=y
 #
 # Bus support
@@ -231,44 +271,71 @@ CONFIG_XSCALE_PMU=y
 # Kernel Features
 #
 CONFIG_TICK_ONESHOT=y
-# CONFIG_NO_HZ is not set
+CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
 CONFIG_PREEMPT=y
 CONFIG_HZ=100
 CONFIG_AEABI=y
 CONFIG_OABI_COMPAT=y
-# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=1
+CONFIG_ZONE_DMA_FLAG=0
-CONFIG_BOUNCE=y
 CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
 #
 # Boot options
 #
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=tty1 root=/dev/mmcblk0p2 rootfstype=ext2 rootdelay=1 ip=192.168.0.202:192.168.0.200:192.168.0.200:255.255.255.0 debug"
+CONFIG_CMDLINE="console=tty1 root=/dev/mmcblk0p2 rootfstype=ext2 rootdelay=3 ip=192.168.0.202:192.168.0.200:192.168.0.200:255.255.255.0 debug"
 # CONFIG_XIP_KERNEL is not set
 CONFIG_KEXEC=y
 CONFIG_ATAGS_PROC=y
 #
-# CPU Frequency scaling
+# CPU Power Management
-#
+#
-# CONFIG_CPU_FREQ is not set
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+CONFIG_CPU_FREQ_DEBUG=y
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=m
+CONFIG_CPU_FREQ_GOV_USERSPACE=m
+CONFIG_CPU_FREQ_GOV_ONDEMAND=m
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
 #
 # Floating point emulation
@@ -285,6 +352,8 @@ CONFIG_FPE_NWFPE=y
 # Userspace binary formats
 #
 CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
 CONFIG_BINFMT_AOUT=m
 CONFIG_BINFMT_MISC=m
@@ -297,11 +366,8 @@ CONFIG_PM_SLEEP=y
 CONFIG_SUSPEND=y
 CONFIG_SUSPEND_FREEZER=y
 CONFIG_APM_EMULATION=y
+CONFIG_PM_RUNTIME=y
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
-#
-# Networking
-#
 CONFIG_NET=y
 #
@@ -315,6 +381,7 @@ CONFIG_XFRM=y
 # CONFIG_XFRM_SUB_POLICY is not set
 # CONFIG_XFRM_MIGRATE is not set
 # CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
@@ -342,7 +409,6 @@ CONFIG_INET_TUNNEL=m
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
-# CONFIG_IP_VS is not set
 CONFIG_IPV6=m
 # CONFIG_IPV6_PRIVACY is not set
 # CONFIG_IPV6_ROUTER_PREF is not set
@@ -393,18 +459,22 @@ CONFIG_NF_CONNTRACK_SANE=m
 CONFIG_NF_CONNTRACK_SIP=m
 CONFIG_NF_CONNTRACK_TFTP=m
 CONFIG_NF_CT_NETLINK=m
+# CONFIG_NETFILTER_TPROXY is not set
 CONFIG_NETFILTER_XTABLES=m
 CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
 # CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
 # CONFIG_NETFILTER_XT_TARGET_DSCP is not set
+CONFIG_NETFILTER_XT_TARGET_HL=m
+CONFIG_NETFILTER_XT_TARGET_LED=m
 CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
 CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
 # CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
 # CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
 # CONFIG_NETFILTER_XT_TARGET_TRACE is not set
 CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
 # CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
+# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
 CONFIG_NETFILTER_XT_MATCH_COMMENT=m
 CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
 CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
@@ -413,20 +483,23 @@ CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
 CONFIG_NETFILTER_XT_MATCH_DCCP=m
 CONFIG_NETFILTER_XT_MATCH_DSCP=m
 CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
 CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_HL=m
 # CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
 CONFIG_NETFILTER_XT_MATCH_LENGTH=m
 CONFIG_NETFILTER_XT_MATCH_LIMIT=m
 CONFIG_NETFILTER_XT_MATCH_MAC=m
 CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
 # CONFIG_NETFILTER_XT_MATCH_OWNER is not set
 CONFIG_NETFILTER_XT_MATCH_POLICY=m
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
 # CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
 CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
 CONFIG_NETFILTER_XT_MATCH_QUOTA=m
 # CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
 CONFIG_NETFILTER_XT_MATCH_REALM=m
+# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
 CONFIG_NETFILTER_XT_MATCH_SCTP=m
 CONFIG_NETFILTER_XT_MATCH_STATE=m
 CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
@@ -434,20 +507,21 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m
 CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
 CONFIG_NETFILTER_XT_MATCH_TIME=m
 CONFIG_NETFILTER_XT_MATCH_U32=m
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+# CONFIG_NETFILTER_XT_MATCH_OSF is not set
+# CONFIG_IP_VS is not set
 #
 # IP: Netfilter Configuration
 #
+CONFIG_NF_DEFRAG_IPV4=m
 CONFIG_NF_CONNTRACK_IPV4=m
 CONFIG_NF_CONNTRACK_PROC_COMPAT=y
 CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_RECENT=m
+CONFIG_IP_NF_MATCH_ADDRTYPE=m
-CONFIG_IP_NF_MATCH_ECN=m
 CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
 CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
 CONFIG_IP_NF_TARGET_LOG=m
@@ -455,8 +529,8 @@ CONFIG_IP_NF_TARGET_ULOG=m
 CONFIG_NF_NAT=m
 CONFIG_NF_NAT_NEEDED=y
 CONFIG_IP_NF_TARGET_MASQUERADE=m
-CONFIG_IP_NF_TARGET_REDIRECT=m
 CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
 CONFIG_NF_NAT_SNMP_BASIC=m
 CONFIG_NF_NAT_PROTO_GRE=m
 CONFIG_NF_NAT_PROTO_UDPLITE=m
@@ -469,9 +543,9 @@ CONFIG_NF_NAT_PPTP=m
 CONFIG_NF_NAT_H323=m
 CONFIG_NF_NAT_SIP=m
 CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
 CONFIG_IP_NF_TARGET_ECN=m
 CONFIG_IP_NF_TARGET_TTL=m
-CONFIG_IP_NF_TARGET_CLUSTERIP=m
 CONFIG_IP_NF_RAW=m
 CONFIG_IP_NF_ARPTABLES=m
 CONFIG_IP_NF_ARPFILTER=m
@@ -483,30 +557,29 @@ CONFIG_IP_NF_ARP_MANGLE=m
 CONFIG_NF_CONNTRACK_IPV6=m
 CONFIG_IP6_NF_QUEUE=m
 CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_MATCH_AH=m
-CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_EUI64=m
 CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_OPTS=m
 CONFIG_IP6_NF_MATCH_HL=m
 CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_MATCH_AH=m
 CONFIG_IP6_NF_MATCH_MH=m
-CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_MATCH_RT=m
-CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_HL=m
 CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_TARGET_HL=m
 CONFIG_IP6_NF_RAW=m
-#
-# Bridge: Netfilter Configuration
-#
 # CONFIG_BRIDGE_NF_EBTABLES is not set
 # CONFIG_IP_DCCP is not set
 # CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
+CONFIG_STP=m
 CONFIG_BRIDGE=m
+# CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 CONFIG_LLC=m
@@ -517,9 +590,11 @@ CONFIG_LLC=m
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
 CONFIG_NET_CLS_ROUTE=y
-CONFIG_NET_SCH_FIFO=y
+# CONFIG_DCB is not set
 #
 # Network testing
@@ -529,64 +604,34 @@ CONFIG_NET_SCH_FIFO=y
 # CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 CONFIG_BT=y
-CONFIG_BT_L2CAP=m
+CONFIG_BT_L2CAP=y
 CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM=y
 CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP=y
 CONFIG_BT_BNEP_MC_FILTER=y
 CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_HIDP=m
+CONFIG_BT_HIDP=y
 #
 # Bluetooth device drivers
 #
-# CONFIG_BT_HCIUSB is not set
+CONFIG_BT_HCIBTUSB=m
-# CONFIG_BT_HCIBTUSB is not set
+CONFIG_BT_HCIBTSDIO=m
-# CONFIG_BT_HCIBTSDIO is not set
 CONFIG_BT_HCIUART=y
 CONFIG_BT_HCIUART_H4=y
 # CONFIG_BT_HCIUART_BCSP is not set
 # CONFIG_BT_HCIUART_LL is not set
-# CONFIG_BT_HCIBCM203X is not set
+CONFIG_BT_HCIBCM203X=m
-# CONFIG_BT_HCIBPA10X is not set
+CONFIG_BT_HCIBPA10X=m
-# CONFIG_BT_HCIBFUSB is not set
+CONFIG_BT_HCIBFUSB=m
-# CONFIG_BT_HCIVHCI is not set
+CONFIG_BT_HCIVHCI=m
+CONFIG_BT_MRVL=m
+CONFIG_BT_MRVL_SDIO=m
 # CONFIG_AF_RXRPC is not set
 CONFIG_FIB_RULES=y
+# CONFIG_WIRELESS is not set
-#
+# CONFIG_WIMAX is not set
-# Wireless
-#
-CONFIG_CFG80211=m
-CONFIG_NL80211=y
-CONFIG_WIRELESS_EXT=y
-CONFIG_MAC80211=m
-#
-# Rate control algorithm selection
-#
-CONFIG_MAC80211_RC_DEFAULT_PID=y
-# CONFIG_MAC80211_RC_DEFAULT_NONE is not set
-#
-# Selecting 'y' for an algorithm will
-#
-#
-# build the algorithm into mac80211.
-#
-CONFIG_MAC80211_RC_DEFAULT="pid"
-CONFIG_MAC80211_RC_PID=y
-# CONFIG_MAC80211_MESH is not set
-CONFIG_MAC80211_LEDS=y
-# CONFIG_MAC80211_DEBUG_PACKET_ALIGNMENT is not set
-# CONFIG_MAC80211_DEBUG is not set
-CONFIG_IEEE80211=m
-# CONFIG_IEEE80211_DEBUG is not set
-CONFIG_IEEE80211_CRYPT_WEP=m
-CONFIG_IEEE80211_CRYPT_CCMP=m
-CONFIG_IEEE80211_CRYPT_TKIP=m
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
@@ -598,13 +643,19 @@ CONFIG_IEEE80211_CRYPT_TKIP=m
 # Generic Driver Options
 #
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=m
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
 CONFIG_CONNECTOR=m
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
@@ -616,9 +667,9 @@ CONFIG_MTD_PARTITIONS=y
 # User Modules And Translation Layers
 #
 CONFIG_MTD_CHAR=y
-# CONFIG_MTD_BLKDEVS is not set
+CONFIG_HAVE_MTD_OTP=y
-# CONFIG_MTD_BLOCK is not set
+CONFIG_MTD_BLKDEVS=y
-# CONFIG_MTD_BLOCK_RO is not set
+CONFIG_MTD_BLOCK=y
 # CONFIG_FTL is not set
 # CONFIG_NFTL is not set
 # CONFIG_INFTL is not set
@@ -647,7 +698,7 @@ CONFIG_MTD_CFI_I1=y
 # CONFIG_MTD_CFI_I2 is not set
 # CONFIG_MTD_CFI_I4 is not set
 # CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_OTP is not set
+CONFIG_MTD_OTP=y
 CONFIG_MTD_CFI_INTELEXT=y
 # CONFIG_MTD_CFI_AMDSTD is not set
 # CONFIG_MTD_CFI_STAA is not set
@@ -655,19 +706,15 @@ CONFIG_MTD_CFI_UTIL=y
 # CONFIG_MTD_RAM is not set
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
-CONFIG_MTD_XIP=y
+# CONFIG_MTD_XIP is not set
 #
 # Mapping drivers for chip access
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP is not set
-CONFIG_MTD_PHYSMAP_START=0x0
+CONFIG_MTD_PXA2XX=y
-CONFIG_MTD_PHYSMAP_LEN=0x0
-CONFIG_MTD_PHYSMAP_BANKWIDTH=2
-# CONFIG_MTD_PXA2XX is not set
 # CONFIG_MTD_ARM_INTEGRATOR is not set
-# CONFIG_MTD_SHARP_SL is not set
 # CONFIG_MTD_PLATRAM is not set
 #
@@ -675,6 +722,7 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2
 #
 # CONFIG_MTD_DATAFLASH is not set
 # CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SST25L is not set
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
@@ -690,6 +738,11 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2
 # CONFIG_MTD_ONENAND is not set
 #
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+#
 # UBI - Unsorted block images
 #
 # CONFIG_MTD_UBI is not set
@@ -700,15 +753,14 @@ CONFIG_BLK_DEV_LOOP=m
 CONFIG_BLK_DEV_CRYPTOLOOP=m
 CONFIG_BLK_DEV_NBD=m
 # CONFIG_BLK_DEV_UB is not set
-CONFIG_BLK_DEV_RAM=m
+CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
 # CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
-CONFIG_MISC_DEVICES=y
+# CONFIG_MG_DISK is not set
-# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_MISC_DEVICES is not set
-# CONFIG_ENCLOSURE_SERVICES is not set
 CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
@@ -722,7 +774,6 @@ CONFIG_HAVE_IDE=y
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 CONFIG_DUMMY=y
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -732,13 +783,11 @@ CONFIG_DUMMY=y
 # CONFIG_NET_ETHERNET is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
 #
-# Wireless LAN
+# Enable WiMAX (Networking options) to see the WiMAX drivers
 #
-# CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
-# CONFIG_IWLWIFI_LEDS is not set
 #
 # USB Network Adapters
@@ -765,6 +814,7 @@ CONFIG_SLHC=m
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
 # CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
 #
 # Input device support
@@ -786,29 +836,45 @@ CONFIG_INPUT_EVDEV=y
 # Input Device Drivers
 #
 CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
 # CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_QT2160 is not set
 # CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
 # CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
 CONFIG_KEYBOARD_PXA27x=y
-CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
 # CONFIG_INPUT_TABLET is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 # CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
 # CONFIG_TOUCHSCREEN_FUJITSU is not set
 # CONFIG_TOUCHSCREEN_GUNZE is not set
 # CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
 # CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
 # CONFIG_TOUCHSCREEN_MK712 is not set
 # CONFIG_TOUCHSCREEN_PENMOUNT is not set
 # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
 # CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-# CONFIG_TOUCHSCREEN_UCB1400 is not set
 # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
 CONFIG_TOUCHSCREEN_PCAP=y
 CONFIG_INPUT_MISC=y
 # CONFIG_INPUT_ATI_REMOTE is not set
@@ -816,7 +882,10 @@ CONFIG_INPUT_MISC=y
 # CONFIG_INPUT_KEYSPAN_REMOTE is not set
 # CONFIG_INPUT_POWERMATE is not set
 # CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
 CONFIG_INPUT_UINPUT=y
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+CONFIG_INPUT_PCAP=y
 #
 # Hardware I/O ports
@@ -828,6 +897,7 @@ CONFIG_INPUT_UINPUT=y
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 # CONFIG_VT_HW_CONSOLE_BINDING is not set
@@ -842,92 +912,130 @@ CONFIG_DEVKMEM=y
 #
 # Non-8250 serial port support
 #
+# CONFIG_SERIAL_MAX3100 is not set
 CONFIG_SERIAL_PXA=y
 CONFIG_SERIAL_PXA_CONSOLE=y
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=8
 # CONFIG_IPMI_HANDLER is not set
-CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM is not set
-# CONFIG_NVRAM is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
 CONFIG_I2C=y
 CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
 CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
 #
 # I2C Hardware Bus support
 #
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE is not set
 # CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
 CONFIG_I2C_PXA=y
 # CONFIG_I2C_PXA_SLAVE is not set
-# CONFIG_I2C_OCORES is not set
-# CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_SIMTEC is not set
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_TAOS_EVM is not set
-# CONFIG_I2C_STUB is not set
 # CONFIG_I2C_TINY_USB is not set
+#
+# Other I2C/SMBus bus drivers
+#
 # CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
 #
 # Miscellaneous I2C Chip support
 #
 # CONFIG_DS1682 is not set
-# CONFIG_EEPROM_LEGACY is not set
-# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_PCF8575 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_TPS65010 is not set
-# CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
 # CONFIG_I2C_DEBUG_CHIP is not set
 CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
 CONFIG_SPI_MASTER=y
 #
 # SPI Master Controller Drivers
 #
 # CONFIG_SPI_BITBANG is not set
-CONFIG_SPI_PXA2XX=m
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_PXA2XX=y
 #
 # SPI Protocol Masters
 #
-# CONFIG_EEPROM_AT25 is not set
 # CONFIG_SPI_SPIDEV is not set
 # CONFIG_SPI_TLE62X0 is not set
-CONFIG_HAVE_GPIO_LIB=y
 #
-# GPIO Support
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+#
+# Memory mapped GPIO expanders:
 #
 #
 # I2C GPIO expanders:
 #
+# CONFIG_GPIO_MAX732X is not set
 # CONFIG_GPIO_PCA953X is not set
 # CONFIG_GPIO_PCF857X is not set
 #
+# PCI GPIO expanders:
+#
+#
 # SPI GPIO expanders:
 #
+# CONFIG_GPIO_MAX7301 is not set
 # CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+#
+# AC97 GPIO expanders:
+#
 # CONFIG_W1 is not set
-# CONFIG_POWER_SUPPLY is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_APM_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_MAX17040 is not set
 # CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
 # CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
 #
 # Sonics Silicon Backplane
 #
-CONFIG_SSB_POSSIBLE=y
 # CONFIG_SSB is not set
 #
@@ -938,54 +1046,170 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_MFD_ASIC3 is not set
 # CONFIG_HTC_EGPIO is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
 # CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_AB3100_CORE is not set
 CONFIG_EZX_PCAP=y
+CONFIG_REGULATOR=y
-#
+CONFIG_REGULATOR_DEBUG=y
-# Multimedia devices
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
-#
+CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
+CONFIG_REGULATOR_USERSPACE_CONSUMER=y
+# CONFIG_REGULATOR_BQ24022 is not set
+# CONFIG_REGULATOR_MAX1586 is not set
+# CONFIG_REGULATOR_LP3971 is not set
+CONFIG_REGULATOR_PCAP=y
+# CONFIG_REGULATOR_TPS65023 is not set
+# CONFIG_REGULATOR_TPS6507X is not set
+CONFIG_MEDIA_SUPPORT=y
 #
 # Multimedia core support
 #
-CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_DEV=y
-CONFIG_VIDEO_V4L2_COMMON=m
+CONFIG_VIDEO_V4L2_COMMON=y
 CONFIG_VIDEO_ALLOW_V4L1=y
 CONFIG_VIDEO_V4L1_COMPAT=y
 # CONFIG_DVB_CORE is not set
-CONFIG_VIDEO_MEDIA=m
+CONFIG_VIDEO_MEDIA=y
 #
 # Multimedia drivers
 #
 # CONFIG_MEDIA_ATTACH is not set
-CONFIG_MEDIA_TUNER=m
+CONFIG_MEDIA_TUNER=y
-# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set
+CONFIG_MEDIA_TUNER_CUSTOMISE=y
-CONFIG_MEDIA_TUNER_SIMPLE=m
+# CONFIG_MEDIA_TUNER_SIMPLE is not set
-CONFIG_MEDIA_TUNER_TDA8290=m
+# CONFIG_MEDIA_TUNER_TDA8290 is not set
-CONFIG_MEDIA_TUNER_TDA9887=m
+# CONFIG_MEDIA_TUNER_TDA827X is not set
-CONFIG_MEDIA_TUNER_TEA5761=m
+# CONFIG_MEDIA_TUNER_TDA18271 is not set
-CONFIG_MEDIA_TUNER_TEA5767=m
+# CONFIG_MEDIA_TUNER_TDA9887 is not set
-CONFIG_MEDIA_TUNER_MT20XX=m
+# CONFIG_MEDIA_TUNER_TEA5761 is not set
-CONFIG_MEDIA_TUNER_XC2028=m
+# CONFIG_MEDIA_TUNER_TEA5767 is not set
-CONFIG_MEDIA_TUNER_XC5000=m
+# CONFIG_MEDIA_TUNER_MT20XX is not set
-CONFIG_VIDEO_V4L2=m
+# CONFIG_MEDIA_TUNER_MT2060 is not set
-CONFIG_VIDEO_V4L1=m
+# CONFIG_MEDIA_TUNER_MT2266 is not set
+# CONFIG_MEDIA_TUNER_MT2131 is not set
+# CONFIG_MEDIA_TUNER_QT1010 is not set
+# CONFIG_MEDIA_TUNER_XC2028 is not set
+# CONFIG_MEDIA_TUNER_XC5000 is not set
+# CONFIG_MEDIA_TUNER_MXL5005S is not set
+# CONFIG_MEDIA_TUNER_MXL5007T is not set
+# CONFIG_MEDIA_TUNER_MC44S803 is not set
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEO_V4L1=y
+CONFIG_VIDEOBUF_GEN=y
+CONFIG_VIDEOBUF_DMA_SG=y
 CONFIG_VIDEO_CAPTURE_DRIVERS=y
 # CONFIG_VIDEO_ADV_DEBUG is not set
-CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
+#
+# Encoders/decoders and other helper chips
+#
+#
+# Audio decoders
+#
+# CONFIG_VIDEO_TVAUDIO is not set
+# CONFIG_VIDEO_TDA7432 is not set
+# CONFIG_VIDEO_TDA9840 is not set
+# CONFIG_VIDEO_TDA9875 is not set
+# CONFIG_VIDEO_TEA6415C is not set
+# CONFIG_VIDEO_TEA6420 is not set
+# CONFIG_VIDEO_MSP3400 is not set
+# CONFIG_VIDEO_CS5345 is not set
+# CONFIG_VIDEO_CS53L32A is not set
+# CONFIG_VIDEO_M52790 is not set
+# CONFIG_VIDEO_TLV320AIC23B is not set
+# CONFIG_VIDEO_WM8775 is not set
+# CONFIG_VIDEO_WM8739 is not set
+# CONFIG_VIDEO_VP27SMPX is not set
+#
+# RDS decoders
+#
+# CONFIG_VIDEO_SAA6588 is not set
+#
+# Video decoders
+#
+# CONFIG_VIDEO_ADV7180 is not set
+# CONFIG_VIDEO_BT819 is not set
+# CONFIG_VIDEO_BT856 is not set
+# CONFIG_VIDEO_BT866 is not set
+# CONFIG_VIDEO_KS0127 is not set
+# CONFIG_VIDEO_OV7670 is not set
+# CONFIG_VIDEO_MT9V011 is not set
+# CONFIG_VIDEO_TCM825X is not set
+# CONFIG_VIDEO_SAA7110 is not set
+# CONFIG_VIDEO_SAA711X is not set
+# CONFIG_VIDEO_SAA717X is not set
+# CONFIG_VIDEO_SAA7191 is not set
+# CONFIG_VIDEO_TVP514X is not set
+# CONFIG_VIDEO_TVP5150 is not set
+# CONFIG_VIDEO_VPX3220 is not set
+#
+# Video and audio decoders
+#
+# CONFIG_VIDEO_CX25840 is not set
+#
+# MPEG video encoders
+#
+# CONFIG_VIDEO_CX2341X is not set
+#
+# Video encoders
+#
+# CONFIG_VIDEO_SAA7127 is not set
+# CONFIG_VIDEO_SAA7185 is not set
+# CONFIG_VIDEO_ADV7170 is not set
+# CONFIG_VIDEO_ADV7175 is not set
+# CONFIG_VIDEO_THS7303 is not set
+# CONFIG_VIDEO_ADV7343 is not set
+#
+# Video improvement chips
+#
+# CONFIG_VIDEO_UPD64031A is not set
+# CONFIG_VIDEO_UPD64083 is not set
 # CONFIG_VIDEO_VIVI is not set
 # CONFIG_VIDEO_CPIA is not set
 # CONFIG_VIDEO_CPIA2 is not set
 # CONFIG_VIDEO_SAA5246A is not set
 # CONFIG_VIDEO_SAA5249 is not set
-# CONFIG_TUNER_3036 is not set
+CONFIG_SOC_CAMERA=y
+# CONFIG_SOC_CAMERA_MT9M001 is not set
+CONFIG_SOC_CAMERA_MT9M111=y
+# CONFIG_SOC_CAMERA_MT9T031 is not set
+# CONFIG_SOC_CAMERA_MT9V022 is not set
+# CONFIG_SOC_CAMERA_TW9910 is not set
+# CONFIG_SOC_CAMERA_PLATFORM is not set
+# CONFIG_SOC_CAMERA_OV772X is not set
+CONFIG_VIDEO_PXA27x=y
+# CONFIG_VIDEO_SH_MOBILE_CEU is not set
 # CONFIG_V4L_USB_DRIVERS is not set
-# CONFIG_SOC_CAMERA is not set
-# CONFIG_VIDEO_PXA27x is not set
 CONFIG_RADIO_ADAPTERS=y
+# CONFIG_I2C_SI4713 is not set
+# CONFIG_RADIO_SI4713 is not set
 # CONFIG_USB_DSBR is not set
-# CONFIG_USB_SI470X is not set
+# CONFIG_RADIO_SI470X is not set
+# CONFIG_USB_MR800 is not set
+CONFIG_RADIO_TEA5764=y
+CONFIG_RADIO_TEA5764_XTAL=y
 # CONFIG_DAB is not set
 #
@@ -996,6 +1220,7 @@ CONFIG_RADIO_ADAPTERS=y
 CONFIG_FB=y
 # CONFIG_FIRMWARE_EDID is not set
 # CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_IMAGEBLIT=y
@@ -1017,15 +1242,19 @@ CONFIG_FB_CFB_IMAGEBLIT=y
 # CONFIG_FB_UVESA is not set
 # CONFIG_FB_S1D13XXX is not set
 CONFIG_FB_PXA=y
+CONFIG_FB_PXA_OVERLAY=y
 # CONFIG_FB_PXA_SMARTPANEL is not set
 CONFIG_FB_PXA_PARAMETERS=y
 # CONFIG_FB_MBX is not set
-# CONFIG_FB_AM200EPD is not set
+# CONFIG_FB_W100 is not set
 # CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 # CONFIG_LCD_CLASS_DEVICE is not set
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_CORGI is not set
+CONFIG_BACKLIGHT_GENERIC=y
 CONFIG_BACKLIGHT_PWM=y
 #
@@ -1053,85 +1282,60 @@ CONFIG_FONT_MINI_4x6=y
 # CONFIG_FONT_SUN12x22 is not set
 # CONFIG_FONT_10x18 is not set
 # CONFIG_LOGO is not set
-#
-# Sound
-#
 CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
-#
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
-# Advanced Linux Sound Architecture
-#
 CONFIG_SND=y
 CONFIG_SND_TIMER=y
 CONFIG_SND_PCM=y
+CONFIG_SND_JACK=y
 # CONFIG_SND_SEQUENCER is not set
 CONFIG_SND_OSSEMUL=y
 CONFIG_SND_MIXER_OSS=y
 CONFIG_SND_PCM_OSS=y
 CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_HRTIMER is not set
 # CONFIG_SND_DYNAMIC_MINORS is not set
 CONFIG_SND_SUPPORT_OLD_API=y
 CONFIG_SND_VERBOSE_PROCFS=y
 # CONFIG_SND_VERBOSE_PRINTK is not set
 # CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
-#
+# CONFIG_SND_OPL3_LIB_SEQ is not set
-# Generic devices
+# CONFIG_SND_OPL4_LIB_SEQ is not set
-#
+# CONFIG_SND_SBAWE_SEQ is not set
-# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
-# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_ARM is not set
-# CONFIG_SND_MPU401 is not set
+CONFIG_SND_PXA2XX_LIB=y
+# CONFIG_SND_SPI is not set
-#
+# CONFIG_SND_USB is not set
-# ALSA ARM devices
-#
-# CONFIG_SND_PXA2XX_AC97 is not set
-#
-# SPI devices
-#
-#
-# USB devices
-#
-# CONFIG_SND_USB_AUDIO is not set
-# CONFIG_SND_USB_CAIAQ is not set
-#
-# System on Chip audio support
-#
 CONFIG_SND_SOC=y
 CONFIG_SND_PXA2XX_SOC=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
-#
+# CONFIG_SND_SOC_ALL_CODECS is not set
-# ALSA SoC audio for Freescale SOCs
-#
-#
-# SoC Audio for the Texas Instruments OMAP
-#
-#
-# Open Sound System
-#
 # CONFIG_SOUND_PRIME is not set
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
 # CONFIG_HIDRAW is not set
 #
 # USB Input Devices
 #
 # CONFIG_USB_HID is not set
+# CONFIG_HID_PID is not set
 #
 # USB HID Boot Protocol drivers
 #
 # CONFIG_USB_KBD is not set
 # CONFIG_USB_MOUSE is not set
+#
+# Special HID drivers
+#
+CONFIG_HID_APPLE=m
+# CONFIG_HID_WACOM is not set
 CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
@@ -1150,32 +1354,42 @@ CONFIG_USB=y
 # CONFIG_USB_OTG is not set
 # CONFIG_USB_OTG_WHITELIST is not set
 # CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
 #
 # USB Host Controller Drivers
 #
 # CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
 # CONFIG_USB_ISP116X_HCD is not set
 # CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
 CONFIG_USB_OHCI_HCD=y
 # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
 # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
 CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_SL811_HCD is not set
 # CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
 #
 # USB Device Class drivers
 #
 # CONFIG_USB_ACM is not set
 # CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
 #
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
 #
 #
-# may also be needed; see USB_STORAGE Help for more information
+# also be needed; see USB_STORAGE Help for more info
 #
 # CONFIG_USB_LIBUSUAL is not set
@@ -1183,7 +1397,6 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # USB Imaging devices
 #
 # CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MON is not set
 #
 # USB port drivers
@@ -1196,7 +1409,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_EMI62 is not set
 # CONFIG_USB_EMI26 is not set
 # CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_SEVSEG is not set
 # CONFIG_USB_RIO500 is not set
 # CONFIG_USB_LEGOTOWER is not set
 # CONFIG_USB_LCD is not set
@@ -1204,62 +1417,94 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_LED is not set
 # CONFIG_USB_CYPRESS_CY7C63 is not set
 # CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGET is not set
 # CONFIG_USB_IDMOUSE is not set
 # CONFIG_USB_FTDI_ELAN is not set
 # CONFIG_USB_APPLEDISPLAY is not set
 # CONFIG_USB_LD is not set
 # CONFIG_USB_TRANCEVIBRATOR is not set
 # CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
 CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
 # CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
 CONFIG_USB_GADGET_SELECTED=y
-# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_AT91 is not set
 # CONFIG_USB_GADGET_ATMEL_USBA is not set
 # CONFIG_USB_GADGET_FSL_USB2 is not set
-# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
 # CONFIG_USB_GADGET_PXA25X is not set
-# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
 CONFIG_USB_GADGET_PXA27X=y
 CONFIG_USB_PXA27X=y
-# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
-# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_IMX is not set
-# CONFIG_USB_GADGET_OMAP is not set
 # CONFIG_USB_GADGET_S3C2410 is not set
-# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
 # CONFIG_USB_GADGET_DUMMY_HCD is not set
 # CONFIG_USB_GADGET_DUALSPEED is not set
 # CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
 CONFIG_USB_ETH=y
 # CONFIG_USB_ETH_RNDIS is not set
+# CONFIG_USB_ETH_EEM is not set
 # CONFIG_USB_GADGETFS is not set
 # CONFIG_USB_FILE_STORAGE is not set
 # CONFIG_USB_G_SERIAL is not set
 # CONFIG_USB_MIDI_GADGET is not set
 # CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
 CONFIG_MMC=y
 # CONFIG_MMC_DEBUG is not set
 CONFIG_MMC_UNSAFE_RESUME=y
 #
-# MMC/SD Card Drivers
+# MMC/SD/SDIO Card Drivers
 #
 CONFIG_MMC_BLOCK=y
 CONFIG_MMC_BLOCK_BOUNCE=y
-CONFIG_SDIO_UART=y
+CONFIG_SDIO_UART=m
+# CONFIG_MMC_TEST is not set
 #
-# MMC/SD Host Controller Drivers
+# MMC/SD/SDIO Host Controller Drivers
 #
 CONFIG_MMC_PXA=y
-# CONFIG_MMC_SPI is not set
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_AT91 is not set
+# CONFIG_MMC_ATMELMCI is not set
+CONFIG_MMC_SPI=y
+# CONFIG_MEMSTICK is not set
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 #
 # LED drivers
 #
+# CONFIG_LEDS_PCA9532 is not set
 # CONFIG_LEDS_GPIO is not set
+CONFIG_LEDS_LP3944=y
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_PWM is not set
+# CONFIG_LEDS_BD2802 is not set
 #
 # LED Triggers
@@ -1267,7 +1512,14 @@ CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_ACCESSIBILITY is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_HCTOSYS=y
@@ -1297,45 +1549,67 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_PCF8583 is not set
 # CONFIG_RTC_DRV_M41T80 is not set
 # CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
 #
 # SPI RTC drivers
 #
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
 # CONFIG_RTC_DRV_MAX6902 is not set
 # CONFIG_RTC_DRV_R9701 is not set
 # CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
 #
 # Platform RTC drivers
 #
 # CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
 # CONFIG_RTC_DRV_DS1511 is not set
 # CONFIG_RTC_DRV_DS1553 is not set
 # CONFIG_RTC_DRV_DS1742 is not set
 # CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
 # CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
 # CONFIG_RTC_DRV_V3020 is not set
 #
 # on-CPU RTC drivers
 #
-CONFIG_RTC_DRV_SA1100=m
+# CONFIG_RTC_DRV_SA1100 is not set
+# CONFIG_RTC_DRV_PXA is not set
+CONFIG_RTC_DRV_PCAP=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
 #
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+#
 # File systems
 #
 CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=m
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 CONFIG_EXT3_FS_XATTR=y
 # CONFIG_EXT3_FS_POSIX_ACL is not set
 # CONFIG_EXT3_FS_SECURITY is not set
-# CONFIG_EXT4DEV_FS is not set
+# CONFIG_EXT4_FS is not set
 CONFIG_JBD=m
-CONFIG_FS_MBCACHE=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=m
 CONFIG_REISERFS_FS=m
 # CONFIG_REISERFS_CHECK is not set
 # CONFIG_REISERFS_PROC_INFO is not set
@@ -1350,6 +1624,10 @@ CONFIG_XFS_FS=m
 # CONFIG_XFS_RT is not set
 # CONFIG_XFS_DEBUG is not set
 # CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
 CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -1357,6 +1635,12 @@ CONFIG_INOTIFY_USER=y
 CONFIG_AUTOFS_FS=y
 CONFIG_AUTOFS4_FS=y
 CONFIG_FUSE_FS=m
+CONFIG_CUSE=m
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
 #
 # CD-ROM/DVD Filesystems
@@ -1381,15 +1665,13 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 #
 CONFIG_PROC_FS=y
 CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
 CONFIG_SYSFS=y
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
 # CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
-#
-# Miscellaneous filesystems
-#
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@@ -1397,13 +1679,35 @@ CONFIG_TMPFS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-# CONFIG_JFFS2_FS is not set
+CONFIG_JFFS2_FS=m
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
 CONFIG_CRAMFS=m
+CONFIG_SQUASHFS=m
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
 # CONFIG_VXFS_FS is not set
 # CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
-# CONFIG_ROMFS_FS is not set
+CONFIG_ROMFS_FS=m
+CONFIG_ROMFS_BACKED_BY_BLOCK=y
+# CONFIG_ROMFS_BACKED_BY_MTD is not set
+# CONFIG_ROMFS_BACKED_BY_BOTH is not set
+CONFIG_ROMFS_ON_BLOCK=y
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
@@ -1411,19 +1715,18 @@ CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 CONFIG_NFS_V3_ACL=y
 # CONFIG_NFS_V4 is not set
+# CONFIG_ROOT_NFS is not set
 CONFIG_NFSD=m
 CONFIG_NFSD_V2_ACL=y
 CONFIG_NFSD_V3=y
 CONFIG_NFSD_V3_ACL=y
 # CONFIG_NFSD_V4 is not set
-# CONFIG_ROOT_NFS is not set
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=m
 CONFIG_NFS_ACL_SUPPORT=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
-# CONFIG_SUNRPC_BIND34 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -1490,25 +1793,83 @@ CONFIG_NLS_UTF8=m
 #
 # Kernel hacking
 #
-# CONFIG_PRINTK_TIME is not set
+CONFIG_PRINTK_TIME=y
 CONFIG_ENABLE_WARN_DEPRECATED=y
-# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
+CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_SHIRQ is not set
-CONFIG_FRAME_POINTER=y
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+CONFIG_DEBUG_PREEMPT=y
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_DEBUG_PI_LIST=y
+# CONFIG_RT_MUTEX_TESTER is not set
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_MUTEXES=y
+CONFIG_DEBUG_LOCK_ALLOC=y
+CONFIG_PROVE_LOCKING=y
+CONFIG_LOCKDEP=y
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_LOCKDEP is not set
+CONFIG_TRACE_IRQFLAGS=y
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
-# CONFIG_DEBUG_USER is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARM_UNWIND=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
 #
 # Security options
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
 CONFIG_CRYPTO=y
@@ -1516,12 +1877,20 @@ CONFIG_CRYPTO=y
 # Crypto core or helper
 #
 CONFIG_CRYPTO_ALGAPI=m
+CONFIG_CRYPTO_ALGAPI2=m
 CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEAD2=m
 CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_BLKCIPHER2=m
 CONFIG_CRYPTO_HASH=m
+CONFIG_CRYPTO_HASH2=m
+CONFIG_CRYPTO_RNG2=m
+CONFIG_CRYPTO_PCOMP=m
 CONFIG_CRYPTO_MANAGER=m
+CONFIG_CRYPTO_MANAGER2=m
 CONFIG_CRYPTO_GF128MUL=m
 CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_WORKQUEUE=m
 CONFIG_CRYPTO_CRYPTD=m
 CONFIG_CRYPTO_AUTHENC=m
 CONFIG_CRYPTO_TEST=m
@@ -1549,14 +1918,20 @@ CONFIG_CRYPTO_XTS=m
 #
 CONFIG_CRYPTO_HMAC=m
 CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_VMAC=m
 #
 # Digest
 #
 CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_GHASH=m
 CONFIG_CRYPTO_MD4=m
 CONFIG_CRYPTO_MD5=m
 CONFIG_CRYPTO_MICHAEL_MIC=m
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
 CONFIG_CRYPTO_SHA1=m
 CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
@@ -1587,28 +1962,40 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m
 # Compression
 #
 CONFIG_CRYPTO_DEFLATE=m
+# CONFIG_CRYPTO_ZLIB is not set
 # CONFIG_CRYPTO_LZO is not set
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
-# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+CONFIG_GENERIC_FIND_LAST_BIT=y
-# CONFIG_GENERIC_FIND_NEXT_BIT is not set
 CONFIG_CRC_CCITT=m
-CONFIG_CRC16=m
+CONFIG_CRC16=y
-# CONFIG_CRC_ITU_T is not set
+# CONFIG_CRC_T10DIF is not set
+CONFIG_CRC_ITU_T=y
 CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
+CONFIG_CRC7=y
 CONFIG_LIBCRC32C=m
-CONFIG_ZLIB_INFLATE=m
+CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=m
+CONFIG_LZO_COMPRESS=m
+CONFIG_LZO_DECOMPRESS=m
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
 CONFIG_TEXTSEARCH=y
 CONFIG_TEXTSEARCH_KMP=m
 CONFIG_TEXTSEARCH_BM=m
 CONFIG_TEXTSEARCH_FSM=m
-CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/h3600_defconfig b/arch/arm/configs/h3600_defconfig
index f6aed7747d4d..efa78e144e5c 100644
--- a/arch/arm/configs/h3600_defconfig
+++ b/arch/arm/configs/h3600_defconfig
@@ -1,86 +1,189 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc4
+# Linux kernel version: 2.6.32-rc5
-# Thu Jun  9 01:59:03 2005
+# Sat Oct 24 00:09:30 2009
 #
 CONFIG_ARM=y
-CONFIG_MMU=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_UID16=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPUFREQ=y
+CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_IOMAP=y
+CONFIG_ARCH_MTD_XIP=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
-CONFIG_CLEAN_COMPILE=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-#
-# General setup
-#
 CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
-CONFIG_SYSCTL=y
+# CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
-CONFIG_HOTPLUG=y
-CONFIG_KOBJECT_UEVENT=y
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 # CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
+CONFIG_ELF_CORE=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_EPOLL=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
+CONFIG_AIO=y
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
+#
-CONFIG_CC_ALIGN_JUMPS=0
+# Kernel Performance Events And Counters
-# CONFIG_TINY_SHMEM is not set
+#
-CONFIG_BASE_SMALL=0
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
 #
-# Loadable module support
+# GCOV-based kernel profiling
 #
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 # CONFIG_MODULE_UNLOAD is not set
-CONFIG_OBSOLETE_MODPARM=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
-# CONFIG_KMOD is not set
+CONFIG_BLOCK=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+CONFIG_FREEZER=y
 #
 # System Type
 #
-# CONFIG_ARCH_CLPS7500 is not set
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
 # CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_GEMINI is not set
 # CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_MXC is not set
-# CONFIG_ARCH_IOP3XX is not set
+# CONFIG_ARCH_STMP3XXX is not set
-# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
 # CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
 # CONFIG_ARCH_RPC is not set
 CONFIG_ARCH_SA1100=y
 # CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_BCMRING is not set
-# CONFIG_ARCH_IMX is not set
-# CONFIG_ARCH_H720X is not set
 #
 # SA11x0 Implementations
@@ -106,27 +209,31 @@ CONFIG_CPU_32=y
 CONFIG_CPU_SA1100=y
 CONFIG_CPU_32v4=y
 CONFIG_CPU_ABRT_EV4=y
+CONFIG_CPU_PABRT_LEGACY=y
 CONFIG_CPU_CACHE_V4WB=y
 CONFIG_CPU_CACHE_VIVT=y
 CONFIG_CPU_TLB_V4WB=y
-CONFIG_CPU_MINICACHE=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
 #
 # Processor Features
 #
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
 #
 # Bus support
 #
 CONFIG_ISA=y
-CONFIG_ISA_DMA_API=y
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
-#
-# PCCARD (PCMCIA/CardBus) support
-#
 CONFIG_PCCARD=y
 # CONFIG_PCMCIA_DEBUG is not set
 CONFIG_PCMCIA=y
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA_IOCTL=y
 #
 # PC-card bridges
@@ -138,11 +245,41 @@ CONFIG_PCMCIA_SA1100=y
 #
 # Kernel Features
 #
-# CONFIG_SMP is not set
+CONFIG_TICK_ONESHOT=y
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
-CONFIG_DISCONTIGMEM=y
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_FLATMEM_MANUAL is not set
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM=y
+CONFIG_HAVE_MEMORY_PRESENT=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 # CONFIG_LEDS is not set
 CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
 #
 # Boot options
@@ -151,22 +288,26 @@ CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_CMDLINE=""
 # CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
 #
-# CPU Frequency scaling
+# CPU Power Management
 #
 CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_TABLE=y
 # CONFIG_CPU_FREQ_DEBUG is not set
-CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT is not set
-# CONFIG_CPU_FREQ_STAT_DETAILS is not set
 # CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
 CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
 # CONFIG_CPU_FREQ_GOV_PERFORMANCE is not set
 # CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
 CONFIG_CPU_FREQ_GOV_USERSPACE=y
 # CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
 CONFIG_CPU_FREQ_SA1100=y
+# CONFIG_CPU_IDLE is not set
 #
 # Floating point emulation
@@ -183,6 +324,8 @@ CONFIG_FPE_NWFPE=y
 # Userspace binary formats
 #
 CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
 # CONFIG_BINFMT_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
 # CONFIG_ARTHUR is not set
@@ -191,8 +334,120 @@ CONFIG_BINFMT_ELF=y
 # Power management options
 #
 CONFIG_PM=y
-# CONFIG_PM_LEGACY is not set
+# CONFIG_PM_DEBUG is not set
-# CONFIG_APM is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_APM_EMULATION is not set
+# CONFIG_PM_RUNTIME is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+CONFIG_IRDA=m
+#
+# IrDA protocols
+#
+CONFIG_IRLAN=m
+CONFIG_IRNET=m
+CONFIG_IRCOMM=m
+# CONFIG_IRDA_ULTRA is not set
+#
+# IrDA options
+#
+# CONFIG_IRDA_CACHE_LAST_LSAP is not set
+# CONFIG_IRDA_FAST_RR is not set
+# CONFIG_IRDA_DEBUG is not set
+#
+# Infrared-port device drivers
+#
+#
+# SIR device drivers
+#
+# CONFIG_IRTTY_SIR is not set
+#
+# Dongle support
+#
+#
+# FIR device drivers
+#
+CONFIG_SA1100_FIR=m
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 #
 # Device Drivers
@@ -201,15 +456,17 @@ CONFIG_PM=y
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
-#
+CONFIG_EXTRA_FIRMWARE=""
-# Memory Technology Devices (MTD)
+# CONFIG_SYS_HYPERVISOR is not set
-#
+# CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_REDBOOT_PARTS=y
@@ -218,15 +475,20 @@ CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
 # CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
 # CONFIG_MTD_CMDLINE_PARTS is not set
 # CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
 #
 # User Modules And Translation Layers
 #
 CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
 CONFIG_MTD_BLOCK=y
 # CONFIG_FTL is not set
 # CONFIG_NFTL is not set
 # CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 #
 # RAM/ROM/Flash chip drivers
@@ -249,6 +511,7 @@ CONFIG_MTD_MAP_BANK_WIDTH_4=y
 CONFIG_MTD_CFI_I2=y
 # CONFIG_MTD_CFI_I4 is not set
 # CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
 CONFIG_MTD_CFI_INTELEXT=y
 # CONFIG_MTD_CFI_AMDSTD is not set
 # CONFIG_MTD_CFI_STAA is not set
@@ -265,7 +528,7 @@ CONFIG_MTD_CFI_UTIL=y
 # CONFIG_MTD_PHYSMAP is not set
 # CONFIG_MTD_ARM_INTEGRATOR is not set
 CONFIG_MTD_SA1100=y
-# CONFIG_MTD_EDB7312 is not set
+# CONFIG_MTD_PLATRAM is not set
 #
 # Self-contained MTD device drivers
@@ -273,7 +536,6 @@ CONFIG_MTD_SA1100=y
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLKMTD is not set
 # CONFIG_MTD_BLOCK2MTD is not set
 #
@@ -282,26 +544,21 @@ CONFIG_MTD_SA1100=y
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-#
-# NAND Flash Device Drivers
-#
 # CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
 #
-# Parallel port support
+# LPDDR flash memory drivers
 #
-# CONFIG_PARPORT is not set
+# CONFIG_MTD_LPDDR is not set
 #
-# Plug and Play support
+# UBI - Unsorted block images
 #
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
 # CONFIG_PNP is not set
+CONFIG_BLK_DEV=y
-#
-# Block devices
-#
-# CONFIG_BLK_DEV_XD is not set
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=m
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
@@ -309,212 +566,58 @@ CONFIG_BLK_DEV_LOOP=m
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_BLK_DEV_INITRD=y
+# CONFIG_BLK_DEV_XIP is not set
-CONFIG_INITRAMFS_SOURCE=""
 # CONFIG_CDROM_PKTCDVD is not set
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
 # CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+CONFIG_IDE=y
 #
-# ATA/ATAPI/MFM/RLL support
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
-#
-CONFIG_IDE=m
-CONFIG_BLK_DEV_IDE=m
-#
-# Please see Documentation/ide.txt for help/info on IDE drives
 #
 # CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_BLK_DEV_IDEDISK=m
+CONFIG_IDE_GD=y
-# CONFIG_IDEDISK_MULTI_MODE is not set
+CONFIG_IDE_GD_ATA=y
-# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_IDE_GD_ATAPI is not set
-CONFIG_BLK_DEV_IDECD=m
+CONFIG_BLK_DEV_IDECS=y
+# CONFIG_BLK_DEV_IDECD is not set
 # CONFIG_BLK_DEV_IDETAPE is not set
-# CONFIG_BLK_DEV_IDEFLOPPY is not set
 # CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
 #
 # IDE chipset support/bugfixes
 #
-CONFIG_IDE_GENERIC=m
+# CONFIG_BLK_DEV_PLATFORM is not set
-# CONFIG_IDE_ARM is not set
-# CONFIG_IDE_CHIPSETS is not set
 # CONFIG_BLK_DEV_IDEDMA is not set
-# CONFIG_IDEDMA_AUTO is not set
-# CONFIG_BLK_DEV_HD is not set
 #
 # SCSI device support
 #
+# CONFIG_RAID_ATTRS is not set
 # CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
-#
+# CONFIG_SCSI_NETLINK is not set
-# Multi-device support (RAID and LVM)
+# CONFIG_ATA is not set
-#
 # CONFIG_MD is not set
-#
-# Fusion MPT device support
-#
-#
-# IEEE 1394 (FireWire) support
-#
-#
-# I2O device support
-#
-#
-# Networking support
-#
-CONFIG_NET=y
-#
-# Networking options
-#
-# CONFIG_PACKET is not set
-CONFIG_UNIX=y
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-# CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_TUNNEL is not set
-# CONFIG_IP_TCPDIAG is not set
-# CONFIG_IP_TCPDIAG_IPV6 is not set
-# CONFIG_IPV6 is not set
-# CONFIG_NETFILTER is not set
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-# CONFIG_NET_CLS_ROUTE is not set
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_HAMRADIO is not set
-CONFIG_IRDA=m
-#
-# IrDA protocols
-#
-CONFIG_IRLAN=m
-CONFIG_IRNET=m
-CONFIG_IRCOMM=m
-# CONFIG_IRDA_ULTRA is not set
-#
-# IrDA options
-#
-# CONFIG_IRDA_CACHE_LAST_LSAP is not set
-# CONFIG_IRDA_FAST_RR is not set
-# CONFIG_IRDA_DEBUG is not set
-#
-# Infrared-port device drivers
-#
-#
-# SIR device drivers
-#
-# CONFIG_IRTTY_SIR is not set
-#
-# Dongle support
-#
-#
-# Old SIR device drivers
-#
-# CONFIG_IRPORT_SIR is not set
-#
-# Old Serial dongle support
-#
-#
-# FIR device drivers
-#
-# CONFIG_NSC_FIR is not set
-# CONFIG_WINBOND_FIR is not set
-# CONFIG_SMC_IRCC_FIR is not set
-# CONFIG_ALI_FIR is not set
-CONFIG_SA1100_FIR=m
-# CONFIG_VIA_FIR is not set
-# CONFIG_BT is not set
 CONFIG_NETDEVICES=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
+# CONFIG_VETH is not set
-#
-# ARCnet devices
-#
 # CONFIG_ARCNET is not set
-#
-# Ethernet (10 or 100Mbit)
-#
 # CONFIG_NET_ETHERNET is not set
+# CONFIG_NETDEV_1000 is not set
-#
+# CONFIG_NETDEV_10000 is not set
-# Ethernet (1000 Mbit)
-#
-#
-# Ethernet (10000 Mbit)
-#
-#
-# Token Ring devices
-#
 # CONFIG_TR is not set
+# CONFIG_WLAN is not set
 #
-# Wireless LAN (non-hamradio)
+# Enable WiMAX (Networking options) to see the WiMAX drivers
-#
-# CONFIG_NET_RADIO is not set
-#
-# PCMCIA network device support
 #
 CONFIG_NET_PCMCIA=y
 # CONFIG_PCMCIA_3C589 is not set
@@ -525,10 +628,6 @@ CONFIG_PCMCIA_PCNET=y
 # CONFIG_PCMCIA_SMC91C92 is not set
 # CONFIG_PCMCIA_XIRC2PS is not set
 # CONFIG_PCMCIA_AXNET is not set
-#
-# Wan interfaces
-#
 # CONFIG_WAN is not set
 CONFIG_PPP=m
 # CONFIG_PPP_MULTILINK is not set
@@ -537,20 +636,23 @@ CONFIG_PPP_ASYNC=m
 # CONFIG_PPP_SYNC_TTY is not set
 CONFIG_PPP_DEFLATE=m
 CONFIG_PPP_BSDCOMP=m
+# CONFIG_PPP_MPPE is not set
 # CONFIG_PPPOE is not set
+# CONFIG_PPPOL2TP is not set
 # CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
+CONFIG_SLHC=m
 # CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
-#
+# CONFIG_NET_POLL_CONTROLLER is not set
-# ISDN subsystem
-#
 # CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
 #
 # Input device support
 #
 CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
 #
 # Userland interfaces
@@ -560,7 +662,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
@@ -568,47 +669,42 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # Input Device Drivers
 #
 CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_KEYBOARD_SUNKBD is not set
 # CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_MATRIX is not set
 # CONFIG_KEYBOARD_NEWTON is not set
-CONFIG_INPUT_MOUSE=y
+# CONFIG_KEYBOARD_OPENCORES is not set
-CONFIG_MOUSE_PS2=y
+# CONFIG_KEYBOARD_STOWAWAY is not set
-# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_MOUSE_INPORT is not set
+# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_MOUSE_LOGIBM is not set
+# CONFIG_INPUT_MOUSE is not set
-# CONFIG_MOUSE_PC110PAD is not set
-# CONFIG_MOUSE_VSXXXAA is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 #
 # Hardware I/O ports
 #
-CONFIG_SERIO=y
+# CONFIG_SERIO is not set
-CONFIG_SERIO_SERPORT=y
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_SERIO_RAW is not set
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 #
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 #
 # Serial drivers
 #
-CONFIG_SERIAL_8250=m
+# CONFIG_SERIAL_8250 is not set
-# CONFIG_SERIAL_8250_CS is not set
-CONFIG_SERIAL_8250_NR_UARTS=4
-# CONFIG_SERIAL_8250_EXTENDED is not set
 #
 # Non-8250 serial port support
@@ -618,71 +714,125 @@ CONFIG_SERIAL_SA1100_CONSOLE=y
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
 #
-# IPMI
+# PCMCIA character devices
 #
-# CONFIG_IPMI_HANDLER is not set
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
 #
-# Watchdog Cards
+# PPS support
 #
-# CONFIG_WATCHDOG is not set
+# CONFIG_PPS is not set
-# CONFIG_NVRAM is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
-# CONFIG_RTC is not set
+CONFIG_GPIOLIB=y
-# CONFIG_DTLK is not set
+# CONFIG_GPIO_SYSFS is not set
-# CONFIG_R3964 is not set
 #
-# Ftape, the floppy tape device driver
+# Memory mapped GPIO expanders:
 #
-# CONFIG_DRM is not set
 #
-# PCMCIA character devices
+# I2C GPIO expanders:
 #
-# CONFIG_SYNCLINK_CS is not set
-# CONFIG_RAW_DRIVER is not set
 #
-# TPM devices
+# PCI GPIO expanders:
 #
 #
-# I2C support
+# SPI GPIO expanders:
 #
-# CONFIG_I2C is not set
 #
-# Misc devices
+# AC97 GPIO expanders:
 #
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
 #
-# Multimedia devices
+# Sonics Silicon Backplane
 #
-# CONFIG_VIDEO_DEV is not set
+# CONFIG_SSB is not set
 #
-# Digital Video Broadcasting Devices
+# Multifunction device drivers
 #
-# CONFIG_DVB is not set
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+CONFIG_HTC_EGPIO=y
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+#
+# Multimedia Capabilities Port drivers
+#
+# CONFIG_MCP_SA11X0 is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
 #
 # Graphics support
 #
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_SOFT_CURSOR=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
 # CONFIG_FB_MODE_HELPERS is not set
 # CONFIG_FB_TILEBLITTING is not set
+#
+# Frame buffer hardware drivers
+#
 CONFIG_FB_SA1100=y
 # CONFIG_FB_S1D13XXX is not set
 # CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
 #
 # Console display driver support
@@ -691,65 +841,54 @@ CONFIG_FB_SA1100=y
 # CONFIG_MDA_CONSOLE is not set
 CONFIG_DUMMY_CONSOLE=y
 # CONFIG_FRAMEBUFFER_CONSOLE is not set
-#
-# Logo configuration
-#
 # CONFIG_LOGO is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
-#
+# CONFIG_USB_SUPPORT is not set
-# Sound
+# CONFIG_MMC is not set
-#
+# CONFIG_MEMSTICK is not set
-CONFIG_SOUND=y
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
-#
+CONFIG_RTC_LIB=y
-# Advanced Linux Sound Architecture
+# CONFIG_RTC_CLASS is not set
-#
+# CONFIG_DMADEVICES is not set
-# CONFIG_SND is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
-#
-# Open Sound System
-#
-# CONFIG_SOUND_PRIME is not set
-#
-# USB support
-#
-CONFIG_USB_ARCH_HAS_HCD=y
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-# CONFIG_USB is not set
 #
-# USB Gadget Support
+# TI VLYNQ
 #
-# CONFIG_USB_GADGET is not set
+# CONFIG_STAGING is not set
-#
-# MMC/SD Card support
-#
-# CONFIG_MMC is not set
 #
 # File systems
 #
 CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
 # CONFIG_EXT3_FS is not set
-# CONFIG_JBD is not set
+# CONFIG_EXT4_FS is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
-#
-# XFS support
-#
 # CONFIG_XFS_FS is not set
-# CONFIG_MINIX_FS is not set
+# CONFIG_OCFS2_FS is not set
-# CONFIG_ROMFS_FS is not set
+# CONFIG_BTRFS_FS is not set
-# CONFIG_QUOTA is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
 CONFIG_DNOTIFY=y
+# CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
 #
 # CD-ROM/DVD Filesystems
@@ -771,16 +910,13 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 # Pseudo filesystems
 #
 CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
 CONFIG_SYSFS=y
-# CONFIG_DEVFS_FS is not set
-# CONFIG_DEVPTS_FS_XATTR is not set
 # CONFIG_TMPFS is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
-#
-# Miscellaneous filesystems
-#
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@@ -788,34 +924,37 @@ CONFIG_RAMFS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-# CONFIG_JFFS_FS is not set
 CONFIG_JFFS2_FS=y
 CONFIG_JFFS2_FS_DEBUG=0
-# CONFIG_JFFS2_FS_NAND is not set
+CONFIG_JFFS2_FS_WRITEBUFFER=y
-# CONFIG_JFFS2_FS_NOR_ECC is not set
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
 # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
 CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
 CONFIG_CRAMFS=m
+# CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
-#
-# Network File Systems
-#
 CONFIG_NFS_FS=y
 # CONFIG_NFS_V3 is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
 CONFIG_NFSD=m
 # CONFIG_NFSD_V3 is not set
-CONFIG_NFSD_TCP=y
+# CONFIG_NFSD_V4 is not set
 CONFIG_LOCKD=y
 CONFIG_EXPORTFS=m
+CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -831,10 +970,6 @@ CONFIG_SMB_FS=m
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-#
-# Native Language Support
-#
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 # CONFIG_NLS_CODEPAGE_437 is not set
@@ -875,20 +1010,34 @@ CONFIG_NLS_DEFAULT="iso8859-1"
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
 # CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
 #
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
-CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
 CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_MEMORY_INIT=y
 CONFIG_FRAME_POINTER=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_DEBUG_USER is not set
 #
@@ -896,21 +1045,120 @@ CONFIG_FRAME_POINTER=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=m
+CONFIG_CRYPTO_ALGAPI2=m
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=m
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_MANAGER2 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=m
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
 #
-# Cryptographic options
+# Compression
 #
-# CONFIG_CRYPTO is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
 #
-# Hardware crypto devices
+# Random Number Generation
 #
+CONFIG_CRYPTO_ANSI_CPRNG=m
+CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
 #
 # Library routines
 #
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
 CONFIG_CRC_CCITT=m
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/mx3_defconfig b/arch/arm/configs/mx3_defconfig
index a4f9a2a8149c..7734ccab2119 100644
--- a/arch/arm/configs/mx3_defconfig
+++ b/arch/arm/configs/mx3_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.31-rc4
+# Linux kernel version: 2.6.32-rc5
-# Tue Jul 28 14:11:34 2009
+# Sun Nov  1 22:56:24 2009
 #
 CONFIG_ARM=y
 CONFIG_HAVE_PWM=y
@@ -9,7 +9,6 @@ CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_GENERIC_GPIO=y
 CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_MMU=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_HAVE_LATENCYTOP_SUPPORT=y
@@ -46,11 +45,12 @@ CONFIG_SYSVIPC_SYSCTL=y
 #
 # RCU Subsystem
 #
-CONFIG_CLASSIC_RCU=y
+CONFIG_TREE_RCU=y
-# CONFIG_TREE_RCU is not set
+# CONFIG_TREE_PREEMPT_RCU is not set
-# CONFIG_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
 # CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_PREEMPT_RCU_TRACE is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
@@ -87,16 +87,14 @@ CONFIG_SHMEM=y
 CONFIG_AIO=y
 #
-# Performance Counters
+# Kernel Performance Events And Counters
 #
 CONFIG_VM_EVENT_COUNTERS=y
-# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
 # CONFIG_PROFILING is not set
-# CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
 # CONFIG_KPROBES is not set
 CONFIG_HAVE_KPROBES=y
@@ -139,6 +137,7 @@ CONFIG_FREEZER=y
 #
 # System Type
 #
+CONFIG_MMU=y
 # CONFIG_ARCH_AAEC2000 is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_REALVIEW is not set
@@ -153,6 +152,7 @@ CONFIG_ARCH_MXC=y
 # CONFIG_ARCH_STMP3XXX is not set
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
 # CONFIG_ARCH_IOP13XX is not set
 # CONFIG_ARCH_IOP32X is not set
 # CONFIG_ARCH_IOP33X is not set
@@ -175,18 +175,22 @@ CONFIG_ARCH_MXC=y
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
 # CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
 # CONFIG_ARCH_U300 is not set
 # CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_BCMRING is not set
 #
 # Freescale MXC Implementations
 #
 # CONFIG_ARCH_MX1 is not set
 # CONFIG_ARCH_MX2 is not set
+# CONFIG_ARCH_MX25 is not set
 CONFIG_ARCH_MX3=y
+# CONFIG_ARCH_MXC91231 is not set
 CONFIG_ARCH_MX31=y
 CONFIG_ARCH_MX35=y
@@ -205,6 +209,7 @@ CONFIG_MACH_QONG=y
 CONFIG_MACH_PCM043=y
 CONFIG_MACH_ARMADILLO5X0=y
 CONFIG_MACH_MX35_3DS=y
+CONFIG_MACH_KZM_ARM11_01=y
 CONFIG_MXC_IRQ_PRIOR=y
 CONFIG_MXC_PWM=y
 CONFIG_ARCH_HAS_RNGA=y
@@ -218,7 +223,7 @@ CONFIG_CPU_V6=y
 # CONFIG_CPU_32v6K is not set
 CONFIG_CPU_32v6=y
 CONFIG_CPU_ABRT_EV6=y
-CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_PABRT_V6=y
 CONFIG_CPU_CACHE_V6=y
 CONFIG_CPU_CACHE_VIPT=y
 CONFIG_CPU_COPY_V6=y
@@ -236,6 +241,7 @@ CONFIG_ARM_THUMB=y
 # CONFIG_CPU_BPREDICT_DISABLE is not set
 CONFIG_OUTER_CACHE=y
 CONFIG_CACHE_L2X0=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
 # CONFIG_ARM_ERRATA_411920 is not set
 CONFIG_COMMON_CLKDEV=y
@@ -257,6 +263,8 @@ CONFIG_VMSPLIT_3G=y
 # CONFIG_VMSPLIT_2G is not set
 # CONFIG_VMSPLIT_1G is not set
 CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
 CONFIG_PREEMPT=y
 CONFIG_HZ=100
 CONFIG_AEABI=y
@@ -277,6 +285,7 @@ CONFIG_ZONE_DMA_FLAG=0
 CONFIG_VIRT_TO_BUS=y
 CONFIG_HAVE_MLOCK=y
 CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
 CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 CONFIG_ALIGNMENT_TRAP=y
 # CONFIG_UACCESS_WITH_MEMCPY is not set
@@ -326,6 +335,7 @@ CONFIG_PM_SLEEP=y
 CONFIG_SUSPEND=y
 CONFIG_SUSPEND_FREEZER=y
 # CONFIG_APM_EMULATION is not set
+# CONFIG_PM_RUNTIME is not set
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
 CONFIG_NET=y
@@ -367,6 +377,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
 # CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
@@ -407,6 +418,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # Generic Driver Options
 #
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=m
@@ -416,9 +428,9 @@ CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_REDBOOT_PARTS is not set
 CONFIG_MTD_CMDLINE_PARTS=y
 # CONFIG_MTD_AFS_PARTS is not set
@@ -587,14 +599,12 @@ CONFIG_DNET=y
 # CONFIG_B44 is not set
 # CONFIG_CS89x0 is not set
 # CONFIG_KS8842 is not set
+# CONFIG_KS8851_MLL is not set
 CONFIG_FEC=y
 # CONFIG_FEC2 is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
+CONFIG_WLAN=y
-#
-# Wireless LAN
-#
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
@@ -608,6 +618,7 @@ CONFIG_FEC=y
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
 # CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
 #
 # Input device support
@@ -630,7 +641,14 @@ CONFIG_DEVKMEM=y
 #
 # Serial drivers
 #
-# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_8250=m
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
 #
 # Non-8250 serial port support
@@ -649,6 +667,7 @@ CONFIG_UNIX98_PTYS=y
 # CONFIG_TCG_TPM is not set
 CONFIG_I2C=y
 CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_HELPER_AUTO=y
@@ -681,15 +700,17 @@ CONFIG_I2C_IMX=y
 # Miscellaneous I2C Chip support
 #
 # CONFIG_DS1682 is not set
-# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_PCF8575 is not set
-# CONFIG_SENSORS_PCA9539 is not set
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
 # CONFIG_I2C_DEBUG_CHIP is not set
 # CONFIG_SPI is not set
+#
+# PPS support
+#
+# CONFIG_PPS is not set
 CONFIG_ARCH_REQUIRE_GPIOLIB=y
 CONFIG_GPIOLIB=y
 # CONFIG_GPIO_SYSFS is not set
@@ -712,6 +733,10 @@ CONFIG_GPIOLIB=y
 #
 # SPI GPIO expanders:
 #
+#
+# AC97 GPIO expanders:
+#
 CONFIG_W1=y
 #
@@ -734,7 +759,6 @@ CONFIG_W1_SLAVE_THERM=y
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
 # CONFIG_THERMAL is not set
-# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 CONFIG_SSB_POSSIBLE=y
@@ -759,12 +783,24 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_MFD_TC6393XB is not set
 # CONFIG_PMIC_DA903X is not set
 # CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
 CONFIG_MFD_WM8350=y
 CONFIG_MFD_WM8350_CONFIG_MODE_0=y
 CONFIG_MFD_WM8352_CONFIG_MODE_0=y
 CONFIG_MFD_WM8350_I2C=y
 # CONFIG_MFD_PCF50633 is not set
 # CONFIG_AB3100_CORE is not set
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+# CONFIG_REGULATOR_MAX1586 is not set
+CONFIG_REGULATOR_WM8350=y
+# CONFIG_REGULATOR_LP3971 is not set
+# CONFIG_REGULATOR_TPS65023 is not set
+# CONFIG_REGULATOR_TPS6507X is not set
 CONFIG_MEDIA_SUPPORT=y
 #
@@ -874,10 +910,12 @@ CONFIG_MMC_BLOCK_BOUNCE=y
 # MMC/SD/SDIO Host Controller Drivers
 #
 # CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_AT91 is not set
+# CONFIG_MMC_ATMELMCI is not set
 CONFIG_MMC_MXC=y
 # CONFIG_MEMSTICK is not set
-# CONFIG_ACCESSIBILITY is not set
 # CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
 CONFIG_RTC_LIB=y
 # CONFIG_RTC_CLASS is not set
 CONFIG_DMADEVICES=y
@@ -896,16 +934,11 @@ CONFIG_DMA_ENGINE=y
 # CONFIG_ASYNC_TX_DMA is not set
 # CONFIG_DMATEST is not set
 # CONFIG_AUXDISPLAY is not set
-CONFIG_REGULATOR=y
-# CONFIG_REGULATOR_DEBUG is not set
-# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
-# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
-# CONFIG_REGULATOR_BQ24022 is not set
-# CONFIG_REGULATOR_MAX1586 is not set
-CONFIG_REGULATOR_WM8350=y
-# CONFIG_REGULATOR_LP3971 is not set
 # CONFIG_UIO is not set
+#
+# TI VLYNQ
+#
 # CONFIG_STAGING is not set
 #
@@ -921,6 +954,7 @@ CONFIG_REGULATOR_WM8350=y
 # CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
 CONFIG_FILE_LOCKING=y
 CONFIG_FSNOTIFY=y
 # CONFIG_DNOTIFY is not set
@@ -995,7 +1029,6 @@ CONFIG_UBIFS_FS_ZLIB=y
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-# CONFIG_NILFS2_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
@@ -1033,6 +1066,7 @@ CONFIG_MSDOS_PARTITION=y
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
 # CONFIG_HEADERS_CHECK is not set
@@ -1062,7 +1096,6 @@ CONFIG_CRYPTO=y
 #
 # Crypto core or helper
 #
-# CONFIG_CRYPTO_FIPS is not set
 CONFIG_CRYPTO_ALGAPI=y
 CONFIG_CRYPTO_ALGAPI2=y
 CONFIG_CRYPTO_AEAD2=y
@@ -1104,11 +1137,13 @@ CONFIG_CRYPTO_CBC=y
 #
 # CONFIG_CRYPTO_HMAC is not set
 # CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
 #
 # Digest
 #
 # CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
 # CONFIG_CRYPTO_MD4 is not set
 CONFIG_CRYPTO_MD5=y
 # CONFIG_CRYPTO_MICHAEL_MIC is not set
diff --git a/arch/arm/configs/w90p910_defconfig b/arch/arm/configs/nuc910_defconfig
index 5245655a0ad3..5245655a0ad3 100644
--- a/arch/arm/configs/w90p910_defconfig
+++ b/arch/arm/configs/nuc910_defconfig
diff --git a/arch/arm/configs/nuc950_defconfig b/arch/arm/configs/nuc950_defconfig
new file mode 100644
index 000000000000..df1de9b45ca4
--- /dev/null
+++ b/arch/arm/configs/nuc950_defconfig
@@ -0,0 +1,922 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32-rc7
+# Tue Nov 17 12:31:33 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+CONFIG_USER_NS=y
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_COMPAT_BRK=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+# CONFIG_MODULES is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_FREEZER is not set
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+CONFIG_ARCH_W90X900=y
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_BCMRING is not set
+CONFIG_CPU_NUC950=y
+#
+# W90P910 Machines
+#
+# CONFIG_MACH_W90P910EVB is not set
+#
+# NUC950 Machines
+#
+CONFIG_MACH_W90P950EVB=y
+#
+# NUC960 Machines
+#
+# CONFIG_MACH_W90N960EVB is not set
+#
+# NUC932 Machines
+#
+# CONFIG_MACH_NUC932EVB is not set
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_COMMON_CLKDEV=y
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="root=/dev/ram0 console=ttyS0,115200n8 rdinit=/sbin/init mem=64M"
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+CONFIG_ATAGS_PROC=y
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+#
+# Floating point emulation
+#
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+CONFIG_BINFMT_AOUT=y
+CONFIG_BINFMT_MISC=y
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_NET is not set
+#
+# Device Drivers
+#
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_PLATRAM is not set
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_MG_DISK is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_PHONE is not set
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=1
+CONFIG_SERIAL_8250_RUNTIME_UARTS=1
+# CONFIG_SERIAL_8250_EXTENDED is not set
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_GPIO_SYSFS is not set
+#
+# Memory mapped GPIO expanders:
+#
+#
+# I2C GPIO expanders:
+#
+#
+# PCI GPIO expanders:
+#
+#
+# SPI GPIO expanders:
+#
+#
+# AC97 GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+# CONFIG_USB_GADGET is not set
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+CONFIG_GENERIC_ACL=y
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
+CONFIG_ROMFS_BACKED_BY_BLOCK=y
+# CONFIG_ROMFS_BACKED_BY_MTD is not set
+# CONFIG_ROMFS_BACKED_BY_BOTH is not set
+CONFIG_ROMFS_ON_BLOCK=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_ARM_UNWIND=y
+# CONFIG_DEBUG_USER is not set
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
+#
+# Library routines
+#
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+# CONFIG_CRC32 is not set
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/nuc960_defconfig b/arch/arm/configs/nuc960_defconfig
new file mode 100644
index 000000000000..4b2cd9eae9bc
--- /dev/null
+++ b/arch/arm/configs/nuc960_defconfig
@@ -0,0 +1,922 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32-rc7
+# Tue Nov 17 12:20:11 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+CONFIG_USER_NS=y
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_COMPAT_BRK=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+# CONFIG_MODULES is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_FREEZER is not set
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+CONFIG_ARCH_W90X900=y
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_BCMRING is not set
+CONFIG_CPU_NUC960=y
+#
+# W90P910 Machines
+#
+# CONFIG_MACH_W90P910EVB is not set
+#
+# NUC950 Machines
+#
+# CONFIG_MACH_W90P950EVB is not set
+#
+# NUC960 Machines
+#
+CONFIG_MACH_W90N960EVB=y
+#
+# NUC932 Machines
+#
+# CONFIG_MACH_NUC932EVB is not set
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_COMMON_CLKDEV=y
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="root=/dev/ram0 console=ttyS0,115200n8 rdinit=/sbin/init mem=64M"
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+CONFIG_ATAGS_PROC=y
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+#
+# Floating point emulation
+#
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+CONFIG_BINFMT_AOUT=y
+CONFIG_BINFMT_MISC=y
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_NET is not set
+#
+# Device Drivers
+#
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_PLATRAM is not set
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_MG_DISK is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_PHONE is not set
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=1
+CONFIG_SERIAL_8250_RUNTIME_UARTS=1
+# CONFIG_SERIAL_8250_EXTENDED is not set
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_GPIO_SYSFS is not set
+#
+# Memory mapped GPIO expanders:
+#
+#
+# I2C GPIO expanders:
+#
+#
+# PCI GPIO expanders:
+#
+#
+# SPI GPIO expanders:
+#
+#
+# AC97 GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+# CONFIG_USB_GADGET is not set
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+CONFIG_GENERIC_ACL=y
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
+CONFIG_ROMFS_BACKED_BY_BLOCK=y
+# CONFIG_ROMFS_BACKED_BY_MTD is not set
+# CONFIG_ROMFS_BACKED_BY_BOTH is not set
+CONFIG_ROMFS_ON_BLOCK=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_ARM_UNWIND=y
+# CONFIG_DEBUG_USER is not set
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
+#
+# Library routines
+#
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+# CONFIG_CRC32 is not set
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
new file mode 100644
index 000000000000..15fde22ce3f3
--- /dev/null
+++ b/arch/arm/configs/u8500_defconfig
@@ -0,0 +1,680 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32-rc8
+# Mon Nov 30 11:11:29 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_LOCKBREAK=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_USE_GENERIC_SMP_HELPERS=y
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_STOP_MACHINE=y
+CONFIG_BLOCK=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_FREEZER is not set
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_BCMRING is not set
+CONFIG_ARCH_U8500=y
+CONFIG_PLAT_NOMADIK=y
+CONFIG_HAS_MTU=y
+#
+# ST-Ericsson platform type
+#
+#
+# ST-Ericsson Multicore Mobile Platforms
+#
+CONFIG_MACH_U8500_MOP=y
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_ARM_THUMBEE is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_HAS_TLS_REG=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
+# CONFIG_ARM_ERRATA_430973 is not set
+# CONFIG_ARM_ERRATA_458693 is not set
+# CONFIG_ARM_ERRATA_460075 is not set
+CONFIG_ARM_GIC=y
+CONFIG_COMMON_CLKDEV=y
+#
+# Bus support
+#
+CONFIG_ARM_AMBA=y
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+#
+# Kernel Features
+#
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_SMP=y
+CONFIG_HAVE_ARM_SCU=y
+CONFIG_HAVE_ARM_TWD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_NR_CPUS=2
+# CONFIG_HOTPLUG_CPU is not set
+CONFIG_LOCAL_TIMERS=y
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+# CONFIG_THUMB2_KERNEL is not set
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="root=/dev/ram0 console=ttyAMA2,115200n8"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+#
+# Floating point emulation
+#
+#
+# At least one emulation must be selected
+#
+# CONFIG_FPE_NWFPE is not set
+# CONFIG_FPE_FASTFPE is not set
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_NET is not set
+#
+# Device Drivers
+#
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=65536
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_PHONE is not set
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_AMBA_PL010 is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+# CONFIG_SERIAL_MAX3100 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+CONFIG_SPI_PL022=y
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+CONFIG_GENERIC_ACL=y
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=m
+# CONFIG_MISC_FILESYSTEMS is not set
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARM_UNWIND=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
+#
+# Library routines
+#
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+CONFIG_CRC_T10DIF=m
+# CONFIG_CRC_ITU_T is not set
+# CONFIG_CRC32 is not set
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 3d0cdd21b882..9fd6d3ab68c0 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -331,15 +331,15 @@ static inline void outer_flush_range(unsigned long start, unsigned long end)
 * Convert calls to our calling convention.
 */
 #define flush_cache_all()               __cpuc_flush_kern_all()
-#ifndef CONFIG_CPU_CACHE_VIPT
-static inline void flush_cache_mm(struct mm_struct *mm)
+static inline void vivt_flush_cache_mm(struct mm_struct *mm)
 {
        if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm)))
                __cpuc_flush_user_all();
 }
 static inline void
-flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
+vivt_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
 {
        if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm)))
                __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
@@ -347,7 +347,7 @@ flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long
 }
 static inline void
-flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
+vivt_flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
 {
        if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
                unsigned long addr = user_addr & PAGE_MASK;
@@ -356,7 +356,7 @@ flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned l
 }
 static inline void
-flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
+vivt_flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
                         unsigned long uaddr, void *kaddr,
                         unsigned long len, int write)
 {
@@ -365,6 +365,16 @@ flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
                __cpuc_coherent_kern_range(addr, addr + len);
        }
 }
+#ifndef CONFIG_CPU_CACHE_VIPT
+#define flush_cache_mm(mm) \
+                vivt_flush_cache_mm(mm)
+#define flush_cache_range(vma,start,end) \
+                vivt_flush_cache_range(vma,start,end)
+#define flush_cache_page(vma,addr,pfn) \
+                vivt_flush_cache_page(vma,addr,pfn)
+#define flush_ptrace_access(vma,page,ua,ka,len,write) \
+                vivt_flush_ptrace_access(vma,page,ua,ka,len,write)
 #else
 extern void flush_cache_mm(struct mm_struct *mm);
 extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
@@ -410,8 +420,6 @@ extern void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
 */
 extern void flush_dcache_page(struct page *);
-extern void __flush_dcache_page(struct address_space *mapping, struct page *page);
 static inline void __flush_icache_all(void)
 {
 #ifdef CONFIG_ARM_ERRATA_411920
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index ff46dfa68a97..a96300bf83fd 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -15,20 +15,15 @@
 * must not be used by drivers.
 */
 #ifndef __arch_page_to_dma
-#if !defined(CONFIG_HIGHMEM)
 static inline dma_addr_t page_to_dma(struct device *dev, struct page *page)
 {
-        return (dma_addr_t)__virt_to_bus((unsigned long)page_address(page));
+        return (dma_addr_t)__pfn_to_bus(page_to_pfn(page));
 }
-#elif defined(__pfn_to_bus)
-static inline dma_addr_t page_to_dma(struct device *dev, struct page *page)
+static inline struct page *dma_to_page(struct device *dev, dma_addr_t addr)
 {
-        return (dma_addr_t)__pfn_to_bus(page_to_pfn(page));
+        return pfn_to_page(__bus_to_pfn(addr));
 }
-#else
-#error "this machine class needs to define __arch_page_to_dma to use HIGHMEM"
-#endif
 static inline void *dma_to_virt(struct device *dev, dma_addr_t addr)
 {
@@ -45,6 +40,11 @@ static inline dma_addr_t page_to_dma(struct device *dev, struct page *page)
        return __arch_page_to_dma(dev, page);
 }
+static inline struct page *dma_to_page(struct device *dev, dma_addr_t addr)
+{
+        return __arch_dma_to_page(dev, addr);
+}
 static inline void *dma_to_virt(struct device *dev, dma_addr_t addr)
 {
        return __arch_dma_to_virt(dev, addr);
@@ -257,9 +257,11 @@ extern int dma_needs_bounce(struct device*, dma_addr_t, size_t);
 */
 extern dma_addr_t dma_map_single(struct device *, void *, size_t,
                enum dma_data_direction);
+extern void dma_unmap_single(struct device *, dma_addr_t, size_t,
+                enum dma_data_direction);
 extern dma_addr_t dma_map_page(struct device *, struct page *,
                unsigned long, size_t, enum dma_data_direction);
-extern void dma_unmap_single(struct device *, dma_addr_t, size_t,
+extern void dma_unmap_page(struct device *, dma_addr_t, size_t,
                enum dma_data_direction);
 /*
@@ -352,7 +354,6 @@ static inline void dma_unmap_single(struct device *dev, dma_addr_t handle,
 {
        /* nothing to do */
 }
-#endif /* CONFIG_DMABOUNCE */
 /**
 * dma_unmap_page - unmap a buffer previously mapped through dma_map_page()
@@ -371,8 +372,9 @@ static inline void dma_unmap_single(struct device *dev, dma_addr_t handle,
 static inline void dma_unmap_page(struct device *dev, dma_addr_t handle,
                size_t size, enum dma_data_direction dir)
 {
-        dma_unmap_single(dev, handle, size, dir);
+        /* nothing to do */
 }
+#endif /* CONFIG_DMABOUNCE */
 /**
 * dma_sync_single_range_for_cpu
diff --git a/arch/arm/include/asm/hardware/cache-tauros2.h b/arch/arm/include/asm/hardware/cache-tauros2.h
new file mode 100644
index 000000000000..538f17ca905b
--- /dev/null
+++ b/arch/arm/include/asm/hardware/cache-tauros2.h
@@ -0,0 +1,11 @@
+/*
+ * arch/arm/include/asm/hardware/cache-tauros2.h
+ *
+ * Copyright (C) 2008 Marvell Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+extern void __init tauros2_init(void);
diff --git a/arch/arm/include/asm/hardware/coresight.h b/arch/arm/include/asm/hardware/coresight.h
new file mode 100644
index 000000000000..f82b25d4f73e
--- /dev/null
+++ b/arch/arm/include/asm/hardware/coresight.h
@@ -0,0 +1,165 @@
+/*
+ * linux/arch/arm/include/asm/hardware/coresight.h
+ *
+ * CoreSight components' registers
+ *
+ * Copyright (C) 2009 Nokia Corporation.
+ * Alexander Shishkin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_HARDWARE_CORESIGHT_H
+#define __ASM_HARDWARE_CORESIGHT_H
+#define TRACER_ACCESSED_BIT     0
+#define TRACER_RUNNING_BIT      1
+#define TRACER_CYCLE_ACC_BIT    2
+#define TRACER_ACCESSED         BIT(TRACER_ACCESSED_BIT)
+#define TRACER_RUNNING          BIT(TRACER_RUNNING_BIT)
+#define TRACER_CYCLE_ACC        BIT(TRACER_CYCLE_ACC_BIT)
+struct tracectx {
+        unsigned int    etb_bufsz;
+        void __iomem    *etb_regs;
+        void __iomem    *etm_regs;
+        unsigned long   flags;
+        int             ncmppairs;
+        int             etm_portsz;
+        struct device   *dev;
+        struct clk      *emu_clk;
+        struct mutex    mutex;
+};
+#define TRACER_TIMEOUT 10000
+#define etm_writel(t, v, x) \
+        (__raw_writel((v), (t)->etm_regs + (x)))
+#define etm_readl(t, x) (__raw_readl((t)->etm_regs + (x)))
+/* CoreSight Management Registers */
+#define CSMR_LOCKACCESS 0xfb0
+#define CSMR_LOCKSTATUS 0xfb4
+#define CSMR_AUTHSTATUS 0xfb8
+#define CSMR_DEVID      0xfc8
+#define CSMR_DEVTYPE    0xfcc
+/* CoreSight Component Registers */
+#define CSCR_CLASS      0xff4
+#define CSCR_PRSR       0x314
+#define UNLOCK_MAGIC    0xc5acce55
+/* ETM control register, "ETM Architecture", 3.3.1 */
+#define ETMR_CTRL               0
+#define ETMCTRL_POWERDOWN       1
+#define ETMCTRL_PROGRAM         (1 << 10)
+#define ETMCTRL_PORTSEL         (1 << 11)
+#define ETMCTRL_DO_CONTEXTID    (3 << 14)
+#define ETMCTRL_PORTMASK1       (7 << 4)
+#define ETMCTRL_PORTMASK2       (1 << 21)
+#define ETMCTRL_PORTMASK        (ETMCTRL_PORTMASK1 | ETMCTRL_PORTMASK2)
+#define ETMCTRL_PORTSIZE(x) ((((x) & 7) << 4) | (!!((x) & 8)) << 21)
+#define ETMCTRL_DO_CPRT         (1 << 1)
+#define ETMCTRL_DATAMASK        (3 << 2)
+#define ETMCTRL_DATA_DO_DATA    (1 << 2)
+#define ETMCTRL_DATA_DO_ADDR    (1 << 3)
+#define ETMCTRL_DATA_DO_BOTH    (ETMCTRL_DATA_DO_DATA | ETMCTRL_DATA_DO_ADDR)
+#define ETMCTRL_BRANCH_OUTPUT   (1 << 8)
+#define ETMCTRL_CYCLEACCURATE   (1 << 12)
+/* ETM configuration code register */
+#define ETMR_CONFCODE           (0x04)
+/* ETM trace start/stop resource control register */
+#define ETMR_TRACESSCTRL        (0x18)
+/* ETM trigger event register */
+#define ETMR_TRIGEVT            (0x08)
+/* address access type register bits, "ETM architecture",
+ * table 3-27 */
+/* - access type */
+#define ETMAAT_IFETCH           0
+#define ETMAAT_IEXEC            1
+#define ETMAAT_IEXECPASS        2
+#define ETMAAT_IEXECFAIL        3
+#define ETMAAT_DLOADSTORE       4
+#define ETMAAT_DLOAD            5
+#define ETMAAT_DSTORE           6
+/* - comparison access size */
+#define ETMAAT_JAVA             (0 << 3)
+#define ETMAAT_THUMB            (1 << 3)
+#define ETMAAT_ARM              (3 << 3)
+/* - data value comparison control */
+#define ETMAAT_NOVALCMP         (0 << 5)
+#define ETMAAT_VALMATCH         (1 << 5)
+#define ETMAAT_VALNOMATCH       (3 << 5)
+/* - exact match */
+#define ETMAAT_EXACTMATCH       (1 << 7)
+/* - context id comparator control */
+#define ETMAAT_IGNCONTEXTID     (0 << 8)
+#define ETMAAT_VALUE1           (1 << 8)
+#define ETMAAT_VALUE2           (2 << 8)
+#define ETMAAT_VALUE3           (3 << 8)
+/* - security level control */
+#define ETMAAT_IGNSECURITY      (0 << 10)
+#define ETMAAT_NSONLY           (1 << 10)
+#define ETMAAT_SONLY            (2 << 10)
+#define ETMR_COMP_VAL(x)        (0x40 + (x) * 4)
+#define ETMR_COMP_ACC_TYPE(x)   (0x80 + (x) * 4)
+/* ETM status register, "ETM Architecture", 3.3.2 */
+#define ETMR_STATUS             (0x10)
+#define ETMST_OVERFLOW          (1 << 0)
+#define ETMST_PROGBIT           (1 << 1)
+#define ETMST_STARTSTOP         (1 << 2)
+#define ETMST_TRIGGER           (1 << 3)
+#define etm_progbit(t)          (etm_readl((t), ETMR_STATUS) & ETMST_PROGBIT)
+#define etm_started(t)          (etm_readl((t), ETMR_STATUS) & ETMST_STARTSTOP)
+#define etm_triggered(t)        (etm_readl((t), ETMR_STATUS) & ETMST_TRIGGER)
+#define ETMR_TRACEENCTRL2       0x1c
+#define ETMR_TRACEENCTRL        0x24
+#define ETMTE_INCLEXCL          (1 << 24)
+#define ETMR_TRACEENEVT         0x20
+#define ETMCTRL_OPTS            (ETMCTRL_DO_CPRT | \
+                                ETMCTRL_DATA_DO_ADDR | \
+                                ETMCTRL_BRANCH_OUTPUT | \
+                                ETMCTRL_DO_CONTEXTID)
+/* ETB registers, "CoreSight Components TRM", 9.3 */
+#define ETBR_DEPTH              0x04
+#define ETBR_STATUS             0x0c
+#define ETBR_READMEM            0x10
+#define ETBR_READADDR           0x14
+#define ETBR_WRITEADDR          0x18
+#define ETBR_TRIGGERCOUNT       0x1c
+#define ETBR_CTRL               0x20
+#define ETBR_FORMATTERCTRL      0x304
+#define ETBFF_ENFTC             1
+#define ETBFF_ENFCONT           (1 << 1)
+#define ETBFF_FONFLIN           (1 << 4)
+#define ETBFF_MANUAL_FLUSH      (1 << 6)
+#define ETBFF_TRIGIN            (1 << 8)
+#define ETBFF_TRIGEVT           (1 << 9)
+#define ETBFF_TRIGFL            (1 << 10)
+#define etb_writel(t, v, x) \
+        (__raw_writel((v), (t)->etb_regs + (x)))
+#define etb_readl(t, x) (__raw_readl((t)->etb_regs + (x)))
+#define etm_lock(t) do { etm_writel((t), 0, CSMR_LOCKACCESS); } while (0)
+#define etm_unlock(t) \
+        do { etm_writel((t), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0)
+#define etb_lock(t) do { etb_writel((t), 0, CSMR_LOCKACCESS); } while (0)
+#define etb_unlock(t) \
+        do { etb_writel((t), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0)
+#endif /* __ASM_HARDWARE_CORESIGHT_H */
diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h
index 8d60ad267e3a..5daea2961d48 100644
--- a/arch/arm/include/asm/hardware/iop3xx.h
+++ b/arch/arm/include/asm/hardware/iop3xx.h
@@ -234,7 +234,13 @@ extern int iop3xx_get_init_atu(void);
 void iop3xx_map_io(void);
 void iop_init_cp6_handler(void);
 void iop_init_time(unsigned long tickrate);
-unsigned long iop_gettimeoffset(void);
+static inline u32 read_tmr0(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c0, c1, 0" : "=r" (val));
+        return val;
+}
 static inline void write_tmr0(u32 val)
 {
@@ -253,6 +259,11 @@ static inline u32 read_tcr0(void)
        return val;
 }
+static inline void write_tcr0(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c2, c1, 0" : : "r" (val));
+}
 static inline u32 read_tcr1(void)
 {
        u32 val;
@@ -260,6 +271,11 @@ static inline u32 read_tcr1(void)
        return val;
 }
+static inline void write_tcr1(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c3, c1, 0" : : "r" (val));
+}
 static inline void write_trr0(u32 val)
 {
        asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val));
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index cefedf062138..5421d82a2572 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -125,8 +125,10 @@
 * private definitions which should NOT be used outside memory.h
 * files.  Use virt_to_phys/phys_to_virt/__pa/__va instead.
 */
+#ifndef __virt_to_phys
 #define __virt_to_phys(x)       ((x) - PAGE_OFFSET + PHYS_OFFSET)
 #define __phys_to_virt(x)       ((x) - PHYS_OFFSET + PAGE_OFFSET)
+#endif
 /*
 * Convert a physical address to a Page Frame Number and back
@@ -134,6 +136,12 @@
 #define __phys_to_pfn(paddr)    ((paddr) >> PAGE_SHIFT)
 #define __pfn_to_phys(pfn)      ((pfn) << PAGE_SHIFT)
+/*
+ * Convert a page to/from a physical address
+ */
+#define page_to_phys(page)      (__pfn_to_phys(page_to_pfn(page)))
+#define phys_to_page(phys)      (pfn_to_page(__phys_to_pfn(phys)))
 #ifndef __ASSEMBLY__
 /*
@@ -194,7 +202,8 @@ static inline void *phys_to_virt(unsigned long x)
 #ifndef __virt_to_bus
 #define __virt_to_bus   __virt_to_phys
 #define __bus_to_virt   __phys_to_virt
-#define __pfn_to_bus(x) ((x) << PAGE_SHIFT)
+#define __pfn_to_bus(x) __pfn_to_phys(x)
+#define __bus_to_pfn(x) __phys_to_pfn(x)
 #endif
 static inline __deprecated unsigned long virt_to_bus(void *x)
@@ -293,11 +302,6 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
 #endif /* !CONFIG_DISCONTIGMEM */
 /*
- * For BIO.  "will die".  Kill me when bio_to_phys() and bvec_to_phys() die.
- */
-#define page_to_phys(page)      (page_to_pfn(page) << PAGE_SHIFT)
-/*
 * Optional coherency support.  Currently used only by selected
 * Intel XSC3-based systems.
 */
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 201ccaa11f61..11397687f42c 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -304,13 +304,23 @@ PTE_BIT_FUNC(mkyoung,   |= L_PTE_YOUNG);
 static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
+#define __pgprot_modify(prot,mask,bits)         \
+        __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
 /*
 * Mark the prot value as uncacheable and unbufferable.
 */
 #define pgprot_noncached(prot) \
-        __pgprot((pgprot_val(prot) & ~L_PTE_MT_MASK) | L_PTE_MT_UNCACHED)
+        __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
 #define pgprot_writecombine(prot) \
-        __pgprot((pgprot_val(prot) & ~L_PTE_MT_MASK) | L_PTE_MT_BUFFERABLE)
+        __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE)
+#if __LINUX_ARM_ARCH__ >= 7
+#define pgprot_dmacoherent(prot) \
+        __pgprot_modify(prot, L_PTE_MT_MASK|L_PTE_EXEC, L_PTE_MT_BUFFERABLE)
+#else
+#define pgprot_dmacoherent(prot) \
+        __pgprot_modify(prot, L_PTE_MT_MASK|L_PTE_EXEC, L_PTE_MT_UNCACHED)
+#endif
 #define pmd_none(pmd)           (!pmd_val(pmd))
 #define pmd_present(pmd)        (pmd_val(pmd))
diff --git a/arch/arm/include/asm/swab.h b/arch/arm/include/asm/swab.h
index ca2bf2f6d6ea..9997ad20eff1 100644
--- a/arch/arm/include/asm/swab.h
+++ b/arch/arm/include/asm/swab.h
@@ -22,6 +22,24 @@
 #  define __SWAB_64_THRU_32__
 #endif
+#if defined(__KERNEL__) && __LINUX_ARM_ARCH__ >= 6
+static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
+{
+        __asm__ ("rev16 %0, %1" : "=r" (x) : "r" (x));
+        return x;
+}
+#define __arch_swab16 __arch_swab16
+static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
+{
+        __asm__ ("rev %0, %1" : "=r" (x) : "r" (x));
+        return x;
+}
+#define __arch_swab32 __arch_swab32
+#else
 static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
 {
        __u32 t;
@@ -48,3 +66,4 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
 #endif
+#endif
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index d65b2f5bf41f..058e7e90881d 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -138,21 +138,26 @@ extern unsigned int user_debug;
 #define dmb() __asm__ __volatile__ ("" : : : "memory")
 #endif
-#ifndef CONFIG_SMP
+#if __LINUX_ARM_ARCH__ >= 7 || defined(CONFIG_SMP)
+#define mb()            dmb()
+#define rmb()           dmb()
+#define wmb()           dmb()
+#else
 #define mb()    do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
 #define rmb()   do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
 #define wmb()   do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
+#endif
+#ifndef CONFIG_SMP
 #define smp_mb()        barrier()
 #define smp_rmb()       barrier()
 #define smp_wmb()       barrier()
 #else
-#define mb()            dmb()
+#define smp_mb()        mb()
-#define rmb()           dmb()
+#define smp_rmb()       rmb()
-#define wmb()           dmb()
+#define smp_wmb()       wmb()
-#define smp_mb()        dmb()
-#define smp_rmb()       dmb()
-#define smp_wmb()       dmb()
 #endif
 #define read_barrier_depends()          do { } while(0)
 #define smp_read_barrier_depends()      do { } while(0)
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 79087dd6d869..e7ccf7e697ce 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -17,6 +17,8 @@ obj-y		:= compat.o elf.o entry-armv.o entry-common.o irq.o \
                   process.o ptrace.o return_address.o setup.o signal.o \
                   sys_arm.o stacktrace.o time.o traps.o
+obj-$(CONFIG_OC_ETM)            += etm.o
 obj-$(CONFIG_ISA_DMA_API)       += dma.o
 obj-$(CONFIG_ARCH_ACORN)        += ecard.o 
 obj-$(CONFIG_FIQ)               += fiq.o
diff --git a/arch/arm/kernel/etm.c b/arch/arm/kernel/etm.c
new file mode 100644
index 000000000000..827753966301
--- /dev/null
+++ b/arch/arm/kernel/etm.c
@@ -0,0 +1,641 @@
+/*
+ * linux/arch/arm/kernel/etm.c
+ *
+ * Driver for ARM's Embedded Trace Macrocell and Embedded Trace Buffer.
+ *
+ * Copyright (C) 2009 Nokia Corporation.
+ * Alexander Shishkin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/io.h>
+#include <linux/sysrq.h>
+#include <linux/device.h>
+#include <linux/clk.h>
+#include <linux/amba/bus.h>
+#include <linux/fs.h>
+#include <linux/uaccess.h>
+#include <linux/miscdevice.h>
+#include <linux/vmalloc.h>
+#include <linux/mutex.h>
+#include <asm/hardware/coresight.h>
+#include <asm/sections.h>
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Alexander Shishkin");
+static struct tracectx tracer;
+static inline bool trace_isrunning(struct tracectx *t)
+{
+        return !!(t->flags & TRACER_RUNNING);
+}
+static int etm_setup_address_range(struct tracectx *t, int n,
+                unsigned long start, unsigned long end, int exclude, int data)
+{
+        u32 flags = ETMAAT_ARM | ETMAAT_IGNCONTEXTID | ETMAAT_NSONLY | \
+                    ETMAAT_NOVALCMP;
+        if (n < 1 || n > t->ncmppairs)
+                return -EINVAL;
+        /* comparators and ranges are numbered starting with 1 as opposed
+         * to bits in a word */
+        n--;
+        if (data)
+                flags |= ETMAAT_DLOADSTORE;
+        else
+                flags |= ETMAAT_IEXEC;
+        /* first comparator for the range */
+        etm_writel(t, flags, ETMR_COMP_ACC_TYPE(n * 2));
+        etm_writel(t, start, ETMR_COMP_VAL(n * 2));
+        /* second comparator is right next to it */
+        etm_writel(t, flags, ETMR_COMP_ACC_TYPE(n * 2 + 1));
+        etm_writel(t, end, ETMR_COMP_VAL(n * 2 + 1));
+        flags = exclude ? ETMTE_INCLEXCL : 0;
+        etm_writel(t, flags | (1 << n), ETMR_TRACEENCTRL);
+        return 0;
+}
+static int trace_start(struct tracectx *t)
+{
+        u32 v;
+        unsigned long timeout = TRACER_TIMEOUT;
+        etb_unlock(t);
+        etb_writel(t, 0, ETBR_FORMATTERCTRL);
+        etb_writel(t, 1, ETBR_CTRL);
+        etb_lock(t);
+        /* configure etm */
+        v = ETMCTRL_OPTS | ETMCTRL_PROGRAM | ETMCTRL_PORTSIZE(t->etm_portsz);
+        if (t->flags & TRACER_CYCLE_ACC)
+                v |= ETMCTRL_CYCLEACCURATE;
+        etm_unlock(t);
+        etm_writel(t, v, ETMR_CTRL);
+        while (!(etm_readl(t, ETMR_CTRL) & ETMCTRL_PROGRAM) && --timeout)
+                ;
+        if (!timeout) {
+                dev_dbg(t->dev, "Waiting for progbit to assert timed out\n");
+                etm_lock(t);
+                return -EFAULT;
+        }
+        etm_setup_address_range(t, 1, (unsigned long)_stext,
+                        (unsigned long)_etext, 0, 0);
+        etm_writel(t, 0, ETMR_TRACEENCTRL2);
+        etm_writel(t, 0, ETMR_TRACESSCTRL);
+        etm_writel(t, 0x6f, ETMR_TRACEENEVT);
+        v &= ~ETMCTRL_PROGRAM;
+        v |= ETMCTRL_PORTSEL;
+        etm_writel(t, v, ETMR_CTRL);
+        timeout = TRACER_TIMEOUT;
+        while (etm_readl(t, ETMR_CTRL) & ETMCTRL_PROGRAM && --timeout)
+                ;
+        if (!timeout) {
+                dev_dbg(t->dev, "Waiting for progbit to deassert timed out\n");
+                etm_lock(t);
+                return -EFAULT;
+        }
+        etm_lock(t);
+        t->flags |= TRACER_RUNNING;
+        return 0;
+}
+static int trace_stop(struct tracectx *t)
+{
+        unsigned long timeout = TRACER_TIMEOUT;
+        etm_unlock(t);
+        etm_writel(t, 0x440, ETMR_CTRL);
+        while (!(etm_readl(t, ETMR_CTRL) & ETMCTRL_PROGRAM) && --timeout)
+                ;
+        if (!timeout) {
+                dev_dbg(t->dev, "Waiting for progbit to assert timed out\n");
+                etm_lock(t);
+                return -EFAULT;
+        }
+        etm_lock(t);
+        etb_unlock(t);
+        etb_writel(t, ETBFF_MANUAL_FLUSH, ETBR_FORMATTERCTRL);
+        timeout = TRACER_TIMEOUT;
+        while (etb_readl(t, ETBR_FORMATTERCTRL) &
+                        ETBFF_MANUAL_FLUSH && --timeout)
+                ;
+        if (!timeout) {
+                dev_dbg(t->dev, "Waiting for formatter flush to commence "
+                                "timed out\n");
+                etb_lock(t);
+                return -EFAULT;
+        }
+        etb_writel(t, 0, ETBR_CTRL);
+        etb_lock(t);
+        t->flags &= ~TRACER_RUNNING;
+        return 0;
+}
+static int etb_getdatalen(struct tracectx *t)
+{
+        u32 v;
+        int rp, wp;
+        v = etb_readl(t, ETBR_STATUS);
+        if (v & 1)
+                return t->etb_bufsz;
+        rp = etb_readl(t, ETBR_READADDR);
+        wp = etb_readl(t, ETBR_WRITEADDR);
+        if (rp > wp) {
+                etb_writel(t, 0, ETBR_READADDR);
+                etb_writel(t, 0, ETBR_WRITEADDR);
+                return 0;
+        }
+        return wp - rp;
+}
+/* sysrq+v will always stop the running trace and leave it at that */
+static void etm_dump(void)
+{
+        struct tracectx *t = &tracer;
+        u32 first = 0;
+        int length;
+        if (!t->etb_regs) {
+                printk(KERN_INFO "No tracing hardware found\n");
+                return;
+        }
+        if (trace_isrunning(t))
+                trace_stop(t);
+        etb_unlock(t);
+        length = etb_getdatalen(t);
+        if (length == t->etb_bufsz)
+                first = etb_readl(t, ETBR_WRITEADDR);
+        etb_writel(t, first, ETBR_READADDR);
+        printk(KERN_INFO "Trace buffer contents length: %d\n", length);
+        printk(KERN_INFO "--- ETB buffer begin ---\n");
+        for (; length; length--)
+                printk("%08x", cpu_to_be32(etb_readl(t, ETBR_READMEM)));
+        printk(KERN_INFO "\n--- ETB buffer end ---\n");
+        /* deassert the overflow bit */
+        etb_writel(t, 1, ETBR_CTRL);
+        etb_writel(t, 0, ETBR_CTRL);
+        etb_writel(t, 0, ETBR_TRIGGERCOUNT);
+        etb_writel(t, 0, ETBR_READADDR);
+        etb_writel(t, 0, ETBR_WRITEADDR);
+        etb_lock(t);
+}
+static void sysrq_etm_dump(int key, struct tty_struct *tty)
+{
+        dev_dbg(tracer.dev, "Dumping ETB buffer\n");
+        etm_dump();
+}
+static struct sysrq_key_op sysrq_etm_op = {
+        .handler = sysrq_etm_dump,
+        .help_msg = "ETM buffer dump",
+        .action_msg = "etm",
+};
+static int etb_open(struct inode *inode, struct file *file)
+{
+        if (!tracer.etb_regs)
+                return -ENODEV;
+        file->private_data = &tracer;
+        return nonseekable_open(inode, file);
+}
+static ssize_t etb_read(struct file *file, char __user *data,
+                size_t len, loff_t *ppos)
+{
+        int total, i;
+        long length;
+        struct tracectx *t = file->private_data;
+        u32 first = 0;
+        u32 *buf;
+        mutex_lock(&t->mutex);
+        if (trace_isrunning(t)) {
+                length = 0;
+                goto out;
+        }
+        etb_unlock(t);
+        total = etb_getdatalen(t);
+        if (total == t->etb_bufsz)
+                first = etb_readl(t, ETBR_WRITEADDR);
+        etb_writel(t, first, ETBR_READADDR);
+        length = min(total * 4, (int)len);
+        buf = vmalloc(length);
+        dev_dbg(t->dev, "ETB buffer length: %d\n", total);
+        dev_dbg(t->dev, "ETB status reg: %x\n", etb_readl(t, ETBR_STATUS));
+        for (i = 0; i < length / 4; i++)
+                buf[i] = etb_readl(t, ETBR_READMEM);
+        /* the only way to deassert overflow bit in ETB status is this */
+        etb_writel(t, 1, ETBR_CTRL);
+        etb_writel(t, 0, ETBR_CTRL);
+        etb_writel(t, 0, ETBR_WRITEADDR);
+        etb_writel(t, 0, ETBR_READADDR);
+        etb_writel(t, 0, ETBR_TRIGGERCOUNT);
+        etb_lock(t);
+        length -= copy_to_user(data, buf, length);
+        vfree(buf);
+out:
+        mutex_unlock(&t->mutex);
+        return length;
+}
+static int etb_release(struct inode *inode, struct file *file)
+{
+        /* there's nothing to do here, actually */
+        return 0;
+}
+static const struct file_operations etb_fops = {
+        .owner = THIS_MODULE,
+        .read = etb_read,
+        .open = etb_open,
+        .release = etb_release,
+};
+static struct miscdevice etb_miscdev = {
+        .name = "tracebuf",
+        .minor = 0,
+        .fops = &etb_fops,
+};
+static int __init etb_probe(struct amba_device *dev, struct amba_id *id)
+{
+        struct tracectx *t = &tracer;
+        int ret = 0;
+        ret = amba_request_regions(dev, NULL);
+        if (ret)
+                goto out;
+        t->etb_regs = ioremap_nocache(dev->res.start, resource_size(&dev->res));
+        if (!t->etb_regs) {
+                ret = -ENOMEM;
+                goto out_release;
+        }
+        amba_set_drvdata(dev, t);
+        etb_miscdev.parent = &dev->dev;
+        ret = misc_register(&etb_miscdev);
+        if (ret)
+                goto out_unmap;
+        t->emu_clk = clk_get(&dev->dev, "emu_src_ck");
+        if (IS_ERR(t->emu_clk)) {
+                dev_dbg(&dev->dev, "Failed to obtain emu_src_ck.\n");
+                return -EFAULT;
+        }
+        clk_enable(t->emu_clk);
+        etb_unlock(t);
+        t->etb_bufsz = etb_readl(t, ETBR_DEPTH);
+        dev_dbg(&dev->dev, "Size: %x\n", t->etb_bufsz);
+        /* make sure trace capture is disabled */
+        etb_writel(t, 0, ETBR_CTRL);
+        etb_writel(t, 0x1000, ETBR_FORMATTERCTRL);
+        etb_lock(t);
+        dev_dbg(&dev->dev, "ETB AMBA driver initialized.\n");
+out:
+        return ret;
+out_unmap:
+        amba_set_drvdata(dev, NULL);
+        iounmap(t->etb_regs);
+out_release:
+        amba_release_regions(dev);
+        return ret;
+}
+static int etb_remove(struct amba_device *dev)
+{
+        struct tracectx *t = amba_get_drvdata(dev);
+        amba_set_drvdata(dev, NULL);
+        iounmap(t->etb_regs);
+        t->etb_regs = NULL;
+        clk_disable(t->emu_clk);
+        clk_put(t->emu_clk);
+        amba_release_regions(dev);
+        return 0;
+}
+static struct amba_id etb_ids[] = {
+        {
+                .id     = 0x0003b907,
+                .mask   = 0x0007ffff,
+        },
+        { 0, 0 },
+};
+static struct amba_driver etb_driver = {
+        .drv            = {
+                .name   = "etb",
+                .owner  = THIS_MODULE,
+        },
+        .probe          = etb_probe,
+        .remove         = etb_remove,
+        .id_table       = etb_ids,
+};
+/* use a sysfs file "trace_running" to start/stop tracing */
+static ssize_t trace_running_show(struct kobject *kobj,
+                                  struct kobj_attribute *attr,
+                                  char *buf)
+{
+        return sprintf(buf, "%x\n", trace_isrunning(&tracer));
+}
+static ssize_t trace_running_store(struct kobject *kobj,
+                                   struct kobj_attribute *attr,
+                                   const char *buf, size_t n)
+{
+        unsigned int value;
+        int ret;
+        if (sscanf(buf, "%u", &value) != 1)
+                return -EINVAL;
+        mutex_lock(&tracer.mutex);
+        ret = value ? trace_start(&tracer) : trace_stop(&tracer);
+        mutex_unlock(&tracer.mutex);
+        return ret ? : n;
+}
+static struct kobj_attribute trace_running_attr =
+        __ATTR(trace_running, 0644, trace_running_show, trace_running_store);
+static ssize_t trace_info_show(struct kobject *kobj,
+                                  struct kobj_attribute *attr,
+                                  char *buf)
+{
+        u32 etb_wa, etb_ra, etb_st, etb_fc, etm_ctrl, etm_st;
+        int datalen;
+        etb_unlock(&tracer);
+        datalen = etb_getdatalen(&tracer);
+        etb_wa = etb_readl(&tracer, ETBR_WRITEADDR);
+        etb_ra = etb_readl(&tracer, ETBR_READADDR);
+        etb_st = etb_readl(&tracer, ETBR_STATUS);
+        etb_fc = etb_readl(&tracer, ETBR_FORMATTERCTRL);
+        etb_lock(&tracer);
+        etm_unlock(&tracer);
+        etm_ctrl = etm_readl(&tracer, ETMR_CTRL);
+        etm_st = etm_readl(&tracer, ETMR_STATUS);
+        etm_lock(&tracer);
+        return sprintf(buf, "Trace buffer len: %d\nComparator pairs: %d\n"
+                        "ETBR_WRITEADDR:\t%08x\n"
+                        "ETBR_READADDR:\t%08x\n"
+                        "ETBR_STATUS:\t%08x\n"
+                        "ETBR_FORMATTERCTRL:\t%08x\n"
+                        "ETMR_CTRL:\t%08x\n"
+                        "ETMR_STATUS:\t%08x\n",
+                        datalen,
+                        tracer.ncmppairs,
+                        etb_wa,
+                        etb_ra,
+                        etb_st,
+                        etb_fc,
+                        etm_ctrl,
+                        etm_st
+                        );
+}
+static struct kobj_attribute trace_info_attr =
+        __ATTR(trace_info, 0444, trace_info_show, NULL);
+static ssize_t trace_mode_show(struct kobject *kobj,
+                                  struct kobj_attribute *attr,
+                                  char *buf)
+{
+        return sprintf(buf, "%d %d\n",
+                        !!(tracer.flags & TRACER_CYCLE_ACC),
+                        tracer.etm_portsz);
+}
+static ssize_t trace_mode_store(struct kobject *kobj,
+                                   struct kobj_attribute *attr,
+                                   const char *buf, size_t n)
+{
+        unsigned int cycacc, portsz;
+        if (sscanf(buf, "%u %u", &cycacc, &portsz) != 2)
+                return -EINVAL;
+        mutex_lock(&tracer.mutex);
+        if (cycacc)
+                tracer.flags |= TRACER_CYCLE_ACC;
+        else
+                tracer.flags &= ~TRACER_CYCLE_ACC;
+        tracer.etm_portsz = portsz & 0x0f;
+        mutex_unlock(&tracer.mutex);
+        return n;
+}
+static struct kobj_attribute trace_mode_attr =
+        __ATTR(trace_mode, 0644, trace_mode_show, trace_mode_store);
+static int __init etm_probe(struct amba_device *dev, struct amba_id *id)
+{
+        struct tracectx *t = &tracer;
+        int ret = 0;
+        if (t->etm_regs) {
+                dev_dbg(&dev->dev, "ETM already initialized\n");
+                ret = -EBUSY;
+                goto out;
+        }
+        ret = amba_request_regions(dev, NULL);
+        if (ret)
+                goto out;
+        t->etm_regs = ioremap_nocache(dev->res.start, resource_size(&dev->res));
+        if (!t->etm_regs) {
+                ret = -ENOMEM;
+                goto out_release;
+        }
+        amba_set_drvdata(dev, t);
+        mutex_init(&t->mutex);
+        t->dev = &dev->dev;
+        t->flags = TRACER_CYCLE_ACC;
+        t->etm_portsz = 1;
+        etm_unlock(t);
+        ret = etm_readl(t, CSCR_PRSR);
+        t->ncmppairs = etm_readl(t, ETMR_CONFCODE) & 0xf;
+        etm_writel(t, 0x440, ETMR_CTRL);
+        etm_lock(t);
+        ret = sysfs_create_file(&dev->dev.kobj,
+                        &trace_running_attr.attr);
+        if (ret)
+                goto out_unmap;
+        /* failing to create any of these two is not fatal */
+        ret = sysfs_create_file(&dev->dev.kobj, &trace_info_attr.attr);
+        if (ret)
+                dev_dbg(&dev->dev, "Failed to create trace_info in sysfs\n");
+        ret = sysfs_create_file(&dev->dev.kobj, &trace_mode_attr.attr);
+        if (ret)
+                dev_dbg(&dev->dev, "Failed to create trace_mode in sysfs\n");
+        dev_dbg(t->dev, "ETM AMBA driver initialized.\n");
+out:
+        return ret;
+out_unmap:
+        amba_set_drvdata(dev, NULL);
+        iounmap(t->etm_regs);
+out_release:
+        amba_release_regions(dev);
+        return ret;
+}
+static int etm_remove(struct amba_device *dev)
+{
+        struct tracectx *t = amba_get_drvdata(dev);
+        amba_set_drvdata(dev, NULL);
+        iounmap(t->etm_regs);
+        t->etm_regs = NULL;
+        amba_release_regions(dev);
+        sysfs_remove_file(&dev->dev.kobj, &trace_running_attr.attr);
+        sysfs_remove_file(&dev->dev.kobj, &trace_info_attr.attr);
+        sysfs_remove_file(&dev->dev.kobj, &trace_mode_attr.attr);
+        return 0;
+}
+static struct amba_id etm_ids[] = {
+        {
+                .id     = 0x0003b921,
+                .mask   = 0x0007ffff,
+        },
+        { 0, 0 },
+};
+static struct amba_driver etm_driver = {
+        .drv            = {
+                .name   = "etm",
+                .owner  = THIS_MODULE,
+        },
+        .probe          = etm_probe,
+        .remove         = etm_remove,
+        .id_table       = etm_ids,
+};
+static int __init etm_init(void)
+{
+        int retval;
+        retval = amba_driver_register(&etb_driver);
+        if (retval) {
+                printk(KERN_ERR "Failed to register etb\n");
+                return retval;
+        }
+        retval = amba_driver_register(&etm_driver);
+        if (retval) {
+                amba_driver_unregister(&etb_driver);
+                printk(KERN_ERR "Failed to probe etm\n");
+                return retval;
+        }
+        /* not being able to install this handler is not fatal */
+        (void)register_sysrq_key('v', &sysrq_etm_op);
+        return 0;
+}
+device_initcall(etm_init);
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index e5dfc2895e24..573b803dc6bf 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -32,7 +32,7 @@
 * numbers for r1.
 *
 */
-        .section ".text.head", "ax"
+        __HEAD
 ENTRY(stext)
        setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
                                                @ and irqs disabled
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 38ccbe1d3b2c..eb62bf947212 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -74,7 +74,7 @@
 * crap here - that's what the boot loader (or in extreme, well justified
 * circumstances, zImage) is for.
 */
-        .section ".text.head", "ax"
+        __HEAD
 ENTRY(stext)
        setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
                                                @ and irqs disabled
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index aecf87dfbaec..71151bd87a36 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -24,13 +24,11 @@ SECTIONS
 #else
        . = PAGE_OFFSET + TEXT_OFFSET;
 #endif
-        .text.head : {
-                _stext = .;
-                _sinittext = .;
-                *(.text.head)
-        }
        .init : {                       /* Init code and data           */
+                _stext = .;
+                _sinittext = .;
+                        HEAD_TEXT
                        INIT_TEXT
                _einittext = .;
                __proc_info_begin = .;
@@ -42,43 +40,31 @@ SECTIONS
                __tagtable_begin = .;
                        *(.taglist.init)
                __tagtable_end = .;
-                . = ALIGN(16);
-                __setup_start = .;
+                INIT_SETUP(16)
-                        *(.init.setup)
-                __setup_end = .;
                __early_begin = .;
                        *(.early_param.init)
                __early_end = .;
-                __initcall_start = .;
-                        INITCALLS
+                INIT_CALLS
-                __initcall_end = .;
+                CON_INITCALL
-                __con_initcall_start = .;
+                SECURITY_INITCALL
-                        *(.con_initcall.init)
+                INIT_RAM_FS
-                __con_initcall_end = .;
-                __security_initcall_start = .;
-                        *(.security_initcall.init)
-                __security_initcall_end = .;
-#ifdef CONFIG_BLK_DEV_INITRD
-                . = ALIGN(32);
-                __initramfs_start = .;
-                        usr/built-in.o(.init.ramfs)
-                __initramfs_end = .;
-#endif
-                . = ALIGN(PAGE_SIZE);
-                __per_cpu_load = .;
-                __per_cpu_start = .;
-                        *(.data.percpu.page_aligned)
-                        *(.data.percpu)
-                        *(.data.percpu.shared_aligned)
-                __per_cpu_end = .;
 #ifndef CONFIG_XIP_KERNEL
                __init_begin = _stext;
                INIT_DATA
-                . = ALIGN(PAGE_SIZE);
-                __init_end = .;
 #endif
        }
+        PERCPU(PAGE_SIZE)
+#ifndef CONFIG_XIP_KERNEL
+        . = ALIGN(PAGE_SIZE);
+        __init_end = .;
+#endif
        /DISCARD/ : {                   /* Exit code and data           */
                EXIT_TEXT
                EXIT_DATA
@@ -157,7 +143,7 @@ SECTIONS
                 * first, the init task union, aligned
                 * to an 8192 byte boundary.
                 */
-                *(.data.init_task)
+                INIT_TASK_DATA(THREAD_SIZE)
 #ifdef CONFIG_XIP_KERNEL
                . = ALIGN(PAGE_SIZE);
@@ -167,17 +153,8 @@ SECTIONS
                __init_end = .;
 #endif
-                . = ALIGN(PAGE_SIZE);
+                NOSAVE_DATA
-                __nosave_begin = .;
+                CACHELINE_ALIGNED_DATA(32)
-                *(.data.nosave)
-                . = ALIGN(PAGE_SIZE);
-                __nosave_end = .;
-                /*
-                 * then the cacheline aligned data
-                 */
-                . = ALIGN(32);
-                *(.data.cacheline_aligned)
                /*
                 * The exception fixup table (might need resorting at runtime)
@@ -256,20 +233,10 @@ SECTIONS
        }
 #endif
-        .bss : {
+        BSS_SECTION(0, 0, 0)
-                __bss_start = .;        /* BSS                          */
+        _end = .;
-                *(.bss)
-                *(COMMON)
+        STABS_DEBUG
-                __bss_stop = .;
-                _end = .;
-        }
-                                        /* Stabs debugging sections.    */
-        .stab 0 : { *(.stab) }
-        .stabstr 0 : { *(.stabstr) }
-        .stab.excl 0 : { *(.stab.excl) }
-        .stab.exclstr 0 : { *(.stab.exclstr) }
-        .stab.index 0 : { *(.stab.index) }
-        .stab.indexstr 0 : { *(.stab.indexstr) }
        .comment 0 : { *(.comment) }
 }
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 2fd88437348b..0b2ee953f164 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -1,5 +1,20 @@
 if ARCH_AT91
+config HAVE_AT91_DATAFLASH_CARD
+        bool
+config HAVE_NAND_ATMEL_BUSWIDTH_16
+        bool
+config HAVE_AT91_USART3
+        bool
+config HAVE_AT91_USART4
+        bool
+config HAVE_AT91_USART5
+        bool
 menu "Atmel AT91 System-on-Chip"
 choice
@@ -10,54 +25,69 @@ config ARCH_AT91RM9200
        select CPU_ARM920T
        select GENERIC_TIME
        select GENERIC_CLOCKEVENTS
+        select HAVE_AT91_USART3
 config ARCH_AT91SAM9260
        bool "AT91SAM9260 or AT91SAM9XE"
        select CPU_ARM926T
        select GENERIC_TIME
        select GENERIC_CLOCKEVENTS
+        select HAVE_AT91_USART3
+        select HAVE_AT91_USART4
+        select HAVE_AT91_USART5
 config ARCH_AT91SAM9261
        bool "AT91SAM9261"
        select CPU_ARM926T
        select GENERIC_TIME
        select GENERIC_CLOCKEVENTS
+        select HAVE_FB_ATMEL
 config ARCH_AT91SAM9G10
        bool "AT91SAM9G10"
        select CPU_ARM926T
        select GENERIC_TIME
        select GENERIC_CLOCKEVENTS
+        select HAVE_FB_ATMEL
 config ARCH_AT91SAM9263
        bool "AT91SAM9263"
        select CPU_ARM926T
        select GENERIC_TIME
        select GENERIC_CLOCKEVENTS
+        select HAVE_FB_ATMEL
 config ARCH_AT91SAM9RL
        bool "AT91SAM9RL"
        select CPU_ARM926T
        select GENERIC_TIME
        select GENERIC_CLOCKEVENTS
+        select HAVE_AT91_USART3
+        select HAVE_FB_ATMEL
 config ARCH_AT91SAM9G20
        bool "AT91SAM9G20"
        select CPU_ARM926T
        select GENERIC_TIME
        select GENERIC_CLOCKEVENTS
+        select HAVE_AT91_USART3
+        select HAVE_AT91_USART4
+        select HAVE_AT91_USART5
 config ARCH_AT91SAM9G45
        bool "AT91SAM9G45"
        select CPU_ARM926T
        select GENERIC_TIME
        select GENERIC_CLOCKEVENTS
+        select HAVE_AT91_USART3
+        select HAVE_FB_ATMEL
 config ARCH_AT91CAP9
        bool "AT91CAP9"
        select CPU_ARM926T
        select GENERIC_TIME
        select GENERIC_CLOCKEVENTS
+        select HAVE_FB_ATMEL
 config ARCH_AT91X40
        bool "AT91x40"
@@ -76,93 +106,88 @@ comment "AT91RM9200 Board Type"
 config MACH_ONEARM
        bool "Ajeco 1ARM Single Board Computer"
-        depends on ARCH_AT91RM9200
        help
          Select this if you are using Ajeco's 1ARM Single Board Computer.
          <http://www.ajeco.fi/products.htm>
 config ARCH_AT91RM9200DK
        bool "Atmel AT91RM9200-DK Development board"
-        depends on ARCH_AT91RM9200
+        select HAVE_AT91_DATAFLASH_CARD
        help
          Select this if you are using Atmel's AT91RM9200-DK Development board.
          (Discontinued)
 config MACH_AT91RM9200EK
        bool "Atmel AT91RM9200-EK Evaluation Kit"
-        depends on ARCH_AT91RM9200
+        select HAVE_AT91_DATAFLASH_CARD
        help
          Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit.
          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3507>
 config MACH_CSB337
        bool "Cogent CSB337"
-        depends on ARCH_AT91RM9200
        help
          Select this if you are using Cogent's CSB337 board.
          <http://www.cogcomp.com/csb_csb337.htm>
 config MACH_CSB637
        bool "Cogent CSB637"
-        depends on ARCH_AT91RM9200
        help
          Select this if you are using Cogent's CSB637 board.
          <http://www.cogcomp.com/csb_csb637.htm>
 config MACH_CARMEVA
        bool "Conitec ARM&EVA"
-        depends on ARCH_AT91RM9200
        help
          Select this if you are using Conitec's AT91RM9200-MCU-Module.
          <http://www.conitec.net/english/linuxboard.htm>
 config MACH_ATEB9200
        bool "Embest ATEB9200"
-        depends on ARCH_AT91RM9200
        help
          Select this if you are using Embest's ATEB9200 board.
          <http://www.embedinfo.com/english/product/ATEB9200.asp>
 config MACH_KB9200
        bool "KwikByte KB920x"
-        depends on ARCH_AT91RM9200
        help
          Select this if you are using KwikByte's KB920x board.
          <http://kwikbyte.com/KB9202_description_new.htm>
 config MACH_PICOTUX2XX
        bool "picotux 200"
-        depends on ARCH_AT91RM9200
        help
          Select this if you are using a picotux 200.
          <http://www.picotux.com/>
 config MACH_KAFA
        bool "Sperry-Sun KAFA board"
-        depends on ARCH_AT91RM9200
        help
          Select this if you are using Sperry-Sun's KAFA board.
 config MACH_ECBAT91
        bool "emQbit ECB_AT91 SBC"
-        depends on ARCH_AT91RM9200
+        select HAVE_AT91_DATAFLASH_CARD
        help
          Select this if you are using emQbit's ECB_AT91 board.
          <http://wiki.emqbit.com/free-ecb-at91>
 config MACH_YL9200
        bool "ucDragon YL-9200"
-        depends on ARCH_AT91RM9200
        help
          Select this if you are using the ucDragon YL-9200 board.
 config MACH_CPUAT91
        bool "Eukrea CPUAT91"
-        depends on ARCH_AT91RM9200
        help
          Select this if you are using the Eukrea Electromatique's
          CPUAT91 board <http://www.eukrea.com/>.
+config MACH_ECO920
+        bool "eco920"
+        help
+          Select this if you are using the eco920 board
 endif
 # ----------------------------------------------------------
@@ -173,7 +198,6 @@ comment "AT91SAM9260 Variants"
 config ARCH_AT91SAM9260_SAM9XE
        bool "AT91SAM9XE"
-        depends on ARCH_AT91SAM9260
        help
          Select this if you are using Atmel's AT91SAM9XE System-on-Chip.
          They are basically AT91SAM9260s with various sizes of embedded Flash.
@@ -182,28 +206,27 @@ comment "AT91SAM9260 / AT91SAM9XE Board Type"
 config MACH_AT91SAM9260EK
        bool "Atmel AT91SAM9260-EK / AT91SAM9XE Evaluation Kit"
-        depends on ARCH_AT91SAM9260
+        select HAVE_AT91_DATAFLASH_CARD
+        select HAVE_NAND_ATMEL_BUSWIDTH_16
        help
          Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit
          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933>
 config MACH_CAM60
        bool "KwikByte KB9260 (CAM60) board"
-        depends on ARCH_AT91SAM9260
        help
          Select this if you are using KwikByte's KB9260 (CAM60) board based on the Atmel AT91SAM9260.
          <http://www.kwikbyte.com/KB9260.html>
 config MACH_SAM9_L9260
        bool "Olimex SAM9-L9260 board"
-        depends on ARCH_AT91SAM9260
+        select HAVE_AT91_DATAFLASH_CARD
        help
          Select this if you are using Olimex's SAM9-L9260 board based on the Atmel AT91SAM9260.
          <http://www.olimex.com/dev/sam9-L9260.html>
 config MACH_AFEB9260
        bool "Custom afeb9260 board v1"
-        depends on ARCH_AT91SAM9260
        help
          Select this if you are using custom afeb9260 board based on
          open hardware design. Select this for revision 1 of the board.
@@ -212,21 +235,18 @@ config MACH_AFEB9260
 config MACH_USB_A9260
        bool "CALAO USB-A9260"
-        depends on ARCH_AT91SAM9260
        help
          Select this if you are using a Calao Systems USB-A9260.
          <http://www.calao-systems.com>
 config MACH_QIL_A9260
        bool "CALAO QIL-A9260 board"
-        depends on ARCH_AT91SAM9260
        help
          Select this if you are using a Calao Systems QIL-A9260 Board.
          <http://www.calao-systems.com>
 config MACH_CPU9260
        bool "Eukrea CPU9260 board"
-        depends on ARCH_AT91SAM9260
        help
          Select this if you are using a Eukrea Electromatique's
          CPU9260 Board <http://www.eukrea.com/>
@@ -241,7 +261,8 @@ comment "AT91SAM9261 Board Type"
 config MACH_AT91SAM9261EK
        bool "Atmel AT91SAM9261-EK Evaluation Kit"
-        depends on ARCH_AT91SAM9261
+        select HAVE_AT91_DATAFLASH_CARD
+        select HAVE_NAND_ATMEL_BUSWIDTH_16
        help
          Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit.
          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820>
@@ -256,7 +277,8 @@ comment "AT91SAM9G10 Board Type"
 config MACH_AT91SAM9G10EK
        bool "Atmel AT91SAM9G10-EK Evaluation Kit"
-        depends on ARCH_AT91SAM9G10
+        select HAVE_AT91_DATAFLASH_CARD
+        select HAVE_NAND_ATMEL_BUSWIDTH_16
        help
          Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit.
          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588>
@@ -271,21 +293,21 @@ comment "AT91SAM9263 Board Type"
 config MACH_AT91SAM9263EK
        bool "Atmel AT91SAM9263-EK Evaluation Kit"
-        depends on ARCH_AT91SAM9263
+        select HAVE_AT91_DATAFLASH_CARD
+        select HAVE_NAND_ATMEL_BUSWIDTH_16
        help
          Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit.
          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057>
 config MACH_USB_A9263
        bool "CALAO USB-A9263"
-        depends on ARCH_AT91SAM9263
        help
          Select this if you are using a Calao Systems USB-A9263.
          <http://www.calao-systems.com>
 config MACH_NEOCORE926
        bool "Adeneo NEOCORE926"
-        depends on ARCH_AT91SAM9263
+        select HAVE_AT91_DATAFLASH_CARD
        help
          Select this if you are using the Adeneo Neocore 926 board.
@@ -299,7 +321,6 @@ comment "AT91SAM9RL Board Type"
 config MACH_AT91SAM9RLEK
        bool "Atmel AT91SAM9RL-EK Evaluation Kit"
-        depends on ARCH_AT91SAM9RL
        help
          Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit.
@@ -313,14 +334,15 @@ comment "AT91SAM9G20 Board Type"
 config MACH_AT91SAM9G20EK
        bool "Atmel AT91SAM9G20-EK Evaluation Kit"
-        depends on ARCH_AT91SAM9G20
+        select HAVE_AT91_DATAFLASH_CARD
+        select HAVE_NAND_ATMEL_BUSWIDTH_16
        help
          Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit
          that embeds only one SD/MMC slot.
 config MACH_AT91SAM9G20EK_2MMC
        bool "Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots"
-        depends on ARCH_AT91SAM9G20
+        select HAVE_NAND_ATMEL_BUSWIDTH_16
        help
          Select this if you are using an Atmel AT91SAM9G20-EK Evaluation Kit
          with 2 SD/MMC Slots. This is the case for AT91SAM9G20-EK rev. C and
@@ -328,7 +350,6 @@ config MACH_AT91SAM9G20EK_2MMC
 config MACH_CPU9G20
        bool "Eukrea CPU9G20 board"
-        depends on ARCH_AT91SAM9G20
        help
          Select this if you are using a Eukrea Electromatique's
          CPU9G20 Board <http://www.eukrea.com/>
@@ -343,7 +364,7 @@ comment "AT91SAM9G45 Board Type"
 config MACH_AT91SAM9G45EKES
        bool "Atmel AT91SAM9G45-EKES Evaluation Kit"
-        depends on ARCH_AT91SAM9G45
+        select HAVE_NAND_ATMEL_BUSWIDTH_16
        help
          Select this if you are using Atmel's AT91SAM9G45-EKES Evaluation Kit.
          "ES" at the end of the name means that this board is an
@@ -359,7 +380,8 @@ comment "AT91CAP9 Board Type"
 config MACH_AT91CAP9ADK
        bool "Atmel AT91CAP9A-DK Evaluation Kit"
-        depends on ARCH_AT91CAP9
+        select HAVE_AT91_DATAFLASH_CARD
+        select HAVE_NAND_ATMEL_BUSWIDTH_16
        help
          Select this if you are using Atmel's AT91CAP9A-DK Evaluation Kit.
          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4138>
@@ -388,13 +410,13 @@ comment "AT91 Board Options"
 config MTD_AT91_DATAFLASH_CARD
        bool "Enable DataFlash Card support"
-        depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9G10EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_ECBAT91 || MACH_SAM9_L9260 || MACH_AT91CAP9ADK || MACH_NEOCORE926)
+        depends on HAVE_AT91_DATAFLASH_CARD
        help
          Enable support for the DataFlash card.
 config MTD_NAND_ATMEL_BUSWIDTH_16
        bool "Enable 16-bit data bus interface to NAND flash"
-        depends on (MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9G10EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_AT91SAM9G20EK_2MMC || MACH_AT91SAM9G45EKES || MACH_AT91CAP9ADK)
+        depends on HAVE_NAND_ATMEL_BUSWIDTH_16
        help
          On AT91SAM926x boards both types of NAND flash can be present
          (8 and 16 bit data bus width).
@@ -456,15 +478,15 @@ config AT91_EARLY_USART2
 config AT91_EARLY_USART3
        bool "USART3"
-        depends on (ARCH_AT91RM9200 || ARCH_AT91SAM9RL || ARCH_AT91SAM9260 || ARCH_AT91SAM9G20 || ARCH_AT91SAM9G45)
+        depends on HAVE_AT91_USART3
 config AT91_EARLY_USART4
        bool "USART4"
-        depends on ARCH_AT91SAM9260 || ARCH_AT91SAM9G20
+        depends on HAVE_AT91_USART4
 config AT91_EARLY_USART5
        bool "USART5"
-        depends on ARCH_AT91SAM9260 || ARCH_AT91SAM9G20
+        depends on HAVE_AT91_USART5
 endchoice
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index ada440aab0c5..709fbad4a3ee 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_MACH_PICOTUX2XX)	+= board-picotux200.o
 obj-$(CONFIG_MACH_ECBAT91)      += board-ecbat91.o
 obj-$(CONFIG_MACH_YL9200)       += board-yl-9200.o
 obj-$(CONFIG_MACH_CPUAT91)      += board-cpuat91.o
+obj-$(CONFIG_MACH_ECO920)       += board-eco920.o
 # AT91SAM9260 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
@@ -77,6 +78,7 @@ obj-y				+= leds.o
 # Power Management
 obj-$(CONFIG_PM)                += pm.o
 obj-$(CONFIG_AT91_SLOW_CLOCK)   += pm_slowclock.o
+obj-$(CONFIG_CPU_IDLE)  += cpuidle.o
 ifeq ($(CONFIG_PM_DEBUG),y)
 CFLAGS_pm.o += -DDEBUG
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index 332b784050b2..a57af3e99c7c 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -131,6 +131,62 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
 /* --------------------------------------------------------------------
+ *  USB Host HS (EHCI)
+ *  Needs an OHCI host for low and full speed management
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
+static u64 ehci_dmamask = DMA_BIT_MASK(32);
+static struct at91_usbh_data usbh_ehci_data;
+static struct resource usbh_ehci_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_EHCI_BASE,
+                .end    = AT91SAM9G45_EHCI_BASE + SZ_1M - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_UHPHS,
+                .end    = AT91SAM9G45_ID_UHPHS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device at91_usbh_ehci_device = {
+        .name           = "atmel-ehci",
+        .id             = -1,
+        .dev            = {
+                                .dma_mask               = &ehci_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &usbh_ehci_data,
+        },
+        .resource       = usbh_ehci_resources,
+        .num_resources  = ARRAY_SIZE(usbh_ehci_resources),
+};
+void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data)
+{
+        int i;
+        if (!data)
+                return;
+        /* Enable VBus control for UHP ports */
+        for (i = 0; i < data->ports; i++) {
+                if (data->vbus_pin[i])
+                        at91_set_gpio_output(data->vbus_pin[i], 0);
+        }
+        usbh_ehci_data = *data;
+        at91_clock_associate("uhphs_clk", &at91_usbh_ehci_device.dev, "ehci_clk");
+        platform_device_register(&at91_usbh_ehci_device);
+}
+#else
+void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) {}
+#endif
+/* --------------------------------------------------------------------
 *  USB HS Device (Gadget)
 * -------------------------------------------------------------------- */
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
new file mode 100644
index 000000000000..295a96609e71
--- /dev/null
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -0,0 +1,158 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/board.h>
+#include <mach/at91rm9200_mc.h>
+#include "generic.h"
+static void __init eco920_map_io(void)
+{
+        at91rm9200_initialize(18432000, AT91RM9200_PQFP);
+        /* Setup the LEDs */
+        at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1);
+        /* DBGU on ttyS0. (Rx & Tx only */
+        at91_register_uart(0, 0, 0);
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
+}
+static void __init eco920_init_irq(void)
+{
+        at91rm9200_init_interrupts(NULL);
+}
+static struct at91_eth_data __initdata eco920_eth_data = {
+        .phy_irq_pin    = AT91_PIN_PC2,
+        .is_rmii        = 1,
+};
+static struct at91_usbh_data __initdata eco920_usbh_data = {
+        .ports          = 1,
+};
+static struct at91_udc_data __initdata eco920_udc_data = {
+        .vbus_pin       = AT91_PIN_PB12,
+        .pullup_pin     = AT91_PIN_PB13,
+};
+static struct at91_mmc_data __initdata eco920_mmc_data = {
+        .slot_b         = 0,
+        .wire4          = 0,
+};
+static struct physmap_flash_data eco920_flash_data = {
+        .width  = 2,
+};
+static struct resource eco920_flash_resource = {
+        .start          = 0x11000000,
+        .end            = 0x11ffffff,
+        .flags          = IORESOURCE_MEM,
+};
+static struct platform_device eco920_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &eco920_flash_data,
+        },
+        .resource       = &eco920_flash_resource,
+        .num_resources  = 1,
+};
+static struct resource at91_beeper_resources[] = {
+        [0] = {
+                .start          = AT91RM9200_BASE_TC3,
+                .end            = AT91RM9200_BASE_TC3 + 0x39,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+static struct platform_device at91_beeper = {
+        .name           = "at91_beeper",
+        .id             = 0,
+        .resource       = at91_beeper_resources,
+        .num_resources  = ARRAY_SIZE(at91_beeper_resources),
+};
+static struct spi_board_info eco920_spi_devices[] = {
+        {       /* CAN controller */
+                .modalias       = "tlv5638",
+                .chip_select    = 3,
+                .max_speed_hz   = 20 * 1000 * 1000,
+                .mode           = SPI_CPHA,
+        },
+};
+static void __init eco920_board_init(void)
+{
+        at91_add_device_serial();
+        at91_add_device_eth(&eco920_eth_data);
+        at91_add_device_usbh(&eco920_usbh_data);
+        at91_add_device_udc(&eco920_udc_data);
+        at91_add_device_mmc(0, &eco920_mmc_data);
+        platform_device_register(&eco920_flash);
+        at91_sys_write(AT91_SMC_CSR(7), AT91_SMC_RWHOLD_(1)
+                                | AT91_SMC_RWSETUP_(1)
+                                | AT91_SMC_DBW_8
+                                | AT91_SMC_WSEN
+                                | AT91_SMC_NWS_(15));
+        at91_set_A_periph(AT91_PIN_PC6, 1);
+        at91_set_gpio_input(AT91_PIN_PA23, 0);
+        at91_set_deglitch(AT91_PIN_PA23, 1);
+/* Initialization of the Static Memory Controller for Chip Select 3 */
+        at91_sys_write(AT91_SMC_CSR(3),
+                AT91_SMC_DBW_16  |      /* 16 bit */
+                AT91_SMC_WSEN    |
+                AT91_SMC_NWS_(5) |      /* wait states */
+                AT91_SMC_TDF_(1)        /* float time */
+        );
+        at91_clock_associate("tc3_clk", &at91_beeper.dev, "at91_beeper");
+        at91_set_B_periph(AT91_PIN_PB6, 0);
+        platform_device_register(&at91_beeper);
+        at91_add_device_spi(eco920_spi_devices, ARRAY_SIZE(eco920_spi_devices));
+}
+MACHINE_START(ECO920, "eco920")
+        /* Maintainer: Sascha Hauer */
+        .phys_io        = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91rm9200_timer,
+        .map_io         = eco920_map_io,
+        .init_irq       = eco920_init_irq,
+        .init_machine   = eco920_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index 64c3843f323d..1cf4d8681078 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -366,6 +366,7 @@ static void __init ek_board_init(void)
        at91_add_device_serial();
        /* USB HS Host */
        at91_add_device_usbh_ohci(&ek_usbh_hs_data);
+        at91_add_device_usbh_ehci(&ek_usbh_hs_data);
        /* USB HS Device */
        at91_add_device_usba(&ek_usba_udc_data);
        /* SPI */
diff --git a/arch/arm/mach-at91/cpuidle.c b/arch/arm/mach-at91/cpuidle.c
new file mode 100644
index 000000000000..1cfeac1483d6
--- /dev/null
+++ b/arch/arm/mach-at91/cpuidle.c
@@ -0,0 +1,94 @@
+/*
+ * based on arch/arm/mach-kirkwood/cpuidle.c
+ *
+ * CPU idle support for AT91 SoC
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * The cpu idle uses wait-for-interrupt and RAM self refresh in order
+ * to implement two idle states -
+ * #1 wait-for-interrupt
+ * #2 wait-for-interrupt and RAM self refresh
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/cpuidle.h>
+#include <asm/proc-fns.h>
+#include <linux/io.h>
+#include "pm.h"
+#define AT91_MAX_STATES 2
+static DEFINE_PER_CPU(struct cpuidle_device, at91_cpuidle_device);
+static struct cpuidle_driver at91_idle_driver = {
+        .name =         "at91_idle",
+        .owner =        THIS_MODULE,
+};
+/* Actual code that puts the SoC in different idle states */
+static int at91_enter_idle(struct cpuidle_device *dev,
+                               struct cpuidle_state *state)
+{
+        struct timeval before, after;
+        int idle_time;
+        u32 saved_lpr;
+        local_irq_disable();
+        do_gettimeofday(&before);
+        if (state == &dev->states[0])
+                /* Wait for interrupt state */
+                cpu_do_idle();
+        else if (state == &dev->states[1]) {
+                asm("b 1f; .align 5; 1:");
+                asm("mcr p15, 0, r0, c7, c10, 4");      /* drain write buffer */
+                saved_lpr = sdram_selfrefresh_enable();
+                cpu_do_idle();
+                sdram_selfrefresh_disable(saved_lpr);
+        }
+        do_gettimeofday(&after);
+        local_irq_enable();
+        idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
+                        (after.tv_usec - before.tv_usec);
+        return idle_time;
+}
+/* Initialize CPU idle by registering the idle states */
+static int at91_init_cpuidle(void)
+{
+        struct cpuidle_device *device;
+        cpuidle_register_driver(&at91_idle_driver);
+        device = &per_cpu(at91_cpuidle_device, smp_processor_id());
+        device->state_count = AT91_MAX_STATES;
+        /* Wait for interrupt state */
+        device->states[0].enter = at91_enter_idle;
+        device->states[0].exit_latency = 1;
+        device->states[0].target_residency = 10000;
+        device->states[0].flags = CPUIDLE_FLAG_TIME_VALID;
+        strcpy(device->states[0].name, "WFI");
+        strcpy(device->states[0].desc, "Wait for interrupt");
+        /* Wait for interrupt and RAM self refresh state */
+        device->states[1].enter = at91_enter_idle;
+        device->states[1].exit_latency = 10;
+        device->states[1].target_residency = 10000;
+        device->states[1].flags = CPUIDLE_FLAG_TIME_VALID;
+        strcpy(device->states[1].name, "RAM_SR");
+        strcpy(device->states[1].desc, "WFI and RAM Self Refresh");
+        if (cpuidle_register_device(device)) {
+                printk(KERN_ERR "at91_init_cpuidle: Failed registering\n");
+                return -EIO;
+        }
+        return 0;
+}
+device_initcall(at91_init_cpuidle);
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index 2f4fcedc02ba..2295d80dd893 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -98,6 +98,7 @@ struct at91_usbh_data {
 };
 extern void __init at91_add_device_usbh(struct at91_usbh_data *data);
 extern void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data);
+extern void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data);
 /* NAND / SmartMedia */
 struct atmel_nand_data {
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 4028724d490d..615668986480 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -29,62 +29,7 @@
 #include <mach/cpu.h>
 #include "generic.h"
+#include "pm.h"
-#ifdef CONFIG_ARCH_AT91RM9200
-#include <mach/at91rm9200_mc.h>
-/*
- * The AT91RM9200 goes into self-refresh mode with this command, and will
- * terminate self-refresh automatically on the next SDRAM access.
- */
-#define sdram_selfrefresh_enable()      at91_sys_write(AT91_SDRAMC_SRR, 1)
-#define sdram_selfrefresh_disable()     do {} while (0)
-#elif defined(CONFIG_ARCH_AT91CAP9)
-#include <mach/at91cap9_ddrsdr.h>
-static u32 saved_lpr;
-static inline void sdram_selfrefresh_enable(void)
-{
-        u32 lpr;
-        saved_lpr = at91_sys_read(AT91_DDRSDRC_LPR);
-        lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
-        at91_sys_write(AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
-}
-#define sdram_selfrefresh_disable()     at91_sys_write(AT91_DDRSDRC_LPR, saved_lpr)
-#else
-#include <mach/at91sam9_sdramc.h>
-#ifdef CONFIG_ARCH_AT91SAM9263
-/*
- * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
- * handle those cases both here and in the Suspend-To-RAM support.
- */
-#define AT91_SDRAMC     AT91_SDRAMC0
-#warning Assuming EB1 SDRAM controller is *NOT* used
-#endif
-static u32 saved_lpr;
-static inline void sdram_selfrefresh_enable(void)
-{
-        u32 lpr;
-        saved_lpr = at91_sys_read(AT91_SDRAMC_LPR);
-        lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
-        at91_sys_write(AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
-}
-#define sdram_selfrefresh_disable()     at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
-#endif
 /*
 * Show the reason for the previous system reset.
@@ -260,6 +205,7 @@ extern u32 at91_slow_clock_sz;
 static int at91_pm_enter(suspend_state_t state)
 {
+        u32 saved_lpr;
        at91_gpio_suspend();
        at91_irq_suspend();
@@ -315,9 +261,9 @@ static int at91_pm_enter(suspend_state_t state)
                         */
                        asm("b 1f; .align 5; 1:");
                        asm("mcr p15, 0, r0, c7, c10, 4");      /* drain write buffer */
-                        sdram_selfrefresh_enable();
+                        saved_lpr = sdram_selfrefresh_enable();
                        asm("mcr p15, 0, r0, c7, c0, 4");       /* wait for interrupt */
-                        sdram_selfrefresh_disable();
+                        sdram_selfrefresh_disable(saved_lpr);
                        break;
                case PM_SUSPEND_ON:
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
new file mode 100644
index 000000000000..08322c44df1a
--- /dev/null
+++ b/arch/arm/mach-at91/pm.h
@@ -0,0 +1,67 @@
+#ifdef CONFIG_ARCH_AT91RM9200
+#include <mach/at91rm9200_mc.h>
+/*
+ * The AT91RM9200 goes into self-refresh mode with this command, and will
+ * terminate self-refresh automatically on the next SDRAM access.
+ *
+ * Self-refresh mode is exited as soon as a memory access is made, but we don't
+ * know for sure when that happens. However, we need to restore the low-power
+ * mode if it was enabled before going idle. Restoring low-power mode while
+ * still in self-refresh is "not recommended", but seems to work.
+ */
+static inline u32 sdram_selfrefresh_enable(void)
+{
+        u32 saved_lpr = at91_sys_read(AT91_SDRAMC_LPR);
+        at91_sys_write(AT91_SDRAMC_LPR, 0);
+        at91_sys_write(AT91_SDRAMC_SRR, 1);
+        return saved_lpr;
+}
+#define sdram_selfrefresh_disable(saved_lpr)    at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
+#elif defined(CONFIG_ARCH_AT91CAP9)
+#include <mach/at91cap9_ddrsdr.h>
+static inline u32 sdram_selfrefresh_enable(void)
+{
+        u32 saved_lpr, lpr;
+        saved_lpr = at91_sys_read(AT91_DDRSDRC_LPR);
+        lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
+        at91_sys_write(AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
+        return saved_lpr;
+}
+#define sdram_selfrefresh_disable(saved_lpr)    at91_sys_write(AT91_DDRSDRC_LPR, saved_lpr)
+#else
+#include <mach/at91sam9_sdramc.h>
+#ifdef CONFIG_ARCH_AT91SAM9263
+/*
+ * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
+ * handle those cases both here and in the Suspend-To-RAM support.
+ */
+#define AT91_SDRAMC     AT91_SDRAMC0
+#warning Assuming EB1 SDRAM controller is *NOT* used
+#endif
+static inline u32 sdram_selfrefresh_enable(void)
+{
+        u32 saved_lpr, lpr;
+        saved_lpr = at91_sys_read(AT91_SDRAMC_LPR);
+        lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
+        at91_sys_write(AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
+        return saved_lpr;
+}
+#define sdram_selfrefresh_disable(saved_lpr)    at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
+#endif
diff --git a/arch/arm/mach-bcmring/include/mach/io.h b/arch/arm/mach-bcmring/include/mach/io.h
index 4db0eff90357..dae5e9b166ea 100644
--- a/arch/arm/mach-bcmring/include/mach/io.h
+++ b/arch/arm/mach-bcmring/include/mach/io.h
@@ -23,34 +23,11 @@
 #define IO_SPACE_LIMIT 0xffffffff
-#define __io(a)         ((void __iomem *)HW_IO_PHYS_TO_VIRT(a))
+/*
+ * We don't actually have real ISA nor PCI buses, but there is so many
-/* Do not enable mem_pci for a big endian arm architecture or unexpected byteswaps will */
+ * drivers out there that might just work if we fake them...
-/* happen in readw/writew etc. */
+ */
+#define __io(a)         __typesafe_io(a)
-#define readb(c)        __raw_readb(c)
+#define __mem_pci(a)    (a)
-#define readw(c)        __raw_readw(c)
-#define readl(c)        __raw_readl(c)
-#define readb_relaxed(addr) readb(addr)
-#define readw_relaxed(addr) readw(addr)
-#define readl_relaxed(addr) readl(addr)
-#define readsb(p, d, l)   __raw_readsb(p, d, l)
-#define readsw(p, d, l)   __raw_readsw(p, d, l)
-#define readsl(p, d, l)   __raw_readsl(p, d, l)
-#define writeb(v, c)     __raw_writeb(v, c)
-#define writew(v, c)     __raw_writew(v, c)
-#define writel(v, c)     __raw_writel(v, c)
-#define writesb(p, d, l)  __raw_writesb(p, d, l)
-#define writesw(p, d, l)  __raw_writesw(p, d, l)
-#define writesl(p, d, l)  __raw_writesl(p, d, l)
-#define memset_io(c, v, l)    _memset_io((c), (v), (l))
-#define memcpy_fromio(a, c, l)    _memcpy_fromio((a), (c), (l))
-#define memcpy_toio(c, a, l)  _memcpy_toio((c), (a), (l))
-#define eth_io_copy_and_sum(s, c, l, b) eth_copy_and_sum((s), (c), (l), (b))
 #endif
diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig
new file mode 100644
index 000000000000..3b9a32ace909
--- /dev/null
+++ b/arch/arm/mach-dove/Kconfig
@@ -0,0 +1,14 @@
+if ARCH_DOVE
+menu "Marvell Dove Implementations"
+config MACH_DOVE_DB
+        bool "Marvell DB-MV88AP510 Development Board"
+        select I2C_BOARDINFO
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell DB-MV88AP510 Development Board.
+endmenu
+endif
diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile
new file mode 100644
index 000000000000..7ab3be53f642
--- /dev/null
+++ b/arch/arm/mach-dove/Makefile
@@ -0,0 +1,3 @@
+obj-y                           += common.o addr-map.o irq.o pcie.o
+obj-$(CONFIG_MACH_DOVE_DB)      += dove-db-setup.o
diff --git a/arch/arm/mach-dove/Makefile.boot b/arch/arm/mach-dove/Makefile.boot
new file mode 100644
index 000000000000..67039c3e0c48
--- /dev/null
+++ b/arch/arm/mach-dove/Makefile.boot
@@ -0,0 +1,3 @@
+   zreladdr-y   := 0x00008000
+params_phys-y   := 0x00000100
+initrd_phys-y   := 0x00800000
diff --git a/arch/arm/mach-dove/addr-map.c b/arch/arm/mach-dove/addr-map.c
new file mode 100644
index 000000000000..00be4fc26dd7
--- /dev/null
+++ b/arch/arm/mach-dove/addr-map.c
@@ -0,0 +1,149 @@
+/*
+ * arch/arm/mach-dove/addr-map.c
+ *
+ * Address map functions for Marvell Dove 88AP510 SoC
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mbus.h>
+#include <linux/io.h>
+#include <asm/mach/arch.h>
+#include <asm/setup.h>
+#include "common.h"
+/*
+ * Generic Address Decode Windows bit settings
+ */
+#define TARGET_DDR              0x0
+#define TARGET_BOOTROM          0x1
+#define TARGET_CESA             0x3
+#define TARGET_PCIE0            0x4
+#define TARGET_PCIE1            0x8
+#define TARGET_SCRATCHPAD       0xd
+#define ATTR_CESA               0x01
+#define ATTR_BOOTROM            0xfd
+#define ATTR_DEV_SPI0_ROM       0xfe
+#define ATTR_DEV_SPI1_ROM       0xfb
+#define ATTR_PCIE_IO            0xe0
+#define ATTR_PCIE_MEM           0xe8
+#define ATTR_SCRATCHPAD         0x0
+/*
+ * CPU Address Decode Windows registers
+ */
+#define WIN_CTRL(n)     (BRIDGE_VIRT_BASE + ((n) << 4) + 0x0)
+#define WIN_BASE(n)     (BRIDGE_VIRT_BASE + ((n) << 4) + 0x4)
+#define WIN_REMAP_LO(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x8)
+#define WIN_REMAP_HI(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0xc)
+struct mbus_dram_target_info dove_mbus_dram_info;
+static inline void __iomem *ddr_map_sc(int i)
+{
+        return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4));
+}
+static int cpu_win_can_remap(int win)
+{
+        if (win < 4)
+                return 1;
+        return 0;
+}
+static void __init setup_cpu_win(int win, u32 base, u32 size,
+                                 u8 target, u8 attr, int remap)
+{
+        u32 ctrl;
+        base &= 0xffff0000;
+        ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
+        writel(base, WIN_BASE(win));
+        writel(ctrl, WIN_CTRL(win));
+        if (cpu_win_can_remap(win)) {
+                if (remap < 0)
+                        remap = base;
+                writel(remap & 0xffff0000, WIN_REMAP_LO(win));
+                writel(0, WIN_REMAP_HI(win));
+        }
+}
+void __init dove_setup_cpu_mbus(void)
+{
+        int i;
+        int cs;
+        /*
+         * First, disable and clear windows.
+         */
+        for (i = 0; i < 8; i++) {
+                writel(0, WIN_BASE(i));
+                writel(0, WIN_CTRL(i));
+                if (cpu_win_can_remap(i)) {
+                        writel(0, WIN_REMAP_LO(i));
+                        writel(0, WIN_REMAP_HI(i));
+                }
+        }
+        /*
+         * Setup windows for PCIe IO+MEM space.
+         */
+        setup_cpu_win(0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE,
+                      TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE);
+        setup_cpu_win(1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE,
+                      TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE);
+        setup_cpu_win(2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE,
+                      TARGET_PCIE0, ATTR_PCIE_MEM, -1);
+        setup_cpu_win(3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE,
+                      TARGET_PCIE1, ATTR_PCIE_MEM, -1);
+        /*
+         * Setup window for CESA engine.
+         */
+        setup_cpu_win(4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE,
+                      TARGET_CESA, ATTR_CESA, -1);
+        /*
+         * Setup the Window to the BootROM for Standby and Sleep Resume
+         */
+        setup_cpu_win(5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE,
+                      TARGET_BOOTROM, ATTR_BOOTROM, -1);
+        /*
+         * Setup the Window to the PMU Scratch Pad space
+         */
+        setup_cpu_win(6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE,
+                      TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1);
+        /*
+         * Setup MBUS dram target info.
+         */
+        dove_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
+        for (i = 0, cs = 0; i < 2; i++) {
+                u32 map = readl(ddr_map_sc(i));
+                /*
+                 * Chip select enabled?
+                 */
+                if (map & 1) {
+                        struct mbus_dram_window *w;
+                        w = &dove_mbus_dram_info.cs[cs++];
+                        w->cs_index = i;
+                        w->mbus_attr = 0; /* CS address decoding done inside */
+                                          /* the DDR controller, no need to  */
+                                          /* provide attributes */
+                        w->base = map & 0xff800000;
+                        w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
+                }
+        }
+        dove_mbus_dram_info.num_cs = cs;
+}
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
new file mode 100644
index 000000000000..806972a68c87
--- /dev/null
+++ b/arch/arm/mach-dove/common.c
@@ -0,0 +1,781 @@
+/*
+ * arch/arm/mach-dove/common.c
+ *
+ * Core functions for Marvell Dove 88AP510 System On Chip
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/serial_8250.h>
+#include <linux/clk.h>
+#include <linux/mbus.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/mv643xx_i2c.h>
+#include <linux/ata_platform.h>
+#include <linux/spi/orion_spi.h>
+#include <linux/gpio.h>
+#include <asm/page.h>
+#include <asm/setup.h>
+#include <asm/timex.h>
+#include <asm/hardware/cache-tauros2.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <asm/mach/pci.h>
+#include <mach/dove.h>
+#include <mach/bridge-regs.h>
+#include <asm/mach/arch.h>
+#include <linux/irq.h>
+#include <plat/mv_xor.h>
+#include <plat/ehci-orion.h>
+#include <plat/time.h>
+#include "common.h"
+/*****************************************************************************
+ * I/O Address Mapping
+ ****************************************************************************/
+static struct map_desc dove_io_desc[] __initdata = {
+        {
+                .virtual        = DOVE_SB_REGS_VIRT_BASE,
+                .pfn            = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
+                .length         = DOVE_SB_REGS_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = DOVE_NB_REGS_VIRT_BASE,
+                .pfn            = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
+                .length         = DOVE_NB_REGS_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = DOVE_PCIE0_IO_VIRT_BASE,
+                .pfn            = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE),
+                .length         = DOVE_PCIE0_IO_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = DOVE_PCIE1_IO_VIRT_BASE,
+                .pfn            = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE),
+                .length         = DOVE_PCIE1_IO_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+void __init dove_map_io(void)
+{
+        iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
+}
+/*****************************************************************************
+ * EHCI
+ ****************************************************************************/
+static struct orion_ehci_data dove_ehci_data = {
+        .dram           = &dove_mbus_dram_info,
+        .phy_version    = EHCI_PHY_NA,
+};
+static u64 ehci_dmamask = DMA_BIT_MASK(32);
+/*****************************************************************************
+ * EHCI0
+ ****************************************************************************/
+static struct resource dove_ehci0_resources[] = {
+        {
+                .start  = DOVE_USB0_PHYS_BASE,
+                .end    = DOVE_USB0_PHYS_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_DOVE_USB0,
+                .end    = IRQ_DOVE_USB0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device dove_ehci0 = {
+        .name           = "orion-ehci",
+        .id             = 0,
+        .dev            = {
+                .dma_mask               = &ehci_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data          = &dove_ehci_data,
+        },
+        .resource       = dove_ehci0_resources,
+        .num_resources  = ARRAY_SIZE(dove_ehci0_resources),
+};
+void __init dove_ehci0_init(void)
+{
+        platform_device_register(&dove_ehci0);
+}
+/*****************************************************************************
+ * EHCI1
+ ****************************************************************************/
+static struct resource dove_ehci1_resources[] = {
+        {
+                .start  = DOVE_USB1_PHYS_BASE,
+                .end    = DOVE_USB1_PHYS_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_DOVE_USB1,
+                .end    = IRQ_DOVE_USB1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device dove_ehci1 = {
+        .name           = "orion-ehci",
+        .id             = 1,
+        .dev            = {
+                .dma_mask               = &ehci_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data          = &dove_ehci_data,
+        },
+        .resource       = dove_ehci1_resources,
+        .num_resources  = ARRAY_SIZE(dove_ehci1_resources),
+};
+void __init dove_ehci1_init(void)
+{
+        platform_device_register(&dove_ehci1);
+}
+/*****************************************************************************
+ * GE00
+ ****************************************************************************/
+struct mv643xx_eth_shared_platform_data dove_ge00_shared_data = {
+        .t_clk          = 0,
+        .dram           = &dove_mbus_dram_info,
+};
+static struct resource dove_ge00_shared_resources[] = {
+        {
+                .name   = "ge00 base",
+                .start  = DOVE_GE00_PHYS_BASE + 0x2000,
+                .end    = DOVE_GE00_PHYS_BASE + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+static struct platform_device dove_ge00_shared = {
+        .name           = MV643XX_ETH_SHARED_NAME,
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &dove_ge00_shared_data,
+        },
+        .num_resources  = 1,
+        .resource       = dove_ge00_shared_resources,
+};
+static struct resource dove_ge00_resources[] = {
+        {
+                .name   = "ge00 irq",
+                .start  = IRQ_DOVE_GE00_SUM,
+                .end    = IRQ_DOVE_GE00_SUM,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device dove_ge00 = {
+        .name           = MV643XX_ETH_NAME,
+        .id             = 0,
+        .num_resources  = 1,
+        .resource       = dove_ge00_resources,
+        .dev            = {
+                .coherent_dma_mask      = 0xffffffff,
+        },
+};
+void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
+{
+        eth_data->shared = &dove_ge00_shared;
+        dove_ge00.dev.platform_data = eth_data;
+        platform_device_register(&dove_ge00_shared);
+        platform_device_register(&dove_ge00);
+}
+/*****************************************************************************
+ * SoC RTC
+ ****************************************************************************/
+static struct resource dove_rtc_resource[] = {
+        {
+                .start  = DOVE_RTC_PHYS_BASE,
+                .end    = DOVE_RTC_PHYS_BASE + 32 - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_DOVE_RTC,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+void __init dove_rtc_init(void)
+{
+        platform_device_register_simple("rtc-mv", -1, dove_rtc_resource, 2);
+}
+/*****************************************************************************
+ * SATA
+ ****************************************************************************/
+static struct resource dove_sata_resources[] = {
+        {
+                .name   = "sata base",
+                .start  = DOVE_SATA_PHYS_BASE,
+                .end    = DOVE_SATA_PHYS_BASE + 0x5000 - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "sata irq",
+                .start  = IRQ_DOVE_SATA,
+                .end    = IRQ_DOVE_SATA,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device dove_sata = {
+        .name           = "sata_mv",
+        .id             = 0,
+        .dev            = {
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .num_resources  = ARRAY_SIZE(dove_sata_resources),
+        .resource       = dove_sata_resources,
+};
+void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
+{
+        sata_data->dram = &dove_mbus_dram_info;
+        dove_sata.dev.platform_data = sata_data;
+        platform_device_register(&dove_sata);
+}
+/*****************************************************************************
+ * UART0
+ ****************************************************************************/
+static struct plat_serial8250_port dove_uart0_data[] = {
+        {
+                .mapbase        = DOVE_UART0_PHYS_BASE,
+                .membase        = (char *)DOVE_UART0_VIRT_BASE,
+                .irq            = IRQ_DOVE_UART_0,
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = 0,
+        }, {
+        },
+};
+static struct resource dove_uart0_resources[] = {
+        {
+                .start          = DOVE_UART0_PHYS_BASE,
+                .end            = DOVE_UART0_PHYS_BASE + SZ_256 - 1,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = IRQ_DOVE_UART_0,
+                .end            = IRQ_DOVE_UART_0,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device dove_uart0 = {
+        .name                   = "serial8250",
+        .id                     = 0,
+        .dev                    = {
+                .platform_data  = dove_uart0_data,
+        },
+        .resource               = dove_uart0_resources,
+        .num_resources          = ARRAY_SIZE(dove_uart0_resources),
+};
+void __init dove_uart0_init(void)
+{
+        platform_device_register(&dove_uart0);
+}
+/*****************************************************************************
+ * UART1
+ ****************************************************************************/
+static struct plat_serial8250_port dove_uart1_data[] = {
+        {
+                .mapbase        = DOVE_UART1_PHYS_BASE,
+                .membase        = (char *)DOVE_UART1_VIRT_BASE,
+                .irq            = IRQ_DOVE_UART_1,
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = 0,
+        }, {
+        },
+};
+static struct resource dove_uart1_resources[] = {
+        {
+                .start          = DOVE_UART1_PHYS_BASE,
+                .end            = DOVE_UART1_PHYS_BASE + SZ_256 - 1,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = IRQ_DOVE_UART_1,
+                .end            = IRQ_DOVE_UART_1,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device dove_uart1 = {
+        .name                   = "serial8250",
+        .id                     = 1,
+        .dev                    = {
+                .platform_data  = dove_uart1_data,
+        },
+        .resource               = dove_uart1_resources,
+        .num_resources          = ARRAY_SIZE(dove_uart1_resources),
+};
+void __init dove_uart1_init(void)
+{
+        platform_device_register(&dove_uart1);
+}
+/*****************************************************************************
+ * UART2
+ ****************************************************************************/
+static struct plat_serial8250_port dove_uart2_data[] = {
+        {
+                .mapbase        = DOVE_UART2_PHYS_BASE,
+                .membase        = (char *)DOVE_UART2_VIRT_BASE,
+                .irq            = IRQ_DOVE_UART_2,
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = 0,
+        }, {
+        },
+};
+static struct resource dove_uart2_resources[] = {
+        {
+                .start          = DOVE_UART2_PHYS_BASE,
+                .end            = DOVE_UART2_PHYS_BASE + SZ_256 - 1,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = IRQ_DOVE_UART_2,
+                .end            = IRQ_DOVE_UART_2,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device dove_uart2 = {
+        .name                   = "serial8250",
+        .id                     = 2,
+        .dev                    = {
+                .platform_data  = dove_uart2_data,
+        },
+        .resource               = dove_uart2_resources,
+        .num_resources          = ARRAY_SIZE(dove_uart2_resources),
+};
+void __init dove_uart2_init(void)
+{
+        platform_device_register(&dove_uart2);
+}
+/*****************************************************************************
+ * UART3
+ ****************************************************************************/
+static struct plat_serial8250_port dove_uart3_data[] = {
+        {
+                .mapbase        = DOVE_UART3_PHYS_BASE,
+                .membase        = (char *)DOVE_UART3_VIRT_BASE,
+                .irq            = IRQ_DOVE_UART_3,
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = 0,
+        }, {
+        },
+};
+static struct resource dove_uart3_resources[] = {
+        {
+                .start          = DOVE_UART3_PHYS_BASE,
+                .end            = DOVE_UART3_PHYS_BASE + SZ_256 - 1,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = IRQ_DOVE_UART_3,
+                .end            = IRQ_DOVE_UART_3,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device dove_uart3 = {
+        .name                   = "serial8250",
+        .id                     = 3,
+        .dev                    = {
+                .platform_data  = dove_uart3_data,
+        },
+        .resource               = dove_uart3_resources,
+        .num_resources          = ARRAY_SIZE(dove_uart3_resources),
+};
+void __init dove_uart3_init(void)
+{
+        platform_device_register(&dove_uart3);
+}
+/*****************************************************************************
+ * SPI0
+ ****************************************************************************/
+static struct orion_spi_info dove_spi0_data = {
+        .tclk           = 0,
+};
+static struct resource dove_spi0_resources[] = {
+        {
+                .start  = DOVE_SPI0_PHYS_BASE,
+                .end    = DOVE_SPI0_PHYS_BASE + SZ_512 - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_DOVE_SPI0,
+                .end    = IRQ_DOVE_SPI0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device dove_spi0 = {
+        .name           = "orion_spi",
+        .id             = 0,
+        .resource       = dove_spi0_resources,
+        .dev            = {
+                .platform_data  = &dove_spi0_data,
+        },
+        .num_resources  = ARRAY_SIZE(dove_spi0_resources),
+};
+void __init dove_spi0_init(void)
+{
+        platform_device_register(&dove_spi0);
+}
+/*****************************************************************************
+ * SPI1
+ ****************************************************************************/
+static struct orion_spi_info dove_spi1_data = {
+        .tclk           = 0,
+};
+static struct resource dove_spi1_resources[] = {
+        {
+                .start  = DOVE_SPI1_PHYS_BASE,
+                .end    = DOVE_SPI1_PHYS_BASE + SZ_512 - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_DOVE_SPI1,
+                .end    = IRQ_DOVE_SPI1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device dove_spi1 = {
+        .name           = "orion_spi",
+        .id             = 1,
+        .resource       = dove_spi1_resources,
+        .dev            = {
+                .platform_data  = &dove_spi1_data,
+        },
+        .num_resources  = ARRAY_SIZE(dove_spi1_resources),
+};
+void __init dove_spi1_init(void)
+{
+        platform_device_register(&dove_spi1);
+}
+/*****************************************************************************
+ * I2C
+ ****************************************************************************/
+static struct mv64xxx_i2c_pdata dove_i2c_data = {
+        .freq_m         = 10, /* assumes 166 MHz TCLK gets 94.3kHz */
+        .freq_n         = 3,
+        .timeout        = 1000, /* Default timeout of 1 second */
+};
+static struct resource dove_i2c_resources[] = {
+        {
+                .name   = "i2c base",
+                .start  = DOVE_I2C_PHYS_BASE,
+                .end    = DOVE_I2C_PHYS_BASE + 0x20 - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "i2c irq",
+                .start  = IRQ_DOVE_I2C,
+                .end    = IRQ_DOVE_I2C,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device dove_i2c = {
+        .name           = MV64XXX_I2C_CTLR_NAME,
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(dove_i2c_resources),
+        .resource       = dove_i2c_resources,
+        .dev            = {
+                .platform_data = &dove_i2c_data,
+        },
+};
+void __init dove_i2c_init(void)
+{
+        platform_device_register(&dove_i2c);
+}
+/*****************************************************************************
+ * Time handling
+ ****************************************************************************/
+static int get_tclk(void)
+{
+        /* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */
+        return 166666667;
+}
+static void dove_timer_init(void)
+{
+        orion_time_init(IRQ_DOVE_BRIDGE, get_tclk());
+}
+struct sys_timer dove_timer = {
+        .init = dove_timer_init,
+};
+/*****************************************************************************
+ * XOR
+ ****************************************************************************/
+static struct mv_xor_platform_shared_data dove_xor_shared_data = {
+        .dram           = &dove_mbus_dram_info,
+};
+/*****************************************************************************
+ * XOR 0
+ ****************************************************************************/
+static u64 dove_xor0_dmamask = DMA_BIT_MASK(32);
+static struct resource dove_xor0_shared_resources[] = {
+        {
+                .name   = "xor 0 low",
+                .start  = DOVE_XOR0_PHYS_BASE,
+                .end    = DOVE_XOR0_PHYS_BASE + 0xff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "xor 0 high",
+                .start  = DOVE_XOR0_HIGH_PHYS_BASE,
+                .end    = DOVE_XOR0_HIGH_PHYS_BASE + 0xff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+static struct platform_device dove_xor0_shared = {
+        .name           = MV_XOR_SHARED_NAME,
+        .id             = 0,
+        .dev            = {
+                .platform_data = &dove_xor_shared_data,
+        },
+        .num_resources  = ARRAY_SIZE(dove_xor0_shared_resources),
+        .resource       = dove_xor0_shared_resources,
+};
+static struct resource dove_xor00_resources[] = {
+        [0] = {
+                .start  = IRQ_DOVE_XOR_00,
+                .end    = IRQ_DOVE_XOR_00,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct mv_xor_platform_data dove_xor00_data = {
+        .shared         = &dove_xor0_shared,
+        .hw_id          = 0,
+        .pool_size      = PAGE_SIZE,
+};
+static struct platform_device dove_xor00_channel = {
+        .name           = MV_XOR_NAME,
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(dove_xor00_resources),
+        .resource       = dove_xor00_resources,
+        .dev            = {
+                .dma_mask               = &dove_xor0_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(64),
+                .platform_data          = (void *)&dove_xor00_data,
+        },
+};
+static struct resource dove_xor01_resources[] = {
+        [0] = {
+                .start  = IRQ_DOVE_XOR_01,
+                .end    = IRQ_DOVE_XOR_01,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct mv_xor_platform_data dove_xor01_data = {
+        .shared         = &dove_xor0_shared,
+        .hw_id          = 1,
+        .pool_size      = PAGE_SIZE,
+};
+static struct platform_device dove_xor01_channel = {
+        .name           = MV_XOR_NAME,
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(dove_xor01_resources),
+        .resource       = dove_xor01_resources,
+        .dev            = {
+                .dma_mask               = &dove_xor0_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(64),
+                .platform_data          = (void *)&dove_xor01_data,
+        },
+};
+void __init dove_xor0_init(void)
+{
+        platform_device_register(&dove_xor0_shared);
+        /*
+         * two engines can't do memset simultaneously, this limitation
+         * satisfied by removing memset support from one of the engines.
+         */
+        dma_cap_set(DMA_MEMCPY, dove_xor00_data.cap_mask);
+        dma_cap_set(DMA_XOR, dove_xor00_data.cap_mask);
+        platform_device_register(&dove_xor00_channel);
+        dma_cap_set(DMA_MEMCPY, dove_xor01_data.cap_mask);
+        dma_cap_set(DMA_MEMSET, dove_xor01_data.cap_mask);
+        dma_cap_set(DMA_XOR, dove_xor01_data.cap_mask);
+        platform_device_register(&dove_xor01_channel);
+}
+/*****************************************************************************
+ * XOR 1
+ ****************************************************************************/
+static u64 dove_xor1_dmamask = DMA_BIT_MASK(32);
+static struct resource dove_xor1_shared_resources[] = {
+        {
+                .name   = "xor 0 low",
+                .start  = DOVE_XOR1_PHYS_BASE,
+                .end    = DOVE_XOR1_PHYS_BASE + 0xff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "xor 0 high",
+                .start  = DOVE_XOR1_HIGH_PHYS_BASE,
+                .end    = DOVE_XOR1_HIGH_PHYS_BASE + 0xff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+static struct platform_device dove_xor1_shared = {
+        .name           = MV_XOR_SHARED_NAME,
+        .id             = 1,
+        .dev            = {
+                .platform_data = &dove_xor_shared_data,
+        },
+        .num_resources  = ARRAY_SIZE(dove_xor1_shared_resources),
+        .resource       = dove_xor1_shared_resources,
+};
+static struct resource dove_xor10_resources[] = {
+        [0] = {
+                .start  = IRQ_DOVE_XOR_10,
+                .end    = IRQ_DOVE_XOR_10,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct mv_xor_platform_data dove_xor10_data = {
+        .shared         = &dove_xor1_shared,
+        .hw_id          = 0,
+        .pool_size      = PAGE_SIZE,
+};
+static struct platform_device dove_xor10_channel = {
+        .name           = MV_XOR_NAME,
+        .id             = 2,
+        .num_resources  = ARRAY_SIZE(dove_xor10_resources),
+        .resource       = dove_xor10_resources,
+        .dev            = {
+                .dma_mask               = &dove_xor1_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(64),
+                .platform_data          = (void *)&dove_xor10_data,
+        },
+};
+static struct resource dove_xor11_resources[] = {
+        [0] = {
+                .start  = IRQ_DOVE_XOR_11,
+                .end    = IRQ_DOVE_XOR_11,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct mv_xor_platform_data dove_xor11_data = {
+        .shared         = &dove_xor1_shared,
+        .hw_id          = 1,
+        .pool_size      = PAGE_SIZE,
+};
+static struct platform_device dove_xor11_channel = {
+        .name           = MV_XOR_NAME,
+        .id             = 3,
+        .num_resources  = ARRAY_SIZE(dove_xor11_resources),
+        .resource       = dove_xor11_resources,
+        .dev            = {
+                .dma_mask               = &dove_xor1_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(64),
+                .platform_data          = (void *)&dove_xor11_data,
+        },
+};
+void __init dove_xor1_init(void)
+{
+        platform_device_register(&dove_xor1_shared);
+        /*
+         * two engines can't do memset simultaneously, this limitation
+         * satisfied by removing memset support from one of the engines.
+         */
+        dma_cap_set(DMA_MEMCPY, dove_xor10_data.cap_mask);
+        dma_cap_set(DMA_XOR, dove_xor10_data.cap_mask);
+        platform_device_register(&dove_xor10_channel);
+        dma_cap_set(DMA_MEMCPY, dove_xor11_data.cap_mask);
+        dma_cap_set(DMA_MEMSET, dove_xor11_data.cap_mask);
+        dma_cap_set(DMA_XOR, dove_xor11_data.cap_mask);
+        platform_device_register(&dove_xor11_channel);
+}
+void __init dove_init(void)
+{
+        int tclk;
+        tclk = get_tclk();
+        printk(KERN_INFO "Dove 88AP510 SoC, ");
+        printk(KERN_INFO "TCLK = %dMHz\n", (tclk + 499999) / 1000000);
+#ifdef CONFIG_CACHE_TAUROS2
+        tauros2_init();
+#endif
+        dove_setup_cpu_mbus();
+        dove_ge00_shared_data.t_clk = tclk;
+        dove_uart0_data[0].uartclk = tclk;
+        dove_uart1_data[0].uartclk = tclk;
+        dove_uart2_data[0].uartclk = tclk;
+        dove_uart3_data[0].uartclk = tclk;
+        dove_spi0_data.tclk = tclk;
+        dove_spi1_data.tclk = tclk;
+        /* internal devices that every board has */
+        dove_rtc_init();
+        dove_xor0_init();
+        dove_xor1_init();
+}
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
new file mode 100644
index 000000000000..b29e8937de4f
--- /dev/null
+++ b/arch/arm/mach-dove/common.h
@@ -0,0 +1,40 @@
+/*
+ * arch/arm/mach-dove/common.h
+ *
+ * Core functions for Marvell Dove 88AP510 System On Chip
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ARCH_DOVE_COMMON_H
+#define __ARCH_DOVE_COMMON_H
+struct mv643xx_eth_platform_data;
+struct mv_sata_platform_data;
+extern struct sys_timer dove_timer;
+extern struct mbus_dram_target_info dove_mbus_dram_info;
+/*
+ * Basic Dove init functions used early by machine-setup.
+ */
+void dove_map_io(void);
+void dove_init(void);
+void dove_init_irq(void);
+void dove_setup_cpu_mbus(void);
+void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data);
+void dove_sata_init(struct mv_sata_platform_data *sata_data);
+void dove_pcie_init(int init_port0, int init_port1);
+void dove_ehci0_init(void);
+void dove_ehci1_init(void);
+void dove_uart0_init(void);
+void dove_uart1_init(void);
+void dove_uart2_init(void);
+void dove_uart3_init(void);
+void dove_spi0_init(void);
+void dove_spi1_init(void);
+void dove_i2c_init(void);
+#endif
diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c
new file mode 100644
index 000000000000..f2971b745224
--- /dev/null
+++ b/arch/arm/mach-dove/dove-db-setup.c
@@ -0,0 +1,102 @@
+/*
+ * arch/arm/mach-dove/dove-db-setup.c
+ *
+ * Marvell DB-MV88AP510-BP Development Board Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/nand.h>
+#include <linux/timer.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/i2c.h>
+#include <linux/pci.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/orion_spi.h>
+#include <linux/spi/flash.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/dove.h>
+#include "common.h"
+static struct mv643xx_eth_platform_data dove_db_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR_DEFAULT,
+};
+static struct mv_sata_platform_data dove_db_sata_data = {
+        .n_ports        = 1,
+};
+/*****************************************************************************
+ * SPI Devices:
+ *      SPI0: 4M Flash ST-M25P32-VMF6P
+ ****************************************************************************/
+static const struct flash_platform_data dove_db_spi_flash_data = {
+        .type           = "m25p64",
+};
+static struct spi_board_info __initdata dove_db_spi_flash_info[] = {
+        {
+                .modalias       = "m25p80",
+                .platform_data  = &dove_db_spi_flash_data,
+                .irq            = -1,
+                .max_speed_hz   = 20000000,
+                .bus_num        = 0,
+                .chip_select    = 0,
+        },
+};
+/*****************************************************************************
+ * PCI
+ ****************************************************************************/
+static int __init dove_db_pci_init(void)
+{
+        if (machine_is_dove_db())
+                dove_pcie_init(1, 1);
+        return 0;
+}
+subsys_initcall(dove_db_pci_init);
+/*****************************************************************************
+ * Board Init
+ ****************************************************************************/
+static void __init dove_db_init(void)
+{
+        /*
+         * Basic Dove setup. Needs to be called early.
+         */
+        dove_init();
+        dove_ge00_init(&dove_db_ge00_data);
+        dove_ehci0_init();
+        dove_ehci1_init();
+        dove_sata_init(&dove_db_sata_data);
+        dove_spi0_init();
+        dove_spi1_init();
+        dove_uart0_init();
+        dove_uart1_init();
+        dove_i2c_init();
+        spi_register_board_info(dove_db_spi_flash_info,
+                                ARRAY_SIZE(dove_db_spi_flash_info));
+}
+MACHINE_START(DOVE_DB, "Marvell DB-MV88AP510-BP Development Board")
+        .phys_io        = DOVE_SB_REGS_PHYS_BASE,
+        .io_pg_offst    = ((DOVE_SB_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = dove_db_init,
+        .map_io         = dove_map_io,
+        .init_irq       = dove_init_irq,
+        .timer          = &dove_timer,
+MACHINE_END
diff --git a/arch/arm/mach-dove/include/mach/bridge-regs.h b/arch/arm/mach-dove/include/mach/bridge-regs.h
new file mode 100644
index 000000000000..214a4c31f069
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/bridge-regs.h
@@ -0,0 +1,58 @@
+/*
+ * arch/arm/mach-dove/include/mach/bridge-regs.h
+ *
+ * Mbus-L to Mbus Bridge Registers
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_BRIDGE_REGS_H
+#define __ASM_ARCH_BRIDGE_REGS_H
+#include <mach/dove.h>
+#define CPU_CONFIG              (BRIDGE_VIRT_BASE | 0x0000)
+#define CPU_CONTROL             (BRIDGE_VIRT_BASE | 0x0104)
+#define  CPU_CTRL_PCIE0_LINK    0x00000001
+#define  CPU_RESET              0x00000002
+#define  CPU_CTRL_PCIE1_LINK    0x00000008
+#define RSTOUTn_MASK            (BRIDGE_VIRT_BASE | 0x0108)
+#define  SOFT_RESET_OUT_EN      0x00000004
+#define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE | 0x010c)
+#define  SOFT_RESET             0x00000001
+#define BRIDGE_CAUSE            (BRIDGE_VIRT_BASE | 0x0110)
+#define BRIDGE_MASK             (BRIDGE_VIRT_BASE | 0x0114)
+#define  BRIDGE_INT_TIMER0      0x0002
+#define  BRIDGE_INT_TIMER1      0x0004
+#define  BRIDGE_INT_TIMER1_CLR  (~0x0004)
+#define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE | 0x0200)
+#define IRQ_CAUSE_LOW_OFF       0x0000
+#define IRQ_MASK_LOW_OFF        0x0004
+#define FIQ_MASK_LOW_OFF        0x0008
+#define ENDPOINT_MASK_LOW_OFF   0x000c
+#define IRQ_CAUSE_HIGH_OFF      0x0010
+#define IRQ_MASK_HIGH_OFF       0x0014
+#define FIQ_MASK_HIGH_OFF       0x0018
+#define ENDPOINT_MASK_HIGH_OFF  0x001c
+#define PCIE_INTERRUPT_MASK_OFF 0x0020
+#define IRQ_MASK_LOW            (IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)
+#define FIQ_MASK_LOW            (IRQ_VIRT_BASE + FIQ_MASK_LOW_OFF)
+#define ENDPOINT_MASK_LOW       (IRQ_VIRT_BASE + ENDPOINT_MASK_LOW_OFF)
+#define IRQ_MASK_HIGH           (IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)
+#define FIQ_MASK_HIGH           (IRQ_VIRT_BASE + FIQ_MASK_HIGH_OFF)
+#define ENDPOINT_MASK_HIGH      (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)
+#define PCIE_INTERRUPT_MASK     (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)
+#define POWER_MANAGEMENT        (BRIDGE_VIRT_BASE | 0x011c)
+#define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE | 0x0300)
+#endif
diff --git a/arch/arm/mach-dove/include/mach/debug-macro.S b/arch/arm/mach-dove/include/mach/debug-macro.S
new file mode 100644
index 000000000000..9b89ec7d3040
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/debug-macro.S
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/mach-dove/include/mach/debug-macro.S
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <mach/bridge-regs.h>
+        .macro  addruart,rx
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1                                 @ MMU enabled?
+        ldreq   \rx, =DOVE_SB_REGS_PHYS_BASE
+        ldrne   \rx, =DOVE_SB_REGS_VIRT_BASE
+        orr     \rx, \rx, #0x00012000
+        .endm
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h
new file mode 100644
index 000000000000..f6a08397f046
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/dove.h
@@ -0,0 +1,180 @@
+/*
+ * arch/arm/mach-dove/include/mach/dove.h
+ *
+ * Generic definitions for Marvell Dove 88AP510 SoC
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_DOVE_H
+#define __ASM_ARCH_DOVE_H
+#include <mach/vmalloc.h>
+/*
+ * Marvell Dove address maps.
+ *
+ * phys         virt            size
+ * c8000000     fdb00000        1M      Cryptographic SRAM
+ * e0000000     @runtime        128M    PCIe-0 Memory space
+ * e8000000     @runtime        128M    PCIe-1 Memory space
+ * f1000000     fde00000        8M      on-chip south-bridge registers
+ * f1800000     fe600000        8M      on-chip north-bridge registers
+ * f2000000     fee00000        1M      PCIe-0 I/O space
+ * f2100000     fef00000        1M      PCIe-1 I/O space
+ */
+#define DOVE_CESA_PHYS_BASE             0xc8000000
+#define DOVE_CESA_VIRT_BASE             0xfdb00000
+#define DOVE_CESA_SIZE                  SZ_1M
+#define DOVE_PCIE0_MEM_PHYS_BASE        0xe0000000
+#define DOVE_PCIE0_MEM_SIZE             SZ_128M
+#define DOVE_PCIE1_MEM_PHYS_BASE        0xe8000000
+#define DOVE_PCIE1_MEM_SIZE             SZ_128M
+#define DOVE_BOOTROM_PHYS_BASE          0xf8000000
+#define DOVE_BOOTROM_SIZE               SZ_128M
+#define DOVE_SCRATCHPAD_PHYS_BASE       0xf0000000
+#define DOVE_SCRATCHPAD_VIRT_BASE       0xfdd00000
+#define DOVE_SCRATCHPAD_SIZE            SZ_1M
+#define DOVE_SB_REGS_PHYS_BASE          0xf1000000
+#define DOVE_SB_REGS_VIRT_BASE          0xfde00000
+#define DOVE_SB_REGS_SIZE               SZ_8M
+#define DOVE_NB_REGS_PHYS_BASE          0xf1800000
+#define DOVE_NB_REGS_VIRT_BASE          0xfe600000
+#define DOVE_NB_REGS_SIZE               SZ_8M
+#define DOVE_PCIE0_IO_PHYS_BASE         0xf2000000
+#define DOVE_PCIE0_IO_VIRT_BASE         0xfee00000
+#define DOVE_PCIE0_IO_BUS_BASE          0x00000000
+#define DOVE_PCIE0_IO_SIZE              SZ_1M
+#define DOVE_PCIE1_IO_PHYS_BASE         0xf2100000
+#define DOVE_PCIE1_IO_VIRT_BASE         0xfef00000
+#define DOVE_PCIE1_IO_BUS_BASE          0x00100000
+#define DOVE_PCIE1_IO_SIZE              SZ_1M
+/*
+ * Dove Core Registers Map
+ */
+/* SPI, I2C, UART */
+#define DOVE_I2C_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0x11000)
+#define DOVE_UART0_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x12000)
+#define DOVE_UART0_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x12000)
+#define DOVE_UART1_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x12100)
+#define DOVE_UART1_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x12100)
+#define DOVE_UART2_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x12200)
+#define DOVE_UART2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x12200)
+#define DOVE_UART3_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x12300)
+#define DOVE_UART3_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x12300)
+#define DOVE_SPI0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x10600)
+#define DOVE_SPI1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x14600)
+/* North-South Bridge */
+#define BRIDGE_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE | 0x20000)
+/* Cryptographic Engine */
+#define DOVE_CRYPT_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x30000)
+/* PCIe 0 */
+#define DOVE_PCIE0_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x40000)
+/* USB */
+#define DOVE_USB0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x50000)
+#define DOVE_USB1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x51000)
+/* XOR 0 Engine */
+#define DOVE_XOR0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x60800)
+#define DOVE_XOR0_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0x60800)
+#define DOVE_XOR0_HIGH_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE | 0x60A00)
+#define DOVE_XOR0_HIGH_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE | 0x60A00)
+/* XOR 1 Engine */
+#define DOVE_XOR1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x60900)
+#define DOVE_XOR1_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0x60900)
+#define DOVE_XOR1_HIGH_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE | 0x60B00)
+#define DOVE_XOR1_HIGH_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE | 0x60B00)
+/* Gigabit Ethernet */
+#define DOVE_GE00_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x70000)
+/* PCIe 1 */
+#define DOVE_PCIE1_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x80000)
+/* CAFE */
+#define DOVE_SDIO0_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x92000)
+#define DOVE_SDIO1_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x90000)
+#define DOVE_CAM_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0x94000)
+#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x98000)
+/* SATA */
+#define DOVE_SATA_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xa0000)
+/* I2S/SPDIF */
+#define DOVE_AUD0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xb0000)
+#define DOVE_AUD1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xb4000)
+/* NAND Flash Controller */
+#define DOVE_NFC_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0xc0000)
+/* MPP, GPIO, Reset Sampling */
+#define DOVE_MPP_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE | 0xd0200)
+#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
+#define DOVE_RESET_SAMPLE_LO    (DOVE_MPP_VIRT_BASE | 0x014)
+#define DOVE_RESET_SAMPLE_HI    (DOVE_MPP_VIRT_BASE | 0x018)
+#define DOVE_GPIO_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
+#define DOVE_MPP_GENERAL_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
+#define  DOVE_AU1_SPDIFO_GPIO_EN        (1 << 1)
+#define  DOVE_NAND_GPIO_EN              (1 << 0)
+#define DOVE_MPP_CTRL4_VIRT_BASE        (DOVE_GPIO_VIRT_BASE + 0x40)
+/* Power Management */
+#define DOVE_PMU_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE | 0xd0000)
+/* Real Time Clock */
+#define DOVE_RTC_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0xd8500)
+/* AC97 */
+#define DOVE_AC97_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xe0000)
+#define DOVE_AC97_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0xe0000)
+/* Peripheral DMA */
+#define DOVE_PDMA_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xe4000)
+#define DOVE_PDMA_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0xe4000)
+#define DOVE_GLOBAL_CONFIG_1    (DOVE_SB_REGS_VIRT_BASE | 0xe802C)
+#define  DOVE_TWSI_ENABLE_OPTION1       (1 << 7)
+#define DOVE_GLOBAL_CONFIG_2    (DOVE_SB_REGS_VIRT_BASE | 0xe8030)
+#define  DOVE_TWSI_ENABLE_OPTION2       (1 << 20)
+#define  DOVE_TWSI_ENABLE_OPTION3       (1 << 21)
+#define  DOVE_TWSI_OPTION3_GPIO         (1 << 22)
+#define DOVE_SSP_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0xec000)
+#define DOVE_SSP_CTRL_STATUS_1  (DOVE_SB_REGS_VIRT_BASE | 0xe8034)
+#define  DOVE_SSP_ON_AU1                (1 << 0)
+#define  DOVE_SSP_CLOCK_ENABLE          (1 << 1)
+#define  DOVE_SSP_BPB_CLOCK_SRC_SSP     (1 << 11)
+/* Memory Controller */
+#define DOVE_MC_VIRT_BASE       (DOVE_NB_REGS_VIRT_BASE | 0x00000)
+/* LCD Controller */
+#define DOVE_LCD_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE | 0x10000)
+#define DOVE_LCD1_PHYS_BASE     (DOVE_NB_REGS_PHYS_BASE | 0x20000)
+#define DOVE_LCD2_PHYS_BASE     (DOVE_NB_REGS_PHYS_BASE | 0x10000)
+#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x30000)
+/* Graphic Engine */
+#define DOVE_GPU_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE | 0x40000)
+/* Video Engine */
+#define DOVE_VPU_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE | 0x400000)
+#endif
diff --git a/arch/arm/mach-dove/include/mach/entry-macro.S b/arch/arm/mach-dove/include/mach/entry-macro.S
new file mode 100644
index 000000000000..e84c78c2a8b7
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/entry-macro.S
@@ -0,0 +1,39 @@
+/*
+ * arch/arm/mach-dove/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for Marvell Dove platforms
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <mach/bridge-regs.h>
+        .macro  disable_fiq
+        .endm
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =IRQ_VIRT_BASE
+        .endm
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        @ check low interrupts
+        ldr     \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
+        ldr     \tmp, [\base, #IRQ_MASK_LOW_OFF]
+        mov     \irqnr, #31
+        ands    \irqstat, \irqstat, \tmp
+        @ if no low interrupts set, check high interrupts
+        ldreq   \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
+        ldreq   \tmp, [\base, #IRQ_MASK_HIGH_OFF]
+        moveq   \irqnr, #63
+        andeqs  \irqstat, \irqstat, \tmp
+        @ find first active interrupt source
+        clzne   \irqstat, \irqstat
+        subne   \irqnr, \irqnr, \irqstat
+        .endm
diff --git a/arch/arm/mach-dove/include/mach/gpio.h b/arch/arm/mach-dove/include/mach/gpio.h
new file mode 100644
index 000000000000..0ee70ff39e11
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/gpio.h
@@ -0,0 +1,49 @@
+/*
+ * arch/arm/mach-dove/include/mach/gpio.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
+#include <asm/errno.h>
+#include <mach/irqs.h>
+#include <plat/gpio.h>
+#include <asm-generic/gpio.h>           /* cansleep wrappers */
+#define GPIO_MAX        64
+#define GPIO_BASE_LO            (DOVE_GPIO_VIRT_BASE + 0x00)
+#define GPIO_BASE_HI            (DOVE_GPIO_VIRT_BASE + 0x20)
+#define GPIO_BASE(pin)          ((pin < 32) ? GPIO_BASE_LO : GPIO_BASE_HI)
+#define GPIO_OUT(pin)           (GPIO_BASE(pin) + 0x00)
+#define GPIO_IO_CONF(pin)       (GPIO_BASE(pin) + 0x04)
+#define GPIO_BLINK_EN(pin)      (GPIO_BASE(pin) + 0x08)
+#define GPIO_IN_POL(pin)        (GPIO_BASE(pin) + 0x0c)
+#define GPIO_DATA_IN(pin)       (GPIO_BASE(pin) + 0x10)
+#define GPIO_EDGE_CAUSE(pin)    (GPIO_BASE(pin) + 0x14)
+#define GPIO_EDGE_MASK(pin)     (GPIO_BASE(pin) + 0x18)
+#define GPIO_LEVEL_MASK(pin)    (GPIO_BASE(pin) + 0x1c)
+static inline int gpio_to_irq(int pin)
+{
+        if (pin < NR_GPIO_IRQS)
+                return pin + IRQ_DOVE_GPIO_START;
+        return -EINVAL;
+}
+static inline int irq_to_gpio(int irq)
+{
+        if (IRQ_DOVE_GPIO_START < irq && irq < NR_IRQS)
+                return irq - IRQ_DOVE_GPIO_START;
+        return -EINVAL;
+}
+#endif
diff --git a/arch/arm/mach-dove/include/mach/hardware.h b/arch/arm/mach-dove/include/mach/hardware.h
new file mode 100644
index 000000000000..32b0826e7873
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/hardware.h
@@ -0,0 +1,26 @@
+/*
+ * arch/arm/mach-dove/include/mach/hardware.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+#include "dove.h"
+#define pcibios_assign_all_busses()     1
+#define PCIBIOS_MIN_IO                  0x1000
+#define PCIBIOS_MIN_MEM                 0x01000000
+#define PCIMEM_BASE                     DOVE_PCIE0_MEM_PHYS_BASE
+/* Macros below are required for compatibility with PXA AC'97 driver.   */
+#define __REG(x)        (*((volatile u32 *)((x) - DOVE_SB_REGS_PHYS_BASE + \
+                                DOVE_SB_REGS_VIRT_BASE)))
+#define __PREG(x)       (((u32)&(x)) - DOVE_SB_REGS_VIRT_BASE + \
+                DOVE_SB_REGS_PHYS_BASE)
+#endif
diff --git a/arch/arm/mach-dove/include/mach/io.h b/arch/arm/mach-dove/include/mach/io.h
new file mode 100644
index 000000000000..3b3e4721ce2e
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/io.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/mach-dove/include/mach/io.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+#include "dove.h"
+#define IO_SPACE_LIMIT          0xffffffff
+#define __io(a)  ((void __iomem *)(((a) - DOVE_PCIE0_IO_PHYS_BASE) +\
+                                   DOVE_PCIE0_IO_VIRT_BASE))
+#define __mem_pci(a)            (a)
+#endif
diff --git a/arch/arm/mach-dove/include/mach/irqs.h b/arch/arm/mach-dove/include/mach/irqs.h
new file mode 100644
index 000000000000..46681466f92b
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/irqs.h
@@ -0,0 +1,101 @@
+/*
+ * arch/arm/mach-dove/include/mach/irqs.h
+ *
+ * IRQ definitions for Marvell Dove 88AP510 SoC
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+/*
+ * Dove Low Interrupt Controller
+ */
+#define IRQ_DOVE_BRIDGE         0
+#define IRQ_DOVE_H2C            1
+#define IRQ_DOVE_C2H            2
+#define IRQ_DOVE_NAND           3
+#define IRQ_DOVE_PDMA           4
+#define IRQ_DOVE_SPI1           5
+#define IRQ_DOVE_SPI0           6
+#define IRQ_DOVE_UART_0         7
+#define IRQ_DOVE_UART_1         8
+#define IRQ_DOVE_UART_2         9
+#define IRQ_DOVE_UART_3         10
+#define IRQ_DOVE_I2C            11
+#define IRQ_DOVE_GPIO_0_7       12
+#define IRQ_DOVE_GPIO_8_15      13
+#define IRQ_DOVE_GPIO_16_23     14
+#define IRQ_DOVE_PCIE0_ERR      15
+#define IRQ_DOVE_PCIE0          16
+#define IRQ_DOVE_PCIE1_ERR      17
+#define IRQ_DOVE_PCIE1          18
+#define IRQ_DOVE_I2S0           19
+#define IRQ_DOVE_I2S0_ERR       20
+#define IRQ_DOVE_I2S1           21
+#define IRQ_DOVE_I2S1_ERR       22
+#define IRQ_DOVE_USB_ERR        23
+#define IRQ_DOVE_USB0           24
+#define IRQ_DOVE_USB1           25
+#define IRQ_DOVE_GE00_RX        26
+#define IRQ_DOVE_GE00_TX        27
+#define IRQ_DOVE_GE00_MISC      28
+#define IRQ_DOVE_GE00_SUM       29
+#define IRQ_DOVE_GE00_ERR       30
+#define IRQ_DOVE_CRYPTO         31
+/*
+ * Dove High Interrupt Controller
+ */
+#define IRQ_DOVE_AC97           32
+#define IRQ_DOVE_PMU            33
+#define IRQ_DOVE_CAM            34
+#define IRQ_DOVE_SDIO0          35
+#define IRQ_DOVE_SDIO1          36
+#define IRQ_DOVE_SDIO0_WAKEUP   37
+#define IRQ_DOVE_SDIO1_WAKEUP   38
+#define IRQ_DOVE_XOR_00         39
+#define IRQ_DOVE_XOR_01         40
+#define IRQ_DOVE_XOR0_ERR       41
+#define IRQ_DOVE_XOR_10         42
+#define IRQ_DOVE_XOR_11         43
+#define IRQ_DOVE_XOR1_ERR       44
+#define IRQ_DOVE_LCD_DCON       45
+#define IRQ_DOVE_LCD1           46
+#define IRQ_DOVE_LCD0           47
+#define IRQ_DOVE_GPU            48
+#define IRQ_DOVE_PERFORM_MNTR   49
+#define IRQ_DOVE_VPRO_DMA1      51
+#define IRQ_DOVE_SSP_TIMER      54
+#define IRQ_DOVE_SSP            55
+#define IRQ_DOVE_MC_L2_ERR      56
+#define IRQ_DOVE_CRYPTO_ERR     59
+#define IRQ_DOVE_GPIO_24_31     60
+#define IRQ_DOVE_HIGH_GPIO      61
+#define IRQ_DOVE_SATA           62
+/*
+ * DOVE General Purpose Pins
+ */
+#define IRQ_DOVE_GPIO_START     64
+#define NR_GPIO_IRQS            64
+/*
+ * PMU interrupts
+ */
+#define IRQ_DOVE_PMU_START      (IRQ_DOVE_GPIO_START + NR_GPIO_IRQS)
+#define NR_PMU_IRQS             7
+#define IRQ_DOVE_RTC            (IRQ_DOVE_PMU_START + 5)
+#define NR_IRQS                 (IRQ_DOVE_PMU_START + NR_PMU_IRQS)
+/* Required for compatability with PXA AC97 driver.     */
+#define IRQ_AC97                IRQ_DOVE_AC97
+/* Required for compatability with PXA DMA driver.      */
+#define IRQ_DMA                 IRQ_DOVE_PDMA
+/* Required for compatability with PXA NAND driver      */
+#define IRQ_NAND                IRQ_DOVE_NAND
+#endif
diff --git a/arch/arm/mach-dove/include/mach/memory.h b/arch/arm/mach-dove/include/mach/memory.h
new file mode 100644
index 000000000000..d66872074946
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/memory.h
@@ -0,0 +1,10 @@
+/*
+ * arch/arm/mach-dove/include/mach/memory.h
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+#define PHYS_OFFSET             UL(0x00000000)
+#endif
diff --git a/arch/arm/mach-dove/include/mach/pm.h b/arch/arm/mach-dove/include/mach/pm.h
new file mode 100644
index 000000000000..3ad9f946a9e8
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/pm.h
@@ -0,0 +1,54 @@
+/*
+ * arch/arm/mach-dove/include/mach/pm.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_PM_H
+#define __ASM_ARCH_PM_H
+#include <asm/errno.h>
+#include <mach/irqs.h>
+#define CLOCK_GATING_CONTROL    (DOVE_PMU_VIRT_BASE + 0x38)
+#define  CLOCK_GATING_USB0_MASK         (1 << 0)
+#define  CLOCK_GATING_USB1_MASK         (1 << 1)
+#define  CLOCK_GATING_GBE_MASK          (1 << 2)
+#define  CLOCK_GATING_SATA_MASK         (1 << 3)
+#define  CLOCK_GATING_PCIE0_MASK        (1 << 4)
+#define  CLOCK_GATING_PCIE1_MASK        (1 << 5)
+#define  CLOCK_GATING_SDIO0_MASK        (1 << 8)
+#define  CLOCK_GATING_SDIO1_MASK        (1 << 9)
+#define  CLOCK_GATING_NAND_MASK         (1 << 10)
+#define  CLOCK_GATING_CAMERA_MASK       (1 << 11)
+#define  CLOCK_GATING_I2S0_MASK         (1 << 12)
+#define  CLOCK_GATING_I2S1_MASK         (1 << 13)
+#define  CLOCK_GATING_CRYPTO_MASK       (1 << 15)
+#define  CLOCK_GATING_AC97_MASK         (1 << 21)
+#define  CLOCK_GATING_PDMA_MASK         (1 << 22)
+#define  CLOCK_GATING_XOR0_MASK         (1 << 23)
+#define  CLOCK_GATING_XOR1_MASK         (1 << 24)
+#define  CLOCK_GATING_GIGA_PHY_MASK     (1 << 30)
+#define PMU_INTERRUPT_CAUSE     (DOVE_PMU_VIRT_BASE + 0x50)
+#define PMU_INTERRUPT_MASK      (DOVE_PMU_VIRT_BASE + 0x54)
+static inline int pmu_to_irq(int pin)
+{
+        if (pin < NR_PMU_IRQS)
+                return pin + IRQ_DOVE_PMU_START;
+        return -EINVAL;
+}
+static inline int irq_to_pmu(int irq)
+{
+        if (IRQ_DOVE_PMU_START < irq && irq < NR_IRQS)
+                return irq - IRQ_DOVE_PMU_START;
+        return -EINVAL;
+}
+#endif
diff --git a/arch/arm/mach-dove/include/mach/system.h b/arch/arm/mach-dove/include/mach/system.h
new file mode 100644
index 000000000000..356afda56853
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/system.h
@@ -0,0 +1,36 @@
+/*
+ * arch/arm/mach-dove/include/mach/system.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+#include <mach/bridge-regs.h>
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+static inline void arch_reset(char mode, const char *cmd)
+{
+        /*
+         * Enable soft reset to assert RSTOUTn.
+         */
+        writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
+        /*
+         * Assert soft reset.
+         */
+        writel(SOFT_RESET, SYSTEM_SOFT_RESET);
+        while (1)
+                ;
+}
+#endif
diff --git a/arch/arm/mach-dove/include/mach/timex.h b/arch/arm/mach-dove/include/mach/timex.h
new file mode 100644
index 000000000000..251d538541db
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/timex.h
@@ -0,0 +1,9 @@
+/*
+ * arch/arm/mach-dove/include/mach/timex.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#define CLOCK_TICK_RATE         (100 * HZ)
diff --git a/arch/arm/mach-dove/include/mach/uncompress.h b/arch/arm/mach-dove/include/mach/uncompress.h
new file mode 100644
index 000000000000..2c5cdd7a3eed
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/uncompress.h
@@ -0,0 +1,37 @@
+/*
+ * arch/arm/mach-dove/include/mach/uncompress.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <mach/dove.h>
+#define UART_THR ((volatile unsigned char *)(DOVE_UART0_PHYS_BASE + 0x0))
+#define UART_LSR ((volatile unsigned char *)(DOVE_UART0_PHYS_BASE + 0x14))
+#define LSR_THRE        0x20
+static void putc(const char c)
+{
+        int i;
+        for (i = 0; i < 0x1000; i++) {
+                /* Transmit fifo not full? */
+                if (*UART_LSR & LSR_THRE)
+                        break;
+        }
+        *UART_THR = c;
+}
+static void flush(void)
+{
+}
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-dove/include/mach/vmalloc.h b/arch/arm/mach-dove/include/mach/vmalloc.h
new file mode 100644
index 000000000000..8b2c974755c6
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/vmalloc.h
@@ -0,0 +1,5 @@
+/*
+ * arch/arm/mach-dove/include/mach/vmalloc.h
+ */
+#define VMALLOC_END     0xfd800000
diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
new file mode 100644
index 000000000000..61bfcb3b08c2
--- /dev/null
+++ b/arch/arm/mach-dove/irq.c
@@ -0,0 +1,133 @@
+/*
+ * arch/arm/mach-dove/irq.c
+ *
+ * Dove IRQ handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+#include <asm/mach/arch.h>
+#include <plat/irq.h>
+#include <asm/mach/irq.h>
+#include <mach/pm.h>
+#include <mach/bridge-regs.h>
+#include "common.h"
+static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+        int irqoff;
+        BUG_ON(irq < IRQ_DOVE_GPIO_0_7 || irq > IRQ_DOVE_HIGH_GPIO);
+        irqoff = irq <= IRQ_DOVE_GPIO_16_23 ? irq - IRQ_DOVE_GPIO_0_7 :
+                3 + irq - IRQ_DOVE_GPIO_24_31;
+        orion_gpio_irq_handler(irqoff << 3);
+        if (irq == IRQ_DOVE_HIGH_GPIO) {
+                orion_gpio_irq_handler(40);
+                orion_gpio_irq_handler(48);
+                orion_gpio_irq_handler(56);
+        }
+}
+static void pmu_irq_mask(unsigned int irq)
+{
+        int pin = irq_to_pmu(irq);
+        u32 u;
+        u = readl(PMU_INTERRUPT_MASK);
+        u &= ~(1 << (pin & 31));
+        writel(u, PMU_INTERRUPT_MASK);
+}
+static void pmu_irq_unmask(unsigned int irq)
+{
+        int pin = irq_to_pmu(irq);
+        u32 u;
+        u = readl(PMU_INTERRUPT_MASK);
+        u |= 1 << (pin & 31);
+        writel(u, PMU_INTERRUPT_MASK);
+}
+static void pmu_irq_ack(unsigned int irq)
+{
+        int pin = irq_to_pmu(irq);
+        u32 u;
+        u = ~(1 << (pin & 31));
+        writel(u, PMU_INTERRUPT_CAUSE);
+}
+static struct irq_chip pmu_irq_chip = {
+        .name           = "pmu_irq",
+        .mask           = pmu_irq_mask,
+        .unmask         = pmu_irq_unmask,
+        .ack            = pmu_irq_ack,
+};
+static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+        unsigned long cause = readl(PMU_INTERRUPT_CAUSE);
+        cause &= readl(PMU_INTERRUPT_MASK);
+        if (cause == 0) {
+                do_bad_IRQ(irq, desc);
+                return;
+        }
+        for (irq = 0; irq < NR_PMU_IRQS; irq++) {
+                if (!(cause & (1 << irq)))
+                        continue;
+                irq = pmu_to_irq(irq);
+                desc = irq_desc + irq;
+                desc_handle_irq(irq, desc);
+        }
+}
+void __init dove_init_irq(void)
+{
+        int i;
+        orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
+        orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
+        /*
+         * Mask and clear GPIO IRQ interrupts.
+         */
+        writel(0, GPIO_LEVEL_MASK(0));
+        writel(0, GPIO_EDGE_MASK(0));
+        writel(0, GPIO_EDGE_CAUSE(0));
+        /*
+         * Mask and clear PMU interrupts
+         */
+        writel(0, PMU_INTERRUPT_MASK);
+        writel(0, PMU_INTERRUPT_CAUSE);
+        for (i = IRQ_DOVE_GPIO_START; i < IRQ_DOVE_PMU_START; i++) {
+                set_irq_chip(i, &orion_gpio_irq_chip);
+                set_irq_handler(i, handle_level_irq);
+                irq_desc[i].status |= IRQ_LEVEL;
+                set_irq_flags(i, IRQF_VALID);
+        }
+        set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
+        set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
+        set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
+        set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);
+        set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);
+        for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
+                set_irq_chip(i, &pmu_irq_chip);
+                set_irq_handler(i, handle_level_irq);
+                irq_desc[i].status |= IRQ_LEVEL;
+                set_irq_flags(i, IRQF_VALID);
+        }
+        set_irq_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);
+}
diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
new file mode 100644
index 000000000000..502d1ca2f4b7
--- /dev/null
+++ b/arch/arm/mach-dove/pcie.c
@@ -0,0 +1,238 @@
+/*
+ * arch/arm/mach-dove/pcie.c
+ *
+ * PCIe functions for Marvell Dove 88AP510 SoC
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/mbus.h>
+#include <asm/mach/pci.h>
+#include <asm/mach/arch.h>
+#include <asm/setup.h>
+#include <asm/delay.h>
+#include <plat/pcie.h>
+#include <mach/irqs.h>
+#include <mach/bridge-regs.h>
+#include "common.h"
+struct pcie_port {
+        u8                      index;
+        u8                      root_bus_nr;
+        void __iomem            *base;
+        spinlock_t              conf_lock;
+        char                    io_space_name[16];
+        char                    mem_space_name[16];
+        struct resource         res[2];
+};
+static struct pcie_port pcie_port[2];
+static int num_pcie_ports;
+static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
+{
+        struct pcie_port *pp;
+        if (nr >= num_pcie_ports)
+                return 0;
+        pp = &pcie_port[nr];
+        pp->root_bus_nr = sys->busnr;
+        /*
+         * Generic PCIe unit setup.
+         */
+        orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
+        orion_pcie_setup(pp->base, &dove_mbus_dram_info);
+        /*
+         * IORESOURCE_IO
+         */
+        snprintf(pp->io_space_name, sizeof(pp->io_space_name),
+                 "PCIe %d I/O", pp->index);
+        pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
+        pp->res[0].name = pp->io_space_name;
+        if (pp->index == 0) {
+                pp->res[0].start = DOVE_PCIE0_IO_PHYS_BASE;
+                pp->res[0].end = pp->res[0].start + DOVE_PCIE0_IO_SIZE - 1;
+        } else {
+                pp->res[0].start = DOVE_PCIE1_IO_PHYS_BASE;
+                pp->res[0].end = pp->res[0].start + DOVE_PCIE1_IO_SIZE - 1;
+        }
+        pp->res[0].flags = IORESOURCE_IO;
+        if (request_resource(&ioport_resource, &pp->res[0]))
+                panic("Request PCIe IO resource failed\n");
+        sys->resource[0] = &pp->res[0];
+        /*
+         * IORESOURCE_MEM
+         */
+        snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
+                 "PCIe %d MEM", pp->index);
+        pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
+        pp->res[1].name = pp->mem_space_name;
+        if (pp->index == 0) {
+                pp->res[1].start = DOVE_PCIE0_MEM_PHYS_BASE;
+                pp->res[1].end = pp->res[1].start + DOVE_PCIE0_MEM_SIZE - 1;
+        } else {
+                pp->res[1].start = DOVE_PCIE1_MEM_PHYS_BASE;
+                pp->res[1].end = pp->res[1].start + DOVE_PCIE1_MEM_SIZE - 1;
+        }
+        pp->res[1].flags = IORESOURCE_MEM;
+        if (request_resource(&iomem_resource, &pp->res[1]))
+                panic("Request PCIe Memory resource failed\n");
+        sys->resource[1] = &pp->res[1];
+        sys->resource[2] = NULL;
+        return 1;
+}
+static struct pcie_port *bus_to_port(int bus)
+{
+        int i;
+        for (i = num_pcie_ports - 1; i >= 0; i--) {
+                int rbus = pcie_port[i].root_bus_nr;
+                if (rbus != -1 && rbus <= bus)
+                        break;
+        }
+        return i >= 0 ? pcie_port + i : NULL;
+}
+static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
+{
+        /*
+         * Don't go out when trying to access nonexisting devices
+         * on the local bus.
+         */
+        if (bus == pp->root_bus_nr && dev > 1)
+                return 0;
+        return 1;
+}
+static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
+                        int size, u32 *val)
+{
+        struct pcie_port *pp = bus_to_port(bus->number);
+        unsigned long flags;
+        int ret;
+        if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
+                *val = 0xffffffff;
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        }
+        spin_lock_irqsave(&pp->conf_lock, flags);
+        ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
+        spin_unlock_irqrestore(&pp->conf_lock, flags);
+        return ret;
+}
+static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
+                        int where, int size, u32 val)
+{
+        struct pcie_port *pp = bus_to_port(bus->number);
+        unsigned long flags;
+        int ret;
+        if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        spin_lock_irqsave(&pp->conf_lock, flags);
+        ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
+        spin_unlock_irqrestore(&pp->conf_lock, flags);
+        return ret;
+}
+static struct pci_ops pcie_ops = {
+        .read = pcie_rd_conf,
+        .write = pcie_wr_conf,
+};
+static void __devinit rc_pci_fixup(struct pci_dev *dev)
+{
+        /*
+         * Prevent enumeration of root complex.
+         */
+        if (dev->bus->parent == NULL && dev->devfn == 0) {
+                int i;
+                for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
+                        dev->resource[i].start = 0;
+                        dev->resource[i].end   = 0;
+                        dev->resource[i].flags = 0;
+                }
+        }
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
+static struct pci_bus __init *
+dove_pcie_scan_bus(int nr, struct pci_sys_data *sys)
+{
+        struct pci_bus *bus;
+        if (nr < num_pcie_ports) {
+                bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
+        } else {
+                bus = NULL;
+                BUG();
+        }
+        return bus;
+}
+static int __init dove_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        struct pcie_port *pp = bus_to_port(dev->bus->number);
+        return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0;
+}
+static struct hw_pci dove_pci __initdata = {
+        .nr_controllers = 2,
+        .swizzle        = pci_std_swizzle,
+        .setup          = dove_pcie_setup,
+        .scan           = dove_pcie_scan_bus,
+        .map_irq        = dove_pcie_map_irq,
+};
+static void __init add_pcie_port(int index, unsigned long base)
+{
+        printk(KERN_INFO "Dove PCIe port %d: ", index);
+        if (orion_pcie_link_up((void __iomem *)base)) {
+                struct pcie_port *pp = &pcie_port[num_pcie_ports++];
+                printk(KERN_INFO "link up\n");
+                pp->index = index;
+                pp->root_bus_nr = -1;
+                pp->base = (void __iomem *)base;
+                spin_lock_init(&pp->conf_lock);
+                memset(pp->res, 0, sizeof(pp->res));
+        } else {
+                printk(KERN_INFO "link down, ignoring\n");
+        }
+}
+void __init dove_pcie_init(int init_port0, int init_port1)
+{
+        if (init_port0)
+                add_pcie_port(0, DOVE_PCIE0_VIRT_BASE);
+        if (init_port1)
+                add_pcie_port(1, DOVE_PCIE1_VIRT_BASE);
+        pci_common_init(&dove_pci);
+}
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index b4357c388d2e..1f0d66561bbe 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -31,6 +31,7 @@
 #include <mach/hardware.h>
 #include <mach/fb.h>
+#include <mach/ep93xx_keypad.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
@@ -728,6 +729,82 @@ void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data)
        platform_device_register(&ep93xx_fb_device);
 }
+/*************************************************************************
+ * EP93xx matrix keypad peripheral handling
+ *************************************************************************/
+static struct resource ep93xx_keypad_resource[] = {
+        {
+                .start  = EP93XX_KEY_MATRIX_PHYS_BASE,
+                .end    = EP93XX_KEY_MATRIX_PHYS_BASE + 0x0c - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_EP93XX_KEY,
+                .end    = IRQ_EP93XX_KEY,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device ep93xx_keypad_device = {
+        .name                   = "ep93xx-keypad",
+        .id                     = -1,
+        .num_resources          = ARRAY_SIZE(ep93xx_keypad_resource),
+        .resource               = ep93xx_keypad_resource,
+};
+void __init ep93xx_register_keypad(struct ep93xx_keypad_platform_data *data)
+{
+        ep93xx_keypad_device.dev.platform_data = data;
+        platform_device_register(&ep93xx_keypad_device);
+}
+int ep93xx_keypad_acquire_gpio(struct platform_device *pdev)
+{
+        int err;
+        int i;
+        for (i = 0; i < 8; i++) {
+                err = gpio_request(EP93XX_GPIO_LINE_C(i), dev_name(&pdev->dev));
+                if (err)
+                        goto fail_gpio_c;
+                err = gpio_request(EP93XX_GPIO_LINE_D(i), dev_name(&pdev->dev));
+                if (err)
+                        goto fail_gpio_d;
+        }
+        /* Enable the keypad controller; GPIO ports C and D used for keypad */
+        ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_KEYS |
+                                 EP93XX_SYSCON_DEVCFG_GONK);
+        return 0;
+fail_gpio_d:
+        gpio_free(EP93XX_GPIO_LINE_C(i));
+fail_gpio_c:
+        for ( ; i >= 0; --i) {
+                gpio_free(EP93XX_GPIO_LINE_C(i));
+                gpio_free(EP93XX_GPIO_LINE_D(i));
+        }
+        return err;
+}
+EXPORT_SYMBOL(ep93xx_keypad_acquire_gpio);
+void ep93xx_keypad_release_gpio(struct platform_device *pdev)
+{
+        int i;
+        for (i = 0; i < 8; i++) {
+                gpio_free(EP93XX_GPIO_LINE_C(i));
+                gpio_free(EP93XX_GPIO_LINE_D(i));
+        }
+        /* Disable the keypad controller; GPIO ports C and D used for GPIO */
+        ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
+                               EP93XX_SYSCON_DEVCFG_GONK);
+}
+EXPORT_SYMBOL(ep93xx_keypad_release_gpio);
 extern void ep93xx_gpio_init(void);
 void __init ep93xx_init_devices(void)
diff --git a/arch/arm/mach-ep93xx/include/mach/clkdev.h b/arch/arm/mach-ep93xx/include/mach/clkdev.h
index 04b37a89801c..50cb991eadeb 100644
--- a/arch/arm/mach-ep93xx/include/mach/clkdev.h
+++ b/arch/arm/mach-ep93xx/include/mach/clkdev.h
@@ -1,3 +1,7 @@
+/*
+ * arch/arm/mach-ep93xx/include/mach/clkdev.h
+ */
 #ifndef __ASM_MACH_CLKDEV_H
 #define __ASM_MACH_CLKDEV_H
diff --git a/arch/arm/mach-ep93xx/include/mach/dma.h b/arch/arm/mach-ep93xx/include/mach/dma.h
index ef6bd9d13148..3a5961d3f3b1 100644
--- a/arch/arm/mach-ep93xx/include/mach/dma.h
+++ b/arch/arm/mach-ep93xx/include/mach/dma.h
@@ -1,3 +1,7 @@
+/*
+ * arch/arm/mach-ep93xx/include/mach/dma.h
+ */
 #ifndef __ASM_ARCH_DMA_H
 #define __ASM_ARCH_DMA_H
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
index b1f937eda29c..d55194a4c093 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -134,6 +134,7 @@
 #define EP93XX_UART3_PHYS_BASE          EP93XX_APB_PHYS(0x000e0000)
 #define EP93XX_UART3_BASE               EP93XX_APB_IOMEM(0x000e0000)
+#define EP93XX_KEY_MATRIX_PHYS_BASE     EP93XX_APB_PHYS(0x000f0000)
 #define EP93XX_KEY_MATRIX_BASE          EP93XX_APB_IOMEM(0x000f0000)
 #define EP93XX_ADC_BASE                 EP93XX_APB_IOMEM(0x00100000)
diff --git a/arch/arm/mach-ep93xx/include/mach/hardware.h b/arch/arm/mach-ep93xx/include/mach/hardware.h
index 349fa7cb72d5..5a3ce024b593 100644
--- a/arch/arm/mach-ep93xx/include/mach/hardware.h
+++ b/arch/arm/mach-ep93xx/include/mach/hardware.h
@@ -1,6 +1,7 @@
 /*
 * arch/arm/mach-ep93xx/include/mach/hardware.h
 */
 #ifndef __ASM_ARCH_HARDWARE_H
 #define __ASM_ARCH_HARDWARE_H
diff --git a/arch/arm/mach-ep93xx/include/mach/io.h b/arch/arm/mach-ep93xx/include/mach/io.h
index cebcc1c53d63..594b77f21054 100644
--- a/arch/arm/mach-ep93xx/include/mach/io.h
+++ b/arch/arm/mach-ep93xx/include/mach/io.h
@@ -1,6 +1,7 @@
 /*
 * arch/arm/mach-ep93xx/include/mach/io.h
 */
 #ifndef __ASM_MACH_IO_H
 #define __ASM_MACH_IO_H
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index 469fd968d517..c6dc14dbca18 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -8,6 +8,7 @@ struct i2c_gpio_platform_data;
 struct i2c_board_info;
 struct platform_device;
 struct ep93xxfb_mach_info;
+struct ep93xx_keypad_platform_data;
 struct ep93xx_eth_data
 {
@@ -39,6 +40,9 @@ void ep93xx_register_fb(struct ep93xxfb_mach_info *data);
 void ep93xx_register_pwm(int pwm0, int pwm1);
 int ep93xx_pwm_acquire_gpio(struct platform_device *pdev);
 void ep93xx_pwm_release_gpio(struct platform_device *pdev);
+void ep93xx_register_keypad(struct ep93xx_keypad_platform_data *data);
+int ep93xx_keypad_acquire_gpio(struct platform_device *pdev);
+void ep93xx_keypad_release_gpio(struct platform_device *pdev);
 void ep93xx_init_devices(void);
 extern struct sys_timer ep93xx_timer;
diff --git a/arch/arm/mach-iop13xx/include/mach/memory.h b/arch/arm/mach-iop13xx/include/mach/memory.h
index 42ae29b288a1..25b1da9a5035 100644
--- a/arch/arm/mach-iop13xx/include/mach/memory.h
+++ b/arch/arm/mach-iop13xx/include/mach/memory.h
@@ -64,6 +64,8 @@ static inline unsigned long __lbus_to_virt(dma_addr_t x)
                (dma_addr_t)page_to_phys(page);                         \
        })
+#define __arch_dma_to_page(dev, addr)   phys_to_page(addr)
 #endif /* CONFIG_ARCH_IOP13XX */
 #endif /* !ASSEMBLY */
diff --git a/arch/arm/mach-iop13xx/include/mach/time.h b/arch/arm/mach-iop13xx/include/mach/time.h
index d6d52527589d..f1c00d6d560b 100644
--- a/arch/arm/mach-iop13xx/include/mach/time.h
+++ b/arch/arm/mach-iop13xx/include/mach/time.h
@@ -20,7 +20,6 @@
 #define IOP13XX_CORE_FREQ_1200          (5 << 16)
 void iop_init_time(unsigned long tickrate);
-unsigned long iop_gettimeoffset(void);
 static inline unsigned long iop13xx_core_freq(void)
 {
@@ -66,6 +65,13 @@ static inline unsigned long iop13xx_xsi_bus_ratio(void)
        return 2;
 }
+static inline u32 read_tmr0(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c0, c9, 0" : "=r" (val));
+        return val;
+}
 static inline void write_tmr0(u32 val)
 {
        asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val));
@@ -83,6 +89,11 @@ static inline u32 read_tcr0(void)
        return val;
 }
+static inline void write_tcr0(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c2, c9, 0" : : "r" (val));
+}
 static inline u32 read_tcr1(void)
 {
        u32 val;
@@ -90,6 +101,11 @@ static inline u32 read_tcr1(void)
        return val;
 }
+static inline void write_tcr1(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c3, c9, 0" : : "r" (val));
+}
 static inline void write_trr0(u32 val)
 {
        asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (val));
diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c
index 5051c03d437c..f91f3154577d 100644
--- a/arch/arm/mach-iop13xx/iq81340mc.c
+++ b/arch/arm/mach-iop13xx/iq81340mc.c
@@ -87,7 +87,6 @@ static void __init iq81340mc_timer_init(void)
 static struct sys_timer iq81340mc_timer = {
       .init       = iq81340mc_timer_init,
-       .offset     = iop_gettimeoffset,
 };
 MACHINE_START(IQ81340MC, "Intel IQ81340MC")
diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c
index bc443073a8e3..ddb7a3435de9 100644
--- a/arch/arm/mach-iop13xx/iq81340sc.c
+++ b/arch/arm/mach-iop13xx/iq81340sc.c
@@ -89,7 +89,6 @@ static void __init iq81340sc_timer_init(void)
 static struct sys_timer iq81340sc_timer = {
       .init       = iq81340sc_timer_init,
-       .offset     = iop_gettimeoffset,
 };
 MACHINE_START(IQ81340SC, "Intel IQ81340SC")
diff --git a/arch/arm/mach-iop32x/em7210.c b/arch/arm/mach-iop32x/em7210.c
index 3ad4696ade42..2bef9b6e1cc9 100644
--- a/arch/arm/mach-iop32x/em7210.c
+++ b/arch/arm/mach-iop32x/em7210.c
@@ -42,7 +42,6 @@ static void __init em7210_timer_init(void)
 static struct sys_timer em7210_timer = {
        .init           = em7210_timer_init,
-        .offset         = iop_gettimeoffset,
 };
 /*
diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c
index a9c2dfdb2507..93370a46b620 100644
--- a/arch/arm/mach-iop32x/glantank.c
+++ b/arch/arm/mach-iop32x/glantank.c
@@ -47,7 +47,6 @@ static void __init glantank_timer_init(void)
 static struct sys_timer glantank_timer = {
        .init           = glantank_timer_init,
-        .offset         = iop_gettimeoffset,
 };
diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c
index dd1cd9904518..a7a08dda7f33 100644
--- a/arch/arm/mach-iop32x/iq31244.c
+++ b/arch/arm/mach-iop32x/iq31244.c
@@ -78,7 +78,6 @@ static void __init iq31244_timer_init(void)
 static struct sys_timer iq31244_timer = {
        .init           = iq31244_timer_init,
-        .offset         = iop_gettimeoffset,
 };
diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c
index fbe27798759d..0200f80c1e17 100644
--- a/arch/arm/mach-iop32x/iq80321.c
+++ b/arch/arm/mach-iop32x/iq80321.c
@@ -46,7 +46,6 @@ static void __init iq80321_timer_init(void)
 static struct sys_timer iq80321_timer = {
        .init           = iq80321_timer_init,
-        .offset         = iop_gettimeoffset,
 };
diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c
index d2e427899729..2a5c637639bb 100644
--- a/arch/arm/mach-iop32x/n2100.c
+++ b/arch/arm/mach-iop32x/n2100.c
@@ -53,7 +53,6 @@ static void __init n2100_timer_init(void)
 static struct sys_timer n2100_timer = {
        .init           = n2100_timer_init,
-        .offset         = iop_gettimeoffset,
 };
diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c
index d51e10cddf20..394e95a30b75 100644
--- a/arch/arm/mach-iop33x/iq80331.c
+++ b/arch/arm/mach-iop33x/iq80331.c
@@ -48,7 +48,6 @@ static void __init iq80331_timer_init(void)
 static struct sys_timer iq80331_timer = {
        .init           = iq80331_timer_init,
-        .offset         = iop_gettimeoffset,
 };
diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c
index 92fb44cdbcad..a40badf126c2 100644
--- a/arch/arm/mach-iop33x/iq80332.c
+++ b/arch/arm/mach-iop33x/iq80332.c
@@ -48,7 +48,6 @@ static void __init iq80332_timer_init(void)
 static struct sys_timer iq80332_timer = {
        .init           = iq80332_timer_init,
-        .offset         = iop_gettimeoffset,
 };
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 0aca451b216d..8bf09ae5b347 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -33,10 +33,18 @@ config MACH_SHEEVAPLUG
          Marvell SheevaPlug Reference Board.
 config MACH_TS219
-        bool "QNAP TS-119 and TS-219 Turbo NAS"
+        bool "QNAP TS-110, TS-119, TS-210, TS-219 and TS-219P Turbo NAS"
        help
          Say 'Y' here if you want your kernel to support the
-          QNAP TS-119 and TS-219 Turbo NAS devices.
+          QNAP TS-110, TS-119, TS-210, TS-219 and TS-219P Turbo NAS
+          devices.
+config MACH_TS41X
+        bool "QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS"
+        help
+          Say 'Y' here if you want your kernel to support the
+          QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS
+          devices.
 config MACH_OPENRD_BASE
        bool "Marvell OpenRD Base Board"
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 80ab0ec90ee1..9f2f67b2b63d 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -5,7 +5,8 @@ obj-$(CONFIG_MACH_RD88F6192_NAS)	+= rd88f6192-nas-setup.o
 obj-$(CONFIG_MACH_RD88F6281)            += rd88f6281-setup.o
 obj-$(CONFIG_MACH_MV88F6281GTW_GE)      += mv88f6281gtw_ge-setup.o
 obj-$(CONFIG_MACH_SHEEVAPLUG)           += sheevaplug-setup.o
-obj-$(CONFIG_MACH_TS219)                += ts219-setup.o
+obj-$(CONFIG_MACH_TS219)                += ts219-setup.o tsx1x-common.o
+obj-$(CONFIG_MACH_TS41X)                += ts41x-setup.o tsx1x-common.o
 obj-$(CONFIG_MACH_OPENRD_BASE)          += openrd_base-setup.o
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index ec1a64f263d2..2830f0fe80e0 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -1,6 +1,6 @@
 /*
 *
- * QNAP TS-119/TS-219 Turbo NAS Board Setup
+ * QNAP TS-11x/TS-21x Turbo NAS Board Setup
 *
 * Copyright (C) 2009  Martin Michlmayr <tbm@cyrius.com>
 * Copyright (C) 2008  Byron Bradley <byron.bbradley@gmail.com>
@@ -14,87 +14,17 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/orion_spi.h>
 #include <linux/i2c.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/ata_platform.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
-#include <linux/timex.h>
-#include <linux/serial_reg.h>
-#include <linux/pci.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
 #include "common.h"
 #include "mpp.h"
+#include "tsx1x-common.h"
-/****************************************************************************
- * 16 MiB NOR flash. The struct mtd_partition is not in the same order as the
- *     partitions on the device because we want to keep compatability with
- *     the QNAP firmware.
- * Layout as used by QNAP:
- *  0x00000000-0x00080000 : "U-Boot"
- *  0x00200000-0x00400000 : "Kernel"
- *  0x00400000-0x00d00000 : "RootFS"
- *  0x00d00000-0x01000000 : "RootFS2"
- *  0x00080000-0x000c0000 : "U-Boot Config"
- *  0x000c0000-0x00200000 : "NAS Config"
- *
- * We'll use "RootFS1" instead of "RootFS" to stay compatible with the layout
- * used by the QNAP TS-109/TS-209.
- *
- ***************************************************************************/
-static struct mtd_partition qnap_ts219_partitions[] = {
-        {
-                .name           = "U-Boot",
-                .size           = 0x00080000,
-                .offset         = 0,
-                .mask_flags     = MTD_WRITEABLE,
-        }, {
-                .name           = "Kernel",
-                .size           = 0x00200000,
-                .offset         = 0x00200000,
-        }, {
-                .name           = "RootFS1",
-                .size           = 0x00900000,
-                .offset         = 0x00400000,
-        }, {
-                .name           = "RootFS2",
-                .size           = 0x00300000,
-                .offset         = 0x00d00000,
-        }, {
-                .name           = "U-Boot Config",
-                .size           = 0x00040000,
-                .offset         = 0x00080000,
-        }, {
-                .name           = "NAS Config",
-                .size           = 0x00140000,
-                .offset         = 0x000c0000,
-        },
-};
-static const struct flash_platform_data qnap_ts219_flash = {
-        .type           = "m25p128",
-        .name           = "spi_flash",
-        .parts          = qnap_ts219_partitions,
-        .nr_parts       = ARRAY_SIZE(qnap_ts219_partitions),
-};
-static struct spi_board_info __initdata qnap_ts219_spi_slave_info[] = {
-        {
-                .modalias       = "m25p80",
-                .platform_data  = &qnap_ts219_flash,
-                .irq            = -1,
-                .max_speed_hz   = 20000000,
-                .bus_num        = 0,
-                .chip_select    = 0,
-        },
-};
 static struct i2c_board_info __initdata qnap_ts219_i2c_rtc = {
        I2C_BOARD_INFO("s35390a", 0x30),
@@ -152,36 +82,10 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = {
        MPP14_UART1_RXD,        /* PIC controller */
        MPP15_GPIO,             /* USB Copy button */
        MPP16_GPIO,             /* Reset button */
+        MPP36_GPIO,             /* RAM: 0: 256 MB, 1: 512 MB */
        0
 };
-/*****************************************************************************
- * QNAP TS-x19 specific power off method via UART1-attached PIC
- ****************************************************************************/
-#define UART1_REG(x)    (UART1_VIRT_BASE + ((UART_##x) << 2))
-void qnap_ts219_power_off(void)
-{
-        /* 19200 baud divisor */
-        const unsigned divisor = ((kirkwood_tclk + (8 * 19200)) / (16 * 19200));
-        pr_info("%s: triggering power-off...\n", __func__);
-        /* hijack UART1 and reset into sane state (19200,8n1) */
-        writel(0x83, UART1_REG(LCR));
-        writel(divisor & 0xff, UART1_REG(DLL));
-        writel((divisor >> 8) & 0xff, UART1_REG(DLM));
-        writel(0x03, UART1_REG(LCR));
-        writel(0x00, UART1_REG(IER));
-        writel(0x00, UART1_REG(FCR));
-        writel(0x00, UART1_REG(MCR));
-        /* send the power-off command 'A' to PIC */
-        writel('A', UART1_REG(TX));
-}
 static void __init qnap_ts219_init(void)
 {
        /*
@@ -192,9 +96,7 @@ static void __init qnap_ts219_init(void)
        kirkwood_uart0_init();
        kirkwood_uart1_init(); /* A PIC controller is connected here. */
-        spi_register_board_info(qnap_ts219_spi_slave_info,
+        qnap_tsx1x_register_flash();
-                                ARRAY_SIZE(qnap_ts219_spi_slave_info));
-        kirkwood_spi_init();
        kirkwood_i2c_init();
        i2c_register_board_info(0, &qnap_ts219_i2c_rtc, 1);
        kirkwood_ge00_init(&qnap_ts219_ge00_data);
@@ -202,7 +104,7 @@ static void __init qnap_ts219_init(void)
        kirkwood_ehci_init();
        platform_device_register(&qnap_ts219_button_device);
-        pm_power_off = qnap_ts219_power_off;
+        pm_power_off = qnap_tsx1x_power_off;
 }
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
new file mode 100644
index 000000000000..de49c2d9e74b
--- /dev/null
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -0,0 +1,154 @@
+/*
+ *
+ * QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS Board Setup
+ *
+ * Copyright (C) 2009  Martin Michlmayr <tbm@cyrius.com>
+ * Copyright (C) 2008  Byron Bradley <byron.bbradley@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/ata_platform.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/kirkwood.h>
+#include "common.h"
+#include "mpp.h"
+#include "tsx1x-common.h"
+static struct i2c_board_info __initdata qnap_ts41x_i2c_rtc = {
+        I2C_BOARD_INFO("s35390a", 0x30),
+};
+static struct mv643xx_eth_platform_data qnap_ts41x_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
+};
+static struct mv643xx_eth_platform_data qnap_ts41x_ge01_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
+};
+static struct mv_sata_platform_data qnap_ts41x_sata_data = {
+        .n_ports        = 2,
+};
+static struct gpio_keys_button qnap_ts41x_buttons[] = {
+        {
+                .code           = KEY_COPY,
+                .gpio           = 43,
+                .desc           = "USB Copy",
+                .active_low     = 1,
+        },
+        {
+                .code           = KEY_RESTART,
+                .gpio           = 37,
+                .desc           = "Reset",
+                .active_low     = 1,
+        },
+};
+static struct gpio_keys_platform_data qnap_ts41x_button_data = {
+        .buttons        = qnap_ts41x_buttons,
+        .nbuttons       = ARRAY_SIZE(qnap_ts41x_buttons),
+};
+static struct platform_device qnap_ts41x_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &qnap_ts41x_button_data,
+        }
+};
+static unsigned int qnap_ts41x_mpp_config[] __initdata = {
+        MPP0_SPI_SCn,
+        MPP1_SPI_MOSI,
+        MPP2_SPI_SCK,
+        MPP3_SPI_MISO,
+        MPP6_SYSRST_OUTn,
+        MPP7_PEX_RST_OUTn,
+        MPP8_TW_SDA,
+        MPP9_TW_SCK,
+        MPP10_UART0_TXD,
+        MPP11_UART0_RXD,
+        MPP13_UART1_TXD,        /* PIC controller */
+        MPP14_UART1_RXD,        /* PIC controller */
+        MPP15_SATA0_ACTn,
+        MPP16_SATA1_ACTn,
+        MPP20_GE1_0,
+        MPP21_GE1_1,
+        MPP22_GE1_2,
+        MPP23_GE1_3,
+        MPP24_GE1_4,
+        MPP25_GE1_5,
+        MPP26_GE1_6,
+        MPP27_GE1_7,
+        MPP30_GE1_10,
+        MPP31_GE1_11,
+        MPP32_GE1_12,
+        MPP33_GE1_13,
+        MPP36_GPIO,             /* RAM: 0: 256 MB, 1: 512 MB */
+        MPP37_GPIO,             /* Reset button */
+        MPP43_GPIO,             /* USB Copy button */
+        MPP44_GPIO,             /* Board ID: 0: TS-419U, 1: TS-419 */
+        MPP45_GPIO,             /* JP1: 0: console, 1: LCD */
+        MPP46_GPIO,             /* External SATA HDD1 error indicator */
+        MPP47_GPIO,             /* External SATA HDD2 error indicator */
+        MPP48_GPIO,             /* External SATA HDD3 error indicator */
+        MPP49_GPIO,             /* External SATA HDD4 error indicator */
+        0
+};
+static void __init qnap_ts41x_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_init();
+        kirkwood_mpp_conf(qnap_ts41x_mpp_config);
+        kirkwood_uart0_init();
+        kirkwood_uart1_init(); /* A PIC controller is connected here. */
+        qnap_tsx1x_register_flash();
+        kirkwood_i2c_init();
+        i2c_register_board_info(0, &qnap_ts41x_i2c_rtc, 1);
+        kirkwood_ge00_init(&qnap_ts41x_ge00_data);
+        kirkwood_ge01_init(&qnap_ts41x_ge01_data);
+        kirkwood_sata_init(&qnap_ts41x_sata_data);
+        kirkwood_ehci_init();
+        platform_device_register(&qnap_ts41x_button_device);
+        pm_power_off = qnap_tsx1x_power_off;
+}
+static int __init ts41x_pci_init(void)
+{
+        if (machine_is_ts41x())
+                kirkwood_pcie_init();
+   return 0;
+}
+subsys_initcall(ts41x_pci_init);
+MACHINE_START(TS41X, "QNAP TS-41x")
+        /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
+        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
+        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = qnap_ts41x_init,
+        .map_io         = kirkwood_map_io,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &kirkwood_timer,
+MACHINE_END
diff --git a/arch/arm/mach-kirkwood/tsx1x-common.c b/arch/arm/mach-kirkwood/tsx1x-common.c
new file mode 100644
index 000000000000..7221c20b2afa
--- /dev/null
+++ b/arch/arm/mach-kirkwood/tsx1x-common.c
@@ -0,0 +1,113 @@
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/orion_spi.h>
+#include <linux/serial_reg.h>
+#include <mach/kirkwood.h>
+#include "common.h"
+/*
+ * QNAP TS-x1x Boards flash
+ */
+/****************************************************************************
+ * 16 MiB NOR flash. The struct mtd_partition is not in the same order as the
+ *     partitions on the device because we want to keep compatability with
+ *     the QNAP firmware.
+ * Layout as used by QNAP:
+ *  0x00000000-0x00080000 : "U-Boot"
+ *  0x00200000-0x00400000 : "Kernel"
+ *  0x00400000-0x00d00000 : "RootFS"
+ *  0x00d00000-0x01000000 : "RootFS2"
+ *  0x00080000-0x000c0000 : "U-Boot Config"
+ *  0x000c0000-0x00200000 : "NAS Config"
+ *
+ * We'll use "RootFS1" instead of "RootFS" to stay compatible with the layout
+ * used by the QNAP TS-109/TS-209.
+ *
+ ***************************************************************************/
+struct mtd_partition qnap_tsx1x_partitions[] = {
+        {
+                .name           = "U-Boot",
+                .size           = 0x00080000,
+                .offset         = 0,
+                .mask_flags     = MTD_WRITEABLE,
+        }, {
+                .name           = "Kernel",
+                .size           = 0x00200000,
+                .offset         = 0x00200000,
+        }, {
+                .name           = "RootFS1",
+                .size           = 0x00900000,
+                .offset         = 0x00400000,
+        }, {
+                .name           = "RootFS2",
+                .size           = 0x00300000,
+                .offset         = 0x00d00000,
+        }, {
+                .name           = "U-Boot Config",
+                .size           = 0x00040000,
+                .offset         = 0x00080000,
+        }, {
+                .name           = "NAS Config",
+                .size           = 0x00140000,
+                .offset         = 0x000c0000,
+        },
+};
+const struct flash_platform_data qnap_tsx1x_flash = {
+        .type           = "m25p128",
+        .name           = "spi_flash",
+        .parts          = qnap_tsx1x_partitions,
+        .nr_parts       = ARRAY_SIZE(qnap_tsx1x_partitions),
+};
+struct spi_board_info __initdata qnap_tsx1x_spi_slave_info[] = {
+        {
+                .modalias       = "m25p80",
+                .platform_data  = &qnap_tsx1x_flash,
+                .irq            = -1,
+                .max_speed_hz   = 20000000,
+                .bus_num        = 0,
+                .chip_select    = 0,
+        },
+};
+void qnap_tsx1x_register_flash(void)
+{
+        spi_register_board_info(qnap_tsx1x_spi_slave_info,
+                                ARRAY_SIZE(qnap_tsx1x_spi_slave_info));
+        kirkwood_spi_init();
+}
+/*****************************************************************************
+ * QNAP TS-x1x specific power off method via UART1-attached PIC
+ ****************************************************************************/
+#define UART1_REG(x)    (UART1_VIRT_BASE + ((UART_##x) << 2))
+void qnap_tsx1x_power_off(void)
+{
+        /* 19200 baud divisor */
+        const unsigned divisor = ((kirkwood_tclk + (8 * 19200)) / (16 * 19200));
+        pr_info("%s: triggering power-off...\n", __func__);
+        /* hijack UART1 and reset into sane state (19200,8n1) */
+        writel(0x83, UART1_REG(LCR));
+        writel(divisor & 0xff, UART1_REG(DLL));
+        writel((divisor >> 8) & 0xff, UART1_REG(DLM));
+        writel(0x03, UART1_REG(LCR));
+        writel(0x00, UART1_REG(IER));
+        writel(0x00, UART1_REG(FCR));
+        writel(0x00, UART1_REG(MCR));
+        /* send the power-off command 'A' to PIC */
+        writel('A', UART1_REG(TX));
+}
diff --git a/arch/arm/mach-kirkwood/tsx1x-common.h b/arch/arm/mach-kirkwood/tsx1x-common.h
new file mode 100644
index 000000000000..9a592962a6ea
--- /dev/null
+++ b/arch/arm/mach-kirkwood/tsx1x-common.h
@@ -0,0 +1,7 @@
+#ifndef __ARCH_KIRKWOOD_TSX1X_COMMON_H
+#define __ARCH_KIRKWOOD_TSX1X_COMMON_H
+extern void qnap_tsx1x_register_flash(void);
+extern void qnap_tsx1x_power_off(void);
+#endif
diff --git a/arch/arm/mach-ks8695/include/mach/memory.h b/arch/arm/mach-ks8695/include/mach/memory.h
index 76e5308685a4..ffa19aae6e05 100644
--- a/arch/arm/mach-ks8695/include/mach/memory.h
+++ b/arch/arm/mach-ks8695/include/mach/memory.h
@@ -41,6 +41,13 @@ extern struct bus_type platform_bus_type;
                __dma = __dma - PHYS_OFFSET + KS8695_PCIMEM_PA; \
           __dma; })
+#define __arch_dma_to_page(dev, x)      \
+        ({ dma_addr_t __dma = x;                                \
+           if (!is_lbus_device(dev))                            \
+                __dma += PHYS_OFFSET - KS8695_PCIMEM_PA;        \
+           phys_to_page(__dma);                                 \
+        })
 #endif
 #endif
diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
index 4562452d4074..a2d307ec0420 100644
--- a/arch/arm/mach-mmp/aspenite.c
+++ b/arch/arm/mach-mmp/aspenite.c
@@ -13,6 +13,9 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/smc91x.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/nand.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -85,12 +88,48 @@ static struct platform_device smc91x_device = {
        .resource       = smc91x_resources,
 };
+static struct mtd_partition aspenite_nand_partitions[] = {
+        {
+                .name           = "bootloader",
+                .offset         = 0,
+                .size           = SZ_1M,
+                .mask_flags     = MTD_WRITEABLE,
+        }, {
+                .name           = "reserved",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = SZ_128K,
+                .mask_flags     = MTD_WRITEABLE,
+        }, {
+                .name           = "reserved",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = SZ_8M,
+                .mask_flags     = MTD_WRITEABLE,
+        }, {
+                .name           = "kernel",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = (SZ_2M + SZ_1M),
+                .mask_flags     = 0,
+        }, {
+                .name           = "filesystem",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = SZ_48M,
+                .mask_flags     = 0,
+        }
+};
+static struct pxa3xx_nand_platform_data aspenite_nand_info = {
+        .enable_arbiter = 1,
+        .parts          = aspenite_nand_partitions,
+        .nr_parts       = ARRAY_SIZE(aspenite_nand_partitions),
+};
 static void __init common_init(void)
 {
        mfp_config(ARRAY_AND_SIZE(common_pin_config));
        /* on-chip devices */
        pxa168_add_uart(1);
+        pxa168_add_nand(&aspenite_nand_info);
        /* off-chip devices */
        platform_device_register(&smc91x_device);
diff --git a/arch/arm/mach-mmp/clock.c b/arch/arm/mach-mmp/clock.c
index 2d9cc5a7122f..2a46ed5cc2a2 100644
--- a/arch/arm/mach-mmp/clock.c
+++ b/arch/arm/mach-mmp/clock.c
@@ -34,6 +34,21 @@ struct clkops apbc_clk_ops = {
        .disable        = apbc_clk_disable,
 };
+static void apmu_clk_enable(struct clk *clk)
+{
+        __raw_writel(clk->enable_val, clk->clk_rst);
+}
+static void apmu_clk_disable(struct clk *clk)
+{
+        __raw_writel(0, clk->clk_rst);
+}
+struct clkops apmu_clk_ops = {
+        .enable         = apmu_clk_enable,
+        .disable        = apmu_clk_disable,
+};
 static DEFINE_SPINLOCK(clocks_lock);
 int clk_enable(struct clk *clk)
diff --git a/arch/arm/mach-mmp/clock.h b/arch/arm/mach-mmp/clock.h
index ed967e78e6a8..eefffbe683b0 100644
--- a/arch/arm/mach-mmp/clock.h
+++ b/arch/arm/mach-mmp/clock.h
@@ -25,6 +25,7 @@ struct clk {
 };
 extern struct clkops apbc_clk_ops;
+extern struct clkops apmu_clk_ops;
 #define APBC_CLK(_name, _reg, _fnclksel, _rate)                 \
 struct clk clk_##_name = {                                      \
diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h
index 16295cfd5e29..d68871b0f28c 100644
--- a/arch/arm/mach-mmp/include/mach/irqs.h
+++ b/arch/arm/mach-mmp/include/mach/irqs.h
@@ -31,7 +31,9 @@
 #define IRQ_PXA168_DDR_INT              26
 #define IRQ_PXA168_UART1                27
 #define IRQ_PXA168_UART2                28
+#define IRQ_PXA168_UART3                29
 #define IRQ_PXA168_WDT                  35
+#define IRQ_PXA168_MAIN_PMU             36
 #define IRQ_PXA168_FRQ_CHANGE           38
 #define IRQ_PXA168_SDH1                 39
 #define IRQ_PXA168_SDH2                 40
@@ -46,7 +48,7 @@
 #define IRQ_PXA168_USB2                 51
 #define IRQ_PXA168_AC97                 57
 #define IRQ_PXA168_TWSI1                58
-#define IRQ_PXA168_PMU                  60
+#define IRQ_PXA168_AP_PMU               60
 #define IRQ_PXA168_SM_INT               63
 /*
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
index 6bf1f0eefcd1..3ad612cbdf09 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -4,6 +4,7 @@
 #include <linux/i2c.h>
 #include <mach/devices.h>
 #include <plat/i2c.h>
+#include <plat/pxa3xx_nand.h>
 extern struct pxa_device_desc pxa168_device_uart1;
 extern struct pxa_device_desc pxa168_device_uart2;
@@ -13,6 +14,7 @@ extern struct pxa_device_desc pxa168_device_pwm1;
 extern struct pxa_device_desc pxa168_device_pwm2;
 extern struct pxa_device_desc pxa168_device_pwm3;
 extern struct pxa_device_desc pxa168_device_pwm4;
+extern struct pxa_device_desc pxa168_device_nand;
 static inline int pxa168_add_uart(int id)
 {
@@ -64,4 +66,9 @@ static inline int pxa168_add_pwm(int id)
        return pxa_register_device(d, NULL, 0);
 }
+static inline int pxa168_add_nand(struct pxa3xx_nand_platform_data *info)
+{
+        return pxa_register_device(&pxa168_device_nand, info, sizeof(*info));
+}
 #endif /* __ASM_MACH_PXA168_H */
diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h
index 6ae1ed7a0a9f..4f0b4ec6f5d0 100644
--- a/arch/arm/mach-mmp/include/mach/pxa910.h
+++ b/arch/arm/mach-mmp/include/mach/pxa910.h
@@ -4,6 +4,7 @@
 #include <linux/i2c.h>
 #include <mach/devices.h>
 #include <plat/i2c.h>
+#include <plat/pxa3xx_nand.h>
 extern struct pxa_device_desc pxa910_device_uart1;
 extern struct pxa_device_desc pxa910_device_uart2;
@@ -13,6 +14,7 @@ extern struct pxa_device_desc pxa910_device_pwm1;
 extern struct pxa_device_desc pxa910_device_pwm2;
 extern struct pxa_device_desc pxa910_device_pwm3;
 extern struct pxa_device_desc pxa910_device_pwm4;
+extern struct pxa_device_desc pxa910_device_nand;
 static inline int pxa910_add_uart(int id)
 {
@@ -64,4 +66,9 @@ static inline int pxa910_add_pwm(int id)
        return pxa_register_device(d, NULL, 0);
 }
+static inline int pxa910_add_nand(struct pxa3xx_nand_platform_data *info)
+{
+        return pxa_register_device(&pxa910_device_nand, info, sizeof(*info));
+}
 #endif /* __ASM_MACH_PXA910_H */
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 71b1ae338753..37dbdde17fac 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -19,6 +19,7 @@
 #include <mach/addr-map.h>
 #include <mach/cputype.h>
 #include <mach/regs-apbc.h>
+#include <mach/regs-apmu.h>
 #include <mach/irqs.h>
 #include <mach/gpio.h>
 #include <mach/dma.h>
@@ -72,6 +73,8 @@ static APBC_CLK(pwm2, PXA168_PWM2, 1, 13000000);
 static APBC_CLK(pwm3, PXA168_PWM3, 1, 13000000);
 static APBC_CLK(pwm4, PXA168_PWM4, 1, 13000000);
+static APMU_CLK(nand, NAND, 0x01db, 208000000);
 /* device and clock bindings */
 static struct clk_lookup pxa168_clkregs[] = {
        INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
@@ -82,6 +85,7 @@ static struct clk_lookup pxa168_clkregs[] = {
        INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL),
        INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL),
        INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL),
+        INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
 };
 static int __init pxa168_init(void)
@@ -127,3 +131,4 @@ PXA168_DEVICE(pwm1, "pxa168-pwm", 0, NONE, 0xd401a000, 0x10);
 PXA168_DEVICE(pwm2, "pxa168-pwm", 1, NONE, 0xd401a400, 0x10);
 PXA168_DEVICE(pwm3, "pxa168-pwm", 2, NONE, 0xd401a800, 0x10);
 PXA168_DEVICE(pwm4, "pxa168-pwm", 3, NONE, 0xd401ac00, 0x10);
+PXA168_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x80, 97, 99);
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index 5882ca6b49fb..d4049508a4df 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -110,6 +110,8 @@ static APBC_CLK(pwm2, PXA910_PWM2, 1, 13000000);
 static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000);
 static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000);
+static APMU_CLK(nand, NAND, 0x01db, 208000000);
 /* device and clock bindings */
 static struct clk_lookup pxa910_clkregs[] = {
        INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
@@ -120,6 +122,7 @@ static struct clk_lookup pxa910_clkregs[] = {
        INIT_CLKREG(&clk_pwm2, "pxa910-pwm.1", NULL),
        INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL),
        INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL),
+        INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
 };
 static int __init pxa910_init(void)
@@ -174,3 +177,4 @@ PXA910_DEVICE(pwm1, "pxa910-pwm", 0, NONE, 0xd401a000, 0x10);
 PXA910_DEVICE(pwm2, "pxa910-pwm", 1, NONE, 0xd401a400, 0x10);
 PXA910_DEVICE(pwm3, "pxa910-pwm", 2, NONE, 0xd401a800, 0x10);
 PXA910_DEVICE(pwm4, "pxa910-pwm", 3, NONE, 0xd401ac00, 0x10);
+PXA910_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x80, 97, 99);
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
index 08cfef6c92a2..8f49b2b12608 100644
--- a/arch/arm/mach-mmp/ttc_dkb.c
+++ b/arch/arm/mach-mmp/ttc_dkb.c
@@ -11,9 +11,13 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/onenand.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
 #include <mach/addr-map.h>
 #include <mach/mfp-pxa910.h>
 #include <mach/pxa910.h>
@@ -26,6 +30,86 @@ static unsigned long ttc_dkb_pin_config[] __initdata = {
        /* UART2 */
        GPIO47_UART2_RXD,
        GPIO48_UART2_TXD,
+        /* DFI */
+        DF_IO0_ND_IO0,
+        DF_IO1_ND_IO1,
+        DF_IO2_ND_IO2,
+        DF_IO3_ND_IO3,
+        DF_IO4_ND_IO4,
+        DF_IO5_ND_IO5,
+        DF_IO6_ND_IO6,
+        DF_IO7_ND_IO7,
+        DF_IO8_ND_IO8,
+        DF_IO9_ND_IO9,
+        DF_IO10_ND_IO10,
+        DF_IO11_ND_IO11,
+        DF_IO12_ND_IO12,
+        DF_IO13_ND_IO13,
+        DF_IO14_ND_IO14,
+        DF_IO15_ND_IO15,
+        DF_nCS0_SM_nCS2_nCS0,
+        DF_ALE_SM_WEn_ND_ALE,
+        DF_CLE_SM_OEn_ND_CLE,
+        DF_WEn_DF_WEn,
+        DF_REn_DF_REn,
+        DF_RDY0_DF_RDY0,
+};
+static struct mtd_partition ttc_dkb_onenand_partitions[] = {
+        {
+                .name           = "bootloader",
+                .offset         = 0,
+                .size           = SZ_1M,
+                .mask_flags     = MTD_WRITEABLE,
+        }, {
+                .name           = "reserved",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = SZ_128K,
+                .mask_flags     = MTD_WRITEABLE,
+        }, {
+                .name           = "reserved",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = SZ_8M,
+                .mask_flags     = MTD_WRITEABLE,
+        }, {
+                .name           = "kernel",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = (SZ_2M + SZ_1M),
+                .mask_flags     = 0,
+        }, {
+                .name           = "filesystem",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = SZ_48M,
+                .mask_flags     = 0,
+        }
+};
+static struct onenand_platform_data ttc_dkb_onenand_info = {
+        .parts          = ttc_dkb_onenand_partitions,
+        .nr_parts       = ARRAY_SIZE(ttc_dkb_onenand_partitions),
+};
+static struct resource ttc_dkb_resource_onenand[] = {
+        [0] = {
+                .start  = SMC_CS0_PHYS_BASE,
+                .end    = SMC_CS0_PHYS_BASE + SZ_1M,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+static struct platform_device ttc_dkb_device_onenand = {
+        .name           = "onenand-flash",
+        .id             = -1,
+        .resource       = ttc_dkb_resource_onenand,
+        .num_resources  = ARRAY_SIZE(ttc_dkb_resource_onenand),
+        .dev            = {
+                .platform_data  = &ttc_dkb_onenand_info,
+        },
+};
+static struct platform_device *ttc_dkb_devices[] = {
+        &ttc_dkb_device_onenand,
 };
 static void __init ttc_dkb_init(void)
@@ -34,6 +118,9 @@ static void __init ttc_dkb_init(void)
        /* on-chip devices */
        pxa910_add_uart(1);
+        /* off-chip devices */
+        platform_add_devices(ARRAY_AND_SIZE(ttc_dkb_devices));
 }
 MACHINE_START(TTC_DKB, "PXA910-based TTC_DKB Development Platform")
diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-mx2/Kconfig
index c8a2eac4d13c..b96c6a389363 100644
--- a/arch/arm/mach-mx2/Kconfig
+++ b/arch/arm/mach-mx2/Kconfig
@@ -6,11 +6,13 @@ choice
 config MACH_MX21
        bool "i.MX21 support"
+        select ARCH_MXC_AUDMUX_V1
        help
          This enables support for Freescale's MX2 based i.MX21 processor.
 config MACH_MX27
        bool "i.MX27 support"
+        select ARCH_MXC_AUDMUX_V1
        help
          This enables support for Freescale's MX2 based i.MX27 processor.
@@ -102,4 +104,11 @@ config MACH_PCA100
          Include support for phyCARD-s (aka pca100) platform. This
          includes specific configurations for the module and its peripherals.
+config MACH_MXT_TD60
+        bool "Maxtrack i-MXT TD60"
+        depends on MACH_MX27
+        help
+          Include support for i-MXT (aka td60) platform. This
+          includes specific configurations for the module and its peripherals.
 endif
diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile
index 19560f045632..52aca0aaf9b5 100644
--- a/arch/arm/mach-mx2/Makefile
+++ b/arch/arm/mach-mx2/Makefile
@@ -20,4 +20,5 @@ obj-$(CONFIG_MACH_MX27LITE) += mx27lite.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX27) += eukrea_cpuimx27.o
 obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
 obj-$(CONFIG_MACH_PCA100) += pca100.o
+obj-$(CONFIG_MACH_MXT_TD60) += mxt_td60.o
diff --git a/arch/arm/mach-mx2/clock_imx21.c b/arch/arm/mach-mx2/clock_imx21.c
index eede79855f4a..91901b5d56c2 100644
--- a/arch/arm/mach-mx2/clock_imx21.c
+++ b/arch/arm/mach-mx2/clock_imx21.c
@@ -1000,7 +1000,7 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href)
        clk_enable(&per_clk[0]);
        clk_enable(&gpio_clk);
-#ifdef CONFIG_DEBUG_LL_CONSOLE
+#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
        clk_enable(&uart_clk[0]);
 #endif
diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c
index ff5e33298914..b010bf9ceaab 100644
--- a/arch/arm/mach-mx2/clock_imx27.c
+++ b/arch/arm/mach-mx2/clock_imx27.c
@@ -651,8 +651,8 @@ static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk1)
        _REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk)
        _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk1)
-        _REGISTER_CLOCK(NULL, "ssi1", ssi1_clk)
+        _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
-        _REGISTER_CLOCK(NULL, "ssi2", ssi2_clk)
+        _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
        _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
        _REGISTER_CLOCK(NULL, "vpu", vpu_clk)
        _REGISTER_CLOCK(NULL, "dma", dma_clk)
@@ -751,7 +751,7 @@ int __init mx27_clocks_init(unsigned long fref)
        clk_enable(&emi_clk);
        clk_enable(&iim_clk);
-#ifdef CONFIG_DEBUG_LL_CONSOLE
+#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
        clk_enable(&uart1_clk);
 #endif
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c
index 50199aff0143..3d398ce09b31 100644
--- a/arch/arm/mach-mx2/devices.c
+++ b/arch/arm/mach-mx2/devices.c
@@ -530,6 +530,84 @@ struct platform_device mxc_usbh2 = {
 };
 #endif
+static struct resource imx_ssi_resources0[] = {
+        {
+                .start  = SSI1_BASE_ADDR,
+                .end    = SSI1_BASE_ADDR + 0x6F,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = MXC_INT_SSI1,
+                .end    = MXC_INT_SSI1,
+                .flags  = IORESOURCE_IRQ,
+        }, {
+                .name   = "tx0",
+                .start  = DMA_REQ_SSI1_TX0,
+                .end    = DMA_REQ_SSI1_TX0,
+                .flags  = IORESOURCE_DMA,
+        }, {
+                .name   = "rx0",
+                .start  = DMA_REQ_SSI1_RX0,
+                .end    = DMA_REQ_SSI1_RX0,
+                .flags  = IORESOURCE_DMA,
+        }, {
+                .name   = "tx1",
+                .start  = DMA_REQ_SSI1_TX1,
+                .end    = DMA_REQ_SSI1_TX1,
+                .flags  = IORESOURCE_DMA,
+        }, {
+                .name   = "rx1",
+                .start  = DMA_REQ_SSI1_RX1,
+                .end    = DMA_REQ_SSI1_RX1,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+static struct resource imx_ssi_resources1[] = {
+        {
+                .start  = SSI2_BASE_ADDR,
+                .end    = SSI2_BASE_ADDR + 0x6F,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = MXC_INT_SSI2,
+                .end    = MXC_INT_SSI2,
+                .flags  = IORESOURCE_IRQ,
+        }, {
+                .name   = "tx0",
+                .start  = DMA_REQ_SSI2_TX0,
+                .end    = DMA_REQ_SSI2_TX0,
+                .flags  = IORESOURCE_DMA,
+        }, {
+                .name   = "rx0",
+                .start  = DMA_REQ_SSI2_RX0,
+                .end    = DMA_REQ_SSI2_RX0,
+                .flags  = IORESOURCE_DMA,
+        }, {
+                .name   = "tx1",
+                .start  = DMA_REQ_SSI2_TX1,
+                .end    = DMA_REQ_SSI2_TX1,
+                .flags  = IORESOURCE_DMA,
+        }, {
+                .name   = "rx1",
+                .start  = DMA_REQ_SSI2_RX1,
+                .end    = DMA_REQ_SSI2_RX1,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+struct platform_device imx_ssi_device0 = {
+        .name = "imx-ssi",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(imx_ssi_resources0),
+        .resource = imx_ssi_resources0,
+};
+struct platform_device imx_ssi_device1 = {
+        .name = "imx-ssi",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(imx_ssi_resources1),
+        .resource = imx_ssi_resources1,
+};
 /* GPIO port description */
 static struct mxc_gpio_port imx_gpio_ports[] = {
        {
diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-mx2/devices.h
index d315406d6725..97306aa18f1c 100644
--- a/arch/arm/mach-mx2/devices.h
+++ b/arch/arm/mach-mx2/devices.h
@@ -26,4 +26,5 @@ extern struct platform_device mxc_usbh2;
 extern struct platform_device mxc_spi_device0;
 extern struct platform_device mxc_spi_device1;
 extern struct platform_device mxc_spi_device2;
+extern struct platform_device imx_ssi_device0;
+extern struct platform_device imx_ssi_device1;
diff --git a/arch/arm/mach-mx2/mxt_td60.c b/arch/arm/mach-mx2/mxt_td60.c
new file mode 100644
index 000000000000..03dbbdc98955
--- /dev/null
+++ b/arch/arm/mach-mx2/mxt_td60.c
@@ -0,0 +1,319 @@
+/*
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *  Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/i2c.h>
+#include <linux/irq.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <linux/gpio.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux.h>
+#include <mach/mxc_nand.h>
+#include <mach/i2c.h>
+#include <linux/i2c/pca953x.h>
+#include <mach/imxfb.h>
+#include <mach/mmc.h>
+#include "devices.h"
+static unsigned int mxt_td60_pins[] __initdata = {
+        /* UART0 */
+        PE12_PF_UART1_TXD,
+        PE13_PF_UART1_RXD,
+        PE14_PF_UART1_CTS,
+        PE15_PF_UART1_RTS,
+        /* UART1 */
+        PE3_PF_UART2_CTS,
+        PE4_PF_UART2_RTS,
+        PE6_PF_UART2_TXD,
+        PE7_PF_UART2_RXD,
+        /* UART2 */
+        PE8_PF_UART3_TXD,
+        PE9_PF_UART3_RXD,
+        PE10_PF_UART3_CTS,
+        PE11_PF_UART3_RTS,
+        /* UART3 */
+        PB26_AF_UART4_RTS,
+        PB28_AF_UART4_TXD,
+        PB29_AF_UART4_CTS,
+        PB31_AF_UART4_RXD,
+        /* UART4 */
+        PB18_AF_UART5_TXD,
+        PB19_AF_UART5_RXD,
+        PB20_AF_UART5_CTS,
+        PB21_AF_UART5_RTS,
+        /* UART5 */
+        PB10_AF_UART6_TXD,
+        PB12_AF_UART6_CTS,
+        PB11_AF_UART6_RXD,
+        PB13_AF_UART6_RTS,
+        /* FEC */
+        PD0_AIN_FEC_TXD0,
+        PD1_AIN_FEC_TXD1,
+        PD2_AIN_FEC_TXD2,
+        PD3_AIN_FEC_TXD3,
+        PD4_AOUT_FEC_RX_ER,
+        PD5_AOUT_FEC_RXD1,
+        PD6_AOUT_FEC_RXD2,
+        PD7_AOUT_FEC_RXD3,
+        PD8_AF_FEC_MDIO,
+        PD9_AIN_FEC_MDC,
+        PD10_AOUT_FEC_CRS,
+        PD11_AOUT_FEC_TX_CLK,
+        PD12_AOUT_FEC_RXD0,
+        PD13_AOUT_FEC_RX_DV,
+        PD14_AOUT_FEC_RX_CLK,
+        PD15_AOUT_FEC_COL,
+        PD16_AIN_FEC_TX_ER,
+        PF23_AIN_FEC_TX_EN,
+        /* I2C1 */
+        PD17_PF_I2C_DATA,
+        PD18_PF_I2C_CLK,
+        /* I2C2 */
+        PC5_PF_I2C2_SDA,
+        PC6_PF_I2C2_SCL,
+        /* FB */
+        PA5_PF_LSCLK,
+        PA6_PF_LD0,
+        PA7_PF_LD1,
+        PA8_PF_LD2,
+        PA9_PF_LD3,
+        PA10_PF_LD4,
+        PA11_PF_LD5,
+        PA12_PF_LD6,
+        PA13_PF_LD7,
+        PA14_PF_LD8,
+        PA15_PF_LD9,
+        PA16_PF_LD10,
+        PA17_PF_LD11,
+        PA18_PF_LD12,
+        PA19_PF_LD13,
+        PA20_PF_LD14,
+        PA21_PF_LD15,
+        PA22_PF_LD16,
+        PA23_PF_LD17,
+        PA25_PF_CLS,
+        PA27_PF_SPL_SPR,
+        PA28_PF_HSYNC,
+        PA29_PF_VSYNC,
+        PA30_PF_CONTRAST,
+        PA31_PF_OE_ACD,
+        /* OWIRE */
+        PE16_AF_OWIRE,
+        /* SDHC1*/
+        PE18_PF_SD1_D0,
+        PE19_PF_SD1_D1,
+        PE20_PF_SD1_D2,
+        PE21_PF_SD1_D3,
+        PE22_PF_SD1_CMD,
+        PE23_PF_SD1_CLK,
+        PF8_AF_ATA_IORDY,
+        /* SDHC2*/
+        PB4_PF_SD2_D0,
+        PB5_PF_SD2_D1,
+        PB6_PF_SD2_D2,
+        PB7_PF_SD2_D3,
+        PB8_PF_SD2_CMD,
+        PB9_PF_SD2_CLK,
+};
+static struct mxc_nand_platform_data mxt_td60_nand_board_info = {
+        .width = 1,
+        .hw_ecc = 1,
+};
+static struct imxi2c_platform_data mxt_td60_i2c_data = {
+        .bitrate = 100000,
+};
+/* PCA9557 */
+static int mxt_td60_pca9557_setup(struct i2c_client *client,
+                                unsigned gpio_base, unsigned ngpio,
+                                void *context)
+{
+        static int mxt_td60_gpio_value[] = {
+                -1, -1, -1, -1, -1, -1, -1, 1
+        };
+        int n;
+        for (n = 0; n < ARRAY_SIZE(mxt_td60_gpio_value); ++n) {
+                gpio_request(gpio_base + n, "MXT_TD60 GPIO Exp");
+                if (mxt_td60_gpio_value[n] < 0)
+                        gpio_direction_input(gpio_base + n);
+                else
+                        gpio_direction_output(gpio_base + n,
+                                                mxt_td60_gpio_value[n]);
+                gpio_export(gpio_base + n, 0);
+        }
+        return 0;
+}
+static struct pca953x_platform_data mxt_td60_pca9557_pdata = {
+        .gpio_base      = 240, /* place PCA9557 after all MX27 gpio pins */
+        .invert         = 0, /* Do not invert */
+        .setup          = mxt_td60_pca9557_setup,
+};
+static struct i2c_board_info mxt_td60_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("pca9557", 0x18),
+                .platform_data = &mxt_td60_pca9557_pdata,
+        },
+};
+static struct imxi2c_platform_data mxt_td60_i2c2_data = {
+        .bitrate = 100000,
+};
+static struct i2c_board_info mxt_td60_i2c2_devices[] = {
+};
+static struct imx_fb_videomode mxt_td60_modes[] = {
+        {
+                .mode = {
+                        .name           = "Chimei LW700AT9003",
+                        .refresh        = 60,
+                        .xres           = 800,
+                        .yres           = 480,
+                        .pixclock       = 30303,
+                        .hsync_len      = 64,
+                        .left_margin    = 0x67,
+                        .right_margin   = 0x68,
+                        .vsync_len      = 16,
+                        .upper_margin   = 0x0f,
+                        .lower_margin   = 0x0f,
+                },
+                .bpp            = 16,
+                .pcr            = 0xFA208B83,
+        },
+};
+static struct imx_fb_platform_data mxt_td60_fb_data = {
+        .mode = mxt_td60_modes,
+        .num_modes = ARRAY_SIZE(mxt_td60_modes),
+        /*
+         * - HSYNC active high
+         * - VSYNC active high
+         * - clk notenabled while idle
+         * - clock inverted
+         * - data not inverted
+         * - data enable low active
+         * - enable sharp mode
+         */
+        .pwmr           = 0x00A903FF,
+        .lscr1          = 0x00120300,
+        .dmacr          = 0x00020010,
+};
+static int mxt_td60_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
+                                void *data)
+{
+        return request_irq(IRQ_GPIOF(8), detect_irq, IRQF_TRIGGER_FALLING,
+                                "sdhc1-card-detect", data);
+}
+static void mxt_td60_sdhc1_exit(struct device *dev, void *data)
+{
+        free_irq(IRQ_GPIOF(8), data);
+}
+static struct imxmmc_platform_data sdhc1_pdata = {
+        .init = mxt_td60_sdhc1_init,
+        .exit = mxt_td60_sdhc1_exit,
+};
+static struct platform_device *platform_devices[] __initdata = {
+        &mxc_fec_device,
+};
+static struct imxuart_platform_data uart_pdata[] = {
+        {
+                .flags = IMXUART_HAVE_RTSCTS,
+        }, {
+                .flags = IMXUART_HAVE_RTSCTS,
+        }, {
+                .flags = IMXUART_HAVE_RTSCTS,
+        }, {
+                .flags = IMXUART_HAVE_RTSCTS,
+        }, {
+                .flags = IMXUART_HAVE_RTSCTS,
+        }, {
+                .flags = IMXUART_HAVE_RTSCTS,
+        },
+};
+static void __init mxt_td60_board_init(void)
+{
+        mxc_gpio_setup_multiple_pins(mxt_td60_pins, ARRAY_SIZE(mxt_td60_pins),
+                        "MXT_TD60");
+        mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
+        mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
+        mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
+        mxc_register_device(&mxc_uart_device3, &uart_pdata[3]);
+        mxc_register_device(&mxc_uart_device4, &uart_pdata[4]);
+        mxc_register_device(&mxc_uart_device5, &uart_pdata[5]);
+        mxc_register_device(&mxc_nand_device, &mxt_td60_nand_board_info);
+        i2c_register_board_info(0, mxt_td60_i2c_devices,
+                                ARRAY_SIZE(mxt_td60_i2c_devices));
+        i2c_register_board_info(1, mxt_td60_i2c2_devices,
+                                ARRAY_SIZE(mxt_td60_i2c2_devices));
+        mxc_register_device(&mxc_i2c_device0, &mxt_td60_i2c_data);
+        mxc_register_device(&mxc_i2c_device1, &mxt_td60_i2c2_data);
+        mxc_register_device(&mxc_fb_device, &mxt_td60_fb_data);
+        mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
+        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
+static void __init mxt_td60_timer_init(void)
+{
+        mx27_clocks_init(26000000);
+}
+static struct sys_timer mxt_td60_timer = {
+        .init   = mxt_td60_timer_init,
+};
+MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60")
+        /* maintainer: Maxtrack Industrial */
+        .phys_io        = AIPI_BASE_ADDR,
+        .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = mx27_map_io,
+        .init_irq       = mx27_init_irq,
+        .init_machine   = mxt_td60_board_init,
+        .timer          = &mxt_td60_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx2/pca100.c b/arch/arm/mach-mx2/pca100.c
index fe5b165b88cc..aea3d340d2e1 100644
--- a/arch/arm/mach-mx2/pca100.c
+++ b/arch/arm/mach-mx2/pca100.c
@@ -237,7 +237,7 @@ MACHINE_START(PCA100, "phyCARD-i.MX27")
        .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
        .boot_params    = PHYS_OFFSET + 0x100,
        .map_io         = mx27_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx27_init_irq,
        .init_machine   = pca100_init,
        .timer          = &pca100_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 851f2458bf65..ea8ed109a7c2 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -2,11 +2,13 @@ if ARCH_MX3
 config ARCH_MX31
        select ARCH_HAS_RNGA
+        select ARCH_MXC_AUDMUX_V2
        bool
 config ARCH_MX35
        bool
        select ARCH_MXC_IOMUX_V3
+        select ARCH_MXC_AUDMUX_V2
 comment "MX3 platforms:"
@@ -61,6 +63,7 @@ config MACH_MX31_3DS
 config MACH_MX31MOBOARD
        bool "Support mx31moboard platforms (EPFL Mobots group)"
        select ARCH_MX31
+        select MXC_ULPI
        help
          Include support for mx31moboard platform. This includes specific
          configurations for the board and its peripherals.
@@ -100,4 +103,12 @@ config MACH_MX35_3DS
        help
          Include support for MX35PDK platform. This includes specific
          configurations for the board and its peripherals.
+config MACH_KZM_ARM11_01
+        bool "Support KZM-ARM11-01(Kyoto Microcomputer)"
+        select ARCH_MX31
+        help
+          Include support for KZM-ARM11-01. This includes specific
+          configurations for the board and its peripherals.
 endif
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
index 6b9775471be6..93c7b296be6a 100644
--- a/arch/arm/mach-mx3/Makefile
+++ b/arch/arm/mach-mx3/Makefile
@@ -4,12 +4,12 @@
 # Object file lists.
-obj-y                           := mm.o devices.o
+obj-y                           := mm.o devices.o cpu.o
 obj-$(CONFIG_ARCH_MX31)         += clock.o iomux.o
 obj-$(CONFIG_ARCH_MX35)         += clock-imx35.o
 obj-$(CONFIG_MACH_MX31ADS)      += mx31ads.o
 obj-$(CONFIG_MACH_MX31LILLY)    += mx31lilly.o mx31lilly-db.o
-obj-$(CONFIG_MACH_MX31LITE)     += mx31lite.o
+obj-$(CONFIG_MACH_MX31LITE)     += mx31lite.o mx31lite-db.o
 obj-$(CONFIG_MACH_PCM037)       += pcm037.o
 obj-$(CONFIG_MACH_PCM037_EET)   += pcm037_eet.o
 obj-$(CONFIG_MACH_MX31_3DS)     += mx31pdk.o
@@ -19,3 +19,4 @@ obj-$(CONFIG_MACH_QONG)		+= qong.o
 obj-$(CONFIG_MACH_PCM043)       += pcm043.o
 obj-$(CONFIG_MACH_ARMADILLO5X0) += armadillo5x0.o
 obj-$(CONFIG_MACH_MX35_3DS)     += mx35pdk.o
+obj-$(CONFIG_MACH_KZM_ARM11_01) += kzmarm11.o
diff --git a/arch/arm/mach-mx3/armadillo5x0.c b/arch/arm/mach-mx3/armadillo5x0.c
index 776c0ee1b3cd..54aab401dbdf 100644
--- a/arch/arm/mach-mx3/armadillo5x0.c
+++ b/arch/arm/mach-mx3/armadillo5x0.c
@@ -33,6 +33,9 @@
 #include <linux/irq.h>
 #include <linux/mtd/physmap.h>
 #include <linux/io.h>
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+#include <linux/i2c.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -97,6 +100,47 @@ static int armadillo5x0_pins[] = {
        MX31_PIN_FPSHIFT__FPSHIFT,
        MX31_PIN_DRDY0__DRDY0,
        IOMUX_MODE(MX31_PIN_LCS1, IOMUX_CONFIG_GPIO), /*ADV7125_PSAVE*/
+        /* I2C2 */
+        MX31_PIN_CSPI2_MOSI__SCL,
+        MX31_PIN_CSPI2_MISO__SDA,
+};
+/* RTC over I2C*/
+#define ARMADILLO5X0_RTC_GPIO   IOMUX_TO_GPIO(MX31_PIN_SRXD4)
+static struct i2c_board_info armadillo5x0_i2c_rtc = {
+        I2C_BOARD_INFO("s35390a", 0x30),
+};
+/* GPIO BUTTONS */
+static struct gpio_keys_button armadillo5x0_buttons[] = {
+        {
+                .code           = KEY_ENTER, /*28*/
+                .gpio           = IOMUX_TO_GPIO(MX31_PIN_SCLK0),
+                .active_low     = 1,
+                .desc           = "menu",
+                .wakeup         = 1,
+        }, {
+                .code           = KEY_BACK, /*158*/
+                .gpio           = IOMUX_TO_GPIO(MX31_PIN_SRST0),
+                .active_low     = 1,
+                .desc           = "back",
+                .wakeup         = 1,
+        }
+};
+static struct gpio_keys_platform_data armadillo5x0_button_data = {
+        .buttons        = armadillo5x0_buttons,
+        .nbuttons       = ARRAY_SIZE(armadillo5x0_buttons),
+};
+static struct platform_device armadillo5x0_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &armadillo5x0_button_data,
+        }
 };
 /*
@@ -278,7 +322,7 @@ static struct resource armadillo5x0_smc911x_resources[] = {
 };
 static struct smsc911x_platform_config smsc911x_info = {
-        .flags          = SMSC911X_USE_32BIT,
+        .flags          = SMSC911X_USE_16BIT,
        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
 };
@@ -300,6 +344,8 @@ static struct imxuart_platform_data uart_pdata = {
 static struct platform_device *devices[] __initdata = {
        &armadillo5x0_smc911x_device,
+        &mxc_i2c_device1,
+        &armadillo5x0_button_device,
 };
 /*
@@ -335,6 +381,18 @@ static void __init armadillo5x0_init(void)
        /* set NAND page size to 2k if not configured via boot mode pins */
        __raw_writel(__raw_readl(MXC_CCM_RCSR) | (1 << 30), MXC_CCM_RCSR);
+        /* RTC */
+        /* Get RTC IRQ and register the chip */
+        if (gpio_request(ARMADILLO5X0_RTC_GPIO, "rtc") == 0) {
+                if (gpio_direction_input(ARMADILLO5X0_RTC_GPIO) == 0)
+                        armadillo5x0_i2c_rtc.irq = gpio_to_irq(ARMADILLO5X0_RTC_GPIO);
+                else
+                        gpio_free(ARMADILLO5X0_RTC_GPIO);
+        }
+        if (armadillo5x0_i2c_rtc.irq == 0)
+                pr_warning("armadillo5x0_init: failed to get RTC IRQ\n");
+        i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1);
 }
 static void __init armadillo5x0_timer_init(void)
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c
index c595260ec1f9..7584b4c6c556 100644
--- a/arch/arm/mach-mx3/clock-imx35.c
+++ b/arch/arm/mach-mx3/clock-imx35.c
@@ -335,7 +335,7 @@ static void clk_cgr_disable(struct clk *clk)
 DEFINE_CLOCK(asrc_clk,   0, CCM_CGR0,  0, NULL, NULL);
 DEFINE_CLOCK(ata_clk,    0, CCM_CGR0,  2, get_rate_ipg, NULL);
-DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0,  4, NULL, NULL);
+/* DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0,  4, NULL, NULL); */
 DEFINE_CLOCK(can1_clk,   0, CCM_CGR0,  6, get_rate_ipg, NULL);
 DEFINE_CLOCK(can2_clk,   1, CCM_CGR0,  8, get_rate_ipg, NULL);
 DEFINE_CLOCK(cspi1_clk,  0, CCM_CGR0, 10, get_rate_ipg, NULL);
@@ -381,12 +381,43 @@ DEFINE_CLOCK(uart3_clk,  2, CCM_CGR2, 20, get_rate_uart, NULL);
 DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, get_rate_otg, NULL);
 DEFINE_CLOCK(wdog_clk,   0, CCM_CGR2, 24, NULL, NULL);
 DEFINE_CLOCK(max_clk,    0, CCM_CGR2, 26, NULL, NULL);
-DEFINE_CLOCK(admux_clk,  0, CCM_CGR2, 30, NULL, NULL);
+DEFINE_CLOCK(audmux_clk, 0, CCM_CGR2, 30, NULL, NULL);
 DEFINE_CLOCK(csi_clk,    0, CCM_CGR3,  0, get_rate_csi, NULL);
 DEFINE_CLOCK(iim_clk,    0, CCM_CGR3,  2, NULL, NULL);
 DEFINE_CLOCK(gpu2d_clk,  0, CCM_CGR3,  4, NULL, NULL);
+DEFINE_CLOCK(usbahb_clk, 0, 0,         0, get_rate_ahb, NULL);
+static int clk_dummy_enable(struct clk *clk)
+{
+        return 0;
+}
+static void clk_dummy_disable(struct clk *clk)
+{
+}
+static unsigned long get_rate_nfc(struct clk *clk)
+{
+        unsigned long div1;
+        div1 = (__raw_readl(CCM_BASE + CCM_PDR4) >> 28) + 1;
+        return get_rate_ahb(NULL) / div1;
+}
+/* NAND Controller: It seems it can't be disabled */
+static struct clk nfc_clk = {
+        .id             = 0,
+        .enable_reg     = 0,
+        .enable_shift   = 0,
+        .get_rate       = get_rate_nfc,
+        .set_rate       = NULL, /* set_rate_nfc, */
+        .enable         = clk_dummy_enable,
+        .disable        = clk_dummy_disable
+};
 #define _REGISTER_CLOCK(d, n, c)        \
        {                               \
                .dev_id = d,            \
@@ -397,7 +428,6 @@ DEFINE_CLOCK(gpu2d_clk,  0, CCM_CGR3,  4, NULL, NULL);
 static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK(NULL, "asrc", asrc_clk)
        _REGISTER_CLOCK(NULL, "ata", ata_clk)
-        _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
        _REGISTER_CLOCK(NULL, "can", can1_clk)
        _REGISTER_CLOCK(NULL, "can", can2_clk)
        _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
@@ -434,8 +464,8 @@ static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK(NULL, "sdma", sdma_clk)
        _REGISTER_CLOCK(NULL, "spba", spba_clk)
        _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
-        _REGISTER_CLOCK(NULL, "ssi", ssi1_clk)
+        _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
-        _REGISTER_CLOCK(NULL, "ssi", ssi2_clk)
+        _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
        _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
        _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
        _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
@@ -443,12 +473,14 @@ static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk)
        _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
        _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
+        _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usbahb_clk)
        _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk)
        _REGISTER_CLOCK(NULL, "max", max_clk)
-        _REGISTER_CLOCK(NULL, "admux", admux_clk)
+        _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
        _REGISTER_CLOCK(NULL, "csi", csi_clk)
        _REGISTER_CLOCK(NULL, "iim", iim_clk)
        _REGISTER_CLOCK(NULL, "gpu2d", gpu2d_clk)
+        _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
 };
 int __init mx35_clocks_init()
@@ -456,7 +488,7 @@ int __init mx35_clocks_init()
        int i;
        unsigned int ll = 0;
-#ifdef CONFIG_DEBUG_LL_CONSOLE
+#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
        ll = (3 << 16);
 #endif
diff --git a/arch/arm/mach-mx3/clock.c b/arch/arm/mach-mx3/clock.c
index b2a3bcf8266e..27a318af0d20 100644
--- a/arch/arm/mach-mx3/clock.c
+++ b/arch/arm/mach-mx3/clock.c
@@ -558,8 +558,8 @@ static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk)
        _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
        _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
-        _REGISTER_CLOCK(NULL, "ssi", ssi1_clk)
+        _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
-        _REGISTER_CLOCK(NULL, "ssi", ssi2_clk)
+        _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
        _REGISTER_CLOCK(NULL, "firi", firi_clk)
        _REGISTER_CLOCK(NULL, "ata", ata_clk)
        _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
@@ -616,6 +616,8 @@ int __init mx31_clocks_init(unsigned long fref)
        clk_enable(&serial_pll_clk);
+        mx31_read_cpu_rev();
        if (mx31_revision() >= CHIP_REV_2_0) {
                reg = __raw_readl(MXC_CCM_PMCR1);
                /* No PLL restart on DVFS switch; enable auto EMI handshake */
diff --git a/arch/arm/mach-mx3/cpu.c b/arch/arm/mach-mx3/cpu.c
new file mode 100644
index 000000000000..db828809c675
--- /dev/null
+++ b/arch/arm/mach-mx3/cpu.c
@@ -0,0 +1,57 @@
+/*
+ * MX3 CPU type detection
+ *
+ * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/iim.h>
+unsigned int mx31_cpu_rev;
+EXPORT_SYMBOL(mx31_cpu_rev);
+struct mx3_cpu_type {
+        u8 srev;
+        const char *name;
+        const char *v;
+        unsigned int rev;
+};
+static struct mx3_cpu_type mx31_cpu_type[] __initdata = {
+        { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0",  .rev = CHIP_REV_1_0   },
+        { .srev = 0x10, .name = "i.MX31",    .v = "1.1",  .rev = CHIP_REV_1_1   },
+        { .srev = 0x11, .name = "i.MX31L",   .v = "1.1",  .rev = CHIP_REV_1_1   },
+        { .srev = 0x12, .name = "i.MX31",    .v = "1.15", .rev = CHIP_REV_1_1   },
+        { .srev = 0x13, .name = "i.MX31L",   .v = "1.15", .rev = CHIP_REV_1_1   },
+        { .srev = 0x14, .name = "i.MX31",    .v = "1.2",  .rev = CHIP_REV_1_2   },
+        { .srev = 0x15, .name = "i.MX31L",   .v = "1.2",  .rev = CHIP_REV_1_2   },
+        { .srev = 0x28, .name = "i.MX31",    .v = "2.0",  .rev = CHIP_REV_2_0   },
+        { .srev = 0x29, .name = "i.MX31L",   .v = "2.0",  .rev = CHIP_REV_2_0   },
+};
+void __init mx31_read_cpu_rev(void)
+{
+        u32 i, srev;
+        /* read SREV register from IIM module */
+        srev = __raw_readl(IO_ADDRESS(IIM_BASE_ADDR) + MXC_IIMSREV);
+        for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
+                if (srev == mx31_cpu_type[i].srev) {
+                        printk(KERN_INFO
+                                "CPU identified as %s, silicon rev %s\n",
+                                mx31_cpu_type[i].name, mx31_cpu_type[i].v);
+                        mx31_cpu_rev = mx31_cpu_type[i].rev;
+                        return;
+                }
+        printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev);
+}
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index e6abe181b967..6adb586515ea 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -537,6 +537,44 @@ struct platform_device mxc_fec_device = {
 };
 #endif
+static struct resource imx_ssi_resources0[] = {
+        {
+                .start  = SSI1_BASE_ADDR,
+                .end    = SSI1_BASE_ADDR + 0xfff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = MX31_INT_SSI1,
+                .end    = MX31_INT_SSI1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct resource imx_ssi_resources1[] = {
+        {
+                .start  = SSI2_BASE_ADDR,
+                .end    = SSI2_BASE_ADDR + 0xfff,
+                .flags  = IORESOURCE_MEM
+        }, {
+                .start  = MX31_INT_SSI2,
+                .end    = MX31_INT_SSI2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+struct platform_device imx_ssi_device0 = {
+        .name = "imx-ssi",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(imx_ssi_resources0),
+        .resource = imx_ssi_resources0,
+};
+struct platform_device imx_ssi_device1 = {
+        .name = "imx-ssi",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(imx_ssi_resources1),
+        .resource = imx_ssi_resources1,
+};
 static int mx3_devices_init(void)
 {
        if (cpu_is_mx31()) {
@@ -546,7 +584,7 @@ static int mx3_devices_init(void)
        }
        if (cpu_is_mx35()) {
                mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR;
-                mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0xfff;
+                mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0x1fff;
                otg_resources[0].start = MX35_OTG_BASE_ADDR;
                otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff;
                otg_resources[1].start = MXC_INT_USBOTG;
@@ -555,6 +593,10 @@ static int mx3_devices_init(void)
                mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff;
                mxc_usbh1_resources[1].start = MXC_INT_USBHS;
                mxc_usbh1_resources[1].end = MXC_INT_USBHS;
+                imx_ssi_resources0[1].start = MX35_INT_SSI1;
+                imx_ssi_resources0[1].end = MX35_INT_SSI1;
+                imx_ssi_resources1[1].start = MX35_INT_SSI2;
+                imx_ssi_resources1[1].end = MX35_INT_SSI2;
        }
        return 0;
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
index ab87419dc9a0..42cf175eac6b 100644
--- a/arch/arm/mach-mx3/devices.h
+++ b/arch/arm/mach-mx3/devices.h
@@ -23,4 +23,6 @@ extern struct platform_device mxc_rnga_device;
 extern struct platform_device mxc_spi_device0;
 extern struct platform_device mxc_spi_device1;
 extern struct platform_device mxc_spi_device2;
+extern struct platform_device imx_ssi_device0;
+extern struct platform_device imx_ssi_device1;
diff --git a/arch/arm/mach-mx3/kzmarm11.c b/arch/arm/mach-mx3/kzmarm11.c
new file mode 100644
index 000000000000..6fa99ce3008a
--- /dev/null
+++ b/arch/arm/mach-mx3/kzmarm11.c
@@ -0,0 +1,268 @@
+/*
+ * KZM-ARM11-01 support
+ *  Copyright (C) 2009  Yoichi Yuasa <yuasa@linux-mips.org>
+ *
+ * based on code for MX31ADS,
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+#include <linux/smsc911x.h>
+#include <linux/types.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+#include <asm/setup.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <mach/board-kzmarm11.h>
+#include <mach/clock.h>
+#include <mach/common.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx3.h>
+#include <mach/memory.h>
+#include "devices.h"
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+/*
+ * KZM-ARM11-01 has an external UART on FPGA
+ */
+static struct plat_serial8250_port serial_platform_data[] = {
+        {
+                .membase        = IO_ADDRESS(KZM_ARM11_16550),
+                .mapbase        = KZM_ARM11_16550,
+                .irq            = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
+                .irqflags       = IRQ_TYPE_EDGE_RISING,
+                .uartclk        = 14745600,
+                .regshift       = 0,
+                .iotype         = UPIO_MEM,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+                                  UPF_BUGGY_UART,
+        },
+        {},
+};
+static struct resource serial8250_resources[] = {
+        {
+                .start  = KZM_ARM11_16550,
+                .end    = KZM_ARM11_16550 + 0x10,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
+                .end    = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device serial_device = {
+        .name           = "serial8250",
+        .id             = PLAT8250_DEV_PLATFORM,
+        .dev            = {
+                                .platform_data = serial_platform_data,
+                          },
+        .num_resources  = ARRAY_SIZE(serial8250_resources),
+        .resource       = serial8250_resources,
+};
+static int __init kzm_init_ext_uart(void)
+{
+        u8 tmp;
+        /*
+         * GPIO 1-1: external UART interrupt line
+         */
+        mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO));
+        gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "ext-uart-int");
+        gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
+        /*
+         * Unmask UART interrupt
+         */
+        tmp = __raw_readb(IO_ADDRESS(KZM_ARM11_CTL1));
+        tmp |= 0x2;
+        __raw_writeb(tmp, IO_ADDRESS(KZM_ARM11_CTL1));
+        return platform_device_register(&serial_device);
+}
+#else
+static inline int kzm_init_ext_uart(void)
+{
+        return 0;
+}
+#endif
+/*
+ * SMSC LAN9118
+ */
+#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
+static struct smsc911x_platform_config kzm_smsc9118_config = {
+        .phy_interface  = PHY_INTERFACE_MODE_MII,
+        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
+        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
+        .flags          = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
+};
+static struct resource kzm_smsc9118_resources[] = {
+        {
+                .start  = CS5_BASE_ADDR,
+                .end    = CS5_BASE_ADDR + SZ_128K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = IOMUX_TO_IRQ(MX31_PIN_GPIO1_2),
+                .end    = IOMUX_TO_IRQ(MX31_PIN_GPIO1_2),
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
+        },
+};
+static struct platform_device kzm_smsc9118_device = {
+        .name           = "smsc911x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(kzm_smsc9118_resources),
+        .resource       = kzm_smsc9118_resources,
+        .dev            = {
+                                .platform_data = &kzm_smsc9118_config,
+                          },
+};
+static int __init kzm_init_smsc9118(void)
+{
+        /*
+         * GPIO 1-2: SMSC9118 interrupt line
+         */
+        mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_2, IOMUX_CONFIG_GPIO));
+        gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2), "smsc9118-int");
+        gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));
+        return platform_device_register(&kzm_smsc9118_device);
+}
+#else
+static inline int kzm_init_smsc9118(void)
+{
+        return 0;
+}
+#endif
+#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
+static struct imxuart_platform_data uart_pdata = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+static void __init kzm_init_imx_uart(void)
+{
+        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        mxc_register_device(&mxc_uart_device1, &uart_pdata);
+}
+#else
+static inline void kzm_init_imx_uart(void)
+{
+}
+#endif
+static int kzm_pins[] __initdata = {
+        MX31_PIN_CTS1__CTS1,
+        MX31_PIN_RTS1__RTS1,
+        MX31_PIN_TXD1__TXD1,
+        MX31_PIN_RXD1__RXD1,
+        MX31_PIN_DCD_DCE1__DCD_DCE1,
+        MX31_PIN_RI_DCE1__RI_DCE1,
+        MX31_PIN_DSR_DCE1__DSR_DCE1,
+        MX31_PIN_DTR_DCE1__DTR_DCE1,
+        MX31_PIN_CTS2__CTS2,
+        MX31_PIN_RTS2__RTS2,
+        MX31_PIN_TXD2__TXD2,
+        MX31_PIN_RXD2__RXD2,
+        MX31_PIN_DCD_DTE1__DCD_DTE2,
+        MX31_PIN_RI_DTE1__RI_DTE2,
+        MX31_PIN_DSR_DTE1__DSR_DTE2,
+        MX31_PIN_DTR_DTE1__DTR_DTE2,
+};
+/*
+ * Board specific initialization.
+ */
+static void __init kzm_board_init(void)
+{
+        mxc_iomux_setup_multiple_pins(kzm_pins,
+                                      ARRAY_SIZE(kzm_pins), "kzm");
+        kzm_init_ext_uart();
+        kzm_init_smsc9118();
+        kzm_init_imx_uart();
+        pr_info("Clock input source is 26MHz\n");
+}
+/*
+ * This structure defines static mappings for the kzm-arm11-01 board.
+ */
+static struct map_desc kzm_io_desc[] __initdata = {
+        {
+                .virtual        = CS4_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(CS4_BASE_ADDR),
+                .length         = CS4_SIZE,
+                .type           = MT_DEVICE
+        },
+        {
+                .virtual        = CS5_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(CS5_BASE_ADDR),
+                .length         = CS5_SIZE,
+                .type           = MT_DEVICE
+        },
+};
+/*
+ * Set up static virtual mappings.
+ */
+static void __init kzm_map_io(void)
+{
+        mx31_map_io();
+        iotable_init(kzm_io_desc, ARRAY_SIZE(kzm_io_desc));
+}
+static void __init kzm_timer_init(void)
+{
+        mx31_clocks_init(26000000);
+}
+static struct sys_timer kzm_timer = {
+        .init   = kzm_timer_init,
+};
+/*
+ * The following uses standard kernel macros define in arch.h in order to
+ * initialize __mach_desc_KZM_ARM11_01 data structure.
+ */
+MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
+        .phys_io        = AIPS1_BASE_ADDR,
+        .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = kzm_map_io,
+        .init_irq       = mx31_init_irq,
+        .init_machine   = kzm_board_init,
+        .timer          = &kzm_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx3/mx31lilly-db.c b/arch/arm/mach-mx3/mx31lilly-db.c
index 3b3a78f49c23..7aebd74a12e8 100644
--- a/arch/arm/mach-mx3/mx31lilly-db.c
+++ b/arch/arm/mach-mx3/mx31lilly-db.c
@@ -109,6 +109,9 @@ static int mxc_mmc1_get_ro(struct device *dev)
 static int gpio_det, gpio_wp;
+#define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
+                        PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
 static int mxc_mmc1_init(struct device *dev,
                         irq_handler_t detect_irq, void *data)
 {
@@ -117,6 +120,13 @@ static int mxc_mmc1_init(struct device *dev,
        gpio_det = IOMUX_TO_GPIO(MX31_PIN_GPIO1_1);
        gpio_wp = IOMUX_TO_GPIO(MX31_PIN_LCS0);
+        mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, MMC_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, MMC_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, MMC_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, MMC_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SD1_CMD, MMC_PAD_CFG);
        ret = gpio_request(gpio_det, "MMC detect");
        if (ret)
                return ret;
diff --git a/arch/arm/mach-mx3/mx31lilly.c b/arch/arm/mach-mx3/mx31lilly.c
index 423025150f6f..9ce029f554b9 100644
--- a/arch/arm/mach-mx3/mx31lilly.c
+++ b/arch/arm/mach-mx3/mx31lilly.c
@@ -31,6 +31,8 @@
 #include <linux/interrupt.h>
 #include <linux/smsc911x.h>
 #include <linux/mtd/physmap.h>
+#include <linux/spi/spi.h>
+#include <linux/mfd/mc13783.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -41,6 +43,7 @@
 #include <mach/common.h>
 #include <mach/iomux-mx3.h>
 #include <mach/board-mx31lilly.h>
+#include <mach/spi.h>
 #include "devices.h"
@@ -108,7 +111,36 @@ static struct platform_device physmap_flash_device = {
 static struct platform_device *devices[] __initdata = {
        &smsc91x_device,
        &physmap_flash_device,
-        &mxc_i2c_device1,
+};
+/* SPI */
+static int spi_internal_chipselect[] = {
+        MXC_SPI_CS(0),
+        MXC_SPI_CS(1),
+        MXC_SPI_CS(2),
+};
+static struct spi_imx_master spi0_pdata = {
+        .chipselect = spi_internal_chipselect,
+        .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
+};
+static struct spi_imx_master spi1_pdata = {
+        .chipselect = spi_internal_chipselect,
+        .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
+};
+static struct mc13783_platform_data mc13783_pdata __initdata = {
+        .flags = MC13783_USE_RTC | MC13783_USE_TOUCHSCREEN,
+};
+static struct spi_board_info mc13783_dev __initdata = {
+        .modalias       = "mc13783",
+        .max_speed_hz   = 1000000,
+        .bus_num        = 1,
+        .chip_select    = 0,
+        .platform_data  = &mc13783_pdata,
 };
 static int mx31lilly_baseboard;
@@ -128,8 +160,27 @@ static void __init mx31lilly_board_init(void)
        }
        mxc_iomux_alloc_pin(MX31_PIN_CS4__CS4, "Ethernet CS");
-        mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MOSI__SCL, "I2C SCL");
-        mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MISO__SDA, "I2C SDA");
+        /* SPI */
+        mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SCLK__SCLK, "SPI1_CLK");
+        mxc_iomux_alloc_pin(MX31_PIN_CSPI1_MOSI__MOSI, "SPI1_TX");
+        mxc_iomux_alloc_pin(MX31_PIN_CSPI1_MISO__MISO, "SPI1_RX");
+        mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, "SPI1_RDY");
+        mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS0__SS0, "SPI1_SS0");
+        mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS1__SS1, "SPI1_SS1");
+        mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS2__SS2, "SPI1_SS2");
+        mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SCLK__SCLK, "SPI2_CLK");
+        mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MOSI__MOSI, "SPI2_TX");
+        mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MISO__MISO, "SPI2_RX");
+        mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, "SPI2_RDY");
+        mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS0__SS0, "SPI2_SS0");
+        mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS1__SS1, "SPI2_SS1");
+        mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS2__SS2, "SPI2_SS2");
+        mxc_register_device(&mxc_spi_device0, &spi0_pdata);
+        mxc_register_device(&mxc_spi_device1, &spi1_pdata);
+        spi_register_board_info(&mc13783_dev, 1);
        platform_add_devices(devices, ARRAY_SIZE(devices));
 }
diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c
new file mode 100644
index 000000000000..694611d6b057
--- /dev/null
+++ b/arch/arm/mach-mx3/mx31lite-db.c
@@ -0,0 +1,198 @@
+/*
+ *  LogicPD i.MX31 SOM-LV development board support
+ *
+ *    Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ *
+ *  based on code for other MX31 boards,
+ *
+ *    Copyright 2005-2007 Freescale Semiconductor
+ *    Copyright (c) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
+ *    Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <linux/platform_device.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx3.h>
+#include <mach/board-mx31lite.h>
+#include <mach/mmc.h>
+#include <mach/spi.h>
+#include "devices.h"
+/*
+ * This file contains board-specific initialization routines for the
+ * LogicPD i.MX31 SOM-LV development board, aka 'LiteKit'.
+ * If you design an own baseboard for the module, use this file as base
+ * for support code.
+ */
+static unsigned int litekit_db_board_pins[] __initdata = {
+        /* UART1 */
+        MX31_PIN_CTS1__CTS1,
+        MX31_PIN_RTS1__RTS1,
+        MX31_PIN_TXD1__TXD1,
+        MX31_PIN_RXD1__RXD1,
+        /* SPI 0 */
+        MX31_PIN_CSPI1_SCLK__SCLK,
+        MX31_PIN_CSPI1_MOSI__MOSI,
+        MX31_PIN_CSPI1_MISO__MISO,
+        MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
+        MX31_PIN_CSPI1_SS0__SS0,
+        MX31_PIN_CSPI1_SS1__SS1,
+        MX31_PIN_CSPI1_SS2__SS2,
+};
+/* UART */
+static struct imxuart_platform_data uart_pdata __initdata = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+/* MMC */
+static int gpio_det, gpio_wp;
+#define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
+                        PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
+static int mxc_mmc1_get_ro(struct device *dev)
+{
+        return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_LCS0));
+}
+static int mxc_mmc1_init(struct device *dev,
+                         irq_handler_t detect_irq, void *data)
+{
+        int ret;
+        gpio_det = IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1);
+        gpio_wp = IOMUX_TO_GPIO(MX31_PIN_GPIO1_6);
+        mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, MMC_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, MMC_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, MMC_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, MMC_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SD1_CMD, MMC_PAD_CFG);
+        ret = gpio_request(gpio_det, "MMC detect");
+        if (ret)
+                return ret;
+        ret = gpio_request(gpio_wp, "MMC w/p");
+        if (ret)
+                goto exit_free_det;
+        gpio_direction_input(gpio_det);
+        gpio_direction_input(gpio_wp);
+        ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), detect_irq,
+                          IRQF_DISABLED | IRQF_TRIGGER_FALLING,
+                          "MMC detect", data);
+        if (ret)
+                goto exit_free_wp;
+        return 0;
+exit_free_wp:
+        gpio_free(gpio_wp);
+exit_free_det:
+        gpio_free(gpio_det);
+        return ret;
+}
+static void mxc_mmc1_exit(struct device *dev, void *data)
+{
+        gpio_free(gpio_det);
+        gpio_free(gpio_wp);
+        free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), data);
+}
+static struct imxmmc_platform_data mmc_pdata = {
+        .get_ro  = mxc_mmc1_get_ro,
+        .init      = mxc_mmc1_init,
+        .exit      = mxc_mmc1_exit,
+};
+/* SPI */
+static int spi_internal_chipselect[] = {
+        MXC_SPI_CS(0),
+        MXC_SPI_CS(1),
+        MXC_SPI_CS(2),
+};
+static struct spi_imx_master spi0_pdata = {
+        .chipselect     = spi_internal_chipselect,
+        .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
+};
+/* GPIO LEDs */
+static struct gpio_led litekit_leds[] = {
+        {
+                .name           = "GPIO0",
+                .gpio           = IOMUX_TO_GPIO(MX31_PIN_COMPARE),
+                .active_low     = 1,
+                .default_state  = LEDS_GPIO_DEFSTATE_OFF,
+        },
+        {
+                .name           = "GPIO1",
+                .gpio           = IOMUX_TO_GPIO(MX31_PIN_CAPTURE),
+                .active_low     = 1,
+                .default_state  = LEDS_GPIO_DEFSTATE_OFF,
+        }
+};
+static struct gpio_led_platform_data litekit_led_platform_data = {
+        .leds           = litekit_leds,
+        .num_leds       = ARRAY_SIZE(litekit_leds),
+};
+static struct platform_device litekit_led_device = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &litekit_led_platform_data,
+        },
+};
+void __init mx31lite_db_init(void)
+{
+        mxc_iomux_setup_multiple_pins(litekit_db_board_pins,
+                                        ARRAY_SIZE(litekit_db_board_pins),
+                                        "development board pins");
+        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        mxc_register_device(&mxcsdhc_device0, &mmc_pdata);
+        mxc_register_device(&mxc_spi_device0, &spi0_pdata);
+        platform_device_register(&litekit_led_device);
+}
diff --git a/arch/arm/mach-mx3/mx31lite.c b/arch/arm/mach-mx3/mx31lite.c
index a8d57decdfdb..def6b6736594 100644
--- a/arch/arm/mach-mx3/mx31lite.c
+++ b/arch/arm/mach-mx3/mx31lite.c
@@ -2,6 +2,7 @@
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
 *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *  Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -25,38 +26,47 @@
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/smsc911x.h>
+#include <linux/mfd/mc13783.h>
+#include <linux/spi/spi.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <linux/mtd/physmap.h>
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <mach/common.h>
 #include <asm/page.h>
 #include <asm/setup.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
 #include <mach/board-mx31lite.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/irqs.h>
 #include <mach/mxc_nand.h>
+#include <mach/spi.h>
+#include <mach/mxc_ehci.h>
+#include <mach/ulpi.h>
 #include "devices.h"
 /*
- * This file contains the board-specific initialization routines.
+ * This file contains the module-specific initialization routines.
 */
 static unsigned int mx31lite_pins[] = {
-        /* UART1 */
-        MX31_PIN_CTS1__CTS1,
-        MX31_PIN_RTS1__RTS1,
-        MX31_PIN_TXD1__TXD1,
-        MX31_PIN_RXD1__RXD1,
        /* LAN9117 IRQ pin */
        IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO),
-};
+        /* SPI 1 */
+        MX31_PIN_CSPI2_SCLK__SCLK,
-static struct imxuart_platform_data uart_pdata = {
+        MX31_PIN_CSPI2_MOSI__MOSI,
-        .flags = IMXUART_HAVE_RTSCTS,
+        MX31_PIN_CSPI2_MISO__MISO,
+        MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
+        MX31_PIN_CSPI2_SS0__SS0,
+        MX31_PIN_CSPI2_SS1__SS1,
+        MX31_PIN_CSPI2_SS2__SS2,
 };
 static struct mxc_nand_platform_data mx31lite_nand_board_info = {
@@ -93,6 +103,111 @@ static struct platform_device smsc911x_device = {
 };
 /*
+ * SPI
+ *
+ * The MC13783 is the only hard-wired SPI device on the module.
+ */
+static int spi_internal_chipselect[] = {
+        MXC_SPI_CS(0),
+};
+static struct spi_imx_master spi1_pdata = {
+        .chipselect     = spi_internal_chipselect,
+        .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
+};
+static struct mc13783_platform_data mc13783_pdata __initdata = {
+        .flags  = MC13783_USE_RTC |
+                  MC13783_USE_REGULATOR,
+};
+static struct spi_board_info mc13783_spi_dev __initdata = {
+        .modalias       = "mc13783",
+        .max_speed_hz   = 1000000,
+        .bus_num        = 1,
+        .chip_select    = 0,
+        .platform_data  = &mc13783_pdata,
+        .irq            = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
+};
+/*
+ * USB
+ */
+#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
+                        PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
+static int usbh2_init(struct platform_device *pdev)
+{
+        int pins[] = {
+                MX31_PIN_USBH2_DATA0__USBH2_DATA0,
+                MX31_PIN_USBH2_DATA1__USBH2_DATA1,
+                MX31_PIN_USBH2_CLK__USBH2_CLK,
+                MX31_PIN_USBH2_DIR__USBH2_DIR,
+                MX31_PIN_USBH2_NXT__USBH2_NXT,
+                MX31_PIN_USBH2_STP__USBH2_STP,
+        };
+        mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2");
+        mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
+        mxc_iomux_set_gpr(MUX_PGP_UH2, true);
+        /* chip select */
+        mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO),
+                                "USBH2_CS");
+        gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
+        gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);
+        return 0;
+}
+static struct mxc_usbh_platform_data usbh2_pdata = {
+        .init   = usbh2_init,
+        .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
+        .flags  = MXC_EHCI_POWER_PINS_ENABLED,
+};
+/*
+ * NOR flash
+ */
+static struct physmap_flash_data nor_flash_data = {
+        .width  = 2,
+};
+static struct resource nor_flash_resource = {
+        .start  = 0xa0000000,
+        .end    = 0xa1ffffff,
+        .flags  = IORESOURCE_MEM,
+};
+static struct platform_device physmap_flash_device = {
+        .name   = "physmap-flash",
+        .id     = 0,
+        .dev    = {
+                .platform_data  = &nor_flash_data,
+        },
+        .resource = &nor_flash_resource,
+        .num_resources = 1,
+};
+/*
 * This structure defines the MX31 memory map.
 */
 static struct map_desc mx31lite_io_desc[] __initdata = {
@@ -118,19 +233,40 @@ void __init mx31lite_map_io(void)
        iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc));
 }
-/*
+static int mx31lite_baseboard;
- * Board specific initialization.
+core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444);
- */
 static void __init mxc_board_init(void)
 {
        int ret;
+        switch (mx31lite_baseboard) {
+        case MX31LITE_NOBOARD:
+                break;
+        case MX31LITE_DB:
+                mx31lite_db_init();
+                break;
+        default:
+                printk(KERN_ERR "Illegal mx31lite_baseboard type %d\n",
+                                mx31lite_baseboard);
+        }
        mxc_iomux_setup_multiple_pins(mx31lite_pins, ARRAY_SIZE(mx31lite_pins),
                                      "mx31lite");
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        /* NOR and NAND flash */
+        platform_device_register(&physmap_flash_device);
        mxc_register_device(&mxc_nand_device, &mx31lite_nand_board_info);
+        mxc_register_device(&mxc_spi_device1, &spi1_pdata);
+        spi_register_board_info(&mc13783_spi_dev, 1);
+        /* USB */
+        usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+                                USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+        mxc_register_device(&mxc_usbh2, &usbh2_pdata);
        /* SMSC9117 IRQ pin */
        ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
        if (ret)
@@ -150,12 +286,7 @@ struct sys_timer mx31lite_timer = {
        .init   = mx31lite_timer_init,
 };
-/*
+MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
- * The following uses standard kernel macros defined in arch.h in order to
- * initialize __mach_desc_MX31LITE data structure.
- */
-MACHINE_START(MX31LITE, "LogicPD MX31 LITEKIT")
        /* Maintainer: Freescale Semiconductor, Inc. */
        .phys_io        = AIPS1_BASE_ADDR,
        .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c
index 5592cdb8d0ad..8fc624f141cb 100644
--- a/arch/arm/mach-mx3/mx31moboard-devboard.c
+++ b/arch/arm/mach-mx3/mx31moboard-devboard.c
@@ -22,11 +22,15 @@
 #include <linux/platform_device.h>
 #include <linux/types.h>
+#include <linux/usb/otg.h>
 #include <mach/common.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/hardware.h>
 #include <mach/mmc.h>
+#include <mach/mxc_ehci.h>
+#include <mach/ulpi.h>
 #include "devices.h"
@@ -39,6 +43,12 @@ static unsigned int devboard_pins[] = {
        MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0,
        MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD,
        MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29,
+        /* USB H1 */
+        MX31_PIN_CSPI1_MISO__USBH1_RXDP, MX31_PIN_CSPI1_MOSI__USBH1_RXDM,
+        MX31_PIN_CSPI1_SS0__USBH1_TXDM, MX31_PIN_CSPI1_SS1__USBH1_TXDP,
+        MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB,
+        MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND,
+        MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12,
 };
 static struct imxuart_platform_data uart_pdata = {
@@ -98,6 +108,80 @@ static struct imxmmc_platform_data sdhc2_pdata = {
        .exit   = devboard_sdhc2_exit,
 };
+#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
+                        PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
+static int devboard_usbh1_hw_init(struct platform_device *pdev)
+{
+        mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG);
+        return 0;
+}
+#define USBH1_VBUSEN_B  IOMUX_TO_GPIO(MX31_PIN_NFRE_B)
+#define USBH1_MODE      IOMUX_TO_GPIO(MX31_PIN_NFALE)
+static int devboard_isp1105_init(struct otg_transceiver *otg)
+{
+        int ret = gpio_request(USBH1_MODE, "usbh1-mode");
+        if (ret)
+                return ret;
+        /* single ended */
+        gpio_direction_output(USBH1_MODE, 0);
+        ret = gpio_request(USBH1_VBUSEN_B, "usbh1-vbusen");
+        if (ret) {
+                gpio_free(USBH1_MODE);
+                return ret;
+        }
+        gpio_direction_output(USBH1_VBUSEN_B, 1);
+        return 0;
+}
+static int devboard_isp1105_set_vbus(struct otg_transceiver *otg, bool on)
+{
+        if (on)
+                gpio_set_value(USBH1_VBUSEN_B, 0);
+        else
+                gpio_set_value(USBH1_VBUSEN_B, 1);
+        return 0;
+}
+static struct mxc_usbh_platform_data usbh1_pdata = {
+        .init   = devboard_usbh1_hw_init,
+        .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
+        .flags  = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
+};
+static int __init devboard_usbh1_init(void)
+{
+        struct otg_transceiver *otg;
+        otg = kzalloc(sizeof(*otg), GFP_KERNEL);
+        if (!otg)
+                return -ENOMEM;
+        otg->label      = "ISP1105";
+        otg->init       = devboard_isp1105_init;
+        otg->set_vbus   = devboard_isp1105_set_vbus;
+        usbh1_pdata.otg = otg;
+        return mxc_register_device(&mx31_usbh1, &usbh1_pdata);
+}
 /*
 * system init for baseboard usage. Will be called by mx31moboard init.
 */
@@ -111,4 +195,6 @@ void __init mx31moboard_devboard_init(void)
        mxc_register_device(&mxc_uart_device1, &uart_pdata);
        mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
+        devboard_usbh1_init();
 }
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c
index 2bfaffb344f0..85184a35e674 100644
--- a/arch/arm/mach-mx3/mx31moboard-marxbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c
@@ -16,17 +16,26 @@
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
+#include <linux/delay.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
+#include <linux/i2c.h>
+#include <linux/spi/spi.h>
 #include <linux/platform_device.h>
 #include <linux/types.h>
+#include <linux/usb/otg.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/mmc.h>
+#include <mach/mxc_ehci.h>
+#include <mach/ulpi.h>
+#include <media/soc_camera.h>
 #include "devices.h"
@@ -37,7 +46,6 @@ static unsigned int marxbot_pins[] = {
        MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD,
        MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29,
        /* CSI */
-        MX31_PIN_CSI_D4__CSI_D4, MX31_PIN_CSI_D5__CSI_D5,
        MX31_PIN_CSI_D6__CSI_D6, MX31_PIN_CSI_D7__CSI_D7,
        MX31_PIN_CSI_D8__CSI_D8, MX31_PIN_CSI_D9__CSI_D9,
        MX31_PIN_CSI_D10__CSI_D10, MX31_PIN_CSI_D11__CSI_D11,
@@ -45,10 +53,19 @@ static unsigned int marxbot_pins[] = {
        MX31_PIN_CSI_D14__CSI_D14, MX31_PIN_CSI_D15__CSI_D15,
        MX31_PIN_CSI_HSYNC__CSI_HSYNC, MX31_PIN_CSI_MCLK__CSI_MCLK,
        MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_VSYNC__CSI_VSYNC,
+        MX31_PIN_CSI_D4__GPIO3_4, MX31_PIN_CSI_D5__GPIO3_5,
        MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1,
        MX31_PIN_TXD2__GPIO1_28,
        /* dsPIC resets */
        MX31_PIN_STXD5__GPIO1_21, MX31_PIN_SRXD5__GPIO1_22,
+        /*battery detection */
+        MX31_PIN_LCS0__GPIO3_23,
+        /* USB H1 */
+        MX31_PIN_CSPI1_MISO__USBH1_RXDP, MX31_PIN_CSPI1_MOSI__USBH1_RXDM,
+        MX31_PIN_CSPI1_SS0__USBH1_TXDM, MX31_PIN_CSPI1_SS1__USBH1_TXDP,
+        MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB,
+        MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND,
+        MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12,
 };
 #define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR)
@@ -120,6 +137,166 @@ static void dspics_resets_init(void)
        }
 }
+static struct spi_board_info marxbot_spi_board_info[] __initdata = {
+        {
+                .modalias = "spidev",
+                .max_speed_hz = 300000,
+                .bus_num = 1,
+                .chip_select = 1, /* according spi1_cs[] ! */
+        },
+};
+#define TURRETCAM_POWER IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
+#define BASECAM_POWER   IOMUX_TO_GPIO(MX31_PIN_CSI_D5)
+#define TURRETCAM_RST_B IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
+#define BASECAM_RST_B   IOMUX_TO_GPIO(MX31_PIN_CSI_D4)
+#define CAM_CHOICE      IOMUX_TO_GPIO(MX31_PIN_TXD2)
+static int marxbot_basecam_power(struct device *dev, int on)
+{
+        gpio_set_value(BASECAM_POWER, !on);
+        return 0;
+}
+static int marxbot_basecam_reset(struct device *dev)
+{
+        gpio_set_value(BASECAM_RST_B, 0);
+        udelay(100);
+        gpio_set_value(BASECAM_RST_B, 1);
+        return 0;
+}
+static struct i2c_board_info marxbot_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("mt9t031", 0x5d),
+        },
+};
+static struct soc_camera_link base_iclink = {
+        .bus_id         = 0,            /* Must match with the camera ID */
+        .power          = marxbot_basecam_power,
+        .reset          = marxbot_basecam_reset,
+        .board_info     = &marxbot_i2c_devices[0],
+        .i2c_adapter_id = 0,
+        .module_name    = "mt9t031",
+};
+static struct platform_device marxbot_camera[] = {
+        {
+                .name   = "soc-camera-pdrv",
+                .id     = 0,
+                .dev    = {
+                        .platform_data = &base_iclink,
+                },
+        },
+};
+static struct platform_device *marxbot_cameras[] __initdata = {
+        &marxbot_camera[0],
+};
+static int __init marxbot_cam_init(void)
+{
+        int ret = gpio_request(CAM_CHOICE, "cam-choice");
+        if (ret)
+                return ret;
+        gpio_direction_output(CAM_CHOICE, 1);
+        ret = gpio_request(BASECAM_RST_B, "basecam-reset");
+        if (ret)
+                return ret;
+        gpio_direction_output(BASECAM_RST_B, 1);
+        ret = gpio_request(BASECAM_POWER, "basecam-standby");
+        if (ret)
+                return ret;
+        gpio_direction_output(BASECAM_POWER, 0);
+        ret = gpio_request(TURRETCAM_RST_B, "turretcam-reset");
+        if (ret)
+                return ret;
+        gpio_direction_output(TURRETCAM_RST_B, 1);
+        ret = gpio_request(TURRETCAM_POWER, "turretcam-standby");
+        if (ret)
+                return ret;
+        gpio_direction_output(TURRETCAM_POWER, 0);
+        return 0;
+}
+#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
+                        PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
+static int marxbot_usbh1_hw_init(struct platform_device *pdev)
+{
+        mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG);
+        return 0;
+}
+#define USBH1_VBUSEN_B  IOMUX_TO_GPIO(MX31_PIN_NFRE_B)
+#define USBH1_MODE      IOMUX_TO_GPIO(MX31_PIN_NFALE)
+static int marxbot_isp1105_init(struct otg_transceiver *otg)
+{
+        int ret = gpio_request(USBH1_MODE, "usbh1-mode");
+        if (ret)
+                return ret;
+        /* single ended */
+        gpio_direction_output(USBH1_MODE, 0);
+        ret = gpio_request(USBH1_VBUSEN_B, "usbh1-vbusen");
+        if (ret) {
+                gpio_free(USBH1_MODE);
+                return ret;
+        }
+        gpio_direction_output(USBH1_VBUSEN_B, 1);
+        return 0;
+}
+static int marxbot_isp1105_set_vbus(struct otg_transceiver *otg, bool on)
+{
+        if (on)
+                gpio_set_value(USBH1_VBUSEN_B, 0);
+        else
+                gpio_set_value(USBH1_VBUSEN_B, 1);
+        return 0;
+}
+static struct mxc_usbh_platform_data usbh1_pdata = {
+        .init   = marxbot_usbh1_hw_init,
+        .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
+        .flags  = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
+};
+static int __init marxbot_usbh1_init(void)
+{
+        struct otg_transceiver *otg;
+        otg = kzalloc(sizeof(*otg), GFP_KERNEL);
+        if (!otg)
+                return -ENOMEM;
+        otg->label      = "ISP1105";
+        otg->init       = marxbot_isp1105_init;
+        otg->set_vbus   = marxbot_isp1105_set_vbus;
+        usbh1_pdata.otg = otg;
+        return mxc_register_device(&mx31_usbh1, &usbh1_pdata);
+}
 /*
 * system init for baseboard usage. Will be called by mx31moboard init.
 */
@@ -133,4 +310,17 @@ void __init mx31moboard_marxbot_init(void)
        dspics_resets_init();
        mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
+        spi_register_board_info(marxbot_spi_board_info,
+                ARRAY_SIZE(marxbot_spi_board_info));
+        marxbot_cam_init();
+        platform_add_devices(marxbot_cameras, ARRAY_SIZE(marxbot_cameras));
+        /* battery present pin */
+        gpio_request(IOMUX_TO_GPIO(MX31_PIN_LCS0), "bat-present");
+        gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_LCS0));
+        gpio_export(IOMUX_TO_GPIO(MX31_PIN_LCS0), false);
+        marxbot_usbh1_init();
 }
diff --git a/arch/arm/mach-mx3/mx31moboard.c b/arch/arm/mach-mx3/mx31moboard.c
index 9243de54041a..b70529145936 100644
--- a/arch/arm/mach-mx3/mx31moboard.c
+++ b/arch/arm/mach-mx3/mx31moboard.c
@@ -17,6 +17,7 @@
 */
 #include <linux/delay.h>
+#include <linux/dma-mapping.h>
 #include <linux/fsl_devices.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
@@ -26,8 +27,14 @@
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/partitions.h>
 #include <linux/platform_device.h>
+#include <linux/regulator/machine.h>
+#include <linux/mfd/mc13783.h>
+#include <linux/spi/spi.h>
 #include <linux/types.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
@@ -37,16 +44,20 @@
 #include <mach/hardware.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
+#include <mach/ipu.h>
 #include <mach/i2c.h>
 #include <mach/mmc.h>
-#include <mach/mx31.h>
+#include <mach/mxc_ehci.h>
+#include <mach/mx3_camera.h>
+#include <mach/spi.h>
+#include <mach/ulpi.h>
 #include "devices.h"
 static unsigned int moboard_pins[] = {
        /* UART0 */
-        MX31_PIN_CTS1__CTS1, MX31_PIN_RTS1__RTS1,
        MX31_PIN_TXD1__TXD1, MX31_PIN_RXD1__RXD1,
+        MX31_PIN_CTS1__GPIO2_7,
        /* UART4 */
        MX31_PIN_PC_RST__CTS5, MX31_PIN_PC_VS2__RTS5,
        MX31_PIN_PC_BVD2__TXD5, MX31_PIN_PC_BVD1__RXD5,
@@ -73,12 +84,31 @@ static unsigned int moboard_pins[] = {
        MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR,
        MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP,
        MX31_PIN_USB_OC__GPIO1_30,
+        /* USB H2 */
+        MX31_PIN_USBH2_DATA0__USBH2_DATA0,
+        MX31_PIN_USBH2_DATA1__USBH2_DATA1,
+        MX31_PIN_STXD3__USBH2_DATA2, MX31_PIN_SRXD3__USBH2_DATA3,
+        MX31_PIN_SCK3__USBH2_DATA4, MX31_PIN_SFS3__USBH2_DATA5,
+        MX31_PIN_STXD6__USBH2_DATA6, MX31_PIN_SRXD6__USBH2_DATA7,
+        MX31_PIN_USBH2_CLK__USBH2_CLK, MX31_PIN_USBH2_DIR__USBH2_DIR,
+        MX31_PIN_USBH2_NXT__USBH2_NXT, MX31_PIN_USBH2_STP__USBH2_STP,
+        MX31_PIN_SCK6__GPIO1_25,
        /* LEDs */
        MX31_PIN_SVEN0__GPIO2_0, MX31_PIN_STX0__GPIO2_1,
        MX31_PIN_SRX0__GPIO2_2, MX31_PIN_SIMPD0__GPIO2_3,
        /* SEL */
        MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9,
        MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
+        /* SPI1 */
+        MX31_PIN_CSPI2_MOSI__MOSI, MX31_PIN_CSPI2_MISO__MISO,
+        MX31_PIN_CSPI2_SCLK__SCLK, MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
+        MX31_PIN_CSPI2_SS0__SS0, MX31_PIN_CSPI2_SS2__SS2,
+        /* Atlas IRQ */
+        MX31_PIN_GPIO1_3__GPIO1_3,
+        /* SPI2 */
+        MX31_PIN_CSPI3_MOSI__MOSI, MX31_PIN_CSPI3_MISO__MISO,
+        MX31_PIN_CSPI3_SCLK__SCLK, MX31_PIN_CSPI3_SPI_RDY__SPI_RDY,
+        MX31_PIN_CSPI2_SS1__CSPI3_SS1,
 };
 static struct physmap_flash_data mx31moboard_flash_data = {
@@ -101,7 +131,18 @@ static struct platform_device mx31moboard_flash = {
        .num_resources = 1,
 };
-static struct imxuart_platform_data uart_pdata = {
+static int moboard_uart0_init(struct platform_device *pdev)
+{
+        gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack");
+        gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0);
+        return 0;
+}
+static struct imxuart_platform_data uart0_pdata = {
+        .init = moboard_uart0_init,
+};
+static struct imxuart_platform_data uart4_pdata = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
@@ -113,6 +154,103 @@ static struct imxi2c_platform_data moboard_i2c1_pdata = {
        .bitrate = 100000,
 };
+static int moboard_spi1_cs[] = {
+        MXC_SPI_CS(0),
+        MXC_SPI_CS(2),
+};
+static struct spi_imx_master moboard_spi1_master = {
+        .chipselect     = moboard_spi1_cs,
+        .num_chipselect = ARRAY_SIZE(moboard_spi1_cs),
+};
+static struct regulator_consumer_supply sdhc_consumers[] = {
+        {
+                .dev    = &mxcsdhc_device0.dev,
+                .supply = "sdhc0_vcc",
+        },
+        {
+                .dev    = &mxcsdhc_device1.dev,
+                .supply = "sdhc1_vcc",
+        },
+};
+static struct regulator_init_data sdhc_vreg_data = {
+        .constraints = {
+                .min_uV = 2700000,
+                .max_uV = 3000000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                        REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
+                .valid_modes_mask = REGULATOR_MODE_NORMAL |
+                        REGULATOR_MODE_FAST,
+                .always_on = 0,
+                .boot_on = 1,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(sdhc_consumers),
+        .consumer_supplies = sdhc_consumers,
+};
+static struct regulator_consumer_supply cam_consumers[] = {
+        {
+                .dev    = &mx3_camera.dev,
+                .supply = "cam_vcc",
+        },
+};
+static struct regulator_init_data cam_vreg_data = {
+        .constraints = {
+                .min_uV = 2700000,
+                .max_uV = 3000000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                        REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
+                .valid_modes_mask = REGULATOR_MODE_NORMAL |
+                        REGULATOR_MODE_FAST,
+                .always_on = 0,
+                .boot_on = 1,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(cam_consumers),
+        .consumer_supplies = cam_consumers,
+};
+static struct mc13783_regulator_init_data moboard_regulators[] = {
+        {
+                .id = MC13783_REGU_VMMC1,
+                .init_data = &sdhc_vreg_data,
+        },
+        {
+                .id = MC13783_REGU_VCAM,
+                .init_data = &cam_vreg_data,
+        },
+};
+static struct mc13783_platform_data moboard_pmic = {
+        .regulators = moboard_regulators,
+        .num_regulators = ARRAY_SIZE(moboard_regulators),
+        .flags = MC13783_USE_REGULATOR | MC13783_USE_RTC |
+                MC13783_USE_ADC,
+};
+static struct spi_board_info moboard_spi_board_info[] __initdata = {
+        {
+                .modalias = "mc13783",
+                .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
+                .max_speed_hz = 300000,
+                .bus_num = 1,
+                .chip_select = 0,
+                .platform_data = &moboard_pmic,
+                .mode = SPI_CS_HIGH,
+        },
+};
+static int moboard_spi2_cs[] = {
+        MXC_SPI_CS(1),
+};
+static struct spi_imx_master moboard_spi2_master = {
+        .chipselect     = moboard_spi2_cs,
+        .num_chipselect = ARRAY_SIZE(moboard_spi2_cs),
+};
 #define SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_ATA_CS0)
 #define SDHC1_WP IOMUX_TO_GPIO(MX31_PIN_ATA_CS1)
@@ -208,6 +346,56 @@ static struct fsl_usb2_platform_data usb_pdata = {
        .phy_mode       = FSL_USB2_PHY_ULPI,
 };
+#define USBH2_EN_B IOMUX_TO_GPIO(MX31_PIN_SCK6)
+static int moboard_usbh2_hw_init(struct platform_device *pdev)
+{
+        int ret = gpio_request(USBH2_EN_B, "usbh2-en");
+        if (ret)
+                return ret;
+        mxc_iomux_set_gpr(MUX_PGP_UH2, true);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
+        gpio_direction_output(USBH2_EN_B, 0);
+        return 0;
+}
+static int moboard_usbh2_hw_exit(struct platform_device *pdev)
+{
+        gpio_free(USBH2_EN_B);
+        return 0;
+}
+static struct mxc_usbh_platform_data usbh2_pdata = {
+        .init   = moboard_usbh2_hw_init,
+        .exit   = moboard_usbh2_hw_exit,
+        .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
+        .flags  = MXC_EHCI_POWER_PINS_ENABLED,
+};
+static int __init moboard_usbh2_init(void)
+{
+        usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+                        USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+        return mxc_register_device(&mx31_usbh2, &usbh2_pdata);
+}
 static struct gpio_led mx31moboard_leds[] = {
        {
                .name   = "coreboard-led-0:red:running",
@@ -266,11 +454,48 @@ static void mx31moboard_init_sel_gpios(void)
        }
 }
+static struct ipu_platform_data mx3_ipu_data = {
+        .irq_base = MXC_IPU_IRQ_START,
+};
 static struct platform_device *devices[] __initdata = {
        &mx31moboard_flash,
        &mx31moboard_leds_device,
 };
+static struct mx3_camera_pdata camera_pdata = {
+        .dma_dev        = &mx3_ipu.dev,
+        .flags          = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10,
+        .mclk_10khz     = 4800,
+};
+#define CAMERA_BUF_SIZE (4*1024*1024)
+static int __init mx31moboard_cam_alloc_dma(const size_t buf_size)
+{
+        dma_addr_t dma_handle;
+        void *buf;
+        int dma;
+        if (buf_size < 2 * 1024 * 1024)
+                return -EINVAL;
+        buf = dma_alloc_coherent(NULL, buf_size, &dma_handle, GFP_KERNEL);
+        if (!buf) {
+                pr_err("%s: cannot allocate camera buffer-memory\n", __func__);
+                return -ENOMEM;
+        }
+        memset(buf, 0, buf_size);
+        dma = dma_declare_coherent_memory(&mx3_camera.dev,
+                                        dma_handle, dma_handle, buf_size,
+                                        DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
+        /* The way we call dma_declare_coherent_memory only a malloc can fail */
+        return dma & DMA_MEMORY_MAP ? 0 : -ENOMEM;
+}
 static int mx31moboard_baseboard;
 core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444);
@@ -284,20 +509,34 @@ static void __init mxc_board_init(void)
        platform_add_devices(devices, ARRAY_SIZE(devices));
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        mxc_register_device(&mxc_uart_device0, &uart0_pdata);
-        mxc_register_device(&mxc_uart_device4, &uart_pdata);
+        mxc_register_device(&mxc_uart_device4, &uart4_pdata);
        mx31moboard_init_sel_gpios();
        mxc_register_device(&mxc_i2c_device0, &moboard_i2c0_pdata);
        mxc_register_device(&mxc_i2c_device1, &moboard_i2c1_pdata);
+        mxc_register_device(&mxc_spi_device1, &moboard_spi1_master);
+        mxc_register_device(&mxc_spi_device2, &moboard_spi2_master);
+        gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3), "pmic-irq");
+        gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
+        spi_register_board_info(moboard_spi_board_info,
+                ARRAY_SIZE(moboard_spi_board_info));
        mxc_register_device(&mxcsdhc_device0, &sdhc1_pdata);
+        mxc_register_device(&mx3_ipu, &mx3_ipu_data);
+        if (!mx31moboard_cam_alloc_dma(CAMERA_BUF_SIZE))
+                mxc_register_device(&mx3_camera, &camera_pdata);
        usb_xcvr_reset();
        moboard_usbotg_init();
        mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
+        moboard_usbh2_init();
        switch (mx31moboard_baseboard) {
        case MX31NOBOARD:
diff --git a/arch/arm/mach-mx3/mx35pdk.c b/arch/arm/mach-mx3/mx35pdk.c
index 6ff186e46ceb..0bbc65ea23c8 100644
--- a/arch/arm/mach-mx3/mx35pdk.c
+++ b/arch/arm/mach-mx3/mx35pdk.c
@@ -23,6 +23,7 @@
 #include <linux/platform_device.h>
 #include <linux/memory.h>
 #include <linux/gpio.h>
+#include <linux/fsl_devices.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -69,6 +70,15 @@ static struct pad_desc mx35pdk_pads[] = {
        MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
        MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
        MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
+        /* USBOTG */
+        MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
+        MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
+};
+/* OTG config */
+static struct fsl_usb2_platform_data usb_pdata = {
+        .operating_mode = FSL_USB2_DR_DEVICE,
+        .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
 };
 /*
@@ -81,6 +91,8 @@ static void __init mxc_board_init(void)
        platform_add_devices(devices, ARRAY_SIZE(devices));
        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
 }
 static void __init mx35pdk_timer_init(void)
diff --git a/arch/arm/mach-mx3/pcm043.c b/arch/arm/mach-mx3/pcm043.c
index e18a224671fa..e3aa829be586 100644
--- a/arch/arm/mach-mx3/pcm043.c
+++ b/arch/arm/mach-mx3/pcm043.c
@@ -43,6 +43,7 @@
 #include <mach/iomux-mx35.h>
 #include <mach/ipu.h>
 #include <mach/mx3fb.h>
+#include <mach/mxc_nand.h>
 #include "devices.h"
@@ -206,6 +207,11 @@ static struct pad_desc pcm043_pads[] = {
        MX35_PAD_ATA_CS0__GPIO2_6,
 };
+static struct mxc_nand_platform_data pcm037_nand_board_info = {
+        .width = 1,
+        .hw_ecc = 1,
+};
 /*
 * Board specific initialization.
 */
@@ -216,6 +222,7 @@ static void __init mxc_board_init(void)
        platform_add_devices(devices, ARRAY_SIZE(devices));
        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info);
        mxc_register_device(&mxc_uart_device1, &uart_pdata);
diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig
index 2a02b49c40f0..3c5e0f522e9c 100644
--- a/arch/arm/mach-nomadik/Kconfig
+++ b/arch/arm/mach-nomadik/Kconfig
@@ -5,13 +5,13 @@ menu "Nomadik boards"
 config MACH_NOMADIK_8815NHK
        bool "ST 8815 Nomadik Hardware Kit (evaluation board)"
        select NOMADIK_8815
+        select HAS_MTU
 endmenu
 config NOMADIK_8815
        bool
 config I2C_BITBANG_8815NHK
        tristate "Driver for bit-bang busses found on the 8815 NHK"
        depends on I2C && MACH_NOMADIK_8815NHK
diff --git a/arch/arm/mach-nomadik/Makefile b/arch/arm/mach-nomadik/Makefile
index 412040982a40..36f67fb207d2 100644
--- a/arch/arm/mach-nomadik/Makefile
+++ b/arch/arm/mach-nomadik/Makefile
@@ -7,7 +7,7 @@
 # Object file lists.
-obj-y                   += clock.o timer.o gpio.o
+obj-y                   += clock.o gpio.o
 # Cpu revision
 obj-$(CONFIG_NOMADIK_8815) += cpu-8815.o
diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c
index 6bfd537d5afb..116394484e71 100644
--- a/arch/arm/mach-nomadik/board-nhk8815.c
+++ b/arch/arm/mach-nomadik/board-nhk8815.c
@@ -25,11 +25,18 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/flash.h>
+#include <plat/mtu.h>
 #include <mach/setup.h>
 #include <mach/nand.h>
 #include <mach/fsmc.h>
 #include "clock.h"
+/* Initial value for SRC control register: all timers use MXTAL/8 source */
+#define SRC_CR_INIT_MASK        0x00007fff
+#define SRC_CR_INIT_VAL         0x2aaa8000
 /* These adresses span 16MB, so use three individual pages */
 static struct resource nhk8815_nand_resources[] = {
        {
@@ -239,6 +246,26 @@ static struct platform_device *nhk8815_platform_devices[] __initdata = {
        /* will add more devices */
 };
+static void __init nomadik_timer_init(void)
+{
+        u32 src_cr;
+        /* Configure timer sources in "system reset controller" ctrl reg */
+        src_cr = readl(io_p2v(NOMADIK_SRC_BASE));
+        src_cr &= SRC_CR_INIT_MASK;
+        src_cr |= SRC_CR_INIT_VAL;
+        writel(src_cr, io_p2v(NOMADIK_SRC_BASE));
+        /* Save global pointer to mtu, used by platform timer code */
+        mtu_base = io_p2v(NOMADIK_MTU0_BASE);
+        nmdk_timer_init();
+}
+static struct sys_timer nomadik_timer = {
+        .init   = nomadik_timer_init,
+};
 static void __init nhk8815_platform_init(void)
 {
        int i;
diff --git a/arch/arm/mach-nomadik/include/mach/setup.h b/arch/arm/mach-nomadik/include/mach/setup.h
index a4e468cf63da..b7897edf1f35 100644
--- a/arch/arm/mach-nomadik/include/mach/setup.h
+++ b/arch/arm/mach-nomadik/include/mach/setup.h
@@ -15,7 +15,7 @@
 extern void cpu8815_map_io(void);
 extern void cpu8815_platform_init(void);
 extern void cpu8815_init_irq(void);
-extern struct sys_timer nomadik_timer;
+extern void nmdk_timer_init(void);
 #endif /* NOMADIK_8815 */
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index aad194f61a33..6f1bbbc4d15f 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -100,3 +100,11 @@ config MACH_OMAP_ZOOM2
 config MACH_OMAP_4430SDP
        bool "OMAP 4430 SDP board"
        depends on ARCH_OMAP4
+config OMAP3_EMU
+        bool "OMAP3 debugging peripherals"
+        depends on ARCH_OMAP3
+        select OC_ETM
+        help
+          Say Y here to enable debugging hardware of omap3
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 8cb16777661a..e141cabcfcce 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -44,6 +44,9 @@ obj-$(CONFIG_ARCH_OMAP4)		+= cm4xxx.o
 obj-$(CONFIG_ARCH_OMAP2)                += clock24xx.o
 obj-$(CONFIG_ARCH_OMAP3)                += clock34xx.o
+# EMU peripherals
+obj-$(CONFIG_OMAP3_EMU)         += emu.o
 iommu-y                                 += iommu2.o
 iommu-$(CONFIG_ARCH_OMAP3)              += omap3-iommu.o
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 7c5c00df3c70..066e88a18824 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -119,7 +119,7 @@ static struct omap_clk omap34xx_clks[] = {
        CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X),
        CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck,   CK_343X),
        CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X),
-        CLK(NULL,       "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X),
+        CLK("etb",      "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X),
        CLK(NULL,       "dpll4_ck",     &dpll4_ck,      CK_343X),
        CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck,   CK_343X),
        CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X),
@@ -138,7 +138,7 @@ static struct omap_clk omap34xx_clks[] = {
        CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X),
        CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck,   CK_343X),
        CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X),
-        CLK(NULL,       "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X),
+        CLK("etb",      "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X),
        CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2),
        CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2),
        CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck, CK_343X),
@@ -147,7 +147,7 @@ static struct omap_clk omap34xx_clks[] = {
        CLK(NULL,       "dpll1_fck",    &dpll1_fck,     CK_343X),
        CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_343X),
        CLK(NULL,       "arm_fck",      &arm_fck,       CK_343X),
-        CLK(NULL,       "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X),
+        CLK("etb",      "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X),
        CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_343X),
        CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_343X),
        CLK(NULL,       "l3_ick",       &l3_ick,        CK_343X),
@@ -302,7 +302,7 @@ static struct omap_clk omap34xx_clks[] = {
        CLK("omap-mcbsp.2", "fck",      &mcbsp2_fck,    CK_343X),
        CLK("omap-mcbsp.3", "fck",      &mcbsp3_fck,    CK_343X),
        CLK("omap-mcbsp.4", "fck",      &mcbsp4_fck,    CK_343X),
-        CLK(NULL,       "emu_src_ck",   &emu_src_ck,    CK_343X),
+        CLK("etb",      "emu_src_ck",   &emu_src_ck,    CK_343X),
        CLK(NULL,       "pclk_fck",     &pclk_fck,      CK_343X),
        CLK(NULL,       "pclkx2_fck",   &pclkx2_fck,    CK_343X),
        CLK(NULL,       "atclk_fck",    &atclk_fck,     CK_343X),
diff --git a/arch/arm/mach-omap2/emu.c b/arch/arm/mach-omap2/emu.c
new file mode 100644
index 000000000000..ec0d984a26fc
--- /dev/null
+++ b/arch/arm/mach-omap2/emu.c
@@ -0,0 +1,66 @@
+/*
+ * emu.c
+ *
+ * ETM and ETB CoreSight components' resources as found in OMAP3xxx.
+ *
+ * Copyright (C) 2009 Nokia Corporation.
+ * Alexander Shishkin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/amba/bus.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Alexander Shishkin");
+/* Cortex CoreSight components within omap3xxx EMU */
+#define ETM_BASE        (L4_EMU_34XX_PHYS + 0x10000)
+#define DBG_BASE        (L4_EMU_34XX_PHYS + 0x11000)
+#define ETB_BASE        (L4_EMU_34XX_PHYS + 0x1b000)
+#define DAPCTL          (L4_EMU_34XX_PHYS + 0x1d000)
+static struct amba_device omap3_etb_device = {
+        .dev            = {
+                .init_name = "etb",
+        },
+        .res            = {
+                .start  = ETB_BASE,
+                .end    = ETB_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        .periphid       = 0x000bb907,
+};
+static struct amba_device omap3_etm_device = {
+        .dev            = {
+                .init_name = "etm",
+        },
+        .res            = {
+                .start  = ETM_BASE,
+                .end    = ETM_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        .periphid       = 0x102bb921,
+};
+static int __init emu_init(void)
+{
+        amba_device_register(&omap3_etb_device, &iomem_resource);
+        amba_device_register(&omap3_etm_device, &iomem_resource);
+        return 0;
+}
+subsys_initcall(emu_init);
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index a6f8eab14ba5..d89c6adbe8bc 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -2,34 +2,105 @@ if ARCH_PXA
 menu "Intel PXA2xx/PXA3xx Implementations"
-if PXA3xx
+comment "Intel/Marvell Dev Platforms (sorted by hardware release time)"
-menu "Supported PXA3xx Processor Variants"
+config ARCH_LUBBOCK
+        bool "Intel DBPXA250 Development Platform (aka Lubbock)"
+        select PXA25x
+        select SA1111
+        select PXA_HAVE_BOARD_IRQS
-config CPU_PXA300
+config MACH_MAINSTONE
-        bool "PXA300 (codename Monahans-L)"
+        bool "Intel HCDDBBVA0 Development Platform (aka Mainstone)"
+        select PXA27x
+        select HAVE_PWM
+        select PXA_HAVE_BOARD_IRQS
-config CPU_PXA310
+config MACH_ZYLONITE
-        bool "PXA310 (codename Monahans-LV)"
+        bool
+        select PXA3xx
+        select PXA_SSP
+        select HAVE_PWM
+        select PXA_HAVE_BOARD_IRQS
+config MACH_ZYLONITE300
+        bool "PXA3xx Development Platform (aka Zylonite) PXA300/310"
        select CPU_PXA300
+        select CPU_PXA310
+        select MACH_ZYLONITE
-config CPU_PXA320
+config MACH_ZYLONITE320
-        bool "PXA320 (codename Monahans-P)"
+        bool "PXA3xx Development Platform (aka Zylonite) PXA320"
+        select CPU_PXA320
+        select MACH_ZYLONITE
-config CPU_PXA930
+config MACH_LITTLETON
-        bool "PXA930 (codename Tavor-P)"
+        bool "PXA3xx Form Factor Platform (aka Littleton)"
+        select PXA3xx
+        select PXA_SSP
-config CPU_PXA935
+config MACH_TAVOREVB
-        bool "PXA935 (codename Tavor-P65)"
+        bool "PXA930 Evaluation Board (aka TavorEVB)"
+        select PXA3xx
        select CPU_PXA930
-config CPU_PXA950
+config MACH_SAAR
-        bool "PXA950 (codename Tavor-PV2)"
+        bool "PXA930 Handheld Platform (aka SAAR)"
+        select PXA3xx
        select CPU_PXA930
-endmenu
+comment "Third Party Dev Platforms (sorted by vendor name)"
-endif
+config ARCH_PXA_IDP
+        bool "Accelent Xscale IDP"
+        select PXA25x
+config ARCH_VIPER
+        bool "Arcom/Eurotech VIPER SBC"
+        select PXA25x
+        select ISA
+        select I2C_GPIO
+        select HAVE_PWM
+        select PXA_HAVE_BOARD_IRQS
+        select PXA_HAVE_ISA_IRQS
+config MACH_BALLOON3
+        bool "Balloon 3 board"
+        select PXA27x
+        select IWMMXT
+        select PXA_HAVE_BOARD_IRQS
+config MACH_CSB726
+        bool "Enable Cogent CSB726 System On a Module"
+        select PXA27x
+        select IWMMXT
+        help
+          Say Y here if you intend to run this kernel on a Cogent
+          CSB726 System On Module.
+config CSB726_CSB701
+        bool "Enable support for CSB701 baseboard"
+        depends on MACH_CSB726
+config MACH_ARMCORE
+        bool "CompuLab CM-X255/CM-X270 modules"
+        select PXA27x
+        select IWMMXT
+        select PXA25x
+        select PXA_SSP
+config MACH_EM_X270
+        bool "CompuLab EM-x270 platform"
+        select PXA27x
+config MACH_EXEDA
+        bool "CompuLab eXeda platform"
+        select PXA27x
+config MACH_CM_X300
+        bool "CompuLab CM-X300 modules"
+        select PXA3xx
+        select CPU_PXA300
 config ARCH_GUMSTIX
        bool "Gumstix XScale 255 boards"
@@ -62,185 +133,24 @@ config MACH_STARGATE2
        select IWMMXT
        select PXA_HAVE_BOARD_IRQS
-config ARCH_LUBBOCK
+config MACH_XCEP
-        bool "Intel DBPXA250 Development Platform"
+        bool "Iskratel Electronics XCEP"
-        select PXA25x
-        select SA1111
-        select PXA_HAVE_BOARD_IRQS
-config MACH_LOGICPD_PXA270
-        bool "LogicPD PXA270 Card Engine Development Platform"
-        select PXA27x
-        select HAVE_PWM
-        select PXA_HAVE_BOARD_IRQS
-config MACH_MAINSTONE
-        bool "Intel HCDDBBVA0 Development Platform"
-        select PXA27x
-        select HAVE_PWM
-        select PXA_HAVE_BOARD_IRQS
-config MACH_MP900C
-        bool "Nec Mobilepro 900/c"
-        select PXA25x
-config MACH_BALLOON3
-        bool "Balloon 3 board"
-        select PXA27x
-        select IWMMXT
-        select PXA_HAVE_BOARD_IRQS
-config ARCH_PXA_IDP
-        bool "Accelent Xscale IDP"
-        select PXA25x
-config PXA_SHARPSL
-        bool "SHARP Zaurus SL-5600, SL-C7xx and SL-Cxx00 Models"
-        select SHARP_SCOOP
-        select SHARP_PARAM
-        help
-          Say Y here if you intend to run this kernel on a
-          Sharp Zaurus SL-5600 (Poodle), SL-C700 (Corgi),
-          SL-C750 (Shepherd), SL-C760 (Husky), SL-C1000 (Akita),
-          SL-C3000 (Spitz), SL-C3100 (Borzoi) or SL-C6000x (Tosa)
-          handheld computer.
-config SHARPSL_PM
-        bool
-        select APM_EMULATION
-config CORGI_SSP_DEPRECATED
-        bool
-        select PXA_SSP
-        help
-          This option will include corgi_ssp.c and corgi_lcd.c
-          that corgi_ts.c and other legacy drivers (corgi_bl.c
-          and sharpsl_pm.c) may depend on.
-config MACH_POODLE
-        bool "Enable Sharp SL-5600 (Poodle) Support"
-        depends on PXA_SHARPSL
        select PXA25x
-        select SHARP_LOCOMO
+        select MTD
+        select MTD_PARTITIONS
+        select MTD_PHYSMAP
+        select MTD_CFI_INTELEXT
+        select MTD_CFI
+        select MTD_CHAR
+        select SMC91X
        select PXA_SSP
-config MACH_CORGI
-        bool "Enable Sharp SL-C700 (Corgi) Support"
-        depends on PXA_SHARPSL
-        select PXA25x
-        select PXA_SHARP_C7xx
-config MACH_SHEPHERD
-        bool "Enable Sharp SL-C750 (Shepherd) Support"
-        depends on PXA_SHARPSL
-        select PXA25x
-        select PXA_SHARP_C7xx
-config MACH_HUSKY
-        bool "Enable Sharp SL-C760 (Husky) Support"
-        depends on PXA_SHARPSL
-        select PXA25x
-        select PXA_SHARP_C7xx
-config MACH_AKITA
-        bool "Enable Sharp SL-1000 (Akita) Support"
-        depends on PXA_SHARPSL
-        select PXA27x
-        select PXA_SHARP_Cxx00
-        select MACH_SPITZ
-        select I2C
-        select I2C_PXA
-config MACH_SPITZ
-        bool "Enable Sharp Zaurus SL-3000 (Spitz) Support"
-        depends on PXA_SHARPSL
-        select PXA27x
-        select PXA_SHARP_Cxx00
-config MACH_BORZOI
-        bool "Enable Sharp Zaurus SL-3100 (Borzoi) Support"
-        depends on PXA_SHARPSL
-        select PXA27x
-        select PXA_SHARP_Cxx00
-config MACH_TOSA
-        bool "Enable Sharp SL-6000x (Tosa) Support"
-        depends on PXA_SHARPSL
-        select PXA25x
-        select PXA_HAVE_BOARD_IRQS
-config ARCH_VIPER
-        bool "Arcom/Eurotech VIPER SBC"
-        select PXA25x
-        select ISA
-        select I2C_GPIO
-        select HAVE_PWM
-        select PXA_HAVE_BOARD_IRQS
-        select PXA_HAVE_ISA_IRQS
-config ARCH_PXA_ESERIES
-        bool "PXA based Toshiba e-series PDAs"
-        select PXA25x
-        select PXA_HAVE_BOARD_IRQS
-config MACH_E330
-        bool "Toshiba e330"
-        default y
-        depends on ARCH_PXA_ESERIES
-        help
-          Say Y here if you intend to run this kernel on a Toshiba
-          e330 family PDA.
-config MACH_E350
-        bool "Toshiba e350"
-        default y
-        depends on ARCH_PXA_ESERIES
-        help
-          Say Y here if you intend to run this kernel on a Toshiba
-          e350 family PDA.
-config MACH_E740
-        bool "Toshiba e740"
-        default y
-        depends on ARCH_PXA_ESERIES
-        select FB_W100
-        help
-          Say Y here if you intend to run this kernel on a Toshiba
-          e740 family PDA.
-config MACH_E750
-        bool "Toshiba e750"
-        default y
-        depends on ARCH_PXA_ESERIES
-        select FB_W100
-        help
-          Say Y here if you intend to run this kernel on a Toshiba
-          e750 family PDA.
-config MACH_E400
-        bool "Toshiba e400"
-        default y
-        depends on ARCH_PXA_ESERIES
        help
-          Say Y here if you intend to run this kernel on a Toshiba
+          PXA255 based Single Board Computer with SMC 91C111 ethernet chip and 64 MB of flash.
-          e400 family PDA.
+          Tuned for usage in Libera instruments for particle accelerators.
-config MACH_E800
-        bool "Toshiba e800"
-        default y
-        depends on ARCH_PXA_ESERIES
-        select FB_W100
-        help
-          Say Y here if you intend to run this kernel on a Toshiba
-          e800 family PDA.
 config TRIZEPS_PXA
        bool "PXA based Keith und Koep Trizeps DIMM-Modules"
-config MACH_H5000
-        bool "HP iPAQ h5000"
-        select PXA25x
 config MACH_TRIZEPS4
        bool "Keith und Koep Trizeps4 DIMM-Module"
        depends on TRIZEPS_PXA
@@ -274,13 +184,38 @@ config TRIZEPS_PCMCIA
        help
          Enable PCMCIA support for Trizeps modules
-config MACH_EM_X270
+config MACH_LOGICPD_PXA270
-        bool "CompuLab EM-x270 platform"
+        bool "LogicPD PXA270 Card Engine Development Platform"
        select PXA27x
+        select HAVE_PWM
+        select PXA_HAVE_BOARD_IRQS
-config MACH_EXEDA
+config MACH_PCM027
-        bool "CompuLab eXeda platform"
+        bool "Phytec phyCORE-PXA270 CPU module (PCM-027)"
        select PXA27x
+        select IWMMXT
+        select PXA_SSP
+        select PXA_HAVE_BOARD_IRQS
+config MACH_PCM990_BASEBOARD
+        bool "PHYTEC PCM-990 development board"
+        select HAVE_PWM
+        depends on MACH_PCM027
+choice
+        prompt "display on pcm990"
+        depends on MACH_PCM990_BASEBOARD
+config PCM990_DISPLAY_SHARP
+        bool "sharp lq084v1dg21 stn display"
+config PCM990_DISPLAY_NEC
+        bool "nec nl6448bc20_18d tft display"
+config PCM990_DISPLAY_NONE
+        bool "no display"
+endchoice
 config MACH_COLIBRI
        bool "Toradex Colibri PXA270"
@@ -290,45 +225,15 @@ config MACH_COLIBRI300
        bool "Toradex Colibri PXA300/310"
        select PXA3xx
        select CPU_PXA300
+        select CPU_PXA310
+        select HAVE_PWM
 config MACH_COLIBRI320
        bool "Toradex Colibri PXA320"
        select PXA3xx
        select CPU_PXA320
-config MACH_ZYLONITE
+comment "End-user Products (sorted by vendor name)"
-        bool "PXA3xx Development Platform (aka Zylonite)"
-        select PXA3xx
-        select PXA_SSP
-        select HAVE_PWM
-        select PXA_HAVE_BOARD_IRQS
-config MACH_LITTLETON
-        bool "PXA3xx Form Factor Platform (aka Littleton)"
-        select PXA3xx
-        select PXA_SSP
-config MACH_TAVOREVB
-        bool "PXA930 Evaluation Board (aka TavorEVB)"
-        select PXA3xx
-        select CPU_PXA930
-config MACH_SAAR
-        bool "PXA930 Handheld Platform (aka SAAR)"
-        select PXA3xx
-        select CPU_PXA930
-config MACH_ARMCORE
-        bool "CompuLab CM-X255/CM-X270 modules"
-        select PXA27x
-        select IWMMXT
-        select PXA25x
-        select PXA_SSP
-config MACH_CM_X300
-        bool "CompuLab CM-X300 modules"
-        select PXA3xx
-        select CPU_PXA300
 config MACH_H4700
        bool "HP iPAQ hx4700"
@@ -338,6 +243,15 @@ config MACH_H4700
        select HAVE_PWM
        select PXA_HAVE_BOARD_IRQS
+config MACH_H5000
+        bool "HP iPAQ h5000"
+        select PXA25x
+config MACH_HIMALAYA
+        bool "HTC Himalaya Support"
+        select CPU_PXA26x
+        select FB_W100
 config MACH_MAGICIAN
        bool "Enable HTC Magician Support"
        select PXA27x
@@ -346,11 +260,6 @@ config MACH_MAGICIAN
        select HAVE_PWM
        select PXA_HAVE_BOARD_IRQS
-config MACH_HIMALAYA
-        bool "HTC Himalaya Support"
-        select CPU_PXA26x
-        select FB_W100
 config MACH_MIOA701
        bool "Mitac Mio A701 Support"
        select PXA27x
@@ -362,13 +271,47 @@ config MACH_MIOA701
          MIO A701. Currently there is only basic support
          for this PDA.
-config MACH_PCM027
+config PXA_EZX
-        bool "Phytec phyCORE-PXA270 CPU module (PCM-027)"
+        bool "Motorola EZX Platform"
        select PXA27x
        select IWMMXT
-        select PXA_SSP
+        select HAVE_PWM
        select PXA_HAVE_BOARD_IRQS
+config MACH_EZX_A780
+        bool "Motorola EZX A780"
+        default y
+        depends on PXA_EZX
+config MACH_EZX_E680
+        bool "Motorola EZX E680"
+        default y
+        depends on PXA_EZX
+config MACH_EZX_A1200
+        bool "Motorola EZX A1200"
+        default y
+        depends on PXA_EZX
+config MACH_EZX_A910
+        bool "Motorola EZX A910"
+        default y
+        depends on PXA_EZX
+config MACH_EZX_E6
+        bool "Motorola EZX E6"
+        default y
+        depends on PXA_EZX
+config MACH_EZX_E2
+        bool "Motorola EZX E2"
+        default y
+        depends on PXA_EZX
+config MACH_MP900C
+        bool "Nec Mobilepro 900/c"
+        select PXA25x
 config ARCH_PXA_PALM
        bool "PXA based Palm PDAs"
        select HAVE_PWM
@@ -421,109 +364,172 @@ config MACH_PALMZ72
          Say Y here if you intend to run this kernel on Palm Zire 72
          handheld computer.
-config MACH_TREO680
+config MACH_PALMLD
-        bool "Palm Treo 680"
+        bool "Palm LifeDrive"
        default y
        depends on ARCH_PXA_PALM
        select PXA27x
        select IWMMXT
        help
-          Say Y here if you intend to run this kernel on Palm Treo 680
+          Say Y here if you intend to run this kernel on a Palm LifeDrive
+          handheld computer.
+config PALM_TREO
+        bool
+        depends on ARCH_PXA_PALM
+config MACH_CENTRO
+        bool "Palm Centro 685 (GSM)"
+        default y
+        depends on ARCH_PXA_PALM
+        select PXA27x
+        select IWMMXT
+        select PALM_TREO
+        help
+          Say Y here if you intend to run this kernel on Palm Centro 685 (GSM)
          smartphone.
-config MACH_PALMLD
+config MACH_TREO680
-        bool "Palm LifeDrive"
+        bool "Palm Treo 680"
        default y
        depends on ARCH_PXA_PALM
        select PXA27x
        select IWMMXT
+        select PALM_TREO
        help
-          Say Y here if you intend to run this kernel on a Palm LifeDrive
+          Say Y here if you intend to run this kernel on Palm Treo 680
+          smartphone.
+config PXA_SHARPSL
+        bool "SHARP Zaurus SL-5600, SL-C7xx and SL-Cxx00 Models"
+        select SHARP_SCOOP
+        select SHARP_PARAM
+        help
+          Say Y here if you intend to run this kernel on a
+          Sharp Zaurus SL-5600 (Poodle), SL-C700 (Corgi),
+          SL-C750 (Shepherd), SL-C760 (Husky), SL-C1000 (Akita),
+          SL-C3000 (Spitz), SL-C3100 (Borzoi) or SL-C6000x (Tosa)
          handheld computer.
-config MACH_PCM990_BASEBOARD
+config SHARPSL_PM
-        bool "PHYTEC PCM-990 development board"
+        bool
-        select HAVE_PWM
+        select APM_EMULATION
-        depends on MACH_PCM027
-choice
+config CORGI_SSP_DEPRECATED
-        prompt "display on pcm990"
+        bool
-        depends on MACH_PCM990_BASEBOARD
+        select PXA_SSP
+        help
+          This option will include corgi_ssp.c and corgi_lcd.c
+          that corgi_ts.c and other legacy drivers (corgi_bl.c
+          and sharpsl_pm.c) may depend on.
-config PCM990_DISPLAY_SHARP
+config MACH_POODLE
-        bool "sharp lq084v1dg21 stn display"
+        bool "Enable Sharp SL-5600 (Poodle) Support"
+        depends on PXA_SHARPSL
+        select PXA25x
+        select SHARP_LOCOMO
+        select PXA_SSP
-config PCM990_DISPLAY_NEC
+config MACH_CORGI
-        bool "nec nl6448bc20_18d tft display"
+        bool "Enable Sharp SL-C700 (Corgi) Support"
+        depends on PXA_SHARPSL
+        select PXA25x
+        select PXA_SHARP_C7xx
-config PCM990_DISPLAY_NONE
+config MACH_SHEPHERD
-        bool "no display"
+        bool "Enable Sharp SL-C750 (Shepherd) Support"
+        depends on PXA_SHARPSL
+        select PXA25x
+        select PXA_SHARP_C7xx
-endchoice
+config MACH_HUSKY
+        bool "Enable Sharp SL-C760 (Husky) Support"
+        depends on PXA_SHARPSL
+        select PXA25x
+        select PXA_SHARP_C7xx
-config MACH_CSB726
+config MACH_AKITA
-        bool "Enable Cogent CSB726 System On a Module"
+        bool "Enable Sharp SL-1000 (Akita) Support"
+        depends on PXA_SHARPSL
        select PXA27x
-        select IWMMXT
+        select PXA_SHARP_Cxx00
-        help
+        select MACH_SPITZ
-          Say Y here if you intend to run this kernel on a Cogent
+        select I2C
-          CSB726 System On Module.
+        select I2C_PXA
-config CSB726_CSB701
+config MACH_SPITZ
-        bool "Enable supprot for CSB701 baseboard"
+        bool "Enable Sharp Zaurus SL-3000 (Spitz) Support"
-        depends on MACH_CSB726
+        depends on PXA_SHARPSL
+        select PXA27x
+        select PXA_SHARP_Cxx00
-config PXA_EZX
+config MACH_BORZOI
-        bool "Motorola EZX Platform"
+        bool "Enable Sharp Zaurus SL-3100 (Borzoi) Support"
+        depends on PXA_SHARPSL
        select PXA27x
-        select IWMMXT
+        select PXA_SHARP_Cxx00
-        select HAVE_PWM
+config MACH_TOSA
+        bool "Enable Sharp SL-6000x (Tosa) Support"
+        depends on PXA_SHARPSL
+        select PXA25x
        select PXA_HAVE_BOARD_IRQS
-config MACH_EZX_A780
+config ARCH_PXA_ESERIES
-        bool "Motorola EZX A780"
+        bool "PXA based Toshiba e-series PDAs"
-        default y
+        select PXA25x
-        depends on PXA_EZX
+        select PXA_HAVE_BOARD_IRQS
-config MACH_EZX_E680
+config MACH_E330
-        bool "Motorola EZX E680"
+        bool "Toshiba e330"
        default y
-        depends on PXA_EZX
+        depends on ARCH_PXA_ESERIES
+        help
+          Say Y here if you intend to run this kernel on a Toshiba
+          e330 family PDA.
-config MACH_EZX_A1200
+config MACH_E350
-        bool "Motorola EZX A1200"
+        bool "Toshiba e350"
        default y
-        depends on PXA_EZX
+        depends on ARCH_PXA_ESERIES
+        help
+          Say Y here if you intend to run this kernel on a Toshiba
+          e350 family PDA.
-config MACH_EZX_A910
+config MACH_E740
-        bool "Motorola EZX A910"
+        bool "Toshiba e740"
        default y
-        depends on PXA_EZX
+        depends on ARCH_PXA_ESERIES
+        select FB_W100
+        help
+          Say Y here if you intend to run this kernel on a Toshiba
+          e740 family PDA.
-config MACH_EZX_E6
+config MACH_E750
-        bool "Motorola EZX E6"
+        bool "Toshiba e750"
        default y
-        depends on PXA_EZX
+        depends on ARCH_PXA_ESERIES
+        select FB_W100
+        help
+          Say Y here if you intend to run this kernel on a Toshiba
+          e750 family PDA.
-config MACH_EZX_E2
+config MACH_E400
-        bool "Motorola EZX E2"
+        bool "Toshiba e400"
        default y
-        depends on PXA_EZX
+        depends on ARCH_PXA_ESERIES
+        help
+          Say Y here if you intend to run this kernel on a Toshiba
+          e400 family PDA.
-config MACH_XCEP
+config MACH_E800
-        bool "Iskratel Electronics XCEP"
+        bool "Toshiba e800"
-        select PXA25x
+        default y
-        select MTD
+        depends on ARCH_PXA_ESERIES
-        select MTD_PARTITIONS
+        select FB_W100
-        select MTD_PHYSMAP
-        select MTD_CFI_INTELEXT
-        select MTD_CFI
-        select MTD_CHAR
-        select SMC91X
-        select PXA_SSP
        help
-          PXA255 based Single Board Computer with SMC 91C111 ethernet chip and 64 MB of flash.
+          Say Y here if you intend to run this kernel on a Toshiba
-          Tuned for usage in Libera instruments for particle accelerators.
+          e800 family PDA.
 endmenu
@@ -551,6 +557,42 @@ config PXA3xx
        help
          Select code specific to PXA3xx variants
+config CPU_PXA300
+        bool
+        select PXA3xx
+        help
+          PXA300 (codename Monahans-L)
+config CPU_PXA310
+        bool
+        select CPU_PXA300
+        help
+          PXA310 (codename Monahans-LV)
+config CPU_PXA320
+        bool
+        select PXA3xx
+        help
+          PXA320 (codename Monahans-P)
+config CPU_PXA930
+        bool
+        select PXA3xx
+        help
+          PXA930 (codename Tavor-P)
+config CPU_PXA935
+        bool
+        select CPU_PXA930
+        help
+          PXA935 (codename Tavor-P65)
+config CPU_PXA950
+        bool
+        select CPU_PXA930
+        help
+          PXA950 (codename Tavor-PV2)
 config PXA_SHARP_C7xx
        bool
        select PXA_SSP
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index f10e152bfc27..b5d29e60a341 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -24,33 +24,63 @@ obj-$(CONFIG_CPU_PXA300)	+= pxa300.o
 obj-$(CONFIG_CPU_PXA320)        += pxa320.o
 obj-$(CONFIG_CPU_PXA930)        += pxa930.o
-# Specific board support
+# NOTE: keep the order of boards in accordance to their order in Kconfig
-obj-$(CONFIG_ARCH_GUMSTIX)      += gumstix.o
-obj-$(CONFIG_GUMSTIX_AM200EPD)  += am200epd.o
+# Intel/Marvell Dev Platforms
-obj-$(CONFIG_GUMSTIX_AM300EPD)  += am300epd.o
 obj-$(CONFIG_ARCH_LUBBOCK)      += lubbock.o
-obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o
 obj-$(CONFIG_MACH_MAINSTONE)    += mainstone.o
-obj-$(CONFIG_MACH_BALLOON3)     += balloon3.o
+obj-$(CONFIG_MACH_ZYLONITE300)  += zylonite.o zylonite_pxa300.o
-obj-$(CONFIG_MACH_MP900C)       += mp900.o
+obj-$(CONFIG_MACH_ZYLONITE320)  += zylonite.o zylonite_pxa320.o
+obj-$(CONFIG_MACH_LITTLETON)    += littleton.o
+obj-$(CONFIG_MACH_TAVOREVB)     += tavorevb.o
+obj-$(CONFIG_MACH_SAAR)         += saar.o
+# 3rd Party Dev Platforms
 obj-$(CONFIG_ARCH_PXA_IDP)      += idp.o
+obj-$(CONFIG_ARCH_VIPER)        += viper.o
+obj-$(CONFIG_MACH_BALLOON3)     += balloon3.o
+obj-$(CONFIG_MACH_CSB726)       += csb726.o
+obj-$(CONFIG_CSB726_CSB701)     += csb701.o
+obj-$(CONFIG_MACH_ARMCORE)      += cm-x2xx.o cm-x255.o cm-x270.o
+ifeq ($(CONFIG_PCI),y)
+obj-$(CONFIG_MACH_ARMCORE)      += cm-x2xx-pci.o
+endif
+obj-$(CONFIG_MACH_EM_X270)      += em-x270.o
+obj-$(CONFIG_MACH_CM_X300)      += cm-x300.o
+obj-$(CONFIG_ARCH_GUMSTIX)      += gumstix.o
+obj-$(CONFIG_GUMSTIX_AM200EPD)  += am200epd.o
+obj-$(CONFIG_GUMSTIX_AM300EPD)  += am300epd.o
+obj-$(CONFIG_MACH_INTELMOTE2)   += imote2.o
+obj-$(CONFIG_MACH_STARGATE2)    += stargate2.o
+obj-$(CONFIG_MACH_XCEP)         += xcep.o
 obj-$(CONFIG_MACH_TRIZEPS4)     += trizeps4.o
+obj-$(CONFIG_MACH_LOGICPD_PXA270)       += lpd270.o
+obj-$(CONFIG_MACH_PCM027)               += pcm027.o
+obj-$(CONFIG_MACH_PCM990_BASEBOARD)     += pcm990-baseboard.o
 obj-$(CONFIG_MACH_COLIBRI)      += colibri-pxa270.o
 obj-$(CONFIG_MACH_COLIBRI300)   += colibri-pxa3xx.o colibri-pxa300.o
 obj-$(CONFIG_MACH_COLIBRI320)   += colibri-pxa3xx.o colibri-pxa320.o
+# End-user Products
+obj-$(CONFIG_MACH_H4700)        += hx4700.o
 obj-$(CONFIG_MACH_H5000)        += h5000.o
+obj-$(CONFIG_MACH_HIMALAYA)     += himalaya.o
+obj-$(CONFIG_MACH_MAGICIAN)     += magician.o
+obj-$(CONFIG_MACH_MIOA701)      += mioa701.o mioa701_bootresume.o
+obj-$(CONFIG_PXA_EZX)           += ezx.o
+obj-$(CONFIG_MACH_MP900C)       += mp900.o
+obj-$(CONFIG_MACH_PALMTE2)      += palmte2.o
+obj-$(CONFIG_MACH_PALMTC)       += palmtc.o
+obj-$(CONFIG_MACH_PALMT5)       += palmt5.o
+obj-$(CONFIG_MACH_PALMTX)       += palmtx.o
+obj-$(CONFIG_MACH_PALMZ72)      += palmz72.o
+obj-$(CONFIG_MACH_PALMLD)       += palmld.o
+obj-$(CONFIG_PALM_TREO)         += palmtreo.o
 obj-$(CONFIG_PXA_SHARP_C7xx)    += corgi.o sharpsl_pm.o corgi_pm.o
 obj-$(CONFIG_PXA_SHARP_Cxx00)   += spitz.o sharpsl_pm.o spitz_pm.o
 obj-$(CONFIG_CORGI_SSP_DEPRECATED)      += corgi_ssp.o corgi_lcd.o
 obj-$(CONFIG_MACH_POODLE)       += poodle.o
-obj-$(CONFIG_MACH_PCM027)       += pcm027.o
-obj-$(CONFIG_MACH_PCM990_BASEBOARD)     += pcm990-baseboard.o
 obj-$(CONFIG_MACH_TOSA)         += tosa.o
-obj-$(CONFIG_MACH_EM_X270)      += em-x270.o
-obj-$(CONFIG_MACH_H4700)        += hx4700.o
-obj-$(CONFIG_MACH_MAGICIAN)     += magician.o
-obj-$(CONFIG_MACH_HIMALAYA)     += himalaya.o
-obj-$(CONFIG_MACH_MIOA701)      += mioa701.o mioa701_bootresume.o
 obj-$(CONFIG_ARCH_PXA_ESERIES)  += eseries.o
 obj-$(CONFIG_MACH_E330)         += e330.o
 obj-$(CONFIG_MACH_E350)         += e350.o
@@ -58,34 +88,6 @@ obj-$(CONFIG_MACH_E740)		+= e740.o
 obj-$(CONFIG_MACH_E750)         += e750.o
 obj-$(CONFIG_MACH_E400)         += e400.o
 obj-$(CONFIG_MACH_E800)         += e800.o
-obj-$(CONFIG_MACH_PALMTE2)      += palmte2.o
-obj-$(CONFIG_MACH_PALMTC)       += palmtc.o
-obj-$(CONFIG_MACH_PALMT5)       += palmt5.o
-obj-$(CONFIG_MACH_PALMTX)       += palmtx.o
-obj-$(CONFIG_MACH_PALMLD)       += palmld.o
-obj-$(CONFIG_MACH_PALMZ72)      += palmz72.o
-obj-$(CONFIG_MACH_TREO680)      += treo680.o
-obj-$(CONFIG_ARCH_VIPER)        += viper.o
-ifeq ($(CONFIG_MACH_ZYLONITE),y)
-  obj-y                         += zylonite.o
-  obj-$(CONFIG_CPU_PXA300)      += zylonite_pxa300.o
-  obj-$(CONFIG_CPU_PXA320)      += zylonite_pxa320.o
-endif
-obj-$(CONFIG_MACH_LITTLETON)    += littleton.o
-obj-$(CONFIG_MACH_TAVOREVB)     += tavorevb.o
-obj-$(CONFIG_MACH_SAAR)         += saar.o
-obj-$(CONFIG_MACH_ARMCORE)      += cm-x2xx.o cm-x255.o cm-x270.o
-obj-$(CONFIG_MACH_CM_X300)      += cm-x300.o
-obj-$(CONFIG_PXA_EZX)           += ezx.o
-obj-$(CONFIG_MACH_XCEP)         += xcep.o
-obj-$(CONFIG_MACH_INTELMOTE2)   += imote2.o
-obj-$(CONFIG_MACH_STARGATE2)    += stargate2.o
-obj-$(CONFIG_MACH_CSB726)       += csb726.o
-obj-$(CONFIG_CSB726_CSB701)     += csb701.o
 # Support for blinky lights
 led-y := leds.o
@@ -95,8 +97,4 @@ led-$(CONFIG_ARCH_PXA_IDP)	+= leds-idp.o
 obj-$(CONFIG_LEDS)              += $(led-y)
-ifeq ($(CONFIG_PCI),y)
-obj-$(CONFIG_MACH_ARMCORE) += cm-x2xx-pci.o
-endif
 obj-$(CONFIG_TOSA_BT)           += tosa-bt.o
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c
index f23138b8fca3..b8cd07ca9380 100644
--- a/arch/arm/mach-pxa/balloon3.c
+++ b/arch/arm/mach-pxa/balloon3.c
@@ -306,6 +306,10 @@ static void __init balloon3_init(void)
         */
        ARB_CNTRL = ARB_CORE_PARK | 0x234;
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        pxa_set_i2c_info(NULL);
        if (balloon3_has(BALLOON3_FEATURE_AUDIO))
                pxa_set_ac97_info(NULL);
diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c
index b50ef39eabfc..bff6e78f033d 100644
--- a/arch/arm/mach-pxa/cm-x2xx.c
+++ b/arch/arm/mach-pxa/cm-x2xx.c
@@ -453,6 +453,10 @@ static inline void cmx2xx_init_ac97(void) {}
 static void __init cmx2xx_init(void)
 {
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        cmx2xx_pm_init();
        if (cpu_is_pxa25x())
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index 102916f1e465..d37cfa132a65 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -3,9 +3,10 @@
 *
 * Support for the CompuLab CM-X300 modules
 *
- * Copyright (C) 2008 CompuLab Ltd.
+ * Copyright (C) 2008,2009 CompuLab Ltd.
 *
 * Mike Rapoport <mike@compulab.co.il>
+ * Igor Grinberg <grinberg@compulab.co.il>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
@@ -16,30 +17,41 @@
 #include <linux/kernel.h>
 #include <linux/interrupt.h>
 #include <linux/init.h>
+#include <linux/delay.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/dm9000.h>
 #include <linux/leds.h>
 #include <linux/rtc-v3020.h>
+#include <linux/pwm_backlight.h>
 #include <linux/i2c.h>
 #include <linux/i2c/pca953x.h>
+#include <linux/mfd/da903x.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi_gpio.h>
+#include <linux/spi/tdo24m.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/setup.h>
 #include <mach/pxa300.h>
+#include <mach/pxa27x-udc.h>
 #include <mach/pxafb.h>
 #include <mach/mmc.h>
 #include <mach/ohci.h>
 #include <plat/i2c.h>
-#include <mach/pxa3xx_nand.h>
+#include <plat/pxa3xx_nand.h>
+#include <mach/audio.h>
 #include <asm/mach/map.h>
 #include "generic.h"
+#include "devices.h"
 #define CM_X300_ETH_PHYS        0x08000010
@@ -53,7 +65,7 @@
 #define GPIO97_RTC_RD           (97)
 #define GPIO98_RTC_IO           (98)
-static mfp_cfg_t cm_x300_mfp_cfg[] __initdata = {
+static mfp_cfg_t cm_x3xx_mfp_cfg[] __initdata = {
        /* LCD */
        GPIO54_LCD_LDD_0,
        GPIO55_LCD_LDD_1,
@@ -137,7 +149,6 @@ static mfp_cfg_t cm_x300_mfp_cfg[] __initdata = {
        GPIO36_UART1_DTR,
        /* GPIOs */
-        GPIO79_GPIO,                    /* LED */
        GPIO82_GPIO | MFP_PULL_HIGH,    /* MMC CD */
        GPIO85_GPIO,                    /* MMC WP */
        GPIO99_GPIO,                    /* Ethernet IRQ */
@@ -151,6 +162,50 @@ static mfp_cfg_t cm_x300_mfp_cfg[] __initdata = {
        /* Standard I2C */
        GPIO21_I2C_SCL,
        GPIO22_I2C_SDA,
+        /* PWM Backlight */
+        GPIO19_PWM2_OUT,
+};
+static mfp_cfg_t cm_x3xx_rev_lt130_mfp_cfg[] __initdata = {
+        /* GPIOs */
+        GPIO79_GPIO,                    /* LED */
+        GPIO77_GPIO,                    /* WiFi reset */
+        GPIO78_GPIO,                    /* BT reset */
+};
+static mfp_cfg_t cm_x3xx_rev_ge130_mfp_cfg[] __initdata = {
+        /* GPIOs */
+        GPIO76_GPIO,                    /* LED */
+        GPIO71_GPIO,                    /* WiFi reset */
+        GPIO70_GPIO,                    /* BT reset */
+};
+static mfp_cfg_t cm_x310_mfp_cfg[] __initdata = {
+        /* USB PORT 2 */
+        ULPI_STP,
+        ULPI_NXT,
+        ULPI_DIR,
+        GPIO30_ULPI_DATA_OUT_0,
+        GPIO31_ULPI_DATA_OUT_1,
+        GPIO32_ULPI_DATA_OUT_2,
+        GPIO33_ULPI_DATA_OUT_3,
+        GPIO34_ULPI_DATA_OUT_4,
+        GPIO35_ULPI_DATA_OUT_5,
+        GPIO36_ULPI_DATA_OUT_6,
+        GPIO37_ULPI_DATA_OUT_7,
+        GPIO38_ULPI_CLK,
+        /* external PHY reset pin */
+        GPIO127_GPIO,
+        /* USB PORT 3 */
+        GPIO77_USB_P3_1,
+        GPIO78_USB_P3_2,
+        GPIO79_USB_P3_3,
+        GPIO80_USB_P3_4,
+        GPIO81_USB_P3_5,
+        GPIO82_USB_P3_6,
+        GPIO0_2_USBH_PEN,
 };
 #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
@@ -195,17 +250,18 @@ static void __init cm_x300_init_dm9000(void)
 static inline void cm_x300_init_dm9000(void) {}
 #endif
+/* LCD */
 #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
 static struct pxafb_mode_info cm_x300_lcd_modes[] = {
        [0] = {
-                .pixclock       = 38000,
+                .pixclock       = 38250,
                .bpp            = 16,
                .xres           = 480,
                .yres           = 640,
                .hsync_len      = 8,
                .vsync_len      = 2,
                .left_margin    = 8,
-                .upper_margin   = 0,
+                .upper_margin   = 2,
                .right_margin   = 24,
                .lower_margin   = 4,
                .cmap_greyscale = 0,
@@ -227,7 +283,7 @@ static struct pxafb_mode_info cm_x300_lcd_modes[] = {
 static struct pxafb_mach_info cm_x300_lcd = {
        .modes                  = cm_x300_lcd_modes,
-        .num_modes              = 2,
+        .num_modes              = ARRAY_SIZE(cm_x300_lcd_modes),
        .lcd_conn               = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
 };
@@ -239,6 +295,87 @@ static void __init cm_x300_init_lcd(void)
 static inline void cm_x300_init_lcd(void) {}
 #endif
+#if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE)
+static struct platform_pwm_backlight_data cm_x300_backlight_data = {
+        .pwm_id         = 2,
+        .max_brightness = 100,
+        .dft_brightness = 100,
+        .pwm_period_ns  = 10000,
+};
+static struct platform_device cm_x300_backlight_device = {
+        .name           = "pwm-backlight",
+        .dev            = {
+                .parent = &pxa27x_device_pwm0.dev,
+                .platform_data  = &cm_x300_backlight_data,
+        },
+};
+static void cm_x300_init_bl(void)
+{
+        platform_device_register(&cm_x300_backlight_device);
+}
+#else
+static inline void cm_x300_init_bl(void) {}
+#endif
+#if defined(CONFIG_SPI_GPIO) || defined(CONFIG_SPI_GPIO_MODULE)
+#define GPIO_LCD_BASE   (144)
+#define GPIO_LCD_DIN    (GPIO_LCD_BASE + 8)     /* aux_gpio3_0 */
+#define GPIO_LCD_DOUT   (GPIO_LCD_BASE + 9)     /* aux_gpio3_1 */
+#define GPIO_LCD_SCL    (GPIO_LCD_BASE + 10)    /* aux_gpio3_2 */
+#define GPIO_LCD_CS     (GPIO_LCD_BASE + 11)    /* aux_gpio3_3 */
+#define LCD_SPI_BUS_NUM (1)
+static struct spi_gpio_platform_data cm_x300_spi_gpio_pdata = {
+        .sck            = GPIO_LCD_SCL,
+        .mosi           = GPIO_LCD_DIN,
+        .miso           = GPIO_LCD_DOUT,
+        .num_chipselect = 1,
+};
+static struct platform_device cm_x300_spi_gpio = {
+        .name           = "spi_gpio",
+        .id             = LCD_SPI_BUS_NUM,
+        .dev            = {
+                .platform_data  = &cm_x300_spi_gpio_pdata,
+        },
+};
+static struct tdo24m_platform_data cm_x300_tdo24m_pdata = {
+        .model = TDO35S,
+};
+static struct spi_board_info cm_x300_spi_devices[] __initdata = {
+        {
+                .modalias               = "tdo24m",
+                .max_speed_hz           = 1000000,
+                .bus_num                = LCD_SPI_BUS_NUM,
+                .chip_select            = 0,
+                .controller_data        = (void *) GPIO_LCD_CS,
+                .platform_data          = &cm_x300_tdo24m_pdata,
+        },
+};
+static void __init cm_x300_init_spi(void)
+{
+        spi_register_board_info(cm_x300_spi_devices,
+                                ARRAY_SIZE(cm_x300_spi_devices));
+        platform_device_register(&cm_x300_spi_gpio);
+}
+#else
+static inline void cm_x300_init_spi(void) {}
+#endif
+#if defined(CONFIG_SND_PXA2XX_LIB_AC97)
+static void __init cm_x300_init_ac97(void)
+{
+        pxa_set_ac97_info(NULL);
+}
+#else
+static inline void cm_x300_init_ac97(void) {}
+#endif
 #if defined(CONFIG_MTD_NAND_PXA3xx) || defined(CONFIG_MTD_NAND_PXA3xx_MODULE)
 static struct mtd_partition cm_x300_nand_partitions[] = {
        [0] = {
@@ -333,9 +470,19 @@ static inline void cm_x300_init_mmc(void) {}
 #endif
 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+static int cm_x300_ohci_init(struct device *dev)
+{
+        if (cpu_is_pxa300())
+                UP2OCR = UP2OCR_HXS
+                        | UP2OCR_HXOE | UP2OCR_DMPDE | UP2OCR_DPPDE;
+        return 0;
+}
 static struct pxaohci_platform_data cm_x300_ohci_platform_data = {
        .port_mode      = PMM_PERPORT_MODE,
-        .flags          = ENABLE_PORT1 | ENABLE_PORT2 | POWER_CONTROL_LOW,
+        .flags          = ENABLE_PORT_ALL | POWER_CONTROL_LOW,
+        .init           = cm_x300_ohci_init,
 };
 static void __init cm_x300_init_ohci(void)
@@ -351,7 +498,6 @@ static struct gpio_led cm_x300_leds[] = {
        [0] = {
                .name = "cm-x300:green",
                .default_trigger = "heartbeat",
-                .gpio = 79,
                .active_low = 1,
        },
 };
@@ -371,6 +517,11 @@ static struct platform_device cm_x300_led_device = {
 static void __init cm_x300_init_leds(void)
 {
+        if (system_rev < 130)
+                cm_x300_leds[0].gpio = 79;
+        else
+                cm_x300_leds[0].gpio = 76;
        platform_device_register(&cm_x300_led_device);
 }
 #else
@@ -433,11 +584,94 @@ static void __init cm_x300_init_rtc(void)
 static inline void cm_x300_init_rtc(void) {}
 #endif
-static void __init cm_x300_init(void)
+/* DA9030 */
+struct da903x_subdev_info cm_x300_da9030_subdevs[] = {
+        {
+                .name = "da903x-backlight",
+                .id = DA9030_ID_WLED,
+        }
+};
+static struct da903x_platform_data cm_x300_da9030_info = {
+        .num_subdevs = ARRAY_SIZE(cm_x300_da9030_subdevs),
+        .subdevs = cm_x300_da9030_subdevs,
+};
+static struct i2c_board_info cm_x300_pmic_info = {
+        I2C_BOARD_INFO("da9030", 0x49),
+        .irq = IRQ_GPIO(0),
+        .platform_data = &cm_x300_da9030_info,
+};
+static struct i2c_pxa_platform_data cm_x300_pwr_i2c_info = {
+        .use_pio = 1,
+};
+static void __init cm_x300_init_da9030(void)
+{
+        pxa3xx_set_i2c_power_info(&cm_x300_pwr_i2c_info);
+        i2c_register_board_info(1, &cm_x300_pmic_info, 1);
+}
+static void __init cm_x300_init_wi2wi(void)
+{
+        int bt_reset, wlan_en;
+        int err;
+        if (system_rev < 130) {
+                wlan_en = 77;
+                bt_reset = 78;
+        } else {
+                wlan_en = 71;
+                bt_reset = 70;
+        }
+        /* Libertas and CSR reset */
+        err = gpio_request(wlan_en, "wlan en");
+        if (err) {
+                pr_err("CM-X300: failed to request wlan en gpio: %d\n", err);
+        } else {
+                gpio_direction_output(wlan_en, 1);
+                gpio_free(wlan_en);
+        }
+        err = gpio_request(bt_reset, "bt reset");
+        if (err) {
+                pr_err("CM-X300: failed to request bt reset gpio: %d\n", err);
+        } else {
+                gpio_direction_output(bt_reset, 1);
+                udelay(10);
+                gpio_set_value(bt_reset, 0);
+                udelay(10);
+                gpio_set_value(bt_reset, 1);
+                gpio_free(bt_reset);
+        }
+}
+/* MFP */
+static void __init cm_x300_init_mfp(void)
 {
        /* board-processor specific GPIO initialization */
-        pxa3xx_mfp_config(ARRAY_AND_SIZE(cm_x300_mfp_cfg));
+        pxa3xx_mfp_config(ARRAY_AND_SIZE(cm_x3xx_mfp_cfg));
+        if (system_rev < 130)
+                pxa3xx_mfp_config(ARRAY_AND_SIZE(cm_x3xx_rev_lt130_mfp_cfg));
+        else
+                pxa3xx_mfp_config(ARRAY_AND_SIZE(cm_x3xx_rev_ge130_mfp_cfg));
+        if (cpu_is_pxa310())
+                pxa3xx_mfp_config(ARRAY_AND_SIZE(cm_x310_mfp_cfg));
+}
+static void __init cm_x300_init(void)
+{
+        cm_x300_init_mfp();
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
+        cm_x300_init_da9030();
        cm_x300_init_dm9000();
        cm_x300_init_lcd();
        cm_x300_init_ohci();
@@ -445,7 +679,11 @@ static void __init cm_x300_init(void)
        cm_x300_init_nand();
        cm_x300_init_leds();
        cm_x300_init_i2c();
+        cm_x300_init_spi();
        cm_x300_init_rtc();
+        cm_x300_init_ac97();
+        cm_x300_init_wi2wi();
+        cm_x300_init_bl();
 }
 static void __init cm_x300_fixup(struct machine_desc *mdesc, struct tag *tags,
diff --git a/arch/arm/mach-pxa/colibri-pxa270.c b/arch/arm/mach-pxa/colibri-pxa270.c
index 01bcfaae75bc..061c45316de8 100644
--- a/arch/arm/mach-pxa/colibri-pxa270.c
+++ b/arch/arm/mach-pxa/colibri-pxa270.c
@@ -130,6 +130,9 @@ static struct platform_device *colibri_pxa270_devices[] __initdata = {
 static void __init colibri_pxa270_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa270_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        platform_add_devices(ARRAY_AND_SIZE(colibri_pxa270_devices));
 }
diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c
index 37c239c56568..45c23fd6df31 100644
--- a/arch/arm/mach-pxa/colibri-pxa300.c
+++ b/arch/arm/mach-pxa/colibri-pxa300.c
@@ -170,6 +170,10 @@ static inline void colibri_pxa310_init_ac97(void) {}
 void __init colibri_pxa300_init(void)
 {
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        colibri_pxa300_init_eth();
        colibri_pxa300_init_ohci();
        colibri_pxa3xx_init_nand();
diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c
index ec0e14b96682..ae835fad7d10 100644
--- a/arch/arm/mach-pxa/colibri-pxa320.c
+++ b/arch/arm/mach-pxa/colibri-pxa320.c
@@ -199,6 +199,10 @@ static void __init colibri_pxa320_init_uart(void)
 void __init colibri_pxa320_init(void)
 {
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        colibri_pxa320_init_eth();
        colibri_pxa320_init_ohci();
        colibri_pxa3xx_init_nand();
diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c b/arch/arm/mach-pxa/colibri-pxa3xx.c
index efebaf4d734d..e6c0a2287eb8 100644
--- a/arch/arm/mach-pxa/colibri-pxa3xx.c
+++ b/arch/arm/mach-pxa/colibri-pxa3xx.c
@@ -25,7 +25,7 @@
 #include <mach/colibri.h>
 #include <mach/mmc.h>
 #include <mach/pxafb.h>
-#include <mach/pxa3xx_nand.h>
+#include <plat/pxa3xx_nand.h>
 #include "generic.h"
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index b536b5a5a10d..74446cf8ae69 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -671,6 +671,10 @@ static void __init corgi_init(void)
        pxa2xx_mfp_config(ARRAY_AND_SIZE(corgi_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        corgi_init_spi();
        pxa_set_udc_info(&udc_info);
diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c
index a093282fe4db..d4a0733e905b 100644
--- a/arch/arm/mach-pxa/corgi_pm.c
+++ b/arch/arm/mach-pxa/corgi_pm.c
@@ -214,8 +214,8 @@ static struct sharpsl_charger_machinfo corgi_pm_machinfo = {
        .fatal_acin_volt  = SHARPSL_FATAL_ACIN_VOLT,
        .fatal_noacin_volt= SHARPSL_FATAL_NOACIN_VOLT,
        .bat_levels       = 40,
-        .bat_levels_noac  = spitz_battery_levels_noac,
+        .bat_levels_noac  = sharpsl_battery_levels_noac,
-        .bat_levels_acin  = spitz_battery_levels_acin,
+        .bat_levels_acin  = sharpsl_battery_levels_acin,
        .status_high_acin = 188,
        .status_low_acin  = 178,
        .status_high_noac = 185,
diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c
index 965480eb4fe6..88575b87bd33 100644
--- a/arch/arm/mach-pxa/csb726.c
+++ b/arch/arm/mach-pxa/csb726.c
@@ -268,6 +268,9 @@ static void __init csb726_init(void)
 /*      MSC2 = 0x06697ff4; *//* none/SM501 */
        MSC2 = (MSC2 & ~0xffff) | 0x7ff4; /* SM501 */
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        pxa_set_i2c_info(NULL);
        pxa27x_set_i2c_power_info(NULL);
        pxa_set_mci_info(&csb726_mci);
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index 46fabe1cca11..3395463bb5a6 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -4,17 +4,18 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
+#include <mach/hardware.h>
 #include <mach/udc.h>
 #include <mach/pxafb.h>
 #include <mach/mmc.h>
 #include <mach/irda.h>
-#include <plat/i2c.h>
 #include <mach/ohci.h>
 #include <mach/pxa27x_keypad.h>
 #include <mach/pxa2xx_spi.h>
 #include <mach/camera.h>
 #include <mach/audio.h>
-#include <mach/pxa3xx_nand.h>
+#include <plat/i2c.h>
+#include <plat/pxa3xx_nand.h>
 #include "devices.h"
 #include "generic.h"
@@ -167,13 +168,18 @@ static struct resource pxa_resource_ffuart[] = {
        }
 };
-struct platform_device pxa_device_ffuart= {
+struct platform_device pxa_device_ffuart = {
        .name           = "pxa2xx-uart",
        .id             = 0,
        .resource       = pxa_resource_ffuart,
        .num_resources  = ARRAY_SIZE(pxa_resource_ffuart),
 };
+void __init pxa_set_ffuart_info(void *info)
+{
+        pxa_register_device(&pxa_device_ffuart, info);
+}
 static struct resource pxa_resource_btuart[] = {
        {
                .start  = 0x40200000,
@@ -193,6 +199,11 @@ struct platform_device pxa_device_btuart = {
        .num_resources  = ARRAY_SIZE(pxa_resource_btuart),
 };
+void __init pxa_set_btuart_info(void *info)
+{
+        pxa_register_device(&pxa_device_btuart, info);
+}
 static struct resource pxa_resource_stuart[] = {
        {
                .start  = 0x40700000,
@@ -212,6 +223,11 @@ struct platform_device pxa_device_stuart = {
        .num_resources  = ARRAY_SIZE(pxa_resource_stuart),
 };
+void __init pxa_set_stuart_info(void *info)
+{
+        pxa_register_device(&pxa_device_stuart, info);
+}
 static struct resource pxa_resource_hwuart[] = {
        {
                .start  = 0x41600000,
@@ -231,6 +247,14 @@ struct platform_device pxa_device_hwuart = {
        .num_resources  = ARRAY_SIZE(pxa_resource_hwuart),
 };
+void __init pxa_set_hwuart_info(void *info)
+{
+        if (cpu_is_pxa255())
+                pxa_register_device(&pxa_device_hwuart, info);
+        else
+                pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware");
+}
 static struct resource pxai2c_resources[] = {
        {
                .start  = 0x40301680,
diff --git a/arch/arm/mach-pxa/e330.c b/arch/arm/mach-pxa/e330.c
index 74d3f8987c5c..8fde3387279d 100644
--- a/arch/arm/mach-pxa/e330.c
+++ b/arch/arm/mach-pxa/e330.c
@@ -55,6 +55,9 @@ static struct platform_device *devices[] __initdata = {
 static void __init e330_init(void)
 {
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        eseries_register_clks();
        eseries_get_tmio_gpios();
        platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-pxa/e350.c b/arch/arm/mach-pxa/e350.c
index 080036272131..f50f055f5720 100644
--- a/arch/arm/mach-pxa/e350.c
+++ b/arch/arm/mach-pxa/e350.c
@@ -56,6 +56,9 @@ static struct platform_device *devices[] __initdata = {
 static void __init e350_init(void)
 {
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        eseries_register_clks();
        eseries_get_tmio_gpios();
        platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-pxa/e400.c b/arch/arm/mach-pxa/e400.c
index ed9c0c3f64a2..55b950f12844 100644
--- a/arch/arm/mach-pxa/e400.c
+++ b/arch/arm/mach-pxa/e400.c
@@ -130,6 +130,9 @@ static struct platform_device *devices[] __initdata = {
 static void __init e400_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(e400_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        /* Fixme - e400 may have a switched clock */
        eseries_register_clks();
        eseries_get_tmio_gpios();
diff --git a/arch/arm/mach-pxa/e740.c b/arch/arm/mach-pxa/e740.c
index 49acdfa6650d..94b23a9e3877 100644
--- a/arch/arm/mach-pxa/e740.c
+++ b/arch/arm/mach-pxa/e740.c
@@ -192,6 +192,9 @@ static struct platform_device *devices[] __initdata = {
 static void __init e740_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(e740_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        eseries_register_clks();
        clk_add_alias("CLK_CK48M", e740_t7l66xb_device.name,
                        "UDCCLK", &pxa25x_device_udc.dev),
diff --git a/arch/arm/mach-pxa/e750.c b/arch/arm/mach-pxa/e750.c
index 4052ece3ef49..5eccbce73a33 100644
--- a/arch/arm/mach-pxa/e750.c
+++ b/arch/arm/mach-pxa/e750.c
@@ -194,6 +194,9 @@ static struct platform_device *devices[] __initdata = {
 static void __init e750_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(e750_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        clk_add_alias("CLK_CK3P6MI", e750_tc6393xb_device.name,
                        "GPIO11_CLK", NULL),
        eseries_get_tmio_gpios();
diff --git a/arch/arm/mach-pxa/e800.c b/arch/arm/mach-pxa/e800.c
index 9866c7b9e784..aad129bed199 100644
--- a/arch/arm/mach-pxa/e800.c
+++ b/arch/arm/mach-pxa/e800.c
@@ -195,6 +195,9 @@ static struct platform_device *devices[] __initdata = {
 static void __init e800_init(void)
 {
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        clk_add_alias("CLK_CK3P6MI", e800_tc6393xb_device.name,
                        "GPIO11_CLK", NULL),
        eseries_get_tmio_gpios();
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index aec7f4214b14..1c0de808b54d 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -967,7 +967,7 @@ static inline void em_x270_init_gpio_keys(void) {}
 #if defined(CONFIG_VIDEO_PXA27x) || defined(CONFIG_VIDEO_PXA27x_MODULE)
 static struct regulator *em_x270_camera_ldo;
-static int em_x270_sensor_init(struct device *dev)
+static int em_x270_sensor_init(void)
 {
        int ret;
@@ -996,7 +996,6 @@ static int em_x270_sensor_init(struct device *dev)
 }
 struct pxacamera_platform_data em_x270_camera_platform_data = {
-        .init   = em_x270_sensor_init,
        .flags  = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 |
                PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN,
        .mclk_10khz = 2600,
@@ -1049,8 +1048,10 @@ static struct platform_device em_x270_camera = {
 static void  __init em_x270_init_camera(void)
 {
-        pxa_set_camera_info(&em_x270_camera_platform_data);
+        if (em_x270_sensor_init() == 0) {
-        platform_device_register(&em_x270_camera);
+                pxa_set_camera_info(&em_x270_camera_platform_data);
+                platform_device_register(&em_x270_camera);
+        }
 }
 #else
 static inline void em_x270_init_camera(void) {}
@@ -1286,6 +1287,10 @@ static void __init em_x270_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(common_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
 #ifdef CONFIG_PM
        pxa27x_set_pwrmode(PWRMODE_DEEPSLEEP);
 #endif
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c
index 588b265e5755..626c82b13970 100644
--- a/arch/arm/mach-pxa/ezx.c
+++ b/arch/arm/mach-pxa/ezx.c
@@ -17,7 +17,11 @@
 #include <linux/delay.h>
 #include <linux/pwm_backlight.h>
 #include <linux/input.h>
+#include <linux/gpio.h>
 #include <linux/gpio_keys.h>
+#include <linux/leds-lp3944.h>
+#include <media/soc_camera.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -29,6 +33,7 @@
 #include <plat/i2c.h>
 #include <mach/hardware.h>
 #include <mach/pxa27x_keypad.h>
+#include <mach/camera.h>
 #include "devices.h"
 #include "generic.h"
@@ -38,6 +43,9 @@
 #define GPIO15_A910_FLIP_LID            15
 #define GPIO12_E680_LOCK_SWITCH         12
 #define GPIO15_E6_LOCK_SWITCH           15
+#define GPIO50_nCAM_EN                  50
+#define GPIO19_GEN1_CAM_RST             19
+#define GPIO28_GEN2_CAM_RST             28
 static struct platform_pwm_backlight_data ezx_backlight_data = {
        .pwm_id         = 0,
@@ -191,8 +199,8 @@ static unsigned long gen1_pin_config[] __initdata = {
        GPIO94_CIF_DD_5,
        GPIO17_CIF_DD_6,
        GPIO108_CIF_DD_7,
-        GPIO50_GPIO,                            /* CAM_EN */
+        GPIO50_GPIO | MFP_LPM_DRIVE_HIGH,       /* CAM_EN */
-        GPIO19_GPIO,                            /* CAM_RST */
+        GPIO19_GPIO | MFP_LPM_DRIVE_HIGH,       /* CAM_RST */
        /* EMU */
        GPIO120_GPIO,                           /* EMU_MUX1 */
@@ -248,8 +256,8 @@ static unsigned long gen2_pin_config[] __initdata = {
        GPIO48_CIF_DD_5,
        GPIO93_CIF_DD_6,
        GPIO12_CIF_DD_7,
-        GPIO50_GPIO,                            /* CAM_EN */
+        GPIO50_GPIO | MFP_LPM_DRIVE_HIGH,       /* CAM_EN */
-        GPIO28_GPIO,                            /* CAM_RST */
+        GPIO28_GPIO | MFP_LPM_DRIVE_HIGH,       /* CAM_RST */
        GPIO17_GPIO,                            /* CAM_FLASH */
 };
 #endif
@@ -683,6 +691,81 @@ static struct platform_device a780_gpio_keys = {
        },
 };
+/* camera */
+static int a780_camera_init(void)
+{
+        int err;
+        /*
+         * GPIO50_nCAM_EN is active low
+         * GPIO19_GEN1_CAM_RST is active on rising edge
+         */
+        err = gpio_request(GPIO50_nCAM_EN, "nCAM_EN");
+        if (err) {
+                pr_err("%s: Failed to request nCAM_EN\n", __func__);
+                goto fail;
+        }
+        err = gpio_request(GPIO19_GEN1_CAM_RST, "CAM_RST");
+        if (err) {
+                pr_err("%s: Failed to request CAM_RST\n", __func__);
+                goto fail_gpio_cam_rst;
+        }
+        gpio_direction_output(GPIO50_nCAM_EN, 1);
+        gpio_direction_output(GPIO19_GEN1_CAM_RST, 0);
+        return 0;
+fail_gpio_cam_rst:
+        gpio_free(GPIO50_nCAM_EN);
+fail:
+        return err;
+}
+static int a780_camera_power(struct device *dev, int on)
+{
+        gpio_set_value(GPIO50_nCAM_EN, !on);
+        return 0;
+}
+static int a780_camera_reset(struct device *dev)
+{
+        gpio_set_value(GPIO19_GEN1_CAM_RST, 0);
+        msleep(10);
+        gpio_set_value(GPIO19_GEN1_CAM_RST, 1);
+        return 0;
+}
+struct pxacamera_platform_data a780_pxacamera_platform_data = {
+        .flags  = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 |
+                PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN,
+        .mclk_10khz = 5000,
+};
+static struct i2c_board_info a780_camera_i2c_board_info = {
+        I2C_BOARD_INFO("mt9m111", 0x5d),
+};
+static struct soc_camera_link a780_iclink = {
+        .bus_id         = 0,
+        .flags          = SOCAM_SENSOR_INVERT_PCLK,
+        .i2c_adapter_id = 0,
+        .board_info     = &a780_camera_i2c_board_info,
+        .module_name    = "mt9m111",
+        .power          = a780_camera_power,
+        .reset          = a780_camera_reset,
+};
+static struct platform_device a780_camera = {
+        .name   = "soc-camera-pdrv",
+        .id     = 0,
+        .dev    = {
+                .platform_data = &a780_iclink,
+        },
+};
 static struct platform_device *a780_devices[] __initdata = {
        &a780_gpio_keys,
 };
@@ -693,12 +776,21 @@ static void __init a780_init(void)
        pxa2xx_mfp_config(ARRAY_AND_SIZE(gen1_pin_config));
        pxa2xx_mfp_config(ARRAY_AND_SIZE(a780_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        pxa_set_i2c_info(NULL);
        set_pxa_fb_info(&ezx_fb_info_1);
        pxa_set_keypad_info(&a780_keypad_platform_data);
+        if (a780_camera_init() == 0) {
+                pxa_set_camera_info(&a780_pxacamera_platform_data);
+                platform_device_register(&a780_camera);
+        }
        platform_add_devices(ARRAY_AND_SIZE(ezx_devices));
        platform_add_devices(ARRAY_AND_SIZE(a780_devices));
 }
@@ -754,6 +846,10 @@ static void __init e680_init(void)
        pxa2xx_mfp_config(ARRAY_AND_SIZE(gen1_pin_config));
        pxa2xx_mfp_config(ARRAY_AND_SIZE(e680_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        pxa_set_i2c_info(NULL);
        i2c_register_board_info(0, ARRAY_AND_SIZE(e680_i2c_board_info));
@@ -816,6 +912,10 @@ static void __init a1200_init(void)
        pxa2xx_mfp_config(ARRAY_AND_SIZE(gen2_pin_config));
        pxa2xx_mfp_config(ARRAY_AND_SIZE(a1200_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        pxa_set_i2c_info(NULL);
        i2c_register_board_info(0, ARRAY_AND_SIZE(a1200_i2c_board_info));
@@ -864,6 +964,131 @@ static struct platform_device a910_gpio_keys = {
        },
 };
+/* camera */
+static int a910_camera_init(void)
+{
+        int err;
+        /*
+         * GPIO50_nCAM_EN is active low
+         * GPIO28_GEN2_CAM_RST is active on rising edge
+         */
+        err = gpio_request(GPIO50_nCAM_EN, "nCAM_EN");
+        if (err) {
+                pr_err("%s: Failed to request nCAM_EN\n", __func__);
+                goto fail;
+        }
+        err = gpio_request(GPIO28_GEN2_CAM_RST, "CAM_RST");
+        if (err) {
+                pr_err("%s: Failed to request CAM_RST\n", __func__);
+                goto fail_gpio_cam_rst;
+        }
+        gpio_direction_output(GPIO50_nCAM_EN, 1);
+        gpio_direction_output(GPIO28_GEN2_CAM_RST, 0);
+        return 0;
+fail_gpio_cam_rst:
+        gpio_free(GPIO50_nCAM_EN);
+fail:
+        return err;
+}
+static int a910_camera_power(struct device *dev, int on)
+{
+        gpio_set_value(GPIO50_nCAM_EN, !on);
+        return 0;
+}
+static int a910_camera_reset(struct device *dev)
+{
+        gpio_set_value(GPIO28_GEN2_CAM_RST, 0);
+        msleep(10);
+        gpio_set_value(GPIO28_GEN2_CAM_RST, 1);
+        return 0;
+}
+struct pxacamera_platform_data a910_pxacamera_platform_data = {
+        .flags  = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 |
+                PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN,
+        .mclk_10khz = 5000,
+};
+static struct i2c_board_info a910_camera_i2c_board_info = {
+        I2C_BOARD_INFO("mt9m111", 0x5d),
+};
+static struct soc_camera_link a910_iclink = {
+        .bus_id         = 0,
+        .i2c_adapter_id = 0,
+        .board_info     = &a910_camera_i2c_board_info,
+        .module_name    = "mt9m111",
+        .power          = a910_camera_power,
+        .reset          = a910_camera_reset,
+};
+static struct platform_device a910_camera = {
+        .name   = "soc-camera-pdrv",
+        .id     = 0,
+        .dev    = {
+                .platform_data = &a910_iclink,
+        },
+};
+/* leds-lp3944 */
+static struct lp3944_platform_data a910_lp3944_leds = {
+        .leds_size = LP3944_LEDS_MAX,
+        .leds = {
+                [0] = {
+                        .name = "a910:red:",
+                        .status = LP3944_LED_STATUS_OFF,
+                        .type = LP3944_LED_TYPE_LED,
+                },
+                [1] = {
+                        .name = "a910:green:",
+                        .status = LP3944_LED_STATUS_OFF,
+                        .type = LP3944_LED_TYPE_LED,
+                },
+                [2] {
+                        .name = "a910:blue:",
+                        .status = LP3944_LED_STATUS_OFF,
+                        .type = LP3944_LED_TYPE_LED,
+                },
+                /* Leds 3 and 4 are used as display power switches */
+                [3] = {
+                        .name = "a910::cli_display",
+                        .status = LP3944_LED_STATUS_OFF,
+                        .type = LP3944_LED_TYPE_LED_INVERTED
+                },
+                [4] = {
+                        .name = "a910::main_display",
+                        .status = LP3944_LED_STATUS_ON,
+                        .type = LP3944_LED_TYPE_LED_INVERTED
+                },
+                [5] = { .type = LP3944_LED_TYPE_NONE },
+                [6] = {
+                        .name = "a910::torch",
+                        .status = LP3944_LED_STATUS_OFF,
+                        .type = LP3944_LED_TYPE_LED,
+                },
+                [7] = {
+                        .name = "a910::flash",
+                        .status = LP3944_LED_STATUS_OFF,
+                        .type = LP3944_LED_TYPE_LED_INVERTED,
+                },
+        },
+};
+static struct i2c_board_info __initdata a910_i2c_board_info[] = {
+        {
+                I2C_BOARD_INFO("lp3944", 0x60),
+                .platform_data = &a910_lp3944_leds,
+        },
+};
 static struct platform_device *a910_devices[] __initdata = {
        &a910_gpio_keys,
 };
@@ -874,12 +1099,22 @@ static void __init a910_init(void)
        pxa2xx_mfp_config(ARRAY_AND_SIZE(gen2_pin_config));
        pxa2xx_mfp_config(ARRAY_AND_SIZE(a910_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        pxa_set_i2c_info(NULL);
+        i2c_register_board_info(0, ARRAY_AND_SIZE(a910_i2c_board_info));
        set_pxa_fb_info(&ezx_fb_info_2);
        pxa_set_keypad_info(&a910_keypad_platform_data);
+        if (a910_camera_init() == 0) {
+                pxa_set_camera_info(&a910_pxacamera_platform_data);
+                platform_device_register(&a910_camera);
+        }
        platform_add_devices(ARRAY_AND_SIZE(ezx_devices));
        platform_add_devices(ARRAY_AND_SIZE(a910_devices));
 }
@@ -935,6 +1170,10 @@ static void __init e6_init(void)
        pxa2xx_mfp_config(ARRAY_AND_SIZE(gen2_pin_config));
        pxa2xx_mfp_config(ARRAY_AND_SIZE(e6_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        pxa_set_i2c_info(NULL);
        i2c_register_board_info(0, ARRAY_AND_SIZE(e6_i2c_board_info));
@@ -971,6 +1210,10 @@ static void __init e2_init(void)
        pxa2xx_mfp_config(ARRAY_AND_SIZE(gen2_pin_config));
        pxa2xx_mfp_config(ARRAY_AND_SIZE(e2_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        pxa_set_i2c_info(NULL);
        i2c_register_board_info(0, ARRAY_AND_SIZE(e2_i2c_board_info));
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index 485fede83d97..890fb90a672f 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -67,3 +67,8 @@ extern struct sysdev_class pxa_irq_sysclass;
 extern struct sysdev_class pxa_gpio_sysclass;
 extern struct sysdev_class pxa2xx_mfp_sysclass;
 extern struct sysdev_class pxa3xx_mfp_sysclass;
+void __init pxa_set_ffuart_info(void *info);
+void __init pxa_set_btuart_info(void *info);
+void __init pxa_set_stuart_info(void *info);
+void __init pxa_set_hwuart_info(void *info);
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c
index 1708c0109844..96c345129135 100644
--- a/arch/arm/mach-pxa/gumstix.c
+++ b/arch/arm/mach-pxa/gumstix.c
@@ -211,6 +211,11 @@ static void __init gumstix_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(gumstix_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
+        pxa_set_hwuart_info(NULL);
        gumstix_bluetooth_init();
        gumstix_udc_init();
        gumstix_mmc_init();
diff --git a/arch/arm/mach-pxa/h5000.c b/arch/arm/mach-pxa/h5000.c
index f3d220c32e07..c1cab0871c99 100644
--- a/arch/arm/mach-pxa/h5000.c
+++ b/arch/arm/mach-pxa/h5000.c
@@ -193,6 +193,9 @@ static void __init h5000_init(void)
        fix_msc();
        pxa2xx_mfp_config(ARRAY_AND_SIZE(h5000_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        pxa_set_udc_info(&h5000_udc_mach_info);
        platform_add_devices(ARRAY_AND_SIZE(devices));
 }
diff --git a/arch/arm/mach-pxa/himalaya.c b/arch/arm/mach-pxa/himalaya.c
index cea99fe65b97..f9a2e4b0f090 100644
--- a/arch/arm/mach-pxa/himalaya.c
+++ b/arch/arm/mach-pxa/himalaya.c
@@ -150,6 +150,9 @@ static void __init himalaya_lcd_init(void)
 static void __init himalaya_init(void)
 {
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        himalaya_lcd_init();
        platform_add_devices(devices, ARRAY_SIZE(devices));
 }
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index 83bd3c6e3884..848c861dd23f 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -820,6 +820,7 @@ static struct platform_device *devices[] __initdata = {
        &gpio_keys,
        &backlight,
        &w3220,
+        &hx4700_lcd,
        &egpio,
        &bq24022,
        &gpio_vbus,
@@ -849,6 +850,10 @@ static void __init hx4700_init(void)
        pxa2xx_mfp_config(ARRAY_AND_SIZE(hx4700_pin_config));
        hx4700_gpio_request(ARRAY_AND_SIZE(global_gpios));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        platform_add_devices(devices, ARRAY_SIZE(devices));
        pxa_set_ficp_info(&ficp_info);
diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c
index b6486ef20b17..5c9e11d74f49 100644
--- a/arch/arm/mach-pxa/idp.c
+++ b/arch/arm/mach-pxa/idp.c
@@ -179,6 +179,9 @@ static void __init idp_init(void)
        printk("idp_init()\n");
        pxa2xx_mfp_config(ARRAY_AND_SIZE(idp_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        platform_device_register(&smc91x_device);
        //platform_device_register(&mst_audio_device);
diff --git a/arch/arm/mach-pxa/imote2.c b/arch/arm/mach-pxa/imote2.c
index 2a4945db31c5..5b0862df61ab 100644
--- a/arch/arm/mach-pxa/imote2.c
+++ b/arch/arm/mach-pxa/imote2.c
@@ -554,8 +554,12 @@ static struct i2c_pxa_platform_data i2c_pdata = {
 static void __init imote2_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(imote2_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        /* SPI chip select directions - all other directions should
         * be handled by drivers.*/
        gpio_direction_output(37, 0);
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
index aa3d9f70a08a..50f1297bf5ac 100644
--- a/arch/arm/mach-pxa/include/mach/hardware.h
+++ b/arch/arm/mach-pxa/include/mach/hardware.h
@@ -105,6 +105,7 @@
 *
 *  PXA935      A0      0x56056931      0x1E653013
 *  PXA935      B0      0x56056936      0x6E653013
+ *  PXA935      B1      0x56056938      0x8E653013
 */
 #ifdef CONFIG_PXA25x
 #define __cpu_is_pxa210(id)                             \
@@ -283,7 +284,7 @@
                _id == 0x3;                             \
         })
-#define __cpu_is_pxa9xx(id)                             \
+#define __cpu_is_pxa93x(id)                             \
        ({                                              \
                unsigned int _id = (id) >> 4 & 0xfff;   \
                _id == 0x683 || _id == 0x693;           \
@@ -299,9 +300,9 @@
                __cpu_is_pxa3xx(read_cpuid_id());       \
         })
-#define cpu_is_pxa9xx()                                 \
+#define cpu_is_pxa93x()                                 \
        ({                                              \
-                __cpu_is_pxa9xx(read_cpuid_id());       \
+                __cpu_is_pxa93x(read_cpuid_id());       \
         })
 /*
 * return current memory and LCD clock frequency in units of 10kHz
diff --git a/arch/arm/mach-pxa/include/mach/palmtreo.h b/arch/arm/mach-pxa/include/mach/palmtreo.h
new file mode 100644
index 000000000000..2d3f14e3be29
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/palmtreo.h
@@ -0,0 +1,67 @@
+/*
+ * GPIOs and interrupts for Palm Treo smartphones
+ *
+ * currently supported:
+ *     Palm Treo 680 (GSM)
+ *     Palm Centro 685 (GSM)
+ *
+ * Author:     Tomas Cech <sleep_walker@suse.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * find more info at www.hackndev.com
+ *
+ */
+#ifndef _INCLUDE_TREO_H_
+#define _INCLUDE_TREO_H_
+/* GPIOs */
+#define GPIO_NR_TREO_POWER_DETECT       0
+#define GPIO_NR_TREO_AMP_EN             27
+#define GPIO_NR_TREO_GREEN_LED  20
+#define GPIO_NR_TREO_RED_LED            79
+#define GPIO_NR_TREO_SD_DETECT_N        113
+#define GPIO_NR_TREO_EP_DETECT_N        116
+#define GPIO_NR_TREO_USB_DETECT 1
+#define GPIO_NR_TREO_USB_PULLUP 114
+#define GPIO_NR_TREO_GSM_POWER  40
+#define GPIO_NR_TREO_GSM_RESET  87
+#define GPIO_NR_TREO_GSM_WAKE   57
+#define GPIO_NR_TREO_GSM_HOST_WAKE      14
+#define GPIO_NR_TREO_GSM_TRIGGER        10
+#define GPIO_NR_TREO_IR_EN              115
+#define GPIO_NR_TREO_IR_TXD             47
+#define GPIO_NR_TREO_BL_POWER   38
+#define GPIO_NR_TREO_LCD_POWER  25
+/* Treo680 specific GPIOs */
+#ifdef CONFIG_MACH_TREO680
+#define GPIO_NR_TREO680_SD_READONLY     33
+#define GPIO_NR_TREO680_SD_POWER        42
+#define GPIO_NR_TREO680_VIBRATE_EN      44
+#define GPIO_NR_TREO680_KEYB_BL         24
+#define GPIO_NR_TREO680_BT_EN           43
+#endif /* CONFIG_MACH_TREO680 */
+/* Centro685 specific GPIOs */
+#define GPIO_NR_CENTRO_SD_POWER         21
+#define GPIO_NR_CENTRO_VIBRATE_EN       22
+#define GPIO_NR_CENTRO_KEYB_BL          33
+#define GPIO_NR_CENTRO_BT_EN            80
+/* Various addresses  */
+#define TREO_PHYS_RAM_START     0xa0000000
+#define TREO_PHYS_IO_START      0x40000000
+#define TREO_STR_BASE   0xa2000000
+/* BACKLIGHT */
+#define TREO_MAX_INTENSITY              254
+#define TREO_DEFAULT_INTENSITY  160
+#define TREO_LIMIT_MASK         0x7F
+#define TREO_PRESCALER          63
+#define TREO_PERIOD_NS          3500
+#endif
diff --git a/arch/arm/mach-pxa/include/mach/pxafb.h b/arch/arm/mach-pxa/include/mach/pxafb.h
index f73061c90b5e..160ec83f51a6 100644
--- a/arch/arm/mach-pxa/include/mach/pxafb.h
+++ b/arch/arm/mach-pxa/include/mach/pxafb.h
@@ -76,7 +76,8 @@ struct pxafb_mode_info {
        u_char          bpp;
        u_int           cmap_greyscale:1,
                        depth:8,
-                        unused:23;
+                        transparency:1,
+                        unused:22;
        /* Parallel Mode Timing */
        u_char          hsync_len;
diff --git a/arch/arm/mach-pxa/include/mach/regs-u2d.h b/arch/arm/mach-pxa/include/mach/regs-u2d.h
new file mode 100644
index 000000000000..44b0b20b69a4
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/regs-u2d.h
@@ -0,0 +1,199 @@
+#ifndef __ASM_ARCH_PXA3xx_U2D_H
+#define __ASM_ARCH_PXA3xx_U2D_H
+#include <mach/bitfield.h>
+/*
+ * USB2 device controller registers and bits definitions
+ */
+#define U2DCR           (0x0000)        /* U2D Control Register */
+#define U2DCR_NDC       (1   << 31)     /* NAK During Config */
+#define U2DCR_HSTC      (0x7 << 28)     /* High Speed Timeout Calibration */
+#define U2DCR_SPEOREN   (1   << 27)     /* Short Packet EOR INTR generation Enable */
+#define U2DCR_FSTC      (0x7 << 24)     /* Full Speed Timeout Calibration */
+#define U2DCR_UCLKOVR   (1   << 22)     /* UTM Clock Override */
+#define U2DCR_ABP       (1   << 21)     /* Application Bus Power */
+#define U2DCR_ADD       (1   << 20)     /* Application Device Disconnect */
+#define U2DCR_CC        (1   << 19)     /* Configuration Change */
+#define U2DCR_HS        (1   << 18)     /* High Speed USB Detection */
+#define U2DCR_SMAC      (1   << 17)     /* Switch Endpoint Memory to Active Configuration */
+#define U2DCR_DWRE      (1   << 16)     /* Device Remote Wake-up Feature */
+#define U2DCR_ACN       (0xf << 12)     /* Active U2D Configuration Number */
+#define U2DCR_AIN       (0xf << 8)      /* Active U2D Interface Number */
+#define U2DCR_AAISN     (0xf << 4)      /* Active U2D Alternate Interface Setting Number */
+#define U2DCR_EMCE      (1   << 3)      /* Endpoint Memory Configuration Error */
+#define U2DCR_UDR       (1   << 2)      /* U2D Resume */
+#define U2DCR_UDA       (1   << 1)      /* U2D Active */
+#define U2DCR_UDE       (1   << 0)      /* U2D Enable */
+#define U2DICR                  (0x0004)        /* U2D Interrupt Control Register */
+#define U2DISR                  (0x000C)        /* U2D Interrupt Status Register */
+#define U2DINT_CC               (1 << 31)       /* Interrupt - Configuration Change */
+#define U2DINT_SOF              (1 << 30)       /* Interrupt - SOF */
+#define U2DINT_USOF             (1 << 29)       /* Interrupt - micro SOF */
+#define U2DINT_RU               (1 << 28)       /* Interrupt - Resume */
+#define U2DINT_SU               (1 << 27)       /* Interrupt - Suspend */
+#define U2DINT_RS               (1 << 26)       /* Interrupt - Reset */
+#define U2DINT_DPE              (1 << 25)       /* Interrupt - Data Packet Error */
+#define U2DINT_FIFOERR          (0x4)           /* Interrupt - endpoint FIFO error */
+#define U2DINT_PACKETCMP        (0x2)           /* Interrupt - endpoint packet complete */
+#define U2DINT_SPACKETCMP       (0x1)           /* Interrupt - endpoint short packet complete */
+#define U2DFNR                  (0x0014)        /* U2D Frame Number Register */
+#define U2DINT(n, intr)         (((intr) & 0x07) << (((n) & 0x07) * 3))
+#define U2DICR2                 (0x0008)        /* U2D Interrupt Control Register 2 */
+#define U2DISR2                 (0x0010)        /* U2D Interrupt Status Register 2 */
+#define U2DOTGCR                (0x0020)        /* U2D OTG Control Register */
+#define U2DOTGCR_OTGEN          (1 << 31)       /* On-The-Go Enable */
+#define U2DOTGCR_AALTHNP        (1 << 30)       /* A-device Alternate Host Negotiation Protocal Port Support */
+#define U2DOTGCR_AHNP           (1 << 29)       /* A-device Host Negotiation Protocal Support */
+#define U2DOTGCR_BHNP           (1 << 28)       /* B-device Host Negotiation Protocal Enable */
+#ifdef CONFIG_CPU_PXA930
+#define U2DOTGCR_LPA            (1 << 15)       /* ULPI low power mode active */
+#define U2DOTGCR_IESI           (1 << 13)       /* OTG interrupt Enable */
+#define U2DOTGCR_ISSI           (1 << 12)       /* OTG interrupt status */
+#endif
+#define U2DOTGCR_CKAF   (1 << 5)        /* Carkit Mode Alternate Function Select */
+#define U2DOTGCR_UTMID  (1 << 4)        /* UTMI Interface Disable */
+#define U2DOTGCR_ULAF   (1 << 3)        /* ULPI Mode Alternate Function Select */
+#define U2DOTGCR_SMAF   (1 << 2)        /* Serial Mode Alternate Function Select */
+#define U2DOTGCR_RTSM   (1 << 1)        /* Return to Synchronous Mode (ULPI Mode) */
+#define U2DOTGCR_ULE    (1 << 0)        /* ULPI Wrapper Enable */
+#define U2DOTGICR       (0x0024)        /* U2D OTG Interrupt Control Register */
+#define U2DOTGISR       (0x0028)        /* U2D OTG Interrupt Status Register */
+#define U2DOTGINT_SF    (1 << 17)       /* OTG Set Feature Command Received */
+#define U2DOTGINT_SI    (1 << 16)       /* OTG Interrupt */
+#define U2DOTGINT_RLS1  (1 << 14)       /* RXCMD Linestate[1] Change Interrupt Rise */
+#define U2DOTGINT_RLS0  (1 << 13)       /* RXCMD Linestate[0] Change Interrupt Rise */
+#define U2DOTGINT_RID   (1 << 12)       /* RXCMD OTG ID Change Interrupt Rise */
+#define U2DOTGINT_RSE   (1 << 11)       /* RXCMD OTG Session End Interrupt Rise */
+#define U2DOTGINT_RSV   (1 << 10)       /* RXCMD OTG Session Valid Interrupt Rise */
+#define U2DOTGINT_RVV   (1 << 9)        /* RXCMD OTG Vbus Valid Interrupt Rise */
+#define U2DOTGINT_RCK   (1 << 8)        /* RXCMD Carkit Interrupt Rise */
+#define U2DOTGINT_FLS1  (1 << 6)        /* RXCMD Linestate[1] Change Interrupt Fall */
+#define U2DOTGINT_FLS0  (1 << 5)        /* RXCMD Linestate[0] Change Interrupt Fall */
+#define U2DOTGINT_FID   (1 << 4)        /* RXCMD OTG ID Change Interrupt Fall */
+#define U2DOTGINT_FSE   (1 << 3)        /* RXCMD OTG Session End Interrupt Fall */
+#define U2DOTGINT_FSV   (1 << 2)        /* RXCMD OTG Session Valid Interrupt Fall */
+#define U2DOTGINT_FVV   (1 << 1)        /* RXCMD OTG Vbus Valid Interrupt Fall */
+#define U2DOTGINT_FCK   (1 << 0)        /* RXCMD Carkit Interrupt Fall */
+#define U2DOTGUSR       (0x002C)        /* U2D OTG ULPI Status Register */
+#define U2DOTGUSR_LPA   (1 << 31)       /* ULPI Low Power Mode Active */
+#define U2DOTGUSR_S6A   (1 << 30)       /* ULPI Serial Mode (6-pin) Active */
+#define U2DOTGUSR_S3A   (1 << 29)       /* ULPI Serial Mode (3-pin) Active */
+#define U2DOTGUSR_CKA   (1 << 28)       /* ULPI Car Kit Mode Active */
+#define U2DOTGUSR_LS1   (1 << 6)        /* RXCMD Linestate 1 Status */
+#define U2DOTGUSR_LS0   (1 << 5)        /* RXCMD Linestate 0 Status */
+#define U2DOTGUSR_ID    (1 << 4)        /* OTG IDGnd Status */
+#define U2DOTGUSR_SE    (1 << 3)        /* OTG Session End Status */
+#define U2DOTGUSR_SV    (1 << 2)        /* OTG Session Valid Status */
+#define U2DOTGUSR_VV    (1 << 1)        /* OTG Vbus Valid Status */
+#define U2DOTGUSR_CK    (1 << 0)        /* Carkit Interrupt Status */
+#define U2DOTGUCR       (0x0030)        /* U2D OTG ULPI Control Register */
+#define U2DOTGUCR_RUN   (1    << 25)    /* RUN */
+#define U2DOTGUCR_RNW   (1    << 24)    /* Read or Write operation */
+#define U2DOTGUCR_ADDR  (0x3f << 16)    /* Address of the ULPI PHY register */
+#define U2DOTGUCR_WDATA (0xff << 8)     /* The data for a WRITE command */
+#define U2DOTGUCR_RDATA (0xff << 0)     /* The data for a READ command */
+#define U2DP3CR         (0x0034)        /* U2D Port 3 Control Register */
+#define U2DP3CR_P2SS    (0x3 << 8)      /* Host Port 2 Serial Mode Select */
+#define U2DP3CR_P3SS    (0x7 << 4)      /* Host Port 3 Serial Mode Select */
+#define U2DP3CR_VPVMBEN (0x1 << 2)      /* Host Port 3 Vp/Vm Block Enable */
+#define U2DP3CR_CFG     (0x3 << 0)      /* Host Port 3 Configuration */
+#define U2DCSR0         (0x0100)        /* U2D Control/Status Register - Endpoint 0 */
+#define U2DCSR0_IPA     (1 << 8)        /* IN Packet Adjusted */
+#define U2DCSR0_SA      (1 << 7)        /* SETUP Active */
+#define U2DCSR0_RNE     (1 << 6)        /* Receive FIFO Not Empty */
+#define U2DCSR0_FST     (1 << 5)        /* Force Stall */
+#define U2DCSR0_SST     (1 << 4)        /* Send Stall */
+#define U2DCSR0_DME     (1 << 3)        /* DMA Enable */
+#define U2DCSR0_FTF     (1 << 2)        /* Flush Transmit FIFO */
+#define U2DCSR0_IPR     (1 << 1)        /* IN Packet Ready */
+#define U2DCSR0_OPC     (1 << 0)        /* OUT Packet Complete */
+#define U2DCSR(x)       (0x0100 + ((x) << 2))   /* U2D Control/Status Register - Endpoint x */
+#define U2DCSR_BF       (1 << 10)       /* Buffer Full, for OUT eps */
+#define U2DCSR_BE       (1 << 10)       /* Buffer Empty, for IN eps */
+#define U2DCSR_DPE      (1 << 9)        /* Data Packet Error, for ISO eps only */
+#define U2DCSR_FEF      (1 << 8)        /* Flush Endpoint FIFO */
+#define U2DCSR_SP       (1 << 7)        /* Short Packet Control/Status, for OUT eps only, readonly */
+#define U2DCSR_BNE      (1 << 6)        /* Buffer Not Empty, for OUT eps */
+#define U2DCSR_BNF      (1 << 6)        /* Buffer Not Full, for IN eps */
+#define U2DCSR_FST      (1 << 5)        /* Force STALL, write 1 set */
+#define U2DCSR_SST      (1 << 4)        /* Sent STALL, write 1 clear */
+#define U2DCSR_DME      (1 << 3)        /* DMA Enable */
+#define U2DCSR_TRN      (1 << 2)        /* Tx/Rx NAK, write 1 clear */
+#define U2DCSR_PC       (1 << 1)        /* Packet Complete, write 1 clear */
+#define U2DCSR_FS       (1 << 0)        /* FIFO needs Service */
+#define U2DBCR0         (0x0200)                /* U2D Byte Count Register - Endpoint 0 */
+#define U2DBCR(x)       (0x0200 + ((x) << 2))   /* U2D Byte Count Register - Endpoint x */
+#define U2DDR0          (0x0300)                /* U2D Data Register - Endpoint 0 */
+#define U2DEPCR(x)      (0x0400 + ((x) << 2))   /* U2D Configuration Register - Endpoint x */
+#define U2DEPCR_EE      (1 << 0)                /* Endpoint Enable */
+#define U2DEPCR_BS_MASK (0x3FE)                 /* Buffer Size, BS*8=FIFO size, max 8184B = 8KB */
+#define U2DSCA          (0x0500)                /* U2D Setup Command Address */
+#define U2DSCA_VALUE    (0x0120)
+#define U2DEN0          (0x0504)                /* U2D Endpoint Information Register - Endpoint 0 */
+#define U2DEN(x)        (0x0504 + ((x) << 2))   /* U2D Endpoint Information Register - Endpoint x */
+/* U2DMA registers */
+#define U2DMACSR0               (0x1000)        /* U2DMA Control/Status Register - Channel 0 */
+#define U2DMACSR(x)             (0x1000 + ((x) << 2))   /* U2DMA Control/Status Register - Channel x */
+#define U2DMACSR_RUN            (1 << 31)       /* Run Bit (read / write) */
+#define U2DMACSR_STOPIRQEN      (1 << 29)       /* Stop Interrupt Enable (read / write) */
+#define U2DMACSR_EORIRQEN       (1 << 28)       /* End of Receive Interrupt Enable (R/W) */
+#define U2DMACSR_EORJMPEN       (1 << 27)       /* Jump to next descriptor on EOR */
+#define U2DMACSR_EORSTOPEN      (1 << 26)       /* STOP on an EOR */
+#define U2DMACSR_RASIRQEN       (1 << 23)       /* Request After Cnannel Stopped Interrupt Enable */
+#define U2DMACSR_MASKRUN        (1 << 22)       /* Mask Run */
+#define U2DMACSR_SCEMC          (3 << 18)       /* System Bus Split Completion Error Message Class */
+#define U2DMACSR_SCEMI          (0x1f << 13)    /* System Bus Split Completion Error Message Index */
+#define U2DMACSR_BUSERRTYPE     (7 << 10)       /* PX Bus Error Type */
+#define U2DMACSR_EORINTR        (1 << 9)        /* End Of Receive */
+#define U2DMACSR_REQPEND        (1 << 8)        /* Request Pending */
+#define U2DMACSR_RASINTR        (1 << 4)        /* Request After Channel Stopped (read / write 1 clear) */#define U2DMACSR_STOPINTR     (1 << 3)        /* Stop Interrupt (read only) */
+#define U2DMACSR_ENDINTR        (1 << 2)        /* End Interrupt (read / write 1 clear) */
+#define U2DMACSR_STARTINTR      (1 << 1)        /* Start Interrupt (read / write 1 clear) */
+#define U2DMACSR_BUSERRINTR     (1 << 0)        /* Bus Error Interrupt (read / write 1 clear) */
+#define U2DMACR         (0x1080)                /* U2DMA Control Register */
+#define U2DMAINT        (0x10F0)                /* U2DMA Interrupt Register */
+#define U2DMABR0        (0x1100)                /* U2DMA Branch Register - Channel 0 */
+#define U2DMABR(x)      (0x1100 + (x) << 2)     /* U2DMA Branch Register - Channel x */
+#define U2DMADADR0      (0x1200)                /* U2DMA Descriptor Address Register - Channel 0 */
+#define U2DMADADR(x)    (0x1200 + (x) * 0x10)   /* U2DMA Descriptor Address Register - Channel x */
+#define U2DMADADR_STOP  (1U << 0)
+#define U2DMASADR0      (0x1204)                /* U2DMA Source Address Register - Channel 0 */
+#define U2DMASADR(x)    (0x1204 + (x) * 0x10)   /* U2DMA Source Address Register - Channel x */
+#define U2DMATADR0      (0x1208)                /* U2DMA Target Address Register - Channel 0 */
+#define U2DMATADR(x)    (0x1208 + (x) * 0x10)   /* U2DMA Target Address Register - Channel x */
+#define U2DMACMDR0      (0x120C)                /* U2DMA Command Address Register - Channel 0 */
+#define U2DMACMDR(x)    (0x120C + (x) * 0x10)   /* U2DMA Command Address Register - Channel x */
+#define U2DMACMDR_XFRDIS        (1 << 31)       /* Transfer Direction */
+#define U2DMACMDR_STARTIRQEN    (1 << 22)       /* Start Interrupt Enable */
+#define U2DMACMDR_ENDIRQEN      (1 << 21)       /* End Interrupt Enable */
+#define U2DMACMDR_PACKCOMP      (1 << 13)       /* Packet Complete */
+#define U2DMACMDR_LEN           (0x07ff)        /* length mask (max = 2K - 1) */
+#endif /* __ASM_ARCH_PXA3xx_U2D_H */
diff --git a/arch/arm/mach-pxa/include/mach/treo680.h b/arch/arm/mach-pxa/include/mach/treo680.h
deleted file mode 100644
index af443b24d99a..000000000000
--- a/arch/arm/mach-pxa/include/mach/treo680.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * GPIOs and interrupts for Palm Treo 680 smartphone
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-#ifndef _INCLUDE_TREO680_H_
-#define _INCLUDE_TREO680_H_
-/* GPIOs */
-#define GPIO_NR_TREO680_POWER_DETECT    0
-#define GPIO_NR_TREO680_AMP_EN          27
-#define GPIO_NR_TREO680_KEYB_BL         24
-#define GPIO_NR_TREO680_VIBRATE_EN      44
-#define GPIO_NR_TREO680_GREEN_LED       20
-#define GPIO_NR_TREO680_RED_LED         79
-#define GPIO_NR_TREO680_SD_DETECT_N     113
-#define GPIO_NR_TREO680_SD_READONLY     33
-#define GPIO_NR_TREO680_EP_DETECT_N     116
-#define GPIO_NR_TREO680_SD_POWER        42
-#define GPIO_NR_TREO680_USB_DETECT      1
-#define GPIO_NR_TREO680_USB_PULLUP      114
-#define GPIO_NR_TREO680_GSM_POWER       40
-#define GPIO_NR_TREO680_GSM_RESET       87
-#define GPIO_NR_TREO680_GSM_WAKE        57
-#define GPIO_NR_TREO680_GSM_HOST_WAKE   14
-#define GPIO_NR_TREO680_GSM_TRIGGER     10
-#define GPIO_NR_TREO680_BT_EN           43
-#define GPIO_NR_TREO680_IR_EN           115
-#define GPIO_NR_TREO680_IR_TXD          47
-#define GPIO_NR_TREO680_BL_POWER        38
-#define GPIO_NR_TREO680_LCD_POWER       25
-/* Various addresses  */
-#define TREO680_PHYS_RAM_START  0xa0000000
-#define TREO680_PHYS_IO_START   0x40000000
-#define TREO680_STR_BASE        0xa2000000
-/* BACKLIGHT */
-#define TREO680_MAX_INTENSITY           254
-#define TREO680_DEFAULT_INTENSITY       160
-#define TREO680_LIMIT_MASK              0x7F
-#define TREO680_PRESCALER               63
-#define TREO680_PERIOD_NS               3500
-#endif
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index 13848955d133..f28c1715b910 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -44,10 +44,10 @@
 #include <mach/ssp.h>
 #include <mach/mmc.h>
 #include <mach/pxa2xx_spi.h>
-#include <plat/i2c.h>
 #include <mach/pxa27x_keypad.h>
-#include <mach/pxa3xx_nand.h>
 #include <mach/littleton.h>
+#include <plat/i2c.h>
+#include <plat/pxa3xx_nand.h>
 #include "generic.h"
@@ -413,6 +413,10 @@ static void __init littleton_init(void)
        /* initialize MFP configurations */
        pxa3xx_mfp_config(ARRAY_AND_SIZE(littleton_mfp_cfg));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        /*
         * Note: we depend bootloader set the correct
         * value to MSC register for SMC91x.
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index d64395f26a3e..1373c22dbb83 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -455,6 +455,10 @@ static void __init lpd270_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(lpd270_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        lpd270_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
        lpd270_flash_data[1].width = 4;
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index c6a94d3fdd61..98ee7e590299 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -518,6 +518,10 @@ static void __init lubbock_init(void)
        pxa2xx_mfp_config(ARRAY_AND_SIZE(lubbock_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        clk_add_alias("SA1111_CLK", NULL, "GPIO11_CLK", NULL);
        pxa_set_udc_info(&udc_info);
        set_pxa_fb_info(&sharp_lm8v31);
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index 5360c07f5138..8a38d604dc77 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -742,6 +742,10 @@ static void __init magician_init(void)
        pxa2xx_mfp_config(ARRAY_AND_SIZE(magician_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        platform_add_devices(ARRAY_AND_SIZE(devices));
        err = gpio_request(GPIO83_MAGICIAN_nIR_EN, "nIR_EN");
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index a4eeae345e64..851ee0fc32e2 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -576,6 +576,10 @@ static void __init mainstone_init(void)
        pxa2xx_mfp_config(ARRAY_AND_SIZE(mainstone_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        mst_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
        mst_flash_data[1].width = 4;
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index 3cab452e5567..2466a44d8fda 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -798,6 +798,9 @@ static void __init mioa701_machine_init(void)
        UP2OCR = UP2OCR_HXOE;
        pxa2xx_mfp_config(ARRAY_AND_SIZE(mioa701_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        mio_gpio_request(ARRAY_AND_SIZE(global_gpios));
        bootstrap_init();
        set_pxa_fb_info(&mioa701_pxafb_info);
diff --git a/arch/arm/mach-pxa/mp900.c b/arch/arm/mach-pxa/mp900.c
index a65713ce019e..6d4503927a76 100644
--- a/arch/arm/mach-pxa/mp900.c
+++ b/arch/arm/mach-pxa/mp900.c
@@ -84,6 +84,9 @@ static struct platform_device *devices[] __initdata = {
 static void __init mp900c_init(void)
 {
        printk(KERN_INFO "MobilePro 900/C machine init\n");
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        platform_add_devices(devices, ARRAY_SIZE(devices));
 }
diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c
index 1ad029dd4438..59140217890a 100644
--- a/arch/arm/mach-pxa/palmld.c
+++ b/arch/arm/mach-pxa/palmld.c
@@ -530,6 +530,10 @@ static void __init palmld_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(palmld_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        palmld_pm_init();
        set_pxa_fb_info(&palmld_lcd_screen);
        pxa_set_mci_info(&palmld_mci_platform_data);
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c
index 2dd7ce28556b..7f89ca20f13a 100644
--- a/arch/arm/mach-pxa/palmt5.c
+++ b/arch/arm/mach-pxa/palmt5.c
@@ -419,6 +419,10 @@ static void __init palmt5_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(palmt5_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        palmt5_pm_init();
        set_pxa_fb_info(&palmt5_lcd_screen);
        pxa_set_mci_info(&palmt5_mci_platform_data);
diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c
index 0b92291a58f6..308417592007 100644
--- a/arch/arm/mach-pxa/palmtc.c
+++ b/arch/arm/mach-pxa/palmtc.c
@@ -416,6 +416,11 @@ static void __init palmtc_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(palmtc_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
+        pxa_set_hwuart_info(NULL);
        set_pxa_fb_info(&palmtc_lcd_screen);
        pxa_set_mci_info(&palmtc_mci_platform_data);
        pxa_set_udc_info(&palmtc_udc_info);
diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c
index 277c4062e3c6..265d62bae7de 100644
--- a/arch/arm/mach-pxa/palmte2.c
+++ b/arch/arm/mach-pxa/palmte2.c
@@ -373,6 +373,10 @@ static void __init palmte2_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(palmte2_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        set_pxa_fb_info(&palmte2_lcd_screen);
        pxa_set_mci_info(&palmte2_mci_platform_data);
        palmte2_udc_init();
diff --git a/arch/arm/mach-pxa/treo680.c b/arch/arm/mach-pxa/palmtreo.c
index fe085076fbf2..606eb7e8a17e 100644
--- a/arch/arm/mach-pxa/treo680.c
+++ b/arch/arm/mach-pxa/palmtreo.c
@@ -1,5 +1,9 @@
 /*
- * Hardware definitions for Palm Treo 680
+ * Hardware definitions for Palm Treo smartphones
+ *
+ * currently supported:
+ *     Palm Treo 680 (GSM)
+ *     Palm Centro 685 (GSM)
 *
 * Author:     Tomas Cech <sleep_walker@suse.cz>
 *
@@ -31,7 +35,7 @@
 #include <mach/pxa27x.h>
 #include <mach/pxa27x-udc.h>
 #include <mach/audio.h>
-#include <mach/treo680.h>
+#include <mach/palmtreo.h>
 #include <mach/mmc.h>
 #include <mach/pxafb.h>
 #include <mach/irda.h>
@@ -50,7 +54,7 @@
 /******************************************************************************
 * Pin configuration
 ******************************************************************************/
-static unsigned long treo680_pin_config[] __initdata = {
+static unsigned long treo_pin_config[] __initdata = {
        /* MMC */
        GPIO32_MMC_CLK,
        GPIO92_MMC_DAT_0,
@@ -58,7 +62,6 @@ static unsigned long treo680_pin_config[] __initdata = {
        GPIO110_MMC_DAT_2,
        GPIO111_MMC_DAT_3,
        GPIO112_MMC_CMD,
-        GPIO33_GPIO,                            /* SD read only */
        GPIO113_GPIO,                           /* SD detect */
        /* AC97 */
@@ -80,12 +83,10 @@ static unsigned long treo680_pin_config[] __initdata = {
        GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,       /* usb detect */
        /* MATRIX KEYPAD */
-        GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
        GPIO101_KP_MKIN_1,
        GPIO102_KP_MKIN_2,
        GPIO97_KP_MKIN_3,
        GPIO98_KP_MKIN_4,
-        GPIO99_KP_MKIN_5,
        GPIO91_KP_MKIN_6,
        GPIO13_KP_MKIN_7,
        GPIO103_KP_MKOUT_0 | MFP_LPM_DRIVE_HIGH,
@@ -150,19 +151,57 @@ static unsigned long treo680_pin_config[] __initdata = {
        GPIO11_GPIO | WAKEUP_ON_EDGE_BOTH,      /* bluetooth host wake up */
 };
+#ifdef CONFIG_MACH_TREO680
+static unsigned long treo680_pin_config[] __initdata = {
+        GPIO33_GPIO,    /* SD read only */
+        /* MATRIX KEYPAD - different wake up source */
+        GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO99_KP_MKIN_5,
+};
+#endif /* CONFIG_MACH_TREO680 */
+#ifdef CONFIG_MACH_CENTRO
+static unsigned long centro685_pin_config[] __initdata = {
+        /* Bluetooth attached to BT UART*/
+        MFP_CFG_OUT(GPIO80, AF0, DRIVE_LOW),    /* power: LOW = off */
+        GPIO42_BTUART_RXD,
+        GPIO43_BTUART_TXD,
+        GPIO44_BTUART_CTS,
+        GPIO45_BTUART_RTS,
+        /* MATRIX KEYPAD - different wake up source */
+        GPIO100_KP_MKIN_0,
+        GPIO99_KP_MKIN_5 | WAKEUP_ON_LEVEL_HIGH,
+};
+#endif /* CONFIG_MACH_CENTRO */
 /******************************************************************************
 * SD/MMC card controller
 ******************************************************************************/
+#ifdef CONFIG_MACH_TREO680
 static struct pxamci_platform_data treo680_mci_platform_data = {
        .ocr_mask               = MMC_VDD_32_33 | MMC_VDD_33_34,
-        .gpio_card_detect       = GPIO_NR_TREO680_SD_DETECT_N,
+        .gpio_card_detect       = GPIO_NR_TREO_SD_DETECT_N,
        .gpio_card_ro           = GPIO_NR_TREO680_SD_READONLY,
        .gpio_power             = GPIO_NR_TREO680_SD_POWER,
 };
+#endif /* CONFIG_MACH_TREO680 */
+#ifdef CONFIG_MACH_CENTRO
+static struct pxamci_platform_data centro_mci_platform_data = {
+        .ocr_mask               = MMC_VDD_32_33 | MMC_VDD_33_34,
+        .gpio_card_detect       = GPIO_NR_TREO_SD_DETECT_N,
+        .gpio_card_ro           = -1,
+        .gpio_power             = GPIO_NR_CENTRO_SD_POWER,
+        .gpio_power_invert      = 1,
+};
+#endif /* CONFIG_MACH_CENTRO */
 /******************************************************************************
 * GPIO keyboard
 ******************************************************************************/
+#ifdef CONFIG_MACH_TREO680
 static unsigned int treo680_matrix_keys[] = {
        KEY(0, 0, KEY_F8),              /* Red/Off/Power */
        KEY(0, 1, KEY_LEFT),
@@ -232,92 +271,167 @@ static struct pxa27x_keypad_platform_data treo680_keypad_platform_data = {
        .debounce_interval      = 30,
 };
+#endif /* CONFIG_MACH_TREO680 */
+#ifdef CONFIG_MACH_CENTRO
+static unsigned int centro_matrix_keys[] = {
+        KEY(0, 0, KEY_F9),              /* Home */
+        KEY(0, 1, KEY_LEFT),
+        KEY(0, 2, KEY_LEFTCTRL),        /* Alternate */
+        KEY(0, 3, KEY_L),
+        KEY(0, 4, KEY_A),
+        KEY(0, 5, KEY_Q),
+        KEY(0, 6, KEY_P),
+        KEY(1, 0, KEY_RIGHTCTRL),       /* Menu */
+        KEY(1, 1, KEY_RIGHT),
+        KEY(1, 2, KEY_LEFTSHIFT),       /* Left shift */
+        KEY(1, 3, KEY_Z),
+        KEY(1, 4, KEY_S),
+        KEY(1, 5, KEY_W),
+        KEY(2, 0, KEY_F1),              /* Phone */
+        KEY(2, 1, KEY_UP),
+        KEY(2, 2, KEY_0),
+        KEY(2, 3, KEY_X),
+        KEY(2, 4, KEY_D),
+        KEY(2, 5, KEY_E),
+        KEY(3, 0, KEY_F10),             /* Calendar */
+        KEY(3, 1, KEY_DOWN),
+        KEY(3, 2, KEY_SPACE),
+        KEY(3, 3, KEY_C),
+        KEY(3, 4, KEY_F),
+        KEY(3, 5, KEY_R),
+        KEY(4, 0, KEY_F12),             /* Mail */
+        KEY(4, 1, KEY_KPENTER),
+        KEY(4, 2, KEY_RIGHTALT),        /* Alt */
+        KEY(4, 3, KEY_V),
+        KEY(4, 4, KEY_G),
+        KEY(4, 5, KEY_T),
+        KEY(5, 0, KEY_F8),              /* Red/Off/Power */
+        KEY(5, 1, KEY_PAGEUP),          /* Side up */
+        KEY(5, 2, KEY_DOT),
+        KEY(5, 3, KEY_B),
+        KEY(5, 4, KEY_H),
+        KEY(5, 5, KEY_Y),
+        KEY(6, 0, KEY_TAB),             /* Side Activate */
+        KEY(6, 1, KEY_PAGEDOWN),        /* Side down */
+        KEY(6, 2, KEY_ENTER),
+        KEY(6, 3, KEY_N),
+        KEY(6, 4, KEY_J),
+        KEY(6, 5, KEY_U),
+        KEY(7, 0, KEY_F6),              /* Green/Call */
+        KEY(7, 1, KEY_O),
+        KEY(7, 2, KEY_BACKSPACE),
+        KEY(7, 3, KEY_M),
+        KEY(7, 4, KEY_K),
+        KEY(7, 5, KEY_I),
+};
+static struct pxa27x_keypad_platform_data centro_keypad_platform_data = {
+        .matrix_key_rows        = 8,
+        .matrix_key_cols        = 7,
+        .matrix_key_map         = centro_matrix_keys,
+        .matrix_key_map_size    = ARRAY_SIZE(centro_matrix_keys),
+        .direct_key_map         = { KEY_CONNECT },
+        .direct_key_num         = 1,
+        .debounce_interval      = 30,
+};
+#endif /* CONFIG_MACH_CENTRO */
 /******************************************************************************
 * aSoC audio
 ******************************************************************************/
-static pxa2xx_audio_ops_t treo680_ac97_pdata = {
+static pxa2xx_audio_ops_t treo_ac97_pdata = {
        .reset_gpio     = 95,
 };
 /******************************************************************************
 * Backlight
 ******************************************************************************/
-static int treo680_backlight_init(struct device *dev)
+static int treo_backlight_init(struct device *dev)
 {
        int ret;
-        ret = gpio_request(GPIO_NR_TREO680_BL_POWER, "BL POWER");
+        ret = gpio_request(GPIO_NR_TREO_BL_POWER, "BL POWER");
        if (ret)
                goto err;
-        ret = gpio_direction_output(GPIO_NR_TREO680_BL_POWER, 0);
+        ret = gpio_direction_output(GPIO_NR_TREO_BL_POWER, 0);
        if (ret)
                goto err2;
        return 0;
 err2:
-        gpio_free(GPIO_NR_TREO680_BL_POWER);
+        gpio_free(GPIO_NR_TREO_BL_POWER);
 err:
        return ret;
 }
-static int treo680_backlight_notify(int brightness)
+static int treo_backlight_notify(int brightness)
 {
-        gpio_set_value(GPIO_NR_TREO680_BL_POWER, brightness);
+        gpio_set_value(GPIO_NR_TREO_BL_POWER, brightness);
-        return TREO680_MAX_INTENSITY - brightness;
+        return TREO_MAX_INTENSITY - brightness;
 };
-static void treo680_backlight_exit(struct device *dev)
+static void treo_backlight_exit(struct device *dev)
 {
-        gpio_free(GPIO_NR_TREO680_BL_POWER);
+        gpio_free(GPIO_NR_TREO_BL_POWER);
 }
-static struct platform_pwm_backlight_data treo680_backlight_data = {
+static struct platform_pwm_backlight_data treo_backlight_data = {
        .pwm_id         = 0,
-        .max_brightness = TREO680_MAX_INTENSITY,
+        .max_brightness = TREO_MAX_INTENSITY,
-        .dft_brightness = TREO680_DEFAULT_INTENSITY,
+        .dft_brightness = TREO_DEFAULT_INTENSITY,
-        .pwm_period_ns  = TREO680_PERIOD_NS,
+        .pwm_period_ns  = TREO_PERIOD_NS,
-        .init           = treo680_backlight_init,
+        .init           = treo_backlight_init,
-        .notify         = treo680_backlight_notify,
+        .notify         = treo_backlight_notify,
-        .exit           = treo680_backlight_exit,
+        .exit           = treo_backlight_exit,
 };
-static struct platform_device treo680_backlight = {
+static struct platform_device treo_backlight = {
        .name   = "pwm-backlight",
        .dev    = {
                .parent         = &pxa27x_device_pwm0.dev,
-                .platform_data  = &treo680_backlight_data,
+                .platform_data  = &treo_backlight_data,
        },
 };
 /******************************************************************************
 * IrDA
 ******************************************************************************/
-static struct pxaficp_platform_data treo680_ficp_info = {
+static struct pxaficp_platform_data treo_ficp_info = {
-        .gpio_pwdown            = GPIO_NR_TREO680_IR_EN,
+        .gpio_pwdown            = GPIO_NR_TREO_IR_EN,
        .transceiver_cap        = IR_SIRMODE | IR_OFF,
 };
 /******************************************************************************
 * UDC
 ******************************************************************************/
-static struct pxa2xx_udc_mach_info treo680_udc_info __initdata = {
+static struct pxa2xx_udc_mach_info treo_udc_info __initdata = {
-        .gpio_vbus              = GPIO_NR_TREO680_USB_DETECT,
+        .gpio_vbus              = GPIO_NR_TREO_USB_DETECT,
        .gpio_vbus_inverted     = 1,
-        .gpio_pullup            = GPIO_NR_TREO680_USB_PULLUP,
+        .gpio_pullup            = GPIO_NR_TREO_USB_PULLUP,
 };
 /******************************************************************************
 * USB host
 ******************************************************************************/
+#ifdef CONFIG_MACH_TREO680
 static struct pxaohci_platform_data treo680_ohci_info = {
        .port_mode    = PMM_PERPORT_MODE,
        .flags        = ENABLE_PORT1 | ENABLE_PORT3,
        .power_budget = 0,
 };
+#endif /* CONFIG_MACH_TREO680 */
 /******************************************************************************
 * Power supply
@@ -326,41 +440,41 @@ static int power_supply_init(struct device *dev)
 {
        int ret;
-        ret = gpio_request(GPIO_NR_TREO680_POWER_DETECT, "CABLE_STATE_AC");
+        ret = gpio_request(GPIO_NR_TREO_POWER_DETECT, "CABLE_STATE_AC");
        if (ret)
                goto err1;
-        ret = gpio_direction_input(GPIO_NR_TREO680_POWER_DETECT);
+        ret = gpio_direction_input(GPIO_NR_TREO_POWER_DETECT);
        if (ret)
                goto err2;
        return 0;
 err2:
-        gpio_free(GPIO_NR_TREO680_POWER_DETECT);
+        gpio_free(GPIO_NR_TREO_POWER_DETECT);
 err1:
        return ret;
 }
-static int treo680_is_ac_online(void)
+static int treo_is_ac_online(void)
 {
-        return gpio_get_value(GPIO_NR_TREO680_POWER_DETECT);
+        return gpio_get_value(GPIO_NR_TREO_POWER_DETECT);
 }
 static void power_supply_exit(struct device *dev)
 {
-        gpio_free(GPIO_NR_TREO680_POWER_DETECT);
+        gpio_free(GPIO_NR_TREO_POWER_DETECT);
 }
-static char *treo680_supplicants[] = {
+static char *treo_supplicants[] = {
        "main-battery",
 };
 static struct pda_power_pdata power_supply_info = {
        .init            = power_supply_init,
-        .is_ac_online    = treo680_is_ac_online,
+        .is_ac_online    = treo_is_ac_online,
        .exit            = power_supply_exit,
-        .supplied_to     = treo680_supplicants,
+        .supplied_to     = treo_supplicants,
-        .num_supplicants = ARRAY_SIZE(treo680_supplicants),
+        .num_supplicants = ARRAY_SIZE(treo_supplicants),
 };
 static struct platform_device power_supply = {
@@ -374,7 +488,8 @@ static struct platform_device power_supply = {
 /******************************************************************************
 * Vibra and LEDs
 ******************************************************************************/
-static struct gpio_led gpio_leds[] = {
+#ifdef CONFIG_MACH_TREO680
+static struct gpio_led treo680_gpio_leds[] = {
        {
                .name                   = "treo680:vibra:vibra",
                .default_trigger        = "none",
@@ -383,34 +498,68 @@ static struct gpio_led gpio_leds[] = {
        {
                .name                   = "treo680:green:led",
                .default_trigger        = "mmc0",
-                .gpio                   = GPIO_NR_TREO680_GREEN_LED,
+                .gpio                   = GPIO_NR_TREO_GREEN_LED,
        },
        {
-                .name                   = "treo680:keybbl:keybbl",
+                .name                   = "treo680:white:keybbl",
                .default_trigger        = "none",
                .gpio                   = GPIO_NR_TREO680_KEYB_BL,
        },
 };
-static struct gpio_led_platform_data gpio_led_info = {
+static struct gpio_led_platform_data treo680_gpio_led_info = {
-        .leds           = gpio_leds,
+        .leds           = treo680_gpio_leds,
-        .num_leds       = ARRAY_SIZE(gpio_leds),
+        .num_leds       = ARRAY_SIZE(treo680_gpio_leds),
 };
 static struct platform_device treo680_leds = {
        .name   = "leds-gpio",
        .id     = -1,
        .dev    = {
-                .platform_data  = &gpio_led_info,
+                .platform_data  = &treo680_gpio_led_info,
        }
 };
+#endif /* CONFIG_MACH_TREO680 */
+#ifdef CONFIG_MACH_CENTRO
+static struct gpio_led centro_gpio_leds[] = {
+        {
+                .name                   = "centro:vibra:vibra",
+                .default_trigger        = "none",
+                .gpio                   = GPIO_NR_CENTRO_VIBRATE_EN,
+        },
+        {
+                .name                   = "centro:green:led",
+                .default_trigger        = "mmc0",
+                .gpio                   = GPIO_NR_TREO_GREEN_LED,
+        },
+        {
+                .name                   = "centro:white:keybbl",
+                .default_trigger        = "none",
+                .active_low             = 1,
+                .gpio                   = GPIO_NR_CENTRO_KEYB_BL,
+        },
+};
+static struct gpio_led_platform_data centro_gpio_led_info = {
+        .leds           = centro_gpio_leds,
+        .num_leds       = ARRAY_SIZE(centro_gpio_leds),
+};
+static struct platform_device centro_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &centro_gpio_led_info,
+        }
+};
+#endif /* CONFIG_MACH_CENTRO */
 /******************************************************************************
 * Framebuffer
 ******************************************************************************/
 /* TODO: add support for 324x324 */
-static struct pxafb_mode_info treo680_lcd_modes[] = {
+static struct pxafb_mode_info treo_lcd_modes[] = {
 {
        .pixclock               = 86538,
        .xres                   = 320,
@@ -427,21 +576,21 @@ static struct pxafb_mode_info treo680_lcd_modes[] = {
 },
 };
-static void treo680_lcd_power(int on, struct fb_var_screeninfo *info)
+static void treo_lcd_power(int on, struct fb_var_screeninfo *info)
 {
-        gpio_set_value(GPIO_NR_TREO680_BL_POWER, on);
+        gpio_set_value(GPIO_NR_TREO_BL_POWER, on);
 }
-static struct pxafb_mach_info treo680_lcd_screen = {
+static struct pxafb_mach_info treo_lcd_screen = {
-        .modes          = treo680_lcd_modes,
+        .modes          = treo_lcd_modes,
-        .num_modes      = ARRAY_SIZE(treo680_lcd_modes),
+        .num_modes      = ARRAY_SIZE(treo_lcd_modes),
        .lcd_conn       = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
 };
 /******************************************************************************
 * Power management - standby
 ******************************************************************************/
-static void __init treo680_pm_init(void)
+static void __init treo_pm_init(void)
 {
        static u32 resume[] = {
                0xe3a00101,     /* mov  r0,     #0x40000000 */
@@ -450,70 +599,118 @@ static void __init treo680_pm_init(void)
        };
        /* this is where the bootloader jumps */
-        memcpy(phys_to_virt(TREO680_STR_BASE), resume, sizeof(resume));
+        memcpy(phys_to_virt(TREO_STR_BASE), resume, sizeof(resume));
 }
 /******************************************************************************
 * Machine init
 ******************************************************************************/
-static struct platform_device *devices[] __initdata = {
+static struct platform_device *treo_devices[] __initdata = {
-        &treo680_backlight,
+        &treo_backlight,
-        &treo680_leds,
        &power_supply,
 };
+#ifdef CONFIG_MACH_TREO680
+static struct platform_device *treo680_devices[] __initdata = {
+        &treo680_leds,
+};
+#endif /* CONFIG_MACH_TREO680 */
+#ifdef CONFIG_MACH_CENTRO
+static struct platform_device *centro_devices[] __initdata = {
+        &centro_leds,
+};
+#endif /* CONFIG_MACH_CENTRO */
 /* setup udc GPIOs initial state */
-static void __init treo680_udc_init(void)
+static void __init treo_udc_init(void)
 {
-        if (!gpio_request(GPIO_NR_TREO680_USB_PULLUP, "UDC Vbus")) {
+        if (!gpio_request(GPIO_NR_TREO_USB_PULLUP, "UDC Vbus")) {
-                gpio_direction_output(GPIO_NR_TREO680_USB_PULLUP, 1);
+                gpio_direction_output(GPIO_NR_TREO_USB_PULLUP, 1);
-                gpio_free(GPIO_NR_TREO680_USB_PULLUP);
+                gpio_free(GPIO_NR_TREO_USB_PULLUP);
        }
 }
-static void __init treo680_lcd_power_init(void)
+static void __init treo_lcd_power_init(void)
 {
        int ret;
-        ret = gpio_request(GPIO_NR_TREO680_LCD_POWER, "LCD POWER");
+        ret = gpio_request(GPIO_NR_TREO_LCD_POWER, "LCD POWER");
        if (ret) {
                pr_err("Treo680: LCD power GPIO request failed!\n");
                return;
        }
-        ret = gpio_direction_output(GPIO_NR_TREO680_LCD_POWER, 0);
+        ret = gpio_direction_output(GPIO_NR_TREO_LCD_POWER, 0);
        if (ret) {
                pr_err("Treo680: setting LCD power GPIO direction failed!\n");
-                gpio_free(GPIO_NR_TREO680_LCD_POWER);
+                gpio_free(GPIO_NR_TREO_LCD_POWER);
                return;
        }
-        treo680_lcd_screen.pxafb_lcd_power = treo680_lcd_power;
+        treo_lcd_screen.pxafb_lcd_power = treo_lcd_power;
 }
+static void __init treo_init(void)
+{
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
+        treo_pm_init();
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(treo_pin_config));
+        treo_lcd_power_init();
+        set_pxa_fb_info(&treo_lcd_screen);
+        treo_udc_init();
+        pxa_set_udc_info(&treo_udc_info);
+        pxa_set_ac97_info(&treo_ac97_pdata);
+        pxa_set_ficp_info(&treo_ficp_info);
+        platform_add_devices(ARRAY_AND_SIZE(treo_devices));
+}
+#ifdef CONFIG_MACH_TREO680
 static void __init treo680_init(void)
 {
-        treo680_pm_init();
+        treo_init();
        pxa2xx_mfp_config(ARRAY_AND_SIZE(treo680_pin_config));
-        pxa_set_keypad_info(&treo680_keypad_platform_data);
-        treo680_lcd_power_init();
-        set_pxa_fb_info(&treo680_lcd_screen);
        pxa_set_mci_info(&treo680_mci_platform_data);
-        treo680_udc_init();
+        pxa_set_keypad_info(&treo680_keypad_platform_data);
-        pxa_set_udc_info(&treo680_udc_info);
-        pxa_set_ac97_info(&treo680_ac97_pdata);
-        pxa_set_ficp_info(&treo680_ficp_info);
        pxa_set_ohci_info(&treo680_ohci_info);
-        platform_add_devices(devices, ARRAY_SIZE(devices));
+        platform_add_devices(ARRAY_AND_SIZE(treo680_devices));
 }
 MACHINE_START(TREO680, "Palm Treo 680")
-        .phys_io        = TREO680_PHYS_IO_START,
+        .phys_io        = TREO_PHYS_IO_START,
-        .io_pg_offst    = io_p2v(0x40000000),
+        .io_pg_offst    = io_p2v(0x40000000),
-        .boot_params    = 0xa0000100,
+        .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa_map_io,
-        .init_irq       = pxa27x_init_irq,
+        .init_irq       = pxa27x_init_irq,
-        .timer          = &pxa_timer,
+        .timer          = &pxa_timer,
-        .init_machine   = treo680_init,
+        .init_machine   = treo680_init,
+MACHINE_END
+#endif /* CONFIG_MACH_TREO680 */
+#ifdef CONFIG_MACH_CENTRO
+static void __init centro_init(void)
+{
+        treo_init();
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(centro685_pin_config));
+        pxa_set_mci_info(&centro_mci_platform_data);
+        pxa_set_keypad_info(&centro_keypad_platform_data);
+        platform_add_devices(ARRAY_AND_SIZE(centro_devices));
+}
+MACHINE_START(CENTRO, "Palm Centro 685")
+        .phys_io        = TREO_PHYS_IO_START,
+        .io_pg_offst    = io_p2v(0x40000000),
+        .boot_params    = 0xa0000100,
+        .map_io         = pxa_map_io,
+        .init_irq       = pxa27x_init_irq,
+        .timer          = &pxa_timer,
+       .init_machine   = centro_init,
 MACHINE_END
+#endif /* CONFIG_MACH_CENTRO */
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
index 76a2b37eaf30..7bf18c2f002f 100644
--- a/arch/arm/mach-pxa/palmtx.c
+++ b/arch/arm/mach-pxa/palmtx.c
@@ -570,6 +570,10 @@ static void __init palmtx_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(palmtx_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        palmtx_pm_init();
        set_pxa_fb_info(&palmtx_lcd_screen);
        pxa_set_mci_info(&palmtx_mci_platform_data);
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
index c2bf493c5f53..d787ac7cfdd8 100644
--- a/arch/arm/mach-pxa/palmz72.c
+++ b/arch/arm/mach-pxa/palmz72.c
@@ -491,6 +491,10 @@ static void __init palmz72_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(palmz72_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        set_pxa_fb_info(&palmz72_lcd_screen);
        pxa_set_mci_info(&palmz72_mci_platform_data);
        palmz72_udc_init();
diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c
index 6abfa2979c61..2190af066470 100644
--- a/arch/arm/mach-pxa/pcm027.c
+++ b/arch/arm/mach-pxa/pcm027.c
@@ -227,6 +227,10 @@ static void __init pcm027_init(void)
        pxa2xx_mfp_config(pcm027_pin_config, ARRAY_SIZE(pcm027_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        platform_add_devices(devices, ARRAY_SIZE(devices));
        /* at last call the baseboard to initialize itself */
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index bbda57078e0f..d5255ae74fe3 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -359,19 +359,12 @@ static unsigned long pcm990_camera_pin_config[] = {
        GPIO44_CIF_LV,
 };
-static int pcm990_pxacamera_init(struct device *dev)
-{
-        pxa2xx_mfp_config(ARRAY_AND_SIZE(pcm990_camera_pin_config));
-        return 0;
-}
 /*
 * CICR4: PCLK_EN:      Pixel clock is supplied by the sensor
 *      MCLK_EN:        Master clock is generated by PXA
 *      PCP:            Data sampled on the falling edge of pixel clock
 */
 struct pxacamera_platform_data pcm990_pxacamera_platform_data = {
-        .init   = pcm990_pxacamera_init,
        .flags  = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 | PXA_CAMERA_DATAWIDTH_10 |
                PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN/* | PXA_CAMERA_PCP*/,
        .mclk_10khz = 1000,
@@ -532,6 +525,7 @@ void __init pcm990_baseboard_init(void)
        pxa_set_ac97_info(NULL);
 #if defined(CONFIG_VIDEO_PXA27x) || defined(CONFIG_VIDEO_PXA27x_MODULE)
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(pcm990_camera_pin_config));
        pxa_set_camera_info(&pcm990_pxacamera_platform_data);
        i2c_register_board_info(0, ARRAY_AND_SIZE(pcm990_i2c_devices));
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index a186994f77fb..e5eeb3a62d01 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -449,6 +449,10 @@ static void __init poodle_init(void)
        pxa2xx_mfp_config(ARRAY_AND_SIZE(poodle_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        platform_scoop_config = &poodle_pcmcia_config;
        ret = platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 77c2693cfeef..2c1b0b70d01d 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -322,9 +322,6 @@ void __init pxa26x_init_irq(void)
 static struct platform_device *pxa25x_devices[] __initdata = {
        &pxa25x_device_udc,
-        &pxa_device_ffuart,
-        &pxa_device_btuart,
-        &pxa_device_stuart,
        &pxa_device_i2s,
        &sa1100_device_rtc,
        &pxa25x_device_ssp,
@@ -372,10 +369,8 @@ static int __init pxa25x_init(void)
        }
        /* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */
-        if (cpu_is_pxa255()) {
+        if (cpu_is_pxa255())
                clks_register(&pxa25x_hwuart_clkreg, 1);
-                ret = platform_device_register(&pxa_device_hwuart);
-        }
        return ret;
 }
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index ec68cc16b4e3..6a0b73167e03 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -364,9 +364,6 @@ void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
 static struct platform_device *devices[] __initdata = {
        &pxa27x_device_udc,
-        &pxa_device_ffuart,
-        &pxa_device_btuart,
-        &pxa_device_stuart,
        &pxa_device_i2s,
        &sa1100_device_rtc,
        &pxa_device_rtc,
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 09b7b1a10cad..fcb0721f4669 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -30,6 +30,7 @@
 #include <mach/pm.h>
 #include <mach/dma.h>
 #include <mach/ssp.h>
+#include <mach/regs-intc.h>
 #include <plat/i2c.h>
 #include "generic.h"
@@ -45,6 +46,9 @@
 #define ACCR_D0CS       (1 << 26)
 #define ACCR_PCCE       (1 << 11)
+#define PECR_IE(n)      ((1 << ((n) * 2)) << 28)
+#define PECR_IS(n)      ((1 << ((n) * 2)) << 29)
 /* crystal frequency to static memory controller multiplier (SMCFS) */
 static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
@@ -237,6 +241,7 @@ static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
 static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
 static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
 static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
+static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
 static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
 static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
 static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
@@ -261,6 +266,7 @@ static struct clk_lookup pxa3xx_clkregs[] = {
        INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
        INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
        INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
+        INIT_CLKREG(&clk_pxa3xx_u2d, NULL, "U2DCLK"),
        INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
        INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
        INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
@@ -530,6 +536,43 @@ static inline void pxa3xx_init_pm(void) {}
 #define pxa3xx_set_wake NULL
 #endif
+static void pxa_ack_ext_wakeup(unsigned int irq)
+{
+        PECR |= PECR_IS(irq - IRQ_WAKEUP0);
+}
+static void pxa_mask_ext_wakeup(unsigned int irq)
+{
+        ICMR2 &= ~(1 << ((irq - PXA_IRQ(0)) & 0x1f));
+        PECR &= ~PECR_IE(irq - IRQ_WAKEUP0);
+}
+static void pxa_unmask_ext_wakeup(unsigned int irq)
+{
+        ICMR2 |= 1 << ((irq - PXA_IRQ(0)) & 0x1f);
+        PECR |= PECR_IE(irq - IRQ_WAKEUP0);
+}
+static struct irq_chip pxa_ext_wakeup_chip = {
+        .name           = "WAKEUP",
+        .ack            = pxa_ack_ext_wakeup,
+        .mask           = pxa_mask_ext_wakeup,
+        .unmask         = pxa_unmask_ext_wakeup,
+};
+static void __init pxa_init_ext_wakeup_irq(set_wake_t fn)
+{
+        int irq;
+        for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
+                set_irq_chip(irq, &pxa_ext_wakeup_chip);
+                set_irq_handler(irq, handle_edge_irq);
+                set_irq_flags(irq, IRQF_VALID);
+        }
+        pxa_ext_wakeup_chip.set_wake = fn;
+}
 void __init pxa3xx_init_irq(void)
 {
        /* enable CP6 access */
@@ -539,6 +582,7 @@ void __init pxa3xx_init_irq(void)
        __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
        pxa_init_irq(56, pxa3xx_set_wake);
+        pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
        pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL);
 }
@@ -553,9 +597,6 @@ void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
 static struct platform_device *devices[] __initdata = {
        &pxa27x_device_udc,
-        &pxa_device_ffuart,
-        &pxa_device_btuart,
-        &pxa_device_stuart,
        &pxa_device_i2s,
        &sa1100_device_rtc,
        &pxa_device_rtc,
diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c
index 8241a63ea589..115b6f234bdd 100644
--- a/arch/arm/mach-pxa/saar.c
+++ b/arch/arm/mach-pxa/saar.c
@@ -22,9 +22,13 @@
 #include <linux/i2c.h>
 #include <linux/smc91x.h>
 #include <linux/mfd/da903x.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/onenand.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
 #include <mach/pxa930.h>
 #include <plat/i2c.h>
@@ -33,7 +37,7 @@
 #include "devices.h"
 #include "generic.h"
-#define GPIO_LCD_RESET  (16)
+#define GPIO_LCD_RESET          (16)
 /* SAAR MFP configurations */
 static mfp_cfg_t saar_mfp_cfg[] __initdata = {
@@ -56,6 +60,31 @@ static mfp_cfg_t saar_mfp_cfg[] __initdata = {
        /* Ethernet */
        DF_nCS1_nCS3,
        GPIO97_GPIO,
+        /* DFI */
+        DF_INT_RnB_ND_INT_RnB,
+        DF_nRE_nOE_ND_nRE,
+        DF_nWE_ND_nWE,
+        DF_CLE_nOE_ND_CLE,
+        DF_nADV1_ALE_ND_ALE,
+        DF_nADV2_ALE_nCS3,
+        DF_nCS0_ND_nCS0,
+        DF_IO0_ND_IO0,
+        DF_IO1_ND_IO1,
+        DF_IO2_ND_IO2,
+        DF_IO3_ND_IO3,
+        DF_IO4_ND_IO4,
+        DF_IO5_ND_IO5,
+        DF_IO6_ND_IO6,
+        DF_IO7_ND_IO7,
+        DF_IO8_ND_IO8,
+        DF_IO9_ND_IO9,
+        DF_IO10_ND_IO10,
+        DF_IO11_ND_IO11,
+        DF_IO12_ND_IO12,
+        DF_IO13_ND_IO13,
+        DF_IO14_ND_IO14,
+        DF_IO15_ND_IO15,
 };
 #define SAAR_ETH_PHYS   (0x14000000)
@@ -451,10 +480,15 @@ static inline void saar_init_lcd(void) {}
 #endif
 #if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE)
+static struct da9034_backlight_pdata saar_da9034_backlight = {
+        .output_current = 4,    /* 4mA */
+};
 static struct da903x_subdev_info saar_da9034_subdevs[] = {
        [0] = {
                .name           = "da903x-backlight",
                .id             = DA9034_ID_WLED,
+                .platform_data  = &saar_da9034_backlight,
        },
 };
@@ -480,12 +514,81 @@ static void __init saar_init_i2c(void)
 #else
 static inline void saar_init_i2c(void) {}
 #endif
+#if defined(CONFIG_MTD_ONENAND) || defined(CONFIG_MTD_ONENAND_MODULE)
+static struct mtd_partition saar_onenand_partitions[] = {
+        {
+                .name           = "bootloader",
+                .offset         = 0,
+                .size           = SZ_1M,
+                .mask_flags     = MTD_WRITEABLE,
+        }, {
+                .name           = "reserved",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = SZ_128K,
+                .mask_flags     = MTD_WRITEABLE,
+        }, {
+                .name           = "reserved",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = SZ_8M,
+                .mask_flags     = MTD_WRITEABLE,
+        }, {
+                .name           = "kernel",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = (SZ_2M + SZ_1M),
+                .mask_flags     = 0,
+        }, {
+                .name           = "filesystem",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = SZ_48M,
+                .mask_flags     = 0,
+        }
+};
+static struct onenand_platform_data saar_onenand_info = {
+        .parts          = saar_onenand_partitions,
+        .nr_parts       = ARRAY_SIZE(saar_onenand_partitions),
+};
+#define SMC_CS0_PHYS_BASE       (0x10000000)
+static struct resource saar_resource_onenand[] = {
+        [0] = {
+                .start  = SMC_CS0_PHYS_BASE,
+                .end    = SMC_CS0_PHYS_BASE + SZ_1M,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+static struct platform_device saar_device_onenand = {
+        .name           = "onenand-flash",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &saar_onenand_info,
+        },
+        .resource       = saar_resource_onenand,
+        .num_resources  = ARRAY_SIZE(saar_resource_onenand),
+};
+static void __init saar_init_onenand(void)
+{
+        platform_device_register(&saar_device_onenand);
+}
+#else
+static void __init saar_init_onenand(void) {}
+#endif
 static void __init saar_init(void)
 {
        /* initialize MFP configurations */
        pxa3xx_mfp_config(ARRAY_AND_SIZE(saar_mfp_cfg));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        platform_device_register(&smc91x_device);
+        saar_init_onenand();
        saar_init_i2c();
        saar_init_lcd();
diff --git a/arch/arm/mach-pxa/sharpsl.h b/arch/arm/mach-pxa/sharpsl.h
index 55259f4756c8..1439785d3979 100644
--- a/arch/arm/mach-pxa/sharpsl.h
+++ b/arch/arm/mach-pxa/sharpsl.h
@@ -42,8 +42,8 @@ void corgi_lcdtg_hw_init(int mode);
 #define MAX1111_BATT_TEMP   2u
 #define MAX1111_ACIN_VOLT   6u
-extern struct battery_thresh spitz_battery_levels_acin[];
+extern struct battery_thresh sharpsl_battery_levels_acin[];
-extern struct battery_thresh spitz_battery_levels_noac[];
+extern struct battery_thresh sharpsl_battery_levels_noac[];
 int sharpsl_pm_pxa_read_max1111(int channel);
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
index 629e05d1196e..67229a1ef55c 100644
--- a/arch/arm/mach-pxa/sharpsl_pm.c
+++ b/arch/arm/mach-pxa/sharpsl_pm.c
@@ -78,7 +78,7 @@ DEFINE_LED_TRIGGER(sharpsl_charge_led_trigger);
-struct battery_thresh spitz_battery_levels_acin[] = {
+struct battery_thresh sharpsl_battery_levels_acin[] = {
        { 213, 100},
        { 212,  98},
        { 211,  95},
@@ -121,7 +121,7 @@ struct battery_thresh spitz_battery_levels_acin[] = {
        {   0,   0},
 };
-struct battery_thresh  spitz_battery_levels_noac[] = {
+struct battery_thresh sharpsl_battery_levels_noac[] = {
        { 213, 100},
        { 212,  98},
        { 211,  95},
@@ -165,19 +165,20 @@ struct battery_thresh  spitz_battery_levels_noac[] = {
 };
 /* MAX1111 Commands */
-#define MAXCTRL_PD0      1u << 0
+#define MAXCTRL_PD0      (1u << 0)
-#define MAXCTRL_PD1      1u << 1
+#define MAXCTRL_PD1      (1u << 1)
-#define MAXCTRL_SGL      1u << 2
+#define MAXCTRL_SGL      (1u << 2)
-#define MAXCTRL_UNI      1u << 3
+#define MAXCTRL_UNI      (1u << 3)
 #define MAXCTRL_SEL_SH   4
-#define MAXCTRL_STR      1u << 7
+#define MAXCTRL_STR      (1u << 7)
 /*
 * Read MAX1111 ADC
 */
 int sharpsl_pm_pxa_read_max1111(int channel)
 {
-        if (machine_is_tosa()) // Ugly, better move this function into another module
+        /* Ugly, better move this function into another module */
+        if (machine_is_tosa())
            return 0;
 #ifdef CONFIG_CORGI_SSP_DEPRECATED
@@ -238,7 +239,7 @@ EXPORT_SYMBOL(sharpsl_battery_kick);
 static void sharpsl_battery_thread(struct work_struct *private_)
 {
-        int voltage, percent, apm_status, i = 0;
+        int voltage, percent, apm_status, i;
        if (!sharpsl_pm.machinfo)
                return;
@@ -250,15 +251,14 @@ static void sharpsl_battery_thread(struct work_struct *private_)
                        && time_after(jiffies, sharpsl_pm.charge_start_time +  SHARPSL_CHARGE_ON_TIME_INTERVAL))
                schedule_delayed_work(&toggle_charger, 0);
-        while(1) {
+        for (i = 0; i < 5; i++) {
                voltage = sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT);
+                if (voltage > 0)
-                if (voltage > 0) break;
-                if (i++ > 5) {
-                        voltage = sharpsl_pm.machinfo->bat_levels_noac[0].voltage;
-                        dev_warn(sharpsl_pm.dev, "Warning: Cannot read main battery!\n");
                        break;
-                }
+        }
+        if (voltage <= 0) {
+                voltage = sharpsl_pm.machinfo->bat_levels_noac[0].voltage;
+                dev_warn(sharpsl_pm.dev, "Warning: Cannot read main battery!\n");
        }
        voltage = sharpsl_average_value(voltage);
@@ -266,8 +266,10 @@ static void sharpsl_battery_thread(struct work_struct *private_)
        percent = get_percentage(voltage);
        /* At low battery voltages, the voltage has a tendency to start
-           creeping back up so we try to avoid this here */
+           creeping back up so we try to avoid this here */
-        if ((sharpsl_pm.battstat.ac_status == APM_AC_ONLINE) || (apm_status == APM_BATTERY_STATUS_HIGH) ||  percent <= sharpsl_pm.battstat.mainbat_percent) {
+        if ((sharpsl_pm.battstat.ac_status == APM_AC_ONLINE)
+            || (apm_status == APM_BATTERY_STATUS_HIGH)
+            || percent <= sharpsl_pm.battstat.mainbat_percent) {
                sharpsl_pm.battstat.mainbat_voltage = voltage;
                sharpsl_pm.battstat.mainbat_status = apm_status;
                sharpsl_pm.battstat.mainbat_percent = percent;
@@ -279,8 +281,8 @@ static void sharpsl_battery_thread(struct work_struct *private_)
 #ifdef CONFIG_BACKLIGHT_CORGI
        /* If battery is low. limit backlight intensity to save power. */
        if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE)
-                        && ((sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_LOW) ||
+            && ((sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_LOW)
-                        (sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_CRITICAL))) {
+            || (sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_CRITICAL))) {
                if (!(sharpsl_pm.flags & SHARPSL_BL_LIMIT)) {
                        sharpsl_pm.machinfo->backlight_limit(1);
                        sharpsl_pm.flags |= SHARPSL_BL_LIMIT;
@@ -293,8 +295,8 @@ static void sharpsl_battery_thread(struct work_struct *private_)
        /* Suspend if critical battery level */
        if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE)
-                        && (sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_CRITICAL)
+             && (sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_CRITICAL)
-                        && !(sharpsl_pm.flags & SHARPSL_APM_QUEUED)) {
+             && !(sharpsl_pm.flags & SHARPSL_APM_QUEUED)) {
                sharpsl_pm.flags |= SHARPSL_APM_QUEUED;
                dev_err(sharpsl_pm.dev, "Fatal Off\n");
                apm_queue_event(APM_CRITICAL_SUSPEND);
@@ -346,7 +348,7 @@ static void sharpsl_charge_error(void)
 static void sharpsl_charge_toggle(struct work_struct *private_)
 {
-        dev_dbg(sharpsl_pm.dev, "Toogling Charger at time: %lx\n", jiffies);
+        dev_dbg(sharpsl_pm.dev, "Toggling Charger at time: %lx\n", jiffies);
        if (!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN)) {
                sharpsl_charge_off();
@@ -368,7 +370,7 @@ static void sharpsl_ac_timer(unsigned long data)
 {
        int acin = sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN);
-        dev_dbg(sharpsl_pm.dev, "AC Status: %d\n",acin);
+        dev_dbg(sharpsl_pm.dev, "AC Status: %d\n", acin);
        sharpsl_average_clear();
        if (acin && (sharpsl_pm.charge_mode != CHRG_ON))
@@ -472,14 +474,14 @@ static int sharpsl_average_value(int ad)
        sharpsl_ad[sharpsl_ad_index] = ad;
        sharpsl_ad_index++;
        if (sharpsl_ad_index >= SHARPSL_CNV_VALUE_NUM) {
-                for (i=0; i < (SHARPSL_CNV_VALUE_NUM-1); i++)
+                for (i = 0; i < (SHARPSL_CNV_VALUE_NUM-1); i++)
                        sharpsl_ad[i] = sharpsl_ad[i+1];
                sharpsl_ad_index = SHARPSL_CNV_VALUE_NUM - 1;
        }
-        for (i=0; i < sharpsl_ad_index; i++)
+        for (i = 0; i < sharpsl_ad_index; i++)
                ad_val += sharpsl_ad[i];
-        return (ad_val / sharpsl_ad_index);
+        return ad_val / sharpsl_ad_index;
 }
 /*
@@ -492,8 +494,8 @@ static int get_select_val(int *val)
        /* Find MAX val */
        temp = val[0];
-        j=0;
+        j = 0;
-        for (i=1; i<5; i++) {
+        for (i = 1; i < 5; i++) {
                if (temp < val[i]) {
                        temp = val[i];
                        j = i;
@@ -502,21 +504,21 @@ static int get_select_val(int *val)
        /* Find MIN val */
        temp = val[4];
-        k=4;
+        k = 4;
-        for (i=3; i>=0; i--) {
+        for (i = 3; i >= 0; i--) {
                if (temp > val[i]) {
                        temp = val[i];
                        k = i;
                }
        }
-        for (i=0; i<5; i++)
+        for (i = 0; i < 5; i++)
-                if (i != j && i != k )
+                if (i != j && i != k)
                        sum += val[i];
        dev_dbg(sharpsl_pm.dev, "Average: %d from values: %d, %d, %d, %d, %d\n", sum/3, val[0], val[1], val[2], val[3], val[4]);
-        return (sum/3);
+        return sum/3;
 }
 static int sharpsl_check_battery_temp(void)
@@ -524,7 +526,7 @@ static int sharpsl_check_battery_temp(void)
        int val, i, buff[5];
        /* Check battery temperature */
-        for (i=0; i<5; i++) {
+        for (i = 0; i < 5; i++) {
                mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_TEMP);
                sharpsl_pm.machinfo->measure_temp(1);
                mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_TEMP);
@@ -557,7 +559,7 @@ static int sharpsl_check_battery_voltage(void)
                sharpsl_pm.machinfo->discharge1(1);
        /* Check battery voltage */
-        for (i=0; i<5; i++) {
+        for (i = 0; i < 5; i++) {
                buff[i] = sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT);
                mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_VOLT);
        }
@@ -581,16 +583,16 @@ static int sharpsl_ac_check(void)
 {
        int temp, i, buff[5];
-        for (i=0; i<5; i++) {
+        for (i = 0; i < 5; i++) {
                buff[i] = sharpsl_pm.machinfo->read_devdata(SHARPSL_ACIN_VOLT);
                mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_ACIN);
        }
        temp = get_select_val(buff);
-        dev_dbg(sharpsl_pm.dev, "AC Voltage: %d\n",temp);
+        dev_dbg(sharpsl_pm.dev, "AC Voltage: %d\n", temp);
        if ((temp > sharpsl_pm.machinfo->charge_acin_high) || (temp < sharpsl_pm.machinfo->charge_acin_low)) {
-                dev_err(sharpsl_pm.dev, "Error: AC check failed.\n");
+                dev_err(sharpsl_pm.dev, "Error: AC check failed: voltage %d.\n", temp);
                return -1;
        }
@@ -624,9 +626,9 @@ static int sharpsl_pm_resume(struct platform_device *pdev)
 static void corgi_goto_sleep(unsigned long alarm_time, unsigned int alarm_enable, suspend_state_t state)
 {
-        dev_dbg(sharpsl_pm.dev, "Time is: %08x\n",RCNR);
+        dev_dbg(sharpsl_pm.dev, "Time is: %08x\n", RCNR);
-        dev_dbg(sharpsl_pm.dev, "Offline Charge Activate = %d\n",sharpsl_pm.flags & SHARPSL_DO_OFFLINE_CHRG);
+        dev_dbg(sharpsl_pm.dev, "Offline Charge Activate = %d\n", sharpsl_pm.flags & SHARPSL_DO_OFFLINE_CHRG);
        /* not charging and AC-IN! */
        if ((sharpsl_pm.flags & SHARPSL_DO_OFFLINE_CHRG) && (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN))) {
@@ -644,12 +646,12 @@ static void corgi_goto_sleep(unsigned long alarm_time, unsigned int alarm_enable
        if ((sharpsl_pm.charge_mode == CHRG_ON) && ((alarm_enable && ((alarm_time - RCNR) > (SHARPSL_BATCHK_TIME_SUSPEND + 30))) || !alarm_enable)) {
                RTSR &= RTSR_ALE;
                RTAR = RCNR + SHARPSL_BATCHK_TIME_SUSPEND;
-                dev_dbg(sharpsl_pm.dev, "Charging alarm at: %08x\n",RTAR);
+                dev_dbg(sharpsl_pm.dev, "Charging alarm at: %08x\n", RTAR);
                sharpsl_pm.flags |= SHARPSL_ALARM_ACTIVE;
        } else if (alarm_enable) {
                RTSR &= RTSR_ALE;
                RTAR = alarm_time;
-                dev_dbg(sharpsl_pm.dev, "User alarm at: %08x\n",RTAR);
+                dev_dbg(sharpsl_pm.dev, "User alarm at: %08x\n", RTAR);
        } else {
                dev_dbg(sharpsl_pm.dev, "No alarms set.\n");
        }
@@ -658,19 +660,18 @@ static void corgi_goto_sleep(unsigned long alarm_time, unsigned int alarm_enable
        sharpsl_pm.machinfo->postsuspend();
-        dev_dbg(sharpsl_pm.dev, "Corgi woken up from suspend: %08x\n",PEDR);
+        dev_dbg(sharpsl_pm.dev, "Corgi woken up from suspend: %08x\n", PEDR);
 }
 static int corgi_enter_suspend(unsigned long alarm_time, unsigned int alarm_enable, suspend_state_t state)
 {
-        if (!sharpsl_pm.machinfo->should_wakeup(!(sharpsl_pm.flags & SHARPSL_ALARM_ACTIVE) && alarm_enable) )
+        if (!sharpsl_pm.machinfo->should_wakeup(!(sharpsl_pm.flags & SHARPSL_ALARM_ACTIVE) && alarm_enable)) {
-        {
                if (!(sharpsl_pm.flags & SHARPSL_ALARM_ACTIVE)) {
                        dev_dbg(sharpsl_pm.dev, "No user triggered wakeup events and not charging. Strange. Suspend.\n");
                        corgi_goto_sleep(alarm_time, alarm_enable, state);
                        return 1;
                }
-                if(sharpsl_off_charge_battery()) {
+                if (sharpsl_off_charge_battery()) {
                        dev_dbg(sharpsl_pm.dev, "Charging. Suspend...\n");
                        corgi_goto_sleep(alarm_time, alarm_enable, state);
                        return 1;
@@ -697,7 +698,7 @@ static int corgi_pxa_pm_enter(suspend_state_t state)
        corgi_goto_sleep(alarm_time, alarm_status, state);
-        while (corgi_enter_suspend(alarm_time,alarm_status,state))
+        while (corgi_enter_suspend(alarm_time, alarm_status, state))
                {}
        if (sharpsl_pm.machinfo->earlyresume)
@@ -732,7 +733,7 @@ static int sharpsl_fatal_check(void)
                sharpsl_pm.machinfo->discharge1(1);
        /* Check battery : check inserting battery ? */
-        for (i=0; i<5; i++) {
+        for (i = 0; i < 5; i++) {
                buff[i] = sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT);
                mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_VOLT);
        }
@@ -812,7 +813,7 @@ static int sharpsl_off_charge_battery(void)
                mdelay(SHARPSL_CHARGE_CO_CHECK_TIME);
                time = RCNR;
-                while(1) {
+                while (1) {
                        /* Check if any wakeup event had occurred */
                        if (sharpsl_pm.machinfo->charger_wakeup() != 0)
                                return 0;
@@ -835,9 +836,9 @@ static int sharpsl_off_charge_battery(void)
        mdelay(SHARPSL_CHARGE_CO_CHECK_TIME);
        time = RCNR;
-        while(1) {
+        while (1) {
                /* Check if any wakeup event had occurred */
-                if (sharpsl_pm.machinfo->charger_wakeup() != 0)
+                if (sharpsl_pm.machinfo->charger_wakeup())
                        return 0;
                /* Check for timeout */
                if ((RCNR-time) > SHARPSL_WAIT_CO_TIME) {
@@ -864,12 +865,12 @@ static int sharpsl_off_charge_battery(void)
 static ssize_t battery_percentage_show(struct device *dev, struct device_attribute *attr, char *buf)
 {
-        return sprintf(buf, "%d\n",sharpsl_pm.battstat.mainbat_percent);
+        return sprintf(buf, "%d\n", sharpsl_pm.battstat.mainbat_percent);
 }
 static ssize_t battery_voltage_show(struct device *dev, struct device_attribute *attr, char *buf)
 {
-        return sprintf(buf, "%d\n",sharpsl_pm.battstat.mainbat_voltage);
+        return sprintf(buf, "%d\n", sharpsl_pm.battstat.mainbat_voltage);
 }
 static DEVICE_ATTR(battery_percentage, 0444, battery_percentage_show, NULL);
@@ -943,8 +944,7 @@ static int __init sharpsl_pm_probe(struct platform_device *pdev)
                }
        }
-        if (sharpsl_pm.machinfo->batfull_irq)
+        if (sharpsl_pm.machinfo->batfull_irq) {
-        {
                /* Register interrupt handler. */
                if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr, IRQF_DISABLED | IRQF_TRIGGER_RISING, "CO", sharpsl_chrg_full_isr)) {
                        dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull));
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index d98023f55503..4b50f144fa48 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -768,6 +768,10 @@ static void __init common_init(void)
        pxa2xx_mfp_config(ARRAY_AND_SIZE(spitz_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        spitz_init_spi();
        platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c
index 724ffb030317..fc5a70c40358 100644
--- a/arch/arm/mach-pxa/spitz_pm.c
+++ b/arch/arm/mach-pxa/spitz_pm.c
@@ -103,7 +103,7 @@ static void spitz_presuspend(void)
        PFER = GPIO_bit(SPITZ_GPIO_KEY_INT) | GPIO_bit(SPITZ_GPIO_RESET);
        PWER = GPIO_bit(SPITZ_GPIO_KEY_INT) | GPIO_bit(SPITZ_GPIO_RESET) | PWER_RTC;
        PKWR = GPIO_bit(SPITZ_GPIO_SYNC) | GPIO_bit(SPITZ_GPIO_KEY_INT) | GPIO_bit(SPITZ_GPIO_RESET);
-        PKSR = 0xffffffff; // clear
+        PKSR = 0xffffffff; /* clear */
        /* nRESET_OUT Disable */
        PSLR |= PSLR_SL_ROD;
@@ -149,7 +149,7 @@ static int spitz_should_wakeup(unsigned int resume_on_alarm)
        if (resume_on_alarm && (PEDR & PWER_RTC))
                is_resume |= PWER_RTC;
-        dev_dbg(sharpsl_pm.dev, "is_resume: %x\n",is_resume);
+        dev_dbg(sharpsl_pm.dev, "is_resume: %x\n", is_resume);
        return is_resume;
 }
@@ -160,7 +160,7 @@ static unsigned long spitz_charger_wakeup(void)
 unsigned long spitzpm_read_devdata(int type)
 {
-        switch(type) {
+        switch (type) {
        case SHARPSL_STATUS_ACIN:
                return (((~GPLR(SPITZ_GPIO_AC_IN)) & GPIO_bit(SPITZ_GPIO_AC_IN)) != 0);
        case SHARPSL_STATUS_LOCK:
@@ -199,7 +199,7 @@ struct sharpsl_charger_machinfo spitz_pm_machinfo = {
 #if defined(CONFIG_LCD_CORGI)
        .backlight_limit = corgi_lcd_limit_intensity,
 #elif defined(CONFIG_BACKLIGHT_CORGI)
-        .backlight_limit  = corgibl_limit_intensity,
+        .backlight_limit  = corgibl_limit_intensity,
 #endif
        .charge_on_volt   = SHARPSL_CHARGE_ON_VOLT,
        .charge_on_temp   = SHARPSL_CHARGE_ON_TEMP,
@@ -208,8 +208,8 @@ struct sharpsl_charger_machinfo spitz_pm_machinfo = {
        .fatal_acin_volt  = SHARPSL_FATAL_ACIN_VOLT,
        .fatal_noacin_volt= SHARPSL_FATAL_NOACIN_VOLT,
        .bat_levels       = 40,
-        .bat_levels_noac  = spitz_battery_levels_noac,
+        .bat_levels_noac  = sharpsl_battery_levels_noac,
-        .bat_levels_acin  = spitz_battery_levels_acin,
+        .bat_levels_acin  = sharpsl_battery_levels_acin,
        .status_high_acin = 188,
        .status_low_acin  = 178,
        .status_high_noac = 185,
@@ -241,7 +241,7 @@ static int __devinit spitzpm_init(void)
 static void spitzpm_exit(void)
 {
-        platform_device_unregister(spitzpm_device);
+        platform_device_unregister(spitzpm_device);
 }
 module_init(spitzpm_init);
diff --git a/arch/arm/mach-pxa/ssp.c b/arch/arm/mach-pxa/ssp.c
index 965e38c6bafe..9ebe658590fa 100644
--- a/arch/arm/mach-pxa/ssp.c
+++ b/arch/arm/mach-pxa/ssp.c
@@ -342,8 +342,9 @@ void ssp_free(struct ssp_device *ssp)
 }
 EXPORT_SYMBOL(ssp_free);
-static int __devinit ssp_probe(struct platform_device *pdev, int type)
+static int __devinit ssp_probe(struct platform_device *pdev)
 {
+        const struct platform_device_id *id = platform_get_device_id(pdev);
        struct resource *res;
        struct ssp_device *ssp;
        int ret = 0;
@@ -413,7 +414,7 @@ static int __devinit ssp_probe(struct platform_device *pdev, int type)
         */
        ssp->port_id = pdev->id + 1;
        ssp->use_count = 0;
-        ssp->type = type;
+        ssp->type = (int)id->driver_data;
        mutex_lock(&ssp_lock);
        list_add(&ssp->node, &ssp_list);
@@ -457,75 +458,31 @@ static int __devexit ssp_remove(struct platform_device *pdev)
        return 0;
 }
-static int __devinit pxa25x_ssp_probe(struct platform_device *pdev)
+static const struct platform_device_id ssp_id_table[] = {
-{
+        { "pxa25x-ssp",         PXA25x_SSP },
-        return ssp_probe(pdev, PXA25x_SSP);
+        { "pxa25x-nssp",        PXA25x_NSSP },
-}
+        { "pxa27x-ssp",         PXA27x_SSP },
+        { },
-static int __devinit pxa25x_nssp_probe(struct platform_device *pdev)
-{
-        return ssp_probe(pdev, PXA25x_NSSP);
-}
-static int __devinit pxa27x_ssp_probe(struct platform_device *pdev)
-{
-        return ssp_probe(pdev, PXA27x_SSP);
-}
-static struct platform_driver pxa25x_ssp_driver = {
-        .driver         = {
-                .name   = "pxa25x-ssp",
-        },
-        .probe          = pxa25x_ssp_probe,
-        .remove         = __devexit_p(ssp_remove),
 };
-static struct platform_driver pxa25x_nssp_driver = {
+static struct platform_driver ssp_driver = {
-        .driver         = {
+        .probe          = ssp_probe,
-                .name   = "pxa25x-nssp",
-        },
-        .probe          = pxa25x_nssp_probe,
        .remove         = __devexit_p(ssp_remove),
-};
-static struct platform_driver pxa27x_ssp_driver = {
        .driver         = {
-                .name   = "pxa27x-ssp",
+                .owner  = THIS_MODULE,
+                .name   = "pxa2xx-ssp",
        },
-        .probe          = pxa27x_ssp_probe,
+        .id_table       = ssp_id_table,
-        .remove         = __devexit_p(ssp_remove),
 };
 static int __init pxa_ssp_init(void)
 {
-        int ret = 0;
+        return platform_driver_register(&ssp_driver);
-        ret = platform_driver_register(&pxa25x_ssp_driver);
-        if (ret) {
-                printk(KERN_ERR "failed to register pxa25x_ssp_driver");
-                return ret;
-        }
-        ret = platform_driver_register(&pxa25x_nssp_driver);
-        if (ret) {
-                printk(KERN_ERR "failed to register pxa25x_nssp_driver");
-                return ret;
-        }
-        ret = platform_driver_register(&pxa27x_ssp_driver);
-        if (ret) {
-                printk(KERN_ERR "failed to register pxa27x_ssp_driver");
-                return ret;
-        }
-        return ret;
 }
 static void __exit pxa_ssp_exit(void)
 {
-        platform_driver_unregister(&pxa25x_ssp_driver);
+        platform_driver_unregister(&ssp_driver);
-        platform_driver_unregister(&pxa25x_nssp_driver);
-        platform_driver_unregister(&pxa27x_ssp_driver);
 }
 arch_initcall(pxa_ssp_init);
diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c
index 3b205b69f3fb..a98a434f0111 100644
--- a/arch/arm/mach-pxa/stargate2.c
+++ b/arch/arm/mach-pxa/stargate2.c
@@ -760,6 +760,10 @@ static void __init stargate2_init(void)
        pxa2xx_mfp_config(ARRAY_AND_SIZE(stargate2_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        /* spi chip selects */
        gpio_direction_output(37, 0);
        gpio_direction_output(24, 0);
diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c
index b75353a2ec75..f02dcb5b4e97 100644
--- a/arch/arm/mach-pxa/tavorevb.c
+++ b/arch/arm/mach-pxa/tavorevb.c
@@ -477,6 +477,10 @@ static void __init tavorevb_init(void)
        /* initialize MFP configurations */
        pxa3xx_mfp_config(ARRAY_AND_SIZE(tavorevb_mfp_cfg));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        platform_device_register(&smc91x_device);
        tavorevb_init_lcd();
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index e81a52673d49..c854c168a451 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -825,6 +825,11 @@ static void __init tosa_init(void)
        int dummy;
        pxa2xx_mfp_config(ARRAY_AND_SIZE(tosa_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        gpio_set_wake(MFP_PIN_GPIO1, 1);
        /* We can't pass to gpio-keys since it will drop the Reset altfunc */
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
index 3981e0356d12..0aa858ebc573 100644
--- a/arch/arm/mach-pxa/trizeps4.c
+++ b/arch/arm/mach-pxa/trizeps4.c
@@ -524,6 +524,10 @@ static void __init trizeps4_init(void)
                                        ARRAY_SIZE(trizeps4_devices));
        }
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        if (0)  /* dont know how to determine LCD */
                set_pxa_fb_info(&sharp_lcd);
        else
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index d33c232b686c..cf0d71b7797e 100644
--- a/arch/arm/mach-pxa/viper.c
+++ b/arch/arm/mach-pxa/viper.c
@@ -301,15 +301,6 @@ static void __init viper_init_irq(void)
        set_irq_chained_handler(gpio_to_irq(VIPER_CPLD_GPIO),
                                viper_irq_handler);
        set_irq_type(gpio_to_irq(VIPER_CPLD_GPIO), IRQ_TYPE_EDGE_BOTH);
-#ifndef CONFIG_SERIAL_PXA
-        /*
-         * 8250 doesn't support IRQ_TYPE being passed as part
-         * of the plat_serial8250_port structure...
-         */
-        set_irq_type(gpio_to_irq(VIPER_UARTA_GPIO), IRQ_TYPE_EDGE_RISING);
-        set_irq_type(gpio_to_irq(VIPER_UARTB_GPIO), IRQ_TYPE_EDGE_RISING);
-#endif
 }
 /* Flat Panel */
@@ -539,6 +530,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
        {
                .mapbase        = VIPER_UARTA_PHYS,
                .irq            = gpio_to_irq(VIPER_UARTA_GPIO),
+                .irqflags       = IRQF_TRIGGER_RISING,
                .uartclk        = 1843200,
                .regshift       = 1,
                .iotype         = UPIO_MEM,
@@ -548,6 +540,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
        {
                .mapbase        = VIPER_UARTB_PHYS,
                .irq            = gpio_to_irq(VIPER_UARTB_GPIO),
+                .irqflags       = IRQF_TRIGGER_RISING,
                .uartclk        = 1843200,
                .regshift       = 1,
                .iotype         = UPIO_MEM,
@@ -908,6 +901,10 @@ static void __init viper_init(void)
        pxa2xx_mfp_config(ARRAY_AND_SIZE(viper_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        /* Wake-up serial console */
        viper_init_serial_gpio();
diff --git a/arch/arm/mach-pxa/xcep.c b/arch/arm/mach-pxa/xcep.c
index 3fd79cbb36c8..d3b4e3f2e033 100644
--- a/arch/arm/mach-pxa/xcep.c
+++ b/arch/arm/mach-pxa/xcep.c
@@ -165,6 +165,11 @@ static void __init xcep_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(xcep_pin_config));
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
+        pxa_set_hwuart_info(NULL);
        /* See Intel XScale Developer's Guide for details */
        /* Set RDF and RDN to appropriate values (chip select 3 (smc91x)) */
        MSC1 = (MSC1 & 0xffff) | 0xD5540000;
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index 09784d3954e4..b66e9e2d06e7 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -31,7 +31,7 @@
 #include <mach/mmc.h>
 #include <mach/ohci.h>
 #include <mach/pxa27x_keypad.h>
-#include <mach/pxa3xx_nand.h>
+#include <plat/pxa3xx_nand.h>
 #include "devices.h"
 #include "generic.h"
@@ -444,6 +444,10 @@ static inline void zylonite_init_ohci(void) {}
 static void __init zylonite_init(void)
 {
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
        /* board-processor specific initialization */
        zylonite_pxa300_init();
        zylonite_pxa320_init();
diff --git a/arch/arm/mach-s3c2400/include/mach/map.h b/arch/arm/mach-s3c2400/include/mach/map.h
index 1535540edc82..3fd889200e99 100644
--- a/arch/arm/mach-s3c2400/include/mach/map.h
+++ b/arch/arm/mach-s3c2400/include/mach/map.h
@@ -1,6 +1,6 @@
 /* arch/arm/mach-s3c2400/include/mach/map.h
 *
- * Copyright 2003,2007  Simtec Electronics
+ * Copyright 2003-2007 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index 3d4e9da3fa52..dd1fcc7e6708 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -81,6 +81,14 @@ config ARCH_H1940
        help
          Say Y here if you are using the HP IPAQ H1940
+config H1940BT
+        tristate "Control the state of H1940 bluetooth chip"
+        depends on ARCH_H1940
+        select RFKILL
+        help
+          This is a simple driver that is able to control
+          the state of built in bluetooth chip on h1940.
 config PM_H1940
        bool
        help
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile
index 2ab5ba4b266f..0d468e96e83e 100644
--- a/arch/arm/mach-s3c2410/Makefile
+++ b/arch/arm/mach-s3c2410/Makefile
@@ -21,7 +21,8 @@ obj-$(CONFIG_S3C2410_PLLTABLE)	+= pll.o
 # Machine support
 obj-$(CONFIG_ARCH_SMDK2410)     += mach-smdk2410.o
-obj-$(CONFIG_ARCH_H1940)        += mach-h1940.o h1940-bluetooth.o
+obj-$(CONFIG_ARCH_H1940)        += mach-h1940.o
+obj-$(CONFIG_H1940BT)           += h1940-bluetooth.o
 obj-$(CONFIG_PM_H1940)          += pm-h1940.o
 obj-$(CONFIG_MACH_N30)          += mach-n30.o
 obj-$(CONFIG_ARCH_BAST)         += mach-bast.o usb-simtec.o
diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c
index 9a37c87152b0..217b102866d0 100644
--- a/arch/arm/mach-s3c2410/bast-irq.c
+++ b/arch/arm/mach-s3c2410/bast-irq.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s3c2410/bast-irq.c
 *
- * Copyright (c) 2003,2005 Simtec Electronics
+ * Copyright 2003-2005 Simtec Electronics
 *   Ben Dooks <ben@simtec.co.uk>
 *
 * http://www.simtec.co.uk/products/EB2410ITX/
@@ -141,7 +141,7 @@ static __init int bast_irq_init(void)
        unsigned int i;
        if (machine_is_bast()) {
-                printk(KERN_INFO "BAST PC104 IRQ routing, (c) 2005 Simtec Electronics\n");
+                printk(KERN_INFO "BAST PC104 IRQ routing, Copyright 2005 Simtec Electronics\n");
                /* zap all the IRQs */
diff --git a/arch/arm/mach-s3c2410/cpu-freq.c b/arch/arm/mach-s3c2410/cpu-freq.c
index 9d1186877d08..75189df995ae 100644
--- a/arch/arm/mach-s3c2410/cpu-freq.c
+++ b/arch/arm/mach-s3c2410/cpu-freq.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s3c2410/cpu-freq.c
 *
- * Copyright (c) 2006,2008 Simtec Electronics
+ * Copyright (c) 2006-2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *
diff --git a/arch/arm/mach-s3c2410/h1940-bluetooth.c b/arch/arm/mach-s3c2410/h1940-bluetooth.c
index 5aabf117cbb0..b7d1f8d27bc2 100644
--- a/arch/arm/mach-s3c2410/h1940-bluetooth.c
+++ b/arch/arm/mach-s3c2410/h1940-bluetooth.c
@@ -17,6 +17,7 @@
 #include <linux/ctype.h>
 #include <linux/leds.h>
 #include <linux/gpio.h>
+#include <linux/rfkill.h>
 #include <mach/regs-gpio.h>
 #include <mach/hardware.h>
@@ -24,21 +25,10 @@
 #define DRV_NAME              "h1940-bt"
-#ifdef CONFIG_LEDS_H1940
-DEFINE_LED_TRIGGER(bt_led_trigger);
-#endif
-static int state;
 /* Bluetooth control */
 static void h1940bt_enable(int on)
 {
        if (on) {
-#ifdef CONFIG_LEDS_H1940
-                /* flashing Blue */
-                led_trigger_event(bt_led_trigger, LED_HALF);
-#endif
                /* Power on the chip */
                h1940_latch_control(0, H1940_LATCH_BLUETOOTH_POWER);
                /* Reset the chip */
@@ -46,48 +36,31 @@ static void h1940bt_enable(int on)
                s3c2410_gpio_setpin(S3C2410_GPH(1), 1);
                mdelay(10);
                s3c2410_gpio_setpin(S3C2410_GPH(1), 0);
-                state = 1;
        }
        else {
-#ifdef CONFIG_LEDS_H1940
-                led_trigger_event(bt_led_trigger, 0);
-#endif
                s3c2410_gpio_setpin(S3C2410_GPH(1), 1);
                mdelay(10);
                s3c2410_gpio_setpin(S3C2410_GPH(1), 0);
                mdelay(10);
                h1940_latch_control(H1940_LATCH_BLUETOOTH_POWER, 0);
-                state = 0;
        }
 }
-static ssize_t h1940bt_show(struct device *dev, struct device_attribute *attr, char *buf)
+static int h1940bt_set_block(void *data, bool blocked)
 {
-        return snprintf(buf, PAGE_SIZE, "%d\n", state);
+        h1940bt_enable(!blocked);
+        return 0;
 }
-static ssize_t h1940bt_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
+static const struct rfkill_ops h1940bt_rfkill_ops = {
-{
+        .set_block = h1940bt_set_block,
-        int new_state;
+};
-        char *endp;
-        new_state = simple_strtoul(buf, &endp, 0);
-        if (*endp && !isspace(*endp))
-                return -EINVAL;
-        h1940bt_enable(new_state);
-        return count;
-}
-static DEVICE_ATTR(enable, 0644,
-                h1940bt_show,
-                h1940bt_store);
 static int __init h1940bt_probe(struct platform_device *pdev)
 {
+        struct rfkill *rfk;
+        int ret = 0;
        /* Configures BT serial port GPIOs */
        s3c2410_gpio_cfgpin(S3C2410_GPH(0), S3C2410_GPH0_nCTS0);
        s3c2410_gpio_pullup(S3C2410_GPH(0), 1);
@@ -98,21 +71,44 @@ static int __init h1940bt_probe(struct platform_device *pdev)
        s3c2410_gpio_cfgpin(S3C2410_GPH(3), S3C2410_GPH3_RXD0);
        s3c2410_gpio_pullup(S3C2410_GPH(3), 1);
-#ifdef CONFIG_LEDS_H1940
-        led_trigger_register_simple("h1940-bluetooth", &bt_led_trigger);
-#endif
-        /* disable BT by default */
+        rfk = rfkill_alloc(DRV_NAME, &pdev->dev, RFKILL_TYPE_BLUETOOTH,
-        h1940bt_enable(0);
+                        &h1940bt_rfkill_ops, NULL);
+        if (!rfk) {
+                ret = -ENOMEM;
+                goto err_rfk_alloc;
+        }
+        rfkill_set_led_trigger_name(rfk, "h1940-bluetooth");
+        ret = rfkill_register(rfk);
+        if (ret)
+                goto err_rfkill;
+        platform_set_drvdata(pdev, rfk);
+        return 0;
-        return device_create_file(&pdev->dev, &dev_attr_enable);
+err_rfkill:
+        rfkill_destroy(rfk);
+err_rfk_alloc:
+        return ret;
 }
 static int h1940bt_remove(struct platform_device *pdev)
 {
-#ifdef CONFIG_LEDS_H1940
+        struct rfkill *rfk = platform_get_drvdata(pdev);
-        led_trigger_unregister_simple(bt_led_trigger);
-#endif
+        platform_set_drvdata(pdev, NULL);
+        if (rfk) {
+                rfkill_unregister(rfk);
+                rfkill_destroy(rfk);
+        }
+        rfk = NULL;
+        h1940bt_enable(0);
        return 0;
 }
diff --git a/arch/arm/mach-s3c2410/include/mach/bast-cpld.h b/arch/arm/mach-s3c2410/include/mach/bast-cpld.h
index 20493b048360..bee2a7a932a0 100644
--- a/arch/arm/mach-s3c2410/include/mach/bast-cpld.h
+++ b/arch/arm/mach-s3c2410/include/mach/bast-cpld.h
@@ -1,6 +1,6 @@
 /* arch/arm/mach-s3c2410/include/mach/bast-cpld.h
 *
- * Copyright (c) 2003,2004 Simtec Electronics
+ * Copyright (c) 2003-2004 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * BAST - CPLD control constants
diff --git a/arch/arm/mach-s3c2410/include/mach/bast-irq.h b/arch/arm/mach-s3c2410/include/mach/bast-irq.h
index 501c202b53cf..cac428c42e7f 100644
--- a/arch/arm/mach-s3c2410/include/mach/bast-irq.h
+++ b/arch/arm/mach-s3c2410/include/mach/bast-irq.h
@@ -1,6 +1,6 @@
 /* arch/arm/mach-s3c2410/include/mach/bast-irq.h
 *
- * Copyright (c) 2003,2004 Simtec Electronics
+ * Copyright (c) 2003-2004 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * Machine BAST - IRQ Number definitions
diff --git a/arch/arm/mach-s3c2410/include/mach/bast-map.h b/arch/arm/mach-s3c2410/include/mach/bast-map.h
index c2c5baf07345..6e7dc9d0cf0e 100644
--- a/arch/arm/mach-s3c2410/include/mach/bast-map.h
+++ b/arch/arm/mach-s3c2410/include/mach/bast-map.h
@@ -1,6 +1,6 @@
 /* arch/arm/mach-s3c2410/include/mach/bast-map.h
 *
- * Copyright (c) 2003,2004 Simtec Electronics
+ * Copyright (c) 2003-2004 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * Machine BAST - Memory map definitions
diff --git a/arch/arm/mach-s3c2410/include/mach/bast-pmu.h b/arch/arm/mach-s3c2410/include/mach/bast-pmu.h
index 61684cb8ce59..4c38b39b741d 100644
--- a/arch/arm/mach-s3c2410/include/mach/bast-pmu.h
+++ b/arch/arm/mach-s3c2410/include/mach/bast-pmu.h
@@ -1,6 +1,6 @@
 /* arch/arm/mach-s3c2410/include/mach/bast-pmu.h
 *
- * Copyright (c) 2003,2004 Simtec Electronics
+ * Copyright (c) 2003-2004 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *      Vincent Sanders <vince@simtec.co.uk>
 *
diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h
index 92e2687009ea..08ac5f96c012 100644
--- a/arch/arm/mach-s3c2410/include/mach/dma.h
+++ b/arch/arm/mach-s3c2410/include/mach/dma.h
@@ -1,6 +1,6 @@
 /* arch/arm/mach-s3c2410/include/mach/dma.h
 *
- * Copyright (C) 2003,2004,2006 Simtec Electronics
+ * Copyright (C) 2003-2006 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * Samsung S3C24XX DMA support
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
index 801dff13858d..035a493952db 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
@@ -1,6 +1,6 @@
 /* arch/arm/mach-s3c2410/include/mach/gpio-fns.h
 *
- * Copyright (c) 2003,2009 Simtec Electronics
+ * Copyright (c) 2003-2009 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * S3C2410 - hardware
diff --git a/arch/arm/mach-s3c2410/include/mach/osiris-map.h b/arch/arm/mach-s3c2410/include/mach/osiris-map.h
index 639eff523d4e..17380f848428 100644
--- a/arch/arm/mach-s3c2410/include/mach/osiris-map.h
+++ b/arch/arm/mach-s3c2410/include/mach/osiris-map.h
@@ -1,6 +1,6 @@
 /* arch/arm/mach-s3c2410/include/mach/osiris-map.h
 *
- * (c) 2005 Simtec Electronics
+ * Copyright 2005 Simtec Electronics
 *      http://www.simtec.co.uk/products/
 *      Ben Dooks <ben@simtec.co.uk>
 *
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-clock.h
index 2a5d90e957fb..9a0d169be137 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-clock.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-clock.h
@@ -1,7 +1,7 @@
 /* arch/arm/mach-s3c2410/include/mach/regs-clock.h
 *
- * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk>
+ * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
- *                    http://armlinux.simtec.co.uk/
+ *      http://armlinux.simtec.co.uk/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
index f6e8eec879c8..ebc85c6dadbf 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
@@ -1,7 +1,7 @@
 /* arch/arm/mach-s3c2410/include/mach/regs-gpio.h
 *
- * Copyright (c) 2003,2004 Simtec Electronics <linux@simtec.co.uk>
+ * Copyright (c) 2003-2004 Simtec Electronics <linux@simtec.co.uk>
- *                         http://www.simtec.co.uk/products/SWLINUX/
+ *      http://www.simtec.co.uk/products/SWLINUX/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-power.h b/arch/arm/mach-s3c2410/include/mach/regs-power.h
index 2d36353f57d7..4932b87bdf3d 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-power.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-power.h
@@ -1,7 +1,7 @@
 /* arch/arm/mach-s3c2410/include/mach/regs-power.h
 *
- * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk>
+ * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
- *                    http://armlinux.simtec.co.uk/
+ *      http://armlinux.simtec.co.uk/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s3c2410/include/mach/uncompress.h b/arch/arm/mach-s3c2410/include/mach/uncompress.h
index c9432103750d..72f756c5e504 100644
--- a/arch/arm/mach-s3c2410/include/mach/uncompress.h
+++ b/arch/arm/mach-s3c2410/include/mach/uncompress.h
@@ -1,7 +1,6 @@
 /* arch/arm/mach-s3c2410/include/mach/uncompress.h
 *
- * Copyright (c) 2003, 2007 Simtec Electronics
+ * Copyright (c) 2003-2007 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *
diff --git a/arch/arm/mach-s3c2410/include/mach/vr1000-irq.h b/arch/arm/mach-s3c2410/include/mach/vr1000-irq.h
index f53f85b4ad8b..47add133b8ee 100644
--- a/arch/arm/mach-s3c2410/include/mach/vr1000-irq.h
+++ b/arch/arm/mach-s3c2410/include/mach/vr1000-irq.h
@@ -1,6 +1,6 @@
 /* arch/arm/mach-s3c2410/include/mach/vr1000-irq.h
 *
- * Copyright (c) 2003,2004 Simtec Electronics
+ * Copyright (c) 2003-2004 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * Machine VR1000 - IRQ Number definitions
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 647c9adb018f..4c79ac8a6c33 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s3c2410/mach-bast.c
 *
- * Copyright (c) 2003-2005,2008 Simtec Electronics
+ * Copyright 2003-2008 Simtec Electronics
 *   Ben Dooks <ben@simtec.co.uk>
 *
 * http://www.simtec.co.uk/products/EB2410ITX/
@@ -61,11 +61,12 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/cpu-freq.h>
+#include <plat/audio-simtec.h>
 #include "usb-simtec.h"
 #include "nor-simtec.h"
-#define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"
+#define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"
 /* macros for virtual address mods for the io space entries */
 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
@@ -247,7 +248,7 @@ static int chip0_map[] = { 1 };
 static int chip1_map[] = { 2 };
 static int chip2_map[] = { 3 };
-static struct mtd_partition bast_default_nand_part[] = {
+static struct mtd_partition __initdata bast_default_nand_part[] = {
        [0] = {
                .name   = "Boot Agent",
                .size   = SZ_16K,
@@ -273,7 +274,7 @@ static struct mtd_partition bast_default_nand_part[] = {
 * socket.
 */
-static struct s3c2410_nand_set bast_nand_sets[] = {
+static struct s3c2410_nand_set __initdata bast_nand_sets[] = {
        [0] = {
                .name           = "SmartMedia",
                .nr_chips       = 1,
@@ -323,7 +324,7 @@ static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
        __raw_writeb(tmp, BAST_VA_CTRL2);
 }
-static struct s3c2410_platform_nand bast_nand_info = {
+static struct s3c2410_platform_nand __initdata bast_nand_info = {
        .tacls          = 30,
        .twrph0         = 60,
        .twrph1         = 60,
@@ -608,6 +609,11 @@ static struct s3c_cpufreq_board __initdata bast_cpufreq = {
        .need_io        = 1,
 };
+static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = {
+        .have_mic       = 1,
+        .have_lout      = 1,
+};
 static void __init bast_map_io(void)
 {
        /* initialise the clocks */
@@ -625,7 +631,6 @@ static void __init bast_map_io(void)
        s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
-        s3c_device_nand.dev.platform_data = &bast_nand_info;
        s3c_device_hwmon.dev.platform_data = &bast_hwmon_info;
        s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
@@ -639,6 +644,7 @@ static void __init bast_init(void)
        sysdev_register(&bast_pm_sysdev);
        s3c_i2c0_set_platdata(&bast_i2c_info);
+        s3c_nand_set_platdata(&bast_nand_info);
        s3c24xx_fb_set_platdata(&bast_fb_info);
        platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
@@ -647,6 +653,7 @@ static void __init bast_init(void)
        usb_simtec_init();
        nor_simtec_init();
+        simtec_audio_add(NULL, true, &bast_audio);
        s3c_cpufreq_setboard(&bast_cpufreq);
 }
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index d9cd5ddecf4a..49053254c98d 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -21,6 +21,11 @@
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/pwm_backlight.h>
+#include <video/platform_lcd.h>
+#include <linux/mmc/host.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -32,9 +37,12 @@
 #include <plat/regs-serial.h>
 #include <mach/regs-lcd.h>
-#include <mach/regs-gpio.h>
 #include <mach/regs-clock.h>
+#include <mach/regs-gpio.h>
+#include <mach/gpio-fns.h>
+#include <mach/gpio-nrs.h>
 #include <mach/h1940.h>
 #include <mach/h1940-latch.h>
 #include <mach/fb.h>
@@ -46,6 +54,7 @@
 #include <plat/cpu.h>
 #include <plat/pll.h>
 #include <plat/pm.h>
+#include <plat/mci.h>
 static struct map_desc h1940_iodesc[] __initdata = {
        [0] = {
@@ -171,16 +180,90 @@ static struct s3c2410fb_mach_info h1940_fb_info __initdata = {
        .gpdup_mask=    0xffffffff,
 };
-static struct platform_device s3c_device_leds = {
+static struct platform_device h1940_device_leds = {
        .name             = "h1940-leds",
        .id               = -1,
 };
-static struct platform_device s3c_device_bluetooth = {
+static struct platform_device h1940_device_bluetooth = {
        .name             = "h1940-bt",
        .id               = -1,
 };
+static struct s3c24xx_mci_pdata h1940_mmc_cfg = {
+        .gpio_detect   = S3C2410_GPF(5),
+        .gpio_wprotect = S3C2410_GPH(8),
+        .set_power     = NULL,
+        .ocr_avail     = MMC_VDD_32_33,
+};
+static int h1940_backlight_init(struct device *dev)
+{
+        gpio_request(S3C2410_GPB(0), "Backlight");
+        s3c2410_gpio_setpin(S3C2410_GPB(0), 0);
+        s3c2410_gpio_pullup(S3C2410_GPB(0), 0);
+        s3c2410_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPB0_TOUT0);
+        return 0;
+}
+static void h1940_backlight_exit(struct device *dev)
+{
+        s3c2410_gpio_cfgpin(S3C2410_GPB(0), 1/*S3C2410_GPB0_OUTP*/);
+}
+static struct platform_pwm_backlight_data backlight_data = {
+        .pwm_id         = 0,
+        .max_brightness = 100,
+        .dft_brightness = 50,
+        /* tcnt = 0x31 */
+        .pwm_period_ns  = 36296,
+        .init           = h1940_backlight_init,
+        .exit           = h1940_backlight_exit,
+};
+static struct platform_device h1940_backlight = {
+        .name = "pwm-backlight",
+        .dev  = {
+                .parent = &s3c_device_timer[0].dev,
+                .platform_data = &backlight_data,
+        },
+        .id   = -1,
+};
+static void h1940_lcd_power_set(struct plat_lcd_data *pd,
+                                        unsigned int power)
+{
+        int value;
+        if (!power) {
+                /* set to 3ec */
+                s3c2410_gpio_setpin(S3C2410_GPC(0), 0);
+                /* wait for 3ac */
+                do {
+                        value = s3c2410_gpio_getpin(S3C2410_GPC(6));
+                } while (value);
+                /* set to 38c */
+                s3c2410_gpio_setpin(S3C2410_GPC(5), 0);
+        } else {
+                /* Set to 3ac */
+                s3c2410_gpio_setpin(S3C2410_GPC(5), 1);
+                /* Set to 3ad */
+                s3c2410_gpio_setpin(S3C2410_GPC(0), 1);
+        }
+}
+static struct plat_lcd_data h1940_lcd_power_data = {
+        .set_power      = h1940_lcd_power_set,
+};
+static struct platform_device h1940_lcd_powerdev = {
+        .name                   = "platform-lcd",
+        .dev.parent             = &s3c_device_lcd.dev,
+        .dev.platform_data      = &h1940_lcd_power_data,
+};
 static struct platform_device *h1940_devices[] __initdata = {
        &s3c_device_usb,
        &s3c_device_lcd,
@@ -188,8 +271,13 @@ static struct platform_device *h1940_devices[] __initdata = {
        &s3c_device_i2c0,
        &s3c_device_iis,
        &s3c_device_usbgadget,
-        &s3c_device_leds,
+        &h1940_device_leds,
-        &s3c_device_bluetooth,
+        &h1940_device_bluetooth,
+        &s3c_device_sdi,
+        &s3c_device_rtc,
+        &s3c_device_timer[0],
+        &h1940_backlight,
+        &h1940_lcd_powerdev,
 };
 static void __init h1940_map_io(void)
@@ -219,6 +307,8 @@ static void __init h1940_init(void)
        s3c24xx_udc_set_platdata(&h1940_udc_cfg);
        s3c_i2c0_set_platdata(NULL);
+        s3c_device_sdi.dev.platform_data = &h1940_mmc_cfg;
        /* Turn off suspend on both USB ports, and switch the
         * selectable USB port to USB device mode. */
@@ -231,6 +321,11 @@ static void __init h1940_init(void)
              | (0x03 << S3C24XX_PLLCON_SDIVSHIFT);
        writel(tmp, S3C2410_UPLLCON);
+        gpio_request(S3C2410_GPC(0), "LCD power");
+        gpio_request(S3C2410_GPC(5), "LCD power");
+        gpio_request(S3C2410_GPC(6), "LCD power");
        platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices));
 }
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 0f6ed61af415..0405712c2263 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -338,7 +338,7 @@ static struct platform_device *n35_devices[] __initdata = {
        &n35_button_device,
 };
-static struct s3c2410_platform_i2c n30_i2ccfg = {
+static struct s3c2410_platform_i2c __initdata n30_i2ccfg = {
        .flags          = 0,
        .slave_addr     = 0x10,
        .frequency      = 10*1000,
@@ -500,8 +500,8 @@ static void __init n30_init_irq(void)
 static void __init n30_init(void)
 {
        s3c24xx_fb_set_platdata(&n30_fb_info);
-        s3c_device_i2c0.dev.platform_data = &n30_i2ccfg;
        s3c24xx_udc_set_platdata(&n30_udc_cfg);
+        s3c_i2c0_set_platdata(&n30_i2ccfg);
        /* Turn off suspend on both USB ports, and switch the
         * selectable USB port to USB device mode. */
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index 2cc9849eb448..ab092bcda393 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -258,7 +258,7 @@ static struct platform_device *qt2410_devices[] __initdata = {
        &qt2410_led,
 };
-static struct mtd_partition qt2410_nand_part[] = {
+static struct mtd_partition __initdata qt2410_nand_part[] = {
        [0] = {
                .name   = "U-Boot",
                .size   = 0x30000,
@@ -286,7 +286,7 @@ static struct mtd_partition qt2410_nand_part[] = {
        },
 };
-static struct s3c2410_nand_set qt2410_nand_sets[] = {
+static struct s3c2410_nand_set __initdata qt2410_nand_sets[] = {
        [0] = {
                .name           = "NAND",
                .nr_chips       = 1,
@@ -299,7 +299,7 @@ static struct s3c2410_nand_set qt2410_nand_sets[] = {
 * chips and beyond.
 */
-static struct s3c2410_platform_nand qt2410_nand_info = {
+static struct s3c2410_platform_nand __initdata qt2410_nand_info = {
        .tacls          = 20,
        .twrph0         = 60,
        .twrph1         = 20,
@@ -331,7 +331,7 @@ static void __init qt2410_map_io(void)
 static void __init qt2410_machine_init(void)
 {
-        s3c_device_nand.dev.platform_data = &qt2410_nand_info;
+        s3c_nand_set_platdata(&qt2410_nand_info);
        switch (tft_type) {
        case 'p': /* production */
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index 1628cc773a2c..0d61fb577170 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s3c2410/mach-vr1000.c
 *
- * Copyright (c) 2003-2005,2008 Simtec Electronics
+ * Copyright (c) 2003-2008 Simtec Electronics
 *   Ben Dooks <ben@simtec.co.uk>
 *
 * Machine support for Thorcom VR1000 board. Designed for Thorcom by
@@ -49,6 +49,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/iic.h>
+#include <plat/audio-simtec.h>
 #include "usb-simtec.h"
 #include "nor-simtec.h"
@@ -393,6 +394,7 @@ static void __init vr1000_init(void)
                                ARRAY_SIZE(vr1000_i2c_devs));
        nor_simtec_init();
+        simtec_audio_add(NULL, true, NULL);
 }
 MACHINE_START(VR1000, "Thorcom-VR1000")
diff --git a/arch/arm/mach-s3c2410/pll.c b/arch/arm/mach-s3c2410/pll.c
index f178c2fd9d85..8338865e11c0 100644
--- a/arch/arm/mach-s3c2410/pll.c
+++ b/arch/arm/mach-s3c2410/pll.c
@@ -1,6 +1,6 @@
 /* arch/arm/mach-s3c2410/pll.c
 *
- * Copyright (c) 2006,2007 Simtec Electronics
+ * Copyright (c) 2006-2007 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *      Vincent Sanders <vince@arm.linux.org.uk>
diff --git a/arch/arm/mach-s3c2410/usb-simtec.c b/arch/arm/mach-s3c2410/usb-simtec.c
index 50e25fc5f8ab..6b9d0d83a6f9 100644
--- a/arch/arm/mach-s3c2410/usb-simtec.c
+++ b/arch/arm/mach-s3c2410/usb-simtec.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s3c2410/usb-simtec.c
 *
- * Copyright (c) 2004,2005 Simtec Electronics
+ * Copyright 2004-2005 Simtec Electronics
 *   Ben Dooks <ben@simtec.co.uk>
 *
 * http://www.simtec.co.uk/products/EB2410ITX/
@@ -108,7 +108,7 @@ int usb_simtec_init(void)
 {
        int ret;
-        printk("USB Power Control, (c) 2004 Simtec Electronics\n");
+        printk("USB Power Control, Copyright 2004 Simtec Electronics\n");
        ret = gpio_request(S3C2410_GPB(4), "USB power control");
        if (ret < 0) {
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c
index 8df506eac903..c9fa3fca486c 100644
--- a/arch/arm/mach-s3c2412/mach-jive.c
+++ b/arch/arm/mach-s3c2412/mach-jive.c
@@ -96,7 +96,7 @@ static struct s3c2410_uartcfg jive_uartcfgs[] = {
 * 0x017d0000-0x02bd0000 : cramfs B
 * 0x02bd0000-0x03fd0000 : yaffs
 */
-static struct mtd_partition jive_imageA_nand_part[] = {
+static struct mtd_partition __initdata jive_imageA_nand_part[] = {
 #ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
        /* Don't allow access to the bootloader from linux */
@@ -154,7 +154,7 @@ static struct mtd_partition jive_imageA_nand_part[] = {
        },
 };
-static struct mtd_partition jive_imageB_nand_part[] = {
+static struct mtd_partition __initdata jive_imageB_nand_part[] = {
 #ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
        /* Don't allow access to the bootloader from linux */
@@ -213,7 +213,7 @@ static struct mtd_partition jive_imageB_nand_part[] = {
        },
 };
-static struct s3c2410_nand_set jive_nand_sets[] = {
+static struct s3c2410_nand_set __initdata jive_nand_sets[] = {
        [0] = {
                .name           = "flash",
                .nr_chips       = 1,
@@ -222,7 +222,7 @@ static struct s3c2410_nand_set jive_nand_sets[] = {
        },
 };
-static struct s3c2410_platform_nand jive_nand_info = {
+static struct s3c2410_platform_nand __initdata jive_nand_info = {
        /* set taken from osiris nand timings, possibly still conservative */
        .tacls          = 30,
        .twrph0         = 55,
@@ -631,7 +631,8 @@ static void __init jive_machine_init(void)
        s3c_pm_init();
-        s3c_device_nand.dev.platform_data = &jive_nand_info;
+        /** TODO - check that this is after the cmdline option! */
+        s3c_nand_set_platdata(&jive_nand_info);
        /* initialise the spi */
diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c
index 11e8ad49fc7b..a6ba591b26bb 100644
--- a/arch/arm/mach-s3c2412/mach-vstms.c
+++ b/arch/arm/mach-s3c2412/mach-vstms.c
@@ -76,7 +76,7 @@ static struct s3c2410_uartcfg vstms_uartcfgs[] __initdata = {
        }
 };
-static struct mtd_partition vstms_nand_part[] = {
+static struct mtd_partition __initdata vstms_nand_part[] = {
        [0] = {
                .name   = "Boot Agent",
                .size   = 0x7C000,
@@ -99,7 +99,7 @@ static struct mtd_partition vstms_nand_part[] = {
        },
 };
-static struct s3c2410_nand_set vstms_nand_sets[] = {
+static struct s3c2410_nand_set __initdata vstms_nand_sets[] = {
        [0] = {
                .name           = "NAND",
                .nr_chips       = 1,
@@ -112,7 +112,7 @@ static struct s3c2410_nand_set vstms_nand_sets[] = {
 * chips and beyond.
 */
-static struct s3c2410_platform_nand vstms_nand_info = {
+static struct s3c2410_platform_nand __initdata vstms_nand_info = {
        .tacls          = 20,
        .twrph0         = 60,
        .twrph1         = 20,
@@ -143,8 +143,6 @@ static void __init vstms_fixup(struct machine_desc *desc,
 static void __init vstms_map_io(void)
 {
-        s3c_device_nand.dev.platform_data = &vstms_nand_info;
        s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc));
        s3c24xx_init_clocks(12000000);
        s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs));
@@ -153,6 +151,8 @@ static void __init vstms_map_io(void)
 static void __init vstms_init(void)
 {
        s3c_i2c0_set_platdata(NULL);
+        s3c_nand_set_platdata(&vstms_nand_info);
        platform_add_devices(vstms_devices, ARRAY_SIZE(vstms_devices));
 }
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
index a8b69d77571b..cf10e14b7b49 100644
--- a/arch/arm/mach-s3c2440/Kconfig
+++ b/arch/arm/mach-s3c2440/Kconfig
@@ -53,6 +53,19 @@ config MACH_OSIRIS
          Say Y here if you are using the Simtec IM2440D20 module, also
          known as the Osiris.
+config MACH_OSIRIS_DVS
+        tristate "Simtec IM2440D20 (OSIRIS) Dynamic Voltage Scaling driver"
+        depends on MACH_OSIRIS
+        select TPS65010
+        help
+          Say Y/M here if you want to have dynamic voltage scaling support
+          on the Simtec IM2440D20 (OSIRIS) module via the TPS65011.
+          The DVS driver alters the voltage supplied to the ARM core
+          depending on the frequency it is running at. The driver itself
+          does not do any of the frequency alteration, which is left up
+          to the cpufreq driver.
 config MACH_RX3715
        bool "HP iPAQ rx3715"
        select CPU_S3C2440
diff --git a/arch/arm/mach-s3c2440/Makefile b/arch/arm/mach-s3c2440/Makefile
index bfadcf684a2a..5f3224531885 100644
--- a/arch/arm/mach-s3c2440/Makefile
+++ b/arch/arm/mach-s3c2440/Makefile
@@ -23,3 +23,7 @@ obj-$(CONFIG_ARCH_S3C2440)	+= mach-smdk2440.o
 obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o
 obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o
 obj-$(CONFIG_MACH_MINI2440) += mach-mini2440.o
+# extra machine support
+obj-$(CONFIG_MACH_OSIRIS_DVS)   += mach-osiris-dvs.o
diff --git a/arch/arm/mach-s3c2440/irq.c b/arch/arm/mach-s3c2440/irq.c
index 63c5ab65727f..0c049b95c378 100644
--- a/arch/arm/mach-s3c2440/irq.c
+++ b/arch/arm/mach-s3c2440/irq.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s3c2440/irq.c
 *
- * Copyright (c) 2003,2004 Simtec Electronics
+ * Copyright (c) 2003-2004 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * This program is free software; you can redistribute it and/or modify
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
index 68f3870991bf..62a4c3eba97f 100644
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s3c2440/mach-anubis.c
 *
- * Copyright (c) 2003-2005,2008 Simtec Electronics
+ * Copyright 2003-2009 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *
@@ -53,8 +53,9 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/audio-simtec.h>
-#define COPYRIGHT ", (c) 2005 Simtec Electronics"
+#define COPYRIGHT ", Copyright 2005-2009 Simtec Electronics"
 static struct map_desc anubis_iodesc[] __initdata = {
  /* ISA IO areas */
@@ -138,7 +139,7 @@ static int external_map[]   = { 2 };
 static int chip0_map[]      = { 0 };
 static int chip1_map[]      = { 1 };
-static struct mtd_partition anubis_default_nand_part[] = {
+static struct mtd_partition __initdata anubis_default_nand_part[] = {
        [0] = {
                .name   = "Boot Agent",
                .size   = SZ_16K,
@@ -161,7 +162,7 @@ static struct mtd_partition anubis_default_nand_part[] = {
        }
 };
-static struct mtd_partition anubis_default_nand_part_large[] = {
+static struct mtd_partition __initdata anubis_default_nand_part_large[] = {
        [0] = {
                .name   = "Boot Agent",
                .size   = SZ_128K,
@@ -191,7 +192,7 @@ static struct mtd_partition anubis_default_nand_part_large[] = {
 * socket.
 */
-static struct s3c2410_nand_set anubis_nand_sets[] = {
+static struct s3c2410_nand_set __initdata anubis_nand_sets[] = {
        [1] = {
                .name           = "External",
                .nr_chips       = 1,
@@ -233,7 +234,7 @@ static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
        __raw_writeb(tmp, ANUBIS_VA_CTRL1);
 }
-static struct s3c2410_platform_nand anubis_nand_info = {
+static struct s3c2410_platform_nand __initdata anubis_nand_info = {
        .tacls          = 25,
        .twrph0         = 55,
        .twrph1         = 40,
@@ -437,6 +438,17 @@ static struct i2c_board_info anubis_i2c_devs[] __initdata = {
        }
 };
+/* Audio setup */
+static struct s3c24xx_audio_simtec_pdata __initdata anubis_audio = {
+        .have_mic       = 1,
+        .have_lout      = 1,
+        .output_cdclk   = 1,
+        .use_mpllin     = 1,
+        .amp_gpio       = S3C2410_GPB(2),
+        .amp_gain[0]    = S3C2410_GPD(10),
+        .amp_gain[1]    = S3C2410_GPD(11),
+};
 static void __init anubis_map_io(void)
 {
        /* initialise the clocks */
@@ -454,8 +466,6 @@ static void __init anubis_map_io(void)
        s3c24xx_register_clocks(anubis_clocks, ARRAY_SIZE(anubis_clocks));
-        s3c_device_nand.dev.platform_data = &anubis_nand_info;
        s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
        s3c24xx_init_clocks(0);
        s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
@@ -476,6 +486,9 @@ static void __init anubis_map_io(void)
 static void __init anubis_init(void)
 {
        s3c_i2c0_set_platdata(NULL);
+        s3c_nand_set_platdata(&anubis_nand_info);
+        simtec_audio_add(NULL, false, &anubis_audio);
        platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
        i2c_register_board_info(0, anubis_i2c_devs,
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c
index dfc7010935da..aa69290e04c6 100644
--- a/arch/arm/mach-s3c2440/mach-at2440evb.c
+++ b/arch/arm/mach-s3c2440/mach-at2440evb.c
@@ -96,7 +96,7 @@ static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = {
 /* NAND Flash on AT2440EVB board */
-static struct mtd_partition at2440evb_default_nand_part[] = {
+static struct mtd_partition __initdata at2440evb_default_nand_part[] = {
        [0] = {
                .name   = "Boot Agent",
                .size   = SZ_256K,
@@ -114,7 +114,7 @@ static struct mtd_partition at2440evb_default_nand_part[] = {
        },
 };
-static struct s3c2410_nand_set at2440evb_nand_sets[] = {
+static struct s3c2410_nand_set __initdata at2440evb_nand_sets[] = {
        [0] = {
                .name           = "nand",
                .nr_chips       = 1,
@@ -123,7 +123,7 @@ static struct s3c2410_nand_set at2440evb_nand_sets[] = {
        },
 };
-static struct s3c2410_platform_nand at2440evb_nand_info = {
+static struct s3c2410_platform_nand __initdata at2440evb_nand_info = {
        .tacls          = 25,
        .twrph0         = 55,
        .twrph1         = 40,
@@ -216,8 +216,6 @@ static struct platform_device *at2440evb_devices[] __initdata = {
 static void __init at2440evb_map_io(void)
 {
-        s3c_device_nand.dev.platform_data = &at2440evb_nand_info;
-        s3c_device_sdi.name = "s3c2440-sdi";
        s3c_device_sdi.dev.platform_data = &at2440evb_mci_pdata;
        s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc));
@@ -228,6 +226,7 @@ static void __init at2440evb_map_io(void)
 static void __init at2440evb_init(void)
 {
        s3c24xx_fb_set_platdata(&at2440evb_fb_info);
+        s3c_nand_set_platdata(&at2440evb_nand_info);
        s3c_i2c0_set_platdata(NULL);
        platform_add_devices(at2440evb_devices, ARRAY_SIZE(at2440evb_devices));
diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c
index 1c3382fefdd2..547d4fc99131 100644
--- a/arch/arm/mach-s3c2440/mach-mini2440.c
+++ b/arch/arm/mach-s3c2440/mach-mini2440.c
@@ -532,7 +532,6 @@ static void __init mini2440_map_io(void)
        s3c24xx_init_clocks(12000000);
        s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs));
-        s3c_device_nand.dev.platform_data = &mini2440_nand_info;
        s3c_device_sdi.dev.platform_data = &mini2440_mmc_cfg;
 }
@@ -677,8 +676,11 @@ static void __init mini2440_init(void)
                printk("\n");
                s3c24xx_fb_set_platdata(&mini2440_fb_info);
        }
        s3c24xx_udc_set_platdata(&mini2440_udc_cfg);
+        s3c_nand_set_platdata(&mini2440_nand_info);
        s3c_i2c0_set_platdata(NULL);
        i2c_register_board_info(0, mini2440_i2c_devs,
                                ARRAY_SIZE(mini2440_i2c_devs));
diff --git a/arch/arm/mach-s3c2440/mach-osiris-dvs.c b/arch/arm/mach-s3c2440/mach-osiris-dvs.c
new file mode 100644
index 000000000000..ad2792dfbee1
--- /dev/null
+++ b/arch/arm/mach-s3c2440/mach-osiris-dvs.c
@@ -0,0 +1,194 @@
+/* linux/arch/arm/mach-s3c2440/mach-osiris-dvs.c
+ *
+ * Copyright (c) 2009 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Simtec Osiris Dynamic Voltage Scaling support.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/cpufreq.h>
+#include <linux/gpio.h>
+#include <linux/i2c/tps65010.h>
+#include <plat/cpu-freq.h>
+#define OSIRIS_GPIO_DVS S3C2410_GPB(5)
+static bool dvs_en;
+static void osiris_dvs_tps_setdvs(bool on)
+{
+        unsigned vregs1 = 0, vdcdc2 = 0;
+        if (!on) {
+                vdcdc2 = TPS_VCORE_DISCH | TPS_LP_COREOFF;
+                vregs1 = TPS_LDO1_OFF;  /* turn off in low-power mode */
+        }
+        dvs_en = on;
+        vdcdc2 |= TPS_VCORE_1_3V | TPS_VCORE_LP_1_0V;
+        vregs1 |= TPS_LDO2_ENABLE | TPS_LDO1_ENABLE;
+        tps65010_config_vregs1(vregs1);
+        tps65010_config_vdcdc2(vdcdc2);
+}
+static bool is_dvs(struct s3c_freq *f)
+{
+        /* at the moment, we assume ARMCLK = HCLK => DVS */
+        return f->armclk == f->hclk;
+}
+/* keep track of current state */
+static bool cur_dvs = false;
+static int osiris_dvs_notify(struct notifier_block *nb,
+                              unsigned long val, void *data)
+{
+        struct cpufreq_freqs *cf = data;
+        struct s3c_cpufreq_freqs *freqs = to_s3c_cpufreq(cf);
+        bool old_dvs = is_dvs(&freqs->old);
+        bool new_dvs = is_dvs(&freqs->new);
+        int ret = 0;
+        if (!dvs_en)
+                return 0;
+        printk(KERN_DEBUG "%s: old %ld,%ld new %ld,%ld\n", __func__,
+               freqs->old.armclk, freqs->old.hclk,
+               freqs->new.armclk, freqs->new.hclk);
+        switch (val) {
+        case CPUFREQ_PRECHANGE:
+                if (old_dvs & !new_dvs ||
+                    cur_dvs & !new_dvs) {
+                        pr_debug("%s: exiting dvs\n", __func__);
+                        cur_dvs = false;
+                        gpio_set_value(OSIRIS_GPIO_DVS, 1);
+                }
+                break;
+        case CPUFREQ_POSTCHANGE:
+                if (!old_dvs & new_dvs ||
+                    !cur_dvs & new_dvs) {
+                        pr_debug("entering dvs\n");
+                        cur_dvs = true;
+                        gpio_set_value(OSIRIS_GPIO_DVS, 0);
+                }
+                break;
+        }
+        return ret;
+}
+static struct notifier_block osiris_dvs_nb = {
+        .notifier_call  = osiris_dvs_notify,
+};
+static int __devinit osiris_dvs_probe(struct platform_device *pdev)
+{
+        int ret;
+        dev_info(&pdev->dev, "initialising\n");
+        ret = gpio_request(OSIRIS_GPIO_DVS, "osiris-dvs");
+        if (ret) {
+                dev_err(&pdev->dev, "cannot claim gpio\n");
+                goto err_nogpio;
+        }
+        /* start with dvs disabled */
+        gpio_direction_output(OSIRIS_GPIO_DVS, 1);
+        ret = cpufreq_register_notifier(&osiris_dvs_nb,
+                                        CPUFREQ_TRANSITION_NOTIFIER);
+        if (ret) {
+                dev_err(&pdev->dev, "failed to register with cpufreq\n");
+                goto err_nofreq;
+        }
+        osiris_dvs_tps_setdvs(true);
+        return 0;
+err_nofreq:
+        gpio_free(OSIRIS_GPIO_DVS);
+err_nogpio:
+        return ret;
+}
+static int __devexit osiris_dvs_remove(struct platform_device *pdev)
+{
+        dev_info(&pdev->dev, "exiting\n");
+        /* disable any current dvs */
+        gpio_set_value(OSIRIS_GPIO_DVS, 1);
+        osiris_dvs_tps_setdvs(false);
+        cpufreq_unregister_notifier(&osiris_dvs_nb,
+                                    CPUFREQ_TRANSITION_NOTIFIER);
+        gpio_free(OSIRIS_GPIO_DVS);
+        return 0;
+}
+/* the CONFIG_PM block is so small, it isn't worth actaully compiling it
+ * out if the configuration isn't set. */
+static int osiris_dvs_suspend(struct device *dev)
+{
+        gpio_set_value(OSIRIS_GPIO_DVS, 1);
+        osiris_dvs_tps_setdvs(false);
+        cur_dvs = false;
+        return 0;
+}
+static int osiris_dvs_resume(struct device *dev)
+{
+        osiris_dvs_tps_setdvs(true);
+        return 0;
+}
+static const struct dev_pm_ops osiris_dvs_pm = {
+        .suspend        = osiris_dvs_suspend,
+        .resume         = osiris_dvs_resume,
+};
+static struct platform_driver osiris_dvs_driver = {
+        .probe          = osiris_dvs_probe,
+        .remove         = __devexit_p(osiris_dvs_remove),
+        .driver         = {
+                .name   = "osiris-dvs",
+                .owner  = THIS_MODULE,
+                .pm     = &osiris_dvs_pm,
+        },
+};
+static int __init osiris_dvs_init(void)
+{
+        return platform_driver_register(&osiris_dvs_driver);
+}
+static void __exit osiris_dvs_exit(void)
+{
+        platform_driver_unregister(&osiris_dvs_driver);
+}
+module_init(osiris_dvs_init);
+module_exit(osiris_dvs_exit);
+MODULE_DESCRIPTION("Simtec OSIRIS DVS support");
+MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:osiris-dvs");
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index 2105a41281a4..015dfb2a80da 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s3c2440/mach-osiris.c
 *
- * Copyright (c) 2005,2008 Simtec Electronics
+ * Copyright (c) 2005-2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *
@@ -23,6 +23,8 @@
 #include <linux/i2c.h>
 #include <linux/io.h>
+#include <linux/i2c/tps65010.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
@@ -148,7 +150,7 @@ static int external_map[]   = { 2 };
 static int chip0_map[]      = { 0 };
 static int chip1_map[]      = { 1 };
-static struct mtd_partition osiris_default_nand_part[] = {
+static struct mtd_partition __initdata osiris_default_nand_part[] = {
        [0] = {
                .name   = "Boot Agent",
                .size   = SZ_16K,
@@ -171,7 +173,7 @@ static struct mtd_partition osiris_default_nand_part[] = {
        }
 };
-static struct mtd_partition osiris_default_nand_part_large[] = {
+static struct mtd_partition __initdata osiris_default_nand_part_large[] = {
        [0] = {
                .name   = "Boot Agent",
                .size   = SZ_128K,
@@ -201,7 +203,7 @@ static struct mtd_partition osiris_default_nand_part_large[] = {
 * socket.
 */
-static struct s3c2410_nand_set osiris_nand_sets[] = {
+static struct s3c2410_nand_set __initdata osiris_nand_sets[] = {
        [1] = {
                .name           = "External",
                .nr_chips       = 1,
@@ -243,7 +245,7 @@ static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
        __raw_writeb(tmp, OSIRIS_VA_CTRL0);
 }
-static struct s3c2410_platform_nand osiris_nand_info = {
+static struct s3c2410_platform_nand __initdata osiris_nand_info = {
        .tacls          = 25,
        .twrph0         = 60,
        .twrph1         = 60,
@@ -326,12 +328,44 @@ static struct sys_device osiris_pm_sysdev = {
        .cls            = &osiris_pm_sysclass,
 };
+/* Link for DVS driver to TPS65011 */
+static void osiris_tps_release(struct device *dev)
+{
+        /* static device, do not need to release anything */
+}
+static struct platform_device osiris_tps_device = {
+        .name   = "osiris-dvs",
+        .id     = -1,
+        .dev.release = osiris_tps_release,
+};
+static int osiris_tps_setup(struct i2c_client *client, void *context)
+{
+        osiris_tps_device.dev.parent = &client->dev;
+        return platform_device_register(&osiris_tps_device);
+}
+static int osiris_tps_remove(struct i2c_client *client, void *context)
+{
+        platform_device_unregister(&osiris_tps_device);
+        return 0;
+}
+static struct tps65010_board osiris_tps_board = {
+        .base           = -1,   /* GPIO can go anywhere at the moment */
+        .setup          = osiris_tps_setup,
+        .teardown       = osiris_tps_remove,
+};
 /* I2C devices fitted. */
 static struct i2c_board_info osiris_i2c_devs[] __initdata = {
        {
                I2C_BOARD_INFO("tps65011", 0x48),
                .irq    = IRQ_EINT20,
+                .platform_data = &osiris_tps_board,
        },
 };
@@ -377,8 +411,6 @@ static void __init osiris_map_io(void)
        s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));
-        s3c_device_nand.dev.platform_data = &osiris_nand_info;
        s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
        s3c24xx_init_clocks(0);
        s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
@@ -408,6 +440,7 @@ static void __init osiris_init(void)
        sysdev_register(&osiris_pm_sysdev);
        s3c_i2c0_set_platdata(NULL);
+        s3c_nand_set_platdata(&osiris_nand_info);
        s3c_cpufreq_setboard(&osiris_cpufreq);
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
index bc8d8d1ebd1a..a952a13afb1f 100644
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s3c2440/mach-rx3715.c
 *
- * Copyright (c) 2003,2004 Simtec Electronics
+ * Copyright (c) 2003-2004 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * http://www.handhelds.org/projects/rx3715.html
@@ -149,7 +149,7 @@ static struct s3c2410fb_mach_info rx3715_fb_info __initdata = {
        .gpdup_mask =   0xffffffff,
 };
-static struct mtd_partition rx3715_nand_part[] = {
+static struct mtd_partition __initdata rx3715_nand_part[] = {
        [0] = {
                .name           = "Whole Flash",
                .offset         = 0,
@@ -158,7 +158,7 @@ static struct mtd_partition rx3715_nand_part[] = {
        }
 };
-static struct s3c2410_nand_set rx3715_nand_sets[] = {
+static struct s3c2410_nand_set __initdata rx3715_nand_sets[] = {
        [0] = {
                .name           = "Internal",
                .nr_chips       = 1,
@@ -167,7 +167,7 @@ static struct s3c2410_nand_set rx3715_nand_sets[] = {
        },
 };
-static struct s3c2410_platform_nand rx3715_nand_info = {
+static struct s3c2410_platform_nand __initdata rx3715_nand_info = {
        .tacls          = 25,
        .twrph0         = 50,
        .twrph1         = 15,
@@ -186,8 +186,6 @@ static struct platform_device *rx3715_devices[] __initdata = {
 static void __init rx3715_map_io(void)
 {
-        s3c_device_nand.dev.platform_data = &rx3715_nand_info;
        s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc));
        s3c24xx_init_clocks(16934000);
        s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
@@ -205,6 +203,7 @@ static void __init rx3715_init_machine(void)
 #endif
        s3c_pm_init();
+        s3c_nand_set_platdata(&rx3715_nand_info);
        s3c24xx_fb_set_platdata(&rx3715_fb_info);
        platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices));
 }
diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c
index db6eafbd4d90..ec13e748ccc5 100644
--- a/arch/arm/mach-s3c2440/mach-smdk2440.c
+++ b/arch/arm/mach-s3c2440/mach-smdk2440.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s3c2440/mach-smdk2440.c
 *
- * Copyright (c) 2004,2005 Simtec Electronics
+ * Copyright (c) 2004-2005 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * http://www.fluff.org/ben/smdk2440/
diff --git a/arch/arm/mach-s3c2442/mach-gta02.c b/arch/arm/mach-s3c2442/mach-gta02.c
index 0fb385bd9cd9..f76d6ff4aeb9 100644
--- a/arch/arm/mach-s3c2442/mach-gta02.c
+++ b/arch/arm/mach-s3c2442/mach-gta02.c
@@ -423,7 +423,7 @@ static struct i2c_board_info gta02_i2c_devs[] __initdata = {
        },
 };
-static struct s3c2410_nand_set gta02_nand_sets[] = {
+static struct s3c2410_nand_set __initdata gta02_nand_sets[] = {
        [0] = {
                /*
                 * This name is also hard-coded in the boot loaders, so
@@ -442,7 +442,7 @@ static struct s3c2410_nand_set gta02_nand_sets[] = {
 * data sheet (K5D2G13ACM-D075 MCP Memory).
 */
-static struct s3c2410_platform_nand gta02_nand_info = {
+static struct s3c2410_platform_nand __initdata gta02_nand_info = {
        .tacls          = 0,
        .twrph0         = 25,
        .twrph1         = 15,
@@ -621,9 +621,9 @@ static void __init gta02_machine_init(void)
 #endif
        s3c_device_usb.dev.platform_data = &gta02_usb_info;
-        s3c_device_nand.dev.platform_data = &gta02_nand_info;
        s3c24xx_udc_set_platdata(&gta02_udc_cfg);
+        s3c_nand_set_platdata(&gta02_nand_info);
        s3c_i2c0_set_platdata(NULL);
        i2c_register_board_info(0, gta02_i2c_devs, ARRAY_SIZE(gta02_i2c_devs));
diff --git a/arch/arm/mach-s3c24a0/include/mach/map.h b/arch/arm/mach-s3c24a0/include/mach/map.h
index 79e4d93ea2b6..d88c8b24fe34 100644
--- a/arch/arm/mach-s3c24a0/include/mach/map.h
+++ b/arch/arm/mach-s3c24a0/include/mach/map.h
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s3c24a0/include/mach/map.h
 *
- * Copyright 2003,2007  Simtec Electronics
+ * Copyright 2003-2007  Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *
diff --git a/arch/arm/mach-s3c24a0/include/mach/regs-clock.h b/arch/arm/mach-s3c24a0/include/mach/regs-clock.h
index af2abd756c30..be0af518b488 100644
--- a/arch/arm/mach-s3c24a0/include/mach/regs-clock.h
+++ b/arch/arm/mach-s3c24a0/include/mach/regs-clock.h
@@ -1,7 +1,7 @@
 /* linux/arch/arm/mach-s3c24a0/include/mach/regs-clock.h
 *
- * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk>
+ * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
- *                    http://armlinux.simtec.co.uk/
+ *      http://armlinux.simtec.co.uk/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s3c6400/include/mach/map.h b/arch/arm/mach-s3c6400/include/mach/map.h
index 866be31872a5..106ee13581e2 100644
--- a/arch/arm/mach-s3c6400/include/mach/map.h
+++ b/arch/arm/mach-s3c6400/include/mach/map.h
@@ -66,6 +66,9 @@
 #define S3C64XX_PA_USBHOST      (0x74300000)
+#define S3C64XX_PA_USB_HSPHY    (0x7C100000)
+#define S3C64XX_VA_USB_HSPHY    S3C_ADDR_CPU(0x00200000)
 /* place VICs close together */
 #define S3C_VA_VIC0             (S3C_VA_IRQ + 0x00)
 #define S3C_VA_VIC1             (S3C_VA_IRQ + 0x10000)
@@ -81,5 +84,6 @@
 #define S3C_PA_FB               S3C64XX_PA_FB
 #define S3C_PA_USBHOST          S3C64XX_PA_USBHOST
 #define S3C_PA_USB_HSOTG        S3C64XX_PA_USB_HSOTG
+#define S3C_VA_USB_HSPHY        S3C64XX_VA_USB_HSPHY
 #endif /* __ASM_ARCH_6400_MAP_H */
diff --git a/arch/arm/mach-s3c6400/include/mach/regs-fb.h b/arch/arm/mach-s3c6400/include/mach/regs-fb.h
index 47019795ce06..f56611526c63 100644
--- a/arch/arm/mach-s3c6400/include/mach/regs-fb.h
+++ b/arch/arm/mach-s3c6400/include/mach/regs-fb.h
@@ -1,195 +1,30 @@
-/* arch/arm/mach-s3c6400/include/mach/regs-fb.h
+/*
- *
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
+ * Copyright 2009 Samsung Electronics Co.
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C64XX - new-style framebuffer register definitions
 *
- * This is the register set for the new style framebuffer interface
+ * Pawel Osciak <p.osciak@samsung.com>
- * found from the S3C2443 onwards and specifically the S3C64XX series
+ * Based on plat-s3c/include/plat/regs-fb.h by Ben Dooks <ben@simtec.co.uk>
- * S3C6400 and S3C6410.
 *
- * The file contains the cpu specific items which change between whichever
+ * Framebuffer register definitions for Samsung S3C64xx.
- * architecture is selected. See <plat/regs-fb.h> for the core definitions
- * that are the same.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-/* include the core definitions here, in case we really do need to
+#ifndef __ASM_ARCH_MACH_REGS_FB_H
- * override them at a later date.
+#define __ASM_ARCH_MACH_REGS_FB_H __FILE__
-*/
-#include <plat/regs-fb.h>
-#define S3C_FB_MAX_WIN (5)  /* number of hardware windows available. */
-#define VIDCON1_FSTATUS_EVEN    (1 << 15)
-/* Video timing controls */
-#define VIDTCON0                                (0x10)
-#define VIDTCON1                                (0x14)
-#define VIDTCON2                                (0x18)
-/* Window position controls */
-#define WINCON(_win)                            (0x20 + ((_win) * 4))
-/* OSD1 and OSD4 do not have register D */
-#define VIDOSD_A(_win)                          (0x40 + ((_win) * 16))
-#define VIDOSD_B(_win)                          (0x44 + ((_win) * 16))
-#define VIDOSD_C(_win)                          (0x48 + ((_win) * 16))
-#define VIDOSD_D(_win)                          (0x4C + ((_win) * 16))
-/* Video buffer addresses */
-#define VIDW_BUF_START(_buff)                   (0xA0 + ((_buff) * 8))
-#define VIDW_BUF_START1(_buff)                  (0xA4 + ((_buff) * 8))
-#define VIDW_BUF_END(_buff)                     (0xD0 + ((_buff) * 8))
-#define VIDW_BUF_END1(_buff)                    (0xD4 + ((_buff) * 8))
-#define VIDW_BUF_SIZE(_buff)                    (0x100 + ((_buff) * 4))
-#define VIDINTCON0                              (0x130)
-#define WxKEYCONy(_win, _con)                   ((0x140 + ((_win) * 8)) + ((_con) * 4))
-/* WINCONx */
-#define WINCONx_CSCWIDTH_MASK                   (0x3 << 26)
-#define WINCONx_CSCWIDTH_SHIFT                  (26)
-#define WINCONx_CSCWIDTH_WIDE                   (0x0 << 26)
-#define WINCONx_CSCWIDTH_NARROW                 (0x3 << 26)
-#define WINCONx_ENLOCAL                         (1 << 22)
-#define WINCONx_BUFSTATUS                       (1 << 21)
-#define WINCONx_BUFSEL                          (1 << 20)
-#define WINCONx_BUFAUTOEN                       (1 << 19)
-#define WINCONx_YCbCr                           (1 << 13)
-#define WINCON1_LOCALSEL_CAMIF                  (1 << 23)
-#define WINCON2_LOCALSEL_CAMIF                  (1 << 23)
-#define WINCON2_BLD_PIX                         (1 << 6)
-#define WINCON2_ALPHA_SEL                       (1 << 1)
-#define WINCON2_BPPMODE_MASK                    (0xf << 2)
-#define WINCON2_BPPMODE_SHIFT                   (2)
-#define WINCON2_BPPMODE_1BPP                    (0x0 << 2)
-#define WINCON2_BPPMODE_2BPP                    (0x1 << 2)
-#define WINCON2_BPPMODE_4BPP                    (0x2 << 2)
-#define WINCON2_BPPMODE_8BPP_1232               (0x4 << 2)
-#define WINCON2_BPPMODE_16BPP_565               (0x5 << 2)
-#define WINCON2_BPPMODE_16BPP_A1555             (0x6 << 2)
-#define WINCON2_BPPMODE_16BPP_I1555             (0x7 << 2)
-#define WINCON2_BPPMODE_18BPP_666               (0x8 << 2)
-#define WINCON2_BPPMODE_18BPP_A1665             (0x9 << 2)
-#define WINCON2_BPPMODE_19BPP_A1666             (0xa << 2)
-#define WINCON2_BPPMODE_24BPP_888               (0xb << 2)
-#define WINCON2_BPPMODE_24BPP_A1887             (0xc << 2)
-#define WINCON2_BPPMODE_25BPP_A1888             (0xd << 2)
-#define WINCON2_BPPMODE_28BPP_A4888             (0xd << 2)
-#define WINCON3_BLD_PIX                         (1 << 6)
-#define WINCON3_ALPHA_SEL                       (1 << 1)
-#define WINCON3_BPPMODE_MASK                    (0xf << 2)
-#define WINCON3_BPPMODE_SHIFT                   (2)
-#define WINCON3_BPPMODE_1BPP                    (0x0 << 2)
-#define WINCON3_BPPMODE_2BPP                    (0x1 << 2)
-#define WINCON3_BPPMODE_4BPP                    (0x2 << 2)
-#define WINCON3_BPPMODE_16BPP_565               (0x5 << 2)
-#define WINCON3_BPPMODE_16BPP_A1555             (0x6 << 2)
-#define WINCON3_BPPMODE_16BPP_I1555             (0x7 << 2)
-#define WINCON3_BPPMODE_18BPP_666               (0x8 << 2)
-#define WINCON3_BPPMODE_18BPP_A1665             (0x9 << 2)
-#define WINCON3_BPPMODE_19BPP_A1666             (0xa << 2)
-#define WINCON3_BPPMODE_24BPP_888               (0xb << 2)
-#define WINCON3_BPPMODE_24BPP_A1887             (0xc << 2)
-#define WINCON3_BPPMODE_25BPP_A1888             (0xd << 2)
-#define WINCON3_BPPMODE_28BPP_A4888             (0xd << 2)
-#define VIDINTCON0_FIFIOSEL_WINDOW2             (0x10 << 5)
-#define VIDINTCON0_FIFIOSEL_WINDOW3             (0x20 << 5)
-#define VIDINTCON0_FIFIOSEL_WINDOW4             (0x40 << 5)
-#define DITHMODE                                (0x170)
-#define WINxMAP(_win)                           (0x180 + ((_win) * 4))
-#define DITHMODE_R_POS_MASK                     (0x3 << 5)
-#define DITHMODE_R_POS_SHIFT                    (5)
-#define DITHMODE_R_POS_8BIT                     (0x0 << 5)
-#define DITHMODE_R_POS_6BIT                     (0x1 << 5)
-#define DITHMODE_R_POS_5BIT                     (0x2 << 5)
-#define DITHMODE_G_POS_MASK                     (0x3 << 3)
-#define DITHMODE_G_POS_SHIFT                    (3)
-#define DITHMODE_G_POS_8BIT                     (0x0 << 3)
-#define DITHMODE_G_POS_6BIT                     (0x1 << 3)
-#define DITHMODE_G_POS_5BIT                     (0x2 << 3)
-#define DITHMODE_B_POS_MASK                     (0x3 << 1)
-#define DITHMODE_B_POS_SHIFT                    (1)
-#define DITHMODE_B_POS_8BIT                     (0x0 << 1)
-#define DITHMODE_B_POS_6BIT                     (0x1 << 1)
-#define DITHMODE_B_POS_5BIT                     (0x2 << 1)
-#define DITHMODE_DITH_EN                        (1 << 0)
+#include <plat/regs-fb-v4.h>
-#define WPALCON                                 (0x1A0)
-#define WPALCON_W4PAL_16BPP_A555                (1 << 8)
-#define WPALCON_W3PAL_16BPP_A555                (1 << 7)
-#define WPALCON_W2PAL_16BPP_A555                (1 << 6)
 /* Palette registers */
 #define WIN2_PAL(_entry)                        (0x300 + ((_entry) * 2))
 #define WIN3_PAL(_entry)                        (0x320 + ((_entry) * 2))
 #define WIN4_PAL(_entry)                        (0x340 + ((_entry) * 2))
 #define WIN0_PAL(_entry)                        (0x400 + ((_entry) * 4))
 #define WIN1_PAL(_entry)                        (0x800 + ((_entry) * 4))
-/* system specific implementation code for palette sizes, and other
- * information that changes depending on which architecture is being
- * compiled.
-*/
-/* return true if window _win has OSD register D */
-#define s3c_fb_has_osd_d(_win) ((_win) != 4 && (_win) != 0)
-static inline unsigned int s3c_fb_win_pal_size(unsigned int win)
-{
-        if (win < 2)
-                return 256;
-        if (win < 4)
-                return 16;
-        if (win == 4)
-                return 4;
-        BUG();  /* shouldn't get here */
-}
-static inline int s3c_fb_validate_win_bpp(unsigned int win, unsigned int bpp)
-{
-        /* all windows can do 1/2 bpp */
-        if ((bpp == 25 || bpp == 19) && win == 0)
-                return 0;       /* win 0 does not have 19 or 25bpp modes */
-        if (bpp == 4 && win == 4)
-                return 0;
-        if (bpp == 8 && (win >= 3))
-                return 0;       /* win 3/4 cannot do 8bpp in any mode */
-        return 1;
-}
 static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
 {
        switch (window) {
@@ -203,57 +38,4 @@ static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
        BUG();
 }
-static inline int s3c_fb_pal_is16(unsigned int window)
+#endif /* __ASM_ARCH_MACH_REGS_FB_H */
-{
-        return window > 1;
-}
-struct s3c_fb_palette {
-        struct fb_bitfield      r;
-        struct fb_bitfield      g;
-        struct fb_bitfield      b;
-        struct fb_bitfield      a;
-};
-static inline void s3c_fb_init_palette(unsigned int window,
-                                       struct s3c_fb_palette *palette)
-{
-        if (window < 2) {
-                /* Windows 0/1 are 8/8/8 or A/8/8/8 */
-                palette->r.offset = 16;
-                palette->r.length = 8;
-                palette->g.offset = 8;
-                palette->g.length = 8;
-                palette->b.offset = 0;
-                palette->b.length = 8;
-        } else {
-                /* currently we assume RGB 5/6/5 */
-                palette->r.offset = 11;
-                palette->r.length = 5;
-                palette->g.offset = 5;
-                palette->g.length = 6;
-                palette->b.offset = 0;
-                palette->b.length = 5;
-        }
-}
-/* Notes on per-window bpp settings
- *
- * Value        Win0     Win1     Win2     Win3     Win 4
- * 0000         1(P)     1(P)     1(P)     1(P)     1(P)
- * 0001         2(P)     2(P)     2(P)     2(P)     2(P)
- * 0010         4(P)     4(P)     4(P)     4(P)     -none-
- * 0011         8(P)     8(P)     -none-   -none-   -none-
- * 0100         -none-   8(A232)  8(A232)  -none-   -none-
- * 0101         16(565)  16(565)  16(565)  16(565)   16(565)
- * 0110         -none-   16(A555) 16(A555) 16(A555)  16(A555)
- * 0111         16(I555) 16(I565) 16(I555) 16(I555)  16(I555)
- * 1000         18(666)  18(666)  18(666)  18(666)   18(666)
- * 1001         -none-   18(A665) 18(A665) 18(A665)  16(A665)
- * 1010         -none-   19(A666) 19(A666) 19(A666)  19(A666)
- * 1011         24(888)  24(888)  24(888)  24(888)   24(888)
- * 1100         -none-   24(A887) 24(A887) 24(A887)  24(A887)
- * 1101         -none-   25(A888) 25(A888) 25(A888)  25(A888)
- * 1110         -none-   -none-   -none-   -none-    -none-
- * 1111         -none-   -none-   -none-   -none-    -none-
-*/
diff --git a/arch/arm/mach-s3c6400/s3c6400.c b/arch/arm/mach-s3c6400/s3c6400.c
index b42bdd0f2138..d876ee503671 100644
--- a/arch/arm/mach-s3c6400/s3c6400.c
+++ b/arch/arm/mach-s3c6400/s3c6400.c
@@ -45,6 +45,7 @@ void __init s3c6400_map_io(void)
        s3c6400_default_sdhci0();
        s3c6400_default_sdhci1();
+        s3c6400_default_sdhci2();
        /* the i2c devices are directly compatible with s3c2440 */
        s3c_i2c0_setname("s3c2440-i2c");
diff --git a/arch/arm/mach-s3c6410/cpu.c b/arch/arm/mach-s3c6410/cpu.c
index 9b67c663d9d8..522c08691952 100644
--- a/arch/arm/mach-s3c6410/cpu.c
+++ b/arch/arm/mach-s3c6410/cpu.c
@@ -58,6 +58,7 @@ void __init s3c6410_map_io(void)
        /* initialise device information early */
        s3c6410_default_sdhci0();
        s3c6410_default_sdhci1();
+        s3c6410_default_sdhci2();
        /* the i2c devices are directly compatible with s3c2440 */
        s3c_i2c0_setname("s3c2440-i2c");
diff --git a/arch/arm/mach-s3c6410/mach-hmt.c b/arch/arm/mach-s3c6410/mach-hmt.c
index c5741056193f..cdd4b5378552 100644
--- a/arch/arm/mach-s3c6410/mach-hmt.c
+++ b/arch/arm/mach-s3c6410/mach-hmt.c
@@ -250,7 +250,7 @@ static void __init hmt_machine_init(void)
 {
        s3c_i2c0_set_platdata(NULL);
        s3c_fb_set_platdata(&hmt_lcd_pdata);
-        s3c_device_nand.dev.platform_data = &hmt_nand_info;
+        s3c_nand_set_platdata(&hmt_nand_info);
        gpio_request(S3C64XX_GPC(7), "usb power");
        gpio_direction_output(S3C64XX_GPC(7), 0);
diff --git a/arch/arm/mach-s3c6410/mach-smdk6410.c b/arch/arm/mach-s3c6410/mach-smdk6410.c
index 9f1a21462620..480d297c1de2 100644
--- a/arch/arm/mach-s3c6410/mach-smdk6410.c
+++ b/arch/arm/mach-s3c6410/mach-smdk6410.c
@@ -25,6 +25,7 @@
 #include <linux/gpio.h>
 #include <linux/delay.h>
 #include <linux/smsc911x.h>
+#include <linux/regulator/fixed.h>
 #ifdef CONFIG_SMDK6410_WM1190_EV1
 #include <linux/mfd/wm8350/core.h>
@@ -184,6 +185,43 @@ static struct platform_device smdk6410_smsc911x = {
        },
 };
+#ifdef CONFIG_REGULATOR
+static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] = {
+        {
+                /* WM8580 */
+                .supply = "PVDD",
+                .dev_name = "0-001b",
+        },
+        {
+                /* WM8580 */
+                .supply = "AVDD",
+                .dev_name = "0-001b",
+        },
+};
+static struct regulator_init_data smdk6410_b_pwr_5v_data = {
+        .constraints = {
+                .always_on = 1,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(smdk6410_b_pwr_5v_consumers),
+        .consumer_supplies = smdk6410_b_pwr_5v_consumers,
+};
+static struct fixed_voltage_config smdk6410_b_pwr_5v_pdata = {
+        .supply_name = "B_PWR_5V",
+        .microvolts = 5000000,
+        .init_data = &smdk6410_b_pwr_5v_data,
+};
+static struct platform_device smdk6410_b_pwr_5v = {
+        .name          = "reg-fixed-voltage",
+        .id            = -1,
+        .dev = {
+                .platform_data = &smdk6410_b_pwr_5v_pdata,
+        },
+};
+#endif
 static struct map_desc smdk6410_iodesc[] = {};
 static struct platform_device *smdk6410_devices[] __initdata = {
@@ -198,6 +236,10 @@ static struct platform_device *smdk6410_devices[] __initdata = {
        &s3c_device_fb,
        &s3c_device_usb,
        &s3c_device_usb_hsotg,
+#ifdef CONFIG_REGULATOR
+        &smdk6410_b_pwr_5v,
+#endif
        &smdk6410_lcd_powerdev,
        &smdk6410_smsc911x,
@@ -232,6 +274,14 @@ static struct regulator_init_data wm8350_dcdc3_data = {
 };
 /* USB, EXT, PCM, ADC/DAC, USB, MMC */
+static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = {
+        {
+                /* WM8580 */
+                .supply = "DVDD",
+                .dev_name = "0-001b",
+        },
+};
 static struct regulator_init_data wm8350_dcdc4_data = {
        .constraints = {
                .name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV",
@@ -239,6 +289,8 @@ static struct regulator_init_data wm8350_dcdc4_data = {
                .max_uV = 3000000,
                .always_on = 1,
        },
+        .num_consumer_supplies = ARRAY_SIZE(wm8350_dcdc4_consumers),
+        .consumer_supplies = wm8350_dcdc4_consumers,
 };
 /* ARM core */
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index b1a4ba504416..0dd2b8c6eabe 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -14,9 +14,23 @@ config CPU_S5PC100
        help
          Enable S5PC100 CPU support
+config S5PC100_SETUP_SDHCI
+        bool
+        select S5PC1XX_SETUP_SDHCI_GPIO
+        help
+          Internal helper functions for S5PC100 based SDHCI systems
 config MACH_SMDKC100
        bool "SMDKC100"
        select CPU_S5PC100
+        select S3C_DEV_FB
+        select S3C_DEV_I2C1
+        select S3C_DEV_HSMMC
+        select S3C_DEV_HSMMC1
+        select S3C_DEV_HSMMC2
+        select S5PC1XX_SETUP_I2C0
        select S5PC1XX_SETUP_I2C1
+        select S5PC1XX_SETUP_FB_24BPP
+        select S5PC100_SETUP_SDHCI
        help
          Machine support for the Samsung SMDKC100
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
index afc89b381d7a..809ff10f768f 100644
--- a/arch/arm/mach-s5pc100/Makefile
+++ b/arch/arm/mach-s5pc100/Makefile
@@ -13,5 +13,9 @@ obj-				:=
 obj-$(CONFIG_CPU_S5PC100)       += cpu.o
+# Helper and device support
+obj-$(CONFIG_S5PC100_SETUP_SDHCI)       += setup-sdhci.o
 # machine support
 obj-$(CONFIG_MACH_SMDKC100)     += mach-smdkc100.o
diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c
index 0e718890da32..d79e7574a852 100644
--- a/arch/arm/mach-s5pc100/cpu.c
+++ b/arch/arm/mach-s5pc100/cpu.c
@@ -22,6 +22,8 @@
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <asm/proc-fns.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
@@ -32,6 +34,7 @@
 #include <plat/cpu-freq.h>
 #include <plat/regs-serial.h>
+#include <plat/regs-power.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
@@ -45,6 +48,23 @@
 static struct map_desc s5pc100_iodesc[] __initdata = {
 };
+static void s5pc100_idle(void)
+{
+        unsigned long tmp;
+        tmp = __raw_readl(S5PC100_PWR_CFG);
+        tmp &= ~S5PC100_PWRCFG_CFG_DEEP_IDLE;
+        tmp &= ~S5PC100_PWRCFG_CFG_WFI_MASK;
+        tmp |= S5PC100_PWRCFG_CFG_WFI_DEEP_IDLE;
+        __raw_writel(tmp, S5PC100_PWR_CFG);
+        tmp = __raw_readl(S5PC100_OTHERS);
+        tmp |= S5PC100_PMU_INT_DISABLE;
+        __raw_writel(tmp, S5PC100_OTHERS);
+        cpu_do_idle();
+}
 /* s5pc100_map_io
 *
 * register the standard cpu IO areas
@@ -55,6 +75,13 @@ void __init s5pc100_map_io(void)
        iotable_init(s5pc100_iodesc, ARRAY_SIZE(s5pc100_iodesc));
        /* initialise device information early */
+        s5pc100_default_sdhci0();
+        s5pc100_default_sdhci1();
+        s5pc100_default_sdhci2();
+        /* the i2c devices are directly compatible with s3c2440 */
+        s3c_i2c0_setname("s3c2440-i2c");
+        s3c_i2c1_setname("s3c2440-i2c");
 }
 void __init s5pc100_init_clocks(int xtal)
@@ -93,5 +120,7 @@ int __init s5pc100_init(void)
 {
        printk(KERN_DEBUG "S5PC100: Initialising architecture\n");
+        s5pc1xx_idle = s5pc100_idle;
        return sysdev_register(&s5pc100_sysdev);
 }
diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h
index c74fc93d7d15..2c4cbe8ee6b7 100644
--- a/arch/arm/mach-s5pc100/include/mach/gpio.h
+++ b/arch/arm/mach-s5pc100/include/mach/gpio.h
@@ -18,40 +18,45 @@
 #define gpio_to_irq     __gpio_to_irq
 /* GPIO bank sizes */
-#define S5PC1XX_GPIO_A0_NR      (8)
+#define S5PC100_GPIO_A0_NR      (8)
-#define S5PC1XX_GPIO_A1_NR      (5)
+#define S5PC100_GPIO_A1_NR      (5)
-#define S5PC1XX_GPIO_B_NR       (8)
+#define S5PC100_GPIO_B_NR       (8)
-#define S5PC1XX_GPIO_C_NR       (5)
+#define S5PC100_GPIO_C_NR       (5)
-#define S5PC1XX_GPIO_D_NR       (7)
+#define S5PC100_GPIO_D_NR       (7)
-#define S5PC1XX_GPIO_E0_NR      (8)
+#define S5PC100_GPIO_E0_NR      (8)
-#define S5PC1XX_GPIO_E1_NR      (6)
+#define S5PC100_GPIO_E1_NR      (6)
-#define S5PC1XX_GPIO_F0_NR      (8)
+#define S5PC100_GPIO_F0_NR      (8)
-#define S5PC1XX_GPIO_F1_NR      (8)
+#define S5PC100_GPIO_F1_NR      (8)
-#define S5PC1XX_GPIO_F2_NR      (8)
+#define S5PC100_GPIO_F2_NR      (8)
-#define S5PC1XX_GPIO_F3_NR      (4)
+#define S5PC100_GPIO_F3_NR      (4)
-#define S5PC1XX_GPIO_G0_NR      (8)
+#define S5PC100_GPIO_G0_NR      (8)
-#define S5PC1XX_GPIO_G1_NR      (3)
+#define S5PC100_GPIO_G1_NR      (3)
-#define S5PC1XX_GPIO_G2_NR      (7)
+#define S5PC100_GPIO_G2_NR      (7)
-#define S5PC1XX_GPIO_G3_NR      (7)
+#define S5PC100_GPIO_G3_NR      (7)
-#define S5PC1XX_GPIO_H0_NR      (8)
+#define S5PC100_GPIO_H0_NR      (8)
-#define S5PC1XX_GPIO_H1_NR      (8)
+#define S5PC100_GPIO_H1_NR      (8)
-#define S5PC1XX_GPIO_H2_NR      (8)
+#define S5PC100_GPIO_H2_NR      (8)
-#define S5PC1XX_GPIO_H3_NR      (8)
+#define S5PC100_GPIO_H3_NR      (8)
-#define S5PC1XX_GPIO_I_NR       (8)
+#define S5PC100_GPIO_I_NR       (8)
-#define S5PC1XX_GPIO_J0_NR      (8)
+#define S5PC100_GPIO_J0_NR      (8)
-#define S5PC1XX_GPIO_J1_NR      (5)
+#define S5PC100_GPIO_J1_NR      (5)
-#define S5PC1XX_GPIO_J2_NR      (8)
+#define S5PC100_GPIO_J2_NR      (8)
-#define S5PC1XX_GPIO_J3_NR      (8)
+#define S5PC100_GPIO_J3_NR      (8)
-#define S5PC1XX_GPIO_J4_NR      (4)
+#define S5PC100_GPIO_J4_NR      (4)
-#define S5PC1XX_GPIO_K0_NR      (8)
+#define S5PC100_GPIO_K0_NR      (8)
-#define S5PC1XX_GPIO_K1_NR      (6)
+#define S5PC100_GPIO_K1_NR      (6)
-#define S5PC1XX_GPIO_K2_NR      (8)
+#define S5PC100_GPIO_K2_NR      (8)
-#define S5PC1XX_GPIO_K3_NR      (8)
+#define S5PC100_GPIO_K3_NR      (8)
-#define S5PC1XX_GPIO_MP00_NR    (8)
+#define S5PC100_GPIO_L0_NR      (8)
-#define S5PC1XX_GPIO_MP01_NR    (8)
+#define S5PC100_GPIO_L1_NR      (8)
-#define S5PC1XX_GPIO_MP02_NR    (8)
+#define S5PC100_GPIO_L2_NR      (8)
-#define S5PC1XX_GPIO_MP03_NR    (8)
+#define S5PC100_GPIO_L3_NR      (8)
-#define S5PC1XX_GPIO_MP04_NR    (5)
+#define S5PC100_GPIO_L4_NR      (8)
+#define S5PC100_GPIO_MP00_NR    (8)
+#define S5PC100_GPIO_MP01_NR    (8)
+#define S5PC100_GPIO_MP02_NR    (8)
+#define S5PC100_GPIO_MP03_NR    (8)
+#define S5PC100_GPIO_MP04_NR    (5)
 /* GPIO bank numbes */
@@ -64,83 +69,94 @@
        ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
 enum s3c_gpio_number {
-        S5PC1XX_GPIO_A0_START   = 0,
+        S5PC100_GPIO_A0_START   = 0,
-        S5PC1XX_GPIO_A1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_A0),
+        S5PC100_GPIO_A1_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_A0),
-        S5PC1XX_GPIO_B_START    = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_A1),
+        S5PC100_GPIO_B_START    = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_A1),
-        S5PC1XX_GPIO_C_START    = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_B),
+        S5PC100_GPIO_C_START    = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_B),
-        S5PC1XX_GPIO_D_START    = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_C),
+        S5PC100_GPIO_D_START    = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_C),
-        S5PC1XX_GPIO_E0_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_D),
+        S5PC100_GPIO_E0_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_D),
-        S5PC1XX_GPIO_E1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_E0),
+        S5PC100_GPIO_E1_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_E0),
-        S5PC1XX_GPIO_F0_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_E1),
+        S5PC100_GPIO_F0_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_E1),
-        S5PC1XX_GPIO_F1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F0),
+        S5PC100_GPIO_F1_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F0),
-        S5PC1XX_GPIO_F2_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F1),
+        S5PC100_GPIO_F2_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F1),
-        S5PC1XX_GPIO_F3_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F2),
+        S5PC100_GPIO_F3_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F2),
-        S5PC1XX_GPIO_G0_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F3),
+        S5PC100_GPIO_G0_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F3),
-        S5PC1XX_GPIO_G1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G0),
+        S5PC100_GPIO_G1_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G0),
-        S5PC1XX_GPIO_G2_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G1),
+        S5PC100_GPIO_G2_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G1),
-        S5PC1XX_GPIO_G3_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G2),
+        S5PC100_GPIO_G3_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G2),
-        S5PC1XX_GPIO_H0_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G3),
+        S5PC100_GPIO_H0_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G3),
-        S5PC1XX_GPIO_H1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H0),
+        S5PC100_GPIO_H1_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H0),
-        S5PC1XX_GPIO_H2_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H1),
+        S5PC100_GPIO_H2_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H1),
-        S5PC1XX_GPIO_H3_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H2),
+        S5PC100_GPIO_H3_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H2),
-        S5PC1XX_GPIO_I_START    = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H3),
+        S5PC100_GPIO_I_START    = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H3),
-        S5PC1XX_GPIO_J0_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_I),
+        S5PC100_GPIO_J0_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_I),
-        S5PC1XX_GPIO_J1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J0),
+        S5PC100_GPIO_J1_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J0),
-        S5PC1XX_GPIO_J2_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J1),
+        S5PC100_GPIO_J2_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J1),
-        S5PC1XX_GPIO_J3_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J2),
+        S5PC100_GPIO_J3_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J2),
-        S5PC1XX_GPIO_J4_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J3),
+        S5PC100_GPIO_J4_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J3),
-        S5PC1XX_GPIO_K0_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J4),
+        S5PC100_GPIO_K0_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J4),
-        S5PC1XX_GPIO_K1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K0),
+        S5PC100_GPIO_K1_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K0),
-        S5PC1XX_GPIO_K2_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K1),
+        S5PC100_GPIO_K2_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K1),
-        S5PC1XX_GPIO_K3_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K2),
+        S5PC100_GPIO_K3_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K2),
-        S5PC1XX_GPIO_MP00_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K3),
+        S5PC100_GPIO_L0_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K3),
-        S5PC1XX_GPIO_MP01_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP00),
+        S5PC100_GPIO_L1_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L0),
-        S5PC1XX_GPIO_MP02_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP01),
+        S5PC100_GPIO_L2_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L1),
-        S5PC1XX_GPIO_MP03_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP02),
+        S5PC100_GPIO_L3_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L2),
-        S5PC1XX_GPIO_MP04_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP03),
+        S5PC100_GPIO_L4_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L3),
+        S5PC100_GPIO_MP00_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L4),
+        S5PC100_GPIO_MP01_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP00),
+        S5PC100_GPIO_MP02_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP01),
+        S5PC100_GPIO_MP03_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP02),
+        S5PC100_GPIO_MP04_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP03),
+        S5PC100_GPIO_END        = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP04),
 };
-/* S5PC1XX GPIO number definitions. */
+/* S5PC100 GPIO number definitions. */
-#define S5PC1XX_GPA0(_nr)       (S5PC1XX_GPIO_A0_START + (_nr))
+#define S5PC100_GPA0(_nr)       (S5PC100_GPIO_A0_START + (_nr))
-#define S5PC1XX_GPA1(_nr)       (S5PC1XX_GPIO_A1_START + (_nr))
+#define S5PC100_GPA1(_nr)       (S5PC100_GPIO_A1_START + (_nr))
-#define S5PC1XX_GPB(_nr)        (S5PC1XX_GPIO_B_START + (_nr))
+#define S5PC100_GPB(_nr)        (S5PC100_GPIO_B_START + (_nr))
-#define S5PC1XX_GPC(_nr)        (S5PC1XX_GPIO_C_START + (_nr))
+#define S5PC100_GPC(_nr)        (S5PC100_GPIO_C_START + (_nr))
-#define S5PC1XX_GPD(_nr)        (S5PC1XX_GPIO_D_START + (_nr))
+#define S5PC100_GPD(_nr)        (S5PC100_GPIO_D_START + (_nr))
-#define S5PC1XX_GPE0(_nr)       (S5PC1XX_GPIO_E0_START + (_nr))
+#define S5PC100_GPE0(_nr)       (S5PC100_GPIO_E0_START + (_nr))
-#define S5PC1XX_GPE1(_nr)       (S5PC1XX_GPIO_E1_START + (_nr))
+#define S5PC100_GPE1(_nr)       (S5PC100_GPIO_E1_START + (_nr))
-#define S5PC1XX_GPF0(_nr)       (S5PC1XX_GPIO_F0_START + (_nr))
+#define S5PC100_GPF0(_nr)       (S5PC100_GPIO_F0_START + (_nr))
-#define S5PC1XX_GPF1(_nr)       (S5PC1XX_GPIO_F1_START + (_nr))
+#define S5PC100_GPF1(_nr)       (S5PC100_GPIO_F1_START + (_nr))
-#define S5PC1XX_GPF2(_nr)       (S5PC1XX_GPIO_F2_START + (_nr))
+#define S5PC100_GPF2(_nr)       (S5PC100_GPIO_F2_START + (_nr))
-#define S5PC1XX_GPF3(_nr)       (S5PC1XX_GPIO_F3_START + (_nr))
+#define S5PC100_GPF3(_nr)       (S5PC100_GPIO_F3_START + (_nr))
-#define S5PC1XX_GPG0(_nr)       (S5PC1XX_GPIO_G0_START + (_nr))
+#define S5PC100_GPG0(_nr)       (S5PC100_GPIO_G0_START + (_nr))
-#define S5PC1XX_GPG1(_nr)       (S5PC1XX_GPIO_G1_START + (_nr))
+#define S5PC100_GPG1(_nr)       (S5PC100_GPIO_G1_START + (_nr))
-#define S5PC1XX_GPG2(_nr)       (S5PC1XX_GPIO_G2_START + (_nr))
+#define S5PC100_GPG2(_nr)       (S5PC100_GPIO_G2_START + (_nr))
-#define S5PC1XX_GPG3(_nr)       (S5PC1XX_GPIO_G3_START + (_nr))
+#define S5PC100_GPG3(_nr)       (S5PC100_GPIO_G3_START + (_nr))
-#define S5PC1XX_GPH0(_nr)       (S5PC1XX_GPIO_H0_START + (_nr))
+#define S5PC100_GPH0(_nr)       (S5PC100_GPIO_H0_START + (_nr))
-#define S5PC1XX_GPH1(_nr)       (S5PC1XX_GPIO_H1_START + (_nr))
+#define S5PC100_GPH1(_nr)       (S5PC100_GPIO_H1_START + (_nr))
-#define S5PC1XX_GPH2(_nr)       (S5PC1XX_GPIO_H2_START + (_nr))
+#define S5PC100_GPH2(_nr)       (S5PC100_GPIO_H2_START + (_nr))
-#define S5PC1XX_GPH3(_nr)       (S5PC1XX_GPIO_H3_START + (_nr))
+#define S5PC100_GPH3(_nr)       (S5PC100_GPIO_H3_START + (_nr))
-#define S5PC1XX_GPI(_nr)        (S5PC1XX_GPIO_I_START + (_nr))
+#define S5PC100_GPI(_nr)        (S5PC100_GPIO_I_START + (_nr))
-#define S5PC1XX_GPJ0(_nr)       (S5PC1XX_GPIO_J0_START + (_nr))
+#define S5PC100_GPJ0(_nr)       (S5PC100_GPIO_J0_START + (_nr))
-#define S5PC1XX_GPJ1(_nr)       (S5PC1XX_GPIO_J1_START + (_nr))
+#define S5PC100_GPJ1(_nr)       (S5PC100_GPIO_J1_START + (_nr))
-#define S5PC1XX_GPJ2(_nr)       (S5PC1XX_GPIO_J2_START + (_nr))
+#define S5PC100_GPJ2(_nr)       (S5PC100_GPIO_J2_START + (_nr))
-#define S5PC1XX_GPJ3(_nr)       (S5PC1XX_GPIO_J3_START + (_nr))
+#define S5PC100_GPJ3(_nr)       (S5PC100_GPIO_J3_START + (_nr))
-#define S5PC1XX_GPJ4(_nr)       (S5PC1XX_GPIO_J4_START + (_nr))
+#define S5PC100_GPJ4(_nr)       (S5PC100_GPIO_J4_START + (_nr))
-#define S5PC1XX_GPK0(_nr)       (S5PC1XX_GPIO_K0_START + (_nr))
+#define S5PC100_GPK0(_nr)       (S5PC100_GPIO_K0_START + (_nr))
-#define S5PC1XX_GPK1(_nr)       (S5PC1XX_GPIO_K1_START + (_nr))
+#define S5PC100_GPK1(_nr)       (S5PC100_GPIO_K1_START + (_nr))
-#define S5PC1XX_GPK2(_nr)       (S5PC1XX_GPIO_K2_START + (_nr))
+#define S5PC100_GPK2(_nr)       (S5PC100_GPIO_K2_START + (_nr))
-#define S5PC1XX_GPK3(_nr)       (S5PC1XX_GPIO_K3_START + (_nr))
+#define S5PC100_GPK3(_nr)       (S5PC100_GPIO_K3_START + (_nr))
-#define S5PC1XX_MP00(_nr)       (S5PC1XX_GPIO_MP00_START + (_nr))
+#define S5PC100_GPL0(_nr)       (S5PC100_GPIO_L0_START + (_nr))
-#define S5PC1XX_MP01(_nr)       (S5PC1XX_GPIO_MP01_START + (_nr))
+#define S5PC100_GPL1(_nr)       (S5PC100_GPIO_L1_START + (_nr))
-#define S5PC1XX_MP02(_nr)       (S5PC1XX_GPIO_MP02_START + (_nr))
+#define S5PC100_GPL2(_nr)       (S5PC100_GPIO_L2_START + (_nr))
-#define S5PC1XX_MP03(_nr)       (S5PC1XX_GPIO_MP03_START + (_nr))
+#define S5PC100_GPL3(_nr)       (S5PC100_GPIO_L3_START + (_nr))
-#define S5PC1XX_MP04(_nr)       (S5PC1XX_GPIO_MP04_START + (_nr))
+#define S5PC100_GPL4(_nr)       (S5PC100_GPIO_L4_START + (_nr))
+#define S5PC100_MP00(_nr)       (S5PC100_GPIO_MP00_START + (_nr))
+#define S5PC100_MP01(_nr)       (S5PC100_GPIO_MP01_START + (_nr))
+#define S5PC100_MP02(_nr)       (S5PC100_GPIO_MP02_START + (_nr))
+#define S5PC100_MP03(_nr)       (S5PC100_GPIO_MP03_START + (_nr))
+#define S5PC100_MP04(_nr)       (S5PC100_GPIO_MP04_START + (_nr))
+#define S5PC100_MP05(_nr)       (S5PC100_GPIO_MP05_START + (_nr))
-/* the end of the S5PC1XX specific gpios */
+/* It used the end of the S5PC1XX gpios */
-#define S5PC1XX_GPIO_END        (S5PC1XX_MP04(S5PC1XX_GPIO_MP04_NR) + 1)
+#define S3C_GPIO_END            S5PC100_GPIO_END
-#define S3C_GPIO_END            S5PC1XX_GPIO_END
 /* define the number of gpios we need to the one after the MP04() range */
-#define ARCH_NR_GPIOS   (S5PC1XX_MP04(S5PC1XX_GPIO_MP04_NR) + 1)
+#define ARCH_NR_GPIOS           (S5PC100_GPIO_END + 1)
 #include <asm-generic/gpio.h>
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h
index 622720dba289..b53fa48a52c6 100644
--- a/arch/arm/mach-s5pc100/include/mach/irqs.h
+++ b/arch/arm/mach-s5pc100/include/mach/irqs.h
@@ -11,4 +11,9 @@
 #include <plat/irqs.h>
+/* LCD */
+#define IRQ_LCD_FIFO            IRQ_LCD0
+#define IRQ_LCD_VSYNC           IRQ_LCD1
+#define IRQ_LCD_SYSTEM          IRQ_LCD2
 #endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index 9e9f39130b2c..4681ebe8bef6 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -17,6 +17,19 @@
 #include <plat/map-base.h>
+/*
+ * map-base.h has already defined virtual memory address
+ * S3C_VA_IRQ           S3C_ADDR(0x00000000)    irq controller(s)
+ * S3C_VA_SYS           S3C_ADDR(0x00100000)    system control
+ * S3C_VA_MEM           S3C_ADDR(0x00200000)    system control (not used)
+ * S3C_VA_TIMER         S3C_ADDR(0x00300000)    timer block
+ * S3C_VA_WATCHDOG      S3C_ADDR(0x00400000)    watchdog
+ * S3C_VA_UART          S3C_ADDR(0x01000000)    UART
+ *
+ * S5PC100 specific virtual memory address can be defined here
+ * S5PC1XX_VA_GPIO      S3C_ADDR(0x00500000)    GPIO
+ *
+ */
 /* Chip ID */
 #define S5PC100_PA_CHIPID       (0xE0000000)
@@ -24,13 +37,20 @@
 #define S5PC1XX_VA_CHIPID       S3C_VA_SYS
 /* System */
-#define S5PC100_PA_SYS          (0xE0100000)
+#define S5PC100_PA_CLK          (0xE0100000)
-#define S5PC100_PA_CLK          (S5PC100_PA_SYS + 0x0)
+#define S5PC100_PA_CLK_OTHER    (0xE0200000)
-#define S5PC100_PA_PWR          (S5PC100_PA_SYS + 0x8000)
+#define S5PC100_PA_PWR          (0xE0108000)
 #define S5PC1XX_PA_CLK          S5PC100_PA_CLK
 #define S5PC1XX_PA_PWR          S5PC100_PA_PWR
+#define S5PC1XX_PA_CLK_OTHER    S5PC100_PA_CLK_OTHER
 #define S5PC1XX_VA_CLK          (S3C_VA_SYS + 0x10000)
 #define S5PC1XX_VA_PWR          (S3C_VA_SYS + 0x20000)
+#define S5PC1XX_VA_CLK_OTHER    (S3C_VA_SYS + 0x30000)
+/* GPIO */
+#define S5PC100_PA_GPIO         (0xE0300000)
+#define S5PC1XX_PA_GPIO         S5PC100_PA_GPIO
+#define S5PC1XX_VA_GPIO         S3C_ADDR(0x00500000)
 /* Interrupt */
 #define S5PC100_PA_VIC          (0xE4000000)
@@ -40,23 +60,64 @@
 #define S5PC1XX_PA_VIC(x)       (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET))
 #define S5PC1XX_VA_VIC(x)       (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
+/* DMA */
+#define S5PC100_PA_MDMA         (0xE8100000)
+#define S5PC100_PA_PDMA0        (0xE9000000)
+#define S5PC100_PA_PDMA1        (0xE9200000)
 /* Timer */
 #define S5PC100_PA_TIMER        (0xEA000000)
 #define S5PC1XX_PA_TIMER        S5PC100_PA_TIMER
 #define S5PC1XX_VA_TIMER        S3C_VA_TIMER
+/* RTC */
+#define S5PC100_PA_RTC          (0xEA300000)
 /* UART */
 #define S5PC100_PA_UART         (0xEC000000)
 #define S5PC1XX_PA_UART         S5PC100_PA_UART
 #define S5PC1XX_VA_UART         S3C_VA_UART
-/* IIC */
+/* I2C */
-#define S5PC100_PA_IIC          (0xEC100000)
+#define S5PC100_PA_I2C          (0xEC100000)
+#define S5PC100_PA_I2C1         (0xEC200000)
+/* USB HS OTG */
+#define S5PC100_PA_USB_HSOTG    (0xED200000)
+#define S5PC100_PA_USB_HSPHY    (0xED300000)
+/* SD/MMC */
+#define S5PC100_PA_HSMMC(x)     (0xED800000 + ((x) * 0x100000))
+#define S5PC100_PA_HSMMC0       S5PC100_PA_HSMMC(0)
+#define S5PC100_PA_HSMMC1       S5PC100_PA_HSMMC(1)
+#define S5PC100_PA_HSMMC2       S5PC100_PA_HSMMC(2)
+/* LCD */
+#define S5PC100_PA_FB           (0xEE000000)
+/* Multimedia */
+#define S5PC100_PA_G2D          (0xEE800000)
+#define S5PC100_PA_JPEG         (0xEE500000)
+#define S5PC100_PA_ROTATOR      (0xEE100000)
+#define S5PC100_PA_G3D          (0xEF000000)
+/* I2S */
+#define S5PC100_PA_I2S0         (0xF2000000)
+#define S5PC100_PA_I2S1         (0xF2100000)
+#define S5PC100_PA_I2S2         (0xF2200000)
+/* KEYPAD */
+#define S5PC100_PA_KEYPAD       (0xF3100000)
+/* ADC & TouchScreen */
+#define S5PC100_PA_TSADC        (0xF3000000)
 /* ETC */
 #define S5PC100_PA_SDRAM        (0x20000000)
+#define S5PC1XX_PA_SDRAM        S5PC100_PA_SDRAM
 /* compatibility defines. */
+#define S3C_PA_RTC              S5PC100_PA_RTC
 #define S3C_PA_UART             S5PC100_PA_UART
 #define S3C_PA_UART0            (S5PC100_PA_UART + 0x0)
 #define S3C_PA_UART1            (S5PC100_PA_UART + 0x400)
@@ -67,9 +128,23 @@
 #define S3C_VA_UART2            (S3C_VA_UART + 0x800)
 #define S3C_VA_UART3            (S3C_VA_UART + 0xC00)
 #define S3C_UART_OFFSET         0x400
+#define S3C_VA_UARTx(x)         (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
+#define S3C_PA_FB               S5PC100_PA_FB
+#define S3C_PA_G2D              S5PC100_PA_G2D
+#define S3C_PA_G3D              S5PC100_PA_G3D
+#define S3C_PA_JPEG             S5PC100_PA_JPEG
+#define S3C_PA_ROTATOR          S5PC100_PA_ROTATOR
 #define S3C_VA_VIC0             (S3C_VA_IRQ + 0x0)
 #define S3C_VA_VIC1             (S3C_VA_IRQ + 0x10000)
 #define S3C_VA_VIC2             (S3C_VA_IRQ + 0x20000)
-#define S3C_PA_IIC              S5PC100_PA_IIC
+#define S3C_PA_IIC              S5PC100_PA_I2C
+#define S3C_PA_IIC1             S5PC100_PA_I2C1
+#define S3C_PA_USB_HSOTG        S5PC100_PA_USB_HSOTG
+#define S3C_PA_USB_HSPHY        S5PC100_PA_USB_HSPHY
+#define S3C_PA_HSMMC0           S5PC100_PA_HSMMC0
+#define S3C_PA_HSMMC1           S5PC100_PA_HSMMC1
+#define S3C_PA_HSMMC2           S5PC100_PA_HSMMC2
+#define S3C_PA_KEYPAD           S5PC100_PA_KEYPAD
+#define S3C_PA_TSADC            S5PC100_PA_TSADC
 #endif /* __ASM_ARCH_C100_MAP_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-fb.h b/arch/arm/mach-s5pc100/include/mach/regs-fb.h
new file mode 100644
index 000000000000..1732cd28c765
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/regs-fb.h
@@ -0,0 +1,139 @@
+/* arch/arm/mach-s5pc100/include/mach/regs-fb.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *   Pawel Osciak <p.osciak@samsung.com>
+ *
+ * Framebuffer register definitions for Samsung S5PC100.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __ASM_ARCH_REGS_FB_H
+#define __ASM_ARCH_REGS_FB_H __FILE__
+#include <plat/regs-fb-v4.h>
+/* VP1 interface timing control */
+#define VP1CON0                                         (0x118)
+#define VP1_RATECON_EN                                  (1 << 31)
+#define VP1_CLKRATE_MASK                                (0xff)
+#define VP1CON1                                         (0x11c)
+#define VP1_VTREGCON_EN                                 (1 << 31)
+#define VP1_VBPD_MASK                                   (0xfff)
+#define VP1_VBPD_SHIFT                                  (16)
+#define WPALCON_H                                       (0x19c)
+#define WPALCON_L                                       (0x1a0)
+/* Pallete contro for WPAL0 and WPAL1 is the same as in S3C64xx, but
+ * different for WPAL2-4
+ */
+/* In WPALCON_L (aka WPALCON) */
+#define WPALCON_W1PAL_32BPP_A888                        (0x7 << 3)
+#define WPALCON_W0PAL_32BPP_A888                        (0x7 << 0)
+/* To set W2PAL-W4PAL consist of one bit from WPALCON_L and two from WPALCON_H,
+ * e.g. W2PAL[2..0] is made of (WPALCON_H[10..9], WPALCON_L[6]).
+ */
+#define WPALCON_L_WxPAL_L_MASK                          (0x1)
+#define WPALCON_L_W2PAL_L_SHIFT                         (6)
+#define WPALCON_L_W3PAL_L_SHIFT                         (7)
+#define WPALCON_L_W4PAL_L_SHIFT                         (8)
+#define WPALCON_L_WxPAL_H_MASK                          (0x3)
+#define WPALCON_H_W2PAL_H_SHIFT                         (9)
+#define WPALCON_H_W3PAL_H_SHIFT                         (13)
+#define WPALCON_H_W4PAL_H_SHIFT                         (17)
+/* Per-window alpha value registers */
+/* For window 0 8-bit alpha values are in VIDW0ALPHAx,
+ * for windows 1-4 alpha values consist of two parts, the 4 low bits are
+ * taken from VIDWxALPHAx and 4 high bits are from VIDOSDxC,
+ * e.g. WIN1_ALPHA0_B[7..0] = (VIDOSD1C[3..0], VIDW1ALPHA0[3..0])
+ */
+#define VIDWxALPHA0(_win)                               (0x200 + (_win * 8))
+#define VIDWxALPHA1(_win)                               (0x204 + (_win * 8))
+/* Only for window 0 in VIDW0ALPHAx. */
+#define VIDW0ALPHAx_R(_x)                               ((_x) << 16)
+#define VIDW0ALPHAx_R_MASK                              (0xff << 16)
+#define VIDW0ALPHAx_R_SHIFT                             (16)
+#define VIDW0ALPHAx_G(_x)                               ((_x) << 8)
+#define VIDW0ALPHAx_G_MASK                              (0xff << 8)
+#define VIDW0ALPHAx_G_SHIFT                             (8)
+#define VIDW0ALPHAx_B(_x)                               ((_x) << 0)
+#define VIDW0ALPHAx_B_MASK                              (0xff << 0)
+#define VIDW0ALPHAx_B_SHIFT                             (0)
+/* Low 4 bits of alpha0-1 for windows 1-4 */
+#define VIDW14ALPHAx_R_L(_x)                            ((_x) << 16)
+#define VIDW14ALPHAx_R_L_MASK                           (0xf << 16)
+#define VIDW14ALPHAx_R_L_SHIFT                          (16)
+#define VIDW14ALPHAx_G_L(_x)                            ((_x) << 8)
+#define VIDW14ALPHAx_G_L_MASK                           (0xf << 8)
+#define VIDW14ALPHAx_G_L_SHIFT                          (8)
+#define VIDW14ALPHAx_B_L(_x)                            ((_x) << 0)
+#define VIDW14ALPHAx_B_L_MASK                           (0xf << 0)
+#define VIDW14ALPHAx_B_L_SHIFT                          (0)
+/* Per-window blending equation control registers */
+#define BLENDEQx(_win)                                  (0x244 + ((_win) * 4))
+#define BLENDEQ1                                        (0x244)
+#define BLENDEQ2                                        (0x248)
+#define BLENDEQ3                                        (0x24c)
+#define BLENDEQ4                                        (0x250)
+#define BLENDEQx_Q_FUNC(_x)                             ((_x) << 18)
+#define BLENDEQx_Q_FUNC_MASK                            (0xf << 18)
+#define BLENDEQx_P_FUNC(_x)                             ((_x) << 12)
+#define BLENDEQx_P_FUNC_MASK                            (0xf << 12)
+#define BLENDEQx_B_FUNC(_x)                             ((_x) << 6)
+#define BLENDEQx_B_FUNC_MASK                            (0xf << 6)
+#define BLENDEQx_A_FUNC(_x)                             ((_x) << 0)
+#define BLENDEQx_A_FUNC_MASK                            (0xf << 0)
+#define BLENDCON                                        (0x260)
+#define BLENDCON_8BIT_ALPHA                             (1 << 0)
+/* Per-window palette base addresses (start of palette memory).
+ * Each window palette area consists of 256 32-bit entries.
+ * START is the first address (entry 0th), END is the address of 255th entry.
+ */
+#define WIN0_PAL_BASE                                   (0x2400)
+#define WIN0_PAL_END                                    (0x27fc)
+#define WIN1_PAL_BASE                                   (0x2800)
+#define WIN1_PAL_END                                    (0x2bfc)
+#define WIN2_PAL_BASE                                   (0x2c00)
+#define WIN2_PAL_END                                    (0x2ffc)
+#define WIN3_PAL_BASE                                   (0x3000)
+#define WIN3_PAL_END                                    (0x33fc)
+#define WIN4_PAL_BASE                                   (0x3400)
+#define WIN4_PAL_END                                    (0x37fc)
+#define WIN0_PAL(_entry)                        (WIN0_PAL_BASE + ((_entry) * 4))
+#define WIN1_PAL(_entry)                        (WIN1_PAL_BASE + ((_entry) * 4))
+#define WIN2_PAL(_entry)                        (WIN2_PAL_BASE + ((_entry) * 4))
+#define WIN3_PAL(_entry)                        (WIN3_PAL_BASE + ((_entry) * 4))
+#define WIN4_PAL(_entry)                        (WIN4_PAL_BASE + ((_entry) * 4))
+static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
+{
+        switch (window) {
+        case 0: return WIN0_PAL(reg);
+        case 1: return WIN1_PAL(reg);
+        case 2: return WIN2_PAL(reg);
+        case 3: return WIN3_PAL(reg);
+        case 4: return WIN4_PAL(reg);
+        }
+        BUG();
+}
+#endif /* __ASM_ARCH_REGS_FB_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/system.h b/arch/arm/mach-s5pc100/include/mach/system.h
index e39014375470..f0d31a2a598c 100644
--- a/arch/arm/mach-s5pc100/include/mach/system.h
+++ b/arch/arm/mach-s5pc100/include/mach/system.h
@@ -11,14 +11,21 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H __FILE__
+#include <linux/io.h>
+#include <mach/map.h>
+#include <plat/regs-clock.h>
+void (*s5pc1xx_idle)(void);
 static void arch_idle(void)
 {
-        /* nothing here yet */
+        if (s5pc1xx_idle)
+                s5pc1xx_idle();
 }
 static void arch_reset(char mode, const char *cmd)
 {
-        /* nothing here yet */
+        __raw_writel(S5PC100_SWRESET_RESETVAL, S5PC100_SWRESET);
+        return;
 }
 #endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 214093cd7632..ae3c52cd0ebb 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -27,16 +27,22 @@
 #include <asm/mach/map.h>
 #include <mach/map.h>
+#include <mach/regs-fb.h>
+#include <video/platform_lcd.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 #include <plat/regs-serial.h>
+#include <plat/gpio-cfg.h>
+#include <plat/regs-gpio.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/s5pc100.h>
+#include <plat/fb.h>
+#include <plat/iic.h>
 #define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
 #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
@@ -73,9 +79,78 @@ static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = {
        },
 };
+/* I2C0 */
+static struct i2c_board_info i2c_devs0[] __initdata = {
+};
+/* I2C1 */
+static struct i2c_board_info i2c_devs1[] __initdata = {
+};
+/* LCD power controller */
+static void smdkc100_lcd_power_set(struct plat_lcd_data *pd,
+                                   unsigned int power)
+{
+        /* backlight */
+        gpio_direction_output(S5PC100_GPD(0), power);
+        if (power) {
+                /* module reset */
+                gpio_direction_output(S5PC100_GPH0(6), 1);
+                mdelay(100);
+                gpio_direction_output(S5PC100_GPH0(6), 0);
+                mdelay(10);
+                gpio_direction_output(S5PC100_GPH0(6), 1);
+                mdelay(10);
+        }
+}
+static struct plat_lcd_data smdkc100_lcd_power_data = {
+        .set_power      = smdkc100_lcd_power_set,
+};
+static struct platform_device smdkc100_lcd_powerdev = {
+        .name                   = "platform-lcd",
+        .dev.parent             = &s3c_device_fb.dev,
+        .dev.platform_data      = &smdkc100_lcd_power_data,
+};
+/* Frame Buffer */
+static struct s3c_fb_pd_win smdkc100_fb_win0 = {
+        /* this is to ensure we use win0 */
+        .win_mode       = {
+                .refresh        = 70,
+                .pixclock       = (8+13+3+800)*(7+5+1+480),
+                .left_margin    = 8,
+                .right_margin   = 13,
+                .upper_margin   = 7,
+                .lower_margin   = 5,
+                .hsync_len      = 3,
+                .vsync_len      = 1,
+                .xres           = 800,
+                .yres           = 480,
+        },
+        .max_bpp        = 32,
+        .default_bpp    = 16,
+};
+static struct s3c_fb_platdata smdkc100_lcd_pdata __initdata = {
+        .win[0]         = &smdkc100_fb_win0,
+        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+        .setup_gpio     = s5pc100_fb_gpio_setup_24bpp,
+};
 static struct map_desc smdkc100_iodesc[] = {};
 static struct platform_device *smdkc100_devices[] __initdata = {
+        &s3c_device_i2c0,
+        &s3c_device_i2c1,
+        &s3c_device_fb,
+        &s3c_device_hsmmc0,
+        &s3c_device_hsmmc1,
+        &s3c_device_hsmmc2,
+        &smdkc100_lcd_powerdev,
 };
 static void __init smdkc100_map_io(void)
@@ -87,12 +162,24 @@ static void __init smdkc100_map_io(void)
 static void __init smdkc100_machine_init(void)
 {
+        /* I2C */
+        s3c_i2c0_set_platdata(NULL);
+        s3c_i2c1_set_platdata(NULL);
+        i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
+        i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
+        s3c_fb_set_platdata(&smdkc100_lcd_pdata);
+        /* LCD init */
+        gpio_request(S5PC100_GPD(0), "GPD");
+        gpio_request(S5PC100_GPH0(6), "GPH0");
+        smdkc100_lcd_power_set(&smdkc100_lcd_power_data, 0);
        platform_add_devices(smdkc100_devices, ARRAY_SIZE(smdkc100_devices));
 }
 MACHINE_START(SMDKC100, "SMDKC100")
        /* Maintainer: Byungho Min <bhmin@samsung.com> */
-        .phys_io        = S5PC1XX_PA_UART & 0xfff00000,
+        .phys_io        = S5PC100_PA_UART & 0xfff00000,
        .io_pg_offst    = (((u32)S5PC1XX_VA_UART) >> 18) & 0xfffc,
        .boot_params    = S5PC100_PA_SDRAM + 0x100,
diff --git a/arch/arm/mach-s5pc100/setup-sdhci.c b/arch/arm/mach-s5pc100/setup-sdhci.c
new file mode 100644
index 000000000000..4385986a3da0
--- /dev/null
+++ b/arch/arm/mach-s5pc100/setup-sdhci.c
@@ -0,0 +1,65 @@
+/* linux/arch/arm/mach-s5pc100/setup-sdhci.c
+ *
+ * Copyright 2008 Samsung Electronics
+ *
+ * S5PC100 - Helper functions for settign up SDHCI device(s) (HSMMC)
+ *
+ * Based on mach-s3c6410/setup-sdhci.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/mmc/card.h>
+#include <linux/mmc/host.h>
+#include <plat/regs-sdhci.h>
+#include <plat/sdhci.h>
+/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
+char *s5pc100_hsmmc_clksrcs[4] = {
+        [0] = "hsmmc",
+        [1] = "hsmmc",
+        /* [2] = "mmc_bus", not yet succesfuuly used yet */
+        /* [3] = "48m", - note not succesfully used yet */
+};
+void s5pc100_setup_sdhci0_cfg_card(struct platform_device *dev,
+                                    void __iomem *r,
+                                    struct mmc_ios *ios,
+                                    struct mmc_card *card)
+{
+        u32 ctrl2, ctrl3;
+        /* don't need to alter anything acording to card-type */
+        writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);
+        ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
+        ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
+        ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
+                  S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
+                  S3C_SDHCI_CTRL2_ENFBCLKRX |
+                  S3C_SDHCI_CTRL2_DFCNT_NONE |
+                  S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
+        if (ios->clock < 25 * 1000000)
+                ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
+                         S3C_SDHCI_CTRL3_FCSEL2 |
+                         S3C_SDHCI_CTRL3_FCSEL1 |
+                         S3C_SDHCI_CTRL3_FCSEL0);
+        else
+                ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
+        writel(ctrl2, r + S3C_SDHCI_CONTROL2);
+        writel(ctrl3, r + S3C_SDHCI_CONTROL3);
+}
diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig
index 4e5c07f4e456..03a7f3857c5e 100644
--- a/arch/arm/mach-sa1100/Kconfig
+++ b/arch/arm/mach-sa1100/Kconfig
@@ -53,23 +53,23 @@ config SA1100_COLLIE
 config SA1100_H3100
        bool "Compaq iPAQ H3100"
+        select HTC_EGPIO
        help
          Say Y here if you intend to run this kernel on the Compaq iPAQ
          H3100 handheld computer.  Information about this machine and the
          Linux port to this machine can be found at:
          <http://www.handhelds.org/Compaq/index.html#iPAQ_H3100>
-          <http://www.compaq.com/products/handhelds/pocketpc/>
 config SA1100_H3600
        bool "Compaq iPAQ H3600/H3700"
+        select HTC_EGPIO
        help
          Say Y here if you intend to run this kernel on the Compaq iPAQ
          H3600 handheld computer.  Information about this machine and the
          Linux port to this machine can be found at:
          <http://www.handhelds.org/Compaq/index.html#iPAQ_H3600>
-          <http://www.compaq.com/products/handhelds/pocketpc/>
 config SA1100_BADGE4
        bool "HP Labs BadgePAD 4"
diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile
index bb7b8198d0c4..89349c1dd7a6 100644
--- a/arch/arm/mach-sa1100/Makefile
+++ b/arch/arm/mach-sa1100/Makefile
@@ -25,8 +25,8 @@ led-$(CONFIG_SA1100_CERF)		+= leds-cerf.o
 obj-$(CONFIG_SA1100_COLLIE)             += collie.o
-obj-$(CONFIG_SA1100_H3100)              += h3600.o
+obj-$(CONFIG_SA1100_H3100)              += h3100.o h3xxx.o
-obj-$(CONFIG_SA1100_H3600)              += h3600.o
+obj-$(CONFIG_SA1100_H3600)              += h3600.o h3xxx.o
 obj-$(CONFIG_SA1100_HACKKIT)            += hackkit.o
 led-$(CONFIG_SA1100_HACKKIT)            += leds-hackkit.o
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index 55e64477a876..169e5b87dbff 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -249,10 +249,10 @@ static void __init assabet_init(void)
 #endif
        }
-        sa11x0_set_flash_data(&assabet_flash_data, assabet_flash_resources,
+        sa11x0_register_mtd(&assabet_flash_data, assabet_flash_resources,
-                              ARRAY_SIZE(assabet_flash_resources));
+                            ARRAY_SIZE(assabet_flash_resources));
-        sa11x0_set_irda_data(&assabet_irda_data);
+        sa11x0_register_irda(&assabet_irda_data);
-        sa11x0_set_mcp_data(&assabet_mcp_data);
+        sa11x0_register_mcp(&assabet_mcp_data);
 }
 /*
diff --git a/arch/arm/mach-sa1100/badge4.c b/arch/arm/mach-sa1100/badge4.c
index ab5883b39ddf..051ec0f0023c 100644
--- a/arch/arm/mach-sa1100/badge4.c
+++ b/arch/arm/mach-sa1100/badge4.c
@@ -212,7 +212,7 @@ static int __init badge4_init(void)
        /* maybe turn on 5v0 from the start */
        badge4_set_5V(BADGE4_5V_INITIALLY, five_v_on);
-        sa11x0_set_flash_data(&badge4_flash_data, &badge4_flash_resource, 1);
+        sa11x0_register_mtd(&badge4_flash_data, &badge4_flash_resource, 1);
        return 0;
 }
diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c
index fd3ad9cfc912..bc950ef418af 100644
--- a/arch/arm/mach-sa1100/cerf.c
+++ b/arch/arm/mach-sa1100/cerf.c
@@ -129,8 +129,8 @@ static struct mcp_plat_data cerf_mcp_data = {
 static void __init cerf_init(void)
 {
        platform_add_devices(cerf_devices, ARRAY_SIZE(cerf_devices));
-        sa11x0_set_flash_data(&cerf_flash_data, &cerf_flash_resource, 1);
+        sa11x0_register_mtd(&cerf_flash_data, &cerf_flash_resource, 1);
-        sa11x0_set_mcp_data(&cerf_mcp_data);
+        sa11x0_register_mcp(&cerf_mcp_data);
 }
 MACHINE_START(CERF, "Intrinsyc CerfBoard/CerfCube")
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
index bbf2ebcc3066..9982c5c28edf 100644
--- a/arch/arm/mach-sa1100/collie.c
+++ b/arch/arm/mach-sa1100/collie.c
@@ -26,6 +26,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/timer.h>
 #include <linux/gpio.h>
+#include <linux/pda_power.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -56,6 +57,7 @@ static struct resource collie_scoop_resources[] = {
 static struct scoop_config collie_scoop_setup = {
        .io_dir         = COLLIE_SCOOP_IO_DIR,
        .io_out         = COLLIE_SCOOP_IO_OUT,
+        .gpio_base      = COLLIE_SCOOP_GPIO_BASE,
 };
 struct platform_device colliescoop_device = {
@@ -85,6 +87,70 @@ static struct scoop_pcmcia_config collie_pcmcia_config = {
 static struct mcp_plat_data collie_mcp_data = {
        .mccr0          = MCCR0_ADM | MCCR0_ExtClk,
        .sclk_rate      = 9216000,
+        .gpio_base      = COLLIE_TC35143_GPIO_BASE,
+};
+/*
+ * Collie AC IN
+ */
+static int collie_power_init(struct device *dev)
+{
+        int ret = gpio_request(COLLIE_GPIO_AC_IN, "ac in");
+        if (ret)
+                goto err_gpio_req;
+        ret = gpio_direction_input(COLLIE_GPIO_AC_IN);
+        if (ret)
+                goto err_gpio_in;
+        return 0;
+err_gpio_in:
+        gpio_free(COLLIE_GPIO_AC_IN);
+err_gpio_req:
+        return ret;
+}
+static void collie_power_exit(struct device *dev)
+{
+        gpio_free(COLLIE_GPIO_AC_IN);
+}
+static int collie_power_ac_online(void)
+{
+        return gpio_get_value(COLLIE_GPIO_AC_IN) == 2;
+}
+static char *collie_ac_supplied_to[] = {
+        "main-battery",
+        "backup-battery",
+};
+static struct pda_power_pdata collie_power_data = {
+        .init                   = collie_power_init,
+        .is_ac_online           = collie_power_ac_online,
+        .exit                   = collie_power_exit,
+        .supplied_to            = collie_ac_supplied_to,
+        .num_supplicants        = ARRAY_SIZE(collie_ac_supplied_to),
+};
+static struct resource collie_power_resource[] = {
+        {
+                .name           = "ac",
+                .start          = gpio_to_irq(COLLIE_GPIO_AC_IN),
+                .end            = gpio_to_irq(COLLIE_GPIO_AC_IN),
+                .flags          = IORESOURCE_IRQ |
+                                  IORESOURCE_IRQ_HIGHEDGE |
+                                  IORESOURCE_IRQ_LOWEDGE,
+        },
+};
+static struct platform_device collie_power_device = {
+        .name                   = "pda-power",
+        .id                     = -1,
+        .dev.platform_data      = &collie_power_data,
+        .resource               = collie_power_resource,
+        .num_resources          = ARRAY_SIZE(collie_power_resource),
 };
 #ifdef CONFIG_SHARP_LOCOMO
@@ -178,6 +244,7 @@ struct platform_device collie_locomo_device = {
 static struct platform_device *devices[] __initdata = {
        &collie_locomo_device,
        &colliescoop_device,
+        &collie_power_device,
 };
 static struct mtd_partition collie_partitions[] = {
@@ -248,22 +315,24 @@ static void __init collie_init(void)
        GPDR = GPIO_LDD8 | GPIO_LDD9 | GPIO_LDD10 | GPIO_LDD11 | GPIO_LDD12 |
                GPIO_LDD13 | GPIO_LDD14 | GPIO_LDD15 | GPIO_SSP_TXD |
                GPIO_SSP_SCLK | GPIO_SSP_SFRM | GPIO_SDLC_SCLK |
-                COLLIE_GPIO_UCB1x00_RESET | COLLIE_GPIO_nMIC_ON |
+                _COLLIE_GPIO_UCB1x00_RESET | _COLLIE_GPIO_nMIC_ON |
-                COLLIE_GPIO_nREMOCON_ON | GPIO_32_768kHz;
+                _COLLIE_GPIO_nREMOCON_ON | GPIO_32_768kHz;
        PPDR = PPC_LDD0 | PPC_LDD1 | PPC_LDD2 | PPC_LDD3 | PPC_LDD4 | PPC_LDD5 |
                PPC_LDD6 | PPC_LDD7 | PPC_L_PCLK | PPC_L_LCLK | PPC_L_FCLK | PPC_L_BIAS |
                PPC_TXD1 | PPC_TXD2 | PPC_TXD3 | PPC_TXD4 | PPC_SCLK | PPC_SFRM;
-        PWER = COLLIE_GPIO_AC_IN | COLLIE_GPIO_CO | COLLIE_GPIO_ON_KEY |
+        PWER = _COLLIE_GPIO_AC_IN | _COLLIE_GPIO_CO | _COLLIE_GPIO_ON_KEY |
-                COLLIE_GPIO_WAKEUP | COLLIE_GPIO_nREMOCON_INT | PWER_RTC;
+                _COLLIE_GPIO_WAKEUP | _COLLIE_GPIO_nREMOCON_INT | PWER_RTC;
-        PGSR = COLLIE_GPIO_nREMOCON_ON;
+        PGSR = _COLLIE_GPIO_nREMOCON_ON;
        PSDR = PPC_RXD1 | PPC_RXD2 | PPC_RXD3 | PPC_RXD4;
        PCFR = PCFR_OPDE;
+        GPSR |= _COLLIE_GPIO_UCB1x00_RESET;
        platform_scoop_config = &collie_pcmcia_config;
@@ -272,9 +341,9 @@ static void __init collie_init(void)
                printk(KERN_WARNING "collie: Unable to register LoCoMo device\n");
        }
-        sa11x0_set_flash_data(&collie_flash_data, collie_flash_resources,
+        sa11x0_register_mtd(&collie_flash_data, collie_flash_resources,
-                              ARRAY_SIZE(collie_flash_resources));
+                            ARRAY_SIZE(collie_flash_resources));
-        sa11x0_set_mcp_data(&collie_mcp_data);
+        sa11x0_register_mcp(&collie_mcp_data);
        sharpsl_save_param();
 }
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 23cfdd593954..9faea1511c1f 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -162,6 +162,17 @@ static void sa1100_power_off(void)
        PMCR = PMCR_SF;
 }
+static void sa11x0_register_device(struct platform_device *dev, void *data)
+{
+        int err;
+        dev->dev.platform_data = data;
+        err = platform_device_register(dev);
+        if (err)
+                printk(KERN_ERR "Unable to register device %s: %d\n",
+                        dev->name, err);
+}
 static struct resource sa11x0udc_resources[] = {
        [0] = {
                .start  = 0x80000000,
@@ -234,9 +245,9 @@ static struct platform_device sa11x0mcp_device = {
        .resource       = sa11x0mcp_resources,
 };
-void sa11x0_set_mcp_data(struct mcp_plat_data *data)
+void sa11x0_register_mcp(struct mcp_plat_data *data)
 {
-        sa11x0mcp_device.dev.platform_data = data;
+        sa11x0_register_device(&sa11x0mcp_device, data);
 }
 static struct resource sa11x0ssp_resources[] = {
@@ -293,13 +304,13 @@ static struct platform_device sa11x0mtd_device = {
        .id             = -1,
 };
-void sa11x0_set_flash_data(struct flash_platform_data *flash,
+void sa11x0_register_mtd(struct flash_platform_data *flash,
-                           struct resource *res, int nr)
+                         struct resource *res, int nr)
 {
        flash->name = "sa1100";
-        sa11x0mtd_device.dev.platform_data = flash;
        sa11x0mtd_device.resource = res;
        sa11x0mtd_device.num_resources = nr;
+        sa11x0_register_device(&sa11x0mtd_device, flash);
 }
 static struct resource sa11x0ir_resources[] = {
@@ -329,9 +340,9 @@ static struct platform_device sa11x0ir_device = {
        .resource       = sa11x0ir_resources,
 };
-void sa11x0_set_irda_data(struct irda_platform_data *irda)
+void sa11x0_register_irda(struct irda_platform_data *irda)
 {
-        sa11x0ir_device.dev.platform_data = irda;
+        sa11x0_register_device(&sa11x0ir_device, irda);
 }
 static struct platform_device sa11x0rtc_device = {
@@ -343,21 +354,15 @@ static struct platform_device *sa11x0_devices[] __initdata = {
        &sa11x0udc_device,
        &sa11x0uart1_device,
        &sa11x0uart3_device,
-        &sa11x0mcp_device,
        &sa11x0ssp_device,
        &sa11x0pcmcia_device,
        &sa11x0fb_device,
-        &sa11x0mtd_device,
        &sa11x0rtc_device,
 };
 static int __init sa1100_init(void)
 {
        pm_power_off = sa1100_power_off;
-        if (sa11x0ir_device.dev.platform_data)
-                platform_device_register(&sa11x0ir_device);
        return platform_add_devices(sa11x0_devices, ARRAY_SIZE(sa11x0_devices));
 }
diff --git a/arch/arm/mach-sa1100/generic.h b/arch/arm/mach-sa1100/generic.h
index 793c2e6c991f..ec03f187c52b 100644
--- a/arch/arm/mach-sa1100/generic.h
+++ b/arch/arm/mach-sa1100/generic.h
@@ -32,14 +32,11 @@ extern unsigned int sa11x0_ppcr_to_freq(unsigned int idx);
 struct flash_platform_data;
 struct resource;
-extern void sa11x0_set_flash_data(struct flash_platform_data *flash,
+void sa11x0_register_mtd(struct flash_platform_data *flash,
-                                  struct resource *res, int nr);
+                         struct resource *res, int nr);
-struct sa11x0_ssp_plat_ops;
-extern void sa11x0_set_ssp_data(struct sa11x0_ssp_plat_ops *ops);
 struct irda_platform_data;
-void sa11x0_set_irda_data(struct irda_platform_data *irda);
+void sa11x0_register_irda(struct irda_platform_data *irda);
 struct mcp_plat_data;
-void sa11x0_set_mcp_data(struct mcp_plat_data *data);
+void sa11x0_register_mcp(struct mcp_plat_data *data);
diff --git a/arch/arm/mach-sa1100/h3100.c b/arch/arm/mach-sa1100/h3100.c
new file mode 100644
index 000000000000..0c7cea0dc013
--- /dev/null
+++ b/arch/arm/mach-sa1100/h3100.c
@@ -0,0 +1,95 @@
+/*
+ * Support for Compaq iPAQ H3100 handheld computer
+ *
+ * Copyright (c) 2000,1 Compaq Computer Corporation. (Author: Jamey Hicks)
+ * Copyright (c) 2009 Dmitry Artamonow <mad_soft@inbox.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/irda.h>
+#include <mach/h3xxx.h>
+#include "generic.h"
+/*
+ * helper for sa1100fb
+ */
+static void h3100_lcd_power(int enable)
+{
+        if (!gpio_request(H3XXX_EGPIO_LCD_ON, "LCD ON")) {
+                gpio_set_value(H3100_GPIO_LCD_3V_ON, enable);
+                gpio_direction_output(H3XXX_EGPIO_LCD_ON, enable);
+                gpio_free(H3XXX_EGPIO_LCD_ON);
+        } else {
+                pr_err("%s: can't request H3XXX_EGPIO_LCD_ON\n", __func__);
+        }
+}
+static void __init h3100_map_io(void)
+{
+        h3xxx_map_io();
+        sa1100fb_lcd_power = h3100_lcd_power;
+        /* Older bootldrs put GPIO2-9 in alternate mode on the
+           assumption that they are used for video */
+        GAFR &= ~0x000001fb;
+}
+/*
+ * This turns the IRDA power on or off on the Compaq H3100
+ */
+static int h3100_irda_set_power(struct device *dev, unsigned int state)
+{
+        gpio_set_value(H3100_GPIO_IR_ON, state);
+        return 0;
+}
+static void h3100_irda_set_speed(struct device *dev, unsigned int speed)
+{
+        gpio_set_value(H3100_GPIO_IR_FSEL, !(speed < 4000000));
+}
+static struct irda_platform_data h3100_irda_data = {
+        .set_power      = h3100_irda_set_power,
+        .set_speed      = h3100_irda_set_speed,
+};
+static struct gpio_default_state h3100_default_gpio[] = {
+        { H3100_GPIO_IR_ON,     GPIO_MODE_OUT0, "IrDA power" },
+        { H3100_GPIO_IR_FSEL,   GPIO_MODE_OUT0, "IrDA fsel" },
+        { H3XXX_GPIO_COM_DCD,   GPIO_MODE_IN,   "COM DCD" },
+        { H3XXX_GPIO_COM_CTS,   GPIO_MODE_IN,   "COM CTS" },
+        { H3XXX_GPIO_COM_RTS,   GPIO_MODE_OUT0, "COM RTS" },
+        { H3100_GPIO_LCD_3V_ON, GPIO_MODE_OUT0, "LCD 3v" },
+};
+static void __init h3100_mach_init(void)
+{
+        h3xxx_init_gpio(h3100_default_gpio, ARRAY_SIZE(h3100_default_gpio));
+        h3xxx_mach_init();
+        sa11x0_register_irda(&h3100_irda_data);
+}
+MACHINE_START(H3100, "Compaq iPAQ H3100")
+        .phys_io        = 0x80000000,
+        .io_pg_offst    = ((0xf8000000) >> 18) & 0xfffc,
+        .boot_params    = 0xc0000100,
+        .map_io         = h3100_map_io,
+        .init_irq       = sa1100_init_irq,
+        .timer          = &sa1100_timer,
+        .init_machine   = h3100_mach_init,
+MACHINE_END
diff --git a/arch/arm/mach-sa1100/h3600.c b/arch/arm/mach-sa1100/h3600.c
index 0eb2f159578b..af3b71459f8d 100644
--- a/arch/arm/mach-sa1100/h3600.c
+++ b/arch/arm/mach-sa1100/h3600.c
@@ -1,421 +1,127 @@
 /*
- * Hardware definitions for Compaq iPAQ H3xxx Handheld Computers
+ * Support for Compaq iPAQ H3600 handheld computer
 *
- * Copyright 2000,1 Compaq Computer Corporation.
+ * Copyright (c) 2000,1 Compaq Computer Corporation. (Author: Jamey Hicks)
+ * Copyright (c) 2009 Dmitry Artamonow <mad_soft@inbox.ru>
 *
- * Use consistent with the GNU GPL is permitted,
+ * This program is free software; you can redistribute it and/or modify
- * provided that this copyright notice is
+ * it under the terms of the GNU General Public License version 2 as
- * preserved in its entirety in all copies and derived works.
+ * published by the Free Software Foundation.
- *
- * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
- * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
- * FITNESS FOR ANY PARTICULAR PURPOSE.
- *
- * Author: Jamey Hicks.
- *
- * History:
- *
- * 2001-10-??   Andrew Christian   Added support for iPAQ H3800
- *                                 and abstracted EGPIO interface.
 *
 */
-#include <linux/module.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
-#include <linux/tty.h>
+#include <linux/gpio.h>
-#include <linux/pm.h>
-#include <linux/device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/serial_core.h>
-#include <asm/irq.h>
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
-#include <asm/setup.h>
-#include <asm/mach/irq.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/flash.h>
 #include <asm/mach/irda.h>
-#include <asm/mach/map.h>
-#include <asm/mach/serial_sa1100.h>
-#include <mach/h3600.h>
+#include <mach/h3xxx.h>
-#include <mach/h3600_gpio.h>
 #include "generic.h"
-void (*assign_h3600_egpio)(enum ipaq_egpio_type x, int level);
-EXPORT_SYMBOL(assign_h3600_egpio);
-static struct mtd_partition h3xxx_partitions[] = {
-        {
-                .name           = "H3XXX boot firmware",
-                .size           = 0x00040000,
-                .offset         = 0,
-                .mask_flags     = MTD_WRITEABLE,  /* force read-only */
-        }, {
-                .name           = "H3XXX rootfs",
-                .size           = MTDPART_SIZ_FULL,
-                .offset         = 0x00040000,
-        }
-};
-static void h3xxx_set_vpp(int vpp)
-{
-        assign_h3600_egpio(IPAQ_EGPIO_VPP_ON, vpp);
-}
-static struct flash_platform_data h3xxx_flash_data = {
-        .map_name       = "cfi_probe",
-        .set_vpp        = h3xxx_set_vpp,
-        .parts          = h3xxx_partitions,
-        .nr_parts       = ARRAY_SIZE(h3xxx_partitions),
-};
-static struct resource h3xxx_flash_resource = {
-        .start          = SA1100_CS0_PHYS,
-        .end            = SA1100_CS0_PHYS + SZ_32M - 1,
-        .flags          = IORESOURCE_MEM,
-};
 /*
- * This turns the IRDA power on or off on the Compaq H3600
+ * helper for sa1100fb
- */
-static int h3600_irda_set_power(struct device *dev, unsigned int state)
-{
-        assign_h3600_egpio( IPAQ_EGPIO_IR_ON, state );
-        return 0;
-}
-static void h3600_irda_set_speed(struct device *dev, unsigned int speed)
-{
-        assign_h3600_egpio(IPAQ_EGPIO_IR_FSEL, !(speed < 4000000));
-}
-static struct irda_platform_data h3600_irda_data = {
-        .set_power      = h3600_irda_set_power,
-        .set_speed      = h3600_irda_set_speed,
-};
-static void h3xxx_mach_init(void)
-{
-        sa11x0_set_flash_data(&h3xxx_flash_data, &h3xxx_flash_resource, 1);
-        sa11x0_set_irda_data(&h3600_irda_data);
-}
-/*
- * low-level UART features
 */
+static void h3600_lcd_power(int enable)
-static void h3600_uart_set_mctrl(struct uart_port *port, u_int mctrl)
 {
-        if (port->mapbase == _Ser3UTCR0) {
+        if (gpio_request(H3XXX_EGPIO_LCD_ON, "LCD power")) {
-                if (mctrl & TIOCM_RTS)
+                pr_err("%s: can't request H3XXX_EGPIO_LCD_ON\n", __func__);
-                        GPCR = GPIO_H3600_COM_RTS;
+                goto err1;
-                else
-                        GPSR = GPIO_H3600_COM_RTS;
        }
-}
+        if (gpio_request(H3600_EGPIO_LCD_PCI, "LCD control")) {
+                pr_err("%s: can't request H3XXX_EGPIO_LCD_PCI\n", __func__);
-static u_int h3600_uart_get_mctrl(struct uart_port *port)
+                goto err2;
-{
+        }
-        u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR;
+        if (gpio_request(H3600_EGPIO_LCD_5V_ON, "LCD 5v")) {
+                pr_err("%s: can't request H3XXX_EGPIO_LCD_5V_ON\n", __func__);
-        if (port->mapbase == _Ser3UTCR0) {
+                goto err3;
-                int gplr = GPLR;
+        }
-                /* DCD and CTS bits are inverted in GPLR by RS232 transceiver */
+        if (gpio_request(H3600_EGPIO_LVDD_ON, "LCD 9v/-6.5v")) {
-                if (gplr & GPIO_H3600_COM_DCD)
+                pr_err("%s: can't request H3600_EGPIO_LVDD_ON\n", __func__);
-                        ret &= ~TIOCM_CD;
+                goto err4;
-                if (gplr & GPIO_H3600_COM_CTS)
-                        ret &= ~TIOCM_CTS;
        }
-        return ret;
+        gpio_direction_output(H3XXX_EGPIO_LCD_ON, enable);
-}
+        gpio_direction_output(H3600_EGPIO_LCD_PCI, enable);
+        gpio_direction_output(H3600_EGPIO_LCD_5V_ON, enable);
+        gpio_direction_output(H3600_EGPIO_LVDD_ON, enable);
-static void h3600_uart_pm(struct uart_port *port, u_int state, u_int oldstate)
+        gpio_free(H3600_EGPIO_LVDD_ON);
-{
+err4:   gpio_free(H3600_EGPIO_LCD_5V_ON);
-        if (port->mapbase == _Ser2UTCR0) { /* TODO: REMOVE THIS */
+err3:   gpio_free(H3600_EGPIO_LCD_PCI);
-                assign_h3600_egpio(IPAQ_EGPIO_IR_ON, !state);
+err2:   gpio_free(H3XXX_EGPIO_LCD_ON);
-        } else if (port->mapbase == _Ser3UTCR0) {
+err1:   return;
-                assign_h3600_egpio(IPAQ_EGPIO_RS232_ON, !state);
-        }
 }
-/*
+static void __init h3600_map_io(void)
- * Enable/Disable wake up events for this serial port.
- * Obviously, we only support this on the normal COM port.
- */
-static int h3600_uart_set_wake(struct uart_port *port, u_int enable)
 {
-        int err = -EINVAL;
+        h3xxx_map_io();
-        if (port->mapbase == _Ser3UTCR0) {
+        sa1100fb_lcd_power = h3600_lcd_power;
-                if (enable)
-                        PWER |= PWER_GPIO23 | PWER_GPIO25; /* DCD and CTS */
-                else
-                        PWER &= ~(PWER_GPIO23 | PWER_GPIO25); /* DCD and CTS */
-                err = 0;
-        }
-        return err;
 }
-static struct sa1100_port_fns h3600_port_fns __initdata = {
-        .set_mctrl      = h3600_uart_set_mctrl,
-        .get_mctrl      = h3600_uart_get_mctrl,
-        .pm             = h3600_uart_pm,
-        .set_wake       = h3600_uart_set_wake,
-};
 /*
- * helper for sa1100fb
+ * This turns the IRDA power on or off on the Compaq H3600
 */
-static void h3xxx_lcd_power(int enable)
+static int h3600_irda_set_power(struct device *dev, unsigned int state)
 {
-        assign_h3600_egpio(IPAQ_EGPIO_LCD_POWER, enable);
+        gpio_set_value(H3600_EGPIO_IR_ON, state);
+        return 0;
 }
-static struct map_desc h3600_io_desc[] __initdata = {
+static void h3600_irda_set_speed(struct device *dev, unsigned int speed)
-        {       /* static memory bank 2  CS#2 */
-                .virtual        =  H3600_BANK_2_VIRT,
-                .pfn            = __phys_to_pfn(SA1100_CS2_PHYS),
-                .length         = 0x02800000,
-                .type           = MT_DEVICE
-        }, {    /* static memory bank 4  CS#4 */
-                .virtual        =  H3600_BANK_4_VIRT,
-                .pfn            = __phys_to_pfn(SA1100_CS4_PHYS),
-                .length         = 0x00800000,
-                .type           = MT_DEVICE
-        }, {    /* EGPIO 0              CS#5 */
-                .virtual        =  H3600_EGPIO_VIRT,
-                .pfn            = __phys_to_pfn(H3600_EGPIO_PHYS),
-                .length         = 0x01000000,
-                .type           = MT_DEVICE
-        }
-};
-/*
- * Common map_io initialization
- */
-static void __init h3xxx_map_io(void)
 {
-        sa1100_map_io();
+        gpio_set_value(H3600_EGPIO_IR_FSEL, !(speed < 4000000));
-        iotable_init(h3600_io_desc, ARRAY_SIZE(h3600_io_desc));
-        sa1100_register_uart_fns(&h3600_port_fns);
-        sa1100_register_uart(0, 3); /* Common serial port */
-//      sa1100_register_uart(1, 1); /* Microcontroller on 3100/3600 */
-        /* Ensure those pins are outputs and driving low  */
-        PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
-        PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
-        /* Configure suspend conditions */
-        PGSR = 0;
-        PWER = PWER_GPIO0 | PWER_RTC;
-        PCFR = PCFR_OPDE;
-        PSDR = 0;
-        sa1100fb_lcd_power = h3xxx_lcd_power;
 }
-/************************* H3100 *************************/
+static int h3600_irda_startup(struct device *dev)
-#ifdef CONFIG_SA1100_H3100
-#define H3100_EGPIO     (*(volatile unsigned int *)H3600_EGPIO_VIRT)
-static unsigned int h3100_egpio = 0;
-static void h3100_control_egpio(enum ipaq_egpio_type x, int setp)
 {
-        unsigned int egpio = 0;
+        int err = gpio_request(H3600_EGPIO_IR_ON, "IrDA power");
-        long         gpio = 0;
+        if (err)
-        unsigned long flags;
+                goto err1;
+        err = gpio_direction_output(H3600_EGPIO_IR_ON, 0);
-        switch (x) {
+        if (err)
-        case IPAQ_EGPIO_LCD_POWER:
+                goto err2;
-                egpio |= EGPIO_H3600_LCD_ON;
+        err = gpio_request(H3600_EGPIO_IR_FSEL, "IrDA fsel");
-                gpio  |= GPIO_H3100_LCD_3V_ON;
+        if (err)
-                break;
+                goto err2;
-        case IPAQ_EGPIO_LCD_ENABLE:
+        err = gpio_direction_output(H3600_EGPIO_IR_FSEL, 0);
-                break;
+        if (err)
-        case IPAQ_EGPIO_CODEC_NRESET:
+                goto err3;
-                egpio |= EGPIO_H3600_CODEC_NRESET;
+        return 0;
-                break;
-        case IPAQ_EGPIO_AUDIO_ON:
-                gpio |= GPIO_H3100_AUD_PWR_ON
-                        | GPIO_H3100_AUD_ON;
-                break;
-        case IPAQ_EGPIO_QMUTE:
-                gpio |= GPIO_H3100_QMUTE;
-                break;
-        case IPAQ_EGPIO_OPT_NVRAM_ON:
-                egpio |= EGPIO_H3600_OPT_NVRAM_ON;
-                break;
-        case IPAQ_EGPIO_OPT_ON:
-                egpio |= EGPIO_H3600_OPT_ON;
-                break;
-        case IPAQ_EGPIO_CARD_RESET:
-                egpio |= EGPIO_H3600_CARD_RESET;
-                break;
-        case IPAQ_EGPIO_OPT_RESET:
-                egpio |= EGPIO_H3600_OPT_RESET;
-                break;
-        case IPAQ_EGPIO_IR_ON:
-                gpio |= GPIO_H3100_IR_ON;
-                break;
-        case IPAQ_EGPIO_IR_FSEL:
-                gpio |= GPIO_H3100_IR_FSEL;
-                break;
-        case IPAQ_EGPIO_RS232_ON:
-                egpio |= EGPIO_H3600_RS232_ON;
-                break;
-        case IPAQ_EGPIO_VPP_ON:
-                egpio |= EGPIO_H3600_VPP_ON;
-                break;
-        }
-        if (egpio || gpio) {
+err3:   gpio_free(H3600_EGPIO_IR_FSEL);
-                local_irq_save(flags);
+err2:   gpio_free(H3600_EGPIO_IR_ON);
-                if (setp) {
+err1:   return err;
-                        h3100_egpio |= egpio;
-                        GPSR = gpio;
-                } else {
-                        h3100_egpio &= ~egpio;
-                        GPCR = gpio;
-                }
-                H3100_EGPIO = h3100_egpio;
-                local_irq_restore(flags);
-        }
 }
-#define H3100_DIRECT_EGPIO (GPIO_H3100_BT_ON      \
+static void h3600_irda_shutdown(struct device *dev)
-                          | GPIO_H3100_GPIO3      \
-                          | GPIO_H3100_QMUTE      \
-                          | GPIO_H3100_LCD_3V_ON  \
-                          | GPIO_H3100_AUD_ON     \
-                          | GPIO_H3100_AUD_PWR_ON \
-                          | GPIO_H3100_IR_ON      \
-                          | GPIO_H3100_IR_FSEL)
-static void __init h3100_map_io(void)
 {
-        h3xxx_map_io();
+        gpio_free(H3600_EGPIO_IR_ON);
+        gpio_free(H3600_EGPIO_IR_FSEL);
-        /* Initialize h3100-specific values here */
-        GPCR = 0x0fffffff;       /* All outputs are set low by default */
-        GPDR = GPIO_H3600_COM_RTS  | GPIO_H3600_L3_CLOCK |
-               GPIO_H3600_L3_MODE  | GPIO_H3600_L3_DATA  |
-               GPIO_H3600_CLK_SET1 | GPIO_H3600_CLK_SET0 |
-               H3100_DIRECT_EGPIO;
-        /* Older bootldrs put GPIO2-9 in alternate mode on the
-           assumption that they are used for video */
-        GAFR &= ~H3100_DIRECT_EGPIO;
-        H3100_EGPIO = h3100_egpio;
-        assign_h3600_egpio = h3100_control_egpio;
 }
-MACHINE_START(H3100, "Compaq iPAQ H3100")
+static struct irda_platform_data h3600_irda_data = {
-        .phys_io        = 0x80000000,
+        .set_power      = h3600_irda_set_power,
-        .io_pg_offst    = ((0xf8000000) >> 18) & 0xfffc,
+        .set_speed      = h3600_irda_set_speed,
-        .boot_params    = 0xc0000100,
+        .startup        = h3600_irda_startup,
-        .map_io         = h3100_map_io,
+        .shutdown       = h3600_irda_shutdown,
-        .init_irq       = sa1100_init_irq,
+};
-        .timer          = &sa1100_timer,
-        .init_machine   = h3xxx_mach_init,
-MACHINE_END
-#endif /* CONFIG_SA1100_H3100 */
-/************************* H3600 *************************/
-#ifdef CONFIG_SA1100_H3600
-#define H3600_EGPIO     (*(volatile unsigned int *)H3600_EGPIO_VIRT)
-static unsigned int h3600_egpio = EGPIO_H3600_RS232_ON;
-static void h3600_control_egpio(enum ipaq_egpio_type x, int setp)
-{
-        unsigned int egpio = 0;
-        unsigned long flags;
-        switch (x) {
-        case IPAQ_EGPIO_LCD_POWER:
-                egpio |= EGPIO_H3600_LCD_ON |
-                         EGPIO_H3600_LCD_PCI |
-                         EGPIO_H3600_LCD_5V_ON |
-                         EGPIO_H3600_LVDD_ON;
-                break;
-        case IPAQ_EGPIO_LCD_ENABLE:
-                break;
-        case IPAQ_EGPIO_CODEC_NRESET:
-                egpio |= EGPIO_H3600_CODEC_NRESET;
-                break;
-        case IPAQ_EGPIO_AUDIO_ON:
-                egpio |= EGPIO_H3600_AUD_AMP_ON |
-                         EGPIO_H3600_AUD_PWR_ON;
-                break;
-        case IPAQ_EGPIO_QMUTE:
-                egpio |= EGPIO_H3600_QMUTE;
-                break;
-        case IPAQ_EGPIO_OPT_NVRAM_ON:
-                egpio |= EGPIO_H3600_OPT_NVRAM_ON;
-                break;
-        case IPAQ_EGPIO_OPT_ON:
-                egpio |= EGPIO_H3600_OPT_ON;
-                break;
-        case IPAQ_EGPIO_CARD_RESET:
-                egpio |= EGPIO_H3600_CARD_RESET;
-                break;
-        case IPAQ_EGPIO_OPT_RESET:
-                egpio |= EGPIO_H3600_OPT_RESET;
-                break;
-        case IPAQ_EGPIO_IR_ON:
-                egpio |= EGPIO_H3600_IR_ON;
-                break;
-        case IPAQ_EGPIO_IR_FSEL:
-                egpio |= EGPIO_H3600_IR_FSEL;
-                break;
-        case IPAQ_EGPIO_RS232_ON:
-                egpio |= EGPIO_H3600_RS232_ON;
-                break;
-        case IPAQ_EGPIO_VPP_ON:
-                egpio |= EGPIO_H3600_VPP_ON;
-                break;
-        }
-        if (egpio) {
+static struct gpio_default_state h3600_default_gpio[] = {
-                local_irq_save(flags);
+        { H3XXX_GPIO_COM_DCD,   GPIO_MODE_IN,   "COM DCD" },
-                if (setp)
+        { H3XXX_GPIO_COM_CTS,   GPIO_MODE_IN,   "COM CTS" },
-                        h3600_egpio |= egpio;
+        { H3XXX_GPIO_COM_RTS,   GPIO_MODE_OUT0, "COM RTS" },
-                else
+};
-                        h3600_egpio &= ~egpio;
-                H3600_EGPIO = h3600_egpio;
-                local_irq_restore(flags);
-        }
-}
-static void __init h3600_map_io(void)
+static void __init h3600_mach_init(void)
 {
-        h3xxx_map_io();
+        h3xxx_init_gpio(h3600_default_gpio, ARRAY_SIZE(h3600_default_gpio));
+        h3xxx_mach_init();
-        /* Initialize h3600-specific values here */
+        sa11x0_register_irda(&h3600_irda_data);
-        GPCR = 0x0fffffff;       /* All outputs are set low by default */
-        GPDR = GPIO_H3600_COM_RTS  | GPIO_H3600_L3_CLOCK |
-               GPIO_H3600_L3_MODE  | GPIO_H3600_L3_DATA  |
-               GPIO_H3600_CLK_SET1 | GPIO_H3600_CLK_SET0 |
-               GPIO_LDD15 | GPIO_LDD14 | GPIO_LDD13 | GPIO_LDD12 |
-               GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9  | GPIO_LDD8;
-        H3600_EGPIO = h3600_egpio;         /* Maintains across sleep? */
-        assign_h3600_egpio = h3600_control_egpio;
 }
 MACHINE_START(H3600, "Compaq iPAQ H3600")
@@ -425,8 +131,6 @@ MACHINE_START(H3600, "Compaq iPAQ H3600")
        .map_io         = h3600_map_io,
        .init_irq       = sa1100_init_irq,
        .timer          = &sa1100_timer,
-        .init_machine   = h3xxx_mach_init,
+        .init_machine   = h3600_mach_init,
 MACHINE_END
-#endif /* CONFIG_SA1100_H3600 */
diff --git a/arch/arm/mach-sa1100/h3xxx.c b/arch/arm/mach-sa1100/h3xxx.c
new file mode 100644
index 000000000000..b0784c974c2d
--- /dev/null
+++ b/arch/arm/mach-sa1100/h3xxx.c
@@ -0,0 +1,313 @@
+/*
+ * Support for Compaq iPAQ H3100 and H3600 handheld computers (common code)
+ *
+ * Copyright (c) 2000,1 Compaq Computer Corporation. (Author: Jamey Hicks)
+ * Copyright (c) 2009 Dmitry Artamonow <mad_soft@inbox.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/mfd/htc-egpio.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/platform_device.h>
+#include <linux/serial_core.h>
+#include <asm/mach/flash.h>
+#include <asm/mach/map.h>
+#include <asm/mach/serial_sa1100.h>
+#include <mach/h3xxx.h>
+#include "generic.h"
+void h3xxx_init_gpio(struct gpio_default_state *s, size_t n)
+{
+        while (n--) {
+                const char *name = s->name;
+                int err;
+                if (!name)
+                        name = "[init]";
+                err = gpio_request(s->gpio, name);
+                if (err) {
+                        printk(KERN_ERR "gpio%u: unable to request: %d\n",
+                                s->gpio, err);
+                        continue;
+                }
+                if (s->mode >= 0) {
+                        err = gpio_direction_output(s->gpio, s->mode);
+                } else {
+                        err = gpio_direction_input(s->gpio);
+                }
+                if (err) {
+                        printk(KERN_ERR "gpio%u: unable to set direction: %d\n",
+                                s->gpio, err);
+                        continue;
+                }
+                if (!s->name)
+                        gpio_free(s->gpio);
+                s++;
+        }
+}
+/*
+ * H3xxx flash support
+ */
+static struct mtd_partition h3xxx_partitions[] = {
+        {
+                .name           = "H3XXX boot firmware",
+                .size           = 0x00040000,
+                .offset         = 0,
+                .mask_flags     = MTD_WRITEABLE,  /* force read-only */
+        }, {
+                .name           = "H3XXX rootfs",
+                .size           = MTDPART_SIZ_FULL,
+                .offset         = 0x00040000,
+        }
+};
+static void h3xxx_set_vpp(int vpp)
+{
+        gpio_set_value(H3XXX_EGPIO_VPP_ON, vpp);
+}
+static int h3xxx_flash_init(void)
+{
+        int err = gpio_request(H3XXX_EGPIO_VPP_ON, "Flash Vpp");
+        if (err) {
+                pr_err("%s: can't request H3XXX_EGPIO_VPP_ON\n", __func__);
+                return err;
+        }
+        err = gpio_direction_output(H3XXX_EGPIO_VPP_ON, 0);
+        if (err)
+                gpio_free(H3XXX_EGPIO_VPP_ON);
+        return err;
+}
+static void h3xxx_flash_exit(void)
+{
+        gpio_free(H3XXX_EGPIO_VPP_ON);
+}
+static struct flash_platform_data h3xxx_flash_data = {
+        .map_name       = "cfi_probe",
+        .set_vpp        = h3xxx_set_vpp,
+        .init           = h3xxx_flash_init,
+        .exit           = h3xxx_flash_exit,
+        .parts          = h3xxx_partitions,
+        .nr_parts       = ARRAY_SIZE(h3xxx_partitions),
+};
+static struct resource h3xxx_flash_resource = {
+        .start          = SA1100_CS0_PHYS,
+        .end            = SA1100_CS0_PHYS + SZ_32M - 1,
+        .flags          = IORESOURCE_MEM,
+};
+/*
+ * H3xxx uart support
+ */
+static void h3xxx_uart_set_mctrl(struct uart_port *port, u_int mctrl)
+{
+        if (port->mapbase == _Ser3UTCR0) {
+                gpio_set_value(H3XXX_GPIO_COM_RTS, !(mctrl & TIOCM_RTS));
+        }
+}
+static u_int h3xxx_uart_get_mctrl(struct uart_port *port)
+{
+        u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR;
+        if (port->mapbase == _Ser3UTCR0) {
+                /*
+                 * DCD and CTS bits are inverted in GPLR by RS232 transceiver
+                 */
+                if (gpio_get_value(H3XXX_GPIO_COM_DCD))
+                        ret &= ~TIOCM_CD;
+                if (gpio_get_value(H3XXX_GPIO_COM_CTS))
+                        ret &= ~TIOCM_CTS;
+        }
+        return ret;
+}
+static void h3xxx_uart_pm(struct uart_port *port, u_int state, u_int oldstate)
+{
+        if (port->mapbase == _Ser3UTCR0) {
+                if (!gpio_request(H3XXX_EGPIO_RS232_ON, "RS232 transceiver")) {
+                        gpio_direction_output(H3XXX_EGPIO_RS232_ON, !state);
+                        gpio_free(H3XXX_EGPIO_RS232_ON);
+                } else {
+                        pr_err("%s: can't request H3XXX_EGPIO_RS232_ON\n",
+                                __func__);
+                }
+        }
+}
+/*
+ * Enable/Disable wake up events for this serial port.
+ * Obviously, we only support this on the normal COM port.
+ */
+static int h3xxx_uart_set_wake(struct uart_port *port, u_int enable)
+{
+        int err = -EINVAL;
+        if (port->mapbase == _Ser3UTCR0) {
+                if (enable)
+                        PWER |= PWER_GPIO23 | PWER_GPIO25; /* DCD and CTS */
+                else
+                        PWER &= ~(PWER_GPIO23 | PWER_GPIO25); /* DCD and CTS */
+                err = 0;
+        }
+        return err;
+}
+static struct sa1100_port_fns h3xxx_port_fns __initdata = {
+        .set_mctrl      = h3xxx_uart_set_mctrl,
+        .get_mctrl      = h3xxx_uart_get_mctrl,
+        .pm             = h3xxx_uart_pm,
+        .set_wake       = h3xxx_uart_set_wake,
+};
+/*
+ * EGPIO
+ */
+static struct resource egpio_resources[] = {
+        [0] = {
+                .start  = H3600_EGPIO_PHYS,
+                .end    = H3600_EGPIO_PHYS + 0x4 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+static struct htc_egpio_chip egpio_chips[] = {
+        [0] = {
+                .reg_start      = 0,
+                .gpio_base      = H3XXX_EGPIO_BASE,
+                .num_gpios      = 16,
+                .direction      = HTC_EGPIO_OUTPUT,
+                .initial_values = 0x0080, /* H3XXX_EGPIO_RS232_ON */
+        },
+};
+static struct htc_egpio_platform_data egpio_info = {
+        .reg_width      = 16,
+        .bus_width      = 16,
+        .chip           = egpio_chips,
+        .num_chips      = ARRAY_SIZE(egpio_chips),
+};
+static struct platform_device h3xxx_egpio = {
+        .name           = "htc-egpio",
+        .id             = -1,
+        .resource       = egpio_resources,
+        .num_resources  = ARRAY_SIZE(egpio_resources),
+        .dev            = {
+                .platform_data = &egpio_info,
+        },
+};
+/*
+ * GPIO keys
+ */
+static struct gpio_keys_button h3xxx_button_table[] = {
+        {
+                .code           = KEY_POWER,
+                .gpio           = H3XXX_GPIO_PWR_BUTTON,
+                .desc           = "Power Button",
+                .active_low     = 1,
+                .type           = EV_KEY,
+                .wakeup         = 1,
+        }, {
+                .code           = KEY_ENTER,
+                .gpio           = H3XXX_GPIO_ACTION_BUTTON,
+                .active_low     = 1,
+                .desc           = "Action button",
+                .type           = EV_KEY,
+                .wakeup         = 0,
+        },
+};
+static struct gpio_keys_platform_data h3xxx_keys_data = {
+        .buttons  = h3xxx_button_table,
+        .nbuttons = ARRAY_SIZE(h3xxx_button_table),
+};
+static struct platform_device h3xxx_keys = {
+        .name   = "gpio-keys",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &h3xxx_keys_data,
+        },
+};
+static struct platform_device *h3xxx_devices[] = {
+        &h3xxx_egpio,
+        &h3xxx_keys,
+};
+void __init h3xxx_mach_init(void)
+{
+        sa1100_register_uart_fns(&h3xxx_port_fns);
+        sa11x0_register_mtd(&h3xxx_flash_data, &h3xxx_flash_resource, 1);
+        platform_add_devices(h3xxx_devices, ARRAY_SIZE(h3xxx_devices));
+}
+static struct map_desc h3600_io_desc[] __initdata = {
+        {       /* static memory bank 2  CS#2 */
+                .virtual        =  H3600_BANK_2_VIRT,
+                .pfn            = __phys_to_pfn(SA1100_CS2_PHYS),
+                .length         = 0x02800000,
+                .type           = MT_DEVICE
+        }, {    /* static memory bank 4  CS#4 */
+                .virtual        =  H3600_BANK_4_VIRT,
+                .pfn            = __phys_to_pfn(SA1100_CS4_PHYS),
+                .length         = 0x00800000,
+                .type           = MT_DEVICE
+        }, {    /* EGPIO 0              CS#5 */
+                .virtual        =  H3600_EGPIO_VIRT,
+                .pfn            = __phys_to_pfn(H3600_EGPIO_PHYS),
+                .length         = 0x01000000,
+                .type           = MT_DEVICE
+        }
+};
+/*
+ * Common map_io initialization
+ */
+void __init h3xxx_map_io(void)
+{
+        sa1100_map_io();
+        iotable_init(h3600_io_desc, ARRAY_SIZE(h3600_io_desc));
+        sa1100_register_uart(0, 3); /* Common serial port */
+//      sa1100_register_uart(1, 1); /* Microcontroller on 3100/3600 */
+        /* Ensure those pins are outputs and driving low  */
+        PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
+        PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
+        /* Configure suspend conditions */
+        PGSR = 0;
+        PCFR = PCFR_OPDE;
+        PSDR = 0;
+        GPCR = 0x0fffffff;      /* All outputs are set low by default */
+        GPDR = 0;               /* Configure all GPIOs as input */
+}
diff --git a/arch/arm/mach-sa1100/hackkit.c b/arch/arm/mach-sa1100/hackkit.c
index e7056c0b562c..51568dfc8e97 100644
--- a/arch/arm/mach-sa1100/hackkit.c
+++ b/arch/arm/mach-sa1100/hackkit.c
@@ -187,7 +187,7 @@ static struct resource hackkit_flash_resource = {
 static void __init hackkit_init(void)
 {
-        sa11x0_set_flash_data(&hackkit_flash_data, &hackkit_flash_resource, 1);
+        sa11x0_register_mtd(&hackkit_flash_data, &hackkit_flash_resource, 1);
 }
 /**********************************************************************
diff --git a/arch/arm/mach-sa1100/include/mach/collie.h b/arch/arm/mach-sa1100/include/mach/collie.h
index 9efb569cdb60..71a0b3fdcc8c 100644
--- a/arch/arm/mach-sa1100/include/mach/collie.h
+++ b/arch/arm/mach-sa1100/include/mach/collie.h
@@ -25,29 +25,39 @@
 #define COLLIE_GPIO_VPEN        (COLLIE_SCOOP_GPIO_BASE + 7)
 #define COLLIE_SCP_LB_VOL_CHG   SCOOP_GPCR_PA19
-#define COLLIE_SCOOP_IO_DIR     ( COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | \
+#define COLLIE_SCOOP_IO_DIR     (COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | \
                                COLLIE_SCP_5VON | COLLIE_SCP_AMP_ON | \
-                                COLLIE_SCP_LB_VOL_CHG )
+                                COLLIE_SCP_LB_VOL_CHG)
-#define COLLIE_SCOOP_IO_OUT     ( COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R )
+#define COLLIE_SCOOP_IO_OUT     (COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R)
-/* GPIOs for which the generic definition doesn't say much */
+/* GPIOs for gpiolib  */
-#define COLLIE_GPIO_ON_KEY              GPIO_GPIO (0)
+#define COLLIE_GPIO_ON_KEY              (0)
-#define COLLIE_GPIO_AC_IN               GPIO_GPIO (1)
+#define COLLIE_GPIO_AC_IN               (1)
-#define COLLIE_GPIO_SDIO_INT            GPIO_GPIO (11)
+#define COLLIE_GPIO_SDIO_INT            (11)
-#define COLLIE_GPIO_CF_IRQ              GPIO_GPIO (14)
+#define COLLIE_GPIO_CF_IRQ              (14)
-#define COLLIE_GPIO_nREMOCON_INT        GPIO_GPIO (15)
+#define COLLIE_GPIO_nREMOCON_INT        (15)
-#define COLLIE_GPIO_UCB1x00_RESET       GPIO_GPIO (16)
+#define COLLIE_GPIO_UCB1x00_RESET       (16)
-#define COLLIE_GPIO_nMIC_ON             GPIO_GPIO (17)
+#define COLLIE_GPIO_nMIC_ON             (17)
-#define COLLIE_GPIO_nREMOCON_ON         GPIO_GPIO (18)
+#define COLLIE_GPIO_nREMOCON_ON         (18)
-#define COLLIE_GPIO_CO                  GPIO_GPIO (20)
+#define COLLIE_GPIO_CO                  (20)
-#define COLLIE_GPIO_MCP_CLK             GPIO_GPIO (21)
+#define COLLIE_GPIO_MCP_CLK             (21)
-#define COLLIE_GPIO_CF_CD               GPIO_GPIO (22)
+#define COLLIE_GPIO_CF_CD               (22)
-#define COLLIE_GPIO_UCB1x00_IRQ         GPIO_GPIO (23)
+#define COLLIE_GPIO_UCB1x00_IRQ         (23)
-#define COLLIE_GPIO_WAKEUP              GPIO_GPIO (24)
+#define COLLIE_GPIO_WAKEUP              (24)
-#define COLLIE_GPIO_GA_INT              GPIO_GPIO (25)
+#define COLLIE_GPIO_GA_INT              (25)
-#define COLLIE_GPIO_MAIN_BAT_LOW        GPIO_GPIO (26)
+#define COLLIE_GPIO_MAIN_BAT_LOW        (26)
+/* GPIO definitions for direct register access */
+#define _COLLIE_GPIO_ON_KEY             GPIO_GPIO(0)
+#define _COLLIE_GPIO_AC_IN              GPIO_GPIO(1)
+#define _COLLIE_GPIO_nREMOCON_INT       GPIO_GPIO(15)
+#define _COLLIE_GPIO_UCB1x00_RESET      GPIO_GPIO(16)
+#define _COLLIE_GPIO_nMIC_ON            GPIO_GPIO(17)
+#define _COLLIE_GPIO_nREMOCON_ON        GPIO_GPIO(18)
+#define _COLLIE_GPIO_CO                 GPIO_GPIO(20)
+#define _COLLIE_GPIO_WAKEUP             GPIO_GPIO(24)
 /* Interrupts */
 #define COLLIE_IRQ_GPIO_ON_KEY          IRQ_GPIO0
@@ -70,19 +80,20 @@
 #define COLLIE_LCM_IRQ_GPIO_nSD_WP      IRQ_LOCOMO_GPIO14
 /* GPIO's on the TC35143AF (Toshiba Analog Frontend) */
-#define COLLIE_TC35143_GPIO_VERSION0    UCB_IO_0        /* GPIO0=Version                 */
+#define COLLIE_TC35143_GPIO_BASE        (GPIO_MAX + 13)
-#define COLLIE_TC35143_GPIO_TBL_CHK     UCB_IO_1        /* GPIO1=TBL_CHK                 */
+#define COLLIE_TC35143_GPIO_VERSION0    UCB_IO_0
-#define COLLIE_TC35143_GPIO_VPEN_ON     UCB_IO_2        /* GPIO2=VPNE_ON                 */
+#define COLLIE_TC35143_GPIO_TBL_CHK     UCB_IO_1
-#define COLLIE_TC35143_GPIO_IR_ON       UCB_IO_3        /* GPIO3=IR_ON                   */
+#define COLLIE_TC35143_GPIO_VPEN_ON     UCB_IO_2
-#define COLLIE_TC35143_GPIO_AMP_ON      UCB_IO_4        /* GPIO4=AMP_ON                  */
+#define COLLIE_TC35143_GPIO_IR_ON       UCB_IO_3
-#define COLLIE_TC35143_GPIO_VERSION1    UCB_IO_5        /* GPIO5=Version                 */
+#define COLLIE_TC35143_GPIO_AMP_ON      UCB_IO_4
-#define COLLIE_TC35143_GPIO_FS8KLPF     UCB_IO_5        /* GPIO5=fs 8k LPF               */
+#define COLLIE_TC35143_GPIO_VERSION1    UCB_IO_5
-#define COLLIE_TC35143_GPIO_BUZZER_BIAS UCB_IO_6        /* GPIO6=BUZZER BIAS             */
+#define COLLIE_TC35143_GPIO_FS8KLPF     UCB_IO_5
-#define COLLIE_TC35143_GPIO_MBAT_ON     UCB_IO_7        /* GPIO7=MBAT_ON                 */
+#define COLLIE_TC35143_GPIO_BUZZER_BIAS UCB_IO_6
-#define COLLIE_TC35143_GPIO_BBAT_ON     UCB_IO_8        /* GPIO8=BBAT_ON                 */
+#define COLLIE_GPIO_MBAT_ON             (COLLIE_TC35143_GPIO_BASE + 7)
-#define COLLIE_TC35143_GPIO_TMP_ON      UCB_IO_9        /* GPIO9=TMP_ON                  */
+#define COLLIE_GPIO_BBAT_ON             (COLLIE_TC35143_GPIO_BASE + 8)
-#define COLLIE_TC35143_GPIO_IN          ( UCB_IO_0 | UCB_IO_2 | UCB_IO_5 )
+#define COLLIE_GPIO_TMP_ON              (COLLIE_TC35143_GPIO_BASE + 9)
-#define COLLIE_TC35143_GPIO_OUT         ( UCB_IO_1 | UCB_IO_3 | UCB_IO_4 | UCB_IO_6 | \
+#define COLLIE_TC35143_GPIO_IN          (UCB_IO_0 | UCB_IO_2 | UCB_IO_5)
-                                        UCB_IO_7 | UCB_IO_8 | UCB_IO_9 )
+#define COLLIE_TC35143_GPIO_OUT         (UCB_IO_1 | UCB_IO_3 | UCB_IO_4 \
+                                                | UCB_IO_6)
 #endif
diff --git a/arch/arm/mach-sa1100/include/mach/gpio.h b/arch/arm/mach-sa1100/include/mach/gpio.h
index 582a0c92da53..7befc104e9a9 100644
--- a/arch/arm/mach-sa1100/include/mach/gpio.h
+++ b/arch/arm/mach-sa1100/include/mach/gpio.h
@@ -49,20 +49,9 @@ static inline void gpio_set_value(unsigned gpio, int value)
 #define gpio_cansleep   __gpio_cansleep
-static inline unsigned gpio_to_irq(unsigned gpio)
+#define gpio_to_irq(gpio)       ((gpio < 11) ? (IRQ_GPIO0 + gpio) : \
-{
+                                        (IRQ_GPIO11 - 11 + gpio))
-        if (gpio < 11)
+#define irq_to_gpio(irq)        ((irq < IRQ_GPIO11_27) ? (irq - IRQ_GPIO0) : \
-                return IRQ_GPIO0 + gpio;
+                                        (irq - IRQ_GPIO11 + 11))
-        else
-                return IRQ_GPIO11 - 11 + gpio;
-}
-static inline unsigned irq_to_gpio(unsigned irq)
-{
-        if (irq < IRQ_GPIO11_27)
-                return irq - IRQ_GPIO0;
-        else
-                return irq - IRQ_GPIO11 + 11;
-}
 #endif
diff --git a/arch/arm/mach-sa1100/include/mach/h3600.h b/arch/arm/mach-sa1100/include/mach/h3600.h
deleted file mode 100644
index 2827faa47421..000000000000
--- a/arch/arm/mach-sa1100/include/mach/h3600.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- *
- * Definitions for H3600 Handheld Computer
- *
- * Copyright 2000 Compaq Computer Corporation.
- *
- * Use consistent with the GNU GPL is permitted,
- * provided that this copyright notice is
- * preserved in its entirety in all copies and derived works.
- *
- * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
- * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
- * FITNESS FOR ANY PARTICULAR PURPOSE.
- *
- * Author: Jamey Hicks.
- *
- * History:
- *
- * 2001-10-??   Andrew Christian   Added support for iPAQ H3800
- *
- */
-#ifndef _INCLUDE_H3600_H_
-#define _INCLUDE_H3600_H_
-typedef int __bitwise pm_request_t;
-#define PM_SUSPEND      ((__force pm_request_t) 1)      /* enter D1-D3 */
-#define PM_RESUME       ((__force pm_request_t) 2)      /* enter D0 */
-/* generalized support for H3xxx series Compaq Pocket PC's */
-#define machine_is_h3xxx() (machine_is_h3100() || machine_is_h3600())
-/* Physical memory regions corresponding to chip selects */
-#define H3600_EGPIO_PHYS        (SA1100_CS5_PHYS + 0x01000000)
-#define H3600_BANK_2_PHYS       SA1100_CS2_PHYS
-#define H3600_BANK_4_PHYS       SA1100_CS4_PHYS
-/* Virtual memory regions corresponding to chip selects 2 & 4 (used on sleeves) */
-#define H3600_EGPIO_VIRT        0xf0000000
-#define H3600_BANK_2_VIRT       0xf1000000
-#define H3600_BANK_4_VIRT       0xf3800000
-/*
-   Machine-independent GPIO definitions
-   --- these are common across all current iPAQ platforms
-*/
-#define GPIO_H3600_NPOWER_BUTTON        GPIO_GPIO (0)   /* Also known as the "off button"  */
-#define GPIO_H3600_PCMCIA_CD1           GPIO_GPIO (10)
-#define GPIO_H3600_PCMCIA_IRQ1          GPIO_GPIO (11)
-/* UDA1341 L3 Interface */
-#define GPIO_H3600_L3_DATA              GPIO_GPIO (14)
-#define GPIO_H3600_L3_MODE              GPIO_GPIO (15)
-#define GPIO_H3600_L3_CLOCK             GPIO_GPIO (16)
-#define GPIO_H3600_PCMCIA_CD0           GPIO_GPIO (17)
-#define GPIO_H3600_SYS_CLK              GPIO_GPIO (19)
-#define GPIO_H3600_PCMCIA_IRQ0          GPIO_GPIO (21)
-#define GPIO_H3600_COM_DCD              GPIO_GPIO (23)
-#define GPIO_H3600_OPT_IRQ              GPIO_GPIO (24)
-#define GPIO_H3600_COM_CTS              GPIO_GPIO (25)
-#define GPIO_H3600_COM_RTS              GPIO_GPIO (26)
-#define IRQ_GPIO_H3600_NPOWER_BUTTON    IRQ_GPIO0
-#define IRQ_GPIO_H3600_PCMCIA_CD1       IRQ_GPIO10
-#define IRQ_GPIO_H3600_PCMCIA_IRQ1      IRQ_GPIO11
-#define IRQ_GPIO_H3600_PCMCIA_CD0       IRQ_GPIO17
-#define IRQ_GPIO_H3600_PCMCIA_IRQ0      IRQ_GPIO21
-#define IRQ_GPIO_H3600_COM_DCD          IRQ_GPIO23
-#define IRQ_GPIO_H3600_OPT_IRQ          IRQ_GPIO24
-#define IRQ_GPIO_H3600_COM_CTS          IRQ_GPIO25
-#ifndef __ASSEMBLY__
-enum ipaq_egpio_type {
-        IPAQ_EGPIO_LCD_POWER,     /* Power to the LCD panel */
-        IPAQ_EGPIO_CODEC_NRESET,  /* Clear to reset the audio codec (remember to return high) */
-        IPAQ_EGPIO_AUDIO_ON,      /* Audio power */
-        IPAQ_EGPIO_QMUTE,         /* Audio muting */
-        IPAQ_EGPIO_OPT_NVRAM_ON,  /* Non-volatile RAM on extension sleeves (SPI interface) */
-        IPAQ_EGPIO_OPT_ON,        /* Power to extension sleeves */
-        IPAQ_EGPIO_CARD_RESET,    /* Reset PCMCIA cards on extension sleeve (???) */
-        IPAQ_EGPIO_OPT_RESET,     /* Reset option pack (???) */
-        IPAQ_EGPIO_IR_ON,         /* IR sensor/emitter power */
-        IPAQ_EGPIO_IR_FSEL,       /* IR speed selection 1->fast, 0->slow */
-        IPAQ_EGPIO_RS232_ON,      /* Maxim RS232 chip power */
-        IPAQ_EGPIO_VPP_ON,        /* Turn on power to flash programming */
-        IPAQ_EGPIO_LCD_ENABLE,    /* Enable/disable LCD controller */
-};
-extern void (*assign_h3600_egpio)(enum ipaq_egpio_type x, int level);
-#endif /* ASSEMBLY */
-#endif /* _INCLUDE_H3600_H_ */
diff --git a/arch/arm/mach-sa1100/include/mach/h3600_gpio.h b/arch/arm/mach-sa1100/include/mach/h3600_gpio.h
deleted file mode 100644
index a36ca76d018b..000000000000
--- a/arch/arm/mach-sa1100/include/mach/h3600_gpio.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- *
- * Definitions for H3600 Handheld Computer
- *
- * Copyright 2000 Compaq Computer Corporation.
- *
- * Use consistent with the GNU GPL is permitted,
- * provided that this copyright notice is
- * preserved in its entirety in all copies and derived works.
- *
- * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
- * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
- * FITNESS FOR ANY PARTICULAR PURPOSE.
- *
- * Author: Jamey Hicks.
- *
- * History:
- *
- * 2001-10-??   Andrew Christian   Added support for iPAQ H3800
- *
- */
-#ifndef _INCLUDE_H3600_GPIO_H_
-#define _INCLUDE_H3600_GPIO_H_
-/*
- * GPIO lines that are common across ALL iPAQ models are in "h3600.h"
- * This file contains machine-specific definitions
- */
-#define GPIO_H3600_SUSPEND              GPIO_GPIO (0)
-/* GPIO[2:9] used by LCD on H3600/3800, used as GPIO on H3100 */
-#define GPIO_H3100_BT_ON                GPIO_GPIO (2)
-#define GPIO_H3100_GPIO3                GPIO_GPIO (3)
-#define GPIO_H3100_QMUTE                GPIO_GPIO (4)
-#define GPIO_H3100_LCD_3V_ON            GPIO_GPIO (5)
-#define GPIO_H3100_AUD_ON               GPIO_GPIO (6)
-#define GPIO_H3100_AUD_PWR_ON           GPIO_GPIO (7)
-#define GPIO_H3100_IR_ON                GPIO_GPIO (8)
-#define GPIO_H3100_IR_FSEL              GPIO_GPIO (9)
-/* for H3600, audio sample rate clock generator */
-#define GPIO_H3600_CLK_SET0             GPIO_GPIO (12)
-#define GPIO_H3600_CLK_SET1             GPIO_GPIO (13)
-#define GPIO_H3600_ACTION_BUTTON        GPIO_GPIO (18)
-#define GPIO_H3600_SOFT_RESET           GPIO_GPIO (20)   /* Also known as BATT_FAULT */
-#define GPIO_H3600_OPT_LOCK             GPIO_GPIO (22)
-#define GPIO_H3600_OPT_DET              GPIO_GPIO (27)
-/****************************************************/
-#define IRQ_GPIO_H3600_ACTION_BUTTON    IRQ_GPIO18
-#define IRQ_GPIO_H3600_OPT_DET          IRQ_GPIO27
-/* H3100 / 3600 EGPIO pins */
-#define EGPIO_H3600_VPP_ON              (1 << 0)
-#define EGPIO_H3600_CARD_RESET          (1 << 1)   /* reset the attached pcmcia/compactflash card.  active high. */
-#define EGPIO_H3600_OPT_RESET           (1 << 2)   /* reset the attached option pack.  active high. */
-#define EGPIO_H3600_CODEC_NRESET        (1 << 3)   /* reset the onboard UDA1341.  active low. */
-#define EGPIO_H3600_OPT_NVRAM_ON        (1 << 4)   /* apply power to optionpack nvram, active high. */
-#define EGPIO_H3600_OPT_ON              (1 << 5)   /* full power to option pack.  active high. */
-#define EGPIO_H3600_LCD_ON              (1 << 6)   /* enable 3.3V to LCD.  active high. */
-#define EGPIO_H3600_RS232_ON            (1 << 7)   /* UART3 transceiver force on.  Active high. */
-/* H3600 only EGPIO pins */
-#define EGPIO_H3600_LCD_PCI             (1 << 8)   /* LCD control IC enable.  active high. */
-#define EGPIO_H3600_IR_ON               (1 << 9)   /* apply power to IR module.  active high. */
-#define EGPIO_H3600_AUD_AMP_ON          (1 << 10)  /* apply power to audio power amp.  active high. */
-#define EGPIO_H3600_AUD_PWR_ON          (1 << 11)  /* apply power to reset of audio circuit.  active high. */
-#define EGPIO_H3600_QMUTE               (1 << 12)  /* mute control for onboard UDA1341.  active high. */
-#define EGPIO_H3600_IR_FSEL             (1 << 13)  /* IR speed select: 1->fast, 0->slow */
-#define EGPIO_H3600_LCD_5V_ON           (1 << 14)  /* enable 5V to LCD. active high. */
-#define EGPIO_H3600_LVDD_ON             (1 << 15)  /* enable 9V and -6.5V to LCD. */
-#endif /* _INCLUDE_H3600_GPIO_H_ */
diff --git a/arch/arm/mach-sa1100/include/mach/h3xxx.h b/arch/arm/mach-sa1100/include/mach/h3xxx.h
new file mode 100644
index 000000000000..7d9df16f04a2
--- /dev/null
+++ b/arch/arm/mach-sa1100/include/mach/h3xxx.h
@@ -0,0 +1,94 @@
+/*
+ * Definitions for Compaq iPAQ H3100 and H3600 handheld computers
+ *
+ * (c) 2000 Compaq Computer Corporation. (Author: Jamey Hicks)
+ * (c) 2009 Dmitry Artamonow <mad_soft@inbox.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef _INCLUDE_H3XXX_H_
+#define _INCLUDE_H3XXX_H_
+/* Physical memory regions corresponding to chip selects */
+#define H3600_EGPIO_PHYS        (SA1100_CS5_PHYS + 0x01000000)
+#define H3600_BANK_2_PHYS       SA1100_CS2_PHYS
+#define H3600_BANK_4_PHYS       SA1100_CS4_PHYS
+/* Virtual memory regions corresponding to chip selects 2 & 4 (used on sleeves) */
+#define H3600_EGPIO_VIRT        0xf0000000
+#define H3600_BANK_2_VIRT       0xf1000000
+#define H3600_BANK_4_VIRT       0xf3800000
+/*
+ * gpiolib numbers for all iPAQs
+ */
+#define H3XXX_GPIO_PWR_BUTTON           0
+#define H3XXX_GPIO_PCMCIA_CD1           10
+#define H3XXX_GPIO_PCMCIA_IRQ1          11
+#define H3XXX_GPIO_PCMCIA_CD0           17
+#define H3XXX_GPIO_ACTION_BUTTON        18
+#define H3XXX_GPIO_SYS_CLK              19
+#define H3XXX_GPIO_PCMCIA_IRQ0          21
+#define H3XXX_GPIO_COM_DCD              23
+#define H3XXX_GPIO_OPTION               24
+#define H3XXX_GPIO_COM_CTS              25
+#define H3XXX_GPIO_COM_RTS              26
+/* machine-specific gpios */
+#define H3100_GPIO_BT_ON                2
+#define H3100_GPIO_QMUTE                4
+#define H3100_GPIO_LCD_3V_ON            5
+#define H3100_GPIO_AUD_ON               6
+#define H3100_GPIO_AUD_PWR_ON           7
+#define H3100_GPIO_IR_ON                8
+#define H3100_GPIO_IR_FSEL              9
+#define H3600_GPIO_CLK_SET0             12      /* audio sample rate clock generator */
+#define H3600_GPIO_CLK_SET1             13
+#define H3600_GPIO_SOFT_RESET           20      /* also known as BATT_FAULT */
+#define H3600_GPIO_OPT_LOCK             22
+#define H3600_GPIO_OPT_DET              27
+/* H3100 / 3600 EGPIO pins */
+#define H3XXX_EGPIO_BASE                (GPIO_MAX + 1)
+#define H3XXX_EGPIO_VPP_ON              (H3XXX_EGPIO_BASE + 0)
+#define H3XXX_EGPIO_CARD_RESET          (H3XXX_EGPIO_BASE + 1) /* reset the attached pcmcia/compactflash card.  active high. */
+#define H3XXX_EGPIO_OPT_RESET           (H3XXX_EGPIO_BASE + 2) /* reset the attached option pack.  active high. */
+#define H3XXX_EGPIO_CODEC_NRESET        (H3XXX_EGPIO_BASE + 3) /* reset the onboard UDA1341.  active low. */
+#define H3XXX_EGPIO_OPT_NVRAM_ON        (H3XXX_EGPIO_BASE + 4) /* apply power to optionpack nvram, active high. */
+#define H3XXX_EGPIO_OPT_ON              (H3XXX_EGPIO_BASE + 5) /* full power to option pack.  active high. */
+#define H3XXX_EGPIO_LCD_ON              (H3XXX_EGPIO_BASE + 6) /* enable 3.3V to LCD.  active high. */
+#define H3XXX_EGPIO_RS232_ON            (H3XXX_EGPIO_BASE + 7) /* UART3 transceiver force on.  Active high. */
+/* H3600 only EGPIO pins */
+#define H3600_EGPIO_LCD_PCI             (H3XXX_EGPIO_BASE + 8) /* LCD control IC enable.  active high. */
+#define H3600_EGPIO_IR_ON               (H3XXX_EGPIO_BASE + 9) /* apply power to IR module.  active high. */
+#define H3600_EGPIO_AUD_AMP_ON          (H3XXX_EGPIO_BASE + 10) /* apply power to audio power amp.  active high. */
+#define H3600_EGPIO_AUD_PWR_ON          (H3XXX_EGPIO_BASE + 11) /* apply power to reset of audio circuit.  active high. */
+#define H3600_EGPIO_QMUTE               (H3XXX_EGPIO_BASE + 12) /* mute control for onboard UDA1341.  active high. */
+#define H3600_EGPIO_IR_FSEL             (H3XXX_EGPIO_BASE + 13) /* IR speed select: 1->fast, 0->slow */
+#define H3600_EGPIO_LCD_5V_ON           (H3XXX_EGPIO_BASE + 14) /* enable 5V to LCD. active high. */
+#define H3600_EGPIO_LVDD_ON             (H3XXX_EGPIO_BASE + 15) /* enable 9V and -6.5V to LCD. */
+struct gpio_default_state {
+        int gpio;
+        int mode;
+        const char *name;
+};
+#define GPIO_MODE_IN    -1
+#define GPIO_MODE_OUT0  0
+#define GPIO_MODE_OUT1  1
+void h3xxx_init_gpio(struct gpio_default_state *s, size_t n);
+void __init h3xxx_map_io(void);
+void __init h3xxx_mach_init(void);
+#endif /* _INCLUDE_H3XXX_H_ */
diff --git a/arch/arm/mach-sa1100/include/mach/mcp.h b/arch/arm/mach-sa1100/include/mach/mcp.h
index fb8b09a57ad7..ed1a331508a7 100644
--- a/arch/arm/mach-sa1100/include/mach/mcp.h
+++ b/arch/arm/mach-sa1100/include/mach/mcp.h
@@ -16,6 +16,7 @@ struct mcp_plat_data {
        u32 mccr0;
        u32 mccr1;
        unsigned int sclk_rate;
+        int gpio_base;
 };
 #endif
diff --git a/arch/arm/mach-sa1100/jornada720.c b/arch/arm/mach-sa1100/jornada720.c
index fd776bb666cd..13ebd2d99bfd 100644
--- a/arch/arm/mach-sa1100/jornada720.c
+++ b/arch/arm/mach-sa1100/jornada720.c
@@ -354,7 +354,7 @@ static struct resource jornada720_flash_resource = {
 static void __init jornada720_mach_init(void)
 {
-        sa11x0_set_flash_data(&jornada720_flash_data, &jornada720_flash_resource, 1);
+        sa11x0_register_mtd(&jornada720_flash_data, &jornada720_flash_resource, 1);
 }
 MACHINE_START(JORNADA720, "HP Jornada 720")
diff --git a/arch/arm/mach-sa1100/lart.c b/arch/arm/mach-sa1100/lart.c
index 1f940df0e5af..68069d6dc07a 100644
--- a/arch/arm/mach-sa1100/lart.c
+++ b/arch/arm/mach-sa1100/lart.c
@@ -28,7 +28,7 @@ static struct mcp_plat_data lart_mcp_data = {
 static void __init lart_init(void)
 {
-        sa11x0_set_mcp_data(&lart_mcp_data);
+        sa11x0_register_mcp(&lart_mcp_data);
 }
 static struct map_desc lart_io_desc[] __initdata = {
diff --git a/arch/arm/mach-sa1100/pleb.c b/arch/arm/mach-sa1100/pleb.c
index e1458bc1868e..1ccd6018d3a3 100644
--- a/arch/arm/mach-sa1100/pleb.c
+++ b/arch/arm/mach-sa1100/pleb.c
@@ -109,7 +109,7 @@ static struct flash_platform_data pleb_flash_data = {
 static void __init pleb_init(void)
 {
-        sa11x0_set_flash_data(&pleb_flash_data, pleb_flash_resources,
+        sa11x0_register_mtd(&pleb_flash_data, pleb_flash_resources,
                              ARRAY_SIZE(pleb_flash_resources));
diff --git a/arch/arm/mach-sa1100/shannon.c b/arch/arm/mach-sa1100/shannon.c
index ddd917d1083d..85e82bb73d7e 100644
--- a/arch/arm/mach-sa1100/shannon.c
+++ b/arch/arm/mach-sa1100/shannon.c
@@ -59,8 +59,8 @@ static struct mcp_plat_data shannon_mcp_data = {
 static void __init shannon_init(void)
 {
-        sa11x0_set_flash_data(&shannon_flash_data, &shannon_flash_resource, 1);
+        sa11x0_register_mtd(&shannon_flash_data, &shannon_flash_resource, 1);
-        sa11x0_set_mcp_data(&shannon_mcp_data);
+        sa11x0_register_mcp(&shannon_mcp_data);
 }
 static void __init shannon_map_io(void)
diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c
index 3c74534f7fee..49cfd64663ac 100644
--- a/arch/arm/mach-sa1100/simpad.c
+++ b/arch/arm/mach-sa1100/simpad.c
@@ -166,9 +166,9 @@ static void __init simpad_map_io(void)
        PCFR = 0;
        PSDR = 0;
-        sa11x0_set_flash_data(&simpad_flash_data, simpad_flash_resources,
+        sa11x0_register_mtd(&simpad_flash_data, simpad_flash_resources,
                              ARRAY_SIZE(simpad_flash_resources));
-        sa11x0_set_mcp_data(&simpad_mcp_data);
+        sa11x0_register_mcp(&simpad_mcp_data);
 }
 static void simpad_power_off(void)
diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile
index 885b5c027c1e..fab46fe9a71f 100644
--- a/arch/arm/mach-u300/Makefile
+++ b/arch/arm/mach-u300/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_MMC)                 += mmc.o
 obj-$(CONFIG_SPI_PL022)           += spi.o
 obj-$(CONFIG_MACH_U300_SPIDUMMY)  += dummyspichip.o
 obj-$(CONFIG_I2C_STU300)          += i2c.o
+obj-$(CONFIG_REGULATOR_AB3100)    += regulator.o
diff --git a/arch/arm/mach-u300/i2c.c b/arch/arm/mach-u300/i2c.c
index 10be1f888b27..c73ed06b6065 100644
--- a/arch/arm/mach-u300/i2c.c
+++ b/arch/arm/mach-u300/i2c.c
@@ -9,13 +9,257 @@
 */
 #include <linux/kernel.h>
 #include <linux/i2c.h>
+#include <linux/mfd/ab3100.h>
+#include <linux/regulator/machine.h>
+#include <linux/amba/bus.h>
 #include <mach/irqs.h>
+/*
+ * Initial settings of ab3100 registers.
+ * Common for below LDO regulator settings are that
+ * bit 7-5 controls voltage. Bit 4 turns regulator ON(1) or OFF(0).
+ * Bit 3-2 controls sleep enable and bit 1-0 controls sleep mode.
+ */
+/* LDO_A 0x16: 2.75V, ON, SLEEP_A, SLEEP OFF GND */
+#define LDO_A_SETTING           0x16
+/* LDO_C 0x10: 2.65V, ON, SLEEP_A or B, SLEEP full power */
+#define LDO_C_SETTING           0x10
+/* LDO_D 0x10: 2.65V, ON, sleep mode not used */
+#define LDO_D_SETTING           0x10
+/* LDO_E 0x10: 1.8V, ON, SLEEP_A or B, SLEEP full power */
+#define LDO_E_SETTING           0x10
+/* LDO_E SLEEP 0x00: 1.8V, not used, SLEEP_A or B, not used */
+#define LDO_E_SLEEP_SETTING     0x00
+/* LDO_F 0xD0: 2.5V, ON, SLEEP_A or B, SLEEP full power */
+#define LDO_F_SETTING           0xD0
+/* LDO_G 0x00: 2.85V, OFF, SLEEP_A or B, SLEEP full power */
+#define LDO_G_SETTING           0x00
+/* LDO_H 0x18: 2.75V, ON, SLEEP_B, SLEEP full power */
+#define LDO_H_SETTING           0x18
+/* LDO_K 0x00: 2.75V, OFF, SLEEP_A or B, SLEEP full power */
+#define LDO_K_SETTING           0x00
+/* LDO_EXT 0x00: Voltage not set, OFF, not used, not used */
+#define LDO_EXT_SETTING         0x00
+/* BUCK 0x7D: 1.2V, ON, SLEEP_A and B, SLEEP low power */
+#define BUCK_SETTING    0x7D
+/* BUCK SLEEP 0xAC: 1.05V, Not used, SLEEP_A and B, Not used */
+#define BUCK_SLEEP_SETTING      0xAC
+static struct regulator_consumer_supply supply_ldo_c[] = {
+        {
+                .dev_name = "ab3100-codec",
+                .supply = "vaudio", /* Powers the codec */
+        },
+};
+/*
+ * This one needs to be a supply so we can turn it off
+ * in order to shut down the system.
+ */
+static struct regulator_consumer_supply supply_ldo_d[] = {
+        {
+                .dev = NULL,
+                .supply = "vana15", /* Powers the SoC (CPU etc) */
+        },
+};
+static struct regulator_consumer_supply supply_ldo_g[] = {
+        {
+                .dev_name = "mmci",
+                .supply = "vmmc", /* Powers MMC/SD card */
+        },
+};
+static struct regulator_consumer_supply supply_ldo_h[] = {
+        {
+                .dev_name = "xgam_pdi",
+                .supply = "vdisp", /* Powers camera, display etc */
+        },
+};
+static struct regulator_consumer_supply supply_ldo_k[] = {
+        {
+                .dev_name = "irda",
+                .supply = "vir", /* Power IrDA */
+        },
+};
+/*
+ * This is a placeholder for whoever wish to use the
+ * external power.
+ */
+static struct regulator_consumer_supply supply_ldo_ext[] = {
+        {
+                .dev = NULL,
+                .supply = "vext", /* External power */
+        },
+};
+/* Preset (hardware defined) voltages for these regulators */
+#define LDO_A_VOLTAGE 2750000
+#define LDO_C_VOLTAGE 2650000
+#define LDO_D_VOLTAGE 2650000
+static struct ab3100_platform_data ab3100_plf_data = {
+        .reg_constraints = {
+                /* LDO A routing and constraints */
+                {
+                        .constraints = {
+                                .name = "vrad",
+                                .min_uV = LDO_A_VOLTAGE,
+                                .max_uV = LDO_A_VOLTAGE,
+                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                                .always_on = 1,
+                                .boot_on = 1,
+                        },
+                },
+                /* LDO C routing and constraints */
+                {
+                        .constraints = {
+                                .min_uV = LDO_C_VOLTAGE,
+                                .max_uV = LDO_C_VOLTAGE,
+                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                        },
+                        .num_consumer_supplies = ARRAY_SIZE(supply_ldo_c),
+                        .consumer_supplies = supply_ldo_c,
+                },
+                /* LDO D routing and constraints */
+                {
+                        .constraints = {
+                                .min_uV = LDO_D_VOLTAGE,
+                                .max_uV = LDO_D_VOLTAGE,
+                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                                /*
+                                 * Actually this is boot_on but we need
+                                 * to reference count it externally to
+                                 * be able to shut down the system.
+                                 */
+                        },
+                        .num_consumer_supplies = ARRAY_SIZE(supply_ldo_d),
+                        .consumer_supplies = supply_ldo_d,
+                },
+                /* LDO E routing and constraints */
+                {
+                        .constraints = {
+                                .name = "vio",
+                                .min_uV = 1800000,
+                                .max_uV = 1800000,
+                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                                .valid_ops_mask =
+                                REGULATOR_CHANGE_VOLTAGE |
+                                REGULATOR_CHANGE_STATUS,
+                                .always_on = 1,
+                                .boot_on = 1,
+                        },
+                },
+                /* LDO F routing and constraints */
+                {
+                        .constraints = {
+                                .name = "vana25",
+                                .min_uV = 2500000,
+                                .max_uV = 2500000,
+                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                                .valid_ops_mask =
+                                REGULATOR_CHANGE_VOLTAGE |
+                                REGULATOR_CHANGE_STATUS,
+                                .always_on = 1,
+                                .boot_on = 1,
+                        },
+                },
+                /* LDO G routing and constraints */
+                {
+                        .constraints = {
+                                .min_uV = 1500000,
+                                .max_uV = 2850000,
+                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                                .valid_ops_mask =
+                                REGULATOR_CHANGE_VOLTAGE |
+                                REGULATOR_CHANGE_STATUS,
+                        },
+                        .num_consumer_supplies = ARRAY_SIZE(supply_ldo_g),
+                        .consumer_supplies = supply_ldo_g,
+                },
+                /* LDO H routing and constraints */
+                {
+                        .constraints = {
+                                .min_uV = 1200000,
+                                .max_uV = 2750000,
+                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                                .valid_ops_mask =
+                                REGULATOR_CHANGE_VOLTAGE |
+                                REGULATOR_CHANGE_STATUS,
+                        },
+                        .num_consumer_supplies = ARRAY_SIZE(supply_ldo_h),
+                        .consumer_supplies = supply_ldo_h,
+                },
+                /* LDO K routing and constraints */
+                {
+                        .constraints = {
+                                .min_uV = 1800000,
+                                .max_uV = 2750000,
+                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                                .valid_ops_mask =
+                                REGULATOR_CHANGE_VOLTAGE |
+                                REGULATOR_CHANGE_STATUS,
+                        },
+                        .num_consumer_supplies = ARRAY_SIZE(supply_ldo_k),
+                        .consumer_supplies = supply_ldo_k,
+                },
+                /* External regulator interface. No fixed voltage specified.
+                 * If we knew the voltage of the external regulator and it
+                 * was connected on the board, we could add the (fixed)
+                 * voltage for it here.
+                 */
+                {
+                        .constraints = {
+                                .min_uV = 0,
+                                .max_uV = 0,
+                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                                .valid_ops_mask =
+                                REGULATOR_CHANGE_STATUS,
+                        },
+                        .num_consumer_supplies = ARRAY_SIZE(supply_ldo_ext),
+                        .consumer_supplies = supply_ldo_ext,
+                },
+                /* Buck converter routing and constraints */
+                {
+                        .constraints = {
+                                .name = "vcore",
+                                .min_uV = 1200000,
+                                .max_uV = 1800000,
+                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                                .valid_ops_mask =
+                                REGULATOR_CHANGE_VOLTAGE |
+                                REGULATOR_CHANGE_STATUS,
+                                .always_on = 1,
+                                .boot_on = 1,
+                        },
+                },
+        },
+        .reg_initvals = {
+                LDO_A_SETTING,
+                LDO_C_SETTING,
+                LDO_E_SETTING,
+                LDO_E_SLEEP_SETTING,
+                LDO_F_SETTING,
+                LDO_G_SETTING,
+                LDO_H_SETTING,
+                LDO_K_SETTING,
+                LDO_EXT_SETTING,
+                BUCK_SETTING,
+                BUCK_SLEEP_SETTING,
+                LDO_D_SETTING,
+        },
+};
 static struct i2c_board_info __initdata bus0_i2c_board_info[] = {
        {
                .type = "ab3100",
                .addr = 0x48,
                .irq = IRQ_U300_IRQ0_EXT,
+                .platform_data = &ab3100_plf_data,
        },
 };
@@ -38,6 +282,11 @@ void __init u300_i2c_register_board_devices(void)
 {
        i2c_register_board_info(0, bus0_i2c_board_info,
                                ARRAY_SIZE(bus0_i2c_board_info));
+        /*
+         * This makes the core shut down all unused regulators
+         * after all the initcalls have completed.
+         */
+        regulator_has_full_constraints();
        i2c_register_board_info(1, bus1_i2c_board_info,
                                ARRAY_SIZE(bus1_i2c_board_info));
 }
diff --git a/arch/arm/mach-u300/mmc.c b/arch/arm/mach-u300/mmc.c
index 7b6b016786bb..109f5a6e71c7 100644
--- a/arch/arm/mach-u300/mmc.c
+++ b/arch/arm/mach-u300/mmc.c
@@ -40,64 +40,6 @@ static unsigned int mmc_status(struct device *dev)
        return mmci_card->mmc_inserted;
 }
-/*
- * Here follows a large chunk of code which will only be enabled if you
- * have both the AB3100 chip mounted and the MMC subsystem activated.
- */
-static u32 mmc_translate_vdd(struct device *dev, unsigned int voltage)
-{
-        int v;
-        /*
-         * MMC Spec:
-         * bit 7:       1.70 - 1.95V
-         * bit 8 - 14:  2.0 - 2.6V
-         * bit 15 - 23: 2.7 - 3.6V
-         *
-         * ab3100 voltages:
-         * 000 - 2.85V
-         * 001 - 2.75V
-         * 010 - 1.8V
-         * 011 - 1.5V
-         */
-        switch (voltage) {
-        case 8:
-                v = 3;
-                break;
-        case 9:
-        case 10:
-        case 11:
-        case 12:
-        case 13:
-        case 14:
-        case 15:
-                v = 1;
-                break;
-        case 16:
-                v = 1;
-                break;
-        case 17:
-        case 18:
-        case 19:
-        case 20:
-        case 21:
-        case 22:
-        case 23:
-        case 24:
-                v = 0;
-                break;
-        default:
-                v = 0;
-                break;
-        }
-        /* PL180 voltage register bits */
-        return v << 2;
-}
 static int mmci_callback(void *data)
 {
        struct mmci_card_event *mmci_card = data;
@@ -154,9 +96,11 @@ int __devinit mmc_init(struct amba_device *adev)
        if (!mmci_card)
                return -ENOMEM;
+        /*
+         * Do not set ocr_mask or voltage translation function,
+         * we have a regulator we can control instead.
+         */
        /* Nominally 2.85V on our platform */
-        mmci_card->mmc0_plat_data.ocr_mask = MMC_VDD_28_29;
-        mmci_card->mmc0_plat_data.translate_vdd = mmc_translate_vdd;
        mmci_card->mmc0_plat_data.status = mmc_status;
        mmci_card->mmc0_plat_data.gpio_wp = -1;
        mmci_card->mmc0_plat_data.gpio_cd = -1;
diff --git a/arch/arm/mach-u300/regulator.c b/arch/arm/mach-u300/regulator.c
new file mode 100644
index 000000000000..9c53f01c62eb
--- /dev/null
+++ b/arch/arm/mach-u300/regulator.c
@@ -0,0 +1,88 @@
+/*
+ * arch/arm/mach-u300/regulator.c
+ *
+ * Copyright (C) 2009 ST-Ericsson AB
+ * License terms: GNU General Public License (GPL) version 2
+ * Handle board-bound regulators and board power not related
+ * to any devices.
+ * Author: Linus Walleij <linus.walleij@stericsson.com>
+ */
+#include <linux/device.h>
+#include <linux/signal.h>
+#include <linux/err.h>
+#include <linux/regulator/consumer.h>
+/* Those are just for writing in syscon */
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/syscon.h>
+/*
+ * Regulators that power the board and chip and which are
+ * not copuled to specific drivers are hogged in these
+ * instances.
+ */
+static struct regulator *main_power_15;
+/*
+ * This function is used from pm.h to shut down the system by
+ * resetting all regulators in turn and then disable regulator
+ * LDO D (main power).
+ */
+void u300_pm_poweroff(void)
+{
+        sigset_t old, all;
+        sigfillset(&all);
+        if (!sigprocmask(SIG_BLOCK, &all, &old)) {
+                /* Disable LDO D to shut down the system */
+                if (main_power_15)
+                        regulator_disable(main_power_15);
+                else
+                        pr_err("regulator not available to shut down system\n");
+                (void) sigprocmask(SIG_SETMASK, &old, NULL);
+        }
+        return;
+}
+/*
+ * Hog the regulators needed to power up the board.
+ */
+static int __init u300_init_boardpower(void)
+{
+        int err;
+        u32 val;
+        pr_info("U300: setting up board power\n");
+        main_power_15 = regulator_get(NULL, "vana15");
+        if (IS_ERR(main_power_15)) {
+                pr_err("could not get vana15");
+                return PTR_ERR(main_power_15);
+        }
+        err = regulator_enable(main_power_15);
+        if (err) {
+                pr_err("could not enable vana15\n");
+                return err;
+        }
+        /*
+         * On U300 a special system controller register pulls up the DC
+         * until the vana15 (LDO D) regulator comes up. At this point, all
+         * regulators are set and we do not need power control via
+         * DC ON anymore. This function will likely be moved whenever
+         * the rest of the U300 power management is implemented.
+         */
+        pr_info("U300: disable system controller pull-up\n");
+        val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMCR);
+        val &= ~U300_SYSCON_PMCR_DCON_ENABLE;
+        writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMCR);
+        /* Register globally exported PM poweroff hook */
+        pm_power_off = u300_pm_poweroff;
+        return 0;
+}
+/*
+ * So at module init time we hog the regulator!
+ */
+module_init(u300_init_boardpower);
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
new file mode 100644
index 000000000000..03625d744857
--- /dev/null
+++ b/arch/arm/mach-ux500/Kconfig
@@ -0,0 +1,15 @@
+menu "ST-Ericsson platform type"
+        depends on ARCH_U8500
+comment "ST-Ericsson Multicore Mobile Platforms"
+config MACH_U8500_MOP
+        bool "U8500 Early Development platform"
+        default y
+        select ARM_GIC
+        select HAS_MTU
+        help
+          Include support for mop500 development platform
+          based on U8500 architecture. The platform is based
+          on early drop silicon version of 8500.
+endmenu
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
new file mode 100644
index 000000000000..95e6e24c0042
--- /dev/null
+++ b/arch/arm/mach-ux500/Makefile
@@ -0,0 +1,8 @@
+#
+# Makefile for the linux kernel, U8500 machine.
+#
+obj-y                           := clock.o
+obj-$(CONFIG_ARCH_U8500)        += cpu-u8500.o
+obj-$(CONFIG_MACH_U8500_MOP)    += board-mop500.o
+obj-$(CONFIG_SMP)               += platsmp.o headsmp.o localtimer.o
diff --git a/arch/arm/mach-ux500/Makefile.boot b/arch/arm/mach-ux500/Makefile.boot
new file mode 100644
index 000000000000..c7e75acfe6c9
--- /dev/null
+++ b/arch/arm/mach-ux500/Makefile.boot
@@ -0,0 +1,4 @@
+   zreladdr-y   := 0x00008000
+params_phys-y   := 0x00000100
+initrd_phys-y   := 0x00800000
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
new file mode 100644
index 000000000000..aa5afbcc90f9
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -0,0 +1,158 @@
+/*
+ * Copyright (C) 2008-2009 ST-Ericsson
+ *
+ * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/pl022.h>
+#include <linux/spi/spi.h>
+#include <asm/localtimer.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <plat/mtu.h>
+#include <mach/hardware.h>
+#include <mach/setup.h>
+#define __MEM_4K_RESOURCE(x) \
+        .res = {.start = (x), .end = (x) + SZ_4K - 1, .flags = IORESOURCE_MEM}
+/* These are active devices on this board */
+static struct amba_device uart0_device = {
+        .dev = { .init_name = "uart0" },
+        __MEM_4K_RESOURCE(U8500_UART0_BASE),
+        .irq = {IRQ_UART0, NO_IRQ},
+};
+static struct amba_device uart1_device = {
+        .dev = { .init_name = "uart1" },
+        __MEM_4K_RESOURCE(U8500_UART1_BASE),
+        .irq = {IRQ_UART1, NO_IRQ},
+};
+static struct amba_device uart2_device = {
+        .dev = { .init_name = "uart2" },
+        __MEM_4K_RESOURCE(U8500_UART2_BASE),
+        .irq = {IRQ_UART2, NO_IRQ},
+};
+static void ab4500_spi_cs_control(u32 command)
+{
+        /* set the FRM signal, which is CS  - TODO */
+}
+struct pl022_config_chip ab4500_chip_info = {
+        .lbm = LOOPBACK_DISABLED,
+        .com_mode = INTERRUPT_TRANSFER,
+        .iface = SSP_INTERFACE_MOTOROLA_SPI,
+        /* we can act as master only */
+        .hierarchy = SSP_MASTER,
+        .slave_tx_disable = 0,
+        .endian_rx = SSP_RX_MSB,
+        .endian_tx = SSP_TX_MSB,
+        .data_size = SSP_DATA_BITS_24,
+        .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
+        .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
+        .clk_phase = SSP_CLK_SECOND_EDGE,
+        .clk_pol = SSP_CLK_POL_IDLE_HIGH,
+        .cs_control = ab4500_spi_cs_control,
+};
+static struct spi_board_info u8500_spi_devices[] = {
+        {
+                .modalias = "ab4500",
+                .controller_data = &ab4500_chip_info,
+                .max_speed_hz = 12000000,
+                .bus_num = 0,
+                .chip_select = 0,
+                .mode = SPI_MODE_0,
+                .irq = IRQ_AB4500,
+        },
+};
+static struct pl022_ssp_controller ssp0_platform_data = {
+        .bus_id = 0,
+        /* pl022 not yet supports dma */
+        .enable_dma = 0,
+        /* on this platform, gpio 31,142,144,214 &
+         * 224 are connected as chip selects
+         */
+        .num_chipselect = 5,
+};
+static struct amba_device pl022_device = {
+        .dev = {
+                .coherent_dma_mask = ~0,
+                .init_name = "pl022",
+                .platform_data = &ssp0_platform_data,
+        },
+        .res = {
+                .start = U8500_SSP0_BASE,
+                .end   = U8500_SSP0_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        .irq = {IRQ_SSP0, NO_IRQ },
+        /* ST-Ericsson modified id */
+        .periphid = SSP_PER_ID,
+};
+static struct amba_device *amba_devs[] __initdata = {
+        &uart0_device,
+        &uart1_device,
+        &uart2_device,
+        &pl022_device,
+};
+static void __init u8500_timer_init(void)
+{
+#ifdef CONFIG_LOCAL_TIMERS
+        /* Setup the local timer base */
+        twd_base = __io_address(U8500_TWD_BASE);
+#endif
+        /* Setup the MTU base */
+        mtu_base = __io_address(U8500_MTU0_BASE);
+        nmdk_timer_init();
+}
+static struct sys_timer u8500_timer = {
+        .init   = u8500_timer_init,
+};
+static void __init u8500_init_machine(void)
+{
+        int i;
+        /* Register the active AMBA devices on this board */
+        for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
+                amba_device_register(amba_devs[i], &iomem_resource);
+        spi_register_board_info(u8500_spi_devices,
+                        ARRAY_SIZE(u8500_spi_devices));
+        u8500_init_devices();
+}
+MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
+        /* Maintainer: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> */
+        .phys_io        = U8500_UART2_BASE,
+        .io_pg_offst    = (IO_ADDRESS(U8500_UART2_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x100,
+        .map_io         = u8500_map_io,
+        .init_irq       = u8500_init_irq,
+        /* we re-use nomadik timer here */
+        .timer          = &u8500_timer,
+        .init_machine   = u8500_init_machine,
+MACHINE_END
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
new file mode 100644
index 000000000000..20b6ebb6783a
--- /dev/null
+++ b/arch/arm/mach-ux500/clock.c
@@ -0,0 +1,95 @@
+/*
+ *  Copyright (C) 2009 ST-Ericsson
+ *      heavily based on realview platform
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/mutex.h>
+#include <asm/clkdev.h>
+/* currently the clk structure
+ * just supports rate. This would
+ * be extended as and when new devices are
+ * added - TODO
+ */
+struct clk {
+        unsigned long           rate;
+};
+int clk_enable(struct clk *clk)
+{
+        return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+void clk_disable(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_disable);
+unsigned long clk_get_rate(struct clk *clk)
+{
+        return clk->rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+        /*TODO*/
+        return rate;
+}
+EXPORT_SYMBOL(clk_round_rate);
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        clk->rate = rate;
+        return 0;
+}
+EXPORT_SYMBOL(clk_set_rate);
+/* ssp clock */
+static struct clk ssp_clk = {
+        .rate = 48000000,
+};
+/* fixed clock */
+static struct clk f38_clk = {
+        .rate = 38400000,
+};
+static struct clk_lookup lookups[] = {
+        {
+                /* UART0 */
+                .dev_id         = "uart0",
+                .clk            = &f38_clk,
+        }, {    /* UART1 */
+                .dev_id         = "uart1",
+                .clk            = &f38_clk,
+        }, {    /* UART2 */
+                .dev_id         = "uart2",
+                .clk            = &f38_clk,
+        }, {    /* SSP */
+                .dev_id         = "pl022",
+                .clk            = &ssp_clk,
+        }
+};
+static int __init clk_init(void)
+{
+        int i;
+        /* register the clock lookups */
+        for (i = 0; i < ARRAY_SIZE(lookups); i++)
+                clkdev_add(&lookups[i]);
+        return 0;
+}
+arch_initcall(clk_init);
diff --git a/arch/arm/mach-ux500/cpu-u8500.c b/arch/arm/mach-ux500/cpu-u8500.c
new file mode 100644
index 000000000000..5f05e5850f71
--- /dev/null
+++ b/arch/arm/mach-ux500/cpu-u8500.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2008-2009 ST-Ericsson
+ *
+ * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/amba/bus.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach/map.h>
+#include <mach/hardware.h>
+/* add any platform devices here - TODO */
+static struct platform_device *platform_devs[] __initdata = {
+        /* yet to be added, add i2c0, gpio.. */
+};
+#define __IO_DEV_DESC(x, sz)    {               \
+        .virtual        = IO_ADDRESS(x),        \
+        .pfn            = __phys_to_pfn(x),     \
+        .length         = sz,                   \
+        .type           = MT_DEVICE,            \
+}
+/* minimum static i/o mapping required to boot U8500 platforms */
+static struct map_desc u8500_io_desc[] __initdata = {
+        __IO_DEV_DESC(U8500_GIC_CPU_BASE, SZ_4K),
+        __IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K),
+        __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
+        __IO_DEV_DESC(U8500_TWD_BASE, SZ_4K),
+        __IO_DEV_DESC(U8500_SCU_BASE, SZ_4K),
+        __IO_DEV_DESC(U8500_BACKUPRAM0_BASE, SZ_8K),
+};
+void __init u8500_map_io(void)
+{
+        iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
+}
+void __init u8500_init_irq(void)
+{
+        gic_dist_init(0, __io_address(U8500_GIC_DIST_BASE), 29);
+        gic_cpu_init(0, __io_address(U8500_GIC_CPU_BASE));
+}
+/*
+ * This function is called from the board init
+ */
+void __init u8500_init_devices(void)
+{
+        /* Register the platform devices */
+        platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
+        return ;
+}
diff --git a/arch/arm/mach-ux500/headsmp.S b/arch/arm/mach-ux500/headsmp.S
new file mode 100644
index 000000000000..a6be2cdf2b2f
--- /dev/null
+++ b/arch/arm/mach-ux500/headsmp.S
@@ -0,0 +1,38 @@
+/*
+ *  Copyright (c) 2009 ST-Ericsson
+ *      This file is based  ARM Realview platform
+ *  Copyright (c) 2003 ARM Limited
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+        __INIT
+/*
+ * U8500 specific entry point for secondary CPUs.
+ */
+ENTRY(u8500_secondary_startup)
+        mrc     p15, 0, r0, c0, c0, 5
+        and     r0, r0, #15
+        adr     r4, 1f
+        ldmia   r4, {r5, r6}
+        sub     r4, r4, r5
+        add     r6, r6, r4
+        dsb
+pen:    ldr     r7, [r6]
+        cmp     r7, r0
+        bne     pen
+        /*
+         * we've been released from the holding pen: secondary_stack
+         * should now contain the SVC stack for this core
+         */
+        b       secondary_startup
+1:      .long   .
+        .long   pen_release
diff --git a/arch/arm/mach-ux500/include/mach/clkdev.h b/arch/arm/mach-ux500/include/mach/clkdev.h
new file mode 100644
index 000000000000..04b37a89801c
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S
new file mode 100644
index 000000000000..8f21b6a95dce
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/debug-macro.S
@@ -0,0 +1,19 @@
+/*
+ * Debugging macro include header
+ *
+ *  Copyright (C) 2009 ST-Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+        .macro  addruart,rx
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1                 @MMU enabled?
+        moveq   \rx, #0x80000000        @MMU off, Physical address
+        movne   \rx, #0xF0000000        @MMU on, Virtual address
+        orr     \rx, \rx, #0x7000
+        .endm
+#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-ux500/include/mach/entry-macro.S b/arch/arm/mach-ux500/include/mach/entry-macro.S
new file mode 100644
index 000000000000..eece3301fef7
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/entry-macro.S
@@ -0,0 +1,89 @@
+/*
+ * Low-level IRQ helper macros for U8500 platforms
+ *
+ * Copyright (C) 2009 ST-Ericsson.
+ *
+ * This file is a copy of ARM Realview platform.
+ *      -just satisfied checkpatch script.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <mach/hardware.h>
+#include <asm/hardware/gic.h>
+                .macro  disable_fiq
+                .endm
+                .macro  get_irqnr_preamble, base, tmp
+                ldr     \base, =IO_ADDRESS(U8500_GIC_CPU_BASE)
+                .endm
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+                /*
+                 * The interrupt numbering scheme is defined in the
+                 * interrupt controller spec.  To wit:
+                 *
+                 * Interrupts 0-15 are IPI
+                 * 16-28 are reserved
+                 * 29-31 are local.  We allow 30 to be used for the watchdog.
+                 * 32-1020 are global
+                 * 1021-1022 are reserved
+                 * 1023 is "spurious" (no interrupt)
+                 *
+                 * For now, we ignore all local interrupts so only return an
+                 * interrupt if it's between 30 and 1020. The test_for_ipi
+                 * routine below will pick up on IPIs.
+                 *
+                 * A simple read from the controller will tell us the number
+                 * of the highest priority enabled interrupt. We then just
+                 * need to check whether it is in the valid range for an
+                 * IRQ (30-1020 inclusive).
+                 */
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                /* bits 12-10 = src CPU, 9-0 = int # */
+                ldr     \irqstat, [\base, #GIC_CPU_INTACK]
+                ldr     \tmp, =1021
+                bic     \irqnr, \irqstat, #0x1c00
+                cmp     \irqnr, #29
+                cmpcc   \irqnr, \irqnr
+                cmpne   \irqnr, \tmp
+                cmpcs   \irqnr, \irqnr
+                .endm
+                /* We assume that irqstat (the raw value of the IRQ
+                 * acknowledge register) is preserved from the macro above.
+                 * If there is an IPI, we immediately signal end of
+                 * interrupt on the controller, since this requires the
+                 * original irqstat value which we won't easily be able
+                 * to recreate later.
+                 */
+                .macro test_for_ipi, irqnr, irqstat, base, tmp
+                bic     \irqnr, \irqstat, #0x1c00
+                cmp     \irqnr, #16
+                strcc   \irqstat, [\base, #GIC_CPU_EOI]
+                cmpcs   \irqnr, \irqnr
+                .endm
+                /* As above, this assumes that irqstat and base
+                 * are preserved..
+                 */
+                .macro test_for_ltirq, irqnr, irqstat, base, tmp
+                bic     \irqnr, \irqstat, #0x1c00
+                mov     \tmp, #0
+                cmp     \irqnr, #29
+                moveq   \tmp, #1
+                streq   \irqstat, [\base, #GIC_CPU_EOI]
+                cmp     \tmp, #0
+                .endm
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
new file mode 100644
index 000000000000..6da650202dc7
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright (C) 2009 ST-Ericsson.
+ *
+ * U8500 hardware definitions
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __MACH_HARDWARE_H
+#define __MACH_HARDWARE_H
+/* macros to get at IO space when running virtually
+ * We dont map all the peripherals, let ioremap do
+ * this for us. We map only very basic peripherals here.
+ */
+#define U8500_IO_VIRTUAL        0xf0000000
+#define U8500_IO_PHYSICAL       0xa0000000
+/* this macro is used in assembly, so no cast */
+#define IO_ADDRESS(x)           \
+        (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL)
+/* typesafe io address */
+#define __io_address(n)         __io(IO_ADDRESS(n))
+/*
+ * Base address definitions for U8500 Onchip IPs. All the
+ * peripherals are contained in a single 1 Mbyte region, with
+ * AHB peripherals at the bottom and APB peripherals at the
+ * top of the region. PER stands for PERIPHERAL region which
+ * itself divided into sub regions.
+ */
+#define U8500_PER3_BASE         0x80000000
+#define U8500_PER2_BASE         0x80110000
+#define U8500_PER1_BASE         0x80120000
+#define U8500_PER4_BASE         0x80150000
+#define U8500_PER6_BASE         0xa03c0000
+#define U8500_PER5_BASE         0xa03e0000
+#define U8500_PER7_BASE         0xa03d0000
+#define U8500_SVA_BASE          0xa0100000
+#define U8500_SIA_BASE          0xa0200000
+#define U8500_SGA_BASE          0xa0300000
+#define U8500_MCDE_BASE         0xa0350000
+#define U8500_DMA_BASE          0xa0362000
+#define U8500_SCU_BASE          0xa0410000
+#define U8500_GIC_CPU_BASE      0xa0410100
+#define U8500_TWD_BASE          0xa0410600
+#define U8500_GIC_DIST_BASE     0xa0411000
+#define U8500_L2CC_BASE         0xa0412000
+#define U8500_TWD_SIZE          0x100
+/* per7 base addressess */
+#define U8500_CR_BASE           (U8500_PER7_BASE + 0x8000)
+#define U8500_MTU0_BASE         (U8500_PER7_BASE + 0xa000)
+#define U8500_MTU1_BASE         (U8500_PER7_BASE + 0xb000)
+#define U8500_TZPC0_BASE        (U8500_PER7_BASE + 0xc000)
+#define U8500_CLKRST7_BASE      (U8500_PER7_BASE + 0xf000)
+/* per6 base addressess */
+#define U8500_RNG_BASE          (U8500_PER6_BASE + 0x0000)
+#define U8500_PKA_BASE          (U8500_PER6_BASE + 0x1000)
+#define U8500_PKAM_BASE         (U8500_PER6_BASE + 0x2000)
+#define U8500_CRYPTO0_BASE      (U8500_PER6_BASE + 0xa000)
+#define U8500_CRYPTO1_BASE      (U8500_PER6_BASE + 0xb000)
+#define U8500_CLKRST6_BASE      (U8500_PER7_BASE + 0xf000)
+/* per5 base addressess */
+#define U8500_USBOTG_BASE       (U8500_PER5_BASE + 0x00000)
+#define U8500_GPIO5_BASE        (U8500_PER5_BASE + 0x1e000)
+#define U8500_CLKRST5_BASE      (U8500_PER7_BASE + 0x1f000)
+/* per4 base addressess */
+#define U8500_BACKUPRAM0_BASE   (U8500_PER4_BASE + 0x0000)
+#define U8500_BACKUPRAM1_BASE   (U8500_PER4_BASE + 0x1000)
+#define U8500_RTT0_BASE         (U8500_PER4_BASE + 0x2000)
+#define U8500_RTT1_BASE         (U8500_PER4_BASE + 0x3000)
+#define U8500_RTC_BASE          (U8500_PER4_BASE + 0x4000)
+#define U8500_SCR_BASE          (U8500_PER4_BASE + 0x5000)
+#define U8500_DMC_BASE          (U8500_PER4_BASE + 0x6000)
+#define U8500_PRCMU_BASE        (U8500_PER4_BASE + 0x7000)
+/* per3 base addressess */
+#define U8500_FSMC_BASE         (U8500_PER3_BASE + 0x0000)
+#define U8500_SSP0_BASE         (U8500_PER3_BASE + 0x2000)
+#define U8500_SSP1_BASE         (U8500_PER3_BASE + 0x3000)
+#define U8500_I2C0_BASE         (U8500_PER3_BASE + 0x4000)
+#define U8500_SDI2_BASE         (U8500_PER3_BASE + 0x5000)
+#define U8500_SKE_BASE          (U8500_PER3_BASE + 0x6000)
+#define U8500_UART2_BASE        (U8500_PER3_BASE + 0x7000)
+#define U8500_SDI5_BASE         (U8500_PER3_BASE + 0x8000)
+#define U8500_GPIO3_BASE        (U8500_PER3_BASE + 0xe000)
+#define U8500_CLKRST3_BASE      (U8500_PER7_BASE + 0xf000)
+/* per2 base addressess */
+#define U8500_I2C3_BASE         (U8500_PER2_BASE + 0x0000)
+#define U8500_SPI2_BASE         (U8500_PER2_BASE + 0x1000)
+#define U8500_SPI1_BASE         (U8500_PER2_BASE + 0x2000)
+#define U8500_PWL_BASE          (U8500_PER2_BASE + 0x3000)
+#define U8500_SDI4_BASE         (U8500_PER2_BASE + 0x4000)
+#define U8500_MSP2_BASE         (U8500_PER2_BASE + 0x7000)
+#define U8500_SDI1_BASE         (U8500_PER2_BASE + 0x8000)
+#define U8500_SDI3_BASE         (U8500_PER2_BASE + 0x9000)
+#define U8500_SPI0_BASE         (U8500_PER2_BASE + 0xa000)
+#define U8500_HSIR_BASE         (U8500_PER2_BASE + 0xb000)
+#define U8500_HSIT_BASE         (U8500_PER2_BASE + 0xc000)
+#define U8500_GPIO2_BASE        (U8500_PER2_BASE + 0xe000)
+#define U8500_CLKRST2_BASE      (U8500_PER2_BASE + 0xf000)
+/* per1 base addresses */
+#define U8500_UART0_BASE        (U8500_PER1_BASE + 0x0000)
+#define U8500_UART1_BASE        (U8500_PER1_BASE + 0x1000)
+#define U8500_I2C1_BASE         (U8500_PER1_BASE + 0x2000)
+#define U8500_MSP0_BASE         (U8500_PER1_BASE + 0x3000)
+#define U8500_MSP1_BASE         (U8500_PER1_BASE + 0x4000)
+#define U8500_SDI0_BASE         (U8500_PER1_BASE + 0x6000)
+#define U8500_I2C2_BASE         (U8500_PER1_BASE + 0x8000)
+#define U8500_SPI3_BASE         (U8500_PER1_BASE + 0x9000)
+#define U8500_SLIM0_BASE        (U8500_PER1_BASE + 0xa000)
+#define U8500_GPIO1_BASE        (U8500_PER1_BASE + 0xe000)
+#define U8500_CLKRST1_BASE      (U8500_PER2_BASE + 0xf000)
+/* ST-Ericsson modified pl022 id */
+#define SSP_PER_ID              0x01080022
+#endif                          /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-ux500/include/mach/io.h b/arch/arm/mach-ux500/include/mach/io.h
new file mode 100644
index 000000000000..1cf3f44ce5b2
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/io.h
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/mach-u8500/include/mach/io.h
+ *
+ * Copyright (C) 1997-1999 Russell King
+ *
+ * Modifications:
+ *  06-12-1997  RMK     Created.
+ *  07-04-1999  RMK     Major cleanup
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+#define IO_SPACE_LIMIT 0xffffffff
+/*
+ * We don't actually have real ISA nor PCI buses, but there is so many
+ * drivers out there that might just work if we fake them...
+ */
+#define __io(a)         __typesafe_io(a)
+#define __mem_pci(a)    (a)
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
new file mode 100644
index 000000000000..394b5dd2200f
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -0,0 +1,71 @@
+/*
+ *  Copyright (C) 2008 STMicroelectronics
+ *  Copyright (C) 2009 ST-Ericsson.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef ASM_ARCH_IRQS_H
+#define ASM_ARCH_IRQS_H
+#include <mach/hardware.h>
+#define IRQ_LOCALTIMER                  29
+#define IRQ_LOCALWDOG                   30
+/* Shared Peripheral Interrupt (SHPI) */
+#define IRQ_SHPI_START                  32
+/* Interrupt numbers generic for shared peripheral */
+#define IRQ_MTU0                (IRQ_SHPI_START + 4)
+#define IRQ_SPI2                (IRQ_SHPI_START + 6)
+#define IRQ_SPI0                (IRQ_SHPI_START + 8)
+#define IRQ_UART0               (IRQ_SHPI_START + 11)
+#define IRQ_I2C3                (IRQ_SHPI_START + 12)
+#define IRQ_SSP0                (IRQ_SHPI_START + 14)
+#define IRQ_MTU1                (IRQ_SHPI_START + 17)
+#define IRQ_RTC_RTT             (IRQ_SHPI_START + 18)
+#define IRQ_UART1               (IRQ_SHPI_START + 19)
+#define IRQ_I2C0                (IRQ_SHPI_START + 21)
+#define IRQ_I2C1                (IRQ_SHPI_START + 22)
+#define IRQ_USBOTG              (IRQ_SHPI_START + 23)
+#define IRQ_DMA                 (IRQ_SHPI_START + 25)
+#define IRQ_UART2               (IRQ_SHPI_START + 26)
+#define IRQ_HSIR_EXCEP          (IRQ_SHPI_START + 29)
+#define IRQ_MSP0                (IRQ_SHPI_START + 31)
+#define IRQ_HSIR_CH0_OVRRUN     (IRQ_SHPI_START + 32)
+#define IRQ_HSIR_CH1_OVRRUN     (IRQ_SHPI_START + 33)
+#define IRQ_HSIR_CH2_OVRRUN     (IRQ_SHPI_START + 34)
+#define IRQ_HSIR_CH3_OVRRUN     (IRQ_SHPI_START + 35)
+#define IRQ_AB4500              (IRQ_SHPI_START + 40)
+#define IRQ_DISP                (IRQ_SHPI_START + 48)
+#define IRQ_SiPI3               (IRQ_SHPI_START + 49)
+#define IRQ_SSP1                (IRQ_SHPI_START + 52)
+#define IRQ_I2C2                (IRQ_SHPI_START + 55)
+#define IRQ_SDMMC0              (IRQ_SHPI_START + 60)
+#define IRQ_MSP1                (IRQ_SHPI_START + 62)
+#define IRQ_SPI1                (IRQ_SHPI_START + 96)
+#define IRQ_MSP2                (IRQ_SHPI_START + 98)
+#define IRQ_SDMMC4              (IRQ_SHPI_START + 99)
+#define IRQ_HSIRD0              (IRQ_SHPI_START + 104)
+#define IRQ_HSIRD1              (IRQ_SHPI_START + 105)
+#define IRQ_HSITD0              (IRQ_SHPI_START + 106)
+#define IRQ_HSITD1              (IRQ_SHPI_START + 107)
+#define IRQ_GPIO0               (IRQ_SHPI_START + 119)
+#define IRQ_GPIO1               (IRQ_SHPI_START + 120)
+#define IRQ_GPIO2               (IRQ_SHPI_START + 121)
+#define IRQ_GPIO3               (IRQ_SHPI_START + 122)
+#define IRQ_GPIO4               (IRQ_SHPI_START + 123)
+#define IRQ_GPIO5               (IRQ_SHPI_START + 124)
+#define IRQ_GPIO6               (IRQ_SHPI_START + 125)
+#define IRQ_GPIO7               (IRQ_SHPI_START + 126)
+#define IRQ_GPIO8               (IRQ_SHPI_START + 127)
+/* There are 128 shared peripheral interrupts assigned to
+ * INTID[160:32]. The first 32 interrupts are reserved.
+ */
+#define NR_IRQS                 161
+#endif /*ASM_ARCH_IRQS_H*/
diff --git a/arch/arm/mach-ux500/include/mach/memory.h b/arch/arm/mach-ux500/include/mach/memory.h
new file mode 100644
index 000000000000..510571a59e25
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/memory.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2009 ST-Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     UL(0x00000000)
+#define BUS_OFFSET      UL(0x00000000)
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h
new file mode 100644
index 000000000000..cf0ce1687f24
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/setup.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2009 ST-Ericsson.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * These symbols are needed for board-specific files to call their
+ * own cpu-specific files
+ */
+#ifndef __ASM_ARCH_SETUP_H
+#define __ASM_ARCH_SETUP_H
+#include <asm/mach/time.h>
+#include <linux/init.h>
+extern void u8500_map_io(void);
+extern void u8500_init_devices(void);
+extern void u8500_init_irq(void);
+/* We re-use nomadik_timer for this platform */
+extern void nmdk_timer_init(void);
+#endif /*  __ASM_ARCH_SETUP_H */
diff --git a/arch/arm/mach-ux500/include/mach/smp.h b/arch/arm/mach-ux500/include/mach/smp.h
new file mode 100644
index 000000000000..b59f7bc9725d
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/smp.h
@@ -0,0 +1,32 @@
+/*
+ * This file is based ARM realview platform.
+ * Copyright (C) ARM Limited.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef ASMARM_ARCH_SMP_H
+#define ASMARM_ARCH_SMP_H
+#include <asm/hardware/gic.h>
+/* This is required to wakeup the secondary core */
+extern void u8500_secondary_startup(void);
+#define hard_smp_processor_id()                         \
+        ({                                              \
+                unsigned int cpunum;                    \
+                __asm__("mrc p15, 0, %0, c0, c0, 5"     \
+                        : "=r" (cpunum));               \
+                cpunum &= 0x0F;                         \
+        })
+/*
+ * We use IRQ1 as the IPI
+ */
+static inline void smp_cross_call(const struct cpumask *mask)
+{
+        gic_raise_softirq(mask, 1);
+}
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/system.h b/arch/arm/mach-ux500/include/mach/system.h
new file mode 100644
index 000000000000..c0cd8006f1a2
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/system.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2009 ST-Ericsson.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+static inline void arch_idle(void)
+{
+        /*
+         * This should do all the clock switching
+         * and wait for interrupt tricks
+         */
+        cpu_do_idle();
+}
+static inline void arch_reset(char mode, const char *cmd)
+{
+        /* yet to be implemented - TODO */
+}
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/timex.h b/arch/arm/mach-ux500/include/mach/timex.h
new file mode 100644
index 000000000000..d0942c174018
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/timex.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+#define CLOCK_TICK_RATE         110000000
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h
new file mode 100644
index 000000000000..8552eb188b50
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/uncompress.h
@@ -0,0 +1,58 @@
+/*
+ *  Copyright (C) 2009 ST-Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+#include <asm/setup.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#define U8500_UART_DR           0x80007000
+#define U8500_UART_LCRH         0x8000702c
+#define U8500_UART_CR           0x80007030
+#define U8500_UART_FR           0x80007018
+static void putc(const char c)
+{
+        /* Do nothing if the UART is not enabled. */
+        if (!(readb(U8500_UART_CR) & 0x1))
+                return;
+        if (c == '\n')
+                putc('\r');
+        while (readb(U8500_UART_FR) & (1 << 5))
+                barrier();
+        writeb(c, U8500_UART_DR);
+}
+static void flush(void)
+{
+        if (!(readb(U8500_UART_CR) & 0x1))
+                return;
+        while (readb(U8500_UART_FR) & (1 << 3))
+                barrier();
+}
+static inline void arch_decomp_setup(void)
+{
+}
+#define arch_decomp_wdog() /* nothing to do here */
+#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-ux500/include/mach/vmalloc.h b/arch/arm/mach-ux500/include/mach/vmalloc.h
new file mode 100644
index 000000000000..86cdbbce1842
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/vmalloc.h
@@ -0,0 +1,18 @@
+/*
+ *  Copyright (C) 2009 ST-Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#define VMALLOC_END     0xf0000000
diff --git a/arch/arm/mach-ux500/localtimer.c b/arch/arm/mach-ux500/localtimer.c
new file mode 100644
index 000000000000..2288f6a7c518
--- /dev/null
+++ b/arch/arm/mach-ux500/localtimer.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2008-2009 ST-Ericsson
+ * Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
+ *
+ * This file is heavily based on relaview platform, almost a copy.
+ *
+ * Copyright (C) 2002 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/clockchips.h>
+#include <asm/irq.h>
+#include <asm/smp_twd.h>
+#include <asm/localtimer.h>
+/*
+ * Setup the local clock events for a CPU.
+ */
+void __cpuinit local_timer_setup(struct clock_event_device *evt)
+{
+        evt->irq = IRQ_LOCALTIMER;
+        twd_timer_setup(evt);
+}
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
new file mode 100644
index 000000000000..8dfe7ca245d8
--- /dev/null
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright (C) 2002 ARM Ltd.
+ * Copyright (C) 2008 STMicroelctronics.
+ * Copyright (C) 2009 ST-Ericsson.
+ * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
+ *
+ * This file is based on arm realview platform
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <asm/cacheflush.h>
+#include <asm/localtimer.h>
+#include <asm/smp_scu.h>
+#include <mach/hardware.h>
+/*
+ * control for which core is the next to come out of the secondary
+ * boot "holding pen"
+ */
+volatile int __cpuinitdata pen_release = -1;
+static unsigned int __init get_core_count(void)
+{
+        return scu_get_core_count(__io_address(U8500_SCU_BASE));
+}
+static DEFINE_SPINLOCK(boot_lock);
+void __cpuinit platform_secondary_init(unsigned int cpu)
+{
+        trace_hardirqs_off();
+        /*
+         * if any interrupts are already enabled for the primary
+         * core (e.g. timer irq), then they will not have been enabled
+         * for us: do so
+         */
+        gic_cpu_init(0, __io_address(U8500_GIC_CPU_BASE));
+        /*
+         * let the primary processor know we're out of the
+         * pen, then head off into the C entry point
+         */
+        pen_release = -1;
+        /*
+         * Synchronise with the boot thread.
+         */
+        spin_lock(&boot_lock);
+        spin_unlock(&boot_lock);
+}
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        unsigned long timeout;
+        /*
+         * set synchronisation state between this boot processor
+         * and the secondary one
+         */
+        spin_lock(&boot_lock);
+        /*
+         * The secondary processor is waiting to be released from
+         * the holding pen - release it, then wait for it to flag
+         * that it has been released by resetting pen_release.
+         */
+        pen_release = cpu;
+        flush_cache_all();
+        timeout = jiffies + (1 * HZ);
+        while (time_before(jiffies, timeout)) {
+                if (pen_release == -1)
+                        break;
+        }
+        /*
+         * now the secondary core is starting up let it run its
+         * calibrations, then wait for it to finish
+         */
+        spin_unlock(&boot_lock);
+        return pen_release != -1 ? -ENOSYS : 0;
+}
+static void __init wakeup_secondary(void)
+{
+        /* nobody is to be released from the pen yet */
+        pen_release = -1;
+        /*
+         * write the address of secondary startup into the backup ram register
+         * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
+         * backup ram register at offset 0x1FF0, which is what boot rom code
+         * is waiting for. This would wake up the secondary core from WFE
+         */
+#define U8500_CPU1_JUMPADDR_OFFSET 0x1FF4
+        __raw_writel(virt_to_phys(u8500_secondary_startup),
+                (void __iomem *)IO_ADDRESS(U8500_BACKUPRAM0_BASE) +
+                U8500_CPU1_JUMPADDR_OFFSET);
+#define U8500_CPU1_WAKEMAGIC_OFFSET 0x1FF0
+        __raw_writel(0xA1FEED01,
+                (void __iomem *)IO_ADDRESS(U8500_BACKUPRAM0_BASE) +
+                U8500_CPU1_WAKEMAGIC_OFFSET);
+        /* make sure write buffer is drained */
+        mb();
+}
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system.
+ */
+void __init smp_init_cpus(void)
+{
+        unsigned int i, ncores = get_core_count();
+        for (i = 0; i < ncores; i++)
+                set_cpu_possible(i, true);
+}
+void __init smp_prepare_cpus(unsigned int max_cpus)
+{
+        unsigned int ncores = get_core_count();
+        unsigned int cpu = smp_processor_id();
+        int i;
+        /* sanity check */
+        if (ncores == 0) {
+                printk(KERN_ERR
+                       "U8500: strange CM count of 0? Default to 1\n");
+                ncores = 1;
+        }
+        if (ncores > num_possible_cpus())       {
+                printk(KERN_WARNING
+                       "U8500: no. of cores (%d) greater than configured "
+                       "maximum of %d - clipping\n",
+                       ncores, num_possible_cpus());
+                ncores = num_possible_cpus();
+        }
+        smp_store_cpu_info(cpu);
+        /*
+         * are we trying to boot more cores than exist?
+         */
+        if (max_cpus > ncores)
+                max_cpus = ncores;
+        /*
+         * Initialise the present map, which describes the set of CPUs
+         * actually populated at the present time.
+         */
+        for (i = 0; i < max_cpus; i++)
+                set_cpu_present(i, true);
+        if (max_cpus > 1) {
+                /*
+                 * Enable the local timer or broadcast device for the
+                 * boot CPU, but only if we have more than one CPU.
+                 */
+                percpu_timer_setup();
+                scu_enable(__io_address(U8500_SCU_BASE));
+                wakeup_secondary();
+        }
+}
diff --git a/arch/arm/mach-w90x900/dev.c b/arch/arm/mach-w90x900/dev.c
index 2a6f98de48d2..51f17b753348 100644
--- a/arch/arm/mach-w90x900/dev.c
+++ b/arch/arm/mach-w90x900/dev.c
@@ -32,6 +32,7 @@
 #include <asm/mach-types.h>
 #include <mach/regs-serial.h>
+#include <mach/nuc900_spi.h>
 #include <mach/map.h>
 #include "cpu.h"
@@ -196,6 +197,18 @@ static struct platform_device nuc900_device_emc = {
 /* SPI device */
+static struct w90p910_spi_info nuc900_spiflash_data = {
+        .num_cs         = 1,
+        .lsb            = 0,
+        .txneg          = 1,
+        .rxneg          = 0,
+        .divider        = 24,
+        .sleep          = 0,
+        .txnum          = 0,
+        .txbitlen       = 1,
+        .bus_num        = 0,
+};
 static struct resource nuc900_spi_resource[] = {
        [0] = {
                .start = W90X900_PA_I2C + SPIOFFSET,
@@ -214,6 +227,9 @@ static struct platform_device nuc900_device_spi = {
        .id             = -1,
        .num_resources  = ARRAY_SIZE(nuc900_spi_resource),
        .resource       = nuc900_spi_resource,
+        .dev            = {
+                                .platform_data = &nuc900_spiflash_data,
+                        }
 };
 /* spi device, spi flash info */
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 9264d814cd7a..dd4698c67cc3 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -388,7 +388,7 @@ config CPU_FEROCEON_OLD_ID
 # ARMv6
 config CPU_V6
-        bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
+        bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || ARCH_DOVE
        select CPU_32v6
        select CPU_ABRT_EV6
        select CPU_PABRT_V6
@@ -764,6 +764,15 @@ config CACHE_L2X0
        help
          This option enables the L2x0 PrimeCell.
+config CACHE_TAUROS2
+        bool "Enable the Tauros2 L2 cache controller"
+        depends on ARCH_DOVE
+        default y
+        select OUTER_CACHE
+        help
+          This option enables the Tauros2 L2 cache controller (as
+          found on PJ1/PJ4).
 config CACHE_XSC3L2
        bool "Enable the L2 cache on XScale3"
        depends on CPU_XSC3
@@ -774,5 +783,5 @@ config CACHE_XSC3L2
 config ARM_L1_CACHE_SHIFT
        int
-        default 6 if ARCH_OMAP3
+        default 6 if ARCH_OMAP3 || ARCH_S5PC1XX
        default 5
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 055cb2aa8134..827e238e5d4a 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -6,7 +6,7 @@ obj-y				:= dma-mapping.o extable.o fault.o init.o \
                                   iomap.o
 obj-$(CONFIG_MMU)               += fault-armv.o flush.o ioremap.o mmap.o \
-                                   pgd.o mmu.o
+                                   pgd.o mmu.o vmregion.o
 ifneq ($(CONFIG_MMU),y)
 obj-y                           += nommu.o
@@ -87,4 +87,4 @@ obj-$(CONFIG_CPU_V7)		+= proc-v7.o
 obj-$(CONFIG_CACHE_FEROCEON_L2) += cache-feroceon-l2.o
 obj-$(CONFIG_CACHE_L2X0)        += cache-l2x0.o
 obj-$(CONFIG_CACHE_XSC3L2)      += cache-xsc3l2.o
+obj-$(CONFIG_CACHE_TAUROS2)     += cache-tauros2.o
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index b480f1d3591f..747f9a9021bb 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -99,18 +99,25 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
        l2x0_base = base;
-        /* disable L2X0 */
+        /*
-        writel(0, l2x0_base + L2X0_CTRL);
+         * Check if l2x0 controller is already enabled.
+         * If you are booting from non-secure mode
+         * accessing the below registers will fault.
+         */
+        if (!(readl(l2x0_base + L2X0_CTRL) & 1)) {
-        aux = readl(l2x0_base + L2X0_AUX_CTRL);
+                /* l2x0 controller is disabled */
-        aux &= aux_mask;
-        aux |= aux_val;
-        writel(aux, l2x0_base + L2X0_AUX_CTRL);
-        l2x0_inv_all();
+                aux = readl(l2x0_base + L2X0_AUX_CTRL);
+                aux &= aux_mask;
+                aux |= aux_val;
+                writel(aux, l2x0_base + L2X0_AUX_CTRL);
-        /* enable L2X0 */
+                l2x0_inv_all();
-        writel(1, l2x0_base + L2X0_CTRL);
+                /* enable L2X0 */
+                writel(1, l2x0_base + L2X0_CTRL);
+        }
        outer_cache.inv_range = l2x0_inv_range;
        outer_cache.clean_range = l2x0_clean_range;
diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c
new file mode 100644
index 000000000000..50868651890f
--- /dev/null
+++ b/arch/arm/mm/cache-tauros2.c
@@ -0,0 +1,263 @@
+/*
+ * arch/arm/mm/cache-tauros2.c - Tauros2 L2 cache controller support
+ *
+ * Copyright (C) 2008 Marvell Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * References:
+ * - PJ1 CPU Core Datasheet,
+ *   Document ID MV-S104837-01, Rev 0.7, January 24 2008.
+ * - PJ4 CPU Core Datasheet,
+ *   Document ID MV-S105190-00, Rev 0.7, March 14 2008.
+ */
+#include <linux/init.h>
+#include <asm/cacheflush.h>
+#include <asm/hardware/cache-tauros2.h>
+/*
+ * When Tauros2 is used on a CPU that supports the v7 hierarchical
+ * cache operations, the cache handling code in proc-v7.S takes care
+ * of everything, including handling DMA coherency.
+ *
+ * So, we only need to register outer cache operations here if we're
+ * being used on a pre-v7 CPU, and we only need to build support for
+ * outer cache operations into the kernel image if the kernel has been
+ * configured to support a pre-v7 CPU.
+ */
+#if __LINUX_ARM_ARCH__ < 7
+/*
+ * Low-level cache maintenance operations.
+ */
+static inline void tauros2_clean_pa(unsigned long addr)
+{
+        __asm__("mcr p15, 1, %0, c7, c11, 3" : : "r" (addr));
+}
+static inline void tauros2_clean_inv_pa(unsigned long addr)
+{
+        __asm__("mcr p15, 1, %0, c7, c15, 3" : : "r" (addr));
+}
+static inline void tauros2_inv_pa(unsigned long addr)
+{
+        __asm__("mcr p15, 1, %0, c7, c7, 3" : : "r" (addr));
+}
+/*
+ * Linux primitives.
+ *
+ * Note that the end addresses passed to Linux primitives are
+ * noninclusive.
+ */
+#define CACHE_LINE_SIZE         32
+static void tauros2_inv_range(unsigned long start, unsigned long end)
+{
+        /*
+         * Clean and invalidate partial first cache line.
+         */
+        if (start & (CACHE_LINE_SIZE - 1)) {
+                tauros2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1));
+                start = (start | (CACHE_LINE_SIZE - 1)) + 1;
+        }
+        /*
+         * Clean and invalidate partial last cache line.
+         */
+        if (end & (CACHE_LINE_SIZE - 1)) {
+                tauros2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1));
+                end &= ~(CACHE_LINE_SIZE - 1);
+        }
+        /*
+         * Invalidate all full cache lines between 'start' and 'end'.
+         */
+        while (start < end) {
+                tauros2_inv_pa(start);
+                start += CACHE_LINE_SIZE;
+        }
+        dsb();
+}
+static void tauros2_clean_range(unsigned long start, unsigned long end)
+{
+        start &= ~(CACHE_LINE_SIZE - 1);
+        while (start < end) {
+                tauros2_clean_pa(start);
+                start += CACHE_LINE_SIZE;
+        }
+        dsb();
+}
+static void tauros2_flush_range(unsigned long start, unsigned long end)
+{
+        start &= ~(CACHE_LINE_SIZE - 1);
+        while (start < end) {
+                tauros2_clean_inv_pa(start);
+                start += CACHE_LINE_SIZE;
+        }
+        dsb();
+}
+#endif
+static inline u32 __init read_extra_features(void)
+{
+        u32 u;
+        __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (u));
+        return u;
+}
+static inline void __init write_extra_features(u32 u)
+{
+        __asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u));
+}
+static void __init disable_l2_prefetch(void)
+{
+        u32 u;
+        /*
+         * Read the CPU Extra Features register and verify that the
+         * Disable L2 Prefetch bit is set.
+         */
+        u = read_extra_features();
+        if (!(u & 0x01000000)) {
+                printk(KERN_INFO "Tauros2: Disabling L2 prefetch.\n");
+                write_extra_features(u | 0x01000000);
+        }
+}
+static inline int __init cpuid_scheme(void)
+{
+        extern int processor_id;
+        return !!((processor_id & 0x000f0000) == 0x000f0000);
+}
+static inline u32 __init read_mmfr3(void)
+{
+        u32 mmfr3;
+        __asm__("mrc p15, 0, %0, c0, c1, 7\n" : "=r" (mmfr3));
+        return mmfr3;
+}
+static inline u32 __init read_actlr(void)
+{
+        u32 actlr;
+        __asm__("mrc p15, 0, %0, c1, c0, 1\n" : "=r" (actlr));
+        return actlr;
+}
+static inline void __init write_actlr(u32 actlr)
+{
+        __asm__("mcr p15, 0, %0, c1, c0, 1\n" : : "r" (actlr));
+}
+void __init tauros2_init(void)
+{
+        extern int processor_id;
+        char *mode;
+        disable_l2_prefetch();
+#ifdef CONFIG_CPU_32v5
+        if ((processor_id & 0xff0f0000) == 0x56050000) {
+                u32 feat;
+                /*
+                 * v5 CPUs with Tauros2 have the L2 cache enable bit
+                 * located in the CPU Extra Features register.
+                 */
+                feat = read_extra_features();
+                if (!(feat & 0x00400000)) {
+                        printk(KERN_INFO "Tauros2: Enabling L2 cache.\n");
+                        write_extra_features(feat | 0x00400000);
+                }
+                mode = "ARMv5";
+                outer_cache.inv_range = tauros2_inv_range;
+                outer_cache.clean_range = tauros2_clean_range;
+                outer_cache.flush_range = tauros2_flush_range;
+        }
+#endif
+#ifdef CONFIG_CPU_32v6
+        /*
+         * Check whether this CPU lacks support for the v7 hierarchical
+         * cache ops.  (PJ4 is in its v6 personality mode if the MMFR3
+         * register indicates no support for the v7 hierarchical cache
+         * ops.)
+         */
+        if (cpuid_scheme() && (read_mmfr3() & 0xf) == 0) {
+                /*
+                 * When Tauros2 is used in an ARMv6 system, the L2
+                 * enable bit is in the ARMv6 ARM-mandated position
+                 * (bit [26] of the System Control Register).
+                 */
+                if (!(get_cr() & 0x04000000)) {
+                        printk(KERN_INFO "Tauros2: Enabling L2 cache.\n");
+                        adjust_cr(0x04000000, 0x04000000);
+                }
+                mode = "ARMv6";
+                outer_cache.inv_range = tauros2_inv_range;
+                outer_cache.clean_range = tauros2_clean_range;
+                outer_cache.flush_range = tauros2_flush_range;
+        }
+#endif
+#ifdef CONFIG_CPU_32v7
+        /*
+         * Check whether this CPU has support for the v7 hierarchical
+         * cache ops.  (PJ4 is in its v7 personality mode if the MMFR3
+         * register indicates support for the v7 hierarchical cache
+         * ops.)
+         *
+         * (Although strictly speaking there may exist CPUs that
+         * implement the v7 cache ops but are only ARMv6 CPUs (due to
+         * not complying with all of the other ARMv7 requirements),
+         * there are no real-life examples of Tauros2 being used on
+         * such CPUs as of yet.)
+         */
+        if (cpuid_scheme() && (read_mmfr3() & 0xf) == 1) {
+                u32 actlr;
+                /*
+                 * When Tauros2 is used in an ARMv7 system, the L2
+                 * enable bit is located in the Auxiliary System Control
+                 * Register (which is the only register allowed by the
+                 * ARMv7 spec to contain fine-grained cache control bits).
+                 */
+                actlr = read_actlr();
+                if (!(actlr & 0x00000002)) {
+                        printk(KERN_INFO "Tauros2: Enabling L2 cache.\n");
+                        write_actlr(actlr | 0x00000002);
+                }
+                mode = "ARMv7";
+        }
+#endif
+        if (mode == NULL) {
+                printk(KERN_CRIT "Tauros2: Unable to detect CPU mode.\n");
+                return;
+        }
+        printk(KERN_INFO "Tauros2: L2 cache support initialised "
+                         "in %s mode.\n", mode);
+}
diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c
index 4127a7bddfe5..841f355319bf 100644
--- a/arch/arm/mm/copypage-v6.c
+++ b/arch/arm/mm/copypage-v6.c
@@ -41,6 +41,14 @@ static void v6_copy_user_highpage_nonaliasing(struct page *to,
        kfrom = kmap_atomic(from, KM_USER0);
        kto = kmap_atomic(to, KM_USER1);
        copy_page(kto, kfrom);
+#ifdef CONFIG_HIGHMEM
+        /*
+         * kmap_atomic() doesn't set the page virtual address, and
+         * kunmap_atomic() takes care of cache flushing already.
+         */
+        if (page_address(to) != NULL)
+#endif
+                __cpuc_flush_dcache_page(kto);
        kunmap_atomic(kto, KM_USER1);
        kunmap_atomic(kfrom, KM_USER0);
 }
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index b9590a7085ca..26325cb5d368 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -63,194 +63,152 @@ static u64 get_coherent_dma_mask(struct device *dev)
        return mask;
 }
-#ifdef CONFIG_MMU
 /*
- * These are the page tables (2MB each) covering uncached, DMA consistent allocations
+ * Allocate a DMA buffer for 'dev' of size 'size' using the
+ * specified gfp mask.  Note that 'size' must be page aligned.
 */
-static pte_t *consistent_pte[NUM_CONSISTENT_PTES];
+static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp)
-static DEFINE_SPINLOCK(consistent_lock);
+{
+        unsigned long order = get_order(size);
+        struct page *page, *p, *e;
+        void *ptr;
+        u64 mask = get_coherent_dma_mask(dev);
-/*
+#ifdef CONFIG_DMA_API_DEBUG
- * VM region handling support.
+        u64 limit = (mask + 1) & ~mask;
- *
+        if (limit && size >= limit) {
- * This should become something generic, handling VM region allocations for
+                dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n",
- * vmalloc and similar (ioremap, module space, etc).
+                        size, mask);
- *
+                return NULL;
- * I envisage vmalloc()'s supporting vm_struct becoming:
+        }
- *
+#endif
- *  struct vm_struct {
- *    struct vm_region  region;
- *    unsigned long     flags;
- *    struct page       **pages;
- *    unsigned int      nr_pages;
- *    unsigned long     phys_addr;
- *  };
- *
- * get_vm_area() would then call vm_region_alloc with an appropriate
- * struct vm_region head (eg):
- *
- *  struct vm_region vmalloc_head = {
- *      .vm_list        = LIST_HEAD_INIT(vmalloc_head.vm_list),
- *      .vm_start       = VMALLOC_START,
- *      .vm_end         = VMALLOC_END,
- *  };
- *
- * However, vmalloc_head.vm_start is variable (typically, it is dependent on
- * the amount of RAM found at boot time.)  I would imagine that get_vm_area()
- * would have to initialise this each time prior to calling vm_region_alloc().
- */
-struct arm_vm_region {
-        struct list_head        vm_list;
-        unsigned long           vm_start;
-        unsigned long           vm_end;
-        struct page             *vm_pages;
-        int                     vm_active;
-};
-static struct arm_vm_region consistent_head = {
+        if (!mask)
-        .vm_list        = LIST_HEAD_INIT(consistent_head.vm_list),
+                return NULL;
-        .vm_start       = CONSISTENT_BASE,
-        .vm_end         = CONSISTENT_END,
-};
-static struct arm_vm_region *
+        if (mask < 0xffffffffULL)
-arm_vm_region_alloc(struct arm_vm_region *head, size_t size, gfp_t gfp)
+                gfp |= GFP_DMA;
-{
-        unsigned long addr = head->vm_start, end = head->vm_end - size;
+        page = alloc_pages(gfp, order);
-        unsigned long flags;
+        if (!page)
-        struct arm_vm_region *c, *new;
+                return NULL;
-        new = kmalloc(sizeof(struct arm_vm_region), gfp);
-        if (!new)
-                goto out;
-        spin_lock_irqsave(&consistent_lock, flags);
-        list_for_each_entry(c, &head->vm_list, vm_list) {
-                if ((addr + size) < addr)
-                        goto nospc;
-                if ((addr + size) <= c->vm_start)
-                        goto found;
-                addr = c->vm_end;
-                if (addr > end)
-                        goto nospc;
-        }
- found:
        /*
-         * Insert this entry _before_ the one we found.
+         * Now split the huge page and free the excess pages
         */
-        list_add_tail(&new->vm_list, &c->vm_list);
+        split_page(page, order);
-        new->vm_start = addr;
+        for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++)
-        new->vm_end = addr + size;
+                __free_page(p);
-        new->vm_active = 1;
+        /*
-        spin_unlock_irqrestore(&consistent_lock, flags);
+         * Ensure that the allocated pages are zeroed, and that any data
-        return new;
+         * lurking in the kernel direct-mapped region is invalidated.
+         */
- nospc:
+        ptr = page_address(page);
-        spin_unlock_irqrestore(&consistent_lock, flags);
+        memset(ptr, 0, size);
-        kfree(new);
+        dmac_flush_range(ptr, ptr + size);
- out:
+        outer_flush_range(__pa(ptr), __pa(ptr) + size);
-        return NULL;
+        return page;
 }
-static struct arm_vm_region *arm_vm_region_find(struct arm_vm_region *head, unsigned long addr)
+/*
+ * Free a DMA buffer.  'size' must be page aligned.
+ */
+static void __dma_free_buffer(struct page *page, size_t size)
 {
-        struct arm_vm_region *c;
+        struct page *e = page + (size >> PAGE_SHIFT);
-        
-        list_for_each_entry(c, &head->vm_list, vm_list) {
+        while (page < e) {
-                if (c->vm_active && c->vm_start == addr)
+                __free_page(page);
-                        goto out;
+                page++;
        }
-        c = NULL;
- out:
-        return c;
 }
+#ifdef CONFIG_MMU
+/*
+ * These are the page tables (2MB each) covering uncached, DMA consistent allocations
+ */
+static pte_t *consistent_pte[NUM_CONSISTENT_PTES];
+#include "vmregion.h"
+static struct arm_vmregion_head consistent_head = {
+        .vm_lock        = __SPIN_LOCK_UNLOCKED(&consistent_head.vm_lock),
+        .vm_list        = LIST_HEAD_INIT(consistent_head.vm_list),
+        .vm_start       = CONSISTENT_BASE,
+        .vm_end         = CONSISTENT_END,
+};
 #ifdef CONFIG_HUGETLB_PAGE
 #error ARM Coherent DMA allocator does not (yet) support huge TLB
 #endif
-static void *
+/*
-__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
+ * Initialise the consistent memory allocation.
-            pgprot_t prot)
+ */
+static int __init consistent_init(void)
 {
-        struct page *page;
+        int ret = 0;
-        struct arm_vm_region *c;
+        pgd_t *pgd;
-        unsigned long order;
+        pmd_t *pmd;
-        u64 mask = get_coherent_dma_mask(dev);
+        pte_t *pte;
-        u64 limit;
+        int i = 0;
+        u32 base = CONSISTENT_BASE;
-        if (!consistent_pte[0]) {
+        do {
-                printk(KERN_ERR "%s: not initialised\n", __func__);
+                pgd = pgd_offset(&init_mm, base);
-                dump_stack();
+                pmd = pmd_alloc(&init_mm, pgd, base);
-                return NULL;
+                if (!pmd) {
-        }
+                        printk(KERN_ERR "%s: no pmd tables\n", __func__);
+                        ret = -ENOMEM;
+                        break;
+                }
+                WARN_ON(!pmd_none(*pmd));
-        if (!mask)
+                pte = pte_alloc_kernel(pmd, base);
-                goto no_page;
+                if (!pte) {
+                        printk(KERN_ERR "%s: no pte tables\n", __func__);
+                        ret = -ENOMEM;
+                        break;
+                }
-        /*
+                consistent_pte[i++] = pte;
-         * Sanity check the allocation size.
+                base += (1 << PGDIR_SHIFT);
-         */
+        } while (base < CONSISTENT_END);
-        size = PAGE_ALIGN(size);
-        limit = (mask + 1) & ~mask;
-        if ((limit && size >= limit) ||
-            size >= (CONSISTENT_END - CONSISTENT_BASE)) {
-                printk(KERN_WARNING "coherent allocation too big "
-                       "(requested %#x mask %#llx)\n", size, mask);
-                goto no_page;
-        }
-        order = get_order(size);
+        return ret;
+}
-        if (mask < 0xffffffffULL)
+core_initcall(consistent_init);
-                gfp |= GFP_DMA;
-        page = alloc_pages(gfp, order);
+static void *
-        if (!page)
+__dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot)
-                goto no_page;
+{
+        struct arm_vmregion *c;
-        /*
+        if (!consistent_pte[0]) {
-         * Invalidate any data that might be lurking in the
+                printk(KERN_ERR "%s: not initialised\n", __func__);
-         * kernel direct-mapped region for device DMA.
+                dump_stack();
-         */
+                return NULL;
-        {
-                void *ptr = page_address(page);
-                memset(ptr, 0, size);
-                dmac_flush_range(ptr, ptr + size);
-                outer_flush_range(__pa(ptr), __pa(ptr) + size);
        }
        /*
         * Allocate a virtual address in the consistent mapping region.
         */
-        c = arm_vm_region_alloc(&consistent_head, size,
+        c = arm_vmregion_alloc(&consistent_head, size,
                            gfp & ~(__GFP_DMA | __GFP_HIGHMEM));
        if (c) {
                pte_t *pte;
-                struct page *end = page + (1 << order);
                int idx = CONSISTENT_PTE_INDEX(c->vm_start);
                u32 off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1);
                pte = consistent_pte[idx] + off;
                c->vm_pages = page;
-                split_page(page, order);
-                /*
-                 * Set the "dma handle"
-                 */
-                *handle = page_to_dma(dev, page);
                do {
                        BUG_ON(!pte_none(*pte));
-                        /*
-                         * x86 does not mark the pages reserved...
-                         */
-                        SetPageReserved(page);
                        set_pte_ext(pte, mk_pte(page, prot), 0);
                        page++;
                        pte++;
@@ -261,48 +219,90 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
                        }
                } while (size -= PAGE_SIZE);
-                /*
-                 * Free the otherwise unused pages.
-                 */
-                while (page < end) {
-                        __free_page(page);
-                        page++;
-                }
                return (void *)c->vm_start;
        }
-        if (page)
-                __free_pages(page, order);
- no_page:
-        *handle = ~0;
        return NULL;
 }
+static void __dma_free_remap(void *cpu_addr, size_t size)
+{
+        struct arm_vmregion *c;
+        unsigned long addr;
+        pte_t *ptep;
+        int idx;
+        u32 off;
+        c = arm_vmregion_find_remove(&consistent_head, (unsigned long)cpu_addr);
+        if (!c) {
+                printk(KERN_ERR "%s: trying to free invalid coherent area: %p\n",
+                       __func__, cpu_addr);
+                dump_stack();
+                return;
+        }
+        if ((c->vm_end - c->vm_start) != size) {
+                printk(KERN_ERR "%s: freeing wrong coherent size (%ld != %d)\n",
+                       __func__, c->vm_end - c->vm_start, size);
+                dump_stack();
+                size = c->vm_end - c->vm_start;
+        }
+        idx = CONSISTENT_PTE_INDEX(c->vm_start);
+        off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1);
+        ptep = consistent_pte[idx] + off;
+        addr = c->vm_start;
+        do {
+                pte_t pte = ptep_get_and_clear(&init_mm, addr, ptep);
+                ptep++;
+                addr += PAGE_SIZE;
+                off++;
+                if (off >= PTRS_PER_PTE) {
+                        off = 0;
+                        ptep = consistent_pte[++idx];
+                }
+                if (pte_none(pte) || !pte_present(pte))
+                        printk(KERN_CRIT "%s: bad page in kernel page table\n",
+                               __func__);
+        } while (size -= PAGE_SIZE);
+        flush_tlb_kernel_range(c->vm_start, c->vm_end);
+        arm_vmregion_free(&consistent_head, c);
+}
 #else   /* !CONFIG_MMU */
+#define __dma_alloc_remap(page, size, gfp, prot)        page_address(page)
+#define __dma_free_remap(addr, size)                    do { } while (0)
+#endif  /* CONFIG_MMU */
 static void *
 __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
            pgprot_t prot)
 {
-        void *virt;
+        struct page *page;
-        u64 mask = get_coherent_dma_mask(dev);
+        void *addr;
-        if (!mask)
+        *handle = ~0;
-                goto error;
+        size = PAGE_ALIGN(size);
-        if (mask < 0xffffffffULL)
+        page = __dma_alloc_buffer(dev, size, gfp);
-                gfp |= GFP_DMA;
+        if (!page)
-        virt = kmalloc(size, gfp);
+                return NULL;
-        if (!virt)
-                goto error;
-        *handle =  virt_to_dma(dev, virt);
+        if (!arch_is_coherent())
-        return virt;
+                addr = __dma_alloc_remap(page, size, gfp, prot);
+        else
+                addr = page_address(page);
-error:
+        if (addr)
-        *handle = ~0;
+                *handle = page_to_dma(dev, page);
-        return NULL;
+        return addr;
 }
-#endif  /* CONFIG_MMU */
 /*
 * Allocate DMA-coherent memory space and return both the kernel remapped
@@ -316,19 +316,8 @@ dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gf
        if (dma_alloc_from_coherent(dev, size, handle, &memory))
                return memory;
-        if (arch_is_coherent()) {
-                void *virt;
-                virt = kmalloc(size, gfp);
-                if (!virt)
-                        return NULL;
-                *handle =  virt_to_dma(dev, virt);
-                return virt;
-        }
        return __dma_alloc(dev, size, handle, gfp,
-                           pgprot_noncached(pgprot_kernel));
+                           pgprot_dmacoherent(pgprot_kernel));
 }
 EXPORT_SYMBOL(dma_alloc_coherent);
@@ -349,15 +338,12 @@ static int dma_mmap(struct device *dev, struct vm_area_struct *vma,
 {
        int ret = -ENXIO;
 #ifdef CONFIG_MMU
-        unsigned long flags, user_size, kern_size;
+        unsigned long user_size, kern_size;
-        struct arm_vm_region *c;
+        struct arm_vmregion *c;
        user_size = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
-        spin_lock_irqsave(&consistent_lock, flags);
+        c = arm_vmregion_find(&consistent_head, (unsigned long)cpu_addr);
-        c = arm_vm_region_find(&consistent_head, (unsigned long)cpu_addr);
-        spin_unlock_irqrestore(&consistent_lock, flags);
        if (c) {
                unsigned long off = vma->vm_pgoff;
@@ -379,7 +365,7 @@ static int dma_mmap(struct device *dev, struct vm_area_struct *vma,
 int dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma,
                      void *cpu_addr, dma_addr_t dma_addr, size_t size)
 {
-        vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+        vma->vm_page_prot = pgprot_dmacoherent(vma->vm_page_prot);
        return dma_mmap(dev, vma, cpu_addr, dma_addr, size);
 }
 EXPORT_SYMBOL(dma_mmap_coherent);
@@ -396,144 +382,23 @@ EXPORT_SYMBOL(dma_mmap_writecombine);
 * free a page as defined by the above mapping.
 * Must not be called with IRQs disabled.
 */
-#ifdef CONFIG_MMU
 void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr_t handle)
 {
-        struct arm_vm_region *c;
-        unsigned long flags, addr;
-        pte_t *ptep;
-        int idx;
-        u32 off;
        WARN_ON(irqs_disabled());
        if (dma_release_from_coherent(dev, get_order(size), cpu_addr))
                return;
-        if (arch_is_coherent()) {
-                kfree(cpu_addr);
-                return;
-        }
        size = PAGE_ALIGN(size);
-        spin_lock_irqsave(&consistent_lock, flags);
+        if (!arch_is_coherent())
-        c = arm_vm_region_find(&consistent_head, (unsigned long)cpu_addr);
+                __dma_free_remap(cpu_addr, size);
-        if (!c)
-                goto no_area;
-        c->vm_active = 0;
-        spin_unlock_irqrestore(&consistent_lock, flags);
-        if ((c->vm_end - c->vm_start) != size) {
-                printk(KERN_ERR "%s: freeing wrong coherent size (%ld != %d)\n",
-                       __func__, c->vm_end - c->vm_start, size);
-                dump_stack();
-                size = c->vm_end - c->vm_start;
-        }
-        idx = CONSISTENT_PTE_INDEX(c->vm_start);
-        off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1);
-        ptep = consistent_pte[idx] + off;
-        addr = c->vm_start;
-        do {
-                pte_t pte = ptep_get_and_clear(&init_mm, addr, ptep);
-                unsigned long pfn;
-                ptep++;
-                addr += PAGE_SIZE;
-                off++;
-                if (off >= PTRS_PER_PTE) {
-                        off = 0;
-                        ptep = consistent_pte[++idx];
-                }
-                if (!pte_none(pte) && pte_present(pte)) {
-                        pfn = pte_pfn(pte);
-                        if (pfn_valid(pfn)) {
-                                struct page *page = pfn_to_page(pfn);
-                                /*
-                                 * x86 does not mark the pages reserved...
-                                 */
-                                ClearPageReserved(page);
-                                __free_page(page);
-                                continue;
-                        }
-                }
-                printk(KERN_CRIT "%s: bad page in kernel page table\n",
-                       __func__);
-        } while (size -= PAGE_SIZE);
-        flush_tlb_kernel_range(c->vm_start, c->vm_end);
-        spin_lock_irqsave(&consistent_lock, flags);
-        list_del(&c->vm_list);
-        spin_unlock_irqrestore(&consistent_lock, flags);
-        kfree(c);
-        return;
- no_area:
+        __dma_free_buffer(dma_to_page(dev, handle), size);
-        spin_unlock_irqrestore(&consistent_lock, flags);
-        printk(KERN_ERR "%s: trying to free invalid coherent area: %p\n",
-               __func__, cpu_addr);
-        dump_stack();
 }
-#else   /* !CONFIG_MMU */
-void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr_t handle)
-{
-        if (dma_release_from_coherent(dev, get_order(size), cpu_addr))
-                return;
-        kfree(cpu_addr);
-}
-#endif  /* CONFIG_MMU */
 EXPORT_SYMBOL(dma_free_coherent);
 /*
- * Initialise the consistent memory allocation.
- */
-static int __init consistent_init(void)
-{
-        int ret = 0;
-#ifdef CONFIG_MMU
-        pgd_t *pgd;
-        pmd_t *pmd;
-        pte_t *pte;
-        int i = 0;
-        u32 base = CONSISTENT_BASE;
-        do {
-                pgd = pgd_offset(&init_mm, base);
-                pmd = pmd_alloc(&init_mm, pgd, base);
-                if (!pmd) {
-                        printk(KERN_ERR "%s: no pmd tables\n", __func__);
-                        ret = -ENOMEM;
-                        break;
-                }
-                WARN_ON(!pmd_none(*pmd));
-                pte = pte_alloc_kernel(pmd, base);
-                if (!pte) {
-                        printk(KERN_ERR "%s: no pte tables\n", __func__);
-                        ret = -ENOMEM;
-                        break;
-                }
-                consistent_pte[i++] = pte;
-                base += (1 << PGDIR_SHIFT);
-        } while (base < CONSISTENT_END);
-#endif  /* !CONFIG_MMU */
-        return ret;
-}
-core_initcall(consistent_init);
-/*
 * Make an area consistent for devices.
 * Note: Drivers should NOT use this function directly, as it will break
 * platforms with CONFIG_DMABOUNCE.
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index d0d17b6a3703..729602291958 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -23,6 +23,8 @@
 #include <asm/pgtable.h>
 #include <asm/tlbflush.h>
+#include "mm.h"
 static unsigned long shared_pte_mask = L_PTE_MT_BUFFERABLE;
 /*
@@ -151,7 +153,14 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
        if (!pfn_valid(pfn))
                return;
+        /*
+         * The zero page is never written to, so never has any dirty
+         * cache lines, and therefore never needs to be flushed.
+         */
        page = pfn_to_page(pfn);
+        if (page == ZERO_PAGE(0))
+                return;
        mapping = page_mapping(page);
 #ifndef CONFIG_SMP
        if (test_and_clear_bit(PG_dcache_dirty, &page->flags))
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 7f294f307c83..329594e760cd 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -35,14 +35,12 @@ static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr)
            :
            : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero)
            : "cc");
-        __flush_icache_all();
 }
 void flush_cache_mm(struct mm_struct *mm)
 {
        if (cache_is_vivt()) {
-                if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm)))
+                vivt_flush_cache_mm(mm);
-                        __cpuc_flush_user_all();
                return;
        }
@@ -52,16 +50,13 @@ void flush_cache_mm(struct mm_struct *mm)
                    :
                    : "r" (0)
                    : "cc");
-                __flush_icache_all();
        }
 }
 void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
 {
        if (cache_is_vivt()) {
-                if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm)))
+                vivt_flush_cache_range(vma, start, end);
-                        __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
-                                                vma->vm_flags);
                return;
        }
@@ -71,22 +66,26 @@ void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned
                    :
                    : "r" (0)
                    : "cc");
-                __flush_icache_all();
        }
+        if (vma->vm_flags & VM_EXEC)
+                __flush_icache_all();
 }
 void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
 {
        if (cache_is_vivt()) {
-                if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
+                vivt_flush_cache_page(vma, user_addr, pfn);
-                        unsigned long addr = user_addr & PAGE_MASK;
-                        __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
-                }
                return;
        }
-        if (cache_is_vipt_aliasing())
+        if (cache_is_vipt_aliasing()) {
                flush_pfn_alias(pfn, user_addr);
+                __flush_icache_all();
+        }
+        if (vma->vm_flags & VM_EXEC && icache_is_vivt_asid_tagged())
+                __flush_icache_all();
 }
 void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
@@ -94,15 +93,13 @@ void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
                         unsigned long len, int write)
 {
        if (cache_is_vivt()) {
-                if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
+                vivt_flush_ptrace_access(vma, page, uaddr, kaddr, len, write);
-                        unsigned long addr = (unsigned long)kaddr;
-                        __cpuc_coherent_kern_range(addr, addr + len);
-                }
                return;
        }
        if (cache_is_vipt_aliasing()) {
                flush_pfn_alias(page_to_pfn(page), uaddr);
+                __flush_icache_all();
                return;
        }
@@ -120,6 +117,8 @@ void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
 void __flush_dcache_page(struct address_space *mapping, struct page *page)
 {
+        void *addr = page_address(page);
        /*
         * Writeback any data associated with the kernel mapping of this
         * page.  This ensures that data in the physical page is mutually
@@ -130,9 +129,9 @@ void __flush_dcache_page(struct address_space *mapping, struct page *page)
         * kmap_atomic() doesn't set the page virtual address, and
         * kunmap_atomic() takes care of cache flushing already.
         */
-        if (page_address(page))
+        if (addr)
 #endif
-                __cpuc_flush_dcache_page(page_address(page));
+                __cpuc_flush_dcache_page(addr);
        /*
         * If this is a page cache page, and we have an aliasing VIPT cache,
@@ -196,7 +195,16 @@ static void __flush_dcache_aliases(struct address_space *mapping, struct page *p
 */
 void flush_dcache_page(struct page *page)
 {
-        struct address_space *mapping = page_mapping(page);
+        struct address_space *mapping;
+        /*
+         * The zero page is never written to, so never has any dirty
+         * cache lines, and therefore never needs to be flushed.
+         */
+        if (page == ZERO_PAGE(0))
+                return;
+        mapping = page_mapping(page);
 #ifndef CONFIG_SMP
        if (!PageHighMem(page) && mapping && !mapping_mapped(mapping))
@@ -242,6 +250,7 @@ void __flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned l
                 * userspace address only.
                 */
                flush_pfn_alias(pfn, vmaddr);
+                __flush_icache_all();
        }
        /*
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
index c4f6f05198e0..a888363398f8 100644
--- a/arch/arm/mm/mm.h
+++ b/arch/arm/mm/mm.h
@@ -24,6 +24,8 @@ struct mem_type {
 const struct mem_type *get_mem_type(unsigned int type);
+extern void __flush_dcache_page(struct address_space *mapping, struct page *page);
 #endif
 struct map_desc;
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index ea67be0223ac..8c7fbd19a4b3 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -881,7 +881,7 @@ void __init reserve_node_zero(pg_data_t *pgdat)
                                BOOTMEM_EXCLUSIVE);
        }
-        if (machine_is_treo680()) {
+        if (machine_is_treo680() || machine_is_centro()) {
                reserve_bootmem_node(pgdat, 0xa0000000, 0x1000,
                                BOOTMEM_EXCLUSIVE);
                reserve_bootmem_node(pgdat, 0xa2000000, 0x1000,
@@ -1036,7 +1036,7 @@ void __init paging_init(struct machine_desc *mdesc)
         */
        zero_page = alloc_bootmem_low_pages(PAGE_SIZE);
        empty_zero_page = virt_to_page(zero_page);
-        flush_dcache_page(empty_zero_page);
+        __flush_dcache_page(NULL, empty_zero_page);
 }
 /*
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 70f75d2e3ead..5485c821101c 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -130,9 +130,16 @@ ENTRY(cpu_v6_set_pte_ext)
+        .type   cpu_v6_name, #object
 cpu_v6_name:
        .asciz  "ARMv6-compatible processor"
+        .size   cpu_v6_name, . - cpu_v6_name
+        .type   cpu_pj4_name, #object
+cpu_pj4_name:
+        .asciz  "Marvell PJ4 processor"
+        .size   cpu_pj4_name, . - cpu_pj4_name
        .align
        __INIT
@@ -241,3 +248,27 @@ __v6_proc_info:
        .long   v6_user_fns
        .long   v6_cache_fns
        .size   __v6_proc_info, . - __v6_proc_info
+        .type   __pj4_v6_proc_info, #object
+__pj4_v6_proc_info:
+        .long   0x560f5810
+        .long   0xff0ffff0
+        .long   PMD_TYPE_SECT | \
+                PMD_SECT_BUFFERABLE | \
+                PMD_SECT_CACHEABLE | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ
+        .long   PMD_TYPE_SECT | \
+                PMD_SECT_XN | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ
+        b       __v6_setup
+        .long   cpu_arch_name
+        .long   cpu_elf_name
+        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+        .long   cpu_pj4_name
+        .long   v6_processor_functions
+        .long   v6wbi_tlb_fns
+        .long   v6_user_fns
+        .long   v6_cache_fns
+        .size   __pj4_v6_proc_info, . - __pj4_v6_proc_info
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 2028f3702881..fab134e29826 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -396,7 +396,7 @@ __xsc3_setup:
        orr     r4, r4, #0x18                   @ cache the page table in L2
        mcr     p15, 0, r4, c2, c0, 0           @ load page table pointer
-        mov     r0, #0                          @ don't allow CP access
+        mov     r0, #1 << 6                     @ cp6 access for early sched_clock
        mcr     p15, 0, r0, c15, c1, 0          @ write CP access register
        mrc     p15, 0, r0, c1, c0, 1           @ get auxiliary control reg
diff --git a/arch/arm/mm/vmregion.c b/arch/arm/mm/vmregion.c
new file mode 100644
index 000000000000..19e09bdb1b8a
--- /dev/null
+++ b/arch/arm/mm/vmregion.c
@@ -0,0 +1,131 @@
+#include <linux/spinlock.h>
+#include <linux/list.h>
+#include <linux/slab.h>
+#include "vmregion.h"
+/*
+ * VM region handling support.
+ *
+ * This should become something generic, handling VM region allocations for
+ * vmalloc and similar (ioremap, module space, etc).
+ *
+ * I envisage vmalloc()'s supporting vm_struct becoming:
+ *
+ *  struct vm_struct {
+ *    struct vmregion   region;
+ *    unsigned long     flags;
+ *    struct page       **pages;
+ *    unsigned int      nr_pages;
+ *    unsigned long     phys_addr;
+ *  };
+ *
+ * get_vm_area() would then call vmregion_alloc with an appropriate
+ * struct vmregion head (eg):
+ *
+ *  struct vmregion vmalloc_head = {
+ *      .vm_list        = LIST_HEAD_INIT(vmalloc_head.vm_list),
+ *      .vm_start       = VMALLOC_START,
+ *      .vm_end         = VMALLOC_END,
+ *  };
+ *
+ * However, vmalloc_head.vm_start is variable (typically, it is dependent on
+ * the amount of RAM found at boot time.)  I would imagine that get_vm_area()
+ * would have to initialise this each time prior to calling vmregion_alloc().
+ */
+struct arm_vmregion *
+arm_vmregion_alloc(struct arm_vmregion_head *head, size_t size, gfp_t gfp)
+{
+        unsigned long addr = head->vm_start, end = head->vm_end - size;
+        unsigned long flags;
+        struct arm_vmregion *c, *new;
+        if (head->vm_end - head->vm_start < size) {
+                printk(KERN_WARNING "%s: allocation too big (requested %#x)\n",
+                        __func__, size);
+                goto out;
+        }
+        new = kmalloc(sizeof(struct arm_vmregion), gfp);
+        if (!new)
+                goto out;
+        spin_lock_irqsave(&head->vm_lock, flags);
+        list_for_each_entry(c, &head->vm_list, vm_list) {
+                if ((addr + size) < addr)
+                        goto nospc;
+                if ((addr + size) <= c->vm_start)
+                        goto found;
+                addr = c->vm_end;
+                if (addr > end)
+                        goto nospc;
+        }
+ found:
+        /*
+         * Insert this entry _before_ the one we found.
+         */
+        list_add_tail(&new->vm_list, &c->vm_list);
+        new->vm_start = addr;
+        new->vm_end = addr + size;
+        new->vm_active = 1;
+        spin_unlock_irqrestore(&head->vm_lock, flags);
+        return new;
+ nospc:
+        spin_unlock_irqrestore(&head->vm_lock, flags);
+        kfree(new);
+ out:
+        return NULL;
+}
+static struct arm_vmregion *__arm_vmregion_find(struct arm_vmregion_head *head, unsigned long addr)
+{
+        struct arm_vmregion *c;
+        list_for_each_entry(c, &head->vm_list, vm_list) {
+                if (c->vm_active && c->vm_start == addr)
+                        goto out;
+        }
+        c = NULL;
+ out:
+        return c;
+}
+struct arm_vmregion *arm_vmregion_find(struct arm_vmregion_head *head, unsigned long addr)
+{
+        struct arm_vmregion *c;
+        unsigned long flags;
+        spin_lock_irqsave(&head->vm_lock, flags);
+        c = __arm_vmregion_find(head, addr);
+        spin_unlock_irqrestore(&head->vm_lock, flags);
+        return c;
+}
+struct arm_vmregion *arm_vmregion_find_remove(struct arm_vmregion_head *head, unsigned long addr)
+{
+        struct arm_vmregion *c;
+        unsigned long flags;
+        spin_lock_irqsave(&head->vm_lock, flags);
+        c = __arm_vmregion_find(head, addr);
+        if (c)
+                c->vm_active = 0;
+        spin_unlock_irqrestore(&head->vm_lock, flags);
+        return c;
+}
+void arm_vmregion_free(struct arm_vmregion_head *head, struct arm_vmregion *c)
+{
+        unsigned long flags;
+        spin_lock_irqsave(&head->vm_lock, flags);
+        list_del(&c->vm_list);
+        spin_unlock_irqrestore(&head->vm_lock, flags);
+        kfree(c);
+}
diff --git a/arch/arm/mm/vmregion.h b/arch/arm/mm/vmregion.h
new file mode 100644
index 000000000000..6b2cdbdf3a85
--- /dev/null
+++ b/arch/arm/mm/vmregion.h
@@ -0,0 +1,29 @@
+#ifndef VMREGION_H
+#define VMREGION_H
+#include <linux/spinlock.h>
+#include <linux/list.h>
+struct page;
+struct arm_vmregion_head {
+        spinlock_t              vm_lock;
+        struct list_head        vm_list;
+        unsigned long           vm_start;
+        unsigned long           vm_end;
+};
+struct arm_vmregion {
+        struct list_head        vm_list;
+        unsigned long           vm_start;
+        unsigned long           vm_end;
+        struct page             *vm_pages;
+        int                     vm_active;
+};
+struct arm_vmregion *arm_vmregion_alloc(struct arm_vmregion_head *, size_t, gfp_t);
+struct arm_vmregion *arm_vmregion_find(struct arm_vmregion_head *, unsigned long);
+struct arm_vmregion *arm_vmregion_find_remove(struct arm_vmregion_head *, unsigned long);
+void arm_vmregion_free(struct arm_vmregion_head *, struct arm_vmregion *);
+#endif
diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c
index 8da95d57c21f..6c8a02ad98e3 100644
--- a/arch/arm/plat-iop/time.c
+++ b/arch/arm/plat-iop/time.c
@@ -19,6 +19,8 @@
 #include <linux/init.h>
 #include <linux/timex.h>
 #include <linux/io.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/uaccess.h>
@@ -26,45 +28,136 @@
 #include <asm/mach/time.h>
 #include <mach/time.h>
+/*
+ * IOP clocksource (free-running timer 1).
+ */
+static cycle_t iop_clocksource_read(struct clocksource *unused)
+{
+        return 0xffffffffu - read_tcr1();
+}
+static struct clocksource iop_clocksource = {
+        .name           = "iop_timer1",
+        .rating         = 300,
+        .read           = iop_clocksource_read,
+        .mask           = CLOCKSOURCE_MASK(32),
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+static void __init iop_clocksource_set_hz(struct clocksource *cs, unsigned int hz)
+{
+        u64 temp;
+        u32 shift;
+        /* Find shift and mult values for hz. */
+        shift = 32;
+        do {
+                temp = (u64) NSEC_PER_SEC << shift;
+                do_div(temp, hz);
+                if ((temp >> 32) == 0)
+                        break;
+        } while (--shift != 0);
+        cs->shift = shift;
+        cs->mult = (u32) temp;
+        printk(KERN_INFO "clocksource: %s uses shift %u mult %#x\n",
+               cs->name, cs->shift, cs->mult);
+}
+/*
+ * IOP sched_clock() implementation via its clocksource.
+ */
+unsigned long long sched_clock(void)
+{
+        cycle_t cyc = iop_clocksource_read(NULL);
+        struct clocksource *cs = &iop_clocksource;
+        return clocksource_cyc2ns(cyc, cs->mult, cs->shift);
+}
+/*
+ * IOP clockevents (interrupting timer 0).
+ */
+static int iop_set_next_event(unsigned long delta,
+                              struct clock_event_device *unused)
+{
+        u32 tmr = IOP_TMR_PRIVILEGED | IOP_TMR_RATIO_1_1;
+        BUG_ON(delta == 0);
+        write_tmr0(tmr & ~(IOP_TMR_EN | IOP_TMR_RELOAD));
+        write_tcr0(delta);
+        write_tmr0((tmr & ~IOP_TMR_RELOAD) | IOP_TMR_EN);
+        return 0;
+}
 static unsigned long ticks_per_jiffy;
-static unsigned long ticks_per_usec;
-static unsigned long next_jiffy_time;
-unsigned long iop_gettimeoffset(void)
+static void iop_set_mode(enum clock_event_mode mode,
+                         struct clock_event_device *unused)
 {
-        unsigned long offset, temp;
+        u32 tmr = read_tmr0();
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                write_tmr0(tmr & ~IOP_TMR_EN);
+                write_tcr0(ticks_per_jiffy - 1);
+                tmr |= (IOP_TMR_RELOAD | IOP_TMR_EN);
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+                /* ->set_next_event sets period and enables timer */
+                tmr &= ~(IOP_TMR_RELOAD | IOP_TMR_EN);
+                break;
+        case CLOCK_EVT_MODE_RESUME:
+                tmr |= IOP_TMR_EN;
+                break;
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_UNUSED:
+        default:
+                tmr &= ~IOP_TMR_EN;
+                break;
+        }
-        /* enable cp6, if necessary, to avoid taking the overhead of an
+        write_tmr0(tmr);
-         * undefined instruction trap
+}
-         */
-        asm volatile (
+static struct clock_event_device iop_clockevent = {
-        "mrc    p15, 0, %0, c15, c1, 0\n\t"
+        .name           = "iop_timer0",
-        "tst    %0, #(1 << 6)\n\t"
+        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-        "orreq  %0, %0, #(1 << 6)\n\t"
+        .rating         = 300,
-        "mcreq  p15, 0, %0, c15, c1, 0\n\t"
+        .set_next_event = iop_set_next_event,
-#ifdef CONFIG_CPU_XSCALE
+        .set_mode       = iop_set_mode,
-        "mrceq  p15, 0, %0, c15, c1, 0\n\t"
+};
-        "moveq  %0, %0\n\t"
-        "subeq  pc, pc, #4\n\t"
+static void __init iop_clockevent_set_hz(struct clock_event_device *ce, unsigned int hz)
-#endif
+{
-        : "=r"(temp) : : "cc");
+        u64 temp;
+        u32 shift;
-        offset = next_jiffy_time - read_tcr1();
+        /* Find shift and mult values for hz. */
-        return offset / ticks_per_usec;
+        shift = 32;
+        do {
+                temp = (u64) hz << shift;
+                do_div(temp, NSEC_PER_SEC);
+                if ((temp >> 32) == 0)
+                        break;
+        } while (--shift != 0);
+        ce->shift = shift;
+        ce->mult = (u32) temp;
+        printk(KERN_INFO "clockevent: %s uses shift %u mult %#lx\n",
+               ce->name, ce->shift, ce->mult);
 }
 static irqreturn_t
 iop_timer_interrupt(int irq, void *dev_id)
 {
-        write_tisr(1);
+        struct clock_event_device *evt = dev_id;
-        while ((signed long)(next_jiffy_time - read_tcr1())
-                >= ticks_per_jiffy) {
-                timer_tick();
-                next_jiffy_time -= ticks_per_jiffy;
-        }
+        write_tisr(1);
+        evt->event_handler(evt);
        return IRQ_HANDLED;
 }
@@ -72,6 +165,7 @@ static struct irqaction iop_timer_irq = {
        .name           = "IOP Timer Tick",
        .handler        = iop_timer_interrupt,
        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .dev_id         = &iop_clockevent,
 };
 static unsigned long iop_tick_rate;
@@ -86,21 +180,33 @@ void __init iop_init_time(unsigned long tick_rate)
        u32 timer_ctl;
        ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ);
-        ticks_per_usec = tick_rate / 1000000;
-        next_jiffy_time = 0xffffffff;
        iop_tick_rate = tick_rate;
        timer_ctl = IOP_TMR_EN | IOP_TMR_PRIVILEGED |
                        IOP_TMR_RELOAD | IOP_TMR_RATIO_1_1;
        /*
-         * We use timer 0 for our timer interrupt, and timer 1 as
+         * Set up interrupting clockevent timer 0.
-         * monotonic counter for tracking missed jiffies.
         */
+        write_tmr0(timer_ctl & ~IOP_TMR_EN);
+        setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
+        iop_clockevent_set_hz(&iop_clockevent, tick_rate);
+        iop_clockevent.max_delta_ns =
+                clockevent_delta2ns(0xfffffffe, &iop_clockevent);
+        iop_clockevent.min_delta_ns =
+                clockevent_delta2ns(0xf, &iop_clockevent);
+        iop_clockevent.cpumask = cpumask_of(0);
+        clockevents_register_device(&iop_clockevent);
        write_trr0(ticks_per_jiffy - 1);
+        write_tcr0(ticks_per_jiffy - 1);
        write_tmr0(timer_ctl);
+        /*
+         * Set up free-running clocksource timer 1.
+         */
        write_trr1(0xffffffff);
+        write_tcr1(0xffffffff);
        write_tmr1(timer_ctl);
+        iop_clocksource_set_hz(&iop_clocksource, tick_rate);
-        setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
+        clocksource_register(&iop_clocksource);
 }
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index ca5c7c226341..8b0a1ee039fa 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -69,10 +69,20 @@ config MXC_PWM
        help
          Enable support for the i.MX PWM controller(s).
+config MXC_ULPI
+        bool
 config ARCH_HAS_RNGA
        bool
        depends on ARCH_MXC
 config ARCH_MXC_IOMUX_V3
        bool
+config ARCH_MXC_AUDMUX_V1
+        bool
+config ARCH_MXC_AUDMUX_V2
+        bool
 endif
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index e3212c8ff421..4cbca9da1505 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -9,3 +9,6 @@ obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o
 obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o
 obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
 obj-$(CONFIG_MXC_PWM)  += pwm.o
+obj-$(CONFIG_MXC_ULPI) += ulpi.o
+obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
+obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o
diff --git a/arch/arm/plat-mxc/audmux-v1.c b/arch/arm/plat-mxc/audmux-v1.c
new file mode 100644
index 000000000000..da6387dcdf21
--- /dev/null
+++ b/arch/arm/plat-mxc/audmux-v1.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * Initial development of this code was funded by
+ * Phytec Messtechnik GmbH, http://www.phytec.de
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <mach/audmux.h>
+#include <mach/hardware.h>
+static void __iomem *audmux_base;
+static unsigned char port_mapping[] = {
+        0x0, 0x4, 0x8, 0x10, 0x14, 0x1c,
+};
+int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr)
+{
+        if (!audmux_base) {
+                printk("%s: not configured\n", __func__);
+                return -ENOSYS;
+        }
+        if (port >= ARRAY_SIZE(port_mapping))
+                return -EINVAL;
+        writel(pcr, audmux_base + port_mapping[port]);
+        return 0;
+}
+EXPORT_SYMBOL_GPL(mxc_audmux_v1_configure_port);
+static int mxc_audmux_v1_init(void)
+{
+        if (cpu_is_mx27() || cpu_is_mx21())
+                audmux_base = IO_ADDRESS(AUDMUX_BASE_ADDR);
+        return 0;
+}
+postcore_initcall(mxc_audmux_v1_init);
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c
new file mode 100644
index 000000000000..6f21096086fd
--- /dev/null
+++ b/arch/arm/plat-mxc/audmux-v2.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * Initial development of this code was funded by
+ * Phytec Messtechnik GmbH, http://www.phytec.de
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <mach/audmux.h>
+#include <mach/hardware.h>
+static struct clk *audmux_clk;
+static void __iomem *audmux_base;
+#define MXC_AUDMUX_V2_PTCR(x)           ((x) * 8)
+#define MXC_AUDMUX_V2_PDCR(x)           ((x) * 8 + 4)
+int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
+                unsigned int pdcr)
+{
+        if (!audmux_base)
+                return -ENOSYS;
+        if (audmux_clk)
+                clk_enable(audmux_clk);
+        writel(ptcr, audmux_base + MXC_AUDMUX_V2_PTCR(port));
+        writel(pdcr, audmux_base + MXC_AUDMUX_V2_PDCR(port));
+        if (audmux_clk)
+                clk_disable(audmux_clk);
+        return 0;
+}
+EXPORT_SYMBOL_GPL(mxc_audmux_v2_configure_port);
+static int mxc_audmux_v2_init(void)
+{
+        int ret;
+        if (cpu_is_mx35()) {
+                audmux_clk = clk_get(NULL, "audmux");
+                if (IS_ERR(audmux_clk)) {
+                        ret = PTR_ERR(audmux_clk);
+                        printk(KERN_ERR "%s: cannot get clock: %d\n", __func__,
+                                        ret);
+                        return ret;
+                }
+        }
+        if (cpu_is_mx31() || cpu_is_mx35())
+                audmux_base = IO_ADDRESS(AUDMUX_BASE_ADDR);
+        return 0;
+}
+postcore_initcall(mxc_audmux_v2_init);
diff --git a/arch/arm/plat-mxc/dma-mx1-mx2.c b/arch/arm/plat-mxc/dma-mx1-mx2.c
index 77646436c00e..9c1b3f9c4f4d 100644
--- a/arch/arm/plat-mxc/dma-mx1-mx2.c
+++ b/arch/arm/plat-mxc/dma-mx1-mx2.c
@@ -156,7 +156,8 @@ static inline int imx_dma_sg_next(int channel, struct scatterlist *sg)
        }
        now = min(imxdma->resbytes, sg->length);
-        imxdma->resbytes -= now;
+        if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
+                imxdma->resbytes -= now;
        if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
                __raw_writel(sg->dma_address, DMA_BASE + DMA_DAR(channel));
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index cfc4a8b43e6a..d65ebe303b9f 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -282,7 +282,7 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
                for (j = port[i].virtual_irq_start;
                        j < port[i].virtual_irq_start + 32; j++) {
                        set_irq_chip(j, &gpio_irq_chip);
-                        set_irq_handler(j, handle_edge_irq);
+                        set_irq_handler(j, handle_level_irq);
                        set_irq_flags(j, IRQF_VALID);
                }
diff --git a/arch/arm/plat-mxc/include/mach/audmux.h b/arch/arm/plat-mxc/include/mach/audmux.h
new file mode 100644
index 000000000000..5cd6466964af
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/audmux.h
@@ -0,0 +1,52 @@
+#ifndef __MACH_AUDMUX_H
+#define __MACH_AUDMUX_H
+#define MX27_AUDMUX_HPCR1_SSI0          0
+#define MX27_AUDMUX_HPCR2_SSI1          1
+#define MX27_AUDMUX_HPCR3_SSI_PINS_4    2
+#define MX27_AUDMUX_PPCR1_SSI_PINS_1    3
+#define MX27_AUDMUX_PPCR2_SSI_PINS_2    4
+#define MX27_AUDMUX_PPCR3_SSI_PINS_3    5
+#define MX31_AUDMUX_PORT1_SSI0          0
+#define MX31_AUDMUX_PORT2_SSI1          1
+#define MX31_AUDMUX_PORT3_SSI_PINS_3    2
+#define MX31_AUDMUX_PORT4_SSI_PINS_4    3
+#define MX31_AUDMUX_PORT5_SSI_PINS_5    4
+#define MX31_AUDMUX_PORT6_SSI_PINS_6    5
+/* Register definitions for the i.MX21/27 Digital Audio Multiplexer */
+#define MXC_AUDMUX_V1_PCR_INMMASK(x)    ((x) & 0xff)
+#define MXC_AUDMUX_V1_PCR_INMEN         (1 << 8)
+#define MXC_AUDMUX_V1_PCR_TXRXEN        (1 << 10)
+#define MXC_AUDMUX_V1_PCR_SYN           (1 << 12)
+#define MXC_AUDMUX_V1_PCR_RXDSEL(x)     (((x) & 0x7) << 13)
+#define MXC_AUDMUX_V1_PCR_RFCSEL(x)     (((x) & 0xf) << 20)
+#define MXC_AUDMUX_V1_PCR_RCLKDIR       (1 << 24)
+#define MXC_AUDMUX_V1_PCR_RFSDIR        (1 << 25)
+#define MXC_AUDMUX_V1_PCR_TFCSEL(x)     (((x) & 0xf) << 26)
+#define MXC_AUDMUX_V1_PCR_TCLKDIR       (1 << 30)
+#define MXC_AUDMUX_V1_PCR_TFSDIR        (1 << 31)
+/* Register definitions for the i.MX25/31/35 Digital Audio Multiplexer */
+#define MXC_AUDMUX_V2_PTCR_TFSDIR       (1 << 31)
+#define MXC_AUDMUX_V2_PTCR_TFSEL(x)     (((x) & 0xf) << 27)
+#define MXC_AUDMUX_V2_PTCR_TCLKDIR      (1 << 26)
+#define MXC_AUDMUX_V2_PTCR_TCSEL(x)     (((x) & 0xf) << 22)
+#define MXC_AUDMUX_V2_PTCR_RFSDIR       (1 << 21)
+#define MXC_AUDMUX_V2_PTCR_RFSEL(x)     (((x) & 0xf) << 17)
+#define MXC_AUDMUX_V2_PTCR_RCLKDIR      (1 << 16)
+#define MXC_AUDMUX_V2_PTCR_RCSEL(x)     (((x) & 0xf) << 12)
+#define MXC_AUDMUX_V2_PTCR_SYN          (1 << 11)
+#define MXC_AUDMUX_V2_PDCR_RXDSEL(x)    (((x) & 0x7) << 13)
+#define MXC_AUDMUX_V2_PDCR_TXRXEN       (1 << 12)
+#define MXC_AUDMUX_V2_PDCR_MODE(x)      (((x) & 0x3) << 8)
+#define MXC_AUDMUX_V2_PDCR_INMMASK(x)   ((x) & 0xff)
+int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr);
+int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
+                unsigned int pdcr);
+#endif /* __MACH_AUDMUX_H */
diff --git a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h b/arch/arm/plat-mxc/include/mach/board-kzmarm11.h
new file mode 100644
index 000000000000..05ff2f31ef1f
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-kzmarm11.h
@@ -0,0 +1,39 @@
+/*
+ *  Copyright (C) 2009  Yoichi Yuasa <yuasa@linux-mips.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#ifndef __ARM_ARCH_BOARD_KZM_ARM11_H
+#define __ARM_ARCH_BOARD_KZM_ARM11_H
+/*
+ *  KZM-ARM11-01 Board Control Registers on FPGA
+ */
+#define KZM_ARM11_CTL1          (CS4_BASE_ADDR + 0x1000)
+#define KZM_ARM11_CTL2          (CS4_BASE_ADDR + 0x1001)
+#define KZM_ARM11_RSW1          (CS4_BASE_ADDR + 0x1002)
+#define KZM_ARM11_BACK_LIGHT    (CS4_BASE_ADDR + 0x1004)
+#define KZM_ARM11_FPGA_REV      (CS4_BASE_ADDR + 0x1008)
+#define KZM_ARM11_7SEG_LED      (CS4_BASE_ADDR + 0x1010)
+#define KZM_ARM11_LEDS          (CS4_BASE_ADDR + 0x1020)
+#define KZM_ARM11_DIPSW2        (CS4_BASE_ADDR + 0x1003)
+/*
+ * External UART for touch panel on FPGA
+ */
+#define KZM_ARM11_16550         (CS4_BASE_ADDR + 0x1050)
+#endif /* __ARM_ARCH_BOARD_KZM_ARM11_H */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lite.h b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
index 8e64325d6905..0184b638c268 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31lite.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
@@ -1,15 +1,42 @@
 /*
 * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
+ *
+ * Based on code for mobots boards,
+ *   Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
 */
+#ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__
+#define __ASM_ARCH_MXC_BOARD_MX31LITE_H__
+#ifndef __ASSEMBLY__
+enum mx31lilly_boards {
+        MX31LITE_NOBOARD        = 0,
+        MX31LITE_DB             = 1,
+};
 /*
- * This program is free software; you can redistribute it and/or modify
+ * This CPU module needs a baseboard to work. After basic initializing
- * it under the terms of the GNU General Public License version 2 as
+ * its own devices, it calls baseboard's init function.
- * published by the Free Software Foundation.
 */
-#ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__
+extern void mx31lite_db_init(void);
-#define __ASM_ARCH_MXC_BOARD_MX31LITE_H__
-#endif /* __ASM_ARCH_MXC_BOARD_MX31LITE_H__ */
+#endif
+#endif /* __ASM_ARCH_MXC_BOARD_MX31LITE_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
index b3876cc238ca..07be8ad7ec37 100644
--- a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
+++ b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
@@ -58,6 +58,14 @@ imx_dma_setup_single(int channel, dma_addr_t dma_address,
                unsigned int dma_length, unsigned int dev_addr,
                unsigned int dmamode);
+/*
+ * Use this flag as the dma_length argument to imx_dma_setup_sg()
+ * to create an endless running dma loop. The end of the scatterlist
+ * must be linked to the beginning for this to work.
+ */
+#define IMX_DMA_LENGTH_LOOP     ((unsigned int)-1)
 int
 imx_dma_setup_sg(int channel, struct scatterlist *sg,
                unsigned int sgcount, unsigned int dma_length,
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index 446f86763816..eaabd4e96925 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -524,10 +524,18 @@ enum iomux_pins {
 #define MX31_PIN_RTS1__RTS1             IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_TXD1__TXD1             IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_RXD1__RXD1             IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_DCD_DCE1__DCD_DCE1     IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_RI_DCE1__RI_DCE1       IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_DSR_DCE1__DSR_DCE1     IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_DTR_DCE1__DTR_DCE1     IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_CTS2__CTS2             IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_RTS2__RTS2             IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_TXD2__TXD2             IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_RXD2__RXD2             IOMUX_MODE(MX31_PIN_RXD2, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_DCD_DTE1__DCD_DTE2     IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_RI_DTE1__RI_DTE2       IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_DSR_DTE1__DSR_DTE2     IOMUX_MODE(MX31_PIN_DSR_DTE1, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_DTR_DTE1__DTR_DTE2     IOMUX_MODE(MX31_PIN_DTR_DTE1, IOMUX_OCONFIG_ALT3 | IOMUX_ICONFIG_NONE)
 #define MX31_PIN_PC_RST__CTS5           IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT2)
 #define MX31_PIN_PC_VS2__RTS5           IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT2)
 #define MX31_PIN_PC_BVD2__TXD5          IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT2)
@@ -623,6 +631,8 @@ enum iomux_pins {
 #define MX31_PIN_GPIO3_0__GPIO3_0       IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO)
 #define MX31_PIN_GPIO3_1__GPIO3_1       IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO)
 #define MX31_PIN_TXD2__GPIO1_28         IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_CSI_D4__GPIO3_4        IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_CSI_D5__GPIO3_5        IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO)
 #define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0    IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1    IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2    IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC)
@@ -642,12 +652,22 @@ enum iomux_pins {
 #define MX31_PIN_CSPI1_SS2__USBH1_RCV          IOMUX_MODE(MX31_PIN_CSPI1_SS2,  IOMUX_CONFIG_ALT1)
 #define MX31_PIN_CSPI1_SCLK__USBH1_OEB         IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1)
 #define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS       IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_SFS6__USBH1_SUSPEND    IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_NFRE_B__GPIO1_11       IOMUX_MODE(MX31_PIN_NFRE_B, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_NFALE__GPIO1_12        IOMUX_MODE(MX31_PIN_NFALE, IOMUX_CONFIG_GPIO)
 #define MX31_PIN_USBH2_DATA0__USBH2_DATA0      IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_USBH2_DATA1__USBH2_DATA1      IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_STXD3__USBH2_DATA2     IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SRXD3__USBH2_DATA3     IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SCK3__USBH2_DATA4      IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SFS3__USBH2_DATA5      IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_STXD6__USBH2_DATA6     IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SRXD6__USBH2_DATA7     IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_USBH2_CLK__USBH2_CLK          IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_USBH2_DIR__USBH2_DIR          IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_USBH2_NXT__USBH2_NXT          IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_USBH2_STP__USBH2_STP          IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SCK6__GPIO1_25         IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO)
 #define MX31_PIN_USB_OC__GPIO1_30       IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO)
 #define MX31_PIN_I2C_DAT__I2C1_SDA      IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_I2C_CLK__I2C1_SCL      IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC)
@@ -693,7 +713,19 @@ enum iomux_pins {
 #define MX31_PIN_DCD_DCE1__GPIO2_11     IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO)
 #define MX31_PIN_STXD5__GPIO1_21       IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO)
 #define MX31_PIN_SRXD5__GPIO1_22       IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_GPIO1_3__GPIO1_3       IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_CSPI2_SS1__CSPI3_SS1   IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_RTS1__GPIO2_6          IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_CTS1__GPIO2_7          IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_LCS0__GPIO3_23         IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_STXD4__STXD4           IOMUX_MODE(MX31_PIN_STXD4, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SRXD4__SRXD4           IOMUX_MODE(MX31_PIN_SRXD4, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SCK4__SCK4             IOMUX_MODE(MX31_PIN_SCK4, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SFS4__SFS4             IOMUX_MODE(MX31_PIN_SFS4, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_STXD5__STXD5           IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SRXD5__SRXD5           IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SCK5__SCK5             IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SFS5__SFS5             IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC)
 /*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0
 * cspi1_ss1*/
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index a0fa40265468..1deda0184892 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -88,9 +88,7 @@ struct pad_desc {
 #define PAD_CTL_SRE_FAST                (1 << 0)
 /*
- * setups a single pad:
+ * setups a single pad in the iomuxer
- *      - reserves the pad so that it is not claimed by another driver
- *      - setups the iomux according to the configuration
 */
 int mxc_iomux_v3_setup_pad(struct pad_desc *pad);
@@ -101,19 +99,6 @@ int mxc_iomux_v3_setup_pad(struct pad_desc *pad);
 int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count);
 /*
- * releases a single pad:
- *      - make it available for a future use by another driver
- *      - DOES NOT reconfigure the IOMUX in its reset state
- */
-void mxc_iomux_v3_release_pad(struct pad_desc *pad);
-/*
- * releases multiple pads
- * convenvient way to call the above function with tables
- */
-void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count);
-/*
 * Initialise the iomux controller
 */
 void mxc_iomux_v3_init(void __iomem *iomux_v3_base);
diff --git a/arch/arm/plat-mxc/include/mach/iomux.h b/arch/arm/plat-mxc/include/mach/iomux.h
index 6d49f8ae3259..011cfcd8b820 100644
--- a/arch/arm/plat-mxc/include/mach/iomux.h
+++ b/arch/arm/plat-mxc/include/mach/iomux.h
@@ -123,6 +123,7 @@
 #define IRQ_GPIOC(x)  (IRQ_GPIOB(32) + x)
 #define IRQ_GPIOD(x)  (IRQ_GPIOC(32) + x)
 #define IRQ_GPIOE(x)  (IRQ_GPIOD(32) + x)
+#define IRQ_GPIOF(x)  (IRQ_GPIOE(32) + x)
 extern void mxc_gpio_mode(int gpio_mode);
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h
index 21112c695ec5..bb297d8765a7 100644
--- a/arch/arm/plat-mxc/include/mach/mx21.h
+++ b/arch/arm/plat-mxc/include/mach/mx21.h
@@ -25,46 +25,191 @@
 #ifndef __ASM_ARCH_MXC_MX21_H__
 #define __ASM_ARCH_MXC_MX21_H__
+#define MX21_AIPI_BASE_ADDR             0x10000000
+#define MX21_AIPI_BASE_ADDR_VIRT        0xf4000000
+#define MX21_AIPI_SIZE                  SZ_1M
+#define MX21_DMA_BASE_ADDR                      (MX21_AIPI_BASE_ADDR + 0x01000)
+#define MX21_WDOG_BASE_ADDR                     (MX21_AIPI_BASE_ADDR + 0x02000)
+#define MX21_GPT1_BASE_ADDR                     (MX21_AIPI_BASE_ADDR + 0x03000)
+#define MX21_GPT2_BASE_ADDR                     (MX21_AIPI_BASE_ADDR + 0x04000)
+#define MX21_GPT3_BASE_ADDR                     (MX21_AIPI_BASE_ADDR + 0x05000)
+#define MX21_PWM_BASE_ADDR                      (MX21_AIPI_BASE_ADDR + 0x06000)
+#define MX21_RTC_BASE_ADDR                      (MX21_AIPI_BASE_ADDR + 0x07000)
+#define MX21_KPP_BASE_ADDR                      (MX21_AIPI_BASE_ADDR + 0x08000)
+#define MX21_OWIRE_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x09000)
+#define MX21_UART1_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x0a000)
+#define MX21_UART2_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x0b000)
+#define MX21_UART3_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x0c000)
+#define MX21_UART4_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x0d000)
+#define MX21_CSPI1_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x0e000)
+#define MX21_CSPI2_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x0f000)
+#define MX21_SSI1_BASE_ADDR                     (MX21_AIPI_BASE_ADDR + 0x10000)
+#define MX21_SSI2_BASE_ADDR                     (MX21_AIPI_BASE_ADDR + 0x11000)
+#define MX21_I2C_BASE_ADDR                      (MX21_AIPI_BASE_ADDR + 0x12000)
+#define MX21_SDHC1_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x13000)
+#define MX21_SDHC2_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x14000)
+#define MX21_GPIO_BASE_ADDR                     (MX21_AIPI_BASE_ADDR + 0x15000)
+#define MX21_AUDMUX_BASE_ADDR                   (MX21_AIPI_BASE_ADDR + 0x16000)
+#define MX21_CSPI3_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x17000)
+#define MX21_LCDC_BASE_ADDR                     (MX21_AIPI_BASE_ADDR + 0x21000)
+#define MX21_SLCDC_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x22000)
+#define MX21_USBOTG_BASE_ADDR                   (MX21_AIPI_BASE_ADDR + 0x24000)
+#define MX21_EMMA_PP_BASE_ADDR                  (MX21_AIPI_BASE_ADDR + 0x26000)
+#define MX21_EMMA_PRP_BASE_ADDR                 (MX21_AIPI_BASE_ADDR + 0x26400)
+#define MX21_CCM_BASE_ADDR                      (MX21_AIPI_BASE_ADDR + 0x27000)
+#define MX21_SYSCTRL_BASE_ADDR                  (MX21_AIPI_BASE_ADDR + 0x27800)
+#define MX21_JAM_BASE_ADDR                      (MX21_AIPI_BASE_ADDR + 0x3e000)
+#define MX21_MAX_BASE_ADDR                      (MX21_AIPI_BASE_ADDR + 0x3f000)
+#define MX21_AVIC_BASE_ADDR             0x10040000
+#define MX21_SAHB1_BASE_ADDR            0x80000000
+#define MX21_SAHB1_BASE_ADDR_VIRT       0xf4100000
+#define MX21_SAHB1_SIZE                 SZ_1M
+#define MX21_CSI_BASE_ADDR                      (MX2x_SAHB1_BASE_ADDR + 0x0000)
 /* Memory regions and CS */
-#define SDRAM_BASE_ADDR         0xC0000000
+#define MX21_SDRAM_BASE_ADDR            0xc0000000
-#define CSD1_BASE_ADDR          0xC4000000
+#define MX21_CSD1_BASE_ADDR             0xc4000000
-#define CS0_BASE_ADDR           0xC8000000
+#define MX21_CS0_BASE_ADDR              0xc8000000
-#define CS1_BASE_ADDR           0xCC000000
+#define MX21_CS1_BASE_ADDR              0xcc000000
-#define CS2_BASE_ADDR           0xD0000000
+#define MX21_CS2_BASE_ADDR              0xd0000000
-#define CS3_BASE_ADDR           0xD1000000
+#define MX21_CS3_BASE_ADDR              0xd1000000
-#define CS4_BASE_ADDR           0xD2000000
+#define MX21_CS4_BASE_ADDR              0xd2000000
-#define CS5_BASE_ADDR           0xDD000000
+#define MX21_PCMCIA_MEM_BASE_ADDR       0xd4000000
-#define PCMCIA_MEM_BASE_ADDR    0xD4000000
+#define MX21_CS5_BASE_ADDR              0xdd000000
 /* NAND, SDRAM, WEIM etc controllers */
-#define X_MEMC_BASE_ADDR        0xDF000000
+#define MX21_X_MEMC_BASE_ADDR           0xdf000000
-#define X_MEMC_BASE_ADDR_VIRT   0xF4200000
+#define MX21_X_MEMC_BASE_ADDR_VIRT      0xf4200000
-#define X_MEMC_SIZE             SZ_256K
+#define MX21_X_MEMC_SIZE                SZ_256K
-#define SDRAMC_BASE_ADDR        (X_MEMC_BASE_ADDR + 0x0000)
+#define MX21_SDRAMC_BASE_ADDR           (MX21_X_MEMC_BASE_ADDR + 0x0000)
-#define EIM_BASE_ADDR           (X_MEMC_BASE_ADDR + 0x1000)
+#define MX21_EIM_BASE_ADDR              (MX21_X_MEMC_BASE_ADDR + 0x1000)
-#define PCMCIA_CTL_BASE_ADDR    (X_MEMC_BASE_ADDR + 0x2000)
+#define MX21_PCMCIA_CTL_BASE_ADDR       (MX21_X_MEMC_BASE_ADDR + 0x2000)
-#define NFC_BASE_ADDR           (X_MEMC_BASE_ADDR + 0x3000)
+#define MX21_NFC_BASE_ADDR              (MX21_X_MEMC_BASE_ADDR + 0x3000)
-#define IRAM_BASE_ADDR          0xFFFFE800      /* internal ram */
+#define MX21_IRAM_BASE_ADDR             0xffffe800      /* internal ram */
 /* fixed interrupt numbers */
-#define MXC_INT_USBCTRL         58
+#define MX21_INT_CSPI3          6
-#define MXC_INT_USBCTRL         58
+#define MX21_INT_GPIO           8
-#define MXC_INT_USBMNP          57
+#define MX21_INT_FIRI           9
-#define MXC_INT_USBFUNC         56
+#define MX21_INT_SDHC2          10
-#define MXC_INT_USBHOST         55
+#define MX21_INT_SDHC1          11
-#define MXC_INT_USBDMA          54
+#define MX21_INT_I2C            12
-#define MXC_INT_USBWKUP         53
+#define MX21_INT_SSI2           13
-#define MXC_INT_EMMADEC         50
+#define MX21_INT_SSI1           14
-#define MXC_INT_EMMAENC         49
+#define MX21_INT_CSPI2          15
-#define MXC_INT_BMI             30
+#define MX21_INT_CSPI1          16
-#define MXC_INT_FIRI            9
+#define MX21_INT_UART4          17
+#define MX21_INT_UART3          18
+#define MX21_INT_UART2          19
+#define MX21_INT_UART1          20
+#define MX21_INT_KPP            21
+#define MX21_INT_RTC            22
+#define MX21_INT_PWM            23
+#define MX21_INT_GPT3           24
+#define MX21_INT_GPT2           25
+#define MX21_INT_GPT1           26
+#define MX21_INT_WDOG           27
+#define MX21_INT_PCMCIA         28
+#define MX21_INT_NANDFC         29
+#define MX21_INT_BMI            30
+#define MX21_INT_CSI            31
+#define MX21_INT_DMACH0         32
+#define MX21_INT_DMACH1         33
+#define MX21_INT_DMACH2         34
+#define MX21_INT_DMACH3         35
+#define MX21_INT_DMACH4         36
+#define MX21_INT_DMACH5         37
+#define MX21_INT_DMACH6         38
+#define MX21_INT_DMACH7         39
+#define MX21_INT_DMACH8         40
+#define MX21_INT_DMACH9         41
+#define MX21_INT_DMACH10        42
+#define MX21_INT_DMACH11        43
+#define MX21_INT_DMACH12        44
+#define MX21_INT_DMACH13        45
+#define MX21_INT_DMACH14        46
+#define MX21_INT_DMACH15        47
+#define MX21_INT_EMMAENC        49
+#define MX21_INT_EMMADEC        50
+#define MX21_INT_EMMAPRP        51
+#define MX21_INT_EMMAPP         52
+#define MX21_INT_USBWKUP        53
+#define MX21_INT_USBDMA         54
+#define MX21_INT_USBHOST        55
+#define MX21_INT_USBFUNC        56
+#define MX21_INT_USBMNP         57
+#define MX21_INT_USBCTRL        58
+#define MX21_INT_SLCDC          60
+#define MX21_INT_LCDC           61
 /* fixed DMA request numbers */
-#define DMA_REQ_BMI_RX          29
+#define MX21_DMA_REQ_CSPI3_RX   1
-#define DMA_REQ_BMI_TX          28
+#define MX21_DMA_REQ_CSPI3_TX   2
-#define DMA_REQ_FIRI_RX         4
+#define MX21_DMA_REQ_EXT        3
+#define MX21_DMA_REQ_FIRI_RX    4
+#define MX21_DMA_REQ_SDHC2      6
+#define MX21_DMA_REQ_SDHC1      7
+#define MX21_DMA_REQ_SSI2_RX0   8
+#define MX21_DMA_REQ_SSI2_TX0   9
+#define MX21_DMA_REQ_SSI2_RX1   10
+#define MX21_DMA_REQ_SSI2_TX1   11
+#define MX21_DMA_REQ_SSI1_RX0   12
+#define MX21_DMA_REQ_SSI1_TX0   13
+#define MX21_DMA_REQ_SSI1_RX1   14
+#define MX21_DMA_REQ_SSI1_TX1   15
+#define MX21_DMA_REQ_CSPI2_RX   16
+#define MX21_DMA_REQ_CSPI2_TX   17
+#define MX21_DMA_REQ_CSPI1_RX   18
+#define MX21_DMA_REQ_CSPI1_TX   19
+#define MX21_DMA_REQ_UART4_RX   20
+#define MX21_DMA_REQ_UART4_TX   21
+#define MX21_DMA_REQ_UART3_RX   22
+#define MX21_DMA_REQ_UART3_TX   23
+#define MX21_DMA_REQ_UART2_RX   24
+#define MX21_DMA_REQ_UART2_TX   25
+#define MX21_DMA_REQ_UART1_RX   26
+#define MX21_DMA_REQ_UART1_TX   27
+#define MX21_DMA_REQ_BMI_TX     28
+#define MX21_DMA_REQ_BMI_RX     29
+#define MX21_DMA_REQ_CSI_STAT   30
+#define MX21_DMA_REQ_CSI_RX     31
+/* these should go away */
+#define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR
+#define CSD1_BASE_ADDR MX21_CSD1_BASE_ADDR
+#define CS0_BASE_ADDR MX21_CS0_BASE_ADDR
+#define CS1_BASE_ADDR MX21_CS1_BASE_ADDR
+#define CS2_BASE_ADDR MX21_CS2_BASE_ADDR
+#define CS3_BASE_ADDR MX21_CS3_BASE_ADDR
+#define CS4_BASE_ADDR MX21_CS4_BASE_ADDR
+#define PCMCIA_MEM_BASE_ADDR MX21_PCMCIA_MEM_BASE_ADDR
+#define CS5_BASE_ADDR MX21_CS5_BASE_ADDR
+#define X_MEMC_BASE_ADDR MX21_X_MEMC_BASE_ADDR
+#define X_MEMC_BASE_ADDR_VIRT MX21_X_MEMC_BASE_ADDR_VIRT
+#define X_MEMC_SIZE MX21_X_MEMC_SIZE
+#define SDRAMC_BASE_ADDR MX21_SDRAMC_BASE_ADDR
+#define EIM_BASE_ADDR MX21_EIM_BASE_ADDR
+#define PCMCIA_CTL_BASE_ADDR MX21_PCMCIA_CTL_BASE_ADDR
+#define NFC_BASE_ADDR MX21_NFC_BASE_ADDR
+#define IRAM_BASE_ADDR MX21_IRAM_BASE_ADDR
+#define MXC_INT_FIRI MX21_INT_FIRI
+#define MXC_INT_BMI MX21_INT_BMI
+#define MXC_INT_EMMAENC MX21_INT_EMMAENC
+#define MXC_INT_EMMADEC MX21_INT_EMMADEC
+#define MXC_INT_USBWKUP MX21_INT_USBWKUP
+#define MXC_INT_USBDMA MX21_INT_USBDMA
+#define MXC_INT_USBHOST MX21_INT_USBHOST
+#define MXC_INT_USBFUNC MX21_INT_USBFUNC
+#define MXC_INT_USBMNP MX21_INT_USBMNP
+#define MXC_INT_USBCTRL MX21_INT_USBCTRL
+#define MXC_INT_USBCTRL MX21_INT_USBCTRL
+#define DMA_REQ_FIRI_RX MX21_DMA_REQ_FIRI_RX
+#define DMA_REQ_BMI_TX MX21_DMA_REQ_BMI_TX
+#define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX
 #endif /* __ASM_ARCH_MXC_MX21_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index ec64bd9a8ab1..91e738144804 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -1,14 +1,14 @@
 #ifndef __MACH_MX25_H__
 #define __MACH_MX25_H__
-#define MX25_AIPS1_BASE_ADDR            0x43F00000
+#define MX25_AIPS1_BASE_ADDR            0x43f00000
-#define MX25_AIPS1_BASE_ADDR_VIRT       0xFC000000
+#define MX25_AIPS1_BASE_ADDR_VIRT       0xfc000000
 #define MX25_AIPS1_SIZE                 SZ_1M
-#define MX25_AIPS2_BASE_ADDR            0x53F00000
+#define MX25_AIPS2_BASE_ADDR            0x53f00000
-#define MX25_AIPS2_BASE_ADDR_VIRT       0xFC200000
+#define MX25_AIPS2_BASE_ADDR_VIRT       0xfc200000
 #define MX25_AIPS2_SIZE                 SZ_1M
 #define MX25_AVIC_BASE_ADDR             0x68000000
-#define MX25_AVIC_BASE_ADDR_VIRT        0xFC400000
+#define MX25_AVIC_BASE_ADDR_VIRT        0xfc400000
 #define MX25_AVIC_SIZE                  SZ_1M
 #define MX25_IOMUXC_BASE_ADDR           (MX25_AIPS1_BASE_ADDR + 0xac000)
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index dc3ad9aa952a..e2ae19f51710 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -24,87 +24,198 @@
 #ifndef __ASM_ARCH_MXC_MX27_H__
 #define __ASM_ARCH_MXC_MX27_H__
-/* IRAM */
+#define MX27_AIPI_BASE_ADDR             0x10000000
-#define IRAM_BASE_ADDR          0xFFFF4C00      /* internal ram */
+#define MX27_AIPI_BASE_ADDR_VIRT        0xf4000000
+#define MX27_AIPI_SIZE                  SZ_1M
-#define MSHC_BASE_ADDR          (AIPI_BASE_ADDR + 0x18000)
+#define MX27_DMA_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x01000)
-#define GPT5_BASE_ADDR          (AIPI_BASE_ADDR + 0x19000)
+#define MX27_WDOG_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x02000)
-#define GPT4_BASE_ADDR          (AIPI_BASE_ADDR + 0x1A000)
+#define MX27_GPT1_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x03000)
-#define UART5_BASE_ADDR         (AIPI_BASE_ADDR + 0x1B000)
+#define MX27_GPT2_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x04000)
-#define UART6_BASE_ADDR         (AIPI_BASE_ADDR + 0x1C000)
+#define MX27_GPT3_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x05000)
-#define I2C2_BASE_ADDR          (AIPI_BASE_ADDR + 0x1D000)
+#define MX27_PWM_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x06000)
-#define SDHC3_BASE_ADDR         (AIPI_BASE_ADDR + 0x1E000)
+#define MX27_RTC_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x07000)
-#define GPT6_BASE_ADDR          (AIPI_BASE_ADDR + 0x1F000)
+#define MX27_KPP_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x08000)
-#define VPU_BASE_ADDR           (AIPI_BASE_ADDR + 0x23000)
+#define MX27_OWIRE_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x09000)
-#define OTG_BASE_ADDR           USBOTG_BASE_ADDR
+#define MX27_UART1_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x0a000)
-#define SAHARA_BASE_ADDR        (AIPI_BASE_ADDR + 0x25000)
+#define MX27_UART2_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x0b000)
-#define IIM_BASE_ADDR           (AIPI_BASE_ADDR + 0x28000)
+#define MX27_UART3_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x0c000)
-#define RTIC_BASE_ADDR          (AIPI_BASE_ADDR + 0x2A000)
+#define MX27_UART4_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x0d000)
-#define FEC_BASE_ADDR           (AIPI_BASE_ADDR + 0x2B000)
+#define MX27_CSPI1_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x0e000)
-#define SCC_BASE_ADDR           (AIPI_BASE_ADDR + 0x2C000)
+#define MX27_CSPI2_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x0f000)
-#define ETB_BASE_ADDR           (AIPI_BASE_ADDR + 0x3B000)
+#define MX27_SSI1_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x10000)
-#define ETB_RAM_BASE_ADDR       (AIPI_BASE_ADDR + 0x3C000)
+#define MX27_SSI2_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x11000)
+#define MX27_I2C_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x12000)
+#define MX27_SDHC1_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x13000)
+#define MX27_SDHC2_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x14000)
+#define MX27_GPIO_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x15000)
+#define MX27_AUDMUX_BASE_ADDR                   (MX27_AIPI_BASE_ADDR + 0x16000)
+#define MX27_CSPI3_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x17000)
+#define MX27_MSHC_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x18000)
+#define MX27_GPT5_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x19000)
+#define MX27_GPT4_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x1a000)
+#define MX27_UART5_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x1b000)
+#define MX27_UART6_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x1c000)
+#define MX27_I2C2_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x1d000)
+#define MX27_SDHC3_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x1e000)
+#define MX27_GPT6_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x1f000)
+#define MX27_LCDC_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x21000)
+#define MX27_SLCDC_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x22000)
+#define MX27_VPU_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x23000)
+#define MX27_USBOTG_BASE_ADDR                   (MX27_AIPI_BASE_ADDR + 0x24000)
+#define MX27_OTG_BASE_ADDR                      MX27_USBOTG_BASE_ADDR
+#define MX27_SAHARA_BASE_ADDR                   (MX27_AIPI_BASE_ADDR + 0x25000)
+#define MX27_EMMA_PP_BASE_ADDR                  (MX27_AIPI_BASE_ADDR + 0x26000)
+#define MX27_EMMA_PRP_BASE_ADDR                 (MX27_AIPI_BASE_ADDR + 0x26400)
+#define MX27_CCM_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x27000)
+#define MX27_SYSCTRL_BASE_ADDR                  (MX27_AIPI_BASE_ADDR + 0x27800)
+#define MX27_IIM_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x28000)
+#define MX27_RTIC_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x2a000)
+#define MX27_FEC_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x2b000)
+#define MX27_SCC_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x2c000)
+#define MX27_ETB_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x3b000)
+#define MX27_ETB_RAM_BASE_ADDR                  (MX27_AIPI_BASE_ADDR + 0x3c000)
+#define MX27_JAM_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x3e000)
+#define MX27_MAX_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x3f000)
+#define MX27_AVIC_BASE_ADDR             0x10040000
 /* ROM patch */
-#define ROMP_BASE_ADDR          0x10041000
+#define MX27_ROMP_BASE_ADDR             0x10041000
-#define ATA_BASE_ADDR           (SAHB1_BASE_ADDR + 0x1000)
+#define MX27_SAHB1_BASE_ADDR            0x80000000
+#define MX27_SAHB1_BASE_ADDR_VIRT       0xf4100000
+#define MX27_SAHB1_SIZE                 SZ_1M
+#define MX27_CSI_BASE_ADDR                      (MX27_SAHB1_BASE_ADDR + 0x0000)
+#define MX27_ATA_BASE_ADDR                      (MX27_SAHB1_BASE_ADDR + 0x1000)
 /* Memory regions and CS */
-#define SDRAM_BASE_ADDR         0xA0000000
+#define MX27_SDRAM_BASE_ADDR            0xa0000000
-#define CSD1_BASE_ADDR          0xB0000000
+#define MX27_CSD1_BASE_ADDR             0xb0000000
-#define CS0_BASE_ADDR           0xC0000000
+#define MX27_CS0_BASE_ADDR              0xc0000000
-#define CS1_BASE_ADDR           0xC8000000
+#define MX27_CS1_BASE_ADDR              0xc8000000
-#define CS2_BASE_ADDR           0xD0000000
+#define MX27_CS2_BASE_ADDR              0xd0000000
-#define CS3_BASE_ADDR           0xD2000000
+#define MX27_CS3_BASE_ADDR              0xd2000000
-#define CS4_BASE_ADDR           0xD4000000
+#define MX27_CS4_BASE_ADDR              0xd4000000
-#define CS5_BASE_ADDR           0xD6000000
+#define MX27_CS5_BASE_ADDR              0xd6000000
-#define PCMCIA_MEM_BASE_ADDR    0xDC000000
 /* NAND, SDRAM, WEIM, M3IF, EMI controllers */
-#define X_MEMC_BASE_ADDR        0xD8000000
+#define MX27_X_MEMC_BASE_ADDR           0xd8000000
-#define X_MEMC_BASE_ADDR_VIRT   0xF4200000
+#define MX27_X_MEMC_BASE_ADDR_VIRT      0xf4200000
-#define X_MEMC_SIZE             SZ_1M
+#define MX27_X_MEMC_SIZE                SZ_1M
+#define MX27_NFC_BASE_ADDR                      (MX27_X_MEMC_BASE_ADDR)
+#define MX27_SDRAMC_BASE_ADDR                   (MX27_X_MEMC_BASE_ADDR + 0x1000)
+#define MX27_WEIM_BASE_ADDR                     (MX27_X_MEMC_BASE_ADDR + 0x2000)
+#define MX27_M3IF_BASE_ADDR                     (MX27_X_MEMC_BASE_ADDR + 0x3000)
+#define MX27_PCMCIA_CTL_BASE_ADDR               (MX27_X_MEMC_BASE_ADDR + 0x4000)
-#define NFC_BASE_ADDR           (X_MEMC_BASE_ADDR)
+#define MX27_PCMCIA_MEM_BASE_ADDR       0xdc000000
-#define SDRAMC_BASE_ADDR        (X_MEMC_BASE_ADDR + 0x1000)
-#define WEIM_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x2000)
+/* IRAM */
-#define M3IF_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x3000)
+#define MX27_IRAM_BASE_ADDR             0xffff4c00      /* internal ram */
-#define PCMCIA_CTL_BASE_ADDR    (X_MEMC_BASE_ADDR + 0x4000)
 /* fixed interrupt numbers */
-#define MXC_INT_CCM             63
+#define MX27_INT_I2C2           1
-#define MXC_INT_IIM             62
+#define MX27_INT_GPT6           2
-#define MXC_INT_SAHARA          59
+#define MX27_INT_GPT5           3
-#define MXC_INT_SCC_SCM         58
+#define MX27_INT_GPT4           4
-#define MXC_INT_SCC_SMN         57
+#define MX27_INT_RTIC           5
-#define MXC_INT_USB3            56
+#define MX27_INT_CSPI3          6
-#define MXC_INT_USB2            55
+#define MX27_INT_SDHC           7
-#define MXC_INT_USB1            54
+#define MX27_INT_GPIO           8
-#define MXC_INT_VPU             53
+#define MX27_INT_SDHC3          9
-#define MXC_INT_FEC             50
+#define MX27_INT_SDHC2          10
-#define MXC_INT_UART5           49
+#define MX27_INT_SDHC1          11
-#define MXC_INT_UART6           48
+#define MX27_INT_I2C            12
-#define MXC_INT_ATA             30
+#define MX27_INT_SSI2           13
-#define MXC_INT_SDHC3           9
+#define MX27_INT_SSI1           14
-#define MXC_INT_SDHC            7
+#define MX27_INT_CSPI2          15
-#define MXC_INT_RTIC            5
+#define MX27_INT_CSPI1          16
-#define MXC_INT_GPT4            4
+#define MX27_INT_UART4          17
-#define MXC_INT_GPT5            3
+#define MX27_INT_UART3          18
-#define MXC_INT_GPT6            2
+#define MX27_INT_UART2          19
-#define MXC_INT_I2C2            1
+#define MX27_INT_UART1          20
+#define MX27_INT_KPP            21
+#define MX27_INT_RTC            22
+#define MX27_INT_PWM            23
+#define MX27_INT_GPT3           24
+#define MX27_INT_GPT2           25
+#define MX27_INT_GPT1           26
+#define MX27_INT_WDOG           27
+#define MX27_INT_PCMCIA         28
+#define MX27_INT_NANDFC         29
+#define MX27_INT_ATA            30
+#define MX27_INT_CSI            31
+#define MX27_INT_DMACH0         32
+#define MX27_INT_DMACH1         33
+#define MX27_INT_DMACH2         34
+#define MX27_INT_DMACH3         35
+#define MX27_INT_DMACH4         36
+#define MX27_INT_DMACH5         37
+#define MX27_INT_DMACH6         38
+#define MX27_INT_DMACH7         39
+#define MX27_INT_DMACH8         40
+#define MX27_INT_DMACH9         41
+#define MX27_INT_DMACH10        42
+#define MX27_INT_DMACH11        43
+#define MX27_INT_DMACH12        44
+#define MX27_INT_DMACH13        45
+#define MX27_INT_DMACH14        46
+#define MX27_INT_DMACH15        47
+#define MX27_INT_UART6          48
+#define MX27_INT_UART5          49
+#define MX27_INT_FEC            50
+#define MX27_INT_EMMAPRP        51
+#define MX27_INT_EMMAPP         52
+#define MX27_INT_VPU            53
+#define MX27_INT_USB1           54
+#define MX27_INT_USB2           55
+#define MX27_INT_USB3           56
+#define MX27_INT_SCC_SMN        57
+#define MX27_INT_SCC_SCM        58
+#define MX27_INT_SAHARA         59
+#define MX27_INT_SLCDC          60
+#define MX27_INT_LCDC           61
+#define MX27_INT_IIM            62
+#define MX27_INT_CCM            63
 /* fixed DMA request numbers */
-#define DMA_REQ_NFC             37
+#define MX27_DMA_REQ_CSPI3_RX   1
-#define DMA_REQ_SDHC3           36
+#define MX27_DMA_REQ_CSPI3_TX   2
-#define DMA_REQ_UART6_RX        35
+#define MX27_DMA_REQ_EXT        3
-#define DMA_REQ_UART6_TX        34
+#define MX27_DMA_REQ_MSHC       4
-#define DMA_REQ_UART5_RX        33
+#define MX27_DMA_REQ_SDHC2      6
-#define DMA_REQ_UART5_TX        32
+#define MX27_DMA_REQ_SDHC1      7
-#define DMA_REQ_ATA_RCV         29
+#define MX27_DMA_REQ_SSI2_RX0   8
-#define DMA_REQ_ATA_TX          28
+#define MX27_DMA_REQ_SSI2_TX0   9
-#define DMA_REQ_MSHC            4
+#define MX27_DMA_REQ_SSI2_RX1   10
+#define MX27_DMA_REQ_SSI2_TX1   11
+#define MX27_DMA_REQ_SSI1_RX0   12
+#define MX27_DMA_REQ_SSI1_TX0   13
+#define MX27_DMA_REQ_SSI1_RX1   14
+#define MX27_DMA_REQ_SSI1_TX1   15
+#define MX27_DMA_REQ_CSPI2_RX   16
+#define MX27_DMA_REQ_CSPI2_TX   17
+#define MX27_DMA_REQ_CSPI1_RX   18
+#define MX27_DMA_REQ_CSPI1_TX   19
+#define MX27_DMA_REQ_UART4_RX   20
+#define MX27_DMA_REQ_UART4_TX   21
+#define MX27_DMA_REQ_UART3_RX   22
+#define MX27_DMA_REQ_UART3_TX   23
+#define MX27_DMA_REQ_UART2_RX   24
+#define MX27_DMA_REQ_UART2_TX   25
+#define MX27_DMA_REQ_UART1_RX   26
+#define MX27_DMA_REQ_UART1_TX   27
+#define MX27_DMA_REQ_ATA_TX     28
+#define MX27_DMA_REQ_ATA_RCV    29
+#define MX27_DMA_REQ_CSI_STAT   30
+#define MX27_DMA_REQ_CSI_RX     31
+#define MX27_DMA_REQ_UART5_TX   32
+#define MX27_DMA_REQ_UART5_RX   33
+#define MX27_DMA_REQ_UART6_TX   34
+#define MX27_DMA_REQ_UART6_RX   35
+#define MX27_DMA_REQ_SDHC3      36
+#define MX27_DMA_REQ_NFC        37
 /* silicon revisions specific to i.MX27 */
 #define CHIP_REV_1_0            0x00
@@ -114,6 +225,72 @@
 extern int mx27_revision(void);
 #endif
-/* Mandatory defines used globally */
+/* these should go away */
+#define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR
+#define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR
+#define GPT4_BASE_ADDR MX27_GPT4_BASE_ADDR
+#define UART5_BASE_ADDR MX27_UART5_BASE_ADDR
+#define UART6_BASE_ADDR MX27_UART6_BASE_ADDR
+#define I2C2_BASE_ADDR MX27_I2C2_BASE_ADDR
+#define SDHC3_BASE_ADDR MX27_SDHC3_BASE_ADDR
+#define GPT6_BASE_ADDR MX27_GPT6_BASE_ADDR
+#define VPU_BASE_ADDR MX27_VPU_BASE_ADDR
+#define OTG_BASE_ADDR MX27_OTG_BASE_ADDR
+#define SAHARA_BASE_ADDR MX27_SAHARA_BASE_ADDR
+#define IIM_BASE_ADDR MX27_IIM_BASE_ADDR
+#define RTIC_BASE_ADDR MX27_RTIC_BASE_ADDR
+#define FEC_BASE_ADDR MX27_FEC_BASE_ADDR
+#define SCC_BASE_ADDR MX27_SCC_BASE_ADDR
+#define ETB_BASE_ADDR MX27_ETB_BASE_ADDR
+#define ETB_RAM_BASE_ADDR MX27_ETB_RAM_BASE_ADDR
+#define ROMP_BASE_ADDR MX27_ROMP_BASE_ADDR
+#define ATA_BASE_ADDR MX27_ATA_BASE_ADDR
+#define SDRAM_BASE_ADDR MX27_SDRAM_BASE_ADDR
+#define CSD1_BASE_ADDR MX27_CSD1_BASE_ADDR
+#define CS0_BASE_ADDR MX27_CS0_BASE_ADDR
+#define CS1_BASE_ADDR MX27_CS1_BASE_ADDR
+#define CS2_BASE_ADDR MX27_CS2_BASE_ADDR
+#define CS3_BASE_ADDR MX27_CS3_BASE_ADDR
+#define CS4_BASE_ADDR MX27_CS4_BASE_ADDR
+#define CS5_BASE_ADDR MX27_CS5_BASE_ADDR
+#define X_MEMC_BASE_ADDR MX27_X_MEMC_BASE_ADDR
+#define X_MEMC_BASE_ADDR_VIRT MX27_X_MEMC_BASE_ADDR_VIRT
+#define X_MEMC_SIZE MX27_X_MEMC_SIZE
+#define NFC_BASE_ADDR MX27_NFC_BASE_ADDR
+#define SDRAMC_BASE_ADDR MX27_SDRAMC_BASE_ADDR
+#define WEIM_BASE_ADDR MX27_WEIM_BASE_ADDR
+#define M3IF_BASE_ADDR MX27_M3IF_BASE_ADDR
+#define PCMCIA_CTL_BASE_ADDR MX27_PCMCIA_CTL_BASE_ADDR
+#define PCMCIA_MEM_BASE_ADDR MX27_PCMCIA_MEM_BASE_ADDR
+#define IRAM_BASE_ADDR MX27_IRAM_BASE_ADDR
+#define MXC_INT_I2C2 MX27_INT_I2C2
+#define MXC_INT_GPT6 MX27_INT_GPT6
+#define MXC_INT_GPT5 MX27_INT_GPT5
+#define MXC_INT_GPT4 MX27_INT_GPT4
+#define MXC_INT_RTIC MX27_INT_RTIC
+#define MXC_INT_SDHC MX27_INT_SDHC
+#define MXC_INT_SDHC3 MX27_INT_SDHC3
+#define MXC_INT_ATA MX27_INT_ATA
+#define MXC_INT_UART6 MX27_INT_UART6
+#define MXC_INT_UART5 MX27_INT_UART5
+#define MXC_INT_FEC MX27_INT_FEC
+#define MXC_INT_VPU MX27_INT_VPU
+#define MXC_INT_USB1 MX27_INT_USB1
+#define MXC_INT_USB2 MX27_INT_USB2
+#define MXC_INT_USB3 MX27_INT_USB3
+#define MXC_INT_SCC_SMN MX27_INT_SCC_SMN
+#define MXC_INT_SCC_SCM MX27_INT_SCC_SCM
+#define MXC_INT_SAHARA MX27_INT_SAHARA
+#define MXC_INT_IIM MX27_INT_IIM
+#define MXC_INT_CCM MX27_INT_CCM
+#define DMA_REQ_MSHC MX27_DMA_REQ_MSHC
+#define DMA_REQ_ATA_TX MX27_DMA_REQ_ATA_TX
+#define DMA_REQ_ATA_RCV MX27_DMA_REQ_ATA_RCV
+#define DMA_REQ_UART5_TX MX27_DMA_REQ_UART5_TX
+#define DMA_REQ_UART5_RX MX27_DMA_REQ_UART5_RX
+#define DMA_REQ_UART6_TX MX27_DMA_REQ_UART6_TX
+#define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX
+#define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3
+#define DMA_REQ_NFC MX27_DMA_REQ_NFC
 #endif /* __ASM_ARCH_MXC_MX27_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h
index db5d921e0fe6..f2eaf140ed02 100644
--- a/arch/arm/plat-mxc/include/mach/mx2x.h
+++ b/arch/arm/plat-mxc/include/mach/mx2x.h
@@ -25,51 +25,49 @@
 /* The following addresses are common between i.MX21 and i.MX27 */
-/* Register offests */
+/* Register offsets */
-#define AIPI_BASE_ADDR          0x10000000
+#define MX2x_AIPI_BASE_ADDR             0x10000000
-#define AIPI_BASE_ADDR_VIRT     0xF4000000
+#define MX2x_AIPI_BASE_ADDR_VIRT        0xf4000000
-#define AIPI_SIZE               SZ_1M
+#define MX2x_AIPI_SIZE                  SZ_1M
+#define MX2x_DMA_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x01000)
-#define DMA_BASE_ADDR           (AIPI_BASE_ADDR + 0x01000)
+#define MX2x_WDOG_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x02000)
-#define WDOG_BASE_ADDR          (AIPI_BASE_ADDR + 0x02000)
+#define MX2x_GPT1_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x03000)
-#define GPT1_BASE_ADDR          (AIPI_BASE_ADDR + 0x03000)
+#define MX2x_GPT2_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x04000)
-#define GPT2_BASE_ADDR          (AIPI_BASE_ADDR + 0x04000)
+#define MX2x_GPT3_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x05000)
-#define GPT3_BASE_ADDR          (AIPI_BASE_ADDR + 0x05000)
+#define MX2x_PWM_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x06000)
-#define PWM_BASE_ADDR           (AIPI_BASE_ADDR + 0x06000)
+#define MX2x_RTC_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x07000)
-#define RTC_BASE_ADDR           (AIPI_BASE_ADDR + 0x07000)
+#define MX2x_KPP_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x08000)
-#define KPP_BASE_ADDR           (AIPI_BASE_ADDR + 0x08000)
+#define MX2x_OWIRE_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x09000)
-#define OWIRE_BASE_ADDR         (AIPI_BASE_ADDR + 0x09000)
+#define MX2x_UART1_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x0a000)
-#define UART1_BASE_ADDR         (AIPI_BASE_ADDR + 0x0A000)
+#define MX2x_UART2_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x0b000)
-#define UART2_BASE_ADDR         (AIPI_BASE_ADDR + 0x0B000)
+#define MX2x_UART3_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x0c000)
-#define UART3_BASE_ADDR         (AIPI_BASE_ADDR + 0x0C000)
+#define MX2x_UART4_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x0d000)
-#define UART4_BASE_ADDR         (AIPI_BASE_ADDR + 0x0D000)
+#define MX2x_CSPI1_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x0e000)
-#define CSPI1_BASE_ADDR         (AIPI_BASE_ADDR + 0x0E000)
+#define MX2x_CSPI2_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x0f000)
-#define CSPI2_BASE_ADDR         (AIPI_BASE_ADDR + 0x0F000)
+#define MX2x_SSI1_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x10000)
-#define SSI1_BASE_ADDR          (AIPI_BASE_ADDR + 0x10000)
+#define MX2x_SSI2_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x11000)
-#define SSI2_BASE_ADDR          (AIPI_BASE_ADDR + 0x11000)
+#define MX2x_I2C_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x12000)
-#define I2C_BASE_ADDR           (AIPI_BASE_ADDR + 0x12000)
+#define MX2x_SDHC1_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x13000)
-#define SDHC1_BASE_ADDR         (AIPI_BASE_ADDR + 0x13000)
+#define MX2x_SDHC2_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x14000)
-#define SDHC2_BASE_ADDR         (AIPI_BASE_ADDR + 0x14000)
+#define MX2x_GPIO_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x15000)
-#define GPIO_BASE_ADDR          (AIPI_BASE_ADDR + 0x15000)
+#define MX2x_AUDMUX_BASE_ADDR                   (MX2x_AIPI_BASE_ADDR + 0x16000)
-#define AUDMUX_BASE_ADDR        (AIPI_BASE_ADDR + 0x16000)
+#define MX2x_CSPI3_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x17000)
-#define CSPI3_BASE_ADDR         (AIPI_BASE_ADDR + 0x17000)
+#define MX2x_LCDC_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x21000)
-#define LCDC_BASE_ADDR          (AIPI_BASE_ADDR + 0x21000)
+#define MX2x_SLCDC_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x22000)
-#define SLCDC_BASE_ADDR         (AIPI_BASE_ADDR + 0x22000)
+#define MX2x_USBOTG_BASE_ADDR                   (MX2x_AIPI_BASE_ADDR + 0x24000)
-#define USBOTG_BASE_ADDR        (AIPI_BASE_ADDR + 0x24000)
+#define MX2x_EMMA_PP_BASE_ADDR                  (MX2x_AIPI_BASE_ADDR + 0x26000)
-#define EMMA_PP_BASE_ADDR       (AIPI_BASE_ADDR + 0x26000)
+#define MX2x_EMMA_PRP_BASE_ADDR                 (MX2x_AIPI_BASE_ADDR + 0x26400)
-#define EMMA_PRP_BASE_ADDR      (AIPI_BASE_ADDR + 0x26400)
+#define MX2x_CCM_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x27000)
-#define CCM_BASE_ADDR           (AIPI_BASE_ADDR + 0x27000)
+#define MX2x_SYSCTRL_BASE_ADDR                  (MX2x_AIPI_BASE_ADDR + 0x27800)
-#define SYSCTRL_BASE_ADDR       (AIPI_BASE_ADDR + 0x27800)
+#define MX2x_JAM_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x3e000)
-#define JAM_BASE_ADDR           (AIPI_BASE_ADDR + 0x3E000)
+#define MX2x_MAX_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x3f000)
-#define MAX_BASE_ADDR           (AIPI_BASE_ADDR + 0x3F000)
+#define MX2x_AVIC_BASE_ADDR             0x10040000
-#define AVIC_BASE_ADDR          0x10040000
+#define MX2x_SAHB1_BASE_ADDR            0x80000000
-#define SAHB1_BASE_ADDR         0x80000000
+#define MX2x_SAHB1_BASE_ADDR_VIRT       0xf4100000
-#define SAHB1_BASE_ADDR_VIRT    0xF4100000
+#define MX2x_SAHB1_SIZE                 SZ_1M
-#define SAHB1_SIZE              SZ_1M
+#define MX2x_CSI_BASE_ADDR                      (MX2x_SAHB1_BASE_ADDR + 0x0000)
-#define CSI_BASE_ADDR           (SAHB1_BASE_ADDR + 0x0000)
 /*
 * This macro defines the physical to virtual address mapping for all the
@@ -105,78 +103,189 @@
        (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
 /* fixed interrupt numbers */
-#define MXC_INT_LCDC            61
+#define MX2x_INT_CSPI3          6
-#define MXC_INT_SLCDC           60
+#define MX2x_INT_GPIO           8
-#define MXC_INT_EMMAPP          52
+#define MX2x_INT_SDHC2          10
-#define MXC_INT_EMMAPRP         51
+#define MX2x_INT_SDHC1          11
-#define MXC_INT_DMACH15         47
+#define MX2x_INT_I2C            12
-#define MXC_INT_DMACH14         46
+#define MX2x_INT_SSI2           13
-#define MXC_INT_DMACH13         45
+#define MX2x_INT_SSI1           14
-#define MXC_INT_DMACH12         44
+#define MX2x_INT_CSPI2          15
-#define MXC_INT_DMACH11         43
+#define MX2x_INT_CSPI1          16
-#define MXC_INT_DMACH10         42
+#define MX2x_INT_UART4          17
-#define MXC_INT_DMACH9          41
+#define MX2x_INT_UART3          18
-#define MXC_INT_DMACH8          40
+#define MX2x_INT_UART2          19
-#define MXC_INT_DMACH7          39
+#define MX2x_INT_UART1          20
-#define MXC_INT_DMACH6          38
+#define MX2x_INT_KPP            21
-#define MXC_INT_DMACH5          37
+#define MX2x_INT_RTC            22
-#define MXC_INT_DMACH4          36
+#define MX2x_INT_PWM            23
-#define MXC_INT_DMACH3          35
+#define MX2x_INT_GPT3           24
-#define MXC_INT_DMACH2          34
+#define MX2x_INT_GPT2           25
-#define MXC_INT_DMACH1          33
+#define MX2x_INT_GPT1           26
-#define MXC_INT_DMACH0          32
+#define MX2x_INT_WDOG           27
-#define MXC_INT_CSI             31
+#define MX2x_INT_PCMCIA         28
-#define MXC_INT_NANDFC          29
+#define MX2x_INT_NANDFC         29
-#define MXC_INT_PCMCIA          28
+#define MX2x_INT_CSI            31
-#define MXC_INT_WDOG            27
+#define MX2x_INT_DMACH0         32
-#define MXC_INT_GPT1            26
+#define MX2x_INT_DMACH1         33
-#define MXC_INT_GPT2            25
+#define MX2x_INT_DMACH2         34
-#define MXC_INT_GPT3            24
+#define MX2x_INT_DMACH3         35
-#define MXC_INT_GPT             INT_GPT1
+#define MX2x_INT_DMACH4         36
-#define MXC_INT_PWM             23
+#define MX2x_INT_DMACH5         37
-#define MXC_INT_RTC             22
+#define MX2x_INT_DMACH6         38
-#define MXC_INT_KPP             21
+#define MX2x_INT_DMACH7         39
-#define MXC_INT_UART1           20
+#define MX2x_INT_DMACH8         40
-#define MXC_INT_UART2           19
+#define MX2x_INT_DMACH9         41
-#define MXC_INT_UART3           18
+#define MX2x_INT_DMACH10        42
-#define MXC_INT_UART4           17
+#define MX2x_INT_DMACH11        43
-#define MXC_INT_CSPI1           16
+#define MX2x_INT_DMACH12        44
-#define MXC_INT_CSPI2           15
+#define MX2x_INT_DMACH13        45
-#define MXC_INT_SSI1            14
+#define MX2x_INT_DMACH14        46
-#define MXC_INT_SSI2            13
+#define MX2x_INT_DMACH15        47
-#define MXC_INT_I2C             12
+#define MX2x_INT_EMMAPRP        51
-#define MXC_INT_SDHC1           11
+#define MX2x_INT_EMMAPP         52
-#define MXC_INT_SDHC2           10
+#define MX2x_INT_SLCDC          60
-#define MXC_INT_GPIO            8
+#define MX2x_INT_LCDC           61
-#define MXC_INT_CSPI3           6
 /* fixed DMA request numbers */
-#define DMA_REQ_CSI_RX          31
+#define MX2x_DMA_REQ_CSPI3_RX   1
-#define DMA_REQ_CSI_STAT        30
+#define MX2x_DMA_REQ_CSPI3_TX   2
-#define DMA_REQ_UART1_TX        27
+#define MX2x_DMA_REQ_EXT        3
-#define DMA_REQ_UART1_RX        26
+#define MX2x_DMA_REQ_SDHC2      6
-#define DMA_REQ_UART2_TX        25
+#define MX2x_DMA_REQ_SDHC1      7
-#define DMA_REQ_UART2_RX        24
+#define MX2x_DMA_REQ_SSI2_RX0   8
-#define DMA_REQ_UART3_TX        23
+#define MX2x_DMA_REQ_SSI2_TX0   9
-#define DMA_REQ_UART3_RX        22
+#define MX2x_DMA_REQ_SSI2_RX1   10
-#define DMA_REQ_UART4_TX        21
+#define MX2x_DMA_REQ_SSI2_TX1   11
-#define DMA_REQ_UART4_RX        20
+#define MX2x_DMA_REQ_SSI1_RX0   12
-#define DMA_REQ_CSPI1_TX        19
+#define MX2x_DMA_REQ_SSI1_TX0   13
-#define DMA_REQ_CSPI1_RX        18
+#define MX2x_DMA_REQ_SSI1_RX1   14
-#define DMA_REQ_CSPI2_TX        17
+#define MX2x_DMA_REQ_SSI1_TX1   15
-#define DMA_REQ_CSPI2_RX        16
+#define MX2x_DMA_REQ_CSPI2_RX   16
-#define DMA_REQ_SSI1_TX1        15
+#define MX2x_DMA_REQ_CSPI2_TX   17
-#define DMA_REQ_SSI1_RX1        14
+#define MX2x_DMA_REQ_CSPI1_RX   18
-#define DMA_REQ_SSI1_TX0        13
+#define MX2x_DMA_REQ_CSPI1_TX   19
-#define DMA_REQ_SSI1_RX0        12
+#define MX2x_DMA_REQ_UART4_RX   20
-#define DMA_REQ_SSI2_TX1        11
+#define MX2x_DMA_REQ_UART4_TX   21
-#define DMA_REQ_SSI2_RX1        10
+#define MX2x_DMA_REQ_UART3_RX   22
-#define DMA_REQ_SSI2_TX0        9
+#define MX2x_DMA_REQ_UART3_TX   23
-#define DMA_REQ_SSI2_RX0        8
+#define MX2x_DMA_REQ_UART2_RX   24
-#define DMA_REQ_SDHC1           7
+#define MX2x_DMA_REQ_UART2_TX   25
-#define DMA_REQ_SDHC2           6
+#define MX2x_DMA_REQ_UART1_RX   26
-#define DMA_REQ_EXT             3
+#define MX2x_DMA_REQ_UART1_TX   27
-#define DMA_REQ_CSPI3_TX        2
+#define MX2x_DMA_REQ_CSI_STAT   30
-#define DMA_REQ_CSPI3_RX        1
+#define MX2x_DMA_REQ_CSI_RX     31
+/* these should go away */
+#define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR
+#define AIPI_BASE_ADDR_VIRT MX2x_AIPI_BASE_ADDR_VIRT
+#define AIPI_SIZE MX2x_AIPI_SIZE
+#define DMA_BASE_ADDR MX2x_DMA_BASE_ADDR
+#define WDOG_BASE_ADDR MX2x_WDOG_BASE_ADDR
+#define GPT1_BASE_ADDR MX2x_GPT1_BASE_ADDR
+#define GPT2_BASE_ADDR MX2x_GPT2_BASE_ADDR
+#define GPT3_BASE_ADDR MX2x_GPT3_BASE_ADDR
+#define PWM_BASE_ADDR MX2x_PWM_BASE_ADDR
+#define RTC_BASE_ADDR MX2x_RTC_BASE_ADDR
+#define KPP_BASE_ADDR MX2x_KPP_BASE_ADDR
+#define OWIRE_BASE_ADDR MX2x_OWIRE_BASE_ADDR
+#define UART1_BASE_ADDR MX2x_UART1_BASE_ADDR
+#define UART2_BASE_ADDR MX2x_UART2_BASE_ADDR
+#define UART3_BASE_ADDR MX2x_UART3_BASE_ADDR
+#define UART4_BASE_ADDR MX2x_UART4_BASE_ADDR
+#define CSPI1_BASE_ADDR MX2x_CSPI1_BASE_ADDR
+#define CSPI2_BASE_ADDR MX2x_CSPI2_BASE_ADDR
+#define SSI1_BASE_ADDR MX2x_SSI1_BASE_ADDR
+#define SSI2_BASE_ADDR MX2x_SSI2_BASE_ADDR
+#define I2C_BASE_ADDR MX2x_I2C_BASE_ADDR
+#define SDHC1_BASE_ADDR MX2x_SDHC1_BASE_ADDR
+#define SDHC2_BASE_ADDR MX2x_SDHC2_BASE_ADDR
+#define GPIO_BASE_ADDR MX2x_GPIO_BASE_ADDR
+#define AUDMUX_BASE_ADDR MX2x_AUDMUX_BASE_ADDR
+#define CSPI3_BASE_ADDR MX2x_CSPI3_BASE_ADDR
+#define LCDC_BASE_ADDR MX2x_LCDC_BASE_ADDR
+#define SLCDC_BASE_ADDR MX2x_SLCDC_BASE_ADDR
+#define USBOTG_BASE_ADDR MX2x_USBOTG_BASE_ADDR
+#define EMMA_PP_BASE_ADDR MX2x_EMMA_PP_BASE_ADDR
+#define EMMA_PRP_BASE_ADDR MX2x_EMMA_PRP_BASE_ADDR
+#define CCM_BASE_ADDR MX2x_CCM_BASE_ADDR
+#define SYSCTRL_BASE_ADDR MX2x_SYSCTRL_BASE_ADDR
+#define JAM_BASE_ADDR MX2x_JAM_BASE_ADDR
+#define MAX_BASE_ADDR MX2x_MAX_BASE_ADDR
+#define AVIC_BASE_ADDR MX2x_AVIC_BASE_ADDR
+#define SAHB1_BASE_ADDR MX2x_SAHB1_BASE_ADDR
+#define SAHB1_BASE_ADDR_VIRT MX2x_SAHB1_BASE_ADDR_VIRT
+#define SAHB1_SIZE MX2x_SAHB1_SIZE
+#define CSI_BASE_ADDR MX2x_CSI_BASE_ADDR
+#define MXC_INT_CSPI3 MX2x_INT_CSPI3
+#define MXC_INT_GPIO MX2x_INT_GPIO
+#define MXC_INT_SDHC2 MX2x_INT_SDHC2
+#define MXC_INT_SDHC1 MX2x_INT_SDHC1
+#define MXC_INT_I2C MX2x_INT_I2C
+#define MXC_INT_SSI2 MX2x_INT_SSI2
+#define MXC_INT_SSI1 MX2x_INT_SSI1
+#define MXC_INT_CSPI2 MX2x_INT_CSPI2
+#define MXC_INT_CSPI1 MX2x_INT_CSPI1
+#define MXC_INT_UART4 MX2x_INT_UART4
+#define MXC_INT_UART3 MX2x_INT_UART3
+#define MXC_INT_UART2 MX2x_INT_UART2
+#define MXC_INT_UART1 MX2x_INT_UART1
+#define MXC_INT_KPP MX2x_INT_KPP
+#define MXC_INT_RTC MX2x_INT_RTC
+#define MXC_INT_PWM MX2x_INT_PWM
+#define MXC_INT_GPT3 MX2x_INT_GPT3
+#define MXC_INT_GPT2 MX2x_INT_GPT2
+#define MXC_INT_GPT1 MX2x_INT_GPT1
+#define MXC_INT_WDOG MX2x_INT_WDOG
+#define MXC_INT_PCMCIA MX2x_INT_PCMCIA
+#define MXC_INT_NANDFC MX2x_INT_NANDFC
+#define MXC_INT_CSI MX2x_INT_CSI
+#define MXC_INT_DMACH0 MX2x_INT_DMACH0
+#define MXC_INT_DMACH1 MX2x_INT_DMACH1
+#define MXC_INT_DMACH2 MX2x_INT_DMACH2
+#define MXC_INT_DMACH3 MX2x_INT_DMACH3
+#define MXC_INT_DMACH4 MX2x_INT_DMACH4
+#define MXC_INT_DMACH5 MX2x_INT_DMACH5
+#define MXC_INT_DMACH6 MX2x_INT_DMACH6
+#define MXC_INT_DMACH7 MX2x_INT_DMACH7
+#define MXC_INT_DMACH8 MX2x_INT_DMACH8
+#define MXC_INT_DMACH9 MX2x_INT_DMACH9
+#define MXC_INT_DMACH10 MX2x_INT_DMACH10
+#define MXC_INT_DMACH11 MX2x_INT_DMACH11
+#define MXC_INT_DMACH12 MX2x_INT_DMACH12
+#define MXC_INT_DMACH13 MX2x_INT_DMACH13
+#define MXC_INT_DMACH14 MX2x_INT_DMACH14
+#define MXC_INT_DMACH15 MX2x_INT_DMACH15
+#define MXC_INT_EMMAPRP MX2x_INT_EMMAPRP
+#define MXC_INT_EMMAPP MX2x_INT_EMMAPP
+#define MXC_INT_SLCDC MX2x_INT_SLCDC
+#define MXC_INT_LCDC MX2x_INT_LCDC
+#define DMA_REQ_CSPI3_RX MX2x_DMA_REQ_CSPI3_RX
+#define DMA_REQ_CSPI3_TX MX2x_DMA_REQ_CSPI3_TX
+#define DMA_REQ_EXT MX2x_DMA_REQ_EXT
+#define DMA_REQ_SDHC2 MX2x_DMA_REQ_SDHC2
+#define DMA_REQ_SDHC1 MX2x_DMA_REQ_SDHC1
+#define DMA_REQ_SSI2_RX0 MX2x_DMA_REQ_SSI2_RX0
+#define DMA_REQ_SSI2_TX0 MX2x_DMA_REQ_SSI2_TX0
+#define DMA_REQ_SSI2_RX1 MX2x_DMA_REQ_SSI2_RX1
+#define DMA_REQ_SSI2_TX1 MX2x_DMA_REQ_SSI2_TX1
+#define DMA_REQ_SSI1_RX0 MX2x_DMA_REQ_SSI1_RX0
+#define DMA_REQ_SSI1_TX0 MX2x_DMA_REQ_SSI1_TX0
+#define DMA_REQ_SSI1_RX1 MX2x_DMA_REQ_SSI1_RX1
+#define DMA_REQ_SSI1_TX1 MX2x_DMA_REQ_SSI1_TX1
+#define DMA_REQ_CSPI2_RX MX2x_DMA_REQ_CSPI2_RX
+#define DMA_REQ_CSPI2_TX MX2x_DMA_REQ_CSPI2_TX
+#define DMA_REQ_CSPI1_RX MX2x_DMA_REQ_CSPI1_RX
+#define DMA_REQ_CSPI1_TX MX2x_DMA_REQ_CSPI1_TX
+#define DMA_REQ_UART4_RX MX2x_DMA_REQ_UART4_RX
+#define DMA_REQ_UART4_TX MX2x_DMA_REQ_UART4_TX
+#define DMA_REQ_UART3_RX MX2x_DMA_REQ_UART3_RX
+#define DMA_REQ_UART3_TX MX2x_DMA_REQ_UART3_TX
+#define DMA_REQ_UART2_RX MX2x_DMA_REQ_UART2_RX
+#define DMA_REQ_UART2_TX MX2x_DMA_REQ_UART2_TX
+#define DMA_REQ_UART1_RX MX2x_DMA_REQ_UART1_RX
+#define DMA_REQ_UART1_TX MX2x_DMA_REQ_UART1_TX
+#define DMA_REQ_CSI_STAT MX2x_DMA_REQ_CSI_STAT
+#define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX
 #endif /* __ASM_ARCH_MXC_MX2x_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index 14ac0dcc82f4..b8b47d139eb5 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -1,45 +1,218 @@
 /*
 * IRAM
 */
-#define MX31_IRAM_BASE_ADDR             0x1FFC0000      /* internal ram */
+#define MX31_IRAM_BASE_ADDR             0x1ffc0000      /* internal ram */
 #define MX31_IRAM_SIZE                  SZ_16K
-#define MX31_OTG_BASE_ADDR      (AIPS1_BASE_ADDR + 0x00088000)
+#define MX31_L2CC_BASE_ADDR             0x30000000
-#define ATA_BASE_ADDR           (AIPS1_BASE_ADDR + 0x0008C000)
+#define MX31_L2CC_SIZE                  SZ_1M
-#define UART4_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000B0000)
-#define UART5_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000B4000)
-#define MMC_SDHC1_BASE_ADDR     (SPBA0_BASE_ADDR + 0x00004000)
+#define MX31_AIPS1_BASE_ADDR            0x43f00000
-#define MMC_SDHC2_BASE_ADDR     (SPBA0_BASE_ADDR + 0x00008000)
+#define MX31_AIPS1_BASE_ADDR_VIRT       0xfc000000
-#define SIM1_BASE_ADDR          (SPBA0_BASE_ADDR + 0x00018000)
+#define MX31_AIPS1_SIZE                 SZ_1M
-#define IIM_BASE_ADDR           (SPBA0_BASE_ADDR + 0x0001C000)
+#define MX31_MAX_BASE_ADDR                      (MX31_AIPS1_BASE_ADDR + 0x04000)
+#define MX31_EVTMON_BASE_ADDR                   (MX31_AIPS1_BASE_ADDR + 0x08000)
+#define MX31_CLKCTL_BASE_ADDR                   (MX31_AIPS1_BASE_ADDR + 0x0c000)
+#define MX31_ETB_SLOT4_BASE_ADDR                (MX31_AIPS1_BASE_ADDR + 0x10000)
+#define MX31_ETB_SLOT5_BASE_ADDR                (MX31_AIPS1_BASE_ADDR + 0x14000)
+#define MX31_ECT_CTIO_BASE_ADDR                 (MX31_AIPS1_BASE_ADDR + 0x18000)
+#define MX31_I2C_BASE_ADDR                      (MX31_AIPS1_BASE_ADDR + 0x80000)
+#define MX31_I2C3_BASE_ADDR                     (MX31_AIPS1_BASE_ADDR + 0x84000)
+#define MX31_OTG_BASE_ADDR                      (MX31_AIPS1_BASE_ADDR + 0x88000)
+#define MX31_ATA_BASE_ADDR                      (MX31_AIPS1_BASE_ADDR + 0x8c000)
+#define MX31_UART1_BASE_ADDR                    (MX31_AIPS1_BASE_ADDR + 0x90000)
+#define MX31_UART2_BASE_ADDR                    (MX31_AIPS1_BASE_ADDR + 0x94000)
+#define MX31_I2C2_BASE_ADDR                     (MX31_AIPS1_BASE_ADDR + 0x98000)
+#define MX31_OWIRE_BASE_ADDR                    (MX31_AIPS1_BASE_ADDR + 0x9c000)
+#define MX31_SSI1_BASE_ADDR                     (MX31_AIPS1_BASE_ADDR + 0xa0000)
+#define MX31_CSPI1_BASE_ADDR                    (MX31_AIPS1_BASE_ADDR + 0xa4000)
+#define MX31_KPP_BASE_ADDR                      (MX31_AIPS1_BASE_ADDR + 0xa8000)
+#define MX31_IOMUXC_BASE_ADDR                   (MX31_AIPS1_BASE_ADDR + 0xac000)
+#define MX31_UART4_BASE_ADDR                    (MX31_AIPS1_BASE_ADDR + 0xb0000)
+#define MX31_UART5_BASE_ADDR                    (MX31_AIPS1_BASE_ADDR + 0xb4000)
+#define MX31_ECT_IP1_BASE_ADDR                  (MX31_AIPS1_BASE_ADDR + 0xb8000)
+#define MX31_ECT_IP2_BASE_ADDR                  (MX31_AIPS1_BASE_ADDR + 0xbc000)
-#define CSPI3_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00084000)
+#define MX31_SPBA0_BASE_ADDR            0x50000000
-#define FIRI_BASE_ADDR          (AIPS2_BASE_ADDR + 0x0008C000)
+#define MX31_SPBA0_BASE_ADDR_VIRT       0xfc100000
-#define SCM_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000AE000)
+#define MX31_SPBA0_SIZE                 SZ_1M
-#define SMN_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000AF000)
+#define MX31_MMC_SDHC1_BASE_ADDR                (MX31_SPBA0_BASE_ADDR + 0x04000)
-#define MPEG4_ENC_BASE_ADDR     (AIPS2_BASE_ADDR + 0x000C8000)
+#define MX31_MMC_SDHC2_BASE_ADDR                (MX31_SPBA0_BASE_ADDR + 0x08000)
+#define MX31_UART3_BASE_ADDR                    (MX31_SPBA0_BASE_ADDR + 0x0c000)
+#define MX31_CSPI2_BASE_ADDR                    (MX31_SPBA0_BASE_ADDR + 0x10000)
+#define MX31_SSI2_BASE_ADDR                     (MX31_SPBA0_BASE_ADDR + 0x14000)
+#define MX31_SIM1_BASE_ADDR                     (MX31_SPBA0_BASE_ADDR + 0x18000)
+#define MX31_IIM_BASE_ADDR                      (MX31_SPBA0_BASE_ADDR + 0x1c000)
+#define MX31_ATA_DMA_BASE_ADDR                  (MX31_SPBA0_BASE_ADDR + 0x20000)
+#define MX31_MSHC1_BASE_ADDR                    (MX31_SPBA0_BASE_ADDR + 0x24000)
+#define MX31_SPBA_CTRL_BASE_ADDR                (MX31_SPBA0_BASE_ADDR + 0x3c000)
-#define MX31_NFC_BASE_ADDR      (X_MEMC_BASE_ADDR + 0x0000)
+#define MX31_AIPS2_BASE_ADDR            0x53f00000
+#define MX31_AIPS2_BASE_ADDR_VIRT       0xfc200000
+#define MX31_AIPS2_SIZE                 SZ_1M
+#define MX31_CCM_BASE_ADDR                      (MX31_AIPS2_BASE_ADDR + 0x80000)
+#define MX31_CSPI3_BASE_ADDR                    (MX31_AIPS2_BASE_ADDR + 0x84000)
+#define MX31_FIRI_BASE_ADDR                     (MX31_AIPS2_BASE_ADDR + 0x8c000)
+#define MX31_GPT1_BASE_ADDR                     (MX31_AIPS2_BASE_ADDR + 0x90000)
+#define MX31_EPIT1_BASE_ADDR                    (MX31_AIPS2_BASE_ADDR + 0x94000)
+#define MX31_EPIT2_BASE_ADDR                    (MX31_AIPS2_BASE_ADDR + 0x98000)
+#define MX31_GPIO3_BASE_ADDR                    (MX31_AIPS2_BASE_ADDR + 0xa4000)
+#define MX31_SCC_BASE_ADDR                      (MX31_AIPS2_BASE_ADDR + 0xac000)
+#define MX31_SCM_BASE_ADDR                      (MX31_AIPS2_BASE_ADDR + 0xae000)
+#define MX31_SMN_BASE_ADDR                      (MX31_AIPS2_BASE_ADDR + 0xaf000)
+#define MX31_RNGA_BASE_ADDR                     (MX31_AIPS2_BASE_ADDR + 0xb0000)
+#define MX31_IPU_CTRL_BASE_ADDR                 (MX31_AIPS2_BASE_ADDR + 0xc0000)
+#define MX31_AUDMUX_BASE_ADDR                   (MX31_AIPS2_BASE_ADDR + 0xc4000)
+#define MX31_MPEG4_ENC_BASE_ADDR                (MX31_AIPS2_BASE_ADDR + 0xc8000)
+#define MX31_GPIO1_BASE_ADDR                    (MX31_AIPS2_BASE_ADDR + 0xcc000)
+#define MX31_GPIO2_BASE_ADDR                    (MX31_AIPS2_BASE_ADDR + 0xd0000)
+#define MX31_SDMA_BASE_ADDR                     (MX31_AIPS2_BASE_ADDR + 0xd4000)
+#define MX31_RTC_BASE_ADDR                      (MX31_AIPS2_BASE_ADDR + 0xd8000)
+#define MX31_WDOG_BASE_ADDR                     (MX31_AIPS2_BASE_ADDR + 0xdc000)
+#define MX31_PWM_BASE_ADDR                      (MX31_AIPS2_BASE_ADDR + 0xe0000)
+#define MX31_RTIC_BASE_ADDR                     (MX31_AIPS2_BASE_ADDR + 0xec000)
-#define MXC_INT_MPEG4_ENCODER   5
+#define MX31_ROMP_BASE_ADDR             0x60000000
-#define MXC_INT_FIRI            7
+#define MX31_ROMP_BASE_ADDR_VIRT        0xfc500000
+#define MX31_ROMP_SIZE                  SZ_1M
+#define MX31_AVIC_BASE_ADDR             0x68000000
+#define MX31_AVIC_BASE_ADDR_VIRT        0xfc400000
+#define MX31_AVIC_SIZE                  SZ_1M
+#define MX31_IPU_MEM_BASE_ADDR          0x70000000
+#define MX31_CSD0_BASE_ADDR             0x80000000
+#define MX31_CSD1_BASE_ADDR             0x90000000
+#define MX31_CS0_BASE_ADDR              0xa0000000
+#define MX31_CS1_BASE_ADDR              0xa8000000
+#define MX31_CS2_BASE_ADDR              0xb0000000
+#define MX31_CS3_BASE_ADDR              0xb2000000
+#define MX31_CS4_BASE_ADDR              0xb4000000
+#define MX31_CS4_BASE_ADDR_VIRT         0xf4000000
+#define MX31_CS4_SIZE                   SZ_32M
+#define MX31_CS5_BASE_ADDR              0xb6000000
+#define MX31_CS5_BASE_ADDR_VIRT         0xf6000000
+#define MX31_CS5_SIZE                   SZ_32M
+#define MX31_X_MEMC_BASE_ADDR           0xb8000000
+#define MX31_X_MEMC_BASE_ADDR_VIRT      0xfc320000
+#define MX31_X_MEMC_SIZE                SZ_64K
+#define MX31_NFC_BASE_ADDR                      (MX31_X_MEMC_BASE_ADDR + 0x0000)
+#define MX31_ESDCTL_BASE_ADDR                   (MX31_X_MEMC_BASE_ADDR + 0x1000)
+#define MX31_WEIM_BASE_ADDR                     (MX31_X_MEMC_BASE_ADDR + 0x2000)
+#define MX31_M3IF_BASE_ADDR                     (MX31_X_MEMC_BASE_ADDR + 0x3000)
+#define MX31_EMI_CTL_BASE_ADDR                  (MX31_X_MEMC_BASE_ADDR + 0x4000)
+#define MX31_PCMCIA_CTL_BASE_ADDR               MX31_EMI_CTL_BASE_ADDR
+#define MX31_PCMCIA_MEM_BASE_ADDR       0xbc000000
+#define MX31_INT_I2C3           3
+#define MX31_INT_I2C2           4
+#define MX31_INT_MPEG4_ENCODER  5
+#define MX31_INT_RTIC           6
+#define MX31_INT_FIRI           7
 #define MX31_INT_MMC_SDHC2      8
-#define MXC_INT_MMC_SDHC1       9
+#define MX31_INT_MMC_SDHC1      9
+#define MX31_INT_I2C            10
 #define MX31_INT_SSI2           11
 #define MX31_INT_SSI1           12
-#define MXC_INT_MBX             16
+#define MX31_INT_CSPI2          13
-#define MXC_INT_CSPI3           17
+#define MX31_INT_CSPI1          14
-#define MXC_INT_SIM2            20
+#define MX31_INT_ATA            15
-#define MXC_INT_SIM1            21
+#define MX31_INT_MBX            16
-#define MXC_INT_CCM_DVFS        31
+#define MX31_INT_CSPI3          17
-#define MXC_INT_USB1            35
+#define MX31_INT_UART3          18
-#define MXC_INT_USB2            36
+#define MX31_INT_IIM            19
-#define MXC_INT_USB3            37
+#define MX31_INT_SIM2           20
-#define MXC_INT_USB4            38
+#define MX31_INT_SIM1           21
-#define MXC_INT_MSHC2           40
+#define MX31_INT_RNGA           22
-#define MXC_INT_UART4           46
+#define MX31_INT_EVTMON         23
-#define MXC_INT_UART5           47
+#define MX31_INT_KPP            24
-#define MXC_INT_CCM             53
+#define MX31_INT_RTC            25
-#define MXC_INT_PCMCIA          54
+#define MX31_INT_PWM            26
+#define MX31_INT_EPIT2          27
+#define MX31_INT_EPIT1          28
+#define MX31_INT_GPT            29
+#define MX31_INT_POWER_FAIL     30
+#define MX31_INT_CCM_DVFS       31
+#define MX31_INT_UART2          32
+#define MX31_INT_NANDFC         33
+#define MX31_INT_SDMA           34
+#define MX31_INT_USB1           35
+#define MX31_INT_USB2           36
+#define MX31_INT_USB3           37
+#define MX31_INT_USB4           38
+#define MX31_INT_MSHC1          39
+#define MX31_INT_MSHC2          40
+#define MX31_INT_IPU_ERR        41
+#define MX31_INT_IPU_SYN        42
+#define MX31_INT_UART1          45
+#define MX31_INT_UART4          46
+#define MX31_INT_UART5          47
+#define MX31_INT_ECT            48
+#define MX31_INT_SCC_SCM        49
+#define MX31_INT_SCC_SMN        50
+#define MX31_INT_GPIO2          51
+#define MX31_INT_GPIO1          52
+#define MX31_INT_CCM            53
+#define MX31_INT_PCMCIA         54
+#define MX31_INT_WDOG           55
+#define MX31_INT_GPIO3          56
+#define MX31_INT_EXT_POWER      58
+#define MX31_INT_EXT_TEMPER     59
+#define MX31_INT_EXT_SENSOR60   60
+#define MX31_INT_EXT_SENSOR61   61
+#define MX31_INT_EXT_WDOG       62
+#define MX31_INT_EXT_TV         63
+#define MX31_PROD_SIGNATURE             0x1     /* For MX31 */
+/* silicon revisions specific to i.MX31 */
+#define MX31_CHIP_REV_1_0               0x10
+#define MX31_CHIP_REV_1_1               0x11
+#define MX31_CHIP_REV_1_2               0x12
+#define MX31_CHIP_REV_1_3               0x13
+#define MX31_CHIP_REV_2_0               0x20
+#define MX31_CHIP_REV_2_1               0x21
+#define MX31_CHIP_REV_2_2               0x22
+#define MX31_CHIP_REV_2_3               0x23
+#define MX31_CHIP_REV_3_0               0x30
+#define MX31_CHIP_REV_3_1               0x31
+#define MX31_CHIP_REV_3_2               0x32
+#define MX31_SYSTEM_REV_MIN             MX31_CHIP_REV_1_0
+#define MX31_SYSTEM_REV_NUM             3
+/* these should go away */
+#define ATA_BASE_ADDR MX31_ATA_BASE_ADDR
+#define UART4_BASE_ADDR MX31_UART4_BASE_ADDR
+#define UART5_BASE_ADDR MX31_UART5_BASE_ADDR
+#define MMC_SDHC1_BASE_ADDR MX31_MMC_SDHC1_BASE_ADDR
+#define MMC_SDHC2_BASE_ADDR MX31_MMC_SDHC2_BASE_ADDR
+#define SIM1_BASE_ADDR MX31_SIM1_BASE_ADDR
+#define IIM_BASE_ADDR MX31_IIM_BASE_ADDR
+#define CSPI3_BASE_ADDR MX31_CSPI3_BASE_ADDR
+#define FIRI_BASE_ADDR MX31_FIRI_BASE_ADDR
+#define SCM_BASE_ADDR MX31_SCM_BASE_ADDR
+#define SMN_BASE_ADDR MX31_SMN_BASE_ADDR
+#define MPEG4_ENC_BASE_ADDR MX31_MPEG4_ENC_BASE_ADDR
+#define MXC_INT_MPEG4_ENCODER MX31_INT_MPEG4_ENCODER
+#define MXC_INT_FIRI MX31_INT_FIRI
+#define MXC_INT_MMC_SDHC1 MX31_INT_MMC_SDHC1
+#define MXC_INT_MBX MX31_INT_MBX
+#define MXC_INT_CSPI3 MX31_INT_CSPI3
+#define MXC_INT_SIM2 MX31_INT_SIM2
+#define MXC_INT_SIM1 MX31_INT_SIM1
+#define MXC_INT_CCM_DVFS MX31_INT_CCM_DVFS
+#define MXC_INT_USB1 MX31_INT_USB1
+#define MXC_INT_USB2 MX31_INT_USB2
+#define MXC_INT_USB3 MX31_INT_USB3
+#define MXC_INT_USB4 MX31_INT_USB4
+#define MXC_INT_MSHC2 MX31_INT_MSHC2
+#define MXC_INT_UART4 MX31_INT_UART4
+#define MXC_INT_UART5 MX31_INT_UART5
+#define MXC_INT_CCM MX31_INT_CCM
+#define MXC_INT_PCMCIA MX31_INT_PCMCIA
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index ab4cfec6c8ab..af871bce35b6 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -2,29 +2,196 @@
 * IRAM
 */
 #define MX35_IRAM_BASE_ADDR             0x10000000      /* internal ram */
-#define MX35_IRAM_SIZE          SZ_128K
+#define MX35_IRAM_SIZE                  SZ_128K
-#define MXC_FEC_BASE_ADDR       0x50038000
+#define MX35_L2CC_BASE_ADDR             0x30000000
-#define MX35_OTG_BASE_ADDR      0x53ff4000
+#define MX35_L2CC_SIZE                  SZ_1M
-#define MX35_NFC_BASE_ADDR      0xBB000000
+#define MX35_AIPS1_BASE_ADDR            0x43f00000
+#define MX35_AIPS1_BASE_ADDR_VIRT       0xfc000000
+#define MX35_AIPS1_SIZE                 SZ_1M
+#define MX35_MAX_BASE_ADDR                      (MX35_AIPS1_BASE_ADDR + 0x04000)
+#define MX35_EVTMON_BASE_ADDR                   (MX35_AIPS1_BASE_ADDR + 0x08000)
+#define MX35_CLKCTL_BASE_ADDR                   (MX35_AIPS1_BASE_ADDR + 0x0c000)
+#define MX35_ETB_SLOT4_BASE_ADDR                (MX35_AIPS1_BASE_ADDR + 0x10000)
+#define MX35_ETB_SLOT5_BASE_ADDR                (MX35_AIPS1_BASE_ADDR + 0x14000)
+#define MX35_ECT_CTIO_BASE_ADDR                 (MX35_AIPS1_BASE_ADDR + 0x18000)
+#define MX35_I2C_BASE_ADDR                      (MX35_AIPS1_BASE_ADDR + 0x80000)
+#define MX35_I2C3_BASE_ADDR                     (MX35_AIPS1_BASE_ADDR + 0x84000)
+#define MX35_UART1_BASE_ADDR                    (MX35_AIPS1_BASE_ADDR + 0x90000)
+#define MX35_UART2_BASE_ADDR                    (MX35_AIPS1_BASE_ADDR + 0x94000)
+#define MX35_I2C2_BASE_ADDR                     (MX35_AIPS1_BASE_ADDR + 0x98000)
+#define MX35_OWIRE_BASE_ADDR                    (MX35_AIPS1_BASE_ADDR + 0x9c000)
+#define MX35_SSI1_BASE_ADDR                     (MX35_AIPS1_BASE_ADDR + 0xa0000)
+#define MX35_CSPI1_BASE_ADDR                    (MX35_AIPS1_BASE_ADDR + 0xa4000)
+#define MX35_KPP_BASE_ADDR                      (MX35_AIPS1_BASE_ADDR + 0xa8000)
+#define MX35_IOMUXC_BASE_ADDR                   (MX35_AIPS1_BASE_ADDR + 0xac000)
+#define MX35_ECT_IP1_BASE_ADDR                  (MX35_AIPS1_BASE_ADDR + 0xb8000)
+#define MX35_ECT_IP2_BASE_ADDR                  (MX35_AIPS1_BASE_ADDR + 0xbc000)
+#define MX35_SPBA0_BASE_ADDR            0x50000000
+#define MX35_SPBA0_BASE_ADDR_VIRT       0xfc100000
+#define MX35_SPBA0_SIZE                 SZ_1M
+#define MX35_UART3_BASE_ADDR                    (MX35_SPBA0_BASE_ADDR + 0x0c000)
+#define MX35_CSPI2_BASE_ADDR                    (MX35_SPBA0_BASE_ADDR + 0x10000)
+#define MX35_SSI2_BASE_ADDR                     (MX35_SPBA0_BASE_ADDR + 0x14000)
+#define MX35_ATA_DMA_BASE_ADDR                  (MX35_SPBA0_BASE_ADDR + 0x20000)
+#define MX35_MSHC1_BASE_ADDR                    (MX35_SPBA0_BASE_ADDR + 0x24000)
+#define MX35_FEC_BASE_ADDR              0x50038000
+#define MX35_SPBA_CTRL_BASE_ADDR                (MX35_SPBA0_BASE_ADDR + 0x3c000)
+#define MX35_AIPS2_BASE_ADDR            0x53f00000
+#define MX35_AIPS2_BASE_ADDR_VIRT       0xfc200000
+#define MX35_AIPS2_SIZE                 SZ_1M
+#define MX35_CCM_BASE_ADDR                      (MX35_AIPS2_BASE_ADDR + 0x80000)
+#define MX35_GPT1_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0x90000)
+#define MX35_EPIT1_BASE_ADDR                    (MX35_AIPS2_BASE_ADDR + 0x94000)
+#define MX35_EPIT2_BASE_ADDR                    (MX35_AIPS2_BASE_ADDR + 0x98000)
+#define MX35_GPIO3_BASE_ADDR                    (MX35_AIPS2_BASE_ADDR + 0xa4000)
+#define MX35_SCC_BASE_ADDR                      (MX35_AIPS2_BASE_ADDR + 0xac000)
+#define MX35_RNGA_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xb0000)
+#define MX35_IPU_CTRL_BASE_ADDR                 (MX35_AIPS2_BASE_ADDR + 0xc0000)
+#define MX35_AUDMUX_BASE_ADDR                   (MX35_AIPS2_BASE_ADDR + 0xc4000)
+#define MX35_GPIO1_BASE_ADDR                    (MX35_AIPS2_BASE_ADDR + 0xcc000)
+#define MX35_GPIO2_BASE_ADDR                    (MX35_AIPS2_BASE_ADDR + 0xd0000)
+#define MX35_SDMA_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xd4000)
+#define MX35_RTC_BASE_ADDR                      (MX35_AIPS2_BASE_ADDR + 0xd8000)
+#define MX35_WDOG_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xdc000)
+#define MX35_PWM_BASE_ADDR                      (MX35_AIPS2_BASE_ADDR + 0xe0000)
+#define MX35_RTIC_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xec000)
+#define MX35_OTG_BASE_ADDR              0x53ff4000
+#define MX35_ROMP_BASE_ADDR             0x60000000
+#define MX35_ROMP_BASE_ADDR_VIRT        0xfc500000
+#define MX35_ROMP_SIZE                  SZ_1M
+#define MX35_AVIC_BASE_ADDR             0x68000000
+#define MX35_AVIC_BASE_ADDR_VIRT        0xfc400000
+#define MX35_AVIC_SIZE                  SZ_1M
+/*
+ * Memory regions and CS
+ */
+#define MX35_IPU_MEM_BASE_ADDR          0x70000000
+#define MX35_CSD0_BASE_ADDR             0x80000000
+#define MX35_CSD1_BASE_ADDR             0x90000000
+#define MX35_CS0_BASE_ADDR              0xa0000000
+#define MX35_CS1_BASE_ADDR              0xa8000000
+#define MX35_CS2_BASE_ADDR              0xb0000000
+#define MX35_CS3_BASE_ADDR              0xb2000000
+#define MX35_CS4_BASE_ADDR              0xb4000000
+#define MX35_CS4_BASE_ADDR_VIRT         0xf4000000
+#define MX35_CS4_SIZE                   SZ_32M
+#define MX35_CS5_BASE_ADDR              0xb6000000
+#define MX35_CS5_BASE_ADDR_VIRT         0xf6000000
+#define MX35_CS5_SIZE                   SZ_32M
+/*
+ * NAND, SDRAM, WEIM, M3IF, EMI controllers
+ */
+#define MX35_X_MEMC_BASE_ADDR           0xb8000000
+#define MX35_X_MEMC_BASE_ADDR_VIRT      0xfc320000
+#define MX35_X_MEMC_SIZE                SZ_64K
+#define MX35_ESDCTL_BASE_ADDR                   (MX35_X_MEMC_BASE_ADDR + 0x1000)
+#define MX35_WEIM_BASE_ADDR                     (MX35_X_MEMC_BASE_ADDR + 0x2000)
+#define MX35_M3IF_BASE_ADDR                     (MX35_X_MEMC_BASE_ADDR + 0x3000)
+#define MX35_EMI_CTL_BASE_ADDR                  (MX35_X_MEMC_BASE_ADDR + 0x4000)
+#define MX35_PCMCIA_CTL_BASE_ADDR               MX35_EMI_CTL_BASE_ADDR
+#define MX35_NFC_BASE_ADDR              0xbb000000
+#define MX35_PCMCIA_MEM_BASE_ADDR       0xbc000000
 /*
 * Interrupt numbers
 */
-#define MXC_INT_OWIRE           2
+#define MX35_INT_OWIRE          2
+#define MX35_INT_I2C3           3
+#define MX35_INT_I2C2           4
+#define MX35_INT_RTIC           6
 #define MX35_INT_MMC_SDHC1      7
-#define MXC_INT_MMC_SDHC2       8
+#define MX35_INT_MMC_SDHC2      8
-#define MXC_INT_MMC_SDHC3       9
+#define MX35_INT_MMC_SDHC3      9
+#define MX35_INT_I2C            10
 #define MX35_INT_SSI1           11
 #define MX35_INT_SSI2           12
-#define MXC_INT_GPU2D           16
+#define MX35_INT_CSPI2          13
-#define MXC_INT_ASRC            17
+#define MX35_INT_CSPI1          14
-#define MXC_INT_USBHS           35
+#define MX35_INT_ATA            15
-#define MXC_INT_USBOTG          37
+#define MX35_INT_GPU2D          16
-#define MXC_INT_ESAI            40
+#define MX35_INT_ASRC           17
-#define MXC_INT_CAN1            43
+#define MX35_INT_UART3          18
-#define MXC_INT_CAN2            44
+#define MX35_INT_IIM            19
-#define MXC_INT_MLB             46
+#define MX35_INT_RNGA           22
-#define MXC_INT_SPDIF           47
+#define MX35_INT_EVTMON         23
-#define MXC_INT_FEC             57
+#define MX35_INT_KPP            24
+#define MX35_INT_RTC            25
+#define MX35_INT_PWM            26
+#define MX35_INT_EPIT2          27
+#define MX35_INT_EPIT1          28
+#define MX35_INT_GPT            29
+#define MX35_INT_POWER_FAIL     30
+#define MX35_INT_UART2          32
+#define MX35_INT_NANDFC         33
+#define MX35_INT_SDMA           34
+#define MX35_INT_USBHS          35
+#define MX35_INT_USBOTG         37
+#define MX35_INT_MSHC1          39
+#define MX35_INT_ESAI           40
+#define MX35_INT_IPU_ERR        41
+#define MX35_INT_IPU_SYN        42
+#define MX35_INT_CAN1           43
+#define MX35_INT_CAN2           44
+#define MX35_INT_UART1          45
+#define MX35_INT_MLB            46
+#define MX35_INT_SPDIF          47
+#define MX35_INT_ECT            48
+#define MX35_INT_SCC_SCM        49
+#define MX35_INT_SCC_SMN        50
+#define MX35_INT_GPIO2          51
+#define MX35_INT_GPIO1          52
+#define MX35_INT_WDOG           55
+#define MX35_INT_GPIO3          56
+#define MX35_INT_FEC            57
+#define MX35_INT_EXT_POWER      58
+#define MX35_INT_EXT_TEMPER     59
+#define MX35_INT_EXT_SENSOR60   60
+#define MX35_INT_EXT_SENSOR61   61
+#define MX35_INT_EXT_WDOG       62
+#define MX35_INT_EXT_TV         63
+#define MX35_PROD_SIGNATURE             0x1     /* For MX31 */
+/* silicon revisions specific to i.MX31 */
+#define MX35_CHIP_REV_1_0               0x10
+#define MX35_CHIP_REV_1_1               0x11
+#define MX35_CHIP_REV_1_2               0x12
+#define MX35_CHIP_REV_1_3               0x13
+#define MX35_CHIP_REV_2_0               0x20
+#define MX35_CHIP_REV_2_1               0x21
+#define MX35_CHIP_REV_2_2               0x22
+#define MX35_CHIP_REV_2_3               0x23
+#define MX35_CHIP_REV_3_0               0x30
+#define MX35_CHIP_REV_3_1               0x31
+#define MX35_CHIP_REV_3_2               0x32
+#define MX35_SYSTEM_REV_MIN             MX35_CHIP_REV_1_0
+#define MX35_SYSTEM_REV_NUM             3
+/* these should go away */
+#define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR
+#define MXC_INT_OWIRE MX35_INT_OWIRE
+#define MXC_INT_MMC_SDHC2 MX35_INT_MMC_SDHC2
+#define MXC_INT_MMC_SDHC3 MX35_INT_MMC_SDHC3
+#define MXC_INT_GPU2D MX35_INT_GPU2D
+#define MXC_INT_ASRC MX35_INT_ASRC
+#define MXC_INT_USBHS MX35_INT_USBHS
+#define MXC_INT_USBOTG MX35_INT_USBOTG
+#define MXC_INT_ESAI MX35_INT_ESAI
+#define MXC_INT_CAN1 MX35_INT_CAN1
+#define MXC_INT_CAN2 MX35_INT_CAN2
+#define MXC_INT_MLB MX35_INT_MLB
+#define MXC_INT_SPDIF MX35_INT_SPDIF
+#define MXC_INT_FEC MX35_INT_FEC
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
index 009f4440276b..be69272407ad 100644
--- a/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -34,120 +34,117 @@
 *              C0000000        64M     PCMCIA/CF
 */
-#define CS0_BASE_ADDR           0xA0000000
-#define CS1_BASE_ADDR           0xA8000000
-#define CS2_BASE_ADDR           0xB0000000
-#define CS3_BASE_ADDR           0xB2000000
-#define CS4_BASE_ADDR           0xB4000000
-#define CS4_BASE_ADDR_VIRT      0xF4000000
-#define CS4_SIZE                SZ_32M
-#define CS5_BASE_ADDR           0xB6000000
-#define CS5_BASE_ADDR_VIRT      0xF6000000
-#define CS5_SIZE                SZ_32M
-#define PCMCIA_MEM_BASE_ADDR    0xBC000000
 /*
 * L2CC
 */
-#define L2CC_BASE_ADDR          0x30000000
+#define MX3x_L2CC_BASE_ADDR             0x30000000
-#define L2CC_SIZE               SZ_1M
+#define MX3x_L2CC_SIZE                  SZ_1M
 /*
 * AIPS 1
 */
-#define AIPS1_BASE_ADDR         0x43F00000
+#define MX3x_AIPS1_BASE_ADDR            0x43f00000
-#define AIPS1_BASE_ADDR_VIRT    0xFC000000
+#define MX3x_AIPS1_BASE_ADDR_VIRT       0xfc000000
-#define AIPS1_SIZE              SZ_1M
+#define MX3x_AIPS1_SIZE                 SZ_1M
+#define MX3x_MAX_BASE_ADDR                      (MX3x_AIPS1_BASE_ADDR + 0x04000)
-#define MAX_BASE_ADDR           (AIPS1_BASE_ADDR + 0x00004000)
+#define MX3x_EVTMON_BASE_ADDR                   (MX3x_AIPS1_BASE_ADDR + 0x08000)
-#define EVTMON_BASE_ADDR        (AIPS1_BASE_ADDR + 0x00008000)
+#define MX3x_CLKCTL_BASE_ADDR                   (MX3x_AIPS1_BASE_ADDR + 0x0c000)
-#define CLKCTL_BASE_ADDR        (AIPS1_BASE_ADDR + 0x0000C000)
+#define MX3x_ETB_SLOT4_BASE_ADDR                (MX3x_AIPS1_BASE_ADDR + 0x10000)
-#define ETB_SLOT4_BASE_ADDR     (AIPS1_BASE_ADDR + 0x00010000)
+#define MX3x_ETB_SLOT5_BASE_ADDR                (MX3x_AIPS1_BASE_ADDR + 0x14000)
-#define ETB_SLOT5_BASE_ADDR     (AIPS1_BASE_ADDR + 0x00014000)
+#define MX3x_ECT_CTIO_BASE_ADDR                 (MX3x_AIPS1_BASE_ADDR + 0x18000)
-#define ECT_CTIO_BASE_ADDR      (AIPS1_BASE_ADDR + 0x00018000)
+#define MX3x_I2C_BASE_ADDR                      (MX3x_AIPS1_BASE_ADDR + 0x80000)
-#define I2C_BASE_ADDR           (AIPS1_BASE_ADDR + 0x00080000)
+#define MX3x_I2C3_BASE_ADDR                     (MX3x_AIPS1_BASE_ADDR + 0x84000)
-#define I2C3_BASE_ADDR          (AIPS1_BASE_ADDR + 0x00084000)
+#define MX3x_UART1_BASE_ADDR                    (MX3x_AIPS1_BASE_ADDR + 0x90000)
-#define UART1_BASE_ADDR         (AIPS1_BASE_ADDR + 0x00090000)
+#define MX3x_UART2_BASE_ADDR                    (MX3x_AIPS1_BASE_ADDR + 0x94000)
-#define UART2_BASE_ADDR         (AIPS1_BASE_ADDR + 0x00094000)
+#define MX3x_I2C2_BASE_ADDR                     (MX3x_AIPS1_BASE_ADDR + 0x98000)
-#define I2C2_BASE_ADDR          (AIPS1_BASE_ADDR + 0x00098000)
+#define MX3x_OWIRE_BASE_ADDR                    (MX3x_AIPS1_BASE_ADDR + 0x9c000)
-#define OWIRE_BASE_ADDR         (AIPS1_BASE_ADDR + 0x0009C000)
+#define MX3x_SSI1_BASE_ADDR                     (MX3x_AIPS1_BASE_ADDR + 0xa0000)
-#define SSI1_BASE_ADDR          (AIPS1_BASE_ADDR + 0x000A0000)
+#define MX3x_CSPI1_BASE_ADDR                    (MX3x_AIPS1_BASE_ADDR + 0xa4000)
-#define CSPI1_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000A4000)
+#define MX3x_KPP_BASE_ADDR                      (MX3x_AIPS1_BASE_ADDR + 0xa8000)
-#define KPP_BASE_ADDR           (AIPS1_BASE_ADDR + 0x000A8000)
+#define MX3x_IOMUXC_BASE_ADDR                   (MX3x_AIPS1_BASE_ADDR + 0xac000)
-#define IOMUXC_BASE_ADDR        (AIPS1_BASE_ADDR + 0x000AC000)
+#define MX3x_ECT_IP1_BASE_ADDR                  (MX3x_AIPS1_BASE_ADDR + 0xb8000)
-#define ECT_IP1_BASE_ADDR       (AIPS1_BASE_ADDR + 0x000B8000)
+#define MX3x_ECT_IP2_BASE_ADDR                  (MX3x_AIPS1_BASE_ADDR + 0xbc000)
-#define ECT_IP2_BASE_ADDR       (AIPS1_BASE_ADDR + 0x000BC000)
 /*
 * SPBA global module enabled #0
 */
-#define SPBA0_BASE_ADDR         0x50000000
+#define MX3x_SPBA0_BASE_ADDR            0x50000000
-#define SPBA0_BASE_ADDR_VIRT    0xFC100000
+#define MX3x_SPBA0_BASE_ADDR_VIRT       0xfc100000
-#define SPBA0_SIZE              SZ_1M
+#define MX3x_SPBA0_SIZE                 SZ_1M
+#define MX3x_UART3_BASE_ADDR                    (MX3x_SPBA0_BASE_ADDR + 0x0c000)
-#define UART3_BASE_ADDR         (SPBA0_BASE_ADDR + 0x0000C000)
+#define MX3x_CSPI2_BASE_ADDR                    (MX3x_SPBA0_BASE_ADDR + 0x10000)
-#define CSPI2_BASE_ADDR         (SPBA0_BASE_ADDR + 0x00010000)
+#define MX3x_SSI2_BASE_ADDR                     (MX3x_SPBA0_BASE_ADDR + 0x14000)
-#define SSI2_BASE_ADDR          (SPBA0_BASE_ADDR + 0x00014000)
+#define MX3x_ATA_DMA_BASE_ADDR                  (MX3x_SPBA0_BASE_ADDR + 0x20000)
-#define ATA_DMA_BASE_ADDR       (SPBA0_BASE_ADDR + 0x00020000)
+#define MX3x_MSHC1_BASE_ADDR                    (MX3x_SPBA0_BASE_ADDR + 0x24000)
-#define MSHC1_BASE_ADDR         (SPBA0_BASE_ADDR + 0x00024000)
+#define MX3x_SPBA_CTRL_BASE_ADDR                (MX3x_SPBA0_BASE_ADDR + 0x3c000)
-#define SPBA_CTRL_BASE_ADDR     (SPBA0_BASE_ADDR + 0x0003C000)
 /*
 * AIPS 2
 */
-#define AIPS2_BASE_ADDR         0x53F00000
+#define MX3x_AIPS2_BASE_ADDR            0x53f00000
-#define AIPS2_BASE_ADDR_VIRT    0xFC200000
+#define MX3x_AIPS2_BASE_ADDR_VIRT       0xfc200000
-#define AIPS2_SIZE              SZ_1M
+#define MX3x_AIPS2_SIZE                 SZ_1M
-#define CCM_BASE_ADDR           (AIPS2_BASE_ADDR + 0x00080000)
+#define MX3x_CCM_BASE_ADDR                      (MX3x_AIPS2_BASE_ADDR + 0x80000)
-#define GPT1_BASE_ADDR          (AIPS2_BASE_ADDR + 0x00090000)
+#define MX3x_GPT1_BASE_ADDR                     (MX3x_AIPS2_BASE_ADDR + 0x90000)
-#define EPIT1_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00094000)
+#define MX3x_EPIT1_BASE_ADDR                    (MX3x_AIPS2_BASE_ADDR + 0x94000)
-#define EPIT2_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00098000)
+#define MX3x_EPIT2_BASE_ADDR                    (MX3x_AIPS2_BASE_ADDR + 0x98000)
-#define GPIO3_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000A4000)
+#define MX3x_GPIO3_BASE_ADDR                    (MX3x_AIPS2_BASE_ADDR + 0xa4000)
-#define SCC_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000AC000)
+#define MX3x_SCC_BASE_ADDR                      (MX3x_AIPS2_BASE_ADDR + 0xac000)
-#define RNGA_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000B0000)
+#define MX3x_RNGA_BASE_ADDR                     (MX3x_AIPS2_BASE_ADDR + 0xb0000)
-#define IPU_CTRL_BASE_ADDR      (AIPS2_BASE_ADDR + 0x000C0000)
+#define MX3x_IPU_CTRL_BASE_ADDR                 (MX3x_AIPS2_BASE_ADDR + 0xc0000)
-#define AUDMUX_BASE_ADDR        (AIPS2_BASE_ADDR + 0x000C4000)
+#define MX3x_AUDMUX_BASE_ADDR                   (MX3x_AIPS2_BASE_ADDR + 0xc4000)
-#define GPIO1_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000CC000)
+#define MX3x_GPIO1_BASE_ADDR                    (MX3x_AIPS2_BASE_ADDR + 0xcc000)
-#define GPIO2_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000D0000)
+#define MX3x_GPIO2_BASE_ADDR                    (MX3x_AIPS2_BASE_ADDR + 0xd0000)
-#define SDMA_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000D4000)
+#define MX3x_SDMA_BASE_ADDR                     (MX3x_AIPS2_BASE_ADDR + 0xd4000)
-#define RTC_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000D8000)
+#define MX3x_RTC_BASE_ADDR                      (MX3x_AIPS2_BASE_ADDR + 0xd8000)
-#define WDOG_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000DC000)
+#define MX3x_WDOG_BASE_ADDR                     (MX3x_AIPS2_BASE_ADDR + 0xdc000)
-#define PWM_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000E0000)
+#define MX3x_PWM_BASE_ADDR                      (MX3x_AIPS2_BASE_ADDR + 0xe0000)
-#define RTIC_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000EC000)
+#define MX3x_RTIC_BASE_ADDR                     (MX3x_AIPS2_BASE_ADDR + 0xec000)
 /*
 * ROMP and AVIC
 */
-#define ROMP_BASE_ADDR          0x60000000
+#define MX3x_ROMP_BASE_ADDR             0x60000000
-#define ROMP_BASE_ADDR_VIRT     0xFC500000
+#define MX3x_ROMP_BASE_ADDR_VIRT        0xfc500000
-#define ROMP_SIZE               SZ_1M
+#define MX3x_ROMP_SIZE                  SZ_1M
-#define AVIC_BASE_ADDR          0x68000000
+#define MX3x_AVIC_BASE_ADDR             0x68000000
-#define AVIC_BASE_ADDR_VIRT     0xFC400000
+#define MX3x_AVIC_BASE_ADDR_VIRT        0xfc400000
-#define AVIC_SIZE               SZ_1M
+#define MX3x_AVIC_SIZE                  SZ_1M
 /*
- * NAND, SDRAM, WEIM, M3IF, EMI controllers
+ * Memory regions and CS
 */
-#define X_MEMC_BASE_ADDR        0xB8000000
+#define MX3x_IPU_MEM_BASE_ADDR          0x70000000
-#define X_MEMC_BASE_ADDR_VIRT   0xFC320000
+#define MX3x_CSD0_BASE_ADDR             0x80000000
-#define X_MEMC_SIZE             SZ_64K
+#define MX3x_CSD1_BASE_ADDR             0x90000000
-#define ESDCTL_BASE_ADDR        (X_MEMC_BASE_ADDR + 0x1000)
+#define MX3x_CS0_BASE_ADDR              0xa0000000
-#define WEIM_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x2000)
+#define MX3x_CS1_BASE_ADDR              0xa8000000
-#define M3IF_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x3000)
+#define MX3x_CS2_BASE_ADDR              0xb0000000
-#define EMI_CTL_BASE_ADDR       (X_MEMC_BASE_ADDR + 0x4000)
+#define MX3x_CS3_BASE_ADDR              0xb2000000
-#define PCMCIA_CTL_BASE_ADDR    EMI_CTL_BASE_ADDR
+#define MX3x_CS4_BASE_ADDR              0xb4000000
+#define MX3x_CS4_BASE_ADDR_VIRT         0xf4000000
+#define MX3x_CS4_SIZE                   SZ_32M
+#define MX3x_CS5_BASE_ADDR              0xb6000000
+#define MX3x_CS5_BASE_ADDR_VIRT         0xf6000000
+#define MX3x_CS5_SIZE                   SZ_32M
 /*
- * Memory regions and CS
+ * NAND, SDRAM, WEIM, M3IF, EMI controllers
 */
-#define IPU_MEM_BASE_ADDR       0x70000000
+#define MX3x_X_MEMC_BASE_ADDR           0xb8000000
-#define CSD0_BASE_ADDR          0x80000000
+#define MX3x_X_MEMC_BASE_ADDR_VIRT      0xfc320000
-#define CSD1_BASE_ADDR          0x90000000
+#define MX3x_X_MEMC_SIZE                SZ_64K
+#define MX3x_ESDCTL_BASE_ADDR                   (MX3x_X_MEMC_BASE_ADDR + 0x1000)
+#define MX3x_WEIM_BASE_ADDR                     (MX3x_X_MEMC_BASE_ADDR + 0x2000)
+#define MX3x_M3IF_BASE_ADDR                     (MX3x_X_MEMC_BASE_ADDR + 0x3000)
+#define MX3x_EMI_CTL_BASE_ADDR                  (MX3x_X_MEMC_BASE_ADDR + 0x4000)
+#define MX3x_PCMCIA_CTL_BASE_ADDR               MX3x_EMI_CTL_BASE_ADDR
+#define MX3x_PCMCIA_MEM_BASE_ADDR       0xbc000000
 /*!
 * This macro defines the physical to virtual address mapping for all the
@@ -202,74 +199,207 @@
 /*
 * Interrupt numbers
 */
-#define MXC_INT_I2C3            3
+#define MX3x_INT_I2C3           3
-#define MXC_INT_I2C2            4
+#define MX3x_INT_I2C2           4
-#define MXC_INT_RTIC            6
+#define MX3x_INT_RTIC           6
-#define MXC_INT_I2C             10
+#define MX3x_INT_I2C            10
-#define MXC_INT_CSPI2           13
+#define MX3x_INT_CSPI2          13
-#define MXC_INT_CSPI1           14
+#define MX3x_INT_CSPI1          14
-#define MXC_INT_ATA             15
+#define MX3x_INT_ATA            15
-#define MXC_INT_UART3           18
+#define MX3x_INT_UART3          18
-#define MXC_INT_IIM             19
+#define MX3x_INT_IIM            19
-#define MXC_INT_RNGA            22
+#define MX3x_INT_RNGA           22
-#define MXC_INT_EVTMON          23
+#define MX3x_INT_EVTMON         23
-#define MXC_INT_KPP             24
+#define MX3x_INT_KPP            24
-#define MXC_INT_RTC             25
+#define MX3x_INT_RTC            25
-#define MXC_INT_PWM             26
+#define MX3x_INT_PWM            26
-#define MXC_INT_EPIT2           27
+#define MX3x_INT_EPIT2          27
-#define MXC_INT_EPIT1           28
+#define MX3x_INT_EPIT1          28
-#define MXC_INT_GPT             29
+#define MX3x_INT_GPT            29
-#define MXC_INT_POWER_FAIL      30
+#define MX3x_INT_POWER_FAIL     30
-#define MXC_INT_UART2           32
+#define MX3x_INT_UART2          32
-#define MXC_INT_NANDFC          33
+#define MX3x_INT_NANDFC         33
-#define MXC_INT_SDMA            34
+#define MX3x_INT_SDMA           34
-#define MXC_INT_MSHC1           39
+#define MX3x_INT_MSHC1          39
-#define MXC_INT_IPU_ERR         41
+#define MX3x_INT_IPU_ERR        41
-#define MXC_INT_IPU_SYN         42
+#define MX3x_INT_IPU_SYN        42
-#define MXC_INT_UART1           45
+#define MX3x_INT_UART1          45
-#define MXC_INT_ECT             48
+#define MX3x_INT_ECT            48
-#define MXC_INT_SCC_SCM         49
+#define MX3x_INT_SCC_SCM        49
-#define MXC_INT_SCC_SMN         50
+#define MX3x_INT_SCC_SMN        50
-#define MXC_INT_GPIO2           51
+#define MX3x_INT_GPIO2          51
-#define MXC_INT_GPIO1           52
+#define MX3x_INT_GPIO1          52
-#define MXC_INT_WDOG            55
+#define MX3x_INT_WDOG           55
-#define MXC_INT_GPIO3           56
+#define MX3x_INT_GPIO3          56
-#define MXC_INT_EXT_POWER       58
+#define MX3x_INT_EXT_POWER      58
-#define MXC_INT_EXT_TEMPER      59
+#define MX3x_INT_EXT_TEMPER     59
-#define MXC_INT_EXT_SENSOR60    60
+#define MX3x_INT_EXT_SENSOR60   60
-#define MXC_INT_EXT_SENSOR61    61
+#define MX3x_INT_EXT_SENSOR61   61
-#define MXC_INT_EXT_WDOG        62
+#define MX3x_INT_EXT_WDOG       62
-#define MXC_INT_EXT_TV          63
+#define MX3x_INT_EXT_TV         63
-#define PROD_SIGNATURE          0x1     /* For MX31 */
+#define MX3x_PROD_SIGNATURE             0x1     /* For MX31 */
 /* silicon revisions specific to i.MX31 */
-#define CHIP_REV_1_0            0x10
+#define MX3x_CHIP_REV_1_0               0x10
-#define CHIP_REV_1_1            0x11
+#define MX3x_CHIP_REV_1_1               0x11
-#define CHIP_REV_1_2            0x12
+#define MX3x_CHIP_REV_1_2               0x12
-#define CHIP_REV_1_3            0x13
+#define MX3x_CHIP_REV_1_3               0x13
-#define CHIP_REV_2_0            0x20
+#define MX3x_CHIP_REV_2_0               0x20
-#define CHIP_REV_2_1            0x21
+#define MX3x_CHIP_REV_2_1               0x21
-#define CHIP_REV_2_2            0x22
+#define MX3x_CHIP_REV_2_2               0x22
-#define CHIP_REV_2_3            0x23
+#define MX3x_CHIP_REV_2_3               0x23
-#define CHIP_REV_3_0            0x30
+#define MX3x_CHIP_REV_3_0               0x30
-#define CHIP_REV_3_1            0x31
+#define MX3x_CHIP_REV_3_1               0x31
-#define CHIP_REV_3_2            0x32
+#define MX3x_CHIP_REV_3_2               0x32
-#define SYSTEM_REV_MIN          CHIP_REV_1_0
+#define MX3x_SYSTEM_REV_MIN             MX3x_CHIP_REV_1_0
-#define SYSTEM_REV_NUM          3
+#define MX3x_SYSTEM_REV_NUM             3
 /* Mandatory defines used globally */
 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
-extern unsigned int system_rev;
+extern unsigned int mx31_cpu_rev;
+extern void mx31_read_cpu_rev(void);
 static inline int mx31_revision(void)
 {
-        return system_rev;
+        return mx31_cpu_rev;
 }
 #endif
-#endif /*  __ASM_ARCH_MXC_MX31_H__ */
+/* these should go away */
+#define L2CC_BASE_ADDR MX3x_L2CC_BASE_ADDR
+#define L2CC_SIZE MX3x_L2CC_SIZE
+#define AIPS1_BASE_ADDR MX3x_AIPS1_BASE_ADDR
+#define AIPS1_BASE_ADDR_VIRT MX3x_AIPS1_BASE_ADDR_VIRT
+#define AIPS1_SIZE MX3x_AIPS1_SIZE
+#define MAX_BASE_ADDR MX3x_MAX_BASE_ADDR
+#define EVTMON_BASE_ADDR MX3x_EVTMON_BASE_ADDR
+#define CLKCTL_BASE_ADDR MX3x_CLKCTL_BASE_ADDR
+#define ETB_SLOT4_BASE_ADDR MX3x_ETB_SLOT4_BASE_ADDR
+#define ETB_SLOT5_BASE_ADDR MX3x_ETB_SLOT5_BASE_ADDR
+#define ECT_CTIO_BASE_ADDR MX3x_ECT_CTIO_BASE_ADDR
+#define I2C_BASE_ADDR MX3x_I2C_BASE_ADDR
+#define I2C3_BASE_ADDR MX3x_I2C3_BASE_ADDR
+#define UART1_BASE_ADDR MX3x_UART1_BASE_ADDR
+#define UART2_BASE_ADDR MX3x_UART2_BASE_ADDR
+#define I2C2_BASE_ADDR MX3x_I2C2_BASE_ADDR
+#define OWIRE_BASE_ADDR MX3x_OWIRE_BASE_ADDR
+#define SSI1_BASE_ADDR MX3x_SSI1_BASE_ADDR
+#define CSPI1_BASE_ADDR MX3x_CSPI1_BASE_ADDR
+#define KPP_BASE_ADDR MX3x_KPP_BASE_ADDR
+#define IOMUXC_BASE_ADDR MX3x_IOMUXC_BASE_ADDR
+#define ECT_IP1_BASE_ADDR MX3x_ECT_IP1_BASE_ADDR
+#define ECT_IP2_BASE_ADDR MX3x_ECT_IP2_BASE_ADDR
+#define SPBA0_BASE_ADDR MX3x_SPBA0_BASE_ADDR
+#define SPBA0_BASE_ADDR_VIRT MX3x_SPBA0_BASE_ADDR_VIRT
+#define SPBA0_SIZE MX3x_SPBA0_SIZE
+#define UART3_BASE_ADDR MX3x_UART3_BASE_ADDR
+#define CSPI2_BASE_ADDR MX3x_CSPI2_BASE_ADDR
+#define SSI2_BASE_ADDR MX3x_SSI2_BASE_ADDR
+#define ATA_DMA_BASE_ADDR MX3x_ATA_DMA_BASE_ADDR
+#define MSHC1_BASE_ADDR MX3x_MSHC1_BASE_ADDR
+#define SPBA_CTRL_BASE_ADDR MX3x_SPBA_CTRL_BASE_ADDR
+#define AIPS2_BASE_ADDR MX3x_AIPS2_BASE_ADDR
+#define AIPS2_BASE_ADDR_VIRT MX3x_AIPS2_BASE_ADDR_VIRT
+#define AIPS2_SIZE MX3x_AIPS2_SIZE
+#define CCM_BASE_ADDR MX3x_CCM_BASE_ADDR
+#define GPT1_BASE_ADDR MX3x_GPT1_BASE_ADDR
+#define EPIT1_BASE_ADDR MX3x_EPIT1_BASE_ADDR
+#define EPIT2_BASE_ADDR MX3x_EPIT2_BASE_ADDR
+#define GPIO3_BASE_ADDR MX3x_GPIO3_BASE_ADDR
+#define SCC_BASE_ADDR MX3x_SCC_BASE_ADDR
+#define RNGA_BASE_ADDR MX3x_RNGA_BASE_ADDR
+#define IPU_CTRL_BASE_ADDR MX3x_IPU_CTRL_BASE_ADDR
+#define AUDMUX_BASE_ADDR MX3x_AUDMUX_BASE_ADDR
+#define GPIO1_BASE_ADDR MX3x_GPIO1_BASE_ADDR
+#define GPIO2_BASE_ADDR MX3x_GPIO2_BASE_ADDR
+#define SDMA_BASE_ADDR MX3x_SDMA_BASE_ADDR
+#define RTC_BASE_ADDR MX3x_RTC_BASE_ADDR
+#define WDOG_BASE_ADDR MX3x_WDOG_BASE_ADDR
+#define PWM_BASE_ADDR MX3x_PWM_BASE_ADDR
+#define RTIC_BASE_ADDR MX3x_RTIC_BASE_ADDR
+#define ROMP_BASE_ADDR MX3x_ROMP_BASE_ADDR
+#define ROMP_BASE_ADDR_VIRT MX3x_ROMP_BASE_ADDR_VIRT
+#define ROMP_SIZE MX3x_ROMP_SIZE
+#define AVIC_BASE_ADDR MX3x_AVIC_BASE_ADDR
+#define AVIC_BASE_ADDR_VIRT MX3x_AVIC_BASE_ADDR_VIRT
+#define AVIC_SIZE MX3x_AVIC_SIZE
+#define IPU_MEM_BASE_ADDR MX3x_IPU_MEM_BASE_ADDR
+#define CSD0_BASE_ADDR MX3x_CSD0_BASE_ADDR
+#define CSD1_BASE_ADDR MX3x_CSD1_BASE_ADDR
+#define CS0_BASE_ADDR MX3x_CS0_BASE_ADDR
+#define CS1_BASE_ADDR MX3x_CS1_BASE_ADDR
+#define CS2_BASE_ADDR MX3x_CS2_BASE_ADDR
+#define CS3_BASE_ADDR MX3x_CS3_BASE_ADDR
+#define CS4_BASE_ADDR MX3x_CS4_BASE_ADDR
+#define CS4_BASE_ADDR_VIRT MX3x_CS4_BASE_ADDR_VIRT
+#define CS4_SIZE MX3x_CS4_SIZE
+#define CS5_BASE_ADDR MX3x_CS5_BASE_ADDR
+#define CS5_BASE_ADDR_VIRT MX3x_CS5_BASE_ADDR_VIRT
+#define CS5_SIZE MX3x_CS5_SIZE
+#define X_MEMC_BASE_ADDR MX3x_X_MEMC_BASE_ADDR
+#define X_MEMC_BASE_ADDR_VIRT MX3x_X_MEMC_BASE_ADDR_VIRT
+#define X_MEMC_SIZE MX3x_X_MEMC_SIZE
+#define ESDCTL_BASE_ADDR MX3x_ESDCTL_BASE_ADDR
+#define WEIM_BASE_ADDR MX3x_WEIM_BASE_ADDR
+#define M3IF_BASE_ADDR MX3x_M3IF_BASE_ADDR
+#define EMI_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR
+#define PCMCIA_CTL_BASE_ADDR MX3x_PCMCIA_CTL_BASE_ADDR
+#define PCMCIA_MEM_BASE_ADDR MX3x_PCMCIA_MEM_BASE_ADDR
+#define MXC_INT_I2C3 MX3x_INT_I2C3
+#define MXC_INT_I2C2 MX3x_INT_I2C2
+#define MXC_INT_RTIC MX3x_INT_RTIC
+#define MXC_INT_I2C MX3x_INT_I2C
+#define MXC_INT_CSPI2 MX3x_INT_CSPI2
+#define MXC_INT_CSPI1 MX3x_INT_CSPI1
+#define MXC_INT_ATA MX3x_INT_ATA
+#define MXC_INT_UART3 MX3x_INT_UART3
+#define MXC_INT_IIM MX3x_INT_IIM
+#define MXC_INT_RNGA MX3x_INT_RNGA
+#define MXC_INT_EVTMON MX3x_INT_EVTMON
+#define MXC_INT_KPP MX3x_INT_KPP
+#define MXC_INT_RTC MX3x_INT_RTC
+#define MXC_INT_PWM MX3x_INT_PWM
+#define MXC_INT_EPIT2 MX3x_INT_EPIT2
+#define MXC_INT_EPIT1 MX3x_INT_EPIT1
+#define MXC_INT_GPT MX3x_INT_GPT
+#define MXC_INT_POWER_FAIL MX3x_INT_POWER_FAIL
+#define MXC_INT_UART2 MX3x_INT_UART2
+#define MXC_INT_NANDFC MX3x_INT_NANDFC
+#define MXC_INT_SDMA MX3x_INT_SDMA
+#define MXC_INT_MSHC1 MX3x_INT_MSHC1
+#define MXC_INT_IPU_ERR MX3x_INT_IPU_ERR
+#define MXC_INT_IPU_SYN MX3x_INT_IPU_SYN
+#define MXC_INT_UART1 MX3x_INT_UART1
+#define MXC_INT_ECT MX3x_INT_ECT
+#define MXC_INT_SCC_SCM MX3x_INT_SCC_SCM
+#define MXC_INT_SCC_SMN MX3x_INT_SCC_SMN
+#define MXC_INT_GPIO2 MX3x_INT_GPIO2
+#define MXC_INT_GPIO1 MX3x_INT_GPIO1
+#define MXC_INT_WDOG MX3x_INT_WDOG
+#define MXC_INT_GPIO3 MX3x_INT_GPIO3
+#define MXC_INT_EXT_POWER MX3x_INT_EXT_POWER
+#define MXC_INT_EXT_TEMPER MX3x_INT_EXT_TEMPER
+#define MXC_INT_EXT_SENSOR60 MX3x_INT_EXT_SENSOR60
+#define MXC_INT_EXT_SENSOR61 MX3x_INT_EXT_SENSOR61
+#define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG
+#define MXC_INT_EXT_TV MX3x_INT_EXT_TV
+#define PROD_SIGNATURE MX3x_PROD_SIGNATURE
+#define CHIP_REV_1_0 MX3x_CHIP_REV_1_0
+#define CHIP_REV_1_1 MX3x_CHIP_REV_1_1
+#define CHIP_REV_1_2 MX3x_CHIP_REV_1_2
+#define CHIP_REV_1_3 MX3x_CHIP_REV_1_3
+#define CHIP_REV_2_0 MX3x_CHIP_REV_2_0
+#define CHIP_REV_2_1 MX3x_CHIP_REV_2_1
+#define CHIP_REV_2_2 MX3x_CHIP_REV_2_2
+#define CHIP_REV_2_3 MX3x_CHIP_REV_2_3
+#define CHIP_REV_3_0 MX3x_CHIP_REV_3_0
+#define CHIP_REV_3_1 MX3x_CHIP_REV_3_1
+#define CHIP_REV_3_2 MX3x_CHIP_REV_3_2
+#define SYSTEM_REV_MIN MX3x_SYSTEM_REV_MIN
+#define SYSTEM_REV_NUM MX3x_SYSTEM_REV_NUM
+#endif /*  __ASM_ARCH_MXC_MX31_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/ulpi.h b/arch/arm/plat-mxc/include/mach/ulpi.h
new file mode 100644
index 000000000000..96b6ab4c40c3
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/ulpi.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_ULPI_H
+#define __MACH_ULPI_H
+extern struct otg_io_access_ops mxc_ulpi_access_ops;
+#endif /* __MACH_ULPI_H */
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index 082a3908256b..4d5d395ad63b 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -83,6 +83,8 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
        case MACH_TYPE_MX27ADS:
        case MACH_TYPE_PCM038:
        case MACH_TYPE_MX21ADS:
+        case MACH_TYPE_PCA100:
+        case MACH_TYPE_MXT_TD60:
                uart_base = MX2X_UART1_BASE_ADDR;
                break;
        case MACH_TYPE_MX31LITE:
@@ -94,6 +96,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
        case MACH_TYPE_MX31ADS:
        case MACH_TYPE_MX35_3DS:
        case MACH_TYPE_PCM043:
+        case MACH_TYPE_LILLY1131:
                uart_base = MX3X_UART1_BASE_ADDR;
                break;
        case MACH_TYPE_MAGX_ZN5:
diff --git a/arch/arm/plat-mxc/iomux-v3.c b/arch/arm/plat-mxc/iomux-v3.c
index 851ca99bf1b1..b318c6a222d5 100644
--- a/arch/arm/plat-mxc/iomux-v3.c
+++ b/arch/arm/plat-mxc/iomux-v3.c
@@ -31,19 +31,11 @@
 static void __iomem *base;
-static unsigned long iomux_v3_pad_alloc_map[0x200 / BITS_PER_LONG];
 /*
- * setups a single pin:
+ * setups a single pad in the iomuxer
- *      - reserves the pin so that it is not claimed by another driver
- *      - setups the iomux according to the configuration
 */
 int mxc_iomux_v3_setup_pad(struct pad_desc *pad)
 {
-        unsigned int pad_ofs = pad->pad_ctrl_ofs;
-        if (test_and_set_bit(pad_ofs >> 2, iomux_v3_pad_alloc_map))
-                return -EBUSY;
        if (pad->mux_ctrl_ofs)
                __raw_writel(pad->mux_mode, base + pad->mux_ctrl_ofs);
@@ -66,37 +58,13 @@ int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count)
        for (i = 0; i < count; i++) {
                ret = mxc_iomux_v3_setup_pad(p);
                if (ret)
-                        goto setup_error;
+                        return ret;
                p++;
        }
        return 0;
-setup_error:
-        mxc_iomux_v3_release_multiple_pads(pad_list, i);
-        return ret;
 }
 EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads);
-void mxc_iomux_v3_release_pad(struct pad_desc *pad)
-{
-        unsigned int pad_ofs = pad->pad_ctrl_ofs;
-        clear_bit(pad_ofs >> 2, iomux_v3_pad_alloc_map);
-}
-EXPORT_SYMBOL(mxc_iomux_v3_release_pad);
-void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count)
-{
-        struct pad_desc *p = pad_list;
-        int i;
-        for (i = 0; i < count; i++) {
-                mxc_iomux_v3_release_pad(p);
-                p++;
-        }
-}
-EXPORT_SYMBOL(mxc_iomux_v3_release_multiple_pads);
 void mxc_iomux_v3_init(void __iomem *iomux_v3_base)
 {
        base = iomux_v3_base;
diff --git a/arch/arm/plat-mxc/ulpi.c b/arch/arm/plat-mxc/ulpi.c
new file mode 100644
index 000000000000..582c6dfaba4a
--- /dev/null
+++ b/arch/arm/plat-mxc/ulpi.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
+ * Copyright 2009 Daniel Mack <daniel@caiaq.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/usb/otg.h>
+#include <mach/ulpi.h>
+/* ULPIVIEW register bits */
+#define ULPIVW_WU               (1 << 31)       /* Wakeup */
+#define ULPIVW_RUN              (1 << 30)       /* read/write run */
+#define ULPIVW_WRITE            (1 << 29)       /* 0 = read  1 = write */
+#define ULPIVW_SS               (1 << 27)       /* SyncState */
+#define ULPIVW_PORT_MASK        0x07    /* Port field */
+#define ULPIVW_PORT_SHIFT       24
+#define ULPIVW_ADDR_MASK        0xff    /* data address field */
+#define ULPIVW_ADDR_SHIFT       16
+#define ULPIVW_RDATA_MASK       0xff    /* read data field */
+#define ULPIVW_RDATA_SHIFT      8
+#define ULPIVW_WDATA_MASK       0xff    /* write data field */
+#define ULPIVW_WDATA_SHIFT      0
+static int ulpi_poll(void __iomem *view, u32 bit)
+{
+        int timeout = 10000;
+        while (timeout--) {
+                u32 data = __raw_readl(view);
+                if (!(data & bit))
+                        return 0;
+                cpu_relax();
+        };
+        printk(KERN_WARNING "timeout polling for ULPI device\n");
+        return -ETIMEDOUT;
+}
+static int ulpi_read(struct otg_transceiver *otg, u32 reg)
+{
+        int ret;
+        void __iomem *view = otg->io_priv;
+        /* make sure interface is running */
+        if (!(__raw_readl(view) & ULPIVW_SS)) {
+                __raw_writel(ULPIVW_WU, view);
+                /* wait for wakeup */
+                ret = ulpi_poll(view, ULPIVW_WU);
+                if (ret)
+                        return ret;
+        }
+        /* read the register */
+        __raw_writel((ULPIVW_RUN | (reg << ULPIVW_ADDR_SHIFT)), view);
+        /* wait for completion */
+        ret = ulpi_poll(view, ULPIVW_RUN);
+        if (ret)
+                return ret;
+        return (__raw_readl(view) >> ULPIVW_RDATA_SHIFT) & ULPIVW_RDATA_MASK;
+}
+static int ulpi_write(struct otg_transceiver *otg, u32 val, u32 reg)
+{
+        int ret;
+        void __iomem *view = otg->io_priv;
+        /* make sure the interface is running */
+        if (!(__raw_readl(view) & ULPIVW_SS)) {
+                __raw_writel(ULPIVW_WU, view);
+                /* wait for wakeup */
+                ret = ulpi_poll(view, ULPIVW_WU);
+                if (ret)
+                        return ret;
+        }
+        __raw_writel((ULPIVW_RUN | ULPIVW_WRITE |
+                      (reg << ULPIVW_ADDR_SHIFT) |
+                      ((val & ULPIVW_WDATA_MASK) << ULPIVW_WDATA_SHIFT)), view);
+        /* wait for completion */
+        return ulpi_poll(view, ULPIVW_RUN);
+}
+struct otg_io_access_ops mxc_ulpi_access_ops = {
+        .read   = ulpi_read,
+        .write  = ulpi_write,
+};
+EXPORT_SYMBOL_GPL(mxc_ulpi_access_ops);
diff --git a/arch/arm/plat-nomadik/Kconfig b/arch/arm/plat-nomadik/Kconfig
new file mode 100644
index 000000000000..159daf583f85
--- /dev/null
+++ b/arch/arm/plat-nomadik/Kconfig
@@ -0,0 +1,22 @@
+# We keep common IP's here for Nomadik and other similar
+# familiy of processors from ST-Ericsson. At the moment we have
+# just MTU, others to follow soon.
+config PLAT_NOMADIK
+        bool
+        depends on ARCH_NOMADIK || ARCH_U8500
+        default y
+        help
+          Common platform code for Nomadik and other ST-Ericsson
+          platforms.
+if PLAT_NOMADIK
+config HAS_MTU
+        bool
+        help
+          Support for Multi Timer Unit. MTU provides access
+          to multiple interrupt generating programmable
+          32-bit free running decrementing counters.
+endif
diff --git a/arch/arm/plat-nomadik/Makefile b/arch/arm/plat-nomadik/Makefile
new file mode 100644
index 000000000000..37c7cdd0f8f0
--- /dev/null
+++ b/arch/arm/plat-nomadik/Makefile
@@ -0,0 +1,5 @@
+# arch/arm/plat-nomadik/Makefile
+# Copyright 2009 ST-Ericsson
+# Licensed under GPLv2
+obj-$(CONFIG_HAS_MTU)   += timer.o
diff --git a/arch/arm/mach-nomadik/include/mach/mtu.h b/arch/arm/plat-nomadik/include/plat/mtu.h
index 76da7f085330..42c907258b14 100644
--- a/arch/arm/mach-nomadik/include/mach/mtu.h
+++ b/arch/arm/plat-nomadik/include/plat/mtu.h
@@ -1,5 +1,8 @@
-#ifndef __ASM_ARCH_MTU_H
+#ifndef __PLAT_MTU_H
-#define __ASM_ARCH_MTU_H
+#define __PLAT_MTU_H
+/* should be set by the platform code */
+extern void __iomem *mtu_base;
 /*
 * The MTU device hosts four different counters, with 4 set of
@@ -41,5 +44,5 @@
 #define MTU_PCELL2      0xff8
 #define MTU_PCELL3      0xffC
-#endif /* __ASM_ARCH_MTU_H */
+#endif /* __PLAT_MTU_H */
diff --git a/arch/arm/mach-nomadik/timer.c b/arch/arm/plat-nomadik/timer.c
index d1738e7061d4..62f18ad43a28 100644
--- a/arch/arm/mach-nomadik/timer.c
+++ b/arch/arm/plat-nomadik/timer.c
@@ -15,19 +15,14 @@
 #include <linux/clockchips.h>
 #include <linux/jiffies.h>
 #include <asm/mach/time.h>
-#include <mach/mtu.h>
-#define TIMER_CTRL      0x80    /* No divisor */
+#include <plat/mtu.h>
-#define TIMER_PERIODIC  0x40
-#define TIMER_SZ32BIT   0x02
-/* Initial value for SRC control register: all timers use MXTAL/8 source */
-#define SRC_CR_INIT_MASK        0x00007fff
-#define SRC_CR_INIT_VAL         0x2aaa8000
 static u32      nmdk_count;             /* accumulated count */
 static u32      nmdk_cycle;             /* write-once */
-static __iomem void *mtu_base;
+/* setup by the platform code */
+void __iomem *mtu_base;
 /*
 * clocksource: the MTU device is a decrementing counters, so we negate
@@ -93,7 +88,7 @@ static struct clock_event_device nmdk_clkevt = {
 static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
 {
        /* ack: "interrupt clear register" */
-        writel( 1 << 0, mtu_base + MTU_ICR);
+        writel(1 << 0, mtu_base + MTU_ICR);
        /* we can't count lost ticks, unfortunately */
        nmdk_count += nmdk_cycle;
@@ -125,24 +120,14 @@ static void nmdk_timer_reset(void)
        writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0));
 }
-static void __init nmdk_timer_init(void)
+void __init nmdk_timer_init(void)
 {
-        u32 src_cr;
        unsigned long rate;
        int bits;
        rate = CLOCK_TICK_RATE; /* 2.4MHz */
        nmdk_cycle = (rate + HZ/2) / HZ;
-        /* Configure timer sources in "system reset controller" ctrl reg */
-        src_cr = readl(io_p2v(NOMADIK_SRC_BASE));
-        src_cr &= SRC_CR_INIT_MASK;
-        src_cr |= SRC_CR_INIT_VAL;
-        writel(src_cr, io_p2v(NOMADIK_SRC_BASE));
-        /* Save global pointer to mtu, used by functions above */
-        mtu_base = io_p2v(NOMADIK_MTU0_BASE);
        /* Init the timer and register clocksource */
        nmdk_timer_reset();
@@ -150,7 +135,9 @@ static void __init nmdk_timer_init(void)
        bits =  8*sizeof(nmdk_count);
        nmdk_clksrc.mask = CLOCKSOURCE_MASK(bits);
-        clocksource_register(&nmdk_clksrc);
+        if (clocksource_register(&nmdk_clksrc))
+                printk(KERN_ERR "timer: failed to initialize clock "
+                        "source %s\n", nmdk_clksrc.name);
        /* Register irq and clockevents */
        setup_irq(IRQ_MTU0, &nmdk_timer_irq);
@@ -158,7 +145,3 @@ static void __init nmdk_timer_init(void)
        nmdk_clkevt.cpumask = cpumask_of(0);
        clockevents_register_device(&nmdk_clkevt);
 }
-struct sys_timer nomadik_timer = {
-        .init           = nmdk_timer_init,
-};
diff --git a/arch/arm/plat-omap/include/mach/memory.h b/arch/arm/plat-omap/include/mach/memory.h
index 9ad41dc484c1..3325f7b49eaa 100644
--- a/arch/arm/plat-omap/include/mach/memory.h
+++ b/arch/arm/plat-omap/include/mach/memory.h
@@ -68,6 +68,13 @@
                __dma = __dma - PHYS_OFFSET + OMAP1510_LB_OFFSET; \
           __dma; })
+#define __arch_dma_to_page(dev, addr)   \
+        ({ dma_addr_t __dma = addr;                             \
+           if (is_lbus_device(dev))                             \
+                __dma += PHYS_OFFSET - OMAP1510_LB_OFFSET;      \
+           phys_to_page(__dma);                                 \
+        })
 #define __arch_dma_to_virt(dev, addr)   ({ (void *) (is_lbus_device(dev) ? \
                                                lbus_to_virt(addr) : \
                                                __phys_to_virt(addr)); })
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx_nand.h b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
index 3478eae32d8a..3478eae32d8a 100644
--- a/arch/arm/mach-pxa/include/mach/pxa3xx_nand.h
+++ b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
diff --git a/arch/arm/plat-s3c/Kconfig b/arch/arm/plat-s3c/Kconfig
index 8931c5f0e46b..e139a72c2149 100644
--- a/arch/arm/plat-s3c/Kconfig
+++ b/arch/arm/plat-s3c/Kconfig
@@ -159,6 +159,12 @@ config S3C_GPIO_CFG_S3C64XX
          Internal configuration to enable S3C64XX style GPIO configuration
          functions.
+config S5P_GPIO_CFG_S5PC1XX
+        bool
+        help
+          Internal configuration to enable S5PC1XX style GPIO configuration
+          functions.
 # DMA
 config S3C_DMA
@@ -178,6 +184,11 @@ config S3C_DEV_HSMMC1
        help
          Compile in platform device definitions for HSMMC channel 1
+config S3C_DEV_HSMMC2
+        bool
+        help
+          Compile in platform device definitions for HSMMC channel 2
 config S3C_DEV_I2C1
        bool
        help
diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile
index 3c09109e9e84..50444da98425 100644
--- a/arch/arm/plat-s3c/Makefile
+++ b/arch/arm/plat-s3c/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_HAVE_PWM)		+= pwm.o
 obj-$(CONFIG_S3C_DEV_HSMMC)     += dev-hsmmc.o
 obj-$(CONFIG_S3C_DEV_HSMMC1)    += dev-hsmmc1.o
+obj-$(CONFIG_S3C_DEV_HSMMC2)    += dev-hsmmc2.o
 obj-y                           += dev-i2c0.o
 obj-$(CONFIG_S3C_DEV_I2C1)      += dev-i2c1.o
 obj-$(CONFIG_S3C_DEV_FB)        += dev-fb.o
diff --git a/arch/arm/plat-s3c/clock.c b/arch/arm/plat-s3c/clock.c
index 4d01ef1a25dd..619cfa82dcab 100644
--- a/arch/arm/plat-s3c/clock.c
+++ b/arch/arm/plat-s3c/clock.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c24xx/clock.c
 *
- * Copyright (c) 2004-2005 Simtec Electronics
+ * Copyright 2004-2005 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * S3C24XX Core clock control support
@@ -337,7 +337,7 @@ int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
 int __init s3c24xx_register_baseclocks(unsigned long xtal)
 {
-        printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n");
+        printk(KERN_INFO "S3C24XX Clocks, Copyright 2004 Simtec Electronics\n");
        clk_xtal.rate = xtal;
diff --git a/arch/arm/plat-s3c/dev-hsmmc2.c b/arch/arm/plat-s3c/dev-hsmmc2.c
new file mode 100644
index 000000000000..824580bc0e06
--- /dev/null
+++ b/arch/arm/plat-s3c/dev-hsmmc2.c
@@ -0,0 +1,69 @@
+/* linux/arch/arm/plat-s3c/dev-hsmmc2.c
+ *
+ * Copyright (c) 2009 Samsung Electronics
+ * Copyright (c) 2009 Maurus Cuelenaere
+ *
+ * Based on arch/arm/plat-s3c/dev-hsmmc1.c
+ * original file Copyright (c) 2008 Simtec Electronics
+ *
+ * S3C series device definition for hsmmc device 2
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/mmc/host.h>
+#include <mach/map.h>
+#include <plat/sdhci.h>
+#include <plat/devs.h>
+#define S3C_SZ_HSMMC    (0x1000)
+static struct resource s3c_hsmmc2_resource[] = {
+        [0] = {
+                .start = S3C_PA_HSMMC2,
+                .end   = S3C_PA_HSMMC2 + S3C_SZ_HSMMC - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_HSMMC2,
+                .end   = IRQ_HSMMC2,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+static u64 s3c_device_hsmmc2_dmamask = 0xffffffffUL;
+struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata = {
+        .max_width      = 4,
+        .host_caps      = (MMC_CAP_4_BIT_DATA |
+                           MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
+};
+struct platform_device s3c_device_hsmmc2 = {
+        .name           = "s3c-sdhci",
+        .id             = 2,
+        .num_resources  = ARRAY_SIZE(s3c_hsmmc2_resource),
+        .resource       = s3c_hsmmc2_resource,
+        .dev            = {
+                .dma_mask               = &s3c_device_hsmmc2_dmamask,
+                .coherent_dma_mask      = 0xffffffffUL,
+                .platform_data          = &s3c_hsmmc2_def_platdata,
+        },
+};
+void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
+{
+        struct s3c_sdhci_platdata *set = &s3c_hsmmc2_def_platdata;
+        set->max_width = pd->max_width;
+        if (pd->cfg_gpio)
+                set->cfg_gpio = pd->cfg_gpio;
+        if (pd->cfg_card)
+                set->cfg_card = pd->cfg_card;
+}
diff --git a/arch/arm/plat-s3c/dev-i2c0.c b/arch/arm/plat-s3c/dev-i2c0.c
index 428372868fbb..4c761529b949 100644
--- a/arch/arm/plat-s3c/dev-i2c0.c
+++ b/arch/arm/plat-s3c/dev-i2c0.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c/dev-i2c0.c
 *
- * Copyright 2008,2009 Simtec Electronics
+ * Copyright 2008-2009 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *      http://armlinux.simtec.co.uk/
 *
diff --git a/arch/arm/plat-s3c/dev-i2c1.c b/arch/arm/plat-s3c/dev-i2c1.c
index 8349c462788c..d44f79110506 100644
--- a/arch/arm/plat-s3c/dev-i2c1.c
+++ b/arch/arm/plat-s3c/dev-i2c1.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c/dev-i2c1.c
 *
- * Copyright 2008,2009 Simtec Electronics
+ * Copyright 2008-2009 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *      http://armlinux.simtec.co.uk/
 *
diff --git a/arch/arm/plat-s3c/dev-nand.c b/arch/arm/plat-s3c/dev-nand.c
index 4e5323732434..e771e77dcd54 100644
--- a/arch/arm/plat-s3c/dev-nand.c
+++ b/arch/arm/plat-s3c/dev-nand.c
@@ -9,8 +9,12 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
 #include <mach/map.h>
 #include <plat/devs.h>
+#include <plat/nand.h>
 static struct resource s3c_nand_resource[] = {
        [0] = {
@@ -28,3 +32,96 @@ struct platform_device s3c_device_nand = {
 };
 EXPORT_SYMBOL(s3c_device_nand);
+/**
+ * s3c_nand_copy_set() - copy nand set data
+ * @set: The new structure, directly copied from the old.
+ *
+ * Copy all the fields from the NAND set field from what is probably __initdata
+ * to new kernel memory. The code returns 0 if the copy happened correctly or
+ * an error code for the calling function to display.
+ *
+ * Note, we currently do not try and look to see if we've already copied the
+ * data in a previous set.
+ */
+static int __init s3c_nand_copy_set(struct s3c2410_nand_set *set)
+{
+        void *ptr;
+        int size;
+        size = sizeof(struct mtd_partition) * set->nr_partitions;
+        if (size) {
+                ptr = kmemdup(set->partitions, size, GFP_KERNEL);
+                set->partitions = ptr;
+                if (!ptr)
+                        return -ENOMEM;
+        }
+        
+        size = sizeof(int) * set->nr_chips;
+        if (size) {
+                ptr = kmemdup(set->nr_map, size, GFP_KERNEL);
+                set->nr_map = ptr;
+                if (!ptr)
+                        return -ENOMEM;
+        }
+        if (set->ecc_layout) {
+                ptr = kmemdup(set->ecc_layout,
+                              sizeof(struct nand_ecclayout), GFP_KERNEL);
+                set->ecc_layout = ptr;
+                if (!ptr)
+                        return -ENOMEM;
+        }
+        
+        return 0;
+}
+void __init s3c_nand_set_platdata(struct s3c2410_platform_nand *nand)
+{
+        struct s3c2410_platform_nand *npd;
+        int size;
+        int ret;
+        /* note, if we get a failure in allocation, we simply drop out of the
+         * function. If there is so little memory available at initialisation
+         * time then there is little chance the system is going to run.
+         */ 
+        npd = kmemdup(nand, sizeof(struct s3c2410_platform_nand), GFP_KERNEL);
+        if (!npd) {
+                printk(KERN_ERR "%s: failed copying platform data\n", __func__);
+                return;
+        }
+        /* now see if we need to copy any of the nand set data */
+        size = sizeof(struct s3c2410_nand_set) * npd->nr_sets;
+        if (size) {
+                struct s3c2410_nand_set *from = npd->sets;
+                struct s3c2410_nand_set *to;
+                int i;
+                to = kmemdup(from, size, GFP_KERNEL);
+                npd->sets = to; /* set, even if we failed */
+                if (!to) {
+                        printk(KERN_ERR "%s: no memory for sets\n", __func__);
+                        return;
+                }
+                
+                for (i = 0; i < npd->nr_sets; i++) {
+                        ret = s3c_nand_copy_set(to);
+                        if (!ret) {
+                                printk(KERN_ERR "%s: failed to copy set %d\n",
+                                __func__, i);
+                                return;
+                        }
+                        to++;
+                }
+        }
+}
+EXPORT_SYMBOL_GPL(s3c_nand_set_platdata);
diff --git a/arch/arm/plat-s3c/dma.c b/arch/arm/plat-s3c/dma.c
index c9db75c06af5..a995850cd9d5 100644
--- a/arch/arm/plat-s3c/dma.c
+++ b/arch/arm/plat-s3c/dma.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c/dma.c
 *
- * Copyright (c) 2003-2005,2006,2009 Simtec Electronics
+ * Copyright (c) 2003-2009 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *      http://armlinux.simtec.co.uk/
 *
diff --git a/arch/arm/plat-s3c/include/plat/audio-simtec.h b/arch/arm/plat-s3c/include/plat/audio-simtec.h
index 0f440b9168db..53a93656d5db 100644
--- a/arch/arm/plat-s3c/include/plat/audio-simtec.h
+++ b/arch/arm/plat-s3c/include/plat/audio-simtec.h
@@ -33,5 +33,5 @@ struct s3c24xx_audio_simtec_pdata {
        void    (*startup)(void);
 };
-extern int simtec_audio_add(const char *codec_name,
+extern int simtec_audio_add(const char *codec_name, bool has_lr_routing,
                            struct s3c24xx_audio_simtec_pdata *pdata);
diff --git a/arch/arm/plat-s3c/include/plat/cpu-freq.h b/arch/arm/plat-s3c/include/plat/cpu-freq.h
index 7b982b7f28cd..94eb06a2ea5c 100644
--- a/arch/arm/plat-s3c/include/plat/cpu-freq.h
+++ b/arch/arm/plat-s3c/include/plat/cpu-freq.h
@@ -1,6 +1,6 @@
 /* arch/arm/plat-s3c/include/plat/cpu-freq.h
 *
- * Copyright (c) 2006,2007 Simtec Electronics
+ * Copyright (c) 2006-2007 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *
diff --git a/arch/arm/plat-s3c/include/plat/cpu.h b/arch/arm/plat-s3c/include/plat/cpu.h
index fbc3d498e02e..d1131ca11e97 100644
--- a/arch/arm/plat-s3c/include/plat/cpu.h
+++ b/arch/arm/plat-s3c/include/plat/cpu.h
@@ -12,6 +12,9 @@
 /* todo - fix when rmk changes iodescs to use `void __iomem *` */
+#ifndef __SAMSUNG_PLAT_CPU_H
+#define __SAMSUNG_PLAT_CPU_H
 #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
 #ifndef MHZ
@@ -73,3 +76,6 @@ extern struct sysdev_class s3c2443_sysclass;
 extern struct sysdev_class s3c6410_sysclass;
 extern struct sysdev_class s3c64xx_sysclass;
+extern void (*s5pc1xx_idle)(void);
+#endif
diff --git a/arch/arm/plat-s3c/include/plat/dma.h b/arch/arm/plat-s3c/include/plat/dma.h
index 34dba98f08e1..e429d10be3ad 100644
--- a/arch/arm/plat-s3c/include/plat/dma.h
+++ b/arch/arm/plat-s3c/include/plat/dma.h
@@ -1,6 +1,6 @@
 /* arch/arm/plat-s3c/include/plat/dma.h
 *
- * Copyright (C) 2003,2004,2006 Simtec Electronics
+ * Copyright (C) 2003-2006 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * Samsung S3C DMA support
diff --git a/arch/arm/plat-s3c/include/plat/fb.h b/arch/arm/plat-s3c/include/plat/fb.h
index 214ff561b0dd..f8db87930f8b 100644
--- a/arch/arm/plat-s3c/include/plat/fb.h
+++ b/arch/arm/plat-s3c/include/plat/fb.h
@@ -70,4 +70,11 @@ extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd);
 */
 extern void s3c64xx_fb_gpio_setup_24bpp(void);
+/**
+ * s5pc100_fb_gpio_setup_24bpp() - S5PC100 setup function for 24bpp LCD
+ *
+ * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
+ */
+extern void s5pc100_fb_gpio_setup_24bpp(void);
 #endif /* __PLAT_S3C_FB_H */
diff --git a/arch/arm/plat-s3c/include/plat/iic.h b/arch/arm/plat-s3c/include/plat/iic.h
index 67450f115748..3083df00dee6 100644
--- a/arch/arm/plat-s3c/include/plat/iic.h
+++ b/arch/arm/plat-s3c/include/plat/iic.h
@@ -1,6 +1,6 @@
 /* arch/arm/plat-s3c/include/plat/iic.h
 *
- * Copyright 2004,2009 Simtec Electronics
+ * Copyright 2004-2009 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * S3C - I2C Controller platform_device info
diff --git a/arch/arm/plat-s3c/include/plat/nand.h b/arch/arm/plat-s3c/include/plat/nand.h
index 18f958801e64..065985978413 100644
--- a/arch/arm/plat-s3c/include/plat/nand.h
+++ b/arch/arm/plat-s3c/include/plat/nand.h
@@ -55,3 +55,11 @@ struct s3c2410_platform_nand {
                                               int chip);
 };
+/**
+ * s3c_nand_set_platdata() - register NAND platform data.
+ * @nand: The NAND platform data to register with s3c_device_nand.
+ *
+ * This function copies the given NAND platform data, @nand and registers
+ * it with the s3c_device_nand. This allows @nand to be __initdata.
+*/
+extern void s3c_nand_set_platdata(struct s3c2410_platform_nand *nand);
diff --git a/arch/arm/plat-s3c/include/plat/regs-fb-v4.h b/arch/arm/plat-s3c/include/plat/regs-fb-v4.h
new file mode 100644
index 000000000000..a60ed0d06c94
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-fb-v4.h
@@ -0,0 +1,235 @@
+/* arch/arm/plat-s3c/include/plat/regs-fb-v4.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C64XX - new-style framebuffer register definitions
+ *
+ * This is the register set for the new style framebuffer interface
+ * found from the S3C2443 onwards and specifically the S3C64XX series
+ * S3C6400 and S3C6410.
+ *
+ * The file contains the cpu specific items which change between whichever
+ * architecture is selected. See <plat/regs-fb.h> for the core definitions
+ * that are the same.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+/* include the core definitions here, in case we really do need to
+ * override them at a later date.
+*/
+#include <plat/regs-fb.h>
+#define S3C_FB_MAX_WIN (5)  /* number of hardware windows available. */
+#define VIDCON1_FSTATUS_EVEN    (1 << 15)
+/* Video timing controls */
+#define VIDTCON0                                (0x10)
+#define VIDTCON1                                (0x14)
+#define VIDTCON2                                (0x18)
+/* Window position controls */
+#define WINCON(_win)                            (0x20 + ((_win) * 4))
+/* OSD1 and OSD4 do not have register D */
+#define VIDOSD_A(_win)                          (0x40 + ((_win) * 16))
+#define VIDOSD_B(_win)                          (0x44 + ((_win) * 16))
+#define VIDOSD_C(_win)                          (0x48 + ((_win) * 16))
+#define VIDOSD_D(_win)                          (0x4C + ((_win) * 16))
+#define VIDINTCON0                              (0x130)
+#define WxKEYCONy(_win, _con)                   ((0x140 + ((_win) * 8)) + ((_con) * 4))
+/* WINCONx */
+#define WINCONx_CSCWIDTH_MASK                   (0x3 << 26)
+#define WINCONx_CSCWIDTH_SHIFT                  (26)
+#define WINCONx_CSCWIDTH_WIDE                   (0x0 << 26)
+#define WINCONx_CSCWIDTH_NARROW                 (0x3 << 26)
+#define WINCONx_ENLOCAL                         (1 << 22)
+#define WINCONx_BUFSTATUS                       (1 << 21)
+#define WINCONx_BUFSEL                          (1 << 20)
+#define WINCONx_BUFAUTOEN                       (1 << 19)
+#define WINCONx_YCbCr                           (1 << 13)
+#define WINCON1_LOCALSEL_CAMIF                  (1 << 23)
+#define WINCON2_LOCALSEL_CAMIF                  (1 << 23)
+#define WINCON2_BLD_PIX                         (1 << 6)
+#define WINCON2_ALPHA_SEL                       (1 << 1)
+#define WINCON2_BPPMODE_MASK                    (0xf << 2)
+#define WINCON2_BPPMODE_SHIFT                   (2)
+#define WINCON2_BPPMODE_1BPP                    (0x0 << 2)
+#define WINCON2_BPPMODE_2BPP                    (0x1 << 2)
+#define WINCON2_BPPMODE_4BPP                    (0x2 << 2)
+#define WINCON2_BPPMODE_8BPP_1232               (0x4 << 2)
+#define WINCON2_BPPMODE_16BPP_565               (0x5 << 2)
+#define WINCON2_BPPMODE_16BPP_A1555             (0x6 << 2)
+#define WINCON2_BPPMODE_16BPP_I1555             (0x7 << 2)
+#define WINCON2_BPPMODE_18BPP_666               (0x8 << 2)
+#define WINCON2_BPPMODE_18BPP_A1665             (0x9 << 2)
+#define WINCON2_BPPMODE_19BPP_A1666             (0xa << 2)
+#define WINCON2_BPPMODE_24BPP_888               (0xb << 2)
+#define WINCON2_BPPMODE_24BPP_A1887             (0xc << 2)
+#define WINCON2_BPPMODE_25BPP_A1888             (0xd << 2)
+#define WINCON2_BPPMODE_28BPP_A4888             (0xd << 2)
+#define WINCON3_BLD_PIX                         (1 << 6)
+#define WINCON3_ALPHA_SEL                       (1 << 1)
+#define WINCON3_BPPMODE_MASK                    (0xf << 2)
+#define WINCON3_BPPMODE_SHIFT                   (2)
+#define WINCON3_BPPMODE_1BPP                    (0x0 << 2)
+#define WINCON3_BPPMODE_2BPP                    (0x1 << 2)
+#define WINCON3_BPPMODE_4BPP                    (0x2 << 2)
+#define WINCON3_BPPMODE_16BPP_565               (0x5 << 2)
+#define WINCON3_BPPMODE_16BPP_A1555             (0x6 << 2)
+#define WINCON3_BPPMODE_16BPP_I1555             (0x7 << 2)
+#define WINCON3_BPPMODE_18BPP_666               (0x8 << 2)
+#define WINCON3_BPPMODE_18BPP_A1665             (0x9 << 2)
+#define WINCON3_BPPMODE_19BPP_A1666             (0xa << 2)
+#define WINCON3_BPPMODE_24BPP_888               (0xb << 2)
+#define WINCON3_BPPMODE_24BPP_A1887             (0xc << 2)
+#define WINCON3_BPPMODE_25BPP_A1888             (0xd << 2)
+#define WINCON3_BPPMODE_28BPP_A4888             (0xd << 2)
+#define VIDINTCON0_FIFIOSEL_WINDOW2             (0x10 << 5)
+#define VIDINTCON0_FIFIOSEL_WINDOW3             (0x20 << 5)
+#define VIDINTCON0_FIFIOSEL_WINDOW4             (0x40 << 5)
+#define DITHMODE                                (0x170)
+#define WINxMAP(_win)                           (0x180 + ((_win) * 4))
+#define DITHMODE_R_POS_MASK                     (0x3 << 5)
+#define DITHMODE_R_POS_SHIFT                    (5)
+#define DITHMODE_R_POS_8BIT                     (0x0 << 5)
+#define DITHMODE_R_POS_6BIT                     (0x1 << 5)
+#define DITHMODE_R_POS_5BIT                     (0x2 << 5)
+#define DITHMODE_G_POS_MASK                     (0x3 << 3)
+#define DITHMODE_G_POS_SHIFT                    (3)
+#define DITHMODE_G_POS_8BIT                     (0x0 << 3)
+#define DITHMODE_G_POS_6BIT                     (0x1 << 3)
+#define DITHMODE_G_POS_5BIT                     (0x2 << 3)
+#define DITHMODE_B_POS_MASK                     (0x3 << 1)
+#define DITHMODE_B_POS_SHIFT                    (1)
+#define DITHMODE_B_POS_8BIT                     (0x0 << 1)
+#define DITHMODE_B_POS_6BIT                     (0x1 << 1)
+#define DITHMODE_B_POS_5BIT                     (0x2 << 1)
+#define DITHMODE_DITH_EN                        (1 << 0)
+#define WPALCON                                 (0x1A0)
+/* Palette control */
+/* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L),
+ * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */
+#define WPALCON_W4PAL_16BPP_A555                (1 << 8)
+#define WPALCON_W3PAL_16BPP_A555                (1 << 7)
+#define WPALCON_W2PAL_16BPP_A555                (1 << 6)
+/* system specific implementation code for palette sizes, and other
+ * information that changes depending on which architecture is being
+ * compiled.
+*/
+/* return true if window _win has OSD register D */
+#define s3c_fb_has_osd_d(_win) ((_win) != 4 && (_win) != 0)
+static inline unsigned int s3c_fb_win_pal_size(unsigned int win)
+{
+        if (win < 2)
+                return 256;
+        if (win < 4)
+                return 16;
+        if (win == 4)
+                return 4;
+        BUG();  /* shouldn't get here */
+}
+static inline int s3c_fb_validate_win_bpp(unsigned int win, unsigned int bpp)
+{
+        /* all windows can do 1/2 bpp */
+        if ((bpp == 25 || bpp == 19) && win == 0)
+                return 0;       /* win 0 does not have 19 or 25bpp modes */
+        if (bpp == 4 && win == 4)
+                return 0;
+        if (bpp == 8 && (win >= 3))
+                return 0;       /* win 3/4 cannot do 8bpp in any mode */
+        return 1;
+}
+static inline int s3c_fb_pal_is16(unsigned int window)
+{
+        return window > 1;
+}
+struct s3c_fb_palette {
+        struct fb_bitfield      r;
+        struct fb_bitfield      g;
+        struct fb_bitfield      b;
+        struct fb_bitfield      a;
+};
+static inline void s3c_fb_init_palette(unsigned int window,
+                                       struct s3c_fb_palette *palette)
+{
+        if (window < 2) {
+                /* Windows 0/1 are 8/8/8 or A/8/8/8 */
+                palette->r.offset = 16;
+                palette->r.length = 8;
+                palette->g.offset = 8;
+                palette->g.length = 8;
+                palette->b.offset = 0;
+                palette->b.length = 8;
+        } else {
+                /* currently we assume RGB 5/6/5 */
+                palette->r.offset = 11;
+                palette->r.length = 5;
+                palette->g.offset = 5;
+                palette->g.length = 6;
+                palette->b.offset = 0;
+                palette->b.length = 5;
+        }
+}
+/* Notes on per-window bpp settings
+ *
+ * Value        Win0     Win1     Win2     Win3     Win 4
+ * 0000         1(P)     1(P)     1(P)     1(P)     1(P)
+ * 0001         2(P)     2(P)     2(P)     2(P)     2(P)
+ * 0010         4(P)     4(P)     4(P)     4(P)     -none-
+ * 0011         8(P)     8(P)     -none-   -none-   -none-
+ * 0100         -none-   8(A232)  8(A232)  -none-   -none-
+ * 0101         16(565)  16(565)  16(565)  16(565)   16(565)
+ * 0110         -none-   16(A555) 16(A555) 16(A555)  16(A555)
+ * 0111         16(I555) 16(I565) 16(I555) 16(I555)  16(I555)
+ * 1000         18(666)  18(666)  18(666)  18(666)   18(666)
+ * 1001         -none-   18(A665) 18(A665) 18(A665)  16(A665)
+ * 1010         -none-   19(A666) 19(A666) 19(A666)  19(A666)
+ * 1011         24(888)  24(888)  24(888)  24(888)   24(888)
+ * 1100         -none-   24(A887) 24(A887) 24(A887)  24(A887)
+ * 1101         -none-   25(A888) 25(A888) 25(A888)  25(A888)
+ * 1110         -none-   -none-   -none-   -none-    -none-
+ * 1111         -none-   -none-   -none-   -none-    -none-
+*/
diff --git a/arch/arm/plat-s3c/include/plat/regs-nand.h b/arch/arm/plat-s3c/include/plat/regs-nand.h
index b2caa4bca270..238efea7b9e4 100644
--- a/arch/arm/plat-s3c/include/plat/regs-nand.h
+++ b/arch/arm/plat-s3c/include/plat/regs-nand.h
@@ -1,7 +1,7 @@
 /* arch/arm/mach-s3c2410/include/mach/regs-nand.h
 *
- * Copyright (c) 2004,2005 Simtec Electronics <linux@simtec.co.uk>
+ * Copyright (c) 2004-2005 Simtec Electronics <linux@simtec.co.uk>
- *                    http://www.simtec.co.uk/products/SWLINUX/
+ *      http://www.simtec.co.uk/products/SWLINUX/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/plat-s3c/include/plat/regs-serial.h b/arch/arm/plat-s3c/include/plat/regs-serial.h
index 66af75a5cdd1..85d8904e7f24 100644
--- a/arch/arm/plat-s3c/include/plat/regs-serial.h
+++ b/arch/arm/plat-s3c/include/plat/regs-serial.h
@@ -6,7 +6,7 @@
 *
 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
 *
- *  Additional defines, (c) 2003 Simtec Electronics (linux@simtec.co.uk)
+ *  Additional defines, Copyright 2003 Simtec Electronics (linux@simtec.co.uk)
 *
 *  Adapted from:
 *
diff --git a/arch/arm/plat-s3c/include/plat/sdhci.h b/arch/arm/plat-s3c/include/plat/sdhci.h
index f615308ccdfb..53198673b6bd 100644
--- a/arch/arm/plat-s3c/include/plat/sdhci.h
+++ b/arch/arm/plat-s3c/include/plat/sdhci.h
@@ -57,6 +57,7 @@ struct s3c_sdhci_platdata {
 */
 extern void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd);
 extern void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd);
+extern void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd);
 /* Default platform data, exported so that per-cpu initialisation can
 * set the correct one when there are more than one cpu type selected.
@@ -64,11 +65,16 @@ extern void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd);
 extern struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata;
 extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata;
+extern struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata;
 /* Helper function availablity */
 extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
 extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
+extern void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
+extern void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
+extern void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
+extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
 /* S3C6400 SDHCI setup */
@@ -103,6 +109,17 @@ static inline void s3c6400_default_sdhci1(void)
 static inline void s3c6400_default_sdhci1(void) { }
 #endif /* CONFIG_S3C_DEV_HSMMC1 */
+#ifdef CONFIG_S3C_DEV_HSMMC2
+static inline void s3c6400_default_sdhci2(void)
+{
+        s3c_hsmmc2_def_platdata.clocks = s3c6400_hsmmc_clksrcs;
+        s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
+        s3c_hsmmc2_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
+}
+#else
+static inline void s3c6400_default_sdhci2(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC2 */
 #else
 static inline void s3c6400_default_sdhci0(void) { }
 static inline void s3c6400_default_sdhci1(void) { }
@@ -140,9 +157,70 @@ static inline void s3c6410_default_sdhci1(void)
 static inline void s3c6410_default_sdhci1(void) { }
 #endif /* CONFIG_S3C_DEV_HSMMC1 */
+#ifdef CONFIG_S3C_DEV_HSMMC2
+static inline void s3c6410_default_sdhci2(void)
+{
+        s3c_hsmmc2_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
+        s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
+        s3c_hsmmc2_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
+}
+#else
+static inline void s3c6410_default_sdhci2(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC2 */
 #else
 static inline void s3c6410_default_sdhci0(void) { }
 static inline void s3c6410_default_sdhci1(void) { }
 #endif /* CONFIG_S3C6410_SETUP_SDHCI */
+/* S5PC100 SDHCI setup */
+#ifdef CONFIG_S5PC100_SETUP_SDHCI
+extern char *s5pc100_hsmmc_clksrcs[4];
+extern void s5pc100_setup_sdhci0_cfg_card(struct platform_device *dev,
+                                           void __iomem *r,
+                                           struct mmc_ios *ios,
+                                           struct mmc_card *card);
+#ifdef CONFIG_S3C_DEV_HSMMC
+static inline void s5pc100_default_sdhci0(void)
+{
+        s3c_hsmmc0_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
+        s3c_hsmmc0_def_platdata.cfg_gpio = s5pc100_setup_sdhci0_cfg_gpio;
+        s3c_hsmmc0_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card;
+}
+#else
+static inline void s5pc100_default_sdhci0(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC */
+#ifdef CONFIG_S3C_DEV_HSMMC1
+static inline void s5pc100_default_sdhci1(void)
+{
+        s3c_hsmmc1_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
+        s3c_hsmmc1_def_platdata.cfg_gpio = s5pc100_setup_sdhci1_cfg_gpio;
+        s3c_hsmmc1_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card;
+}
+#else
+static inline void s5pc100_default_sdhci1(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC1 */
+#ifdef CONFIG_S3C_DEV_HSMMC2
+static inline void s5pc100_default_sdhci2(void)
+{
+        s3c_hsmmc2_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
+        s3c_hsmmc2_def_platdata.cfg_gpio = s5pc100_setup_sdhci2_cfg_gpio;
+        s3c_hsmmc2_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card;
+}
+#else
+static inline void s5pc100_default_sdhci2(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC1 */
+#else
+static inline void s5pc100_default_sdhci0(void) { }
+static inline void s5pc100_default_sdhci1(void) { }
+static inline void s5pc100_default_sdhci2(void) { }
+#endif /* CONFIG_S5PC100_SETUP_SDHCI */
 #endif /* __PLAT_S3C_SDHCI_H */
diff --git a/arch/arm/plat-s3c/pm-check.c b/arch/arm/plat-s3c/pm-check.c
index 39f2555564da..8eb1f439861c 100644
--- a/arch/arm/plat-s3c/pm-check.c
+++ b/arch/arm/plat-s3c/pm-check.c
@@ -1,7 +1,7 @@
 /* linux/arch/arm/plat-s3c/pm-check.c
 *  originally in linux/arch/arm/plat-s3c24xx/pm.c
 *
- * Copyright (c) 2004,2006,2008 Simtec Electronics
+ * Copyright (c) 2004-2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk
 *      Ben Dooks <ben@simtec.co.uk>
 *
diff --git a/arch/arm/plat-s3c/pm.c b/arch/arm/plat-s3c/pm.c
index 8d97db2c7a0d..767470601e5c 100644
--- a/arch/arm/plat-s3c/pm.c
+++ b/arch/arm/plat-s3c/pm.c
@@ -1,7 +1,7 @@
 /* linux/arch/arm/plat-s3c/pm.c
 *
 * Copyright 2008 Openmoko, Inc.
- * Copyright 2004,2006,2008 Simtec Electronics
+ * Copyright 2004-2008 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *      http://armlinux.simtec.co.uk/
 *
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index 9c7aca489643..20fbf936bb93 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -178,4 +178,11 @@ config MACH_SMDK
        help
          Common machine code for SMDK2410 and SMDK2440
+config S3C24XX_SIMTEC_AUDIO
+        bool
+        depends on (ARCH_BAST || MACH_VR1000 || MACH_OSIRIS || MACH_ANUBIS)
+        default y
+        help
+          Add audio devices for common Simtec S3C24XX boards
 endif
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
index 7780d2dd833a..5dee8c12e8b4 100644
--- a/arch/arm/plat-s3c24xx/Makefile
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -55,3 +55,4 @@ obj-$(CONFIG_S3C24XX_SPI_BUS1_GPD8_GPD9_GPD10)	 += spi-bus1-gpd8_9_10.o
 # machine common support
 obj-$(CONFIG_MACH_SMDK)         += common-smdk.o
+obj-$(CONFIG_S3C24XX_SIMTEC_AUDIO)      += simtec-audio.o
diff --git a/arch/arm/plat-s3c24xx/clock-dclk.c b/arch/arm/plat-s3c24xx/clock-dclk.c
index 0afb217a775e..ac061a1bcb37 100644
--- a/arch/arm/plat-s3c24xx/clock-dclk.c
+++ b/arch/arm/plat-s3c24xx/clock-dclk.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c24xx/clock-dclk.c
 *
- * Copyright (c) 2004,2008 Simtec Electronics
+ * Copyright (c) 2004-2008 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *      http://armlinux.simtec.co.uk/
 *
diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c
index aa119863c5ce..9e0e20ad2e46 100644
--- a/arch/arm/plat-s3c24xx/common-smdk.c
+++ b/arch/arm/plat-s3c24xx/common-smdk.c
@@ -198,7 +198,7 @@ void __init smdk_machine_init(void)
        if (machine_is_smdk2443())
                smdk_nand_info.twrph0 = 50;
-        s3c_device_nand.dev.platform_data = &smdk_nand_info;
+        s3c_nand_set_platdata(&smdk_nand_info);
        platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs));
diff --git a/arch/arm/plat-s3c24xx/cpu-freq.c b/arch/arm/plat-s3c24xx/cpu-freq.c
index 4f1b789a1173..2d42efb9f4e9 100644
--- a/arch/arm/plat-s3c24xx/cpu-freq.c
+++ b/arch/arm/plat-s3c24xx/cpu-freq.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c24xx/cpu-freq.c
 *
- * Copyright (c) 2006,2007,2008 Simtec Electronics
+ * Copyright (c) 2006-2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index f046f8c51084..f65192d5b1d7 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c24xx/dma.c
 *
- * Copyright (c) 2003-2005,2006 Simtec Electronics
+ * Copyright 2003-2006 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * S3C2410 DMA core
@@ -1310,7 +1310,7 @@ int __init s3c24xx_dma_init(unsigned int channels, unsigned int irq,
        int channel;
        int ret;
-        printk("S3C24XX DMA Driver, (c) 2003-2004,2006 Simtec Electronics\n");
+        printk("S3C24XX DMA Driver, Copyright 2003-2006 Simtec Electronics\n");
        dma_channels = channels;
diff --git a/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h b/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h
index c776120b99e6..33d421d78bad 100644
--- a/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h
+++ b/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h
@@ -1,6 +1,6 @@
 /* arch/arm/plat-s3c/include/plat/cpu-freq.h
 *
- * Copyright (c) 2006,2007,2009 Simtec Electronics
+ * Copyright (c) 2006-2009 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *
diff --git a/arch/arm/plat-s3c24xx/include/plat/mci.h b/arch/arm/plat-s3c24xx/include/plat/mci.h
index c2cef6139683..36aaa10fad06 100644
--- a/arch/arm/plat-s3c24xx/include/plat/mci.h
+++ b/arch/arm/plat-s3c24xx/include/plat/mci.h
@@ -1,6 +1,31 @@
 #ifndef _ARCH_MCI_H
 #define _ARCH_MCI_H
+/**
+ * struct s3c24xx_mci_pdata - sd/mmc controller platform data
+ * @no_wprotect: Set this to indicate there is no write-protect switch.
+ * @no_detect: Set this if there is no detect switch.
+ * @wprotect_invert: Invert the default sense of the write protect switch.
+ * @detect_invert: Invert the default sense of the write protect switch.
+ * @use_dma: Set to allow the use of DMA.
+ * @gpio_detect: GPIO number for the card detect line.
+ * @gpio_wprotect: GPIO number for the write protect line.
+ * @ocr_avail: The mask of the available power states, non-zero to use.
+ * @set_power: Callback to control the power mode.
+ *
+ * The @gpio_detect is used for card detection when @no_wprotect is unset,
+ * and the default sense is that 0 returned from gpio_get_value() means
+ * that a card is inserted. If @detect_invert is set, then the value from
+ * gpio_get_value() is inverted, which makes 1 mean card inserted.
+ *
+ * The driver will use @gpio_wprotect to signal whether the card is write
+ * protected if @no_wprotect is not set. A 0 returned from gpio_get_value()
+ * means the card is read/write, and 1 means read-only. The @wprotect_invert
+ * will invert the value returned from gpio_get_value().
+ *
+ * Card power is set by @ocr_availa, using MCC_VDD_ constants if it is set
+ * to a non-zero value, otherwise the default of 3.2-3.4V is used.
+ */
 struct s3c24xx_mci_pdata {
        unsigned int    no_wprotect : 1;
        unsigned int    no_detect : 1;
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-dma.h b/arch/arm/plat-s3c24xx/include/plat/regs-dma.h
index 3bc0a216df97..1b0f4c36d384 100644
--- a/arch/arm/plat-s3c24xx/include/plat/regs-dma.h
+++ b/arch/arm/plat-s3c24xx/include/plat/regs-dma.h
@@ -1,6 +1,6 @@
 /* arch/arm/mach-s3c2410/include/mach/dma.h
 *
- * Copyright (C) 2003,2004,2006 Simtec Electronics
+ * Copyright (C) 2003-2006 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * Samsung S3C24XX DMA support
diff --git a/arch/arm/plat-s3c24xx/irq-pm.c b/arch/arm/plat-s3c24xx/irq-pm.c
index b7acf1a8ecd2..ea8dea3339a4 100644
--- a/arch/arm/plat-s3c24xx/irq-pm.c
+++ b/arch/arm/plat-s3c24xx/irq-pm.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c24xx/irq-om.c
 *
- * Copyright (c) 2003,2004 Simtec Electronics
+ * Copyright (c) 2003-2004 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *      http://armlinux.simtec.co.uk/
 *
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
index d02f5f02045e..ef0f521437d7 100644
--- a/arch/arm/plat-s3c24xx/irq.c
+++ b/arch/arm/plat-s3c24xx/irq.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c24xx/irq.c
 *
- * Copyright (c) 2003,2004 Simtec Electronics 
+ * Copyright (c) 2003-2004 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * This program is free software; you can redistribute it and/or modify
diff --git a/arch/arm/plat-s3c24xx/pm-simtec.c b/arch/arm/plat-s3c24xx/pm-simtec.c
index da0d3217d3e3..663b280d65da 100644
--- a/arch/arm/plat-s3c24xx/pm-simtec.c
+++ b/arch/arm/plat-s3c24xx/pm-simtec.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c24xx/pm-simtec.c
 *
- * Copyright (c) 2004 Simtec Electronics
+ * Copyright 2004 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * http://armlinux.simtec.co.uk/
@@ -35,7 +35,7 @@
 #include <plat/pm.h>
-#define COPYRIGHT ", (c) 2005 Simtec Electronics"
+#define COPYRIGHT ", Copyright 2005 Simtec Electronics"
 /* pm_simtec_init
 *
diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c
index 56e5253ca02c..3620dd299095 100644
--- a/arch/arm/plat-s3c24xx/pm.c
+++ b/arch/arm/plat-s3c24xx/pm.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c24xx/pm.c
 *
- * Copyright (c) 2004,2006 Simtec Electronics
+ * Copyright (c) 2004-2006 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * S3C24XX Power Manager (Suspend-To-RAM) support
diff --git a/arch/arm/plat-s3c24xx/s3c2410-iotiming.c b/arch/arm/plat-s3c24xx/s3c2410-iotiming.c
index d0a3a145cd4d..963fb0b4379e 100644
--- a/arch/arm/plat-s3c24xx/s3c2410-iotiming.c
+++ b/arch/arm/plat-s3c24xx/s3c2410-iotiming.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c24xx/s3c2410-iotiming.c
 *
- * Copyright (c) 2006,2008,2009 Simtec Electronics
+ * Copyright (c) 2006-2009 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *
diff --git a/arch/arm/plat-s3c24xx/s3c2412-iotiming.c b/arch/arm/plat-s3c24xx/s3c2412-iotiming.c
index fd45e47facbc..24993dce10b5 100644
--- a/arch/arm/plat-s3c24xx/s3c2412-iotiming.c
+++ b/arch/arm/plat-s3c24xx/s3c2412-iotiming.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c24xx/s3c2412-iotiming.c
 *
- * Copyright (c) 2006,2008 Simtec Electronics
+ * Copyright (c) 2006-2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *
diff --git a/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c b/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c
index ae2e6c604f27..976002fb1b8f 100644
--- a/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c
+++ b/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c
 *
- * Copyright (c) 2006,2008,2009 Simtec Electronics
+ * Copyright (c) 2006-2009 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *      Vincent Sanders <vince@simtec.co.uk>
diff --git a/arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c b/arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c
index ff9443b233aa..49f65032f2c0 100644
--- a/arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c
+++ b/arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c
@@ -1,6 +1,6 @@
 /* arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c
 *
- * Copyright (c) 2006,2007 Simtec Electronics
+ * Copyright (c) 2006-2007 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *      Vincent Sanders <vince@arm.linux.org.uk>
diff --git a/arch/arm/plat-s3c24xx/s3c244x-clock.c b/arch/arm/plat-s3c24xx/s3c244x-clock.c
index dde41f171aff..79371091aa38 100644
--- a/arch/arm/plat-s3c24xx/s3c244x-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c244x-clock.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c24xx/s3c24xx-clock.c
 *
- * Copyright (c) 2004-2005,2008 Simtec Electronics
+ * Copyright (c) 2004-2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *
diff --git a/arch/arm/plat-s3c24xx/s3c244x-irq.c b/arch/arm/plat-s3c24xx/s3c244x-irq.c
index 0902afd227ca..a75c0c2431ea 100644
--- a/arch/arm/plat-s3c24xx/s3c244x-irq.c
+++ b/arch/arm/plat-s3c24xx/s3c244x-irq.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c24xx/s3c244x-irq.c
 *
- * Copyright (c) 2003,2004 Simtec Electronics
+ * Copyright (c) 2003-2004 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * This program is free software; you can redistribute it and/or modify
diff --git a/arch/arm/plat-s3c24xx/simtec-audio.c b/arch/arm/plat-s3c24xx/simtec-audio.c
new file mode 100644
index 000000000000..6bc832e0d8ea
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/simtec-audio.c
@@ -0,0 +1,77 @@
+/* linux/arch/arm/plat-s3c24xx/simtec-audio.c
+ *
+ * Copyright (c) 2009 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Audio setup for various Simtec S3C24XX implementations
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <mach/bast-map.h>
+#include <mach/bast-irq.h>
+#include <mach/bast-cpld.h>
+#include <mach/hardware.h>
+#include <mach/regs-gpio.h>
+#include <plat/audio-simtec.h>
+#include <plat/devs.h>
+/* platform ops for audio */
+static void simtec_audio_startup_lrroute(void)
+{
+        unsigned int tmp;
+        unsigned long flags;
+        local_irq_save(flags);
+        tmp = __raw_readb(BAST_VA_CTRL1);
+        tmp &= ~BAST_CPLD_CTRL1_LRMASK;
+        tmp |= BAST_CPLD_CTRL1_LRCDAC;
+        __raw_writeb(tmp, BAST_VA_CTRL1);
+        local_irq_restore(flags);
+}
+static struct s3c24xx_audio_simtec_pdata simtec_audio_platdata;
+static char our_name[32];
+static struct platform_device simtec_audio_dev = {
+        .name   = our_name,
+        .id     = -1,
+        .dev    = {
+                .parent         = &s3c_device_iis.dev,
+                .platform_data  = &simtec_audio_platdata,
+        },
+};
+int __init simtec_audio_add(const char *name, bool has_lr_routing,
+                            struct s3c24xx_audio_simtec_pdata *spd)
+{
+        if (!name)
+                name = "tlv320aic23";
+        snprintf(our_name, sizeof(our_name)-1, "s3c24xx-simtec-%s", name);
+        /* copy platform data so the source can be __initdata */
+        if (spd)
+                simtec_audio_platdata = *spd;
+        if (has_lr_routing)
+                simtec_audio_platdata.startup = simtec_audio_startup_lrroute;
+        platform_device_register(&s3c_device_iis);
+        platform_device_register(&simtec_audio_dev);
+        return 0;
+}
diff --git a/arch/arm/plat-s3c64xx/cpu.c b/arch/arm/plat-s3c64xx/cpu.c
index b1fdd83940a6..49796d2db86d 100644
--- a/arch/arm/plat-s3c64xx/cpu.c
+++ b/arch/arm/plat-s3c64xx/cpu.c
@@ -107,6 +107,11 @@ static struct map_desc s3c_iodesc[] __initdata = {
                .pfn            = __phys_to_pfn(S3C64XX_PA_WATCHDOG),
                .length         = SZ_4K,
                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
+                .pfn            = __phys_to_pfn(S3C64XX_PA_USB_HSPHY),
+                .length         = SZ_1K,
+                .type           = MT_DEVICE,
        },
 };
diff --git a/arch/arm/plat-s3c64xx/cpufreq.c b/arch/arm/plat-s3c64xx/cpufreq.c
index e6e0843215df..74c0e8347de5 100644
--- a/arch/arm/plat-s3c64xx/cpufreq.c
+++ b/arch/arm/plat-s3c64xx/cpufreq.c
@@ -19,6 +19,7 @@
 static struct clk *armclk;
 static struct regulator *vddarm;
+static unsigned long regulator_latency;
 #ifdef CONFIG_CPU_S3C6410
 struct s3c64xx_dvfs {
@@ -27,11 +28,10 @@ struct s3c64xx_dvfs {
 };
 static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = {
-        [0] = { 1000000, 1000000 },
+        [0] = { 1000000, 1150000 },
-        [1] = { 1000000, 1050000 },
+        [1] = { 1050000, 1150000 },
-        [2] = { 1050000, 1100000 },
+        [2] = { 1100000, 1150000 },
-        [3] = { 1050000, 1150000 },
+        [3] = { 1200000, 1350000 },
-        [4] = { 1250000, 1350000 },
 };
 static struct cpufreq_frequency_table s3c64xx_freq_table[] = {
@@ -41,9 +41,9 @@ static struct cpufreq_frequency_table s3c64xx_freq_table[] = {
        { 1, 266000 },
        { 2, 333000 },
        { 2, 400000 },
-        { 3, 532000 },
+        { 2, 532000 },
-        { 3, 533000 },
+        { 2, 533000 },
-        { 4, 667000 },
+        { 3, 667000 },
        { 0, CPUFREQ_TABLE_END },
 };
 #endif
@@ -141,7 +141,7 @@ err:
 }
 #ifdef CONFIG_REGULATOR
-static void __init s3c64xx_cpufreq_constrain_voltages(void)
+static void __init s3c64xx_cpufreq_config_regulator(void)
 {
        int count, v, i, found;
        struct cpufreq_frequency_table *freq;
@@ -150,11 +150,10 @@ static void __init s3c64xx_cpufreq_constrain_voltages(void)
        count = regulator_count_voltages(vddarm);
        if (count < 0) {
                pr_err("cpufreq: Unable to check supported voltages\n");
-                return;
        }
        freq = s3c64xx_freq_table;
-        while (freq->frequency != CPUFREQ_TABLE_END) {
+        while (count > 0 && freq->frequency != CPUFREQ_TABLE_END) {
                if (freq->frequency == CPUFREQ_ENTRY_INVALID)
                        continue;
@@ -175,6 +174,10 @@ static void __init s3c64xx_cpufreq_constrain_voltages(void)
                freq++;
        }
+        /* Guess based on having to do an I2C/SPI write; in future we
+         * will be able to query the regulator performance here. */
+        regulator_latency = 1 * 1000 * 1000;
 }
 #endif
@@ -206,7 +209,7 @@ static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
                pr_err("cpufreq: Only frequency scaling available\n");
                vddarm = NULL;
        } else {
-                s3c64xx_cpufreq_constrain_voltages();
+                s3c64xx_cpufreq_config_regulator();
        }
 #endif
@@ -217,8 +220,11 @@ static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
                /* Check for frequencies we can generate */
                r = clk_round_rate(armclk, freq->frequency * 1000);
                r /= 1000;
-                if (r != freq->frequency)
+                if (r != freq->frequency) {
+                        pr_debug("cpufreq: %dkHz unsupported by clock\n",
+                                 freq->frequency);
                        freq->frequency = CPUFREQ_ENTRY_INVALID;
+                }
                /* If we have no regulator then assume startup
                 * frequency is the maximum we can support. */
@@ -230,9 +236,11 @@ static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
        policy->cur = clk_get_rate(armclk) / 1000;
-        /* Pick a conservative guess in ns: we'll need ~1 I2C/SPI
+        /* Datasheet says PLL stabalisation time (if we were to use
-         * write plus clock reprogramming. */
+         * the PLLs, which we don't currently) is ~300us worst case,
-        policy->cpuinfo.transition_latency = 2 * 1000 * 1000;
+         * but add some fudge.
+         */
+        policy->cpuinfo.transition_latency = (500 * 1000) + regulator_latency;
        ret = cpufreq_frequency_table_cpuinfo(policy, s3c64xx_freq_table);
        if (ret != 0) {
diff --git a/arch/arm/plat-s3c64xx/gpiolib.c b/arch/arm/plat-s3c64xx/gpiolib.c
index 92859290ea33..778560457277 100644
--- a/arch/arm/plat-s3c64xx/gpiolib.c
+++ b/arch/arm/plat-s3c64xx/gpiolib.c
@@ -213,6 +213,11 @@ static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = {
        .get_pull       = s3c_gpio_getpull_updown,
 };
+int s3c64xx_gpio2int_gpm(struct gpio_chip *chip, unsigned pin)
+{
+        return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
+}
 static struct s3c_gpio_chip gpio_4bit[] = {
        {
                .base   = S3C64XX_GPA_BASE,
@@ -269,10 +274,16 @@ static struct s3c_gpio_chip gpio_4bit[] = {
                        .base   = S3C64XX_GPM(0),
                        .ngpio  = S3C64XX_GPIO_M_NR,
                        .label  = "GPM",
+                        .to_irq = s3c64xx_gpio2int_gpm,
                },
        },
 };
+int s3c64xx_gpio2int_gpl(struct gpio_chip *chip, unsigned pin)
+{
+        return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
+}
 static struct s3c_gpio_chip gpio_4bit2[] = {
        {
                .base   = S3C64XX_GPH_BASE + 0x4,
@@ -297,6 +308,7 @@ static struct s3c_gpio_chip gpio_4bit2[] = {
                        .base   = S3C64XX_GPL(0),
                        .ngpio  = S3C64XX_GPIO_L_NR,
                        .label  = "GPL",
+                        .to_irq = s3c64xx_gpio2int_gpl,
                },
        },
 };
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h
index c47daf7e2723..e22b49f4f982 100644
--- a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h
+++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h
@@ -36,18 +36,18 @@
 #define S3C64XX_GPC4_SPI_MISO1          (0x02 << 16)
 #define S3C64XX_GPC4_MMC2_CMD           (0x03 << 16)
-#define S3C64XX_GPC4_I2S0_V40_DO        (0x05 << 16)
+#define S3C64XX_GPC4_I2S_V40_DO0        (0x05 << 16)
 #define S3C64XX_GPC4_EINT_G2_4          (0x07 << 16)
 #define S3C64XX_GPC5_SPI_CLK1           (0x02 << 20)
 #define S3C64XX_GPC5_MMC2_CLK           (0x03 << 20)
-#define S3C64XX_GPC5_I2S1_V40_DO        (0x05 << 20)
+#define S3C64XX_GPC5_I2S_V40_DO1        (0x05 << 20)
 #define S3C64XX_GPC5_EINT_G2_5          (0x07 << 20)
 #define S3C64XX_GPC6_SPI_MOSI1          (0x02 << 24)
 #define S3C64XX_GPC6_EINT_G2_6          (0x07 << 24)
 #define S3C64XX_GPC7_SPI_nCS1           (0x02 << 28)
-#define S3C64XX_GPC7_I2S2_V40_DO        (0x05 << 28)
+#define S3C64XX_GPC7_I2S_V40_DO2        (0x05 << 28)
 #define S3C64XX_GPC7_EINT_G2_7          (0x07 << 28)
diff --git a/arch/arm/plat-s3c64xx/irq-eint.c b/arch/arm/plat-s3c64xx/irq-eint.c
index f81b7b818ba0..ebdf183a0911 100644
--- a/arch/arm/plat-s3c64xx/irq-eint.c
+++ b/arch/arm/plat-s3c64xx/irq-eint.c
@@ -65,7 +65,7 @@ static void s3c_irq_eint_maskack(unsigned int irq)
 static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
 {
        int offs = eint_offset(irq);
-        int pin;
+        int pin, pin_val;
        int shift;
        u32 ctrl, mask;
        u32 newvalue = 0;
@@ -109,7 +109,10 @@ static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
                return -1;
        }
-        shift = (offs / 2) * 4;
+        if (offs <= 15)
+                shift = (offs / 2) * 4;
+        else
+                shift = ((offs - 16) / 2) * 4;
        mask = 0x7 << shift;
        ctrl = __raw_readl(reg);
@@ -119,12 +122,18 @@ static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
        /* set the GPIO pin appropriately */
-        if (offs < 23)
+        if (offs < 16) {
                pin = S3C64XX_GPN(offs);
-        else
+                pin_val = S3C_GPIO_SFN(2);
+        } else if (offs < 23) {
+                pin = S3C64XX_GPL(offs + 8 - 16);
+                pin_val = S3C_GPIO_SFN(3);
+        } else {
                pin = S3C64XX_GPM(offs - 23);
+                pin_val = S3C_GPIO_SFN(3);
+        }
-        s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(2));
+        s3c_gpio_cfgpin(pin, pin_val);
        return 0;
 }
diff --git a/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c b/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c
index 5417123b0ac1..a58c0cc7ba5e 100644
--- a/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c
+++ b/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c
@@ -53,3 +53,23 @@ void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
        s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
        s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3));
 }
+void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
+{
+        unsigned int gpio;
+        unsigned int end;
+        end = S3C64XX_GPH(6 + width);
+        /* Set all the necessary GPH pins to special-function 1 */
+        for (gpio = S3C64XX_GPH(6); gpio < end; gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+        /* Set all the necessary GPC pins to special-function 1 */
+        for (gpio = S3C64XX_GPC(4); gpio < S3C64XX_GPC(6); gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+}
diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig
index a8a711c3c064..1608e62b0c9d 100644
--- a/arch/arm/plat-s5pc1xx/Kconfig
+++ b/arch/arm/plat-s5pc1xx/Kconfig
@@ -15,6 +15,9 @@ config PLAT_S5PC1XX
        select ARCH_REQUIRE_GPIOLIB
        select S3C_GPIO_TRACK
        select S3C_GPIO_PULL_UPDOWN
+        select S3C_GPIO_CFG_S3C24XX
+        select S3C_GPIO_CFG_S3C64XX
+        select S5P_GPIO_CFG_S5PC1XX
        help
          Base platform code for any Samsung S5PC1XX device
@@ -34,7 +37,12 @@ config CPU_S5PC100_CLOCK
 # platform specific device setup
-config S5PC100_SETUP_I2C0
+config S5PC1XX_SETUP_FB_24BPP
+        bool
+        help
+          Common setup code for S5PC1XX with an 24bpp RGB display helper.
+config S5PC1XX_SETUP_I2C0
        bool
        default y
        help
@@ -43,8 +51,14 @@ config S5PC100_SETUP_I2C0
          Note, currently since i2c0 is always compiled, this setup helper
          is always compiled with it.
-config S5PC100_SETUP_I2C1
+config S5PC1XX_SETUP_I2C1
        bool
        help
          Common setup code for i2c bus 1.
+config S5PC1XX_SETUP_SDHCI_GPIO
+        bool
+        help
+          Common setup code for SDHCI gpio.
 endif
diff --git a/arch/arm/plat-s5pc1xx/Makefile b/arch/arm/plat-s5pc1xx/Makefile
index f1ecb2c37ee2..278f26806089 100644
--- a/arch/arm/plat-s5pc1xx/Makefile
+++ b/arch/arm/plat-s5pc1xx/Makefile
@@ -13,7 +13,9 @@ obj-				:=
 obj-y                           += dev-uart.o
 obj-y                           += cpu.o
-obj-y                           += irq.o
+obj-y                           += irq.o irq-gpio.o irq-eint.o
+obj-y                           += clock.o
+obj-y                           += gpiolib.o
 # CPU support
@@ -22,5 +24,8 @@ obj-$(CONFIG_CPU_S5PC100_CLOCK)	+= s5pc100-clock.o
 # Device setup
-obj-$(CONFIG_S5PC100_SETUP_I2C0) += setup-i2c0.o
+obj-$(CONFIG_S5P_GPIO_CFG_S5PC1XX) += gpio-config.o
-obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o
+obj-$(CONFIG_S5PC1XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
+obj-$(CONFIG_S5PC1XX_SETUP_I2C0) += setup-i2c0.o
+obj-$(CONFIG_S5PC1XX_SETUP_I2C1) += setup-i2c1.o
+obj-$(CONFIG_S5PC1XX_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
diff --git a/arch/arm/plat-s5pc1xx/clock.c b/arch/arm/plat-s5pc1xx/clock.c
new file mode 100644
index 000000000000..26c21d849790
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/clock.c
@@ -0,0 +1,728 @@
+/* linux/arch/arm/plat-s5pc1xx/clock.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *
+ * S5PC1XX Base clock support
+ *
+ * Based on plat-s3c64xx/clock.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <plat/regs-clock.h>
+#include <plat/devs.h>
+#include <plat/clock.h>
+struct clk clk_27m = {
+        .name           = "clk_27m",
+        .id             = -1,
+        .rate           = 27000000,
+};
+static int clk_48m_ctrl(struct clk *clk, int enable)
+{
+        unsigned long flags;
+        u32 val;
+        /* can't rely on clock lock, this register has other usages */
+        local_irq_save(flags);
+        val = __raw_readl(S5PC100_CLKSRC1);
+        if (enable)
+                val |= S5PC100_CLKSRC1_CLK48M_MASK;
+        else
+                val &= ~S5PC100_CLKSRC1_CLK48M_MASK;
+        __raw_writel(val, S5PC100_CLKSRC1);
+        local_irq_restore(flags);
+        return 0;
+}
+struct clk clk_48m = {
+        .name           = "clk_48m",
+        .id             = -1,
+        .rate           = 48000000,
+        .enable         = clk_48m_ctrl,
+};
+struct clk clk_54m = {
+        .name           = "clk_54m",
+        .id             = -1,
+        .rate           = 54000000,
+};
+static int clk_default_setrate(struct clk *clk, unsigned long rate)
+{
+        clk->rate = rate;
+        return 0;
+}
+static int clk_dummy_enable(struct clk *clk, int enable)
+{
+        return 0;
+}
+struct clk clk_hd0 = {
+        .name           = "hclkd0",
+        .id             = -1,
+        .rate           = 0,
+        .parent         = NULL,
+        .ctrlbit        = 0,
+        .set_rate       = clk_default_setrate,
+        .enable         = clk_dummy_enable,
+};
+struct clk clk_pd0 = {
+        .name           = "pclkd0",
+        .id             = -1,
+        .rate           = 0,
+        .parent         = NULL,
+        .ctrlbit        = 0,
+        .set_rate       = clk_default_setrate,
+        .enable         = clk_dummy_enable,
+};
+static int s5pc1xx_clk_gate(void __iomem *reg, struct clk *clk, int enable)
+{
+        unsigned int ctrlbit = clk->ctrlbit;
+        u32 con;
+        con = __raw_readl(reg);
+        if (enable)
+                con |= ctrlbit;
+        else
+                con &= ~ctrlbit;
+        __raw_writel(con, reg);
+        return 0;
+}
+static int s5pc100_clk_d00_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D00, clk, enable);
+}
+static int s5pc100_clk_d01_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D01, clk, enable);
+}
+static int s5pc100_clk_d02_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D02, clk, enable);
+}
+static int s5pc100_clk_d10_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D10, clk, enable);
+}
+static int s5pc100_clk_d11_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D11, clk, enable);
+}
+static int s5pc100_clk_d12_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D12, clk, enable);
+}
+static int s5pc100_clk_d13_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D13, clk, enable);
+}
+static int s5pc100_clk_d14_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D14, clk, enable);
+}
+static int s5pc100_clk_d15_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D15, clk, enable);
+}
+static int s5pc100_clk_d20_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D20, clk, enable);
+}
+int s5pc100_sclk0_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_SCLKGATE0, clk, enable);
+}
+int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_SCLKGATE1, clk, enable);
+}
+static struct clk s5pc100_init_clocks_disable[] = {
+        {
+                .name           = "dsi",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_DSI,
+        }, {
+                .name           = "csi",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc100_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_CSI,
+        }, {
+                .name           = "ccan",
+                .id             = 0,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_CCAN0,
+        }, {
+                .name           = "ccan",
+                .id             = 1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_CCAN1,
+        }, {
+                .name           = "keypad",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_KEYIF,
+        }, {
+                .name           = "hclkd2",
+                .id             = -1,
+                .parent         = NULL,
+                .enable         = s5pc100_clk_d20_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D20_HCLKD2,
+        }, {
+                .name           = "iis-d2",
+                .id             = -1,
+                .parent         = NULL,
+                .enable         = s5pc100_clk_d20_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D20_I2SD2,
+        },
+};
+static struct clk s5pc100_init_clocks[] = {
+        /* System1 (D0_0) devices */
+        {
+                .name           = "intc",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc100_clk_d00_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D00_INTC,
+        }, {
+                .name           = "tzic",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc100_clk_d00_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D00_TZIC,
+        }, {
+                .name           = "cf-ata",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc100_clk_d00_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D00_CFCON,
+        }, {
+                .name           = "mdma",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc100_clk_d00_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D00_MDMA,
+        }, {
+                .name           = "g2d",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc100_clk_d00_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D00_G2D,
+        }, {
+                .name           = "secss",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc100_clk_d00_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D00_SECSS,
+        }, {
+                .name           = "cssys",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc100_clk_d00_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D00_CSSYS,
+        },
+        /* Memory (D0_1) devices */
+        {
+                .name           = "dmc",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc100_clk_d01_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D01_DMC,
+        }, {
+                .name           = "sromc",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc100_clk_d01_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D01_SROMC,
+        }, {
+                .name           = "onenand",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc100_clk_d01_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D01_ONENAND,
+        }, {
+                .name           = "nand",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc100_clk_d01_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D01_NFCON,
+        }, {
+                .name           = "intmem",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc100_clk_d01_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D01_INTMEM,
+        }, {
+                .name           = "ebi",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc100_clk_d01_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D01_EBI,
+        },
+        /* System2 (D0_2) devices */
+        {
+                .name           = "seckey",
+                .id             = -1,
+                .parent         = &clk_pd0,
+                .enable         = s5pc100_clk_d02_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D02_SECKEY,
+        }, {
+                .name           = "sdm",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc100_clk_d02_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D02_SDM,
+        },
+        /* File (D1_0) devices */
+        {
+                .name           = "pdma",
+                .id             = 0,
+                .parent         = &clk_h,
+                .enable         = s5pc100_clk_d10_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D10_PDMA0,
+        }, {
+                .name           = "pdma",
+                .id             = 1,
+                .parent         = &clk_h,
+                .enable         = s5pc100_clk_d10_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D10_PDMA1,
+        }, {
+                .name           = "usb-host",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc100_clk_d10_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D10_USBHOST,
+        }, {
+                .name           = "otg",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc100_clk_d10_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D10_USBOTG,
+        }, {
+                .name           = "modem",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc100_clk_d10_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D10_MODEMIF,
+        }, {
+                .name           = "hsmmc",
+                .id             = 0,
+                .parent         = &clk_48m,
+                .enable         = s5pc100_clk_d10_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D10_HSMMC0,
+        }, {
+                .name           = "hsmmc",
+                .id             = 1,
+                .parent         = &clk_48m,
+                .enable         = s5pc100_clk_d10_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D10_HSMMC1,
+        }, {
+                .name           = "hsmmc",
+                .id             = 2,
+                .parent         = &clk_48m,
+                .enable         = s5pc100_clk_d10_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D10_HSMMC2,
+        },
+        /* Multimedia1 (D1_1) devices */
+        {
+                .name           = "lcd",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_LCD,
+        }, {
+                .name           = "rotator",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_ROTATOR,
+        }, {
+                .name           = "fimc",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_FIMC0,
+        }, {
+                .name           = "fimc",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_FIMC1,
+        }, {
+                .name           = "fimc",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_FIMC2,
+        }, {
+                .name           = "jpeg",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_JPEG,
+        }, {
+                .name           = "g3d",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_G3D,
+        },
+        /* Multimedia2 (D1_2) devices */
+        {
+                .name           = "tv",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d12_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D12_TV,
+        }, {
+                .name           = "vp",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d12_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D12_VP,
+        }, {
+                .name           = "mixer",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d12_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D12_MIXER,
+        }, {
+                .name           = "hdmi",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d12_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D12_HDMI,
+        }, {
+                .name           = "mfc",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d12_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D12_MFC,
+        },
+        /* System (D1_3) devices */
+        {
+                .name           = "chipid",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d13_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D13_CHIPID,
+        }, {
+                .name           = "gpio",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d13_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D13_GPIO,
+        }, {
+                .name           = "apc",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d13_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D13_APC,
+        }, {
+                .name           = "iec",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d13_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D13_IEC,
+        }, {
+                .name           = "timers",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d13_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D13_PWM,
+        }, {
+                .name           = "systimer",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d13_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D13_SYSTIMER,
+        }, {
+                .name           = "watchdog",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d13_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D13_WDT,
+        }, {
+                .name           = "rtc",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d13_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D13_RTC,
+        },
+        /* Connectivity (D1_4) devices */
+        {
+                .name           = "uart",
+                .id             = 0,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_UART0,
+        }, {
+                .name           = "uart",
+                .id             = 1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_UART1,
+        }, {
+                .name           = "uart",
+                .id             = 2,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_UART2,
+        }, {
+                .name           = "uart",
+                .id             = 3,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_UART3,
+        }, {
+                .name           = "i2c",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_IIC,
+        }, {
+                .name           = "hdmi-i2c",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_HDMI_IIC,
+        }, {
+                .name           = "spi",
+                .id             = 0,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_SPI0,
+        }, {
+                .name           = "spi",
+                .id             = 1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_SPI1,
+        }, {
+                .name           = "spi",
+                .id             = 2,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_SPI2,
+        }, {
+                .name           = "irda",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_IRDA,
+        }, {
+                .name           = "hsitx",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_HSITX,
+        }, {
+                .name           = "hsirx",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_HSIRX,
+        },
+        /* Audio (D1_5) devices */
+        {
+                .name           = "iis",
+                .id             = 0,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_IIS0,
+        }, {
+                .name           = "iis",
+                .id             = 1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_IIS1,
+        }, {
+                .name           = "iis",
+                .id             = 2,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_IIS2,
+        }, {
+                .name           = "ac97",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_AC97,
+        }, {
+                .name           = "pcm",
+                .id             = 0,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_PCM0,
+        }, {
+                .name           = "pcm",
+                .id             = 1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_PCM1,
+        }, {
+                .name           = "spdif",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_SPDIF,
+        }, {
+                .name           = "adc",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_TSADC,
+        }, {
+                .name           = "cg",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_CG,
+        },
+        /* Audio (D2_0) devices: all disabled */
+        /* Special Clocks 0 */
+        {
+                .name           = "sclk_hpm",
+                .id             = -1,
+                .parent         = NULL,
+                .enable         = s5pc100_sclk0_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_HPM,
+        }, {
+                .name           = "sclk_onenand",
+                .id             = -1,
+                .parent         = NULL,
+                .enable         = s5pc100_sclk0_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_ONENAND,
+        }, {
+                .name           = "spi_48",
+                .id             = 0,
+                .parent         = &clk_48m,
+                .enable         = s5pc100_sclk0_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_SPI0_48,
+        }, {
+                .name           = "spi_48",
+                .id             = 1,
+                .parent         = &clk_48m,
+                .enable         = s5pc100_sclk0_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_SPI1_48,
+        }, {
+                .name           = "spi_48",
+                .id             = 2,
+                .parent         = &clk_48m,
+                .enable         = s5pc100_sclk0_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_SPI2_48,
+        }, {
+                .name           = "mmc_48",
+                .id             = 0,
+                .parent         = &clk_48m,
+                .enable         = s5pc100_sclk0_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_MMC0_48,
+        }, {
+                .name           = "mmc_48",
+                .id             = 1,
+                .parent         = &clk_48m,
+                .enable         = s5pc100_sclk0_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_MMC1_48,
+        }, {
+                .name           = "mmc_48",
+                .id             = 2,
+                .parent         = &clk_48m,
+                .enable         = s5pc100_sclk0_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_MMC2_48,
+        },
+        /* Special Clocks 1 */
+};
+static struct clk *clks[] __initdata = {
+        &clk_ext,
+        &clk_epll,
+        &clk_27m,
+        &clk_48m,
+        &clk_54m,
+};
+void __init s5pc1xx_register_clocks(void)
+{
+        struct clk *clkp;
+        int ret;
+        int ptr;
+        int size;
+        s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
+        clkp = s5pc100_init_clocks;
+        size = ARRAY_SIZE(s5pc100_init_clocks);
+        for (ptr = 0; ptr < size; ptr++, clkp++) {
+                ret = s3c24xx_register_clock(clkp);
+                if (ret < 0) {
+                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
+                               clkp->name, ret);
+                }
+        }
+        clkp = s5pc100_init_clocks_disable;
+        size = ARRAY_SIZE(s5pc100_init_clocks_disable);
+        for (ptr = 0; ptr < size; ptr++, clkp++) {
+                ret = s3c24xx_register_clock(clkp);
+                if (ret < 0) {
+                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
+                               clkp->name, ret);
+                }
+                (clkp->enable)(clkp, 0);
+        }
+        s3c_pwmclk_init();
+}
diff --git a/arch/arm/plat-s5pc1xx/cpu.c b/arch/arm/plat-s5pc1xx/cpu.c
index 715a7330794d..02baeaa2a121 100644
--- a/arch/arm/plat-s5pc1xx/cpu.c
+++ b/arch/arm/plat-s5pc1xx/cpu.c
@@ -55,6 +55,16 @@ static struct cpu_table cpu_ids[] __initdata = {
 static struct map_desc s5pc1xx_iodesc[] __initdata = {
        {
+                .virtual        = (unsigned long)S5PC1XX_VA_CLK_OTHER,
+                .pfn            = __phys_to_pfn(S5PC1XX_PA_CLK_OTHER),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5PC1XX_VA_GPIO,
+                .pfn            = __phys_to_pfn(S5PC100_PA_GPIO),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
                .virtual        = (unsigned long)S5PC1XX_VA_CHIPID,
                .pfn            = __phys_to_pfn(S5PC1XX_PA_CHIPID),
                .length         = SZ_16,
diff --git a/arch/arm/plat-s5pc1xx/gpio-config.c b/arch/arm/plat-s5pc1xx/gpio-config.c
new file mode 100644
index 000000000000..bba675df9c75
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/gpio-config.c
@@ -0,0 +1,62 @@
+/* linux/arch/arm/plat-s5pc1xx/gpio-config.c
+ *
+ * Copyright 2009 Samsung Electronics
+ *
+ * S5PC1XX GPIO Configuration.
+ *
+ * Based on plat-s3c64xx/gpio-config.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+#include <mach/gpio-core.h>
+#include <plat/gpio-cfg-s5pc1xx.h>
+s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin, unsigned int off)
+{
+        struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
+        void __iomem *reg;
+        int shift = off * 2;
+        u32 drvstr;
+        if (!chip)
+                return -EINVAL;
+        reg = chip->base + 0x0C;
+        drvstr = __raw_readl(reg);
+        drvstr = 0xffff & (0x3 << shift);
+        drvstr = drvstr >> shift;
+        return (__force s5p_gpio_drvstr_t)drvstr;
+}
+EXPORT_SYMBOL(s5p_gpio_get_drvstr);
+int s5p_gpio_set_drvstr(unsigned int pin, unsigned int off,
+                        s5p_gpio_drvstr_t drvstr)
+{
+        struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
+        void __iomem *reg;
+        int shift = off * 2;
+        u32 tmp;
+        if (!chip)
+                return -EINVAL;
+        reg = chip->base + 0x0C;
+        tmp = __raw_readl(reg);
+        tmp |= drvstr << shift;
+        __raw_writel(tmp, reg);
+        return 0;
+}
+EXPORT_SYMBOL(s5p_gpio_set_drvstr);
diff --git a/arch/arm/plat-s5pc1xx/gpiolib.c b/arch/arm/plat-s5pc1xx/gpiolib.c
new file mode 100644
index 000000000000..facb410e7a71
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/gpiolib.c
@@ -0,0 +1,503 @@
+/*
+ * arch/arm/plat-s5pc1xx/gpiolib.c
+ *
+ *  Copyright 2009 Samsung Electronics Co
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * S5PC1XX - GPIOlib support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <mach/map.h>
+#include <mach/gpio-core.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-helpers.h>
+#include <plat/regs-gpio.h>
+/* S5PC100 GPIO bank summary:
+ *
+ * Bank GPIOs   Style   INT Type
+ * A0   8       4Bit    GPIO_INT0
+ * A1   5       4Bit    GPIO_INT1
+ * B    8       4Bit    GPIO_INT2
+ * C    5       4Bit    GPIO_INT3
+ * D    7       4Bit    GPIO_INT4
+ * E0   8       4Bit    GPIO_INT5
+ * E1   6       4Bit    GPIO_INT6
+ * F0   8       4Bit    GPIO_INT7
+ * F1   8       4Bit    GPIO_INT8
+ * F2   8       4Bit    GPIO_INT9
+ * F3   4       4Bit    GPIO_INT10
+ * G0   8       4Bit    GPIO_INT11
+ * G1   3       4Bit    GPIO_INT12
+ * G2   7       4Bit    GPIO_INT13
+ * G3   7       4Bit    GPIO_INT14
+ * H0   8       4Bit    WKUP_INT
+ * H1   8       4Bit    WKUP_INT
+ * H2   8       4Bit    WKUP_INT
+ * H3   8       4Bit    WKUP_INT
+ * I    8       4Bit    GPIO_INT15
+ * J0   8       4Bit    GPIO_INT16
+ * J1   5       4Bit    GPIO_INT17
+ * J2   8       4Bit    GPIO_INT18
+ * J3   8       4Bit    GPIO_INT19
+ * J4   4       4Bit    GPIO_INT20
+ * K0   8       4Bit    None
+ * K1   6       4Bit    None
+ * K2   8       4Bit    None
+ * K3   8       4Bit    None
+ * L0   8       4Bit    None
+ * L1   8       4Bit    None
+ * L2   8       4Bit    None
+ * L3   8       4Bit    None
+ */
+#define OFF_GPCON       (0x00)
+#define OFF_GPDAT       (0x04)
+#define con_4bit_shift(__off) ((__off) * 4)
+#if 1
+#define gpio_dbg(x...) do { } while (0)
+#else
+#define gpio_dbg(x...) printk(KERN_DEBUG x)
+#endif
+/* The s5pc1xx_gpiolib routines are to control the gpio banks where
+ * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
+ * following example:
+ *
+ * base + 0x00: Control register, 4 bits per gpio
+ *              gpio n: 4 bits starting at (4*n)
+ *              0000 = input, 0001 = output, others mean special-function
+ * base + 0x04: Data register, 1 bit per gpio
+ *              bit n: data bit n
+ *
+ * Note, since the data register is one bit per gpio and is at base + 0x4
+ * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of
+ * the output.
+ */
+static int s5pc1xx_gpiolib_input(struct gpio_chip *chip, unsigned offset)
+{
+        struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
+        void __iomem *base = ourchip->base;
+        unsigned long con;
+        con = __raw_readl(base + OFF_GPCON);
+        con &= ~(0xf << con_4bit_shift(offset));
+        __raw_writel(con, base + OFF_GPCON);
+        gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con);
+        return 0;
+}
+static int s5pc1xx_gpiolib_output(struct gpio_chip *chip,
+                                       unsigned offset, int value)
+{
+        struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
+        void __iomem *base = ourchip->base;
+        unsigned long con;
+        unsigned long dat;
+        con = __raw_readl(base + OFF_GPCON);
+        con &= ~(0xf << con_4bit_shift(offset));
+        con |= 0x1 << con_4bit_shift(offset);
+        dat = __raw_readl(base + OFF_GPDAT);
+        if (value)
+                dat |= 1 << offset;
+        else
+                dat &= ~(1 << offset);
+        __raw_writel(dat, base + OFF_GPDAT);
+        __raw_writel(con, base + OFF_GPCON);
+        __raw_writel(dat, base + OFF_GPDAT);
+        gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
+        return 0;
+}
+static int s5pc1xx_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
+{
+        return S3C_IRQ_GPIO(chip->base + offset);
+}
+static int s5pc1xx_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset)
+{
+        int base;
+        base = chip->base - S5PC100_GPH0(0);
+        if (base == 0)
+                return IRQ_EINT(offset);
+        base = chip->base - S5PC100_GPH1(0);
+        if (base == 0)
+                return IRQ_EINT(8 + offset);
+        base = chip->base - S5PC100_GPH2(0);
+        if (base == 0)
+                return IRQ_EINT(16 + offset);
+        base = chip->base - S5PC100_GPH3(0);
+        if (base == 0)
+                return IRQ_EINT(24 + offset);
+        return -EINVAL;
+}
+static struct s3c_gpio_cfg gpio_cfg = {
+        .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
+        .set_pull       = s3c_gpio_setpull_updown,
+        .get_pull       = s3c_gpio_getpull_updown,
+};
+static struct s3c_gpio_cfg gpio_cfg_eint = {
+        .cfg_eint       = 0xf,
+        .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
+        .set_pull       = s3c_gpio_setpull_updown,
+        .get_pull       = s3c_gpio_getpull_updown,
+};
+static struct s3c_gpio_cfg gpio_cfg_noint = {
+        .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
+        .set_pull       = s3c_gpio_setpull_updown,
+        .get_pull       = s3c_gpio_getpull_updown,
+};
+static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
+        {
+                .base   = S5PC100_GPA0_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPA0(0),
+                        .ngpio  = S5PC100_GPIO_A0_NR,
+                        .label  = "GPA0",
+                },
+        }, {
+                .base   = S5PC100_GPA1_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPA1(0),
+                        .ngpio  = S5PC100_GPIO_A1_NR,
+                        .label  = "GPA1",
+                },
+        }, {
+                .base   = S5PC100_GPB_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPB(0),
+                        .ngpio  = S5PC100_GPIO_B_NR,
+                        .label  = "GPB",
+                },
+        }, {
+                .base   = S5PC100_GPC_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPC(0),
+                        .ngpio  = S5PC100_GPIO_C_NR,
+                        .label  = "GPC",
+                },
+        }, {
+                .base   = S5PC100_GPD_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPD(0),
+                        .ngpio  = S5PC100_GPIO_D_NR,
+                        .label  = "GPD",
+                },
+        }, {
+                .base   = S5PC100_GPE0_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPE0(0),
+                        .ngpio  = S5PC100_GPIO_E0_NR,
+                        .label  = "GPE0",
+                },
+        }, {
+                .base   = S5PC100_GPE1_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPE1(0),
+                        .ngpio  = S5PC100_GPIO_E1_NR,
+                        .label  = "GPE1",
+                },
+        }, {
+                .base   = S5PC100_GPF0_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPF0(0),
+                        .ngpio  = S5PC100_GPIO_F0_NR,
+                        .label  = "GPF0",
+                },
+        }, {
+                .base   = S5PC100_GPF1_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPF1(0),
+                        .ngpio  = S5PC100_GPIO_F1_NR,
+                        .label  = "GPF1",
+                },
+        }, {
+                .base   = S5PC100_GPF2_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPF2(0),
+                        .ngpio  = S5PC100_GPIO_F2_NR,
+                        .label  = "GPF2",
+                },
+        }, {
+                .base   = S5PC100_GPF3_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPF3(0),
+                        .ngpio  = S5PC100_GPIO_F3_NR,
+                        .label  = "GPF3",
+                },
+        }, {
+                .base   = S5PC100_GPG0_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPG0(0),
+                        .ngpio  = S5PC100_GPIO_G0_NR,
+                        .label  = "GPG0",
+                },
+        }, {
+                .base   = S5PC100_GPG1_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPG1(0),
+                        .ngpio  = S5PC100_GPIO_G1_NR,
+                        .label  = "GPG1",
+                },
+        }, {
+                .base   = S5PC100_GPG2_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPG2(0),
+                        .ngpio  = S5PC100_GPIO_G2_NR,
+                        .label  = "GPG2",
+                },
+        }, {
+                .base   = S5PC100_GPG3_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPG3(0),
+                        .ngpio  = S5PC100_GPIO_G3_NR,
+                        .label  = "GPG3",
+                },
+        }, {
+                .base   = S5PC100_GPH0_BASE,
+                .config = &gpio_cfg_eint,
+                .chip   = {
+                        .base   = S5PC100_GPH0(0),
+                        .ngpio  = S5PC100_GPIO_H0_NR,
+                        .label  = "GPH0",
+                },
+        }, {
+                .base   = S5PC100_GPH1_BASE,
+                .config = &gpio_cfg_eint,
+                .chip   = {
+                        .base   = S5PC100_GPH1(0),
+                        .ngpio  = S5PC100_GPIO_H1_NR,
+                        .label  = "GPH1",
+                },
+        }, {
+                .base   = S5PC100_GPH2_BASE,
+                .config = &gpio_cfg_eint,
+                .chip   = {
+                        .base   = S5PC100_GPH2(0),
+                        .ngpio  = S5PC100_GPIO_H2_NR,
+                        .label  = "GPH2",
+                },
+        }, {
+                .base   = S5PC100_GPH3_BASE,
+                .config = &gpio_cfg_eint,
+                .chip   = {
+                        .base   = S5PC100_GPH3(0),
+                        .ngpio  = S5PC100_GPIO_H3_NR,
+                        .label  = "GPH3",
+                },
+        }, {
+                .base   = S5PC100_GPI_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPI(0),
+                        .ngpio  = S5PC100_GPIO_I_NR,
+                        .label  = "GPI",
+                },
+        }, {
+                .base   = S5PC100_GPJ0_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPJ0(0),
+                        .ngpio  = S5PC100_GPIO_J0_NR,
+                        .label  = "GPJ0",
+                },
+        }, {
+                .base   = S5PC100_GPJ1_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPJ1(0),
+                        .ngpio  = S5PC100_GPIO_J1_NR,
+                        .label  = "GPJ1",
+                },
+        }, {
+                .base   = S5PC100_GPJ2_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPJ2(0),
+                        .ngpio  = S5PC100_GPIO_J2_NR,
+                        .label  = "GPJ2",
+                },
+        }, {
+                .base   = S5PC100_GPJ3_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPJ3(0),
+                        .ngpio  = S5PC100_GPIO_J3_NR,
+                        .label  = "GPJ3",
+                },
+        }, {
+                .base   = S5PC100_GPJ4_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPJ4(0),
+                        .ngpio  = S5PC100_GPIO_J4_NR,
+                        .label  = "GPJ4",
+                },
+        }, {
+                .base   = S5PC100_GPK0_BASE,
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PC100_GPK0(0),
+                        .ngpio  = S5PC100_GPIO_K0_NR,
+                        .label  = "GPK0",
+                },
+        }, {
+                .base   = S5PC100_GPK1_BASE,
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PC100_GPK1(0),
+                        .ngpio  = S5PC100_GPIO_K1_NR,
+                        .label  = "GPK1",
+                },
+        }, {
+                .base   = S5PC100_GPK2_BASE,
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PC100_GPK2(0),
+                        .ngpio  = S5PC100_GPIO_K2_NR,
+                        .label  = "GPK2",
+                },
+        }, {
+                .base   = S5PC100_GPK3_BASE,
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PC100_GPK3(0),
+                        .ngpio  = S5PC100_GPIO_K3_NR,
+                        .label  = "GPK3",
+                },
+        }, {
+                .base   = S5PC100_GPL0_BASE,
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PC100_GPL0(0),
+                        .ngpio  = S5PC100_GPIO_L0_NR,
+                        .label  = "GPL0",
+                },
+        }, {
+                .base   = S5PC100_GPL1_BASE,
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PC100_GPL1(0),
+                        .ngpio  = S5PC100_GPIO_L1_NR,
+                        .label  = "GPL1",
+                },
+        }, {
+                .base   = S5PC100_GPL2_BASE,
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PC100_GPL2(0),
+                        .ngpio  = S5PC100_GPIO_L2_NR,
+                        .label  = "GPL2",
+                },
+        }, {
+                .base   = S5PC100_GPL3_BASE,
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PC100_GPL3(0),
+                        .ngpio  = S5PC100_GPIO_L3_NR,
+                        .label  = "GPL3",
+                },
+        }, {
+                .base   = S5PC100_GPL4_BASE,
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PC100_GPL4(0),
+                        .ngpio  = S5PC100_GPIO_L4_NR,
+                        .label  = "GPL4",
+                },
+        },
+};
+/* FIXME move from irq-gpio.c */
+extern struct irq_chip s5pc1xx_gpioint;
+extern void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc);
+static __init void s5pc1xx_gpiolib_link(struct s3c_gpio_chip *chip)
+{
+        chip->chip.direction_input = s5pc1xx_gpiolib_input;
+        chip->chip.direction_output = s5pc1xx_gpiolib_output;
+        chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
+        /* Interrupt */
+        if (chip->config == &gpio_cfg) {
+                int i, irq;
+                chip->chip.to_irq = s5pc1xx_gpiolib_to_irq;
+                for (i = 0;  i < chip->chip.ngpio; i++) {
+                        irq = S3C_IRQ_GPIO_BASE + chip->chip.base + i;
+                        set_irq_chip(irq, &s5pc1xx_gpioint);
+                        set_irq_data(irq, &chip->chip);
+                        set_irq_handler(irq, handle_level_irq);
+                        set_irq_flags(irq, IRQF_VALID);
+                }
+        } else if (chip->config == &gpio_cfg_eint)
+                chip->chip.to_irq = s5pc1xx_gpiolib_to_eint;
+}
+static __init void s5pc1xx_gpiolib_add(struct s3c_gpio_chip *chips,
+                                       int nr_chips,
+                                       void (*fn)(struct s3c_gpio_chip *))
+{
+        for (; nr_chips > 0; nr_chips--, chips++) {
+                if (fn)
+                        (fn)(chips);
+                s3c_gpiolib_add(chips);
+        }
+}
+static __init int s5pc1xx_gpiolib_init(void)
+{
+        struct s3c_gpio_chip *chips;
+        int nr_chips;
+                chips = s5pc100_gpio_chips;
+                nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
+        s5pc1xx_gpiolib_add(chips, nr_chips, s5pc1xx_gpiolib_link);
+        /* Interrupt */
+        set_irq_chained_handler(IRQ_GPIOINT, s5pc1xx_irq_gpioint_handler);
+        return 0;
+}
+core_initcall(s5pc1xx_gpiolib_init);
diff --git a/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg-s5pc1xx.h b/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg-s5pc1xx.h
new file mode 100644
index 000000000000..72ad59f61efc
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg-s5pc1xx.h
@@ -0,0 +1,32 @@
+/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg.h
+ *
+ * Copyright 2009 Samsung Electronic
+ *
+ * S5PC1XX Platform - GPIO pin configuration
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+/* This file contains the necessary definitions to get the basic gpio
+ * pin configuration done such as setting a pin to input or output or
+ * changing the pull-{up,down} configurations.
+ */
+#ifndef __GPIO_CFG_S5PC1XX_H
+#define __GPIO_CFG_S5PC1XX_H __FILE__
+typedef unsigned int __bitwise__ s5p_gpio_drvstr_t;
+#define S5P_GPIO_DRVSTR_LV1     0x00
+#define S5P_GPIO_DRVSTR_LV2     0x01
+#define S5P_GPIO_DRVSTR_LV3     0x10
+#define S5P_GPIO_DRVSTR_LV4     0x11
+extern s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin, unsigned int off);
+extern int s5p_gpio_set_drvstr(unsigned int pin, unsigned int off,
+                        s5p_gpio_drvstr_t drvstr);
+#endif /* __GPIO_CFG_S5PC1XX_H */
diff --git a/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h b/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h
new file mode 100644
index 000000000000..33ad267e8477
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h
@@ -0,0 +1,44 @@
+/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-eint.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *
+ * External Interrupt (GPH0 ~ GPH3) control register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#define S5PC1XX_WKUP_INT_CON0_7         (S5PC1XX_EINT_BASE + 0x0)
+#define S5PC1XX_WKUP_INT_CON8_15        (S5PC1XX_EINT_BASE + 0x4)
+#define S5PC1XX_WKUP_INT_CON16_23       (S5PC1XX_EINT_BASE + 0x8)
+#define S5PC1XX_WKUP_INT_CON24_31       (S5PC1XX_EINT_BASE + 0xC)
+#define S5PC1XX_WKUP_INT_CON(x)         (S5PC1XX_WKUP_INT_CON0_7 + (x * 0x4))
+#define S5PC1XX_WKUP_INT_FLTCON0_3      (S5PC1XX_EINT_BASE + 0x80)
+#define S5PC1XX_WKUP_INT_FLTCON4_7      (S5PC1XX_EINT_BASE + 0x84)
+#define S5PC1XX_WKUP_INT_FLTCON8_11     (S5PC1XX_EINT_BASE + 0x88)
+#define S5PC1XX_WKUP_INT_FLTCON12_15    (S5PC1XX_EINT_BASE + 0x8C)
+#define S5PC1XX_WKUP_INT_FLTCON16_19    (S5PC1XX_EINT_BASE + 0x90)
+#define S5PC1XX_WKUP_INT_FLTCON20_23    (S5PC1XX_EINT_BASE + 0x94)
+#define S5PC1XX_WKUP_INT_FLTCON24_27    (S5PC1XX_EINT_BASE + 0x98)
+#define S5PC1XX_WKUP_INT_FLTCON28_31    (S5PC1XX_EINT_BASE + 0x9C)
+#define S5PC1XX_WKUP_INT_FLTCON(x)      (S5PC1XX_WKUP_INT_FLTCON0_3 + (x * 0x4))
+#define S5PC1XX_WKUP_INT_MASK0_7        (S5PC1XX_EINT_BASE + 0x100)
+#define S5PC1XX_WKUP_INT_MASK8_15       (S5PC1XX_EINT_BASE + 0x104)
+#define S5PC1XX_WKUP_INT_MASK16_23      (S5PC1XX_EINT_BASE + 0x108)
+#define S5PC1XX_WKUP_INT_MASK24_31      (S5PC1XX_EINT_BASE + 0x10C)
+#define S5PC1XX_WKUP_INT_MASK(x)        (S5PC1XX_WKUP_INT_MASK0_7 + (x * 0x4))
+#define S5PC1XX_WKUP_INT_PEND0_7        (S5PC1XX_EINT_BASE + 0x140)
+#define S5PC1XX_WKUP_INT_PEND8_15       (S5PC1XX_EINT_BASE + 0x144)
+#define S5PC1XX_WKUP_INT_PEND16_23      (S5PC1XX_EINT_BASE + 0x148)
+#define S5PC1XX_WKUP_INT_PEND24_31      (S5PC1XX_EINT_BASE + 0x14C)
+#define S5PC1XX_WKUP_INT_PEND(x)        (S5PC1XX_WKUP_INT_PEND0_7 + (x * 0x4))
+#define S5PC1XX_WKUP_INT_LOWLEV         (0x00)
+#define S5PC1XX_WKUP_INT_HILEV          (0x01)
+#define S5PC1XX_WKUP_INT_FALLEDGE       (0x02)
+#define S5PC1XX_WKUP_INT_RISEEDGE       (0x03)
+#define S5PC1XX_WKUP_INT_BOTHEDGE       (0x04)
diff --git a/arch/arm/plat-s5pc1xx/include/plat/irqs.h b/arch/arm/plat-s5pc1xx/include/plat/irqs.h
index f07d8c3b25d6..ef8736366f0d 100644
--- a/arch/arm/plat-s5pc1xx/include/plat/irqs.h
+++ b/arch/arm/plat-s5pc1xx/include/plat/irqs.h
@@ -171,12 +171,21 @@
 #define IRQ_SDMIRQ              S5PC1XX_IRQ_VIC2(30)
 #define IRQ_SDMFIQ              S5PC1XX_IRQ_VIC2(31)
+/* External interrupt */
 #define S3C_IRQ_EINT_BASE       (IRQ_SDMFIQ + 1)
-#define S3C_EINT(x)             ((x) + S3C_IRQ_EINT_BASE)
+#define S3C_EINT(x)             (S3C_IRQ_EINT_BASE + (x - 16))
-#define IRQ_EINT(x)             S3C_EINT(x)
+#define IRQ_EINT(x)             (x < 16 ? IRQ_EINT0 + x : S3C_EINT(x))
+#define IRQ_EINT_BIT(x)         (x < IRQ_EINT16_31 ? x - IRQ_EINT0 : x - S3C_EINT(0))
-#define NR_IRQS                 (IRQ_EINT(31)+1)
+/* GPIO interrupt */
+#define S3C_IRQ_GPIO_BASE       (IRQ_EINT(31) + 1)
+#define S3C_IRQ_GPIO(x)         (S3C_IRQ_GPIO_BASE + (x))
+/*
+ * Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs
+ */
+#define NR_IRQS                 (S3C_IRQ_GPIO(320) + 1)
 #endif /* __ASM_PLAT_S5PC1XX_IRQS_H */
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
index 75c8390cb827..c5cc86e92d65 100644
--- a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
+++ b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
@@ -13,68 +13,69 @@
 #ifndef __PLAT_REGS_CLOCK_H
 #define __PLAT_REGS_CLOCK_H __FILE__
-#define S5PC1XX_CLKREG(x)               (S5PC1XX_VA_CLK + (x))
+#define S5PC100_CLKREG(x)               (S5PC1XX_VA_CLK + (x))
+#define S5PC100_CLKREG_OTHER(x)         (S5PC1XX_VA_CLK_OTHER + (x))
-#define S5PC1XX_APLL_LOCK               S5PC1XX_CLKREG(0x00)
-#define S5PC1XX_MPLL_LOCK               S5PC1XX_CLKREG(0x04)
+/* s5pc100 register for clock */
-#define S5PC1XX_EPLL_LOCK               S5PC1XX_CLKREG(0x08)
+#define S5PC100_APLL_LOCK               S5PC100_CLKREG(0x00)
-#define S5PC100_HPLL_LOCK               S5PC1XX_CLKREG(0x0C)
+#define S5PC100_MPLL_LOCK               S5PC100_CLKREG(0x04)
+#define S5PC100_EPLL_LOCK               S5PC100_CLKREG(0x08)
-#define S5PC1XX_APLL_CON                S5PC1XX_CLKREG(0x100)
+#define S5PC100_HPLL_LOCK               S5PC100_CLKREG(0x0C)
-#define S5PC1XX_MPLL_CON                S5PC1XX_CLKREG(0x104)
-#define S5PC1XX_EPLL_CON                S5PC1XX_CLKREG(0x108)
+#define S5PC100_APLL_CON                S5PC100_CLKREG(0x100)
-#define S5PC100_HPLL_CON                S5PC1XX_CLKREG(0x10C)
+#define S5PC100_MPLL_CON                S5PC100_CLKREG(0x104)
+#define S5PC100_EPLL_CON                S5PC100_CLKREG(0x108)
-#define S5PC1XX_CLK_SRC0                S5PC1XX_CLKREG(0x200)
+#define S5PC100_HPLL_CON                S5PC100_CLKREG(0x10C)
-#define S5PC1XX_CLK_SRC1                S5PC1XX_CLKREG(0x204)
-#define S5PC1XX_CLK_SRC2                S5PC1XX_CLKREG(0x208)
+#define S5PC100_CLKSRC0                 S5PC100_CLKREG(0x200)
-#define S5PC1XX_CLK_SRC3                S5PC1XX_CLKREG(0x20C)
+#define S5PC100_CLKSRC1                 S5PC100_CLKREG(0x204)
+#define S5PC100_CLKSRC2                 S5PC100_CLKREG(0x208)
-#define S5PC1XX_CLK_DIV0                S5PC1XX_CLKREG(0x300)
+#define S5PC100_CLKSRC3                 S5PC100_CLKREG(0x20C)
-#define S5PC1XX_CLK_DIV1                S5PC1XX_CLKREG(0x304)
-#define S5PC1XX_CLK_DIV2                S5PC1XX_CLKREG(0x308)
+#define S5PC100_CLKDIV0                 S5PC100_CLKREG(0x300)
-#define S5PC1XX_CLK_DIV3                S5PC1XX_CLKREG(0x30C)
+#define S5PC100_CLKDIV1                 S5PC100_CLKREG(0x304)
-#define S5PC1XX_CLK_DIV4                S5PC1XX_CLKREG(0x310)
+#define S5PC100_CLKDIV2                 S5PC100_CLKREG(0x308)
+#define S5PC100_CLKDIV3                 S5PC100_CLKREG(0x30C)
-#define S5PC100_CLK_OUT                 S5PC1XX_CLKREG(0x400)
+#define S5PC100_CLKDIV4                 S5PC100_CLKREG(0x310)
-#define S5PC100_CLKGATE_D00             S5PC1XX_CLKREG(0x500)
+#define S5PC100_CLK_OUT                 S5PC100_CLKREG(0x400)
-#define S5PC100_CLKGATE_D01             S5PC1XX_CLKREG(0x504)
-#define S5PC100_CLKGATE_D02             S5PC1XX_CLKREG(0x508)
+#define S5PC100_CLKGATE_D00             S5PC100_CLKREG(0x500)
+#define S5PC100_CLKGATE_D01             S5PC100_CLKREG(0x504)
-#define S5PC100_CLKGATE_D10             S5PC1XX_CLKREG(0x520)
+#define S5PC100_CLKGATE_D02             S5PC100_CLKREG(0x508)
-#define S5PC100_CLKGATE_D11             S5PC1XX_CLKREG(0x524)
-#define S5PC100_CLKGATE_D12             S5PC1XX_CLKREG(0x528)
+#define S5PC100_CLKGATE_D10             S5PC100_CLKREG(0x520)
-#define S5PC100_CLKGATE_D13             S5PC1XX_CLKREG(0x52C)
+#define S5PC100_CLKGATE_D11             S5PC100_CLKREG(0x524)
-#define S5PC100_CLKGATE_D14             S5PC1XX_CLKREG(0x530)
+#define S5PC100_CLKGATE_D12             S5PC100_CLKREG(0x528)
-#define S5PC100_CLKGATE_D15             S5PC1XX_CLKREG(0x534)
+#define S5PC100_CLKGATE_D13             S5PC100_CLKREG(0x52C)
+#define S5PC100_CLKGATE_D14             S5PC100_CLKREG(0x530)
-#define S5PC100_CLKGATE_D20             S5PC1XX_CLKREG(0x540)
+#define S5PC100_CLKGATE_D15             S5PC100_CLKREG(0x534)
-#define S5PC100_SCLKGATE0               S5PC1XX_CLKREG(0x560)
+#define S5PC100_CLKGATE_D20             S5PC100_CLKREG(0x540)
-#define S5PC100_SCLKGATE1               S5PC1XX_CLKREG(0x564)
+#define S5PC100_SCLKGATE0               S5PC100_CLKREG(0x560)
-#define S5PC100_OTHERS          S5PC1XX_CLKREG(0x8200)
+#define S5PC100_SCLKGATE1               S5PC100_CLKREG(0x564)
-#define S5PC1XX_EPLL_EN     (1<<31)
+/* EPLL_CON */
-#define S5PC1XX_EPLL_MASK   0xffffffff
+#define S5PC100_EPLL_EN                 (1<<31)
-#define S5PC1XX_EPLLVAL(_m, _p, _s)   ((_m) << 16 | ((_p) << 8) | ((_s)))
+#define S5PC100_EPLL_MASK               0xffffffff
+#define S5PC100_EPLLVAL(_m, _p, _s)     ((_m) << 16 | ((_p) << 8) | ((_s)))
 /* CLKSRC0 */
-#define S5PC1XX_CLKSRC0_APLL_MASK               (0x1<<0)
+#define S5PC100_CLKSRC0_APLL_MASK               (0x1<<0)
-#define S5PC1XX_CLKSRC0_APLL_SHIFT              (0)
+#define S5PC100_CLKSRC0_APLL_SHIFT              (0)
-#define S5PC1XX_CLKSRC0_MPLL_MASK               (0x1<<4)
+#define S5PC100_CLKSRC0_MPLL_MASK               (0x1<<4)
-#define S5PC1XX_CLKSRC0_MPLL_SHIFT              (4)
+#define S5PC100_CLKSRC0_MPLL_SHIFT              (4)
-#define S5PC1XX_CLKSRC0_EPLL_MASK               (0x1<<8)
+#define S5PC100_CLKSRC0_EPLL_MASK               (0x1<<8)
-#define S5PC1XX_CLKSRC0_EPLL_SHIFT              (8)
+#define S5PC100_CLKSRC0_EPLL_SHIFT              (8)
 #define S5PC100_CLKSRC0_HPLL_MASK               (0x1<<12)
 #define S5PC100_CLKSRC0_HPLL_SHIFT              (12)
 #define S5PC100_CLKSRC0_AMMUX_MASK              (0x1<<16)
 #define S5PC100_CLKSRC0_AMMUX_SHIFT             (16)
 #define S5PC100_CLKSRC0_HREF_MASK               (0x1<<20)
 #define S5PC100_CLKSRC0_HREF_SHIFT              (20)
-#define S5PC1XX_CLKSRC0_ONENAND_MASK    (0x1<<24)
+#define S5PC100_CLKSRC0_ONENAND_MASK    (0x1<<24)
-#define S5PC1XX_CLKSRC0_ONENAND_SHIFT   (24)
+#define S5PC100_CLKSRC0_ONENAND_SHIFT   (24)
 /* CLKSRC1 */
@@ -127,10 +128,9 @@
 #define S5PC100_CLKSRC3_SPDIF_MASK              (0x3<<24)
 #define S5PC100_CLKSRC3_SPDIF_SHIFT             (24)
 /* CLKDIV0 */
-#define S5PC1XX_CLKDIV0_APLL_MASK               (0x1<<0)
+#define S5PC100_CLKDIV0_APLL_MASK               (0x1<<0)
-#define S5PC1XX_CLKDIV0_APLL_SHIFT              (0)
+#define S5PC100_CLKDIV0_APLL_SHIFT              (0)
 #define S5PC100_CLKDIV0_ARM_MASK                (0x7<<4)
 #define S5PC100_CLKDIV0_ARM_SHIFT               (4)
 #define S5PC100_CLKDIV0_D0_MASK         (0x7<<8)
@@ -141,8 +141,8 @@
 #define S5PC100_CLKDIV0_SECSS_SHIFT             (16)
 /* CLKDIV1 */
-#define S5PC100_CLKDIV1_AM_MASK         (0x7<<0)
+#define S5PC100_CLKDIV1_APLL2_MASK              (0x7<<0)
-#define S5PC100_CLKDIV1_AM_SHIFT                (0)
+#define S5PC100_CLKDIV1_APLL2_SHIFT             (0)
 #define S5PC100_CLKDIV1_MPLL_MASK               (0x3<<4)
 #define S5PC100_CLKDIV1_MPLL_SHIFT              (4)
 #define S5PC100_CLKDIV1_MPLL2_MASK              (0x1<<8)
@@ -202,7 +202,6 @@
 #define S5PC100_CLKDIV4_AUDIO2_MASK             (0xf<<20)
 #define S5PC100_CLKDIV4_AUDIO2_SHIFT    (20)
 /* HCLKD0/PCLKD0 Clock Gate 0 Registers */
 #define S5PC100_CLKGATE_D00_INTC                (1<<0)
 #define S5PC100_CLKGATE_D00_TZIC                (1<<1)
@@ -295,8 +294,8 @@
 #define S5PC100_CLKGATE_D20_I2SD2               (1<<1)
 /* Special Clock Gate 0 Registers */
-#define S5PC1XX_CLKGATE_SCLK0_HPM               (1<<0)
+#define S5PC100_CLKGATE_SCLK0_HPM               (1<<0)
-#define S5PC1XX_CLKGATE_SCLK0_PWI               (1<<1)
+#define S5PC100_CLKGATE_SCLK0_PWI               (1<<1)
 #define S5PC100_CLKGATE_SCLK0_ONENAND   (1<<2)
 #define S5PC100_CLKGATE_SCLK0_UART              (1<<3)
 #define S5PC100_CLKGATE_SCLK0_SPI0              (1<<4)
@@ -329,89 +328,28 @@
 #define S5PC100_CLKGATE_SCLK1_SPDIF             (1<<11)
 #define S5PC100_CLKGATE_SCLK1_CAM               (1<<12)
-/* register for power management */
+#define S5PC100_SWRESET         S5PC100_CLKREG_OTHER(0x000)
-#define S5PC100_PWR_CFG                 S5PC1XX_CLKREG(0x8000)
+#define S5PC100_OND_SWRESET     S5PC100_CLKREG_OTHER(0x008)
-#define S5PC100_EINT_WAKEUP_MASK        S5PC1XX_CLKREG(0x8004)
+#define S5PC100_GEN_CTRL        S5PC100_CLKREG_OTHER(0x100)
-#define S5PC100_NORMAL_CFG              S5PC1XX_CLKREG(0x8010)
+#define S5PC100_GEN_STATUS      S5PC100_CLKREG_OTHER(0x104)
-#define S5PC100_STOP_CFG                S5PC1XX_CLKREG(0x8014)
+#define S5PC100_MEM_SYS_CFG     S5PC100_CLKREG_OTHER(0x200)
-#define S5PC100_SLEEP_CFG               S5PC1XX_CLKREG(0x8018)
+#define S5PC100_CAM_MUX_SEL     S5PC100_CLKREG_OTHER(0x300)
-#define S5PC100_STOP_MEM_CFG    S5PC1XX_CLKREG(0x801C)
+#define S5PC100_MIXER_OUT_SEL   S5PC100_CLKREG_OTHER(0x304)
-#define S5PC100_OSC_FREQ                S5PC1XX_CLKREG(0x8100)
+#define S5PC100_LPMP_MODE_SEL   S5PC100_CLKREG_OTHER(0x308)
-#define S5PC100_OSC_STABLE              S5PC1XX_CLKREG(0x8104)
+#define S5PC100_MIPI_PHY_CON0   S5PC100_CLKREG_OTHER(0x400)
-#define S5PC100_PWR_STABLE              S5PC1XX_CLKREG(0x8108)
+#define S5PC100_MIPI_PHY_CON1   S5PC100_CLKREG_OTHER(0x414)
-#define S5PC100_MTC_STABLE              S5PC1XX_CLKREG(0x8110)
+#define S5PC100_HDMI_PHY_CON0   S5PC100_CLKREG_OTHER(0x420)
-#define S5PC100_CLAMP_STABLE    S5PC1XX_CLKREG(0x8114)
-#define S5PC100_OTHERS          S5PC1XX_CLKREG(0x8200)
+#define S5PC100_SWRESET_RESETVAL        0xc100
-#define S5PC100_RST_STAT                S5PC1XX_CLKREG(0x8300)
-#define S5PC100_WAKEUP_STAT     S5PC1XX_CLKREG(0x8304)
-#define S5PC100_BLK_PWR_STAT    S5PC1XX_CLKREG(0x8308)
-#define S5PC100_INFORM0                 S5PC1XX_CLKREG(0x8400)
-#define S5PC100_INFORM1                 S5PC1XX_CLKREG(0x8404)
-#define S5PC100_INFORM2                 S5PC1XX_CLKREG(0x8408)
-#define S5PC100_INFORM3                 S5PC1XX_CLKREG(0x840C)
-#define S5PC100_INFORM4                 S5PC1XX_CLKREG(0x8410)
-#define S5PC100_INFORM5                 S5PC1XX_CLKREG(0x8414)
-#define S5PC100_INFORM6                 S5PC1XX_CLKREG(0x8418)
-#define S5PC100_INFORM7                 S5PC1XX_CLKREG(0x841C)
-#define S5PC100_DCGIDX_MAP0     S5PC1XX_CLKREG(0x8500)
-#define S5PC100_DCGIDX_MAP1     S5PC1XX_CLKREG(0x8504)
-#define S5PC100_DCGIDX_MAP2     S5PC1XX_CLKREG(0x8508)
-#define S5PC100_DCGPERF_MAP0    S5PC1XX_CLKREG(0x850C)
-#define S5PC100_DCGPERF_MAP1    S5PC1XX_CLKREG(0x8510)
-#define S5PC100_DVCIDX_MAP              S5PC1XX_CLKREG(0x8514)
-#define S5PC100_FREQ_CPU                S5PC1XX_CLKREG(0x8518)
-#define S5PC100_FREQ_DPM                S5PC1XX_CLKREG(0x851C)
-#define S5PC100_DVSEMCLK_EN     S5PC1XX_CLKREG(0x8520)
-#define S5PC100_APLL_CON_L8     S5PC1XX_CLKREG(0x8600)
-#define S5PC100_APLL_CON_L7     S5PC1XX_CLKREG(0x8604)
-#define S5PC100_APLL_CON_L6     S5PC1XX_CLKREG(0x8608)
-#define S5PC100_APLL_CON_L5     S5PC1XX_CLKREG(0x860C)
-#define S5PC100_APLL_CON_L4     S5PC1XX_CLKREG(0x8610)
-#define S5PC100_APLL_CON_L3     S5PC1XX_CLKREG(0x8614)
-#define S5PC100_APLL_CON_L2     S5PC1XX_CLKREG(0x8618)
-#define S5PC100_APLL_CON_L1     S5PC1XX_CLKREG(0x861C)
-#define S5PC100_IEM_CONTROL     S5PC1XX_CLKREG(0x8620)
-#define S5PC100_CLKDIV_IEM_L8   S5PC1XX_CLKREG(0x8700)
-#define S5PC100_CLKDIV_IEM_L7   S5PC1XX_CLKREG(0x8704)
-#define S5PC100_CLKDIV_IEM_L6   S5PC1XX_CLKREG(0x8708)
-#define S5PC100_CLKDIV_IEM_L5   S5PC1XX_CLKREG(0x870C)
-#define S5PC100_CLKDIV_IEM_L4   S5PC1XX_CLKREG(0x8710)
-#define S5PC100_CLKDIV_IEM_L3   S5PC1XX_CLKREG(0x8714)
-#define S5PC100_CLKDIV_IEM_L2   S5PC1XX_CLKREG(0x8718)
-#define S5PC100_CLKDIV_IEM_L1   S5PC1XX_CLKREG(0x871C)
-#define S5PC100_IEM_HPMCLK_DIV  S5PC1XX_CLKREG(0x8724)
-#define S5PC100_SWRESET         S5PC1XX_CLKREG(0x100000)
-#define S5PC100_OND_SWRESET             S5PC1XX_CLKREG(0x100008)
-#define S5PC100_GEN_CTRL                S5PC1XX_CLKREG(0x100100)
-#define S5PC100_GEN_STATUS              S5PC1XX_CLKREG(0x100104)
-#define S5PC100_MEM_SYS_CFG             S5PC1XX_CLKREG(0x100200)
-#define S5PC100_CAM_MUX_SEL             S5PC1XX_CLKREG(0x100300)
-#define S5PC100_MIXER_OUT_SEL   S5PC1XX_CLKREG(0x100304)
-#define S5PC100_LPMP_MODE_SEL   S5PC1XX_CLKREG(0x100308)
-#define S5PC100_MIPI_PHY_CON0   S5PC1XX_CLKREG(0x100400)
-#define S5PC100_MIPI_PHY_CON1   S5PC1XX_CLKREG(0x100414)
-#define S5PC100_HDMI_PHY_CON0   S5PC1XX_CLKREG(0x100420)
-#define S5PC100_CFG_WFI_CLEAN   (~(3<<5))
-#define S5PC100_CFG_WFI_IDLE    (1<<5)
-#define S5PC100_CFG_WFI_STOP    (2<<5)
-#define S5PC100_CFG_WFI_SLEEP   (3<<5)
 #define S5PC100_OTHER_SYS_INT   24
 #define S5PC100_OTHER_STA_TYPE  23
 #define STA_TYPE_EXPON          0
 #define STA_TYPE_SFR            1
-#define S5PC100_PWR_STA_EXP_SCALE       0
-#define S5PC100_PWR_STA_CNT             4
-#define S5PC100_PWR_STABLE_COUNT        85500
 #define S5PC100_SLEEP_CFG_OSC_EN        0
 /* OTHERS Resgister */
-#define S5PC100_OTHERS_USB_SIG_MASK     (1 << 16)
+#define S5PC100_OTHERS_USB_SIG_MASK     (1 << 16)
 #define S5PC100_OTHERS_MIPI_DPHY_EN             (1 << 28)
 /* MIPI D-PHY Control Register 0 */
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h b/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h
new file mode 100644
index 000000000000..43c7bc8bf784
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h
@@ -0,0 +1,70 @@
+/* linux/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC1XX - GPIO register definitions
+ */
+#ifndef __ASM_PLAT_S5PC1XX_REGS_GPIO_H
+#define __ASM_PLAT_S5PC1XX_REGS_GPIO_H __FILE__
+#include <mach/map.h>
+/* S5PC100 */
+#define S5PC100_GPIO_BASE       S5PC1XX_VA_GPIO
+#define S5PC100_GPA0_BASE       (S5PC100_GPIO_BASE + 0x0000)
+#define S5PC100_GPA1_BASE       (S5PC100_GPIO_BASE + 0x0020)
+#define S5PC100_GPB_BASE        (S5PC100_GPIO_BASE + 0x0040)
+#define S5PC100_GPC_BASE        (S5PC100_GPIO_BASE + 0x0060)
+#define S5PC100_GPD_BASE        (S5PC100_GPIO_BASE + 0x0080)
+#define S5PC100_GPE0_BASE       (S5PC100_GPIO_BASE + 0x00A0)
+#define S5PC100_GPE1_BASE       (S5PC100_GPIO_BASE + 0x00C0)
+#define S5PC100_GPF0_BASE       (S5PC100_GPIO_BASE + 0x00E0)
+#define S5PC100_GPF1_BASE       (S5PC100_GPIO_BASE + 0x0100)
+#define S5PC100_GPF2_BASE       (S5PC100_GPIO_BASE + 0x0120)
+#define S5PC100_GPF3_BASE       (S5PC100_GPIO_BASE + 0x0140)
+#define S5PC100_GPG0_BASE       (S5PC100_GPIO_BASE + 0x0160)
+#define S5PC100_GPG1_BASE       (S5PC100_GPIO_BASE + 0x0180)
+#define S5PC100_GPG2_BASE       (S5PC100_GPIO_BASE + 0x01A0)
+#define S5PC100_GPG3_BASE       (S5PC100_GPIO_BASE + 0x01C0)
+#define S5PC100_GPH0_BASE       (S5PC100_GPIO_BASE + 0x0C00)
+#define S5PC100_GPH1_BASE       (S5PC100_GPIO_BASE + 0x0C20)
+#define S5PC100_GPH2_BASE       (S5PC100_GPIO_BASE + 0x0C40)
+#define S5PC100_GPH3_BASE       (S5PC100_GPIO_BASE + 0x0C60)
+#define S5PC100_GPI_BASE        (S5PC100_GPIO_BASE + 0x01E0)
+#define S5PC100_GPJ0_BASE       (S5PC100_GPIO_BASE + 0x0200)
+#define S5PC100_GPJ1_BASE       (S5PC100_GPIO_BASE + 0x0220)
+#define S5PC100_GPJ2_BASE       (S5PC100_GPIO_BASE + 0x0240)
+#define S5PC100_GPJ3_BASE       (S5PC100_GPIO_BASE + 0x0260)
+#define S5PC100_GPJ4_BASE       (S5PC100_GPIO_BASE + 0x0280)
+#define S5PC100_GPK0_BASE       (S5PC100_GPIO_BASE + 0x02A0)
+#define S5PC100_GPK1_BASE       (S5PC100_GPIO_BASE + 0x02C0)
+#define S5PC100_GPK2_BASE       (S5PC100_GPIO_BASE + 0x02E0)
+#define S5PC100_GPK3_BASE       (S5PC100_GPIO_BASE + 0x0300)
+#define S5PC100_GPL0_BASE       (S5PC100_GPIO_BASE + 0x0320)
+#define S5PC100_GPL1_BASE       (S5PC100_GPIO_BASE + 0x0340)
+#define S5PC100_GPL2_BASE       (S5PC100_GPIO_BASE + 0x0360)
+#define S5PC100_GPL3_BASE       (S5PC100_GPIO_BASE + 0x0380)
+#define S5PC100_GPL4_BASE       (S5PC100_GPIO_BASE + 0x03A0)
+#define S5PC100_EINT_BASE       (S5PC100_GPIO_BASE + 0x0E00)
+#define S5PC100_UHOST           (S5PC100_GPIO_BASE + 0x0B68)
+#define S5PC100_PDNEN           (S5PC100_GPIO_BASE + 0x0F80)
+/* PDNEN */
+#define S5PC100_PDNEN_CFG_PDNEN (1 << 1)
+#define S5PC100_PDNEN_CFG_AUTO  (0 << 1)
+#define S5PC100_PDNEN_POWERDOWN (1 << 0)
+#define S5PC100_PDNEN_NORMAL    (0 << 0)
+/* Common part */
+/* External interrupt base is same at both s5pc100 and s5pc110 */
+#define S5PC1XX_EINT_BASE       (S5PC100_EINT_BASE)
+#define S5PC100_GPx_INPUT(__gpio)       (0x0 << ((__gpio) * 4))
+#define S5PC100_GPx_OUTPUT(__gpio)      (0x1 << ((__gpio) * 4))
+#define S5PC100_GPx_CONMASK(__gpio)     (0xf << ((__gpio) * 4))
+#endif /* __ASM_PLAT_S5PC1XX_REGS_GPIO_H */
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-power.h b/arch/arm/plat-s5pc1xx/include/plat/regs-power.h
new file mode 100644
index 000000000000..02ffa491b53a
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/include/plat/regs-power.h
@@ -0,0 +1,84 @@
+/* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Jongse Won <jongse.won@samsung.com>
+ *
+ * S5PC1XX clock register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __ASM_ARM_REGS_PWR
+#define __ASM_ARM_REGS_PWR __FILE__
+#define S5PC1XX_PWRREG(x)                       (S5PC1XX_VA_PWR + (x))
+/* s5pc100 (0xE0108000) register for power management */
+#define S5PC100_PWR_CFG                         S5PC1XX_PWRREG(0x0)
+#define S5PC100_EINT_WAKEUP_MASK                S5PC1XX_PWRREG(0x4)
+#define S5PC100_NORMAL_CFG                      S5PC1XX_PWRREG(0x10)
+#define S5PC100_STOP_CFG                        S5PC1XX_PWRREG(0x14)
+#define S5PC100_SLEEP_CFG                       S5PC1XX_PWRREG(0x18)
+#define S5PC100_STOP_MEM_CFG                    S5PC1XX_PWRREG(0x1C)
+#define S5PC100_OSC_FREQ                        S5PC1XX_PWRREG(0x100)
+#define S5PC100_OSC_STABLE                      S5PC1XX_PWRREG(0x104)
+#define S5PC100_PWR_STABLE                      S5PC1XX_PWRREG(0x108)
+#define S5PC100_MTC_STABLE                      S5PC1XX_PWRREG(0x110)
+#define S5PC100_CLAMP_STABLE                    S5PC1XX_PWRREG(0x114)
+#define S5PC100_OTHERS                          S5PC1XX_PWRREG(0x200)
+#define S5PC100_RST_STAT                        S5PC1XX_PWRREG(0x300)
+#define S5PC100_WAKEUP_STAT                     S5PC1XX_PWRREG(0x304)
+#define S5PC100_BLK_PWR_STAT                    S5PC1XX_PWRREG(0x308)
+#define S5PC100_INFORM0                         S5PC1XX_PWRREG(0x400)
+#define S5PC100_INFORM1                         S5PC1XX_PWRREG(0x404)
+#define S5PC100_INFORM2                         S5PC1XX_PWRREG(0x408)
+#define S5PC100_INFORM3                         S5PC1XX_PWRREG(0x40C)
+#define S5PC100_INFORM4                         S5PC1XX_PWRREG(0x410)
+#define S5PC100_INFORM5                         S5PC1XX_PWRREG(0x414)
+#define S5PC100_INFORM6                         S5PC1XX_PWRREG(0x418)
+#define S5PC100_INFORM7                         S5PC1XX_PWRREG(0x41C)
+#define S5PC100_DCGIDX_MAP0                     S5PC1XX_PWRREG(0x500)
+#define S5PC100_DCGIDX_MAP1                     S5PC1XX_PWRREG(0x504)
+#define S5PC100_DCGIDX_MAP2                     S5PC1XX_PWRREG(0x508)
+#define S5PC100_DCGPERF_MAP0                    S5PC1XX_PWRREG(0x50C)
+#define S5PC100_DCGPERF_MAP1                    S5PC1XX_PWRREG(0x510)
+#define S5PC100_DVCIDX_MAP                      S5PC1XX_PWRREG(0x514)
+#define S5PC100_FREQ_CPU                        S5PC1XX_PWRREG(0x518)
+#define S5PC100_FREQ_DPM                        S5PC1XX_PWRREG(0x51C)
+#define S5PC100_DVSEMCLK_EN                     S5PC1XX_PWRREG(0x520)
+#define S5PC100_APLL_CON_L8                     S5PC1XX_PWRREG(0x600)
+#define S5PC100_APLL_CON_L7                     S5PC1XX_PWRREG(0x604)
+#define S5PC100_APLL_CON_L6                     S5PC1XX_PWRREG(0x608)
+#define S5PC100_APLL_CON_L5                     S5PC1XX_PWRREG(0x60C)
+#define S5PC100_APLL_CON_L4                     S5PC1XX_PWRREG(0x610)
+#define S5PC100_APLL_CON_L3                     S5PC1XX_PWRREG(0x614)
+#define S5PC100_APLL_CON_L2                     S5PC1XX_PWRREG(0x618)
+#define S5PC100_APLL_CON_L1                     S5PC1XX_PWRREG(0x61C)
+#define S5PC100_IEM_CONTROL                     S5PC1XX_PWRREG(0x620)
+#define S5PC100_CLKDIV_IEM_L8                   S5PC1XX_PWRREG(0x700)
+#define S5PC100_CLKDIV_IEM_L7                   S5PC1XX_PWRREG(0x704)
+#define S5PC100_CLKDIV_IEM_L6                   S5PC1XX_PWRREG(0x708)
+#define S5PC100_CLKDIV_IEM_L5                   S5PC1XX_PWRREG(0x70C)
+#define S5PC100_CLKDIV_IEM_L4                   S5PC1XX_PWRREG(0x710)
+#define S5PC100_CLKDIV_IEM_L3                   S5PC1XX_PWRREG(0x714)
+#define S5PC100_CLKDIV_IEM_L2                   S5PC1XX_PWRREG(0x718)
+#define S5PC100_CLKDIV_IEM_L1                   S5PC1XX_PWRREG(0x71C)
+#define S5PC100_IEM_HPMCLK_DIV                  S5PC1XX_PWRREG(0x724)
+/* PWR_CFG */
+#define S5PC100_PWRCFG_CFG_DEEP_IDLE            (1 << 31)
+#define S5PC100_PWRCFG_CFG_WFI_MASK             (3 << 5)
+#define S5PC100_PWRCFG_CFG_WFI_IDLE             (0 << 5)
+#define S5PC100_PWRCFG_CFG_WFI_DEEP_IDLE        (1 << 5)
+#define S5PC100_PWRCFG_CFG_WFI_STOP             (2 << 5)
+#define S5PC100_PWRCFG_CFG_WFI_SLEEP            (3 << 5)
+/* SLEEP_CFG */
+#define S5PC100_SLEEP_OSC_EN_SLEEP              (1 << 0)
+/* OTHERS */
+#define S5PC100_PMU_INT_DISABLE                 (1 << 24)
+#endif /* __ASM_ARM_REGS_PWR */
diff --git a/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h b/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
index 45e275131665..2531f34a56f3 100644
--- a/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
+++ b/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
@@ -35,10 +35,9 @@ extern struct clk clk_hpll;
 extern struct clk clk_hd0;
 extern struct clk clk_pd0;
 extern struct clk clk_54m;
-extern struct clk clk_dout_mpll2;
 extern void s5pc1xx_register_clocks(void);
-extern int s5pc1xx_sclk0_ctrl(struct clk *clk, int enable);
+extern int s5pc100_sclk0_ctrl(struct clk *clk, int enable);
-extern int s5pc1xx_sclk1_ctrl(struct clk *clk, int enable);
+extern int s5pc100_sclk1_ctrl(struct clk *clk, int enable);
 /* Some day, belows will be moved to plat-s5pc/include/plat/devs.h */
 extern struct s3c24xx_uart_resources s5pc1xx_uart_resources[];
diff --git a/arch/arm/plat-s5pc1xx/irq-eint.c b/arch/arm/plat-s5pc1xx/irq-eint.c
new file mode 100644
index 000000000000..373122f57d56
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/irq-eint.c
@@ -0,0 +1,281 @@
+/*
+ * linux/arch/arm/plat-s5pc1xx/irq-eint.c
+ *
+ *  Copyright 2009 Samsung Electronics Co.
+ *  Byungho Min <bhmin@samsung.com>
+ *  Kyungin Park <kyungmin.park@samsung.com>
+ *
+ * Based on plat-s3c64xx/irq-eint.c
+ *
+ * S5PC1XX - Interrupt handling for IRQ_EINT(x)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/sysdev.h>
+#include <linux/pm.h>
+#include <linux/gpio.h>
+#include <asm/hardware/vic.h>
+#include <mach/map.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-ext.h>
+#include <plat/pm.h>
+#include <plat/regs-gpio.h>
+#include <plat/regs-irqtype.h>
+/*
+ * bank is a group of external interrupt
+ * bank0 means EINT0 ... EINT7
+ * bank1 means EINT8 ... EINT15
+ * bank2 means EINT16 ... EINT23
+ * bank3 means EINT24 ... EINT31
+ */
+static inline int s3c_get_eint(unsigned int irq)
+{
+        int real;
+        if (irq < IRQ_EINT16_31)
+                real = (irq - IRQ_EINT0);
+        else
+                real = (irq - S3C_IRQ_EINT_BASE) + IRQ_EINT16_31 - IRQ_EINT0;
+        return real;
+}
+static inline int s3c_get_bank(unsigned int irq)
+{
+        return s3c_get_eint(irq) >> 3;
+}
+static inline int s3c_eint_to_bit(unsigned int irq)
+{
+        int real, bit;
+        real = s3c_get_eint(irq);
+        bit = 1 << (real & (8 - 1));
+        return bit;
+}
+static inline void s3c_irq_eint_mask(unsigned int irq)
+{
+        u32 mask;
+        u32 bank = s3c_get_bank(irq);
+        mask = __raw_readl(S5PC1XX_WKUP_INT_MASK(bank));
+        mask |= s3c_eint_to_bit(irq);
+        __raw_writel(mask, S5PC1XX_WKUP_INT_MASK(bank));
+}
+static void s3c_irq_eint_unmask(unsigned int irq)
+{
+        u32 mask;
+        u32 bank = s3c_get_bank(irq);
+        mask = __raw_readl(S5PC1XX_WKUP_INT_MASK(bank));
+        mask &= ~(s3c_eint_to_bit(irq));
+        __raw_writel(mask, S5PC1XX_WKUP_INT_MASK(bank));
+}
+static inline void s3c_irq_eint_ack(unsigned int irq)
+{
+        u32 bank = s3c_get_bank(irq);
+        __raw_writel(s3c_eint_to_bit(irq), S5PC1XX_WKUP_INT_PEND(bank));
+}
+static void s3c_irq_eint_maskack(unsigned int irq)
+{
+        /* compiler should in-line these */
+        s3c_irq_eint_mask(irq);
+        s3c_irq_eint_ack(irq);
+}
+static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
+{
+        u32 bank = s3c_get_bank(irq);
+        int real = s3c_get_eint(irq);
+        int gpio, shift, sfn;
+        u32 ctrl, con = 0;
+        switch (type) {
+        case IRQ_TYPE_NONE:
+                printk(KERN_WARNING "No edge setting!\n");
+                break;
+        case IRQ_TYPE_EDGE_RISING:
+                con = S5PC1XX_WKUP_INT_RISEEDGE;
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                con = S5PC1XX_WKUP_INT_FALLEDGE;
+                break;
+        case IRQ_TYPE_EDGE_BOTH:
+                con = S5PC1XX_WKUP_INT_BOTHEDGE;
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+                con = S5PC1XX_WKUP_INT_LOWLEV;
+                break;
+        case IRQ_TYPE_LEVEL_HIGH:
+                con = S5PC1XX_WKUP_INT_HILEV;
+                break;
+        default:
+                printk(KERN_ERR "No such irq type %d", type);
+                return -EINVAL;
+        }
+        gpio = real & (8 - 1);
+        shift = gpio << 2;
+        ctrl = __raw_readl(S5PC1XX_WKUP_INT_CON(bank));
+        ctrl &= ~(0x7 << shift);
+        ctrl |= con << shift;
+        __raw_writel(ctrl, S5PC1XX_WKUP_INT_CON(bank));
+        switch (real) {
+        case 0 ... 7:
+                        gpio = S5PC100_GPH0(gpio);
+                break;
+        case 8 ... 15:
+                        gpio = S5PC100_GPH1(gpio);
+                break;
+        case 16 ... 23:
+                        gpio = S5PC100_GPH2(gpio);
+                break;
+        case 24 ... 31:
+                        gpio = S5PC100_GPH3(gpio);
+                break;
+        default:
+                return -EINVAL;
+        }
+        sfn = S3C_GPIO_SFN(0x2);
+        s3c_gpio_cfgpin(gpio, sfn);
+        return 0;
+}
+static struct irq_chip s3c_irq_eint = {
+        .name           = "EINT",
+        .mask           = s3c_irq_eint_mask,
+        .unmask         = s3c_irq_eint_unmask,
+        .mask_ack       = s3c_irq_eint_maskack,
+        .ack            = s3c_irq_eint_ack,
+        .set_type       = s3c_irq_eint_set_type,
+        .set_wake       = s3c_irqext_wake,
+};
+/* s3c_irq_demux_eint
+ *
+ * This function demuxes the IRQ from external interrupts,
+ * from IRQ_EINT(16) to IRQ_EINT(31). It is designed to be inlined into
+ * the specific handlers s3c_irq_demux_eintX_Y.
+ */
+static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
+{
+        u32 status = __raw_readl(S5PC1XX_WKUP_INT_PEND((start >> 3)));
+        u32 mask = __raw_readl(S5PC1XX_WKUP_INT_MASK((start >> 3)));
+        unsigned int irq;
+        status &= ~mask;
+        status &= (1 << (end - start + 1)) - 1;
+        for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
+                if (status & 1)
+                        generic_handle_irq(irq);
+                status >>= 1;
+        }
+}
+static void s3c_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
+{
+        s3c_irq_demux_eint(16, 23);
+        s3c_irq_demux_eint(24, 31);
+}
+/*
+ * Handle EINT0 ... EINT15 at VIC directly
+ */
+static void s3c_irq_vic_eint_mask(unsigned int irq)
+{
+        void __iomem *base = get_irq_chip_data(irq);
+        unsigned int real;
+        s3c_irq_eint_mask(irq);
+        real = s3c_get_eint(irq);
+        writel(1 << real, base + VIC_INT_ENABLE_CLEAR);
+}
+static void s3c_irq_vic_eint_unmask(unsigned int irq)
+{
+        void __iomem *base = get_irq_chip_data(irq);
+        unsigned int real;
+        s3c_irq_eint_unmask(irq);
+        real = s3c_get_eint(irq);
+        writel(1 << real, base + VIC_INT_ENABLE);
+}
+static inline void s3c_irq_vic_eint_ack(unsigned int irq)
+{
+        u32 bit;
+        u32 bank = s3c_get_bank(irq);
+        bit = s3c_eint_to_bit(irq);
+        __raw_writel(bit, S5PC1XX_WKUP_INT_PEND(bank));
+}
+static void s3c_irq_vic_eint_maskack(unsigned int irq)
+{
+        /* compiler should in-line these */
+        s3c_irq_vic_eint_mask(irq);
+        s3c_irq_vic_eint_ack(irq);
+}
+static struct irq_chip s3c_irq_vic_eint = {
+        .name           = "EINT",
+        .mask           = s3c_irq_vic_eint_mask,
+        .unmask         = s3c_irq_vic_eint_unmask,
+        .mask_ack       = s3c_irq_vic_eint_maskack,
+        .ack            = s3c_irq_vic_eint_ack,
+        .set_type       = s3c_irq_eint_set_type,
+        .set_wake       = s3c_irqext_wake,
+};
+static int __init s5pc1xx_init_irq_eint(void)
+{
+        int irq;
+        for (irq = IRQ_EINT0; irq <= IRQ_EINT15; irq++) {
+                set_irq_chip(irq, &s3c_irq_vic_eint);
+                set_irq_handler(irq, handle_level_irq);
+                set_irq_flags(irq, IRQF_VALID);
+        }
+        for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) {
+                set_irq_chip(irq, &s3c_irq_eint);
+                set_irq_handler(irq, handle_level_irq);
+                set_irq_flags(irq, IRQF_VALID);
+        }
+        set_irq_chained_handler(IRQ_EINT16_31, s3c_irq_demux_eint16_31);
+        return 0;
+}
+arch_initcall(s5pc1xx_init_irq_eint);
diff --git a/arch/arm/plat-s5pc1xx/irq-gpio.c b/arch/arm/plat-s5pc1xx/irq-gpio.c
new file mode 100644
index 000000000000..fecca7a679b0
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/irq-gpio.c
@@ -0,0 +1,266 @@
+/*
+ * arch/arm/plat-s5pc1xx/irq-gpio.c
+ *
+ * Copyright (C) 2009 Samsung Electronics
+ *
+ * S5PC1XX - Interrupt handling for IRQ_GPIO${group}(x)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <mach/map.h>
+#include <plat/gpio-cfg.h>
+#define S5PC1XX_GPIOREG(x)              (S5PC1XX_VA_GPIO + (x))
+#define CON_OFFSET                      0x700
+#define MASK_OFFSET                     0x900
+#define PEND_OFFSET                     0xA00
+#define CON_OFFSET_2                    0xE00
+#define MASK_OFFSET_2                   0xF00
+#define PEND_OFFSET_2                   0xF40
+#define GPIOINT_LEVEL_LOW               0x0
+#define GPIOINT_LEVEL_HIGH              0x1
+#define GPIOINT_EDGE_FALLING            0x2
+#define GPIOINT_EDGE_RISING             0x3
+#define GPIOINT_EDGE_BOTH               0x4
+static int group_to_con_offset(int group)
+{
+        return group << 2;
+}
+static int group_to_mask_offset(int group)
+{
+        return group << 2;
+}
+static int group_to_pend_offset(int group)
+{
+        return group << 2;
+}
+static int s5pc1xx_get_start(unsigned int group)
+{
+        switch (group) {
+        case 0: return S5PC100_GPIO_A0_START;
+        case 1: return S5PC100_GPIO_A1_START;
+        case 2: return S5PC100_GPIO_B_START;
+        case 3: return S5PC100_GPIO_C_START;
+        case 4: return S5PC100_GPIO_D_START;
+        case 5: return S5PC100_GPIO_E0_START;
+        case 6: return S5PC100_GPIO_E1_START;
+        case 7: return S5PC100_GPIO_F0_START;
+        case 8: return S5PC100_GPIO_F1_START;
+        case 9: return S5PC100_GPIO_F2_START;
+        case 10: return S5PC100_GPIO_F3_START;
+        case 11: return S5PC100_GPIO_G0_START;
+        case 12: return S5PC100_GPIO_G1_START;
+        case 13: return S5PC100_GPIO_G2_START;
+        case 14: return S5PC100_GPIO_G3_START;
+        case 15: return S5PC100_GPIO_I_START;
+        case 16: return S5PC100_GPIO_J0_START;
+        case 17: return S5PC100_GPIO_J1_START;
+        case 18: return S5PC100_GPIO_J2_START;
+        case 19: return S5PC100_GPIO_J3_START;
+        case 20: return S5PC100_GPIO_J4_START;
+        default:
+                BUG();
+        }
+        return -EINVAL;
+}
+static int s5pc1xx_get_group(unsigned int irq)
+{
+        irq -= S3C_IRQ_GPIO(0);
+        switch (irq) {
+        case S5PC100_GPIO_A0_START ... S5PC100_GPIO_A1_START - 1:
+                return 0;
+        case S5PC100_GPIO_A1_START ... S5PC100_GPIO_B_START - 1:
+                return 1;
+        case S5PC100_GPIO_B_START ... S5PC100_GPIO_C_START - 1:
+                return 2;
+        case S5PC100_GPIO_C_START ... S5PC100_GPIO_D_START - 1:
+                return 3;
+        case S5PC100_GPIO_D_START ... S5PC100_GPIO_E0_START - 1:
+                return 4;
+        case S5PC100_GPIO_E0_START ... S5PC100_GPIO_E1_START - 1:
+                return 5;
+        case S5PC100_GPIO_E1_START ... S5PC100_GPIO_F0_START - 1:
+                return 6;
+        case S5PC100_GPIO_F0_START ... S5PC100_GPIO_F1_START - 1:
+                return 7;
+        case S5PC100_GPIO_F1_START ... S5PC100_GPIO_F2_START - 1:
+                return 8;
+        case S5PC100_GPIO_F2_START ... S5PC100_GPIO_F3_START - 1:
+                return 9;
+        case S5PC100_GPIO_F3_START ... S5PC100_GPIO_G0_START - 1:
+                return 10;
+        case S5PC100_GPIO_G0_START ... S5PC100_GPIO_G1_START - 1:
+                return 11;
+        case S5PC100_GPIO_G1_START ... S5PC100_GPIO_G2_START - 1:
+                return 12;
+        case S5PC100_GPIO_G2_START ... S5PC100_GPIO_G3_START - 1:
+                return 13;
+        case S5PC100_GPIO_G3_START ... S5PC100_GPIO_H0_START - 1:
+                return 14;
+        case S5PC100_GPIO_I_START ... S5PC100_GPIO_J0_START - 1:
+                return 15;
+        case S5PC100_GPIO_J0_START ... S5PC100_GPIO_J1_START - 1:
+                return 16;
+        case S5PC100_GPIO_J1_START ... S5PC100_GPIO_J2_START - 1:
+                return 17;
+        case S5PC100_GPIO_J2_START ... S5PC100_GPIO_J3_START - 1:
+                return 18;
+        case S5PC100_GPIO_J3_START ... S5PC100_GPIO_J4_START - 1:
+                return 19;
+        case S5PC100_GPIO_J4_START ... S5PC100_GPIO_K0_START - 1:
+                return 20;
+        default:
+                BUG();
+        }
+        return -EINVAL;
+}
+static int s5pc1xx_get_offset(unsigned int irq)
+{
+        struct gpio_chip *chip = get_irq_data(irq);
+        return irq - S3C_IRQ_GPIO(chip->base);
+}
+static void s5pc1xx_gpioint_ack(unsigned int irq)
+{
+        int group, offset, pend_offset;
+        unsigned int value;
+        group = s5pc1xx_get_group(irq);
+        offset = s5pc1xx_get_offset(irq);
+        pend_offset = group_to_pend_offset(group);
+        value = __raw_readl(S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset);
+        value |= 1 << offset;
+        __raw_writel(value, S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset);
+}
+static void s5pc1xx_gpioint_mask(unsigned int irq)
+{
+        int group, offset, mask_offset;
+        unsigned int value;
+        group = s5pc1xx_get_group(irq);
+        offset = s5pc1xx_get_offset(irq);
+        mask_offset = group_to_mask_offset(group);
+        value = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset);
+        value |= 1 << offset;
+        __raw_writel(value, S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset);
+}
+static void s5pc1xx_gpioint_unmask(unsigned int irq)
+{
+        int group, offset, mask_offset;
+        unsigned int value;
+        group = s5pc1xx_get_group(irq);
+        offset = s5pc1xx_get_offset(irq);
+        mask_offset = group_to_mask_offset(group);
+        value = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset);
+        value &= ~(1 << offset);
+        __raw_writel(value, S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset);
+}
+static void s5pc1xx_gpioint_mask_ack(unsigned int irq)
+{
+        s5pc1xx_gpioint_mask(irq);
+        s5pc1xx_gpioint_ack(irq);
+}
+static int s5pc1xx_gpioint_set_type(unsigned int irq, unsigned int type)
+{
+        int group, offset, con_offset;
+        unsigned int value;
+        group = s5pc1xx_get_group(irq);
+        offset = s5pc1xx_get_offset(irq);
+        con_offset = group_to_con_offset(group);
+        switch (type) {
+        case IRQ_TYPE_NONE:
+                printk(KERN_WARNING "No irq type\n");
+                return -EINVAL;
+        case IRQ_TYPE_EDGE_RISING:
+                type = GPIOINT_EDGE_RISING;
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                type = GPIOINT_EDGE_FALLING;
+                break;
+        case IRQ_TYPE_EDGE_BOTH:
+                type = GPIOINT_EDGE_BOTH;
+                break;
+        case IRQ_TYPE_LEVEL_HIGH:
+                type = GPIOINT_LEVEL_HIGH;
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+                type = GPIOINT_LEVEL_LOW;
+                break;
+        default:
+                BUG();
+        }
+        value = __raw_readl(S5PC1XX_GPIOREG(CON_OFFSET) + con_offset);
+        value &= ~(0xf << (offset * 0x4));
+        value |= (type << (offset * 0x4));
+        __raw_writel(value, S5PC1XX_GPIOREG(CON_OFFSET) + con_offset);
+        return 0;
+}
+struct irq_chip s5pc1xx_gpioint = {
+        .name           = "GPIO",
+        .ack            = s5pc1xx_gpioint_ack,
+        .mask           = s5pc1xx_gpioint_mask,
+        .mask_ack       = s5pc1xx_gpioint_mask_ack,
+        .unmask         = s5pc1xx_gpioint_unmask,
+        .set_type       = s5pc1xx_gpioint_set_type,
+};
+void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc)
+{
+        int group, offset, pend_offset, mask_offset;
+        int real_irq, group_end;
+        unsigned int pend, mask;
+        group_end = 21;
+        for (group = 0; group < group_end; group++) {
+                pend_offset = group_to_pend_offset(group);
+                pend = __raw_readl(S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset);
+                if (!pend)
+                        continue;
+                mask_offset = group_to_mask_offset(group);
+                mask = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset);
+                pend &= ~mask;
+                for (offset = 0; offset < 8; offset++) {
+                        if (pend & (1 << offset)) {
+                                real_irq = s5pc1xx_get_start(group) + offset;
+                                generic_handle_irq(S3C_IRQ_GPIO(real_irq));
+                        }
+                }
+        }
+}
diff --git a/arch/arm/plat-s5pc1xx/irq.c b/arch/arm/plat-s5pc1xx/irq.c
index 80d6dd942cb8..e44fd04ef333 100644
--- a/arch/arm/plat-s5pc1xx/irq.c
+++ b/arch/arm/plat-s5pc1xx/irq.c
@@ -79,7 +79,7 @@ static void s3c_irq_timer_ack(unsigned int irq)
 {
        u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
-        reg &= 0x1f;
+        reg &= 0x1f;  /* mask out pending interrupts */
        reg |= (1 << 5) << (irq - IRQ_TIMER0);
        __raw_writel(reg, S3C64XX_TINT_CSTAT);
 }
diff --git a/arch/arm/plat-s5pc1xx/s5pc100-clock.c b/arch/arm/plat-s5pc1xx/s5pc100-clock.c
index 6b24035172fa..b436d44510c8 100644
--- a/arch/arm/plat-s5pc1xx/s5pc100-clock.c
+++ b/arch/arm/plat-s5pc1xx/s5pc100-clock.c
@@ -49,6 +49,7 @@ static struct clk clk_ext_xtal_mux = {
 #define clk_fin_hpll clk_ext_xtal_mux
 #define clk_fout_mpll   clk_mpll
+#define clk_vclk_54m    clk_54m
 struct clk_sources {
        unsigned int    nr_sources;
@@ -67,746 +68,327 @@ struct clksrc_clk {
        void __iomem            *reg_source;
 };
-static int clk_default_setrate(struct clk *clk, unsigned long rate)
+/* APLL */
-{
+static struct clk clk_fout_apll = {
-        clk->rate = rate;
+        .name           = "fout_apll",
-        return 1;
-}
-struct clk clk_27m = {
-        .name           = "clk_27m",
        .id             = -1,
        .rate           = 27000000,
 };
-static int clk_48m_ctrl(struct clk *clk, int enable)
+static struct clk *clk_src_apll_list[] = {
-{
+        [0] = &clk_fin_apll,
-        unsigned long flags;
+        [1] = &clk_fout_apll,
-        u32 val;
+};
+static struct clk_sources clk_src_apll = {
+        .sources        = clk_src_apll_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_apll_list),
+};
-        /* can't rely on clock lock, this register has other usages */
+static struct clksrc_clk clk_mout_apll = {
-        local_irq_save(flags);
+        .clk    = {
+                .name           = "mout_apll",
+                .id             = -1,
+        },
+        .shift          = S5PC100_CLKSRC0_APLL_SHIFT,
+        .mask           = S5PC100_CLKSRC0_APLL_MASK,
+        .sources        = &clk_src_apll,
+        .reg_source     = S5PC100_CLKSRC0,
+};
-        val = __raw_readl(S5PC1XX_CLK_SRC1);
+static unsigned long s5pc100_clk_dout_apll_get_rate(struct clk *clk)
-        if (enable)
+{
-                val |= S5PC100_CLKSRC1_CLK48M_MASK;
+        unsigned long rate = clk_get_rate(clk->parent);
-        else
+        unsigned int ratio;
-                val &= ~S5PC100_CLKSRC1_CLK48M_MASK;
-        __raw_writel(val, S5PC1XX_CLK_SRC1);
+        ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_APLL_MASK;
-        local_irq_restore(flags);
+        ratio >>= S5PC100_CLKDIV0_APLL_SHIFT;
-        return 0;
+        return rate / (ratio + 1);
 }
-struct clk clk_48m = {
+static struct clk clk_dout_apll = {
-        .name           = "clk_48m",
+        .name           = "dout_apll",
        .id             = -1,
-        .rate           = 48000000,
+        .parent         = &clk_mout_apll.clk,
-        .enable         = clk_48m_ctrl,
+        .get_rate       = s5pc100_clk_dout_apll_get_rate,
 };
-struct clk clk_54m = {
+static unsigned long s5pc100_clk_arm_get_rate(struct clk *clk)
-        .name           = "clk_54m",
+{
-        .id             = -1,
+        unsigned long rate = clk_get_rate(clk->parent);
-        .rate           = 54000000,
+        unsigned int ratio;
-};
-struct clk clk_hpll = {
-        .name           = "hpll",
-        .id             = -1,
-};
-struct clk clk_hd0 = {
+        ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_ARM_MASK;
-        .name           = "hclkd0",
+        ratio >>= S5PC100_CLKDIV0_ARM_SHIFT;
-        .id             = -1,
-        .rate           = 0,
-        .parent         = NULL,
-        .ctrlbit        = 0,
-        .set_rate       = clk_default_setrate,
-};
-struct clk clk_pd0 = {
+        return rate / (ratio + 1);
-        .name           = "pclkd0",
+}
-        .id             = -1,
-        .rate           = 0,
-        .parent         = NULL,
-        .ctrlbit        = 0,
-        .set_rate       = clk_default_setrate,
-};
-static int s5pc1xx_clk_gate(void __iomem *reg,
+static unsigned long s5pc100_clk_arm_round_rate(struct clk *clk,
-                                struct clk *clk,
+                                                unsigned long rate)
-                                int enable)
 {
-        unsigned int ctrlbit = clk->ctrlbit;
+        unsigned long parent = clk_get_rate(clk->parent);
-        u32 con;
+        u32 div;
-        con = __raw_readl(reg);
+        if (parent < rate)
+                return rate;
-        if (enable)
+        div = (parent / rate) - 1;
-                con |= ctrlbit;
+        if (div > S5PC100_CLKDIV0_ARM_MASK)
-        else
+                div = S5PC100_CLKDIV0_ARM_MASK;
-                con &= ~ctrlbit;
-        __raw_writel(con, reg);
+        return parent / (div + 1);
-        return 0;
 }
-static int s5pc1xx_clk_d00_ctrl(struct clk *clk, int enable)
+static int s5pc100_clk_arm_set_rate(struct clk *clk, unsigned long rate)
 {
-        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D00, clk, enable);
+        unsigned long parent = clk_get_rate(clk->parent);
-}
+        u32 div;
+        u32 val;
-static int s5pc1xx_clk_d01_ctrl(struct clk *clk, int enable)
+        if (rate < parent / (S5PC100_CLKDIV0_ARM_MASK + 1))
-{
+                return -EINVAL;
-        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D01, clk, enable);
-}
-static int s5pc1xx_clk_d02_ctrl(struct clk *clk, int enable)
+        rate = clk_round_rate(clk, rate);
-{
+        div = clk_get_rate(clk->parent) / rate;
-        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D02, clk, enable);
-}
-static int s5pc1xx_clk_d10_ctrl(struct clk *clk, int enable)
+        val = __raw_readl(S5PC100_CLKDIV0);
-{
+        val &= S5PC100_CLKDIV0_ARM_MASK;
-        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D10, clk, enable);
+        val |= (div - 1);
-}
+        __raw_writel(val, S5PC100_CLKDIV0);
-static int s5pc1xx_clk_d11_ctrl(struct clk *clk, int enable)
+        return 0;
-{
-        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D11, clk, enable);
 }
-static int s5pc1xx_clk_d12_ctrl(struct clk *clk, int enable)
+static struct clk clk_arm = {
-{
+        .name           = "armclk",
-        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D12, clk, enable);
+        .id             = -1,
-}
+        .parent         = &clk_dout_apll,
+        .get_rate       = s5pc100_clk_arm_get_rate,
+        .set_rate       = s5pc100_clk_arm_set_rate,
+        .round_rate     = s5pc100_clk_arm_round_rate,
+};
-static int s5pc1xx_clk_d13_ctrl(struct clk *clk, int enable)
+static unsigned long s5pc100_clk_dout_d0_bus_get_rate(struct clk *clk)
 {
-        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D13, clk, enable);
+        unsigned long rate = clk_get_rate(clk->parent);
-}
+        unsigned int ratio;
-static int s5pc1xx_clk_d14_ctrl(struct clk *clk, int enable)
+        ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_D0_MASK;
-{
+        ratio >>= S5PC100_CLKDIV0_D0_SHIFT;
-        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D14, clk, enable);
-}
-static int s5pc1xx_clk_d15_ctrl(struct clk *clk, int enable)
+        return rate / (ratio + 1);
-{
-        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D15, clk, enable);
 }
-static int s5pc1xx_clk_d20_ctrl(struct clk *clk, int enable)
+static struct clk clk_dout_d0_bus = {
-{
+        .name           = "dout_d0_bus",
-        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D20, clk, enable);
+        .id             = -1,
-}
+        .parent         = &clk_arm,
+        .get_rate       = s5pc100_clk_dout_d0_bus_get_rate,
+};
-int s5pc1xx_sclk0_ctrl(struct clk *clk, int enable)
+static unsigned long s5pc100_clk_dout_pclkd0_get_rate(struct clk *clk)
 {
-        return s5pc1xx_clk_gate(S5PC100_SCLKGATE0, clk, enable);
+        unsigned long rate = clk_get_rate(clk->parent);
+        unsigned int ratio;
+        ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_PCLKD0_MASK;
+        ratio >>= S5PC100_CLKDIV0_PCLKD0_SHIFT;
+        return rate / (ratio + 1);
 }
-int s5pc1xx_sclk1_ctrl(struct clk *clk, int enable)
+static struct clk clk_dout_pclkd0 = {
+        .name           = "dout_pclkd0",
+        .id             = -1,
+        .parent         = &clk_dout_d0_bus,
+        .get_rate       = s5pc100_clk_dout_pclkd0_get_rate,
+};
+static unsigned long s5pc100_clk_dout_apll2_get_rate(struct clk *clk)
 {
-        return s5pc1xx_clk_gate(S5PC100_SCLKGATE1, clk, enable);
+        unsigned long rate = clk_get_rate(clk->parent);
+        unsigned int ratio;
+        ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_APLL2_MASK;
+        ratio >>= S5PC100_CLKDIV1_APLL2_SHIFT;
+        return rate / (ratio + 1);
 }
-static struct clk init_clocks_disable[] = {
+static struct clk clk_dout_apll2 = {
-        {
+        .name           = "dout_apll2",
-                .name           = "dsi",
+        .id             = -1,
-                .id             = -1,
+        .parent         = &clk_mout_apll.clk,
-                .parent         = &clk_p,
+        .get_rate       = s5pc100_clk_dout_apll2_get_rate,
-                .enable         = s5pc1xx_clk_d11_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D11_DSI,
-        }, {
-                .name           = "csi",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d11_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D11_CSI,
-        }, {
-                .name           = "ccan0",
-                .id             = 0,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_CCAN0,
-        }, {
-                .name           = "ccan1",
-                .id             = 1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_CCAN1,
-        }, {
-                .name           = "keypad",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d15_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D15_KEYIF,
-        }, {
-                .name           = "hclkd2",
-                .id             = -1,
-                .parent         = NULL,
-                .enable         = s5pc1xx_clk_d20_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D20_HCLKD2,
-        }, {
-                .name           = "iis-d2",
-                .id             = -1,
-                .parent         = NULL,
-                .enable         = s5pc1xx_clk_d20_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D20_I2SD2,
-        }, {
-                .name           = "otg",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d10_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D10_USBOTG,
-        },
 };
-static struct clk init_clocks[] = {
+/* MPLL */
-        /* System1 (D0_0) devices */
+static struct clk *clk_src_mpll_list[] = {
-        {
+        [0] = &clk_fin_mpll,
-                .name           = "intc",
+        [1] = &clk_fout_mpll,
-                .id             = -1,
+};
-                .parent         = &clk_hd0,
-                .enable         = s5pc1xx_clk_d00_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D00_INTC,
-        }, {
-                .name           = "tzic",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc1xx_clk_d00_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D00_TZIC,
-        }, {
-                .name           = "cf-ata",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc1xx_clk_d00_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D00_CFCON,
-        }, {
-                .name           = "mdma",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc1xx_clk_d00_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D00_MDMA,
-        }, {
-                .name           = "g2d",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc1xx_clk_d00_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D00_G2D,
-        }, {
-                .name           = "secss",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc1xx_clk_d00_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D00_SECSS,
-        }, {
-                .name           = "cssys",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc1xx_clk_d00_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D00_CSSYS,
-        },
-        /* Memory (D0_1) devices */
+static struct clk_sources clk_src_mpll = {
-        {
+        .sources        = clk_src_mpll_list,
-                .name           = "dmc",
+        .nr_sources     = ARRAY_SIZE(clk_src_mpll_list),
-                .id             = -1,
+};
-                .parent         = &clk_hd0,
-                .enable         = s5pc1xx_clk_d01_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D01_DMC,
-        }, {
-                .name           = "sromc",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc1xx_clk_d01_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D01_SROMC,
-        }, {
-                .name           = "onenand",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc1xx_clk_d01_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D01_ONENAND,
-        }, {
-                .name           = "nand",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc1xx_clk_d01_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D01_NFCON,
-        }, {
-                .name           = "intmem",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc1xx_clk_d01_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D01_INTMEM,
-        }, {
-                .name           = "ebi",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc1xx_clk_d01_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D01_EBI,
-        },
-        /* System2 (D0_2) devices */
+static struct clksrc_clk clk_mout_mpll = {
-        {
+        .clk = {
-                .name           = "seckey",
+                .name           = "mout_mpll",
-                .id             = -1,
-                .parent         = &clk_pd0,
-                .enable         = s5pc1xx_clk_d02_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D02_SECKEY,
-        }, {
-                .name           = "sdm",
                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc1xx_clk_d02_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D02_SDM,
        },
+        .shift          = S5PC100_CLKSRC0_MPLL_SHIFT,
+        .mask           = S5PC100_CLKSRC0_MPLL_MASK,
+        .sources        = &clk_src_mpll,
+        .reg_source     = S5PC100_CLKSRC0,
+};
-        /* File (D1_0) devices */
+static struct clk *clkset_am_list[] = {
-        {
+        [0] = &clk_mout_mpll.clk,
-                .name           = "pdma0",
+        [1] = &clk_dout_apll2,
-                .id             = -1,
+};
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d10_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D10_PDMA0,
-        }, {
-                .name           = "pdma1",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d10_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D10_PDMA1,
-        }, {
-                .name           = "usb-host",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d10_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D10_USBHOST,
-        }, {
-                .name           = "modem",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d10_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D10_MODEMIF,
-        }, {
-                .name           = "hsmmc",
-                .id             = 0,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d10_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D10_HSMMC0,
-        }, {
-                .name           = "hsmmc",
-                .id             = 1,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d10_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D10_HSMMC1,
-        }, {
-                .name           = "hsmmc",
-                .id             = 2,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d10_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D10_HSMMC2,
-        },
-        /* Multimedia1 (D1_1) devices */
+static struct clk_sources clk_src_am = {
-        {
+        .sources        = clkset_am_list,
-                .name           = "lcd",
+        .nr_sources     = ARRAY_SIZE(clkset_am_list),
-                .id             = -1,
+};
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d11_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D11_LCD,
-        }, {
-                .name           = "rotator",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d11_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D11_ROTATOR,
-        }, {
-                .name           = "fimc",
-                .id             = 0,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d11_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D11_FIMC0,
-        }, {
-                .name           = "fimc",
-                .id             = 1,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d11_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D11_FIMC1,
-        }, {
-                .name           = "fimc",
-                .id             = 2,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d11_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D11_FIMC2,
-        }, {
-                .name           = "jpeg",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d11_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D11_JPEG,
-        }, {
-                .name           = "g3d",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d11_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D11_G3D,
-        },
-        /* Multimedia2 (D1_2) devices */
+static struct clksrc_clk clk_mout_am = {
-        {
+        .clk = {
-                .name           = "tv",
+                .name           = "mout_am",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d12_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D12_TV,
-        }, {
-                .name           = "vp",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d12_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D12_VP,
-        }, {
-                .name           = "mixer",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d12_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D12_MIXER,
-        }, {
-                .name           = "hdmi",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d12_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D12_HDMI,
-        }, {
-                .name           = "mfc",
                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d12_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D12_MFC,
        },
+        .shift          = S5PC100_CLKSRC0_AMMUX_SHIFT,
+        .mask           = S5PC100_CLKSRC0_AMMUX_MASK,
+        .sources        = &clk_src_am,
+        .reg_source     = S5PC100_CLKSRC0,
+};
-        /* System (D1_3) devices */
+static unsigned long s5pc100_clk_dout_d1_bus_get_rate(struct clk *clk)
-        {
+{
-                .name           = "chipid",
+        unsigned long rate = clk_get_rate(clk->parent);
-                .id             = -1,
+        unsigned int ratio;
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d13_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D13_CHIPID,
-        }, {
-                .name           = "gpio",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d13_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D13_GPIO,
-        }, {
-                .name           = "apc",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d13_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D13_APC,
-        }, {
-                .name           = "iec",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d13_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D13_IEC,
-        }, {
-                .name           = "timers",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d13_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D13_PWM,
-        }, {
-                .name           = "systimer",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d13_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D13_SYSTIMER,
-        }, {
-                .name           = "watchdog",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d13_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D13_WDT,
-        }, {
-                .name           = "rtc",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d13_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D13_RTC,
-        },
-        /* Connectivity (D1_4) devices */
+        printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
-        {
-                .name           = "uart",
-                .id             = 0,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_UART0,
-        }, {
-                .name           = "uart",
-                .id             = 1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_UART1,
-        }, {
-                .name           = "uart",
-                .id             = 2,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_UART2,
-        }, {
-                .name           = "uart",
-                .id             = 3,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_UART3,
-        }, {
-                .name           = "i2c",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_IIC,
-        }, {
-                .name           = "hdmi-i2c",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_HDMI_IIC,
-        }, {
-                .name           = "spi",
-                .id             = 0,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_SPI0,
-        }, {
-                .name           = "spi",
-                .id             = 1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_SPI1,
-        }, {
-                .name           = "spi",
-                .id             = 2,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_SPI2,
-        }, {
-                .name           = "irda",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_IRDA,
-        }, {
-                .name           = "hsitx",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_HSITX,
-        }, {
-                .name           = "hsirx",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_HSIRX,
-        },
-        /* Audio (D1_5) devices */
+        ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_D1_MASK;
-        {
+        ratio >>= S5PC100_CLKDIV1_D1_SHIFT;
-                .name           = "iis",
-                .id             = 0,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d15_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D15_IIS0,
-        }, {
-                .name           = "iis",
-                .id             = 1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d15_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D15_IIS1,
-        }, {
-                .name           = "iis",
-                .id             = 2,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d15_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D15_IIS2,
-        }, {
-                .name           = "ac97",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d15_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D15_AC97,
-        }, {
-                .name           = "pcm",
-                .id             = 0,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d15_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D15_PCM0,
-        }, {
-                .name           = "pcm",
-                .id             = 1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d15_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D15_PCM1,
-        }, {
-                .name           = "spdif",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d15_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D15_SPDIF,
-        }, {
-                .name           = "adc",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d15_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D15_TSADC,
-        }, {
-                .name           = "keyif",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d15_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D15_KEYIF,
-        }, {
-                .name           = "cg",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d15_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D15_CG,
-        },
-        /* Audio (D2_0) devices: all disabled */
+        return rate / (ratio + 1);
+}
-        /* Special Clocks 1 */
+static struct clk clk_dout_d1_bus = {
-        {
+        .name           = "dout_d1_bus",
-                .name           = "sclk_hpm",
+        .id             = -1,
-                .id             = -1,
+        .parent         = &clk_mout_am.clk,
-                .parent         = NULL,
+        .get_rate       = s5pc100_clk_dout_d1_bus_get_rate,
-                .enable         = s5pc1xx_sclk0_ctrl,
+};
-                .ctrlbit        = S5PC1XX_CLKGATE_SCLK0_HPM,
-        }, {
-                .name           = "sclk_onenand",
-                .id             = -1,
-                .parent         = NULL,
-                .enable         = s5pc1xx_sclk0_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_SCLK0_ONENAND,
-        }, {
-                .name           = "sclk_spi_48",
-                .id             = 0,
-                .parent         = &clk_48m,
-                .enable         = s5pc1xx_sclk0_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_SCLK0_SPI0_48,
-        }, {
-                .name           = "sclk_spi_48",
-                .id             = 1,
-                .parent         = &clk_48m,
-                .enable         = s5pc1xx_sclk0_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_SCLK0_SPI1_48,
-        }, {
-                .name           = "sclk_spi_48",
-                .id             = 2,
-                .parent         = &clk_48m,
-                .enable         = s5pc1xx_sclk0_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_SCLK0_SPI2_48,
-        }, {
-                .name           = "sclk_mmc_48",
-                .id             = 0,
-                .parent         = &clk_48m,
-                .enable         = s5pc1xx_sclk0_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_SCLK0_MMC0_48,
-        }, {
-                .name           = "sclk_mmc_48",
-                .id             = 1,
-                .parent         = &clk_48m,
-                .enable         = s5pc1xx_sclk0_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_SCLK0_MMC1_48,
-        }, {
-                .name           = "sclk_mmc_48",
-                .id             = 2,
-                .parent         = &clk_48m,
-                .enable         = s5pc1xx_sclk0_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_SCLK0_MMC2_48,
-        },
-        /* Special Clocks 2 */
+static struct clk *clkset_onenand_list[] = {
-        {
+        [0] = &clk_dout_d0_bus,
-                .name           = "sclk_tv_54",
+        [1] = &clk_dout_d1_bus,
-                .id             = -1,
+};
-                .parent         = &clk_54m,
-                .enable         = s5pc1xx_sclk1_ctrl,
+static struct clk_sources clk_src_onenand = {
-                .ctrlbit        = S5PC100_CLKGATE_SCLK1_TV54,
+        .sources        = clkset_onenand_list,
-        }, {
+        .nr_sources     = ARRAY_SIZE(clkset_onenand_list),
-                .name           = "sclk_vdac_54",
+};
-                .id             = -1,
-                .parent         = &clk_54m,
+static struct clksrc_clk clk_mout_onenand = {
-                .enable         = s5pc1xx_sclk1_ctrl,
+        .clk = {
-                .ctrlbit        = S5PC100_CLKGATE_SCLK1_VDAC54,
+                .name           = "mout_onenand",
-        }, {
-                .name           = "sclk_spdif",
                .id             = -1,
-                .parent         = NULL,
-                .enable         = s5pc1xx_sclk1_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_SCLK1_SPDIF,
        },
+        .shift          = S5PC100_CLKSRC0_ONENAND_SHIFT,
+        .mask           = S5PC100_CLKSRC0_ONENAND_MASK,
+        .sources        = &clk_src_onenand,
+        .reg_source     = S5PC100_CLKSRC0,
 };
-void __init s5pc1xx_register_clocks(void)
+static unsigned long s5pc100_clk_dout_pclkd1_get_rate(struct clk *clk)
 {
-        struct clk *clkp;
+        unsigned long rate = clk_get_rate(clk->parent);
-        int ret;
+        unsigned int ratio;
-        int ptr;
-        clkp = init_clocks;
+        printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
-        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
-                ret = s3c24xx_register_clock(clkp);
-                if (ret < 0) {
-                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
-                               clkp->name, ret);
-                }
-        }
-        clkp = init_clocks_disable;
+        ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_PCLKD1_MASK;
-        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
+        ratio >>= S5PC100_CLKDIV1_PCLKD1_SHIFT;
-                ret = s3c24xx_register_clock(clkp);
+        return rate / (ratio + 1);
-                if (ret < 0) {
+}
-                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
-                               clkp->name, ret);
-                }
-                (clkp->enable)(clkp, 0);
+static struct clk clk_dout_pclkd1 = {
-        }
+        .name           = "dout_pclkd1",
+        .id             = -1,
+        .parent         = &clk_dout_d1_bus,
+        .get_rate       = s5pc100_clk_dout_pclkd1_get_rate,
+};
+static unsigned long s5pc100_clk_dout_mpll2_get_rate(struct clk *clk)
+{
+        unsigned long rate = clk_get_rate(clk->parent);
+        unsigned int ratio;
+        printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
+        ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_MPLL2_MASK;
+        ratio >>= S5PC100_CLKDIV1_MPLL2_SHIFT;
-        s3c_pwmclk_init();
+        return rate / (ratio + 1);
 }
-static struct clk clk_fout_apll = {
-        .name           = "fout_apll",
+static struct clk clk_dout_mpll2 = {
+        .name           = "dout_mpll2",
        .id             = -1,
+        .parent         = &clk_mout_am.clk,
+        .get_rate       = s5pc100_clk_dout_mpll2_get_rate,
 };
-static struct clk *clk_src_apll_list[] = {
+static unsigned long s5pc100_clk_dout_cam_get_rate(struct clk *clk)
-        [0] = &clk_fin_apll,
+{
-        [1] = &clk_fout_apll,
+        unsigned long rate = clk_get_rate(clk->parent);
-};
+        unsigned int ratio;
-static struct clk_sources clk_src_apll = {
+        printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
-        .sources        = clk_src_apll_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_apll_list),
+        ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_CAM_MASK;
+        ratio >>= S5PC100_CLKDIV1_CAM_SHIFT;
+        return rate / (ratio + 1);
+}
+static struct clk clk_dout_cam = {
+        .name           = "dout_cam",
+        .id             = -1,
+        .parent         = &clk_dout_mpll2,
+        .get_rate       = s5pc100_clk_dout_cam_get_rate,
 };
-static struct clksrc_clk clk_mout_apll = {
+static unsigned long s5pc100_clk_dout_mpll_get_rate(struct clk *clk)
-        .clk    = {
+{
-                .name           = "mout_apll",
+        unsigned long rate = clk_get_rate(clk->parent);
-                .id             = -1,
+        unsigned int ratio;
-        },
-        .shift          = S5PC1XX_CLKSRC0_APLL_SHIFT,
+        printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
-        .mask           = S5PC1XX_CLKSRC0_APLL_MASK,
-        .sources        = &clk_src_apll,
+        ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_MPLL_MASK;
-        .reg_source     = S5PC1XX_CLK_SRC0,
+        ratio >>= S5PC100_CLKDIV1_MPLL_SHIFT;
+        return rate / (ratio + 1);
+}
+static struct clk clk_dout_mpll = {
+        .name           = "dout_mpll",
+        .id             = -1,
+        .parent         = &clk_mout_am.clk,
+        .get_rate       = s5pc100_clk_dout_mpll_get_rate,
 };
+/* EPLL */
 static struct clk clk_fout_epll = {
        .name           = "fout_epll",
        .id             = -1,
@@ -827,91 +409,57 @@ static struct clksrc_clk clk_mout_epll = {
                .name           = "mout_epll",
                .id             = -1,
        },
-        .shift          = S5PC1XX_CLKSRC0_EPLL_SHIFT,
+        .shift          = S5PC100_CLKSRC0_EPLL_SHIFT,
-        .mask           = S5PC1XX_CLKSRC0_EPLL_MASK,
+        .mask           = S5PC100_CLKSRC0_EPLL_MASK,
        .sources        = &clk_src_epll,
-        .reg_source     = S5PC1XX_CLK_SRC0,
+        .reg_source     = S5PC100_CLKSRC0,
 };
-static struct clk *clk_src_mpll_list[] = {
+/* HPLL */
-        [0] = &clk_fin_mpll,
+static struct clk clk_fout_hpll = {
-        [1] = &clk_fout_mpll,
+        .name           = "fout_hpll",
-};
-static struct clk_sources clk_src_mpll = {
-        .sources        = clk_src_mpll_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_mpll_list),
-};
-static struct clksrc_clk clk_mout_mpll = {
-        .clk = {
-                .name           = "mout_mpll",
-                .id             = -1,
-        },
-        .shift          = S5PC1XX_CLKSRC0_MPLL_SHIFT,
-        .mask           = S5PC1XX_CLKSRC0_MPLL_MASK,
-        .sources        = &clk_src_mpll,
-        .reg_source     = S5PC1XX_CLK_SRC0,
-};
-static unsigned long s5pc1xx_clk_doutmpll_get_rate(struct clk *clk)
-{
-        unsigned long rate = clk_get_rate(clk->parent);
-        unsigned long clkdiv;
-        printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
-        clkdiv = __raw_readl(S5PC1XX_CLK_DIV1) & S5PC100_CLKDIV1_MPLL_MASK;
-        rate /= (clkdiv >> S5PC100_CLKDIV1_MPLL_SHIFT) + 1;
-        return rate;
-}
-static struct clk clk_dout_mpll = {
-        .name           = "dout_mpll",
        .id             = -1,
-        .parent         = &clk_mout_mpll.clk,
-        .get_rate       = s5pc1xx_clk_doutmpll_get_rate,
 };
-static unsigned long s5pc1xx_clk_doutmpll2_get_rate(struct clk *clk)
+static struct clk *clk_src_hpll_list[] = {
-{
+        [0] = &clk_27m,
-        unsigned long rate = clk_get_rate(clk->parent);
+        [1] = &clk_fout_hpll,
-        unsigned long clkdiv;
-        printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
-        clkdiv = __raw_readl(S5PC1XX_CLK_DIV1) & S5PC100_CLKDIV1_MPLL2_MASK;
-        rate /= (clkdiv >> S5PC100_CLKDIV1_MPLL2_SHIFT) + 1;
-        return rate;
-}
-struct clk clk_dout_mpll2 = {
-        .name           = "dout_mpll2",
-        .id             = -1,
-        .parent         = &clk_mout_mpll.clk,
-        .get_rate       = s5pc1xx_clk_doutmpll2_get_rate,
 };
-static struct clk *clkset_uart_list[] = {
+static struct clk_sources clk_src_hpll = {
-        &clk_mout_epll.clk,
+        .sources        = clk_src_hpll_list,
-        &clk_dout_mpll,
+        .nr_sources     = ARRAY_SIZE(clk_src_hpll_list),
-        NULL,
-        NULL
 };
-static struct clk_sources clkset_uart = {
+static struct clksrc_clk clk_mout_hpll = {
-        .sources        = clkset_uart_list,
+        .clk    = {
-        .nr_sources     = ARRAY_SIZE(clkset_uart_list),
+                .name           = "mout_hpll",
+                .id             = -1,
+        },
+        .shift          = S5PC100_CLKSRC0_HPLL_SHIFT,
+        .mask           = S5PC100_CLKSRC0_HPLL_MASK,
+        .sources        = &clk_src_hpll,
+        .reg_source     = S5PC100_CLKSRC0,
 };
+/* Peripherals */
+/*
+ * The peripheral clocks are all controlled via clocksource followed
+ * by an optional divider and gate stage. We currently roll this into
+ * one clock which hides the intermediate clock from the mux.
+ *
+ * Note, the JPEG clock can only be an even divider...
+ *
+ * The scaler and LCD clocks depend on the S5PC100 version, and also
+ * have a common parent divisor so are not included here.
+ */
 static inline struct clksrc_clk *to_clksrc(struct clk *clk)
 {
        return container_of(clk, struct clksrc_clk, clk);
 }
-static unsigned long s5pc1xx_getrate_clksrc(struct clk *clk)
+static unsigned long s5pc100_getrate_clksrc(struct clk *clk)
 {
        struct clksrc_clk *sclk = to_clksrc(clk);
        unsigned long rate = clk_get_rate(clk->parent);
@@ -925,7 +473,7 @@ static unsigned long s5pc1xx_getrate_clksrc(struct clk *clk)
        return rate;
 }
-static int s5pc1xx_setrate_clksrc(struct clk *clk, unsigned long rate)
+static int s5pc100_setrate_clksrc(struct clk *clk, unsigned long rate)
 {
        struct clksrc_clk *sclk = to_clksrc(clk);
        void __iomem *reg = sclk->reg_divider;
@@ -938,14 +486,14 @@ static int s5pc1xx_setrate_clksrc(struct clk *clk, unsigned long rate)
                return -EINVAL;
        val = __raw_readl(reg);
-        val &= ~(0xf << sclk->shift);
+        val &= ~(0xf << sclk->divider_shift);
-        val |= (div - 1) << sclk->shift;
+        val |= (div - 1) << sclk->divider_shift;
        __raw_writel(val, reg);
        return 0;
 }
-static int s5pc1xx_setparent_clksrc(struct clk *clk, struct clk *parent)
+static int s5pc100_setparent_clksrc(struct clk *clk, struct clk *parent)
 {
        struct clksrc_clk *sclk = to_clksrc(clk);
        struct clk_sources *srcs = sclk->sources;
@@ -970,7 +518,7 @@ static int s5pc1xx_setparent_clksrc(struct clk *clk, struct clk *parent)
        return -EINVAL;
 }
-static unsigned long s5pc1xx_roundrate_clksrc(struct clk *clk,
+static unsigned long s5pc100_roundrate_clksrc(struct clk *clk,
                                              unsigned long rate)
 {
        unsigned long parent_rate = clk_get_rate(clk->parent);
@@ -992,35 +540,466 @@ static unsigned long s5pc1xx_roundrate_clksrc(struct clk *clk,
        return rate;
 }
+static struct clk *clkset_spi_list[] = {
+        &clk_mout_epll.clk,
+        &clk_dout_mpll2,
+        &clk_fin_epll,
+        &clk_mout_hpll.clk,
+};
+static struct clk_sources clkset_spi = {
+        .sources        = clkset_spi_list,
+        .nr_sources     = ARRAY_SIZE(clkset_spi_list),
+};
+static struct clksrc_clk clk_spi0 = {
+        .clk    = {
+                .name           = "spi_bus",
+                .id             = 0,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_SPI0,
+                .enable         = s5pc100_sclk0_ctrl,
+                .set_parent     = s5pc100_setparent_clksrc,
+                .get_rate       = s5pc100_getrate_clksrc,
+                .set_rate       = s5pc100_setrate_clksrc,
+                .round_rate     = s5pc100_roundrate_clksrc,
+        },
+        .shift          = S5PC100_CLKSRC1_SPI0_SHIFT,
+        .mask           = S5PC100_CLKSRC1_SPI0_MASK,
+        .sources        = &clkset_spi,
+        .divider_shift  = S5PC100_CLKDIV2_SPI0_SHIFT,
+        .reg_divider    = S5PC100_CLKDIV2,
+        .reg_source     = S5PC100_CLKSRC1,
+};
+static struct clksrc_clk clk_spi1 = {
+        .clk    = {
+                .name           = "spi_bus",
+                .id             = 1,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_SPI1,
+                .enable         = s5pc100_sclk0_ctrl,
+                .set_parent     = s5pc100_setparent_clksrc,
+                .get_rate       = s5pc100_getrate_clksrc,
+                .set_rate       = s5pc100_setrate_clksrc,
+                .round_rate     = s5pc100_roundrate_clksrc,
+        },
+        .shift          = S5PC100_CLKSRC1_SPI1_SHIFT,
+        .mask           = S5PC100_CLKSRC1_SPI1_MASK,
+        .sources        = &clkset_spi,
+        .divider_shift  = S5PC100_CLKDIV2_SPI1_SHIFT,
+        .reg_divider    = S5PC100_CLKDIV2,
+        .reg_source     = S5PC100_CLKSRC1,
+};
+static struct clksrc_clk clk_spi2 = {
+        .clk    = {
+                .name           = "spi_bus",
+                .id             = 2,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_SPI2,
+                .enable         = s5pc100_sclk0_ctrl,
+                .set_parent     = s5pc100_setparent_clksrc,
+                .get_rate       = s5pc100_getrate_clksrc,
+                .set_rate       = s5pc100_setrate_clksrc,
+                .round_rate     = s5pc100_roundrate_clksrc,
+        },
+        .shift          = S5PC100_CLKSRC1_SPI2_SHIFT,
+        .mask           = S5PC100_CLKSRC1_SPI2_MASK,
+        .sources        = &clkset_spi,
+        .divider_shift  = S5PC100_CLKDIV2_SPI2_SHIFT,
+        .reg_divider    = S5PC100_CLKDIV2,
+        .reg_source     = S5PC100_CLKSRC1,
+};
+static struct clk *clkset_uart_list[] = {
+        &clk_mout_epll.clk,
+        &clk_dout_mpll,
+};
+static struct clk_sources clkset_uart = {
+        .sources        = clkset_uart_list,
+        .nr_sources     = ARRAY_SIZE(clkset_uart_list),
+};
 static struct clksrc_clk clk_uart_uclk1 = {
        .clk    = {
                .name           = "uclk1",
                .id             = -1,
                .ctrlbit        = S5PC100_CLKGATE_SCLK0_UART,
-                .enable         = s5pc1xx_sclk0_ctrl,
+                .enable         = s5pc100_sclk0_ctrl,
-                .set_parent     = s5pc1xx_setparent_clksrc,
+                .set_parent     = s5pc100_setparent_clksrc,
-                .get_rate       = s5pc1xx_getrate_clksrc,
+                .get_rate       = s5pc100_getrate_clksrc,
-                .set_rate       = s5pc1xx_setrate_clksrc,
+                .set_rate       = s5pc100_setrate_clksrc,
-                .round_rate     = s5pc1xx_roundrate_clksrc,
+                .round_rate     = s5pc100_roundrate_clksrc,
        },
        .shift          = S5PC100_CLKSRC1_UART_SHIFT,
        .mask           = S5PC100_CLKSRC1_UART_MASK,
        .sources        = &clkset_uart,
        .divider_shift  = S5PC100_CLKDIV2_UART_SHIFT,
-        .reg_divider    = S5PC1XX_CLK_DIV2,
+        .reg_divider    = S5PC100_CLKDIV2,
-        .reg_source     = S5PC1XX_CLK_SRC1,
+        .reg_source     = S5PC100_CLKSRC1,
+};
+static struct clk clk_iis_cd0 = {
+        .name           = "iis_cdclk0",
+        .id             = -1,
+};
+static struct clk clk_iis_cd1 = {
+        .name           = "iis_cdclk1",
+        .id             = -1,
+};
+static struct clk clk_iis_cd2 = {
+        .name           = "iis_cdclk2",
+        .id             = -1,
+};
+static struct clk clk_pcm_cd0 = {
+        .name           = "pcm_cdclk0",
+        .id             = -1,
+};
+static struct clk clk_pcm_cd1 = {
+        .name           = "pcm_cdclk1",
+        .id             = -1,
+};
+static struct clk *clkset_audio0_list[] = {
+        &clk_mout_epll.clk,
+        &clk_dout_mpll,
+        &clk_fin_epll,
+        &clk_iis_cd0,
+        &clk_pcm_cd0,
+        &clk_mout_hpll.clk,
+};
+static struct clk_sources clkset_audio0 = {
+        .sources        = clkset_audio0_list,
+        .nr_sources     = ARRAY_SIZE(clkset_audio0_list),
+};
+static struct clksrc_clk clk_audio0 = {
+        .clk    = {
+                .name           = "audio-bus",
+                .id             = 0,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK1_AUDIO0,
+                .enable         = s5pc100_sclk1_ctrl,
+                .set_parent     = s5pc100_setparent_clksrc,
+                .get_rate       = s5pc100_getrate_clksrc,
+                .set_rate       = s5pc100_setrate_clksrc,
+                .round_rate     = s5pc100_roundrate_clksrc,
+        },
+        .shift          = S5PC100_CLKSRC3_AUDIO0_SHIFT,
+        .mask           = S5PC100_CLKSRC3_AUDIO0_MASK,
+        .sources        = &clkset_audio0,
+        .divider_shift  = S5PC100_CLKDIV4_AUDIO0_SHIFT,
+        .reg_divider    = S5PC100_CLKDIV4,
+        .reg_source     = S5PC100_CLKSRC3,
+};
+static struct clk *clkset_audio1_list[] = {
+        &clk_mout_epll.clk,
+        &clk_dout_mpll,
+        &clk_fin_epll,
+        &clk_iis_cd1,
+        &clk_pcm_cd1,
+        &clk_mout_hpll.clk,
+};
+static struct clk_sources clkset_audio1 = {
+        .sources        = clkset_audio1_list,
+        .nr_sources     = ARRAY_SIZE(clkset_audio1_list),
+};
+static struct clksrc_clk clk_audio1 = {
+        .clk    = {
+                .name           = "audio-bus",
+                .id             = 1,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK1_AUDIO1,
+                .enable         = s5pc100_sclk1_ctrl,
+                .set_parent     = s5pc100_setparent_clksrc,
+                .get_rate       = s5pc100_getrate_clksrc,
+                .set_rate       = s5pc100_setrate_clksrc,
+                .round_rate     = s5pc100_roundrate_clksrc,
+        },
+        .shift          = S5PC100_CLKSRC3_AUDIO1_SHIFT,
+        .mask           = S5PC100_CLKSRC3_AUDIO1_MASK,
+        .sources        = &clkset_audio1,
+        .divider_shift  = S5PC100_CLKDIV4_AUDIO1_SHIFT,
+        .reg_divider    = S5PC100_CLKDIV4,
+        .reg_source     = S5PC100_CLKSRC3,
+};
+static struct clk *clkset_audio2_list[] = {
+        &clk_mout_epll.clk,
+        &clk_dout_mpll,
+        &clk_fin_epll,
+        &clk_iis_cd2,
+        &clk_mout_hpll.clk,
+};
+static struct clk_sources clkset_audio2 = {
+        .sources        = clkset_audio2_list,
+        .nr_sources     = ARRAY_SIZE(clkset_audio2_list),
+};
+static struct clksrc_clk clk_audio2 = {
+        .clk    = {
+                .name           = "audio-bus",
+                .id             = 2,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK1_AUDIO2,
+                .enable         = s5pc100_sclk1_ctrl,
+                .set_parent     = s5pc100_setparent_clksrc,
+                .get_rate       = s5pc100_getrate_clksrc,
+                .set_rate       = s5pc100_setrate_clksrc,
+                .round_rate     = s5pc100_roundrate_clksrc,
+        },
+        .shift          = S5PC100_CLKSRC3_AUDIO2_SHIFT,
+        .mask           = S5PC100_CLKSRC3_AUDIO2_MASK,
+        .sources        = &clkset_audio2,
+        .divider_shift  = S5PC100_CLKDIV4_AUDIO2_SHIFT,
+        .reg_divider    = S5PC100_CLKDIV4,
+        .reg_source     = S5PC100_CLKSRC3,
+};
+static struct clk *clkset_spdif_list[] = {
+        &clk_audio0.clk,
+        &clk_audio1.clk,
+        &clk_audio2.clk,
+};
+static struct clk_sources clkset_spdif = {
+        .sources        = clkset_spdif_list,
+        .nr_sources     = ARRAY_SIZE(clkset_spdif_list),
+};
+static struct clksrc_clk clk_spdif = {
+        .clk    = {
+                .name           = "spdif",
+                .id             = -1,
+        },
+        .shift          = S5PC100_CLKSRC3_SPDIF_SHIFT,
+        .mask           = S5PC100_CLKSRC3_SPDIF_MASK,
+        .sources        = &clkset_spdif,
+        .reg_source     = S5PC100_CLKSRC3,
+};
+static struct clk *clkset_lcd_fimc_list[] = {
+        &clk_mout_epll.clk,
+        &clk_dout_mpll,
+        &clk_mout_hpll.clk,
+        &clk_vclk_54m,
+};
+static struct clk_sources clkset_lcd_fimc = {
+        .sources        = clkset_lcd_fimc_list,
+        .nr_sources     = ARRAY_SIZE(clkset_lcd_fimc_list),
+};
+static struct clksrc_clk clk_lcd = {
+        .clk    = {
+                .name           = "lcd",
+                .id             = -1,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK1_LCD,
+                .enable         = s5pc100_sclk1_ctrl,
+                .set_parent     = s5pc100_setparent_clksrc,
+                .get_rate       = s5pc100_getrate_clksrc,
+                .set_rate       = s5pc100_setrate_clksrc,
+                .round_rate     = s5pc100_roundrate_clksrc,
+        },
+        .shift          = S5PC100_CLKSRC2_LCD_SHIFT,
+        .mask           = S5PC100_CLKSRC2_LCD_MASK,
+        .sources        = &clkset_lcd_fimc,
+        .divider_shift  = S5PC100_CLKDIV3_LCD_SHIFT,
+        .reg_divider    = S5PC100_CLKDIV3,
+        .reg_source     = S5PC100_CLKSRC2,
+};
+static struct clksrc_clk clk_fimc0 = {
+        .clk    = {
+                .name           = "fimc",
+                .id             = 0,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK1_FIMC0,
+                .enable         = s5pc100_sclk1_ctrl,
+                .set_parent     = s5pc100_setparent_clksrc,
+                .get_rate       = s5pc100_getrate_clksrc,
+                .set_rate       = s5pc100_setrate_clksrc,
+                .round_rate     = s5pc100_roundrate_clksrc,
+        },
+        .shift          = S5PC100_CLKSRC2_FIMC0_SHIFT,
+        .mask           = S5PC100_CLKSRC2_FIMC0_MASK,
+        .sources        = &clkset_lcd_fimc,
+        .divider_shift  = S5PC100_CLKDIV3_FIMC0_SHIFT,
+        .reg_divider    = S5PC100_CLKDIV3,
+        .reg_source     = S5PC100_CLKSRC2,
+};
+static struct clksrc_clk clk_fimc1 = {
+        .clk    = {
+                .name           = "fimc",
+                .id             = 1,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK1_FIMC1,
+                .enable         = s5pc100_sclk1_ctrl,
+                .set_parent     = s5pc100_setparent_clksrc,
+                .get_rate       = s5pc100_getrate_clksrc,
+                .set_rate       = s5pc100_setrate_clksrc,
+                .round_rate     = s5pc100_roundrate_clksrc,
+        },
+        .shift          = S5PC100_CLKSRC2_FIMC1_SHIFT,
+        .mask           = S5PC100_CLKSRC2_FIMC1_MASK,
+        .sources        = &clkset_lcd_fimc,
+        .divider_shift  = S5PC100_CLKDIV3_FIMC1_SHIFT,
+        .reg_divider    = S5PC100_CLKDIV3,
+        .reg_source     = S5PC100_CLKSRC2,
+};
+static struct clksrc_clk clk_fimc2 = {
+        .clk    = {
+                .name           = "fimc",
+                .id             = 2,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK1_FIMC2,
+                .enable         = s5pc100_sclk1_ctrl,
+                .set_parent     = s5pc100_setparent_clksrc,
+                .get_rate       = s5pc100_getrate_clksrc,
+                .set_rate       = s5pc100_setrate_clksrc,
+                .round_rate     = s5pc100_roundrate_clksrc,
+        },
+        .shift          = S5PC100_CLKSRC2_FIMC2_SHIFT,
+        .mask           = S5PC100_CLKSRC2_FIMC2_MASK,
+        .sources        = &clkset_lcd_fimc,
+        .divider_shift  = S5PC100_CLKDIV3_FIMC2_SHIFT,
+        .reg_divider    = S5PC100_CLKDIV3,
+        .reg_source     = S5PC100_CLKSRC2,
+};
+static struct clk *clkset_mmc_list[] = {
+        &clk_mout_epll.clk,
+        &clk_dout_mpll,
+        &clk_fin_epll,
+        &clk_mout_hpll.clk ,
+};
+static struct clk_sources clkset_mmc = {
+        .sources        = clkset_mmc_list,
+        .nr_sources     = ARRAY_SIZE(clkset_mmc_list),
+};
+static struct clksrc_clk clk_mmc0 = {
+        .clk    = {
+                .name           = "mmc_bus",
+                .id             = 0,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_MMC0,
+                .enable         = s5pc100_sclk0_ctrl,
+                .set_parent     = s5pc100_setparent_clksrc,
+                .get_rate       = s5pc100_getrate_clksrc,
+                .set_rate       = s5pc100_setrate_clksrc,
+                .round_rate     = s5pc100_roundrate_clksrc,
+        },
+        .shift          = S5PC100_CLKSRC2_MMC0_SHIFT,
+        .mask           = S5PC100_CLKSRC2_MMC0_MASK,
+        .sources        = &clkset_mmc,
+        .divider_shift  = S5PC100_CLKDIV3_MMC0_SHIFT,
+        .reg_divider    = S5PC100_CLKDIV3,
+        .reg_source     = S5PC100_CLKSRC2,
+};
+static struct clksrc_clk clk_mmc1 = {
+        .clk    = {
+                .name           = "mmc_bus",
+                .id             = 1,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_MMC1,
+                .enable         = s5pc100_sclk0_ctrl,
+                .set_parent     = s5pc100_setparent_clksrc,
+                .get_rate       = s5pc100_getrate_clksrc,
+                .set_rate       = s5pc100_setrate_clksrc,
+                .round_rate     = s5pc100_roundrate_clksrc,
+        },
+        .shift          = S5PC100_CLKSRC2_MMC1_SHIFT,
+        .mask           = S5PC100_CLKSRC2_MMC1_MASK,
+        .sources        = &clkset_mmc,
+        .divider_shift  = S5PC100_CLKDIV3_MMC1_SHIFT,
+        .reg_divider    = S5PC100_CLKDIV3,
+        .reg_source     = S5PC100_CLKSRC2,
+};
+static struct clksrc_clk clk_mmc2 = {
+        .clk    = {
+                .name           = "mmc_bus",
+                .id             = 2,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_MMC2,
+                .enable         = s5pc100_sclk0_ctrl,
+                .set_parent     = s5pc100_setparent_clksrc,
+                .get_rate       = s5pc100_getrate_clksrc,
+                .set_rate       = s5pc100_setrate_clksrc,
+                .round_rate     = s5pc100_roundrate_clksrc,
+        },
+        .shift          = S5PC100_CLKSRC2_MMC2_SHIFT,
+        .mask           = S5PC100_CLKSRC2_MMC2_MASK,
+        .sources        = &clkset_mmc,
+        .divider_shift  = S5PC100_CLKDIV3_MMC2_SHIFT,
+        .reg_divider    = S5PC100_CLKDIV3,
+        .reg_source     = S5PC100_CLKSRC2,
+};
+static struct clk *clkset_usbhost_list[] = {
+        &clk_mout_epll.clk,
+        &clk_dout_mpll,
+        &clk_mout_hpll.clk,
+        &clk_48m,
+};
+static struct clk_sources clkset_usbhost = {
+        .sources        = clkset_usbhost_list,
+        .nr_sources     = ARRAY_SIZE(clkset_usbhost_list),
+};
+static struct clksrc_clk clk_usbhost = {
+        .clk    = {
+                .name           = "usbhost",
+                .id             = -1,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_USBHOST,
+                .enable         = s5pc100_sclk0_ctrl,
+                .set_parent     = s5pc100_setparent_clksrc,
+                .get_rate       = s5pc100_getrate_clksrc,
+                .set_rate       = s5pc100_setrate_clksrc,
+                .round_rate     = s5pc100_roundrate_clksrc,
+        },
+        .shift          = S5PC100_CLKSRC1_UHOST_SHIFT,
+        .mask           = S5PC100_CLKSRC1_UHOST_MASK,
+        .sources        = &clkset_usbhost,
+        .divider_shift  = S5PC100_CLKDIV2_UHOST_SHIFT,
+        .reg_divider    = S5PC100_CLKDIV2,
+        .reg_source     = S5PC100_CLKSRC1,
 };
 /* Clock initialisation code */
 static struct clksrc_clk *init_parents[] = {
        &clk_mout_apll,
-        &clk_mout_epll,
        &clk_mout_mpll,
+        &clk_mout_am,
+        &clk_mout_onenand,
+        &clk_mout_epll,
+        &clk_mout_hpll,
+        &clk_spi0,
+        &clk_spi1,
+        &clk_spi2,
        &clk_uart_uclk1,
+        &clk_audio0,
+        &clk_audio1,
+        &clk_audio2,
+        &clk_spdif,
+        &clk_lcd,
+        &clk_fimc0,
+        &clk_fimc1,
+        &clk_fimc2,
+        &clk_mmc0,
+        &clk_mmc1,
+        &clk_mmc2,
+        &clk_usbhost,
 };
-static void __init_or_cpufreq s5pc1xx_set_clksrc(struct clksrc_clk *clk)
+static void __init_or_cpufreq s5pc100_set_clksrc(struct clksrc_clk *clk)
 {
        struct clk_sources *srcs = clk->sources;
        u32 clksrc = __raw_readl(clk->reg_source);
@@ -1036,9 +1015,9 @@ static void __init_or_cpufreq s5pc1xx_set_clksrc(struct clksrc_clk *clk)
        clk->clk.parent = srcs->sources[clksrc];
-        printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
+        printk(KERN_INFO "%s: source is %s (%d), rate is %ld.%03ld MHz\n",
-               clk->clk.name, clk->clk.parent->name, clksrc,
+                clk->clk.name, clk->clk.parent->name, clksrc,
-               clk_get_rate(&clk->clk));
+                print_mhz(clk_get_rate(&clk->clk)));
 }
 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
@@ -1052,20 +1031,16 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
        unsigned long hclk;
        unsigned long pclkd0;
        unsigned long pclk;
-        unsigned long apll;
+        unsigned long apll, mpll, epll, hpll;
-        unsigned long mpll;
-        unsigned long hpll;
-        unsigned long epll;
        unsigned int ptr;
        u32 clkdiv0, clkdiv1;
        printk(KERN_DEBUG "%s: registering clocks\n", __func__);
-        clkdiv0 = __raw_readl(S5PC1XX_CLK_DIV0);
+        clkdiv0 = __raw_readl(S5PC100_CLKDIV0);
-        clkdiv1 = __raw_readl(S5PC1XX_CLK_DIV1);
+        clkdiv1 = __raw_readl(S5PC100_CLKDIV1);
-        printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
+        printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n", __func__, clkdiv0, clkdiv1);
-                        __func__, clkdiv0, clkdiv1);
        xtal_clk = clk_get(NULL, "xtal");
        BUG_ON(IS_ERR(xtal_clk));
@@ -1075,48 +1050,81 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
        printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
-        apll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_APLL_CON));
+        apll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_APLL_CON));
-        mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_MPLL_CON));
+        mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_MPLL_CON));
-        epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_EPLL_CON));
+        epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_EPLL_CON));
        hpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_HPLL_CON));
-        printk(KERN_INFO "S5PC100: PLL settings, A=%ld, M=%ld, E=%ld, H=%ld\n",
+        printk(KERN_INFO "S5PC100: Apll=%ld.%03ld Mhz, Mpll=%ld.%03ld Mhz"
-               apll, mpll, epll, hpll);
+                ", Epll=%ld.%03ld Mhz, Hpll=%ld.%03ld Mhz\n",
+                print_mhz(apll), print_mhz(mpll),
+                print_mhz(epll), print_mhz(hpll));
-        armclk = apll / GET_DIV(clkdiv0, S5PC1XX_CLKDIV0_APLL);
+        armclk = apll / GET_DIV(clkdiv0, S5PC100_CLKDIV0_APLL);
        armclk = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_ARM);
        hclkd0 = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_D0);
        pclkd0 = hclkd0 / GET_DIV(clkdiv0, S5PC100_CLKDIV0_PCLKD0);
        hclk = mpll / GET_DIV(clkdiv1, S5PC100_CLKDIV1_D1);
        pclk = hclk / GET_DIV(clkdiv1, S5PC100_CLKDIV1_PCLKD1);
-        printk(KERN_INFO "S5PC100: ARMCLK=%ld, HCLKD0=%ld, PCLKD0=%ld, HCLK=%ld, PCLK=%ld\n",
+        printk(KERN_INFO "S5PC100: ARMCLK=%ld.%03ld MHz, HCLKD0=%ld.%03ld MHz,"
-               armclk, hclkd0, pclkd0, hclk, pclk);
+                " PCLKD0=%ld.%03ld MHz\n, HCLK=%ld.%03ld MHz,"
+                " PCLK=%ld.%03ld MHz\n",
+                print_mhz(armclk), print_mhz(hclkd0),
+                print_mhz(pclkd0), print_mhz(hclk), print_mhz(pclk));
        clk_fout_apll.rate = apll;
        clk_fout_mpll.rate = mpll;
        clk_fout_epll.rate = epll;
-        clk_fout_apll.rate = apll;
+        clk_fout_hpll.rate = hpll;
        clk_h.rate = hclk;
        clk_p.rate = pclk;
+        clk_f.rate = armclk;
        for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
-                s5pc1xx_set_clksrc(init_parents[ptr]);
+                s5pc100_set_clksrc(init_parents[ptr]);
 }
 static struct clk *clks[] __initdata = {
        &clk_ext_xtal_mux,
-        &clk_mout_epll.clk,
+        &clk_mout_apll.clk,
-        &clk_fout_epll,
+        &clk_dout_apll,
+        &clk_dout_d0_bus,
+        &clk_dout_pclkd0,
+        &clk_dout_apll2,
        &clk_mout_mpll.clk,
+        &clk_mout_am.clk,
+        &clk_dout_d1_bus,
+        &clk_mout_onenand.clk,
+        &clk_dout_pclkd1,
+        &clk_dout_mpll2,
+        &clk_dout_cam,
        &clk_dout_mpll,
+        &clk_mout_epll.clk,
+        &clk_fout_epll,
+        &clk_iis_cd0,
+        &clk_iis_cd1,
+        &clk_iis_cd2,
+        &clk_pcm_cd0,
+        &clk_pcm_cd1,
+        &clk_spi0.clk,
+        &clk_spi1.clk,
+        &clk_spi2.clk,
        &clk_uart_uclk1.clk,
-        &clk_ext,
+        &clk_audio0.clk,
-        &clk_epll,
+        &clk_audio1.clk,
-        &clk_27m,
+        &clk_audio2.clk,
-        &clk_48m,
+        &clk_spdif.clk,
-        &clk_54m,
+        &clk_lcd.clk,
+        &clk_fimc0.clk,
+        &clk_fimc1.clk,
+        &clk_fimc2.clk,
+        &clk_mmc0.clk,
+        &clk_mmc1.clk,
+        &clk_mmc2.clk,
+        &clk_usbhost.clk,
+        &clk_arm,
 };
 void __init s5pc100_register_clocks(void)
@@ -1133,7 +1141,4 @@ void __init s5pc100_register_clocks(void)
                               clkp->name, ret);
                }
        }
-        clk_mpll.parent = &clk_mout_mpll.clk;
-        clk_epll.parent = &clk_mout_epll.clk;
 }
diff --git a/arch/arm/plat-s5pc1xx/setup-fb-24bpp.c b/arch/arm/plat-s5pc1xx/setup-fb-24bpp.c
new file mode 100644
index 000000000000..1a63768a9a2e
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/setup-fb-24bpp.c
@@ -0,0 +1,49 @@
+/*
+ * linux/arch/arm/plat-s5pc100/setup-fb-24bpp.c
+ *
+ * Copyright 2009 Samsung Electronics
+ *
+ * Base S5PC1XX setup information for 24bpp LCD framebuffer
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/fb.h>
+#include <linux/gpio.h>
+#include <mach/regs-fb.h>
+#include <mach/map.h>
+#include <plat/fb.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-s5pc1xx.h>
+#define DISR_OFFSET     0x7008
+void s5pc100_fb_gpio_setup_24bpp(void)
+{
+        unsigned int gpio = 0;
+        for (gpio = S5PC100_GPF0(0); gpio <= S5PC100_GPF0(7); gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+        for (gpio = S5PC100_GPF1(0); gpio <= S5PC100_GPF1(7); gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+        for (gpio = S5PC100_GPF2(0); gpio <= S5PC100_GPF2(7); gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+        for (gpio = S5PC100_GPF3(0); gpio <= S5PC100_GPF3(3); gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+}
diff --git a/arch/arm/plat-s5pc1xx/setup-i2c0.c b/arch/arm/plat-s5pc1xx/setup-i2c0.c
index 3d00c025fffb..5e4a7c3a231e 100644
--- a/arch/arm/plat-s5pc1xx/setup-i2c0.c
+++ b/arch/arm/plat-s5pc1xx/setup-i2c0.c
@@ -17,9 +17,14 @@
 struct platform_device; /* don't need the contents */
+#include <linux/gpio.h>
 #include <plat/iic.h>
+#include <plat/gpio-cfg.h>
 void s3c_i2c0_cfg_gpio(struct platform_device *dev)
 {
-        /* Pin configuration would be needed */
+        s3c_gpio_cfgpin(S5PC100_GPD(3), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(S5PC100_GPD(3), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgpin(S5PC100_GPD(4), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(S5PC100_GPD(4), S3C_GPIO_PULL_UP);
 }
diff --git a/arch/arm/plat-s5pc1xx/setup-i2c1.c b/arch/arm/plat-s5pc1xx/setup-i2c1.c
index c8f3ca42f51d..a0a8b4ae6ad8 100644
--- a/arch/arm/plat-s5pc1xx/setup-i2c1.c
+++ b/arch/arm/plat-s5pc1xx/setup-i2c1.c
@@ -17,9 +17,14 @@
 struct platform_device; /* don't need the contents */
+#include <linux/gpio.h>
 #include <plat/iic.h>
+#include <plat/gpio-cfg.h>
 void s3c_i2c1_cfg_gpio(struct platform_device *dev)
 {
-        /* Pin configuration would be needed */
+        s3c_gpio_cfgpin(S5PC100_GPD(5), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(S5PC100_GPD(5), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgpin(S5PC100_GPD(6), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(S5PC100_GPD(6), S3C_GPIO_PULL_UP);
 }
diff --git a/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c b/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c
new file mode 100644
index 000000000000..185c8941e644
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c
@@ -0,0 +1,86 @@
+/* linux/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c
+ *
+ * Copyright 2009 Samsung Eletronics
+ *
+ * S5PC1XX - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/card.h>
+#include <plat/gpio-cfg.h>
+#include <plat/regs-sdhci.h>
+void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
+{
+        unsigned int gpio;
+        unsigned int end;
+        unsigned int num;
+        num = width;
+        /* In case of 8 width, we should decrease the 2 */
+        if (width == 8)
+                num = width - 2;
+        end = S5PC100_GPG0(2 + num);
+        /* Set all the necessary GPG0/GPG1 pins to special-function 0 */
+        for (gpio = S5PC100_GPG0(0); gpio < end; gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+        if (width == 8) {
+                for (gpio = S5PC100_GPG1(0); gpio <= S5PC100_GPG1(1); gpio++) {
+                        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+                }
+        }
+        s3c_gpio_setpull(S5PC100_GPG1(2), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgpin(S5PC100_GPG1(2), S3C_GPIO_SFN(2));
+}
+void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
+{
+        unsigned int gpio;
+        unsigned int end;
+        end = S5PC100_GPG2(2 + width);
+        /* Set all the necessary GPG2 pins to special-function 2 */
+        for (gpio = S5PC100_GPG2(0); gpio < end; gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+        s3c_gpio_setpull(S5PC100_GPG2(6), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgpin(S5PC100_GPG2(6), S3C_GPIO_SFN(2));
+}
+void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
+{
+        unsigned int gpio;
+        unsigned int end;
+        end = S5PC100_GPG3(2 + width);
+        /* Set all the necessary GPG3 pins to special-function 2 */
+        for (gpio = S5PC100_GPG3(0); gpio < end; gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+        s3c_gpio_setpull(S5PC100_GPG3(6), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgpin(S5PC100_GPG3(6), S3C_GPIO_SFN(2));
+}
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
new file mode 100644
index 000000000000..486a0d6301e7
--- /dev/null
+++ b/arch/arm/plat-samsung/Kconfig
@@ -0,0 +1,17 @@
+# arch/arm/plat-samsung/Kconfig
+#
+# Copyright 2009 Simtec Electronics
+#
+# Licensed under GPLv2
+config PLAT_SAMSUNG
+        bool
+        depends on ARCH_S3C2410 || ARCH_S3C24A0 || ARCH_S3C64XX || ARCH_S5PC1XX
+        default y
+        help
+          Base platform code for all Samsung SoC based systems
+if PLAT_SAMSUNG
+endif
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
new file mode 100644
index 000000000000..4478b9f7dc34
--- /dev/null
+++ b/arch/arm/plat-samsung/Makefile
@@ -0,0 +1,11 @@
+# arch/arm/plat-s3c64xx/Makefile
+#
+# Copyright 2009 Simtec Electronics
+#
+# Licensed under GPLv2
+obj-y                           :=
+obj-m                           :=
+obj-n                           := dummy.o
+obj-                            :=
diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig
index 35e3bd9858df..d856354f4272 100644
--- a/arch/avr32/Kconfig
+++ b/arch/avr32/Kconfig
@@ -92,6 +92,7 @@ config PLATFORM_AT32AP
        select PERFORMANCE_COUNTERS
        select ARCH_REQUIRE_GPIOLIB
        select GENERIC_ALLOCATOR
+        select HAVE_FB_ATMEL
 #
 # CPU types
author	Linus Torvalds <torvalds@linux-foundation.org>	2009-12-08 11:12:43 -0500
committer	Linus Torvalds <torvalds@linux-foundation.org>	2009-12-08 11:12:43 -0500
commit	79c9601c2e0dbbe69895d302de4d19f3a31fbd30 (patch)
tree	78d4be2df851b2b4106adcfd736622a90cecf9e9 /arch
parent	41440ffe21f29bdb985cab76b2d0b06d83e63b19 (diff)
parent	3d14b5beba35250c548d3851a2b84fce742d8311 (diff)