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authorHolger Schurig <hs4233@mail.mn-solutions.de>2009-04-01 07:58:21 -0400
committerSascha Hauer <s.hauer@pengutronix.de>2009-04-16 06:57:13 -0400
commit1b3c9bf2cd00e1e8a47177b92900dcff363843cb (patch)
tree9430810565a9726e947f38d069f3e243b5838aea /arch
parent289a689b109dfd086c0459fb35b32a1d96bdb8ce (diff)
imx21: activate i2c
Set the correct clkdev-name for the i2c clock. It also get's rid of the ARCH_NR_GPIOS define on the rationale that isn't an ARCH-wide setting anyway. If a device has two pca953x devices, the reserved number will be wrong. Signed-off-by: Holger Schurig <hs4233@mail.mn-solutions.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-mx2/clock_imx21.c2
-rw-r--r--arch/arm/plat-mxc/include/mach/mx21.h3
2 files changed, 1 insertions, 4 deletions
diff --git a/arch/arm/mach-mx2/clock_imx21.c b/arch/arm/mach-mx2/clock_imx21.c
index cbc5dbb9e144..999d013e06e3 100644
--- a/arch/arm/mach-mx2/clock_imx21.c
+++ b/arch/arm/mach-mx2/clock_imx21.c
@@ -931,7 +931,7 @@ static struct clk_lookup lookups[] __initdata = {
931 _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk[0]) 931 _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk[0])
932 _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk) 932 _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk)
933 _REGISTER_CLOCK(NULL, "gpio", gpio_clk) 933 _REGISTER_CLOCK(NULL, "gpio", gpio_clk)
934 _REGISTER_CLOCK(NULL, "i2c", i2c_clk) 934 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
935 _REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk) 935 _REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk)
936 _REGISTER_CLOCK(NULL, "owire", owire_clk) 936 _REGISTER_CLOCK(NULL, "owire", owire_clk)
937 _REGISTER_CLOCK(NULL, "rtc", rtc_clk) 937 _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h
index e8c4cf56c24e..8b070a041a99 100644
--- a/arch/arm/plat-mxc/include/mach/mx21.h
+++ b/arch/arm/plat-mxc/include/mach/mx21.h
@@ -54,9 +54,6 @@
54 54
55#define IRAM_BASE_ADDR 0xFFFFE800 /* internal ram */ 55#define IRAM_BASE_ADDR 0xFFFFE800 /* internal ram */
56 56
57/* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */
58#define ARCH_NR_GPIOS (6*32 + 16)
59
60/* fixed interrupt numbers */ 57/* fixed interrupt numbers */
61#define MXC_INT_USBCTRL 58 58#define MXC_INT_USBCTRL 58
62#define MXC_INT_USBCTRL 58 59#define MXC_INT_USBCTRL 58