diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2008-08-02 05:55:55 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-08-02 16:32:35 -0400 |
commit | 4baa9922430662431231ac637adedddbb0cfb2d7 (patch) | |
tree | e8fb765ce3e41c01f33de34a0bc9494f0ae19818 /arch | |
parent | ff4db0a043a5dee7180bdffd178e61cd02812c68 (diff) |
[ARM] move include/asm-arm to arch/arm/include/asm
Move platform independent header files to arch/arm/include/asm, leaving
those in asm/arch* and asm/plat* alone.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
182 files changed, 16301 insertions, 6 deletions
diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild new file mode 100644 index 000000000000..73237bd130a2 --- /dev/null +++ b/arch/arm/include/asm/Kbuild | |||
@@ -0,0 +1,3 @@ | |||
1 | include include/asm-generic/Kbuild.asm | ||
2 | |||
3 | unifdef-y += hwcap.h | ||
diff --git a/arch/arm/include/asm/a.out-core.h b/arch/arm/include/asm/a.out-core.h new file mode 100644 index 000000000000..93d04acaa31f --- /dev/null +++ b/arch/arm/include/asm/a.out-core.h | |||
@@ -0,0 +1,49 @@ | |||
1 | /* a.out coredump register dumper | ||
2 | * | ||
3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
4 | * Written by David Howells (dhowells@redhat.com) | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or | ||
7 | * modify it under the terms of the GNU General Public Licence | ||
8 | * as published by the Free Software Foundation; either version | ||
9 | * 2 of the Licence, or (at your option) any later version. | ||
10 | */ | ||
11 | |||
12 | #ifndef _ASM_A_OUT_CORE_H | ||
13 | #define _ASM_A_OUT_CORE_H | ||
14 | |||
15 | #ifdef __KERNEL__ | ||
16 | |||
17 | #include <linux/user.h> | ||
18 | #include <linux/elfcore.h> | ||
19 | |||
20 | /* | ||
21 | * fill in the user structure for an a.out core dump | ||
22 | */ | ||
23 | static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump) | ||
24 | { | ||
25 | struct task_struct *tsk = current; | ||
26 | |||
27 | dump->magic = CMAGIC; | ||
28 | dump->start_code = tsk->mm->start_code; | ||
29 | dump->start_stack = regs->ARM_sp & ~(PAGE_SIZE - 1); | ||
30 | |||
31 | dump->u_tsize = (tsk->mm->end_code - tsk->mm->start_code) >> PAGE_SHIFT; | ||
32 | dump->u_dsize = (tsk->mm->brk - tsk->mm->start_data + PAGE_SIZE - 1) >> PAGE_SHIFT; | ||
33 | dump->u_ssize = 0; | ||
34 | |||
35 | dump->u_debugreg[0] = tsk->thread.debug.bp[0].address; | ||
36 | dump->u_debugreg[1] = tsk->thread.debug.bp[1].address; | ||
37 | dump->u_debugreg[2] = tsk->thread.debug.bp[0].insn.arm; | ||
38 | dump->u_debugreg[3] = tsk->thread.debug.bp[1].insn.arm; | ||
39 | dump->u_debugreg[4] = tsk->thread.debug.nsaved; | ||
40 | |||
41 | if (dump->start_stack < 0x04000000) | ||
42 | dump->u_ssize = (0x04000000 - dump->start_stack) >> PAGE_SHIFT; | ||
43 | |||
44 | dump->regs = *regs; | ||
45 | dump->u_fpvalid = dump_fpu (regs, &dump->u_fp); | ||
46 | } | ||
47 | |||
48 | #endif /* __KERNEL__ */ | ||
49 | #endif /* _ASM_A_OUT_CORE_H */ | ||
diff --git a/arch/arm/include/asm/a.out.h b/arch/arm/include/asm/a.out.h new file mode 100644 index 000000000000..79489fdcc8b8 --- /dev/null +++ b/arch/arm/include/asm/a.out.h | |||
@@ -0,0 +1,34 @@ | |||
1 | #ifndef __ARM_A_OUT_H__ | ||
2 | #define __ARM_A_OUT_H__ | ||
3 | |||
4 | #include <linux/personality.h> | ||
5 | #include <asm/types.h> | ||
6 | |||
7 | struct exec | ||
8 | { | ||
9 | __u32 a_info; /* Use macros N_MAGIC, etc for access */ | ||
10 | __u32 a_text; /* length of text, in bytes */ | ||
11 | __u32 a_data; /* length of data, in bytes */ | ||
12 | __u32 a_bss; /* length of uninitialized data area for file, in bytes */ | ||
13 | __u32 a_syms; /* length of symbol table data in file, in bytes */ | ||
14 | __u32 a_entry; /* start address */ | ||
15 | __u32 a_trsize; /* length of relocation info for text, in bytes */ | ||
16 | __u32 a_drsize; /* length of relocation info for data, in bytes */ | ||
17 | }; | ||
18 | |||
19 | /* | ||
20 | * This is always the same | ||
21 | */ | ||
22 | #define N_TXTADDR(a) (0x00008000) | ||
23 | |||
24 | #define N_TRSIZE(a) ((a).a_trsize) | ||
25 | #define N_DRSIZE(a) ((a).a_drsize) | ||
26 | #define N_SYMSIZE(a) ((a).a_syms) | ||
27 | |||
28 | #define M_ARM 103 | ||
29 | |||
30 | #ifndef LIBRARY_START_TEXT | ||
31 | #define LIBRARY_START_TEXT (0x00c00000) | ||
32 | #endif | ||
33 | |||
34 | #endif /* __A_OUT_GNU_H__ */ | ||
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h new file mode 100644 index 000000000000..6116e4893c0a --- /dev/null +++ b/arch/arm/include/asm/assembler.h | |||
@@ -0,0 +1,116 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/assembler.h | ||
3 | * | ||
4 | * Copyright (C) 1996-2000 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * This file contains arm architecture specific defines | ||
11 | * for the different processors. | ||
12 | * | ||
13 | * Do not include any C declarations in this file - it is included by | ||
14 | * assembler source. | ||
15 | */ | ||
16 | #ifndef __ASSEMBLY__ | ||
17 | #error "Only include this from assembly code" | ||
18 | #endif | ||
19 | |||
20 | #include <asm/ptrace.h> | ||
21 | |||
22 | /* | ||
23 | * Endian independent macros for shifting bytes within registers. | ||
24 | */ | ||
25 | #ifndef __ARMEB__ | ||
26 | #define pull lsr | ||
27 | #define push lsl | ||
28 | #define get_byte_0 lsl #0 | ||
29 | #define get_byte_1 lsr #8 | ||
30 | #define get_byte_2 lsr #16 | ||
31 | #define get_byte_3 lsr #24 | ||
32 | #define put_byte_0 lsl #0 | ||
33 | #define put_byte_1 lsl #8 | ||
34 | #define put_byte_2 lsl #16 | ||
35 | #define put_byte_3 lsl #24 | ||
36 | #else | ||
37 | #define pull lsl | ||
38 | #define push lsr | ||
39 | #define get_byte_0 lsr #24 | ||
40 | #define get_byte_1 lsr #16 | ||
41 | #define get_byte_2 lsr #8 | ||
42 | #define get_byte_3 lsl #0 | ||
43 | #define put_byte_0 lsl #24 | ||
44 | #define put_byte_1 lsl #16 | ||
45 | #define put_byte_2 lsl #8 | ||
46 | #define put_byte_3 lsl #0 | ||
47 | #endif | ||
48 | |||
49 | /* | ||
50 | * Data preload for architectures that support it | ||
51 | */ | ||
52 | #if __LINUX_ARM_ARCH__ >= 5 | ||
53 | #define PLD(code...) code | ||
54 | #else | ||
55 | #define PLD(code...) | ||
56 | #endif | ||
57 | |||
58 | /* | ||
59 | * This can be used to enable code to cacheline align the destination | ||
60 | * pointer when bulk writing to memory. Experiments on StrongARM and | ||
61 | * XScale didn't show this a worthwhile thing to do when the cache is not | ||
62 | * set to write-allocate (this would need further testing on XScale when WA | ||
63 | * is used). | ||
64 | * | ||
65 | * On Feroceon there is much to gain however, regardless of cache mode. | ||
66 | */ | ||
67 | #ifdef CONFIG_CPU_FEROCEON | ||
68 | #define CALGN(code...) code | ||
69 | #else | ||
70 | #define CALGN(code...) | ||
71 | #endif | ||
72 | |||
73 | /* | ||
74 | * Enable and disable interrupts | ||
75 | */ | ||
76 | #if __LINUX_ARM_ARCH__ >= 6 | ||
77 | .macro disable_irq | ||
78 | cpsid i | ||
79 | .endm | ||
80 | |||
81 | .macro enable_irq | ||
82 | cpsie i | ||
83 | .endm | ||
84 | #else | ||
85 | .macro disable_irq | ||
86 | msr cpsr_c, #PSR_I_BIT | SVC_MODE | ||
87 | .endm | ||
88 | |||
89 | .macro enable_irq | ||
90 | msr cpsr_c, #SVC_MODE | ||
91 | .endm | ||
92 | #endif | ||
93 | |||
94 | /* | ||
95 | * Save the current IRQ state and disable IRQs. Note that this macro | ||
96 | * assumes FIQs are enabled, and that the processor is in SVC mode. | ||
97 | */ | ||
98 | .macro save_and_disable_irqs, oldcpsr | ||
99 | mrs \oldcpsr, cpsr | ||
100 | disable_irq | ||
101 | .endm | ||
102 | |||
103 | /* | ||
104 | * Restore interrupt state previously stored in a register. We don't | ||
105 | * guarantee that this will preserve the flags. | ||
106 | */ | ||
107 | .macro restore_irqs, oldcpsr | ||
108 | msr cpsr_c, \oldcpsr | ||
109 | .endm | ||
110 | |||
111 | #define USER(x...) \ | ||
112 | 9999: x; \ | ||
113 | .section __ex_table,"a"; \ | ||
114 | .align 3; \ | ||
115 | .long 9999b,9001f; \ | ||
116 | .previous | ||
diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h new file mode 100644 index 000000000000..325f881ccb50 --- /dev/null +++ b/arch/arm/include/asm/atomic.h | |||
@@ -0,0 +1,212 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/atomic.h | ||
3 | * | ||
4 | * Copyright (C) 1996 Russell King. | ||
5 | * Copyright (C) 2002 Deep Blue Solutions Ltd. | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | #ifndef __ASM_ARM_ATOMIC_H | ||
12 | #define __ASM_ARM_ATOMIC_H | ||
13 | |||
14 | #include <linux/compiler.h> | ||
15 | #include <asm/system.h> | ||
16 | |||
17 | typedef struct { volatile int counter; } atomic_t; | ||
18 | |||
19 | #define ATOMIC_INIT(i) { (i) } | ||
20 | |||
21 | #ifdef __KERNEL__ | ||
22 | |||
23 | #define atomic_read(v) ((v)->counter) | ||
24 | |||
25 | #if __LINUX_ARM_ARCH__ >= 6 | ||
26 | |||
27 | /* | ||
28 | * ARMv6 UP and SMP safe atomic ops. We use load exclusive and | ||
29 | * store exclusive to ensure that these are atomic. We may loop | ||
30 | * to ensure that the update happens. Writing to 'v->counter' | ||
31 | * without using the following operations WILL break the atomic | ||
32 | * nature of these ops. | ||
33 | */ | ||
34 | static inline void atomic_set(atomic_t *v, int i) | ||
35 | { | ||
36 | unsigned long tmp; | ||
37 | |||
38 | __asm__ __volatile__("@ atomic_set\n" | ||
39 | "1: ldrex %0, [%1]\n" | ||
40 | " strex %0, %2, [%1]\n" | ||
41 | " teq %0, #0\n" | ||
42 | " bne 1b" | ||
43 | : "=&r" (tmp) | ||
44 | : "r" (&v->counter), "r" (i) | ||
45 | : "cc"); | ||
46 | } | ||
47 | |||
48 | static inline int atomic_add_return(int i, atomic_t *v) | ||
49 | { | ||
50 | unsigned long tmp; | ||
51 | int result; | ||
52 | |||
53 | __asm__ __volatile__("@ atomic_add_return\n" | ||
54 | "1: ldrex %0, [%2]\n" | ||
55 | " add %0, %0, %3\n" | ||
56 | " strex %1, %0, [%2]\n" | ||
57 | " teq %1, #0\n" | ||
58 | " bne 1b" | ||
59 | : "=&r" (result), "=&r" (tmp) | ||
60 | : "r" (&v->counter), "Ir" (i) | ||
61 | : "cc"); | ||
62 | |||
63 | return result; | ||
64 | } | ||
65 | |||
66 | static inline int atomic_sub_return(int i, atomic_t *v) | ||
67 | { | ||
68 | unsigned long tmp; | ||
69 | int result; | ||
70 | |||
71 | __asm__ __volatile__("@ atomic_sub_return\n" | ||
72 | "1: ldrex %0, [%2]\n" | ||
73 | " sub %0, %0, %3\n" | ||
74 | " strex %1, %0, [%2]\n" | ||
75 | " teq %1, #0\n" | ||
76 | " bne 1b" | ||
77 | : "=&r" (result), "=&r" (tmp) | ||
78 | : "r" (&v->counter), "Ir" (i) | ||
79 | : "cc"); | ||
80 | |||
81 | return result; | ||
82 | } | ||
83 | |||
84 | static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new) | ||
85 | { | ||
86 | unsigned long oldval, res; | ||
87 | |||
88 | do { | ||
89 | __asm__ __volatile__("@ atomic_cmpxchg\n" | ||
90 | "ldrex %1, [%2]\n" | ||
91 | "mov %0, #0\n" | ||
92 | "teq %1, %3\n" | ||
93 | "strexeq %0, %4, [%2]\n" | ||
94 | : "=&r" (res), "=&r" (oldval) | ||
95 | : "r" (&ptr->counter), "Ir" (old), "r" (new) | ||
96 | : "cc"); | ||
97 | } while (res); | ||
98 | |||
99 | return oldval; | ||
100 | } | ||
101 | |||
102 | static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr) | ||
103 | { | ||
104 | unsigned long tmp, tmp2; | ||
105 | |||
106 | __asm__ __volatile__("@ atomic_clear_mask\n" | ||
107 | "1: ldrex %0, [%2]\n" | ||
108 | " bic %0, %0, %3\n" | ||
109 | " strex %1, %0, [%2]\n" | ||
110 | " teq %1, #0\n" | ||
111 | " bne 1b" | ||
112 | : "=&r" (tmp), "=&r" (tmp2) | ||
113 | : "r" (addr), "Ir" (mask) | ||
114 | : "cc"); | ||
115 | } | ||
116 | |||
117 | #else /* ARM_ARCH_6 */ | ||
118 | |||
119 | #include <asm/system.h> | ||
120 | |||
121 | #ifdef CONFIG_SMP | ||
122 | #error SMP not supported on pre-ARMv6 CPUs | ||
123 | #endif | ||
124 | |||
125 | #define atomic_set(v,i) (((v)->counter) = (i)) | ||
126 | |||
127 | static inline int atomic_add_return(int i, atomic_t *v) | ||
128 | { | ||
129 | unsigned long flags; | ||
130 | int val; | ||
131 | |||
132 | raw_local_irq_save(flags); | ||
133 | val = v->counter; | ||
134 | v->counter = val += i; | ||
135 | raw_local_irq_restore(flags); | ||
136 | |||
137 | return val; | ||
138 | } | ||
139 | |||
140 | static inline int atomic_sub_return(int i, atomic_t *v) | ||
141 | { | ||
142 | unsigned long flags; | ||
143 | int val; | ||
144 | |||
145 | raw_local_irq_save(flags); | ||
146 | val = v->counter; | ||
147 | v->counter = val -= i; | ||
148 | raw_local_irq_restore(flags); | ||
149 | |||
150 | return val; | ||
151 | } | ||
152 | |||
153 | static inline int atomic_cmpxchg(atomic_t *v, int old, int new) | ||
154 | { | ||
155 | int ret; | ||
156 | unsigned long flags; | ||
157 | |||
158 | raw_local_irq_save(flags); | ||
159 | ret = v->counter; | ||
160 | if (likely(ret == old)) | ||
161 | v->counter = new; | ||
162 | raw_local_irq_restore(flags); | ||
163 | |||
164 | return ret; | ||
165 | } | ||
166 | |||
167 | static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr) | ||
168 | { | ||
169 | unsigned long flags; | ||
170 | |||
171 | raw_local_irq_save(flags); | ||
172 | *addr &= ~mask; | ||
173 | raw_local_irq_restore(flags); | ||
174 | } | ||
175 | |||
176 | #endif /* __LINUX_ARM_ARCH__ */ | ||
177 | |||
178 | #define atomic_xchg(v, new) (xchg(&((v)->counter), new)) | ||
179 | |||
180 | static inline int atomic_add_unless(atomic_t *v, int a, int u) | ||
181 | { | ||
182 | int c, old; | ||
183 | |||
184 | c = atomic_read(v); | ||
185 | while (c != u && (old = atomic_cmpxchg((v), c, c + a)) != c) | ||
186 | c = old; | ||
187 | return c != u; | ||
188 | } | ||
189 | #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) | ||
190 | |||
191 | #define atomic_add(i, v) (void) atomic_add_return(i, v) | ||
192 | #define atomic_inc(v) (void) atomic_add_return(1, v) | ||
193 | #define atomic_sub(i, v) (void) atomic_sub_return(i, v) | ||
194 | #define atomic_dec(v) (void) atomic_sub_return(1, v) | ||
195 | |||
196 | #define atomic_inc_and_test(v) (atomic_add_return(1, v) == 0) | ||
197 | #define atomic_dec_and_test(v) (atomic_sub_return(1, v) == 0) | ||
198 | #define atomic_inc_return(v) (atomic_add_return(1, v)) | ||
199 | #define atomic_dec_return(v) (atomic_sub_return(1, v)) | ||
200 | #define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0) | ||
201 | |||
202 | #define atomic_add_negative(i,v) (atomic_add_return(i, v) < 0) | ||
203 | |||
204 | /* Atomic operations are already serializing on ARM */ | ||
205 | #define smp_mb__before_atomic_dec() barrier() | ||
206 | #define smp_mb__after_atomic_dec() barrier() | ||
207 | #define smp_mb__before_atomic_inc() barrier() | ||
208 | #define smp_mb__after_atomic_inc() barrier() | ||
209 | |||
210 | #include <asm-generic/atomic.h> | ||
211 | #endif | ||
212 | #endif | ||
diff --git a/arch/arm/include/asm/auxvec.h b/arch/arm/include/asm/auxvec.h new file mode 100644 index 000000000000..c0536f6b29a7 --- /dev/null +++ b/arch/arm/include/asm/auxvec.h | |||
@@ -0,0 +1,4 @@ | |||
1 | #ifndef __ASMARM_AUXVEC_H | ||
2 | #define __ASMARM_AUXVEC_H | ||
3 | |||
4 | #endif | ||
diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h new file mode 100644 index 000000000000..9a1db20e032a --- /dev/null +++ b/arch/arm/include/asm/bitops.h | |||
@@ -0,0 +1,340 @@ | |||
1 | /* | ||
2 | * Copyright 1995, Russell King. | ||
3 | * Various bits and pieces copyrights include: | ||
4 | * Linus Torvalds (test_bit). | ||
5 | * Big endian support: Copyright 2001, Nicolas Pitre | ||
6 | * reworked by rmk. | ||
7 | * | ||
8 | * bit 0 is the LSB of an "unsigned long" quantity. | ||
9 | * | ||
10 | * Please note that the code in this file should never be included | ||
11 | * from user space. Many of these are not implemented in assembler | ||
12 | * since they would be too costly. Also, they require privileged | ||
13 | * instructions (which are not available from user mode) to ensure | ||
14 | * that they are atomic. | ||
15 | */ | ||
16 | |||
17 | #ifndef __ASM_ARM_BITOPS_H | ||
18 | #define __ASM_ARM_BITOPS_H | ||
19 | |||
20 | #ifdef __KERNEL__ | ||
21 | |||
22 | #ifndef _LINUX_BITOPS_H | ||
23 | #error only <linux/bitops.h> can be included directly | ||
24 | #endif | ||
25 | |||
26 | #include <linux/compiler.h> | ||
27 | #include <asm/system.h> | ||
28 | |||
29 | #define smp_mb__before_clear_bit() mb() | ||
30 | #define smp_mb__after_clear_bit() mb() | ||
31 | |||
32 | /* | ||
33 | * These functions are the basis of our bit ops. | ||
34 | * | ||
35 | * First, the atomic bitops. These use native endian. | ||
36 | */ | ||
37 | static inline void ____atomic_set_bit(unsigned int bit, volatile unsigned long *p) | ||
38 | { | ||
39 | unsigned long flags; | ||
40 | unsigned long mask = 1UL << (bit & 31); | ||
41 | |||
42 | p += bit >> 5; | ||
43 | |||
44 | raw_local_irq_save(flags); | ||
45 | *p |= mask; | ||
46 | raw_local_irq_restore(flags); | ||
47 | } | ||
48 | |||
49 | static inline void ____atomic_clear_bit(unsigned int bit, volatile unsigned long *p) | ||
50 | { | ||
51 | unsigned long flags; | ||
52 | unsigned long mask = 1UL << (bit & 31); | ||
53 | |||
54 | p += bit >> 5; | ||
55 | |||
56 | raw_local_irq_save(flags); | ||
57 | *p &= ~mask; | ||
58 | raw_local_irq_restore(flags); | ||
59 | } | ||
60 | |||
61 | static inline void ____atomic_change_bit(unsigned int bit, volatile unsigned long *p) | ||
62 | { | ||
63 | unsigned long flags; | ||
64 | unsigned long mask = 1UL << (bit & 31); | ||
65 | |||
66 | p += bit >> 5; | ||
67 | |||
68 | raw_local_irq_save(flags); | ||
69 | *p ^= mask; | ||
70 | raw_local_irq_restore(flags); | ||
71 | } | ||
72 | |||
73 | static inline int | ||
74 | ____atomic_test_and_set_bit(unsigned int bit, volatile unsigned long *p) | ||
75 | { | ||
76 | unsigned long flags; | ||
77 | unsigned int res; | ||
78 | unsigned long mask = 1UL << (bit & 31); | ||
79 | |||
80 | p += bit >> 5; | ||
81 | |||
82 | raw_local_irq_save(flags); | ||
83 | res = *p; | ||
84 | *p = res | mask; | ||
85 | raw_local_irq_restore(flags); | ||
86 | |||
87 | return res & mask; | ||
88 | } | ||
89 | |||
90 | static inline int | ||
91 | ____atomic_test_and_clear_bit(unsigned int bit, volatile unsigned long *p) | ||
92 | { | ||
93 | unsigned long flags; | ||
94 | unsigned int res; | ||
95 | unsigned long mask = 1UL << (bit & 31); | ||
96 | |||
97 | p += bit >> 5; | ||
98 | |||
99 | raw_local_irq_save(flags); | ||
100 | res = *p; | ||
101 | *p = res & ~mask; | ||
102 | raw_local_irq_restore(flags); | ||
103 | |||
104 | return res & mask; | ||
105 | } | ||
106 | |||
107 | static inline int | ||
108 | ____atomic_test_and_change_bit(unsigned int bit, volatile unsigned long *p) | ||
109 | { | ||
110 | unsigned long flags; | ||
111 | unsigned int res; | ||
112 | unsigned long mask = 1UL << (bit & 31); | ||
113 | |||
114 | p += bit >> 5; | ||
115 | |||
116 | raw_local_irq_save(flags); | ||
117 | res = *p; | ||
118 | *p = res ^ mask; | ||
119 | raw_local_irq_restore(flags); | ||
120 | |||
121 | return res & mask; | ||
122 | } | ||
123 | |||
124 | #include <asm-generic/bitops/non-atomic.h> | ||
125 | |||
126 | /* | ||
127 | * A note about Endian-ness. | ||
128 | * ------------------------- | ||
129 | * | ||
130 | * When the ARM is put into big endian mode via CR15, the processor | ||
131 | * merely swaps the order of bytes within words, thus: | ||
132 | * | ||
133 | * ------------ physical data bus bits ----------- | ||
134 | * D31 ... D24 D23 ... D16 D15 ... D8 D7 ... D0 | ||
135 | * little byte 3 byte 2 byte 1 byte 0 | ||
136 | * big byte 0 byte 1 byte 2 byte 3 | ||
137 | * | ||
138 | * This means that reading a 32-bit word at address 0 returns the same | ||
139 | * value irrespective of the endian mode bit. | ||
140 | * | ||
141 | * Peripheral devices should be connected with the data bus reversed in | ||
142 | * "Big Endian" mode. ARM Application Note 61 is applicable, and is | ||
143 | * available from http://www.arm.com/. | ||
144 | * | ||
145 | * The following assumes that the data bus connectivity for big endian | ||
146 | * mode has been followed. | ||
147 | * | ||
148 | * Note that bit 0 is defined to be 32-bit word bit 0, not byte 0 bit 0. | ||
149 | */ | ||
150 | |||
151 | /* | ||
152 | * Little endian assembly bitops. nr = 0 -> byte 0 bit 0. | ||
153 | */ | ||
154 | extern void _set_bit_le(int nr, volatile unsigned long * p); | ||
155 | extern void _clear_bit_le(int nr, volatile unsigned long * p); | ||
156 | extern void _change_bit_le(int nr, volatile unsigned long * p); | ||
157 | extern int _test_and_set_bit_le(int nr, volatile unsigned long * p); | ||
158 | extern int _test_and_clear_bit_le(int nr, volatile unsigned long * p); | ||
159 | extern int _test_and_change_bit_le(int nr, volatile unsigned long * p); | ||
160 | extern int _find_first_zero_bit_le(const void * p, unsigned size); | ||
161 | extern int _find_next_zero_bit_le(const void * p, int size, int offset); | ||
162 | extern int _find_first_bit_le(const unsigned long *p, unsigned size); | ||
163 | extern int _find_next_bit_le(const unsigned long *p, int size, int offset); | ||
164 | |||
165 | /* | ||
166 | * Big endian assembly bitops. nr = 0 -> byte 3 bit 0. | ||
167 | */ | ||
168 | extern void _set_bit_be(int nr, volatile unsigned long * p); | ||
169 | extern void _clear_bit_be(int nr, volatile unsigned long * p); | ||
170 | extern void _change_bit_be(int nr, volatile unsigned long * p); | ||
171 | extern int _test_and_set_bit_be(int nr, volatile unsigned long * p); | ||
172 | extern int _test_and_clear_bit_be(int nr, volatile unsigned long * p); | ||
173 | extern int _test_and_change_bit_be(int nr, volatile unsigned long * p); | ||
174 | extern int _find_first_zero_bit_be(const void * p, unsigned size); | ||
175 | extern int _find_next_zero_bit_be(const void * p, int size, int offset); | ||
176 | extern int _find_first_bit_be(const unsigned long *p, unsigned size); | ||
177 | extern int _find_next_bit_be(const unsigned long *p, int size, int offset); | ||
178 | |||
179 | #ifndef CONFIG_SMP | ||
180 | /* | ||
181 | * The __* form of bitops are non-atomic and may be reordered. | ||
182 | */ | ||
183 | #define ATOMIC_BITOP_LE(name,nr,p) \ | ||
184 | (__builtin_constant_p(nr) ? \ | ||
185 | ____atomic_##name(nr, p) : \ | ||
186 | _##name##_le(nr,p)) | ||
187 | |||
188 | #define ATOMIC_BITOP_BE(name,nr,p) \ | ||
189 | (__builtin_constant_p(nr) ? \ | ||
190 | ____atomic_##name(nr, p) : \ | ||
191 | _##name##_be(nr,p)) | ||
192 | #else | ||
193 | #define ATOMIC_BITOP_LE(name,nr,p) _##name##_le(nr,p) | ||
194 | #define ATOMIC_BITOP_BE(name,nr,p) _##name##_be(nr,p) | ||
195 | #endif | ||
196 | |||
197 | #define NONATOMIC_BITOP(name,nr,p) \ | ||
198 | (____nonatomic_##name(nr, p)) | ||
199 | |||
200 | #ifndef __ARMEB__ | ||
201 | /* | ||
202 | * These are the little endian, atomic definitions. | ||
203 | */ | ||
204 | #define set_bit(nr,p) ATOMIC_BITOP_LE(set_bit,nr,p) | ||
205 | #define clear_bit(nr,p) ATOMIC_BITOP_LE(clear_bit,nr,p) | ||
206 | #define change_bit(nr,p) ATOMIC_BITOP_LE(change_bit,nr,p) | ||
207 | #define test_and_set_bit(nr,p) ATOMIC_BITOP_LE(test_and_set_bit,nr,p) | ||
208 | #define test_and_clear_bit(nr,p) ATOMIC_BITOP_LE(test_and_clear_bit,nr,p) | ||
209 | #define test_and_change_bit(nr,p) ATOMIC_BITOP_LE(test_and_change_bit,nr,p) | ||
210 | #define find_first_zero_bit(p,sz) _find_first_zero_bit_le(p,sz) | ||
211 | #define find_next_zero_bit(p,sz,off) _find_next_zero_bit_le(p,sz,off) | ||
212 | #define find_first_bit(p,sz) _find_first_bit_le(p,sz) | ||
213 | #define find_next_bit(p,sz,off) _find_next_bit_le(p,sz,off) | ||
214 | |||
215 | #define WORD_BITOFF_TO_LE(x) ((x)) | ||
216 | |||
217 | #else | ||
218 | |||
219 | /* | ||
220 | * These are the big endian, atomic definitions. | ||
221 | */ | ||
222 | #define set_bit(nr,p) ATOMIC_BITOP_BE(set_bit,nr,p) | ||
223 | #define clear_bit(nr,p) ATOMIC_BITOP_BE(clear_bit,nr,p) | ||
224 | #define change_bit(nr,p) ATOMIC_BITOP_BE(change_bit,nr,p) | ||
225 | #define test_and_set_bit(nr,p) ATOMIC_BITOP_BE(test_and_set_bit,nr,p) | ||
226 | #define test_and_clear_bit(nr,p) ATOMIC_BITOP_BE(test_and_clear_bit,nr,p) | ||
227 | #define test_and_change_bit(nr,p) ATOMIC_BITOP_BE(test_and_change_bit,nr,p) | ||
228 | #define find_first_zero_bit(p,sz) _find_first_zero_bit_be(p,sz) | ||
229 | #define find_next_zero_bit(p,sz,off) _find_next_zero_bit_be(p,sz,off) | ||
230 | #define find_first_bit(p,sz) _find_first_bit_be(p,sz) | ||
231 | #define find_next_bit(p,sz,off) _find_next_bit_be(p,sz,off) | ||
232 | |||
233 | #define WORD_BITOFF_TO_LE(x) ((x) ^ 0x18) | ||
234 | |||
235 | #endif | ||
236 | |||
237 | #if __LINUX_ARM_ARCH__ < 5 | ||
238 | |||
239 | #include <asm-generic/bitops/ffz.h> | ||
240 | #include <asm-generic/bitops/__ffs.h> | ||
241 | #include <asm-generic/bitops/fls.h> | ||
242 | #include <asm-generic/bitops/ffs.h> | ||
243 | |||
244 | #else | ||
245 | |||
246 | static inline int constant_fls(int x) | ||
247 | { | ||
248 | int r = 32; | ||
249 | |||
250 | if (!x) | ||
251 | return 0; | ||
252 | if (!(x & 0xffff0000u)) { | ||
253 | x <<= 16; | ||
254 | r -= 16; | ||
255 | } | ||
256 | if (!(x & 0xff000000u)) { | ||
257 | x <<= 8; | ||
258 | r -= 8; | ||
259 | } | ||
260 | if (!(x & 0xf0000000u)) { | ||
261 | x <<= 4; | ||
262 | r -= 4; | ||
263 | } | ||
264 | if (!(x & 0xc0000000u)) { | ||
265 | x <<= 2; | ||
266 | r -= 2; | ||
267 | } | ||
268 | if (!(x & 0x80000000u)) { | ||
269 | x <<= 1; | ||
270 | r -= 1; | ||
271 | } | ||
272 | return r; | ||
273 | } | ||
274 | |||
275 | /* | ||
276 | * On ARMv5 and above those functions can be implemented around | ||
277 | * the clz instruction for much better code efficiency. | ||
278 | */ | ||
279 | |||
280 | #define __fls(x) \ | ||
281 | ( __builtin_constant_p(x) ? constant_fls(x) : \ | ||
282 | ({ int __r; asm("clz\t%0, %1" : "=r"(__r) : "r"(x) : "cc"); 32-__r; }) ) | ||
283 | |||
284 | /* Implement fls() in C so that 64-bit args are suitably truncated */ | ||
285 | static inline int fls(int x) | ||
286 | { | ||
287 | return __fls(x); | ||
288 | } | ||
289 | |||
290 | #define ffs(x) ({ unsigned long __t = (x); fls(__t & -__t); }) | ||
291 | #define __ffs(x) (ffs(x) - 1) | ||
292 | #define ffz(x) __ffs( ~(x) ) | ||
293 | |||
294 | #endif | ||
295 | |||
296 | #include <asm-generic/bitops/fls64.h> | ||
297 | |||
298 | #include <asm-generic/bitops/sched.h> | ||
299 | #include <asm-generic/bitops/hweight.h> | ||
300 | #include <asm-generic/bitops/lock.h> | ||
301 | |||
302 | /* | ||
303 | * Ext2 is defined to use little-endian byte ordering. | ||
304 | * These do not need to be atomic. | ||
305 | */ | ||
306 | #define ext2_set_bit(nr,p) \ | ||
307 | __test_and_set_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) | ||
308 | #define ext2_set_bit_atomic(lock,nr,p) \ | ||
309 | test_and_set_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) | ||
310 | #define ext2_clear_bit(nr,p) \ | ||
311 | __test_and_clear_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) | ||
312 | #define ext2_clear_bit_atomic(lock,nr,p) \ | ||
313 | test_and_clear_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) | ||
314 | #define ext2_test_bit(nr,p) \ | ||
315 | test_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) | ||
316 | #define ext2_find_first_zero_bit(p,sz) \ | ||
317 | _find_first_zero_bit_le(p,sz) | ||
318 | #define ext2_find_next_zero_bit(p,sz,off) \ | ||
319 | _find_next_zero_bit_le(p,sz,off) | ||
320 | #define ext2_find_next_bit(p, sz, off) \ | ||
321 | _find_next_bit_le(p, sz, off) | ||
322 | |||
323 | /* | ||
324 | * Minix is defined to use little-endian byte ordering. | ||
325 | * These do not need to be atomic. | ||
326 | */ | ||
327 | #define minix_set_bit(nr,p) \ | ||
328 | __set_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) | ||
329 | #define minix_test_bit(nr,p) \ | ||
330 | test_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) | ||
331 | #define minix_test_and_set_bit(nr,p) \ | ||
332 | __test_and_set_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) | ||
333 | #define minix_test_and_clear_bit(nr,p) \ | ||
334 | __test_and_clear_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) | ||
335 | #define minix_find_first_zero_bit(p,sz) \ | ||
336 | _find_first_zero_bit_le(p,sz) | ||
337 | |||
338 | #endif /* __KERNEL__ */ | ||
339 | |||
340 | #endif /* _ARM_BITOPS_H */ | ||
diff --git a/arch/arm/include/asm/bug.h b/arch/arm/include/asm/bug.h new file mode 100644 index 000000000000..7b62351f097d --- /dev/null +++ b/arch/arm/include/asm/bug.h | |||
@@ -0,0 +1,24 @@ | |||
1 | #ifndef _ASMARM_BUG_H | ||
2 | #define _ASMARM_BUG_H | ||
3 | |||
4 | |||
5 | #ifdef CONFIG_BUG | ||
6 | #ifdef CONFIG_DEBUG_BUGVERBOSE | ||
7 | extern void __bug(const char *file, int line) __attribute__((noreturn)); | ||
8 | |||
9 | /* give file/line information */ | ||
10 | #define BUG() __bug(__FILE__, __LINE__) | ||
11 | |||
12 | #else | ||
13 | |||
14 | /* this just causes an oops */ | ||
15 | #define BUG() (*(int *)0 = 0) | ||
16 | |||
17 | #endif | ||
18 | |||
19 | #define HAVE_ARCH_BUG | ||
20 | #endif | ||
21 | |||
22 | #include <asm-generic/bug.h> | ||
23 | |||
24 | #endif | ||
diff --git a/arch/arm/include/asm/bugs.h b/arch/arm/include/asm/bugs.h new file mode 100644 index 000000000000..a97f1ea708d1 --- /dev/null +++ b/arch/arm/include/asm/bugs.h | |||
@@ -0,0 +1,21 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/bugs.h | ||
3 | * | ||
4 | * Copyright (C) 1995-2003 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #ifndef __ASM_BUGS_H | ||
11 | #define __ASM_BUGS_H | ||
12 | |||
13 | #ifdef CONFIG_MMU | ||
14 | extern void check_writebuffer_bugs(void); | ||
15 | |||
16 | #define check_bugs() check_writebuffer_bugs() | ||
17 | #else | ||
18 | #define check_bugs() do { } while (0) | ||
19 | #endif | ||
20 | |||
21 | #endif | ||
diff --git a/arch/arm/include/asm/byteorder.h b/arch/arm/include/asm/byteorder.h new file mode 100644 index 000000000000..4fbfb22f65a0 --- /dev/null +++ b/arch/arm/include/asm/byteorder.h | |||
@@ -0,0 +1,58 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/byteorder.h | ||
3 | * | ||
4 | * ARM Endian-ness. In little endian mode, the data bus is connected such | ||
5 | * that byte accesses appear as: | ||
6 | * 0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31 | ||
7 | * and word accesses (data or instruction) appear as: | ||
8 | * d0...d31 | ||
9 | * | ||
10 | * When in big endian mode, byte accesses appear as: | ||
11 | * 0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7 | ||
12 | * and word accesses (data or instruction) appear as: | ||
13 | * d0...d31 | ||
14 | */ | ||
15 | #ifndef __ASM_ARM_BYTEORDER_H | ||
16 | #define __ASM_ARM_BYTEORDER_H | ||
17 | |||
18 | #include <linux/compiler.h> | ||
19 | #include <asm/types.h> | ||
20 | |||
21 | static inline __attribute_const__ __u32 ___arch__swab32(__u32 x) | ||
22 | { | ||
23 | __u32 t; | ||
24 | |||
25 | #ifndef __thumb__ | ||
26 | if (!__builtin_constant_p(x)) { | ||
27 | /* | ||
28 | * The compiler needs a bit of a hint here to always do the | ||
29 | * right thing and not screw it up to different degrees | ||
30 | * depending on the gcc version. | ||
31 | */ | ||
32 | asm ("eor\t%0, %1, %1, ror #16" : "=r" (t) : "r" (x)); | ||
33 | } else | ||
34 | #endif | ||
35 | t = x ^ ((x << 16) | (x >> 16)); /* eor r1,r0,r0,ror #16 */ | ||
36 | |||
37 | x = (x << 24) | (x >> 8); /* mov r0,r0,ror #8 */ | ||
38 | t &= ~0x00FF0000; /* bic r1,r1,#0x00FF0000 */ | ||
39 | x ^= (t >> 8); /* eor r0,r0,r1,lsr #8 */ | ||
40 | |||
41 | return x; | ||
42 | } | ||
43 | |||
44 | #define __arch__swab32(x) ___arch__swab32(x) | ||
45 | |||
46 | #if !defined(__STRICT_ANSI__) || defined(__KERNEL__) | ||
47 | # define __BYTEORDER_HAS_U64__ | ||
48 | # define __SWAB_64_THRU_32__ | ||
49 | #endif | ||
50 | |||
51 | #ifdef __ARMEB__ | ||
52 | #include <linux/byteorder/big_endian.h> | ||
53 | #else | ||
54 | #include <linux/byteorder/little_endian.h> | ||
55 | #endif | ||
56 | |||
57 | #endif | ||
58 | |||
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h new file mode 100644 index 000000000000..cb7a9e97fd7e --- /dev/null +++ b/arch/arm/include/asm/cache.h | |||
@@ -0,0 +1,10 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/cache.h | ||
3 | */ | ||
4 | #ifndef __ASMARM_CACHE_H | ||
5 | #define __ASMARM_CACHE_H | ||
6 | |||
7 | #define L1_CACHE_SHIFT 5 | ||
8 | #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) | ||
9 | |||
10 | #endif | ||
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h new file mode 100644 index 000000000000..9073d9c6567e --- /dev/null +++ b/arch/arm/include/asm/cacheflush.h | |||
@@ -0,0 +1,537 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/cacheflush.h | ||
3 | * | ||
4 | * Copyright (C) 1999-2002 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #ifndef _ASMARM_CACHEFLUSH_H | ||
11 | #define _ASMARM_CACHEFLUSH_H | ||
12 | |||
13 | #include <linux/sched.h> | ||
14 | #include <linux/mm.h> | ||
15 | |||
16 | #include <asm/glue.h> | ||
17 | #include <asm/shmparam.h> | ||
18 | |||
19 | #define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT) | ||
20 | |||
21 | /* | ||
22 | * Cache Model | ||
23 | * =========== | ||
24 | */ | ||
25 | #undef _CACHE | ||
26 | #undef MULTI_CACHE | ||
27 | |||
28 | #if defined(CONFIG_CPU_CACHE_V3) | ||
29 | # ifdef _CACHE | ||
30 | # define MULTI_CACHE 1 | ||
31 | # else | ||
32 | # define _CACHE v3 | ||
33 | # endif | ||
34 | #endif | ||
35 | |||
36 | #if defined(CONFIG_CPU_CACHE_V4) | ||
37 | # ifdef _CACHE | ||
38 | # define MULTI_CACHE 1 | ||
39 | # else | ||
40 | # define _CACHE v4 | ||
41 | # endif | ||
42 | #endif | ||
43 | |||
44 | #if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \ | ||
45 | defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020) | ||
46 | # define MULTI_CACHE 1 | ||
47 | #endif | ||
48 | |||
49 | #if defined(CONFIG_CPU_ARM926T) | ||
50 | # ifdef _CACHE | ||
51 | # define MULTI_CACHE 1 | ||
52 | # else | ||
53 | # define _CACHE arm926 | ||
54 | # endif | ||
55 | #endif | ||
56 | |||
57 | #if defined(CONFIG_CPU_ARM940T) | ||
58 | # ifdef _CACHE | ||
59 | # define MULTI_CACHE 1 | ||
60 | # else | ||
61 | # define _CACHE arm940 | ||
62 | # endif | ||
63 | #endif | ||
64 | |||
65 | #if defined(CONFIG_CPU_ARM946E) | ||
66 | # ifdef _CACHE | ||
67 | # define MULTI_CACHE 1 | ||
68 | # else | ||
69 | # define _CACHE arm946 | ||
70 | # endif | ||
71 | #endif | ||
72 | |||
73 | #if defined(CONFIG_CPU_CACHE_V4WB) | ||
74 | # ifdef _CACHE | ||
75 | # define MULTI_CACHE 1 | ||
76 | # else | ||
77 | # define _CACHE v4wb | ||
78 | # endif | ||
79 | #endif | ||
80 | |||
81 | #if defined(CONFIG_CPU_XSCALE) | ||
82 | # ifdef _CACHE | ||
83 | # define MULTI_CACHE 1 | ||
84 | # else | ||
85 | # define _CACHE xscale | ||
86 | # endif | ||
87 | #endif | ||
88 | |||
89 | #if defined(CONFIG_CPU_XSC3) | ||
90 | # ifdef _CACHE | ||
91 | # define MULTI_CACHE 1 | ||
92 | # else | ||
93 | # define _CACHE xsc3 | ||
94 | # endif | ||
95 | #endif | ||
96 | |||
97 | #if defined(CONFIG_CPU_FEROCEON) | ||
98 | # define MULTI_CACHE 1 | ||
99 | #endif | ||
100 | |||
101 | #if defined(CONFIG_CPU_V6) | ||
102 | //# ifdef _CACHE | ||
103 | # define MULTI_CACHE 1 | ||
104 | //# else | ||
105 | //# define _CACHE v6 | ||
106 | //# endif | ||
107 | #endif | ||
108 | |||
109 | #if defined(CONFIG_CPU_V7) | ||
110 | //# ifdef _CACHE | ||
111 | # define MULTI_CACHE 1 | ||
112 | //# else | ||
113 | //# define _CACHE v7 | ||
114 | //# endif | ||
115 | #endif | ||
116 | |||
117 | #if !defined(_CACHE) && !defined(MULTI_CACHE) | ||
118 | #error Unknown cache maintainence model | ||
119 | #endif | ||
120 | |||
121 | /* | ||
122 | * This flag is used to indicate that the page pointed to by a pte | ||
123 | * is dirty and requires cleaning before returning it to the user. | ||
124 | */ | ||
125 | #define PG_dcache_dirty PG_arch_1 | ||
126 | |||
127 | /* | ||
128 | * MM Cache Management | ||
129 | * =================== | ||
130 | * | ||
131 | * The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files | ||
132 | * implement these methods. | ||
133 | * | ||
134 | * Start addresses are inclusive and end addresses are exclusive; | ||
135 | * start addresses should be rounded down, end addresses up. | ||
136 | * | ||
137 | * See Documentation/cachetlb.txt for more information. | ||
138 | * Please note that the implementation of these, and the required | ||
139 | * effects are cache-type (VIVT/VIPT/PIPT) specific. | ||
140 | * | ||
141 | * flush_cache_kern_all() | ||
142 | * | ||
143 | * Unconditionally clean and invalidate the entire cache. | ||
144 | * | ||
145 | * flush_cache_user_mm(mm) | ||
146 | * | ||
147 | * Clean and invalidate all user space cache entries | ||
148 | * before a change of page tables. | ||
149 | * | ||
150 | * flush_cache_user_range(start, end, flags) | ||
151 | * | ||
152 | * Clean and invalidate a range of cache entries in the | ||
153 | * specified address space before a change of page tables. | ||
154 | * - start - user start address (inclusive, page aligned) | ||
155 | * - end - user end address (exclusive, page aligned) | ||
156 | * - flags - vma->vm_flags field | ||
157 | * | ||
158 | * coherent_kern_range(start, end) | ||
159 | * | ||
160 | * Ensure coherency between the Icache and the Dcache in the | ||
161 | * region described by start, end. If you have non-snooping | ||
162 | * Harvard caches, you need to implement this function. | ||
163 | * - start - virtual start address | ||
164 | * - end - virtual end address | ||
165 | * | ||
166 | * DMA Cache Coherency | ||
167 | * =================== | ||
168 | * | ||
169 | * dma_inv_range(start, end) | ||
170 | * | ||
171 | * Invalidate (discard) the specified virtual address range. | ||
172 | * May not write back any entries. If 'start' or 'end' | ||
173 | * are not cache line aligned, those lines must be written | ||
174 | * back. | ||
175 | * - start - virtual start address | ||
176 | * - end - virtual end address | ||
177 | * | ||
178 | * dma_clean_range(start, end) | ||
179 | * | ||
180 | * Clean (write back) the specified virtual address range. | ||
181 | * - start - virtual start address | ||
182 | * - end - virtual end address | ||
183 | * | ||
184 | * dma_flush_range(start, end) | ||
185 | * | ||
186 | * Clean and invalidate the specified virtual address range. | ||
187 | * - start - virtual start address | ||
188 | * - end - virtual end address | ||
189 | */ | ||
190 | |||
191 | struct cpu_cache_fns { | ||
192 | void (*flush_kern_all)(void); | ||
193 | void (*flush_user_all)(void); | ||
194 | void (*flush_user_range)(unsigned long, unsigned long, unsigned int); | ||
195 | |||
196 | void (*coherent_kern_range)(unsigned long, unsigned long); | ||
197 | void (*coherent_user_range)(unsigned long, unsigned long); | ||
198 | void (*flush_kern_dcache_page)(void *); | ||
199 | |||
200 | void (*dma_inv_range)(const void *, const void *); | ||
201 | void (*dma_clean_range)(const void *, const void *); | ||
202 | void (*dma_flush_range)(const void *, const void *); | ||
203 | }; | ||
204 | |||
205 | struct outer_cache_fns { | ||
206 | void (*inv_range)(unsigned long, unsigned long); | ||
207 | void (*clean_range)(unsigned long, unsigned long); | ||
208 | void (*flush_range)(unsigned long, unsigned long); | ||
209 | }; | ||
210 | |||
211 | /* | ||
212 | * Select the calling method | ||
213 | */ | ||
214 | #ifdef MULTI_CACHE | ||
215 | |||
216 | extern struct cpu_cache_fns cpu_cache; | ||
217 | |||
218 | #define __cpuc_flush_kern_all cpu_cache.flush_kern_all | ||
219 | #define __cpuc_flush_user_all cpu_cache.flush_user_all | ||
220 | #define __cpuc_flush_user_range cpu_cache.flush_user_range | ||
221 | #define __cpuc_coherent_kern_range cpu_cache.coherent_kern_range | ||
222 | #define __cpuc_coherent_user_range cpu_cache.coherent_user_range | ||
223 | #define __cpuc_flush_dcache_page cpu_cache.flush_kern_dcache_page | ||
224 | |||
225 | /* | ||
226 | * These are private to the dma-mapping API. Do not use directly. | ||
227 | * Their sole purpose is to ensure that data held in the cache | ||
228 | * is visible to DMA, or data written by DMA to system memory is | ||
229 | * visible to the CPU. | ||
230 | */ | ||
231 | #define dmac_inv_range cpu_cache.dma_inv_range | ||
232 | #define dmac_clean_range cpu_cache.dma_clean_range | ||
233 | #define dmac_flush_range cpu_cache.dma_flush_range | ||
234 | |||
235 | #else | ||
236 | |||
237 | #define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all) | ||
238 | #define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all) | ||
239 | #define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range) | ||
240 | #define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range) | ||
241 | #define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range) | ||
242 | #define __cpuc_flush_dcache_page __glue(_CACHE,_flush_kern_dcache_page) | ||
243 | |||
244 | extern void __cpuc_flush_kern_all(void); | ||
245 | extern void __cpuc_flush_user_all(void); | ||
246 | extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int); | ||
247 | extern void __cpuc_coherent_kern_range(unsigned long, unsigned long); | ||
248 | extern void __cpuc_coherent_user_range(unsigned long, unsigned long); | ||
249 | extern void __cpuc_flush_dcache_page(void *); | ||
250 | |||
251 | /* | ||
252 | * These are private to the dma-mapping API. Do not use directly. | ||
253 | * Their sole purpose is to ensure that data held in the cache | ||
254 | * is visible to DMA, or data written by DMA to system memory is | ||
255 | * visible to the CPU. | ||
256 | */ | ||
257 | #define dmac_inv_range __glue(_CACHE,_dma_inv_range) | ||
258 | #define dmac_clean_range __glue(_CACHE,_dma_clean_range) | ||
259 | #define dmac_flush_range __glue(_CACHE,_dma_flush_range) | ||
260 | |||
261 | extern void dmac_inv_range(const void *, const void *); | ||
262 | extern void dmac_clean_range(const void *, const void *); | ||
263 | extern void dmac_flush_range(const void *, const void *); | ||
264 | |||
265 | #endif | ||
266 | |||
267 | #ifdef CONFIG_OUTER_CACHE | ||
268 | |||
269 | extern struct outer_cache_fns outer_cache; | ||
270 | |||
271 | static inline void outer_inv_range(unsigned long start, unsigned long end) | ||
272 | { | ||
273 | if (outer_cache.inv_range) | ||
274 | outer_cache.inv_range(start, end); | ||
275 | } | ||
276 | static inline void outer_clean_range(unsigned long start, unsigned long end) | ||
277 | { | ||
278 | if (outer_cache.clean_range) | ||
279 | outer_cache.clean_range(start, end); | ||
280 | } | ||
281 | static inline void outer_flush_range(unsigned long start, unsigned long end) | ||
282 | { | ||
283 | if (outer_cache.flush_range) | ||
284 | outer_cache.flush_range(start, end); | ||
285 | } | ||
286 | |||
287 | #else | ||
288 | |||
289 | static inline void outer_inv_range(unsigned long start, unsigned long end) | ||
290 | { } | ||
291 | static inline void outer_clean_range(unsigned long start, unsigned long end) | ||
292 | { } | ||
293 | static inline void outer_flush_range(unsigned long start, unsigned long end) | ||
294 | { } | ||
295 | |||
296 | #endif | ||
297 | |||
298 | /* | ||
299 | * flush_cache_vmap() is used when creating mappings (eg, via vmap, | ||
300 | * vmalloc, ioremap etc) in kernel space for pages. Since the | ||
301 | * direct-mappings of these pages may contain cached data, we need | ||
302 | * to do a full cache flush to ensure that writebacks don't corrupt | ||
303 | * data placed into these pages via the new mappings. | ||
304 | */ | ||
305 | #define flush_cache_vmap(start, end) flush_cache_all() | ||
306 | #define flush_cache_vunmap(start, end) flush_cache_all() | ||
307 | |||
308 | /* | ||
309 | * Copy user data from/to a page which is mapped into a different | ||
310 | * processes address space. Really, we want to allow our "user | ||
311 | * space" model to handle this. | ||
312 | */ | ||
313 | #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ | ||
314 | do { \ | ||
315 | memcpy(dst, src, len); \ | ||
316 | flush_ptrace_access(vma, page, vaddr, dst, len, 1);\ | ||
317 | } while (0) | ||
318 | |||
319 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ | ||
320 | do { \ | ||
321 | memcpy(dst, src, len); \ | ||
322 | } while (0) | ||
323 | |||
324 | /* | ||
325 | * Convert calls to our calling convention. | ||
326 | */ | ||
327 | #define flush_cache_all() __cpuc_flush_kern_all() | ||
328 | #ifndef CONFIG_CPU_CACHE_VIPT | ||
329 | static inline void flush_cache_mm(struct mm_struct *mm) | ||
330 | { | ||
331 | if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask)) | ||
332 | __cpuc_flush_user_all(); | ||
333 | } | ||
334 | |||
335 | static inline void | ||
336 | flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) | ||
337 | { | ||
338 | if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) | ||
339 | __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end), | ||
340 | vma->vm_flags); | ||
341 | } | ||
342 | |||
343 | static inline void | ||
344 | flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn) | ||
345 | { | ||
346 | if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) { | ||
347 | unsigned long addr = user_addr & PAGE_MASK; | ||
348 | __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags); | ||
349 | } | ||
350 | } | ||
351 | |||
352 | static inline void | ||
353 | flush_ptrace_access(struct vm_area_struct *vma, struct page *page, | ||
354 | unsigned long uaddr, void *kaddr, | ||
355 | unsigned long len, int write) | ||
356 | { | ||
357 | if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) { | ||
358 | unsigned long addr = (unsigned long)kaddr; | ||
359 | __cpuc_coherent_kern_range(addr, addr + len); | ||
360 | } | ||
361 | } | ||
362 | #else | ||
363 | extern void flush_cache_mm(struct mm_struct *mm); | ||
364 | extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); | ||
365 | extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn); | ||
366 | extern void flush_ptrace_access(struct vm_area_struct *vma, struct page *page, | ||
367 | unsigned long uaddr, void *kaddr, | ||
368 | unsigned long len, int write); | ||
369 | #endif | ||
370 | |||
371 | #define flush_cache_dup_mm(mm) flush_cache_mm(mm) | ||
372 | |||
373 | /* | ||
374 | * flush_cache_user_range is used when we want to ensure that the | ||
375 | * Harvard caches are synchronised for the user space address range. | ||
376 | * This is used for the ARM private sys_cacheflush system call. | ||
377 | */ | ||
378 | #define flush_cache_user_range(vma,start,end) \ | ||
379 | __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end)) | ||
380 | |||
381 | /* | ||
382 | * Perform necessary cache operations to ensure that data previously | ||
383 | * stored within this range of addresses can be executed by the CPU. | ||
384 | */ | ||
385 | #define flush_icache_range(s,e) __cpuc_coherent_kern_range(s,e) | ||
386 | |||
387 | /* | ||
388 | * Perform necessary cache operations to ensure that the TLB will | ||
389 | * see data written in the specified area. | ||
390 | */ | ||
391 | #define clean_dcache_area(start,size) cpu_dcache_clean_area(start, size) | ||
392 | |||
393 | /* | ||
394 | * flush_dcache_page is used when the kernel has written to the page | ||
395 | * cache page at virtual address page->virtual. | ||
396 | * | ||
397 | * If this page isn't mapped (ie, page_mapping == NULL), or it might | ||
398 | * have userspace mappings, then we _must_ always clean + invalidate | ||
399 | * the dcache entries associated with the kernel mapping. | ||
400 | * | ||
401 | * Otherwise we can defer the operation, and clean the cache when we are | ||
402 | * about to change to user space. This is the same method as used on SPARC64. | ||
403 | * See update_mmu_cache for the user space part. | ||
404 | */ | ||
405 | extern void flush_dcache_page(struct page *); | ||
406 | |||
407 | extern void __flush_dcache_page(struct address_space *mapping, struct page *page); | ||
408 | |||
409 | static inline void __flush_icache_all(void) | ||
410 | { | ||
411 | asm("mcr p15, 0, %0, c7, c5, 0 @ invalidate I-cache\n" | ||
412 | : | ||
413 | : "r" (0)); | ||
414 | } | ||
415 | |||
416 | #define ARCH_HAS_FLUSH_ANON_PAGE | ||
417 | static inline void flush_anon_page(struct vm_area_struct *vma, | ||
418 | struct page *page, unsigned long vmaddr) | ||
419 | { | ||
420 | extern void __flush_anon_page(struct vm_area_struct *vma, | ||
421 | struct page *, unsigned long); | ||
422 | if (PageAnon(page)) | ||
423 | __flush_anon_page(vma, page, vmaddr); | ||
424 | } | ||
425 | |||
426 | #define flush_dcache_mmap_lock(mapping) \ | ||
427 | spin_lock_irq(&(mapping)->tree_lock) | ||
428 | #define flush_dcache_mmap_unlock(mapping) \ | ||
429 | spin_unlock_irq(&(mapping)->tree_lock) | ||
430 | |||
431 | #define flush_icache_user_range(vma,page,addr,len) \ | ||
432 | flush_dcache_page(page) | ||
433 | |||
434 | /* | ||
435 | * We don't appear to need to do anything here. In fact, if we did, we'd | ||
436 | * duplicate cache flushing elsewhere performed by flush_dcache_page(). | ||
437 | */ | ||
438 | #define flush_icache_page(vma,page) do { } while (0) | ||
439 | |||
440 | static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt, | ||
441 | unsigned offset, size_t size) | ||
442 | { | ||
443 | const void *start = (void __force *)virt + offset; | ||
444 | dmac_inv_range(start, start + size); | ||
445 | } | ||
446 | |||
447 | #define __cacheid_present(val) (val != read_cpuid(CPUID_ID)) | ||
448 | #define __cacheid_type_v7(val) ((val & (7 << 29)) == (4 << 29)) | ||
449 | |||
450 | #define __cacheid_vivt_prev7(val) ((val & (15 << 25)) != (14 << 25)) | ||
451 | #define __cacheid_vipt_prev7(val) ((val & (15 << 25)) == (14 << 25)) | ||
452 | #define __cacheid_vipt_nonaliasing_prev7(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25)) | ||
453 | #define __cacheid_vipt_aliasing_prev7(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23)) | ||
454 | |||
455 | #define __cacheid_vivt(val) (__cacheid_type_v7(val) ? 0 : __cacheid_vivt_prev7(val)) | ||
456 | #define __cacheid_vipt(val) (__cacheid_type_v7(val) ? 1 : __cacheid_vipt_prev7(val)) | ||
457 | #define __cacheid_vipt_nonaliasing(val) (__cacheid_type_v7(val) ? 1 : __cacheid_vipt_nonaliasing_prev7(val)) | ||
458 | #define __cacheid_vipt_aliasing(val) (__cacheid_type_v7(val) ? 0 : __cacheid_vipt_aliasing_prev7(val)) | ||
459 | #define __cacheid_vivt_asid_tagged_instr(val) (__cacheid_type_v7(val) ? ((val & (3 << 14)) == (1 << 14)) : 0) | ||
460 | |||
461 | #if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT) | ||
462 | /* | ||
463 | * VIVT caches only | ||
464 | */ | ||
465 | #define cache_is_vivt() 1 | ||
466 | #define cache_is_vipt() 0 | ||
467 | #define cache_is_vipt_nonaliasing() 0 | ||
468 | #define cache_is_vipt_aliasing() 0 | ||
469 | #define icache_is_vivt_asid_tagged() 0 | ||
470 | |||
471 | #elif !defined(CONFIG_CPU_CACHE_VIVT) && defined(CONFIG_CPU_CACHE_VIPT) | ||
472 | /* | ||
473 | * VIPT caches only | ||
474 | */ | ||
475 | #define cache_is_vivt() 0 | ||
476 | #define cache_is_vipt() 1 | ||
477 | #define cache_is_vipt_nonaliasing() \ | ||
478 | ({ \ | ||
479 | unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ | ||
480 | __cacheid_vipt_nonaliasing(__val); \ | ||
481 | }) | ||
482 | |||
483 | #define cache_is_vipt_aliasing() \ | ||
484 | ({ \ | ||
485 | unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ | ||
486 | __cacheid_vipt_aliasing(__val); \ | ||
487 | }) | ||
488 | |||
489 | #define icache_is_vivt_asid_tagged() \ | ||
490 | ({ \ | ||
491 | unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ | ||
492 | __cacheid_vivt_asid_tagged_instr(__val); \ | ||
493 | }) | ||
494 | |||
495 | #else | ||
496 | /* | ||
497 | * VIVT or VIPT caches. Note that this is unreliable since ARM926 | ||
498 | * and V6 CPUs satisfy the "(val & (15 << 25)) == (14 << 25)" test. | ||
499 | * There's no way to tell from the CacheType register what type (!) | ||
500 | * the cache is. | ||
501 | */ | ||
502 | #define cache_is_vivt() \ | ||
503 | ({ \ | ||
504 | unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ | ||
505 | (!__cacheid_present(__val)) || __cacheid_vivt(__val); \ | ||
506 | }) | ||
507 | |||
508 | #define cache_is_vipt() \ | ||
509 | ({ \ | ||
510 | unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ | ||
511 | __cacheid_present(__val) && __cacheid_vipt(__val); \ | ||
512 | }) | ||
513 | |||
514 | #define cache_is_vipt_nonaliasing() \ | ||
515 | ({ \ | ||
516 | unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ | ||
517 | __cacheid_present(__val) && \ | ||
518 | __cacheid_vipt_nonaliasing(__val); \ | ||
519 | }) | ||
520 | |||
521 | #define cache_is_vipt_aliasing() \ | ||
522 | ({ \ | ||
523 | unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ | ||
524 | __cacheid_present(__val) && \ | ||
525 | __cacheid_vipt_aliasing(__val); \ | ||
526 | }) | ||
527 | |||
528 | #define icache_is_vivt_asid_tagged() \ | ||
529 | ({ \ | ||
530 | unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ | ||
531 | __cacheid_present(__val) && \ | ||
532 | __cacheid_vivt_asid_tagged_instr(__val); \ | ||
533 | }) | ||
534 | |||
535 | #endif | ||
536 | |||
537 | #endif | ||
diff --git a/arch/arm/include/asm/checksum.h b/arch/arm/include/asm/checksum.h new file mode 100644 index 000000000000..6dcc16430868 --- /dev/null +++ b/arch/arm/include/asm/checksum.h | |||
@@ -0,0 +1,139 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/checksum.h | ||
3 | * | ||
4 | * IP checksum routines | ||
5 | * | ||
6 | * Copyright (C) Original authors of ../asm-i386/checksum.h | ||
7 | * Copyright (C) 1996-1999 Russell King | ||
8 | */ | ||
9 | #ifndef __ASM_ARM_CHECKSUM_H | ||
10 | #define __ASM_ARM_CHECKSUM_H | ||
11 | |||
12 | #include <linux/in6.h> | ||
13 | |||
14 | /* | ||
15 | * computes the checksum of a memory block at buff, length len, | ||
16 | * and adds in "sum" (32-bit) | ||
17 | * | ||
18 | * returns a 32-bit number suitable for feeding into itself | ||
19 | * or csum_tcpudp_magic | ||
20 | * | ||
21 | * this function must be called with even lengths, except | ||
22 | * for the last fragment, which may be odd | ||
23 | * | ||
24 | * it's best to have buff aligned on a 32-bit boundary | ||
25 | */ | ||
26 | __wsum csum_partial(const void *buff, int len, __wsum sum); | ||
27 | |||
28 | /* | ||
29 | * the same as csum_partial, but copies from src while it | ||
30 | * checksums, and handles user-space pointer exceptions correctly, when needed. | ||
31 | * | ||
32 | * here even more important to align src and dst on a 32-bit (or even | ||
33 | * better 64-bit) boundary | ||
34 | */ | ||
35 | |||
36 | __wsum | ||
37 | csum_partial_copy_nocheck(const void *src, void *dst, int len, __wsum sum); | ||
38 | |||
39 | __wsum | ||
40 | csum_partial_copy_from_user(const void __user *src, void *dst, int len, __wsum sum, int *err_ptr); | ||
41 | |||
42 | /* | ||
43 | * Fold a partial checksum without adding pseudo headers | ||
44 | */ | ||
45 | static inline __sum16 csum_fold(__wsum sum) | ||
46 | { | ||
47 | __asm__( | ||
48 | "add %0, %1, %1, ror #16 @ csum_fold" | ||
49 | : "=r" (sum) | ||
50 | : "r" (sum) | ||
51 | : "cc"); | ||
52 | return (__force __sum16)(~(__force u32)sum >> 16); | ||
53 | } | ||
54 | |||
55 | /* | ||
56 | * This is a version of ip_compute_csum() optimized for IP headers, | ||
57 | * which always checksum on 4 octet boundaries. | ||
58 | */ | ||
59 | static inline __sum16 | ||
60 | ip_fast_csum(const void *iph, unsigned int ihl) | ||
61 | { | ||
62 | unsigned int tmp1; | ||
63 | __wsum sum; | ||
64 | |||
65 | __asm__ __volatile__( | ||
66 | "ldr %0, [%1], #4 @ ip_fast_csum \n\ | ||
67 | ldr %3, [%1], #4 \n\ | ||
68 | sub %2, %2, #5 \n\ | ||
69 | adds %0, %0, %3 \n\ | ||
70 | ldr %3, [%1], #4 \n\ | ||
71 | adcs %0, %0, %3 \n\ | ||
72 | ldr %3, [%1], #4 \n\ | ||
73 | 1: adcs %0, %0, %3 \n\ | ||
74 | ldr %3, [%1], #4 \n\ | ||
75 | tst %2, #15 @ do this carefully \n\ | ||
76 | subne %2, %2, #1 @ without destroying \n\ | ||
77 | bne 1b @ the carry flag \n\ | ||
78 | adcs %0, %0, %3 \n\ | ||
79 | adc %0, %0, #0" | ||
80 | : "=r" (sum), "=r" (iph), "=r" (ihl), "=r" (tmp1) | ||
81 | : "1" (iph), "2" (ihl) | ||
82 | : "cc", "memory"); | ||
83 | return csum_fold(sum); | ||
84 | } | ||
85 | |||
86 | static inline __wsum | ||
87 | csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len, | ||
88 | unsigned short proto, __wsum sum) | ||
89 | { | ||
90 | __asm__( | ||
91 | "adds %0, %1, %2 @ csum_tcpudp_nofold \n\ | ||
92 | adcs %0, %0, %3 \n" | ||
93 | #ifdef __ARMEB__ | ||
94 | "adcs %0, %0, %4 \n" | ||
95 | #else | ||
96 | "adcs %0, %0, %4, lsl #8 \n" | ||
97 | #endif | ||
98 | "adcs %0, %0, %5 \n\ | ||
99 | adc %0, %0, #0" | ||
100 | : "=&r"(sum) | ||
101 | : "r" (sum), "r" (daddr), "r" (saddr), "r" (len), "Ir" (htons(proto)) | ||
102 | : "cc"); | ||
103 | return sum; | ||
104 | } | ||
105 | /* | ||
106 | * computes the checksum of the TCP/UDP pseudo-header | ||
107 | * returns a 16-bit checksum, already complemented | ||
108 | */ | ||
109 | static inline __sum16 | ||
110 | csum_tcpudp_magic(__be32 saddr, __be32 daddr, unsigned short len, | ||
111 | unsigned short proto, __wsum sum) | ||
112 | { | ||
113 | return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum)); | ||
114 | } | ||
115 | |||
116 | |||
117 | /* | ||
118 | * this routine is used for miscellaneous IP-like checksums, mainly | ||
119 | * in icmp.c | ||
120 | */ | ||
121 | static inline __sum16 | ||
122 | ip_compute_csum(const void *buff, int len) | ||
123 | { | ||
124 | return csum_fold(csum_partial(buff, len, 0)); | ||
125 | } | ||
126 | |||
127 | #define _HAVE_ARCH_IPV6_CSUM | ||
128 | extern __wsum | ||
129 | __csum_ipv6_magic(const struct in6_addr *saddr, const struct in6_addr *daddr, __be32 len, | ||
130 | __be32 proto, __wsum sum); | ||
131 | |||
132 | static inline __sum16 | ||
133 | csum_ipv6_magic(const struct in6_addr *saddr, const struct in6_addr *daddr, __u32 len, | ||
134 | unsigned short proto, __wsum sum) | ||
135 | { | ||
136 | return csum_fold(__csum_ipv6_magic(saddr, daddr, htonl(len), | ||
137 | htonl(proto), sum)); | ||
138 | } | ||
139 | #endif | ||
diff --git a/arch/arm/include/asm/cnt32_to_63.h b/arch/arm/include/asm/cnt32_to_63.h new file mode 100644 index 000000000000..480c873fa746 --- /dev/null +++ b/arch/arm/include/asm/cnt32_to_63.h | |||
@@ -0,0 +1,78 @@ | |||
1 | /* | ||
2 | * include/asm/cnt32_to_63.h -- extend a 32-bit counter to 63 bits | ||
3 | * | ||
4 | * Author: Nicolas Pitre | ||
5 | * Created: December 3, 2006 | ||
6 | * Copyright: MontaVista Software, Inc. | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 | ||
10 | * as published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __INCLUDE_CNT32_TO_63_H__ | ||
14 | #define __INCLUDE_CNT32_TO_63_H__ | ||
15 | |||
16 | #include <linux/compiler.h> | ||
17 | #include <asm/types.h> | ||
18 | #include <asm/byteorder.h> | ||
19 | |||
20 | /* | ||
21 | * Prototype: u64 cnt32_to_63(u32 cnt) | ||
22 | * Many hardware clock counters are only 32 bits wide and therefore have | ||
23 | * a relatively short period making wrap-arounds rather frequent. This | ||
24 | * is a problem when implementing sched_clock() for example, where a 64-bit | ||
25 | * non-wrapping monotonic value is expected to be returned. | ||
26 | * | ||
27 | * To overcome that limitation, let's extend a 32-bit counter to 63 bits | ||
28 | * in a completely lock free fashion. Bits 0 to 31 of the clock are provided | ||
29 | * by the hardware while bits 32 to 62 are stored in memory. The top bit in | ||
30 | * memory is used to synchronize with the hardware clock half-period. When | ||
31 | * the top bit of both counters (hardware and in memory) differ then the | ||
32 | * memory is updated with a new value, incrementing it when the hardware | ||
33 | * counter wraps around. | ||
34 | * | ||
35 | * Because a word store in memory is atomic then the incremented value will | ||
36 | * always be in synch with the top bit indicating to any potential concurrent | ||
37 | * reader if the value in memory is up to date or not with regards to the | ||
38 | * needed increment. And any race in updating the value in memory is harmless | ||
39 | * as the same value would simply be stored more than once. | ||
40 | * | ||
41 | * The only restriction for the algorithm to work properly is that this | ||
42 | * code must be executed at least once per each half period of the 32-bit | ||
43 | * counter to properly update the state bit in memory. This is usually not a | ||
44 | * problem in practice, but if it is then a kernel timer could be scheduled | ||
45 | * to manage for this code to be executed often enough. | ||
46 | * | ||
47 | * Note that the top bit (bit 63) in the returned value should be considered | ||
48 | * as garbage. It is not cleared here because callers are likely to use a | ||
49 | * multiplier on the returned value which can get rid of the top bit | ||
50 | * implicitly by making the multiplier even, therefore saving on a runtime | ||
51 | * clear-bit instruction. Otherwise caller must remember to clear the top | ||
52 | * bit explicitly. | ||
53 | */ | ||
54 | |||
55 | /* this is used only to give gcc a clue about good code generation */ | ||
56 | typedef union { | ||
57 | struct { | ||
58 | #if defined(__LITTLE_ENDIAN) | ||
59 | u32 lo, hi; | ||
60 | #elif defined(__BIG_ENDIAN) | ||
61 | u32 hi, lo; | ||
62 | #endif | ||
63 | }; | ||
64 | u64 val; | ||
65 | } cnt32_to_63_t; | ||
66 | |||
67 | #define cnt32_to_63(cnt_lo) \ | ||
68 | ({ \ | ||
69 | static volatile u32 __m_cnt_hi = 0; \ | ||
70 | cnt32_to_63_t __x; \ | ||
71 | __x.hi = __m_cnt_hi; \ | ||
72 | __x.lo = (cnt_lo); \ | ||
73 | if (unlikely((s32)(__x.hi ^ __x.lo) < 0)) \ | ||
74 | __m_cnt_hi = __x.hi = (__x.hi ^ 0x80000000) + (__x.hi >> 31); \ | ||
75 | __x.val; \ | ||
76 | }) | ||
77 | |||
78 | #endif | ||
diff --git a/arch/arm/include/asm/cpu-multi32.h b/arch/arm/include/asm/cpu-multi32.h new file mode 100644 index 000000000000..e2b5b0b2116a --- /dev/null +++ b/arch/arm/include/asm/cpu-multi32.h | |||
@@ -0,0 +1,69 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/cpu-multi32.h | ||
3 | * | ||
4 | * Copyright (C) 2000 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #include <asm/page.h> | ||
11 | |||
12 | struct mm_struct; | ||
13 | |||
14 | /* | ||
15 | * Don't change this structure - ASM code | ||
16 | * relies on it. | ||
17 | */ | ||
18 | extern struct processor { | ||
19 | /* MISC | ||
20 | * get data abort address/flags | ||
21 | */ | ||
22 | void (*_data_abort)(unsigned long pc); | ||
23 | /* | ||
24 | * Retrieve prefetch fault address | ||
25 | */ | ||
26 | unsigned long (*_prefetch_abort)(unsigned long lr); | ||
27 | /* | ||
28 | * Set up any processor specifics | ||
29 | */ | ||
30 | void (*_proc_init)(void); | ||
31 | /* | ||
32 | * Disable any processor specifics | ||
33 | */ | ||
34 | void (*_proc_fin)(void); | ||
35 | /* | ||
36 | * Special stuff for a reset | ||
37 | */ | ||
38 | void (*reset)(unsigned long addr) __attribute__((noreturn)); | ||
39 | /* | ||
40 | * Idle the processor | ||
41 | */ | ||
42 | int (*_do_idle)(void); | ||
43 | /* | ||
44 | * Processor architecture specific | ||
45 | */ | ||
46 | /* | ||
47 | * clean a virtual address range from the | ||
48 | * D-cache without flushing the cache. | ||
49 | */ | ||
50 | void (*dcache_clean_area)(void *addr, int size); | ||
51 | |||
52 | /* | ||
53 | * Set the page table | ||
54 | */ | ||
55 | void (*switch_mm)(unsigned long pgd_phys, struct mm_struct *mm); | ||
56 | /* | ||
57 | * Set a possibly extended PTE. Non-extended PTEs should | ||
58 | * ignore 'ext'. | ||
59 | */ | ||
60 | void (*set_pte_ext)(pte_t *ptep, pte_t pte, unsigned int ext); | ||
61 | } processor; | ||
62 | |||
63 | #define cpu_proc_init() processor._proc_init() | ||
64 | #define cpu_proc_fin() processor._proc_fin() | ||
65 | #define cpu_reset(addr) processor.reset(addr) | ||
66 | #define cpu_do_idle() processor._do_idle() | ||
67 | #define cpu_dcache_clean_area(addr,sz) processor.dcache_clean_area(addr,sz) | ||
68 | #define cpu_set_pte_ext(ptep,pte,ext) processor.set_pte_ext(ptep,pte,ext) | ||
69 | #define cpu_do_switch_mm(pgd,mm) processor.switch_mm(pgd,mm) | ||
diff --git a/arch/arm/include/asm/cpu-single.h b/arch/arm/include/asm/cpu-single.h new file mode 100644 index 000000000000..f073a6d2a406 --- /dev/null +++ b/arch/arm/include/asm/cpu-single.h | |||
@@ -0,0 +1,44 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/cpu-single.h | ||
3 | * | ||
4 | * Copyright (C) 2000 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | /* | ||
11 | * Single CPU | ||
12 | */ | ||
13 | #ifdef __STDC__ | ||
14 | #define __catify_fn(name,x) name##x | ||
15 | #else | ||
16 | #define __catify_fn(name,x) name/**/x | ||
17 | #endif | ||
18 | #define __cpu_fn(name,x) __catify_fn(name,x) | ||
19 | |||
20 | /* | ||
21 | * If we are supporting multiple CPUs, then we must use a table of | ||
22 | * function pointers for this lot. Otherwise, we can optimise the | ||
23 | * table away. | ||
24 | */ | ||
25 | #define cpu_proc_init __cpu_fn(CPU_NAME,_proc_init) | ||
26 | #define cpu_proc_fin __cpu_fn(CPU_NAME,_proc_fin) | ||
27 | #define cpu_reset __cpu_fn(CPU_NAME,_reset) | ||
28 | #define cpu_do_idle __cpu_fn(CPU_NAME,_do_idle) | ||
29 | #define cpu_dcache_clean_area __cpu_fn(CPU_NAME,_dcache_clean_area) | ||
30 | #define cpu_do_switch_mm __cpu_fn(CPU_NAME,_switch_mm) | ||
31 | #define cpu_set_pte_ext __cpu_fn(CPU_NAME,_set_pte_ext) | ||
32 | |||
33 | #include <asm/page.h> | ||
34 | |||
35 | struct mm_struct; | ||
36 | |||
37 | /* declare all the functions as extern */ | ||
38 | extern void cpu_proc_init(void); | ||
39 | extern void cpu_proc_fin(void); | ||
40 | extern int cpu_do_idle(void); | ||
41 | extern void cpu_dcache_clean_area(void *, int); | ||
42 | extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm); | ||
43 | extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext); | ||
44 | extern void cpu_reset(unsigned long addr) __attribute__((noreturn)); | ||
diff --git a/arch/arm/include/asm/cpu.h b/arch/arm/include/asm/cpu.h new file mode 100644 index 000000000000..634b2d7c612a --- /dev/null +++ b/arch/arm/include/asm/cpu.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/cpu.h | ||
3 | * | ||
4 | * Copyright (C) 2004-2005 ARM Ltd. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #ifndef __ASM_ARM_CPU_H | ||
11 | #define __ASM_ARM_CPU_H | ||
12 | |||
13 | #include <linux/percpu.h> | ||
14 | |||
15 | struct cpuinfo_arm { | ||
16 | struct cpu cpu; | ||
17 | #ifdef CONFIG_SMP | ||
18 | struct task_struct *idle; | ||
19 | unsigned int loops_per_jiffy; | ||
20 | #endif | ||
21 | }; | ||
22 | |||
23 | DECLARE_PER_CPU(struct cpuinfo_arm, cpu_data); | ||
24 | |||
25 | #endif | ||
diff --git a/arch/arm/include/asm/cputime.h b/arch/arm/include/asm/cputime.h new file mode 100644 index 000000000000..3a8002a5fec7 --- /dev/null +++ b/arch/arm/include/asm/cputime.h | |||
@@ -0,0 +1,6 @@ | |||
1 | #ifndef __ARM_CPUTIME_H | ||
2 | #define __ARM_CPUTIME_H | ||
3 | |||
4 | #include <asm-generic/cputime.h> | ||
5 | |||
6 | #endif /* __ARM_CPUTIME_H */ | ||
diff --git a/arch/arm/include/asm/current.h b/arch/arm/include/asm/current.h new file mode 100644 index 000000000000..75d21e2a3ff7 --- /dev/null +++ b/arch/arm/include/asm/current.h | |||
@@ -0,0 +1,15 @@ | |||
1 | #ifndef _ASMARM_CURRENT_H | ||
2 | #define _ASMARM_CURRENT_H | ||
3 | |||
4 | #include <linux/thread_info.h> | ||
5 | |||
6 | static inline struct task_struct *get_current(void) __attribute_const__; | ||
7 | |||
8 | static inline struct task_struct *get_current(void) | ||
9 | { | ||
10 | return current_thread_info()->task; | ||
11 | } | ||
12 | |||
13 | #define current (get_current()) | ||
14 | |||
15 | #endif /* _ASMARM_CURRENT_H */ | ||
diff --git a/arch/arm/include/asm/delay.h b/arch/arm/include/asm/delay.h new file mode 100644 index 000000000000..b2deda181549 --- /dev/null +++ b/arch/arm/include/asm/delay.h | |||
@@ -0,0 +1,44 @@ | |||
1 | /* | ||
2 | * Copyright (C) 1995-2004 Russell King | ||
3 | * | ||
4 | * Delay routines, using a pre-computed "loops_per_second" value. | ||
5 | */ | ||
6 | #ifndef __ASM_ARM_DELAY_H | ||
7 | #define __ASM_ARM_DELAY_H | ||
8 | |||
9 | #include <asm/param.h> /* HZ */ | ||
10 | |||
11 | extern void __delay(int loops); | ||
12 | |||
13 | /* | ||
14 | * This function intentionally does not exist; if you see references to | ||
15 | * it, it means that you're calling udelay() with an out of range value. | ||
16 | * | ||
17 | * With currently imposed limits, this means that we support a max delay | ||
18 | * of 2000us. Further limits: HZ<=1000 and bogomips<=3355 | ||
19 | */ | ||
20 | extern void __bad_udelay(void); | ||
21 | |||
22 | /* | ||
23 | * division by multiplication: you don't have to worry about | ||
24 | * loss of precision. | ||
25 | * | ||
26 | * Use only for very small delays ( < 1 msec). Should probably use a | ||
27 | * lookup table, really, as the multiplications take much too long with | ||
28 | * short delays. This is a "reasonable" implementation, though (and the | ||
29 | * first constant multiplications gets optimized away if the delay is | ||
30 | * a constant) | ||
31 | */ | ||
32 | extern void __udelay(unsigned long usecs); | ||
33 | extern void __const_udelay(unsigned long); | ||
34 | |||
35 | #define MAX_UDELAY_MS 2 | ||
36 | |||
37 | #define udelay(n) \ | ||
38 | (__builtin_constant_p(n) ? \ | ||
39 | ((n) > (MAX_UDELAY_MS * 1000) ? __bad_udelay() : \ | ||
40 | __const_udelay((n) * ((2199023U*HZ)>>11))) : \ | ||
41 | __udelay(n)) | ||
42 | |||
43 | #endif /* defined(_ARM_DELAY_H) */ | ||
44 | |||
diff --git a/arch/arm/include/asm/device.h b/arch/arm/include/asm/device.h new file mode 100644 index 000000000000..c61642b40603 --- /dev/null +++ b/arch/arm/include/asm/device.h | |||
@@ -0,0 +1,15 @@ | |||
1 | /* | ||
2 | * Arch specific extensions to struct device | ||
3 | * | ||
4 | * This file is released under the GPLv2 | ||
5 | */ | ||
6 | #ifndef ASMARM_DEVICE_H | ||
7 | #define ASMARM_DEVICE_H | ||
8 | |||
9 | struct dev_archdata { | ||
10 | #ifdef CONFIG_DMABOUNCE | ||
11 | struct dmabounce_device_info *dmabounce; | ||
12 | #endif | ||
13 | }; | ||
14 | |||
15 | #endif | ||
diff --git a/arch/arm/include/asm/div64.h b/arch/arm/include/asm/div64.h new file mode 100644 index 000000000000..5001390be958 --- /dev/null +++ b/arch/arm/include/asm/div64.h | |||
@@ -0,0 +1,227 @@ | |||
1 | #ifndef __ASM_ARM_DIV64 | ||
2 | #define __ASM_ARM_DIV64 | ||
3 | |||
4 | #include <asm/system.h> | ||
5 | #include <linux/types.h> | ||
6 | |||
7 | /* | ||
8 | * The semantics of do_div() are: | ||
9 | * | ||
10 | * uint32_t do_div(uint64_t *n, uint32_t base) | ||
11 | * { | ||
12 | * uint32_t remainder = *n % base; | ||
13 | * *n = *n / base; | ||
14 | * return remainder; | ||
15 | * } | ||
16 | * | ||
17 | * In other words, a 64-bit dividend with a 32-bit divisor producing | ||
18 | * a 64-bit result and a 32-bit remainder. To accomplish this optimally | ||
19 | * we call a special __do_div64 helper with completely non standard | ||
20 | * calling convention for arguments and results (beware). | ||
21 | */ | ||
22 | |||
23 | #ifdef __ARMEB__ | ||
24 | #define __xh "r0" | ||
25 | #define __xl "r1" | ||
26 | #else | ||
27 | #define __xl "r0" | ||
28 | #define __xh "r1" | ||
29 | #endif | ||
30 | |||
31 | #define __do_div_asm(n, base) \ | ||
32 | ({ \ | ||
33 | register unsigned int __base asm("r4") = base; \ | ||
34 | register unsigned long long __n asm("r0") = n; \ | ||
35 | register unsigned long long __res asm("r2"); \ | ||
36 | register unsigned int __rem asm(__xh); \ | ||
37 | asm( __asmeq("%0", __xh) \ | ||
38 | __asmeq("%1", "r2") \ | ||
39 | __asmeq("%2", "r0") \ | ||
40 | __asmeq("%3", "r4") \ | ||
41 | "bl __do_div64" \ | ||
42 | : "=r" (__rem), "=r" (__res) \ | ||
43 | : "r" (__n), "r" (__base) \ | ||
44 | : "ip", "lr", "cc"); \ | ||
45 | n = __res; \ | ||
46 | __rem; \ | ||
47 | }) | ||
48 | |||
49 | #if __GNUC__ < 4 | ||
50 | |||
51 | /* | ||
52 | * gcc versions earlier than 4.0 are simply too problematic for the | ||
53 | * optimized implementation below. First there is gcc PR 15089 that | ||
54 | * tend to trig on more complex constructs, spurious .global __udivsi3 | ||
55 | * are inserted even if none of those symbols are referenced in the | ||
56 | * generated code, and those gcc versions are not able to do constant | ||
57 | * propagation on long long values anyway. | ||
58 | */ | ||
59 | #define do_div(n, base) __do_div_asm(n, base) | ||
60 | |||
61 | #elif __GNUC__ >= 4 | ||
62 | |||
63 | #include <asm/bug.h> | ||
64 | |||
65 | /* | ||
66 | * If the divisor happens to be constant, we determine the appropriate | ||
67 | * inverse at compile time to turn the division into a few inline | ||
68 | * multiplications instead which is much faster. And yet only if compiling | ||
69 | * for ARMv4 or higher (we need umull/umlal) and if the gcc version is | ||
70 | * sufficiently recent to perform proper long long constant propagation. | ||
71 | * (It is unfortunate that gcc doesn't perform all this internally.) | ||
72 | */ | ||
73 | #define do_div(n, base) \ | ||
74 | ({ \ | ||
75 | unsigned int __r, __b = (base); \ | ||
76 | if (!__builtin_constant_p(__b) || __b == 0 || \ | ||
77 | (__LINUX_ARM_ARCH__ < 4 && (__b & (__b - 1)) != 0)) { \ | ||
78 | /* non-constant divisor (or zero): slow path */ \ | ||
79 | __r = __do_div_asm(n, __b); \ | ||
80 | } else if ((__b & (__b - 1)) == 0) { \ | ||
81 | /* Trivial: __b is constant and a power of 2 */ \ | ||
82 | /* gcc does the right thing with this code. */ \ | ||
83 | __r = n; \ | ||
84 | __r &= (__b - 1); \ | ||
85 | n /= __b; \ | ||
86 | } else { \ | ||
87 | /* Multiply by inverse of __b: n/b = n*(p/b)/p */ \ | ||
88 | /* We rely on the fact that most of this code gets */ \ | ||
89 | /* optimized away at compile time due to constant */ \ | ||
90 | /* propagation and only a couple inline assembly */ \ | ||
91 | /* instructions should remain. Better avoid any */ \ | ||
92 | /* code construct that might prevent that. */ \ | ||
93 | unsigned long long __res, __x, __t, __m, __n = n; \ | ||
94 | unsigned int __c, __p, __z = 0; \ | ||
95 | /* preserve low part of n for reminder computation */ \ | ||
96 | __r = __n; \ | ||
97 | /* determine number of bits to represent __b */ \ | ||
98 | __p = 1 << __div64_fls(__b); \ | ||
99 | /* compute __m = ((__p << 64) + __b - 1) / __b */ \ | ||
100 | __m = (~0ULL / __b) * __p; \ | ||
101 | __m += (((~0ULL % __b + 1) * __p) + __b - 1) / __b; \ | ||
102 | /* compute __res = __m*(~0ULL/__b*__b-1)/(__p << 64) */ \ | ||
103 | __x = ~0ULL / __b * __b - 1; \ | ||
104 | __res = (__m & 0xffffffff) * (__x & 0xffffffff); \ | ||
105 | __res >>= 32; \ | ||
106 | __res += (__m & 0xffffffff) * (__x >> 32); \ | ||
107 | __t = __res; \ | ||
108 | __res += (__x & 0xffffffff) * (__m >> 32); \ | ||
109 | __t = (__res < __t) ? (1ULL << 32) : 0; \ | ||
110 | __res = (__res >> 32) + __t; \ | ||
111 | __res += (__m >> 32) * (__x >> 32); \ | ||
112 | __res /= __p; \ | ||
113 | /* Now sanitize and optimize what we've got. */ \ | ||
114 | if (~0ULL % (__b / (__b & -__b)) == 0) { \ | ||
115 | /* those cases can be simplified with: */ \ | ||
116 | __n /= (__b & -__b); \ | ||
117 | __m = ~0ULL / (__b / (__b & -__b)); \ | ||
118 | __p = 1; \ | ||
119 | __c = 1; \ | ||
120 | } else if (__res != __x / __b) { \ | ||
121 | /* We can't get away without a correction */ \ | ||
122 | /* to compensate for bit truncation errors. */ \ | ||
123 | /* To avoid it we'd need an additional bit */ \ | ||
124 | /* to represent __m which would overflow it. */ \ | ||
125 | /* Instead we do m=p/b and n/b=(n*m+m)/p. */ \ | ||
126 | __c = 1; \ | ||
127 | /* Compute __m = (__p << 64) / __b */ \ | ||
128 | __m = (~0ULL / __b) * __p; \ | ||
129 | __m += ((~0ULL % __b + 1) * __p) / __b; \ | ||
130 | } else { \ | ||
131 | /* Reduce __m/__p, and try to clear bit 31 */ \ | ||
132 | /* of __m when possible otherwise that'll */ \ | ||
133 | /* need extra overflow handling later. */ \ | ||
134 | unsigned int __bits = -(__m & -__m); \ | ||
135 | __bits |= __m >> 32; \ | ||
136 | __bits = (~__bits) << 1; \ | ||
137 | /* If __bits == 0 then setting bit 31 is */ \ | ||
138 | /* unavoidable. Simply apply the maximum */ \ | ||
139 | /* possible reduction in that case. */ \ | ||
140 | /* Otherwise the MSB of __bits indicates the */ \ | ||
141 | /* best reduction we should apply. */ \ | ||
142 | if (!__bits) { \ | ||
143 | __p /= (__m & -__m); \ | ||
144 | __m /= (__m & -__m); \ | ||
145 | } else { \ | ||
146 | __p >>= __div64_fls(__bits); \ | ||
147 | __m >>= __div64_fls(__bits); \ | ||
148 | } \ | ||
149 | /* No correction needed. */ \ | ||
150 | __c = 0; \ | ||
151 | } \ | ||
152 | /* Now we have a combination of 2 conditions: */ \ | ||
153 | /* 1) whether or not we need a correction (__c), and */ \ | ||
154 | /* 2) whether or not there might be an overflow in */ \ | ||
155 | /* the cross product (__m & ((1<<63) | (1<<31))) */ \ | ||
156 | /* Select the best insn combination to perform the */ \ | ||
157 | /* actual __m * __n / (__p << 64) operation. */ \ | ||
158 | if (!__c) { \ | ||
159 | asm ( "umull %Q0, %R0, %1, %Q2\n\t" \ | ||
160 | "mov %Q0, #0" \ | ||
161 | : "=&r" (__res) \ | ||
162 | : "r" (__m), "r" (__n) \ | ||
163 | : "cc" ); \ | ||
164 | } else if (!(__m & ((1ULL << 63) | (1ULL << 31)))) { \ | ||
165 | __res = __m; \ | ||
166 | asm ( "umlal %Q0, %R0, %Q1, %Q2\n\t" \ | ||
167 | "mov %Q0, #0" \ | ||
168 | : "+r" (__res) \ | ||
169 | : "r" (__m), "r" (__n) \ | ||
170 | : "cc" ); \ | ||
171 | } else { \ | ||
172 | asm ( "umull %Q0, %R0, %Q1, %Q2\n\t" \ | ||
173 | "cmn %Q0, %Q1\n\t" \ | ||
174 | "adcs %R0, %R0, %R1\n\t" \ | ||
175 | "adc %Q0, %3, #0" \ | ||
176 | : "=&r" (__res) \ | ||
177 | : "r" (__m), "r" (__n), "r" (__z) \ | ||
178 | : "cc" ); \ | ||
179 | } \ | ||
180 | if (!(__m & ((1ULL << 63) | (1ULL << 31)))) { \ | ||
181 | asm ( "umlal %R0, %Q0, %R1, %Q2\n\t" \ | ||
182 | "umlal %R0, %Q0, %Q1, %R2\n\t" \ | ||
183 | "mov %R0, #0\n\t" \ | ||
184 | "umlal %Q0, %R0, %R1, %R2" \ | ||
185 | : "+r" (__res) \ | ||
186 | : "r" (__m), "r" (__n) \ | ||
187 | : "cc" ); \ | ||
188 | } else { \ | ||
189 | asm ( "umlal %R0, %Q0, %R2, %Q3\n\t" \ | ||
190 | "umlal %R0, %1, %Q2, %R3\n\t" \ | ||
191 | "mov %R0, #0\n\t" \ | ||
192 | "adds %Q0, %1, %Q0\n\t" \ | ||
193 | "adc %R0, %R0, #0\n\t" \ | ||
194 | "umlal %Q0, %R0, %R2, %R3" \ | ||
195 | : "+r" (__res), "+r" (__z) \ | ||
196 | : "r" (__m), "r" (__n) \ | ||
197 | : "cc" ); \ | ||
198 | } \ | ||
199 | __res /= __p; \ | ||
200 | /* The reminder can be computed with 32-bit regs */ \ | ||
201 | /* only, and gcc is good at that. */ \ | ||
202 | { \ | ||
203 | unsigned int __res0 = __res; \ | ||
204 | unsigned int __b0 = __b; \ | ||
205 | __r -= __res0 * __b0; \ | ||
206 | } \ | ||
207 | /* BUG_ON(__r >= __b || __res * __b + __r != n); */ \ | ||
208 | n = __res; \ | ||
209 | } \ | ||
210 | __r; \ | ||
211 | }) | ||
212 | |||
213 | /* our own fls implementation to make sure constant propagation is fine */ | ||
214 | #define __div64_fls(bits) \ | ||
215 | ({ \ | ||
216 | unsigned int __left = (bits), __nr = 0; \ | ||
217 | if (__left & 0xffff0000) __nr += 16, __left >>= 16; \ | ||
218 | if (__left & 0x0000ff00) __nr += 8, __left >>= 8; \ | ||
219 | if (__left & 0x000000f0) __nr += 4, __left >>= 4; \ | ||
220 | if (__left & 0x0000000c) __nr += 2, __left >>= 2; \ | ||
221 | if (__left & 0x00000002) __nr += 1; \ | ||
222 | __nr; \ | ||
223 | }) | ||
224 | |||
225 | #endif | ||
226 | |||
227 | #endif | ||
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h new file mode 100644 index 000000000000..f41335ba6337 --- /dev/null +++ b/arch/arm/include/asm/dma-mapping.h | |||
@@ -0,0 +1,456 @@ | |||
1 | #ifndef ASMARM_DMA_MAPPING_H | ||
2 | #define ASMARM_DMA_MAPPING_H | ||
3 | |||
4 | #ifdef __KERNEL__ | ||
5 | |||
6 | #include <linux/mm.h> /* need struct page */ | ||
7 | |||
8 | #include <linux/scatterlist.h> | ||
9 | |||
10 | /* | ||
11 | * DMA-consistent mapping functions. These allocate/free a region of | ||
12 | * uncached, unwrite-buffered mapped memory space for use with DMA | ||
13 | * devices. This is the "generic" version. The PCI specific version | ||
14 | * is in pci.h | ||
15 | * | ||
16 | * Note: Drivers should NOT use this function directly, as it will break | ||
17 | * platforms with CONFIG_DMABOUNCE. | ||
18 | * Use the driver DMA support - see dma-mapping.h (dma_sync_*) | ||
19 | */ | ||
20 | extern void dma_cache_maint(const void *kaddr, size_t size, int rw); | ||
21 | |||
22 | /* | ||
23 | * Return whether the given device DMA address mask can be supported | ||
24 | * properly. For example, if your device can only drive the low 24-bits | ||
25 | * during bus mastering, then you would pass 0x00ffffff as the mask | ||
26 | * to this function. | ||
27 | * | ||
28 | * FIXME: This should really be a platform specific issue - we should | ||
29 | * return false if GFP_DMA allocations may not satisfy the supplied 'mask'. | ||
30 | */ | ||
31 | static inline int dma_supported(struct device *dev, u64 mask) | ||
32 | { | ||
33 | return dev->dma_mask && *dev->dma_mask != 0; | ||
34 | } | ||
35 | |||
36 | static inline int dma_set_mask(struct device *dev, u64 dma_mask) | ||
37 | { | ||
38 | if (!dev->dma_mask || !dma_supported(dev, dma_mask)) | ||
39 | return -EIO; | ||
40 | |||
41 | *dev->dma_mask = dma_mask; | ||
42 | |||
43 | return 0; | ||
44 | } | ||
45 | |||
46 | static inline int dma_get_cache_alignment(void) | ||
47 | { | ||
48 | return 32; | ||
49 | } | ||
50 | |||
51 | static inline int dma_is_consistent(struct device *dev, dma_addr_t handle) | ||
52 | { | ||
53 | return !!arch_is_coherent(); | ||
54 | } | ||
55 | |||
56 | /* | ||
57 | * DMA errors are defined by all-bits-set in the DMA address. | ||
58 | */ | ||
59 | static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) | ||
60 | { | ||
61 | return dma_addr == ~0; | ||
62 | } | ||
63 | |||
64 | /* | ||
65 | * Dummy noncoherent implementation. We don't provide a dma_cache_sync | ||
66 | * function so drivers using this API are highlighted with build warnings. | ||
67 | */ | ||
68 | static inline void * | ||
69 | dma_alloc_noncoherent(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp) | ||
70 | { | ||
71 | return NULL; | ||
72 | } | ||
73 | |||
74 | static inline void | ||
75 | dma_free_noncoherent(struct device *dev, size_t size, void *cpu_addr, | ||
76 | dma_addr_t handle) | ||
77 | { | ||
78 | } | ||
79 | |||
80 | /** | ||
81 | * dma_alloc_coherent - allocate consistent memory for DMA | ||
82 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | ||
83 | * @size: required memory size | ||
84 | * @handle: bus-specific DMA address | ||
85 | * | ||
86 | * Allocate some uncached, unbuffered memory for a device for | ||
87 | * performing DMA. This function allocates pages, and will | ||
88 | * return the CPU-viewed address, and sets @handle to be the | ||
89 | * device-viewed address. | ||
90 | */ | ||
91 | extern void * | ||
92 | dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp); | ||
93 | |||
94 | /** | ||
95 | * dma_free_coherent - free memory allocated by dma_alloc_coherent | ||
96 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | ||
97 | * @size: size of memory originally requested in dma_alloc_coherent | ||
98 | * @cpu_addr: CPU-view address returned from dma_alloc_coherent | ||
99 | * @handle: device-view address returned from dma_alloc_coherent | ||
100 | * | ||
101 | * Free (and unmap) a DMA buffer previously allocated by | ||
102 | * dma_alloc_coherent(). | ||
103 | * | ||
104 | * References to memory and mappings associated with cpu_addr/handle | ||
105 | * during and after this call executing are illegal. | ||
106 | */ | ||
107 | extern void | ||
108 | dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, | ||
109 | dma_addr_t handle); | ||
110 | |||
111 | /** | ||
112 | * dma_mmap_coherent - map a coherent DMA allocation into user space | ||
113 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | ||
114 | * @vma: vm_area_struct describing requested user mapping | ||
115 | * @cpu_addr: kernel CPU-view address returned from dma_alloc_coherent | ||
116 | * @handle: device-view address returned from dma_alloc_coherent | ||
117 | * @size: size of memory originally requested in dma_alloc_coherent | ||
118 | * | ||
119 | * Map a coherent DMA buffer previously allocated by dma_alloc_coherent | ||
120 | * into user space. The coherent DMA buffer must not be freed by the | ||
121 | * driver until the user space mapping has been released. | ||
122 | */ | ||
123 | int dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma, | ||
124 | void *cpu_addr, dma_addr_t handle, size_t size); | ||
125 | |||
126 | |||
127 | /** | ||
128 | * dma_alloc_writecombine - allocate writecombining memory for DMA | ||
129 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | ||
130 | * @size: required memory size | ||
131 | * @handle: bus-specific DMA address | ||
132 | * | ||
133 | * Allocate some uncached, buffered memory for a device for | ||
134 | * performing DMA. This function allocates pages, and will | ||
135 | * return the CPU-viewed address, and sets @handle to be the | ||
136 | * device-viewed address. | ||
137 | */ | ||
138 | extern void * | ||
139 | dma_alloc_writecombine(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp); | ||
140 | |||
141 | #define dma_free_writecombine(dev,size,cpu_addr,handle) \ | ||
142 | dma_free_coherent(dev,size,cpu_addr,handle) | ||
143 | |||
144 | int dma_mmap_writecombine(struct device *dev, struct vm_area_struct *vma, | ||
145 | void *cpu_addr, dma_addr_t handle, size_t size); | ||
146 | |||
147 | |||
148 | /** | ||
149 | * dma_map_single - map a single buffer for streaming DMA | ||
150 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | ||
151 | * @cpu_addr: CPU direct mapped address of buffer | ||
152 | * @size: size of buffer to map | ||
153 | * @dir: DMA transfer direction | ||
154 | * | ||
155 | * Ensure that any data held in the cache is appropriately discarded | ||
156 | * or written back. | ||
157 | * | ||
158 | * The device owns this memory once this call has completed. The CPU | ||
159 | * can regain ownership by calling dma_unmap_single() or | ||
160 | * dma_sync_single_for_cpu(). | ||
161 | */ | ||
162 | #ifndef CONFIG_DMABOUNCE | ||
163 | static inline dma_addr_t | ||
164 | dma_map_single(struct device *dev, void *cpu_addr, size_t size, | ||
165 | enum dma_data_direction dir) | ||
166 | { | ||
167 | if (!arch_is_coherent()) | ||
168 | dma_cache_maint(cpu_addr, size, dir); | ||
169 | |||
170 | return virt_to_dma(dev, (unsigned long)cpu_addr); | ||
171 | } | ||
172 | #else | ||
173 | extern dma_addr_t dma_map_single(struct device *,void *, size_t, enum dma_data_direction); | ||
174 | #endif | ||
175 | |||
176 | /** | ||
177 | * dma_map_page - map a portion of a page for streaming DMA | ||
178 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | ||
179 | * @page: page that buffer resides in | ||
180 | * @offset: offset into page for start of buffer | ||
181 | * @size: size of buffer to map | ||
182 | * @dir: DMA transfer direction | ||
183 | * | ||
184 | * Ensure that any data held in the cache is appropriately discarded | ||
185 | * or written back. | ||
186 | * | ||
187 | * The device owns this memory once this call has completed. The CPU | ||
188 | * can regain ownership by calling dma_unmap_page() or | ||
189 | * dma_sync_single_for_cpu(). | ||
190 | */ | ||
191 | static inline dma_addr_t | ||
192 | dma_map_page(struct device *dev, struct page *page, | ||
193 | unsigned long offset, size_t size, | ||
194 | enum dma_data_direction dir) | ||
195 | { | ||
196 | return dma_map_single(dev, page_address(page) + offset, size, (int)dir); | ||
197 | } | ||
198 | |||
199 | /** | ||
200 | * dma_unmap_single - unmap a single buffer previously mapped | ||
201 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | ||
202 | * @handle: DMA address of buffer | ||
203 | * @size: size of buffer to map | ||
204 | * @dir: DMA transfer direction | ||
205 | * | ||
206 | * Unmap a single streaming mode DMA translation. The handle and size | ||
207 | * must match what was provided in the previous dma_map_single() call. | ||
208 | * All other usages are undefined. | ||
209 | * | ||
210 | * After this call, reads by the CPU to the buffer are guaranteed to see | ||
211 | * whatever the device wrote there. | ||
212 | */ | ||
213 | #ifndef CONFIG_DMABOUNCE | ||
214 | static inline void | ||
215 | dma_unmap_single(struct device *dev, dma_addr_t handle, size_t size, | ||
216 | enum dma_data_direction dir) | ||
217 | { | ||
218 | /* nothing to do */ | ||
219 | } | ||
220 | #else | ||
221 | extern void dma_unmap_single(struct device *, dma_addr_t, size_t, enum dma_data_direction); | ||
222 | #endif | ||
223 | |||
224 | /** | ||
225 | * dma_unmap_page - unmap a buffer previously mapped through dma_map_page() | ||
226 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | ||
227 | * @handle: DMA address of buffer | ||
228 | * @size: size of buffer to map | ||
229 | * @dir: DMA transfer direction | ||
230 | * | ||
231 | * Unmap a single streaming mode DMA translation. The handle and size | ||
232 | * must match what was provided in the previous dma_map_single() call. | ||
233 | * All other usages are undefined. | ||
234 | * | ||
235 | * After this call, reads by the CPU to the buffer are guaranteed to see | ||
236 | * whatever the device wrote there. | ||
237 | */ | ||
238 | static inline void | ||
239 | dma_unmap_page(struct device *dev, dma_addr_t handle, size_t size, | ||
240 | enum dma_data_direction dir) | ||
241 | { | ||
242 | dma_unmap_single(dev, handle, size, (int)dir); | ||
243 | } | ||
244 | |||
245 | /** | ||
246 | * dma_map_sg - map a set of SG buffers for streaming mode DMA | ||
247 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | ||
248 | * @sg: list of buffers | ||
249 | * @nents: number of buffers to map | ||
250 | * @dir: DMA transfer direction | ||
251 | * | ||
252 | * Map a set of buffers described by scatterlist in streaming | ||
253 | * mode for DMA. This is the scatter-gather version of the | ||
254 | * above dma_map_single interface. Here the scatter gather list | ||
255 | * elements are each tagged with the appropriate dma address | ||
256 | * and length. They are obtained via sg_dma_{address,length}(SG). | ||
257 | * | ||
258 | * NOTE: An implementation may be able to use a smaller number of | ||
259 | * DMA address/length pairs than there are SG table elements. | ||
260 | * (for example via virtual mapping capabilities) | ||
261 | * The routine returns the number of addr/length pairs actually | ||
262 | * used, at most nents. | ||
263 | * | ||
264 | * Device ownership issues as mentioned above for dma_map_single are | ||
265 | * the same here. | ||
266 | */ | ||
267 | #ifndef CONFIG_DMABOUNCE | ||
268 | static inline int | ||
269 | dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, | ||
270 | enum dma_data_direction dir) | ||
271 | { | ||
272 | int i; | ||
273 | |||
274 | for (i = 0; i < nents; i++, sg++) { | ||
275 | char *virt; | ||
276 | |||
277 | sg->dma_address = page_to_dma(dev, sg_page(sg)) + sg->offset; | ||
278 | virt = sg_virt(sg); | ||
279 | |||
280 | if (!arch_is_coherent()) | ||
281 | dma_cache_maint(virt, sg->length, dir); | ||
282 | } | ||
283 | |||
284 | return nents; | ||
285 | } | ||
286 | #else | ||
287 | extern int dma_map_sg(struct device *, struct scatterlist *, int, enum dma_data_direction); | ||
288 | #endif | ||
289 | |||
290 | /** | ||
291 | * dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg | ||
292 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | ||
293 | * @sg: list of buffers | ||
294 | * @nents: number of buffers to map | ||
295 | * @dir: DMA transfer direction | ||
296 | * | ||
297 | * Unmap a set of streaming mode DMA translations. | ||
298 | * Again, CPU read rules concerning calls here are the same as for | ||
299 | * dma_unmap_single() above. | ||
300 | */ | ||
301 | #ifndef CONFIG_DMABOUNCE | ||
302 | static inline void | ||
303 | dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, | ||
304 | enum dma_data_direction dir) | ||
305 | { | ||
306 | |||
307 | /* nothing to do */ | ||
308 | } | ||
309 | #else | ||
310 | extern void dma_unmap_sg(struct device *, struct scatterlist *, int, enum dma_data_direction); | ||
311 | #endif | ||
312 | |||
313 | |||
314 | /** | ||
315 | * dma_sync_single_for_cpu | ||
316 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | ||
317 | * @handle: DMA address of buffer | ||
318 | * @size: size of buffer to map | ||
319 | * @dir: DMA transfer direction | ||
320 | * | ||
321 | * Make physical memory consistent for a single streaming mode DMA | ||
322 | * translation after a transfer. | ||
323 | * | ||
324 | * If you perform a dma_map_single() but wish to interrogate the | ||
325 | * buffer using the cpu, yet do not wish to teardown the PCI dma | ||
326 | * mapping, you must call this function before doing so. At the | ||
327 | * next point you give the PCI dma address back to the card, you | ||
328 | * must first the perform a dma_sync_for_device, and then the | ||
329 | * device again owns the buffer. | ||
330 | */ | ||
331 | #ifndef CONFIG_DMABOUNCE | ||
332 | static inline void | ||
333 | dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle, size_t size, | ||
334 | enum dma_data_direction dir) | ||
335 | { | ||
336 | if (!arch_is_coherent()) | ||
337 | dma_cache_maint((void *)dma_to_virt(dev, handle), size, dir); | ||
338 | } | ||
339 | |||
340 | static inline void | ||
341 | dma_sync_single_for_device(struct device *dev, dma_addr_t handle, size_t size, | ||
342 | enum dma_data_direction dir) | ||
343 | { | ||
344 | if (!arch_is_coherent()) | ||
345 | dma_cache_maint((void *)dma_to_virt(dev, handle), size, dir); | ||
346 | } | ||
347 | #else | ||
348 | extern void dma_sync_single_for_cpu(struct device*, dma_addr_t, size_t, enum dma_data_direction); | ||
349 | extern void dma_sync_single_for_device(struct device*, dma_addr_t, size_t, enum dma_data_direction); | ||
350 | #endif | ||
351 | |||
352 | |||
353 | /** | ||
354 | * dma_sync_sg_for_cpu | ||
355 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | ||
356 | * @sg: list of buffers | ||
357 | * @nents: number of buffers to map | ||
358 | * @dir: DMA transfer direction | ||
359 | * | ||
360 | * Make physical memory consistent for a set of streaming | ||
361 | * mode DMA translations after a transfer. | ||
362 | * | ||
363 | * The same as dma_sync_single_for_* but for a scatter-gather list, | ||
364 | * same rules and usage. | ||
365 | */ | ||
366 | #ifndef CONFIG_DMABOUNCE | ||
367 | static inline void | ||
368 | dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nents, | ||
369 | enum dma_data_direction dir) | ||
370 | { | ||
371 | int i; | ||
372 | |||
373 | for (i = 0; i < nents; i++, sg++) { | ||
374 | char *virt = sg_virt(sg); | ||
375 | if (!arch_is_coherent()) | ||
376 | dma_cache_maint(virt, sg->length, dir); | ||
377 | } | ||
378 | } | ||
379 | |||
380 | static inline void | ||
381 | dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nents, | ||
382 | enum dma_data_direction dir) | ||
383 | { | ||
384 | int i; | ||
385 | |||
386 | for (i = 0; i < nents; i++, sg++) { | ||
387 | char *virt = sg_virt(sg); | ||
388 | if (!arch_is_coherent()) | ||
389 | dma_cache_maint(virt, sg->length, dir); | ||
390 | } | ||
391 | } | ||
392 | #else | ||
393 | extern void dma_sync_sg_for_cpu(struct device*, struct scatterlist*, int, enum dma_data_direction); | ||
394 | extern void dma_sync_sg_for_device(struct device*, struct scatterlist*, int, enum dma_data_direction); | ||
395 | #endif | ||
396 | |||
397 | #ifdef CONFIG_DMABOUNCE | ||
398 | /* | ||
399 | * For SA-1111, IXP425, and ADI systems the dma-mapping functions are "magic" | ||
400 | * and utilize bounce buffers as needed to work around limited DMA windows. | ||
401 | * | ||
402 | * On the SA-1111, a bug limits DMA to only certain regions of RAM. | ||
403 | * On the IXP425, the PCI inbound window is 64MB (256MB total RAM) | ||
404 | * On some ADI engineering systems, PCI inbound window is 32MB (12MB total RAM) | ||
405 | * | ||
406 | * The following are helper functions used by the dmabounce subystem | ||
407 | * | ||
408 | */ | ||
409 | |||
410 | /** | ||
411 | * dmabounce_register_dev | ||
412 | * | ||
413 | * @dev: valid struct device pointer | ||
414 | * @small_buf_size: size of buffers to use with small buffer pool | ||
415 | * @large_buf_size: size of buffers to use with large buffer pool (can be 0) | ||
416 | * | ||
417 | * This function should be called by low-level platform code to register | ||
418 | * a device as requireing DMA buffer bouncing. The function will allocate | ||
419 | * appropriate DMA pools for the device. | ||
420 | * | ||
421 | */ | ||
422 | extern int dmabounce_register_dev(struct device *, unsigned long, unsigned long); | ||
423 | |||
424 | /** | ||
425 | * dmabounce_unregister_dev | ||
426 | * | ||
427 | * @dev: valid struct device pointer | ||
428 | * | ||
429 | * This function should be called by low-level platform code when device | ||
430 | * that was previously registered with dmabounce_register_dev is removed | ||
431 | * from the system. | ||
432 | * | ||
433 | */ | ||
434 | extern void dmabounce_unregister_dev(struct device *); | ||
435 | |||
436 | /** | ||
437 | * dma_needs_bounce | ||
438 | * | ||
439 | * @dev: valid struct device pointer | ||
440 | * @dma_handle: dma_handle of unbounced buffer | ||
441 | * @size: size of region being mapped | ||
442 | * | ||
443 | * Platforms that utilize the dmabounce mechanism must implement | ||
444 | * this function. | ||
445 | * | ||
446 | * The dmabounce routines call this function whenever a dma-mapping | ||
447 | * is requested to determine whether a given buffer needs to be bounced | ||
448 | * or not. The function must return 0 if the buffer is OK for | ||
449 | * DMA access and 1 if the buffer needs to be bounced. | ||
450 | * | ||
451 | */ | ||
452 | extern int dma_needs_bounce(struct device*, dma_addr_t, size_t); | ||
453 | #endif /* CONFIG_DMABOUNCE */ | ||
454 | |||
455 | #endif /* __KERNEL__ */ | ||
456 | #endif | ||
diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h new file mode 100644 index 000000000000..9f2c5305c260 --- /dev/null +++ b/arch/arm/include/asm/dma.h | |||
@@ -0,0 +1,143 @@ | |||
1 | #ifndef __ASM_ARM_DMA_H | ||
2 | #define __ASM_ARM_DMA_H | ||
3 | |||
4 | typedef unsigned int dmach_t; | ||
5 | |||
6 | #include <linux/spinlock.h> | ||
7 | #include <asm/system.h> | ||
8 | #include <asm/scatterlist.h> | ||
9 | #include <asm/arch/dma.h> | ||
10 | |||
11 | /* | ||
12 | * This is the maximum virtual address which can be DMA'd from. | ||
13 | */ | ||
14 | #ifndef MAX_DMA_ADDRESS | ||
15 | #define MAX_DMA_ADDRESS 0xffffffff | ||
16 | #endif | ||
17 | |||
18 | /* | ||
19 | * DMA modes | ||
20 | */ | ||
21 | typedef unsigned int dmamode_t; | ||
22 | |||
23 | #define DMA_MODE_MASK 3 | ||
24 | |||
25 | #define DMA_MODE_READ 0 | ||
26 | #define DMA_MODE_WRITE 1 | ||
27 | #define DMA_MODE_CASCADE 2 | ||
28 | #define DMA_AUTOINIT 4 | ||
29 | |||
30 | extern spinlock_t dma_spin_lock; | ||
31 | |||
32 | static inline unsigned long claim_dma_lock(void) | ||
33 | { | ||
34 | unsigned long flags; | ||
35 | spin_lock_irqsave(&dma_spin_lock, flags); | ||
36 | return flags; | ||
37 | } | ||
38 | |||
39 | static inline void release_dma_lock(unsigned long flags) | ||
40 | { | ||
41 | spin_unlock_irqrestore(&dma_spin_lock, flags); | ||
42 | } | ||
43 | |||
44 | /* Clear the 'DMA Pointer Flip Flop'. | ||
45 | * Write 0 for LSB/MSB, 1 for MSB/LSB access. | ||
46 | */ | ||
47 | #define clear_dma_ff(channel) | ||
48 | |||
49 | /* Set only the page register bits of the transfer address. | ||
50 | * | ||
51 | * NOTE: This is an architecture specific function, and should | ||
52 | * be hidden from the drivers | ||
53 | */ | ||
54 | extern void set_dma_page(dmach_t channel, char pagenr); | ||
55 | |||
56 | /* Request a DMA channel | ||
57 | * | ||
58 | * Some architectures may need to do allocate an interrupt | ||
59 | */ | ||
60 | extern int request_dma(dmach_t channel, const char * device_id); | ||
61 | |||
62 | /* Free a DMA channel | ||
63 | * | ||
64 | * Some architectures may need to do free an interrupt | ||
65 | */ | ||
66 | extern void free_dma(dmach_t channel); | ||
67 | |||
68 | /* Enable DMA for this channel | ||
69 | * | ||
70 | * On some architectures, this may have other side effects like | ||
71 | * enabling an interrupt and setting the DMA registers. | ||
72 | */ | ||
73 | extern void enable_dma(dmach_t channel); | ||
74 | |||
75 | /* Disable DMA for this channel | ||
76 | * | ||
77 | * On some architectures, this may have other side effects like | ||
78 | * disabling an interrupt or whatever. | ||
79 | */ | ||
80 | extern void disable_dma(dmach_t channel); | ||
81 | |||
82 | /* Test whether the specified channel has an active DMA transfer | ||
83 | */ | ||
84 | extern int dma_channel_active(dmach_t channel); | ||
85 | |||
86 | /* Set the DMA scatter gather list for this channel | ||
87 | * | ||
88 | * This should not be called if a DMA channel is enabled, | ||
89 | * especially since some DMA architectures don't update the | ||
90 | * DMA address immediately, but defer it to the enable_dma(). | ||
91 | */ | ||
92 | extern void set_dma_sg(dmach_t channel, struct scatterlist *sg, int nr_sg); | ||
93 | |||
94 | /* Set the DMA address for this channel | ||
95 | * | ||
96 | * This should not be called if a DMA channel is enabled, | ||
97 | * especially since some DMA architectures don't update the | ||
98 | * DMA address immediately, but defer it to the enable_dma(). | ||
99 | */ | ||
100 | extern void __set_dma_addr(dmach_t channel, void *addr); | ||
101 | #define set_dma_addr(channel, addr) \ | ||
102 | __set_dma_addr(channel, bus_to_virt(addr)) | ||
103 | |||
104 | /* Set the DMA byte count for this channel | ||
105 | * | ||
106 | * This should not be called if a DMA channel is enabled, | ||
107 | * especially since some DMA architectures don't update the | ||
108 | * DMA count immediately, but defer it to the enable_dma(). | ||
109 | */ | ||
110 | extern void set_dma_count(dmach_t channel, unsigned long count); | ||
111 | |||
112 | /* Set the transfer direction for this channel | ||
113 | * | ||
114 | * This should not be called if a DMA channel is enabled, | ||
115 | * especially since some DMA architectures don't update the | ||
116 | * DMA transfer direction immediately, but defer it to the | ||
117 | * enable_dma(). | ||
118 | */ | ||
119 | extern void set_dma_mode(dmach_t channel, dmamode_t mode); | ||
120 | |||
121 | /* Set the transfer speed for this channel | ||
122 | */ | ||
123 | extern void set_dma_speed(dmach_t channel, int cycle_ns); | ||
124 | |||
125 | /* Get DMA residue count. After a DMA transfer, this | ||
126 | * should return zero. Reading this while a DMA transfer is | ||
127 | * still in progress will return unpredictable results. | ||
128 | * If called before the channel has been used, it may return 1. | ||
129 | * Otherwise, it returns the number of _bytes_ left to transfer. | ||
130 | */ | ||
131 | extern int get_dma_residue(dmach_t channel); | ||
132 | |||
133 | #ifndef NO_DMA | ||
134 | #define NO_DMA 255 | ||
135 | #endif | ||
136 | |||
137 | #ifdef CONFIG_PCI | ||
138 | extern int isa_dma_bridge_buggy; | ||
139 | #else | ||
140 | #define isa_dma_bridge_buggy (0) | ||
141 | #endif | ||
142 | |||
143 | #endif /* _ARM_DMA_H */ | ||
diff --git a/arch/arm/include/asm/domain.h b/arch/arm/include/asm/domain.h new file mode 100644 index 000000000000..cc7ef4080711 --- /dev/null +++ b/arch/arm/include/asm/domain.h | |||
@@ -0,0 +1,78 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/domain.h | ||
3 | * | ||
4 | * Copyright (C) 1999 Russell King. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #ifndef __ASM_PROC_DOMAIN_H | ||
11 | #define __ASM_PROC_DOMAIN_H | ||
12 | |||
13 | /* | ||
14 | * Domain numbers | ||
15 | * | ||
16 | * DOMAIN_IO - domain 2 includes all IO only | ||
17 | * DOMAIN_USER - domain 1 includes all user memory only | ||
18 | * DOMAIN_KERNEL - domain 0 includes all kernel memory only | ||
19 | * | ||
20 | * The domain numbering depends on whether we support 36 physical | ||
21 | * address for I/O or not. Addresses above the 32 bit boundary can | ||
22 | * only be mapped using supersections and supersections can only | ||
23 | * be set for domain 0. We could just default to DOMAIN_IO as zero, | ||
24 | * but there may be systems with supersection support and no 36-bit | ||
25 | * addressing. In such cases, we want to map system memory with | ||
26 | * supersections to reduce TLB misses and footprint. | ||
27 | * | ||
28 | * 36-bit addressing and supersections are only available on | ||
29 | * CPUs based on ARMv6+ or the Intel XSC3 core. | ||
30 | */ | ||
31 | #ifndef CONFIG_IO_36 | ||
32 | #define DOMAIN_KERNEL 0 | ||
33 | #define DOMAIN_TABLE 0 | ||
34 | #define DOMAIN_USER 1 | ||
35 | #define DOMAIN_IO 2 | ||
36 | #else | ||
37 | #define DOMAIN_KERNEL 2 | ||
38 | #define DOMAIN_TABLE 2 | ||
39 | #define DOMAIN_USER 1 | ||
40 | #define DOMAIN_IO 0 | ||
41 | #endif | ||
42 | |||
43 | /* | ||
44 | * Domain types | ||
45 | */ | ||
46 | #define DOMAIN_NOACCESS 0 | ||
47 | #define DOMAIN_CLIENT 1 | ||
48 | #define DOMAIN_MANAGER 3 | ||
49 | |||
50 | #define domain_val(dom,type) ((type) << (2*(dom))) | ||
51 | |||
52 | #ifndef __ASSEMBLY__ | ||
53 | |||
54 | #ifdef CONFIG_MMU | ||
55 | #define set_domain(x) \ | ||
56 | do { \ | ||
57 | __asm__ __volatile__( \ | ||
58 | "mcr p15, 0, %0, c3, c0 @ set domain" \ | ||
59 | : : "r" (x)); \ | ||
60 | isb(); \ | ||
61 | } while (0) | ||
62 | |||
63 | #define modify_domain(dom,type) \ | ||
64 | do { \ | ||
65 | struct thread_info *thread = current_thread_info(); \ | ||
66 | unsigned int domain = thread->cpu_domain; \ | ||
67 | domain &= ~domain_val(dom, DOMAIN_MANAGER); \ | ||
68 | thread->cpu_domain = domain | domain_val(dom, type); \ | ||
69 | set_domain(thread->cpu_domain); \ | ||
70 | } while (0) | ||
71 | |||
72 | #else | ||
73 | #define set_domain(x) do { } while (0) | ||
74 | #define modify_domain(dom,type) do { } while (0) | ||
75 | #endif | ||
76 | |||
77 | #endif | ||
78 | #endif /* !__ASSEMBLY__ */ | ||
diff --git a/arch/arm/include/asm/ecard.h b/arch/arm/include/asm/ecard.h new file mode 100644 index 000000000000..29f2610efc70 --- /dev/null +++ b/arch/arm/include/asm/ecard.h | |||
@@ -0,0 +1,219 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/ecard.h | ||
3 | * | ||
4 | * definitions for expansion cards | ||
5 | * | ||
6 | * This is a new system as from Linux 1.2.3 | ||
7 | * | ||
8 | * Changelog: | ||
9 | * 11-12-1996 RMK Further minor improvements | ||
10 | * 12-09-1997 RMK Added interrupt enable/disable for card level | ||
11 | * | ||
12 | * Reference: Acorns Risc OS 3 Programmers Reference Manuals. | ||
13 | */ | ||
14 | |||
15 | #ifndef __ASM_ECARD_H | ||
16 | #define __ASM_ECARD_H | ||
17 | |||
18 | /* | ||
19 | * Currently understood cards (but not necessarily | ||
20 | * supported): | ||
21 | * Manufacturer Product ID | ||
22 | */ | ||
23 | #define MANU_ACORN 0x0000 | ||
24 | #define PROD_ACORN_SCSI 0x0002 | ||
25 | #define PROD_ACORN_ETHER1 0x0003 | ||
26 | #define PROD_ACORN_MFM 0x000b | ||
27 | |||
28 | #define MANU_ANT2 0x0011 | ||
29 | #define PROD_ANT_ETHER3 0x00a4 | ||
30 | |||
31 | #define MANU_ATOMWIDE 0x0017 | ||
32 | #define PROD_ATOMWIDE_3PSERIAL 0x0090 | ||
33 | |||
34 | #define MANU_IRLAM_INSTRUMENTS 0x001f | ||
35 | #define MANU_IRLAM_INSTRUMENTS_ETHERN 0x5678 | ||
36 | |||
37 | #define MANU_OAK 0x0021 | ||
38 | #define PROD_OAK_SCSI 0x0058 | ||
39 | |||
40 | #define MANU_MORLEY 0x002b | ||
41 | #define PROD_MORLEY_SCSI_UNCACHED 0x0067 | ||
42 | |||
43 | #define MANU_CUMANA 0x003a | ||
44 | #define PROD_CUMANA_SCSI_2 0x003a | ||
45 | #define PROD_CUMANA_SCSI_1 0x00a0 | ||
46 | |||
47 | #define MANU_ICS 0x003c | ||
48 | #define PROD_ICS_IDE 0x00ae | ||
49 | |||
50 | #define MANU_ICS2 0x003d | ||
51 | #define PROD_ICS2_IDE 0x00ae | ||
52 | |||
53 | #define MANU_SERPORT 0x003f | ||
54 | #define PROD_SERPORT_DSPORT 0x00b9 | ||
55 | |||
56 | #define MANU_ARXE 0x0041 | ||
57 | #define PROD_ARXE_SCSI 0x00be | ||
58 | |||
59 | #define MANU_I3 0x0046 | ||
60 | #define PROD_I3_ETHERLAN500 0x00d4 | ||
61 | #define PROD_I3_ETHERLAN600 0x00ec | ||
62 | #define PROD_I3_ETHERLAN600A 0x011e | ||
63 | |||
64 | #define MANU_ANT 0x0053 | ||
65 | #define PROD_ANT_ETHERM 0x00d8 | ||
66 | #define PROD_ANT_ETHERB 0x00e4 | ||
67 | |||
68 | #define MANU_ALSYSTEMS 0x005b | ||
69 | #define PROD_ALSYS_SCSIATAPI 0x0107 | ||
70 | |||
71 | #define MANU_MCS 0x0063 | ||
72 | #define PROD_MCS_CONNECT32 0x0125 | ||
73 | |||
74 | #define MANU_EESOX 0x0064 | ||
75 | #define PROD_EESOX_SCSI2 0x008c | ||
76 | |||
77 | #define MANU_YELLOWSTONE 0x0096 | ||
78 | #define PROD_YELLOWSTONE_RAPIDE32 0x0120 | ||
79 | |||
80 | #ifdef ECARD_C | ||
81 | #define CONST | ||
82 | #else | ||
83 | #define CONST const | ||
84 | #endif | ||
85 | |||
86 | #define MAX_ECARDS 9 | ||
87 | |||
88 | struct ecard_id { /* Card ID structure */ | ||
89 | unsigned short manufacturer; | ||
90 | unsigned short product; | ||
91 | void *data; | ||
92 | }; | ||
93 | |||
94 | struct in_ecid { /* Packed card ID information */ | ||
95 | unsigned short product; /* Product code */ | ||
96 | unsigned short manufacturer; /* Manufacturer code */ | ||
97 | unsigned char id:4; /* Simple ID */ | ||
98 | unsigned char cd:1; /* Chunk dir present */ | ||
99 | unsigned char is:1; /* Interrupt status pointers */ | ||
100 | unsigned char w:2; /* Width */ | ||
101 | unsigned char country; /* Country */ | ||
102 | unsigned char irqmask; /* IRQ mask */ | ||
103 | unsigned char fiqmask; /* FIQ mask */ | ||
104 | unsigned long irqoff; /* IRQ offset */ | ||
105 | unsigned long fiqoff; /* FIQ offset */ | ||
106 | }; | ||
107 | |||
108 | typedef struct expansion_card ecard_t; | ||
109 | typedef unsigned long *loader_t; | ||
110 | |||
111 | typedef struct expansion_card_ops { /* Card handler routines */ | ||
112 | void (*irqenable)(ecard_t *ec, int irqnr); | ||
113 | void (*irqdisable)(ecard_t *ec, int irqnr); | ||
114 | int (*irqpending)(ecard_t *ec); | ||
115 | void (*fiqenable)(ecard_t *ec, int fiqnr); | ||
116 | void (*fiqdisable)(ecard_t *ec, int fiqnr); | ||
117 | int (*fiqpending)(ecard_t *ec); | ||
118 | } expansioncard_ops_t; | ||
119 | |||
120 | #define ECARD_NUM_RESOURCES (6) | ||
121 | |||
122 | #define ECARD_RES_IOCSLOW (0) | ||
123 | #define ECARD_RES_IOCMEDIUM (1) | ||
124 | #define ECARD_RES_IOCFAST (2) | ||
125 | #define ECARD_RES_IOCSYNC (3) | ||
126 | #define ECARD_RES_MEMC (4) | ||
127 | #define ECARD_RES_EASI (5) | ||
128 | |||
129 | #define ecard_resource_start(ec,nr) ((ec)->resource[nr].start) | ||
130 | #define ecard_resource_end(ec,nr) ((ec)->resource[nr].end) | ||
131 | #define ecard_resource_len(ec,nr) ((ec)->resource[nr].end - \ | ||
132 | (ec)->resource[nr].start + 1) | ||
133 | #define ecard_resource_flags(ec,nr) ((ec)->resource[nr].flags) | ||
134 | |||
135 | /* | ||
136 | * This contains all the info needed on an expansion card | ||
137 | */ | ||
138 | struct expansion_card { | ||
139 | struct expansion_card *next; | ||
140 | |||
141 | struct device dev; | ||
142 | struct resource resource[ECARD_NUM_RESOURCES]; | ||
143 | |||
144 | /* Public data */ | ||
145 | void __iomem *irqaddr; /* address of IRQ register */ | ||
146 | void __iomem *fiqaddr; /* address of FIQ register */ | ||
147 | unsigned char irqmask; /* IRQ mask */ | ||
148 | unsigned char fiqmask; /* FIQ mask */ | ||
149 | unsigned char claimed; /* Card claimed? */ | ||
150 | unsigned char easi; /* EASI card */ | ||
151 | |||
152 | void *irq_data; /* Data for use for IRQ by card */ | ||
153 | void *fiq_data; /* Data for use for FIQ by card */ | ||
154 | const expansioncard_ops_t *ops; /* Enable/Disable Ops for card */ | ||
155 | |||
156 | CONST unsigned int slot_no; /* Slot number */ | ||
157 | CONST unsigned int dma; /* DMA number (for request_dma) */ | ||
158 | CONST unsigned int irq; /* IRQ number (for request_irq) */ | ||
159 | CONST unsigned int fiq; /* FIQ number (for request_irq) */ | ||
160 | CONST struct in_ecid cid; /* Card Identification */ | ||
161 | |||
162 | /* Private internal data */ | ||
163 | const char *card_desc; /* Card description */ | ||
164 | CONST unsigned int podaddr; /* Base Linux address for card */ | ||
165 | CONST loader_t loader; /* loader program */ | ||
166 | u64 dma_mask; | ||
167 | }; | ||
168 | |||
169 | void ecard_setirq(struct expansion_card *ec, const struct expansion_card_ops *ops, void *irq_data); | ||
170 | |||
171 | struct in_chunk_dir { | ||
172 | unsigned int start_offset; | ||
173 | union { | ||
174 | unsigned char string[256]; | ||
175 | unsigned char data[1]; | ||
176 | } d; | ||
177 | }; | ||
178 | |||
179 | /* | ||
180 | * Read a chunk from an expansion card | ||
181 | * cd : where to put read data | ||
182 | * ec : expansion card info struct | ||
183 | * id : id number to find | ||
184 | * num: (n+1)'th id to find. | ||
185 | */ | ||
186 | extern int ecard_readchunk (struct in_chunk_dir *cd, struct expansion_card *ec, int id, int num); | ||
187 | |||
188 | /* | ||
189 | * Request and release ecard resources | ||
190 | */ | ||
191 | extern int ecard_request_resources(struct expansion_card *ec); | ||
192 | extern void ecard_release_resources(struct expansion_card *ec); | ||
193 | |||
194 | void __iomem *ecardm_iomap(struct expansion_card *ec, unsigned int res, | ||
195 | unsigned long offset, unsigned long maxsize); | ||
196 | #define ecardm_iounmap(__ec, __addr) devm_iounmap(&(__ec)->dev, __addr) | ||
197 | |||
198 | extern struct bus_type ecard_bus_type; | ||
199 | |||
200 | #define ECARD_DEV(_d) container_of((_d), struct expansion_card, dev) | ||
201 | |||
202 | struct ecard_driver { | ||
203 | int (*probe)(struct expansion_card *, const struct ecard_id *id); | ||
204 | void (*remove)(struct expansion_card *); | ||
205 | void (*shutdown)(struct expansion_card *); | ||
206 | const struct ecard_id *id_table; | ||
207 | unsigned int id; | ||
208 | struct device_driver drv; | ||
209 | }; | ||
210 | |||
211 | #define ECARD_DRV(_d) container_of((_d), struct ecard_driver, drv) | ||
212 | |||
213 | #define ecard_set_drvdata(ec,data) dev_set_drvdata(&(ec)->dev, (data)) | ||
214 | #define ecard_get_drvdata(ec) dev_get_drvdata(&(ec)->dev) | ||
215 | |||
216 | int ecard_register_driver(struct ecard_driver *); | ||
217 | void ecard_remove_driver(struct ecard_driver *); | ||
218 | |||
219 | #endif | ||
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h new file mode 100644 index 000000000000..4ca751627489 --- /dev/null +++ b/arch/arm/include/asm/elf.h | |||
@@ -0,0 +1,116 @@ | |||
1 | #ifndef __ASMARM_ELF_H | ||
2 | #define __ASMARM_ELF_H | ||
3 | |||
4 | #include <asm/hwcap.h> | ||
5 | |||
6 | #ifndef __ASSEMBLY__ | ||
7 | /* | ||
8 | * ELF register definitions.. | ||
9 | */ | ||
10 | #include <asm/ptrace.h> | ||
11 | #include <asm/user.h> | ||
12 | |||
13 | typedef unsigned long elf_greg_t; | ||
14 | typedef unsigned long elf_freg_t[3]; | ||
15 | |||
16 | #define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t)) | ||
17 | typedef elf_greg_t elf_gregset_t[ELF_NGREG]; | ||
18 | |||
19 | typedef struct user_fp elf_fpregset_t; | ||
20 | #endif | ||
21 | |||
22 | #define EM_ARM 40 | ||
23 | #define EF_ARM_APCS26 0x08 | ||
24 | #define EF_ARM_SOFT_FLOAT 0x200 | ||
25 | #define EF_ARM_EABI_MASK 0xFF000000 | ||
26 | |||
27 | #define R_ARM_NONE 0 | ||
28 | #define R_ARM_PC24 1 | ||
29 | #define R_ARM_ABS32 2 | ||
30 | #define R_ARM_CALL 28 | ||
31 | #define R_ARM_JUMP24 29 | ||
32 | |||
33 | /* | ||
34 | * These are used to set parameters in the core dumps. | ||
35 | */ | ||
36 | #define ELF_CLASS ELFCLASS32 | ||
37 | #ifdef __ARMEB__ | ||
38 | #define ELF_DATA ELFDATA2MSB | ||
39 | #else | ||
40 | #define ELF_DATA ELFDATA2LSB | ||
41 | #endif | ||
42 | #define ELF_ARCH EM_ARM | ||
43 | |||
44 | #ifndef __ASSEMBLY__ | ||
45 | /* | ||
46 | * This yields a string that ld.so will use to load implementation | ||
47 | * specific libraries for optimization. This is more specific in | ||
48 | * intent than poking at uname or /proc/cpuinfo. | ||
49 | * | ||
50 | * For now we just provide a fairly general string that describes the | ||
51 | * processor family. This could be made more specific later if someone | ||
52 | * implemented optimisations that require it. 26-bit CPUs give you | ||
53 | * "v1l" for ARM2 (no SWP) and "v2l" for anything else (ARM1 isn't | ||
54 | * supported). 32-bit CPUs give you "v3[lb]" for anything based on an | ||
55 | * ARM6 or ARM7 core and "armv4[lb]" for anything based on a StrongARM-1 | ||
56 | * core. | ||
57 | */ | ||
58 | #define ELF_PLATFORM_SIZE 8 | ||
59 | #define ELF_PLATFORM (elf_platform) | ||
60 | |||
61 | extern char elf_platform[]; | ||
62 | #endif | ||
63 | |||
64 | /* | ||
65 | * This is used to ensure we don't load something for the wrong architecture. | ||
66 | */ | ||
67 | #define elf_check_arch(x) ((x)->e_machine == EM_ARM && ELF_PROC_OK(x)) | ||
68 | |||
69 | /* | ||
70 | * 32-bit code is always OK. Some cpus can do 26-bit, some can't. | ||
71 | */ | ||
72 | #define ELF_PROC_OK(x) (ELF_THUMB_OK(x) && ELF_26BIT_OK(x)) | ||
73 | |||
74 | #define ELF_THUMB_OK(x) \ | ||
75 | ((elf_hwcap & HWCAP_THUMB && ((x)->e_entry & 1) == 1) || \ | ||
76 | ((x)->e_entry & 3) == 0) | ||
77 | |||
78 | #define ELF_26BIT_OK(x) \ | ||
79 | ((elf_hwcap & HWCAP_26BIT && (x)->e_flags & EF_ARM_APCS26) || \ | ||
80 | ((x)->e_flags & EF_ARM_APCS26) == 0) | ||
81 | |||
82 | #define USE_ELF_CORE_DUMP | ||
83 | #define ELF_EXEC_PAGESIZE 4096 | ||
84 | |||
85 | /* This is the location that an ET_DYN program is loaded if exec'ed. Typical | ||
86 | use of this is to invoke "./ld.so someprog" to test out a new version of | ||
87 | the loader. We need to make sure that it is out of the way of the program | ||
88 | that it will "exec", and that there is sufficient room for the brk. */ | ||
89 | |||
90 | #define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3) | ||
91 | |||
92 | /* When the program starts, a1 contains a pointer to a function to be | ||
93 | registered with atexit, as per the SVR4 ABI. A value of 0 means we | ||
94 | have no such handler. */ | ||
95 | #define ELF_PLAT_INIT(_r, load_addr) (_r)->ARM_r0 = 0 | ||
96 | |||
97 | /* | ||
98 | * Since the FPA coprocessor uses CP1 and CP2, and iWMMXt uses CP0 | ||
99 | * and CP1, we only enable access to the iWMMXt coprocessor if the | ||
100 | * binary is EABI or softfloat (and thus, guaranteed not to use | ||
101 | * FPA instructions.) | ||
102 | */ | ||
103 | #define SET_PERSONALITY(ex, ibcs2) \ | ||
104 | do { \ | ||
105 | if ((ex).e_flags & EF_ARM_APCS26) { \ | ||
106 | set_personality(PER_LINUX); \ | ||
107 | } else { \ | ||
108 | set_personality(PER_LINUX_32BIT); \ | ||
109 | if (elf_hwcap & HWCAP_IWMMXT && (ex).e_flags & (EF_ARM_EABI_MASK | EF_ARM_SOFT_FLOAT)) \ | ||
110 | set_thread_flag(TIF_USING_IWMMXT); \ | ||
111 | else \ | ||
112 | clear_thread_flag(TIF_USING_IWMMXT); \ | ||
113 | } \ | ||
114 | } while (0) | ||
115 | |||
116 | #endif | ||
diff --git a/arch/arm/include/asm/emergency-restart.h b/arch/arm/include/asm/emergency-restart.h new file mode 100644 index 000000000000..108d8c48e42e --- /dev/null +++ b/arch/arm/include/asm/emergency-restart.h | |||
@@ -0,0 +1,6 @@ | |||
1 | #ifndef _ASM_EMERGENCY_RESTART_H | ||
2 | #define _ASM_EMERGENCY_RESTART_H | ||
3 | |||
4 | #include <asm-generic/emergency-restart.h> | ||
5 | |||
6 | #endif /* _ASM_EMERGENCY_RESTART_H */ | ||
diff --git a/arch/arm/include/asm/errno.h b/arch/arm/include/asm/errno.h new file mode 100644 index 000000000000..6e60f0612bb6 --- /dev/null +++ b/arch/arm/include/asm/errno.h | |||
@@ -0,0 +1,6 @@ | |||
1 | #ifndef _ARM_ERRNO_H | ||
2 | #define _ARM_ERRNO_H | ||
3 | |||
4 | #include <asm-generic/errno.h> | ||
5 | |||
6 | #endif | ||
diff --git a/arch/arm/include/asm/fb.h b/arch/arm/include/asm/fb.h new file mode 100644 index 000000000000..d92e99cd8c8a --- /dev/null +++ b/arch/arm/include/asm/fb.h | |||
@@ -0,0 +1,19 @@ | |||
1 | #ifndef _ASM_FB_H_ | ||
2 | #define _ASM_FB_H_ | ||
3 | |||
4 | #include <linux/fb.h> | ||
5 | #include <linux/fs.h> | ||
6 | #include <asm/page.h> | ||
7 | |||
8 | static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma, | ||
9 | unsigned long off) | ||
10 | { | ||
11 | vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); | ||
12 | } | ||
13 | |||
14 | static inline int fb_is_primary_device(struct fb_info *info) | ||
15 | { | ||
16 | return 0; | ||
17 | } | ||
18 | |||
19 | #endif /* _ASM_FB_H_ */ | ||
diff --git a/arch/arm/include/asm/fcntl.h b/arch/arm/include/asm/fcntl.h new file mode 100644 index 000000000000..a80b6607b2ef --- /dev/null +++ b/arch/arm/include/asm/fcntl.h | |||
@@ -0,0 +1,11 @@ | |||
1 | #ifndef _ARM_FCNTL_H | ||
2 | #define _ARM_FCNTL_H | ||
3 | |||
4 | #define O_DIRECTORY 040000 /* must be a directory */ | ||
5 | #define O_NOFOLLOW 0100000 /* don't follow links */ | ||
6 | #define O_DIRECT 0200000 /* direct disk access hint - currently ignored */ | ||
7 | #define O_LARGEFILE 0400000 | ||
8 | |||
9 | #include <asm-generic/fcntl.h> | ||
10 | |||
11 | #endif | ||
diff --git a/arch/arm/include/asm/fiq.h b/arch/arm/include/asm/fiq.h new file mode 100644 index 000000000000..2242ce22ec6c --- /dev/null +++ b/arch/arm/include/asm/fiq.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/fiq.h | ||
3 | * | ||
4 | * Support for FIQ on ARM architectures. | ||
5 | * Written by Philip Blundell <philb@gnu.org>, 1998 | ||
6 | * Re-written by Russell King | ||
7 | */ | ||
8 | |||
9 | #ifndef __ASM_FIQ_H | ||
10 | #define __ASM_FIQ_H | ||
11 | |||
12 | #include <asm/ptrace.h> | ||
13 | |||
14 | struct fiq_handler { | ||
15 | struct fiq_handler *next; | ||
16 | /* Name | ||
17 | */ | ||
18 | const char *name; | ||
19 | /* Called to ask driver to relinquish/ | ||
20 | * reacquire FIQ | ||
21 | * return zero to accept, or -<errno> | ||
22 | */ | ||
23 | int (*fiq_op)(void *, int relinquish); | ||
24 | /* data for the relinquish/reacquire functions | ||
25 | */ | ||
26 | void *dev_id; | ||
27 | }; | ||
28 | |||
29 | extern int claim_fiq(struct fiq_handler *f); | ||
30 | extern void release_fiq(struct fiq_handler *f); | ||
31 | extern void set_fiq_handler(void *start, unsigned int length); | ||
32 | extern void set_fiq_regs(struct pt_regs *regs); | ||
33 | extern void get_fiq_regs(struct pt_regs *regs); | ||
34 | extern void enable_fiq(int fiq); | ||
35 | extern void disable_fiq(int fiq); | ||
36 | |||
37 | #endif | ||
diff --git a/arch/arm/include/asm/flat.h b/arch/arm/include/asm/flat.h new file mode 100644 index 000000000000..1d77e51907f6 --- /dev/null +++ b/arch/arm/include/asm/flat.h | |||
@@ -0,0 +1,19 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/flat.h -- uClinux flat-format executables | ||
3 | */ | ||
4 | |||
5 | #ifndef __ARM_FLAT_H__ | ||
6 | #define __ARM_FLAT_H__ | ||
7 | |||
8 | /* An odd number of words will be pushed after this alignment, so | ||
9 | deliberately misalign the value. */ | ||
10 | #define flat_stack_align(sp) sp = (void *)(((unsigned long)(sp) - 4) | 4) | ||
11 | #define flat_argvp_envp_on_stack() 1 | ||
12 | #define flat_old_ram_flag(flags) (flags) | ||
13 | #define flat_reloc_valid(reloc, size) ((reloc) <= (size)) | ||
14 | #define flat_get_addr_from_rp(rp, relval, flags, persistent) get_unaligned(rp) | ||
15 | #define flat_put_addr_at_rp(rp, val, relval) put_unaligned(val,rp) | ||
16 | #define flat_get_relocate_addr(rel) (rel) | ||
17 | #define flat_set_persistent(relval, p) 0 | ||
18 | |||
19 | #endif /* __ARM_FLAT_H__ */ | ||
diff --git a/arch/arm/include/asm/floppy.h b/arch/arm/include/asm/floppy.h new file mode 100644 index 000000000000..dce20c25ab10 --- /dev/null +++ b/arch/arm/include/asm/floppy.h | |||
@@ -0,0 +1,148 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/floppy.h | ||
3 | * | ||
4 | * Copyright (C) 1996-2000 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * Note that we don't touch FLOPPY_DMA nor FLOPPY_IRQ here | ||
11 | */ | ||
12 | #ifndef __ASM_ARM_FLOPPY_H | ||
13 | #define __ASM_ARM_FLOPPY_H | ||
14 | #if 0 | ||
15 | #include <asm/arch/floppy.h> | ||
16 | #endif | ||
17 | |||
18 | #define fd_outb(val,port) \ | ||
19 | do { \ | ||
20 | if ((port) == FD_DOR) \ | ||
21 | fd_setdor((val)); \ | ||
22 | else \ | ||
23 | outb((val),(port)); \ | ||
24 | } while(0) | ||
25 | |||
26 | #define fd_inb(port) inb((port)) | ||
27 | #define fd_request_irq() request_irq(IRQ_FLOPPYDISK,floppy_interrupt,\ | ||
28 | IRQF_DISABLED,"floppy",NULL) | ||
29 | #define fd_free_irq() free_irq(IRQ_FLOPPYDISK,NULL) | ||
30 | #define fd_disable_irq() disable_irq(IRQ_FLOPPYDISK) | ||
31 | #define fd_enable_irq() enable_irq(IRQ_FLOPPYDISK) | ||
32 | |||
33 | static inline int fd_dma_setup(void *data, unsigned int length, | ||
34 | unsigned int mode, unsigned long addr) | ||
35 | { | ||
36 | set_dma_mode(DMA_FLOPPY, mode); | ||
37 | __set_dma_addr(DMA_FLOPPY, data); | ||
38 | set_dma_count(DMA_FLOPPY, length); | ||
39 | virtual_dma_port = addr; | ||
40 | enable_dma(DMA_FLOPPY); | ||
41 | return 0; | ||
42 | } | ||
43 | #define fd_dma_setup fd_dma_setup | ||
44 | |||
45 | #define fd_request_dma() request_dma(DMA_FLOPPY,"floppy") | ||
46 | #define fd_free_dma() free_dma(DMA_FLOPPY) | ||
47 | #define fd_disable_dma() disable_dma(DMA_FLOPPY) | ||
48 | |||
49 | /* need to clean up dma.h */ | ||
50 | #define DMA_FLOPPYDISK DMA_FLOPPY | ||
51 | |||
52 | /* Floppy_selects is the list of DOR's to select drive fd | ||
53 | * | ||
54 | * On initialisation, the floppy list is scanned, and the drives allocated | ||
55 | * in the order that they are found. This is done by seeking the drive | ||
56 | * to a non-zero track, and then restoring it to track 0. If an error occurs, | ||
57 | * then there is no floppy drive present. [to be put back in again] | ||
58 | */ | ||
59 | static unsigned char floppy_selects[2][4] = | ||
60 | { | ||
61 | { 0x10, 0x21, 0x23, 0x33 }, | ||
62 | { 0x10, 0x21, 0x23, 0x33 } | ||
63 | }; | ||
64 | |||
65 | #define fd_setdor(dor) \ | ||
66 | do { \ | ||
67 | int new_dor = (dor); \ | ||
68 | if (new_dor & 0xf0) \ | ||
69 | new_dor = (new_dor & 0x0c) | floppy_selects[fdc][new_dor & 3]; \ | ||
70 | else \ | ||
71 | new_dor &= 0x0c; \ | ||
72 | outb(new_dor, FD_DOR); \ | ||
73 | } while (0) | ||
74 | |||
75 | /* | ||
76 | * Someday, we'll automatically detect which drives are present... | ||
77 | */ | ||
78 | static inline void fd_scandrives (void) | ||
79 | { | ||
80 | #if 0 | ||
81 | int floppy, drive_count; | ||
82 | |||
83 | fd_disable_irq(); | ||
84 | raw_cmd = &default_raw_cmd; | ||
85 | raw_cmd->flags = FD_RAW_SPIN | FD_RAW_NEED_SEEK; | ||
86 | raw_cmd->track = 0; | ||
87 | raw_cmd->rate = ?; | ||
88 | drive_count = 0; | ||
89 | for (floppy = 0; floppy < 4; floppy ++) { | ||
90 | current_drive = drive_count; | ||
91 | /* | ||
92 | * Turn on floppy motor | ||
93 | */ | ||
94 | if (start_motor(redo_fd_request)) | ||
95 | continue; | ||
96 | /* | ||
97 | * Set up FDC | ||
98 | */ | ||
99 | fdc_specify(); | ||
100 | /* | ||
101 | * Tell FDC to recalibrate | ||
102 | */ | ||
103 | output_byte(FD_RECALIBRATE); | ||
104 | LAST_OUT(UNIT(floppy)); | ||
105 | /* wait for command to complete */ | ||
106 | if (!successful) { | ||
107 | int i; | ||
108 | for (i = drive_count; i < 3; i--) | ||
109 | floppy_selects[fdc][i] = floppy_selects[fdc][i + 1]; | ||
110 | floppy_selects[fdc][3] = 0; | ||
111 | floppy -= 1; | ||
112 | } else | ||
113 | drive_count++; | ||
114 | } | ||
115 | #else | ||
116 | floppy_selects[0][0] = 0x10; | ||
117 | floppy_selects[0][1] = 0x21; | ||
118 | floppy_selects[0][2] = 0x23; | ||
119 | floppy_selects[0][3] = 0x33; | ||
120 | #endif | ||
121 | } | ||
122 | |||
123 | #define FDC1 (0x3f0) | ||
124 | |||
125 | #define FLOPPY0_TYPE 4 | ||
126 | #define FLOPPY1_TYPE 4 | ||
127 | |||
128 | #define N_FDC 1 | ||
129 | #define N_DRIVE 4 | ||
130 | |||
131 | #define CROSS_64KB(a,s) (0) | ||
132 | |||
133 | /* | ||
134 | * This allows people to reverse the order of | ||
135 | * fd0 and fd1, in case their hardware is | ||
136 | * strangely connected (as some RiscPCs | ||
137 | * and A5000s seem to be). | ||
138 | */ | ||
139 | static void driveswap(int *ints, int dummy, int dummy2) | ||
140 | { | ||
141 | floppy_selects[0][0] ^= floppy_selects[0][1]; | ||
142 | floppy_selects[0][1] ^= floppy_selects[0][0]; | ||
143 | floppy_selects[0][0] ^= floppy_selects[0][1]; | ||
144 | } | ||
145 | |||
146 | #define EXTRA_FLOPPY_PARAMS ,{ "driveswap", &driveswap, NULL, 0, 0 } | ||
147 | |||
148 | #endif | ||
diff --git a/arch/arm/include/asm/fpstate.h b/arch/arm/include/asm/fpstate.h new file mode 100644 index 000000000000..ee5e03efc1bb --- /dev/null +++ b/arch/arm/include/asm/fpstate.h | |||
@@ -0,0 +1,93 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/fpstate.h | ||
3 | * | ||
4 | * Copyright (C) 1995 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_ARM_FPSTATE_H | ||
12 | #define __ASM_ARM_FPSTATE_H | ||
13 | |||
14 | |||
15 | #ifndef __ASSEMBLY__ | ||
16 | |||
17 | /* | ||
18 | * VFP storage area has: | ||
19 | * - FPEXC, FPSCR, FPINST and FPINST2. | ||
20 | * - 16 or 32 double precision data registers | ||
21 | * - an implementation-dependant word of state for FLDMX/FSTMX (pre-ARMv6) | ||
22 | * | ||
23 | * FPEXC will always be non-zero once the VFP has been used in this process. | ||
24 | */ | ||
25 | |||
26 | struct vfp_hard_struct { | ||
27 | #ifdef CONFIG_VFPv3 | ||
28 | __u64 fpregs[32]; | ||
29 | #else | ||
30 | __u64 fpregs[16]; | ||
31 | #endif | ||
32 | #if __LINUX_ARM_ARCH__ < 6 | ||
33 | __u32 fpmx_state; | ||
34 | #endif | ||
35 | __u32 fpexc; | ||
36 | __u32 fpscr; | ||
37 | /* | ||
38 | * VFP implementation specific state | ||
39 | */ | ||
40 | __u32 fpinst; | ||
41 | __u32 fpinst2; | ||
42 | |||
43 | #ifdef CONFIG_SMP | ||
44 | __u32 cpu; | ||
45 | #endif | ||
46 | }; | ||
47 | |||
48 | union vfp_state { | ||
49 | struct vfp_hard_struct hard; | ||
50 | }; | ||
51 | |||
52 | extern void vfp_flush_thread(union vfp_state *); | ||
53 | extern void vfp_release_thread(union vfp_state *); | ||
54 | |||
55 | #define FP_HARD_SIZE 35 | ||
56 | |||
57 | struct fp_hard_struct { | ||
58 | unsigned int save[FP_HARD_SIZE]; /* as yet undefined */ | ||
59 | }; | ||
60 | |||
61 | #define FP_SOFT_SIZE 35 | ||
62 | |||
63 | struct fp_soft_struct { | ||
64 | unsigned int save[FP_SOFT_SIZE]; /* undefined information */ | ||
65 | }; | ||
66 | |||
67 | #define IWMMXT_SIZE 0x98 | ||
68 | |||
69 | struct iwmmxt_struct { | ||
70 | unsigned int save[IWMMXT_SIZE / sizeof(unsigned int)]; | ||
71 | }; | ||
72 | |||
73 | union fp_state { | ||
74 | struct fp_hard_struct hard; | ||
75 | struct fp_soft_struct soft; | ||
76 | #ifdef CONFIG_IWMMXT | ||
77 | struct iwmmxt_struct iwmmxt; | ||
78 | #endif | ||
79 | }; | ||
80 | |||
81 | #define FP_SIZE (sizeof(union fp_state) / sizeof(int)) | ||
82 | |||
83 | struct crunch_state { | ||
84 | unsigned int mvdx[16][2]; | ||
85 | unsigned int mvax[4][3]; | ||
86 | unsigned int dspsc[2]; | ||
87 | }; | ||
88 | |||
89 | #define CRUNCH_SIZE sizeof(struct crunch_state) | ||
90 | |||
91 | #endif | ||
92 | |||
93 | #endif | ||
diff --git a/arch/arm/include/asm/ftrace.h b/arch/arm/include/asm/ftrace.h new file mode 100644 index 000000000000..584ef9a8e5a5 --- /dev/null +++ b/arch/arm/include/asm/ftrace.h | |||
@@ -0,0 +1,14 @@ | |||
1 | #ifndef _ASM_ARM_FTRACE | ||
2 | #define _ASM_ARM_FTRACE | ||
3 | |||
4 | #ifdef CONFIG_FTRACE | ||
5 | #define MCOUNT_ADDR ((long)(mcount)) | ||
6 | #define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */ | ||
7 | |||
8 | #ifndef __ASSEMBLY__ | ||
9 | extern void mcount(void); | ||
10 | #endif | ||
11 | |||
12 | #endif | ||
13 | |||
14 | #endif /* _ASM_ARM_FTRACE */ | ||
diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h new file mode 100644 index 000000000000..6a332a9f099c --- /dev/null +++ b/arch/arm/include/asm/futex.h | |||
@@ -0,0 +1,6 @@ | |||
1 | #ifndef _ASM_FUTEX_H | ||
2 | #define _ASM_FUTEX_H | ||
3 | |||
4 | #include <asm-generic/futex.h> | ||
5 | |||
6 | #endif | ||
diff --git a/arch/arm/include/asm/glue.h b/arch/arm/include/asm/glue.h new file mode 100644 index 000000000000..a0e39d5d00c9 --- /dev/null +++ b/arch/arm/include/asm/glue.h | |||
@@ -0,0 +1,149 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/glue.h | ||
3 | * | ||
4 | * Copyright (C) 1997-1999 Russell King | ||
5 | * Copyright (C) 2000-2002 Deep Blue Solutions Ltd. | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | * | ||
11 | * This file provides the glue to stick the processor-specific bits | ||
12 | * into the kernel in an efficient manner. The idea is to use branches | ||
13 | * when we're only targetting one class of TLB, or indirect calls | ||
14 | * when we're targetting multiple classes of TLBs. | ||
15 | */ | ||
16 | #ifdef __KERNEL__ | ||
17 | |||
18 | |||
19 | #ifdef __STDC__ | ||
20 | #define ____glue(name,fn) name##fn | ||
21 | #else | ||
22 | #define ____glue(name,fn) name/**/fn | ||
23 | #endif | ||
24 | #define __glue(name,fn) ____glue(name,fn) | ||
25 | |||
26 | |||
27 | |||
28 | /* | ||
29 | * Data Abort Model | ||
30 | * ================ | ||
31 | * | ||
32 | * We have the following to choose from: | ||
33 | * arm6 - ARM6 style | ||
34 | * arm7 - ARM7 style | ||
35 | * v4_early - ARMv4 without Thumb early abort handler | ||
36 | * v4t_late - ARMv4 with Thumb late abort handler | ||
37 | * v4t_early - ARMv4 with Thumb early abort handler | ||
38 | * v5tej_early - ARMv5 with Thumb and Java early abort handler | ||
39 | * xscale - ARMv5 with Thumb with Xscale extensions | ||
40 | * v6_early - ARMv6 generic early abort handler | ||
41 | * v7_early - ARMv7 generic early abort handler | ||
42 | */ | ||
43 | #undef CPU_DABORT_HANDLER | ||
44 | #undef MULTI_DABORT | ||
45 | |||
46 | #if defined(CONFIG_CPU_ARM610) | ||
47 | # ifdef CPU_DABORT_HANDLER | ||
48 | # define MULTI_DABORT 1 | ||
49 | # else | ||
50 | # define CPU_DABORT_HANDLER cpu_arm6_data_abort | ||
51 | # endif | ||
52 | #endif | ||
53 | |||
54 | #if defined(CONFIG_CPU_ARM710) | ||
55 | # ifdef CPU_DABORT_HANDLER | ||
56 | # define MULTI_DABORT 1 | ||
57 | # else | ||
58 | # define CPU_DABORT_HANDLER cpu_arm7_data_abort | ||
59 | # endif | ||
60 | #endif | ||
61 | |||
62 | #ifdef CONFIG_CPU_ABRT_LV4T | ||
63 | # ifdef CPU_DABORT_HANDLER | ||
64 | # define MULTI_DABORT 1 | ||
65 | # else | ||
66 | # define CPU_DABORT_HANDLER v4t_late_abort | ||
67 | # endif | ||
68 | #endif | ||
69 | |||
70 | #ifdef CONFIG_CPU_ABRT_EV4 | ||
71 | # ifdef CPU_DABORT_HANDLER | ||
72 | # define MULTI_DABORT 1 | ||
73 | # else | ||
74 | # define CPU_DABORT_HANDLER v4_early_abort | ||
75 | # endif | ||
76 | #endif | ||
77 | |||
78 | #ifdef CONFIG_CPU_ABRT_EV4T | ||
79 | # ifdef CPU_DABORT_HANDLER | ||
80 | # define MULTI_DABORT 1 | ||
81 | # else | ||
82 | # define CPU_DABORT_HANDLER v4t_early_abort | ||
83 | # endif | ||
84 | #endif | ||
85 | |||
86 | #ifdef CONFIG_CPU_ABRT_EV5TJ | ||
87 | # ifdef CPU_DABORT_HANDLER | ||
88 | # define MULTI_DABORT 1 | ||
89 | # else | ||
90 | # define CPU_DABORT_HANDLER v5tj_early_abort | ||
91 | # endif | ||
92 | #endif | ||
93 | |||
94 | #ifdef CONFIG_CPU_ABRT_EV5T | ||
95 | # ifdef CPU_DABORT_HANDLER | ||
96 | # define MULTI_DABORT 1 | ||
97 | # else | ||
98 | # define CPU_DABORT_HANDLER v5t_early_abort | ||
99 | # endif | ||
100 | #endif | ||
101 | |||
102 | #ifdef CONFIG_CPU_ABRT_EV6 | ||
103 | # ifdef CPU_DABORT_HANDLER | ||
104 | # define MULTI_DABORT 1 | ||
105 | # else | ||
106 | # define CPU_DABORT_HANDLER v6_early_abort | ||
107 | # endif | ||
108 | #endif | ||
109 | |||
110 | #ifdef CONFIG_CPU_ABRT_EV7 | ||
111 | # ifdef CPU_DABORT_HANDLER | ||
112 | # define MULTI_DABORT 1 | ||
113 | # else | ||
114 | # define CPU_DABORT_HANDLER v7_early_abort | ||
115 | # endif | ||
116 | #endif | ||
117 | |||
118 | #ifndef CPU_DABORT_HANDLER | ||
119 | #error Unknown data abort handler type | ||
120 | #endif | ||
121 | |||
122 | /* | ||
123 | * Prefetch abort handler. If the CPU has an IFAR use that, otherwise | ||
124 | * use the address of the aborted instruction | ||
125 | */ | ||
126 | #undef CPU_PABORT_HANDLER | ||
127 | #undef MULTI_PABORT | ||
128 | |||
129 | #ifdef CONFIG_CPU_PABRT_IFAR | ||
130 | # ifdef CPU_PABORT_HANDLER | ||
131 | # define MULTI_PABORT 1 | ||
132 | # else | ||
133 | # define CPU_PABORT_HANDLER(reg, insn) mrc p15, 0, reg, cr6, cr0, 2 | ||
134 | # endif | ||
135 | #endif | ||
136 | |||
137 | #ifdef CONFIG_CPU_PABRT_NOIFAR | ||
138 | # ifdef CPU_PABORT_HANDLER | ||
139 | # define MULTI_PABORT 1 | ||
140 | # else | ||
141 | # define CPU_PABORT_HANDLER(reg, insn) mov reg, insn | ||
142 | # endif | ||
143 | #endif | ||
144 | |||
145 | #ifndef CPU_PABORT_HANDLER | ||
146 | #error Unknown prefetch abort handler type | ||
147 | #endif | ||
148 | |||
149 | #endif | ||
diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h new file mode 100644 index 000000000000..fff4f800ee42 --- /dev/null +++ b/arch/arm/include/asm/gpio.h | |||
@@ -0,0 +1,7 @@ | |||
1 | #ifndef _ARCH_ARM_GPIO_H | ||
2 | #define _ARCH_ARM_GPIO_H | ||
3 | |||
4 | /* not all ARM platforms necessarily support this API ... */ | ||
5 | #include <asm/arch/gpio.h> | ||
6 | |||
7 | #endif /* _ARCH_ARM_GPIO_H */ | ||
diff --git a/arch/arm/include/asm/hardirq.h b/arch/arm/include/asm/hardirq.h new file mode 100644 index 000000000000..182310b99195 --- /dev/null +++ b/arch/arm/include/asm/hardirq.h | |||
@@ -0,0 +1,32 @@ | |||
1 | #ifndef __ASM_HARDIRQ_H | ||
2 | #define __ASM_HARDIRQ_H | ||
3 | |||
4 | #include <linux/cache.h> | ||
5 | #include <linux/threads.h> | ||
6 | #include <asm/irq.h> | ||
7 | |||
8 | typedef struct { | ||
9 | unsigned int __softirq_pending; | ||
10 | unsigned int local_timer_irqs; | ||
11 | } ____cacheline_aligned irq_cpustat_t; | ||
12 | |||
13 | #include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */ | ||
14 | |||
15 | #if NR_IRQS > 256 | ||
16 | #define HARDIRQ_BITS 9 | ||
17 | #else | ||
18 | #define HARDIRQ_BITS 8 | ||
19 | #endif | ||
20 | |||
21 | /* | ||
22 | * The hardirq mask has to be large enough to have space | ||
23 | * for potentially all IRQ sources in the system nesting | ||
24 | * on a single CPU: | ||
25 | */ | ||
26 | #if (1 << HARDIRQ_BITS) < NR_IRQS | ||
27 | # error HARDIRQ_BITS is too low! | ||
28 | #endif | ||
29 | |||
30 | #define __ARCH_IRQ_EXIT_IRQS_DISABLED 1 | ||
31 | |||
32 | #endif /* __ASM_HARDIRQ_H */ | ||
diff --git a/arch/arm/include/asm/hardware.h b/arch/arm/include/asm/hardware.h new file mode 100644 index 000000000000..eb3b3abb7db7 --- /dev/null +++ b/arch/arm/include/asm/hardware.h | |||
@@ -0,0 +1,18 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/hardware.h | ||
3 | * | ||
4 | * Copyright (C) 1996 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * Common hardware definitions | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_HARDWARE_H | ||
14 | #define __ASM_HARDWARE_H | ||
15 | |||
16 | #include <asm/arch/hardware.h> | ||
17 | |||
18 | #endif | ||
diff --git a/arch/arm/include/asm/hardware/arm_timer.h b/arch/arm/include/asm/hardware/arm_timer.h new file mode 100644 index 000000000000..04be3bdf46b8 --- /dev/null +++ b/arch/arm/include/asm/hardware/arm_timer.h | |||
@@ -0,0 +1,21 @@ | |||
1 | #ifndef __ASM_ARM_HARDWARE_ARM_TIMER_H | ||
2 | #define __ASM_ARM_HARDWARE_ARM_TIMER_H | ||
3 | |||
4 | #define TIMER_LOAD 0x00 | ||
5 | #define TIMER_VALUE 0x04 | ||
6 | #define TIMER_CTRL 0x08 | ||
7 | #define TIMER_CTRL_ONESHOT (1 << 0) | ||
8 | #define TIMER_CTRL_32BIT (1 << 1) | ||
9 | #define TIMER_CTRL_DIV1 (0 << 2) | ||
10 | #define TIMER_CTRL_DIV16 (1 << 2) | ||
11 | #define TIMER_CTRL_DIV256 (2 << 2) | ||
12 | #define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable (versatile only) */ | ||
13 | #define TIMER_CTRL_PERIODIC (1 << 6) | ||
14 | #define TIMER_CTRL_ENABLE (1 << 7) | ||
15 | |||
16 | #define TIMER_INTCLR 0x0c | ||
17 | #define TIMER_RIS 0x10 | ||
18 | #define TIMER_MIS 0x14 | ||
19 | #define TIMER_BGLOAD 0x18 | ||
20 | |||
21 | #endif | ||
diff --git a/arch/arm/include/asm/hardware/arm_twd.h b/arch/arm/include/asm/hardware/arm_twd.h new file mode 100644 index 000000000000..e521b70713c8 --- /dev/null +++ b/arch/arm/include/asm/hardware/arm_twd.h | |||
@@ -0,0 +1,21 @@ | |||
1 | #ifndef __ASM_HARDWARE_TWD_H | ||
2 | #define __ASM_HARDWARE_TWD_H | ||
3 | |||
4 | #define TWD_TIMER_LOAD 0x00 | ||
5 | #define TWD_TIMER_COUNTER 0x04 | ||
6 | #define TWD_TIMER_CONTROL 0x08 | ||
7 | #define TWD_TIMER_INTSTAT 0x0C | ||
8 | |||
9 | #define TWD_WDOG_LOAD 0x20 | ||
10 | #define TWD_WDOG_COUNTER 0x24 | ||
11 | #define TWD_WDOG_CONTROL 0x28 | ||
12 | #define TWD_WDOG_INTSTAT 0x2C | ||
13 | #define TWD_WDOG_RESETSTAT 0x30 | ||
14 | #define TWD_WDOG_DISABLE 0x34 | ||
15 | |||
16 | #define TWD_TIMER_CONTROL_ENABLE (1 << 0) | ||
17 | #define TWD_TIMER_CONTROL_ONESHOT (0 << 1) | ||
18 | #define TWD_TIMER_CONTROL_PERIODIC (1 << 1) | ||
19 | #define TWD_TIMER_CONTROL_IT_ENABLE (1 << 2) | ||
20 | |||
21 | #endif | ||
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h new file mode 100644 index 000000000000..64f2252a25cd --- /dev/null +++ b/arch/arm/include/asm/hardware/cache-l2x0.h | |||
@@ -0,0 +1,56 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/hardware/cache-l2x0.h | ||
3 | * | ||
4 | * Copyright (C) 2007 ARM Limited | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, | ||
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program; if not, write to the Free Software | ||
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
18 | */ | ||
19 | |||
20 | #ifndef __ASM_ARM_HARDWARE_L2X0_H | ||
21 | #define __ASM_ARM_HARDWARE_L2X0_H | ||
22 | |||
23 | #define L2X0_CACHE_ID 0x000 | ||
24 | #define L2X0_CACHE_TYPE 0x004 | ||
25 | #define L2X0_CTRL 0x100 | ||
26 | #define L2X0_AUX_CTRL 0x104 | ||
27 | #define L2X0_EVENT_CNT_CTRL 0x200 | ||
28 | #define L2X0_EVENT_CNT1_CFG 0x204 | ||
29 | #define L2X0_EVENT_CNT0_CFG 0x208 | ||
30 | #define L2X0_EVENT_CNT1_VAL 0x20C | ||
31 | #define L2X0_EVENT_CNT0_VAL 0x210 | ||
32 | #define L2X0_INTR_MASK 0x214 | ||
33 | #define L2X0_MASKED_INTR_STAT 0x218 | ||
34 | #define L2X0_RAW_INTR_STAT 0x21C | ||
35 | #define L2X0_INTR_CLEAR 0x220 | ||
36 | #define L2X0_CACHE_SYNC 0x730 | ||
37 | #define L2X0_INV_LINE_PA 0x770 | ||
38 | #define L2X0_INV_WAY 0x77C | ||
39 | #define L2X0_CLEAN_LINE_PA 0x7B0 | ||
40 | #define L2X0_CLEAN_LINE_IDX 0x7B8 | ||
41 | #define L2X0_CLEAN_WAY 0x7BC | ||
42 | #define L2X0_CLEAN_INV_LINE_PA 0x7F0 | ||
43 | #define L2X0_CLEAN_INV_LINE_IDX 0x7F8 | ||
44 | #define L2X0_CLEAN_INV_WAY 0x7FC | ||
45 | #define L2X0_LOCKDOWN_WAY_D 0x900 | ||
46 | #define L2X0_LOCKDOWN_WAY_I 0x904 | ||
47 | #define L2X0_TEST_OPERATION 0xF00 | ||
48 | #define L2X0_LINE_DATA 0xF10 | ||
49 | #define L2X0_LINE_TAG 0xF30 | ||
50 | #define L2X0_DEBUG_CTRL 0xF40 | ||
51 | |||
52 | #ifndef __ASSEMBLY__ | ||
53 | extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask); | ||
54 | #endif | ||
55 | |||
56 | #endif | ||
diff --git a/arch/arm/include/asm/hardware/clps7111.h b/arch/arm/include/asm/hardware/clps7111.h new file mode 100644 index 000000000000..44477225aed6 --- /dev/null +++ b/arch/arm/include/asm/hardware/clps7111.h | |||
@@ -0,0 +1,184 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/hardware/clps7111.h | ||
3 | * | ||
4 | * This file contains the hardware definitions of the CLPS7111 internal | ||
5 | * registers. | ||
6 | * | ||
7 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License, or | ||
12 | * (at your option) any later version. | ||
13 | * | ||
14 | * This program is distributed in the hope that it will be useful, | ||
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
17 | * GNU General Public License for more details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this program; if not, write to the Free Software | ||
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
22 | */ | ||
23 | #ifndef __ASM_HARDWARE_CLPS7111_H | ||
24 | #define __ASM_HARDWARE_CLPS7111_H | ||
25 | |||
26 | #define CLPS7111_PHYS_BASE (0x80000000) | ||
27 | |||
28 | #ifndef __ASSEMBLY__ | ||
29 | #define clps_readb(off) __raw_readb(CLPS7111_BASE + (off)) | ||
30 | #define clps_readw(off) __raw_readw(CLPS7111_BASE + (off)) | ||
31 | #define clps_readl(off) __raw_readl(CLPS7111_BASE + (off)) | ||
32 | #define clps_writeb(val,off) __raw_writeb(val, CLPS7111_BASE + (off)) | ||
33 | #define clps_writew(val,off) __raw_writew(val, CLPS7111_BASE + (off)) | ||
34 | #define clps_writel(val,off) __raw_writel(val, CLPS7111_BASE + (off)) | ||
35 | #endif | ||
36 | |||
37 | #define PADR (0x0000) | ||
38 | #define PBDR (0x0001) | ||
39 | #define PDDR (0x0003) | ||
40 | #define PADDR (0x0040) | ||
41 | #define PBDDR (0x0041) | ||
42 | #define PDDDR (0x0043) | ||
43 | #define PEDR (0x0080) | ||
44 | #define PEDDR (0x00c0) | ||
45 | #define SYSCON1 (0x0100) | ||
46 | #define SYSFLG1 (0x0140) | ||
47 | #define MEMCFG1 (0x0180) | ||
48 | #define MEMCFG2 (0x01c0) | ||
49 | #define DRFPR (0x0200) | ||
50 | #define INTSR1 (0x0240) | ||
51 | #define INTMR1 (0x0280) | ||
52 | #define LCDCON (0x02c0) | ||
53 | #define TC1D (0x0300) | ||
54 | #define TC2D (0x0340) | ||
55 | #define RTCDR (0x0380) | ||
56 | #define RTCMR (0x03c0) | ||
57 | #define PMPCON (0x0400) | ||
58 | #define CODR (0x0440) | ||
59 | #define UARTDR1 (0x0480) | ||
60 | #define UBRLCR1 (0x04c0) | ||
61 | #define SYNCIO (0x0500) | ||
62 | #define PALLSW (0x0540) | ||
63 | #define PALMSW (0x0580) | ||
64 | #define STFCLR (0x05c0) | ||
65 | #define BLEOI (0x0600) | ||
66 | #define MCEOI (0x0640) | ||
67 | #define TEOI (0x0680) | ||
68 | #define TC1EOI (0x06c0) | ||
69 | #define TC2EOI (0x0700) | ||
70 | #define RTCEOI (0x0740) | ||
71 | #define UMSEOI (0x0780) | ||
72 | #define COEOI (0x07c0) | ||
73 | #define HALT (0x0800) | ||
74 | #define STDBY (0x0840) | ||
75 | |||
76 | #define FBADDR (0x1000) | ||
77 | #define SYSCON2 (0x1100) | ||
78 | #define SYSFLG2 (0x1140) | ||
79 | #define INTSR2 (0x1240) | ||
80 | #define INTMR2 (0x1280) | ||
81 | #define UARTDR2 (0x1480) | ||
82 | #define UBRLCR2 (0x14c0) | ||
83 | #define SS2DR (0x1500) | ||
84 | #define SRXEOF (0x1600) | ||
85 | #define SS2POP (0x16c0) | ||
86 | #define KBDEOI (0x1700) | ||
87 | |||
88 | /* common bits: SYSCON1 / SYSCON2 */ | ||
89 | #define SYSCON_UARTEN (1 << 8) | ||
90 | |||
91 | #define SYSCON1_KBDSCAN(x) ((x) & 15) | ||
92 | #define SYSCON1_KBDSCANMASK (15) | ||
93 | #define SYSCON1_TC1M (1 << 4) | ||
94 | #define SYSCON1_TC1S (1 << 5) | ||
95 | #define SYSCON1_TC2M (1 << 6) | ||
96 | #define SYSCON1_TC2S (1 << 7) | ||
97 | #define SYSCON1_UART1EN SYSCON_UARTEN | ||
98 | #define SYSCON1_BZTOG (1 << 9) | ||
99 | #define SYSCON1_BZMOD (1 << 10) | ||
100 | #define SYSCON1_DBGEN (1 << 11) | ||
101 | #define SYSCON1_LCDEN (1 << 12) | ||
102 | #define SYSCON1_CDENTX (1 << 13) | ||
103 | #define SYSCON1_CDENRX (1 << 14) | ||
104 | #define SYSCON1_SIREN (1 << 15) | ||
105 | #define SYSCON1_ADCKSEL(x) (((x) & 3) << 16) | ||
106 | #define SYSCON1_ADCKSEL_MASK (3 << 16) | ||
107 | #define SYSCON1_EXCKEN (1 << 18) | ||
108 | #define SYSCON1_WAKEDIS (1 << 19) | ||
109 | #define SYSCON1_IRTXM (1 << 20) | ||
110 | |||
111 | /* common bits: SYSFLG1 / SYSFLG2 */ | ||
112 | #define SYSFLG_UBUSY (1 << 11) | ||
113 | #define SYSFLG_URXFE (1 << 22) | ||
114 | #define SYSFLG_UTXFF (1 << 23) | ||
115 | |||
116 | #define SYSFLG1_MCDR (1 << 0) | ||
117 | #define SYSFLG1_DCDET (1 << 1) | ||
118 | #define SYSFLG1_WUDR (1 << 2) | ||
119 | #define SYSFLG1_WUON (1 << 3) | ||
120 | #define SYSFLG1_CTS (1 << 8) | ||
121 | #define SYSFLG1_DSR (1 << 9) | ||
122 | #define SYSFLG1_DCD (1 << 10) | ||
123 | #define SYSFLG1_UBUSY SYSFLG_UBUSY | ||
124 | #define SYSFLG1_NBFLG (1 << 12) | ||
125 | #define SYSFLG1_RSTFLG (1 << 13) | ||
126 | #define SYSFLG1_PFFLG (1 << 14) | ||
127 | #define SYSFLG1_CLDFLG (1 << 15) | ||
128 | #define SYSFLG1_URXFE SYSFLG_URXFE | ||
129 | #define SYSFLG1_UTXFF SYSFLG_UTXFF | ||
130 | #define SYSFLG1_CRXFE (1 << 24) | ||
131 | #define SYSFLG1_CTXFF (1 << 25) | ||
132 | #define SYSFLG1_SSIBUSY (1 << 26) | ||
133 | #define SYSFLG1_ID (1 << 29) | ||
134 | |||
135 | #define SYSFLG2_SSRXOF (1 << 0) | ||
136 | #define SYSFLG2_RESVAL (1 << 1) | ||
137 | #define SYSFLG2_RESFRM (1 << 2) | ||
138 | #define SYSFLG2_SS2RXFE (1 << 3) | ||
139 | #define SYSFLG2_SS2TXFF (1 << 4) | ||
140 | #define SYSFLG2_SS2TXUF (1 << 5) | ||
141 | #define SYSFLG2_CKMODE (1 << 6) | ||
142 | #define SYSFLG2_UBUSY SYSFLG_UBUSY | ||
143 | #define SYSFLG2_URXFE SYSFLG_URXFE | ||
144 | #define SYSFLG2_UTXFF SYSFLG_UTXFF | ||
145 | |||
146 | #define LCDCON_GSEN (1 << 30) | ||
147 | #define LCDCON_GSMD (1 << 31) | ||
148 | |||
149 | #define SYSCON2_SERSEL (1 << 0) | ||
150 | #define SYSCON2_KBD6 (1 << 1) | ||
151 | #define SYSCON2_DRAMZ (1 << 2) | ||
152 | #define SYSCON2_KBWEN (1 << 3) | ||
153 | #define SYSCON2_SS2TXEN (1 << 4) | ||
154 | #define SYSCON2_PCCARD1 (1 << 5) | ||
155 | #define SYSCON2_PCCARD2 (1 << 6) | ||
156 | #define SYSCON2_SS2RXEN (1 << 7) | ||
157 | #define SYSCON2_UART2EN SYSCON_UARTEN | ||
158 | #define SYSCON2_SS2MAEN (1 << 9) | ||
159 | #define SYSCON2_OSTB (1 << 12) | ||
160 | #define SYSCON2_CLKENSL (1 << 13) | ||
161 | #define SYSCON2_BUZFREQ (1 << 14) | ||
162 | |||
163 | /* common bits: UARTDR1 / UARTDR2 */ | ||
164 | #define UARTDR_FRMERR (1 << 8) | ||
165 | #define UARTDR_PARERR (1 << 9) | ||
166 | #define UARTDR_OVERR (1 << 10) | ||
167 | |||
168 | /* common bits: UBRLCR1 / UBRLCR2 */ | ||
169 | #define UBRLCR_BAUD_MASK ((1 << 12) - 1) | ||
170 | #define UBRLCR_BREAK (1 << 12) | ||
171 | #define UBRLCR_PRTEN (1 << 13) | ||
172 | #define UBRLCR_EVENPRT (1 << 14) | ||
173 | #define UBRLCR_XSTOP (1 << 15) | ||
174 | #define UBRLCR_FIFOEN (1 << 16) | ||
175 | #define UBRLCR_WRDLEN5 (0 << 17) | ||
176 | #define UBRLCR_WRDLEN6 (1 << 17) | ||
177 | #define UBRLCR_WRDLEN7 (2 << 17) | ||
178 | #define UBRLCR_WRDLEN8 (3 << 17) | ||
179 | #define UBRLCR_WRDLEN_MASK (3 << 17) | ||
180 | |||
181 | #define SYNCIO_SMCKEN (1 << 13) | ||
182 | #define SYNCIO_TXFRMEN (1 << 14) | ||
183 | |||
184 | #endif /* __ASM_HARDWARE_CLPS7111_H */ | ||
diff --git a/arch/arm/include/asm/hardware/cs89712.h b/arch/arm/include/asm/hardware/cs89712.h new file mode 100644 index 000000000000..f75626933e94 --- /dev/null +++ b/arch/arm/include/asm/hardware/cs89712.h | |||
@@ -0,0 +1,49 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/hardware/cs89712.h | ||
3 | * | ||
4 | * This file contains the hardware definitions of the CS89712 | ||
5 | * additional internal registers. | ||
6 | * | ||
7 | * Copyright (C) 2001 Thomas Gleixner autronix automation <gleixner@autronix.de> | ||
8 | * | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License as published by | ||
12 | * the Free Software Foundation; either version 2 of the License, or | ||
13 | * (at your option) any later version. | ||
14 | * | ||
15 | * This program is distributed in the hope that it will be useful, | ||
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
18 | * GNU General Public License for more details. | ||
19 | * | ||
20 | * You should have received a copy of the GNU General Public License | ||
21 | * along with this program; if not, write to the Free Software | ||
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
23 | */ | ||
24 | #ifndef __ASM_HARDWARE_CS89712_H | ||
25 | #define __ASM_HARDWARE_CS89712_H | ||
26 | |||
27 | /* | ||
28 | * CS89712 additional registers | ||
29 | */ | ||
30 | |||
31 | #define PCDR 0x0002 /* Port C Data register ---------------------------- */ | ||
32 | #define PCDDR 0x0042 /* Port C Data Direction register ------------------ */ | ||
33 | #define SDCONF 0x2300 /* SDRAM Configuration register ---------------------*/ | ||
34 | #define SDRFPR 0x2340 /* SDRAM Refresh period register --------------------*/ | ||
35 | |||
36 | #define SDCONF_ACTIVE (1 << 10) | ||
37 | #define SDCONF_CLKCTL (1 << 9) | ||
38 | #define SDCONF_WIDTH_4 (0 << 7) | ||
39 | #define SDCONF_WIDTH_8 (1 << 7) | ||
40 | #define SDCONF_WIDTH_16 (2 << 7) | ||
41 | #define SDCONF_WIDTH_32 (3 << 7) | ||
42 | #define SDCONF_SIZE_16 (0 << 5) | ||
43 | #define SDCONF_SIZE_64 (1 << 5) | ||
44 | #define SDCONF_SIZE_128 (2 << 5) | ||
45 | #define SDCONF_SIZE_256 (3 << 5) | ||
46 | #define SDCONF_CASLAT_2 (2) | ||
47 | #define SDCONF_CASLAT_3 (3) | ||
48 | |||
49 | #endif /* __ASM_HARDWARE_CS89712_H */ | ||
diff --git a/arch/arm/include/asm/hardware/debug-8250.S b/arch/arm/include/asm/hardware/debug-8250.S new file mode 100644 index 000000000000..22c689255e6e --- /dev/null +++ b/arch/arm/include/asm/hardware/debug-8250.S | |||
@@ -0,0 +1,29 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/hardware/debug-8250.S | ||
3 | * | ||
4 | * Copyright (C) 1994-1999 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #include <linux/serial_reg.h> | ||
11 | |||
12 | .macro senduart,rd,rx | ||
13 | strb \rd, [\rx, #UART_TX << UART_SHIFT] | ||
14 | .endm | ||
15 | |||
16 | .macro busyuart,rd,rx | ||
17 | 1002: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT] | ||
18 | and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE | ||
19 | teq \rd, #UART_LSR_TEMT | UART_LSR_THRE | ||
20 | bne 1002b | ||
21 | .endm | ||
22 | |||
23 | .macro waituart,rd,rx | ||
24 | #ifdef FLOW_CONTROL | ||
25 | 1001: ldrb \rd, [\rx, #UART_MSR << UART_SHIFT] | ||
26 | tst \rd, #UART_MSR_CTS | ||
27 | beq 1001b | ||
28 | #endif | ||
29 | .endm | ||
diff --git a/arch/arm/include/asm/hardware/debug-pl01x.S b/arch/arm/include/asm/hardware/debug-pl01x.S new file mode 100644 index 000000000000..f9fd083eff63 --- /dev/null +++ b/arch/arm/include/asm/hardware/debug-pl01x.S | |||
@@ -0,0 +1,29 @@ | |||
1 | /* arch/arm/include/asm/hardware/debug-pl01x.S | ||
2 | * | ||
3 | * Debugging macro include header | ||
4 | * | ||
5 | * Copyright (C) 1994-1999 Russell King | ||
6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | * | ||
12 | */ | ||
13 | #include <linux/amba/serial.h> | ||
14 | |||
15 | .macro senduart,rd,rx | ||
16 | strb \rd, [\rx, #UART01x_DR] | ||
17 | .endm | ||
18 | |||
19 | .macro waituart,rd,rx | ||
20 | 1001: ldr \rd, [\rx, #UART01x_FR] | ||
21 | tst \rd, #UART01x_FR_TXFF | ||
22 | bne 1001b | ||
23 | .endm | ||
24 | |||
25 | .macro busyuart,rd,rx | ||
26 | 1001: ldr \rd, [\rx, #UART01x_FR] | ||
27 | tst \rd, #UART01x_FR_BUSY | ||
28 | bne 1001b | ||
29 | .endm | ||
diff --git a/arch/arm/include/asm/hardware/dec21285.h b/arch/arm/include/asm/hardware/dec21285.h new file mode 100644 index 000000000000..7068a1c1e4e4 --- /dev/null +++ b/arch/arm/include/asm/hardware/dec21285.h | |||
@@ -0,0 +1,147 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/hardware/dec21285.h | ||
3 | * | ||
4 | * Copyright (C) 1998 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * DC21285 registers | ||
11 | */ | ||
12 | #define DC21285_PCI_IACK 0x79000000 | ||
13 | #define DC21285_ARMCSR_BASE 0x42000000 | ||
14 | #define DC21285_PCI_TYPE_0_CONFIG 0x7b000000 | ||
15 | #define DC21285_PCI_TYPE_1_CONFIG 0x7a000000 | ||
16 | #define DC21285_OUTBOUND_WRITE_FLUSH 0x78000000 | ||
17 | #define DC21285_FLASH 0x41000000 | ||
18 | #define DC21285_PCI_IO 0x7c000000 | ||
19 | #define DC21285_PCI_MEM 0x80000000 | ||
20 | |||
21 | #ifndef __ASSEMBLY__ | ||
22 | #include <asm/hardware.h> | ||
23 | #define DC21285_IO(x) ((volatile unsigned long *)(ARMCSR_BASE+(x))) | ||
24 | #else | ||
25 | #define DC21285_IO(x) (x) | ||
26 | #endif | ||
27 | |||
28 | #define CSR_PCICMD DC21285_IO(0x0004) | ||
29 | #define CSR_CLASSREV DC21285_IO(0x0008) | ||
30 | #define CSR_PCICACHELINESIZE DC21285_IO(0x000c) | ||
31 | #define CSR_PCICSRBASE DC21285_IO(0x0010) | ||
32 | #define CSR_PCICSRIOBASE DC21285_IO(0x0014) | ||
33 | #define CSR_PCISDRAMBASE DC21285_IO(0x0018) | ||
34 | #define CSR_PCIROMBASE DC21285_IO(0x0030) | ||
35 | #define CSR_MBOX0 DC21285_IO(0x0050) | ||
36 | #define CSR_MBOX1 DC21285_IO(0x0054) | ||
37 | #define CSR_MBOX2 DC21285_IO(0x0058) | ||
38 | #define CSR_MBOX3 DC21285_IO(0x005c) | ||
39 | #define CSR_DOORBELL DC21285_IO(0x0060) | ||
40 | #define CSR_DOORBELL_SETUP DC21285_IO(0x0064) | ||
41 | #define CSR_ROMWRITEREG DC21285_IO(0x0068) | ||
42 | #define CSR_CSRBASEMASK DC21285_IO(0x00f8) | ||
43 | #define CSR_CSRBASEOFFSET DC21285_IO(0x00fc) | ||
44 | #define CSR_SDRAMBASEMASK DC21285_IO(0x0100) | ||
45 | #define CSR_SDRAMBASEOFFSET DC21285_IO(0x0104) | ||
46 | #define CSR_ROMBASEMASK DC21285_IO(0x0108) | ||
47 | #define CSR_SDRAMTIMING DC21285_IO(0x010c) | ||
48 | #define CSR_SDRAMADDRSIZE0 DC21285_IO(0x0110) | ||
49 | #define CSR_SDRAMADDRSIZE1 DC21285_IO(0x0114) | ||
50 | #define CSR_SDRAMADDRSIZE2 DC21285_IO(0x0118) | ||
51 | #define CSR_SDRAMADDRSIZE3 DC21285_IO(0x011c) | ||
52 | #define CSR_I2O_INFREEHEAD DC21285_IO(0x0120) | ||
53 | #define CSR_I2O_INPOSTTAIL DC21285_IO(0x0124) | ||
54 | #define CSR_I2O_OUTPOSTHEAD DC21285_IO(0x0128) | ||
55 | #define CSR_I2O_OUTFREETAIL DC21285_IO(0x012c) | ||
56 | #define CSR_I2O_INFREECOUNT DC21285_IO(0x0130) | ||
57 | #define CSR_I2O_OUTPOSTCOUNT DC21285_IO(0x0134) | ||
58 | #define CSR_I2O_INPOSTCOUNT DC21285_IO(0x0138) | ||
59 | #define CSR_SA110_CNTL DC21285_IO(0x013c) | ||
60 | #define SA110_CNTL_INITCMPLETE (1 << 0) | ||
61 | #define SA110_CNTL_ASSERTSERR (1 << 1) | ||
62 | #define SA110_CNTL_RXSERR (1 << 3) | ||
63 | #define SA110_CNTL_SA110DRAMPARITY (1 << 4) | ||
64 | #define SA110_CNTL_PCISDRAMPARITY (1 << 5) | ||
65 | #define SA110_CNTL_DMASDRAMPARITY (1 << 6) | ||
66 | #define SA110_CNTL_DISCARDTIMER (1 << 8) | ||
67 | #define SA110_CNTL_PCINRESET (1 << 9) | ||
68 | #define SA110_CNTL_I2O_256 (0 << 10) | ||
69 | #define SA110_CNTL_I20_512 (1 << 10) | ||
70 | #define SA110_CNTL_I2O_1024 (2 << 10) | ||
71 | #define SA110_CNTL_I2O_2048 (3 << 10) | ||
72 | #define SA110_CNTL_I2O_4096 (4 << 10) | ||
73 | #define SA110_CNTL_I2O_8192 (5 << 10) | ||
74 | #define SA110_CNTL_I2O_16384 (6 << 10) | ||
75 | #define SA110_CNTL_I2O_32768 (7 << 10) | ||
76 | #define SA110_CNTL_WATCHDOG (1 << 13) | ||
77 | #define SA110_CNTL_ROMWIDTH_UNDEF (0 << 14) | ||
78 | #define SA110_CNTL_ROMWIDTH_16 (1 << 14) | ||
79 | #define SA110_CNTL_ROMWIDTH_32 (2 << 14) | ||
80 | #define SA110_CNTL_ROMWIDTH_8 (3 << 14) | ||
81 | #define SA110_CNTL_ROMACCESSTIME(x) ((x)<<16) | ||
82 | #define SA110_CNTL_ROMBURSTTIME(x) ((x)<<20) | ||
83 | #define SA110_CNTL_ROMTRISTATETIME(x) ((x)<<24) | ||
84 | #define SA110_CNTL_XCSDIR(x) ((x)<<28) | ||
85 | #define SA110_CNTL_PCICFN (1 << 31) | ||
86 | |||
87 | /* | ||
88 | * footbridge_cfn_mode() is used when we want | ||
89 | * to check whether we are the central function | ||
90 | */ | ||
91 | #define __footbridge_cfn_mode() (*CSR_SA110_CNTL & SA110_CNTL_PCICFN) | ||
92 | #if defined(CONFIG_FOOTBRIDGE_HOST) && defined(CONFIG_FOOTBRIDGE_ADDIN) | ||
93 | #define footbridge_cfn_mode() __footbridge_cfn_mode() | ||
94 | #elif defined(CONFIG_FOOTBRIDGE_HOST) | ||
95 | #define footbridge_cfn_mode() (1) | ||
96 | #else | ||
97 | #define footbridge_cfn_mode() (0) | ||
98 | #endif | ||
99 | |||
100 | #define CSR_PCIADDR_EXTN DC21285_IO(0x0140) | ||
101 | #define CSR_PREFETCHMEMRANGE DC21285_IO(0x0144) | ||
102 | #define CSR_XBUS_CYCLE DC21285_IO(0x0148) | ||
103 | #define CSR_XBUS_IOSTROBE DC21285_IO(0x014c) | ||
104 | #define CSR_DOORBELL_PCI DC21285_IO(0x0150) | ||
105 | #define CSR_DOORBELL_SA110 DC21285_IO(0x0154) | ||
106 | #define CSR_UARTDR DC21285_IO(0x0160) | ||
107 | #define CSR_RXSTAT DC21285_IO(0x0164) | ||
108 | #define CSR_H_UBRLCR DC21285_IO(0x0168) | ||
109 | #define CSR_M_UBRLCR DC21285_IO(0x016c) | ||
110 | #define CSR_L_UBRLCR DC21285_IO(0x0170) | ||
111 | #define CSR_UARTCON DC21285_IO(0x0174) | ||
112 | #define CSR_UARTFLG DC21285_IO(0x0178) | ||
113 | #define CSR_IRQ_STATUS DC21285_IO(0x0180) | ||
114 | #define CSR_IRQ_RAWSTATUS DC21285_IO(0x0184) | ||
115 | #define CSR_IRQ_ENABLE DC21285_IO(0x0188) | ||
116 | #define CSR_IRQ_DISABLE DC21285_IO(0x018c) | ||
117 | #define CSR_IRQ_SOFT DC21285_IO(0x0190) | ||
118 | #define CSR_FIQ_STATUS DC21285_IO(0x0280) | ||
119 | #define CSR_FIQ_RAWSTATUS DC21285_IO(0x0284) | ||
120 | #define CSR_FIQ_ENABLE DC21285_IO(0x0288) | ||
121 | #define CSR_FIQ_DISABLE DC21285_IO(0x028c) | ||
122 | #define CSR_FIQ_SOFT DC21285_IO(0x0290) | ||
123 | #define CSR_TIMER1_LOAD DC21285_IO(0x0300) | ||
124 | #define CSR_TIMER1_VALUE DC21285_IO(0x0304) | ||
125 | #define CSR_TIMER1_CNTL DC21285_IO(0x0308) | ||
126 | #define CSR_TIMER1_CLR DC21285_IO(0x030c) | ||
127 | #define CSR_TIMER2_LOAD DC21285_IO(0x0320) | ||
128 | #define CSR_TIMER2_VALUE DC21285_IO(0x0324) | ||
129 | #define CSR_TIMER2_CNTL DC21285_IO(0x0328) | ||
130 | #define CSR_TIMER2_CLR DC21285_IO(0x032c) | ||
131 | #define CSR_TIMER3_LOAD DC21285_IO(0x0340) | ||
132 | #define CSR_TIMER3_VALUE DC21285_IO(0x0344) | ||
133 | #define CSR_TIMER3_CNTL DC21285_IO(0x0348) | ||
134 | #define CSR_TIMER3_CLR DC21285_IO(0x034c) | ||
135 | #define CSR_TIMER4_LOAD DC21285_IO(0x0360) | ||
136 | #define CSR_TIMER4_VALUE DC21285_IO(0x0364) | ||
137 | #define CSR_TIMER4_CNTL DC21285_IO(0x0368) | ||
138 | #define CSR_TIMER4_CLR DC21285_IO(0x036c) | ||
139 | |||
140 | #define TIMER_CNTL_ENABLE (1 << 7) | ||
141 | #define TIMER_CNTL_AUTORELOAD (1 << 6) | ||
142 | #define TIMER_CNTL_DIV1 (0) | ||
143 | #define TIMER_CNTL_DIV16 (1 << 2) | ||
144 | #define TIMER_CNTL_DIV256 (2 << 2) | ||
145 | #define TIMER_CNTL_CNTEXT (3 << 2) | ||
146 | |||
147 | |||
diff --git a/arch/arm/include/asm/hardware/entry-macro-iomd.S b/arch/arm/include/asm/hardware/entry-macro-iomd.S new file mode 100644 index 000000000000..e0af4983723f --- /dev/null +++ b/arch/arm/include/asm/hardware/entry-macro-iomd.S | |||
@@ -0,0 +1,139 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/hardware/entry-macro-iomd.S | ||
3 | * | ||
4 | * Low-level IRQ helper macros for IOC/IOMD based platforms | ||
5 | * | ||
6 | * This file is licensed under the terms of the GNU General Public | ||
7 | * License version 2. This program is licensed "as is" without any | ||
8 | * warranty of any kind, whether express or implied. | ||
9 | */ | ||
10 | |||
11 | /* IOC / IOMD based hardware */ | ||
12 | #include <asm/hardware/iomd.h> | ||
13 | |||
14 | .macro disable_fiq | ||
15 | mov r12, #ioc_base_high | ||
16 | .if ioc_base_low | ||
17 | orr r12, r12, #ioc_base_low | ||
18 | .endif | ||
19 | strb r12, [r12, #0x38] @ Disable FIQ register | ||
20 | .endm | ||
21 | |||
22 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
23 | ldrb \irqstat, [\base, #IOMD_IRQREQB] @ get high priority first | ||
24 | ldr \tmp, =irq_prio_h | ||
25 | teq \irqstat, #0 | ||
26 | #ifdef IOMD_BASE | ||
27 | ldreqb \irqstat, [\base, #IOMD_DMAREQ] @ get dma | ||
28 | addeq \tmp, \tmp, #256 @ irq_prio_h table size | ||
29 | teqeq \irqstat, #0 | ||
30 | bne 2406f | ||
31 | #endif | ||
32 | ldreqb \irqstat, [\base, #IOMD_IRQREQA] @ get low priority | ||
33 | addeq \tmp, \tmp, #256 @ irq_prio_d table size | ||
34 | teqeq \irqstat, #0 | ||
35 | #ifdef IOMD_IRQREQC | ||
36 | ldreqb \irqstat, [\base, #IOMD_IRQREQC] | ||
37 | addeq \tmp, \tmp, #256 @ irq_prio_l table size | ||
38 | teqeq \irqstat, #0 | ||
39 | #endif | ||
40 | #ifdef IOMD_IRQREQD | ||
41 | ldreqb \irqstat, [\base, #IOMD_IRQREQD] | ||
42 | addeq \tmp, \tmp, #256 @ irq_prio_lc table size | ||
43 | teqeq \irqstat, #0 | ||
44 | #endif | ||
45 | 2406: ldrneb \irqnr, [\tmp, \irqstat] @ get IRQ number | ||
46 | .endm | ||
47 | |||
48 | /* | ||
49 | * Interrupt table (incorporates priority). Please note that we | ||
50 | * rely on the order of these tables (see above code). | ||
51 | */ | ||
52 | .align 5 | ||
53 | irq_prio_h: .byte 0, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10 | ||
54 | .byte 12, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10 | ||
55 | .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10 | ||
56 | .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10 | ||
57 | .byte 14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10 | ||
58 | .byte 14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10 | ||
59 | .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10 | ||
60 | .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10 | ||
61 | .byte 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10 | ||
62 | .byte 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10 | ||
63 | .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10 | ||
64 | .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10 | ||
65 | .byte 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10 | ||
66 | .byte 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10 | ||
67 | .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10 | ||
68 | .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10 | ||
69 | #ifdef IOMD_BASE | ||
70 | irq_prio_d: .byte 0,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16 | ||
71 | .byte 20,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16 | ||
72 | .byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16 | ||
73 | .byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16 | ||
74 | .byte 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16 | ||
75 | .byte 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16 | ||
76 | .byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16 | ||
77 | .byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16 | ||
78 | .byte 23,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16 | ||
79 | .byte 23,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16 | ||
80 | .byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16 | ||
81 | .byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16 | ||
82 | .byte 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16 | ||
83 | .byte 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16 | ||
84 | .byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16 | ||
85 | .byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16 | ||
86 | #endif | ||
87 | irq_prio_l: .byte 0, 0, 1, 0, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3 | ||
88 | .byte 4, 0, 1, 0, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3 | ||
89 | .byte 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 | ||
90 | .byte 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 | ||
91 | .byte 6, 6, 6, 6, 6, 6, 6, 6, 3, 3, 3, 3, 3, 3, 3, 3 | ||
92 | .byte 6, 6, 6, 6, 6, 6, 6, 6, 3, 3, 3, 3, 3, 3, 3, 3 | ||
93 | .byte 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 | ||
94 | .byte 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 | ||
95 | .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7 | ||
96 | .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7 | ||
97 | .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7 | ||
98 | .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7 | ||
99 | .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7 | ||
100 | .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7 | ||
101 | .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7 | ||
102 | .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7 | ||
103 | #ifdef IOMD_IRQREQC | ||
104 | irq_prio_lc: .byte 24,24,25,24,26,26,26,26,27,27,27,27,27,27,27,27 | ||
105 | .byte 28,24,25,24,26,26,26,26,27,27,27,27,27,27,27,27 | ||
106 | .byte 29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29 | ||
107 | .byte 29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29 | ||
108 | .byte 30,30,30,30,30,30,30,30,27,27,27,27,27,27,27,27 | ||
109 | .byte 30,30,30,30,30,30,30,30,27,27,27,27,27,27,27,27 | ||
110 | .byte 29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29 | ||
111 | .byte 29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29 | ||
112 | .byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31 | ||
113 | .byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31 | ||
114 | .byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31 | ||
115 | .byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31 | ||
116 | .byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31 | ||
117 | .byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31 | ||
118 | .byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31 | ||
119 | .byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31 | ||
120 | #endif | ||
121 | #ifdef IOMD_IRQREQD | ||
122 | irq_prio_ld: .byte 40,40,41,40,42,42,42,42,43,43,43,43,43,43,43,43 | ||
123 | .byte 44,40,41,40,42,42,42,42,43,43,43,43,43,43,43,43 | ||
124 | .byte 45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45 | ||
125 | .byte 45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45 | ||
126 | .byte 46,46,46,46,46,46,46,46,43,43,43,43,43,43,43,43 | ||
127 | .byte 46,46,46,46,46,46,46,46,43,43,43,43,43,43,43,43 | ||
128 | .byte 45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45 | ||
129 | .byte 45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45 | ||
130 | .byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47 | ||
131 | .byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47 | ||
132 | .byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47 | ||
133 | .byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47 | ||
134 | .byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47 | ||
135 | .byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47 | ||
136 | .byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47 | ||
137 | .byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47 | ||
138 | #endif | ||
139 | |||
diff --git a/arch/arm/include/asm/hardware/ep7211.h b/arch/arm/include/asm/hardware/ep7211.h new file mode 100644 index 000000000000..654d5f625c49 --- /dev/null +++ b/arch/arm/include/asm/hardware/ep7211.h | |||
@@ -0,0 +1,40 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/hardware/ep7211.h | ||
3 | * | ||
4 | * This file contains the hardware definitions of the EP7211 internal | ||
5 | * registers. | ||
6 | * | ||
7 | * Copyright (C) 2001 Blue Mug, Inc. All Rights Reserved. | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License, or | ||
12 | * (at your option) any later version. | ||
13 | * | ||
14 | * This program is distributed in the hope that it will be useful, | ||
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
17 | * GNU General Public License for more details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this program; if not, write to the Free Software | ||
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
22 | */ | ||
23 | #ifndef __ASM_HARDWARE_EP7211_H | ||
24 | #define __ASM_HARDWARE_EP7211_H | ||
25 | |||
26 | #include <asm/hardware/clps7111.h> | ||
27 | |||
28 | /* | ||
29 | * define EP7211_BASE to be the base address of the region | ||
30 | * you want to access. | ||
31 | */ | ||
32 | |||
33 | #define EP7211_PHYS_BASE (0x80000000) | ||
34 | |||
35 | /* | ||
36 | * XXX miket@bluemug.com: need to introduce EP7211 registers (those not | ||
37 | * present in 7212) here. | ||
38 | */ | ||
39 | |||
40 | #endif /* __ASM_HARDWARE_EP7211_H */ | ||
diff --git a/arch/arm/include/asm/hardware/ep7212.h b/arch/arm/include/asm/hardware/ep7212.h new file mode 100644 index 000000000000..3b43bbeaf1db --- /dev/null +++ b/arch/arm/include/asm/hardware/ep7212.h | |||
@@ -0,0 +1,83 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/hardware/ep7212.h | ||
3 | * | ||
4 | * This file contains the hardware definitions of the EP7212 internal | ||
5 | * registers. | ||
6 | * | ||
7 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License, or | ||
12 | * (at your option) any later version. | ||
13 | * | ||
14 | * This program is distributed in the hope that it will be useful, | ||
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
17 | * GNU General Public License for more details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this program; if not, write to the Free Software | ||
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
22 | */ | ||
23 | #ifndef __ASM_HARDWARE_EP7212_H | ||
24 | #define __ASM_HARDWARE_EP7212_H | ||
25 | |||
26 | /* | ||
27 | * define EP7212_BASE to be the base address of the region | ||
28 | * you want to access. | ||
29 | */ | ||
30 | |||
31 | #define EP7212_PHYS_BASE (0x80000000) | ||
32 | |||
33 | #ifndef __ASSEMBLY__ | ||
34 | #define ep_readl(off) __raw_readl(EP7212_BASE + (off)) | ||
35 | #define ep_writel(val,off) __raw_writel(val, EP7212_BASE + (off)) | ||
36 | #endif | ||
37 | |||
38 | /* | ||
39 | * These registers are specific to the EP7212 only | ||
40 | */ | ||
41 | #define DAIR 0x2000 | ||
42 | #define DAIR0 0x2040 | ||
43 | #define DAIDR1 0x2080 | ||
44 | #define DAIDR2 0x20c0 | ||
45 | #define DAISR 0x2100 | ||
46 | #define SYSCON3 0x2200 | ||
47 | #define INTSR3 0x2240 | ||
48 | #define INTMR3 0x2280 | ||
49 | #define LEDFLSH 0x22c0 | ||
50 | |||
51 | #define DAIR_DAIEN (1 << 16) | ||
52 | #define DAIR_ECS (1 << 17) | ||
53 | #define DAIR_LCTM (1 << 19) | ||
54 | #define DAIR_LCRM (1 << 20) | ||
55 | #define DAIR_RCTM (1 << 21) | ||
56 | #define DAIR_RCRM (1 << 22) | ||
57 | #define DAIR_LBM (1 << 23) | ||
58 | |||
59 | #define DAIDR2_FIFOEN (1 << 15) | ||
60 | #define DAIDR2_FIFOLEFT (0x0d << 16) | ||
61 | #define DAIDR2_FIFORIGHT (0x11 << 16) | ||
62 | |||
63 | #define DAISR_RCTS (1 << 0) | ||
64 | #define DAISR_RCRS (1 << 1) | ||
65 | #define DAISR_LCTS (1 << 2) | ||
66 | #define DAISR_LCRS (1 << 3) | ||
67 | #define DAISR_RCTU (1 << 4) | ||
68 | #define DAISR_RCRO (1 << 5) | ||
69 | #define DAISR_LCTU (1 << 6) | ||
70 | #define DAISR_LCRO (1 << 7) | ||
71 | #define DAISR_RCNF (1 << 8) | ||
72 | #define DAISR_RCNE (1 << 9) | ||
73 | #define DAISR_LCNF (1 << 10) | ||
74 | #define DAISR_LCNE (1 << 11) | ||
75 | #define DAISR_FIFO (1 << 12) | ||
76 | |||
77 | #define SYSCON3_ADCCON (1 << 0) | ||
78 | #define SYSCON3_DAISEL (1 << 3) | ||
79 | #define SYSCON3_ADCCKNSEN (1 << 4) | ||
80 | #define SYSCON3_FASTWAKE (1 << 8) | ||
81 | #define SYSCON3_DAIEN (1 << 9) | ||
82 | |||
83 | #endif /* __ASM_HARDWARE_EP7212_H */ | ||
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h new file mode 100644 index 000000000000..4924914af188 --- /dev/null +++ b/arch/arm/include/asm/hardware/gic.h | |||
@@ -0,0 +1,42 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/hardware/gic.h | ||
3 | * | ||
4 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #ifndef __ASM_ARM_HARDWARE_GIC_H | ||
11 | #define __ASM_ARM_HARDWARE_GIC_H | ||
12 | |||
13 | #include <linux/compiler.h> | ||
14 | |||
15 | #define GIC_CPU_CTRL 0x00 | ||
16 | #define GIC_CPU_PRIMASK 0x04 | ||
17 | #define GIC_CPU_BINPOINT 0x08 | ||
18 | #define GIC_CPU_INTACK 0x0c | ||
19 | #define GIC_CPU_EOI 0x10 | ||
20 | #define GIC_CPU_RUNNINGPRI 0x14 | ||
21 | #define GIC_CPU_HIGHPRI 0x18 | ||
22 | |||
23 | #define GIC_DIST_CTRL 0x000 | ||
24 | #define GIC_DIST_CTR 0x004 | ||
25 | #define GIC_DIST_ENABLE_SET 0x100 | ||
26 | #define GIC_DIST_ENABLE_CLEAR 0x180 | ||
27 | #define GIC_DIST_PENDING_SET 0x200 | ||
28 | #define GIC_DIST_PENDING_CLEAR 0x280 | ||
29 | #define GIC_DIST_ACTIVE_BIT 0x300 | ||
30 | #define GIC_DIST_PRI 0x400 | ||
31 | #define GIC_DIST_TARGET 0x800 | ||
32 | #define GIC_DIST_CONFIG 0xc00 | ||
33 | #define GIC_DIST_SOFTINT 0xf00 | ||
34 | |||
35 | #ifndef __ASSEMBLY__ | ||
36 | void gic_dist_init(unsigned int gic_nr, void __iomem *base, unsigned int irq_start); | ||
37 | void gic_cpu_init(unsigned int gic_nr, void __iomem *base); | ||
38 | void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); | ||
39 | void gic_raise_softirq(cpumask_t cpumask, unsigned int irq); | ||
40 | #endif | ||
41 | |||
42 | #endif | ||
diff --git a/arch/arm/include/asm/hardware/icst307.h b/arch/arm/include/asm/hardware/icst307.h new file mode 100644 index 000000000000..554f128a1046 --- /dev/null +++ b/arch/arm/include/asm/hardware/icst307.h | |||
@@ -0,0 +1,38 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/hardware/icst307.h | ||
3 | * | ||
4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * Support functions for calculating clocks/divisors for the ICS307 | ||
11 | * clock generators. See http://www.icst.com/ for more information | ||
12 | * on these devices. | ||
13 | * | ||
14 | * This file is similar to the icst525.h file | ||
15 | */ | ||
16 | #ifndef ASMARM_HARDWARE_ICST307_H | ||
17 | #define ASMARM_HARDWARE_ICST307_H | ||
18 | |||
19 | struct icst307_params { | ||
20 | unsigned long ref; | ||
21 | unsigned long vco_max; /* inclusive */ | ||
22 | unsigned short vd_min; /* inclusive */ | ||
23 | unsigned short vd_max; /* inclusive */ | ||
24 | unsigned char rd_min; /* inclusive */ | ||
25 | unsigned char rd_max; /* inclusive */ | ||
26 | }; | ||
27 | |||
28 | struct icst307_vco { | ||
29 | unsigned short v; | ||
30 | unsigned char r; | ||
31 | unsigned char s; | ||
32 | }; | ||
33 | |||
34 | unsigned long icst307_khz(const struct icst307_params *p, struct icst307_vco vco); | ||
35 | struct icst307_vco icst307_khz_to_vco(const struct icst307_params *p, unsigned long freq); | ||
36 | struct icst307_vco icst307_ps_to_vco(const struct icst307_params *p, unsigned long period); | ||
37 | |||
38 | #endif | ||
diff --git a/arch/arm/include/asm/hardware/icst525.h b/arch/arm/include/asm/hardware/icst525.h new file mode 100644 index 000000000000..58f0dc43e2ed --- /dev/null +++ b/arch/arm/include/asm/hardware/icst525.h | |||
@@ -0,0 +1,36 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/hardware/icst525.h | ||
3 | * | ||
4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * Support functions for calculating clocks/divisors for the ICST525 | ||
11 | * clock generators. See http://www.icst.com/ for more information | ||
12 | * on these devices. | ||
13 | */ | ||
14 | #ifndef ASMARM_HARDWARE_ICST525_H | ||
15 | #define ASMARM_HARDWARE_ICST525_H | ||
16 | |||
17 | struct icst525_params { | ||
18 | unsigned long ref; | ||
19 | unsigned long vco_max; /* inclusive */ | ||
20 | unsigned short vd_min; /* inclusive */ | ||
21 | unsigned short vd_max; /* inclusive */ | ||
22 | unsigned char rd_min; /* inclusive */ | ||
23 | unsigned char rd_max; /* inclusive */ | ||
24 | }; | ||
25 | |||
26 | struct icst525_vco { | ||
27 | unsigned short v; | ||
28 | unsigned char r; | ||
29 | unsigned char s; | ||
30 | }; | ||
31 | |||
32 | unsigned long icst525_khz(const struct icst525_params *p, struct icst525_vco vco); | ||
33 | struct icst525_vco icst525_khz_to_vco(const struct icst525_params *p, unsigned long freq); | ||
34 | struct icst525_vco icst525_ps_to_vco(const struct icst525_params *p, unsigned long period); | ||
35 | |||
36 | #endif | ||
diff --git a/arch/arm/include/asm/hardware/ioc.h b/arch/arm/include/asm/hardware/ioc.h new file mode 100644 index 000000000000..1f6b8013becb --- /dev/null +++ b/arch/arm/include/asm/hardware/ioc.h | |||
@@ -0,0 +1,72 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/hardware/ioc.h | ||
3 | * | ||
4 | * Copyright (C) Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * Use these macros to read/write the IOC. All it does is perform the actual | ||
11 | * read/write. | ||
12 | */ | ||
13 | #ifndef __ASMARM_HARDWARE_IOC_H | ||
14 | #define __ASMARM_HARDWARE_IOC_H | ||
15 | |||
16 | #ifndef __ASSEMBLY__ | ||
17 | |||
18 | /* | ||
19 | * We use __raw_base variants here so that we give the compiler the | ||
20 | * chance to keep IOC_BASE in a register. | ||
21 | */ | ||
22 | #define ioc_readb(off) __raw_readb(IOC_BASE + (off)) | ||
23 | #define ioc_writeb(val,off) __raw_writeb(val, IOC_BASE + (off)) | ||
24 | |||
25 | #endif | ||
26 | |||
27 | #define IOC_CONTROL (0x00) | ||
28 | #define IOC_KARTTX (0x04) | ||
29 | #define IOC_KARTRX (0x04) | ||
30 | |||
31 | #define IOC_IRQSTATA (0x10) | ||
32 | #define IOC_IRQREQA (0x14) | ||
33 | #define IOC_IRQCLRA (0x14) | ||
34 | #define IOC_IRQMASKA (0x18) | ||
35 | |||
36 | #define IOC_IRQSTATB (0x20) | ||
37 | #define IOC_IRQREQB (0x24) | ||
38 | #define IOC_IRQMASKB (0x28) | ||
39 | |||
40 | #define IOC_FIQSTAT (0x30) | ||
41 | #define IOC_FIQREQ (0x34) | ||
42 | #define IOC_FIQMASK (0x38) | ||
43 | |||
44 | #define IOC_T0CNTL (0x40) | ||
45 | #define IOC_T0LTCHL (0x40) | ||
46 | #define IOC_T0CNTH (0x44) | ||
47 | #define IOC_T0LTCHH (0x44) | ||
48 | #define IOC_T0GO (0x48) | ||
49 | #define IOC_T0LATCH (0x4c) | ||
50 | |||
51 | #define IOC_T1CNTL (0x50) | ||
52 | #define IOC_T1LTCHL (0x50) | ||
53 | #define IOC_T1CNTH (0x54) | ||
54 | #define IOC_T1LTCHH (0x54) | ||
55 | #define IOC_T1GO (0x58) | ||
56 | #define IOC_T1LATCH (0x5c) | ||
57 | |||
58 | #define IOC_T2CNTL (0x60) | ||
59 | #define IOC_T2LTCHL (0x60) | ||
60 | #define IOC_T2CNTH (0x64) | ||
61 | #define IOC_T2LTCHH (0x64) | ||
62 | #define IOC_T2GO (0x68) | ||
63 | #define IOC_T2LATCH (0x6c) | ||
64 | |||
65 | #define IOC_T3CNTL (0x70) | ||
66 | #define IOC_T3LTCHL (0x70) | ||
67 | #define IOC_T3CNTH (0x74) | ||
68 | #define IOC_T3LTCHH (0x74) | ||
69 | #define IOC_T3GO (0x78) | ||
70 | #define IOC_T3LATCH (0x7c) | ||
71 | |||
72 | #endif | ||
diff --git a/arch/arm/include/asm/hardware/iomd.h b/arch/arm/include/asm/hardware/iomd.h new file mode 100644 index 000000000000..9c5afbd71a69 --- /dev/null +++ b/arch/arm/include/asm/hardware/iomd.h | |||
@@ -0,0 +1,226 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/hardware/iomd.h | ||
3 | * | ||
4 | * Copyright (C) 1999 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * This file contains information out the IOMD ASIC used in the | ||
11 | * Acorn RiscPC and subsequently integrated into the CLPS7500 chips. | ||
12 | */ | ||
13 | #ifndef __ASMARM_HARDWARE_IOMD_H | ||
14 | #define __ASMARM_HARDWARE_IOMD_H | ||
15 | |||
16 | |||
17 | #ifndef __ASSEMBLY__ | ||
18 | |||
19 | /* | ||
20 | * We use __raw_base variants here so that we give the compiler the | ||
21 | * chance to keep IOC_BASE in a register. | ||
22 | */ | ||
23 | #define iomd_readb(off) __raw_readb(IOMD_BASE + (off)) | ||
24 | #define iomd_readl(off) __raw_readl(IOMD_BASE + (off)) | ||
25 | #define iomd_writeb(val,off) __raw_writeb(val, IOMD_BASE + (off)) | ||
26 | #define iomd_writel(val,off) __raw_writel(val, IOMD_BASE + (off)) | ||
27 | |||
28 | #endif | ||
29 | |||
30 | #define IOMD_CONTROL (0x000) | ||
31 | #define IOMD_KARTTX (0x004) | ||
32 | #define IOMD_KARTRX (0x004) | ||
33 | #define IOMD_KCTRL (0x008) | ||
34 | |||
35 | #ifdef CONFIG_ARCH_CLPS7500 | ||
36 | #define IOMD_IOLINES (0x00C) | ||
37 | #endif | ||
38 | |||
39 | #define IOMD_IRQSTATA (0x010) | ||
40 | #define IOMD_IRQREQA (0x014) | ||
41 | #define IOMD_IRQCLRA (0x014) | ||
42 | #define IOMD_IRQMASKA (0x018) | ||
43 | |||
44 | #ifdef CONFIG_ARCH_CLPS7500 | ||
45 | #define IOMD_SUSMODE (0x01C) | ||
46 | #endif | ||
47 | |||
48 | #define IOMD_IRQSTATB (0x020) | ||
49 | #define IOMD_IRQREQB (0x024) | ||
50 | #define IOMD_IRQMASKB (0x028) | ||
51 | |||
52 | #define IOMD_FIQSTAT (0x030) | ||
53 | #define IOMD_FIQREQ (0x034) | ||
54 | #define IOMD_FIQMASK (0x038) | ||
55 | |||
56 | #ifdef CONFIG_ARCH_CLPS7500 | ||
57 | #define IOMD_CLKCTL (0x03C) | ||
58 | #endif | ||
59 | |||
60 | #define IOMD_T0CNTL (0x040) | ||
61 | #define IOMD_T0LTCHL (0x040) | ||
62 | #define IOMD_T0CNTH (0x044) | ||
63 | #define IOMD_T0LTCHH (0x044) | ||
64 | #define IOMD_T0GO (0x048) | ||
65 | #define IOMD_T0LATCH (0x04c) | ||
66 | |||
67 | #define IOMD_T1CNTL (0x050) | ||
68 | #define IOMD_T1LTCHL (0x050) | ||
69 | #define IOMD_T1CNTH (0x054) | ||
70 | #define IOMD_T1LTCHH (0x054) | ||
71 | #define IOMD_T1GO (0x058) | ||
72 | #define IOMD_T1LATCH (0x05c) | ||
73 | |||
74 | #ifdef CONFIG_ARCH_CLPS7500 | ||
75 | #define IOMD_IRQSTATC (0x060) | ||
76 | #define IOMD_IRQREQC (0x064) | ||
77 | #define IOMD_IRQMASKC (0x068) | ||
78 | |||
79 | #define IOMD_VIDMUX (0x06c) | ||
80 | |||
81 | #define IOMD_IRQSTATD (0x070) | ||
82 | #define IOMD_IRQREQD (0x074) | ||
83 | #define IOMD_IRQMASKD (0x078) | ||
84 | #endif | ||
85 | |||
86 | #define IOMD_ROMCR0 (0x080) | ||
87 | #define IOMD_ROMCR1 (0x084) | ||
88 | #ifdef CONFIG_ARCH_RPC | ||
89 | #define IOMD_DRAMCR (0x088) | ||
90 | #endif | ||
91 | #define IOMD_REFCR (0x08C) | ||
92 | |||
93 | #define IOMD_FSIZE (0x090) | ||
94 | #define IOMD_ID0 (0x094) | ||
95 | #define IOMD_ID1 (0x098) | ||
96 | #define IOMD_VERSION (0x09C) | ||
97 | |||
98 | #ifdef CONFIG_ARCH_RPC | ||
99 | #define IOMD_MOUSEX (0x0A0) | ||
100 | #define IOMD_MOUSEY (0x0A4) | ||
101 | #endif | ||
102 | |||
103 | #ifdef CONFIG_ARCH_CLPS7500 | ||
104 | #define IOMD_MSEDAT (0x0A8) | ||
105 | #define IOMD_MSECTL (0x0Ac) | ||
106 | #endif | ||
107 | |||
108 | #ifdef CONFIG_ARCH_RPC | ||
109 | #define IOMD_DMATCR (0x0C0) | ||
110 | #endif | ||
111 | #define IOMD_IOTCR (0x0C4) | ||
112 | #define IOMD_ECTCR (0x0C8) | ||
113 | #ifdef CONFIG_ARCH_RPC | ||
114 | #define IOMD_DMAEXT (0x0CC) | ||
115 | #endif | ||
116 | #ifdef CONFIG_ARCH_CLPS7500 | ||
117 | #define IOMD_ASTCR (0x0CC) | ||
118 | #define IOMD_DRAMCR (0x0D0) | ||
119 | #define IOMD_SELFREF (0x0D4) | ||
120 | #define IOMD_ATODICR (0x0E0) | ||
121 | #define IOMD_ATODSR (0x0E4) | ||
122 | #define IOMD_ATODCC (0x0E8) | ||
123 | #define IOMD_ATODCNT1 (0x0EC) | ||
124 | #define IOMD_ATODCNT2 (0x0F0) | ||
125 | #define IOMD_ATODCNT3 (0x0F4) | ||
126 | #define IOMD_ATODCNT4 (0x0F8) | ||
127 | #endif | ||
128 | |||
129 | #ifdef CONFIG_ARCH_RPC | ||
130 | #define DMA_EXT_IO0 1 | ||
131 | #define DMA_EXT_IO1 2 | ||
132 | #define DMA_EXT_IO2 4 | ||
133 | #define DMA_EXT_IO3 8 | ||
134 | |||
135 | #define IOMD_IO0CURA (0x100) | ||
136 | #define IOMD_IO0ENDA (0x104) | ||
137 | #define IOMD_IO0CURB (0x108) | ||
138 | #define IOMD_IO0ENDB (0x10C) | ||
139 | #define IOMD_IO0CR (0x110) | ||
140 | #define IOMD_IO0ST (0x114) | ||
141 | |||
142 | #define IOMD_IO1CURA (0x120) | ||
143 | #define IOMD_IO1ENDA (0x124) | ||
144 | #define IOMD_IO1CURB (0x128) | ||
145 | #define IOMD_IO1ENDB (0x12C) | ||
146 | #define IOMD_IO1CR (0x130) | ||
147 | #define IOMD_IO1ST (0x134) | ||
148 | |||
149 | #define IOMD_IO2CURA (0x140) | ||
150 | #define IOMD_IO2ENDA (0x144) | ||
151 | #define IOMD_IO2CURB (0x148) | ||
152 | #define IOMD_IO2ENDB (0x14C) | ||
153 | #define IOMD_IO2CR (0x150) | ||
154 | #define IOMD_IO2ST (0x154) | ||
155 | |||
156 | #define IOMD_IO3CURA (0x160) | ||
157 | #define IOMD_IO3ENDA (0x164) | ||
158 | #define IOMD_IO3CURB (0x168) | ||
159 | #define IOMD_IO3ENDB (0x16C) | ||
160 | #define IOMD_IO3CR (0x170) | ||
161 | #define IOMD_IO3ST (0x174) | ||
162 | #endif | ||
163 | |||
164 | #define IOMD_SD0CURA (0x180) | ||
165 | #define IOMD_SD0ENDA (0x184) | ||
166 | #define IOMD_SD0CURB (0x188) | ||
167 | #define IOMD_SD0ENDB (0x18C) | ||
168 | #define IOMD_SD0CR (0x190) | ||
169 | #define IOMD_SD0ST (0x194) | ||
170 | |||
171 | #ifdef CONFIG_ARCH_RPC | ||
172 | #define IOMD_SD1CURA (0x1A0) | ||
173 | #define IOMD_SD1ENDA (0x1A4) | ||
174 | #define IOMD_SD1CURB (0x1A8) | ||
175 | #define IOMD_SD1ENDB (0x1AC) | ||
176 | #define IOMD_SD1CR (0x1B0) | ||
177 | #define IOMD_SD1ST (0x1B4) | ||
178 | #endif | ||
179 | |||
180 | #define IOMD_CURSCUR (0x1C0) | ||
181 | #define IOMD_CURSINIT (0x1C4) | ||
182 | |||
183 | #define IOMD_VIDCUR (0x1D0) | ||
184 | #define IOMD_VIDEND (0x1D4) | ||
185 | #define IOMD_VIDSTART (0x1D8) | ||
186 | #define IOMD_VIDINIT (0x1DC) | ||
187 | #define IOMD_VIDCR (0x1E0) | ||
188 | |||
189 | #define IOMD_DMASTAT (0x1F0) | ||
190 | #define IOMD_DMAREQ (0x1F4) | ||
191 | #define IOMD_DMAMASK (0x1F8) | ||
192 | |||
193 | #define DMA_END_S (1 << 31) | ||
194 | #define DMA_END_L (1 << 30) | ||
195 | |||
196 | #define DMA_CR_C 0x80 | ||
197 | #define DMA_CR_D 0x40 | ||
198 | #define DMA_CR_E 0x20 | ||
199 | |||
200 | #define DMA_ST_OFL 4 | ||
201 | #define DMA_ST_INT 2 | ||
202 | #define DMA_ST_AB 1 | ||
203 | |||
204 | /* | ||
205 | * DMA (MEMC) compatibility | ||
206 | */ | ||
207 | #define HALF_SAM vram_half_sam | ||
208 | #define VDMA_ALIGNMENT (HALF_SAM * 2) | ||
209 | #define VDMA_XFERSIZE (HALF_SAM) | ||
210 | #define VDMA_INIT IOMD_VIDINIT | ||
211 | #define VDMA_START IOMD_VIDSTART | ||
212 | #define VDMA_END IOMD_VIDEND | ||
213 | |||
214 | #ifndef __ASSEMBLY__ | ||
215 | extern unsigned int vram_half_sam; | ||
216 | #define video_set_dma(start,end,offset) \ | ||
217 | do { \ | ||
218 | outl (SCREEN_START + start, VDMA_START); \ | ||
219 | outl (SCREEN_START + end - VDMA_XFERSIZE, VDMA_END); \ | ||
220 | if (offset >= end - VDMA_XFERSIZE) \ | ||
221 | offset |= 0x40000000; \ | ||
222 | outl (SCREEN_START + offset, VDMA_INIT); \ | ||
223 | } while (0) | ||
224 | #endif | ||
225 | |||
226 | #endif | ||
diff --git a/arch/arm/include/asm/hardware/iop3xx-adma.h b/arch/arm/include/asm/hardware/iop3xx-adma.h new file mode 100644 index 000000000000..af64676650a2 --- /dev/null +++ b/arch/arm/include/asm/hardware/iop3xx-adma.h | |||
@@ -0,0 +1,888 @@ | |||
1 | /* | ||
2 | * Copyright © 2006, Intel Corporation. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License along with | ||
14 | * this program; if not, write to the Free Software Foundation, Inc., | ||
15 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | ||
16 | * | ||
17 | */ | ||
18 | #ifndef _ADMA_H | ||
19 | #define _ADMA_H | ||
20 | #include <linux/types.h> | ||
21 | #include <linux/io.h> | ||
22 | #include <asm/hardware.h> | ||
23 | #include <asm/hardware/iop_adma.h> | ||
24 | |||
25 | /* Memory copy units */ | ||
26 | #define DMA_CCR(chan) (chan->mmr_base + 0x0) | ||
27 | #define DMA_CSR(chan) (chan->mmr_base + 0x4) | ||
28 | #define DMA_DAR(chan) (chan->mmr_base + 0xc) | ||
29 | #define DMA_NDAR(chan) (chan->mmr_base + 0x10) | ||
30 | #define DMA_PADR(chan) (chan->mmr_base + 0x14) | ||
31 | #define DMA_PUADR(chan) (chan->mmr_base + 0x18) | ||
32 | #define DMA_LADR(chan) (chan->mmr_base + 0x1c) | ||
33 | #define DMA_BCR(chan) (chan->mmr_base + 0x20) | ||
34 | #define DMA_DCR(chan) (chan->mmr_base + 0x24) | ||
35 | |||
36 | /* Application accelerator unit */ | ||
37 | #define AAU_ACR(chan) (chan->mmr_base + 0x0) | ||
38 | #define AAU_ASR(chan) (chan->mmr_base + 0x4) | ||
39 | #define AAU_ADAR(chan) (chan->mmr_base + 0x8) | ||
40 | #define AAU_ANDAR(chan) (chan->mmr_base + 0xc) | ||
41 | #define AAU_SAR(src, chan) (chan->mmr_base + (0x10 + ((src) << 2))) | ||
42 | #define AAU_DAR(chan) (chan->mmr_base + 0x20) | ||
43 | #define AAU_ABCR(chan) (chan->mmr_base + 0x24) | ||
44 | #define AAU_ADCR(chan) (chan->mmr_base + 0x28) | ||
45 | #define AAU_SAR_EDCR(src_edc) (chan->mmr_base + (0x02c + ((src_edc-4) << 2))) | ||
46 | #define AAU_EDCR0_IDX 8 | ||
47 | #define AAU_EDCR1_IDX 17 | ||
48 | #define AAU_EDCR2_IDX 26 | ||
49 | |||
50 | #define DMA0_ID 0 | ||
51 | #define DMA1_ID 1 | ||
52 | #define AAU_ID 2 | ||
53 | |||
54 | struct iop3xx_aau_desc_ctrl { | ||
55 | unsigned int int_en:1; | ||
56 | unsigned int blk1_cmd_ctrl:3; | ||
57 | unsigned int blk2_cmd_ctrl:3; | ||
58 | unsigned int blk3_cmd_ctrl:3; | ||
59 | unsigned int blk4_cmd_ctrl:3; | ||
60 | unsigned int blk5_cmd_ctrl:3; | ||
61 | unsigned int blk6_cmd_ctrl:3; | ||
62 | unsigned int blk7_cmd_ctrl:3; | ||
63 | unsigned int blk8_cmd_ctrl:3; | ||
64 | unsigned int blk_ctrl:2; | ||
65 | unsigned int dual_xor_en:1; | ||
66 | unsigned int tx_complete:1; | ||
67 | unsigned int zero_result_err:1; | ||
68 | unsigned int zero_result_en:1; | ||
69 | unsigned int dest_write_en:1; | ||
70 | }; | ||
71 | |||
72 | struct iop3xx_aau_e_desc_ctrl { | ||
73 | unsigned int reserved:1; | ||
74 | unsigned int blk1_cmd_ctrl:3; | ||
75 | unsigned int blk2_cmd_ctrl:3; | ||
76 | unsigned int blk3_cmd_ctrl:3; | ||
77 | unsigned int blk4_cmd_ctrl:3; | ||
78 | unsigned int blk5_cmd_ctrl:3; | ||
79 | unsigned int blk6_cmd_ctrl:3; | ||
80 | unsigned int blk7_cmd_ctrl:3; | ||
81 | unsigned int blk8_cmd_ctrl:3; | ||
82 | unsigned int reserved2:7; | ||
83 | }; | ||
84 | |||
85 | struct iop3xx_dma_desc_ctrl { | ||
86 | unsigned int pci_transaction:4; | ||
87 | unsigned int int_en:1; | ||
88 | unsigned int dac_cycle_en:1; | ||
89 | unsigned int mem_to_mem_en:1; | ||
90 | unsigned int crc_data_tx_en:1; | ||
91 | unsigned int crc_gen_en:1; | ||
92 | unsigned int crc_seed_dis:1; | ||
93 | unsigned int reserved:21; | ||
94 | unsigned int crc_tx_complete:1; | ||
95 | }; | ||
96 | |||
97 | struct iop3xx_desc_dma { | ||
98 | u32 next_desc; | ||
99 | union { | ||
100 | u32 pci_src_addr; | ||
101 | u32 pci_dest_addr; | ||
102 | u32 src_addr; | ||
103 | }; | ||
104 | union { | ||
105 | u32 upper_pci_src_addr; | ||
106 | u32 upper_pci_dest_addr; | ||
107 | }; | ||
108 | union { | ||
109 | u32 local_pci_src_addr; | ||
110 | u32 local_pci_dest_addr; | ||
111 | u32 dest_addr; | ||
112 | }; | ||
113 | u32 byte_count; | ||
114 | union { | ||
115 | u32 desc_ctrl; | ||
116 | struct iop3xx_dma_desc_ctrl desc_ctrl_field; | ||
117 | }; | ||
118 | u32 crc_addr; | ||
119 | }; | ||
120 | |||
121 | struct iop3xx_desc_aau { | ||
122 | u32 next_desc; | ||
123 | u32 src[4]; | ||
124 | u32 dest_addr; | ||
125 | u32 byte_count; | ||
126 | union { | ||
127 | u32 desc_ctrl; | ||
128 | struct iop3xx_aau_desc_ctrl desc_ctrl_field; | ||
129 | }; | ||
130 | union { | ||
131 | u32 src_addr; | ||
132 | u32 e_desc_ctrl; | ||
133 | struct iop3xx_aau_e_desc_ctrl e_desc_ctrl_field; | ||
134 | } src_edc[31]; | ||
135 | }; | ||
136 | |||
137 | struct iop3xx_aau_gfmr { | ||
138 | unsigned int gfmr1:8; | ||
139 | unsigned int gfmr2:8; | ||
140 | unsigned int gfmr3:8; | ||
141 | unsigned int gfmr4:8; | ||
142 | }; | ||
143 | |||
144 | struct iop3xx_desc_pq_xor { | ||
145 | u32 next_desc; | ||
146 | u32 src[3]; | ||
147 | union { | ||
148 | u32 data_mult1; | ||
149 | struct iop3xx_aau_gfmr data_mult1_field; | ||
150 | }; | ||
151 | u32 dest_addr; | ||
152 | u32 byte_count; | ||
153 | union { | ||
154 | u32 desc_ctrl; | ||
155 | struct iop3xx_aau_desc_ctrl desc_ctrl_field; | ||
156 | }; | ||
157 | union { | ||
158 | u32 src_addr; | ||
159 | u32 e_desc_ctrl; | ||
160 | struct iop3xx_aau_e_desc_ctrl e_desc_ctrl_field; | ||
161 | u32 data_multiplier; | ||
162 | struct iop3xx_aau_gfmr data_mult_field; | ||
163 | u32 reserved; | ||
164 | } src_edc_gfmr[19]; | ||
165 | }; | ||
166 | |||
167 | struct iop3xx_desc_dual_xor { | ||
168 | u32 next_desc; | ||
169 | u32 src0_addr; | ||
170 | u32 src1_addr; | ||
171 | u32 h_src_addr; | ||
172 | u32 d_src_addr; | ||
173 | u32 h_dest_addr; | ||
174 | u32 byte_count; | ||
175 | union { | ||
176 | u32 desc_ctrl; | ||
177 | struct iop3xx_aau_desc_ctrl desc_ctrl_field; | ||
178 | }; | ||
179 | u32 d_dest_addr; | ||
180 | }; | ||
181 | |||
182 | union iop3xx_desc { | ||
183 | struct iop3xx_desc_aau *aau; | ||
184 | struct iop3xx_desc_dma *dma; | ||
185 | struct iop3xx_desc_pq_xor *pq_xor; | ||
186 | struct iop3xx_desc_dual_xor *dual_xor; | ||
187 | void *ptr; | ||
188 | }; | ||
189 | |||
190 | static inline int iop_adma_get_max_xor(void) | ||
191 | { | ||
192 | return 32; | ||
193 | } | ||
194 | |||
195 | static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan) | ||
196 | { | ||
197 | int id = chan->device->id; | ||
198 | |||
199 | switch (id) { | ||
200 | case DMA0_ID: | ||
201 | case DMA1_ID: | ||
202 | return __raw_readl(DMA_DAR(chan)); | ||
203 | case AAU_ID: | ||
204 | return __raw_readl(AAU_ADAR(chan)); | ||
205 | default: | ||
206 | BUG(); | ||
207 | } | ||
208 | return 0; | ||
209 | } | ||
210 | |||
211 | static inline void iop_chan_set_next_descriptor(struct iop_adma_chan *chan, | ||
212 | u32 next_desc_addr) | ||
213 | { | ||
214 | int id = chan->device->id; | ||
215 | |||
216 | switch (id) { | ||
217 | case DMA0_ID: | ||
218 | case DMA1_ID: | ||
219 | __raw_writel(next_desc_addr, DMA_NDAR(chan)); | ||
220 | break; | ||
221 | case AAU_ID: | ||
222 | __raw_writel(next_desc_addr, AAU_ANDAR(chan)); | ||
223 | break; | ||
224 | } | ||
225 | |||
226 | } | ||
227 | |||
228 | #define IOP_ADMA_STATUS_BUSY (1 << 10) | ||
229 | #define IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT (1024) | ||
230 | #define IOP_ADMA_XOR_MAX_BYTE_COUNT (16 * 1024 * 1024) | ||
231 | #define IOP_ADMA_MAX_BYTE_COUNT (16 * 1024 * 1024) | ||
232 | |||
233 | static inline int iop_chan_is_busy(struct iop_adma_chan *chan) | ||
234 | { | ||
235 | u32 status = __raw_readl(DMA_CSR(chan)); | ||
236 | return (status & IOP_ADMA_STATUS_BUSY) ? 1 : 0; | ||
237 | } | ||
238 | |||
239 | static inline int iop_desc_is_aligned(struct iop_adma_desc_slot *desc, | ||
240 | int num_slots) | ||
241 | { | ||
242 | /* num_slots will only ever be 1, 2, 4, or 8 */ | ||
243 | return (desc->idx & (num_slots - 1)) ? 0 : 1; | ||
244 | } | ||
245 | |||
246 | /* to do: support large (i.e. > hw max) buffer sizes */ | ||
247 | static inline int iop_chan_memcpy_slot_count(size_t len, int *slots_per_op) | ||
248 | { | ||
249 | *slots_per_op = 1; | ||
250 | return 1; | ||
251 | } | ||
252 | |||
253 | /* to do: support large (i.e. > hw max) buffer sizes */ | ||
254 | static inline int iop_chan_memset_slot_count(size_t len, int *slots_per_op) | ||
255 | { | ||
256 | *slots_per_op = 1; | ||
257 | return 1; | ||
258 | } | ||
259 | |||
260 | static inline int iop3xx_aau_xor_slot_count(size_t len, int src_cnt, | ||
261 | int *slots_per_op) | ||
262 | { | ||
263 | static const char slot_count_table[] = { | ||
264 | 1, 1, 1, 1, /* 01 - 04 */ | ||
265 | 2, 2, 2, 2, /* 05 - 08 */ | ||
266 | 4, 4, 4, 4, /* 09 - 12 */ | ||
267 | 4, 4, 4, 4, /* 13 - 16 */ | ||
268 | 8, 8, 8, 8, /* 17 - 20 */ | ||
269 | 8, 8, 8, 8, /* 21 - 24 */ | ||
270 | 8, 8, 8, 8, /* 25 - 28 */ | ||
271 | 8, 8, 8, 8, /* 29 - 32 */ | ||
272 | }; | ||
273 | *slots_per_op = slot_count_table[src_cnt - 1]; | ||
274 | return *slots_per_op; | ||
275 | } | ||
276 | |||
277 | static inline int | ||
278 | iop_chan_interrupt_slot_count(int *slots_per_op, struct iop_adma_chan *chan) | ||
279 | { | ||
280 | switch (chan->device->id) { | ||
281 | case DMA0_ID: | ||
282 | case DMA1_ID: | ||
283 | return iop_chan_memcpy_slot_count(0, slots_per_op); | ||
284 | case AAU_ID: | ||
285 | return iop3xx_aau_xor_slot_count(0, 2, slots_per_op); | ||
286 | default: | ||
287 | BUG(); | ||
288 | } | ||
289 | return 0; | ||
290 | } | ||
291 | |||
292 | static inline int iop_chan_xor_slot_count(size_t len, int src_cnt, | ||
293 | int *slots_per_op) | ||
294 | { | ||
295 | int slot_cnt = iop3xx_aau_xor_slot_count(len, src_cnt, slots_per_op); | ||
296 | |||
297 | if (len <= IOP_ADMA_XOR_MAX_BYTE_COUNT) | ||
298 | return slot_cnt; | ||
299 | |||
300 | len -= IOP_ADMA_XOR_MAX_BYTE_COUNT; | ||
301 | while (len > IOP_ADMA_XOR_MAX_BYTE_COUNT) { | ||
302 | len -= IOP_ADMA_XOR_MAX_BYTE_COUNT; | ||
303 | slot_cnt += *slots_per_op; | ||
304 | } | ||
305 | |||
306 | if (len) | ||
307 | slot_cnt += *slots_per_op; | ||
308 | |||
309 | return slot_cnt; | ||
310 | } | ||
311 | |||
312 | /* zero sum on iop3xx is limited to 1k at a time so it requires multiple | ||
313 | * descriptors | ||
314 | */ | ||
315 | static inline int iop_chan_zero_sum_slot_count(size_t len, int src_cnt, | ||
316 | int *slots_per_op) | ||
317 | { | ||
318 | int slot_cnt = iop3xx_aau_xor_slot_count(len, src_cnt, slots_per_op); | ||
319 | |||
320 | if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) | ||
321 | return slot_cnt; | ||
322 | |||
323 | len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; | ||
324 | while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) { | ||
325 | len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; | ||
326 | slot_cnt += *slots_per_op; | ||
327 | } | ||
328 | |||
329 | if (len) | ||
330 | slot_cnt += *slots_per_op; | ||
331 | |||
332 | return slot_cnt; | ||
333 | } | ||
334 | |||
335 | static inline u32 iop_desc_get_dest_addr(struct iop_adma_desc_slot *desc, | ||
336 | struct iop_adma_chan *chan) | ||
337 | { | ||
338 | union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; | ||
339 | |||
340 | switch (chan->device->id) { | ||
341 | case DMA0_ID: | ||
342 | case DMA1_ID: | ||
343 | return hw_desc.dma->dest_addr; | ||
344 | case AAU_ID: | ||
345 | return hw_desc.aau->dest_addr; | ||
346 | default: | ||
347 | BUG(); | ||
348 | } | ||
349 | return 0; | ||
350 | } | ||
351 | |||
352 | static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc, | ||
353 | struct iop_adma_chan *chan) | ||
354 | { | ||
355 | union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; | ||
356 | |||
357 | switch (chan->device->id) { | ||
358 | case DMA0_ID: | ||
359 | case DMA1_ID: | ||
360 | return hw_desc.dma->byte_count; | ||
361 | case AAU_ID: | ||
362 | return hw_desc.aau->byte_count; | ||
363 | default: | ||
364 | BUG(); | ||
365 | } | ||
366 | return 0; | ||
367 | } | ||
368 | |||
369 | /* translate the src_idx to a descriptor word index */ | ||
370 | static inline int __desc_idx(int src_idx) | ||
371 | { | ||
372 | static const int desc_idx_table[] = { 0, 0, 0, 0, | ||
373 | 0, 1, 2, 3, | ||
374 | 5, 6, 7, 8, | ||
375 | 9, 10, 11, 12, | ||
376 | 14, 15, 16, 17, | ||
377 | 18, 19, 20, 21, | ||
378 | 23, 24, 25, 26, | ||
379 | 27, 28, 29, 30, | ||
380 | }; | ||
381 | |||
382 | return desc_idx_table[src_idx]; | ||
383 | } | ||
384 | |||
385 | static inline u32 iop_desc_get_src_addr(struct iop_adma_desc_slot *desc, | ||
386 | struct iop_adma_chan *chan, | ||
387 | int src_idx) | ||
388 | { | ||
389 | union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; | ||
390 | |||
391 | switch (chan->device->id) { | ||
392 | case DMA0_ID: | ||
393 | case DMA1_ID: | ||
394 | return hw_desc.dma->src_addr; | ||
395 | case AAU_ID: | ||
396 | break; | ||
397 | default: | ||
398 | BUG(); | ||
399 | } | ||
400 | |||
401 | if (src_idx < 4) | ||
402 | return hw_desc.aau->src[src_idx]; | ||
403 | else | ||
404 | return hw_desc.aau->src_edc[__desc_idx(src_idx)].src_addr; | ||
405 | } | ||
406 | |||
407 | static inline void iop3xx_aau_desc_set_src_addr(struct iop3xx_desc_aau *hw_desc, | ||
408 | int src_idx, dma_addr_t addr) | ||
409 | { | ||
410 | if (src_idx < 4) | ||
411 | hw_desc->src[src_idx] = addr; | ||
412 | else | ||
413 | hw_desc->src_edc[__desc_idx(src_idx)].src_addr = addr; | ||
414 | } | ||
415 | |||
416 | static inline void | ||
417 | iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, unsigned long flags) | ||
418 | { | ||
419 | struct iop3xx_desc_dma *hw_desc = desc->hw_desc; | ||
420 | union { | ||
421 | u32 value; | ||
422 | struct iop3xx_dma_desc_ctrl field; | ||
423 | } u_desc_ctrl; | ||
424 | |||
425 | u_desc_ctrl.value = 0; | ||
426 | u_desc_ctrl.field.mem_to_mem_en = 1; | ||
427 | u_desc_ctrl.field.pci_transaction = 0xe; /* memory read block */ | ||
428 | u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; | ||
429 | hw_desc->desc_ctrl = u_desc_ctrl.value; | ||
430 | hw_desc->upper_pci_src_addr = 0; | ||
431 | hw_desc->crc_addr = 0; | ||
432 | } | ||
433 | |||
434 | static inline void | ||
435 | iop_desc_init_memset(struct iop_adma_desc_slot *desc, unsigned long flags) | ||
436 | { | ||
437 | struct iop3xx_desc_aau *hw_desc = desc->hw_desc; | ||
438 | union { | ||
439 | u32 value; | ||
440 | struct iop3xx_aau_desc_ctrl field; | ||
441 | } u_desc_ctrl; | ||
442 | |||
443 | u_desc_ctrl.value = 0; | ||
444 | u_desc_ctrl.field.blk1_cmd_ctrl = 0x2; /* memory block fill */ | ||
445 | u_desc_ctrl.field.dest_write_en = 1; | ||
446 | u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; | ||
447 | hw_desc->desc_ctrl = u_desc_ctrl.value; | ||
448 | } | ||
449 | |||
450 | static inline u32 | ||
451 | iop3xx_desc_init_xor(struct iop3xx_desc_aau *hw_desc, int src_cnt, | ||
452 | unsigned long flags) | ||
453 | { | ||
454 | int i, shift; | ||
455 | u32 edcr; | ||
456 | union { | ||
457 | u32 value; | ||
458 | struct iop3xx_aau_desc_ctrl field; | ||
459 | } u_desc_ctrl; | ||
460 | |||
461 | u_desc_ctrl.value = 0; | ||
462 | switch (src_cnt) { | ||
463 | case 25 ... 32: | ||
464 | u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */ | ||
465 | edcr = 0; | ||
466 | shift = 1; | ||
467 | for (i = 24; i < src_cnt; i++) { | ||
468 | edcr |= (1 << shift); | ||
469 | shift += 3; | ||
470 | } | ||
471 | hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = edcr; | ||
472 | src_cnt = 24; | ||
473 | /* fall through */ | ||
474 | case 17 ... 24: | ||
475 | if (!u_desc_ctrl.field.blk_ctrl) { | ||
476 | hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0; | ||
477 | u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */ | ||
478 | } | ||
479 | edcr = 0; | ||
480 | shift = 1; | ||
481 | for (i = 16; i < src_cnt; i++) { | ||
482 | edcr |= (1 << shift); | ||
483 | shift += 3; | ||
484 | } | ||
485 | hw_desc->src_edc[AAU_EDCR1_IDX].e_desc_ctrl = edcr; | ||
486 | src_cnt = 16; | ||
487 | /* fall through */ | ||
488 | case 9 ... 16: | ||
489 | if (!u_desc_ctrl.field.blk_ctrl) | ||
490 | u_desc_ctrl.field.blk_ctrl = 0x2; /* use EDCR0 */ | ||
491 | edcr = 0; | ||
492 | shift = 1; | ||
493 | for (i = 8; i < src_cnt; i++) { | ||
494 | edcr |= (1 << shift); | ||
495 | shift += 3; | ||
496 | } | ||
497 | hw_desc->src_edc[AAU_EDCR0_IDX].e_desc_ctrl = edcr; | ||
498 | src_cnt = 8; | ||
499 | /* fall through */ | ||
500 | case 2 ... 8: | ||
501 | shift = 1; | ||
502 | for (i = 0; i < src_cnt; i++) { | ||
503 | u_desc_ctrl.value |= (1 << shift); | ||
504 | shift += 3; | ||
505 | } | ||
506 | |||
507 | if (!u_desc_ctrl.field.blk_ctrl && src_cnt > 4) | ||
508 | u_desc_ctrl.field.blk_ctrl = 0x1; /* use mini-desc */ | ||
509 | } | ||
510 | |||
511 | u_desc_ctrl.field.dest_write_en = 1; | ||
512 | u_desc_ctrl.field.blk1_cmd_ctrl = 0x7; /* direct fill */ | ||
513 | u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; | ||
514 | hw_desc->desc_ctrl = u_desc_ctrl.value; | ||
515 | |||
516 | return u_desc_ctrl.value; | ||
517 | } | ||
518 | |||
519 | static inline void | ||
520 | iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt, | ||
521 | unsigned long flags) | ||
522 | { | ||
523 | iop3xx_desc_init_xor(desc->hw_desc, src_cnt, flags); | ||
524 | } | ||
525 | |||
526 | /* return the number of operations */ | ||
527 | static inline int | ||
528 | iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, | ||
529 | unsigned long flags) | ||
530 | { | ||
531 | int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op; | ||
532 | struct iop3xx_desc_aau *hw_desc, *prev_hw_desc, *iter; | ||
533 | union { | ||
534 | u32 value; | ||
535 | struct iop3xx_aau_desc_ctrl field; | ||
536 | } u_desc_ctrl; | ||
537 | int i, j; | ||
538 | |||
539 | hw_desc = desc->hw_desc; | ||
540 | |||
541 | for (i = 0, j = 0; (slot_cnt -= slots_per_op) >= 0; | ||
542 | i += slots_per_op, j++) { | ||
543 | iter = iop_hw_desc_slot_idx(hw_desc, i); | ||
544 | u_desc_ctrl.value = iop3xx_desc_init_xor(iter, src_cnt, flags); | ||
545 | u_desc_ctrl.field.dest_write_en = 0; | ||
546 | u_desc_ctrl.field.zero_result_en = 1; | ||
547 | u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; | ||
548 | iter->desc_ctrl = u_desc_ctrl.value; | ||
549 | |||
550 | /* for the subsequent descriptors preserve the store queue | ||
551 | * and chain them together | ||
552 | */ | ||
553 | if (i) { | ||
554 | prev_hw_desc = | ||
555 | iop_hw_desc_slot_idx(hw_desc, i - slots_per_op); | ||
556 | prev_hw_desc->next_desc = | ||
557 | (u32) (desc->async_tx.phys + (i << 5)); | ||
558 | } | ||
559 | } | ||
560 | |||
561 | return j; | ||
562 | } | ||
563 | |||
564 | static inline void | ||
565 | iop_desc_init_null_xor(struct iop_adma_desc_slot *desc, int src_cnt, | ||
566 | unsigned long flags) | ||
567 | { | ||
568 | struct iop3xx_desc_aau *hw_desc = desc->hw_desc; | ||
569 | union { | ||
570 | u32 value; | ||
571 | struct iop3xx_aau_desc_ctrl field; | ||
572 | } u_desc_ctrl; | ||
573 | |||
574 | u_desc_ctrl.value = 0; | ||
575 | switch (src_cnt) { | ||
576 | case 25 ... 32: | ||
577 | u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */ | ||
578 | hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0; | ||
579 | /* fall through */ | ||
580 | case 17 ... 24: | ||
581 | if (!u_desc_ctrl.field.blk_ctrl) { | ||
582 | hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0; | ||
583 | u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */ | ||
584 | } | ||
585 | hw_desc->src_edc[AAU_EDCR1_IDX].e_desc_ctrl = 0; | ||
586 | /* fall through */ | ||
587 | case 9 ... 16: | ||
588 | if (!u_desc_ctrl.field.blk_ctrl) | ||
589 | u_desc_ctrl.field.blk_ctrl = 0x2; /* use EDCR0 */ | ||
590 | hw_desc->src_edc[AAU_EDCR0_IDX].e_desc_ctrl = 0; | ||
591 | /* fall through */ | ||
592 | case 1 ... 8: | ||
593 | if (!u_desc_ctrl.field.blk_ctrl && src_cnt > 4) | ||
594 | u_desc_ctrl.field.blk_ctrl = 0x1; /* use mini-desc */ | ||
595 | } | ||
596 | |||
597 | u_desc_ctrl.field.dest_write_en = 0; | ||
598 | u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; | ||
599 | hw_desc->desc_ctrl = u_desc_ctrl.value; | ||
600 | } | ||
601 | |||
602 | static inline void iop_desc_set_byte_count(struct iop_adma_desc_slot *desc, | ||
603 | struct iop_adma_chan *chan, | ||
604 | u32 byte_count) | ||
605 | { | ||
606 | union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; | ||
607 | |||
608 | switch (chan->device->id) { | ||
609 | case DMA0_ID: | ||
610 | case DMA1_ID: | ||
611 | hw_desc.dma->byte_count = byte_count; | ||
612 | break; | ||
613 | case AAU_ID: | ||
614 | hw_desc.aau->byte_count = byte_count; | ||
615 | break; | ||
616 | default: | ||
617 | BUG(); | ||
618 | } | ||
619 | } | ||
620 | |||
621 | static inline void | ||
622 | iop_desc_init_interrupt(struct iop_adma_desc_slot *desc, | ||
623 | struct iop_adma_chan *chan) | ||
624 | { | ||
625 | union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; | ||
626 | |||
627 | switch (chan->device->id) { | ||
628 | case DMA0_ID: | ||
629 | case DMA1_ID: | ||
630 | iop_desc_init_memcpy(desc, 1); | ||
631 | hw_desc.dma->byte_count = 0; | ||
632 | hw_desc.dma->dest_addr = 0; | ||
633 | hw_desc.dma->src_addr = 0; | ||
634 | break; | ||
635 | case AAU_ID: | ||
636 | iop_desc_init_null_xor(desc, 2, 1); | ||
637 | hw_desc.aau->byte_count = 0; | ||
638 | hw_desc.aau->dest_addr = 0; | ||
639 | hw_desc.aau->src[0] = 0; | ||
640 | hw_desc.aau->src[1] = 0; | ||
641 | break; | ||
642 | default: | ||
643 | BUG(); | ||
644 | } | ||
645 | } | ||
646 | |||
647 | static inline void | ||
648 | iop_desc_set_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len) | ||
649 | { | ||
650 | int slots_per_op = desc->slots_per_op; | ||
651 | struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter; | ||
652 | int i = 0; | ||
653 | |||
654 | if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) { | ||
655 | hw_desc->byte_count = len; | ||
656 | } else { | ||
657 | do { | ||
658 | iter = iop_hw_desc_slot_idx(hw_desc, i); | ||
659 | iter->byte_count = IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; | ||
660 | len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; | ||
661 | i += slots_per_op; | ||
662 | } while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT); | ||
663 | |||
664 | if (len) { | ||
665 | iter = iop_hw_desc_slot_idx(hw_desc, i); | ||
666 | iter->byte_count = len; | ||
667 | } | ||
668 | } | ||
669 | } | ||
670 | |||
671 | static inline void iop_desc_set_dest_addr(struct iop_adma_desc_slot *desc, | ||
672 | struct iop_adma_chan *chan, | ||
673 | dma_addr_t addr) | ||
674 | { | ||
675 | union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; | ||
676 | |||
677 | switch (chan->device->id) { | ||
678 | case DMA0_ID: | ||
679 | case DMA1_ID: | ||
680 | hw_desc.dma->dest_addr = addr; | ||
681 | break; | ||
682 | case AAU_ID: | ||
683 | hw_desc.aau->dest_addr = addr; | ||
684 | break; | ||
685 | default: | ||
686 | BUG(); | ||
687 | } | ||
688 | } | ||
689 | |||
690 | static inline void iop_desc_set_memcpy_src_addr(struct iop_adma_desc_slot *desc, | ||
691 | dma_addr_t addr) | ||
692 | { | ||
693 | struct iop3xx_desc_dma *hw_desc = desc->hw_desc; | ||
694 | hw_desc->src_addr = addr; | ||
695 | } | ||
696 | |||
697 | static inline void | ||
698 | iop_desc_set_zero_sum_src_addr(struct iop_adma_desc_slot *desc, int src_idx, | ||
699 | dma_addr_t addr) | ||
700 | { | ||
701 | |||
702 | struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter; | ||
703 | int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op; | ||
704 | int i; | ||
705 | |||
706 | for (i = 0; (slot_cnt -= slots_per_op) >= 0; | ||
707 | i += slots_per_op, addr += IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) { | ||
708 | iter = iop_hw_desc_slot_idx(hw_desc, i); | ||
709 | iop3xx_aau_desc_set_src_addr(iter, src_idx, addr); | ||
710 | } | ||
711 | } | ||
712 | |||
713 | static inline void iop_desc_set_xor_src_addr(struct iop_adma_desc_slot *desc, | ||
714 | int src_idx, dma_addr_t addr) | ||
715 | { | ||
716 | |||
717 | struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter; | ||
718 | int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op; | ||
719 | int i; | ||
720 | |||
721 | for (i = 0; (slot_cnt -= slots_per_op) >= 0; | ||
722 | i += slots_per_op, addr += IOP_ADMA_XOR_MAX_BYTE_COUNT) { | ||
723 | iter = iop_hw_desc_slot_idx(hw_desc, i); | ||
724 | iop3xx_aau_desc_set_src_addr(iter, src_idx, addr); | ||
725 | } | ||
726 | } | ||
727 | |||
728 | static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc, | ||
729 | u32 next_desc_addr) | ||
730 | { | ||
731 | /* hw_desc->next_desc is the same location for all channels */ | ||
732 | union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; | ||
733 | BUG_ON(hw_desc.dma->next_desc); | ||
734 | hw_desc.dma->next_desc = next_desc_addr; | ||
735 | } | ||
736 | |||
737 | static inline u32 iop_desc_get_next_desc(struct iop_adma_desc_slot *desc) | ||
738 | { | ||
739 | /* hw_desc->next_desc is the same location for all channels */ | ||
740 | union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; | ||
741 | return hw_desc.dma->next_desc; | ||
742 | } | ||
743 | |||
744 | static inline void iop_desc_clear_next_desc(struct iop_adma_desc_slot *desc) | ||
745 | { | ||
746 | /* hw_desc->next_desc is the same location for all channels */ | ||
747 | union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; | ||
748 | hw_desc.dma->next_desc = 0; | ||
749 | } | ||
750 | |||
751 | static inline void iop_desc_set_block_fill_val(struct iop_adma_desc_slot *desc, | ||
752 | u32 val) | ||
753 | { | ||
754 | struct iop3xx_desc_aau *hw_desc = desc->hw_desc; | ||
755 | hw_desc->src[0] = val; | ||
756 | } | ||
757 | |||
758 | static inline int iop_desc_get_zero_result(struct iop_adma_desc_slot *desc) | ||
759 | { | ||
760 | struct iop3xx_desc_aau *hw_desc = desc->hw_desc; | ||
761 | struct iop3xx_aau_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field; | ||
762 | |||
763 | BUG_ON(!(desc_ctrl.tx_complete && desc_ctrl.zero_result_en)); | ||
764 | return desc_ctrl.zero_result_err; | ||
765 | } | ||
766 | |||
767 | static inline void iop_chan_append(struct iop_adma_chan *chan) | ||
768 | { | ||
769 | u32 dma_chan_ctrl; | ||
770 | |||
771 | dma_chan_ctrl = __raw_readl(DMA_CCR(chan)); | ||
772 | dma_chan_ctrl |= 0x2; | ||
773 | __raw_writel(dma_chan_ctrl, DMA_CCR(chan)); | ||
774 | } | ||
775 | |||
776 | static inline u32 iop_chan_get_status(struct iop_adma_chan *chan) | ||
777 | { | ||
778 | return __raw_readl(DMA_CSR(chan)); | ||
779 | } | ||
780 | |||
781 | static inline void iop_chan_disable(struct iop_adma_chan *chan) | ||
782 | { | ||
783 | u32 dma_chan_ctrl = __raw_readl(DMA_CCR(chan)); | ||
784 | dma_chan_ctrl &= ~1; | ||
785 | __raw_writel(dma_chan_ctrl, DMA_CCR(chan)); | ||
786 | } | ||
787 | |||
788 | static inline void iop_chan_enable(struct iop_adma_chan *chan) | ||
789 | { | ||
790 | u32 dma_chan_ctrl = __raw_readl(DMA_CCR(chan)); | ||
791 | |||
792 | dma_chan_ctrl |= 1; | ||
793 | __raw_writel(dma_chan_ctrl, DMA_CCR(chan)); | ||
794 | } | ||
795 | |||
796 | static inline void iop_adma_device_clear_eot_status(struct iop_adma_chan *chan) | ||
797 | { | ||
798 | u32 status = __raw_readl(DMA_CSR(chan)); | ||
799 | status &= (1 << 9); | ||
800 | __raw_writel(status, DMA_CSR(chan)); | ||
801 | } | ||
802 | |||
803 | static inline void iop_adma_device_clear_eoc_status(struct iop_adma_chan *chan) | ||
804 | { | ||
805 | u32 status = __raw_readl(DMA_CSR(chan)); | ||
806 | status &= (1 << 8); | ||
807 | __raw_writel(status, DMA_CSR(chan)); | ||
808 | } | ||
809 | |||
810 | static inline void iop_adma_device_clear_err_status(struct iop_adma_chan *chan) | ||
811 | { | ||
812 | u32 status = __raw_readl(DMA_CSR(chan)); | ||
813 | |||
814 | switch (chan->device->id) { | ||
815 | case DMA0_ID: | ||
816 | case DMA1_ID: | ||
817 | status &= (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1); | ||
818 | break; | ||
819 | case AAU_ID: | ||
820 | status &= (1 << 5); | ||
821 | break; | ||
822 | default: | ||
823 | BUG(); | ||
824 | } | ||
825 | |||
826 | __raw_writel(status, DMA_CSR(chan)); | ||
827 | } | ||
828 | |||
829 | static inline int | ||
830 | iop_is_err_int_parity(unsigned long status, struct iop_adma_chan *chan) | ||
831 | { | ||
832 | return 0; | ||
833 | } | ||
834 | |||
835 | static inline int | ||
836 | iop_is_err_mcu_abort(unsigned long status, struct iop_adma_chan *chan) | ||
837 | { | ||
838 | return 0; | ||
839 | } | ||
840 | |||
841 | static inline int | ||
842 | iop_is_err_int_tabort(unsigned long status, struct iop_adma_chan *chan) | ||
843 | { | ||
844 | return 0; | ||
845 | } | ||
846 | |||
847 | static inline int | ||
848 | iop_is_err_int_mabort(unsigned long status, struct iop_adma_chan *chan) | ||
849 | { | ||
850 | return test_bit(5, &status); | ||
851 | } | ||
852 | |||
853 | static inline int | ||
854 | iop_is_err_pci_tabort(unsigned long status, struct iop_adma_chan *chan) | ||
855 | { | ||
856 | switch (chan->device->id) { | ||
857 | case DMA0_ID: | ||
858 | case DMA1_ID: | ||
859 | return test_bit(2, &status); | ||
860 | default: | ||
861 | return 0; | ||
862 | } | ||
863 | } | ||
864 | |||
865 | static inline int | ||
866 | iop_is_err_pci_mabort(unsigned long status, struct iop_adma_chan *chan) | ||
867 | { | ||
868 | switch (chan->device->id) { | ||
869 | case DMA0_ID: | ||
870 | case DMA1_ID: | ||
871 | return test_bit(3, &status); | ||
872 | default: | ||
873 | return 0; | ||
874 | } | ||
875 | } | ||
876 | |||
877 | static inline int | ||
878 | iop_is_err_split_tx(unsigned long status, struct iop_adma_chan *chan) | ||
879 | { | ||
880 | switch (chan->device->id) { | ||
881 | case DMA0_ID: | ||
882 | case DMA1_ID: | ||
883 | return test_bit(1, &status); | ||
884 | default: | ||
885 | return 0; | ||
886 | } | ||
887 | } | ||
888 | #endif /* _ADMA_H */ | ||
diff --git a/arch/arm/include/asm/hardware/iop3xx-gpio.h b/arch/arm/include/asm/hardware/iop3xx-gpio.h new file mode 100644 index 000000000000..222e74b7c463 --- /dev/null +++ b/arch/arm/include/asm/hardware/iop3xx-gpio.h | |||
@@ -0,0 +1,73 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/hardware/iop3xx-gpio.h | ||
3 | * | ||
4 | * IOP3xx GPIO wrappers | ||
5 | * | ||
6 | * Copyright (c) 2008 Arnaud Patard <arnaud.patard@rtp-net.org> | ||
7 | * Based on IXP4XX gpio.h file | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License, or | ||
12 | * (at your option) any later version. | ||
13 | * | ||
14 | * This program is distributed in the hope that it will be useful, | ||
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
17 | * GNU General Public License for more details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this program; if not, write to the Free Software | ||
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
22 | * | ||
23 | */ | ||
24 | |||
25 | #ifndef __ASM_ARM_HARDWARE_IOP3XX_GPIO_H | ||
26 | #define __ASM_ARM_HARDWARE_IOP3XX_GPIO_H | ||
27 | |||
28 | #include <asm/hardware.h> | ||
29 | #include <asm-generic/gpio.h> | ||
30 | |||
31 | #define IOP3XX_N_GPIOS 8 | ||
32 | |||
33 | static inline int gpio_get_value(unsigned gpio) | ||
34 | { | ||
35 | if (gpio > IOP3XX_N_GPIOS) | ||
36 | return __gpio_get_value(gpio); | ||
37 | |||
38 | return gpio_line_get(gpio); | ||
39 | } | ||
40 | |||
41 | static inline void gpio_set_value(unsigned gpio, int value) | ||
42 | { | ||
43 | if (gpio > IOP3XX_N_GPIOS) { | ||
44 | __gpio_set_value(gpio, value); | ||
45 | return; | ||
46 | } | ||
47 | gpio_line_set(gpio, value); | ||
48 | } | ||
49 | |||
50 | static inline int gpio_cansleep(unsigned gpio) | ||
51 | { | ||
52 | if (gpio < IOP3XX_N_GPIOS) | ||
53 | return 0; | ||
54 | else | ||
55 | return __gpio_cansleep(gpio); | ||
56 | } | ||
57 | |||
58 | /* | ||
59 | * The GPIOs are not generating any interrupt | ||
60 | * Note : manuals are not clear about this | ||
61 | */ | ||
62 | static inline int gpio_to_irq(int gpio) | ||
63 | { | ||
64 | return -EINVAL; | ||
65 | } | ||
66 | |||
67 | static inline int irq_to_gpio(int gpio) | ||
68 | { | ||
69 | return -EINVAL; | ||
70 | } | ||
71 | |||
72 | #endif | ||
73 | |||
diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h new file mode 100644 index 000000000000..4b8e7f559929 --- /dev/null +++ b/arch/arm/include/asm/hardware/iop3xx.h | |||
@@ -0,0 +1,312 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/hardware/iop3xx.h | ||
3 | * | ||
4 | * Intel IOP32X and IOP33X register definitions | ||
5 | * | ||
6 | * Author: Rory Bolt <rorybolt@pacbell.net> | ||
7 | * Copyright (C) 2002 Rory Bolt | ||
8 | * Copyright (C) 2004 Intel Corp. | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #ifndef __IOP3XX_H | ||
16 | #define __IOP3XX_H | ||
17 | |||
18 | /* | ||
19 | * IOP3XX GPIO handling | ||
20 | */ | ||
21 | #define GPIO_IN 0 | ||
22 | #define GPIO_OUT 1 | ||
23 | #define GPIO_LOW 0 | ||
24 | #define GPIO_HIGH 1 | ||
25 | #define IOP3XX_GPIO_LINE(x) (x) | ||
26 | |||
27 | #ifndef __ASSEMBLY__ | ||
28 | extern void gpio_line_config(int line, int direction); | ||
29 | extern int gpio_line_get(int line); | ||
30 | extern void gpio_line_set(int line, int value); | ||
31 | extern int init_atu; | ||
32 | extern int iop3xx_get_init_atu(void); | ||
33 | #endif | ||
34 | |||
35 | |||
36 | /* | ||
37 | * IOP3XX processor registers | ||
38 | */ | ||
39 | #define IOP3XX_PERIPHERAL_PHYS_BASE 0xffffe000 | ||
40 | #define IOP3XX_PERIPHERAL_VIRT_BASE 0xfeffe000 | ||
41 | #define IOP3XX_PERIPHERAL_SIZE 0x00002000 | ||
42 | #define IOP3XX_PERIPHERAL_UPPER_PA (IOP3XX_PERIPHERAL_PHYS_BASE +\ | ||
43 | IOP3XX_PERIPHERAL_SIZE - 1) | ||
44 | #define IOP3XX_PERIPHERAL_UPPER_VA (IOP3XX_PERIPHERAL_VIRT_BASE +\ | ||
45 | IOP3XX_PERIPHERAL_SIZE - 1) | ||
46 | #define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) (addr) -\ | ||
47 | (IOP3XX_PERIPHERAL_PHYS_BASE\ | ||
48 | - IOP3XX_PERIPHERAL_VIRT_BASE)) | ||
49 | #define IOP3XX_REG_ADDR(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + (reg)) | ||
50 | |||
51 | /* Address Translation Unit */ | ||
52 | #define IOP3XX_ATUVID (volatile u16 *)IOP3XX_REG_ADDR(0x0100) | ||
53 | #define IOP3XX_ATUDID (volatile u16 *)IOP3XX_REG_ADDR(0x0102) | ||
54 | #define IOP3XX_ATUCMD (volatile u16 *)IOP3XX_REG_ADDR(0x0104) | ||
55 | #define IOP3XX_ATUSR (volatile u16 *)IOP3XX_REG_ADDR(0x0106) | ||
56 | #define IOP3XX_ATURID (volatile u8 *)IOP3XX_REG_ADDR(0x0108) | ||
57 | #define IOP3XX_ATUCCR (volatile u32 *)IOP3XX_REG_ADDR(0x0109) | ||
58 | #define IOP3XX_ATUCLSR (volatile u8 *)IOP3XX_REG_ADDR(0x010c) | ||
59 | #define IOP3XX_ATULT (volatile u8 *)IOP3XX_REG_ADDR(0x010d) | ||
60 | #define IOP3XX_ATUHTR (volatile u8 *)IOP3XX_REG_ADDR(0x010e) | ||
61 | #define IOP3XX_ATUBIST (volatile u8 *)IOP3XX_REG_ADDR(0x010f) | ||
62 | #define IOP3XX_IABAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0110) | ||
63 | #define IOP3XX_IAUBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0114) | ||
64 | #define IOP3XX_IABAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0118) | ||
65 | #define IOP3XX_IAUBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x011c) | ||
66 | #define IOP3XX_IABAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0120) | ||
67 | #define IOP3XX_IAUBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0124) | ||
68 | #define IOP3XX_ASVIR (volatile u16 *)IOP3XX_REG_ADDR(0x012c) | ||
69 | #define IOP3XX_ASIR (volatile u16 *)IOP3XX_REG_ADDR(0x012e) | ||
70 | #define IOP3XX_ERBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0130) | ||
71 | #define IOP3XX_ATUILR (volatile u8 *)IOP3XX_REG_ADDR(0x013c) | ||
72 | #define IOP3XX_ATUIPR (volatile u8 *)IOP3XX_REG_ADDR(0x013d) | ||
73 | #define IOP3XX_ATUMGNT (volatile u8 *)IOP3XX_REG_ADDR(0x013e) | ||
74 | #define IOP3XX_ATUMLAT (volatile u8 *)IOP3XX_REG_ADDR(0x013f) | ||
75 | #define IOP3XX_IALR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0140) | ||
76 | #define IOP3XX_IATVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0144) | ||
77 | #define IOP3XX_ERLR (volatile u32 *)IOP3XX_REG_ADDR(0x0148) | ||
78 | #define IOP3XX_ERTVR (volatile u32 *)IOP3XX_REG_ADDR(0x014c) | ||
79 | #define IOP3XX_IALR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0150) | ||
80 | #define IOP3XX_IALR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0154) | ||
81 | #define IOP3XX_IATVR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0158) | ||
82 | #define IOP3XX_OIOWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x015c) | ||
83 | #define IOP3XX_OMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0160) | ||
84 | #define IOP3XX_OUMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0164) | ||
85 | #define IOP3XX_OMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0168) | ||
86 | #define IOP3XX_OUMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x016c) | ||
87 | #define IOP3XX_OUDWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x0178) | ||
88 | #define IOP3XX_ATUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0180) | ||
89 | #define IOP3XX_PCSR (volatile u32 *)IOP3XX_REG_ADDR(0x0184) | ||
90 | #define IOP3XX_ATUISR (volatile u32 *)IOP3XX_REG_ADDR(0x0188) | ||
91 | #define IOP3XX_ATUIMR (volatile u32 *)IOP3XX_REG_ADDR(0x018c) | ||
92 | #define IOP3XX_IABAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0190) | ||
93 | #define IOP3XX_IAUBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0194) | ||
94 | #define IOP3XX_IALR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0198) | ||
95 | #define IOP3XX_IATVR3 (volatile u32 *)IOP3XX_REG_ADDR(0x019c) | ||
96 | #define IOP3XX_OCCAR (volatile u32 *)IOP3XX_REG_ADDR(0x01a4) | ||
97 | #define IOP3XX_OCCDR (volatile u32 *)IOP3XX_REG_ADDR(0x01ac) | ||
98 | #define IOP3XX_PDSCR (volatile u32 *)IOP3XX_REG_ADDR(0x01bc) | ||
99 | #define IOP3XX_PMCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01c0) | ||
100 | #define IOP3XX_PMNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01c1) | ||
101 | #define IOP3XX_APMCR (volatile u16 *)IOP3XX_REG_ADDR(0x01c2) | ||
102 | #define IOP3XX_APMCSR (volatile u16 *)IOP3XX_REG_ADDR(0x01c4) | ||
103 | #define IOP3XX_PCIXCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01e0) | ||
104 | #define IOP3XX_PCIXNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01e1) | ||
105 | #define IOP3XX_PCIXCMD (volatile u16 *)IOP3XX_REG_ADDR(0x01e2) | ||
106 | #define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4) | ||
107 | #define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec) | ||
108 | #define IOP3XX_PCSR_OUT_Q_BUSY (1 << 15) | ||
109 | #define IOP3XX_PCSR_IN_Q_BUSY (1 << 14) | ||
110 | #define IOP3XX_ATUCR_OUT_EN (1 << 1) | ||
111 | |||
112 | #define IOP3XX_INIT_ATU_DEFAULT 0 | ||
113 | #define IOP3XX_INIT_ATU_DISABLE -1 | ||
114 | #define IOP3XX_INIT_ATU_ENABLE 1 | ||
115 | |||
116 | /* Messaging Unit */ | ||
117 | #define IOP3XX_IMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0310) | ||
118 | #define IOP3XX_IMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0314) | ||
119 | #define IOP3XX_OMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0318) | ||
120 | #define IOP3XX_OMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x031c) | ||
121 | #define IOP3XX_IDR (volatile u32 *)IOP3XX_REG_ADDR(0x0320) | ||
122 | #define IOP3XX_IISR (volatile u32 *)IOP3XX_REG_ADDR(0x0324) | ||
123 | #define IOP3XX_IIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0328) | ||
124 | #define IOP3XX_ODR (volatile u32 *)IOP3XX_REG_ADDR(0x032c) | ||
125 | #define IOP3XX_OISR (volatile u32 *)IOP3XX_REG_ADDR(0x0330) | ||
126 | #define IOP3XX_OIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0334) | ||
127 | #define IOP3XX_MUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0350) | ||
128 | #define IOP3XX_QBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0354) | ||
129 | #define IOP3XX_IFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0360) | ||
130 | #define IOP3XX_IFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0364) | ||
131 | #define IOP3XX_IPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0368) | ||
132 | #define IOP3XX_IPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x036c) | ||
133 | #define IOP3XX_OFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0370) | ||
134 | #define IOP3XX_OFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0374) | ||
135 | #define IOP3XX_OPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0378) | ||
136 | #define IOP3XX_OPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x037c) | ||
137 | #define IOP3XX_IAR (volatile u32 *)IOP3XX_REG_ADDR(0x0380) | ||
138 | |||
139 | /* DMA Controller */ | ||
140 | #define IOP3XX_DMA_PHYS_BASE(chan) (IOP3XX_PERIPHERAL_PHYS_BASE + \ | ||
141 | (0x400 + (chan << 6))) | ||
142 | #define IOP3XX_DMA_UPPER_PA(chan) (IOP3XX_DMA_PHYS_BASE(chan) + 0x27) | ||
143 | |||
144 | /* Peripheral bus interface */ | ||
145 | #define IOP3XX_PBCR (volatile u32 *)IOP3XX_REG_ADDR(0x0680) | ||
146 | #define IOP3XX_PBISR (volatile u32 *)IOP3XX_REG_ADDR(0x0684) | ||
147 | #define IOP3XX_PBBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0688) | ||
148 | #define IOP3XX_PBLR0 (volatile u32 *)IOP3XX_REG_ADDR(0x068c) | ||
149 | #define IOP3XX_PBBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0690) | ||
150 | #define IOP3XX_PBLR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0694) | ||
151 | #define IOP3XX_PBBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0698) | ||
152 | #define IOP3XX_PBLR2 (volatile u32 *)IOP3XX_REG_ADDR(0x069c) | ||
153 | #define IOP3XX_PBBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a0) | ||
154 | #define IOP3XX_PBLR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a4) | ||
155 | #define IOP3XX_PBBAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06a8) | ||
156 | #define IOP3XX_PBLR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06ac) | ||
157 | #define IOP3XX_PBBAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b0) | ||
158 | #define IOP3XX_PBLR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b4) | ||
159 | #define IOP3XX_PMBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x06c0) | ||
160 | #define IOP3XX_PMBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x06e0) | ||
161 | #define IOP3XX_PMBR2 (volatile u32 *)IOP3XX_REG_ADDR(0x06e4) | ||
162 | |||
163 | /* Peripheral performance monitoring unit */ | ||
164 | #define IOP3XX_GTMR (volatile u32 *)IOP3XX_REG_ADDR(0x0700) | ||
165 | #define IOP3XX_ESR (volatile u32 *)IOP3XX_REG_ADDR(0x0704) | ||
166 | #define IOP3XX_EMISR (volatile u32 *)IOP3XX_REG_ADDR(0x0708) | ||
167 | #define IOP3XX_GTSR (volatile u32 *)IOP3XX_REG_ADDR(0x0710) | ||
168 | /* PERCR0 DOESN'T EXIST - index from 1! */ | ||
169 | #define IOP3XX_PERCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0710) | ||
170 | |||
171 | /* General Purpose I/O */ | ||
172 | #define IOP3XX_GPOE (volatile u32 *)IOP3XX_GPIO_REG(0x0000) | ||
173 | #define IOP3XX_GPID (volatile u32 *)IOP3XX_GPIO_REG(0x0004) | ||
174 | #define IOP3XX_GPOD (volatile u32 *)IOP3XX_GPIO_REG(0x0008) | ||
175 | |||
176 | /* Timers */ | ||
177 | #define IOP3XX_TU_TMR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0000) | ||
178 | #define IOP3XX_TU_TMR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0004) | ||
179 | #define IOP3XX_TU_TCR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0008) | ||
180 | #define IOP3XX_TU_TCR1 (volatile u32 *)IOP3XX_TIMER_REG(0x000c) | ||
181 | #define IOP3XX_TU_TRR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0010) | ||
182 | #define IOP3XX_TU_TRR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0014) | ||
183 | #define IOP3XX_TU_TISR (volatile u32 *)IOP3XX_TIMER_REG(0x0018) | ||
184 | #define IOP3XX_TU_WDTCR (volatile u32 *)IOP3XX_TIMER_REG(0x001c) | ||
185 | #define IOP_TMR_EN 0x02 | ||
186 | #define IOP_TMR_RELOAD 0x04 | ||
187 | #define IOP_TMR_PRIVILEGED 0x08 | ||
188 | #define IOP_TMR_RATIO_1_1 0x00 | ||
189 | |||
190 | /* Watchdog timer definitions */ | ||
191 | #define IOP_WDTCR_EN_ARM 0x1e1e1e1e | ||
192 | #define IOP_WDTCR_EN 0xe1e1e1e1 | ||
193 | /* iop3xx does not support stopping the watchdog, so we just re-arm */ | ||
194 | #define IOP_WDTCR_DIS_ARM (IOP_WDTCR_EN_ARM) | ||
195 | #define IOP_WDTCR_DIS (IOP_WDTCR_EN) | ||
196 | |||
197 | /* Application accelerator unit */ | ||
198 | #define IOP3XX_AAU_PHYS_BASE (IOP3XX_PERIPHERAL_PHYS_BASE + 0x800) | ||
199 | #define IOP3XX_AAU_UPPER_PA (IOP3XX_AAU_PHYS_BASE + 0xa7) | ||
200 | |||
201 | /* I2C bus interface unit */ | ||
202 | #define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680) | ||
203 | #define IOP3XX_ISR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1684) | ||
204 | #define IOP3XX_ISAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1688) | ||
205 | #define IOP3XX_IDBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x168c) | ||
206 | #define IOP3XX_IBMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1694) | ||
207 | #define IOP3XX_ICR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a0) | ||
208 | #define IOP3XX_ISR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a4) | ||
209 | #define IOP3XX_ISAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a8) | ||
210 | #define IOP3XX_IDBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16ac) | ||
211 | #define IOP3XX_IBMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16b4) | ||
212 | |||
213 | |||
214 | /* | ||
215 | * IOP3XX I/O and Mem space regions for PCI autoconfiguration | ||
216 | */ | ||
217 | #define IOP3XX_PCI_LOWER_MEM_PA 0x80000000 | ||
218 | |||
219 | #define IOP3XX_PCI_IO_WINDOW_SIZE 0x00010000 | ||
220 | #define IOP3XX_PCI_LOWER_IO_PA 0x90000000 | ||
221 | #define IOP3XX_PCI_LOWER_IO_VA 0xfe000000 | ||
222 | #define IOP3XX_PCI_LOWER_IO_BA 0x90000000 | ||
223 | #define IOP3XX_PCI_UPPER_IO_PA (IOP3XX_PCI_LOWER_IO_PA +\ | ||
224 | IOP3XX_PCI_IO_WINDOW_SIZE - 1) | ||
225 | #define IOP3XX_PCI_UPPER_IO_VA (IOP3XX_PCI_LOWER_IO_VA +\ | ||
226 | IOP3XX_PCI_IO_WINDOW_SIZE - 1) | ||
227 | #define IOP3XX_PCI_IO_PHYS_TO_VIRT(addr) (((u32) (addr) -\ | ||
228 | IOP3XX_PCI_LOWER_IO_PA) +\ | ||
229 | IOP3XX_PCI_LOWER_IO_VA) | ||
230 | |||
231 | |||
232 | #ifndef __ASSEMBLY__ | ||
233 | void iop3xx_map_io(void); | ||
234 | void iop_init_cp6_handler(void); | ||
235 | void iop_init_time(unsigned long tickrate); | ||
236 | unsigned long iop_gettimeoffset(void); | ||
237 | |||
238 | static inline void write_tmr0(u32 val) | ||
239 | { | ||
240 | asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (val)); | ||
241 | } | ||
242 | |||
243 | static inline void write_tmr1(u32 val) | ||
244 | { | ||
245 | asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (val)); | ||
246 | } | ||
247 | |||
248 | static inline u32 read_tcr0(void) | ||
249 | { | ||
250 | u32 val; | ||
251 | asm volatile("mrc p6, 0, %0, c2, c1, 0" : "=r" (val)); | ||
252 | return val; | ||
253 | } | ||
254 | |||
255 | static inline u32 read_tcr1(void) | ||
256 | { | ||
257 | u32 val; | ||
258 | asm volatile("mrc p6, 0, %0, c3, c1, 0" : "=r" (val)); | ||
259 | return val; | ||
260 | } | ||
261 | |||
262 | static inline void write_trr0(u32 val) | ||
263 | { | ||
264 | asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val)); | ||
265 | } | ||
266 | |||
267 | static inline void write_trr1(u32 val) | ||
268 | { | ||
269 | asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (val)); | ||
270 | } | ||
271 | |||
272 | static inline void write_tisr(u32 val) | ||
273 | { | ||
274 | asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val)); | ||
275 | } | ||
276 | |||
277 | static inline u32 read_wdtcr(void) | ||
278 | { | ||
279 | u32 val; | ||
280 | asm volatile("mrc p6, 0, %0, c7, c1, 0":"=r" (val)); | ||
281 | return val; | ||
282 | } | ||
283 | static inline void write_wdtcr(u32 val) | ||
284 | { | ||
285 | asm volatile("mcr p6, 0, %0, c7, c1, 0"::"r" (val)); | ||
286 | } | ||
287 | |||
288 | extern unsigned long get_iop_tick_rate(void); | ||
289 | |||
290 | /* only iop13xx has these registers, we define these to present a | ||
291 | * common register interface for the iop_wdt driver. | ||
292 | */ | ||
293 | #define IOP_RCSR_WDT (0) | ||
294 | static inline u32 read_rcsr(void) | ||
295 | { | ||
296 | return 0; | ||
297 | } | ||
298 | static inline void write_wdtsr(u32 val) | ||
299 | { | ||
300 | do { } while (0); | ||
301 | } | ||
302 | |||
303 | extern struct platform_device iop3xx_dma_0_channel; | ||
304 | extern struct platform_device iop3xx_dma_1_channel; | ||
305 | extern struct platform_device iop3xx_aau_channel; | ||
306 | extern struct platform_device iop3xx_i2c0_device; | ||
307 | extern struct platform_device iop3xx_i2c1_device; | ||
308 | |||
309 | #endif | ||
310 | |||
311 | |||
312 | #endif | ||
diff --git a/arch/arm/include/asm/hardware/iop_adma.h b/arch/arm/include/asm/hardware/iop_adma.h new file mode 100644 index 000000000000..cb7e3611bcba --- /dev/null +++ b/arch/arm/include/asm/hardware/iop_adma.h | |||
@@ -0,0 +1,116 @@ | |||
1 | /* | ||
2 | * Copyright © 2006, Intel Corporation. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License along with | ||
14 | * this program; if not, write to the Free Software Foundation, Inc., | ||
15 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | ||
16 | * | ||
17 | */ | ||
18 | #ifndef IOP_ADMA_H | ||
19 | #define IOP_ADMA_H | ||
20 | #include <linux/types.h> | ||
21 | #include <linux/dmaengine.h> | ||
22 | #include <linux/interrupt.h> | ||
23 | |||
24 | #define IOP_ADMA_SLOT_SIZE 32 | ||
25 | #define IOP_ADMA_THRESHOLD 4 | ||
26 | |||
27 | /** | ||
28 | * struct iop_adma_device - internal representation of an ADMA device | ||
29 | * @pdev: Platform device | ||
30 | * @id: HW ADMA Device selector | ||
31 | * @dma_desc_pool: base of DMA descriptor region (DMA address) | ||
32 | * @dma_desc_pool_virt: base of DMA descriptor region (CPU address) | ||
33 | * @common: embedded struct dma_device | ||
34 | */ | ||
35 | struct iop_adma_device { | ||
36 | struct platform_device *pdev; | ||
37 | int id; | ||
38 | dma_addr_t dma_desc_pool; | ||
39 | void *dma_desc_pool_virt; | ||
40 | struct dma_device common; | ||
41 | }; | ||
42 | |||
43 | /** | ||
44 | * struct iop_adma_chan - internal representation of an ADMA device | ||
45 | * @pending: allows batching of hardware operations | ||
46 | * @completed_cookie: identifier for the most recently completed operation | ||
47 | * @lock: serializes enqueue/dequeue operations to the slot pool | ||
48 | * @mmr_base: memory mapped register base | ||
49 | * @chain: device chain view of the descriptors | ||
50 | * @device: parent device | ||
51 | * @common: common dmaengine channel object members | ||
52 | * @last_used: place holder for allocation to continue from where it left off | ||
53 | * @all_slots: complete domain of slots usable by the channel | ||
54 | * @slots_allocated: records the actual size of the descriptor slot pool | ||
55 | * @irq_tasklet: bottom half where iop_adma_slot_cleanup runs | ||
56 | */ | ||
57 | struct iop_adma_chan { | ||
58 | int pending; | ||
59 | dma_cookie_t completed_cookie; | ||
60 | spinlock_t lock; /* protects the descriptor slot pool */ | ||
61 | void __iomem *mmr_base; | ||
62 | struct list_head chain; | ||
63 | struct iop_adma_device *device; | ||
64 | struct dma_chan common; | ||
65 | struct iop_adma_desc_slot *last_used; | ||
66 | struct list_head all_slots; | ||
67 | int slots_allocated; | ||
68 | struct tasklet_struct irq_tasklet; | ||
69 | }; | ||
70 | |||
71 | /** | ||
72 | * struct iop_adma_desc_slot - IOP-ADMA software descriptor | ||
73 | * @slot_node: node on the iop_adma_chan.all_slots list | ||
74 | * @chain_node: node on the op_adma_chan.chain list | ||
75 | * @hw_desc: virtual address of the hardware descriptor chain | ||
76 | * @phys: hardware address of the hardware descriptor chain | ||
77 | * @group_head: first operation in a transaction | ||
78 | * @slot_cnt: total slots used in an transaction (group of operations) | ||
79 | * @slots_per_op: number of slots per operation | ||
80 | * @idx: pool index | ||
81 | * @unmap_src_cnt: number of xor sources | ||
82 | * @unmap_len: transaction bytecount | ||
83 | * @async_tx: support for the async_tx api | ||
84 | * @group_list: list of slots that make up a multi-descriptor transaction | ||
85 | * for example transfer lengths larger than the supported hw max | ||
86 | * @xor_check_result: result of zero sum | ||
87 | * @crc32_result: result crc calculation | ||
88 | */ | ||
89 | struct iop_adma_desc_slot { | ||
90 | struct list_head slot_node; | ||
91 | struct list_head chain_node; | ||
92 | void *hw_desc; | ||
93 | struct iop_adma_desc_slot *group_head; | ||
94 | u16 slot_cnt; | ||
95 | u16 slots_per_op; | ||
96 | u16 idx; | ||
97 | u16 unmap_src_cnt; | ||
98 | size_t unmap_len; | ||
99 | struct dma_async_tx_descriptor async_tx; | ||
100 | union { | ||
101 | u32 *xor_check_result; | ||
102 | u32 *crc32_result; | ||
103 | }; | ||
104 | }; | ||
105 | |||
106 | struct iop_adma_platform_data { | ||
107 | int hw_id; | ||
108 | dma_cap_mask_t cap_mask; | ||
109 | size_t pool_size; | ||
110 | }; | ||
111 | |||
112 | #define to_iop_sw_desc(addr_hw_desc) \ | ||
113 | container_of(addr_hw_desc, struct iop_adma_desc_slot, hw_desc) | ||
114 | #define iop_hw_desc_slot_idx(hw_desc, idx) \ | ||
115 | ( (void *) (((unsigned long) hw_desc) + ((idx) << 5)) ) | ||
116 | #endif | ||
diff --git a/arch/arm/include/asm/hardware/it8152.h b/arch/arm/include/asm/hardware/it8152.h new file mode 100644 index 000000000000..74b5fff7f575 --- /dev/null +++ b/arch/arm/include/asm/hardware/it8152.h | |||
@@ -0,0 +1,99 @@ | |||
1 | /* | ||
2 | * linux/include/arm/hardware/it8152.h | ||
3 | * | ||
4 | * Copyright Compulab Ltd., 2006,2007 | ||
5 | * Mike Rapoport <mike@compulab.co.il> | ||
6 | * | ||
7 | * ITE 8152 companion chip register definitions | ||
8 | */ | ||
9 | |||
10 | #ifndef __ASM_HARDWARE_IT8152_H | ||
11 | #define __ASM_HARDWARE_IT8152_H | ||
12 | extern unsigned long it8152_base_address; | ||
13 | |||
14 | #define IT8152_IO_BASE (it8152_base_address + 0x03e00000) | ||
15 | #define IT8152_CFGREG_BASE (it8152_base_address + 0x03f00000) | ||
16 | |||
17 | #define __REG_IT8152(x) (it8152_base_address + (x)) | ||
18 | |||
19 | #define IT8152_PCI_CFG_ADDR __REG_IT8152(0x3f00800) | ||
20 | #define IT8152_PCI_CFG_DATA __REG_IT8152(0x3f00804) | ||
21 | |||
22 | #define IT8152_INTC_LDCNIRR __REG_IT8152(0x3f00300) | ||
23 | #define IT8152_INTC_LDPNIRR __REG_IT8152(0x3f00304) | ||
24 | #define IT8152_INTC_LDCNIMR __REG_IT8152(0x3f00308) | ||
25 | #define IT8152_INTC_LDPNIMR __REG_IT8152(0x3f0030C) | ||
26 | #define IT8152_INTC_LDNITR __REG_IT8152(0x3f00310) | ||
27 | #define IT8152_INTC_LDNIAR __REG_IT8152(0x3f00314) | ||
28 | #define IT8152_INTC_LPCNIRR __REG_IT8152(0x3f00320) | ||
29 | #define IT8152_INTC_LPPNIRR __REG_IT8152(0x3f00324) | ||
30 | #define IT8152_INTC_LPCNIMR __REG_IT8152(0x3f00328) | ||
31 | #define IT8152_INTC_LPPNIMR __REG_IT8152(0x3f0032C) | ||
32 | #define IT8152_INTC_LPNITR __REG_IT8152(0x3f00330) | ||
33 | #define IT8152_INTC_LPNIAR __REG_IT8152(0x3f00334) | ||
34 | #define IT8152_INTC_PDCNIRR __REG_IT8152(0x3f00340) | ||
35 | #define IT8152_INTC_PDPNIRR __REG_IT8152(0x3f00344) | ||
36 | #define IT8152_INTC_PDCNIMR __REG_IT8152(0x3f00348) | ||
37 | #define IT8152_INTC_PDPNIMR __REG_IT8152(0x3f0034C) | ||
38 | #define IT8152_INTC_PDNITR __REG_IT8152(0x3f00350) | ||
39 | #define IT8152_INTC_PDNIAR __REG_IT8152(0x3f00354) | ||
40 | #define IT8152_INTC_INTC_TYPER __REG_IT8152(0x3f003FC) | ||
41 | |||
42 | #define IT8152_GPIO_GPDR __REG_IT8152(0x3f00500) | ||
43 | |||
44 | /* | ||
45 | Interrupt controller per register summary: | ||
46 | --------------------------------------- | ||
47 | LCDNIRR: | ||
48 | IT8152_LD_IRQ(8) PCICLK stop | ||
49 | IT8152_LD_IRQ(7) MCLK ready | ||
50 | IT8152_LD_IRQ(6) s/w | ||
51 | IT8152_LD_IRQ(5) UART | ||
52 | IT8152_LD_IRQ(4) GPIO | ||
53 | IT8152_LD_IRQ(3) TIMER 4 | ||
54 | IT8152_LD_IRQ(2) TIMER 3 | ||
55 | IT8152_LD_IRQ(1) TIMER 2 | ||
56 | IT8152_LD_IRQ(0) TIMER 1 | ||
57 | |||
58 | LPCNIRR: | ||
59 | IT8152_LP_IRQ(x) serial IRQ x | ||
60 | |||
61 | PCIDNIRR: | ||
62 | IT8152_PD_IRQ(14) PCISERR | ||
63 | IT8152_PD_IRQ(13) CPU/PCI bridge target abort (h2pTADR) | ||
64 | IT8152_PD_IRQ(12) CPU/PCI bridge master abort (h2pMADR) | ||
65 | IT8152_PD_IRQ(11) PCI INTD | ||
66 | IT8152_PD_IRQ(10) PCI INTC | ||
67 | IT8152_PD_IRQ(9) PCI INTB | ||
68 | IT8152_PD_IRQ(8) PCI INTA | ||
69 | IT8152_PD_IRQ(7) serial INTD | ||
70 | IT8152_PD_IRQ(6) serial INTC | ||
71 | IT8152_PD_IRQ(5) serial INTB | ||
72 | IT8152_PD_IRQ(4) serial INTA | ||
73 | IT8152_PD_IRQ(3) serial IRQ IOCHK (IOCHKR) | ||
74 | IT8152_PD_IRQ(2) chaining DMA (CDMAR) | ||
75 | IT8152_PD_IRQ(1) USB (USBR) | ||
76 | IT8152_PD_IRQ(0) Audio controller (ACR) | ||
77 | */ | ||
78 | /* frequently used interrupts */ | ||
79 | #define IT8152_PCISERR IT8152_PD_IRQ(14) | ||
80 | #define IT8152_H2PTADR IT8152_PD_IRQ(13) | ||
81 | #define IT8152_H2PMAR IT8152_PD_IRQ(12) | ||
82 | #define IT8152_PCI_INTD IT8152_PD_IRQ(11) | ||
83 | #define IT8152_PCI_INTC IT8152_PD_IRQ(10) | ||
84 | #define IT8152_PCI_INTB IT8152_PD_IRQ(9) | ||
85 | #define IT8152_PCI_INTA IT8152_PD_IRQ(8) | ||
86 | #define IT8152_CDMA_INT IT8152_PD_IRQ(2) | ||
87 | #define IT8152_USB_INT IT8152_PD_IRQ(1) | ||
88 | #define IT8152_AUDIO_INT IT8152_PD_IRQ(0) | ||
89 | |||
90 | struct pci_dev; | ||
91 | struct pci_sys_data; | ||
92 | |||
93 | extern void it8152_irq_demux(unsigned int irq, struct irq_desc *desc); | ||
94 | extern void it8152_init_irq(void); | ||
95 | extern int it8152_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin); | ||
96 | extern int it8152_pci_setup(int nr, struct pci_sys_data *sys); | ||
97 | extern struct pci_bus *it8152_pci_scan_bus(int nr, struct pci_sys_data *sys); | ||
98 | |||
99 | #endif /* __ASM_HARDWARE_IT8152_H */ | ||
diff --git a/arch/arm/include/asm/hardware/linkup-l1110.h b/arch/arm/include/asm/hardware/linkup-l1110.h new file mode 100644 index 000000000000..7ec91168a576 --- /dev/null +++ b/arch/arm/include/asm/hardware/linkup-l1110.h | |||
@@ -0,0 +1,48 @@ | |||
1 | /* | ||
2 | * | ||
3 | * Definitions for H3600 Handheld Computer | ||
4 | * | ||
5 | * Copyright 2001 Compaq Computer Corporation. | ||
6 | * | ||
7 | * Use consistent with the GNU GPL is permitted, | ||
8 | * provided that this copyright notice is | ||
9 | * preserved in its entirety in all copies and derived works. | ||
10 | * | ||
11 | * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, | ||
12 | * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS | ||
13 | * FITNESS FOR ANY PARTICULAR PURPOSE. | ||
14 | * | ||
15 | * Author: Jamey Hicks. | ||
16 | * | ||
17 | */ | ||
18 | |||
19 | /* LinkUp Systems PCCard/CompactFlash Interface for SA-1100 */ | ||
20 | |||
21 | /* PC Card Status Register */ | ||
22 | #define LINKUP_PRS_S1 (1 << 0) /* voltage control bits S1-S4 */ | ||
23 | #define LINKUP_PRS_S2 (1 << 1) | ||
24 | #define LINKUP_PRS_S3 (1 << 2) | ||
25 | #define LINKUP_PRS_S4 (1 << 3) | ||
26 | #define LINKUP_PRS_BVD1 (1 << 4) | ||
27 | #define LINKUP_PRS_BVD2 (1 << 5) | ||
28 | #define LINKUP_PRS_VS1 (1 << 6) | ||
29 | #define LINKUP_PRS_VS2 (1 << 7) | ||
30 | #define LINKUP_PRS_RDY (1 << 8) | ||
31 | #define LINKUP_PRS_CD1 (1 << 9) | ||
32 | #define LINKUP_PRS_CD2 (1 << 10) | ||
33 | |||
34 | /* PC Card Command Register */ | ||
35 | #define LINKUP_PRC_S1 (1 << 0) | ||
36 | #define LINKUP_PRC_S2 (1 << 1) | ||
37 | #define LINKUP_PRC_S3 (1 << 2) | ||
38 | #define LINKUP_PRC_S4 (1 << 3) | ||
39 | #define LINKUP_PRC_RESET (1 << 4) | ||
40 | #define LINKUP_PRC_APOE (1 << 5) /* Auto Power Off Enable: clears S1-S4 when either nCD goes high */ | ||
41 | #define LINKUP_PRC_CFE (1 << 6) /* CompactFlash mode Enable: addresses A[10:0] only, A[25:11] high */ | ||
42 | #define LINKUP_PRC_SOE (1 << 7) /* signal output driver enable */ | ||
43 | #define LINKUP_PRC_SSP (1 << 8) /* sock select polarity: 0 for socket 0, 1 for socket 1 */ | ||
44 | #define LINKUP_PRC_MBZ (1 << 15) /* must be zero */ | ||
45 | |||
46 | struct linkup_l1110 { | ||
47 | volatile short prc; | ||
48 | }; | ||
diff --git a/arch/arm/include/asm/hardware/locomo.h b/arch/arm/include/asm/hardware/locomo.h new file mode 100644 index 000000000000..954b1be991b4 --- /dev/null +++ b/arch/arm/include/asm/hardware/locomo.h | |||
@@ -0,0 +1,217 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/hardware/locomo.h | ||
3 | * | ||
4 | * This file contains the definitions for the LoCoMo G/A Chip | ||
5 | * | ||
6 | * (C) Copyright 2004 John Lenz | ||
7 | * | ||
8 | * May be copied or modified under the terms of the GNU General Public | ||
9 | * License. See linux/COPYING for more information. | ||
10 | * | ||
11 | * Based on sa1111.h | ||
12 | */ | ||
13 | #ifndef _ASM_ARCH_LOCOMO | ||
14 | #define _ASM_ARCH_LOCOMO | ||
15 | |||
16 | #define locomo_writel(val,addr) ({ *(volatile u16 *)(addr) = (val); }) | ||
17 | #define locomo_readl(addr) (*(volatile u16 *)(addr)) | ||
18 | |||
19 | /* LOCOMO version */ | ||
20 | #define LOCOMO_VER 0x00 | ||
21 | |||
22 | /* Pin status */ | ||
23 | #define LOCOMO_ST 0x04 | ||
24 | |||
25 | /* Pin status */ | ||
26 | #define LOCOMO_C32K 0x08 | ||
27 | |||
28 | /* Interrupt controller */ | ||
29 | #define LOCOMO_ICR 0x0C | ||
30 | |||
31 | /* MCS decoder for boot selecting */ | ||
32 | #define LOCOMO_MCSX0 0x10 | ||
33 | #define LOCOMO_MCSX1 0x14 | ||
34 | #define LOCOMO_MCSX2 0x18 | ||
35 | #define LOCOMO_MCSX3 0x1c | ||
36 | |||
37 | /* Touch panel controller */ | ||
38 | #define LOCOMO_ASD 0x20 /* AD start delay */ | ||
39 | #define LOCOMO_HSD 0x28 /* HSYS delay */ | ||
40 | #define LOCOMO_HSC 0x2c /* HSYS period */ | ||
41 | #define LOCOMO_TADC 0x30 /* tablet ADC clock */ | ||
42 | |||
43 | |||
44 | /* Long time timer */ | ||
45 | #define LOCOMO_LTC 0xd8 /* LTC interrupt setting */ | ||
46 | #define LOCOMO_LTINT 0xdc /* LTC interrupt */ | ||
47 | |||
48 | /* DAC control signal for LCD (COMADJ ) */ | ||
49 | #define LOCOMO_DAC 0xe0 | ||
50 | /* DAC control */ | ||
51 | #define LOCOMO_DAC_SCLOEB 0x08 /* SCL pin output data */ | ||
52 | #define LOCOMO_DAC_TEST 0x04 /* Test bit */ | ||
53 | #define LOCOMO_DAC_SDA 0x02 /* SDA pin level (read-only) */ | ||
54 | #define LOCOMO_DAC_SDAOEB 0x01 /* SDA pin output data */ | ||
55 | |||
56 | /* SPI interface */ | ||
57 | #define LOCOMO_SPI 0x60 | ||
58 | #define LOCOMO_SPIMD 0x00 /* SPI mode setting */ | ||
59 | #define LOCOMO_SPICT 0x04 /* SPI mode control */ | ||
60 | #define LOCOMO_SPIST 0x08 /* SPI status */ | ||
61 | #define LOCOMO_SPI_TEND (1 << 3) /* Transfer end bit */ | ||
62 | #define LOCOMO_SPI_REND (1 << 2) /* Receive end bit */ | ||
63 | #define LOCOMO_SPI_RFW (1 << 1) /* write buffer bit */ | ||
64 | #define LOCOMO_SPI_RFR (1) /* read buffer bit */ | ||
65 | |||
66 | #define LOCOMO_SPIIS 0x10 /* SPI interrupt status */ | ||
67 | #define LOCOMO_SPIWE 0x14 /* SPI interrupt status write enable */ | ||
68 | #define LOCOMO_SPIIE 0x18 /* SPI interrupt enable */ | ||
69 | #define LOCOMO_SPIIR 0x1c /* SPI interrupt request */ | ||
70 | #define LOCOMO_SPITD 0x20 /* SPI transfer data write */ | ||
71 | #define LOCOMO_SPIRD 0x24 /* SPI receive data read */ | ||
72 | #define LOCOMO_SPITS 0x28 /* SPI transfer data shift */ | ||
73 | #define LOCOMO_SPIRS 0x2C /* SPI receive data shift */ | ||
74 | |||
75 | /* GPIO */ | ||
76 | #define LOCOMO_GPD 0x90 /* GPIO direction */ | ||
77 | #define LOCOMO_GPE 0x94 /* GPIO input enable */ | ||
78 | #define LOCOMO_GPL 0x98 /* GPIO level */ | ||
79 | #define LOCOMO_GPO 0x9c /* GPIO out data setting */ | ||
80 | #define LOCOMO_GRIE 0xa0 /* GPIO rise detection */ | ||
81 | #define LOCOMO_GFIE 0xa4 /* GPIO fall detection */ | ||
82 | #define LOCOMO_GIS 0xa8 /* GPIO edge detection status */ | ||
83 | #define LOCOMO_GWE 0xac /* GPIO status write enable */ | ||
84 | #define LOCOMO_GIE 0xb0 /* GPIO interrupt enable */ | ||
85 | #define LOCOMO_GIR 0xb4 /* GPIO interrupt request */ | ||
86 | #define LOCOMO_GPIO(Nb) (0x01 << (Nb)) | ||
87 | #define LOCOMO_GPIO_RTS LOCOMO_GPIO(0) | ||
88 | #define LOCOMO_GPIO_CTS LOCOMO_GPIO(1) | ||
89 | #define LOCOMO_GPIO_DSR LOCOMO_GPIO(2) | ||
90 | #define LOCOMO_GPIO_DTR LOCOMO_GPIO(3) | ||
91 | #define LOCOMO_GPIO_LCD_VSHA_ON LOCOMO_GPIO(4) | ||
92 | #define LOCOMO_GPIO_LCD_VSHD_ON LOCOMO_GPIO(5) | ||
93 | #define LOCOMO_GPIO_LCD_VEE_ON LOCOMO_GPIO(6) | ||
94 | #define LOCOMO_GPIO_LCD_MOD LOCOMO_GPIO(7) | ||
95 | #define LOCOMO_GPIO_DAC_ON LOCOMO_GPIO(8) | ||
96 | #define LOCOMO_GPIO_FL_VR LOCOMO_GPIO(9) | ||
97 | #define LOCOMO_GPIO_DAC_SDATA LOCOMO_GPIO(10) | ||
98 | #define LOCOMO_GPIO_DAC_SCK LOCOMO_GPIO(11) | ||
99 | #define LOCOMO_GPIO_DAC_SLOAD LOCOMO_GPIO(12) | ||
100 | #define LOCOMO_GPIO_CARD_DETECT LOCOMO_GPIO(13) | ||
101 | #define LOCOMO_GPIO_WRITE_PROT LOCOMO_GPIO(14) | ||
102 | #define LOCOMO_GPIO_CARD_POWER LOCOMO_GPIO(15) | ||
103 | |||
104 | /* Start the definitions of the devices. Each device has an initial | ||
105 | * base address and a series of offsets from that base address. */ | ||
106 | |||
107 | /* Keyboard controller */ | ||
108 | #define LOCOMO_KEYBOARD 0x40 | ||
109 | #define LOCOMO_KIB 0x00 /* KIB level */ | ||
110 | #define LOCOMO_KSC 0x04 /* KSTRB control */ | ||
111 | #define LOCOMO_KCMD 0x08 /* KSTRB command */ | ||
112 | #define LOCOMO_KIC 0x0c /* Key interrupt */ | ||
113 | |||
114 | /* Front light adjustment controller */ | ||
115 | #define LOCOMO_FRONTLIGHT 0xc8 | ||
116 | #define LOCOMO_ALS 0x00 /* Adjust light cycle */ | ||
117 | #define LOCOMO_ALD 0x04 /* Adjust light duty */ | ||
118 | |||
119 | #define LOCOMO_ALC_EN 0x8000 | ||
120 | |||
121 | /* Backlight controller: TFT signal */ | ||
122 | #define LOCOMO_BACKLIGHT 0x38 | ||
123 | #define LOCOMO_TC 0x00 /* TFT control signal */ | ||
124 | #define LOCOMO_CPSD 0x04 /* CPS delay */ | ||
125 | |||
126 | /* Audio controller */ | ||
127 | #define LOCOMO_AUDIO 0x54 | ||
128 | #define LOCOMO_ACC 0x00 /* Audio clock */ | ||
129 | #define LOCOMO_PAIF 0xD0 /* PCM audio interface */ | ||
130 | /* Audio clock */ | ||
131 | #define LOCOMO_ACC_XON 0x80 | ||
132 | #define LOCOMO_ACC_XEN 0x40 | ||
133 | #define LOCOMO_ACC_XSEL0 0x00 | ||
134 | #define LOCOMO_ACC_XSEL1 0x20 | ||
135 | #define LOCOMO_ACC_MCLKEN 0x10 | ||
136 | #define LOCOMO_ACC_64FSEN 0x08 | ||
137 | #define LOCOMO_ACC_CLKSEL000 0x00 /* mclk 2 */ | ||
138 | #define LOCOMO_ACC_CLKSEL001 0x01 /* mclk 3 */ | ||
139 | #define LOCOMO_ACC_CLKSEL010 0x02 /* mclk 4 */ | ||
140 | #define LOCOMO_ACC_CLKSEL011 0x03 /* mclk 6 */ | ||
141 | #define LOCOMO_ACC_CLKSEL100 0x04 /* mclk 8 */ | ||
142 | #define LOCOMO_ACC_CLKSEL101 0x05 /* mclk 12 */ | ||
143 | /* PCM audio interface */ | ||
144 | #define LOCOMO_PAIF_SCINV 0x20 | ||
145 | #define LOCOMO_PAIF_SCEN 0x10 | ||
146 | #define LOCOMO_PAIF_LRCRST 0x08 | ||
147 | #define LOCOMO_PAIF_LRCEVE 0x04 | ||
148 | #define LOCOMO_PAIF_LRCINV 0x02 | ||
149 | #define LOCOMO_PAIF_LRCEN 0x01 | ||
150 | |||
151 | /* LED controller */ | ||
152 | #define LOCOMO_LED 0xe8 | ||
153 | #define LOCOMO_LPT0 0x00 | ||
154 | #define LOCOMO_LPT1 0x04 | ||
155 | /* LED control */ | ||
156 | #define LOCOMO_LPT_TOFH 0x80 | ||
157 | #define LOCOMO_LPT_TOFL 0x08 | ||
158 | #define LOCOMO_LPT_TOH(TOH) ((TOH & 0x7) << 4) | ||
159 | #define LOCOMO_LPT_TOL(TOL) ((TOL & 0x7)) | ||
160 | |||
161 | extern struct bus_type locomo_bus_type; | ||
162 | |||
163 | #define LOCOMO_DEVID_KEYBOARD 0 | ||
164 | #define LOCOMO_DEVID_FRONTLIGHT 1 | ||
165 | #define LOCOMO_DEVID_BACKLIGHT 2 | ||
166 | #define LOCOMO_DEVID_AUDIO 3 | ||
167 | #define LOCOMO_DEVID_LED 4 | ||
168 | #define LOCOMO_DEVID_UART 5 | ||
169 | #define LOCOMO_DEVID_SPI 6 | ||
170 | |||
171 | struct locomo_dev { | ||
172 | struct device dev; | ||
173 | unsigned int devid; | ||
174 | unsigned int irq[1]; | ||
175 | |||
176 | void *mapbase; | ||
177 | unsigned long length; | ||
178 | |||
179 | u64 dma_mask; | ||
180 | }; | ||
181 | |||
182 | #define LOCOMO_DEV(_d) container_of((_d), struct locomo_dev, dev) | ||
183 | |||
184 | #define locomo_get_drvdata(d) dev_get_drvdata(&(d)->dev) | ||
185 | #define locomo_set_drvdata(d,p) dev_set_drvdata(&(d)->dev, p) | ||
186 | |||
187 | struct locomo_driver { | ||
188 | struct device_driver drv; | ||
189 | unsigned int devid; | ||
190 | int (*probe)(struct locomo_dev *); | ||
191 | int (*remove)(struct locomo_dev *); | ||
192 | int (*suspend)(struct locomo_dev *, pm_message_t); | ||
193 | int (*resume)(struct locomo_dev *); | ||
194 | }; | ||
195 | |||
196 | #define LOCOMO_DRV(_d) container_of((_d), struct locomo_driver, drv) | ||
197 | |||
198 | #define LOCOMO_DRIVER_NAME(_ldev) ((_ldev)->dev.driver->name) | ||
199 | |||
200 | void locomo_lcd_power(struct locomo_dev *, int, unsigned int); | ||
201 | |||
202 | int locomo_driver_register(struct locomo_driver *); | ||
203 | void locomo_driver_unregister(struct locomo_driver *); | ||
204 | |||
205 | /* GPIO control functions */ | ||
206 | void locomo_gpio_set_dir(struct device *dev, unsigned int bits, unsigned int dir); | ||
207 | int locomo_gpio_read_level(struct device *dev, unsigned int bits); | ||
208 | int locomo_gpio_read_output(struct device *dev, unsigned int bits); | ||
209 | void locomo_gpio_write(struct device *dev, unsigned int bits, unsigned int set); | ||
210 | |||
211 | /* M62332 control function */ | ||
212 | void locomo_m62332_senddata(struct locomo_dev *ldev, unsigned int dac_data, int channel); | ||
213 | |||
214 | /* Frontlight control */ | ||
215 | void locomo_frontlight_set(struct locomo_dev *dev, int duty, int vr, int bpwf); | ||
216 | |||
217 | #endif | ||
diff --git a/arch/arm/include/asm/hardware/memc.h b/arch/arm/include/asm/hardware/memc.h new file mode 100644 index 000000000000..42ba7c167d1f --- /dev/null +++ b/arch/arm/include/asm/hardware/memc.h | |||
@@ -0,0 +1,26 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/hardware/memc.h | ||
3 | * | ||
4 | * Copyright (C) Russell King. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #define VDMA_ALIGNMENT PAGE_SIZE | ||
11 | #define VDMA_XFERSIZE 16 | ||
12 | #define VDMA_INIT 0 | ||
13 | #define VDMA_START 1 | ||
14 | #define VDMA_END 2 | ||
15 | |||
16 | #ifndef __ASSEMBLY__ | ||
17 | extern void memc_write(unsigned int reg, unsigned long val); | ||
18 | |||
19 | #define video_set_dma(start,end,offset) \ | ||
20 | do { \ | ||
21 | memc_write (VDMA_START, (start >> 2)); \ | ||
22 | memc_write (VDMA_END, (end - VDMA_XFERSIZE) >> 2); \ | ||
23 | memc_write (VDMA_INIT, (offset >> 2)); \ | ||
24 | } while (0) | ||
25 | |||
26 | #endif | ||
diff --git a/arch/arm/include/asm/hardware/pci_v3.h b/arch/arm/include/asm/hardware/pci_v3.h new file mode 100644 index 000000000000..2811c7e2cfdf --- /dev/null +++ b/arch/arm/include/asm/hardware/pci_v3.h | |||
@@ -0,0 +1,186 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/hardware/pci_v3.h | ||
3 | * | ||
4 | * Internal header file PCI V3 chip | ||
5 | * | ||
6 | * Copyright (C) ARM Limited | ||
7 | * Copyright (C) 2000-2001 Deep Blue Solutions Ltd. | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License, or | ||
12 | * (at your option) any later version. | ||
13 | * | ||
14 | * This program is distributed in the hope that it will be useful, | ||
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
17 | * GNU General Public License for more details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this program; if not, write to the Free Software | ||
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
22 | */ | ||
23 | #ifndef ASM_ARM_HARDWARE_PCI_V3_H | ||
24 | #define ASM_ARM_HARDWARE_PCI_V3_H | ||
25 | |||
26 | /* ------------------------------------------------------------------------------- | ||
27 | * V3 Local Bus to PCI Bridge definitions | ||
28 | * ------------------------------------------------------------------------------- | ||
29 | * Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04 | ||
30 | * All V3 register names are prefaced by V3_ to avoid clashing with any other | ||
31 | * PCI definitions. Their names match the user's manual. | ||
32 | * | ||
33 | * I'm assuming that I20 is disabled. | ||
34 | * | ||
35 | */ | ||
36 | #define V3_PCI_VENDOR 0x00000000 | ||
37 | #define V3_PCI_DEVICE 0x00000002 | ||
38 | #define V3_PCI_CMD 0x00000004 | ||
39 | #define V3_PCI_STAT 0x00000006 | ||
40 | #define V3_PCI_CC_REV 0x00000008 | ||
41 | #define V3_PCI_HDR_CFG 0x0000000C | ||
42 | #define V3_PCI_IO_BASE 0x00000010 | ||
43 | #define V3_PCI_BASE0 0x00000014 | ||
44 | #define V3_PCI_BASE1 0x00000018 | ||
45 | #define V3_PCI_SUB_VENDOR 0x0000002C | ||
46 | #define V3_PCI_SUB_ID 0x0000002E | ||
47 | #define V3_PCI_ROM 0x00000030 | ||
48 | #define V3_PCI_BPARAM 0x0000003C | ||
49 | #define V3_PCI_MAP0 0x00000040 | ||
50 | #define V3_PCI_MAP1 0x00000044 | ||
51 | #define V3_PCI_INT_STAT 0x00000048 | ||
52 | #define V3_PCI_INT_CFG 0x0000004C | ||
53 | #define V3_LB_BASE0 0x00000054 | ||
54 | #define V3_LB_BASE1 0x00000058 | ||
55 | #define V3_LB_MAP0 0x0000005E | ||
56 | #define V3_LB_MAP1 0x00000062 | ||
57 | #define V3_LB_BASE2 0x00000064 | ||
58 | #define V3_LB_MAP2 0x00000066 | ||
59 | #define V3_LB_SIZE 0x00000068 | ||
60 | #define V3_LB_IO_BASE 0x0000006E | ||
61 | #define V3_FIFO_CFG 0x00000070 | ||
62 | #define V3_FIFO_PRIORITY 0x00000072 | ||
63 | #define V3_FIFO_STAT 0x00000074 | ||
64 | #define V3_LB_ISTAT 0x00000076 | ||
65 | #define V3_LB_IMASK 0x00000077 | ||
66 | #define V3_SYSTEM 0x00000078 | ||
67 | #define V3_LB_CFG 0x0000007A | ||
68 | #define V3_PCI_CFG 0x0000007C | ||
69 | #define V3_DMA_PCI_ADR0 0x00000080 | ||
70 | #define V3_DMA_PCI_ADR1 0x00000090 | ||
71 | #define V3_DMA_LOCAL_ADR0 0x00000084 | ||
72 | #define V3_DMA_LOCAL_ADR1 0x00000094 | ||
73 | #define V3_DMA_LENGTH0 0x00000088 | ||
74 | #define V3_DMA_LENGTH1 0x00000098 | ||
75 | #define V3_DMA_CSR0 0x0000008B | ||
76 | #define V3_DMA_CSR1 0x0000009B | ||
77 | #define V3_DMA_CTLB_ADR0 0x0000008C | ||
78 | #define V3_DMA_CTLB_ADR1 0x0000009C | ||
79 | #define V3_DMA_DELAY 0x000000E0 | ||
80 | #define V3_MAIL_DATA 0x000000C0 | ||
81 | #define V3_PCI_MAIL_IEWR 0x000000D0 | ||
82 | #define V3_PCI_MAIL_IERD 0x000000D2 | ||
83 | #define V3_LB_MAIL_IEWR 0x000000D4 | ||
84 | #define V3_LB_MAIL_IERD 0x000000D6 | ||
85 | #define V3_MAIL_WR_STAT 0x000000D8 | ||
86 | #define V3_MAIL_RD_STAT 0x000000DA | ||
87 | #define V3_QBA_MAP 0x000000DC | ||
88 | |||
89 | /* PCI COMMAND REGISTER bits | ||
90 | */ | ||
91 | #define V3_COMMAND_M_FBB_EN (1 << 9) | ||
92 | #define V3_COMMAND_M_SERR_EN (1 << 8) | ||
93 | #define V3_COMMAND_M_PAR_EN (1 << 6) | ||
94 | #define V3_COMMAND_M_MASTER_EN (1 << 2) | ||
95 | #define V3_COMMAND_M_MEM_EN (1 << 1) | ||
96 | #define V3_COMMAND_M_IO_EN (1 << 0) | ||
97 | |||
98 | /* SYSTEM REGISTER bits | ||
99 | */ | ||
100 | #define V3_SYSTEM_M_RST_OUT (1 << 15) | ||
101 | #define V3_SYSTEM_M_LOCK (1 << 14) | ||
102 | |||
103 | /* PCI_CFG bits | ||
104 | */ | ||
105 | #define V3_PCI_CFG_M_I2O_EN (1 << 15) | ||
106 | #define V3_PCI_CFG_M_IO_REG_DIS (1 << 14) | ||
107 | #define V3_PCI_CFG_M_IO_DIS (1 << 13) | ||
108 | #define V3_PCI_CFG_M_EN3V (1 << 12) | ||
109 | #define V3_PCI_CFG_M_RETRY_EN (1 << 10) | ||
110 | #define V3_PCI_CFG_M_AD_LOW1 (1 << 9) | ||
111 | #define V3_PCI_CFG_M_AD_LOW0 (1 << 8) | ||
112 | |||
113 | /* PCI_BASE register bits (PCI -> Local Bus) | ||
114 | */ | ||
115 | #define V3_PCI_BASE_M_ADR_BASE 0xFFF00000 | ||
116 | #define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00 | ||
117 | #define V3_PCI_BASE_M_PREFETCH (1 << 3) | ||
118 | #define V3_PCI_BASE_M_TYPE (3 << 1) | ||
119 | #define V3_PCI_BASE_M_IO (1 << 0) | ||
120 | |||
121 | /* PCI MAP register bits (PCI -> Local bus) | ||
122 | */ | ||
123 | #define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 | ||
124 | #define V3_PCI_MAP_M_RD_POST_INH (1 << 15) | ||
125 | #define V3_PCI_MAP_M_ROM_SIZE (3 << 10) | ||
126 | #define V3_PCI_MAP_M_SWAP (3 << 8) | ||
127 | #define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 | ||
128 | #define V3_PCI_MAP_M_REG_EN (1 << 1) | ||
129 | #define V3_PCI_MAP_M_ENABLE (1 << 0) | ||
130 | |||
131 | /* | ||
132 | * LB_BASE0,1 register bits (Local bus -> PCI) | ||
133 | */ | ||
134 | #define V3_LB_BASE_ADR_BASE 0xfff00000 | ||
135 | #define V3_LB_BASE_SWAP (3 << 8) | ||
136 | #define V3_LB_BASE_ADR_SIZE (15 << 4) | ||
137 | #define V3_LB_BASE_PREFETCH (1 << 3) | ||
138 | #define V3_LB_BASE_ENABLE (1 << 0) | ||
139 | |||
140 | #define V3_LB_BASE_ADR_SIZE_1MB (0 << 4) | ||
141 | #define V3_LB_BASE_ADR_SIZE_2MB (1 << 4) | ||
142 | #define V3_LB_BASE_ADR_SIZE_4MB (2 << 4) | ||
143 | #define V3_LB_BASE_ADR_SIZE_8MB (3 << 4) | ||
144 | #define V3_LB_BASE_ADR_SIZE_16MB (4 << 4) | ||
145 | #define V3_LB_BASE_ADR_SIZE_32MB (5 << 4) | ||
146 | #define V3_LB_BASE_ADR_SIZE_64MB (6 << 4) | ||
147 | #define V3_LB_BASE_ADR_SIZE_128MB (7 << 4) | ||
148 | #define V3_LB_BASE_ADR_SIZE_256MB (8 << 4) | ||
149 | #define V3_LB_BASE_ADR_SIZE_512MB (9 << 4) | ||
150 | #define V3_LB_BASE_ADR_SIZE_1GB (10 << 4) | ||
151 | #define V3_LB_BASE_ADR_SIZE_2GB (11 << 4) | ||
152 | |||
153 | #define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE) | ||
154 | |||
155 | /* | ||
156 | * LB_MAP0,1 register bits (Local bus -> PCI) | ||
157 | */ | ||
158 | #define V3_LB_MAP_MAP_ADR 0xfff0 | ||
159 | #define V3_LB_MAP_TYPE (7 << 1) | ||
160 | #define V3_LB_MAP_AD_LOW_EN (1 << 0) | ||
161 | |||
162 | #define V3_LB_MAP_TYPE_IACK (0 << 1) | ||
163 | #define V3_LB_MAP_TYPE_IO (1 << 1) | ||
164 | #define V3_LB_MAP_TYPE_MEM (3 << 1) | ||
165 | #define V3_LB_MAP_TYPE_CONFIG (5 << 1) | ||
166 | #define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1) | ||
167 | |||
168 | #define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR) | ||
169 | |||
170 | /* | ||
171 | * LB_BASE2 register bits (Local bus -> PCI IO) | ||
172 | */ | ||
173 | #define V3_LB_BASE2_ADR_BASE 0xff00 | ||
174 | #define V3_LB_BASE2_SWAP (3 << 6) | ||
175 | #define V3_LB_BASE2_ENABLE (1 << 0) | ||
176 | |||
177 | #define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE) | ||
178 | |||
179 | /* | ||
180 | * LB_MAP2 register bits (Local bus -> PCI IO) | ||
181 | */ | ||
182 | #define V3_LB_MAP2_MAP_ADR 0xff00 | ||
183 | |||
184 | #define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR) | ||
185 | |||
186 | #endif | ||
diff --git a/arch/arm/include/asm/hardware/sa1111.h b/arch/arm/include/asm/hardware/sa1111.h new file mode 100644 index 000000000000..6cf98d4f7dc3 --- /dev/null +++ b/arch/arm/include/asm/hardware/sa1111.h | |||
@@ -0,0 +1,581 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/hardware/sa1111.h | ||
3 | * | ||
4 | * Copyright (C) 2000 John G Dorsey <john+@cs.cmu.edu> | ||
5 | * | ||
6 | * This file contains definitions for the SA-1111 Companion Chip. | ||
7 | * (Structure and naming borrowed from SA-1101.h, by Peter Danielsson.) | ||
8 | * | ||
9 | * Macro that calculates real address for registers in the SA-1111 | ||
10 | */ | ||
11 | |||
12 | #ifndef _ASM_ARCH_SA1111 | ||
13 | #define _ASM_ARCH_SA1111 | ||
14 | |||
15 | #include <asm/arch/bitfield.h> | ||
16 | |||
17 | /* | ||
18 | * The SA1111 is always located at virtual 0xf4000000, and is always | ||
19 | * "native" endian. | ||
20 | */ | ||
21 | |||
22 | #define SA1111_VBASE 0xf4000000 | ||
23 | |||
24 | /* Don't use these! */ | ||
25 | #define SA1111_p2v( x ) ((x) - SA1111_BASE + SA1111_VBASE) | ||
26 | #define SA1111_v2p( x ) ((x) - SA1111_VBASE + SA1111_BASE) | ||
27 | |||
28 | #ifndef __ASSEMBLY__ | ||
29 | #define _SA1111(x) ((x) + sa1111->resource.start) | ||
30 | #endif | ||
31 | |||
32 | #define sa1111_writel(val,addr) __raw_writel(val, addr) | ||
33 | #define sa1111_readl(addr) __raw_readl(addr) | ||
34 | |||
35 | /* | ||
36 | * 26 bits of the SA-1110 address bus are available to the SA-1111. | ||
37 | * Use these when feeding target addresses to the DMA engines. | ||
38 | */ | ||
39 | |||
40 | #define SA1111_ADDR_WIDTH (26) | ||
41 | #define SA1111_ADDR_MASK ((1<<SA1111_ADDR_WIDTH)-1) | ||
42 | #define SA1111_DMA_ADDR(x) ((x)&SA1111_ADDR_MASK) | ||
43 | |||
44 | /* | ||
45 | * Don't ask the (SAC) DMA engines to move less than this amount. | ||
46 | */ | ||
47 | |||
48 | #define SA1111_SAC_DMA_MIN_XFER (0x800) | ||
49 | |||
50 | /* | ||
51 | * System Bus Interface (SBI) | ||
52 | * | ||
53 | * Registers | ||
54 | * SKCR Control Register | ||
55 | * SMCR Shared Memory Controller Register | ||
56 | * SKID ID Register | ||
57 | */ | ||
58 | #define SA1111_SKCR 0x0000 | ||
59 | #define SA1111_SMCR 0x0004 | ||
60 | #define SA1111_SKID 0x0008 | ||
61 | |||
62 | #define SKCR_PLL_BYPASS (1<<0) | ||
63 | #define SKCR_RCLKEN (1<<1) | ||
64 | #define SKCR_SLEEP (1<<2) | ||
65 | #define SKCR_DOZE (1<<3) | ||
66 | #define SKCR_VCO_OFF (1<<4) | ||
67 | #define SKCR_SCANTSTEN (1<<5) | ||
68 | #define SKCR_CLKTSTEN (1<<6) | ||
69 | #define SKCR_RDYEN (1<<7) | ||
70 | #define SKCR_SELAC (1<<8) | ||
71 | #define SKCR_OPPC (1<<9) | ||
72 | #define SKCR_PLLTSTEN (1<<10) | ||
73 | #define SKCR_USBIOTSTEN (1<<11) | ||
74 | /* | ||
75 | * Don't believe the specs! Take them, throw them outside. Leave them | ||
76 | * there for a week. Spit on them. Walk on them. Stamp on them. | ||
77 | * Pour gasoline over them and finally burn them. Now think about coding. | ||
78 | * - The October 1999 errata (278260-007) says its bit 13, 1 to enable. | ||
79 | * - The Feb 2001 errata (278260-010) says that the previous errata | ||
80 | * (278260-009) is wrong, and its bit actually 12, fixed in spec | ||
81 | * 278242-003. | ||
82 | * - The SA1111 manual (278242) says bit 12, but 0 to enable. | ||
83 | * - Reality is bit 13, 1 to enable. | ||
84 | * -- rmk | ||
85 | */ | ||
86 | #define SKCR_OE_EN (1<<13) | ||
87 | |||
88 | #define SMCR_DTIM (1<<0) | ||
89 | #define SMCR_MBGE (1<<1) | ||
90 | #define SMCR_DRAC_0 (1<<2) | ||
91 | #define SMCR_DRAC_1 (1<<3) | ||
92 | #define SMCR_DRAC_2 (1<<4) | ||
93 | #define SMCR_DRAC Fld(3, 2) | ||
94 | #define SMCR_CLAT (1<<5) | ||
95 | |||
96 | #define SKID_SIREV_MASK (0x000000f0) | ||
97 | #define SKID_MTREV_MASK (0x0000000f) | ||
98 | #define SKID_ID_MASK (0xffffff00) | ||
99 | #define SKID_SA1111_ID (0x690cc200) | ||
100 | |||
101 | /* | ||
102 | * System Controller | ||
103 | * | ||
104 | * Registers | ||
105 | * SKPCR Power Control Register | ||
106 | * SKCDR Clock Divider Register | ||
107 | * SKAUD Audio Clock Divider Register | ||
108 | * SKPMC PS/2 Mouse Clock Divider Register | ||
109 | * SKPTC PS/2 Track Pad Clock Divider Register | ||
110 | * SKPEN0 PWM0 Enable Register | ||
111 | * SKPWM0 PWM0 Clock Register | ||
112 | * SKPEN1 PWM1 Enable Register | ||
113 | * SKPWM1 PWM1 Clock Register | ||
114 | */ | ||
115 | #define SA1111_SKPCR 0x0200 | ||
116 | #define SA1111_SKCDR 0x0204 | ||
117 | #define SA1111_SKAUD 0x0208 | ||
118 | #define SA1111_SKPMC 0x020c | ||
119 | #define SA1111_SKPTC 0x0210 | ||
120 | #define SA1111_SKPEN0 0x0214 | ||
121 | #define SA1111_SKPWM0 0x0218 | ||
122 | #define SA1111_SKPEN1 0x021c | ||
123 | #define SA1111_SKPWM1 0x0220 | ||
124 | |||
125 | #define SKPCR_UCLKEN (1<<0) | ||
126 | #define SKPCR_ACCLKEN (1<<1) | ||
127 | #define SKPCR_I2SCLKEN (1<<2) | ||
128 | #define SKPCR_L3CLKEN (1<<3) | ||
129 | #define SKPCR_SCLKEN (1<<4) | ||
130 | #define SKPCR_PMCLKEN (1<<5) | ||
131 | #define SKPCR_PTCLKEN (1<<6) | ||
132 | #define SKPCR_DCLKEN (1<<7) | ||
133 | #define SKPCR_PWMCLKEN (1<<8) | ||
134 | |||
135 | /* | ||
136 | * USB Host controller | ||
137 | */ | ||
138 | #define SA1111_USB 0x0400 | ||
139 | |||
140 | /* | ||
141 | * Offsets from SA1111_USB_BASE | ||
142 | */ | ||
143 | #define SA1111_USB_STATUS 0x0118 | ||
144 | #define SA1111_USB_RESET 0x011c | ||
145 | #define SA1111_USB_IRQTEST 0x0120 | ||
146 | |||
147 | #define USB_RESET_FORCEIFRESET (1 << 0) | ||
148 | #define USB_RESET_FORCEHCRESET (1 << 1) | ||
149 | #define USB_RESET_CLKGENRESET (1 << 2) | ||
150 | #define USB_RESET_SIMSCALEDOWN (1 << 3) | ||
151 | #define USB_RESET_USBINTTEST (1 << 4) | ||
152 | #define USB_RESET_SLEEPSTBYEN (1 << 5) | ||
153 | #define USB_RESET_PWRSENSELOW (1 << 6) | ||
154 | #define USB_RESET_PWRCTRLLOW (1 << 7) | ||
155 | |||
156 | #define USB_STATUS_IRQHCIRMTWKUP (1 << 7) | ||
157 | #define USB_STATUS_IRQHCIBUFFACC (1 << 8) | ||
158 | #define USB_STATUS_NIRQHCIM (1 << 9) | ||
159 | #define USB_STATUS_NHCIMFCLR (1 << 10) | ||
160 | #define USB_STATUS_USBPWRSENSE (1 << 11) | ||
161 | |||
162 | /* | ||
163 | * Serial Audio Controller | ||
164 | * | ||
165 | * Registers | ||
166 | * SACR0 Serial Audio Common Control Register | ||
167 | * SACR1 Serial Audio Alternate Mode (I2C/MSB) Control Register | ||
168 | * SACR2 Serial Audio AC-link Control Register | ||
169 | * SASR0 Serial Audio I2S/MSB Interface & FIFO Status Register | ||
170 | * SASR1 Serial Audio AC-link Interface & FIFO Status Register | ||
171 | * SASCR Serial Audio Status Clear Register | ||
172 | * L3_CAR L3 Control Bus Address Register | ||
173 | * L3_CDR L3 Control Bus Data Register | ||
174 | * ACCAR AC-link Command Address Register | ||
175 | * ACCDR AC-link Command Data Register | ||
176 | * ACSAR AC-link Status Address Register | ||
177 | * ACSDR AC-link Status Data Register | ||
178 | * SADTCS Serial Audio DMA Transmit Control/Status Register | ||
179 | * SADTSA Serial Audio DMA Transmit Buffer Start Address A | ||
180 | * SADTCA Serial Audio DMA Transmit Buffer Count Register A | ||
181 | * SADTSB Serial Audio DMA Transmit Buffer Start Address B | ||
182 | * SADTCB Serial Audio DMA Transmit Buffer Count Register B | ||
183 | * SADRCS Serial Audio DMA Receive Control/Status Register | ||
184 | * SADRSA Serial Audio DMA Receive Buffer Start Address A | ||
185 | * SADRCA Serial Audio DMA Receive Buffer Count Register A | ||
186 | * SADRSB Serial Audio DMA Receive Buffer Start Address B | ||
187 | * SADRCB Serial Audio DMA Receive Buffer Count Register B | ||
188 | * SAITR Serial Audio Interrupt Test Register | ||
189 | * SADR Serial Audio Data Register (16 x 32-bit) | ||
190 | */ | ||
191 | |||
192 | #define SA1111_SERAUDIO 0x0600 | ||
193 | |||
194 | /* | ||
195 | * These are offsets from the above base. | ||
196 | */ | ||
197 | #define SA1111_SACR0 0x00 | ||
198 | #define SA1111_SACR1 0x04 | ||
199 | #define SA1111_SACR2 0x08 | ||
200 | #define SA1111_SASR0 0x0c | ||
201 | #define SA1111_SASR1 0x10 | ||
202 | #define SA1111_SASCR 0x18 | ||
203 | #define SA1111_L3_CAR 0x1c | ||
204 | #define SA1111_L3_CDR 0x20 | ||
205 | #define SA1111_ACCAR 0x24 | ||
206 | #define SA1111_ACCDR 0x28 | ||
207 | #define SA1111_ACSAR 0x2c | ||
208 | #define SA1111_ACSDR 0x30 | ||
209 | #define SA1111_SADTCS 0x34 | ||
210 | #define SA1111_SADTSA 0x38 | ||
211 | #define SA1111_SADTCA 0x3c | ||
212 | #define SA1111_SADTSB 0x40 | ||
213 | #define SA1111_SADTCB 0x44 | ||
214 | #define SA1111_SADRCS 0x48 | ||
215 | #define SA1111_SADRSA 0x4c | ||
216 | #define SA1111_SADRCA 0x50 | ||
217 | #define SA1111_SADRSB 0x54 | ||
218 | #define SA1111_SADRCB 0x58 | ||
219 | #define SA1111_SAITR 0x5c | ||
220 | #define SA1111_SADR 0x80 | ||
221 | |||
222 | #ifndef CONFIG_ARCH_PXA | ||
223 | |||
224 | #define SACR0_ENB (1<<0) | ||
225 | #define SACR0_BCKD (1<<2) | ||
226 | #define SACR0_RST (1<<3) | ||
227 | |||
228 | #define SACR1_AMSL (1<<0) | ||
229 | #define SACR1_L3EN (1<<1) | ||
230 | #define SACR1_L3MB (1<<2) | ||
231 | #define SACR1_DREC (1<<3) | ||
232 | #define SACR1_DRPL (1<<4) | ||
233 | #define SACR1_ENLBF (1<<5) | ||
234 | |||
235 | #define SACR2_TS3V (1<<0) | ||
236 | #define SACR2_TS4V (1<<1) | ||
237 | #define SACR2_WKUP (1<<2) | ||
238 | #define SACR2_DREC (1<<3) | ||
239 | #define SACR2_DRPL (1<<4) | ||
240 | #define SACR2_ENLBF (1<<5) | ||
241 | #define SACR2_RESET (1<<6) | ||
242 | |||
243 | #define SASR0_TNF (1<<0) | ||
244 | #define SASR0_RNE (1<<1) | ||
245 | #define SASR0_BSY (1<<2) | ||
246 | #define SASR0_TFS (1<<3) | ||
247 | #define SASR0_RFS (1<<4) | ||
248 | #define SASR0_TUR (1<<5) | ||
249 | #define SASR0_ROR (1<<6) | ||
250 | #define SASR0_L3WD (1<<16) | ||
251 | #define SASR0_L3RD (1<<17) | ||
252 | |||
253 | #define SASR1_TNF (1<<0) | ||
254 | #define SASR1_RNE (1<<1) | ||
255 | #define SASR1_BSY (1<<2) | ||
256 | #define SASR1_TFS (1<<3) | ||
257 | #define SASR1_RFS (1<<4) | ||
258 | #define SASR1_TUR (1<<5) | ||
259 | #define SASR1_ROR (1<<6) | ||
260 | #define SASR1_CADT (1<<16) | ||
261 | #define SASR1_SADR (1<<17) | ||
262 | #define SASR1_RSTO (1<<18) | ||
263 | #define SASR1_CLPM (1<<19) | ||
264 | #define SASR1_CRDY (1<<20) | ||
265 | #define SASR1_RS3V (1<<21) | ||
266 | #define SASR1_RS4V (1<<22) | ||
267 | |||
268 | #define SASCR_TUR (1<<5) | ||
269 | #define SASCR_ROR (1<<6) | ||
270 | #define SASCR_DTS (1<<16) | ||
271 | #define SASCR_RDD (1<<17) | ||
272 | #define SASCR_STO (1<<18) | ||
273 | |||
274 | #define SADTCS_TDEN (1<<0) | ||
275 | #define SADTCS_TDIE (1<<1) | ||
276 | #define SADTCS_TDBDA (1<<3) | ||
277 | #define SADTCS_TDSTA (1<<4) | ||
278 | #define SADTCS_TDBDB (1<<5) | ||
279 | #define SADTCS_TDSTB (1<<6) | ||
280 | #define SADTCS_TBIU (1<<7) | ||
281 | |||
282 | #define SADRCS_RDEN (1<<0) | ||
283 | #define SADRCS_RDIE (1<<1) | ||
284 | #define SADRCS_RDBDA (1<<3) | ||
285 | #define SADRCS_RDSTA (1<<4) | ||
286 | #define SADRCS_RDBDB (1<<5) | ||
287 | #define SADRCS_RDSTB (1<<6) | ||
288 | #define SADRCS_RBIU (1<<7) | ||
289 | |||
290 | #define SAD_CS_DEN (1<<0) | ||
291 | #define SAD_CS_DIE (1<<1) /* Not functional on metal 1 */ | ||
292 | #define SAD_CS_DBDA (1<<3) /* Not functional on metal 1 */ | ||
293 | #define SAD_CS_DSTA (1<<4) | ||
294 | #define SAD_CS_DBDB (1<<5) /* Not functional on metal 1 */ | ||
295 | #define SAD_CS_DSTB (1<<6) | ||
296 | #define SAD_CS_BIU (1<<7) /* Not functional on metal 1 */ | ||
297 | |||
298 | #define SAITR_TFS (1<<0) | ||
299 | #define SAITR_RFS (1<<1) | ||
300 | #define SAITR_TUR (1<<2) | ||
301 | #define SAITR_ROR (1<<3) | ||
302 | #define SAITR_CADT (1<<4) | ||
303 | #define SAITR_SADR (1<<5) | ||
304 | #define SAITR_RSTO (1<<6) | ||
305 | #define SAITR_TDBDA (1<<8) | ||
306 | #define SAITR_TDBDB (1<<9) | ||
307 | #define SAITR_RDBDA (1<<10) | ||
308 | #define SAITR_RDBDB (1<<11) | ||
309 | |||
310 | #endif /* !CONFIG_ARCH_PXA */ | ||
311 | |||
312 | /* | ||
313 | * General-Purpose I/O Interface | ||
314 | * | ||
315 | * Registers | ||
316 | * PA_DDR GPIO Block A Data Direction | ||
317 | * PA_DRR/PA_DWR GPIO Block A Data Value Register (read/write) | ||
318 | * PA_SDR GPIO Block A Sleep Direction | ||
319 | * PA_SSR GPIO Block A Sleep State | ||
320 | * PB_DDR GPIO Block B Data Direction | ||
321 | * PB_DRR/PB_DWR GPIO Block B Data Value Register (read/write) | ||
322 | * PB_SDR GPIO Block B Sleep Direction | ||
323 | * PB_SSR GPIO Block B Sleep State | ||
324 | * PC_DDR GPIO Block C Data Direction | ||
325 | * PC_DRR/PC_DWR GPIO Block C Data Value Register (read/write) | ||
326 | * PC_SDR GPIO Block C Sleep Direction | ||
327 | * PC_SSR GPIO Block C Sleep State | ||
328 | */ | ||
329 | |||
330 | #define _PA_DDR _SA1111( 0x1000 ) | ||
331 | #define _PA_DRR _SA1111( 0x1004 ) | ||
332 | #define _PA_DWR _SA1111( 0x1004 ) | ||
333 | #define _PA_SDR _SA1111( 0x1008 ) | ||
334 | #define _PA_SSR _SA1111( 0x100c ) | ||
335 | #define _PB_DDR _SA1111( 0x1010 ) | ||
336 | #define _PB_DRR _SA1111( 0x1014 ) | ||
337 | #define _PB_DWR _SA1111( 0x1014 ) | ||
338 | #define _PB_SDR _SA1111( 0x1018 ) | ||
339 | #define _PB_SSR _SA1111( 0x101c ) | ||
340 | #define _PC_DDR _SA1111( 0x1020 ) | ||
341 | #define _PC_DRR _SA1111( 0x1024 ) | ||
342 | #define _PC_DWR _SA1111( 0x1024 ) | ||
343 | #define _PC_SDR _SA1111( 0x1028 ) | ||
344 | #define _PC_SSR _SA1111( 0x102c ) | ||
345 | |||
346 | #define SA1111_GPIO 0x1000 | ||
347 | |||
348 | #define SA1111_GPIO_PADDR (0x000) | ||
349 | #define SA1111_GPIO_PADRR (0x004) | ||
350 | #define SA1111_GPIO_PADWR (0x004) | ||
351 | #define SA1111_GPIO_PASDR (0x008) | ||
352 | #define SA1111_GPIO_PASSR (0x00c) | ||
353 | #define SA1111_GPIO_PBDDR (0x010) | ||
354 | #define SA1111_GPIO_PBDRR (0x014) | ||
355 | #define SA1111_GPIO_PBDWR (0x014) | ||
356 | #define SA1111_GPIO_PBSDR (0x018) | ||
357 | #define SA1111_GPIO_PBSSR (0x01c) | ||
358 | #define SA1111_GPIO_PCDDR (0x020) | ||
359 | #define SA1111_GPIO_PCDRR (0x024) | ||
360 | #define SA1111_GPIO_PCDWR (0x024) | ||
361 | #define SA1111_GPIO_PCSDR (0x028) | ||
362 | #define SA1111_GPIO_PCSSR (0x02c) | ||
363 | |||
364 | #define GPIO_A0 (1 << 0) | ||
365 | #define GPIO_A1 (1 << 1) | ||
366 | #define GPIO_A2 (1 << 2) | ||
367 | #define GPIO_A3 (1 << 3) | ||
368 | |||
369 | #define GPIO_B0 (1 << 8) | ||
370 | #define GPIO_B1 (1 << 9) | ||
371 | #define GPIO_B2 (1 << 10) | ||
372 | #define GPIO_B3 (1 << 11) | ||
373 | #define GPIO_B4 (1 << 12) | ||
374 | #define GPIO_B5 (1 << 13) | ||
375 | #define GPIO_B6 (1 << 14) | ||
376 | #define GPIO_B7 (1 << 15) | ||
377 | |||
378 | #define GPIO_C0 (1 << 16) | ||
379 | #define GPIO_C1 (1 << 17) | ||
380 | #define GPIO_C2 (1 << 18) | ||
381 | #define GPIO_C3 (1 << 19) | ||
382 | #define GPIO_C4 (1 << 20) | ||
383 | #define GPIO_C5 (1 << 21) | ||
384 | #define GPIO_C6 (1 << 22) | ||
385 | #define GPIO_C7 (1 << 23) | ||
386 | |||
387 | /* | ||
388 | * Interrupt Controller | ||
389 | * | ||
390 | * Registers | ||
391 | * INTTEST0 Test register 0 | ||
392 | * INTTEST1 Test register 1 | ||
393 | * INTEN0 Interrupt Enable register 0 | ||
394 | * INTEN1 Interrupt Enable register 1 | ||
395 | * INTPOL0 Interrupt Polarity selection 0 | ||
396 | * INTPOL1 Interrupt Polarity selection 1 | ||
397 | * INTTSTSEL Interrupt source selection | ||
398 | * INTSTATCLR0 Interrupt Status/Clear 0 | ||
399 | * INTSTATCLR1 Interrupt Status/Clear 1 | ||
400 | * INTSET0 Interrupt source set 0 | ||
401 | * INTSET1 Interrupt source set 1 | ||
402 | * WAKE_EN0 Wake-up source enable 0 | ||
403 | * WAKE_EN1 Wake-up source enable 1 | ||
404 | * WAKE_POL0 Wake-up polarity selection 0 | ||
405 | * WAKE_POL1 Wake-up polarity selection 1 | ||
406 | */ | ||
407 | #define SA1111_INTC 0x1600 | ||
408 | |||
409 | /* | ||
410 | * These are offsets from the above base. | ||
411 | */ | ||
412 | #define SA1111_INTTEST0 0x0000 | ||
413 | #define SA1111_INTTEST1 0x0004 | ||
414 | #define SA1111_INTEN0 0x0008 | ||
415 | #define SA1111_INTEN1 0x000c | ||
416 | #define SA1111_INTPOL0 0x0010 | ||
417 | #define SA1111_INTPOL1 0x0014 | ||
418 | #define SA1111_INTTSTSEL 0x0018 | ||
419 | #define SA1111_INTSTATCLR0 0x001c | ||
420 | #define SA1111_INTSTATCLR1 0x0020 | ||
421 | #define SA1111_INTSET0 0x0024 | ||
422 | #define SA1111_INTSET1 0x0028 | ||
423 | #define SA1111_WAKEEN0 0x002c | ||
424 | #define SA1111_WAKEEN1 0x0030 | ||
425 | #define SA1111_WAKEPOL0 0x0034 | ||
426 | #define SA1111_WAKEPOL1 0x0038 | ||
427 | |||
428 | /* | ||
429 | * PS/2 Trackpad and Mouse Interfaces | ||
430 | * | ||
431 | * Registers | ||
432 | * PS2CR Control Register | ||
433 | * PS2STAT Status Register | ||
434 | * PS2DATA Transmit/Receive Data register | ||
435 | * PS2CLKDIV Clock Division Register | ||
436 | * PS2PRECNT Clock Precount Register | ||
437 | * PS2TEST1 Test register 1 | ||
438 | * PS2TEST2 Test register 2 | ||
439 | * PS2TEST3 Test register 3 | ||
440 | * PS2TEST4 Test register 4 | ||
441 | */ | ||
442 | |||
443 | #define SA1111_KBD 0x0a00 | ||
444 | #define SA1111_MSE 0x0c00 | ||
445 | |||
446 | /* | ||
447 | * These are offsets from the above bases. | ||
448 | */ | ||
449 | #define SA1111_PS2CR 0x0000 | ||
450 | #define SA1111_PS2STAT 0x0004 | ||
451 | #define SA1111_PS2DATA 0x0008 | ||
452 | #define SA1111_PS2CLKDIV 0x000c | ||
453 | #define SA1111_PS2PRECNT 0x0010 | ||
454 | |||
455 | #define PS2CR_ENA 0x08 | ||
456 | #define PS2CR_FKD 0x02 | ||
457 | #define PS2CR_FKC 0x01 | ||
458 | |||
459 | #define PS2STAT_STP 0x0100 | ||
460 | #define PS2STAT_TXE 0x0080 | ||
461 | #define PS2STAT_TXB 0x0040 | ||
462 | #define PS2STAT_RXF 0x0020 | ||
463 | #define PS2STAT_RXB 0x0010 | ||
464 | #define PS2STAT_ENA 0x0008 | ||
465 | #define PS2STAT_RXP 0x0004 | ||
466 | #define PS2STAT_KBD 0x0002 | ||
467 | #define PS2STAT_KBC 0x0001 | ||
468 | |||
469 | /* | ||
470 | * PCMCIA Interface | ||
471 | * | ||
472 | * Registers | ||
473 | * PCSR Status Register | ||
474 | * PCCR Control Register | ||
475 | * PCSSR Sleep State Register | ||
476 | */ | ||
477 | |||
478 | #define SA1111_PCMCIA 0x1600 | ||
479 | |||
480 | /* | ||
481 | * These are offsets from the above base. | ||
482 | */ | ||
483 | #define SA1111_PCCR 0x0000 | ||
484 | #define SA1111_PCSSR 0x0004 | ||
485 | #define SA1111_PCSR 0x0008 | ||
486 | |||
487 | #define PCSR_S0_READY (1<<0) | ||
488 | #define PCSR_S1_READY (1<<1) | ||
489 | #define PCSR_S0_DETECT (1<<2) | ||
490 | #define PCSR_S1_DETECT (1<<3) | ||
491 | #define PCSR_S0_VS1 (1<<4) | ||
492 | #define PCSR_S0_VS2 (1<<5) | ||
493 | #define PCSR_S1_VS1 (1<<6) | ||
494 | #define PCSR_S1_VS2 (1<<7) | ||
495 | #define PCSR_S0_WP (1<<8) | ||
496 | #define PCSR_S1_WP (1<<9) | ||
497 | #define PCSR_S0_BVD1 (1<<10) | ||
498 | #define PCSR_S0_BVD2 (1<<11) | ||
499 | #define PCSR_S1_BVD1 (1<<12) | ||
500 | #define PCSR_S1_BVD2 (1<<13) | ||
501 | |||
502 | #define PCCR_S0_RST (1<<0) | ||
503 | #define PCCR_S1_RST (1<<1) | ||
504 | #define PCCR_S0_FLT (1<<2) | ||
505 | #define PCCR_S1_FLT (1<<3) | ||
506 | #define PCCR_S0_PWAITEN (1<<4) | ||
507 | #define PCCR_S1_PWAITEN (1<<5) | ||
508 | #define PCCR_S0_PSE (1<<6) | ||
509 | #define PCCR_S1_PSE (1<<7) | ||
510 | |||
511 | #define PCSSR_S0_SLEEP (1<<0) | ||
512 | #define PCSSR_S1_SLEEP (1<<1) | ||
513 | |||
514 | |||
515 | |||
516 | |||
517 | extern struct bus_type sa1111_bus_type; | ||
518 | |||
519 | #define SA1111_DEVID_SBI 0 | ||
520 | #define SA1111_DEVID_SK 1 | ||
521 | #define SA1111_DEVID_USB 2 | ||
522 | #define SA1111_DEVID_SAC 3 | ||
523 | #define SA1111_DEVID_SSP 4 | ||
524 | #define SA1111_DEVID_PS2 5 | ||
525 | #define SA1111_DEVID_GPIO 6 | ||
526 | #define SA1111_DEVID_INT 7 | ||
527 | #define SA1111_DEVID_PCMCIA 8 | ||
528 | |||
529 | struct sa1111_dev { | ||
530 | struct device dev; | ||
531 | unsigned int devid; | ||
532 | struct resource res; | ||
533 | void __iomem *mapbase; | ||
534 | unsigned int skpcr_mask; | ||
535 | unsigned int irq[6]; | ||
536 | u64 dma_mask; | ||
537 | }; | ||
538 | |||
539 | #define SA1111_DEV(_d) container_of((_d), struct sa1111_dev, dev) | ||
540 | |||
541 | #define sa1111_get_drvdata(d) dev_get_drvdata(&(d)->dev) | ||
542 | #define sa1111_set_drvdata(d,p) dev_set_drvdata(&(d)->dev, p) | ||
543 | |||
544 | struct sa1111_driver { | ||
545 | struct device_driver drv; | ||
546 | unsigned int devid; | ||
547 | int (*probe)(struct sa1111_dev *); | ||
548 | int (*remove)(struct sa1111_dev *); | ||
549 | int (*suspend)(struct sa1111_dev *, pm_message_t); | ||
550 | int (*resume)(struct sa1111_dev *); | ||
551 | }; | ||
552 | |||
553 | #define SA1111_DRV(_d) container_of((_d), struct sa1111_driver, drv) | ||
554 | |||
555 | #define SA1111_DRIVER_NAME(_sadev) ((_sadev)->dev.driver->name) | ||
556 | |||
557 | /* | ||
558 | * These frob the SKPCR register. | ||
559 | */ | ||
560 | void sa1111_enable_device(struct sa1111_dev *); | ||
561 | void sa1111_disable_device(struct sa1111_dev *); | ||
562 | |||
563 | unsigned int sa1111_pll_clock(struct sa1111_dev *); | ||
564 | |||
565 | #define SA1111_AUDIO_ACLINK 0 | ||
566 | #define SA1111_AUDIO_I2S 1 | ||
567 | |||
568 | void sa1111_select_audio_mode(struct sa1111_dev *sadev, int mode); | ||
569 | int sa1111_set_audio_rate(struct sa1111_dev *sadev, int rate); | ||
570 | int sa1111_get_audio_rate(struct sa1111_dev *sadev); | ||
571 | |||
572 | int sa1111_check_dma_bug(dma_addr_t addr); | ||
573 | |||
574 | int sa1111_driver_register(struct sa1111_driver *); | ||
575 | void sa1111_driver_unregister(struct sa1111_driver *); | ||
576 | |||
577 | void sa1111_set_io_dir(struct sa1111_dev *sadev, unsigned int bits, unsigned int dir, unsigned int sleep_dir); | ||
578 | void sa1111_set_io(struct sa1111_dev *sadev, unsigned int bits, unsigned int v); | ||
579 | void sa1111_set_sleep_io(struct sa1111_dev *sadev, unsigned int bits, unsigned int v); | ||
580 | |||
581 | #endif /* _ASM_ARCH_SA1111 */ | ||
diff --git a/arch/arm/include/asm/hardware/scoop.h b/arch/arm/include/asm/hardware/scoop.h new file mode 100644 index 000000000000..dfb8330599f9 --- /dev/null +++ b/arch/arm/include/asm/hardware/scoop.h | |||
@@ -0,0 +1,69 @@ | |||
1 | /* | ||
2 | * Definitions for the SCOOP interface found on various Sharp PDAs | ||
3 | * | ||
4 | * Copyright (c) 2004 Richard Purdie | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | */ | ||
11 | |||
12 | #define SCOOP_MCR 0x00 | ||
13 | #define SCOOP_CDR 0x04 | ||
14 | #define SCOOP_CSR 0x08 | ||
15 | #define SCOOP_CPR 0x0C | ||
16 | #define SCOOP_CCR 0x10 | ||
17 | #define SCOOP_IRR 0x14 | ||
18 | #define SCOOP_IRM 0x14 | ||
19 | #define SCOOP_IMR 0x18 | ||
20 | #define SCOOP_ISR 0x1C | ||
21 | #define SCOOP_GPCR 0x20 | ||
22 | #define SCOOP_GPWR 0x24 | ||
23 | #define SCOOP_GPRR 0x28 | ||
24 | |||
25 | #define SCOOP_GPCR_PA22 ( 1 << 12 ) | ||
26 | #define SCOOP_GPCR_PA21 ( 1 << 11 ) | ||
27 | #define SCOOP_GPCR_PA20 ( 1 << 10 ) | ||
28 | #define SCOOP_GPCR_PA19 ( 1 << 9 ) | ||
29 | #define SCOOP_GPCR_PA18 ( 1 << 8 ) | ||
30 | #define SCOOP_GPCR_PA17 ( 1 << 7 ) | ||
31 | #define SCOOP_GPCR_PA16 ( 1 << 6 ) | ||
32 | #define SCOOP_GPCR_PA15 ( 1 << 5 ) | ||
33 | #define SCOOP_GPCR_PA14 ( 1 << 4 ) | ||
34 | #define SCOOP_GPCR_PA13 ( 1 << 3 ) | ||
35 | #define SCOOP_GPCR_PA12 ( 1 << 2 ) | ||
36 | #define SCOOP_GPCR_PA11 ( 1 << 1 ) | ||
37 | |||
38 | struct scoop_config { | ||
39 | unsigned short io_out; | ||
40 | unsigned short io_dir; | ||
41 | unsigned short suspend_clr; | ||
42 | unsigned short suspend_set; | ||
43 | int gpio_base; | ||
44 | }; | ||
45 | |||
46 | /* Structure for linking scoop devices to PCMCIA sockets */ | ||
47 | struct scoop_pcmcia_dev { | ||
48 | struct device *dev; /* Pointer to this socket's scoop device */ | ||
49 | int irq; /* irq for socket */ | ||
50 | int cd_irq; | ||
51 | const char *cd_irq_str; | ||
52 | unsigned char keep_vs; | ||
53 | unsigned char keep_rd; | ||
54 | }; | ||
55 | |||
56 | struct scoop_pcmcia_config { | ||
57 | struct scoop_pcmcia_dev *devs; | ||
58 | int num_devs; | ||
59 | void (*pcmcia_init)(void); | ||
60 | void (*power_ctrl)(struct device *scoop, unsigned short cpr, int nr); | ||
61 | }; | ||
62 | |||
63 | extern struct scoop_pcmcia_config *platform_scoop_config; | ||
64 | |||
65 | void reset_scoop(struct device *dev); | ||
66 | unsigned short __deprecated set_scoop_gpio(struct device *dev, unsigned short bit); | ||
67 | unsigned short __deprecated reset_scoop_gpio(struct device *dev, unsigned short bit); | ||
68 | unsigned short read_scoop_reg(struct device *dev, unsigned short reg); | ||
69 | void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data); | ||
diff --git a/arch/arm/include/asm/hardware/sharpsl_pm.h b/arch/arm/include/asm/hardware/sharpsl_pm.h new file mode 100644 index 000000000000..2d00db22b981 --- /dev/null +++ b/arch/arm/include/asm/hardware/sharpsl_pm.h | |||
@@ -0,0 +1,106 @@ | |||
1 | /* | ||
2 | * SharpSL Battery/PM Driver | ||
3 | * | ||
4 | * Copyright (c) 2004-2005 Richard Purdie | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | */ | ||
11 | |||
12 | #include <linux/interrupt.h> | ||
13 | |||
14 | struct sharpsl_charger_machinfo { | ||
15 | void (*init)(void); | ||
16 | void (*exit)(void); | ||
17 | int gpio_acin; | ||
18 | int gpio_batfull; | ||
19 | int batfull_irq; | ||
20 | int gpio_batlock; | ||
21 | int gpio_fatal; | ||
22 | void (*discharge)(int); | ||
23 | void (*discharge1)(int); | ||
24 | void (*charge)(int); | ||
25 | void (*measure_temp)(int); | ||
26 | void (*presuspend)(void); | ||
27 | void (*postsuspend)(void); | ||
28 | void (*earlyresume)(void); | ||
29 | unsigned long (*read_devdata)(int); | ||
30 | #define SHARPSL_BATT_VOLT 1 | ||
31 | #define SHARPSL_BATT_TEMP 2 | ||
32 | #define SHARPSL_ACIN_VOLT 3 | ||
33 | #define SHARPSL_STATUS_ACIN 4 | ||
34 | #define SHARPSL_STATUS_LOCK 5 | ||
35 | #define SHARPSL_STATUS_CHRGFULL 6 | ||
36 | #define SHARPSL_STATUS_FATAL 7 | ||
37 | unsigned long (*charger_wakeup)(void); | ||
38 | int (*should_wakeup)(unsigned int resume_on_alarm); | ||
39 | void (*backlight_limit)(int); | ||
40 | int (*backlight_get_status) (void); | ||
41 | int charge_on_volt; | ||
42 | int charge_on_temp; | ||
43 | int charge_acin_high; | ||
44 | int charge_acin_low; | ||
45 | int fatal_acin_volt; | ||
46 | int fatal_noacin_volt; | ||
47 | int bat_levels; | ||
48 | struct battery_thresh *bat_levels_noac; | ||
49 | struct battery_thresh *bat_levels_acin; | ||
50 | struct battery_thresh *bat_levels_noac_bl; | ||
51 | struct battery_thresh *bat_levels_acin_bl; | ||
52 | int status_high_acin; | ||
53 | int status_low_acin; | ||
54 | int status_high_noac; | ||
55 | int status_low_noac; | ||
56 | }; | ||
57 | |||
58 | struct battery_thresh { | ||
59 | int voltage; | ||
60 | int percentage; | ||
61 | }; | ||
62 | |||
63 | struct battery_stat { | ||
64 | int ac_status; /* APM AC Present/Not Present */ | ||
65 | int mainbat_status; /* APM Main Battery Status */ | ||
66 | int mainbat_percent; /* Main Battery Percentage Charge */ | ||
67 | int mainbat_voltage; /* Main Battery Voltage */ | ||
68 | }; | ||
69 | |||
70 | struct sharpsl_pm_status { | ||
71 | struct device *dev; | ||
72 | struct timer_list ac_timer; | ||
73 | struct timer_list chrg_full_timer; | ||
74 | |||
75 | int charge_mode; | ||
76 | #define CHRG_ERROR (-1) | ||
77 | #define CHRG_OFF (0) | ||
78 | #define CHRG_ON (1) | ||
79 | #define CHRG_DONE (2) | ||
80 | |||
81 | unsigned int flags; | ||
82 | #define SHARPSL_SUSPENDED (1 << 0) /* Device is Suspended */ | ||
83 | #define SHARPSL_ALARM_ACTIVE (1 << 1) /* Alarm is for charging event (not user) */ | ||
84 | #define SHARPSL_BL_LIMIT (1 << 2) /* Backlight Intensity Limited */ | ||
85 | #define SHARPSL_APM_QUEUED (1 << 3) /* APM Event Queued */ | ||
86 | #define SHARPSL_DO_OFFLINE_CHRG (1 << 4) /* Trigger the offline charger */ | ||
87 | |||
88 | int full_count; | ||
89 | unsigned long charge_start_time; | ||
90 | struct sharpsl_charger_machinfo *machinfo; | ||
91 | struct battery_stat battstat; | ||
92 | }; | ||
93 | |||
94 | extern struct sharpsl_pm_status sharpsl_pm; | ||
95 | |||
96 | |||
97 | #define SHARPSL_LED_ERROR 2 | ||
98 | #define SHARPSL_LED_ON 1 | ||
99 | #define SHARPSL_LED_OFF 0 | ||
100 | |||
101 | void sharpsl_battery_kick(void); | ||
102 | void sharpsl_pm_led(int val); | ||
103 | irqreturn_t sharpsl_ac_isr(int irq, void *dev_id); | ||
104 | irqreturn_t sharpsl_chrg_full_isr(int irq, void *dev_id); | ||
105 | irqreturn_t sharpsl_fatal_isr(int irq, void *dev_id); | ||
106 | |||
diff --git a/arch/arm/include/asm/hardware/ssp.h b/arch/arm/include/asm/hardware/ssp.h new file mode 100644 index 000000000000..3b42e181997c --- /dev/null +++ b/arch/arm/include/asm/hardware/ssp.h | |||
@@ -0,0 +1,28 @@ | |||
1 | /* | ||
2 | * ssp.h | ||
3 | * | ||
4 | * Copyright (C) 2003 Russell King, All Rights Reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #ifndef SSP_H | ||
11 | #define SSP_H | ||
12 | |||
13 | struct ssp_state { | ||
14 | unsigned int cr0; | ||
15 | unsigned int cr1; | ||
16 | }; | ||
17 | |||
18 | int ssp_write_word(u16 data); | ||
19 | int ssp_read_word(u16 *data); | ||
20 | int ssp_flush(void); | ||
21 | void ssp_enable(void); | ||
22 | void ssp_disable(void); | ||
23 | void ssp_save_state(struct ssp_state *ssp); | ||
24 | void ssp_restore_state(struct ssp_state *ssp); | ||
25 | int ssp_init(void); | ||
26 | void ssp_exit(void); | ||
27 | |||
28 | #endif | ||
diff --git a/arch/arm/include/asm/hardware/uengine.h b/arch/arm/include/asm/hardware/uengine.h new file mode 100644 index 000000000000..b442d65c6593 --- /dev/null +++ b/arch/arm/include/asm/hardware/uengine.h | |||
@@ -0,0 +1,62 @@ | |||
1 | /* | ||
2 | * Generic library functions for the microengines found on the Intel | ||
3 | * IXP2000 series of network processors. | ||
4 | * | ||
5 | * Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org> | ||
6 | * Dedicated to Marija Kulikova. | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU Lesser General Public License as | ||
10 | * published by the Free Software Foundation; either version 2.1 of the | ||
11 | * License, or (at your option) any later version. | ||
12 | */ | ||
13 | |||
14 | #ifndef __IXP2000_UENGINE_H | ||
15 | #define __IXP2000_UENGINE_H | ||
16 | |||
17 | extern u32 ixp2000_uengine_mask; | ||
18 | |||
19 | struct ixp2000_uengine_code | ||
20 | { | ||
21 | u32 cpu_model_bitmask; | ||
22 | u8 cpu_min_revision; | ||
23 | u8 cpu_max_revision; | ||
24 | |||
25 | u32 uengine_parameters; | ||
26 | |||
27 | struct ixp2000_reg_value { | ||
28 | int reg; | ||
29 | u32 value; | ||
30 | } *initial_reg_values; | ||
31 | |||
32 | int num_insns; | ||
33 | u8 *insns; | ||
34 | }; | ||
35 | |||
36 | u32 ixp2000_uengine_csr_read(int uengine, int offset); | ||
37 | void ixp2000_uengine_csr_write(int uengine, int offset, u32 value); | ||
38 | void ixp2000_uengine_reset(u32 uengine_mask); | ||
39 | void ixp2000_uengine_set_mode(int uengine, u32 mode); | ||
40 | void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns); | ||
41 | void ixp2000_uengine_init_context(int uengine, int context, int pc); | ||
42 | void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask); | ||
43 | void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask); | ||
44 | int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c); | ||
45 | |||
46 | #define IXP2000_UENGINE_8_CONTEXTS 0x00000000 | ||
47 | #define IXP2000_UENGINE_4_CONTEXTS 0x80000000 | ||
48 | #define IXP2000_UENGINE_PRN_UPDATE_EVERY 0x40000000 | ||
49 | #define IXP2000_UENGINE_PRN_UPDATE_ON_ACCESS 0x00000000 | ||
50 | #define IXP2000_UENGINE_NN_FROM_SELF 0x00100000 | ||
51 | #define IXP2000_UENGINE_NN_FROM_PREVIOUS 0x00000000 | ||
52 | #define IXP2000_UENGINE_ASSERT_EMPTY_AT_3 0x000c0000 | ||
53 | #define IXP2000_UENGINE_ASSERT_EMPTY_AT_2 0x00080000 | ||
54 | #define IXP2000_UENGINE_ASSERT_EMPTY_AT_1 0x00040000 | ||
55 | #define IXP2000_UENGINE_ASSERT_EMPTY_AT_0 0x00000000 | ||
56 | #define IXP2000_UENGINE_LM_ADDR1_GLOBAL 0x00020000 | ||
57 | #define IXP2000_UENGINE_LM_ADDR1_PER_CONTEXT 0x00000000 | ||
58 | #define IXP2000_UENGINE_LM_ADDR0_GLOBAL 0x00010000 | ||
59 | #define IXP2000_UENGINE_LM_ADDR0_PER_CONTEXT 0x00000000 | ||
60 | |||
61 | |||
62 | #endif | ||
diff --git a/arch/arm/include/asm/hardware/vic.h b/arch/arm/include/asm/hardware/vic.h new file mode 100644 index 000000000000..263f2c362a30 --- /dev/null +++ b/arch/arm/include/asm/hardware/vic.h | |||
@@ -0,0 +1,45 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/hardware/vic.h | ||
3 | * | ||
4 | * Copyright (c) ARM Limited 2003. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
19 | */ | ||
20 | #ifndef __ASM_ARM_HARDWARE_VIC_H | ||
21 | #define __ASM_ARM_HARDWARE_VIC_H | ||
22 | |||
23 | #define VIC_IRQ_STATUS 0x00 | ||
24 | #define VIC_FIQ_STATUS 0x04 | ||
25 | #define VIC_RAW_STATUS 0x08 | ||
26 | #define VIC_INT_SELECT 0x0c /* 1 = FIQ, 0 = IRQ */ | ||
27 | #define VIC_INT_ENABLE 0x10 /* 1 = enable, 0 = disable */ | ||
28 | #define VIC_INT_ENABLE_CLEAR 0x14 | ||
29 | #define VIC_INT_SOFT 0x18 | ||
30 | #define VIC_INT_SOFT_CLEAR 0x1c | ||
31 | #define VIC_PROTECT 0x20 | ||
32 | #define VIC_VECT_ADDR 0x30 | ||
33 | #define VIC_DEF_VECT_ADDR 0x34 | ||
34 | |||
35 | #define VIC_VECT_ADDR0 0x100 /* 0 to 15 */ | ||
36 | #define VIC_VECT_CNTL0 0x200 /* 0 to 15 */ | ||
37 | #define VIC_ITCR 0x300 /* VIC test control register */ | ||
38 | |||
39 | #define VIC_VECT_CNTL_ENABLE (1 << 5) | ||
40 | |||
41 | #ifndef __ASSEMBLY__ | ||
42 | void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources); | ||
43 | #endif | ||
44 | |||
45 | #endif | ||
diff --git a/arch/arm/include/asm/hw_irq.h b/arch/arm/include/asm/hw_irq.h new file mode 100644 index 000000000000..f1a08a500604 --- /dev/null +++ b/arch/arm/include/asm/hw_irq.h | |||
@@ -0,0 +1,9 @@ | |||
1 | /* | ||
2 | * Nothing to see here yet | ||
3 | */ | ||
4 | #ifndef _ARCH_ARM_HW_IRQ_H | ||
5 | #define _ARCH_ARM_HW_IRQ_H | ||
6 | |||
7 | #include <asm/mach/irq.h> | ||
8 | |||
9 | #endif | ||
diff --git a/arch/arm/include/asm/hwcap.h b/arch/arm/include/asm/hwcap.h new file mode 100644 index 000000000000..81f4c899a555 --- /dev/null +++ b/arch/arm/include/asm/hwcap.h | |||
@@ -0,0 +1,29 @@ | |||
1 | #ifndef __ASMARM_HWCAP_H | ||
2 | #define __ASMARM_HWCAP_H | ||
3 | |||
4 | /* | ||
5 | * HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP | ||
6 | */ | ||
7 | #define HWCAP_SWP 1 | ||
8 | #define HWCAP_HALF 2 | ||
9 | #define HWCAP_THUMB 4 | ||
10 | #define HWCAP_26BIT 8 /* Play it safe */ | ||
11 | #define HWCAP_FAST_MULT 16 | ||
12 | #define HWCAP_FPA 32 | ||
13 | #define HWCAP_VFP 64 | ||
14 | #define HWCAP_EDSP 128 | ||
15 | #define HWCAP_JAVA 256 | ||
16 | #define HWCAP_IWMMXT 512 | ||
17 | #define HWCAP_CRUNCH 1024 | ||
18 | #define HWCAP_THUMBEE 2048 | ||
19 | |||
20 | #if defined(__KERNEL__) && !defined(__ASSEMBLY__) | ||
21 | /* | ||
22 | * This yields a mask that user programs can use to figure out what | ||
23 | * instruction set this cpu supports. | ||
24 | */ | ||
25 | #define ELF_HWCAP (elf_hwcap) | ||
26 | extern unsigned int elf_hwcap; | ||
27 | #endif | ||
28 | |||
29 | #endif | ||
diff --git a/arch/arm/include/asm/ide.h b/arch/arm/include/asm/ide.h new file mode 100644 index 000000000000..b507ce8e5019 --- /dev/null +++ b/arch/arm/include/asm/ide.h | |||
@@ -0,0 +1,23 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/ide.h | ||
3 | * | ||
4 | * Copyright (C) 1994-1996 Linus Torvalds & authors | ||
5 | */ | ||
6 | |||
7 | /* | ||
8 | * This file contains the ARM architecture specific IDE code. | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASMARM_IDE_H | ||
12 | #define __ASMARM_IDE_H | ||
13 | |||
14 | #ifdef __KERNEL__ | ||
15 | |||
16 | #define __ide_mm_insw(port,addr,len) readsw(port,addr,len) | ||
17 | #define __ide_mm_insl(port,addr,len) readsl(port,addr,len) | ||
18 | #define __ide_mm_outsw(port,addr,len) writesw(port,addr,len) | ||
19 | #define __ide_mm_outsl(port,addr,len) writesl(port,addr,len) | ||
20 | |||
21 | #endif /* __KERNEL__ */ | ||
22 | |||
23 | #endif /* __ASMARM_IDE_H */ | ||
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h new file mode 100644 index 000000000000..ffe07c0f46d8 --- /dev/null +++ b/arch/arm/include/asm/io.h | |||
@@ -0,0 +1,287 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/io.h | ||
3 | * | ||
4 | * Copyright (C) 1996-2000 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * Modifications: | ||
11 | * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both | ||
12 | * constant addresses and variable addresses. | ||
13 | * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture | ||
14 | * specific IO header files. | ||
15 | * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. | ||
16 | * 04-Apr-1999 PJB Added check_signature. | ||
17 | * 12-Dec-1999 RMK More cleanups | ||
18 | * 18-Jun-2000 RMK Removed virt_to_* and friends definitions | ||
19 | * 05-Oct-2004 BJD Moved memory string functions to use void __iomem | ||
20 | */ | ||
21 | #ifndef __ASM_ARM_IO_H | ||
22 | #define __ASM_ARM_IO_H | ||
23 | |||
24 | #ifdef __KERNEL__ | ||
25 | |||
26 | #include <linux/types.h> | ||
27 | #include <asm/byteorder.h> | ||
28 | #include <asm/memory.h> | ||
29 | |||
30 | /* | ||
31 | * ISA I/O bus memory addresses are 1:1 with the physical address. | ||
32 | */ | ||
33 | #define isa_virt_to_bus virt_to_phys | ||
34 | #define isa_page_to_bus page_to_phys | ||
35 | #define isa_bus_to_virt phys_to_virt | ||
36 | |||
37 | /* | ||
38 | * Generic IO read/write. These perform native-endian accesses. Note | ||
39 | * that some architectures will want to re-define __raw_{read,write}w. | ||
40 | */ | ||
41 | extern void __raw_writesb(void __iomem *addr, const void *data, int bytelen); | ||
42 | extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen); | ||
43 | extern void __raw_writesl(void __iomem *addr, const void *data, int longlen); | ||
44 | |||
45 | extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen); | ||
46 | extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen); | ||
47 | extern void __raw_readsl(const void __iomem *addr, void *data, int longlen); | ||
48 | |||
49 | #define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile unsigned char __force *)(a) = (v)) | ||
50 | #define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)) | ||
51 | #define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile unsigned int __force *)(a) = (v)) | ||
52 | |||
53 | #define __raw_readb(a) (__chk_io_ptr(a), *(volatile unsigned char __force *)(a)) | ||
54 | #define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a)) | ||
55 | #define __raw_readl(a) (__chk_io_ptr(a), *(volatile unsigned int __force *)(a)) | ||
56 | |||
57 | /* | ||
58 | * Architecture ioremap implementation. | ||
59 | */ | ||
60 | #define MT_DEVICE 0 | ||
61 | #define MT_DEVICE_NONSHARED 1 | ||
62 | #define MT_DEVICE_CACHED 2 | ||
63 | #define MT_DEVICE_IXP2000 3 | ||
64 | /* | ||
65 | * types 4 onwards can be found in asm/mach/map.h and are undefined | ||
66 | * for ioremap | ||
67 | */ | ||
68 | |||
69 | /* | ||
70 | * __arm_ioremap takes CPU physical address. | ||
71 | * __arm_ioremap_pfn takes a Page Frame Number and an offset into that page | ||
72 | */ | ||
73 | extern void __iomem * __arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int); | ||
74 | extern void __iomem * __arm_ioremap(unsigned long, size_t, unsigned int); | ||
75 | extern void __iounmap(volatile void __iomem *addr); | ||
76 | |||
77 | /* | ||
78 | * Bad read/write accesses... | ||
79 | */ | ||
80 | extern void __readwrite_bug(const char *fn); | ||
81 | |||
82 | /* | ||
83 | * Now, pick up the machine-defined IO definitions | ||
84 | */ | ||
85 | #include <asm/arch/io.h> | ||
86 | |||
87 | /* | ||
88 | * IO port access primitives | ||
89 | * ------------------------- | ||
90 | * | ||
91 | * The ARM doesn't have special IO access instructions; all IO is memory | ||
92 | * mapped. Note that these are defined to perform little endian accesses | ||
93 | * only. Their primary purpose is to access PCI and ISA peripherals. | ||
94 | * | ||
95 | * Note that for a big endian machine, this implies that the following | ||
96 | * big endian mode connectivity is in place, as described by numerous | ||
97 | * ARM documents: | ||
98 | * | ||
99 | * PCI: D0-D7 D8-D15 D16-D23 D24-D31 | ||
100 | * ARM: D24-D31 D16-D23 D8-D15 D0-D7 | ||
101 | * | ||
102 | * The machine specific io.h include defines __io to translate an "IO" | ||
103 | * address to a memory address. | ||
104 | * | ||
105 | * Note that we prevent GCC re-ordering or caching values in expressions | ||
106 | * by introducing sequence points into the in*() definitions. Note that | ||
107 | * __raw_* do not guarantee this behaviour. | ||
108 | * | ||
109 | * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. | ||
110 | */ | ||
111 | #ifdef __io | ||
112 | #define outb(v,p) __raw_writeb(v,__io(p)) | ||
113 | #define outw(v,p) __raw_writew((__force __u16) \ | ||
114 | cpu_to_le16(v),__io(p)) | ||
115 | #define outl(v,p) __raw_writel((__force __u32) \ | ||
116 | cpu_to_le32(v),__io(p)) | ||
117 | |||
118 | #define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __v; }) | ||
119 | #define inw(p) ({ __u16 __v = le16_to_cpu((__force __le16) \ | ||
120 | __raw_readw(__io(p))); __v; }) | ||
121 | #define inl(p) ({ __u32 __v = le32_to_cpu((__force __le32) \ | ||
122 | __raw_readl(__io(p))); __v; }) | ||
123 | |||
124 | #define outsb(p,d,l) __raw_writesb(__io(p),d,l) | ||
125 | #define outsw(p,d,l) __raw_writesw(__io(p),d,l) | ||
126 | #define outsl(p,d,l) __raw_writesl(__io(p),d,l) | ||
127 | |||
128 | #define insb(p,d,l) __raw_readsb(__io(p),d,l) | ||
129 | #define insw(p,d,l) __raw_readsw(__io(p),d,l) | ||
130 | #define insl(p,d,l) __raw_readsl(__io(p),d,l) | ||
131 | #endif | ||
132 | |||
133 | #define outb_p(val,port) outb((val),(port)) | ||
134 | #define outw_p(val,port) outw((val),(port)) | ||
135 | #define outl_p(val,port) outl((val),(port)) | ||
136 | #define inb_p(port) inb((port)) | ||
137 | #define inw_p(port) inw((port)) | ||
138 | #define inl_p(port) inl((port)) | ||
139 | |||
140 | #define outsb_p(port,from,len) outsb(port,from,len) | ||
141 | #define outsw_p(port,from,len) outsw(port,from,len) | ||
142 | #define outsl_p(port,from,len) outsl(port,from,len) | ||
143 | #define insb_p(port,to,len) insb(port,to,len) | ||
144 | #define insw_p(port,to,len) insw(port,to,len) | ||
145 | #define insl_p(port,to,len) insl(port,to,len) | ||
146 | |||
147 | /* | ||
148 | * String version of IO memory access ops: | ||
149 | */ | ||
150 | extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t); | ||
151 | extern void _memcpy_toio(volatile void __iomem *, const void *, size_t); | ||
152 | extern void _memset_io(volatile void __iomem *, int, size_t); | ||
153 | |||
154 | #define mmiowb() | ||
155 | |||
156 | /* | ||
157 | * Memory access primitives | ||
158 | * ------------------------ | ||
159 | * | ||
160 | * These perform PCI memory accesses via an ioremap region. They don't | ||
161 | * take an address as such, but a cookie. | ||
162 | * | ||
163 | * Again, this are defined to perform little endian accesses. See the | ||
164 | * IO port primitives for more information. | ||
165 | */ | ||
166 | #ifdef __mem_pci | ||
167 | #define readb(c) ({ __u8 __v = __raw_readb(__mem_pci(c)); __v; }) | ||
168 | #define readw(c) ({ __u16 __v = le16_to_cpu((__force __le16) \ | ||
169 | __raw_readw(__mem_pci(c))); __v; }) | ||
170 | #define readl(c) ({ __u32 __v = le32_to_cpu((__force __le32) \ | ||
171 | __raw_readl(__mem_pci(c))); __v; }) | ||
172 | #define readb_relaxed(addr) readb(addr) | ||
173 | #define readw_relaxed(addr) readw(addr) | ||
174 | #define readl_relaxed(addr) readl(addr) | ||
175 | |||
176 | #define readsb(p,d,l) __raw_readsb(__mem_pci(p),d,l) | ||
177 | #define readsw(p,d,l) __raw_readsw(__mem_pci(p),d,l) | ||
178 | #define readsl(p,d,l) __raw_readsl(__mem_pci(p),d,l) | ||
179 | |||
180 | #define writeb(v,c) __raw_writeb(v,__mem_pci(c)) | ||
181 | #define writew(v,c) __raw_writew((__force __u16) \ | ||
182 | cpu_to_le16(v),__mem_pci(c)) | ||
183 | #define writel(v,c) __raw_writel((__force __u32) \ | ||
184 | cpu_to_le32(v),__mem_pci(c)) | ||
185 | |||
186 | #define writesb(p,d,l) __raw_writesb(__mem_pci(p),d,l) | ||
187 | #define writesw(p,d,l) __raw_writesw(__mem_pci(p),d,l) | ||
188 | #define writesl(p,d,l) __raw_writesl(__mem_pci(p),d,l) | ||
189 | |||
190 | #define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l)) | ||
191 | #define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l)) | ||
192 | #define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l)) | ||
193 | |||
194 | #elif !defined(readb) | ||
195 | |||
196 | #define readb(c) (__readwrite_bug("readb"),0) | ||
197 | #define readw(c) (__readwrite_bug("readw"),0) | ||
198 | #define readl(c) (__readwrite_bug("readl"),0) | ||
199 | #define writeb(v,c) __readwrite_bug("writeb") | ||
200 | #define writew(v,c) __readwrite_bug("writew") | ||
201 | #define writel(v,c) __readwrite_bug("writel") | ||
202 | |||
203 | #define check_signature(io,sig,len) (0) | ||
204 | |||
205 | #endif /* __mem_pci */ | ||
206 | |||
207 | /* | ||
208 | * ioremap and friends. | ||
209 | * | ||
210 | * ioremap takes a PCI memory address, as specified in | ||
211 | * Documentation/IO-mapping.txt. | ||
212 | * | ||
213 | */ | ||
214 | #ifndef __arch_ioremap | ||
215 | #define ioremap(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE) | ||
216 | #define ioremap_nocache(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE) | ||
217 | #define ioremap_cached(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE_CACHED) | ||
218 | #define iounmap(cookie) __iounmap(cookie) | ||
219 | #else | ||
220 | #define ioremap(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE) | ||
221 | #define ioremap_nocache(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE) | ||
222 | #define ioremap_cached(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE_CACHED) | ||
223 | #define iounmap(cookie) __arch_iounmap(cookie) | ||
224 | #endif | ||
225 | |||
226 | /* | ||
227 | * io{read,write}{8,16,32} macros | ||
228 | */ | ||
229 | #ifndef ioread8 | ||
230 | #define ioread8(p) ({ unsigned int __v = __raw_readb(p); __v; }) | ||
231 | #define ioread16(p) ({ unsigned int __v = le16_to_cpu((__force __le16)__raw_readw(p)); __v; }) | ||
232 | #define ioread32(p) ({ unsigned int __v = le32_to_cpu((__force __le32)__raw_readl(p)); __v; }) | ||
233 | |||
234 | #define iowrite8(v,p) __raw_writeb(v, p) | ||
235 | #define iowrite16(v,p) __raw_writew((__force __u16)cpu_to_le16(v), p) | ||
236 | #define iowrite32(v,p) __raw_writel((__force __u32)cpu_to_le32(v), p) | ||
237 | |||
238 | #define ioread8_rep(p,d,c) __raw_readsb(p,d,c) | ||
239 | #define ioread16_rep(p,d,c) __raw_readsw(p,d,c) | ||
240 | #define ioread32_rep(p,d,c) __raw_readsl(p,d,c) | ||
241 | |||
242 | #define iowrite8_rep(p,s,c) __raw_writesb(p,s,c) | ||
243 | #define iowrite16_rep(p,s,c) __raw_writesw(p,s,c) | ||
244 | #define iowrite32_rep(p,s,c) __raw_writesl(p,s,c) | ||
245 | |||
246 | extern void __iomem *ioport_map(unsigned long port, unsigned int nr); | ||
247 | extern void ioport_unmap(void __iomem *addr); | ||
248 | #endif | ||
249 | |||
250 | struct pci_dev; | ||
251 | |||
252 | extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen); | ||
253 | extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr); | ||
254 | |||
255 | /* | ||
256 | * can the hardware map this into one segment or not, given no other | ||
257 | * constraints. | ||
258 | */ | ||
259 | #define BIOVEC_MERGEABLE(vec1, vec2) \ | ||
260 | ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2))) | ||
261 | |||
262 | #ifdef CONFIG_MMU | ||
263 | #define ARCH_HAS_VALID_PHYS_ADDR_RANGE | ||
264 | extern int valid_phys_addr_range(unsigned long addr, size_t size); | ||
265 | extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); | ||
266 | #endif | ||
267 | |||
268 | /* | ||
269 | * Convert a physical pointer to a virtual kernel pointer for /dev/mem | ||
270 | * access | ||
271 | */ | ||
272 | #define xlate_dev_mem_ptr(p) __va(p) | ||
273 | |||
274 | /* | ||
275 | * Convert a virtual cached pointer to an uncached pointer | ||
276 | */ | ||
277 | #define xlate_dev_kmem_ptr(p) p | ||
278 | |||
279 | /* | ||
280 | * Register ISA memory and port locations for glibc iopl/inb/outb | ||
281 | * emulation. | ||
282 | */ | ||
283 | extern void register_isa_ports(unsigned int mmio, unsigned int io, | ||
284 | unsigned int io_shift); | ||
285 | |||
286 | #endif /* __KERNEL__ */ | ||
287 | #endif /* __ASM_ARM_IO_H */ | ||
diff --git a/arch/arm/include/asm/ioctl.h b/arch/arm/include/asm/ioctl.h new file mode 100644 index 000000000000..b279fe06dfe5 --- /dev/null +++ b/arch/arm/include/asm/ioctl.h | |||
@@ -0,0 +1 @@ | |||
#include <asm-generic/ioctl.h> | |||
diff --git a/arch/arm/include/asm/ioctls.h b/arch/arm/include/asm/ioctls.h new file mode 100644 index 000000000000..a91d8a1523cf --- /dev/null +++ b/arch/arm/include/asm/ioctls.h | |||
@@ -0,0 +1,84 @@ | |||
1 | #ifndef __ASM_ARM_IOCTLS_H | ||
2 | #define __ASM_ARM_IOCTLS_H | ||
3 | |||
4 | #include <asm/ioctl.h> | ||
5 | |||
6 | /* 0x54 is just a magic number to make these relatively unique ('T') */ | ||
7 | |||
8 | #define TCGETS 0x5401 | ||
9 | #define TCSETS 0x5402 | ||
10 | #define TCSETSW 0x5403 | ||
11 | #define TCSETSF 0x5404 | ||
12 | #define TCGETA 0x5405 | ||
13 | #define TCSETA 0x5406 | ||
14 | #define TCSETAW 0x5407 | ||
15 | #define TCSETAF 0x5408 | ||
16 | #define TCSBRK 0x5409 | ||
17 | #define TCXONC 0x540A | ||
18 | #define TCFLSH 0x540B | ||
19 | #define TIOCEXCL 0x540C | ||
20 | #define TIOCNXCL 0x540D | ||
21 | #define TIOCSCTTY 0x540E | ||
22 | #define TIOCGPGRP 0x540F | ||
23 | #define TIOCSPGRP 0x5410 | ||
24 | #define TIOCOUTQ 0x5411 | ||
25 | #define TIOCSTI 0x5412 | ||
26 | #define TIOCGWINSZ 0x5413 | ||
27 | #define TIOCSWINSZ 0x5414 | ||
28 | #define TIOCMGET 0x5415 | ||
29 | #define TIOCMBIS 0x5416 | ||
30 | #define TIOCMBIC 0x5417 | ||
31 | #define TIOCMSET 0x5418 | ||
32 | #define TIOCGSOFTCAR 0x5419 | ||
33 | #define TIOCSSOFTCAR 0x541A | ||
34 | #define FIONREAD 0x541B | ||
35 | #define TIOCINQ FIONREAD | ||
36 | #define TIOCLINUX 0x541C | ||
37 | #define TIOCCONS 0x541D | ||
38 | #define TIOCGSERIAL 0x541E | ||
39 | #define TIOCSSERIAL 0x541F | ||
40 | #define TIOCPKT 0x5420 | ||
41 | #define FIONBIO 0x5421 | ||
42 | #define TIOCNOTTY 0x5422 | ||
43 | #define TIOCSETD 0x5423 | ||
44 | #define TIOCGETD 0x5424 | ||
45 | #define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ | ||
46 | #define TIOCSBRK 0x5427 /* BSD compatibility */ | ||
47 | #define TIOCCBRK 0x5428 /* BSD compatibility */ | ||
48 | #define TIOCGSID 0x5429 /* Return the session ID of FD */ | ||
49 | #define TCGETS2 _IOR('T',0x2A, struct termios2) | ||
50 | #define TCSETS2 _IOW('T',0x2B, struct termios2) | ||
51 | #define TCSETSW2 _IOW('T',0x2C, struct termios2) | ||
52 | #define TCSETSF2 _IOW('T',0x2D, struct termios2) | ||
53 | #define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ | ||
54 | #define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ | ||
55 | |||
56 | #define FIONCLEX 0x5450 /* these numbers need to be adjusted. */ | ||
57 | #define FIOCLEX 0x5451 | ||
58 | #define FIOASYNC 0x5452 | ||
59 | #define TIOCSERCONFIG 0x5453 | ||
60 | #define TIOCSERGWILD 0x5454 | ||
61 | #define TIOCSERSWILD 0x5455 | ||
62 | #define TIOCGLCKTRMIOS 0x5456 | ||
63 | #define TIOCSLCKTRMIOS 0x5457 | ||
64 | #define TIOCSERGSTRUCT 0x5458 /* For debugging only */ | ||
65 | #define TIOCSERGETLSR 0x5459 /* Get line status register */ | ||
66 | #define TIOCSERGETMULTI 0x545A /* Get multiport config */ | ||
67 | #define TIOCSERSETMULTI 0x545B /* Set multiport config */ | ||
68 | |||
69 | #define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */ | ||
70 | #define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ | ||
71 | #define FIOQSIZE 0x545E | ||
72 | |||
73 | /* Used for packet mode */ | ||
74 | #define TIOCPKT_DATA 0 | ||
75 | #define TIOCPKT_FLUSHREAD 1 | ||
76 | #define TIOCPKT_FLUSHWRITE 2 | ||
77 | #define TIOCPKT_STOP 4 | ||
78 | #define TIOCPKT_START 8 | ||
79 | #define TIOCPKT_NOSTOP 16 | ||
80 | #define TIOCPKT_DOSTOP 32 | ||
81 | |||
82 | #define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ | ||
83 | |||
84 | #endif | ||
diff --git a/arch/arm/include/asm/ipcbuf.h b/arch/arm/include/asm/ipcbuf.h new file mode 100644 index 000000000000..97683975f7df --- /dev/null +++ b/arch/arm/include/asm/ipcbuf.h | |||
@@ -0,0 +1,29 @@ | |||
1 | #ifndef __ASMARM_IPCBUF_H | ||
2 | #define __ASMARM_IPCBUF_H | ||
3 | |||
4 | /* | ||
5 | * The ipc64_perm structure for arm architecture. | ||
6 | * Note extra padding because this structure is passed back and forth | ||
7 | * between kernel and user space. | ||
8 | * | ||
9 | * Pad space is left for: | ||
10 | * - 32-bit mode_t and seq | ||
11 | * - 2 miscellaneous 32-bit values | ||
12 | */ | ||
13 | |||
14 | struct ipc64_perm | ||
15 | { | ||
16 | __kernel_key_t key; | ||
17 | __kernel_uid32_t uid; | ||
18 | __kernel_gid32_t gid; | ||
19 | __kernel_uid32_t cuid; | ||
20 | __kernel_gid32_t cgid; | ||
21 | __kernel_mode_t mode; | ||
22 | unsigned short __pad1; | ||
23 | unsigned short seq; | ||
24 | unsigned short __pad2; | ||
25 | unsigned long __unused1; | ||
26 | unsigned long __unused2; | ||
27 | }; | ||
28 | |||
29 | #endif /* __ASMARM_IPCBUF_H */ | ||
diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h new file mode 100644 index 000000000000..9cb01907e43b --- /dev/null +++ b/arch/arm/include/asm/irq.h | |||
@@ -0,0 +1,28 @@ | |||
1 | #ifndef __ASM_ARM_IRQ_H | ||
2 | #define __ASM_ARM_IRQ_H | ||
3 | |||
4 | #include <asm/arch/irqs.h> | ||
5 | |||
6 | #ifndef irq_canonicalize | ||
7 | #define irq_canonicalize(i) (i) | ||
8 | #endif | ||
9 | |||
10 | #ifndef NR_IRQS | ||
11 | #define NR_IRQS 128 | ||
12 | #endif | ||
13 | |||
14 | /* | ||
15 | * Use this value to indicate lack of interrupt | ||
16 | * capability | ||
17 | */ | ||
18 | #ifndef NO_IRQ | ||
19 | #define NO_IRQ ((unsigned int)(-1)) | ||
20 | #endif | ||
21 | |||
22 | #ifndef __ASSEMBLY__ | ||
23 | struct irqaction; | ||
24 | extern void migrate_irqs(void); | ||
25 | #endif | ||
26 | |||
27 | #endif | ||
28 | |||
diff --git a/arch/arm/include/asm/irq_regs.h b/arch/arm/include/asm/irq_regs.h new file mode 100644 index 000000000000..3dd9c0b70270 --- /dev/null +++ b/arch/arm/include/asm/irq_regs.h | |||
@@ -0,0 +1 @@ | |||
#include <asm-generic/irq_regs.h> | |||
diff --git a/arch/arm/include/asm/irqflags.h b/arch/arm/include/asm/irqflags.h new file mode 100644 index 000000000000..6d09974e6646 --- /dev/null +++ b/arch/arm/include/asm/irqflags.h | |||
@@ -0,0 +1,132 @@ | |||
1 | #ifndef __ASM_ARM_IRQFLAGS_H | ||
2 | #define __ASM_ARM_IRQFLAGS_H | ||
3 | |||
4 | #ifdef __KERNEL__ | ||
5 | |||
6 | #include <asm/ptrace.h> | ||
7 | |||
8 | /* | ||
9 | * CPU interrupt mask handling. | ||
10 | */ | ||
11 | #if __LINUX_ARM_ARCH__ >= 6 | ||
12 | |||
13 | #define raw_local_irq_save(x) \ | ||
14 | ({ \ | ||
15 | __asm__ __volatile__( \ | ||
16 | "mrs %0, cpsr @ local_irq_save\n" \ | ||
17 | "cpsid i" \ | ||
18 | : "=r" (x) : : "memory", "cc"); \ | ||
19 | }) | ||
20 | |||
21 | #define raw_local_irq_enable() __asm__("cpsie i @ __sti" : : : "memory", "cc") | ||
22 | #define raw_local_irq_disable() __asm__("cpsid i @ __cli" : : : "memory", "cc") | ||
23 | #define local_fiq_enable() __asm__("cpsie f @ __stf" : : : "memory", "cc") | ||
24 | #define local_fiq_disable() __asm__("cpsid f @ __clf" : : : "memory", "cc") | ||
25 | |||
26 | #else | ||
27 | |||
28 | /* | ||
29 | * Save the current interrupt enable state & disable IRQs | ||
30 | */ | ||
31 | #define raw_local_irq_save(x) \ | ||
32 | ({ \ | ||
33 | unsigned long temp; \ | ||
34 | (void) (&temp == &x); \ | ||
35 | __asm__ __volatile__( \ | ||
36 | "mrs %0, cpsr @ local_irq_save\n" \ | ||
37 | " orr %1, %0, #128\n" \ | ||
38 | " msr cpsr_c, %1" \ | ||
39 | : "=r" (x), "=r" (temp) \ | ||
40 | : \ | ||
41 | : "memory", "cc"); \ | ||
42 | }) | ||
43 | |||
44 | /* | ||
45 | * Enable IRQs | ||
46 | */ | ||
47 | #define raw_local_irq_enable() \ | ||
48 | ({ \ | ||
49 | unsigned long temp; \ | ||
50 | __asm__ __volatile__( \ | ||
51 | "mrs %0, cpsr @ local_irq_enable\n" \ | ||
52 | " bic %0, %0, #128\n" \ | ||
53 | " msr cpsr_c, %0" \ | ||
54 | : "=r" (temp) \ | ||
55 | : \ | ||
56 | : "memory", "cc"); \ | ||
57 | }) | ||
58 | |||
59 | /* | ||
60 | * Disable IRQs | ||
61 | */ | ||
62 | #define raw_local_irq_disable() \ | ||
63 | ({ \ | ||
64 | unsigned long temp; \ | ||
65 | __asm__ __volatile__( \ | ||
66 | "mrs %0, cpsr @ local_irq_disable\n" \ | ||
67 | " orr %0, %0, #128\n" \ | ||
68 | " msr cpsr_c, %0" \ | ||
69 | : "=r" (temp) \ | ||
70 | : \ | ||
71 | : "memory", "cc"); \ | ||
72 | }) | ||
73 | |||
74 | /* | ||
75 | * Enable FIQs | ||
76 | */ | ||
77 | #define local_fiq_enable() \ | ||
78 | ({ \ | ||
79 | unsigned long temp; \ | ||
80 | __asm__ __volatile__( \ | ||
81 | "mrs %0, cpsr @ stf\n" \ | ||
82 | " bic %0, %0, #64\n" \ | ||
83 | " msr cpsr_c, %0" \ | ||
84 | : "=r" (temp) \ | ||
85 | : \ | ||
86 | : "memory", "cc"); \ | ||
87 | }) | ||
88 | |||
89 | /* | ||
90 | * Disable FIQs | ||
91 | */ | ||
92 | #define local_fiq_disable() \ | ||
93 | ({ \ | ||
94 | unsigned long temp; \ | ||
95 | __asm__ __volatile__( \ | ||
96 | "mrs %0, cpsr @ clf\n" \ | ||
97 | " orr %0, %0, #64\n" \ | ||
98 | " msr cpsr_c, %0" \ | ||
99 | : "=r" (temp) \ | ||
100 | : \ | ||
101 | : "memory", "cc"); \ | ||
102 | }) | ||
103 | |||
104 | #endif | ||
105 | |||
106 | /* | ||
107 | * Save the current interrupt enable state. | ||
108 | */ | ||
109 | #define raw_local_save_flags(x) \ | ||
110 | ({ \ | ||
111 | __asm__ __volatile__( \ | ||
112 | "mrs %0, cpsr @ local_save_flags" \ | ||
113 | : "=r" (x) : : "memory", "cc"); \ | ||
114 | }) | ||
115 | |||
116 | /* | ||
117 | * restore saved IRQ & FIQ state | ||
118 | */ | ||
119 | #define raw_local_irq_restore(x) \ | ||
120 | __asm__ __volatile__( \ | ||
121 | "msr cpsr_c, %0 @ local_irq_restore\n" \ | ||
122 | : \ | ||
123 | : "r" (x) \ | ||
124 | : "memory", "cc") | ||
125 | |||
126 | #define raw_irqs_disabled_flags(flags) \ | ||
127 | ({ \ | ||
128 | (int)((flags) & PSR_I_BIT); \ | ||
129 | }) | ||
130 | |||
131 | #endif | ||
132 | #endif | ||
diff --git a/arch/arm/include/asm/kdebug.h b/arch/arm/include/asm/kdebug.h new file mode 100644 index 000000000000..6ece1b037665 --- /dev/null +++ b/arch/arm/include/asm/kdebug.h | |||
@@ -0,0 +1 @@ | |||
#include <asm-generic/kdebug.h> | |||
diff --git a/arch/arm/include/asm/kexec.h b/arch/arm/include/asm/kexec.h new file mode 100644 index 000000000000..c8986bb99ed5 --- /dev/null +++ b/arch/arm/include/asm/kexec.h | |||
@@ -0,0 +1,31 @@ | |||
1 | #ifndef _ARM_KEXEC_H | ||
2 | #define _ARM_KEXEC_H | ||
3 | |||
4 | #ifdef CONFIG_KEXEC | ||
5 | |||
6 | /* Maximum physical address we can use pages from */ | ||
7 | #define KEXEC_SOURCE_MEMORY_LIMIT (-1UL) | ||
8 | /* Maximum address we can reach in physical address mode */ | ||
9 | #define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL) | ||
10 | /* Maximum address we can use for the control code buffer */ | ||
11 | #define KEXEC_CONTROL_MEMORY_LIMIT (-1UL) | ||
12 | |||
13 | #define KEXEC_CONTROL_CODE_SIZE 4096 | ||
14 | |||
15 | #define KEXEC_ARCH KEXEC_ARCH_ARM | ||
16 | |||
17 | #define KEXEC_ARM_ATAGS_OFFSET 0x1000 | ||
18 | #define KEXEC_ARM_ZIMAGE_OFFSET 0x8000 | ||
19 | |||
20 | #ifndef __ASSEMBLY__ | ||
21 | |||
22 | struct kimage; | ||
23 | /* Provide a dummy definition to avoid build failures. */ | ||
24 | static inline void crash_setup_regs(struct pt_regs *newregs, | ||
25 | struct pt_regs *oldregs) { } | ||
26 | |||
27 | #endif /* __ASSEMBLY__ */ | ||
28 | |||
29 | #endif /* CONFIG_KEXEC */ | ||
30 | |||
31 | #endif /* _ARM_KEXEC_H */ | ||
diff --git a/arch/arm/include/asm/kgdb.h b/arch/arm/include/asm/kgdb.h new file mode 100644 index 000000000000..67af4b841984 --- /dev/null +++ b/arch/arm/include/asm/kgdb.h | |||
@@ -0,0 +1,104 @@ | |||
1 | /* | ||
2 | * ARM KGDB support | ||
3 | * | ||
4 | * Author: Deepak Saxena <dsaxena@mvista.com> | ||
5 | * | ||
6 | * Copyright (C) 2002 MontaVista Software Inc. | ||
7 | * | ||
8 | */ | ||
9 | |||
10 | #ifndef __ARM_KGDB_H__ | ||
11 | #define __ARM_KGDB_H__ | ||
12 | |||
13 | #include <linux/ptrace.h> | ||
14 | |||
15 | /* | ||
16 | * GDB assumes that we're a user process being debugged, so | ||
17 | * it will send us an SWI command to write into memory as the | ||
18 | * debug trap. When an SWI occurs, the next instruction addr is | ||
19 | * placed into R14_svc before jumping to the vector trap. | ||
20 | * This doesn't work for kernel debugging as we are already in SVC | ||
21 | * we would loose the kernel's LR, which is a bad thing. This | ||
22 | * is bad thing. | ||
23 | * | ||
24 | * By doing this as an undefined instruction trap, we force a mode | ||
25 | * switch from SVC to UND mode, allowing us to save full kernel state. | ||
26 | * | ||
27 | * We also define a KGDB_COMPILED_BREAK which can be used to compile | ||
28 | * in breakpoints. This is important for things like sysrq-G and for | ||
29 | * the initial breakpoint from trap_init(). | ||
30 | * | ||
31 | * Note to ARM HW designers: Add real trap support like SH && PPC to | ||
32 | * make our lives much much simpler. :) | ||
33 | */ | ||
34 | #define BREAK_INSTR_SIZE 4 | ||
35 | #define GDB_BREAKINST 0xef9f0001 | ||
36 | #define KGDB_BREAKINST 0xe7ffdefe | ||
37 | #define KGDB_COMPILED_BREAK 0xe7ffdeff | ||
38 | #define CACHE_FLUSH_IS_SAFE 1 | ||
39 | |||
40 | #ifndef __ASSEMBLY__ | ||
41 | |||
42 | static inline void arch_kgdb_breakpoint(void) | ||
43 | { | ||
44 | asm(".word 0xe7ffdeff"); | ||
45 | } | ||
46 | |||
47 | extern void kgdb_handle_bus_error(void); | ||
48 | extern int kgdb_fault_expected; | ||
49 | |||
50 | #endif /* !__ASSEMBLY__ */ | ||
51 | |||
52 | /* | ||
53 | * From Kevin Hilman: | ||
54 | * | ||
55 | * gdb is expecting the following registers layout. | ||
56 | * | ||
57 | * r0-r15: 1 long word each | ||
58 | * f0-f7: unused, 3 long words each !! | ||
59 | * fps: unused, 1 long word | ||
60 | * cpsr: 1 long word | ||
61 | * | ||
62 | * Even though f0-f7 and fps are not used, they need to be | ||
63 | * present in the registers sent for correct processing in | ||
64 | * the host-side gdb. | ||
65 | * | ||
66 | * In particular, it is crucial that CPSR is in the right place, | ||
67 | * otherwise gdb will not be able to correctly interpret stepping over | ||
68 | * conditional branches. | ||
69 | */ | ||
70 | #define _GP_REGS 16 | ||
71 | #define _FP_REGS 8 | ||
72 | #define _EXTRA_REGS 2 | ||
73 | #define GDB_MAX_REGS (_GP_REGS + (_FP_REGS * 3) + _EXTRA_REGS) | ||
74 | |||
75 | #define KGDB_MAX_NO_CPUS 1 | ||
76 | #define BUFMAX 400 | ||
77 | #define NUMREGBYTES (GDB_MAX_REGS << 2) | ||
78 | #define NUMCRITREGBYTES (32 << 2) | ||
79 | |||
80 | #define _R0 0 | ||
81 | #define _R1 1 | ||
82 | #define _R2 2 | ||
83 | #define _R3 3 | ||
84 | #define _R4 4 | ||
85 | #define _R5 5 | ||
86 | #define _R6 6 | ||
87 | #define _R7 7 | ||
88 | #define _R8 8 | ||
89 | #define _R9 9 | ||
90 | #define _R10 10 | ||
91 | #define _FP 11 | ||
92 | #define _IP 12 | ||
93 | #define _SPT 13 | ||
94 | #define _LR 14 | ||
95 | #define _PC 15 | ||
96 | #define _CPSR (GDB_MAX_REGS - 1) | ||
97 | |||
98 | /* | ||
99 | * So that we can denote the end of a frame for tracing, | ||
100 | * in the simple case: | ||
101 | */ | ||
102 | #define CFI_END_FRAME(func) __CFI_END_FRAME(_PC, _SPT, func) | ||
103 | |||
104 | #endif /* __ASM_KGDB_H__ */ | ||
diff --git a/arch/arm/include/asm/kmap_types.h b/arch/arm/include/asm/kmap_types.h new file mode 100644 index 000000000000..45def13ee17a --- /dev/null +++ b/arch/arm/include/asm/kmap_types.h | |||
@@ -0,0 +1,24 @@ | |||
1 | #ifndef __ARM_KMAP_TYPES_H | ||
2 | #define __ARM_KMAP_TYPES_H | ||
3 | |||
4 | /* | ||
5 | * This is the "bare minimum". AIO seems to require this. | ||
6 | */ | ||
7 | enum km_type { | ||
8 | KM_BOUNCE_READ, | ||
9 | KM_SKB_SUNRPC_DATA, | ||
10 | KM_SKB_DATA_SOFTIRQ, | ||
11 | KM_USER0, | ||
12 | KM_USER1, | ||
13 | KM_BIO_SRC_IRQ, | ||
14 | KM_BIO_DST_IRQ, | ||
15 | KM_PTE0, | ||
16 | KM_PTE1, | ||
17 | KM_IRQ0, | ||
18 | KM_IRQ1, | ||
19 | KM_SOFTIRQ0, | ||
20 | KM_SOFTIRQ1, | ||
21 | KM_TYPE_NR | ||
22 | }; | ||
23 | |||
24 | #endif | ||
diff --git a/arch/arm/include/asm/kprobes.h b/arch/arm/include/asm/kprobes.h new file mode 100644 index 000000000000..a5d0d99ad387 --- /dev/null +++ b/arch/arm/include/asm/kprobes.h | |||
@@ -0,0 +1,79 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/kprobes.h | ||
3 | * | ||
4 | * Copyright (C) 2006, 2007 Motorola Inc. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, | ||
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
13 | * General Public License for more details. | ||
14 | */ | ||
15 | |||
16 | #ifndef _ARM_KPROBES_H | ||
17 | #define _ARM_KPROBES_H | ||
18 | |||
19 | #include <linux/types.h> | ||
20 | #include <linux/ptrace.h> | ||
21 | #include <linux/percpu.h> | ||
22 | |||
23 | #define __ARCH_WANT_KPROBES_INSN_SLOT | ||
24 | #define MAX_INSN_SIZE 2 | ||
25 | #define MAX_STACK_SIZE 64 /* 32 would probably be OK */ | ||
26 | |||
27 | /* | ||
28 | * This undefined instruction must be unique and | ||
29 | * reserved solely for kprobes' use. | ||
30 | */ | ||
31 | #define KPROBE_BREAKPOINT_INSTRUCTION 0xe7f001f8 | ||
32 | |||
33 | #define regs_return_value(regs) ((regs)->ARM_r0) | ||
34 | #define flush_insn_slot(p) do { } while (0) | ||
35 | #define kretprobe_blacklist_size 0 | ||
36 | |||
37 | typedef u32 kprobe_opcode_t; | ||
38 | |||
39 | struct kprobe; | ||
40 | typedef void (kprobe_insn_handler_t)(struct kprobe *, struct pt_regs *); | ||
41 | |||
42 | /* Architecture specific copy of original instruction. */ | ||
43 | struct arch_specific_insn { | ||
44 | kprobe_opcode_t *insn; | ||
45 | kprobe_insn_handler_t *insn_handler; | ||
46 | }; | ||
47 | |||
48 | struct prev_kprobe { | ||
49 | struct kprobe *kp; | ||
50 | unsigned int status; | ||
51 | }; | ||
52 | |||
53 | /* per-cpu kprobe control block */ | ||
54 | struct kprobe_ctlblk { | ||
55 | unsigned int kprobe_status; | ||
56 | struct prev_kprobe prev_kprobe; | ||
57 | struct pt_regs jprobe_saved_regs; | ||
58 | char jprobes_stack[MAX_STACK_SIZE]; | ||
59 | }; | ||
60 | |||
61 | void arch_remove_kprobe(struct kprobe *); | ||
62 | void kretprobe_trampoline(void); | ||
63 | |||
64 | int kprobe_trap_handler(struct pt_regs *regs, unsigned int instr); | ||
65 | int kprobe_fault_handler(struct pt_regs *regs, unsigned int fsr); | ||
66 | int kprobe_exceptions_notify(struct notifier_block *self, | ||
67 | unsigned long val, void *data); | ||
68 | |||
69 | enum kprobe_insn { | ||
70 | INSN_REJECTED, | ||
71 | INSN_GOOD, | ||
72 | INSN_GOOD_NO_SLOT | ||
73 | }; | ||
74 | |||
75 | enum kprobe_insn arm_kprobe_decode_insn(kprobe_opcode_t, | ||
76 | struct arch_specific_insn *); | ||
77 | void __init arm_kprobe_decode_init(void); | ||
78 | |||
79 | #endif /* _ARM_KPROBES_H */ | ||
diff --git a/arch/arm/include/asm/leds.h b/arch/arm/include/asm/leds.h new file mode 100644 index 000000000000..c545739f39b7 --- /dev/null +++ b/arch/arm/include/asm/leds.h | |||
@@ -0,0 +1,50 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/leds.h | ||
3 | * | ||
4 | * Copyright (C) 1998 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * Event-driven interface for LEDs on machines | ||
11 | * Added led_start and led_stop- Alex Holden, 28th Dec 1998. | ||
12 | */ | ||
13 | #ifndef ASM_ARM_LEDS_H | ||
14 | #define ASM_ARM_LEDS_H | ||
15 | |||
16 | |||
17 | typedef enum { | ||
18 | led_idle_start, | ||
19 | led_idle_end, | ||
20 | led_timer, | ||
21 | led_start, | ||
22 | led_stop, | ||
23 | led_claim, /* override idle & timer leds */ | ||
24 | led_release, /* restore idle & timer leds */ | ||
25 | led_start_timer_mode, | ||
26 | led_stop_timer_mode, | ||
27 | led_green_on, | ||
28 | led_green_off, | ||
29 | led_amber_on, | ||
30 | led_amber_off, | ||
31 | led_red_on, | ||
32 | led_red_off, | ||
33 | led_blue_on, | ||
34 | led_blue_off, | ||
35 | /* | ||
36 | * I want this between led_timer and led_start, but | ||
37 | * someone has decided to export this to user space | ||
38 | */ | ||
39 | led_halted | ||
40 | } led_event_t; | ||
41 | |||
42 | /* Use this routine to handle LEDs */ | ||
43 | |||
44 | #ifdef CONFIG_LEDS | ||
45 | extern void (*leds_event)(led_event_t); | ||
46 | #else | ||
47 | #define leds_event(e) | ||
48 | #endif | ||
49 | |||
50 | #endif | ||
diff --git a/arch/arm/include/asm/limits.h b/arch/arm/include/asm/limits.h new file mode 100644 index 000000000000..08d8c6600804 --- /dev/null +++ b/arch/arm/include/asm/limits.h | |||
@@ -0,0 +1,11 @@ | |||
1 | #ifndef __ASM_PIPE_H | ||
2 | #define __ASM_PIPE_H | ||
3 | |||
4 | #ifndef PAGE_SIZE | ||
5 | #include <asm/page.h> | ||
6 | #endif | ||
7 | |||
8 | #define PIPE_BUF PAGE_SIZE | ||
9 | |||
10 | #endif | ||
11 | |||
diff --git a/arch/arm/include/asm/linkage.h b/arch/arm/include/asm/linkage.h new file mode 100644 index 000000000000..5a25632b1bc0 --- /dev/null +++ b/arch/arm/include/asm/linkage.h | |||
@@ -0,0 +1,11 @@ | |||
1 | #ifndef __ASM_LINKAGE_H | ||
2 | #define __ASM_LINKAGE_H | ||
3 | |||
4 | #define __ALIGN .align 0 | ||
5 | #define __ALIGN_STR ".align 0" | ||
6 | |||
7 | #define ENDPROC(name) \ | ||
8 | .type name, %function; \ | ||
9 | END(name) | ||
10 | |||
11 | #endif | ||
diff --git a/arch/arm/include/asm/local.h b/arch/arm/include/asm/local.h new file mode 100644 index 000000000000..c11c530f74d0 --- /dev/null +++ b/arch/arm/include/asm/local.h | |||
@@ -0,0 +1 @@ | |||
#include <asm-generic/local.h> | |||
diff --git a/arch/arm/include/asm/locks.h b/arch/arm/include/asm/locks.h new file mode 100644 index 000000000000..ef4c897772d1 --- /dev/null +++ b/arch/arm/include/asm/locks.h | |||
@@ -0,0 +1,274 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/locks.h | ||
3 | * | ||
4 | * Copyright (C) 2000 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * Interrupt safe locking assembler. | ||
11 | */ | ||
12 | #ifndef __ASM_PROC_LOCKS_H | ||
13 | #define __ASM_PROC_LOCKS_H | ||
14 | |||
15 | #if __LINUX_ARM_ARCH__ >= 6 | ||
16 | |||
17 | #define __down_op(ptr,fail) \ | ||
18 | ({ \ | ||
19 | __asm__ __volatile__( \ | ||
20 | "@ down_op\n" \ | ||
21 | "1: ldrex lr, [%0]\n" \ | ||
22 | " sub lr, lr, %1\n" \ | ||
23 | " strex ip, lr, [%0]\n" \ | ||
24 | " teq ip, #0\n" \ | ||
25 | " bne 1b\n" \ | ||
26 | " teq lr, #0\n" \ | ||
27 | " movmi ip, %0\n" \ | ||
28 | " blmi " #fail \ | ||
29 | : \ | ||
30 | : "r" (ptr), "I" (1) \ | ||
31 | : "ip", "lr", "cc"); \ | ||
32 | smp_mb(); \ | ||
33 | }) | ||
34 | |||
35 | #define __down_op_ret(ptr,fail) \ | ||
36 | ({ \ | ||
37 | unsigned int ret; \ | ||
38 | __asm__ __volatile__( \ | ||
39 | "@ down_op_ret\n" \ | ||
40 | "1: ldrex lr, [%1]\n" \ | ||
41 | " sub lr, lr, %2\n" \ | ||
42 | " strex ip, lr, [%1]\n" \ | ||
43 | " teq ip, #0\n" \ | ||
44 | " bne 1b\n" \ | ||
45 | " teq lr, #0\n" \ | ||
46 | " movmi ip, %1\n" \ | ||
47 | " movpl ip, #0\n" \ | ||
48 | " blmi " #fail "\n" \ | ||
49 | " mov %0, ip" \ | ||
50 | : "=&r" (ret) \ | ||
51 | : "r" (ptr), "I" (1) \ | ||
52 | : "ip", "lr", "cc"); \ | ||
53 | smp_mb(); \ | ||
54 | ret; \ | ||
55 | }) | ||
56 | |||
57 | #define __up_op(ptr,wake) \ | ||
58 | ({ \ | ||
59 | smp_mb(); \ | ||
60 | __asm__ __volatile__( \ | ||
61 | "@ up_op\n" \ | ||
62 | "1: ldrex lr, [%0]\n" \ | ||
63 | " add lr, lr, %1\n" \ | ||
64 | " strex ip, lr, [%0]\n" \ | ||
65 | " teq ip, #0\n" \ | ||
66 | " bne 1b\n" \ | ||
67 | " cmp lr, #0\n" \ | ||
68 | " movle ip, %0\n" \ | ||
69 | " blle " #wake \ | ||
70 | : \ | ||
71 | : "r" (ptr), "I" (1) \ | ||
72 | : "ip", "lr", "cc"); \ | ||
73 | }) | ||
74 | |||
75 | /* | ||
76 | * The value 0x01000000 supports up to 128 processors and | ||
77 | * lots of processes. BIAS must be chosen such that sub'ing | ||
78 | * BIAS once per CPU will result in the long remaining | ||
79 | * negative. | ||
80 | */ | ||
81 | #define RW_LOCK_BIAS 0x01000000 | ||
82 | #define RW_LOCK_BIAS_STR "0x01000000" | ||
83 | |||
84 | #define __down_op_write(ptr,fail) \ | ||
85 | ({ \ | ||
86 | __asm__ __volatile__( \ | ||
87 | "@ down_op_write\n" \ | ||
88 | "1: ldrex lr, [%0]\n" \ | ||
89 | " sub lr, lr, %1\n" \ | ||
90 | " strex ip, lr, [%0]\n" \ | ||
91 | " teq ip, #0\n" \ | ||
92 | " bne 1b\n" \ | ||
93 | " teq lr, #0\n" \ | ||
94 | " movne ip, %0\n" \ | ||
95 | " blne " #fail \ | ||
96 | : \ | ||
97 | : "r" (ptr), "I" (RW_LOCK_BIAS) \ | ||
98 | : "ip", "lr", "cc"); \ | ||
99 | smp_mb(); \ | ||
100 | }) | ||
101 | |||
102 | #define __up_op_write(ptr,wake) \ | ||
103 | ({ \ | ||
104 | smp_mb(); \ | ||
105 | __asm__ __volatile__( \ | ||
106 | "@ up_op_write\n" \ | ||
107 | "1: ldrex lr, [%0]\n" \ | ||
108 | " adds lr, lr, %1\n" \ | ||
109 | " strex ip, lr, [%0]\n" \ | ||
110 | " teq ip, #0\n" \ | ||
111 | " bne 1b\n" \ | ||
112 | " movcs ip, %0\n" \ | ||
113 | " blcs " #wake \ | ||
114 | : \ | ||
115 | : "r" (ptr), "I" (RW_LOCK_BIAS) \ | ||
116 | : "ip", "lr", "cc"); \ | ||
117 | }) | ||
118 | |||
119 | #define __down_op_read(ptr,fail) \ | ||
120 | __down_op(ptr, fail) | ||
121 | |||
122 | #define __up_op_read(ptr,wake) \ | ||
123 | ({ \ | ||
124 | smp_mb(); \ | ||
125 | __asm__ __volatile__( \ | ||
126 | "@ up_op_read\n" \ | ||
127 | "1: ldrex lr, [%0]\n" \ | ||
128 | " add lr, lr, %1\n" \ | ||
129 | " strex ip, lr, [%0]\n" \ | ||
130 | " teq ip, #0\n" \ | ||
131 | " bne 1b\n" \ | ||
132 | " teq lr, #0\n" \ | ||
133 | " moveq ip, %0\n" \ | ||
134 | " bleq " #wake \ | ||
135 | : \ | ||
136 | : "r" (ptr), "I" (1) \ | ||
137 | : "ip", "lr", "cc"); \ | ||
138 | }) | ||
139 | |||
140 | #else | ||
141 | |||
142 | #define __down_op(ptr,fail) \ | ||
143 | ({ \ | ||
144 | __asm__ __volatile__( \ | ||
145 | "@ down_op\n" \ | ||
146 | " mrs ip, cpsr\n" \ | ||
147 | " orr lr, ip, #128\n" \ | ||
148 | " msr cpsr_c, lr\n" \ | ||
149 | " ldr lr, [%0]\n" \ | ||
150 | " subs lr, lr, %1\n" \ | ||
151 | " str lr, [%0]\n" \ | ||
152 | " msr cpsr_c, ip\n" \ | ||
153 | " movmi ip, %0\n" \ | ||
154 | " blmi " #fail \ | ||
155 | : \ | ||
156 | : "r" (ptr), "I" (1) \ | ||
157 | : "ip", "lr", "cc"); \ | ||
158 | smp_mb(); \ | ||
159 | }) | ||
160 | |||
161 | #define __down_op_ret(ptr,fail) \ | ||
162 | ({ \ | ||
163 | unsigned int ret; \ | ||
164 | __asm__ __volatile__( \ | ||
165 | "@ down_op_ret\n" \ | ||
166 | " mrs ip, cpsr\n" \ | ||
167 | " orr lr, ip, #128\n" \ | ||
168 | " msr cpsr_c, lr\n" \ | ||
169 | " ldr lr, [%1]\n" \ | ||
170 | " subs lr, lr, %2\n" \ | ||
171 | " str lr, [%1]\n" \ | ||
172 | " msr cpsr_c, ip\n" \ | ||
173 | " movmi ip, %1\n" \ | ||
174 | " movpl ip, #0\n" \ | ||
175 | " blmi " #fail "\n" \ | ||
176 | " mov %0, ip" \ | ||
177 | : "=&r" (ret) \ | ||
178 | : "r" (ptr), "I" (1) \ | ||
179 | : "ip", "lr", "cc"); \ | ||
180 | smp_mb(); \ | ||
181 | ret; \ | ||
182 | }) | ||
183 | |||
184 | #define __up_op(ptr,wake) \ | ||
185 | ({ \ | ||
186 | smp_mb(); \ | ||
187 | __asm__ __volatile__( \ | ||
188 | "@ up_op\n" \ | ||
189 | " mrs ip, cpsr\n" \ | ||
190 | " orr lr, ip, #128\n" \ | ||
191 | " msr cpsr_c, lr\n" \ | ||
192 | " ldr lr, [%0]\n" \ | ||
193 | " adds lr, lr, %1\n" \ | ||
194 | " str lr, [%0]\n" \ | ||
195 | " msr cpsr_c, ip\n" \ | ||
196 | " movle ip, %0\n" \ | ||
197 | " blle " #wake \ | ||
198 | : \ | ||
199 | : "r" (ptr), "I" (1) \ | ||
200 | : "ip", "lr", "cc"); \ | ||
201 | }) | ||
202 | |||
203 | /* | ||
204 | * The value 0x01000000 supports up to 128 processors and | ||
205 | * lots of processes. BIAS must be chosen such that sub'ing | ||
206 | * BIAS once per CPU will result in the long remaining | ||
207 | * negative. | ||
208 | */ | ||
209 | #define RW_LOCK_BIAS 0x01000000 | ||
210 | #define RW_LOCK_BIAS_STR "0x01000000" | ||
211 | |||
212 | #define __down_op_write(ptr,fail) \ | ||
213 | ({ \ | ||
214 | __asm__ __volatile__( \ | ||
215 | "@ down_op_write\n" \ | ||
216 | " mrs ip, cpsr\n" \ | ||
217 | " orr lr, ip, #128\n" \ | ||
218 | " msr cpsr_c, lr\n" \ | ||
219 | " ldr lr, [%0]\n" \ | ||
220 | " subs lr, lr, %1\n" \ | ||
221 | " str lr, [%0]\n" \ | ||
222 | " msr cpsr_c, ip\n" \ | ||
223 | " movne ip, %0\n" \ | ||
224 | " blne " #fail \ | ||
225 | : \ | ||
226 | : "r" (ptr), "I" (RW_LOCK_BIAS) \ | ||
227 | : "ip", "lr", "cc"); \ | ||
228 | smp_mb(); \ | ||
229 | }) | ||
230 | |||
231 | #define __up_op_write(ptr,wake) \ | ||
232 | ({ \ | ||
233 | __asm__ __volatile__( \ | ||
234 | "@ up_op_write\n" \ | ||
235 | " mrs ip, cpsr\n" \ | ||
236 | " orr lr, ip, #128\n" \ | ||
237 | " msr cpsr_c, lr\n" \ | ||
238 | " ldr lr, [%0]\n" \ | ||
239 | " adds lr, lr, %1\n" \ | ||
240 | " str lr, [%0]\n" \ | ||
241 | " msr cpsr_c, ip\n" \ | ||
242 | " movcs ip, %0\n" \ | ||
243 | " blcs " #wake \ | ||
244 | : \ | ||
245 | : "r" (ptr), "I" (RW_LOCK_BIAS) \ | ||
246 | : "ip", "lr", "cc"); \ | ||
247 | smp_mb(); \ | ||
248 | }) | ||
249 | |||
250 | #define __down_op_read(ptr,fail) \ | ||
251 | __down_op(ptr, fail) | ||
252 | |||
253 | #define __up_op_read(ptr,wake) \ | ||
254 | ({ \ | ||
255 | smp_mb(); \ | ||
256 | __asm__ __volatile__( \ | ||
257 | "@ up_op_read\n" \ | ||
258 | " mrs ip, cpsr\n" \ | ||
259 | " orr lr, ip, #128\n" \ | ||
260 | " msr cpsr_c, lr\n" \ | ||
261 | " ldr lr, [%0]\n" \ | ||
262 | " adds lr, lr, %1\n" \ | ||
263 | " str lr, [%0]\n" \ | ||
264 | " msr cpsr_c, ip\n" \ | ||
265 | " moveq ip, %0\n" \ | ||
266 | " bleq " #wake \ | ||
267 | : \ | ||
268 | : "r" (ptr), "I" (1) \ | ||
269 | : "ip", "lr", "cc"); \ | ||
270 | }) | ||
271 | |||
272 | #endif | ||
273 | |||
274 | #endif | ||
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h new file mode 100644 index 000000000000..c59842dc7cb8 --- /dev/null +++ b/arch/arm/include/asm/mach/arch.h | |||
@@ -0,0 +1,60 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/mach/arch.h | ||
3 | * | ||
4 | * Copyright (C) 2000 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASSEMBLY__ | ||
12 | |||
13 | struct tag; | ||
14 | struct meminfo; | ||
15 | struct sys_timer; | ||
16 | |||
17 | struct machine_desc { | ||
18 | /* | ||
19 | * Note! The first four elements are used | ||
20 | * by assembler code in head.S, head-common.S | ||
21 | */ | ||
22 | unsigned int nr; /* architecture number */ | ||
23 | unsigned int phys_io; /* start of physical io */ | ||
24 | unsigned int io_pg_offst; /* byte offset for io | ||
25 | * page tabe entry */ | ||
26 | |||
27 | const char *name; /* architecture name */ | ||
28 | unsigned long boot_params; /* tagged list */ | ||
29 | |||
30 | unsigned int video_start; /* start of video RAM */ | ||
31 | unsigned int video_end; /* end of video RAM */ | ||
32 | |||
33 | unsigned int reserve_lp0 :1; /* never has lp0 */ | ||
34 | unsigned int reserve_lp1 :1; /* never has lp1 */ | ||
35 | unsigned int reserve_lp2 :1; /* never has lp2 */ | ||
36 | unsigned int soft_reboot :1; /* soft reboot */ | ||
37 | void (*fixup)(struct machine_desc *, | ||
38 | struct tag *, char **, | ||
39 | struct meminfo *); | ||
40 | void (*map_io)(void);/* IO mapping function */ | ||
41 | void (*init_irq)(void); | ||
42 | struct sys_timer *timer; /* system tick timer */ | ||
43 | void (*init_machine)(void); | ||
44 | }; | ||
45 | |||
46 | /* | ||
47 | * Set of macros to define architecture features. This is built into | ||
48 | * a table by the linker. | ||
49 | */ | ||
50 | #define MACHINE_START(_type,_name) \ | ||
51 | static const struct machine_desc __mach_desc_##_type \ | ||
52 | __used \ | ||
53 | __attribute__((__section__(".arch.info.init"))) = { \ | ||
54 | .nr = MACH_TYPE_##_type, \ | ||
55 | .name = _name, | ||
56 | |||
57 | #define MACHINE_END \ | ||
58 | }; | ||
59 | |||
60 | #endif | ||
diff --git a/arch/arm/include/asm/mach/dma.h b/arch/arm/include/asm/mach/dma.h new file mode 100644 index 000000000000..fc7278ea7146 --- /dev/null +++ b/arch/arm/include/asm/mach/dma.h | |||
@@ -0,0 +1,57 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/mach/dma.h | ||
3 | * | ||
4 | * Copyright (C) 1998-2000 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * This header file describes the interface between the generic DMA handler | ||
11 | * (dma.c) and the architecture-specific DMA backends (dma-*.c) | ||
12 | */ | ||
13 | |||
14 | struct dma_struct; | ||
15 | typedef struct dma_struct dma_t; | ||
16 | |||
17 | struct dma_ops { | ||
18 | int (*request)(dmach_t, dma_t *); /* optional */ | ||
19 | void (*free)(dmach_t, dma_t *); /* optional */ | ||
20 | void (*enable)(dmach_t, dma_t *); /* mandatory */ | ||
21 | void (*disable)(dmach_t, dma_t *); /* mandatory */ | ||
22 | int (*residue)(dmach_t, dma_t *); /* optional */ | ||
23 | int (*setspeed)(dmach_t, dma_t *, int); /* optional */ | ||
24 | char *type; | ||
25 | }; | ||
26 | |||
27 | struct dma_struct { | ||
28 | void *addr; /* single DMA address */ | ||
29 | unsigned long count; /* single DMA size */ | ||
30 | struct scatterlist buf; /* single DMA */ | ||
31 | int sgcount; /* number of DMA SG */ | ||
32 | struct scatterlist *sg; /* DMA Scatter-Gather List */ | ||
33 | |||
34 | unsigned int active:1; /* Transfer active */ | ||
35 | unsigned int invalid:1; /* Address/Count changed */ | ||
36 | |||
37 | dmamode_t dma_mode; /* DMA mode */ | ||
38 | int speed; /* DMA speed */ | ||
39 | |||
40 | unsigned int lock; /* Device is allocated */ | ||
41 | const char *device_id; /* Device name */ | ||
42 | |||
43 | unsigned int dma_base; /* Controller base address */ | ||
44 | int dma_irq; /* Controller IRQ */ | ||
45 | struct scatterlist cur_sg; /* Current controller buffer */ | ||
46 | unsigned int state; | ||
47 | |||
48 | struct dma_ops *d_ops; | ||
49 | }; | ||
50 | |||
51 | /* Prototype: void arch_dma_init(dma) | ||
52 | * Purpose : Initialise architecture specific DMA | ||
53 | * Params : dma - pointer to array of DMA structures | ||
54 | */ | ||
55 | extern void arch_dma_init(dma_t *dma); | ||
56 | |||
57 | extern void isa_init_dma(dma_t *dma); | ||
diff --git a/arch/arm/include/asm/mach/flash.h b/arch/arm/include/asm/mach/flash.h new file mode 100644 index 000000000000..4ca69fe2c850 --- /dev/null +++ b/arch/arm/include/asm/mach/flash.h | |||
@@ -0,0 +1,39 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/mach/flash.h | ||
3 | * | ||
4 | * Copyright (C) 2003 Russell King, All Rights Reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #ifndef ASMARM_MACH_FLASH_H | ||
11 | #define ASMARM_MACH_FLASH_H | ||
12 | |||
13 | struct mtd_partition; | ||
14 | struct mtd_info; | ||
15 | |||
16 | /* | ||
17 | * map_name: the map probe function name | ||
18 | * name: flash device name (eg, as used with mtdparts=) | ||
19 | * width: width of mapped device | ||
20 | * init: method called at driver/device initialisation | ||
21 | * exit: method called at driver/device removal | ||
22 | * set_vpp: method called to enable or disable VPP | ||
23 | * mmcontrol: method called to enable or disable Sync. Burst Read in OneNAND | ||
24 | * parts: optional array of mtd_partitions for static partitioning | ||
25 | * nr_parts: number of mtd_partitions for static partitoning | ||
26 | */ | ||
27 | struct flash_platform_data { | ||
28 | const char *map_name; | ||
29 | const char *name; | ||
30 | unsigned int width; | ||
31 | int (*init)(void); | ||
32 | void (*exit)(void); | ||
33 | void (*set_vpp)(int on); | ||
34 | void (*mmcontrol)(struct mtd_info *mtd, int sync_read); | ||
35 | struct mtd_partition *parts; | ||
36 | unsigned int nr_parts; | ||
37 | }; | ||
38 | |||
39 | #endif | ||
diff --git a/arch/arm/include/asm/mach/irda.h b/arch/arm/include/asm/mach/irda.h new file mode 100644 index 000000000000..38f77b5e56cf --- /dev/null +++ b/arch/arm/include/asm/mach/irda.h | |||
@@ -0,0 +1,20 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/mach/irda.h | ||
3 | * | ||
4 | * Copyright (C) 2004 Russell King. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #ifndef __ASM_ARM_MACH_IRDA_H | ||
11 | #define __ASM_ARM_MACH_IRDA_H | ||
12 | |||
13 | struct irda_platform_data { | ||
14 | int (*startup)(struct device *); | ||
15 | void (*shutdown)(struct device *); | ||
16 | int (*set_power)(struct device *, unsigned int state); | ||
17 | void (*set_speed)(struct device *, unsigned int speed); | ||
18 | }; | ||
19 | |||
20 | #endif | ||
diff --git a/arch/arm/include/asm/mach/irq.h b/arch/arm/include/asm/mach/irq.h new file mode 100644 index 000000000000..c57b52ce574a --- /dev/null +++ b/arch/arm/include/asm/mach/irq.h | |||
@@ -0,0 +1,54 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/mach/irq.h | ||
3 | * | ||
4 | * Copyright (C) 1995-2000 Russell King. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #ifndef __ASM_ARM_MACH_IRQ_H | ||
11 | #define __ASM_ARM_MACH_IRQ_H | ||
12 | |||
13 | #include <linux/irq.h> | ||
14 | |||
15 | struct seq_file; | ||
16 | |||
17 | /* | ||
18 | * This is internal. Do not use it. | ||
19 | */ | ||
20 | extern void (*init_arch_irq)(void); | ||
21 | extern void init_FIQ(void); | ||
22 | extern int show_fiq_list(struct seq_file *, void *); | ||
23 | |||
24 | /* | ||
25 | * Obsolete inline function for calling irq descriptor handlers. | ||
26 | */ | ||
27 | static inline void desc_handle_irq(unsigned int irq, struct irq_desc *desc) | ||
28 | { | ||
29 | desc->handle_irq(irq, desc); | ||
30 | } | ||
31 | |||
32 | void set_irq_flags(unsigned int irq, unsigned int flags); | ||
33 | |||
34 | #define IRQF_VALID (1 << 0) | ||
35 | #define IRQF_PROBE (1 << 1) | ||
36 | #define IRQF_NOAUTOEN (1 << 2) | ||
37 | |||
38 | /* | ||
39 | * This is for easy migration, but should be changed in the source | ||
40 | */ | ||
41 | #define do_bad_IRQ(irq,desc) \ | ||
42 | do { \ | ||
43 | spin_lock(&desc->lock); \ | ||
44 | handle_bad_irq(irq, desc); \ | ||
45 | spin_unlock(&desc->lock); \ | ||
46 | } while(0) | ||
47 | |||
48 | extern unsigned long irq_err_count; | ||
49 | static inline void ack_bad_irq(int irq) | ||
50 | { | ||
51 | irq_err_count++; | ||
52 | } | ||
53 | |||
54 | #endif | ||
diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h new file mode 100644 index 000000000000..06f583b13999 --- /dev/null +++ b/arch/arm/include/asm/mach/map.h | |||
@@ -0,0 +1,36 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/map.h | ||
3 | * | ||
4 | * Copyright (C) 1999-2000 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * Page table mapping constructs and function prototypes | ||
11 | */ | ||
12 | #include <asm/io.h> | ||
13 | |||
14 | struct map_desc { | ||
15 | unsigned long virtual; | ||
16 | unsigned long pfn; | ||
17 | unsigned long length; | ||
18 | unsigned int type; | ||
19 | }; | ||
20 | |||
21 | /* types 0-3 are defined in asm/io.h */ | ||
22 | #define MT_CACHECLEAN 4 | ||
23 | #define MT_MINICLEAN 5 | ||
24 | #define MT_LOW_VECTORS 6 | ||
25 | #define MT_HIGH_VECTORS 7 | ||
26 | #define MT_MEMORY 8 | ||
27 | #define MT_ROM 9 | ||
28 | |||
29 | #define MT_NONSHARED_DEVICE MT_DEVICE_NONSHARED | ||
30 | #define MT_IXP2000_DEVICE MT_DEVICE_IXP2000 | ||
31 | |||
32 | #ifdef CONFIG_MMU | ||
33 | extern void iotable_init(struct map_desc *, int); | ||
34 | #else | ||
35 | #define iotable_init(map,num) do { } while (0) | ||
36 | #endif | ||
diff --git a/arch/arm/include/asm/mach/mmc.h b/arch/arm/include/asm/mach/mmc.h new file mode 100644 index 000000000000..4da332b03144 --- /dev/null +++ b/arch/arm/include/asm/mach/mmc.h | |||
@@ -0,0 +1,15 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/mach/mmc.h | ||
3 | */ | ||
4 | #ifndef ASMARM_MACH_MMC_H | ||
5 | #define ASMARM_MACH_MMC_H | ||
6 | |||
7 | #include <linux/mmc/host.h> | ||
8 | |||
9 | struct mmc_platform_data { | ||
10 | unsigned int ocr_mask; /* available voltages */ | ||
11 | u32 (*translate_vdd)(struct device *, unsigned int); | ||
12 | unsigned int (*status)(struct device *); | ||
13 | }; | ||
14 | |||
15 | #endif | ||
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h new file mode 100644 index 000000000000..32da1ae17e06 --- /dev/null +++ b/arch/arm/include/asm/mach/pci.h | |||
@@ -0,0 +1,72 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/mach/pci.h | ||
3 | * | ||
4 | * Copyright (C) 2000 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | struct pci_sys_data; | ||
12 | struct pci_bus; | ||
13 | |||
14 | struct hw_pci { | ||
15 | struct list_head buses; | ||
16 | int nr_controllers; | ||
17 | int (*setup)(int nr, struct pci_sys_data *); | ||
18 | struct pci_bus *(*scan)(int nr, struct pci_sys_data *); | ||
19 | void (*preinit)(void); | ||
20 | void (*postinit)(void); | ||
21 | u8 (*swizzle)(struct pci_dev *dev, u8 *pin); | ||
22 | int (*map_irq)(struct pci_dev *dev, u8 slot, u8 pin); | ||
23 | }; | ||
24 | |||
25 | /* | ||
26 | * Per-controller structure | ||
27 | */ | ||
28 | struct pci_sys_data { | ||
29 | struct list_head node; | ||
30 | int busnr; /* primary bus number */ | ||
31 | u64 mem_offset; /* bus->cpu memory mapping offset */ | ||
32 | unsigned long io_offset; /* bus->cpu IO mapping offset */ | ||
33 | struct pci_bus *bus; /* PCI bus */ | ||
34 | struct resource *resource[3]; /* Primary PCI bus resources */ | ||
35 | /* Bridge swizzling */ | ||
36 | u8 (*swizzle)(struct pci_dev *, u8 *); | ||
37 | /* IRQ mapping */ | ||
38 | int (*map_irq)(struct pci_dev *, u8, u8); | ||
39 | struct hw_pci *hw; | ||
40 | }; | ||
41 | |||
42 | /* | ||
43 | * This is the standard PCI-PCI bridge swizzling algorithm. | ||
44 | */ | ||
45 | u8 pci_std_swizzle(struct pci_dev *dev, u8 *pinp); | ||
46 | |||
47 | /* | ||
48 | * Call this with your hw_pci struct to initialise the PCI system. | ||
49 | */ | ||
50 | void pci_common_init(struct hw_pci *); | ||
51 | |||
52 | /* | ||
53 | * PCI controllers | ||
54 | */ | ||
55 | extern int iop3xx_pci_setup(int nr, struct pci_sys_data *); | ||
56 | extern struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *); | ||
57 | extern void iop3xx_pci_preinit(void); | ||
58 | extern void iop3xx_pci_preinit_cond(void); | ||
59 | |||
60 | extern int dc21285_setup(int nr, struct pci_sys_data *); | ||
61 | extern struct pci_bus *dc21285_scan_bus(int nr, struct pci_sys_data *); | ||
62 | extern void dc21285_preinit(void); | ||
63 | extern void dc21285_postinit(void); | ||
64 | |||
65 | extern int via82c505_setup(int nr, struct pci_sys_data *); | ||
66 | extern struct pci_bus *via82c505_scan_bus(int nr, struct pci_sys_data *); | ||
67 | extern void via82c505_init(void *sysdata); | ||
68 | |||
69 | extern int pci_v3_setup(int nr, struct pci_sys_data *); | ||
70 | extern struct pci_bus *pci_v3_scan_bus(int nr, struct pci_sys_data *); | ||
71 | extern void pci_v3_preinit(void); | ||
72 | extern void pci_v3_postinit(void); | ||
diff --git a/arch/arm/include/asm/mach/serial_at91.h b/arch/arm/include/asm/mach/serial_at91.h new file mode 100644 index 000000000000..ea6d063923b8 --- /dev/null +++ b/arch/arm/include/asm/mach/serial_at91.h | |||
@@ -0,0 +1,33 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/mach/serial_at91.h | ||
3 | * | ||
4 | * Based on serial_sa1100.h by Nicolas Pitre | ||
5 | * | ||
6 | * Copyright (C) 2002 ATMEL Rousset | ||
7 | * | ||
8 | * Low level machine dependent UART functions. | ||
9 | */ | ||
10 | |||
11 | struct uart_port; | ||
12 | |||
13 | /* | ||
14 | * This is a temporary structure for registering these | ||
15 | * functions; it is intended to be discarded after boot. | ||
16 | */ | ||
17 | struct atmel_port_fns { | ||
18 | void (*set_mctrl)(struct uart_port *, u_int); | ||
19 | u_int (*get_mctrl)(struct uart_port *); | ||
20 | void (*enable_ms)(struct uart_port *); | ||
21 | void (*pm)(struct uart_port *, u_int, u_int); | ||
22 | int (*set_wake)(struct uart_port *, u_int); | ||
23 | int (*open)(struct uart_port *); | ||
24 | void (*close)(struct uart_port *); | ||
25 | }; | ||
26 | |||
27 | #if defined(CONFIG_SERIAL_ATMEL) | ||
28 | void atmel_register_uart_fns(struct atmel_port_fns *fns); | ||
29 | #else | ||
30 | #define atmel_register_uart_fns(fns) do { } while (0) | ||
31 | #endif | ||
32 | |||
33 | |||
diff --git a/arch/arm/include/asm/mach/serial_sa1100.h b/arch/arm/include/asm/mach/serial_sa1100.h new file mode 100644 index 000000000000..d09064bf95a0 --- /dev/null +++ b/arch/arm/include/asm/mach/serial_sa1100.h | |||
@@ -0,0 +1,31 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/mach/serial_sa1100.h | ||
3 | * | ||
4 | * Author: Nicolas Pitre | ||
5 | * | ||
6 | * Moved and changed lots, Russell King | ||
7 | * | ||
8 | * Low level machine dependent UART functions. | ||
9 | */ | ||
10 | |||
11 | struct uart_port; | ||
12 | struct uart_info; | ||
13 | |||
14 | /* | ||
15 | * This is a temporary structure for registering these | ||
16 | * functions; it is intended to be discarded after boot. | ||
17 | */ | ||
18 | struct sa1100_port_fns { | ||
19 | void (*set_mctrl)(struct uart_port *, u_int); | ||
20 | u_int (*get_mctrl)(struct uart_port *); | ||
21 | void (*pm)(struct uart_port *, u_int, u_int); | ||
22 | int (*set_wake)(struct uart_port *, u_int); | ||
23 | }; | ||
24 | |||
25 | #ifdef CONFIG_SERIAL_SA1100 | ||
26 | void sa1100_register_uart_fns(struct sa1100_port_fns *fns); | ||
27 | void sa1100_register_uart(int idx, int port); | ||
28 | #else | ||
29 | #define sa1100_register_uart_fns(fns) do { } while (0) | ||
30 | #define sa1100_register_uart(idx,port) do { } while (0) | ||
31 | #endif | ||
diff --git a/arch/arm/include/asm/mach/sharpsl_param.h b/arch/arm/include/asm/mach/sharpsl_param.h new file mode 100644 index 000000000000..7a24ecf04220 --- /dev/null +++ b/arch/arm/include/asm/mach/sharpsl_param.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /* | ||
2 | * Hardware parameter area specific to Sharp SL series devices | ||
3 | * | ||
4 | * Copyright (c) 2005 Richard Purdie | ||
5 | * | ||
6 | * Based on Sharp's 2.4 kernel patches | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | struct sharpsl_param_info { | ||
15 | unsigned int comadj_keyword; | ||
16 | unsigned int comadj; | ||
17 | |||
18 | unsigned int uuid_keyword; | ||
19 | unsigned char uuid[16]; | ||
20 | |||
21 | unsigned int touch_keyword; | ||
22 | unsigned int touch_xp; | ||
23 | unsigned int touch_yp; | ||
24 | unsigned int touch_xd; | ||
25 | unsigned int touch_yd; | ||
26 | |||
27 | unsigned int adadj_keyword; | ||
28 | unsigned int adadj; | ||
29 | |||
30 | unsigned int phad_keyword; | ||
31 | unsigned int phadadj; | ||
32 | } __attribute__((packed)); | ||
33 | |||
34 | |||
35 | extern struct sharpsl_param_info sharpsl_param; | ||
36 | extern void sharpsl_save_param(void); | ||
37 | |||
diff --git a/arch/arm/include/asm/mach/time.h b/arch/arm/include/asm/mach/time.h new file mode 100644 index 000000000000..b2cc1fcd0400 --- /dev/null +++ b/arch/arm/include/asm/mach/time.h | |||
@@ -0,0 +1,57 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/mach/time.h | ||
3 | * | ||
4 | * Copyright (C) 2004 MontaVista Software, Inc. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #ifndef __ASM_ARM_MACH_TIME_H | ||
11 | #define __ASM_ARM_MACH_TIME_H | ||
12 | |||
13 | #include <linux/sysdev.h> | ||
14 | |||
15 | /* | ||
16 | * This is our kernel timer structure. | ||
17 | * | ||
18 | * - init | ||
19 | * Initialise the kernels jiffy timer source, claim interrupt | ||
20 | * using setup_irq. This is called early on during initialisation | ||
21 | * while interrupts are still disabled on the local CPU. | ||
22 | * - suspend | ||
23 | * Suspend the kernel jiffy timer source, if necessary. This | ||
24 | * is called with interrupts disabled, after all normal devices | ||
25 | * have been suspended. If no action is required, set this to | ||
26 | * NULL. | ||
27 | * - resume | ||
28 | * Resume the kernel jiffy timer source, if necessary. This | ||
29 | * is called with interrupts disabled before any normal devices | ||
30 | * are resumed. If no action is required, set this to NULL. | ||
31 | * - offset | ||
32 | * Return the timer offset in microseconds since the last timer | ||
33 | * interrupt. Note: this must take account of any unprocessed | ||
34 | * timer interrupt which may be pending. | ||
35 | */ | ||
36 | struct sys_timer { | ||
37 | struct sys_device dev; | ||
38 | void (*init)(void); | ||
39 | void (*suspend)(void); | ||
40 | void (*resume)(void); | ||
41 | #ifndef CONFIG_GENERIC_TIME | ||
42 | unsigned long (*offset)(void); | ||
43 | #endif | ||
44 | }; | ||
45 | |||
46 | extern struct sys_timer *system_timer; | ||
47 | extern void timer_tick(void); | ||
48 | |||
49 | /* | ||
50 | * Kernel time keeping support. | ||
51 | */ | ||
52 | struct timespec; | ||
53 | extern int (*set_rtc)(void); | ||
54 | extern void save_time_delta(struct timespec *delta, struct timespec *rtc); | ||
55 | extern void restore_time_delta(struct timespec *delta, struct timespec *rtc); | ||
56 | |||
57 | #endif | ||
diff --git a/arch/arm/include/asm/mach/udc_pxa2xx.h b/arch/arm/include/asm/mach/udc_pxa2xx.h new file mode 100644 index 000000000000..270902c353fd --- /dev/null +++ b/arch/arm/include/asm/mach/udc_pxa2xx.h | |||
@@ -0,0 +1,29 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/mach/udc_pxa2xx.h | ||
3 | * | ||
4 | * This supports machine-specific differences in how the PXA2xx | ||
5 | * USB Device Controller (UDC) is wired. | ||
6 | * | ||
7 | * It is set in linux/arch/arm/mach-pxa/<machine>.c or in | ||
8 | * linux/arch/mach-ixp4xx/<machine>.c and used in | ||
9 | * the probe routine of linux/drivers/usb/gadget/pxa2xx_udc.c | ||
10 | */ | ||
11 | |||
12 | struct pxa2xx_udc_mach_info { | ||
13 | int (*udc_is_connected)(void); /* do we see host? */ | ||
14 | void (*udc_command)(int cmd); | ||
15 | #define PXA2XX_UDC_CMD_CONNECT 0 /* let host see us */ | ||
16 | #define PXA2XX_UDC_CMD_DISCONNECT 1 /* so host won't see us */ | ||
17 | |||
18 | /* Boards following the design guidelines in the developer's manual, | ||
19 | * with on-chip GPIOs not Lubbock's weird hardware, can have a sane | ||
20 | * VBUS IRQ and omit the methods above. Store the GPIO number | ||
21 | * here; for GPIO 0, also mask in one of the pxa_gpio_mode() bits. | ||
22 | * Note that sometimes the signals go through inverters... | ||
23 | */ | ||
24 | bool gpio_vbus_inverted; | ||
25 | u16 gpio_vbus; /* high == vbus present */ | ||
26 | bool gpio_pullup_inverted; | ||
27 | u16 gpio_pullup; /* high == pullup activated */ | ||
28 | }; | ||
29 | |||
diff --git a/arch/arm/include/asm/mc146818rtc.h b/arch/arm/include/asm/mc146818rtc.h new file mode 100644 index 000000000000..7b81e0c42543 --- /dev/null +++ b/arch/arm/include/asm/mc146818rtc.h | |||
@@ -0,0 +1,28 @@ | |||
1 | /* | ||
2 | * Machine dependent access functions for RTC registers. | ||
3 | */ | ||
4 | #ifndef _ASM_MC146818RTC_H | ||
5 | #define _ASM_MC146818RTC_H | ||
6 | |||
7 | #include <asm/arch/irqs.h> | ||
8 | #include <asm/io.h> | ||
9 | |||
10 | #ifndef RTC_PORT | ||
11 | #define RTC_PORT(x) (0x70 + (x)) | ||
12 | #define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */ | ||
13 | #endif | ||
14 | |||
15 | /* | ||
16 | * The yet supported machines all access the RTC index register via | ||
17 | * an ISA port access but the way to access the date register differs ... | ||
18 | */ | ||
19 | #define CMOS_READ(addr) ({ \ | ||
20 | outb_p((addr),RTC_PORT(0)); \ | ||
21 | inb_p(RTC_PORT(1)); \ | ||
22 | }) | ||
23 | #define CMOS_WRITE(val, addr) ({ \ | ||
24 | outb_p((addr),RTC_PORT(0)); \ | ||
25 | outb_p((val),RTC_PORT(1)); \ | ||
26 | }) | ||
27 | |||
28 | #endif /* _ASM_MC146818RTC_H */ | ||
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h new file mode 100644 index 000000000000..92069221dca9 --- /dev/null +++ b/arch/arm/include/asm/memory.h | |||
@@ -0,0 +1,334 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/memory.h | ||
3 | * | ||
4 | * Copyright (C) 2000-2002 Russell King | ||
5 | * modification for nommu, Hyok S. Choi, 2004 | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | * | ||
11 | * Note: this file should not be included by non-asm/.h files | ||
12 | */ | ||
13 | #ifndef __ASM_ARM_MEMORY_H | ||
14 | #define __ASM_ARM_MEMORY_H | ||
15 | |||
16 | /* | ||
17 | * Allow for constants defined here to be used from assembly code | ||
18 | * by prepending the UL suffix only with actual C code compilation. | ||
19 | */ | ||
20 | #ifndef __ASSEMBLY__ | ||
21 | #define UL(x) (x##UL) | ||
22 | #else | ||
23 | #define UL(x) (x) | ||
24 | #endif | ||
25 | |||
26 | #include <linux/compiler.h> | ||
27 | #include <asm/arch/memory.h> | ||
28 | #include <asm/sizes.h> | ||
29 | |||
30 | #ifdef CONFIG_MMU | ||
31 | |||
32 | #ifndef TASK_SIZE | ||
33 | /* | ||
34 | * TASK_SIZE - the maximum size of a user space task. | ||
35 | * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area | ||
36 | */ | ||
37 | #define TASK_SIZE UL(0xbf000000) | ||
38 | #define TASK_UNMAPPED_BASE UL(0x40000000) | ||
39 | #endif | ||
40 | |||
41 | /* | ||
42 | * The maximum size of a 26-bit user space task. | ||
43 | */ | ||
44 | #define TASK_SIZE_26 UL(0x04000000) | ||
45 | |||
46 | /* | ||
47 | * Page offset: 3GB | ||
48 | */ | ||
49 | #ifndef PAGE_OFFSET | ||
50 | #define PAGE_OFFSET UL(0xc0000000) | ||
51 | #endif | ||
52 | |||
53 | /* | ||
54 | * The module space lives between the addresses given by TASK_SIZE | ||
55 | * and PAGE_OFFSET - it must be within 32MB of the kernel text. | ||
56 | */ | ||
57 | #define MODULE_END (PAGE_OFFSET) | ||
58 | #define MODULE_START (MODULE_END - 16*1048576) | ||
59 | |||
60 | #if TASK_SIZE > MODULE_START | ||
61 | #error Top of user space clashes with start of module space | ||
62 | #endif | ||
63 | |||
64 | /* | ||
65 | * The XIP kernel gets mapped at the bottom of the module vm area. | ||
66 | * Since we use sections to map it, this macro replaces the physical address | ||
67 | * with its virtual address while keeping offset from the base section. | ||
68 | */ | ||
69 | #define XIP_VIRT_ADDR(physaddr) (MODULE_START + ((physaddr) & 0x000fffff)) | ||
70 | |||
71 | /* | ||
72 | * Allow 16MB-aligned ioremap pages | ||
73 | */ | ||
74 | #define IOREMAP_MAX_ORDER 24 | ||
75 | |||
76 | #else /* CONFIG_MMU */ | ||
77 | |||
78 | /* | ||
79 | * The limitation of user task size can grow up to the end of free ram region. | ||
80 | * It is difficult to define and perhaps will never meet the original meaning | ||
81 | * of this define that was meant to. | ||
82 | * Fortunately, there is no reference for this in noMMU mode, for now. | ||
83 | */ | ||
84 | #ifndef TASK_SIZE | ||
85 | #define TASK_SIZE (CONFIG_DRAM_SIZE) | ||
86 | #endif | ||
87 | |||
88 | #ifndef TASK_UNMAPPED_BASE | ||
89 | #define TASK_UNMAPPED_BASE UL(0x00000000) | ||
90 | #endif | ||
91 | |||
92 | #ifndef PHYS_OFFSET | ||
93 | #define PHYS_OFFSET (CONFIG_DRAM_BASE) | ||
94 | #endif | ||
95 | |||
96 | #ifndef END_MEM | ||
97 | #define END_MEM (CONFIG_DRAM_BASE + CONFIG_DRAM_SIZE) | ||
98 | #endif | ||
99 | |||
100 | #ifndef PAGE_OFFSET | ||
101 | #define PAGE_OFFSET (PHYS_OFFSET) | ||
102 | #endif | ||
103 | |||
104 | /* | ||
105 | * The module can be at any place in ram in nommu mode. | ||
106 | */ | ||
107 | #define MODULE_END (END_MEM) | ||
108 | #define MODULE_START (PHYS_OFFSET) | ||
109 | |||
110 | #endif /* !CONFIG_MMU */ | ||
111 | |||
112 | /* | ||
113 | * Size of DMA-consistent memory region. Must be multiple of 2M, | ||
114 | * between 2MB and 14MB inclusive. | ||
115 | */ | ||
116 | #ifndef CONSISTENT_DMA_SIZE | ||
117 | #define CONSISTENT_DMA_SIZE SZ_2M | ||
118 | #endif | ||
119 | |||
120 | /* | ||
121 | * Physical vs virtual RAM address space conversion. These are | ||
122 | * private definitions which should NOT be used outside memory.h | ||
123 | * files. Use virt_to_phys/phys_to_virt/__pa/__va instead. | ||
124 | */ | ||
125 | #ifndef __virt_to_phys | ||
126 | #define __virt_to_phys(x) ((x) - PAGE_OFFSET + PHYS_OFFSET) | ||
127 | #define __phys_to_virt(x) ((x) - PHYS_OFFSET + PAGE_OFFSET) | ||
128 | #endif | ||
129 | |||
130 | /* | ||
131 | * Convert a physical address to a Page Frame Number and back | ||
132 | */ | ||
133 | #define __phys_to_pfn(paddr) ((paddr) >> PAGE_SHIFT) | ||
134 | #define __pfn_to_phys(pfn) ((pfn) << PAGE_SHIFT) | ||
135 | |||
136 | #ifndef __ASSEMBLY__ | ||
137 | |||
138 | /* | ||
139 | * The DMA mask corresponding to the maximum bus address allocatable | ||
140 | * using GFP_DMA. The default here places no restriction on DMA | ||
141 | * allocations. This must be the smallest DMA mask in the system, | ||
142 | * so a successful GFP_DMA allocation will always satisfy this. | ||
143 | */ | ||
144 | #ifndef ISA_DMA_THRESHOLD | ||
145 | #define ISA_DMA_THRESHOLD (0xffffffffULL) | ||
146 | #endif | ||
147 | |||
148 | #ifndef arch_adjust_zones | ||
149 | #define arch_adjust_zones(node,size,holes) do { } while (0) | ||
150 | #endif | ||
151 | |||
152 | /* | ||
153 | * PFNs are used to describe any physical page; this means | ||
154 | * PFN 0 == physical address 0. | ||
155 | * | ||
156 | * This is the PFN of the first RAM page in the kernel | ||
157 | * direct-mapped view. We assume this is the first page | ||
158 | * of RAM in the mem_map as well. | ||
159 | */ | ||
160 | #define PHYS_PFN_OFFSET (PHYS_OFFSET >> PAGE_SHIFT) | ||
161 | |||
162 | /* | ||
163 | * These are *only* valid on the kernel direct mapped RAM memory. | ||
164 | * Note: Drivers should NOT use these. They are the wrong | ||
165 | * translation for translating DMA addresses. Use the driver | ||
166 | * DMA support - see dma-mapping.h. | ||
167 | */ | ||
168 | static inline unsigned long virt_to_phys(void *x) | ||
169 | { | ||
170 | return __virt_to_phys((unsigned long)(x)); | ||
171 | } | ||
172 | |||
173 | static inline void *phys_to_virt(unsigned long x) | ||
174 | { | ||
175 | return (void *)(__phys_to_virt((unsigned long)(x))); | ||
176 | } | ||
177 | |||
178 | /* | ||
179 | * Drivers should NOT use these either. | ||
180 | */ | ||
181 | #define __pa(x) __virt_to_phys((unsigned long)(x)) | ||
182 | #define __va(x) ((void *)__phys_to_virt((unsigned long)(x))) | ||
183 | #define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) | ||
184 | |||
185 | /* | ||
186 | * Virtual <-> DMA view memory address translations | ||
187 | * Again, these are *only* valid on the kernel direct mapped RAM | ||
188 | * memory. Use of these is *deprecated* (and that doesn't mean | ||
189 | * use the __ prefixed forms instead.) See dma-mapping.h. | ||
190 | */ | ||
191 | static inline __deprecated unsigned long virt_to_bus(void *x) | ||
192 | { | ||
193 | return __virt_to_bus((unsigned long)x); | ||
194 | } | ||
195 | |||
196 | static inline __deprecated void *bus_to_virt(unsigned long x) | ||
197 | { | ||
198 | return (void *)__bus_to_virt(x); | ||
199 | } | ||
200 | |||
201 | /* | ||
202 | * Conversion between a struct page and a physical address. | ||
203 | * | ||
204 | * Note: when converting an unknown physical address to a | ||
205 | * struct page, the resulting pointer must be validated | ||
206 | * using VALID_PAGE(). It must return an invalid struct page | ||
207 | * for any physical address not corresponding to a system | ||
208 | * RAM address. | ||
209 | * | ||
210 | * page_to_pfn(page) convert a struct page * to a PFN number | ||
211 | * pfn_to_page(pfn) convert a _valid_ PFN number to struct page * | ||
212 | * pfn_valid(pfn) indicates whether a PFN number is valid | ||
213 | * | ||
214 | * virt_to_page(k) convert a _valid_ virtual address to struct page * | ||
215 | * virt_addr_valid(k) indicates whether a virtual address is valid | ||
216 | */ | ||
217 | #ifndef CONFIG_DISCONTIGMEM | ||
218 | |||
219 | #define ARCH_PFN_OFFSET PHYS_PFN_OFFSET | ||
220 | |||
221 | #ifndef CONFIG_SPARSEMEM | ||
222 | #define pfn_valid(pfn) ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr)) | ||
223 | #endif | ||
224 | |||
225 | #define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) | ||
226 | #define virt_addr_valid(kaddr) ((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory) | ||
227 | |||
228 | #define PHYS_TO_NID(addr) (0) | ||
229 | |||
230 | #else /* CONFIG_DISCONTIGMEM */ | ||
231 | |||
232 | /* | ||
233 | * This is more complex. We have a set of mem_map arrays spread | ||
234 | * around in memory. | ||
235 | */ | ||
236 | #include <linux/numa.h> | ||
237 | |||
238 | #define arch_pfn_to_nid(pfn) PFN_TO_NID(pfn) | ||
239 | #define arch_local_page_offset(pfn, nid) LOCAL_MAP_NR((pfn) << PAGE_SHIFT) | ||
240 | |||
241 | #define pfn_valid(pfn) \ | ||
242 | ({ \ | ||
243 | unsigned int nid = PFN_TO_NID(pfn); \ | ||
244 | int valid = nid < MAX_NUMNODES; \ | ||
245 | if (valid) { \ | ||
246 | pg_data_t *node = NODE_DATA(nid); \ | ||
247 | valid = (pfn - node->node_start_pfn) < \ | ||
248 | node->node_spanned_pages; \ | ||
249 | } \ | ||
250 | valid; \ | ||
251 | }) | ||
252 | |||
253 | #define virt_to_page(kaddr) \ | ||
254 | (ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr)) | ||
255 | |||
256 | #define virt_addr_valid(kaddr) (KVADDR_TO_NID(kaddr) < MAX_NUMNODES) | ||
257 | |||
258 | /* | ||
259 | * Common discontigmem stuff. | ||
260 | * PHYS_TO_NID is used by the ARM kernel/setup.c | ||
261 | */ | ||
262 | #define PHYS_TO_NID(addr) PFN_TO_NID((addr) >> PAGE_SHIFT) | ||
263 | |||
264 | /* | ||
265 | * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory | ||
266 | * and returns the mem_map of that node. | ||
267 | */ | ||
268 | #define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr)) | ||
269 | |||
270 | /* | ||
271 | * Given a page frame number, find the owning node of the memory | ||
272 | * and returns the mem_map of that node. | ||
273 | */ | ||
274 | #define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn)) | ||
275 | |||
276 | #ifdef NODE_MEM_SIZE_BITS | ||
277 | #define NODE_MEM_SIZE_MASK ((1 << NODE_MEM_SIZE_BITS) - 1) | ||
278 | |||
279 | /* | ||
280 | * Given a kernel address, find the home node of the underlying memory. | ||
281 | */ | ||
282 | #define KVADDR_TO_NID(addr) \ | ||
283 | (((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MEM_SIZE_BITS) | ||
284 | |||
285 | /* | ||
286 | * Given a page frame number, convert it to a node id. | ||
287 | */ | ||
288 | #define PFN_TO_NID(pfn) \ | ||
289 | (((pfn) - PHYS_PFN_OFFSET) >> (NODE_MEM_SIZE_BITS - PAGE_SHIFT)) | ||
290 | |||
291 | /* | ||
292 | * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory | ||
293 | * and returns the index corresponding to the appropriate page in the | ||
294 | * node's mem_map. | ||
295 | */ | ||
296 | #define LOCAL_MAP_NR(addr) \ | ||
297 | (((unsigned long)(addr) & NODE_MEM_SIZE_MASK) >> PAGE_SHIFT) | ||
298 | |||
299 | #endif /* NODE_MEM_SIZE_BITS */ | ||
300 | |||
301 | #endif /* !CONFIG_DISCONTIGMEM */ | ||
302 | |||
303 | /* | ||
304 | * For BIO. "will die". Kill me when bio_to_phys() and bvec_to_phys() die. | ||
305 | */ | ||
306 | #define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT) | ||
307 | |||
308 | /* | ||
309 | * Optional device DMA address remapping. Do _not_ use directly! | ||
310 | * We should really eliminate virt_to_bus() here - it's deprecated. | ||
311 | */ | ||
312 | #ifndef __arch_page_to_dma | ||
313 | #define page_to_dma(dev, page) ((dma_addr_t)__virt_to_bus((unsigned long)page_address(page))) | ||
314 | #define dma_to_virt(dev, addr) ((void *)__bus_to_virt(addr)) | ||
315 | #define virt_to_dma(dev, addr) ((dma_addr_t)__virt_to_bus((unsigned long)(addr))) | ||
316 | #else | ||
317 | #define page_to_dma(dev, page) (__arch_page_to_dma(dev, page)) | ||
318 | #define dma_to_virt(dev, addr) (__arch_dma_to_virt(dev, addr)) | ||
319 | #define virt_to_dma(dev, addr) (__arch_virt_to_dma(dev, addr)) | ||
320 | #endif | ||
321 | |||
322 | /* | ||
323 | * Optional coherency support. Currently used only by selected | ||
324 | * Intel XSC3-based systems. | ||
325 | */ | ||
326 | #ifndef arch_is_coherent | ||
327 | #define arch_is_coherent() 0 | ||
328 | #endif | ||
329 | |||
330 | #endif | ||
331 | |||
332 | #include <asm-generic/memory_model.h> | ||
333 | |||
334 | #endif | ||
diff --git a/arch/arm/include/asm/mman.h b/arch/arm/include/asm/mman.h new file mode 100644 index 000000000000..54570d2e95b7 --- /dev/null +++ b/arch/arm/include/asm/mman.h | |||
@@ -0,0 +1,17 @@ | |||
1 | #ifndef __ARM_MMAN_H__ | ||
2 | #define __ARM_MMAN_H__ | ||
3 | |||
4 | #include <asm-generic/mman.h> | ||
5 | |||
6 | #define MAP_GROWSDOWN 0x0100 /* stack-like segment */ | ||
7 | #define MAP_DENYWRITE 0x0800 /* ETXTBSY */ | ||
8 | #define MAP_EXECUTABLE 0x1000 /* mark it as an executable */ | ||
9 | #define MAP_LOCKED 0x2000 /* pages are locked */ | ||
10 | #define MAP_NORESERVE 0x4000 /* don't check for reservations */ | ||
11 | #define MAP_POPULATE 0x8000 /* populate (prefault) page tables */ | ||
12 | #define MAP_NONBLOCK 0x10000 /* do not block on IO */ | ||
13 | |||
14 | #define MCL_CURRENT 1 /* lock all current mappings */ | ||
15 | #define MCL_FUTURE 2 /* lock all future mappings */ | ||
16 | |||
17 | #endif /* __ARM_MMAN_H__ */ | ||
diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h new file mode 100644 index 000000000000..53099d4ee421 --- /dev/null +++ b/arch/arm/include/asm/mmu.h | |||
@@ -0,0 +1,33 @@ | |||
1 | #ifndef __ARM_MMU_H | ||
2 | #define __ARM_MMU_H | ||
3 | |||
4 | #ifdef CONFIG_MMU | ||
5 | |||
6 | typedef struct { | ||
7 | #ifdef CONFIG_CPU_HAS_ASID | ||
8 | unsigned int id; | ||
9 | #endif | ||
10 | unsigned int kvm_seq; | ||
11 | } mm_context_t; | ||
12 | |||
13 | #ifdef CONFIG_CPU_HAS_ASID | ||
14 | #define ASID(mm) ((mm)->context.id & 255) | ||
15 | #else | ||
16 | #define ASID(mm) (0) | ||
17 | #endif | ||
18 | |||
19 | #else | ||
20 | |||
21 | /* | ||
22 | * From nommu.h: | ||
23 | * Copyright (C) 2002, David McCullough <davidm@snapgear.com> | ||
24 | * modified for 2.6 by Hyok S. Choi <hyok.choi@samsung.com> | ||
25 | */ | ||
26 | typedef struct { | ||
27 | struct vm_list_struct *vmlist; | ||
28 | unsigned long end_brk; | ||
29 | } mm_context_t; | ||
30 | |||
31 | #endif | ||
32 | |||
33 | #endif | ||
diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h new file mode 100644 index 000000000000..a301e446007f --- /dev/null +++ b/arch/arm/include/asm/mmu_context.h | |||
@@ -0,0 +1,117 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/mmu_context.h | ||
3 | * | ||
4 | * Copyright (C) 1996 Russell King. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * Changelog: | ||
11 | * 27-06-1996 RMK Created | ||
12 | */ | ||
13 | #ifndef __ASM_ARM_MMU_CONTEXT_H | ||
14 | #define __ASM_ARM_MMU_CONTEXT_H | ||
15 | |||
16 | #include <linux/compiler.h> | ||
17 | #include <asm/cacheflush.h> | ||
18 | #include <asm/proc-fns.h> | ||
19 | #include <asm-generic/mm_hooks.h> | ||
20 | |||
21 | void __check_kvm_seq(struct mm_struct *mm); | ||
22 | |||
23 | #ifdef CONFIG_CPU_HAS_ASID | ||
24 | |||
25 | /* | ||
26 | * On ARMv6, we have the following structure in the Context ID: | ||
27 | * | ||
28 | * 31 7 0 | ||
29 | * +-------------------------+-----------+ | ||
30 | * | process ID | ASID | | ||
31 | * +-------------------------+-----------+ | ||
32 | * | context ID | | ||
33 | * +-------------------------------------+ | ||
34 | * | ||
35 | * The ASID is used to tag entries in the CPU caches and TLBs. | ||
36 | * The context ID is used by debuggers and trace logic, and | ||
37 | * should be unique within all running processes. | ||
38 | */ | ||
39 | #define ASID_BITS 8 | ||
40 | #define ASID_MASK ((~0) << ASID_BITS) | ||
41 | #define ASID_FIRST_VERSION (1 << ASID_BITS) | ||
42 | |||
43 | extern unsigned int cpu_last_asid; | ||
44 | |||
45 | void __init_new_context(struct task_struct *tsk, struct mm_struct *mm); | ||
46 | void __new_context(struct mm_struct *mm); | ||
47 | |||
48 | static inline void check_context(struct mm_struct *mm) | ||
49 | { | ||
50 | if (unlikely((mm->context.id ^ cpu_last_asid) >> ASID_BITS)) | ||
51 | __new_context(mm); | ||
52 | |||
53 | if (unlikely(mm->context.kvm_seq != init_mm.context.kvm_seq)) | ||
54 | __check_kvm_seq(mm); | ||
55 | } | ||
56 | |||
57 | #define init_new_context(tsk,mm) (__init_new_context(tsk,mm),0) | ||
58 | |||
59 | #else | ||
60 | |||
61 | static inline void check_context(struct mm_struct *mm) | ||
62 | { | ||
63 | if (unlikely(mm->context.kvm_seq != init_mm.context.kvm_seq)) | ||
64 | __check_kvm_seq(mm); | ||
65 | } | ||
66 | |||
67 | #define init_new_context(tsk,mm) 0 | ||
68 | |||
69 | #endif | ||
70 | |||
71 | #define destroy_context(mm) do { } while(0) | ||
72 | |||
73 | /* | ||
74 | * This is called when "tsk" is about to enter lazy TLB mode. | ||
75 | * | ||
76 | * mm: describes the currently active mm context | ||
77 | * tsk: task which is entering lazy tlb | ||
78 | * cpu: cpu number which is entering lazy tlb | ||
79 | * | ||
80 | * tsk->mm will be NULL | ||
81 | */ | ||
82 | static inline void | ||
83 | enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) | ||
84 | { | ||
85 | } | ||
86 | |||
87 | /* | ||
88 | * This is the actual mm switch as far as the scheduler | ||
89 | * is concerned. No registers are touched. We avoid | ||
90 | * calling the CPU specific function when the mm hasn't | ||
91 | * actually changed. | ||
92 | */ | ||
93 | static inline void | ||
94 | switch_mm(struct mm_struct *prev, struct mm_struct *next, | ||
95 | struct task_struct *tsk) | ||
96 | { | ||
97 | #ifdef CONFIG_MMU | ||
98 | unsigned int cpu = smp_processor_id(); | ||
99 | |||
100 | #ifdef CONFIG_SMP | ||
101 | /* check for possible thread migration */ | ||
102 | if (!cpus_empty(next->cpu_vm_mask) && !cpu_isset(cpu, next->cpu_vm_mask)) | ||
103 | __flush_icache_all(); | ||
104 | #endif | ||
105 | if (!cpu_test_and_set(cpu, next->cpu_vm_mask) || prev != next) { | ||
106 | check_context(next); | ||
107 | cpu_switch_mm(next->pgd, next); | ||
108 | if (cache_is_vivt()) | ||
109 | cpu_clear(cpu, prev->cpu_vm_mask); | ||
110 | } | ||
111 | #endif | ||
112 | } | ||
113 | |||
114 | #define deactivate_mm(tsk,mm) do { } while (0) | ||
115 | #define activate_mm(prev,next) switch_mm(prev, next, NULL) | ||
116 | |||
117 | #endif | ||
diff --git a/arch/arm/include/asm/mmzone.h b/arch/arm/include/asm/mmzone.h new file mode 100644 index 000000000000..f2fbb5084901 --- /dev/null +++ b/arch/arm/include/asm/mmzone.h | |||
@@ -0,0 +1,30 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/mmzone.h | ||
3 | * | ||
4 | * 1999-12-29 Nicolas Pitre Created | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #ifndef __ASM_MMZONE_H | ||
11 | #define __ASM_MMZONE_H | ||
12 | |||
13 | /* | ||
14 | * Currently defined in arch/arm/mm/discontig.c | ||
15 | */ | ||
16 | extern pg_data_t discontig_node_data[]; | ||
17 | |||
18 | /* | ||
19 | * Return a pointer to the node data for node n. | ||
20 | */ | ||
21 | #define NODE_DATA(nid) (&discontig_node_data[nid]) | ||
22 | |||
23 | /* | ||
24 | * NODE_MEM_MAP gives the kaddr for the mem_map of the node. | ||
25 | */ | ||
26 | #define NODE_MEM_MAP(nid) (NODE_DATA(nid)->node_mem_map) | ||
27 | |||
28 | #include <asm/arch/memory.h> | ||
29 | |||
30 | #endif | ||
diff --git a/arch/arm/include/asm/module.h b/arch/arm/include/asm/module.h new file mode 100644 index 000000000000..24b168dc31a3 --- /dev/null +++ b/arch/arm/include/asm/module.h | |||
@@ -0,0 +1,18 @@ | |||
1 | #ifndef _ASM_ARM_MODULE_H | ||
2 | #define _ASM_ARM_MODULE_H | ||
3 | |||
4 | struct mod_arch_specific | ||
5 | { | ||
6 | int foo; | ||
7 | }; | ||
8 | |||
9 | #define Elf_Shdr Elf32_Shdr | ||
10 | #define Elf_Sym Elf32_Sym | ||
11 | #define Elf_Ehdr Elf32_Ehdr | ||
12 | |||
13 | /* | ||
14 | * Include the ARM architecture version. | ||
15 | */ | ||
16 | #define MODULE_ARCH_VERMAGIC "ARMv" __stringify(__LINUX_ARM_ARCH__) " " | ||
17 | |||
18 | #endif /* _ASM_ARM_MODULE_H */ | ||
diff --git a/arch/arm/include/asm/msgbuf.h b/arch/arm/include/asm/msgbuf.h new file mode 100644 index 000000000000..33b35b946eaa --- /dev/null +++ b/arch/arm/include/asm/msgbuf.h | |||
@@ -0,0 +1,31 @@ | |||
1 | #ifndef _ASMARM_MSGBUF_H | ||
2 | #define _ASMARM_MSGBUF_H | ||
3 | |||
4 | /* | ||
5 | * The msqid64_ds structure for arm architecture. | ||
6 | * Note extra padding because this structure is passed back and forth | ||
7 | * between kernel and user space. | ||
8 | * | ||
9 | * Pad space is left for: | ||
10 | * - 64-bit time_t to solve y2038 problem | ||
11 | * - 2 miscellaneous 32-bit values | ||
12 | */ | ||
13 | |||
14 | struct msqid64_ds { | ||
15 | struct ipc64_perm msg_perm; | ||
16 | __kernel_time_t msg_stime; /* last msgsnd time */ | ||
17 | unsigned long __unused1; | ||
18 | __kernel_time_t msg_rtime; /* last msgrcv time */ | ||
19 | unsigned long __unused2; | ||
20 | __kernel_time_t msg_ctime; /* last change time */ | ||
21 | unsigned long __unused3; | ||
22 | unsigned long msg_cbytes; /* current number of bytes on queue */ | ||
23 | unsigned long msg_qnum; /* number of messages in queue */ | ||
24 | unsigned long msg_qbytes; /* max number of bytes on queue */ | ||
25 | __kernel_pid_t msg_lspid; /* pid of last msgsnd */ | ||
26 | __kernel_pid_t msg_lrpid; /* last receive pid */ | ||
27 | unsigned long __unused4; | ||
28 | unsigned long __unused5; | ||
29 | }; | ||
30 | |||
31 | #endif /* _ASMARM_MSGBUF_H */ | ||
diff --git a/arch/arm/include/asm/mtd-xip.h b/arch/arm/include/asm/mtd-xip.h new file mode 100644 index 000000000000..9eb127cc7db2 --- /dev/null +++ b/arch/arm/include/asm/mtd-xip.h | |||
@@ -0,0 +1,26 @@ | |||
1 | /* | ||
2 | * MTD primitives for XIP support. Architecture specific functions | ||
3 | * | ||
4 | * Do not include this file directly. It's included from linux/mtd/xip.h | ||
5 | * | ||
6 | * Author: Nicolas Pitre | ||
7 | * Created: Nov 2, 2004 | ||
8 | * Copyright: (C) 2004 MontaVista Software, Inc. | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | * | ||
14 | * $Id: xip.h,v 1.2 2004/12/01 15:49:10 nico Exp $ | ||
15 | */ | ||
16 | |||
17 | #ifndef __ARM_MTD_XIP_H__ | ||
18 | #define __ARM_MTD_XIP_H__ | ||
19 | |||
20 | #include <asm/hardware.h> | ||
21 | #include <asm/arch/mtd-xip.h> | ||
22 | |||
23 | /* fill instruction prefetch */ | ||
24 | #define xip_iprefetch() do { asm volatile (".rep 8; nop; .endr"); } while (0) | ||
25 | |||
26 | #endif /* __ARM_MTD_XIP_H__ */ | ||
diff --git a/arch/arm/include/asm/mutex.h b/arch/arm/include/asm/mutex.h new file mode 100644 index 000000000000..93226cf23ae0 --- /dev/null +++ b/arch/arm/include/asm/mutex.h | |||
@@ -0,0 +1,127 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/mutex.h | ||
3 | * | ||
4 | * ARM optimized mutex locking primitives | ||
5 | * | ||
6 | * Please look into asm-generic/mutex-xchg.h for a formal definition. | ||
7 | */ | ||
8 | #ifndef _ASM_MUTEX_H | ||
9 | #define _ASM_MUTEX_H | ||
10 | |||
11 | #if __LINUX_ARM_ARCH__ < 6 | ||
12 | /* On pre-ARMv6 hardware the swp based implementation is the most efficient. */ | ||
13 | # include <asm-generic/mutex-xchg.h> | ||
14 | #else | ||
15 | |||
16 | /* | ||
17 | * Attempting to lock a mutex on ARMv6+ can be done with a bastardized | ||
18 | * atomic decrement (it is not a reliable atomic decrement but it satisfies | ||
19 | * the defined semantics for our purpose, while being smaller and faster | ||
20 | * than a real atomic decrement or atomic swap. The idea is to attempt | ||
21 | * decrementing the lock value only once. If once decremented it isn't zero, | ||
22 | * or if its store-back fails due to a dispute on the exclusive store, we | ||
23 | * simply bail out immediately through the slow path where the lock will be | ||
24 | * reattempted until it succeeds. | ||
25 | */ | ||
26 | static inline void | ||
27 | __mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *)) | ||
28 | { | ||
29 | int __ex_flag, __res; | ||
30 | |||
31 | __asm__ ( | ||
32 | |||
33 | "ldrex %0, [%2] \n\t" | ||
34 | "sub %0, %0, #1 \n\t" | ||
35 | "strex %1, %0, [%2] " | ||
36 | |||
37 | : "=&r" (__res), "=&r" (__ex_flag) | ||
38 | : "r" (&(count)->counter) | ||
39 | : "cc","memory" ); | ||
40 | |||
41 | __res |= __ex_flag; | ||
42 | if (unlikely(__res != 0)) | ||
43 | fail_fn(count); | ||
44 | } | ||
45 | |||
46 | static inline int | ||
47 | __mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *)) | ||
48 | { | ||
49 | int __ex_flag, __res; | ||
50 | |||
51 | __asm__ ( | ||
52 | |||
53 | "ldrex %0, [%2] \n\t" | ||
54 | "sub %0, %0, #1 \n\t" | ||
55 | "strex %1, %0, [%2] " | ||
56 | |||
57 | : "=&r" (__res), "=&r" (__ex_flag) | ||
58 | : "r" (&(count)->counter) | ||
59 | : "cc","memory" ); | ||
60 | |||
61 | __res |= __ex_flag; | ||
62 | if (unlikely(__res != 0)) | ||
63 | __res = fail_fn(count); | ||
64 | return __res; | ||
65 | } | ||
66 | |||
67 | /* | ||
68 | * Same trick is used for the unlock fast path. However the original value, | ||
69 | * rather than the result, is used to test for success in order to have | ||
70 | * better generated assembly. | ||
71 | */ | ||
72 | static inline void | ||
73 | __mutex_fastpath_unlock(atomic_t *count, void (*fail_fn)(atomic_t *)) | ||
74 | { | ||
75 | int __ex_flag, __res, __orig; | ||
76 | |||
77 | __asm__ ( | ||
78 | |||
79 | "ldrex %0, [%3] \n\t" | ||
80 | "add %1, %0, #1 \n\t" | ||
81 | "strex %2, %1, [%3] " | ||
82 | |||
83 | : "=&r" (__orig), "=&r" (__res), "=&r" (__ex_flag) | ||
84 | : "r" (&(count)->counter) | ||
85 | : "cc","memory" ); | ||
86 | |||
87 | __orig |= __ex_flag; | ||
88 | if (unlikely(__orig != 0)) | ||
89 | fail_fn(count); | ||
90 | } | ||
91 | |||
92 | /* | ||
93 | * If the unlock was done on a contended lock, or if the unlock simply fails | ||
94 | * then the mutex remains locked. | ||
95 | */ | ||
96 | #define __mutex_slowpath_needs_to_unlock() 1 | ||
97 | |||
98 | /* | ||
99 | * For __mutex_fastpath_trylock we use another construct which could be | ||
100 | * described as a "single value cmpxchg". | ||
101 | * | ||
102 | * This provides the needed trylock semantics like cmpxchg would, but it is | ||
103 | * lighter and less generic than a true cmpxchg implementation. | ||
104 | */ | ||
105 | static inline int | ||
106 | __mutex_fastpath_trylock(atomic_t *count, int (*fail_fn)(atomic_t *)) | ||
107 | { | ||
108 | int __ex_flag, __res, __orig; | ||
109 | |||
110 | __asm__ ( | ||
111 | |||
112 | "1: ldrex %0, [%3] \n\t" | ||
113 | "subs %1, %0, #1 \n\t" | ||
114 | "strexeq %2, %1, [%3] \n\t" | ||
115 | "movlt %0, #0 \n\t" | ||
116 | "cmpeq %2, #0 \n\t" | ||
117 | "bgt 1b " | ||
118 | |||
119 | : "=&r" (__orig), "=&r" (__res), "=&r" (__ex_flag) | ||
120 | : "r" (&count->counter) | ||
121 | : "cc", "memory" ); | ||
122 | |||
123 | return __orig; | ||
124 | } | ||
125 | |||
126 | #endif | ||
127 | #endif | ||
diff --git a/arch/arm/include/asm/nwflash.h b/arch/arm/include/asm/nwflash.h new file mode 100644 index 000000000000..04e5a557a884 --- /dev/null +++ b/arch/arm/include/asm/nwflash.h | |||
@@ -0,0 +1,9 @@ | |||
1 | #ifndef _FLASH_H | ||
2 | #define _FLASH_H | ||
3 | |||
4 | #define FLASH_MINOR 160 /* MAJOR is 10 - miscdevice */ | ||
5 | #define CMD_WRITE_DISABLE 0 | ||
6 | #define CMD_WRITE_ENABLE 0x28 | ||
7 | #define CMD_WRITE_BASE64K_ENABLE 0x47 | ||
8 | |||
9 | #endif /* _FLASH_H */ | ||
diff --git a/arch/arm/include/asm/page-nommu.h b/arch/arm/include/asm/page-nommu.h new file mode 100644 index 000000000000..3574c0deb37f --- /dev/null +++ b/arch/arm/include/asm/page-nommu.h | |||
@@ -0,0 +1,49 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/page-nommu.h | ||
3 | * | ||
4 | * Copyright (C) 2004 Hyok S. Choi | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #ifndef _ASMARM_PAGE_NOMMU_H | ||
12 | #define _ASMARM_PAGE_NOMMU_H | ||
13 | |||
14 | #if !defined(CONFIG_SMALL_TASKS) && PAGE_SHIFT < 13 | ||
15 | #define KTHREAD_SIZE (8192) | ||
16 | #else | ||
17 | #define KTHREAD_SIZE PAGE_SIZE | ||
18 | #endif | ||
19 | |||
20 | #define get_user_page(vaddr) __get_free_page(GFP_KERNEL) | ||
21 | #define free_user_page(page, addr) free_page(addr) | ||
22 | |||
23 | #define clear_page(page) memset((page), 0, PAGE_SIZE) | ||
24 | #define copy_page(to,from) memcpy((to), (from), PAGE_SIZE) | ||
25 | |||
26 | #define clear_user_page(page, vaddr, pg) clear_page(page) | ||
27 | #define copy_user_page(to, from, vaddr, pg) copy_page(to, from) | ||
28 | |||
29 | /* | ||
30 | * These are used to make use of C type-checking.. | ||
31 | */ | ||
32 | typedef unsigned long pte_t; | ||
33 | typedef unsigned long pmd_t; | ||
34 | typedef unsigned long pgd_t[2]; | ||
35 | typedef unsigned long pgprot_t; | ||
36 | |||
37 | #define pte_val(x) (x) | ||
38 | #define pmd_val(x) (x) | ||
39 | #define pgd_val(x) ((x)[0]) | ||
40 | #define pgprot_val(x) (x) | ||
41 | |||
42 | #define __pte(x) (x) | ||
43 | #define __pmd(x) (x) | ||
44 | #define __pgprot(x) (x) | ||
45 | |||
46 | extern unsigned long memory_start; | ||
47 | extern unsigned long memory_end; | ||
48 | |||
49 | #endif | ||
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h new file mode 100644 index 000000000000..cf2e2680daaa --- /dev/null +++ b/arch/arm/include/asm/page.h | |||
@@ -0,0 +1,199 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/page.h | ||
3 | * | ||
4 | * Copyright (C) 1995-2003 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #ifndef _ASMARM_PAGE_H | ||
11 | #define _ASMARM_PAGE_H | ||
12 | |||
13 | /* PAGE_SHIFT determines the page size */ | ||
14 | #define PAGE_SHIFT 12 | ||
15 | #define PAGE_SIZE (1UL << PAGE_SHIFT) | ||
16 | #define PAGE_MASK (~(PAGE_SIZE-1)) | ||
17 | |||
18 | #ifndef __ASSEMBLY__ | ||
19 | |||
20 | #ifndef CONFIG_MMU | ||
21 | |||
22 | #include "page-nommu.h" | ||
23 | |||
24 | #else | ||
25 | |||
26 | #include <asm/glue.h> | ||
27 | |||
28 | /* | ||
29 | * User Space Model | ||
30 | * ================ | ||
31 | * | ||
32 | * This section selects the correct set of functions for dealing with | ||
33 | * page-based copying and clearing for user space for the particular | ||
34 | * processor(s) we're building for. | ||
35 | * | ||
36 | * We have the following to choose from: | ||
37 | * v3 - ARMv3 | ||
38 | * v4wt - ARMv4 with writethrough cache, without minicache | ||
39 | * v4wb - ARMv4 with writeback cache, without minicache | ||
40 | * v4_mc - ARMv4 with minicache | ||
41 | * xscale - Xscale | ||
42 | * xsc3 - XScalev3 | ||
43 | */ | ||
44 | #undef _USER | ||
45 | #undef MULTI_USER | ||
46 | |||
47 | #ifdef CONFIG_CPU_COPY_V3 | ||
48 | # ifdef _USER | ||
49 | # define MULTI_USER 1 | ||
50 | # else | ||
51 | # define _USER v3 | ||
52 | # endif | ||
53 | #endif | ||
54 | |||
55 | #ifdef CONFIG_CPU_COPY_V4WT | ||
56 | # ifdef _USER | ||
57 | # define MULTI_USER 1 | ||
58 | # else | ||
59 | # define _USER v4wt | ||
60 | # endif | ||
61 | #endif | ||
62 | |||
63 | #ifdef CONFIG_CPU_COPY_V4WB | ||
64 | # ifdef _USER | ||
65 | # define MULTI_USER 1 | ||
66 | # else | ||
67 | # define _USER v4wb | ||
68 | # endif | ||
69 | #endif | ||
70 | |||
71 | #ifdef CONFIG_CPU_COPY_FEROCEON | ||
72 | # ifdef _USER | ||
73 | # define MULTI_USER 1 | ||
74 | # else | ||
75 | # define _USER feroceon | ||
76 | # endif | ||
77 | #endif | ||
78 | |||
79 | #ifdef CONFIG_CPU_SA1100 | ||
80 | # ifdef _USER | ||
81 | # define MULTI_USER 1 | ||
82 | # else | ||
83 | # define _USER v4_mc | ||
84 | # endif | ||
85 | #endif | ||
86 | |||
87 | #ifdef CONFIG_CPU_XSCALE | ||
88 | # ifdef _USER | ||
89 | # define MULTI_USER 1 | ||
90 | # else | ||
91 | # define _USER xscale_mc | ||
92 | # endif | ||
93 | #endif | ||
94 | |||
95 | #ifdef CONFIG_CPU_XSC3 | ||
96 | # ifdef _USER | ||
97 | # define MULTI_USER 1 | ||
98 | # else | ||
99 | # define _USER xsc3_mc | ||
100 | # endif | ||
101 | #endif | ||
102 | |||
103 | #ifdef CONFIG_CPU_COPY_V6 | ||
104 | # define MULTI_USER 1 | ||
105 | #endif | ||
106 | |||
107 | #if !defined(_USER) && !defined(MULTI_USER) | ||
108 | #error Unknown user operations model | ||
109 | #endif | ||
110 | |||
111 | struct cpu_user_fns { | ||
112 | void (*cpu_clear_user_page)(void *p, unsigned long user); | ||
113 | void (*cpu_copy_user_page)(void *to, const void *from, | ||
114 | unsigned long user); | ||
115 | }; | ||
116 | |||
117 | #ifdef MULTI_USER | ||
118 | extern struct cpu_user_fns cpu_user; | ||
119 | |||
120 | #define __cpu_clear_user_page cpu_user.cpu_clear_user_page | ||
121 | #define __cpu_copy_user_page cpu_user.cpu_copy_user_page | ||
122 | |||
123 | #else | ||
124 | |||
125 | #define __cpu_clear_user_page __glue(_USER,_clear_user_page) | ||
126 | #define __cpu_copy_user_page __glue(_USER,_copy_user_page) | ||
127 | |||
128 | extern void __cpu_clear_user_page(void *p, unsigned long user); | ||
129 | extern void __cpu_copy_user_page(void *to, const void *from, | ||
130 | unsigned long user); | ||
131 | #endif | ||
132 | |||
133 | #define clear_user_page(addr,vaddr,pg) __cpu_clear_user_page(addr, vaddr) | ||
134 | #define copy_user_page(to,from,vaddr,pg) __cpu_copy_user_page(to, from, vaddr) | ||
135 | |||
136 | #define clear_page(page) memzero((void *)(page), PAGE_SIZE) | ||
137 | extern void copy_page(void *to, const void *from); | ||
138 | |||
139 | #undef STRICT_MM_TYPECHECKS | ||
140 | |||
141 | #ifdef STRICT_MM_TYPECHECKS | ||
142 | /* | ||
143 | * These are used to make use of C type-checking.. | ||
144 | */ | ||
145 | typedef struct { unsigned long pte; } pte_t; | ||
146 | typedef struct { unsigned long pmd; } pmd_t; | ||
147 | typedef struct { unsigned long pgd[2]; } pgd_t; | ||
148 | typedef struct { unsigned long pgprot; } pgprot_t; | ||
149 | |||
150 | #define pte_val(x) ((x).pte) | ||
151 | #define pmd_val(x) ((x).pmd) | ||
152 | #define pgd_val(x) ((x).pgd[0]) | ||
153 | #define pgprot_val(x) ((x).pgprot) | ||
154 | |||
155 | #define __pte(x) ((pte_t) { (x) } ) | ||
156 | #define __pmd(x) ((pmd_t) { (x) } ) | ||
157 | #define __pgprot(x) ((pgprot_t) { (x) } ) | ||
158 | |||
159 | #else | ||
160 | /* | ||
161 | * .. while these make it easier on the compiler | ||
162 | */ | ||
163 | typedef unsigned long pte_t; | ||
164 | typedef unsigned long pmd_t; | ||
165 | typedef unsigned long pgd_t[2]; | ||
166 | typedef unsigned long pgprot_t; | ||
167 | |||
168 | #define pte_val(x) (x) | ||
169 | #define pmd_val(x) (x) | ||
170 | #define pgd_val(x) ((x)[0]) | ||
171 | #define pgprot_val(x) (x) | ||
172 | |||
173 | #define __pte(x) (x) | ||
174 | #define __pmd(x) (x) | ||
175 | #define __pgprot(x) (x) | ||
176 | |||
177 | #endif /* STRICT_MM_TYPECHECKS */ | ||
178 | |||
179 | #endif /* CONFIG_MMU */ | ||
180 | |||
181 | typedef struct page *pgtable_t; | ||
182 | |||
183 | #include <asm/memory.h> | ||
184 | |||
185 | #endif /* !__ASSEMBLY__ */ | ||
186 | |||
187 | #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ | ||
188 | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) | ||
189 | |||
190 | /* | ||
191 | * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers. | ||
192 | */ | ||
193 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) | ||
194 | #define ARCH_SLAB_MINALIGN 8 | ||
195 | #endif | ||
196 | |||
197 | #include <asm-generic/page.h> | ||
198 | |||
199 | #endif | ||
diff --git a/arch/arm/include/asm/param.h b/arch/arm/include/asm/param.h new file mode 100644 index 000000000000..8b24bf94c06b --- /dev/null +++ b/arch/arm/include/asm/param.h | |||
@@ -0,0 +1,31 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/param.h | ||
3 | * | ||
4 | * Copyright (C) 1995-1999 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #ifndef __ASM_PARAM_H | ||
11 | #define __ASM_PARAM_H | ||
12 | |||
13 | #ifdef __KERNEL__ | ||
14 | # define HZ CONFIG_HZ /* Internal kernel timer frequency */ | ||
15 | # define USER_HZ 100 /* User interfaces are in "ticks" */ | ||
16 | # define CLOCKS_PER_SEC (USER_HZ) /* like times() */ | ||
17 | #else | ||
18 | # define HZ 100 | ||
19 | #endif | ||
20 | |||
21 | #define EXEC_PAGESIZE 4096 | ||
22 | |||
23 | #ifndef NOGROUP | ||
24 | #define NOGROUP (-1) | ||
25 | #endif | ||
26 | |||
27 | /* max length of hostname */ | ||
28 | #define MAXHOSTNAMELEN 64 | ||
29 | |||
30 | #endif | ||
31 | |||
diff --git a/arch/arm/include/asm/parport.h b/arch/arm/include/asm/parport.h new file mode 100644 index 000000000000..26e94b09035a --- /dev/null +++ b/arch/arm/include/asm/parport.h | |||
@@ -0,0 +1,18 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/parport.h: ARM-specific parport initialisation | ||
3 | * | ||
4 | * Copyright (C) 1999, 2000 Tim Waugh <tim@cyberelk.demon.co.uk> | ||
5 | * | ||
6 | * This file should only be included by drivers/parport/parport_pc.c. | ||
7 | */ | ||
8 | |||
9 | #ifndef __ASMARM_PARPORT_H | ||
10 | #define __ASMARM_PARPORT_H | ||
11 | |||
12 | static int __devinit parport_pc_find_isa_ports (int autoirq, int autodma); | ||
13 | static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma) | ||
14 | { | ||
15 | return parport_pc_find_isa_ports (autoirq, autodma); | ||
16 | } | ||
17 | |||
18 | #endif /* !(_ASMARM_PARPORT_H) */ | ||
diff --git a/arch/arm/include/asm/pci.h b/arch/arm/include/asm/pci.h new file mode 100644 index 000000000000..2d84792f2e12 --- /dev/null +++ b/arch/arm/include/asm/pci.h | |||
@@ -0,0 +1,91 @@ | |||
1 | #ifndef ASMARM_PCI_H | ||
2 | #define ASMARM_PCI_H | ||
3 | |||
4 | #ifdef __KERNEL__ | ||
5 | #include <asm-generic/pci-dma-compat.h> | ||
6 | |||
7 | #include <asm/hardware.h> /* for PCIBIOS_MIN_* */ | ||
8 | |||
9 | #define pcibios_scan_all_fns(a, b) 0 | ||
10 | |||
11 | #ifdef CONFIG_PCI_HOST_ITE8152 | ||
12 | /* ITE bridge requires setting latency timer to avoid early bus access | ||
13 | termination by PIC bus mater devices | ||
14 | */ | ||
15 | extern void pcibios_set_master(struct pci_dev *dev); | ||
16 | #else | ||
17 | static inline void pcibios_set_master(struct pci_dev *dev) | ||
18 | { | ||
19 | /* No special bus mastering setup handling */ | ||
20 | } | ||
21 | #endif | ||
22 | |||
23 | static inline void pcibios_penalize_isa_irq(int irq, int active) | ||
24 | { | ||
25 | /* We don't do dynamic PCI IRQ allocation */ | ||
26 | } | ||
27 | |||
28 | /* | ||
29 | * The PCI address space does equal the physical memory address space. | ||
30 | * The networking and block device layers use this boolean for bounce | ||
31 | * buffer decisions. | ||
32 | */ | ||
33 | #define PCI_DMA_BUS_IS_PHYS (0) | ||
34 | |||
35 | /* | ||
36 | * Whether pci_unmap_{single,page} is a nop depends upon the | ||
37 | * configuration. | ||
38 | */ | ||
39 | #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) dma_addr_t ADDR_NAME; | ||
40 | #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) __u32 LEN_NAME; | ||
41 | #define pci_unmap_addr(PTR, ADDR_NAME) ((PTR)->ADDR_NAME) | ||
42 | #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL)) | ||
43 | #define pci_unmap_len(PTR, LEN_NAME) ((PTR)->LEN_NAME) | ||
44 | #define pci_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL)) | ||
45 | |||
46 | #ifdef CONFIG_PCI | ||
47 | static inline void pci_dma_burst_advice(struct pci_dev *pdev, | ||
48 | enum pci_dma_burst_strategy *strat, | ||
49 | unsigned long *strategy_parameter) | ||
50 | { | ||
51 | *strat = PCI_DMA_BURST_INFINITY; | ||
52 | *strategy_parameter = ~0UL; | ||
53 | } | ||
54 | #endif | ||
55 | |||
56 | #define HAVE_PCI_MMAP | ||
57 | extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | ||
58 | enum pci_mmap_state mmap_state, int write_combine); | ||
59 | |||
60 | extern void | ||
61 | pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, | ||
62 | struct resource *res); | ||
63 | |||
64 | extern void | ||
65 | pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, | ||
66 | struct pci_bus_region *region); | ||
67 | |||
68 | static inline struct resource * | ||
69 | pcibios_select_root(struct pci_dev *pdev, struct resource *res) | ||
70 | { | ||
71 | struct resource *root = NULL; | ||
72 | |||
73 | if (res->flags & IORESOURCE_IO) | ||
74 | root = &ioport_resource; | ||
75 | if (res->flags & IORESOURCE_MEM) | ||
76 | root = &iomem_resource; | ||
77 | |||
78 | return root; | ||
79 | } | ||
80 | |||
81 | /* | ||
82 | * Dummy implementation; always return 0. | ||
83 | */ | ||
84 | static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) | ||
85 | { | ||
86 | return 0; | ||
87 | } | ||
88 | |||
89 | #endif /* __KERNEL__ */ | ||
90 | |||
91 | #endif | ||
diff --git a/arch/arm/include/asm/percpu.h b/arch/arm/include/asm/percpu.h new file mode 100644 index 000000000000..b4e32d8ec072 --- /dev/null +++ b/arch/arm/include/asm/percpu.h | |||
@@ -0,0 +1,6 @@ | |||
1 | #ifndef __ARM_PERCPU | ||
2 | #define __ARM_PERCPU | ||
3 | |||
4 | #include <asm-generic/percpu.h> | ||
5 | |||
6 | #endif | ||
diff --git a/arch/arm/include/asm/pgalloc.h b/arch/arm/include/asm/pgalloc.h new file mode 100644 index 000000000000..3dcd64bf1824 --- /dev/null +++ b/arch/arm/include/asm/pgalloc.h | |||
@@ -0,0 +1,136 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/pgalloc.h | ||
3 | * | ||
4 | * Copyright (C) 2000-2001 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #ifndef _ASMARM_PGALLOC_H | ||
11 | #define _ASMARM_PGALLOC_H | ||
12 | |||
13 | #include <asm/domain.h> | ||
14 | #include <asm/pgtable-hwdef.h> | ||
15 | #include <asm/processor.h> | ||
16 | #include <asm/cacheflush.h> | ||
17 | #include <asm/tlbflush.h> | ||
18 | |||
19 | #define check_pgt_cache() do { } while (0) | ||
20 | |||
21 | #ifdef CONFIG_MMU | ||
22 | |||
23 | #define _PAGE_USER_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_USER)) | ||
24 | #define _PAGE_KERNEL_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_KERNEL)) | ||
25 | |||
26 | /* | ||
27 | * Since we have only two-level page tables, these are trivial | ||
28 | */ | ||
29 | #define pmd_alloc_one(mm,addr) ({ BUG(); ((pmd_t *)2); }) | ||
30 | #define pmd_free(mm, pmd) do { } while (0) | ||
31 | #define pgd_populate(mm,pmd,pte) BUG() | ||
32 | |||
33 | extern pgd_t *get_pgd_slow(struct mm_struct *mm); | ||
34 | extern void free_pgd_slow(struct mm_struct *mm, pgd_t *pgd); | ||
35 | |||
36 | #define pgd_alloc(mm) get_pgd_slow(mm) | ||
37 | #define pgd_free(mm, pgd) free_pgd_slow(mm, pgd) | ||
38 | |||
39 | /* | ||
40 | * Allocate one PTE table. | ||
41 | * | ||
42 | * This actually allocates two hardware PTE tables, but we wrap this up | ||
43 | * into one table thus: | ||
44 | * | ||
45 | * +------------+ | ||
46 | * | h/w pt 0 | | ||
47 | * +------------+ | ||
48 | * | h/w pt 1 | | ||
49 | * +------------+ | ||
50 | * | Linux pt 0 | | ||
51 | * +------------+ | ||
52 | * | Linux pt 1 | | ||
53 | * +------------+ | ||
54 | */ | ||
55 | static inline pte_t * | ||
56 | pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr) | ||
57 | { | ||
58 | pte_t *pte; | ||
59 | |||
60 | pte = (pte_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO); | ||
61 | if (pte) { | ||
62 | clean_dcache_area(pte, sizeof(pte_t) * PTRS_PER_PTE); | ||
63 | pte += PTRS_PER_PTE; | ||
64 | } | ||
65 | |||
66 | return pte; | ||
67 | } | ||
68 | |||
69 | static inline pgtable_t | ||
70 | pte_alloc_one(struct mm_struct *mm, unsigned long addr) | ||
71 | { | ||
72 | struct page *pte; | ||
73 | |||
74 | pte = alloc_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, 0); | ||
75 | if (pte) { | ||
76 | void *page = page_address(pte); | ||
77 | clean_dcache_area(page, sizeof(pte_t) * PTRS_PER_PTE); | ||
78 | pgtable_page_ctor(pte); | ||
79 | } | ||
80 | |||
81 | return pte; | ||
82 | } | ||
83 | |||
84 | /* | ||
85 | * Free one PTE table. | ||
86 | */ | ||
87 | static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) | ||
88 | { | ||
89 | if (pte) { | ||
90 | pte -= PTRS_PER_PTE; | ||
91 | free_page((unsigned long)pte); | ||
92 | } | ||
93 | } | ||
94 | |||
95 | static inline void pte_free(struct mm_struct *mm, pgtable_t pte) | ||
96 | { | ||
97 | pgtable_page_dtor(pte); | ||
98 | __free_page(pte); | ||
99 | } | ||
100 | |||
101 | static inline void __pmd_populate(pmd_t *pmdp, unsigned long pmdval) | ||
102 | { | ||
103 | pmdp[0] = __pmd(pmdval); | ||
104 | pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t)); | ||
105 | flush_pmd_entry(pmdp); | ||
106 | } | ||
107 | |||
108 | /* | ||
109 | * Populate the pmdp entry with a pointer to the pte. This pmd is part | ||
110 | * of the mm address space. | ||
111 | * | ||
112 | * Ensure that we always set both PMD entries. | ||
113 | */ | ||
114 | static inline void | ||
115 | pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep) | ||
116 | { | ||
117 | unsigned long pte_ptr = (unsigned long)ptep; | ||
118 | |||
119 | /* | ||
120 | * The pmd must be loaded with the physical | ||
121 | * address of the PTE table | ||
122 | */ | ||
123 | pte_ptr -= PTRS_PER_PTE * sizeof(void *); | ||
124 | __pmd_populate(pmdp, __pa(pte_ptr) | _PAGE_KERNEL_TABLE); | ||
125 | } | ||
126 | |||
127 | static inline void | ||
128 | pmd_populate(struct mm_struct *mm, pmd_t *pmdp, pgtable_t ptep) | ||
129 | { | ||
130 | __pmd_populate(pmdp, page_to_pfn(ptep) << PAGE_SHIFT | _PAGE_USER_TABLE); | ||
131 | } | ||
132 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
133 | |||
134 | #endif /* CONFIG_MMU */ | ||
135 | |||
136 | #endif | ||
diff --git a/arch/arm/include/asm/pgtable-hwdef.h b/arch/arm/include/asm/pgtable-hwdef.h new file mode 100644 index 000000000000..fd1521d5cb9d --- /dev/null +++ b/arch/arm/include/asm/pgtable-hwdef.h | |||
@@ -0,0 +1,90 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/pgtable-hwdef.h | ||
3 | * | ||
4 | * Copyright (C) 1995-2002 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #ifndef _ASMARM_PGTABLE_HWDEF_H | ||
11 | #define _ASMARM_PGTABLE_HWDEF_H | ||
12 | |||
13 | /* | ||
14 | * Hardware page table definitions. | ||
15 | * | ||
16 | * + Level 1 descriptor (PMD) | ||
17 | * - common | ||
18 | */ | ||
19 | #define PMD_TYPE_MASK (3 << 0) | ||
20 | #define PMD_TYPE_FAULT (0 << 0) | ||
21 | #define PMD_TYPE_TABLE (1 << 0) | ||
22 | #define PMD_TYPE_SECT (2 << 0) | ||
23 | #define PMD_BIT4 (1 << 4) | ||
24 | #define PMD_DOMAIN(x) ((x) << 5) | ||
25 | #define PMD_PROTECTION (1 << 9) /* v5 */ | ||
26 | /* | ||
27 | * - section | ||
28 | */ | ||
29 | #define PMD_SECT_BUFFERABLE (1 << 2) | ||
30 | #define PMD_SECT_CACHEABLE (1 << 3) | ||
31 | #define PMD_SECT_XN (1 << 4) /* v6 */ | ||
32 | #define PMD_SECT_AP_WRITE (1 << 10) | ||
33 | #define PMD_SECT_AP_READ (1 << 11) | ||
34 | #define PMD_SECT_TEX(x) ((x) << 12) /* v5 */ | ||
35 | #define PMD_SECT_APX (1 << 15) /* v6 */ | ||
36 | #define PMD_SECT_S (1 << 16) /* v6 */ | ||
37 | #define PMD_SECT_nG (1 << 17) /* v6 */ | ||
38 | #define PMD_SECT_SUPER (1 << 18) /* v6 */ | ||
39 | |||
40 | #define PMD_SECT_UNCACHED (0) | ||
41 | #define PMD_SECT_BUFFERED (PMD_SECT_BUFFERABLE) | ||
42 | #define PMD_SECT_WT (PMD_SECT_CACHEABLE) | ||
43 | #define PMD_SECT_WB (PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE) | ||
44 | #define PMD_SECT_MINICACHE (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE) | ||
45 | #define PMD_SECT_WBWA (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE) | ||
46 | #define PMD_SECT_NONSHARED_DEV (PMD_SECT_TEX(2)) | ||
47 | |||
48 | /* | ||
49 | * - coarse table (not used) | ||
50 | */ | ||
51 | |||
52 | /* | ||
53 | * + Level 2 descriptor (PTE) | ||
54 | * - common | ||
55 | */ | ||
56 | #define PTE_TYPE_MASK (3 << 0) | ||
57 | #define PTE_TYPE_FAULT (0 << 0) | ||
58 | #define PTE_TYPE_LARGE (1 << 0) | ||
59 | #define PTE_TYPE_SMALL (2 << 0) | ||
60 | #define PTE_TYPE_EXT (3 << 0) /* v5 */ | ||
61 | #define PTE_BUFFERABLE (1 << 2) | ||
62 | #define PTE_CACHEABLE (1 << 3) | ||
63 | |||
64 | /* | ||
65 | * - extended small page/tiny page | ||
66 | */ | ||
67 | #define PTE_EXT_XN (1 << 0) /* v6 */ | ||
68 | #define PTE_EXT_AP_MASK (3 << 4) | ||
69 | #define PTE_EXT_AP0 (1 << 4) | ||
70 | #define PTE_EXT_AP1 (2 << 4) | ||
71 | #define PTE_EXT_AP_UNO_SRO (0 << 4) | ||
72 | #define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0) | ||
73 | #define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1) | ||
74 | #define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0) | ||
75 | #define PTE_EXT_TEX(x) ((x) << 6) /* v5 */ | ||
76 | #define PTE_EXT_APX (1 << 9) /* v6 */ | ||
77 | #define PTE_EXT_COHERENT (1 << 9) /* XScale3 */ | ||
78 | #define PTE_EXT_SHARED (1 << 10) /* v6 */ | ||
79 | #define PTE_EXT_NG (1 << 11) /* v6 */ | ||
80 | |||
81 | /* | ||
82 | * - small page | ||
83 | */ | ||
84 | #define PTE_SMALL_AP_MASK (0xff << 4) | ||
85 | #define PTE_SMALL_AP_UNO_SRO (0x00 << 4) | ||
86 | #define PTE_SMALL_AP_UNO_SRW (0x55 << 4) | ||
87 | #define PTE_SMALL_AP_URO_SRW (0xaa << 4) | ||
88 | #define PTE_SMALL_AP_URW_SRW (0xff << 4) | ||
89 | |||
90 | #endif | ||
diff --git a/arch/arm/include/asm/pgtable-nommu.h b/arch/arm/include/asm/pgtable-nommu.h new file mode 100644 index 000000000000..b011f2e939aa --- /dev/null +++ b/arch/arm/include/asm/pgtable-nommu.h | |||
@@ -0,0 +1,118 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/pgtable-nommu.h | ||
3 | * | ||
4 | * Copyright (C) 1995-2002 Russell King | ||
5 | * Copyright (C) 2004 Hyok S. Choi | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | #ifndef _ASMARM_PGTABLE_NOMMU_H | ||
12 | #define _ASMARM_PGTABLE_NOMMU_H | ||
13 | |||
14 | #ifndef __ASSEMBLY__ | ||
15 | |||
16 | #include <linux/slab.h> | ||
17 | #include <asm/processor.h> | ||
18 | #include <asm/page.h> | ||
19 | |||
20 | /* | ||
21 | * Trivial page table functions. | ||
22 | */ | ||
23 | #define pgd_present(pgd) (1) | ||
24 | #define pgd_none(pgd) (0) | ||
25 | #define pgd_bad(pgd) (0) | ||
26 | #define pgd_clear(pgdp) | ||
27 | #define kern_addr_valid(addr) (1) | ||
28 | #define pmd_offset(a, b) ((void *)0) | ||
29 | /* FIXME */ | ||
30 | /* | ||
31 | * PMD_SHIFT determines the size of the area a second-level page table can map | ||
32 | * PGDIR_SHIFT determines what a third-level page table entry can map | ||
33 | */ | ||
34 | #define PGDIR_SHIFT 21 | ||
35 | |||
36 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) | ||
37 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | ||
38 | /* FIXME */ | ||
39 | |||
40 | #define PAGE_NONE __pgprot(0) | ||
41 | #define PAGE_SHARED __pgprot(0) | ||
42 | #define PAGE_COPY __pgprot(0) | ||
43 | #define PAGE_READONLY __pgprot(0) | ||
44 | #define PAGE_KERNEL __pgprot(0) | ||
45 | |||
46 | #define swapper_pg_dir ((pgd_t *) 0) | ||
47 | |||
48 | #define __swp_type(x) (0) | ||
49 | #define __swp_offset(x) (0) | ||
50 | #define __swp_entry(typ,off) ((swp_entry_t) { ((typ) | ((off) << 7)) }) | ||
51 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | ||
52 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) | ||
53 | |||
54 | |||
55 | typedef pte_t *pte_addr_t; | ||
56 | |||
57 | static inline int pte_file(pte_t pte) { return 0; } | ||
58 | |||
59 | /* | ||
60 | * ZERO_PAGE is a global shared page that is always zero: used | ||
61 | * for zero-mapped memory areas etc.. | ||
62 | */ | ||
63 | #define ZERO_PAGE(vaddr) (virt_to_page(0)) | ||
64 | |||
65 | /* | ||
66 | * Mark the prot value as uncacheable and unbufferable. | ||
67 | */ | ||
68 | #define pgprot_noncached(prot) __pgprot(0) | ||
69 | #define pgprot_writecombine(prot) __pgprot(0) | ||
70 | |||
71 | |||
72 | /* | ||
73 | * These would be in other places but having them here reduces the diffs. | ||
74 | */ | ||
75 | extern unsigned int kobjsize(const void *objp); | ||
76 | |||
77 | /* | ||
78 | * No page table caches to initialise. | ||
79 | */ | ||
80 | #define pgtable_cache_init() do { } while (0) | ||
81 | #define io_remap_page_range remap_page_range | ||
82 | #define io_remap_pfn_range remap_pfn_range | ||
83 | |||
84 | |||
85 | /* | ||
86 | * All 32bit addresses are effectively valid for vmalloc... | ||
87 | * Sort of meaningless for non-VM targets. | ||
88 | */ | ||
89 | #define VMALLOC_START 0 | ||
90 | #define VMALLOC_END 0xffffffff | ||
91 | |||
92 | #define FIRST_USER_ADDRESS (0) | ||
93 | |||
94 | #include <asm-generic/pgtable.h> | ||
95 | |||
96 | #else | ||
97 | |||
98 | /* | ||
99 | * dummy tlb and user structures. | ||
100 | */ | ||
101 | #define v3_tlb_fns (0) | ||
102 | #define v4_tlb_fns (0) | ||
103 | #define v4wb_tlb_fns (0) | ||
104 | #define v4wbi_tlb_fns (0) | ||
105 | #define v6wbi_tlb_fns (0) | ||
106 | #define v7wbi_tlb_fns (0) | ||
107 | |||
108 | #define v3_user_fns (0) | ||
109 | #define v4_user_fns (0) | ||
110 | #define v4_mc_user_fns (0) | ||
111 | #define v4wb_user_fns (0) | ||
112 | #define v4wt_user_fns (0) | ||
113 | #define v6_user_fns (0) | ||
114 | #define xscale_mc_user_fns (0) | ||
115 | |||
116 | #endif /*__ASSEMBLY__*/ | ||
117 | |||
118 | #endif /* _ASMARM_PGTABLE_H */ | ||
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h new file mode 100644 index 000000000000..8ab060a53ab0 --- /dev/null +++ b/arch/arm/include/asm/pgtable.h | |||
@@ -0,0 +1,401 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/pgtable.h | ||
3 | * | ||
4 | * Copyright (C) 1995-2002 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #ifndef _ASMARM_PGTABLE_H | ||
11 | #define _ASMARM_PGTABLE_H | ||
12 | |||
13 | #include <asm-generic/4level-fixup.h> | ||
14 | #include <asm/proc-fns.h> | ||
15 | |||
16 | #ifndef CONFIG_MMU | ||
17 | |||
18 | #include "pgtable-nommu.h" | ||
19 | |||
20 | #else | ||
21 | |||
22 | #include <asm/memory.h> | ||
23 | #include <asm/arch/vmalloc.h> | ||
24 | #include <asm/pgtable-hwdef.h> | ||
25 | |||
26 | /* | ||
27 | * Just any arbitrary offset to the start of the vmalloc VM area: the | ||
28 | * current 8MB value just means that there will be a 8MB "hole" after the | ||
29 | * physical memory until the kernel virtual memory starts. That means that | ||
30 | * any out-of-bounds memory accesses will hopefully be caught. | ||
31 | * The vmalloc() routines leaves a hole of 4kB between each vmalloced | ||
32 | * area for the same reason. ;) | ||
33 | * | ||
34 | * Note that platforms may override VMALLOC_START, but they must provide | ||
35 | * VMALLOC_END. VMALLOC_END defines the (exclusive) limit of this space, | ||
36 | * which may not overlap IO space. | ||
37 | */ | ||
38 | #ifndef VMALLOC_START | ||
39 | #define VMALLOC_OFFSET (8*1024*1024) | ||
40 | #define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) | ||
41 | #endif | ||
42 | |||
43 | /* | ||
44 | * Hardware-wise, we have a two level page table structure, where the first | ||
45 | * level has 4096 entries, and the second level has 256 entries. Each entry | ||
46 | * is one 32-bit word. Most of the bits in the second level entry are used | ||
47 | * by hardware, and there aren't any "accessed" and "dirty" bits. | ||
48 | * | ||
49 | * Linux on the other hand has a three level page table structure, which can | ||
50 | * be wrapped to fit a two level page table structure easily - using the PGD | ||
51 | * and PTE only. However, Linux also expects one "PTE" table per page, and | ||
52 | * at least a "dirty" bit. | ||
53 | * | ||
54 | * Therefore, we tweak the implementation slightly - we tell Linux that we | ||
55 | * have 2048 entries in the first level, each of which is 8 bytes (iow, two | ||
56 | * hardware pointers to the second level.) The second level contains two | ||
57 | * hardware PTE tables arranged contiguously, followed by Linux versions | ||
58 | * which contain the state information Linux needs. We, therefore, end up | ||
59 | * with 512 entries in the "PTE" level. | ||
60 | * | ||
61 | * This leads to the page tables having the following layout: | ||
62 | * | ||
63 | * pgd pte | ||
64 | * | | | ||
65 | * +--------+ +0 | ||
66 | * | |-----> +------------+ +0 | ||
67 | * +- - - - + +4 | h/w pt 0 | | ||
68 | * | |-----> +------------+ +1024 | ||
69 | * +--------+ +8 | h/w pt 1 | | ||
70 | * | | +------------+ +2048 | ||
71 | * +- - - - + | Linux pt 0 | | ||
72 | * | | +------------+ +3072 | ||
73 | * +--------+ | Linux pt 1 | | ||
74 | * | | +------------+ +4096 | ||
75 | * | ||
76 | * See L_PTE_xxx below for definitions of bits in the "Linux pt", and | ||
77 | * PTE_xxx for definitions of bits appearing in the "h/w pt". | ||
78 | * | ||
79 | * PMD_xxx definitions refer to bits in the first level page table. | ||
80 | * | ||
81 | * The "dirty" bit is emulated by only granting hardware write permission | ||
82 | * iff the page is marked "writable" and "dirty" in the Linux PTE. This | ||
83 | * means that a write to a clean page will cause a permission fault, and | ||
84 | * the Linux MM layer will mark the page dirty via handle_pte_fault(). | ||
85 | * For the hardware to notice the permission change, the TLB entry must | ||
86 | * be flushed, and ptep_set_access_flags() does that for us. | ||
87 | * | ||
88 | * The "accessed" or "young" bit is emulated by a similar method; we only | ||
89 | * allow accesses to the page if the "young" bit is set. Accesses to the | ||
90 | * page will cause a fault, and handle_pte_fault() will set the young bit | ||
91 | * for us as long as the page is marked present in the corresponding Linux | ||
92 | * PTE entry. Again, ptep_set_access_flags() will ensure that the TLB is | ||
93 | * up to date. | ||
94 | * | ||
95 | * However, when the "young" bit is cleared, we deny access to the page | ||
96 | * by clearing the hardware PTE. Currently Linux does not flush the TLB | ||
97 | * for us in this case, which means the TLB will retain the transation | ||
98 | * until either the TLB entry is evicted under pressure, or a context | ||
99 | * switch which changes the user space mapping occurs. | ||
100 | */ | ||
101 | #define PTRS_PER_PTE 512 | ||
102 | #define PTRS_PER_PMD 1 | ||
103 | #define PTRS_PER_PGD 2048 | ||
104 | |||
105 | /* | ||
106 | * PMD_SHIFT determines the size of the area a second-level page table can map | ||
107 | * PGDIR_SHIFT determines what a third-level page table entry can map | ||
108 | */ | ||
109 | #define PMD_SHIFT 21 | ||
110 | #define PGDIR_SHIFT 21 | ||
111 | |||
112 | #define LIBRARY_TEXT_START 0x0c000000 | ||
113 | |||
114 | #ifndef __ASSEMBLY__ | ||
115 | extern void __pte_error(const char *file, int line, unsigned long val); | ||
116 | extern void __pmd_error(const char *file, int line, unsigned long val); | ||
117 | extern void __pgd_error(const char *file, int line, unsigned long val); | ||
118 | |||
119 | #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte)) | ||
120 | #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd)) | ||
121 | #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd)) | ||
122 | #endif /* !__ASSEMBLY__ */ | ||
123 | |||
124 | #define PMD_SIZE (1UL << PMD_SHIFT) | ||
125 | #define PMD_MASK (~(PMD_SIZE-1)) | ||
126 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) | ||
127 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | ||
128 | |||
129 | /* | ||
130 | * This is the lowest virtual address we can permit any user space | ||
131 | * mapping to be mapped at. This is particularly important for | ||
132 | * non-high vector CPUs. | ||
133 | */ | ||
134 | #define FIRST_USER_ADDRESS PAGE_SIZE | ||
135 | |||
136 | #define FIRST_USER_PGD_NR 1 | ||
137 | #define USER_PTRS_PER_PGD ((TASK_SIZE/PGDIR_SIZE) - FIRST_USER_PGD_NR) | ||
138 | |||
139 | /* | ||
140 | * section address mask and size definitions. | ||
141 | */ | ||
142 | #define SECTION_SHIFT 20 | ||
143 | #define SECTION_SIZE (1UL << SECTION_SHIFT) | ||
144 | #define SECTION_MASK (~(SECTION_SIZE-1)) | ||
145 | |||
146 | /* | ||
147 | * ARMv6 supersection address mask and size definitions. | ||
148 | */ | ||
149 | #define SUPERSECTION_SHIFT 24 | ||
150 | #define SUPERSECTION_SIZE (1UL << SUPERSECTION_SHIFT) | ||
151 | #define SUPERSECTION_MASK (~(SUPERSECTION_SIZE-1)) | ||
152 | |||
153 | /* | ||
154 | * "Linux" PTE definitions. | ||
155 | * | ||
156 | * We keep two sets of PTEs - the hardware and the linux version. | ||
157 | * This allows greater flexibility in the way we map the Linux bits | ||
158 | * onto the hardware tables, and allows us to have YOUNG and DIRTY | ||
159 | * bits. | ||
160 | * | ||
161 | * The PTE table pointer refers to the hardware entries; the "Linux" | ||
162 | * entries are stored 1024 bytes below. | ||
163 | */ | ||
164 | #define L_PTE_PRESENT (1 << 0) | ||
165 | #define L_PTE_FILE (1 << 1) /* only when !PRESENT */ | ||
166 | #define L_PTE_YOUNG (1 << 1) | ||
167 | #define L_PTE_BUFFERABLE (1 << 2) /* matches PTE */ | ||
168 | #define L_PTE_CACHEABLE (1 << 3) /* matches PTE */ | ||
169 | #define L_PTE_USER (1 << 4) | ||
170 | #define L_PTE_WRITE (1 << 5) | ||
171 | #define L_PTE_EXEC (1 << 6) | ||
172 | #define L_PTE_DIRTY (1 << 7) | ||
173 | #define L_PTE_SHARED (1 << 10) /* shared(v6), coherent(xsc3) */ | ||
174 | |||
175 | #ifndef __ASSEMBLY__ | ||
176 | |||
177 | /* | ||
178 | * The pgprot_* and protection_map entries will be fixed up in runtime | ||
179 | * to include the cachable and bufferable bits based on memory policy, | ||
180 | * as well as any architecture dependent bits like global/ASID and SMP | ||
181 | * shared mapping bits. | ||
182 | */ | ||
183 | #define _L_PTE_DEFAULT L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_CACHEABLE | L_PTE_BUFFERABLE | ||
184 | #define _L_PTE_READ L_PTE_USER | L_PTE_EXEC | ||
185 | |||
186 | extern pgprot_t pgprot_user; | ||
187 | extern pgprot_t pgprot_kernel; | ||
188 | |||
189 | #define PAGE_NONE pgprot_user | ||
190 | #define PAGE_COPY __pgprot(pgprot_val(pgprot_user) | _L_PTE_READ) | ||
191 | #define PAGE_SHARED __pgprot(pgprot_val(pgprot_user) | _L_PTE_READ | \ | ||
192 | L_PTE_WRITE) | ||
193 | #define PAGE_READONLY __pgprot(pgprot_val(pgprot_user) | _L_PTE_READ) | ||
194 | #define PAGE_KERNEL pgprot_kernel | ||
195 | |||
196 | #define __PAGE_NONE __pgprot(_L_PTE_DEFAULT) | ||
197 | #define __PAGE_COPY __pgprot(_L_PTE_DEFAULT | _L_PTE_READ) | ||
198 | #define __PAGE_SHARED __pgprot(_L_PTE_DEFAULT | _L_PTE_READ | L_PTE_WRITE) | ||
199 | #define __PAGE_READONLY __pgprot(_L_PTE_DEFAULT | _L_PTE_READ) | ||
200 | |||
201 | #endif /* __ASSEMBLY__ */ | ||
202 | |||
203 | /* | ||
204 | * The table below defines the page protection levels that we insert into our | ||
205 | * Linux page table version. These get translated into the best that the | ||
206 | * architecture can perform. Note that on most ARM hardware: | ||
207 | * 1) We cannot do execute protection | ||
208 | * 2) If we could do execute protection, then read is implied | ||
209 | * 3) write implies read permissions | ||
210 | */ | ||
211 | #define __P000 __PAGE_NONE | ||
212 | #define __P001 __PAGE_READONLY | ||
213 | #define __P010 __PAGE_COPY | ||
214 | #define __P011 __PAGE_COPY | ||
215 | #define __P100 __PAGE_READONLY | ||
216 | #define __P101 __PAGE_READONLY | ||
217 | #define __P110 __PAGE_COPY | ||
218 | #define __P111 __PAGE_COPY | ||
219 | |||
220 | #define __S000 __PAGE_NONE | ||
221 | #define __S001 __PAGE_READONLY | ||
222 | #define __S010 __PAGE_SHARED | ||
223 | #define __S011 __PAGE_SHARED | ||
224 | #define __S100 __PAGE_READONLY | ||
225 | #define __S101 __PAGE_READONLY | ||
226 | #define __S110 __PAGE_SHARED | ||
227 | #define __S111 __PAGE_SHARED | ||
228 | |||
229 | #ifndef __ASSEMBLY__ | ||
230 | /* | ||
231 | * ZERO_PAGE is a global shared page that is always zero: used | ||
232 | * for zero-mapped memory areas etc.. | ||
233 | */ | ||
234 | extern struct page *empty_zero_page; | ||
235 | #define ZERO_PAGE(vaddr) (empty_zero_page) | ||
236 | |||
237 | #define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) | ||
238 | #define pfn_pte(pfn,prot) (__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))) | ||
239 | |||
240 | #define pte_none(pte) (!pte_val(pte)) | ||
241 | #define pte_clear(mm,addr,ptep) set_pte_ext(ptep, __pte(0), 0) | ||
242 | #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) | ||
243 | #define pte_offset_kernel(dir,addr) (pmd_page_vaddr(*(dir)) + __pte_index(addr)) | ||
244 | #define pte_offset_map(dir,addr) (pmd_page_vaddr(*(dir)) + __pte_index(addr)) | ||
245 | #define pte_offset_map_nested(dir,addr) (pmd_page_vaddr(*(dir)) + __pte_index(addr)) | ||
246 | #define pte_unmap(pte) do { } while (0) | ||
247 | #define pte_unmap_nested(pte) do { } while (0) | ||
248 | |||
249 | #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext) | ||
250 | |||
251 | #define set_pte_at(mm,addr,ptep,pteval) do { \ | ||
252 | set_pte_ext(ptep, pteval, (addr) >= TASK_SIZE ? 0 : PTE_EXT_NG); \ | ||
253 | } while (0) | ||
254 | |||
255 | /* | ||
256 | * The following only work if pte_present() is true. | ||
257 | * Undefined behaviour if not.. | ||
258 | */ | ||
259 | #define pte_present(pte) (pte_val(pte) & L_PTE_PRESENT) | ||
260 | #define pte_write(pte) (pte_val(pte) & L_PTE_WRITE) | ||
261 | #define pte_dirty(pte) (pte_val(pte) & L_PTE_DIRTY) | ||
262 | #define pte_young(pte) (pte_val(pte) & L_PTE_YOUNG) | ||
263 | #define pte_special(pte) (0) | ||
264 | |||
265 | /* | ||
266 | * The following only works if pte_present() is not true. | ||
267 | */ | ||
268 | #define pte_file(pte) (pte_val(pte) & L_PTE_FILE) | ||
269 | #define pte_to_pgoff(x) (pte_val(x) >> 2) | ||
270 | #define pgoff_to_pte(x) __pte(((x) << 2) | L_PTE_FILE) | ||
271 | |||
272 | #define PTE_FILE_MAX_BITS 30 | ||
273 | |||
274 | #define PTE_BIT_FUNC(fn,op) \ | ||
275 | static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; } | ||
276 | |||
277 | PTE_BIT_FUNC(wrprotect, &= ~L_PTE_WRITE); | ||
278 | PTE_BIT_FUNC(mkwrite, |= L_PTE_WRITE); | ||
279 | PTE_BIT_FUNC(mkclean, &= ~L_PTE_DIRTY); | ||
280 | PTE_BIT_FUNC(mkdirty, |= L_PTE_DIRTY); | ||
281 | PTE_BIT_FUNC(mkold, &= ~L_PTE_YOUNG); | ||
282 | PTE_BIT_FUNC(mkyoung, |= L_PTE_YOUNG); | ||
283 | |||
284 | static inline pte_t pte_mkspecial(pte_t pte) { return pte; } | ||
285 | |||
286 | /* | ||
287 | * Mark the prot value as uncacheable and unbufferable. | ||
288 | */ | ||
289 | #define pgprot_noncached(prot) __pgprot(pgprot_val(prot) & ~(L_PTE_CACHEABLE | L_PTE_BUFFERABLE)) | ||
290 | #define pgprot_writecombine(prot) __pgprot(pgprot_val(prot) & ~L_PTE_CACHEABLE) | ||
291 | |||
292 | #define pmd_none(pmd) (!pmd_val(pmd)) | ||
293 | #define pmd_present(pmd) (pmd_val(pmd)) | ||
294 | #define pmd_bad(pmd) (pmd_val(pmd) & 2) | ||
295 | |||
296 | #define copy_pmd(pmdpd,pmdps) \ | ||
297 | do { \ | ||
298 | pmdpd[0] = pmdps[0]; \ | ||
299 | pmdpd[1] = pmdps[1]; \ | ||
300 | flush_pmd_entry(pmdpd); \ | ||
301 | } while (0) | ||
302 | |||
303 | #define pmd_clear(pmdp) \ | ||
304 | do { \ | ||
305 | pmdp[0] = __pmd(0); \ | ||
306 | pmdp[1] = __pmd(0); \ | ||
307 | clean_pmd_entry(pmdp); \ | ||
308 | } while (0) | ||
309 | |||
310 | static inline pte_t *pmd_page_vaddr(pmd_t pmd) | ||
311 | { | ||
312 | unsigned long ptr; | ||
313 | |||
314 | ptr = pmd_val(pmd) & ~(PTRS_PER_PTE * sizeof(void *) - 1); | ||
315 | ptr += PTRS_PER_PTE * sizeof(void *); | ||
316 | |||
317 | return __va(ptr); | ||
318 | } | ||
319 | |||
320 | #define pmd_page(pmd) virt_to_page(__va(pmd_val(pmd))) | ||
321 | |||
322 | /* | ||
323 | * Permanent address of a page. We never have highmem, so this is trivial. | ||
324 | */ | ||
325 | #define pages_to_mb(x) ((x) >> (20 - PAGE_SHIFT)) | ||
326 | |||
327 | /* | ||
328 | * Conversion functions: convert a page and protection to a page entry, | ||
329 | * and a page entry and page directory to the page they refer to. | ||
330 | */ | ||
331 | #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) | ||
332 | |||
333 | /* | ||
334 | * The "pgd_xxx()" functions here are trivial for a folded two-level | ||
335 | * setup: the pgd is never bad, and a pmd always exists (as it's folded | ||
336 | * into the pgd entry) | ||
337 | */ | ||
338 | #define pgd_none(pgd) (0) | ||
339 | #define pgd_bad(pgd) (0) | ||
340 | #define pgd_present(pgd) (1) | ||
341 | #define pgd_clear(pgdp) do { } while (0) | ||
342 | #define set_pgd(pgd,pgdp) do { } while (0) | ||
343 | |||
344 | /* to find an entry in a page-table-directory */ | ||
345 | #define pgd_index(addr) ((addr) >> PGDIR_SHIFT) | ||
346 | |||
347 | #define pgd_offset(mm, addr) ((mm)->pgd+pgd_index(addr)) | ||
348 | |||
349 | /* to find an entry in a kernel page-table-directory */ | ||
350 | #define pgd_offset_k(addr) pgd_offset(&init_mm, addr) | ||
351 | |||
352 | /* Find an entry in the second-level page table.. */ | ||
353 | #define pmd_offset(dir, addr) ((pmd_t *)(dir)) | ||
354 | |||
355 | /* Find an entry in the third-level page table.. */ | ||
356 | #define __pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) | ||
357 | |||
358 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) | ||
359 | { | ||
360 | const unsigned long mask = L_PTE_EXEC | L_PTE_WRITE | L_PTE_USER; | ||
361 | pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); | ||
362 | return pte; | ||
363 | } | ||
364 | |||
365 | extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; | ||
366 | |||
367 | /* Encode and decode a swap entry. | ||
368 | * | ||
369 | * We support up to 32GB of swap on 4k machines | ||
370 | */ | ||
371 | #define __swp_type(x) (((x).val >> 2) & 0x7f) | ||
372 | #define __swp_offset(x) ((x).val >> 9) | ||
373 | #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 2) | ((offset) << 9) }) | ||
374 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | ||
375 | #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) | ||
376 | |||
377 | /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */ | ||
378 | /* FIXME: this is not correct */ | ||
379 | #define kern_addr_valid(addr) (1) | ||
380 | |||
381 | #include <asm-generic/pgtable.h> | ||
382 | |||
383 | /* | ||
384 | * We provide our own arch_get_unmapped_area to cope with VIPT caches. | ||
385 | */ | ||
386 | #define HAVE_ARCH_UNMAPPED_AREA | ||
387 | |||
388 | /* | ||
389 | * remap a physical page `pfn' of size `size' with page protection `prot' | ||
390 | * into virtual address `from' | ||
391 | */ | ||
392 | #define io_remap_pfn_range(vma,from,pfn,size,prot) \ | ||
393 | remap_pfn_range(vma, from, pfn, size, prot) | ||
394 | |||
395 | #define pgtable_cache_init() do { } while (0) | ||
396 | |||
397 | #endif /* !__ASSEMBLY__ */ | ||
398 | |||
399 | #endif /* CONFIG_MMU */ | ||
400 | |||
401 | #endif /* _ASMARM_PGTABLE_H */ | ||
diff --git a/arch/arm/include/asm/poll.h b/arch/arm/include/asm/poll.h new file mode 100644 index 000000000000..c98509d3149e --- /dev/null +++ b/arch/arm/include/asm/poll.h | |||
@@ -0,0 +1 @@ | |||
#include <asm-generic/poll.h> | |||
diff --git a/arch/arm/include/asm/posix_types.h b/arch/arm/include/asm/posix_types.h new file mode 100644 index 000000000000..2446d23bfdbf --- /dev/null +++ b/arch/arm/include/asm/posix_types.h | |||
@@ -0,0 +1,77 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/posix_types.h | ||
3 | * | ||
4 | * Copyright (C) 1996-1998 Russell King. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * Changelog: | ||
11 | * 27-06-1996 RMK Created | ||
12 | */ | ||
13 | #ifndef __ARCH_ARM_POSIX_TYPES_H | ||
14 | #define __ARCH_ARM_POSIX_TYPES_H | ||
15 | |||
16 | /* | ||
17 | * This file is generally used by user-level software, so you need to | ||
18 | * be a little careful about namespace pollution etc. Also, we cannot | ||
19 | * assume GCC is being used. | ||
20 | */ | ||
21 | |||
22 | typedef unsigned long __kernel_ino_t; | ||
23 | typedef unsigned short __kernel_mode_t; | ||
24 | typedef unsigned short __kernel_nlink_t; | ||
25 | typedef long __kernel_off_t; | ||
26 | typedef int __kernel_pid_t; | ||
27 | typedef unsigned short __kernel_ipc_pid_t; | ||
28 | typedef unsigned short __kernel_uid_t; | ||
29 | typedef unsigned short __kernel_gid_t; | ||
30 | typedef unsigned int __kernel_size_t; | ||
31 | typedef int __kernel_ssize_t; | ||
32 | typedef int __kernel_ptrdiff_t; | ||
33 | typedef long __kernel_time_t; | ||
34 | typedef long __kernel_suseconds_t; | ||
35 | typedef long __kernel_clock_t; | ||
36 | typedef int __kernel_timer_t; | ||
37 | typedef int __kernel_clockid_t; | ||
38 | typedef int __kernel_daddr_t; | ||
39 | typedef char * __kernel_caddr_t; | ||
40 | typedef unsigned short __kernel_uid16_t; | ||
41 | typedef unsigned short __kernel_gid16_t; | ||
42 | typedef unsigned int __kernel_uid32_t; | ||
43 | typedef unsigned int __kernel_gid32_t; | ||
44 | |||
45 | typedef unsigned short __kernel_old_uid_t; | ||
46 | typedef unsigned short __kernel_old_gid_t; | ||
47 | typedef unsigned short __kernel_old_dev_t; | ||
48 | |||
49 | #ifdef __GNUC__ | ||
50 | typedef long long __kernel_loff_t; | ||
51 | #endif | ||
52 | |||
53 | typedef struct { | ||
54 | int val[2]; | ||
55 | } __kernel_fsid_t; | ||
56 | |||
57 | #if defined(__KERNEL__) | ||
58 | |||
59 | #undef __FD_SET | ||
60 | #define __FD_SET(fd, fdsetp) \ | ||
61 | (((fd_set *)(fdsetp))->fds_bits[(fd) >> 5] |= (1<<((fd) & 31))) | ||
62 | |||
63 | #undef __FD_CLR | ||
64 | #define __FD_CLR(fd, fdsetp) \ | ||
65 | (((fd_set *)(fdsetp))->fds_bits[(fd) >> 5] &= ~(1<<((fd) & 31))) | ||
66 | |||
67 | #undef __FD_ISSET | ||
68 | #define __FD_ISSET(fd, fdsetp) \ | ||
69 | ((((fd_set *)(fdsetp))->fds_bits[(fd) >> 5] & (1<<((fd) & 31))) != 0) | ||
70 | |||
71 | #undef __FD_ZERO | ||
72 | #define __FD_ZERO(fdsetp) \ | ||
73 | (memset (fdsetp, 0, sizeof (*(fd_set *)(fdsetp)))) | ||
74 | |||
75 | #endif | ||
76 | |||
77 | #endif | ||
diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h new file mode 100644 index 000000000000..db80203b68e0 --- /dev/null +++ b/arch/arm/include/asm/proc-fns.h | |||
@@ -0,0 +1,241 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/proc-fns.h | ||
3 | * | ||
4 | * Copyright (C) 1997-1999 Russell King | ||
5 | * Copyright (C) 2000 Deep Blue Solutions Ltd | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | #ifndef __ASM_PROCFNS_H | ||
12 | #define __ASM_PROCFNS_H | ||
13 | |||
14 | #ifdef __KERNEL__ | ||
15 | |||
16 | |||
17 | /* | ||
18 | * Work out if we need multiple CPU support | ||
19 | */ | ||
20 | #undef MULTI_CPU | ||
21 | #undef CPU_NAME | ||
22 | |||
23 | /* | ||
24 | * CPU_NAME - the prefix for CPU related functions | ||
25 | */ | ||
26 | |||
27 | #ifdef CONFIG_CPU_32 | ||
28 | # ifdef CONFIG_CPU_ARM610 | ||
29 | # ifdef CPU_NAME | ||
30 | # undef MULTI_CPU | ||
31 | # define MULTI_CPU | ||
32 | # else | ||
33 | # define CPU_NAME cpu_arm6 | ||
34 | # endif | ||
35 | # endif | ||
36 | # ifdef CONFIG_CPU_ARM7TDMI | ||
37 | # ifdef CPU_NAME | ||
38 | # undef MULTI_CPU | ||
39 | # define MULTI_CPU | ||
40 | # else | ||
41 | # define CPU_NAME cpu_arm7tdmi | ||
42 | # endif | ||
43 | # endif | ||
44 | # ifdef CONFIG_CPU_ARM710 | ||
45 | # ifdef CPU_NAME | ||
46 | # undef MULTI_CPU | ||
47 | # define MULTI_CPU | ||
48 | # else | ||
49 | # define CPU_NAME cpu_arm7 | ||
50 | # endif | ||
51 | # endif | ||
52 | # ifdef CONFIG_CPU_ARM720T | ||
53 | # ifdef CPU_NAME | ||
54 | # undef MULTI_CPU | ||
55 | # define MULTI_CPU | ||
56 | # else | ||
57 | # define CPU_NAME cpu_arm720 | ||
58 | # endif | ||
59 | # endif | ||
60 | # ifdef CONFIG_CPU_ARM740T | ||
61 | # ifdef CPU_NAME | ||
62 | # undef MULTI_CPU | ||
63 | # define MULTI_CPU | ||
64 | # else | ||
65 | # define CPU_NAME cpu_arm740 | ||
66 | # endif | ||
67 | # endif | ||
68 | # ifdef CONFIG_CPU_ARM9TDMI | ||
69 | # ifdef CPU_NAME | ||
70 | # undef MULTI_CPU | ||
71 | # define MULTI_CPU | ||
72 | # else | ||
73 | # define CPU_NAME cpu_arm9tdmi | ||
74 | # endif | ||
75 | # endif | ||
76 | # ifdef CONFIG_CPU_ARM920T | ||
77 | # ifdef CPU_NAME | ||
78 | # undef MULTI_CPU | ||
79 | # define MULTI_CPU | ||
80 | # else | ||
81 | # define CPU_NAME cpu_arm920 | ||
82 | # endif | ||
83 | # endif | ||
84 | # ifdef CONFIG_CPU_ARM922T | ||
85 | # ifdef CPU_NAME | ||
86 | # undef MULTI_CPU | ||
87 | # define MULTI_CPU | ||
88 | # else | ||
89 | # define CPU_NAME cpu_arm922 | ||
90 | # endif | ||
91 | # endif | ||
92 | # ifdef CONFIG_CPU_ARM925T | ||
93 | # ifdef CPU_NAME | ||
94 | # undef MULTI_CPU | ||
95 | # define MULTI_CPU | ||
96 | # else | ||
97 | # define CPU_NAME cpu_arm925 | ||
98 | # endif | ||
99 | # endif | ||
100 | # ifdef CONFIG_CPU_ARM926T | ||
101 | # ifdef CPU_NAME | ||
102 | # undef MULTI_CPU | ||
103 | # define MULTI_CPU | ||
104 | # else | ||
105 | # define CPU_NAME cpu_arm926 | ||
106 | # endif | ||
107 | # endif | ||
108 | # ifdef CONFIG_CPU_ARM940T | ||
109 | # ifdef CPU_NAME | ||
110 | # undef MULTI_CPU | ||
111 | # define MULTI_CPU | ||
112 | # else | ||
113 | # define CPU_NAME cpu_arm940 | ||
114 | # endif | ||
115 | # endif | ||
116 | # ifdef CONFIG_CPU_ARM946E | ||
117 | # ifdef CPU_NAME | ||
118 | # undef MULTI_CPU | ||
119 | # define MULTI_CPU | ||
120 | # else | ||
121 | # define CPU_NAME cpu_arm946 | ||
122 | # endif | ||
123 | # endif | ||
124 | # ifdef CONFIG_CPU_SA110 | ||
125 | # ifdef CPU_NAME | ||
126 | # undef MULTI_CPU | ||
127 | # define MULTI_CPU | ||
128 | # else | ||
129 | # define CPU_NAME cpu_sa110 | ||
130 | # endif | ||
131 | # endif | ||
132 | # ifdef CONFIG_CPU_SA1100 | ||
133 | # ifdef CPU_NAME | ||
134 | # undef MULTI_CPU | ||
135 | # define MULTI_CPU | ||
136 | # else | ||
137 | # define CPU_NAME cpu_sa1100 | ||
138 | # endif | ||
139 | # endif | ||
140 | # ifdef CONFIG_CPU_ARM1020 | ||
141 | # ifdef CPU_NAME | ||
142 | # undef MULTI_CPU | ||
143 | # define MULTI_CPU | ||
144 | # else | ||
145 | # define CPU_NAME cpu_arm1020 | ||
146 | # endif | ||
147 | # endif | ||
148 | # ifdef CONFIG_CPU_ARM1020E | ||
149 | # ifdef CPU_NAME | ||
150 | # undef MULTI_CPU | ||
151 | # define MULTI_CPU | ||
152 | # else | ||
153 | # define CPU_NAME cpu_arm1020e | ||
154 | # endif | ||
155 | # endif | ||
156 | # ifdef CONFIG_CPU_ARM1022 | ||
157 | # ifdef CPU_NAME | ||
158 | # undef MULTI_CPU | ||
159 | # define MULTI_CPU | ||
160 | # else | ||
161 | # define CPU_NAME cpu_arm1022 | ||
162 | # endif | ||
163 | # endif | ||
164 | # ifdef CONFIG_CPU_ARM1026 | ||
165 | # ifdef CPU_NAME | ||
166 | # undef MULTI_CPU | ||
167 | # define MULTI_CPU | ||
168 | # else | ||
169 | # define CPU_NAME cpu_arm1026 | ||
170 | # endif | ||
171 | # endif | ||
172 | # ifdef CONFIG_CPU_XSCALE | ||
173 | # ifdef CPU_NAME | ||
174 | # undef MULTI_CPU | ||
175 | # define MULTI_CPU | ||
176 | # else | ||
177 | # define CPU_NAME cpu_xscale | ||
178 | # endif | ||
179 | # endif | ||
180 | # ifdef CONFIG_CPU_XSC3 | ||
181 | # ifdef CPU_NAME | ||
182 | # undef MULTI_CPU | ||
183 | # define MULTI_CPU | ||
184 | # else | ||
185 | # define CPU_NAME cpu_xsc3 | ||
186 | # endif | ||
187 | # endif | ||
188 | # ifdef CONFIG_CPU_FEROCEON | ||
189 | # ifdef CPU_NAME | ||
190 | # undef MULTI_CPU | ||
191 | # define MULTI_CPU | ||
192 | # else | ||
193 | # define CPU_NAME cpu_feroceon | ||
194 | # endif | ||
195 | # endif | ||
196 | # ifdef CONFIG_CPU_V6 | ||
197 | # ifdef CPU_NAME | ||
198 | # undef MULTI_CPU | ||
199 | # define MULTI_CPU | ||
200 | # else | ||
201 | # define CPU_NAME cpu_v6 | ||
202 | # endif | ||
203 | # endif | ||
204 | # ifdef CONFIG_CPU_V7 | ||
205 | # ifdef CPU_NAME | ||
206 | # undef MULTI_CPU | ||
207 | # define MULTI_CPU | ||
208 | # else | ||
209 | # define CPU_NAME cpu_v7 | ||
210 | # endif | ||
211 | # endif | ||
212 | #endif | ||
213 | |||
214 | #ifndef __ASSEMBLY__ | ||
215 | |||
216 | #ifndef MULTI_CPU | ||
217 | #include <asm/cpu-single.h> | ||
218 | #else | ||
219 | #include <asm/cpu-multi32.h> | ||
220 | #endif | ||
221 | |||
222 | #include <asm/memory.h> | ||
223 | |||
224 | #ifdef CONFIG_MMU | ||
225 | |||
226 | #define cpu_switch_mm(pgd,mm) cpu_do_switch_mm(virt_to_phys(pgd),mm) | ||
227 | |||
228 | #define cpu_get_pgd() \ | ||
229 | ({ \ | ||
230 | unsigned long pg; \ | ||
231 | __asm__("mrc p15, 0, %0, c2, c0, 0" \ | ||
232 | : "=r" (pg) : : "cc"); \ | ||
233 | pg &= ~0x3fff; \ | ||
234 | (pgd_t *)phys_to_virt(pg); \ | ||
235 | }) | ||
236 | |||
237 | #endif | ||
238 | |||
239 | #endif /* __ASSEMBLY__ */ | ||
240 | #endif /* __KERNEL__ */ | ||
241 | #endif /* __ASM_PROCFNS_H */ | ||
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h new file mode 100644 index 000000000000..b01d5e7e3d5a --- /dev/null +++ b/arch/arm/include/asm/processor.h | |||
@@ -0,0 +1,131 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/processor.h | ||
3 | * | ||
4 | * Copyright (C) 1995-1999 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_ARM_PROCESSOR_H | ||
12 | #define __ASM_ARM_PROCESSOR_H | ||
13 | |||
14 | /* | ||
15 | * Default implementation of macro that returns current | ||
16 | * instruction pointer ("program counter"). | ||
17 | */ | ||
18 | #define current_text_addr() ({ __label__ _l; _l: &&_l;}) | ||
19 | |||
20 | #ifdef __KERNEL__ | ||
21 | |||
22 | #include <asm/ptrace.h> | ||
23 | #include <asm/types.h> | ||
24 | |||
25 | #ifdef __KERNEL__ | ||
26 | #define STACK_TOP ((current->personality == PER_LINUX_32BIT) ? \ | ||
27 | TASK_SIZE : TASK_SIZE_26) | ||
28 | #define STACK_TOP_MAX TASK_SIZE | ||
29 | #endif | ||
30 | |||
31 | union debug_insn { | ||
32 | u32 arm; | ||
33 | u16 thumb; | ||
34 | }; | ||
35 | |||
36 | struct debug_entry { | ||
37 | u32 address; | ||
38 | union debug_insn insn; | ||
39 | }; | ||
40 | |||
41 | struct debug_info { | ||
42 | int nsaved; | ||
43 | struct debug_entry bp[2]; | ||
44 | }; | ||
45 | |||
46 | struct thread_struct { | ||
47 | /* fault info */ | ||
48 | unsigned long address; | ||
49 | unsigned long trap_no; | ||
50 | unsigned long error_code; | ||
51 | /* debugging */ | ||
52 | struct debug_info debug; | ||
53 | }; | ||
54 | |||
55 | #define INIT_THREAD { } | ||
56 | |||
57 | #ifdef CONFIG_MMU | ||
58 | #define nommu_start_thread(regs) do { } while (0) | ||
59 | #else | ||
60 | #define nommu_start_thread(regs) regs->ARM_r10 = current->mm->start_data | ||
61 | #endif | ||
62 | |||
63 | #define start_thread(regs,pc,sp) \ | ||
64 | ({ \ | ||
65 | unsigned long *stack = (unsigned long *)sp; \ | ||
66 | set_fs(USER_DS); \ | ||
67 | memzero(regs->uregs, sizeof(regs->uregs)); \ | ||
68 | if (current->personality & ADDR_LIMIT_32BIT) \ | ||
69 | regs->ARM_cpsr = USR_MODE; \ | ||
70 | else \ | ||
71 | regs->ARM_cpsr = USR26_MODE; \ | ||
72 | if (elf_hwcap & HWCAP_THUMB && pc & 1) \ | ||
73 | regs->ARM_cpsr |= PSR_T_BIT; \ | ||
74 | regs->ARM_pc = pc & ~1; /* pc */ \ | ||
75 | regs->ARM_sp = sp; /* sp */ \ | ||
76 | regs->ARM_r2 = stack[2]; /* r2 (envp) */ \ | ||
77 | regs->ARM_r1 = stack[1]; /* r1 (argv) */ \ | ||
78 | regs->ARM_r0 = stack[0]; /* r0 (argc) */ \ | ||
79 | nommu_start_thread(regs); \ | ||
80 | }) | ||
81 | |||
82 | /* Forward declaration, a strange C thing */ | ||
83 | struct task_struct; | ||
84 | |||
85 | /* Free all resources held by a thread. */ | ||
86 | extern void release_thread(struct task_struct *); | ||
87 | |||
88 | /* Prepare to copy thread state - unlazy all lazy status */ | ||
89 | #define prepare_to_copy(tsk) do { } while (0) | ||
90 | |||
91 | unsigned long get_wchan(struct task_struct *p); | ||
92 | |||
93 | #define cpu_relax() barrier() | ||
94 | |||
95 | /* | ||
96 | * Create a new kernel thread | ||
97 | */ | ||
98 | extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); | ||
99 | |||
100 | #define task_pt_regs(p) \ | ||
101 | ((struct pt_regs *)(THREAD_START_SP + task_stack_page(p)) - 1) | ||
102 | |||
103 | #define KSTK_EIP(tsk) task_pt_regs(tsk)->ARM_pc | ||
104 | #define KSTK_ESP(tsk) task_pt_regs(tsk)->ARM_sp | ||
105 | |||
106 | /* | ||
107 | * Prefetching support - only ARMv5. | ||
108 | */ | ||
109 | #if __LINUX_ARM_ARCH__ >= 5 | ||
110 | |||
111 | #define ARCH_HAS_PREFETCH | ||
112 | static inline void prefetch(const void *ptr) | ||
113 | { | ||
114 | __asm__ __volatile__( | ||
115 | "pld\t%0" | ||
116 | : | ||
117 | : "o" (*(char *)ptr) | ||
118 | : "cc"); | ||
119 | } | ||
120 | |||
121 | #define ARCH_HAS_PREFETCHW | ||
122 | #define prefetchw(ptr) prefetch(ptr) | ||
123 | |||
124 | #define ARCH_HAS_SPINLOCK_PREFETCH | ||
125 | #define spin_lock_prefetch(x) do { } while (0) | ||
126 | |||
127 | #endif | ||
128 | |||
129 | #endif | ||
130 | |||
131 | #endif /* __ASM_ARM_PROCESSOR_H */ | ||
diff --git a/arch/arm/include/asm/procinfo.h b/arch/arm/include/asm/procinfo.h new file mode 100644 index 000000000000..ca52e584ef74 --- /dev/null +++ b/arch/arm/include/asm/procinfo.h | |||
@@ -0,0 +1,49 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/procinfo.h | ||
3 | * | ||
4 | * Copyright (C) 1996-1999 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #ifndef __ASM_PROCINFO_H | ||
11 | #define __ASM_PROCINFO_H | ||
12 | |||
13 | #ifdef __KERNEL__ | ||
14 | |||
15 | struct cpu_tlb_fns; | ||
16 | struct cpu_user_fns; | ||
17 | struct cpu_cache_fns; | ||
18 | struct processor; | ||
19 | |||
20 | /* | ||
21 | * Note! struct processor is always defined if we're | ||
22 | * using MULTI_CPU, otherwise this entry is unused, | ||
23 | * but still exists. | ||
24 | * | ||
25 | * NOTE! The following structure is defined by assembly | ||
26 | * language, NOT C code. For more information, check: | ||
27 | * arch/arm/mm/proc-*.S and arch/arm/kernel/head.S | ||
28 | */ | ||
29 | struct proc_info_list { | ||
30 | unsigned int cpu_val; | ||
31 | unsigned int cpu_mask; | ||
32 | unsigned long __cpu_mm_mmu_flags; /* used by head.S */ | ||
33 | unsigned long __cpu_io_mmu_flags; /* used by head.S */ | ||
34 | unsigned long __cpu_flush; /* used by head.S */ | ||
35 | const char *arch_name; | ||
36 | const char *elf_name; | ||
37 | unsigned int elf_hwcap; | ||
38 | const char *cpu_name; | ||
39 | struct processor *proc; | ||
40 | struct cpu_tlb_fns *tlb; | ||
41 | struct cpu_user_fns *user; | ||
42 | struct cpu_cache_fns *cache; | ||
43 | }; | ||
44 | |||
45 | #else /* __KERNEL__ */ | ||
46 | #include <asm/elf.h> | ||
47 | #warning "Please include asm/elf.h instead" | ||
48 | #endif /* __KERNEL__ */ | ||
49 | #endif | ||
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h new file mode 100644 index 000000000000..b415c0e85458 --- /dev/null +++ b/arch/arm/include/asm/ptrace.h | |||
@@ -0,0 +1,162 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/ptrace.h | ||
3 | * | ||
4 | * Copyright (C) 1996-2003 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #ifndef __ASM_ARM_PTRACE_H | ||
11 | #define __ASM_ARM_PTRACE_H | ||
12 | |||
13 | #include <asm/hwcap.h> | ||
14 | |||
15 | #define PTRACE_GETREGS 12 | ||
16 | #define PTRACE_SETREGS 13 | ||
17 | #define PTRACE_GETFPREGS 14 | ||
18 | #define PTRACE_SETFPREGS 15 | ||
19 | /* PTRACE_ATTACH is 16 */ | ||
20 | /* PTRACE_DETACH is 17 */ | ||
21 | #define PTRACE_GETWMMXREGS 18 | ||
22 | #define PTRACE_SETWMMXREGS 19 | ||
23 | /* 20 is unused */ | ||
24 | #define PTRACE_OLDSETOPTIONS 21 | ||
25 | #define PTRACE_GET_THREAD_AREA 22 | ||
26 | #define PTRACE_SET_SYSCALL 23 | ||
27 | /* PTRACE_SYSCALL is 24 */ | ||
28 | #define PTRACE_GETCRUNCHREGS 25 | ||
29 | #define PTRACE_SETCRUNCHREGS 26 | ||
30 | |||
31 | /* | ||
32 | * PSR bits | ||
33 | */ | ||
34 | #define USR26_MODE 0x00000000 | ||
35 | #define FIQ26_MODE 0x00000001 | ||
36 | #define IRQ26_MODE 0x00000002 | ||
37 | #define SVC26_MODE 0x00000003 | ||
38 | #define USR_MODE 0x00000010 | ||
39 | #define FIQ_MODE 0x00000011 | ||
40 | #define IRQ_MODE 0x00000012 | ||
41 | #define SVC_MODE 0x00000013 | ||
42 | #define ABT_MODE 0x00000017 | ||
43 | #define UND_MODE 0x0000001b | ||
44 | #define SYSTEM_MODE 0x0000001f | ||
45 | #define MODE32_BIT 0x00000010 | ||
46 | #define MODE_MASK 0x0000001f | ||
47 | #define PSR_T_BIT 0x00000020 | ||
48 | #define PSR_F_BIT 0x00000040 | ||
49 | #define PSR_I_BIT 0x00000080 | ||
50 | #define PSR_A_BIT 0x00000100 | ||
51 | #define PSR_J_BIT 0x01000000 | ||
52 | #define PSR_Q_BIT 0x08000000 | ||
53 | #define PSR_V_BIT 0x10000000 | ||
54 | #define PSR_C_BIT 0x20000000 | ||
55 | #define PSR_Z_BIT 0x40000000 | ||
56 | #define PSR_N_BIT 0x80000000 | ||
57 | #define PCMASK 0 | ||
58 | |||
59 | /* | ||
60 | * Groups of PSR bits | ||
61 | */ | ||
62 | #define PSR_f 0xff000000 /* Flags */ | ||
63 | #define PSR_s 0x00ff0000 /* Status */ | ||
64 | #define PSR_x 0x0000ff00 /* Extension */ | ||
65 | #define PSR_c 0x000000ff /* Control */ | ||
66 | |||
67 | #ifndef __ASSEMBLY__ | ||
68 | |||
69 | /* | ||
70 | * This struct defines the way the registers are stored on the | ||
71 | * stack during a system call. Note that sizeof(struct pt_regs) | ||
72 | * has to be a multiple of 8. | ||
73 | */ | ||
74 | struct pt_regs { | ||
75 | long uregs[18]; | ||
76 | }; | ||
77 | |||
78 | #define ARM_cpsr uregs[16] | ||
79 | #define ARM_pc uregs[15] | ||
80 | #define ARM_lr uregs[14] | ||
81 | #define ARM_sp uregs[13] | ||
82 | #define ARM_ip uregs[12] | ||
83 | #define ARM_fp uregs[11] | ||
84 | #define ARM_r10 uregs[10] | ||
85 | #define ARM_r9 uregs[9] | ||
86 | #define ARM_r8 uregs[8] | ||
87 | #define ARM_r7 uregs[7] | ||
88 | #define ARM_r6 uregs[6] | ||
89 | #define ARM_r5 uregs[5] | ||
90 | #define ARM_r4 uregs[4] | ||
91 | #define ARM_r3 uregs[3] | ||
92 | #define ARM_r2 uregs[2] | ||
93 | #define ARM_r1 uregs[1] | ||
94 | #define ARM_r0 uregs[0] | ||
95 | #define ARM_ORIG_r0 uregs[17] | ||
96 | |||
97 | #ifdef __KERNEL__ | ||
98 | |||
99 | #define user_mode(regs) \ | ||
100 | (((regs)->ARM_cpsr & 0xf) == 0) | ||
101 | |||
102 | #ifdef CONFIG_ARM_THUMB | ||
103 | #define thumb_mode(regs) \ | ||
104 | (((regs)->ARM_cpsr & PSR_T_BIT)) | ||
105 | #else | ||
106 | #define thumb_mode(regs) (0) | ||
107 | #endif | ||
108 | |||
109 | #define isa_mode(regs) \ | ||
110 | ((((regs)->ARM_cpsr & PSR_J_BIT) >> 23) | \ | ||
111 | (((regs)->ARM_cpsr & PSR_T_BIT) >> 5)) | ||
112 | |||
113 | #define processor_mode(regs) \ | ||
114 | ((regs)->ARM_cpsr & MODE_MASK) | ||
115 | |||
116 | #define interrupts_enabled(regs) \ | ||
117 | (!((regs)->ARM_cpsr & PSR_I_BIT)) | ||
118 | |||
119 | #define fast_interrupts_enabled(regs) \ | ||
120 | (!((regs)->ARM_cpsr & PSR_F_BIT)) | ||
121 | |||
122 | /* Are the current registers suitable for user mode? | ||
123 | * (used to maintain security in signal handlers) | ||
124 | */ | ||
125 | static inline int valid_user_regs(struct pt_regs *regs) | ||
126 | { | ||
127 | if (user_mode(regs) && (regs->ARM_cpsr & PSR_I_BIT) == 0) { | ||
128 | regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT); | ||
129 | return 1; | ||
130 | } | ||
131 | |||
132 | /* | ||
133 | * Force CPSR to something logical... | ||
134 | */ | ||
135 | regs->ARM_cpsr &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | PSR_T_BIT | MODE32_BIT; | ||
136 | if (!(elf_hwcap & HWCAP_26BIT)) | ||
137 | regs->ARM_cpsr |= USR_MODE; | ||
138 | |||
139 | return 0; | ||
140 | } | ||
141 | |||
142 | #define pc_pointer(v) \ | ||
143 | ((v) & ~PCMASK) | ||
144 | |||
145 | #define instruction_pointer(regs) \ | ||
146 | (pc_pointer((regs)->ARM_pc)) | ||
147 | |||
148 | #ifdef CONFIG_SMP | ||
149 | extern unsigned long profile_pc(struct pt_regs *regs); | ||
150 | #else | ||
151 | #define profile_pc(regs) instruction_pointer(regs) | ||
152 | #endif | ||
153 | |||
154 | #define predicate(x) ((x) & 0xf0000000) | ||
155 | #define PREDICATE_ALWAYS 0xe0000000 | ||
156 | |||
157 | #endif /* __KERNEL__ */ | ||
158 | |||
159 | #endif /* __ASSEMBLY__ */ | ||
160 | |||
161 | #endif | ||
162 | |||
diff --git a/arch/arm/include/asm/resource.h b/arch/arm/include/asm/resource.h new file mode 100644 index 000000000000..734b581b5b6a --- /dev/null +++ b/arch/arm/include/asm/resource.h | |||
@@ -0,0 +1,6 @@ | |||
1 | #ifndef _ARM_RESOURCE_H | ||
2 | #define _ARM_RESOURCE_H | ||
3 | |||
4 | #include <asm-generic/resource.h> | ||
5 | |||
6 | #endif | ||
diff --git a/arch/arm/include/asm/scatterlist.h b/arch/arm/include/asm/scatterlist.h new file mode 100644 index 000000000000..ca0a37d03400 --- /dev/null +++ b/arch/arm/include/asm/scatterlist.h | |||
@@ -0,0 +1,27 @@ | |||
1 | #ifndef _ASMARM_SCATTERLIST_H | ||
2 | #define _ASMARM_SCATTERLIST_H | ||
3 | |||
4 | #include <asm/memory.h> | ||
5 | #include <asm/types.h> | ||
6 | |||
7 | struct scatterlist { | ||
8 | #ifdef CONFIG_DEBUG_SG | ||
9 | unsigned long sg_magic; | ||
10 | #endif | ||
11 | unsigned long page_link; | ||
12 | unsigned int offset; /* buffer offset */ | ||
13 | dma_addr_t dma_address; /* dma address */ | ||
14 | unsigned int length; /* length */ | ||
15 | }; | ||
16 | |||
17 | /* | ||
18 | * These macros should be used after a pci_map_sg call has been done | ||
19 | * to get bus addresses of each of the SG entries and their lengths. | ||
20 | * You should only work with the number of sg entries pci_map_sg | ||
21 | * returns, or alternatively stop on the first sg_dma_len(sg) which | ||
22 | * is 0. | ||
23 | */ | ||
24 | #define sg_dma_address(sg) ((sg)->dma_address) | ||
25 | #define sg_dma_len(sg) ((sg)->length) | ||
26 | |||
27 | #endif /* _ASMARM_SCATTERLIST_H */ | ||
diff --git a/arch/arm/include/asm/sections.h b/arch/arm/include/asm/sections.h new file mode 100644 index 000000000000..2b8c5160388f --- /dev/null +++ b/arch/arm/include/asm/sections.h | |||
@@ -0,0 +1 @@ | |||
#include <asm-generic/sections.h> | |||
diff --git a/arch/arm/include/asm/segment.h b/arch/arm/include/asm/segment.h new file mode 100644 index 000000000000..9e24c21f6304 --- /dev/null +++ b/arch/arm/include/asm/segment.h | |||
@@ -0,0 +1,11 @@ | |||
1 | #ifndef __ASM_ARM_SEGMENT_H | ||
2 | #define __ASM_ARM_SEGMENT_H | ||
3 | |||
4 | #define __KERNEL_CS 0x0 | ||
5 | #define __KERNEL_DS 0x0 | ||
6 | |||
7 | #define __USER_CS 0x1 | ||
8 | #define __USER_DS 0x1 | ||
9 | |||
10 | #endif /* __ASM_ARM_SEGMENT_H */ | ||
11 | |||
diff --git a/arch/arm/include/asm/sembuf.h b/arch/arm/include/asm/sembuf.h new file mode 100644 index 000000000000..1c0283954289 --- /dev/null +++ b/arch/arm/include/asm/sembuf.h | |||
@@ -0,0 +1,25 @@ | |||
1 | #ifndef _ASMARM_SEMBUF_H | ||
2 | #define _ASMARM_SEMBUF_H | ||
3 | |||
4 | /* | ||
5 | * The semid64_ds structure for arm architecture. | ||
6 | * Note extra padding because this structure is passed back and forth | ||
7 | * between kernel and user space. | ||
8 | * | ||
9 | * Pad space is left for: | ||
10 | * - 64-bit time_t to solve y2038 problem | ||
11 | * - 2 miscellaneous 32-bit values | ||
12 | */ | ||
13 | |||
14 | struct semid64_ds { | ||
15 | struct ipc64_perm sem_perm; /* permissions .. see ipc.h */ | ||
16 | __kernel_time_t sem_otime; /* last semop time */ | ||
17 | unsigned long __unused1; | ||
18 | __kernel_time_t sem_ctime; /* last change time */ | ||
19 | unsigned long __unused2; | ||
20 | unsigned long sem_nsems; /* no. of semaphores in array */ | ||
21 | unsigned long __unused3; | ||
22 | unsigned long __unused4; | ||
23 | }; | ||
24 | |||
25 | #endif /* _ASMARM_SEMBUF_H */ | ||
diff --git a/arch/arm/include/asm/serial.h b/arch/arm/include/asm/serial.h new file mode 100644 index 000000000000..ebb049091e26 --- /dev/null +++ b/arch/arm/include/asm/serial.h | |||
@@ -0,0 +1,19 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/serial.h | ||
3 | * | ||
4 | * Copyright (C) 1996 Russell King. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * Changelog: | ||
11 | * 15-10-1996 RMK Created | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_SERIAL_H | ||
15 | #define __ASM_SERIAL_H | ||
16 | |||
17 | #define BASE_BAUD (1843200 / 16) | ||
18 | |||
19 | #endif | ||
diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h new file mode 100644 index 000000000000..7bbf105463f1 --- /dev/null +++ b/arch/arm/include/asm/setup.h | |||
@@ -0,0 +1,226 @@ | |||
1 | /* | ||
2 | * linux/include/asm/setup.h | ||
3 | * | ||
4 | * Copyright (C) 1997-1999 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * Structure passed to kernel to tell it about the | ||
11 | * hardware it's running on. See Documentation/arm/Setup | ||
12 | * for more info. | ||
13 | */ | ||
14 | #ifndef __ASMARM_SETUP_H | ||
15 | #define __ASMARM_SETUP_H | ||
16 | |||
17 | #include <asm/types.h> | ||
18 | |||
19 | #define COMMAND_LINE_SIZE 1024 | ||
20 | |||
21 | /* The list ends with an ATAG_NONE node. */ | ||
22 | #define ATAG_NONE 0x00000000 | ||
23 | |||
24 | struct tag_header { | ||
25 | __u32 size; | ||
26 | __u32 tag; | ||
27 | }; | ||
28 | |||
29 | /* The list must start with an ATAG_CORE node */ | ||
30 | #define ATAG_CORE 0x54410001 | ||
31 | |||
32 | struct tag_core { | ||
33 | __u32 flags; /* bit 0 = read-only */ | ||
34 | __u32 pagesize; | ||
35 | __u32 rootdev; | ||
36 | }; | ||
37 | |||
38 | /* it is allowed to have multiple ATAG_MEM nodes */ | ||
39 | #define ATAG_MEM 0x54410002 | ||
40 | |||
41 | struct tag_mem32 { | ||
42 | __u32 size; | ||
43 | __u32 start; /* physical start address */ | ||
44 | }; | ||
45 | |||
46 | /* VGA text type displays */ | ||
47 | #define ATAG_VIDEOTEXT 0x54410003 | ||
48 | |||
49 | struct tag_videotext { | ||
50 | __u8 x; | ||
51 | __u8 y; | ||
52 | __u16 video_page; | ||
53 | __u8 video_mode; | ||
54 | __u8 video_cols; | ||
55 | __u16 video_ega_bx; | ||
56 | __u8 video_lines; | ||
57 | __u8 video_isvga; | ||
58 | __u16 video_points; | ||
59 | }; | ||
60 | |||
61 | /* describes how the ramdisk will be used in kernel */ | ||
62 | #define ATAG_RAMDISK 0x54410004 | ||
63 | |||
64 | struct tag_ramdisk { | ||
65 | __u32 flags; /* bit 0 = load, bit 1 = prompt */ | ||
66 | __u32 size; /* decompressed ramdisk size in _kilo_ bytes */ | ||
67 | __u32 start; /* starting block of floppy-based RAM disk image */ | ||
68 | }; | ||
69 | |||
70 | /* describes where the compressed ramdisk image lives (virtual address) */ | ||
71 | /* | ||
72 | * this one accidentally used virtual addresses - as such, | ||
73 | * it's deprecated. | ||
74 | */ | ||
75 | #define ATAG_INITRD 0x54410005 | ||
76 | |||
77 | /* describes where the compressed ramdisk image lives (physical address) */ | ||
78 | #define ATAG_INITRD2 0x54420005 | ||
79 | |||
80 | struct tag_initrd { | ||
81 | __u32 start; /* physical start address */ | ||
82 | __u32 size; /* size of compressed ramdisk image in bytes */ | ||
83 | }; | ||
84 | |||
85 | /* board serial number. "64 bits should be enough for everybody" */ | ||
86 | #define ATAG_SERIAL 0x54410006 | ||
87 | |||
88 | struct tag_serialnr { | ||
89 | __u32 low; | ||
90 | __u32 high; | ||
91 | }; | ||
92 | |||
93 | /* board revision */ | ||
94 | #define ATAG_REVISION 0x54410007 | ||
95 | |||
96 | struct tag_revision { | ||
97 | __u32 rev; | ||
98 | }; | ||
99 | |||
100 | /* initial values for vesafb-type framebuffers. see struct screen_info | ||
101 | * in include/linux/tty.h | ||
102 | */ | ||
103 | #define ATAG_VIDEOLFB 0x54410008 | ||
104 | |||
105 | struct tag_videolfb { | ||
106 | __u16 lfb_width; | ||
107 | __u16 lfb_height; | ||
108 | __u16 lfb_depth; | ||
109 | __u16 lfb_linelength; | ||
110 | __u32 lfb_base; | ||
111 | __u32 lfb_size; | ||
112 | __u8 red_size; | ||
113 | __u8 red_pos; | ||
114 | __u8 green_size; | ||
115 | __u8 green_pos; | ||
116 | __u8 blue_size; | ||
117 | __u8 blue_pos; | ||
118 | __u8 rsvd_size; | ||
119 | __u8 rsvd_pos; | ||
120 | }; | ||
121 | |||
122 | /* command line: \0 terminated string */ | ||
123 | #define ATAG_CMDLINE 0x54410009 | ||
124 | |||
125 | struct tag_cmdline { | ||
126 | char cmdline[1]; /* this is the minimum size */ | ||
127 | }; | ||
128 | |||
129 | /* acorn RiscPC specific information */ | ||
130 | #define ATAG_ACORN 0x41000101 | ||
131 | |||
132 | struct tag_acorn { | ||
133 | __u32 memc_control_reg; | ||
134 | __u32 vram_pages; | ||
135 | __u8 sounddefault; | ||
136 | __u8 adfsdrives; | ||
137 | }; | ||
138 | |||
139 | /* footbridge memory clock, see arch/arm/mach-footbridge/arch.c */ | ||
140 | #define ATAG_MEMCLK 0x41000402 | ||
141 | |||
142 | struct tag_memclk { | ||
143 | __u32 fmemclk; | ||
144 | }; | ||
145 | |||
146 | struct tag { | ||
147 | struct tag_header hdr; | ||
148 | union { | ||
149 | struct tag_core core; | ||
150 | struct tag_mem32 mem; | ||
151 | struct tag_videotext videotext; | ||
152 | struct tag_ramdisk ramdisk; | ||
153 | struct tag_initrd initrd; | ||
154 | struct tag_serialnr serialnr; | ||
155 | struct tag_revision revision; | ||
156 | struct tag_videolfb videolfb; | ||
157 | struct tag_cmdline cmdline; | ||
158 | |||
159 | /* | ||
160 | * Acorn specific | ||
161 | */ | ||
162 | struct tag_acorn acorn; | ||
163 | |||
164 | /* | ||
165 | * DC21285 specific | ||
166 | */ | ||
167 | struct tag_memclk memclk; | ||
168 | } u; | ||
169 | }; | ||
170 | |||
171 | struct tagtable { | ||
172 | __u32 tag; | ||
173 | int (*parse)(const struct tag *); | ||
174 | }; | ||
175 | |||
176 | #define tag_member_present(tag,member) \ | ||
177 | ((unsigned long)(&((struct tag *)0L)->member + 1) \ | ||
178 | <= (tag)->hdr.size * 4) | ||
179 | |||
180 | #define tag_next(t) ((struct tag *)((__u32 *)(t) + (t)->hdr.size)) | ||
181 | #define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2) | ||
182 | |||
183 | #define for_each_tag(t,base) \ | ||
184 | for (t = base; t->hdr.size; t = tag_next(t)) | ||
185 | |||
186 | #ifdef __KERNEL__ | ||
187 | |||
188 | #define __tag __used __attribute__((__section__(".taglist.init"))) | ||
189 | #define __tagtable(tag, fn) \ | ||
190 | static struct tagtable __tagtable_##fn __tag = { tag, fn } | ||
191 | |||
192 | /* | ||
193 | * Memory map description | ||
194 | */ | ||
195 | #ifdef CONFIG_ARCH_LH7A40X | ||
196 | # define NR_BANKS 16 | ||
197 | #else | ||
198 | # define NR_BANKS 8 | ||
199 | #endif | ||
200 | |||
201 | struct membank { | ||
202 | unsigned long start; | ||
203 | unsigned long size; | ||
204 | int node; | ||
205 | }; | ||
206 | |||
207 | struct meminfo { | ||
208 | int nr_banks; | ||
209 | struct membank bank[NR_BANKS]; | ||
210 | }; | ||
211 | |||
212 | /* | ||
213 | * Early command line parameters. | ||
214 | */ | ||
215 | struct early_params { | ||
216 | const char *arg; | ||
217 | void (*fn)(char **p); | ||
218 | }; | ||
219 | |||
220 | #define __early_param(name,fn) \ | ||
221 | static struct early_params __early_##fn __used \ | ||
222 | __attribute__((__section__(".early_param.init"))) = { name, fn } | ||
223 | |||
224 | #endif /* __KERNEL__ */ | ||
225 | |||
226 | #endif | ||
diff --git a/arch/arm/include/asm/shmbuf.h b/arch/arm/include/asm/shmbuf.h new file mode 100644 index 000000000000..2e5c67ba1c97 --- /dev/null +++ b/arch/arm/include/asm/shmbuf.h | |||
@@ -0,0 +1,42 @@ | |||
1 | #ifndef _ASMARM_SHMBUF_H | ||
2 | #define _ASMARM_SHMBUF_H | ||
3 | |||
4 | /* | ||
5 | * The shmid64_ds structure for arm architecture. | ||
6 | * Note extra padding because this structure is passed back and forth | ||
7 | * between kernel and user space. | ||
8 | * | ||
9 | * Pad space is left for: | ||
10 | * - 64-bit time_t to solve y2038 problem | ||
11 | * - 2 miscellaneous 32-bit values | ||
12 | */ | ||
13 | |||
14 | struct shmid64_ds { | ||
15 | struct ipc64_perm shm_perm; /* operation perms */ | ||
16 | size_t shm_segsz; /* size of segment (bytes) */ | ||
17 | __kernel_time_t shm_atime; /* last attach time */ | ||
18 | unsigned long __unused1; | ||
19 | __kernel_time_t shm_dtime; /* last detach time */ | ||
20 | unsigned long __unused2; | ||
21 | __kernel_time_t shm_ctime; /* last change time */ | ||
22 | unsigned long __unused3; | ||
23 | __kernel_pid_t shm_cpid; /* pid of creator */ | ||
24 | __kernel_pid_t shm_lpid; /* pid of last operator */ | ||
25 | unsigned long shm_nattch; /* no. of current attaches */ | ||
26 | unsigned long __unused4; | ||
27 | unsigned long __unused5; | ||
28 | }; | ||
29 | |||
30 | struct shminfo64 { | ||
31 | unsigned long shmmax; | ||
32 | unsigned long shmmin; | ||
33 | unsigned long shmmni; | ||
34 | unsigned long shmseg; | ||
35 | unsigned long shmall; | ||
36 | unsigned long __unused1; | ||
37 | unsigned long __unused2; | ||
38 | unsigned long __unused3; | ||
39 | unsigned long __unused4; | ||
40 | }; | ||
41 | |||
42 | #endif /* _ASMARM_SHMBUF_H */ | ||
diff --git a/arch/arm/include/asm/shmparam.h b/arch/arm/include/asm/shmparam.h new file mode 100644 index 000000000000..a5223b3a9bf9 --- /dev/null +++ b/arch/arm/include/asm/shmparam.h | |||
@@ -0,0 +1,16 @@ | |||
1 | #ifndef _ASMARM_SHMPARAM_H | ||
2 | #define _ASMARM_SHMPARAM_H | ||
3 | |||
4 | /* | ||
5 | * This should be the size of the virtually indexed cache/ways, | ||
6 | * or page size, whichever is greater since the cache aliases | ||
7 | * every size/ways bytes. | ||
8 | */ | ||
9 | #define SHMLBA (4 * PAGE_SIZE) /* attach addr a multiple of this */ | ||
10 | |||
11 | /* | ||
12 | * Enforce SHMLBA in shmat | ||
13 | */ | ||
14 | #define __ARCH_FORCE_SHMLBA | ||
15 | |||
16 | #endif /* _ASMARM_SHMPARAM_H */ | ||
diff --git a/arch/arm/include/asm/sigcontext.h b/arch/arm/include/asm/sigcontext.h new file mode 100644 index 000000000000..fc0b80b6a6fc --- /dev/null +++ b/arch/arm/include/asm/sigcontext.h | |||
@@ -0,0 +1,34 @@ | |||
1 | #ifndef _ASMARM_SIGCONTEXT_H | ||
2 | #define _ASMARM_SIGCONTEXT_H | ||
3 | |||
4 | /* | ||
5 | * Signal context structure - contains all info to do with the state | ||
6 | * before the signal handler was invoked. Note: only add new entries | ||
7 | * to the end of the structure. | ||
8 | */ | ||
9 | struct sigcontext { | ||
10 | unsigned long trap_no; | ||
11 | unsigned long error_code; | ||
12 | unsigned long oldmask; | ||
13 | unsigned long arm_r0; | ||
14 | unsigned long arm_r1; | ||
15 | unsigned long arm_r2; | ||
16 | unsigned long arm_r3; | ||
17 | unsigned long arm_r4; | ||
18 | unsigned long arm_r5; | ||
19 | unsigned long arm_r6; | ||
20 | unsigned long arm_r7; | ||
21 | unsigned long arm_r8; | ||
22 | unsigned long arm_r9; | ||
23 | unsigned long arm_r10; | ||
24 | unsigned long arm_fp; | ||
25 | unsigned long arm_ip; | ||
26 | unsigned long arm_sp; | ||
27 | unsigned long arm_lr; | ||
28 | unsigned long arm_pc; | ||
29 | unsigned long arm_cpsr; | ||
30 | unsigned long fault_address; | ||
31 | }; | ||
32 | |||
33 | |||
34 | #endif | ||
diff --git a/arch/arm/include/asm/siginfo.h b/arch/arm/include/asm/siginfo.h new file mode 100644 index 000000000000..5e21852e6039 --- /dev/null +++ b/arch/arm/include/asm/siginfo.h | |||
@@ -0,0 +1,6 @@ | |||
1 | #ifndef _ASMARM_SIGINFO_H | ||
2 | #define _ASMARM_SIGINFO_H | ||
3 | |||
4 | #include <asm-generic/siginfo.h> | ||
5 | |||
6 | #endif | ||
diff --git a/arch/arm/include/asm/signal.h b/arch/arm/include/asm/signal.h new file mode 100644 index 000000000000..d0fb487aba4f --- /dev/null +++ b/arch/arm/include/asm/signal.h | |||
@@ -0,0 +1,164 @@ | |||
1 | #ifndef _ASMARM_SIGNAL_H | ||
2 | #define _ASMARM_SIGNAL_H | ||
3 | |||
4 | #include <linux/types.h> | ||
5 | |||
6 | /* Avoid too many header ordering problems. */ | ||
7 | struct siginfo; | ||
8 | |||
9 | #ifdef __KERNEL__ | ||
10 | /* Most things should be clean enough to redefine this at will, if care | ||
11 | is taken to make libc match. */ | ||
12 | |||
13 | #define _NSIG 64 | ||
14 | #define _NSIG_BPW 32 | ||
15 | #define _NSIG_WORDS (_NSIG / _NSIG_BPW) | ||
16 | |||
17 | typedef unsigned long old_sigset_t; /* at least 32 bits */ | ||
18 | |||
19 | typedef struct { | ||
20 | unsigned long sig[_NSIG_WORDS]; | ||
21 | } sigset_t; | ||
22 | |||
23 | #else | ||
24 | /* Here we must cater to libcs that poke about in kernel headers. */ | ||
25 | |||
26 | #define NSIG 32 | ||
27 | typedef unsigned long sigset_t; | ||
28 | |||
29 | #endif /* __KERNEL__ */ | ||
30 | |||
31 | #define SIGHUP 1 | ||
32 | #define SIGINT 2 | ||
33 | #define SIGQUIT 3 | ||
34 | #define SIGILL 4 | ||
35 | #define SIGTRAP 5 | ||
36 | #define SIGABRT 6 | ||
37 | #define SIGIOT 6 | ||
38 | #define SIGBUS 7 | ||
39 | #define SIGFPE 8 | ||
40 | #define SIGKILL 9 | ||
41 | #define SIGUSR1 10 | ||
42 | #define SIGSEGV 11 | ||
43 | #define SIGUSR2 12 | ||
44 | #define SIGPIPE 13 | ||
45 | #define SIGALRM 14 | ||
46 | #define SIGTERM 15 | ||
47 | #define SIGSTKFLT 16 | ||
48 | #define SIGCHLD 17 | ||
49 | #define SIGCONT 18 | ||
50 | #define SIGSTOP 19 | ||
51 | #define SIGTSTP 20 | ||
52 | #define SIGTTIN 21 | ||
53 | #define SIGTTOU 22 | ||
54 | #define SIGURG 23 | ||
55 | #define SIGXCPU 24 | ||
56 | #define SIGXFSZ 25 | ||
57 | #define SIGVTALRM 26 | ||
58 | #define SIGPROF 27 | ||
59 | #define SIGWINCH 28 | ||
60 | #define SIGIO 29 | ||
61 | #define SIGPOLL SIGIO | ||
62 | /* | ||
63 | #define SIGLOST 29 | ||
64 | */ | ||
65 | #define SIGPWR 30 | ||
66 | #define SIGSYS 31 | ||
67 | #define SIGUNUSED 31 | ||
68 | |||
69 | /* These should not be considered constants from userland. */ | ||
70 | #define SIGRTMIN 32 | ||
71 | #define SIGRTMAX _NSIG | ||
72 | |||
73 | #define SIGSWI 32 | ||
74 | |||
75 | /* | ||
76 | * SA_FLAGS values: | ||
77 | * | ||
78 | * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. | ||
79 | * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. | ||
80 | * SA_SIGINFO deliver the signal with SIGINFO structs | ||
81 | * SA_THIRTYTWO delivers the signal in 32-bit mode, even if the task | ||
82 | * is running in 26-bit. | ||
83 | * SA_ONSTACK allows alternate signal stacks (see sigaltstack(2)). | ||
84 | * SA_RESTART flag to get restarting signals (which were the default long ago) | ||
85 | * SA_NODEFER prevents the current signal from being masked in the handler. | ||
86 | * SA_RESETHAND clears the handler when the signal is delivered. | ||
87 | * | ||
88 | * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single | ||
89 | * Unix names RESETHAND and NODEFER respectively. | ||
90 | */ | ||
91 | #define SA_NOCLDSTOP 0x00000001 | ||
92 | #define SA_NOCLDWAIT 0x00000002 | ||
93 | #define SA_SIGINFO 0x00000004 | ||
94 | #define SA_THIRTYTWO 0x02000000 | ||
95 | #define SA_RESTORER 0x04000000 | ||
96 | #define SA_ONSTACK 0x08000000 | ||
97 | #define SA_RESTART 0x10000000 | ||
98 | #define SA_NODEFER 0x40000000 | ||
99 | #define SA_RESETHAND 0x80000000 | ||
100 | |||
101 | #define SA_NOMASK SA_NODEFER | ||
102 | #define SA_ONESHOT SA_RESETHAND | ||
103 | |||
104 | |||
105 | /* | ||
106 | * sigaltstack controls | ||
107 | */ | ||
108 | #define SS_ONSTACK 1 | ||
109 | #define SS_DISABLE 2 | ||
110 | |||
111 | #define MINSIGSTKSZ 2048 | ||
112 | #define SIGSTKSZ 8192 | ||
113 | |||
114 | #include <asm-generic/signal.h> | ||
115 | |||
116 | #ifdef __KERNEL__ | ||
117 | struct old_sigaction { | ||
118 | __sighandler_t sa_handler; | ||
119 | old_sigset_t sa_mask; | ||
120 | unsigned long sa_flags; | ||
121 | __sigrestore_t sa_restorer; | ||
122 | }; | ||
123 | |||
124 | struct sigaction { | ||
125 | __sighandler_t sa_handler; | ||
126 | unsigned long sa_flags; | ||
127 | __sigrestore_t sa_restorer; | ||
128 | sigset_t sa_mask; /* mask last for extensibility */ | ||
129 | }; | ||
130 | |||
131 | struct k_sigaction { | ||
132 | struct sigaction sa; | ||
133 | }; | ||
134 | |||
135 | #else | ||
136 | /* Here we must cater to libcs that poke about in kernel headers. */ | ||
137 | |||
138 | struct sigaction { | ||
139 | union { | ||
140 | __sighandler_t _sa_handler; | ||
141 | void (*_sa_sigaction)(int, struct siginfo *, void *); | ||
142 | } _u; | ||
143 | sigset_t sa_mask; | ||
144 | unsigned long sa_flags; | ||
145 | void (*sa_restorer)(void); | ||
146 | }; | ||
147 | |||
148 | #define sa_handler _u._sa_handler | ||
149 | #define sa_sigaction _u._sa_sigaction | ||
150 | |||
151 | #endif /* __KERNEL__ */ | ||
152 | |||
153 | typedef struct sigaltstack { | ||
154 | void __user *ss_sp; | ||
155 | int ss_flags; | ||
156 | size_t ss_size; | ||
157 | } stack_t; | ||
158 | |||
159 | #ifdef __KERNEL__ | ||
160 | #include <asm/sigcontext.h> | ||
161 | #define ptrace_signal_deliver(regs, cookie) do { } while (0) | ||
162 | #endif | ||
163 | |||
164 | #endif | ||
diff --git a/arch/arm/include/asm/sizes.h b/arch/arm/include/asm/sizes.h new file mode 100644 index 000000000000..503843db1565 --- /dev/null +++ b/arch/arm/include/asm/sizes.h | |||
@@ -0,0 +1,56 @@ | |||
1 | /* | ||
2 | * This program is free software; you can redistribute it and/or modify | ||
3 | * it under the terms of the GNU General Public License as published by | ||
4 | * the Free Software Foundation; either version 2 of the License, or | ||
5 | * (at your option) any later version. | ||
6 | * | ||
7 | * This program is distributed in the hope that it will be useful, | ||
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
10 | * GNU General Public License for more details. | ||
11 | * | ||
12 | * You should have received a copy of the GNU General Public License | ||
13 | * along with this program; if not, write to the Free Software | ||
14 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
15 | */ | ||
16 | /* DO NOT EDIT!! - this file automatically generated | ||
17 | * from .s file by awk -f s2h.awk | ||
18 | */ | ||
19 | /* Size definitions | ||
20 | * Copyright (C) ARM Limited 1998. All rights reserved. | ||
21 | */ | ||
22 | |||
23 | #ifndef __sizes_h | ||
24 | #define __sizes_h 1 | ||
25 | |||
26 | /* handy sizes */ | ||
27 | #define SZ_16 0x00000010 | ||
28 | #define SZ_256 0x00000100 | ||
29 | #define SZ_512 0x00000200 | ||
30 | |||
31 | #define SZ_1K 0x00000400 | ||
32 | #define SZ_4K 0x00001000 | ||
33 | #define SZ_8K 0x00002000 | ||
34 | #define SZ_16K 0x00004000 | ||
35 | #define SZ_64K 0x00010000 | ||
36 | #define SZ_128K 0x00020000 | ||
37 | #define SZ_256K 0x00040000 | ||
38 | #define SZ_512K 0x00080000 | ||
39 | |||
40 | #define SZ_1M 0x00100000 | ||
41 | #define SZ_2M 0x00200000 | ||
42 | #define SZ_4M 0x00400000 | ||
43 | #define SZ_8M 0x00800000 | ||
44 | #define SZ_16M 0x01000000 | ||
45 | #define SZ_32M 0x02000000 | ||
46 | #define SZ_64M 0x04000000 | ||
47 | #define SZ_128M 0x08000000 | ||
48 | #define SZ_256M 0x10000000 | ||
49 | #define SZ_512M 0x20000000 | ||
50 | |||
51 | #define SZ_1G 0x40000000 | ||
52 | #define SZ_2G 0x80000000 | ||
53 | |||
54 | #endif | ||
55 | |||
56 | /* END */ | ||
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h new file mode 100644 index 000000000000..cc12a525a06a --- /dev/null +++ b/arch/arm/include/asm/smp.h | |||
@@ -0,0 +1,147 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/smp.h | ||
3 | * | ||
4 | * Copyright (C) 2004-2005 ARM Ltd. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #ifndef __ASM_ARM_SMP_H | ||
11 | #define __ASM_ARM_SMP_H | ||
12 | |||
13 | #include <linux/threads.h> | ||
14 | #include <linux/cpumask.h> | ||
15 | #include <linux/thread_info.h> | ||
16 | |||
17 | #include <asm/arch/smp.h> | ||
18 | |||
19 | #ifndef CONFIG_SMP | ||
20 | # error "<asm/smp.h> included in non-SMP build" | ||
21 | #endif | ||
22 | |||
23 | #define raw_smp_processor_id() (current_thread_info()->cpu) | ||
24 | |||
25 | /* | ||
26 | * at the moment, there's not a big penalty for changing CPUs | ||
27 | * (the >big< penalty is running SMP in the first place) | ||
28 | */ | ||
29 | #define PROC_CHANGE_PENALTY 15 | ||
30 | |||
31 | struct seq_file; | ||
32 | |||
33 | /* | ||
34 | * generate IPI list text | ||
35 | */ | ||
36 | extern void show_ipi_list(struct seq_file *p); | ||
37 | |||
38 | /* | ||
39 | * Called from assembly code, this handles an IPI. | ||
40 | */ | ||
41 | asmlinkage void do_IPI(struct pt_regs *regs); | ||
42 | |||
43 | /* | ||
44 | * Setup the SMP cpu_possible_map | ||
45 | */ | ||
46 | extern void smp_init_cpus(void); | ||
47 | |||
48 | /* | ||
49 | * Move global data into per-processor storage. | ||
50 | */ | ||
51 | extern void smp_store_cpu_info(unsigned int cpuid); | ||
52 | |||
53 | /* | ||
54 | * Raise an IPI cross call on CPUs in callmap. | ||
55 | */ | ||
56 | extern void smp_cross_call(cpumask_t callmap); | ||
57 | |||
58 | /* | ||
59 | * Broadcast a timer interrupt to the other CPUs. | ||
60 | */ | ||
61 | extern void smp_send_timer(void); | ||
62 | |||
63 | /* | ||
64 | * Broadcast a clock event to other CPUs. | ||
65 | */ | ||
66 | extern void smp_timer_broadcast(cpumask_t mask); | ||
67 | |||
68 | /* | ||
69 | * Boot a secondary CPU, and assign it the specified idle task. | ||
70 | * This also gives us the initial stack to use for this CPU. | ||
71 | */ | ||
72 | extern int boot_secondary(unsigned int cpu, struct task_struct *); | ||
73 | |||
74 | /* | ||
75 | * Called from platform specific assembly code, this is the | ||
76 | * secondary CPU entry point. | ||
77 | */ | ||
78 | asmlinkage void secondary_start_kernel(void); | ||
79 | |||
80 | /* | ||
81 | * Perform platform specific initialisation of the specified CPU. | ||
82 | */ | ||
83 | extern void platform_secondary_init(unsigned int cpu); | ||
84 | |||
85 | /* | ||
86 | * Initial data for bringing up a secondary CPU. | ||
87 | */ | ||
88 | struct secondary_data { | ||
89 | unsigned long pgdir; | ||
90 | void *stack; | ||
91 | }; | ||
92 | extern struct secondary_data secondary_data; | ||
93 | |||
94 | extern int __cpu_disable(void); | ||
95 | extern int mach_cpu_disable(unsigned int cpu); | ||
96 | |||
97 | extern void __cpu_die(unsigned int cpu); | ||
98 | extern void cpu_die(void); | ||
99 | |||
100 | extern void platform_cpu_die(unsigned int cpu); | ||
101 | extern int platform_cpu_kill(unsigned int cpu); | ||
102 | extern void platform_cpu_enable(unsigned int cpu); | ||
103 | |||
104 | extern void arch_send_call_function_single_ipi(int cpu); | ||
105 | extern void arch_send_call_function_ipi(cpumask_t mask); | ||
106 | |||
107 | /* | ||
108 | * Local timer interrupt handling function (can be IPI'ed). | ||
109 | */ | ||
110 | extern void local_timer_interrupt(void); | ||
111 | |||
112 | #ifdef CONFIG_LOCAL_TIMERS | ||
113 | |||
114 | /* | ||
115 | * Stop a local timer interrupt. | ||
116 | */ | ||
117 | extern void local_timer_stop(unsigned int cpu); | ||
118 | |||
119 | /* | ||
120 | * Platform provides this to acknowledge a local timer IRQ | ||
121 | */ | ||
122 | extern int local_timer_ack(void); | ||
123 | |||
124 | #else | ||
125 | |||
126 | static inline void local_timer_stop(unsigned int cpu) | ||
127 | { | ||
128 | } | ||
129 | |||
130 | #endif | ||
131 | |||
132 | /* | ||
133 | * Setup a local timer interrupt for a CPU. | ||
134 | */ | ||
135 | extern void local_timer_setup(unsigned int cpu); | ||
136 | |||
137 | /* | ||
138 | * show local interrupt info | ||
139 | */ | ||
140 | extern void show_local_irqs(struct seq_file *); | ||
141 | |||
142 | /* | ||
143 | * Called from assembly, this is the local timer IRQ handler | ||
144 | */ | ||
145 | asmlinkage void do_local_timer(struct pt_regs *); | ||
146 | |||
147 | #endif /* ifndef __ASM_ARM_SMP_H */ | ||
diff --git a/arch/arm/include/asm/socket.h b/arch/arm/include/asm/socket.h new file mode 100644 index 000000000000..6817be9573a6 --- /dev/null +++ b/arch/arm/include/asm/socket.h | |||
@@ -0,0 +1,57 @@ | |||
1 | #ifndef _ASMARM_SOCKET_H | ||
2 | #define _ASMARM_SOCKET_H | ||
3 | |||
4 | #include <asm/sockios.h> | ||
5 | |||
6 | /* For setsockopt(2) */ | ||
7 | #define SOL_SOCKET 1 | ||
8 | |||
9 | #define SO_DEBUG 1 | ||
10 | #define SO_REUSEADDR 2 | ||
11 | #define SO_TYPE 3 | ||
12 | #define SO_ERROR 4 | ||
13 | #define SO_DONTROUTE 5 | ||
14 | #define SO_BROADCAST 6 | ||
15 | #define SO_SNDBUF 7 | ||
16 | #define SO_RCVBUF 8 | ||
17 | #define SO_SNDBUFFORCE 32 | ||
18 | #define SO_RCVBUFFORCE 33 | ||
19 | #define SO_KEEPALIVE 9 | ||
20 | #define SO_OOBINLINE 10 | ||
21 | #define SO_NO_CHECK 11 | ||
22 | #define SO_PRIORITY 12 | ||
23 | #define SO_LINGER 13 | ||
24 | #define SO_BSDCOMPAT 14 | ||
25 | /* To add :#define SO_REUSEPORT 15 */ | ||
26 | #define SO_PASSCRED 16 | ||
27 | #define SO_PEERCRED 17 | ||
28 | #define SO_RCVLOWAT 18 | ||
29 | #define SO_SNDLOWAT 19 | ||
30 | #define SO_RCVTIMEO 20 | ||
31 | #define SO_SNDTIMEO 21 | ||
32 | |||
33 | /* Security levels - as per NRL IPv6 - don't actually do anything */ | ||
34 | #define SO_SECURITY_AUTHENTICATION 22 | ||
35 | #define SO_SECURITY_ENCRYPTION_TRANSPORT 23 | ||
36 | #define SO_SECURITY_ENCRYPTION_NETWORK 24 | ||
37 | |||
38 | #define SO_BINDTODEVICE 25 | ||
39 | |||
40 | /* Socket filtering */ | ||
41 | #define SO_ATTACH_FILTER 26 | ||
42 | #define SO_DETACH_FILTER 27 | ||
43 | |||
44 | #define SO_PEERNAME 28 | ||
45 | #define SO_TIMESTAMP 29 | ||
46 | #define SCM_TIMESTAMP SO_TIMESTAMP | ||
47 | |||
48 | #define SO_ACCEPTCONN 30 | ||
49 | |||
50 | #define SO_PEERSEC 31 | ||
51 | #define SO_PASSSEC 34 | ||
52 | #define SO_TIMESTAMPNS 35 | ||
53 | #define SCM_TIMESTAMPNS SO_TIMESTAMPNS | ||
54 | |||
55 | #define SO_MARK 36 | ||
56 | |||
57 | #endif /* _ASM_SOCKET_H */ | ||
diff --git a/arch/arm/include/asm/sockios.h b/arch/arm/include/asm/sockios.h new file mode 100644 index 000000000000..a2588a2512df --- /dev/null +++ b/arch/arm/include/asm/sockios.h | |||
@@ -0,0 +1,13 @@ | |||
1 | #ifndef __ARCH_ARM_SOCKIOS_H | ||
2 | #define __ARCH_ARM_SOCKIOS_H | ||
3 | |||
4 | /* Socket-level I/O control calls. */ | ||
5 | #define FIOSETOWN 0x8901 | ||
6 | #define SIOCSPGRP 0x8902 | ||
7 | #define FIOGETOWN 0x8903 | ||
8 | #define SIOCGPGRP 0x8904 | ||
9 | #define SIOCATMARK 0x8905 | ||
10 | #define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */ | ||
11 | #define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */ | ||
12 | |||
13 | #endif | ||
diff --git a/arch/arm/include/asm/sparsemem.h b/arch/arm/include/asm/sparsemem.h new file mode 100644 index 000000000000..277158191a0d --- /dev/null +++ b/arch/arm/include/asm/sparsemem.h | |||
@@ -0,0 +1,10 @@ | |||
1 | #ifndef ASMARM_SPARSEMEM_H | ||
2 | #define ASMARM_SPARSEMEM_H | ||
3 | |||
4 | #include <asm/memory.h> | ||
5 | |||
6 | #define MAX_PHYSADDR_BITS 32 | ||
7 | #define MAX_PHYSMEM_BITS 32 | ||
8 | #define SECTION_SIZE_BITS NODE_MEM_SIZE_BITS | ||
9 | |||
10 | #endif | ||
diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h new file mode 100644 index 000000000000..2b41ebbfa7ff --- /dev/null +++ b/arch/arm/include/asm/spinlock.h | |||
@@ -0,0 +1,224 @@ | |||
1 | #ifndef __ASM_SPINLOCK_H | ||
2 | #define __ASM_SPINLOCK_H | ||
3 | |||
4 | #if __LINUX_ARM_ARCH__ < 6 | ||
5 | #error SMP not supported on pre-ARMv6 CPUs | ||
6 | #endif | ||
7 | |||
8 | /* | ||
9 | * ARMv6 Spin-locking. | ||
10 | * | ||
11 | * We exclusively read the old value. If it is zero, we may have | ||
12 | * won the lock, so we try exclusively storing it. A memory barrier | ||
13 | * is required after we get a lock, and before we release it, because | ||
14 | * V6 CPUs are assumed to have weakly ordered memory. | ||
15 | * | ||
16 | * Unlocked value: 0 | ||
17 | * Locked value: 1 | ||
18 | */ | ||
19 | |||
20 | #define __raw_spin_is_locked(x) ((x)->lock != 0) | ||
21 | #define __raw_spin_unlock_wait(lock) \ | ||
22 | do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0) | ||
23 | |||
24 | #define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock) | ||
25 | |||
26 | static inline void __raw_spin_lock(raw_spinlock_t *lock) | ||
27 | { | ||
28 | unsigned long tmp; | ||
29 | |||
30 | __asm__ __volatile__( | ||
31 | "1: ldrex %0, [%1]\n" | ||
32 | " teq %0, #0\n" | ||
33 | #ifdef CONFIG_CPU_32v6K | ||
34 | " wfene\n" | ||
35 | #endif | ||
36 | " strexeq %0, %2, [%1]\n" | ||
37 | " teqeq %0, #0\n" | ||
38 | " bne 1b" | ||
39 | : "=&r" (tmp) | ||
40 | : "r" (&lock->lock), "r" (1) | ||
41 | : "cc"); | ||
42 | |||
43 | smp_mb(); | ||
44 | } | ||
45 | |||
46 | static inline int __raw_spin_trylock(raw_spinlock_t *lock) | ||
47 | { | ||
48 | unsigned long tmp; | ||
49 | |||
50 | __asm__ __volatile__( | ||
51 | " ldrex %0, [%1]\n" | ||
52 | " teq %0, #0\n" | ||
53 | " strexeq %0, %2, [%1]" | ||
54 | : "=&r" (tmp) | ||
55 | : "r" (&lock->lock), "r" (1) | ||
56 | : "cc"); | ||
57 | |||
58 | if (tmp == 0) { | ||
59 | smp_mb(); | ||
60 | return 1; | ||
61 | } else { | ||
62 | return 0; | ||
63 | } | ||
64 | } | ||
65 | |||
66 | static inline void __raw_spin_unlock(raw_spinlock_t *lock) | ||
67 | { | ||
68 | smp_mb(); | ||
69 | |||
70 | __asm__ __volatile__( | ||
71 | " str %1, [%0]\n" | ||
72 | #ifdef CONFIG_CPU_32v6K | ||
73 | " mcr p15, 0, %1, c7, c10, 4\n" /* DSB */ | ||
74 | " sev" | ||
75 | #endif | ||
76 | : | ||
77 | : "r" (&lock->lock), "r" (0) | ||
78 | : "cc"); | ||
79 | } | ||
80 | |||
81 | /* | ||
82 | * RWLOCKS | ||
83 | * | ||
84 | * | ||
85 | * Write locks are easy - we just set bit 31. When unlocking, we can | ||
86 | * just write zero since the lock is exclusively held. | ||
87 | */ | ||
88 | |||
89 | static inline void __raw_write_lock(raw_rwlock_t *rw) | ||
90 | { | ||
91 | unsigned long tmp; | ||
92 | |||
93 | __asm__ __volatile__( | ||
94 | "1: ldrex %0, [%1]\n" | ||
95 | " teq %0, #0\n" | ||
96 | #ifdef CONFIG_CPU_32v6K | ||
97 | " wfene\n" | ||
98 | #endif | ||
99 | " strexeq %0, %2, [%1]\n" | ||
100 | " teq %0, #0\n" | ||
101 | " bne 1b" | ||
102 | : "=&r" (tmp) | ||
103 | : "r" (&rw->lock), "r" (0x80000000) | ||
104 | : "cc"); | ||
105 | |||
106 | smp_mb(); | ||
107 | } | ||
108 | |||
109 | static inline int __raw_write_trylock(raw_rwlock_t *rw) | ||
110 | { | ||
111 | unsigned long tmp; | ||
112 | |||
113 | __asm__ __volatile__( | ||
114 | "1: ldrex %0, [%1]\n" | ||
115 | " teq %0, #0\n" | ||
116 | " strexeq %0, %2, [%1]" | ||
117 | : "=&r" (tmp) | ||
118 | : "r" (&rw->lock), "r" (0x80000000) | ||
119 | : "cc"); | ||
120 | |||
121 | if (tmp == 0) { | ||
122 | smp_mb(); | ||
123 | return 1; | ||
124 | } else { | ||
125 | return 0; | ||
126 | } | ||
127 | } | ||
128 | |||
129 | static inline void __raw_write_unlock(raw_rwlock_t *rw) | ||
130 | { | ||
131 | smp_mb(); | ||
132 | |||
133 | __asm__ __volatile__( | ||
134 | "str %1, [%0]\n" | ||
135 | #ifdef CONFIG_CPU_32v6K | ||
136 | " mcr p15, 0, %1, c7, c10, 4\n" /* DSB */ | ||
137 | " sev\n" | ||
138 | #endif | ||
139 | : | ||
140 | : "r" (&rw->lock), "r" (0) | ||
141 | : "cc"); | ||
142 | } | ||
143 | |||
144 | /* write_can_lock - would write_trylock() succeed? */ | ||
145 | #define __raw_write_can_lock(x) ((x)->lock == 0) | ||
146 | |||
147 | /* | ||
148 | * Read locks are a bit more hairy: | ||
149 | * - Exclusively load the lock value. | ||
150 | * - Increment it. | ||
151 | * - Store new lock value if positive, and we still own this location. | ||
152 | * If the value is negative, we've already failed. | ||
153 | * - If we failed to store the value, we want a negative result. | ||
154 | * - If we failed, try again. | ||
155 | * Unlocking is similarly hairy. We may have multiple read locks | ||
156 | * currently active. However, we know we won't have any write | ||
157 | * locks. | ||
158 | */ | ||
159 | static inline void __raw_read_lock(raw_rwlock_t *rw) | ||
160 | { | ||
161 | unsigned long tmp, tmp2; | ||
162 | |||
163 | __asm__ __volatile__( | ||
164 | "1: ldrex %0, [%2]\n" | ||
165 | " adds %0, %0, #1\n" | ||
166 | " strexpl %1, %0, [%2]\n" | ||
167 | #ifdef CONFIG_CPU_32v6K | ||
168 | " wfemi\n" | ||
169 | #endif | ||
170 | " rsbpls %0, %1, #0\n" | ||
171 | " bmi 1b" | ||
172 | : "=&r" (tmp), "=&r" (tmp2) | ||
173 | : "r" (&rw->lock) | ||
174 | : "cc"); | ||
175 | |||
176 | smp_mb(); | ||
177 | } | ||
178 | |||
179 | static inline void __raw_read_unlock(raw_rwlock_t *rw) | ||
180 | { | ||
181 | unsigned long tmp, tmp2; | ||
182 | |||
183 | smp_mb(); | ||
184 | |||
185 | __asm__ __volatile__( | ||
186 | "1: ldrex %0, [%2]\n" | ||
187 | " sub %0, %0, #1\n" | ||
188 | " strex %1, %0, [%2]\n" | ||
189 | " teq %1, #0\n" | ||
190 | " bne 1b" | ||
191 | #ifdef CONFIG_CPU_32v6K | ||
192 | "\n cmp %0, #0\n" | ||
193 | " mcreq p15, 0, %0, c7, c10, 4\n" | ||
194 | " seveq" | ||
195 | #endif | ||
196 | : "=&r" (tmp), "=&r" (tmp2) | ||
197 | : "r" (&rw->lock) | ||
198 | : "cc"); | ||
199 | } | ||
200 | |||
201 | static inline int __raw_read_trylock(raw_rwlock_t *rw) | ||
202 | { | ||
203 | unsigned long tmp, tmp2 = 1; | ||
204 | |||
205 | __asm__ __volatile__( | ||
206 | "1: ldrex %0, [%2]\n" | ||
207 | " adds %0, %0, #1\n" | ||
208 | " strexpl %1, %0, [%2]\n" | ||
209 | : "=&r" (tmp), "+r" (tmp2) | ||
210 | : "r" (&rw->lock) | ||
211 | : "cc"); | ||
212 | |||
213 | smp_mb(); | ||
214 | return tmp2 == 0; | ||
215 | } | ||
216 | |||
217 | /* read_can_lock - would read_trylock() succeed? */ | ||
218 | #define __raw_read_can_lock(x) ((x)->lock < 0x80000000) | ||
219 | |||
220 | #define _raw_spin_relax(lock) cpu_relax() | ||
221 | #define _raw_read_relax(lock) cpu_relax() | ||
222 | #define _raw_write_relax(lock) cpu_relax() | ||
223 | |||
224 | #endif /* __ASM_SPINLOCK_H */ | ||
diff --git a/arch/arm/include/asm/spinlock_types.h b/arch/arm/include/asm/spinlock_types.h new file mode 100644 index 000000000000..43e83f6d2ee5 --- /dev/null +++ b/arch/arm/include/asm/spinlock_types.h | |||
@@ -0,0 +1,20 @@ | |||
1 | #ifndef __ASM_SPINLOCK_TYPES_H | ||
2 | #define __ASM_SPINLOCK_TYPES_H | ||
3 | |||
4 | #ifndef __LINUX_SPINLOCK_TYPES_H | ||
5 | # error "please don't include this file directly" | ||
6 | #endif | ||
7 | |||
8 | typedef struct { | ||
9 | volatile unsigned int lock; | ||
10 | } raw_spinlock_t; | ||
11 | |||
12 | #define __RAW_SPIN_LOCK_UNLOCKED { 0 } | ||
13 | |||
14 | typedef struct { | ||
15 | volatile unsigned int lock; | ||
16 | } raw_rwlock_t; | ||
17 | |||
18 | #define __RAW_RW_LOCK_UNLOCKED { 0 } | ||
19 | |||
20 | #endif | ||
diff --git a/arch/arm/include/asm/stat.h b/arch/arm/include/asm/stat.h new file mode 100644 index 000000000000..42c0c13999d5 --- /dev/null +++ b/arch/arm/include/asm/stat.h | |||
@@ -0,0 +1,87 @@ | |||
1 | #ifndef _ASMARM_STAT_H | ||
2 | #define _ASMARM_STAT_H | ||
3 | |||
4 | struct __old_kernel_stat { | ||
5 | unsigned short st_dev; | ||
6 | unsigned short st_ino; | ||
7 | unsigned short st_mode; | ||
8 | unsigned short st_nlink; | ||
9 | unsigned short st_uid; | ||
10 | unsigned short st_gid; | ||
11 | unsigned short st_rdev; | ||
12 | unsigned long st_size; | ||
13 | unsigned long st_atime; | ||
14 | unsigned long st_mtime; | ||
15 | unsigned long st_ctime; | ||
16 | }; | ||
17 | |||
18 | #define STAT_HAVE_NSEC | ||
19 | |||
20 | struct stat { | ||
21 | #if defined(__ARMEB__) | ||
22 | unsigned short st_dev; | ||
23 | unsigned short __pad1; | ||
24 | #else | ||
25 | unsigned long st_dev; | ||
26 | #endif | ||
27 | unsigned long st_ino; | ||
28 | unsigned short st_mode; | ||
29 | unsigned short st_nlink; | ||
30 | unsigned short st_uid; | ||
31 | unsigned short st_gid; | ||
32 | #if defined(__ARMEB__) | ||
33 | unsigned short st_rdev; | ||
34 | unsigned short __pad2; | ||
35 | #else | ||
36 | unsigned long st_rdev; | ||
37 | #endif | ||
38 | unsigned long st_size; | ||
39 | unsigned long st_blksize; | ||
40 | unsigned long st_blocks; | ||
41 | unsigned long st_atime; | ||
42 | unsigned long st_atime_nsec; | ||
43 | unsigned long st_mtime; | ||
44 | unsigned long st_mtime_nsec; | ||
45 | unsigned long st_ctime; | ||
46 | unsigned long st_ctime_nsec; | ||
47 | unsigned long __unused4; | ||
48 | unsigned long __unused5; | ||
49 | }; | ||
50 | |||
51 | /* This matches struct stat64 in glibc2.1, hence the absolutely | ||
52 | * insane amounts of padding around dev_t's. | ||
53 | * Note: The kernel zero's the padded region because glibc might read them | ||
54 | * in the hope that the kernel has stretched to using larger sizes. | ||
55 | */ | ||
56 | struct stat64 { | ||
57 | unsigned long long st_dev; | ||
58 | unsigned char __pad0[4]; | ||
59 | |||
60 | #define STAT64_HAS_BROKEN_ST_INO 1 | ||
61 | unsigned long __st_ino; | ||
62 | unsigned int st_mode; | ||
63 | unsigned int st_nlink; | ||
64 | |||
65 | unsigned long st_uid; | ||
66 | unsigned long st_gid; | ||
67 | |||
68 | unsigned long long st_rdev; | ||
69 | unsigned char __pad3[4]; | ||
70 | |||
71 | long long st_size; | ||
72 | unsigned long st_blksize; | ||
73 | unsigned long long st_blocks; /* Number 512-byte blocks allocated. */ | ||
74 | |||
75 | unsigned long st_atime; | ||
76 | unsigned long st_atime_nsec; | ||
77 | |||
78 | unsigned long st_mtime; | ||
79 | unsigned long st_mtime_nsec; | ||
80 | |||
81 | unsigned long st_ctime; | ||
82 | unsigned long st_ctime_nsec; | ||
83 | |||
84 | unsigned long long st_ino; | ||
85 | }; | ||
86 | |||
87 | #endif | ||
diff --git a/arch/arm/include/asm/statfs.h b/arch/arm/include/asm/statfs.h new file mode 100644 index 000000000000..a02e6a8c3d70 --- /dev/null +++ b/arch/arm/include/asm/statfs.h | |||
@@ -0,0 +1,42 @@ | |||
1 | #ifndef _ASMARM_STATFS_H | ||
2 | #define _ASMARM_STATFS_H | ||
3 | |||
4 | #ifndef __KERNEL_STRICT_NAMES | ||
5 | # include <linux/types.h> | ||
6 | typedef __kernel_fsid_t fsid_t; | ||
7 | #endif | ||
8 | |||
9 | struct statfs { | ||
10 | __u32 f_type; | ||
11 | __u32 f_bsize; | ||
12 | __u32 f_blocks; | ||
13 | __u32 f_bfree; | ||
14 | __u32 f_bavail; | ||
15 | __u32 f_files; | ||
16 | __u32 f_ffree; | ||
17 | __kernel_fsid_t f_fsid; | ||
18 | __u32 f_namelen; | ||
19 | __u32 f_frsize; | ||
20 | __u32 f_spare[5]; | ||
21 | }; | ||
22 | |||
23 | /* | ||
24 | * With EABI there is 4 bytes of padding added to this structure. | ||
25 | * Let's pack it so the padding goes away to simplify dual ABI support. | ||
26 | * Note that user space does NOT have to pack this structure. | ||
27 | */ | ||
28 | struct statfs64 { | ||
29 | __u32 f_type; | ||
30 | __u32 f_bsize; | ||
31 | __u64 f_blocks; | ||
32 | __u64 f_bfree; | ||
33 | __u64 f_bavail; | ||
34 | __u64 f_files; | ||
35 | __u64 f_ffree; | ||
36 | __kernel_fsid_t f_fsid; | ||
37 | __u32 f_namelen; | ||
38 | __u32 f_frsize; | ||
39 | __u32 f_spare[5]; | ||
40 | } __attribute__ ((packed,aligned(4))); | ||
41 | |||
42 | #endif | ||
diff --git a/arch/arm/include/asm/string.h b/arch/arm/include/asm/string.h new file mode 100644 index 000000000000..e50c4a39b699 --- /dev/null +++ b/arch/arm/include/asm/string.h | |||
@@ -0,0 +1,50 @@ | |||
1 | #ifndef __ASM_ARM_STRING_H | ||
2 | #define __ASM_ARM_STRING_H | ||
3 | |||
4 | /* | ||
5 | * We don't do inline string functions, since the | ||
6 | * optimised inline asm versions are not small. | ||
7 | */ | ||
8 | |||
9 | #define __HAVE_ARCH_STRRCHR | ||
10 | extern char * strrchr(const char * s, int c); | ||
11 | |||
12 | #define __HAVE_ARCH_STRCHR | ||
13 | extern char * strchr(const char * s, int c); | ||
14 | |||
15 | #define __HAVE_ARCH_MEMCPY | ||
16 | extern void * memcpy(void *, const void *, __kernel_size_t); | ||
17 | |||
18 | #define __HAVE_ARCH_MEMMOVE | ||
19 | extern void * memmove(void *, const void *, __kernel_size_t); | ||
20 | |||
21 | #define __HAVE_ARCH_MEMCHR | ||
22 | extern void * memchr(const void *, int, __kernel_size_t); | ||
23 | |||
24 | #define __HAVE_ARCH_MEMZERO | ||
25 | #define __HAVE_ARCH_MEMSET | ||
26 | extern void * memset(void *, int, __kernel_size_t); | ||
27 | |||
28 | extern void __memzero(void *ptr, __kernel_size_t n); | ||
29 | |||
30 | #define memset(p,v,n) \ | ||
31 | ({ \ | ||
32 | void *__p = (p); size_t __n = n; \ | ||
33 | if ((__n) != 0) { \ | ||
34 | if (__builtin_constant_p((v)) && (v) == 0) \ | ||
35 | __memzero((__p),(__n)); \ | ||
36 | else \ | ||
37 | memset((__p),(v),(__n)); \ | ||
38 | } \ | ||
39 | (__p); \ | ||
40 | }) | ||
41 | |||
42 | #define memzero(p,n) \ | ||
43 | ({ \ | ||
44 | void *__p = (p); size_t __n = n; \ | ||
45 | if ((__n) != 0) \ | ||
46 | __memzero((__p),(__n)); \ | ||
47 | (__p); \ | ||
48 | }) | ||
49 | |||
50 | #endif | ||
diff --git a/arch/arm/include/asm/suspend.h b/arch/arm/include/asm/suspend.h new file mode 100644 index 000000000000..cf0d0bdee74d --- /dev/null +++ b/arch/arm/include/asm/suspend.h | |||
@@ -0,0 +1,4 @@ | |||
1 | #ifndef _ASMARM_SUSPEND_H | ||
2 | #define _ASMARM_SUSPEND_H | ||
3 | |||
4 | #endif | ||
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h new file mode 100644 index 000000000000..514af792a598 --- /dev/null +++ b/arch/arm/include/asm/system.h | |||
@@ -0,0 +1,388 @@ | |||
1 | #ifndef __ASM_ARM_SYSTEM_H | ||
2 | #define __ASM_ARM_SYSTEM_H | ||
3 | |||
4 | #ifdef __KERNEL__ | ||
5 | |||
6 | #include <asm/memory.h> | ||
7 | |||
8 | #define CPU_ARCH_UNKNOWN 0 | ||
9 | #define CPU_ARCH_ARMv3 1 | ||
10 | #define CPU_ARCH_ARMv4 2 | ||
11 | #define CPU_ARCH_ARMv4T 3 | ||
12 | #define CPU_ARCH_ARMv5 4 | ||
13 | #define CPU_ARCH_ARMv5T 5 | ||
14 | #define CPU_ARCH_ARMv5TE 6 | ||
15 | #define CPU_ARCH_ARMv5TEJ 7 | ||
16 | #define CPU_ARCH_ARMv6 8 | ||
17 | #define CPU_ARCH_ARMv7 9 | ||
18 | |||
19 | /* | ||
20 | * CR1 bits (CP#15 CR1) | ||
21 | */ | ||
22 | #define CR_M (1 << 0) /* MMU enable */ | ||
23 | #define CR_A (1 << 1) /* Alignment abort enable */ | ||
24 | #define CR_C (1 << 2) /* Dcache enable */ | ||
25 | #define CR_W (1 << 3) /* Write buffer enable */ | ||
26 | #define CR_P (1 << 4) /* 32-bit exception handler */ | ||
27 | #define CR_D (1 << 5) /* 32-bit data address range */ | ||
28 | #define CR_L (1 << 6) /* Implementation defined */ | ||
29 | #define CR_B (1 << 7) /* Big endian */ | ||
30 | #define CR_S (1 << 8) /* System MMU protection */ | ||
31 | #define CR_R (1 << 9) /* ROM MMU protection */ | ||
32 | #define CR_F (1 << 10) /* Implementation defined */ | ||
33 | #define CR_Z (1 << 11) /* Implementation defined */ | ||
34 | #define CR_I (1 << 12) /* Icache enable */ | ||
35 | #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ | ||
36 | #define CR_RR (1 << 14) /* Round Robin cache replacement */ | ||
37 | #define CR_L4 (1 << 15) /* LDR pc can set T bit */ | ||
38 | #define CR_DT (1 << 16) | ||
39 | #define CR_IT (1 << 18) | ||
40 | #define CR_ST (1 << 19) | ||
41 | #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */ | ||
42 | #define CR_U (1 << 22) /* Unaligned access operation */ | ||
43 | #define CR_XP (1 << 23) /* Extended page tables */ | ||
44 | #define CR_VE (1 << 24) /* Vectored interrupts */ | ||
45 | |||
46 | #define CPUID_ID 0 | ||
47 | #define CPUID_CACHETYPE 1 | ||
48 | #define CPUID_TCM 2 | ||
49 | #define CPUID_TLBTYPE 3 | ||
50 | |||
51 | /* | ||
52 | * This is used to ensure the compiler did actually allocate the register we | ||
53 | * asked it for some inline assembly sequences. Apparently we can't trust | ||
54 | * the compiler from one version to another so a bit of paranoia won't hurt. | ||
55 | * This string is meant to be concatenated with the inline asm string and | ||
56 | * will cause compilation to stop on mismatch. | ||
57 | * (for details, see gcc PR 15089) | ||
58 | */ | ||
59 | #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" | ||
60 | |||
61 | #ifndef __ASSEMBLY__ | ||
62 | |||
63 | #include <linux/linkage.h> | ||
64 | #include <linux/stringify.h> | ||
65 | #include <linux/irqflags.h> | ||
66 | |||
67 | #ifdef CONFIG_CPU_CP15 | ||
68 | #define read_cpuid(reg) \ | ||
69 | ({ \ | ||
70 | unsigned int __val; \ | ||
71 | asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \ | ||
72 | : "=r" (__val) \ | ||
73 | : \ | ||
74 | : "cc"); \ | ||
75 | __val; \ | ||
76 | }) | ||
77 | #else | ||
78 | extern unsigned int processor_id; | ||
79 | #define read_cpuid(reg) (processor_id) | ||
80 | #endif | ||
81 | |||
82 | /* | ||
83 | * The CPU ID never changes at run time, so we might as well tell the | ||
84 | * compiler that it's constant. Use this function to read the CPU ID | ||
85 | * rather than directly reading processor_id or read_cpuid() directly. | ||
86 | */ | ||
87 | static inline unsigned int read_cpuid_id(void) __attribute_const__; | ||
88 | |||
89 | static inline unsigned int read_cpuid_id(void) | ||
90 | { | ||
91 | return read_cpuid(CPUID_ID); | ||
92 | } | ||
93 | |||
94 | #define __exception __attribute__((section(".exception.text"))) | ||
95 | |||
96 | struct thread_info; | ||
97 | struct task_struct; | ||
98 | |||
99 | /* information about the system we're running on */ | ||
100 | extern unsigned int system_rev; | ||
101 | extern unsigned int system_serial_low; | ||
102 | extern unsigned int system_serial_high; | ||
103 | extern unsigned int mem_fclk_21285; | ||
104 | |||
105 | struct pt_regs; | ||
106 | |||
107 | void die(const char *msg, struct pt_regs *regs, int err) | ||
108 | __attribute__((noreturn)); | ||
109 | |||
110 | struct siginfo; | ||
111 | void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info, | ||
112 | unsigned long err, unsigned long trap); | ||
113 | |||
114 | void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int, | ||
115 | struct pt_regs *), | ||
116 | int sig, const char *name); | ||
117 | |||
118 | #define xchg(ptr,x) \ | ||
119 | ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) | ||
120 | |||
121 | extern asmlinkage void __backtrace(void); | ||
122 | extern asmlinkage void c_backtrace(unsigned long fp, int pmode); | ||
123 | |||
124 | struct mm_struct; | ||
125 | extern void show_pte(struct mm_struct *mm, unsigned long addr); | ||
126 | extern void __show_regs(struct pt_regs *); | ||
127 | |||
128 | extern int cpu_architecture(void); | ||
129 | extern void cpu_init(void); | ||
130 | |||
131 | void arm_machine_restart(char mode); | ||
132 | extern void (*arm_pm_restart)(char str); | ||
133 | |||
134 | /* | ||
135 | * Intel's XScale3 core supports some v6 features (supersections, L2) | ||
136 | * but advertises itself as v5 as it does not support the v6 ISA. For | ||
137 | * this reason, we need a way to explicitly test for this type of CPU. | ||
138 | */ | ||
139 | #ifndef CONFIG_CPU_XSC3 | ||
140 | #define cpu_is_xsc3() 0 | ||
141 | #else | ||
142 | static inline int cpu_is_xsc3(void) | ||
143 | { | ||
144 | extern unsigned int processor_id; | ||
145 | |||
146 | if ((processor_id & 0xffffe000) == 0x69056000) | ||
147 | return 1; | ||
148 | |||
149 | return 0; | ||
150 | } | ||
151 | #endif | ||
152 | |||
153 | #if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3) | ||
154 | #define cpu_is_xscale() 0 | ||
155 | #else | ||
156 | #define cpu_is_xscale() 1 | ||
157 | #endif | ||
158 | |||
159 | #define UDBG_UNDEFINED (1 << 0) | ||
160 | #define UDBG_SYSCALL (1 << 1) | ||
161 | #define UDBG_BADABORT (1 << 2) | ||
162 | #define UDBG_SEGV (1 << 3) | ||
163 | #define UDBG_BUS (1 << 4) | ||
164 | |||
165 | extern unsigned int user_debug; | ||
166 | |||
167 | #if __LINUX_ARM_ARCH__ >= 4 | ||
168 | #define vectors_high() (cr_alignment & CR_V) | ||
169 | #else | ||
170 | #define vectors_high() (0) | ||
171 | #endif | ||
172 | |||
173 | #if __LINUX_ARM_ARCH__ >= 7 | ||
174 | #define isb() __asm__ __volatile__ ("isb" : : : "memory") | ||
175 | #define dsb() __asm__ __volatile__ ("dsb" : : : "memory") | ||
176 | #define dmb() __asm__ __volatile__ ("dmb" : : : "memory") | ||
177 | #elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6 | ||
178 | #define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \ | ||
179 | : : "r" (0) : "memory") | ||
180 | #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ | ||
181 | : : "r" (0) : "memory") | ||
182 | #define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \ | ||
183 | : : "r" (0) : "memory") | ||
184 | #else | ||
185 | #define isb() __asm__ __volatile__ ("" : : : "memory") | ||
186 | #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ | ||
187 | : : "r" (0) : "memory") | ||
188 | #define dmb() __asm__ __volatile__ ("" : : : "memory") | ||
189 | #endif | ||
190 | |||
191 | #ifndef CONFIG_SMP | ||
192 | #define mb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0) | ||
193 | #define rmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0) | ||
194 | #define wmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0) | ||
195 | #define smp_mb() barrier() | ||
196 | #define smp_rmb() barrier() | ||
197 | #define smp_wmb() barrier() | ||
198 | #else | ||
199 | #define mb() dmb() | ||
200 | #define rmb() dmb() | ||
201 | #define wmb() dmb() | ||
202 | #define smp_mb() dmb() | ||
203 | #define smp_rmb() dmb() | ||
204 | #define smp_wmb() dmb() | ||
205 | #endif | ||
206 | #define read_barrier_depends() do { } while(0) | ||
207 | #define smp_read_barrier_depends() do { } while(0) | ||
208 | |||
209 | #define set_mb(var, value) do { var = value; smp_mb(); } while (0) | ||
210 | #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); | ||
211 | |||
212 | extern unsigned long cr_no_alignment; /* defined in entry-armv.S */ | ||
213 | extern unsigned long cr_alignment; /* defined in entry-armv.S */ | ||
214 | |||
215 | static inline unsigned int get_cr(void) | ||
216 | { | ||
217 | unsigned int val; | ||
218 | asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc"); | ||
219 | return val; | ||
220 | } | ||
221 | |||
222 | static inline void set_cr(unsigned int val) | ||
223 | { | ||
224 | asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" | ||
225 | : : "r" (val) : "cc"); | ||
226 | isb(); | ||
227 | } | ||
228 | |||
229 | #ifndef CONFIG_SMP | ||
230 | extern void adjust_cr(unsigned long mask, unsigned long set); | ||
231 | #endif | ||
232 | |||
233 | #define CPACC_FULL(n) (3 << (n * 2)) | ||
234 | #define CPACC_SVC(n) (1 << (n * 2)) | ||
235 | #define CPACC_DISABLE(n) (0 << (n * 2)) | ||
236 | |||
237 | static inline unsigned int get_copro_access(void) | ||
238 | { | ||
239 | unsigned int val; | ||
240 | asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access" | ||
241 | : "=r" (val) : : "cc"); | ||
242 | return val; | ||
243 | } | ||
244 | |||
245 | static inline void set_copro_access(unsigned int val) | ||
246 | { | ||
247 | asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access" | ||
248 | : : "r" (val) : "cc"); | ||
249 | isb(); | ||
250 | } | ||
251 | |||
252 | /* | ||
253 | * switch_mm() may do a full cache flush over the context switch, | ||
254 | * so enable interrupts over the context switch to avoid high | ||
255 | * latency. | ||
256 | */ | ||
257 | #define __ARCH_WANT_INTERRUPTS_ON_CTXSW | ||
258 | |||
259 | /* | ||
260 | * switch_to(prev, next) should switch from task `prev' to `next' | ||
261 | * `prev' will never be the same as `next'. schedule() itself | ||
262 | * contains the memory barrier to tell GCC not to cache `current'. | ||
263 | */ | ||
264 | extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *); | ||
265 | |||
266 | #define switch_to(prev,next,last) \ | ||
267 | do { \ | ||
268 | last = __switch_to(prev,task_thread_info(prev), task_thread_info(next)); \ | ||
269 | } while (0) | ||
270 | |||
271 | #if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) | ||
272 | /* | ||
273 | * On the StrongARM, "swp" is terminally broken since it bypasses the | ||
274 | * cache totally. This means that the cache becomes inconsistent, and, | ||
275 | * since we use normal loads/stores as well, this is really bad. | ||
276 | * Typically, this causes oopsen in filp_close, but could have other, | ||
277 | * more disasterous effects. There are two work-arounds: | ||
278 | * 1. Disable interrupts and emulate the atomic swap | ||
279 | * 2. Clean the cache, perform atomic swap, flush the cache | ||
280 | * | ||
281 | * We choose (1) since its the "easiest" to achieve here and is not | ||
282 | * dependent on the processor type. | ||
283 | * | ||
284 | * NOTE that this solution won't work on an SMP system, so explcitly | ||
285 | * forbid it here. | ||
286 | */ | ||
287 | #define swp_is_buggy | ||
288 | #endif | ||
289 | |||
290 | static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size) | ||
291 | { | ||
292 | extern void __bad_xchg(volatile void *, int); | ||
293 | unsigned long ret; | ||
294 | #ifdef swp_is_buggy | ||
295 | unsigned long flags; | ||
296 | #endif | ||
297 | #if __LINUX_ARM_ARCH__ >= 6 | ||
298 | unsigned int tmp; | ||
299 | #endif | ||
300 | |||
301 | switch (size) { | ||
302 | #if __LINUX_ARM_ARCH__ >= 6 | ||
303 | case 1: | ||
304 | asm volatile("@ __xchg1\n" | ||
305 | "1: ldrexb %0, [%3]\n" | ||
306 | " strexb %1, %2, [%3]\n" | ||
307 | " teq %1, #0\n" | ||
308 | " bne 1b" | ||
309 | : "=&r" (ret), "=&r" (tmp) | ||
310 | : "r" (x), "r" (ptr) | ||
311 | : "memory", "cc"); | ||
312 | break; | ||
313 | case 4: | ||
314 | asm volatile("@ __xchg4\n" | ||
315 | "1: ldrex %0, [%3]\n" | ||
316 | " strex %1, %2, [%3]\n" | ||
317 | " teq %1, #0\n" | ||
318 | " bne 1b" | ||
319 | : "=&r" (ret), "=&r" (tmp) | ||
320 | : "r" (x), "r" (ptr) | ||
321 | : "memory", "cc"); | ||
322 | break; | ||
323 | #elif defined(swp_is_buggy) | ||
324 | #ifdef CONFIG_SMP | ||
325 | #error SMP is not supported on this platform | ||
326 | #endif | ||
327 | case 1: | ||
328 | raw_local_irq_save(flags); | ||
329 | ret = *(volatile unsigned char *)ptr; | ||
330 | *(volatile unsigned char *)ptr = x; | ||
331 | raw_local_irq_restore(flags); | ||
332 | break; | ||
333 | |||
334 | case 4: | ||
335 | raw_local_irq_save(flags); | ||
336 | ret = *(volatile unsigned long *)ptr; | ||
337 | *(volatile unsigned long *)ptr = x; | ||
338 | raw_local_irq_restore(flags); | ||
339 | break; | ||
340 | #else | ||
341 | case 1: | ||
342 | asm volatile("@ __xchg1\n" | ||
343 | " swpb %0, %1, [%2]" | ||
344 | : "=&r" (ret) | ||
345 | : "r" (x), "r" (ptr) | ||
346 | : "memory", "cc"); | ||
347 | break; | ||
348 | case 4: | ||
349 | asm volatile("@ __xchg4\n" | ||
350 | " swp %0, %1, [%2]" | ||
351 | : "=&r" (ret) | ||
352 | : "r" (x), "r" (ptr) | ||
353 | : "memory", "cc"); | ||
354 | break; | ||
355 | #endif | ||
356 | default: | ||
357 | __bad_xchg(ptr, size), ret = 0; | ||
358 | break; | ||
359 | } | ||
360 | |||
361 | return ret; | ||
362 | } | ||
363 | |||
364 | extern void disable_hlt(void); | ||
365 | extern void enable_hlt(void); | ||
366 | |||
367 | #include <asm-generic/cmpxchg-local.h> | ||
368 | |||
369 | /* | ||
370 | * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make | ||
371 | * them available. | ||
372 | */ | ||
373 | #define cmpxchg_local(ptr, o, n) \ | ||
374 | ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\ | ||
375 | (unsigned long)(n), sizeof(*(ptr)))) | ||
376 | #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) | ||
377 | |||
378 | #ifndef CONFIG_SMP | ||
379 | #include <asm-generic/cmpxchg.h> | ||
380 | #endif | ||
381 | |||
382 | #endif /* __ASSEMBLY__ */ | ||
383 | |||
384 | #define arch_align_stack(x) (x) | ||
385 | |||
386 | #endif /* __KERNEL__ */ | ||
387 | |||
388 | #endif | ||
diff --git a/arch/arm/include/asm/termbits.h b/arch/arm/include/asm/termbits.h new file mode 100644 index 000000000000..f784d11f40b5 --- /dev/null +++ b/arch/arm/include/asm/termbits.h | |||
@@ -0,0 +1,197 @@ | |||
1 | #ifndef __ASM_ARM_TERMBITS_H | ||
2 | #define __ASM_ARM_TERMBITS_H | ||
3 | |||
4 | typedef unsigned char cc_t; | ||
5 | typedef unsigned int speed_t; | ||
6 | typedef unsigned int tcflag_t; | ||
7 | |||
8 | #define NCCS 19 | ||
9 | struct termios { | ||
10 | tcflag_t c_iflag; /* input mode flags */ | ||
11 | tcflag_t c_oflag; /* output mode flags */ | ||
12 | tcflag_t c_cflag; /* control mode flags */ | ||
13 | tcflag_t c_lflag; /* local mode flags */ | ||
14 | cc_t c_line; /* line discipline */ | ||
15 | cc_t c_cc[NCCS]; /* control characters */ | ||
16 | }; | ||
17 | |||
18 | struct termios2 { | ||
19 | tcflag_t c_iflag; /* input mode flags */ | ||
20 | tcflag_t c_oflag; /* output mode flags */ | ||
21 | tcflag_t c_cflag; /* control mode flags */ | ||
22 | tcflag_t c_lflag; /* local mode flags */ | ||
23 | cc_t c_line; /* line discipline */ | ||
24 | cc_t c_cc[NCCS]; /* control characters */ | ||
25 | speed_t c_ispeed; /* input speed */ | ||
26 | speed_t c_ospeed; /* output speed */ | ||
27 | }; | ||
28 | |||
29 | struct ktermios { | ||
30 | tcflag_t c_iflag; /* input mode flags */ | ||
31 | tcflag_t c_oflag; /* output mode flags */ | ||
32 | tcflag_t c_cflag; /* control mode flags */ | ||
33 | tcflag_t c_lflag; /* local mode flags */ | ||
34 | cc_t c_line; /* line discipline */ | ||
35 | cc_t c_cc[NCCS]; /* control characters */ | ||
36 | speed_t c_ispeed; /* input speed */ | ||
37 | speed_t c_ospeed; /* output speed */ | ||
38 | }; | ||
39 | |||
40 | |||
41 | /* c_cc characters */ | ||
42 | #define VINTR 0 | ||
43 | #define VQUIT 1 | ||
44 | #define VERASE 2 | ||
45 | #define VKILL 3 | ||
46 | #define VEOF 4 | ||
47 | #define VTIME 5 | ||
48 | #define VMIN 6 | ||
49 | #define VSWTC 7 | ||
50 | #define VSTART 8 | ||
51 | #define VSTOP 9 | ||
52 | #define VSUSP 10 | ||
53 | #define VEOL 11 | ||
54 | #define VREPRINT 12 | ||
55 | #define VDISCARD 13 | ||
56 | #define VWERASE 14 | ||
57 | #define VLNEXT 15 | ||
58 | #define VEOL2 16 | ||
59 | |||
60 | /* c_iflag bits */ | ||
61 | #define IGNBRK 0000001 | ||
62 | #define BRKINT 0000002 | ||
63 | #define IGNPAR 0000004 | ||
64 | #define PARMRK 0000010 | ||
65 | #define INPCK 0000020 | ||
66 | #define ISTRIP 0000040 | ||
67 | #define INLCR 0000100 | ||
68 | #define IGNCR 0000200 | ||
69 | #define ICRNL 0000400 | ||
70 | #define IUCLC 0001000 | ||
71 | #define IXON 0002000 | ||
72 | #define IXANY 0004000 | ||
73 | #define IXOFF 0010000 | ||
74 | #define IMAXBEL 0020000 | ||
75 | #define IUTF8 0040000 | ||
76 | |||
77 | /* c_oflag bits */ | ||
78 | #define OPOST 0000001 | ||
79 | #define OLCUC 0000002 | ||
80 | #define ONLCR 0000004 | ||
81 | #define OCRNL 0000010 | ||
82 | #define ONOCR 0000020 | ||
83 | #define ONLRET 0000040 | ||
84 | #define OFILL 0000100 | ||
85 | #define OFDEL 0000200 | ||
86 | #define NLDLY 0000400 | ||
87 | #define NL0 0000000 | ||
88 | #define NL1 0000400 | ||
89 | #define CRDLY 0003000 | ||
90 | #define CR0 0000000 | ||
91 | #define CR1 0001000 | ||
92 | #define CR2 0002000 | ||
93 | #define CR3 0003000 | ||
94 | #define TABDLY 0014000 | ||
95 | #define TAB0 0000000 | ||
96 | #define TAB1 0004000 | ||
97 | #define TAB2 0010000 | ||
98 | #define TAB3 0014000 | ||
99 | #define XTABS 0014000 | ||
100 | #define BSDLY 0020000 | ||
101 | #define BS0 0000000 | ||
102 | #define BS1 0020000 | ||
103 | #define VTDLY 0040000 | ||
104 | #define VT0 0000000 | ||
105 | #define VT1 0040000 | ||
106 | #define FFDLY 0100000 | ||
107 | #define FF0 0000000 | ||
108 | #define FF1 0100000 | ||
109 | |||
110 | /* c_cflag bit meaning */ | ||
111 | #define CBAUD 0010017 | ||
112 | #define B0 0000000 /* hang up */ | ||
113 | #define B50 0000001 | ||
114 | #define B75 0000002 | ||
115 | #define B110 0000003 | ||
116 | #define B134 0000004 | ||
117 | #define B150 0000005 | ||
118 | #define B200 0000006 | ||
119 | #define B300 0000007 | ||
120 | #define B600 0000010 | ||
121 | #define B1200 0000011 | ||
122 | #define B1800 0000012 | ||
123 | #define B2400 0000013 | ||
124 | #define B4800 0000014 | ||
125 | #define B9600 0000015 | ||
126 | #define B19200 0000016 | ||
127 | #define B38400 0000017 | ||
128 | #define EXTA B19200 | ||
129 | #define EXTB B38400 | ||
130 | #define CSIZE 0000060 | ||
131 | #define CS5 0000000 | ||
132 | #define CS6 0000020 | ||
133 | #define CS7 0000040 | ||
134 | #define CS8 0000060 | ||
135 | #define CSTOPB 0000100 | ||
136 | #define CREAD 0000200 | ||
137 | #define PARENB 0000400 | ||
138 | #define PARODD 0001000 | ||
139 | #define HUPCL 0002000 | ||
140 | #define CLOCAL 0004000 | ||
141 | #define CBAUDEX 0010000 | ||
142 | #define BOTHER 0010000 | ||
143 | #define B57600 0010001 | ||
144 | #define B115200 0010002 | ||
145 | #define B230400 0010003 | ||
146 | #define B460800 0010004 | ||
147 | #define B500000 0010005 | ||
148 | #define B576000 0010006 | ||
149 | #define B921600 0010007 | ||
150 | #define B1000000 0010010 | ||
151 | #define B1152000 0010011 | ||
152 | #define B1500000 0010012 | ||
153 | #define B2000000 0010013 | ||
154 | #define B2500000 0010014 | ||
155 | #define B3000000 0010015 | ||
156 | #define B3500000 0010016 | ||
157 | #define B4000000 0010017 | ||
158 | #define CIBAUD 002003600000 /* input baud rate */ | ||
159 | #define CMSPAR 010000000000 /* mark or space (stick) parity */ | ||
160 | #define CRTSCTS 020000000000 /* flow control */ | ||
161 | |||
162 | #define IBSHIFT 16 | ||
163 | |||
164 | /* c_lflag bits */ | ||
165 | #define ISIG 0000001 | ||
166 | #define ICANON 0000002 | ||
167 | #define XCASE 0000004 | ||
168 | #define ECHO 0000010 | ||
169 | #define ECHOE 0000020 | ||
170 | #define ECHOK 0000040 | ||
171 | #define ECHONL 0000100 | ||
172 | #define NOFLSH 0000200 | ||
173 | #define TOSTOP 0000400 | ||
174 | #define ECHOCTL 0001000 | ||
175 | #define ECHOPRT 0002000 | ||
176 | #define ECHOKE 0004000 | ||
177 | #define FLUSHO 0010000 | ||
178 | #define PENDIN 0040000 | ||
179 | #define IEXTEN 0100000 | ||
180 | |||
181 | /* tcflow() and TCXONC use these */ | ||
182 | #define TCOOFF 0 | ||
183 | #define TCOON 1 | ||
184 | #define TCIOFF 2 | ||
185 | #define TCION 3 | ||
186 | |||
187 | /* tcflush() and TCFLSH use these */ | ||
188 | #define TCIFLUSH 0 | ||
189 | #define TCOFLUSH 1 | ||
190 | #define TCIOFLUSH 2 | ||
191 | |||
192 | /* tcsetattr uses these */ | ||
193 | #define TCSANOW 0 | ||
194 | #define TCSADRAIN 1 | ||
195 | #define TCSAFLUSH 2 | ||
196 | |||
197 | #endif /* __ASM_ARM_TERMBITS_H */ | ||
diff --git a/arch/arm/include/asm/termios.h b/arch/arm/include/asm/termios.h new file mode 100644 index 000000000000..293e3f1bc3f2 --- /dev/null +++ b/arch/arm/include/asm/termios.h | |||
@@ -0,0 +1,92 @@ | |||
1 | #ifndef __ASM_ARM_TERMIOS_H | ||
2 | #define __ASM_ARM_TERMIOS_H | ||
3 | |||
4 | #include <asm/termbits.h> | ||
5 | #include <asm/ioctls.h> | ||
6 | |||
7 | struct winsize { | ||
8 | unsigned short ws_row; | ||
9 | unsigned short ws_col; | ||
10 | unsigned short ws_xpixel; | ||
11 | unsigned short ws_ypixel; | ||
12 | }; | ||
13 | |||
14 | #define NCC 8 | ||
15 | struct termio { | ||
16 | unsigned short c_iflag; /* input mode flags */ | ||
17 | unsigned short c_oflag; /* output mode flags */ | ||
18 | unsigned short c_cflag; /* control mode flags */ | ||
19 | unsigned short c_lflag; /* local mode flags */ | ||
20 | unsigned char c_line; /* line discipline */ | ||
21 | unsigned char c_cc[NCC]; /* control characters */ | ||
22 | }; | ||
23 | |||
24 | #ifdef __KERNEL__ | ||
25 | /* intr=^C quit=^| erase=del kill=^U | ||
26 | eof=^D vtime=\0 vmin=\1 sxtc=\0 | ||
27 | start=^Q stop=^S susp=^Z eol=\0 | ||
28 | reprint=^R discard=^U werase=^W lnext=^V | ||
29 | eol2=\0 | ||
30 | */ | ||
31 | #define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0" | ||
32 | #endif | ||
33 | |||
34 | /* modem lines */ | ||
35 | #define TIOCM_LE 0x001 | ||
36 | #define TIOCM_DTR 0x002 | ||
37 | #define TIOCM_RTS 0x004 | ||
38 | #define TIOCM_ST 0x008 | ||
39 | #define TIOCM_SR 0x010 | ||
40 | #define TIOCM_CTS 0x020 | ||
41 | #define TIOCM_CAR 0x040 | ||
42 | #define TIOCM_RNG 0x080 | ||
43 | #define TIOCM_DSR 0x100 | ||
44 | #define TIOCM_CD TIOCM_CAR | ||
45 | #define TIOCM_RI TIOCM_RNG | ||
46 | #define TIOCM_OUT1 0x2000 | ||
47 | #define TIOCM_OUT2 0x4000 | ||
48 | #define TIOCM_LOOP 0x8000 | ||
49 | |||
50 | /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ | ||
51 | |||
52 | #ifdef __KERNEL__ | ||
53 | |||
54 | /* | ||
55 | * Translate a "termio" structure into a "termios". Ugh. | ||
56 | */ | ||
57 | #define SET_LOW_TERMIOS_BITS(termios, termio, x) { \ | ||
58 | unsigned short __tmp; \ | ||
59 | get_user(__tmp,&(termio)->x); \ | ||
60 | *(unsigned short *) &(termios)->x = __tmp; \ | ||
61 | } | ||
62 | |||
63 | #define user_termio_to_kernel_termios(termios, termio) \ | ||
64 | ({ \ | ||
65 | SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \ | ||
66 | SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \ | ||
67 | SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \ | ||
68 | SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \ | ||
69 | copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \ | ||
70 | }) | ||
71 | |||
72 | /* | ||
73 | * Translate a "termios" structure into a "termio". Ugh. | ||
74 | */ | ||
75 | #define kernel_termios_to_user_termio(termio, termios) \ | ||
76 | ({ \ | ||
77 | put_user((termios)->c_iflag, &(termio)->c_iflag); \ | ||
78 | put_user((termios)->c_oflag, &(termio)->c_oflag); \ | ||
79 | put_user((termios)->c_cflag, &(termio)->c_cflag); \ | ||
80 | put_user((termios)->c_lflag, &(termio)->c_lflag); \ | ||
81 | put_user((termios)->c_line, &(termio)->c_line); \ | ||
82 | copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ | ||
83 | }) | ||
84 | |||
85 | #define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2)) | ||
86 | #define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2)) | ||
87 | #define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) | ||
88 | #define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) | ||
89 | |||
90 | #endif /* __KERNEL__ */ | ||
91 | |||
92 | #endif /* __ASM_ARM_TERMIOS_H */ | ||
diff --git a/arch/arm/include/asm/therm.h b/arch/arm/include/asm/therm.h new file mode 100644 index 000000000000..f002f0197d78 --- /dev/null +++ b/arch/arm/include/asm/therm.h | |||
@@ -0,0 +1,28 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/therm.h: Definitions for Dallas Semiconductor | ||
3 | * DS1620 thermometer driver (as used in the Rebel.com NetWinder) | ||
4 | */ | ||
5 | #ifndef __ASM_THERM_H | ||
6 | #define __ASM_THERM_H | ||
7 | |||
8 | /* ioctl numbers for /dev/therm */ | ||
9 | #define CMD_SET_THERMOSTATE 0x53 | ||
10 | #define CMD_GET_THERMOSTATE 0x54 | ||
11 | #define CMD_GET_STATUS 0x56 | ||
12 | #define CMD_GET_TEMPERATURE 0x57 | ||
13 | #define CMD_SET_THERMOSTATE2 0x58 | ||
14 | #define CMD_GET_THERMOSTATE2 0x59 | ||
15 | #define CMD_GET_TEMPERATURE2 0x5a | ||
16 | #define CMD_GET_FAN 0x5b | ||
17 | #define CMD_SET_FAN 0x5c | ||
18 | |||
19 | #define FAN_OFF 0 | ||
20 | #define FAN_ON 1 | ||
21 | #define FAN_ALWAYS_ON 2 | ||
22 | |||
23 | struct therm { | ||
24 | int hi; | ||
25 | int lo; | ||
26 | }; | ||
27 | |||
28 | #endif | ||
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h new file mode 100644 index 000000000000..e56fa48e4ae7 --- /dev/null +++ b/arch/arm/include/asm/thread_info.h | |||
@@ -0,0 +1,153 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/thread_info.h | ||
3 | * | ||
4 | * Copyright (C) 2002 Russell King. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #ifndef __ASM_ARM_THREAD_INFO_H | ||
11 | #define __ASM_ARM_THREAD_INFO_H | ||
12 | |||
13 | #ifdef __KERNEL__ | ||
14 | |||
15 | #include <linux/compiler.h> | ||
16 | #include <asm/fpstate.h> | ||
17 | |||
18 | #define THREAD_SIZE_ORDER 1 | ||
19 | #define THREAD_SIZE 8192 | ||
20 | #define THREAD_START_SP (THREAD_SIZE - 8) | ||
21 | |||
22 | #ifndef __ASSEMBLY__ | ||
23 | |||
24 | struct task_struct; | ||
25 | struct exec_domain; | ||
26 | |||
27 | #include <asm/types.h> | ||
28 | #include <asm/domain.h> | ||
29 | |||
30 | typedef unsigned long mm_segment_t; | ||
31 | |||
32 | struct cpu_context_save { | ||
33 | __u32 r4; | ||
34 | __u32 r5; | ||
35 | __u32 r6; | ||
36 | __u32 r7; | ||
37 | __u32 r8; | ||
38 | __u32 r9; | ||
39 | __u32 sl; | ||
40 | __u32 fp; | ||
41 | __u32 sp; | ||
42 | __u32 pc; | ||
43 | __u32 extra[2]; /* Xscale 'acc' register, etc */ | ||
44 | }; | ||
45 | |||
46 | /* | ||
47 | * low level task data that entry.S needs immediate access to. | ||
48 | * __switch_to() assumes cpu_context follows immediately after cpu_domain. | ||
49 | */ | ||
50 | struct thread_info { | ||
51 | unsigned long flags; /* low level flags */ | ||
52 | int preempt_count; /* 0 => preemptable, <0 => bug */ | ||
53 | mm_segment_t addr_limit; /* address limit */ | ||
54 | struct task_struct *task; /* main task structure */ | ||
55 | struct exec_domain *exec_domain; /* execution domain */ | ||
56 | __u32 cpu; /* cpu */ | ||
57 | __u32 cpu_domain; /* cpu domain */ | ||
58 | struct cpu_context_save cpu_context; /* cpu context */ | ||
59 | __u32 syscall; /* syscall number */ | ||
60 | __u8 used_cp[16]; /* thread used copro */ | ||
61 | unsigned long tp_value; | ||
62 | struct crunch_state crunchstate; | ||
63 | union fp_state fpstate __attribute__((aligned(8))); | ||
64 | union vfp_state vfpstate; | ||
65 | #ifdef CONFIG_ARM_THUMBEE | ||
66 | unsigned long thumbee_state; /* ThumbEE Handler Base register */ | ||
67 | #endif | ||
68 | struct restart_block restart_block; | ||
69 | }; | ||
70 | |||
71 | #define INIT_THREAD_INFO(tsk) \ | ||
72 | { \ | ||
73 | .task = &tsk, \ | ||
74 | .exec_domain = &default_exec_domain, \ | ||
75 | .flags = 0, \ | ||
76 | .preempt_count = 1, \ | ||
77 | .addr_limit = KERNEL_DS, \ | ||
78 | .cpu_domain = domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \ | ||
79 | domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ | ||
80 | domain_val(DOMAIN_IO, DOMAIN_CLIENT), \ | ||
81 | .restart_block = { \ | ||
82 | .fn = do_no_restart_syscall, \ | ||
83 | }, \ | ||
84 | } | ||
85 | |||
86 | #define init_thread_info (init_thread_union.thread_info) | ||
87 | #define init_stack (init_thread_union.stack) | ||
88 | |||
89 | /* | ||
90 | * how to get the thread information struct from C | ||
91 | */ | ||
92 | static inline struct thread_info *current_thread_info(void) __attribute_const__; | ||
93 | |||
94 | static inline struct thread_info *current_thread_info(void) | ||
95 | { | ||
96 | register unsigned long sp asm ("sp"); | ||
97 | return (struct thread_info *)(sp & ~(THREAD_SIZE - 1)); | ||
98 | } | ||
99 | |||
100 | #define thread_saved_pc(tsk) \ | ||
101 | ((unsigned long)(pc_pointer(task_thread_info(tsk)->cpu_context.pc))) | ||
102 | #define thread_saved_fp(tsk) \ | ||
103 | ((unsigned long)(task_thread_info(tsk)->cpu_context.fp)) | ||
104 | |||
105 | extern void crunch_task_disable(struct thread_info *); | ||
106 | extern void crunch_task_copy(struct thread_info *, void *); | ||
107 | extern void crunch_task_restore(struct thread_info *, void *); | ||
108 | extern void crunch_task_release(struct thread_info *); | ||
109 | |||
110 | extern void iwmmxt_task_disable(struct thread_info *); | ||
111 | extern void iwmmxt_task_copy(struct thread_info *, void *); | ||
112 | extern void iwmmxt_task_restore(struct thread_info *, void *); | ||
113 | extern void iwmmxt_task_release(struct thread_info *); | ||
114 | extern void iwmmxt_task_switch(struct thread_info *); | ||
115 | |||
116 | #endif | ||
117 | |||
118 | /* | ||
119 | * We use bit 30 of the preempt_count to indicate that kernel | ||
120 | * preemption is occurring. See <asm/hardirq.h>. | ||
121 | */ | ||
122 | #define PREEMPT_ACTIVE 0x40000000 | ||
123 | |||
124 | /* | ||
125 | * thread information flags: | ||
126 | * TIF_SYSCALL_TRACE - syscall trace active | ||
127 | * TIF_SIGPENDING - signal pending | ||
128 | * TIF_NEED_RESCHED - rescheduling necessary | ||
129 | * TIF_USEDFPU - FPU was used by this task this quantum (SMP) | ||
130 | * TIF_POLLING_NRFLAG - true if poll_idle() is polling TIF_NEED_RESCHED | ||
131 | */ | ||
132 | #define TIF_SIGPENDING 0 | ||
133 | #define TIF_NEED_RESCHED 1 | ||
134 | #define TIF_SYSCALL_TRACE 8 | ||
135 | #define TIF_POLLING_NRFLAG 16 | ||
136 | #define TIF_USING_IWMMXT 17 | ||
137 | #define TIF_MEMDIE 18 | ||
138 | #define TIF_FREEZE 19 | ||
139 | |||
140 | #define _TIF_SIGPENDING (1 << TIF_SIGPENDING) | ||
141 | #define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) | ||
142 | #define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) | ||
143 | #define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG) | ||
144 | #define _TIF_USING_IWMMXT (1 << TIF_USING_IWMMXT) | ||
145 | #define _TIF_FREEZE (1 << TIF_FREEZE) | ||
146 | |||
147 | /* | ||
148 | * Change these and you break ASM code in entry-common.S | ||
149 | */ | ||
150 | #define _TIF_WORK_MASK 0x000000ff | ||
151 | |||
152 | #endif /* __KERNEL__ */ | ||
153 | #endif /* __ASM_ARM_THREAD_INFO_H */ | ||
diff --git a/arch/arm/include/asm/thread_notify.h b/arch/arm/include/asm/thread_notify.h new file mode 100644 index 000000000000..f27379d7f72a --- /dev/null +++ b/arch/arm/include/asm/thread_notify.h | |||
@@ -0,0 +1,48 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/thread_notify.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Russell King. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #ifndef ASMARM_THREAD_NOTIFY_H | ||
11 | #define ASMARM_THREAD_NOTIFY_H | ||
12 | |||
13 | #ifdef __KERNEL__ | ||
14 | |||
15 | #ifndef __ASSEMBLY__ | ||
16 | |||
17 | #include <linux/notifier.h> | ||
18 | #include <asm/thread_info.h> | ||
19 | |||
20 | static inline int thread_register_notifier(struct notifier_block *n) | ||
21 | { | ||
22 | extern struct atomic_notifier_head thread_notify_head; | ||
23 | return atomic_notifier_chain_register(&thread_notify_head, n); | ||
24 | } | ||
25 | |||
26 | static inline void thread_unregister_notifier(struct notifier_block *n) | ||
27 | { | ||
28 | extern struct atomic_notifier_head thread_notify_head; | ||
29 | atomic_notifier_chain_unregister(&thread_notify_head, n); | ||
30 | } | ||
31 | |||
32 | static inline void thread_notify(unsigned long rc, struct thread_info *thread) | ||
33 | { | ||
34 | extern struct atomic_notifier_head thread_notify_head; | ||
35 | atomic_notifier_call_chain(&thread_notify_head, rc, thread); | ||
36 | } | ||
37 | |||
38 | #endif | ||
39 | |||
40 | /* | ||
41 | * These are the reason codes for the thread notifier. | ||
42 | */ | ||
43 | #define THREAD_NOTIFY_FLUSH 0 | ||
44 | #define THREAD_NOTIFY_RELEASE 1 | ||
45 | #define THREAD_NOTIFY_SWITCH 2 | ||
46 | |||
47 | #endif | ||
48 | #endif | ||
diff --git a/arch/arm/include/asm/timex.h b/arch/arm/include/asm/timex.h new file mode 100644 index 000000000000..e50e2926cd6e --- /dev/null +++ b/arch/arm/include/asm/timex.h | |||
@@ -0,0 +1,24 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/timex.h | ||
3 | * | ||
4 | * Copyright (C) 1997,1998 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * Architecture Specific TIME specifications | ||
11 | */ | ||
12 | #ifndef _ASMARM_TIMEX_H | ||
13 | #define _ASMARM_TIMEX_H | ||
14 | |||
15 | #include <asm/arch/timex.h> | ||
16 | |||
17 | typedef unsigned long cycles_t; | ||
18 | |||
19 | static inline cycles_t get_cycles (void) | ||
20 | { | ||
21 | return 0; | ||
22 | } | ||
23 | |||
24 | #endif | ||
diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h new file mode 100644 index 000000000000..857f1dfac794 --- /dev/null +++ b/arch/arm/include/asm/tlb.h | |||
@@ -0,0 +1,94 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/tlb.h | ||
3 | * | ||
4 | * Copyright (C) 2002 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * Experimentation shows that on a StrongARM, it appears to be faster | ||
11 | * to use the "invalidate whole tlb" rather than "invalidate single | ||
12 | * tlb" for this. | ||
13 | * | ||
14 | * This appears true for both the process fork+exit case, as well as | ||
15 | * the munmap-large-area case. | ||
16 | */ | ||
17 | #ifndef __ASMARM_TLB_H | ||
18 | #define __ASMARM_TLB_H | ||
19 | |||
20 | #include <asm/cacheflush.h> | ||
21 | #include <asm/tlbflush.h> | ||
22 | |||
23 | #ifndef CONFIG_MMU | ||
24 | |||
25 | #include <linux/pagemap.h> | ||
26 | #include <asm-generic/tlb.h> | ||
27 | |||
28 | #else /* !CONFIG_MMU */ | ||
29 | |||
30 | #include <asm/pgalloc.h> | ||
31 | |||
32 | /* | ||
33 | * TLB handling. This allows us to remove pages from the page | ||
34 | * tables, and efficiently handle the TLB issues. | ||
35 | */ | ||
36 | struct mmu_gather { | ||
37 | struct mm_struct *mm; | ||
38 | unsigned int fullmm; | ||
39 | }; | ||
40 | |||
41 | DECLARE_PER_CPU(struct mmu_gather, mmu_gathers); | ||
42 | |||
43 | static inline struct mmu_gather * | ||
44 | tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush) | ||
45 | { | ||
46 | struct mmu_gather *tlb = &get_cpu_var(mmu_gathers); | ||
47 | |||
48 | tlb->mm = mm; | ||
49 | tlb->fullmm = full_mm_flush; | ||
50 | |||
51 | return tlb; | ||
52 | } | ||
53 | |||
54 | static inline void | ||
55 | tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end) | ||
56 | { | ||
57 | if (tlb->fullmm) | ||
58 | flush_tlb_mm(tlb->mm); | ||
59 | |||
60 | /* keep the page table cache within bounds */ | ||
61 | check_pgt_cache(); | ||
62 | |||
63 | put_cpu_var(mmu_gathers); | ||
64 | } | ||
65 | |||
66 | #define tlb_remove_tlb_entry(tlb,ptep,address) do { } while (0) | ||
67 | |||
68 | /* | ||
69 | * In the case of tlb vma handling, we can optimise these away in the | ||
70 | * case where we're doing a full MM flush. When we're doing a munmap, | ||
71 | * the vmas are adjusted to only cover the region to be torn down. | ||
72 | */ | ||
73 | static inline void | ||
74 | tlb_start_vma(struct mmu_gather *tlb, struct vm_area_struct *vma) | ||
75 | { | ||
76 | if (!tlb->fullmm) | ||
77 | flush_cache_range(vma, vma->vm_start, vma->vm_end); | ||
78 | } | ||
79 | |||
80 | static inline void | ||
81 | tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma) | ||
82 | { | ||
83 | if (!tlb->fullmm) | ||
84 | flush_tlb_range(vma, vma->vm_start, vma->vm_end); | ||
85 | } | ||
86 | |||
87 | #define tlb_remove_page(tlb,page) free_page_and_swap_cache(page) | ||
88 | #define pte_free_tlb(tlb, ptep) pte_free((tlb)->mm, ptep) | ||
89 | #define pmd_free_tlb(tlb, pmdp) pmd_free((tlb)->mm, pmdp) | ||
90 | |||
91 | #define tlb_migrate_finish(mm) do { } while (0) | ||
92 | |||
93 | #endif /* CONFIG_MMU */ | ||
94 | #endif | ||
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h new file mode 100644 index 000000000000..0d0d40f1b599 --- /dev/null +++ b/arch/arm/include/asm/tlbflush.h | |||
@@ -0,0 +1,500 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/tlbflush.h | ||
3 | * | ||
4 | * Copyright (C) 1999-2003 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #ifndef _ASMARM_TLBFLUSH_H | ||
11 | #define _ASMARM_TLBFLUSH_H | ||
12 | |||
13 | |||
14 | #ifndef CONFIG_MMU | ||
15 | |||
16 | #define tlb_flush(tlb) ((void) tlb) | ||
17 | |||
18 | #else /* CONFIG_MMU */ | ||
19 | |||
20 | #include <asm/glue.h> | ||
21 | |||
22 | #define TLB_V3_PAGE (1 << 0) | ||
23 | #define TLB_V4_U_PAGE (1 << 1) | ||
24 | #define TLB_V4_D_PAGE (1 << 2) | ||
25 | #define TLB_V4_I_PAGE (1 << 3) | ||
26 | #define TLB_V6_U_PAGE (1 << 4) | ||
27 | #define TLB_V6_D_PAGE (1 << 5) | ||
28 | #define TLB_V6_I_PAGE (1 << 6) | ||
29 | |||
30 | #define TLB_V3_FULL (1 << 8) | ||
31 | #define TLB_V4_U_FULL (1 << 9) | ||
32 | #define TLB_V4_D_FULL (1 << 10) | ||
33 | #define TLB_V4_I_FULL (1 << 11) | ||
34 | #define TLB_V6_U_FULL (1 << 12) | ||
35 | #define TLB_V6_D_FULL (1 << 13) | ||
36 | #define TLB_V6_I_FULL (1 << 14) | ||
37 | |||
38 | #define TLB_V6_U_ASID (1 << 16) | ||
39 | #define TLB_V6_D_ASID (1 << 17) | ||
40 | #define TLB_V6_I_ASID (1 << 18) | ||
41 | |||
42 | #define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */ | ||
43 | #define TLB_DCLEAN (1 << 30) | ||
44 | #define TLB_WB (1 << 31) | ||
45 | |||
46 | /* | ||
47 | * MMU TLB Model | ||
48 | * ============= | ||
49 | * | ||
50 | * We have the following to choose from: | ||
51 | * v3 - ARMv3 | ||
52 | * v4 - ARMv4 without write buffer | ||
53 | * v4wb - ARMv4 with write buffer without I TLB flush entry instruction | ||
54 | * v4wbi - ARMv4 with write buffer with I TLB flush entry instruction | ||
55 | * fr - Feroceon (v4wbi with non-outer-cacheable page table walks) | ||
56 | * v6wbi - ARMv6 with write buffer with I TLB flush entry instruction | ||
57 | */ | ||
58 | #undef _TLB | ||
59 | #undef MULTI_TLB | ||
60 | |||
61 | #define v3_tlb_flags (TLB_V3_FULL | TLB_V3_PAGE) | ||
62 | |||
63 | #ifdef CONFIG_CPU_TLB_V3 | ||
64 | # define v3_possible_flags v3_tlb_flags | ||
65 | # define v3_always_flags v3_tlb_flags | ||
66 | # ifdef _TLB | ||
67 | # define MULTI_TLB 1 | ||
68 | # else | ||
69 | # define _TLB v3 | ||
70 | # endif | ||
71 | #else | ||
72 | # define v3_possible_flags 0 | ||
73 | # define v3_always_flags (-1UL) | ||
74 | #endif | ||
75 | |||
76 | #define v4_tlb_flags (TLB_V4_U_FULL | TLB_V4_U_PAGE) | ||
77 | |||
78 | #ifdef CONFIG_CPU_TLB_V4WT | ||
79 | # define v4_possible_flags v4_tlb_flags | ||
80 | # define v4_always_flags v4_tlb_flags | ||
81 | # ifdef _TLB | ||
82 | # define MULTI_TLB 1 | ||
83 | # else | ||
84 | # define _TLB v4 | ||
85 | # endif | ||
86 | #else | ||
87 | # define v4_possible_flags 0 | ||
88 | # define v4_always_flags (-1UL) | ||
89 | #endif | ||
90 | |||
91 | #define v4wbi_tlb_flags (TLB_WB | TLB_DCLEAN | \ | ||
92 | TLB_V4_I_FULL | TLB_V4_D_FULL | \ | ||
93 | TLB_V4_I_PAGE | TLB_V4_D_PAGE) | ||
94 | |||
95 | #ifdef CONFIG_CPU_TLB_V4WBI | ||
96 | # define v4wbi_possible_flags v4wbi_tlb_flags | ||
97 | # define v4wbi_always_flags v4wbi_tlb_flags | ||
98 | # ifdef _TLB | ||
99 | # define MULTI_TLB 1 | ||
100 | # else | ||
101 | # define _TLB v4wbi | ||
102 | # endif | ||
103 | #else | ||
104 | # define v4wbi_possible_flags 0 | ||
105 | # define v4wbi_always_flags (-1UL) | ||
106 | #endif | ||
107 | |||
108 | #define fr_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_L2CLEAN_FR | \ | ||
109 | TLB_V4_I_FULL | TLB_V4_D_FULL | \ | ||
110 | TLB_V4_I_PAGE | TLB_V4_D_PAGE) | ||
111 | |||
112 | #ifdef CONFIG_CPU_TLB_FEROCEON | ||
113 | # define fr_possible_flags fr_tlb_flags | ||
114 | # define fr_always_flags fr_tlb_flags | ||
115 | # ifdef _TLB | ||
116 | # define MULTI_TLB 1 | ||
117 | # else | ||
118 | # define _TLB v4wbi | ||
119 | # endif | ||
120 | #else | ||
121 | # define fr_possible_flags 0 | ||
122 | # define fr_always_flags (-1UL) | ||
123 | #endif | ||
124 | |||
125 | #define v4wb_tlb_flags (TLB_WB | TLB_DCLEAN | \ | ||
126 | TLB_V4_I_FULL | TLB_V4_D_FULL | \ | ||
127 | TLB_V4_D_PAGE) | ||
128 | |||
129 | #ifdef CONFIG_CPU_TLB_V4WB | ||
130 | # define v4wb_possible_flags v4wb_tlb_flags | ||
131 | # define v4wb_always_flags v4wb_tlb_flags | ||
132 | # ifdef _TLB | ||
133 | # define MULTI_TLB 1 | ||
134 | # else | ||
135 | # define _TLB v4wb | ||
136 | # endif | ||
137 | #else | ||
138 | # define v4wb_possible_flags 0 | ||
139 | # define v4wb_always_flags (-1UL) | ||
140 | #endif | ||
141 | |||
142 | #define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | \ | ||
143 | TLB_V6_I_FULL | TLB_V6_D_FULL | \ | ||
144 | TLB_V6_I_PAGE | TLB_V6_D_PAGE | \ | ||
145 | TLB_V6_I_ASID | TLB_V6_D_ASID) | ||
146 | |||
147 | #ifdef CONFIG_CPU_TLB_V6 | ||
148 | # define v6wbi_possible_flags v6wbi_tlb_flags | ||
149 | # define v6wbi_always_flags v6wbi_tlb_flags | ||
150 | # ifdef _TLB | ||
151 | # define MULTI_TLB 1 | ||
152 | # else | ||
153 | # define _TLB v6wbi | ||
154 | # endif | ||
155 | #else | ||
156 | # define v6wbi_possible_flags 0 | ||
157 | # define v6wbi_always_flags (-1UL) | ||
158 | #endif | ||
159 | |||
160 | #ifdef CONFIG_CPU_TLB_V7 | ||
161 | # define v7wbi_possible_flags v6wbi_tlb_flags | ||
162 | # define v7wbi_always_flags v6wbi_tlb_flags | ||
163 | # ifdef _TLB | ||
164 | # define MULTI_TLB 1 | ||
165 | # else | ||
166 | # define _TLB v7wbi | ||
167 | # endif | ||
168 | #else | ||
169 | # define v7wbi_possible_flags 0 | ||
170 | # define v7wbi_always_flags (-1UL) | ||
171 | #endif | ||
172 | |||
173 | #ifndef _TLB | ||
174 | #error Unknown TLB model | ||
175 | #endif | ||
176 | |||
177 | #ifndef __ASSEMBLY__ | ||
178 | |||
179 | #include <linux/sched.h> | ||
180 | |||
181 | struct cpu_tlb_fns { | ||
182 | void (*flush_user_range)(unsigned long, unsigned long, struct vm_area_struct *); | ||
183 | void (*flush_kern_range)(unsigned long, unsigned long); | ||
184 | unsigned long tlb_flags; | ||
185 | }; | ||
186 | |||
187 | /* | ||
188 | * Select the calling method | ||
189 | */ | ||
190 | #ifdef MULTI_TLB | ||
191 | |||
192 | #define __cpu_flush_user_tlb_range cpu_tlb.flush_user_range | ||
193 | #define __cpu_flush_kern_tlb_range cpu_tlb.flush_kern_range | ||
194 | |||
195 | #else | ||
196 | |||
197 | #define __cpu_flush_user_tlb_range __glue(_TLB,_flush_user_tlb_range) | ||
198 | #define __cpu_flush_kern_tlb_range __glue(_TLB,_flush_kern_tlb_range) | ||
199 | |||
200 | extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long, struct vm_area_struct *); | ||
201 | extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long); | ||
202 | |||
203 | #endif | ||
204 | |||
205 | extern struct cpu_tlb_fns cpu_tlb; | ||
206 | |||
207 | #define __cpu_tlb_flags cpu_tlb.tlb_flags | ||
208 | |||
209 | /* | ||
210 | * TLB Management | ||
211 | * ============== | ||
212 | * | ||
213 | * The arch/arm/mm/tlb-*.S files implement these methods. | ||
214 | * | ||
215 | * The TLB specific code is expected to perform whatever tests it | ||
216 | * needs to determine if it should invalidate the TLB for each | ||
217 | * call. Start addresses are inclusive and end addresses are | ||
218 | * exclusive; it is safe to round these addresses down. | ||
219 | * | ||
220 | * flush_tlb_all() | ||
221 | * | ||
222 | * Invalidate the entire TLB. | ||
223 | * | ||
224 | * flush_tlb_mm(mm) | ||
225 | * | ||
226 | * Invalidate all TLB entries in a particular address | ||
227 | * space. | ||
228 | * - mm - mm_struct describing address space | ||
229 | * | ||
230 | * flush_tlb_range(mm,start,end) | ||
231 | * | ||
232 | * Invalidate a range of TLB entries in the specified | ||
233 | * address space. | ||
234 | * - mm - mm_struct describing address space | ||
235 | * - start - start address (may not be aligned) | ||
236 | * - end - end address (exclusive, may not be aligned) | ||
237 | * | ||
238 | * flush_tlb_page(vaddr,vma) | ||
239 | * | ||
240 | * Invalidate the specified page in the specified address range. | ||
241 | * - vaddr - virtual address (may not be aligned) | ||
242 | * - vma - vma_struct describing address range | ||
243 | * | ||
244 | * flush_kern_tlb_page(kaddr) | ||
245 | * | ||
246 | * Invalidate the TLB entry for the specified page. The address | ||
247 | * will be in the kernels virtual memory space. Current uses | ||
248 | * only require the D-TLB to be invalidated. | ||
249 | * - kaddr - Kernel virtual memory address | ||
250 | */ | ||
251 | |||
252 | /* | ||
253 | * We optimise the code below by: | ||
254 | * - building a set of TLB flags that might be set in __cpu_tlb_flags | ||
255 | * - building a set of TLB flags that will always be set in __cpu_tlb_flags | ||
256 | * - if we're going to need __cpu_tlb_flags, access it once and only once | ||
257 | * | ||
258 | * This allows us to build optimal assembly for the single-CPU type case, | ||
259 | * and as close to optimal given the compiler constrants for multi-CPU | ||
260 | * case. We could do better for the multi-CPU case if the compiler | ||
261 | * implemented the "%?" method, but this has been discontinued due to too | ||
262 | * many people getting it wrong. | ||
263 | */ | ||
264 | #define possible_tlb_flags (v3_possible_flags | \ | ||
265 | v4_possible_flags | \ | ||
266 | v4wbi_possible_flags | \ | ||
267 | fr_possible_flags | \ | ||
268 | v4wb_possible_flags | \ | ||
269 | v6wbi_possible_flags) | ||
270 | |||
271 | #define always_tlb_flags (v3_always_flags & \ | ||
272 | v4_always_flags & \ | ||
273 | v4wbi_always_flags & \ | ||
274 | fr_always_flags & \ | ||
275 | v4wb_always_flags & \ | ||
276 | v6wbi_always_flags) | ||
277 | |||
278 | #define tlb_flag(f) ((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f))) | ||
279 | |||
280 | static inline void local_flush_tlb_all(void) | ||
281 | { | ||
282 | const int zero = 0; | ||
283 | const unsigned int __tlb_flag = __cpu_tlb_flags; | ||
284 | |||
285 | if (tlb_flag(TLB_WB)) | ||
286 | dsb(); | ||
287 | |||
288 | if (tlb_flag(TLB_V3_FULL)) | ||
289 | asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc"); | ||
290 | if (tlb_flag(TLB_V4_U_FULL | TLB_V6_U_FULL)) | ||
291 | asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc"); | ||
292 | if (tlb_flag(TLB_V4_D_FULL | TLB_V6_D_FULL)) | ||
293 | asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc"); | ||
294 | if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL)) | ||
295 | asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); | ||
296 | |||
297 | if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL | | ||
298 | TLB_V6_I_PAGE | TLB_V6_D_PAGE | | ||
299 | TLB_V6_I_ASID | TLB_V6_D_ASID)) { | ||
300 | /* flush the branch target cache */ | ||
301 | asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); | ||
302 | dsb(); | ||
303 | isb(); | ||
304 | } | ||
305 | } | ||
306 | |||
307 | static inline void local_flush_tlb_mm(struct mm_struct *mm) | ||
308 | { | ||
309 | const int zero = 0; | ||
310 | const int asid = ASID(mm); | ||
311 | const unsigned int __tlb_flag = __cpu_tlb_flags; | ||
312 | |||
313 | if (tlb_flag(TLB_WB)) | ||
314 | dsb(); | ||
315 | |||
316 | if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask)) { | ||
317 | if (tlb_flag(TLB_V3_FULL)) | ||
318 | asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc"); | ||
319 | if (tlb_flag(TLB_V4_U_FULL)) | ||
320 | asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc"); | ||
321 | if (tlb_flag(TLB_V4_D_FULL)) | ||
322 | asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc"); | ||
323 | if (tlb_flag(TLB_V4_I_FULL)) | ||
324 | asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); | ||
325 | } | ||
326 | |||
327 | if (tlb_flag(TLB_V6_U_ASID)) | ||
328 | asm("mcr p15, 0, %0, c8, c7, 2" : : "r" (asid) : "cc"); | ||
329 | if (tlb_flag(TLB_V6_D_ASID)) | ||
330 | asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc"); | ||
331 | if (tlb_flag(TLB_V6_I_ASID)) | ||
332 | asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc"); | ||
333 | |||
334 | if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL | | ||
335 | TLB_V6_I_PAGE | TLB_V6_D_PAGE | | ||
336 | TLB_V6_I_ASID | TLB_V6_D_ASID)) { | ||
337 | /* flush the branch target cache */ | ||
338 | asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); | ||
339 | dsb(); | ||
340 | } | ||
341 | } | ||
342 | |||
343 | static inline void | ||
344 | local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) | ||
345 | { | ||
346 | const int zero = 0; | ||
347 | const unsigned int __tlb_flag = __cpu_tlb_flags; | ||
348 | |||
349 | uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm); | ||
350 | |||
351 | if (tlb_flag(TLB_WB)) | ||
352 | dsb(); | ||
353 | |||
354 | if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) { | ||
355 | if (tlb_flag(TLB_V3_PAGE)) | ||
356 | asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (uaddr) : "cc"); | ||
357 | if (tlb_flag(TLB_V4_U_PAGE)) | ||
358 | asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc"); | ||
359 | if (tlb_flag(TLB_V4_D_PAGE)) | ||
360 | asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc"); | ||
361 | if (tlb_flag(TLB_V4_I_PAGE)) | ||
362 | asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc"); | ||
363 | if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL)) | ||
364 | asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); | ||
365 | } | ||
366 | |||
367 | if (tlb_flag(TLB_V6_U_PAGE)) | ||
368 | asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc"); | ||
369 | if (tlb_flag(TLB_V6_D_PAGE)) | ||
370 | asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc"); | ||
371 | if (tlb_flag(TLB_V6_I_PAGE)) | ||
372 | asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc"); | ||
373 | |||
374 | if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL | | ||
375 | TLB_V6_I_PAGE | TLB_V6_D_PAGE | | ||
376 | TLB_V6_I_ASID | TLB_V6_D_ASID)) { | ||
377 | /* flush the branch target cache */ | ||
378 | asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); | ||
379 | dsb(); | ||
380 | } | ||
381 | } | ||
382 | |||
383 | static inline void local_flush_tlb_kernel_page(unsigned long kaddr) | ||
384 | { | ||
385 | const int zero = 0; | ||
386 | const unsigned int __tlb_flag = __cpu_tlb_flags; | ||
387 | |||
388 | kaddr &= PAGE_MASK; | ||
389 | |||
390 | if (tlb_flag(TLB_WB)) | ||
391 | dsb(); | ||
392 | |||
393 | if (tlb_flag(TLB_V3_PAGE)) | ||
394 | asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (kaddr) : "cc"); | ||
395 | if (tlb_flag(TLB_V4_U_PAGE)) | ||
396 | asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc"); | ||
397 | if (tlb_flag(TLB_V4_D_PAGE)) | ||
398 | asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc"); | ||
399 | if (tlb_flag(TLB_V4_I_PAGE)) | ||
400 | asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc"); | ||
401 | if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL)) | ||
402 | asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); | ||
403 | |||
404 | if (tlb_flag(TLB_V6_U_PAGE)) | ||
405 | asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc"); | ||
406 | if (tlb_flag(TLB_V6_D_PAGE)) | ||
407 | asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc"); | ||
408 | if (tlb_flag(TLB_V6_I_PAGE)) | ||
409 | asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc"); | ||
410 | |||
411 | if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL | | ||
412 | TLB_V6_I_PAGE | TLB_V6_D_PAGE | | ||
413 | TLB_V6_I_ASID | TLB_V6_D_ASID)) { | ||
414 | /* flush the branch target cache */ | ||
415 | asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); | ||
416 | dsb(); | ||
417 | isb(); | ||
418 | } | ||
419 | } | ||
420 | |||
421 | /* | ||
422 | * flush_pmd_entry | ||
423 | * | ||
424 | * Flush a PMD entry (word aligned, or double-word aligned) to | ||
425 | * RAM if the TLB for the CPU we are running on requires this. | ||
426 | * This is typically used when we are creating PMD entries. | ||
427 | * | ||
428 | * clean_pmd_entry | ||
429 | * | ||
430 | * Clean (but don't drain the write buffer) if the CPU requires | ||
431 | * these operations. This is typically used when we are removing | ||
432 | * PMD entries. | ||
433 | */ | ||
434 | static inline void flush_pmd_entry(pmd_t *pmd) | ||
435 | { | ||
436 | const unsigned int __tlb_flag = __cpu_tlb_flags; | ||
437 | |||
438 | if (tlb_flag(TLB_DCLEAN)) | ||
439 | asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd" | ||
440 | : : "r" (pmd) : "cc"); | ||
441 | |||
442 | if (tlb_flag(TLB_L2CLEAN_FR)) | ||
443 | asm("mcr p15, 1, %0, c15, c9, 1 @ L2 flush_pmd" | ||
444 | : : "r" (pmd) : "cc"); | ||
445 | |||
446 | if (tlb_flag(TLB_WB)) | ||
447 | dsb(); | ||
448 | } | ||
449 | |||
450 | static inline void clean_pmd_entry(pmd_t *pmd) | ||
451 | { | ||
452 | const unsigned int __tlb_flag = __cpu_tlb_flags; | ||
453 | |||
454 | if (tlb_flag(TLB_DCLEAN)) | ||
455 | asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd" | ||
456 | : : "r" (pmd) : "cc"); | ||
457 | |||
458 | if (tlb_flag(TLB_L2CLEAN_FR)) | ||
459 | asm("mcr p15, 1, %0, c15, c9, 1 @ L2 flush_pmd" | ||
460 | : : "r" (pmd) : "cc"); | ||
461 | } | ||
462 | |||
463 | #undef tlb_flag | ||
464 | #undef always_tlb_flags | ||
465 | #undef possible_tlb_flags | ||
466 | |||
467 | /* | ||
468 | * Convert calls to our calling convention. | ||
469 | */ | ||
470 | #define local_flush_tlb_range(vma,start,end) __cpu_flush_user_tlb_range(start,end,vma) | ||
471 | #define local_flush_tlb_kernel_range(s,e) __cpu_flush_kern_tlb_range(s,e) | ||
472 | |||
473 | #ifndef CONFIG_SMP | ||
474 | #define flush_tlb_all local_flush_tlb_all | ||
475 | #define flush_tlb_mm local_flush_tlb_mm | ||
476 | #define flush_tlb_page local_flush_tlb_page | ||
477 | #define flush_tlb_kernel_page local_flush_tlb_kernel_page | ||
478 | #define flush_tlb_range local_flush_tlb_range | ||
479 | #define flush_tlb_kernel_range local_flush_tlb_kernel_range | ||
480 | #else | ||
481 | extern void flush_tlb_all(void); | ||
482 | extern void flush_tlb_mm(struct mm_struct *mm); | ||
483 | extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr); | ||
484 | extern void flush_tlb_kernel_page(unsigned long kaddr); | ||
485 | extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); | ||
486 | extern void flush_tlb_kernel_range(unsigned long start, unsigned long end); | ||
487 | #endif | ||
488 | |||
489 | /* | ||
490 | * if PG_dcache_dirty is set for the page, we need to ensure that any | ||
491 | * cache entries for the kernels virtual memory range are written | ||
492 | * back to the page. | ||
493 | */ | ||
494 | extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte); | ||
495 | |||
496 | #endif | ||
497 | |||
498 | #endif /* CONFIG_MMU */ | ||
499 | |||
500 | #endif | ||
diff --git a/arch/arm/include/asm/topology.h b/arch/arm/include/asm/topology.h new file mode 100644 index 000000000000..accbd7cad9b5 --- /dev/null +++ b/arch/arm/include/asm/topology.h | |||
@@ -0,0 +1,6 @@ | |||
1 | #ifndef _ASM_ARM_TOPOLOGY_H | ||
2 | #define _ASM_ARM_TOPOLOGY_H | ||
3 | |||
4 | #include <asm-generic/topology.h> | ||
5 | |||
6 | #endif /* _ASM_ARM_TOPOLOGY_H */ | ||
diff --git a/arch/arm/include/asm/traps.h b/arch/arm/include/asm/traps.h new file mode 100644 index 000000000000..aa399aec568e --- /dev/null +++ b/arch/arm/include/asm/traps.h | |||
@@ -0,0 +1,29 @@ | |||
1 | #ifndef _ASMARM_TRAP_H | ||
2 | #define _ASMARM_TRAP_H | ||
3 | |||
4 | #include <linux/list.h> | ||
5 | |||
6 | struct undef_hook { | ||
7 | struct list_head node; | ||
8 | u32 instr_mask; | ||
9 | u32 instr_val; | ||
10 | u32 cpsr_mask; | ||
11 | u32 cpsr_val; | ||
12 | int (*fn)(struct pt_regs *regs, unsigned int instr); | ||
13 | }; | ||
14 | |||
15 | void register_undef_hook(struct undef_hook *hook); | ||
16 | void unregister_undef_hook(struct undef_hook *hook); | ||
17 | |||
18 | static inline int in_exception_text(unsigned long ptr) | ||
19 | { | ||
20 | extern char __exception_text_start[]; | ||
21 | extern char __exception_text_end[]; | ||
22 | |||
23 | return ptr >= (unsigned long)&__exception_text_start && | ||
24 | ptr < (unsigned long)&__exception_text_end; | ||
25 | } | ||
26 | |||
27 | extern void __init early_trap_init(void); | ||
28 | |||
29 | #endif | ||
diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h new file mode 100644 index 000000000000..345df01534a4 --- /dev/null +++ b/arch/arm/include/asm/types.h | |||
@@ -0,0 +1,31 @@ | |||
1 | #ifndef __ASM_ARM_TYPES_H | ||
2 | #define __ASM_ARM_TYPES_H | ||
3 | |||
4 | #include <asm-generic/int-ll64.h> | ||
5 | |||
6 | #ifndef __ASSEMBLY__ | ||
7 | |||
8 | typedef unsigned short umode_t; | ||
9 | |||
10 | #endif /* __ASSEMBLY__ */ | ||
11 | |||
12 | /* | ||
13 | * These aren't exported outside the kernel to avoid name space clashes | ||
14 | */ | ||
15 | #ifdef __KERNEL__ | ||
16 | |||
17 | #define BITS_PER_LONG 32 | ||
18 | |||
19 | #ifndef __ASSEMBLY__ | ||
20 | |||
21 | /* Dma addresses are 32-bits wide. */ | ||
22 | |||
23 | typedef u32 dma_addr_t; | ||
24 | typedef u32 dma64_addr_t; | ||
25 | |||
26 | #endif /* __ASSEMBLY__ */ | ||
27 | |||
28 | #endif /* __KERNEL__ */ | ||
29 | |||
30 | #endif | ||
31 | |||
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h new file mode 100644 index 000000000000..d0f51ff900b5 --- /dev/null +++ b/arch/arm/include/asm/uaccess.h | |||
@@ -0,0 +1,444 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/uaccess.h | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License version 2 as | ||
6 | * published by the Free Software Foundation. | ||
7 | */ | ||
8 | #ifndef _ASMARM_UACCESS_H | ||
9 | #define _ASMARM_UACCESS_H | ||
10 | |||
11 | /* | ||
12 | * User space memory access functions | ||
13 | */ | ||
14 | #include <linux/sched.h> | ||
15 | #include <asm/errno.h> | ||
16 | #include <asm/memory.h> | ||
17 | #include <asm/domain.h> | ||
18 | #include <asm/system.h> | ||
19 | |||
20 | #define VERIFY_READ 0 | ||
21 | #define VERIFY_WRITE 1 | ||
22 | |||
23 | /* | ||
24 | * The exception table consists of pairs of addresses: the first is the | ||
25 | * address of an instruction that is allowed to fault, and the second is | ||
26 | * the address at which the program should continue. No registers are | ||
27 | * modified, so it is entirely up to the continuation code to figure out | ||
28 | * what to do. | ||
29 | * | ||
30 | * All the routines below use bits of fixup code that are out of line | ||
31 | * with the main instruction path. This means when everything is well, | ||
32 | * we don't even have to jump over them. Further, they do not intrude | ||
33 | * on our cache or tlb entries. | ||
34 | */ | ||
35 | |||
36 | struct exception_table_entry | ||
37 | { | ||
38 | unsigned long insn, fixup; | ||
39 | }; | ||
40 | |||
41 | extern int fixup_exception(struct pt_regs *regs); | ||
42 | |||
43 | /* | ||
44 | * These two are intentionally not defined anywhere - if the kernel | ||
45 | * code generates any references to them, that's a bug. | ||
46 | */ | ||
47 | extern int __get_user_bad(void); | ||
48 | extern int __put_user_bad(void); | ||
49 | |||
50 | /* | ||
51 | * Note that this is actually 0x1,0000,0000 | ||
52 | */ | ||
53 | #define KERNEL_DS 0x00000000 | ||
54 | #define get_ds() (KERNEL_DS) | ||
55 | |||
56 | #ifdef CONFIG_MMU | ||
57 | |||
58 | #define USER_DS TASK_SIZE | ||
59 | #define get_fs() (current_thread_info()->addr_limit) | ||
60 | |||
61 | static inline void set_fs(mm_segment_t fs) | ||
62 | { | ||
63 | current_thread_info()->addr_limit = fs; | ||
64 | modify_domain(DOMAIN_KERNEL, fs ? DOMAIN_CLIENT : DOMAIN_MANAGER); | ||
65 | } | ||
66 | |||
67 | #define segment_eq(a,b) ((a) == (b)) | ||
68 | |||
69 | #define __addr_ok(addr) ({ \ | ||
70 | unsigned long flag; \ | ||
71 | __asm__("cmp %2, %0; movlo %0, #0" \ | ||
72 | : "=&r" (flag) \ | ||
73 | : "0" (current_thread_info()->addr_limit), "r" (addr) \ | ||
74 | : "cc"); \ | ||
75 | (flag == 0); }) | ||
76 | |||
77 | /* We use 33-bit arithmetic here... */ | ||
78 | #define __range_ok(addr,size) ({ \ | ||
79 | unsigned long flag, roksum; \ | ||
80 | __chk_user_ptr(addr); \ | ||
81 | __asm__("adds %1, %2, %3; sbcccs %1, %1, %0; movcc %0, #0" \ | ||
82 | : "=&r" (flag), "=&r" (roksum) \ | ||
83 | : "r" (addr), "Ir" (size), "0" (current_thread_info()->addr_limit) \ | ||
84 | : "cc"); \ | ||
85 | flag; }) | ||
86 | |||
87 | /* | ||
88 | * Single-value transfer routines. They automatically use the right | ||
89 | * size if we just have the right pointer type. Note that the functions | ||
90 | * which read from user space (*get_*) need to take care not to leak | ||
91 | * kernel data even if the calling code is buggy and fails to check | ||
92 | * the return value. This means zeroing out the destination variable | ||
93 | * or buffer on error. Normally this is done out of line by the | ||
94 | * fixup code, but there are a few places where it intrudes on the | ||
95 | * main code path. When we only write to user space, there is no | ||
96 | * problem. | ||
97 | */ | ||
98 | extern int __get_user_1(void *); | ||
99 | extern int __get_user_2(void *); | ||
100 | extern int __get_user_4(void *); | ||
101 | |||
102 | #define __get_user_x(__r2,__p,__e,__s,__i...) \ | ||
103 | __asm__ __volatile__ ( \ | ||
104 | __asmeq("%0", "r0") __asmeq("%1", "r2") \ | ||
105 | "bl __get_user_" #__s \ | ||
106 | : "=&r" (__e), "=r" (__r2) \ | ||
107 | : "0" (__p) \ | ||
108 | : __i, "cc") | ||
109 | |||
110 | #define get_user(x,p) \ | ||
111 | ({ \ | ||
112 | register const typeof(*(p)) __user *__p asm("r0") = (p);\ | ||
113 | register unsigned long __r2 asm("r2"); \ | ||
114 | register int __e asm("r0"); \ | ||
115 | switch (sizeof(*(__p))) { \ | ||
116 | case 1: \ | ||
117 | __get_user_x(__r2, __p, __e, 1, "lr"); \ | ||
118 | break; \ | ||
119 | case 2: \ | ||
120 | __get_user_x(__r2, __p, __e, 2, "r3", "lr"); \ | ||
121 | break; \ | ||
122 | case 4: \ | ||
123 | __get_user_x(__r2, __p, __e, 4, "lr"); \ | ||
124 | break; \ | ||
125 | default: __e = __get_user_bad(); break; \ | ||
126 | } \ | ||
127 | x = (typeof(*(p))) __r2; \ | ||
128 | __e; \ | ||
129 | }) | ||
130 | |||
131 | extern int __put_user_1(void *, unsigned int); | ||
132 | extern int __put_user_2(void *, unsigned int); | ||
133 | extern int __put_user_4(void *, unsigned int); | ||
134 | extern int __put_user_8(void *, unsigned long long); | ||
135 | |||
136 | #define __put_user_x(__r2,__p,__e,__s) \ | ||
137 | __asm__ __volatile__ ( \ | ||
138 | __asmeq("%0", "r0") __asmeq("%2", "r2") \ | ||
139 | "bl __put_user_" #__s \ | ||
140 | : "=&r" (__e) \ | ||
141 | : "0" (__p), "r" (__r2) \ | ||
142 | : "ip", "lr", "cc") | ||
143 | |||
144 | #define put_user(x,p) \ | ||
145 | ({ \ | ||
146 | register const typeof(*(p)) __r2 asm("r2") = (x); \ | ||
147 | register const typeof(*(p)) __user *__p asm("r0") = (p);\ | ||
148 | register int __e asm("r0"); \ | ||
149 | switch (sizeof(*(__p))) { \ | ||
150 | case 1: \ | ||
151 | __put_user_x(__r2, __p, __e, 1); \ | ||
152 | break; \ | ||
153 | case 2: \ | ||
154 | __put_user_x(__r2, __p, __e, 2); \ | ||
155 | break; \ | ||
156 | case 4: \ | ||
157 | __put_user_x(__r2, __p, __e, 4); \ | ||
158 | break; \ | ||
159 | case 8: \ | ||
160 | __put_user_x(__r2, __p, __e, 8); \ | ||
161 | break; \ | ||
162 | default: __e = __put_user_bad(); break; \ | ||
163 | } \ | ||
164 | __e; \ | ||
165 | }) | ||
166 | |||
167 | #else /* CONFIG_MMU */ | ||
168 | |||
169 | /* | ||
170 | * uClinux has only one addr space, so has simplified address limits. | ||
171 | */ | ||
172 | #define USER_DS KERNEL_DS | ||
173 | |||
174 | #define segment_eq(a,b) (1) | ||
175 | #define __addr_ok(addr) (1) | ||
176 | #define __range_ok(addr,size) (0) | ||
177 | #define get_fs() (KERNEL_DS) | ||
178 | |||
179 | static inline void set_fs(mm_segment_t fs) | ||
180 | { | ||
181 | } | ||
182 | |||
183 | #define get_user(x,p) __get_user(x,p) | ||
184 | #define put_user(x,p) __put_user(x,p) | ||
185 | |||
186 | #endif /* CONFIG_MMU */ | ||
187 | |||
188 | #define access_ok(type,addr,size) (__range_ok(addr,size) == 0) | ||
189 | |||
190 | /* | ||
191 | * The "__xxx" versions of the user access functions do not verify the | ||
192 | * address space - it must have been done previously with a separate | ||
193 | * "access_ok()" call. | ||
194 | * | ||
195 | * The "xxx_error" versions set the third argument to EFAULT if an | ||
196 | * error occurs, and leave it unchanged on success. Note that these | ||
197 | * versions are void (ie, don't return a value as such). | ||
198 | */ | ||
199 | #define __get_user(x,ptr) \ | ||
200 | ({ \ | ||
201 | long __gu_err = 0; \ | ||
202 | __get_user_err((x),(ptr),__gu_err); \ | ||
203 | __gu_err; \ | ||
204 | }) | ||
205 | |||
206 | #define __get_user_error(x,ptr,err) \ | ||
207 | ({ \ | ||
208 | __get_user_err((x),(ptr),err); \ | ||
209 | (void) 0; \ | ||
210 | }) | ||
211 | |||
212 | #define __get_user_err(x,ptr,err) \ | ||
213 | do { \ | ||
214 | unsigned long __gu_addr = (unsigned long)(ptr); \ | ||
215 | unsigned long __gu_val; \ | ||
216 | __chk_user_ptr(ptr); \ | ||
217 | switch (sizeof(*(ptr))) { \ | ||
218 | case 1: __get_user_asm_byte(__gu_val,__gu_addr,err); break; \ | ||
219 | case 2: __get_user_asm_half(__gu_val,__gu_addr,err); break; \ | ||
220 | case 4: __get_user_asm_word(__gu_val,__gu_addr,err); break; \ | ||
221 | default: (__gu_val) = __get_user_bad(); \ | ||
222 | } \ | ||
223 | (x) = (__typeof__(*(ptr)))__gu_val; \ | ||
224 | } while (0) | ||
225 | |||
226 | #define __get_user_asm_byte(x,addr,err) \ | ||
227 | __asm__ __volatile__( \ | ||
228 | "1: ldrbt %1,[%2],#0\n" \ | ||
229 | "2:\n" \ | ||
230 | " .section .fixup,\"ax\"\n" \ | ||
231 | " .align 2\n" \ | ||
232 | "3: mov %0, %3\n" \ | ||
233 | " mov %1, #0\n" \ | ||
234 | " b 2b\n" \ | ||
235 | " .previous\n" \ | ||
236 | " .section __ex_table,\"a\"\n" \ | ||
237 | " .align 3\n" \ | ||
238 | " .long 1b, 3b\n" \ | ||
239 | " .previous" \ | ||
240 | : "+r" (err), "=&r" (x) \ | ||
241 | : "r" (addr), "i" (-EFAULT) \ | ||
242 | : "cc") | ||
243 | |||
244 | #ifndef __ARMEB__ | ||
245 | #define __get_user_asm_half(x,__gu_addr,err) \ | ||
246 | ({ \ | ||
247 | unsigned long __b1, __b2; \ | ||
248 | __get_user_asm_byte(__b1, __gu_addr, err); \ | ||
249 | __get_user_asm_byte(__b2, __gu_addr + 1, err); \ | ||
250 | (x) = __b1 | (__b2 << 8); \ | ||
251 | }) | ||
252 | #else | ||
253 | #define __get_user_asm_half(x,__gu_addr,err) \ | ||
254 | ({ \ | ||
255 | unsigned long __b1, __b2; \ | ||
256 | __get_user_asm_byte(__b1, __gu_addr, err); \ | ||
257 | __get_user_asm_byte(__b2, __gu_addr + 1, err); \ | ||
258 | (x) = (__b1 << 8) | __b2; \ | ||
259 | }) | ||
260 | #endif | ||
261 | |||
262 | #define __get_user_asm_word(x,addr,err) \ | ||
263 | __asm__ __volatile__( \ | ||
264 | "1: ldrt %1,[%2],#0\n" \ | ||
265 | "2:\n" \ | ||
266 | " .section .fixup,\"ax\"\n" \ | ||
267 | " .align 2\n" \ | ||
268 | "3: mov %0, %3\n" \ | ||
269 | " mov %1, #0\n" \ | ||
270 | " b 2b\n" \ | ||
271 | " .previous\n" \ | ||
272 | " .section __ex_table,\"a\"\n" \ | ||
273 | " .align 3\n" \ | ||
274 | " .long 1b, 3b\n" \ | ||
275 | " .previous" \ | ||
276 | : "+r" (err), "=&r" (x) \ | ||
277 | : "r" (addr), "i" (-EFAULT) \ | ||
278 | : "cc") | ||
279 | |||
280 | #define __put_user(x,ptr) \ | ||
281 | ({ \ | ||
282 | long __pu_err = 0; \ | ||
283 | __put_user_err((x),(ptr),__pu_err); \ | ||
284 | __pu_err; \ | ||
285 | }) | ||
286 | |||
287 | #define __put_user_error(x,ptr,err) \ | ||
288 | ({ \ | ||
289 | __put_user_err((x),(ptr),err); \ | ||
290 | (void) 0; \ | ||
291 | }) | ||
292 | |||
293 | #define __put_user_err(x,ptr,err) \ | ||
294 | do { \ | ||
295 | unsigned long __pu_addr = (unsigned long)(ptr); \ | ||
296 | __typeof__(*(ptr)) __pu_val = (x); \ | ||
297 | __chk_user_ptr(ptr); \ | ||
298 | switch (sizeof(*(ptr))) { \ | ||
299 | case 1: __put_user_asm_byte(__pu_val,__pu_addr,err); break; \ | ||
300 | case 2: __put_user_asm_half(__pu_val,__pu_addr,err); break; \ | ||
301 | case 4: __put_user_asm_word(__pu_val,__pu_addr,err); break; \ | ||
302 | case 8: __put_user_asm_dword(__pu_val,__pu_addr,err); break; \ | ||
303 | default: __put_user_bad(); \ | ||
304 | } \ | ||
305 | } while (0) | ||
306 | |||
307 | #define __put_user_asm_byte(x,__pu_addr,err) \ | ||
308 | __asm__ __volatile__( \ | ||
309 | "1: strbt %1,[%2],#0\n" \ | ||
310 | "2:\n" \ | ||
311 | " .section .fixup,\"ax\"\n" \ | ||
312 | " .align 2\n" \ | ||
313 | "3: mov %0, %3\n" \ | ||
314 | " b 2b\n" \ | ||
315 | " .previous\n" \ | ||
316 | " .section __ex_table,\"a\"\n" \ | ||
317 | " .align 3\n" \ | ||
318 | " .long 1b, 3b\n" \ | ||
319 | " .previous" \ | ||
320 | : "+r" (err) \ | ||
321 | : "r" (x), "r" (__pu_addr), "i" (-EFAULT) \ | ||
322 | : "cc") | ||
323 | |||
324 | #ifndef __ARMEB__ | ||
325 | #define __put_user_asm_half(x,__pu_addr,err) \ | ||
326 | ({ \ | ||
327 | unsigned long __temp = (unsigned long)(x); \ | ||
328 | __put_user_asm_byte(__temp, __pu_addr, err); \ | ||
329 | __put_user_asm_byte(__temp >> 8, __pu_addr + 1, err); \ | ||
330 | }) | ||
331 | #else | ||
332 | #define __put_user_asm_half(x,__pu_addr,err) \ | ||
333 | ({ \ | ||
334 | unsigned long __temp = (unsigned long)(x); \ | ||
335 | __put_user_asm_byte(__temp >> 8, __pu_addr, err); \ | ||
336 | __put_user_asm_byte(__temp, __pu_addr + 1, err); \ | ||
337 | }) | ||
338 | #endif | ||
339 | |||
340 | #define __put_user_asm_word(x,__pu_addr,err) \ | ||
341 | __asm__ __volatile__( \ | ||
342 | "1: strt %1,[%2],#0\n" \ | ||
343 | "2:\n" \ | ||
344 | " .section .fixup,\"ax\"\n" \ | ||
345 | " .align 2\n" \ | ||
346 | "3: mov %0, %3\n" \ | ||
347 | " b 2b\n" \ | ||
348 | " .previous\n" \ | ||
349 | " .section __ex_table,\"a\"\n" \ | ||
350 | " .align 3\n" \ | ||
351 | " .long 1b, 3b\n" \ | ||
352 | " .previous" \ | ||
353 | : "+r" (err) \ | ||
354 | : "r" (x), "r" (__pu_addr), "i" (-EFAULT) \ | ||
355 | : "cc") | ||
356 | |||
357 | #ifndef __ARMEB__ | ||
358 | #define __reg_oper0 "%R2" | ||
359 | #define __reg_oper1 "%Q2" | ||
360 | #else | ||
361 | #define __reg_oper0 "%Q2" | ||
362 | #define __reg_oper1 "%R2" | ||
363 | #endif | ||
364 | |||
365 | #define __put_user_asm_dword(x,__pu_addr,err) \ | ||
366 | __asm__ __volatile__( \ | ||
367 | "1: strt " __reg_oper1 ", [%1], #4\n" \ | ||
368 | "2: strt " __reg_oper0 ", [%1], #0\n" \ | ||
369 | "3:\n" \ | ||
370 | " .section .fixup,\"ax\"\n" \ | ||
371 | " .align 2\n" \ | ||
372 | "4: mov %0, %3\n" \ | ||
373 | " b 3b\n" \ | ||
374 | " .previous\n" \ | ||
375 | " .section __ex_table,\"a\"\n" \ | ||
376 | " .align 3\n" \ | ||
377 | " .long 1b, 4b\n" \ | ||
378 | " .long 2b, 4b\n" \ | ||
379 | " .previous" \ | ||
380 | : "+r" (err), "+r" (__pu_addr) \ | ||
381 | : "r" (x), "i" (-EFAULT) \ | ||
382 | : "cc") | ||
383 | |||
384 | |||
385 | #ifdef CONFIG_MMU | ||
386 | extern unsigned long __must_check __copy_from_user(void *to, const void __user *from, unsigned long n); | ||
387 | extern unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n); | ||
388 | extern unsigned long __must_check __clear_user(void __user *addr, unsigned long n); | ||
389 | #else | ||
390 | #define __copy_from_user(to,from,n) (memcpy(to, (void __force *)from, n), 0) | ||
391 | #define __copy_to_user(to,from,n) (memcpy((void __force *)to, from, n), 0) | ||
392 | #define __clear_user(addr,n) (memset((void __force *)addr, 0, n), 0) | ||
393 | #endif | ||
394 | |||
395 | extern unsigned long __must_check __strncpy_from_user(char *to, const char __user *from, unsigned long count); | ||
396 | extern unsigned long __must_check __strnlen_user(const char __user *s, long n); | ||
397 | |||
398 | static inline unsigned long __must_check copy_from_user(void *to, const void __user *from, unsigned long n) | ||
399 | { | ||
400 | if (access_ok(VERIFY_READ, from, n)) | ||
401 | n = __copy_from_user(to, from, n); | ||
402 | else /* security hole - plug it */ | ||
403 | memzero(to, n); | ||
404 | return n; | ||
405 | } | ||
406 | |||
407 | static inline unsigned long __must_check copy_to_user(void __user *to, const void *from, unsigned long n) | ||
408 | { | ||
409 | if (access_ok(VERIFY_WRITE, to, n)) | ||
410 | n = __copy_to_user(to, from, n); | ||
411 | return n; | ||
412 | } | ||
413 | |||
414 | #define __copy_to_user_inatomic __copy_to_user | ||
415 | #define __copy_from_user_inatomic __copy_from_user | ||
416 | |||
417 | static inline unsigned long __must_check clear_user(void __user *to, unsigned long n) | ||
418 | { | ||
419 | if (access_ok(VERIFY_WRITE, to, n)) | ||
420 | n = __clear_user(to, n); | ||
421 | return n; | ||
422 | } | ||
423 | |||
424 | static inline long __must_check strncpy_from_user(char *dst, const char __user *src, long count) | ||
425 | { | ||
426 | long res = -EFAULT; | ||
427 | if (access_ok(VERIFY_READ, src, 1)) | ||
428 | res = __strncpy_from_user(dst, src, count); | ||
429 | return res; | ||
430 | } | ||
431 | |||
432 | #define strlen_user(s) strnlen_user(s, ~0UL >> 1) | ||
433 | |||
434 | static inline long __must_check strnlen_user(const char __user *s, long n) | ||
435 | { | ||
436 | unsigned long res = 0; | ||
437 | |||
438 | if (__addr_ok(s)) | ||
439 | res = __strnlen_user(s, n); | ||
440 | |||
441 | return res; | ||
442 | } | ||
443 | |||
444 | #endif /* _ASMARM_UACCESS_H */ | ||
diff --git a/arch/arm/include/asm/ucontext.h b/arch/arm/include/asm/ucontext.h new file mode 100644 index 000000000000..bf65e9f4525d --- /dev/null +++ b/arch/arm/include/asm/ucontext.h | |||
@@ -0,0 +1,103 @@ | |||
1 | #ifndef _ASMARM_UCONTEXT_H | ||
2 | #define _ASMARM_UCONTEXT_H | ||
3 | |||
4 | #include <asm/fpstate.h> | ||
5 | |||
6 | /* | ||
7 | * struct sigcontext only has room for the basic registers, but struct | ||
8 | * ucontext now has room for all registers which need to be saved and | ||
9 | * restored. Coprocessor registers are stored in uc_regspace. Each | ||
10 | * coprocessor's saved state should start with a documented 32-bit magic | ||
11 | * number, followed by a 32-bit word giving the coproccesor's saved size. | ||
12 | * uc_regspace may be expanded if necessary, although this takes some | ||
13 | * coordination with glibc. | ||
14 | */ | ||
15 | |||
16 | struct ucontext { | ||
17 | unsigned long uc_flags; | ||
18 | struct ucontext *uc_link; | ||
19 | stack_t uc_stack; | ||
20 | struct sigcontext uc_mcontext; | ||
21 | sigset_t uc_sigmask; | ||
22 | /* Allow for uc_sigmask growth. Glibc uses a 1024-bit sigset_t. */ | ||
23 | int __unused[32 - (sizeof (sigset_t) / sizeof (int))]; | ||
24 | /* Last for extensibility. Eight byte aligned because some | ||
25 | coprocessors require eight byte alignment. */ | ||
26 | unsigned long uc_regspace[128] __attribute__((__aligned__(8))); | ||
27 | }; | ||
28 | |||
29 | #ifdef __KERNEL__ | ||
30 | |||
31 | /* | ||
32 | * Coprocessor save state. The magic values and specific | ||
33 | * coprocessor's layouts are part of the userspace ABI. Each one of | ||
34 | * these should be a multiple of eight bytes and aligned to eight | ||
35 | * bytes, to prevent unpredictable padding in the signal frame. | ||
36 | */ | ||
37 | |||
38 | #ifdef CONFIG_CRUNCH | ||
39 | #define CRUNCH_MAGIC 0x5065cf03 | ||
40 | #define CRUNCH_STORAGE_SIZE (CRUNCH_SIZE + 8) | ||
41 | |||
42 | struct crunch_sigframe { | ||
43 | unsigned long magic; | ||
44 | unsigned long size; | ||
45 | struct crunch_state storage; | ||
46 | } __attribute__((__aligned__(8))); | ||
47 | #endif | ||
48 | |||
49 | #ifdef CONFIG_IWMMXT | ||
50 | /* iwmmxt_area is 0x98 bytes long, preceeded by 8 bytes of signature */ | ||
51 | #define IWMMXT_MAGIC 0x12ef842a | ||
52 | #define IWMMXT_STORAGE_SIZE (IWMMXT_SIZE + 8) | ||
53 | |||
54 | struct iwmmxt_sigframe { | ||
55 | unsigned long magic; | ||
56 | unsigned long size; | ||
57 | struct iwmmxt_struct storage; | ||
58 | } __attribute__((__aligned__(8))); | ||
59 | #endif /* CONFIG_IWMMXT */ | ||
60 | |||
61 | #ifdef CONFIG_VFP | ||
62 | #if __LINUX_ARM_ARCH__ < 6 | ||
63 | /* For ARM pre-v6, we use fstmiax and fldmiax. This adds one extra | ||
64 | * word after the registers, and a word of padding at the end for | ||
65 | * alignment. */ | ||
66 | #define VFP_MAGIC 0x56465001 | ||
67 | #define VFP_STORAGE_SIZE 152 | ||
68 | #else | ||
69 | #define VFP_MAGIC 0x56465002 | ||
70 | #define VFP_STORAGE_SIZE 144 | ||
71 | #endif | ||
72 | |||
73 | struct vfp_sigframe | ||
74 | { | ||
75 | unsigned long magic; | ||
76 | unsigned long size; | ||
77 | union vfp_state storage; | ||
78 | }; | ||
79 | #endif /* CONFIG_VFP */ | ||
80 | |||
81 | /* | ||
82 | * Auxiliary signal frame. This saves stuff like FP state. | ||
83 | * The layout of this structure is not part of the user ABI, | ||
84 | * because the config options aren't. uc_regspace is really | ||
85 | * one of these. | ||
86 | */ | ||
87 | struct aux_sigframe { | ||
88 | #ifdef CONFIG_CRUNCH | ||
89 | struct crunch_sigframe crunch; | ||
90 | #endif | ||
91 | #ifdef CONFIG_IWMMXT | ||
92 | struct iwmmxt_sigframe iwmmxt; | ||
93 | #endif | ||
94 | #if 0 && defined CONFIG_VFP /* Not yet saved. */ | ||
95 | struct vfp_sigframe vfp; | ||
96 | #endif | ||
97 | /* Something that isn't a valid magic number for any coprocessor. */ | ||
98 | unsigned long end_magic; | ||
99 | } __attribute__((__aligned__(8))); | ||
100 | |||
101 | #endif | ||
102 | |||
103 | #endif /* !_ASMARM_UCONTEXT_H */ | ||
diff --git a/arch/arm/include/asm/unaligned.h b/arch/arm/include/asm/unaligned.h new file mode 100644 index 000000000000..44593a894903 --- /dev/null +++ b/arch/arm/include/asm/unaligned.h | |||
@@ -0,0 +1,19 @@ | |||
1 | #ifndef _ASM_ARM_UNALIGNED_H | ||
2 | #define _ASM_ARM_UNALIGNED_H | ||
3 | |||
4 | #include <linux/unaligned/le_byteshift.h> | ||
5 | #include <linux/unaligned/be_byteshift.h> | ||
6 | #include <linux/unaligned/generic.h> | ||
7 | |||
8 | /* | ||
9 | * Select endianness | ||
10 | */ | ||
11 | #ifndef __ARMEB__ | ||
12 | #define get_unaligned __get_unaligned_le | ||
13 | #define put_unaligned __put_unaligned_le | ||
14 | #else | ||
15 | #define get_unaligned __get_unaligned_be | ||
16 | #define put_unaligned __put_unaligned_be | ||
17 | #endif | ||
18 | |||
19 | #endif /* _ASM_ARM_UNALIGNED_H */ | ||
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h new file mode 100644 index 000000000000..f95fbb2fcb5f --- /dev/null +++ b/arch/arm/include/asm/unistd.h | |||
@@ -0,0 +1,450 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/unistd.h | ||
3 | * | ||
4 | * Copyright (C) 2001-2005 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * Please forward _all_ changes to this file to rmk@arm.linux.org.uk, | ||
11 | * no matter what the change is. Thanks! | ||
12 | */ | ||
13 | #ifndef __ASM_ARM_UNISTD_H | ||
14 | #define __ASM_ARM_UNISTD_H | ||
15 | |||
16 | #define __NR_OABI_SYSCALL_BASE 0x900000 | ||
17 | |||
18 | #if defined(__thumb__) || defined(__ARM_EABI__) | ||
19 | #define __NR_SYSCALL_BASE 0 | ||
20 | #else | ||
21 | #define __NR_SYSCALL_BASE __NR_OABI_SYSCALL_BASE | ||
22 | #endif | ||
23 | |||
24 | /* | ||
25 | * This file contains the system call numbers. | ||
26 | */ | ||
27 | |||
28 | #define __NR_restart_syscall (__NR_SYSCALL_BASE+ 0) | ||
29 | #define __NR_exit (__NR_SYSCALL_BASE+ 1) | ||
30 | #define __NR_fork (__NR_SYSCALL_BASE+ 2) | ||
31 | #define __NR_read (__NR_SYSCALL_BASE+ 3) | ||
32 | #define __NR_write (__NR_SYSCALL_BASE+ 4) | ||
33 | #define __NR_open (__NR_SYSCALL_BASE+ 5) | ||
34 | #define __NR_close (__NR_SYSCALL_BASE+ 6) | ||
35 | /* 7 was sys_waitpid */ | ||
36 | #define __NR_creat (__NR_SYSCALL_BASE+ 8) | ||
37 | #define __NR_link (__NR_SYSCALL_BASE+ 9) | ||
38 | #define __NR_unlink (__NR_SYSCALL_BASE+ 10) | ||
39 | #define __NR_execve (__NR_SYSCALL_BASE+ 11) | ||
40 | #define __NR_chdir (__NR_SYSCALL_BASE+ 12) | ||
41 | #define __NR_time (__NR_SYSCALL_BASE+ 13) | ||
42 | #define __NR_mknod (__NR_SYSCALL_BASE+ 14) | ||
43 | #define __NR_chmod (__NR_SYSCALL_BASE+ 15) | ||
44 | #define __NR_lchown (__NR_SYSCALL_BASE+ 16) | ||
45 | /* 17 was sys_break */ | ||
46 | /* 18 was sys_stat */ | ||
47 | #define __NR_lseek (__NR_SYSCALL_BASE+ 19) | ||
48 | #define __NR_getpid (__NR_SYSCALL_BASE+ 20) | ||
49 | #define __NR_mount (__NR_SYSCALL_BASE+ 21) | ||
50 | #define __NR_umount (__NR_SYSCALL_BASE+ 22) | ||
51 | #define __NR_setuid (__NR_SYSCALL_BASE+ 23) | ||
52 | #define __NR_getuid (__NR_SYSCALL_BASE+ 24) | ||
53 | #define __NR_stime (__NR_SYSCALL_BASE+ 25) | ||
54 | #define __NR_ptrace (__NR_SYSCALL_BASE+ 26) | ||
55 | #define __NR_alarm (__NR_SYSCALL_BASE+ 27) | ||
56 | /* 28 was sys_fstat */ | ||
57 | #define __NR_pause (__NR_SYSCALL_BASE+ 29) | ||
58 | #define __NR_utime (__NR_SYSCALL_BASE+ 30) | ||
59 | /* 31 was sys_stty */ | ||
60 | /* 32 was sys_gtty */ | ||
61 | #define __NR_access (__NR_SYSCALL_BASE+ 33) | ||
62 | #define __NR_nice (__NR_SYSCALL_BASE+ 34) | ||
63 | /* 35 was sys_ftime */ | ||
64 | #define __NR_sync (__NR_SYSCALL_BASE+ 36) | ||
65 | #define __NR_kill (__NR_SYSCALL_BASE+ 37) | ||
66 | #define __NR_rename (__NR_SYSCALL_BASE+ 38) | ||
67 | #define __NR_mkdir (__NR_SYSCALL_BASE+ 39) | ||
68 | #define __NR_rmdir (__NR_SYSCALL_BASE+ 40) | ||
69 | #define __NR_dup (__NR_SYSCALL_BASE+ 41) | ||
70 | #define __NR_pipe (__NR_SYSCALL_BASE+ 42) | ||
71 | #define __NR_times (__NR_SYSCALL_BASE+ 43) | ||
72 | /* 44 was sys_prof */ | ||
73 | #define __NR_brk (__NR_SYSCALL_BASE+ 45) | ||
74 | #define __NR_setgid (__NR_SYSCALL_BASE+ 46) | ||
75 | #define __NR_getgid (__NR_SYSCALL_BASE+ 47) | ||
76 | /* 48 was sys_signal */ | ||
77 | #define __NR_geteuid (__NR_SYSCALL_BASE+ 49) | ||
78 | #define __NR_getegid (__NR_SYSCALL_BASE+ 50) | ||
79 | #define __NR_acct (__NR_SYSCALL_BASE+ 51) | ||
80 | #define __NR_umount2 (__NR_SYSCALL_BASE+ 52) | ||
81 | /* 53 was sys_lock */ | ||
82 | #define __NR_ioctl (__NR_SYSCALL_BASE+ 54) | ||
83 | #define __NR_fcntl (__NR_SYSCALL_BASE+ 55) | ||
84 | /* 56 was sys_mpx */ | ||
85 | #define __NR_setpgid (__NR_SYSCALL_BASE+ 57) | ||
86 | /* 58 was sys_ulimit */ | ||
87 | /* 59 was sys_olduname */ | ||
88 | #define __NR_umask (__NR_SYSCALL_BASE+ 60) | ||
89 | #define __NR_chroot (__NR_SYSCALL_BASE+ 61) | ||
90 | #define __NR_ustat (__NR_SYSCALL_BASE+ 62) | ||
91 | #define __NR_dup2 (__NR_SYSCALL_BASE+ 63) | ||
92 | #define __NR_getppid (__NR_SYSCALL_BASE+ 64) | ||
93 | #define __NR_getpgrp (__NR_SYSCALL_BASE+ 65) | ||
94 | #define __NR_setsid (__NR_SYSCALL_BASE+ 66) | ||
95 | #define __NR_sigaction (__NR_SYSCALL_BASE+ 67) | ||
96 | /* 68 was sys_sgetmask */ | ||
97 | /* 69 was sys_ssetmask */ | ||
98 | #define __NR_setreuid (__NR_SYSCALL_BASE+ 70) | ||
99 | #define __NR_setregid (__NR_SYSCALL_BASE+ 71) | ||
100 | #define __NR_sigsuspend (__NR_SYSCALL_BASE+ 72) | ||
101 | #define __NR_sigpending (__NR_SYSCALL_BASE+ 73) | ||
102 | #define __NR_sethostname (__NR_SYSCALL_BASE+ 74) | ||
103 | #define __NR_setrlimit (__NR_SYSCALL_BASE+ 75) | ||
104 | #define __NR_getrlimit (__NR_SYSCALL_BASE+ 76) /* Back compat 2GB limited rlimit */ | ||
105 | #define __NR_getrusage (__NR_SYSCALL_BASE+ 77) | ||
106 | #define __NR_gettimeofday (__NR_SYSCALL_BASE+ 78) | ||
107 | #define __NR_settimeofday (__NR_SYSCALL_BASE+ 79) | ||
108 | #define __NR_getgroups (__NR_SYSCALL_BASE+ 80) | ||
109 | #define __NR_setgroups (__NR_SYSCALL_BASE+ 81) | ||
110 | #define __NR_select (__NR_SYSCALL_BASE+ 82) | ||
111 | #define __NR_symlink (__NR_SYSCALL_BASE+ 83) | ||
112 | /* 84 was sys_lstat */ | ||
113 | #define __NR_readlink (__NR_SYSCALL_BASE+ 85) | ||
114 | #define __NR_uselib (__NR_SYSCALL_BASE+ 86) | ||
115 | #define __NR_swapon (__NR_SYSCALL_BASE+ 87) | ||
116 | #define __NR_reboot (__NR_SYSCALL_BASE+ 88) | ||
117 | #define __NR_readdir (__NR_SYSCALL_BASE+ 89) | ||
118 | #define __NR_mmap (__NR_SYSCALL_BASE+ 90) | ||
119 | #define __NR_munmap (__NR_SYSCALL_BASE+ 91) | ||
120 | #define __NR_truncate (__NR_SYSCALL_BASE+ 92) | ||
121 | #define __NR_ftruncate (__NR_SYSCALL_BASE+ 93) | ||
122 | #define __NR_fchmod (__NR_SYSCALL_BASE+ 94) | ||
123 | #define __NR_fchown (__NR_SYSCALL_BASE+ 95) | ||
124 | #define __NR_getpriority (__NR_SYSCALL_BASE+ 96) | ||
125 | #define __NR_setpriority (__NR_SYSCALL_BASE+ 97) | ||
126 | /* 98 was sys_profil */ | ||
127 | #define __NR_statfs (__NR_SYSCALL_BASE+ 99) | ||
128 | #define __NR_fstatfs (__NR_SYSCALL_BASE+100) | ||
129 | /* 101 was sys_ioperm */ | ||
130 | #define __NR_socketcall (__NR_SYSCALL_BASE+102) | ||
131 | #define __NR_syslog (__NR_SYSCALL_BASE+103) | ||
132 | #define __NR_setitimer (__NR_SYSCALL_BASE+104) | ||
133 | #define __NR_getitimer (__NR_SYSCALL_BASE+105) | ||
134 | #define __NR_stat (__NR_SYSCALL_BASE+106) | ||
135 | #define __NR_lstat (__NR_SYSCALL_BASE+107) | ||
136 | #define __NR_fstat (__NR_SYSCALL_BASE+108) | ||
137 | /* 109 was sys_uname */ | ||
138 | /* 110 was sys_iopl */ | ||
139 | #define __NR_vhangup (__NR_SYSCALL_BASE+111) | ||
140 | /* 112 was sys_idle */ | ||
141 | #define __NR_syscall (__NR_SYSCALL_BASE+113) /* syscall to call a syscall! */ | ||
142 | #define __NR_wait4 (__NR_SYSCALL_BASE+114) | ||
143 | #define __NR_swapoff (__NR_SYSCALL_BASE+115) | ||
144 | #define __NR_sysinfo (__NR_SYSCALL_BASE+116) | ||
145 | #define __NR_ipc (__NR_SYSCALL_BASE+117) | ||
146 | #define __NR_fsync (__NR_SYSCALL_BASE+118) | ||
147 | #define __NR_sigreturn (__NR_SYSCALL_BASE+119) | ||
148 | #define __NR_clone (__NR_SYSCALL_BASE+120) | ||
149 | #define __NR_setdomainname (__NR_SYSCALL_BASE+121) | ||
150 | #define __NR_uname (__NR_SYSCALL_BASE+122) | ||
151 | /* 123 was sys_modify_ldt */ | ||
152 | #define __NR_adjtimex (__NR_SYSCALL_BASE+124) | ||
153 | #define __NR_mprotect (__NR_SYSCALL_BASE+125) | ||
154 | #define __NR_sigprocmask (__NR_SYSCALL_BASE+126) | ||
155 | /* 127 was sys_create_module */ | ||
156 | #define __NR_init_module (__NR_SYSCALL_BASE+128) | ||
157 | #define __NR_delete_module (__NR_SYSCALL_BASE+129) | ||
158 | /* 130 was sys_get_kernel_syms */ | ||
159 | #define __NR_quotactl (__NR_SYSCALL_BASE+131) | ||
160 | #define __NR_getpgid (__NR_SYSCALL_BASE+132) | ||
161 | #define __NR_fchdir (__NR_SYSCALL_BASE+133) | ||
162 | #define __NR_bdflush (__NR_SYSCALL_BASE+134) | ||
163 | #define __NR_sysfs (__NR_SYSCALL_BASE+135) | ||
164 | #define __NR_personality (__NR_SYSCALL_BASE+136) | ||
165 | /* 137 was sys_afs_syscall */ | ||
166 | #define __NR_setfsuid (__NR_SYSCALL_BASE+138) | ||
167 | #define __NR_setfsgid (__NR_SYSCALL_BASE+139) | ||
168 | #define __NR__llseek (__NR_SYSCALL_BASE+140) | ||
169 | #define __NR_getdents (__NR_SYSCALL_BASE+141) | ||
170 | #define __NR__newselect (__NR_SYSCALL_BASE+142) | ||
171 | #define __NR_flock (__NR_SYSCALL_BASE+143) | ||
172 | #define __NR_msync (__NR_SYSCALL_BASE+144) | ||
173 | #define __NR_readv (__NR_SYSCALL_BASE+145) | ||
174 | #define __NR_writev (__NR_SYSCALL_BASE+146) | ||
175 | #define __NR_getsid (__NR_SYSCALL_BASE+147) | ||
176 | #define __NR_fdatasync (__NR_SYSCALL_BASE+148) | ||
177 | #define __NR__sysctl (__NR_SYSCALL_BASE+149) | ||
178 | #define __NR_mlock (__NR_SYSCALL_BASE+150) | ||
179 | #define __NR_munlock (__NR_SYSCALL_BASE+151) | ||
180 | #define __NR_mlockall (__NR_SYSCALL_BASE+152) | ||
181 | #define __NR_munlockall (__NR_SYSCALL_BASE+153) | ||
182 | #define __NR_sched_setparam (__NR_SYSCALL_BASE+154) | ||
183 | #define __NR_sched_getparam (__NR_SYSCALL_BASE+155) | ||
184 | #define __NR_sched_setscheduler (__NR_SYSCALL_BASE+156) | ||
185 | #define __NR_sched_getscheduler (__NR_SYSCALL_BASE+157) | ||
186 | #define __NR_sched_yield (__NR_SYSCALL_BASE+158) | ||
187 | #define __NR_sched_get_priority_max (__NR_SYSCALL_BASE+159) | ||
188 | #define __NR_sched_get_priority_min (__NR_SYSCALL_BASE+160) | ||
189 | #define __NR_sched_rr_get_interval (__NR_SYSCALL_BASE+161) | ||
190 | #define __NR_nanosleep (__NR_SYSCALL_BASE+162) | ||
191 | #define __NR_mremap (__NR_SYSCALL_BASE+163) | ||
192 | #define __NR_setresuid (__NR_SYSCALL_BASE+164) | ||
193 | #define __NR_getresuid (__NR_SYSCALL_BASE+165) | ||
194 | /* 166 was sys_vm86 */ | ||
195 | /* 167 was sys_query_module */ | ||
196 | #define __NR_poll (__NR_SYSCALL_BASE+168) | ||
197 | #define __NR_nfsservctl (__NR_SYSCALL_BASE+169) | ||
198 | #define __NR_setresgid (__NR_SYSCALL_BASE+170) | ||
199 | #define __NR_getresgid (__NR_SYSCALL_BASE+171) | ||
200 | #define __NR_prctl (__NR_SYSCALL_BASE+172) | ||
201 | #define __NR_rt_sigreturn (__NR_SYSCALL_BASE+173) | ||
202 | #define __NR_rt_sigaction (__NR_SYSCALL_BASE+174) | ||
203 | #define __NR_rt_sigprocmask (__NR_SYSCALL_BASE+175) | ||
204 | #define __NR_rt_sigpending (__NR_SYSCALL_BASE+176) | ||
205 | #define __NR_rt_sigtimedwait (__NR_SYSCALL_BASE+177) | ||
206 | #define __NR_rt_sigqueueinfo (__NR_SYSCALL_BASE+178) | ||
207 | #define __NR_rt_sigsuspend (__NR_SYSCALL_BASE+179) | ||
208 | #define __NR_pread64 (__NR_SYSCALL_BASE+180) | ||
209 | #define __NR_pwrite64 (__NR_SYSCALL_BASE+181) | ||
210 | #define __NR_chown (__NR_SYSCALL_BASE+182) | ||
211 | #define __NR_getcwd (__NR_SYSCALL_BASE+183) | ||
212 | #define __NR_capget (__NR_SYSCALL_BASE+184) | ||
213 | #define __NR_capset (__NR_SYSCALL_BASE+185) | ||
214 | #define __NR_sigaltstack (__NR_SYSCALL_BASE+186) | ||
215 | #define __NR_sendfile (__NR_SYSCALL_BASE+187) | ||
216 | /* 188 reserved */ | ||
217 | /* 189 reserved */ | ||
218 | #define __NR_vfork (__NR_SYSCALL_BASE+190) | ||
219 | #define __NR_ugetrlimit (__NR_SYSCALL_BASE+191) /* SuS compliant getrlimit */ | ||
220 | #define __NR_mmap2 (__NR_SYSCALL_BASE+192) | ||
221 | #define __NR_truncate64 (__NR_SYSCALL_BASE+193) | ||
222 | #define __NR_ftruncate64 (__NR_SYSCALL_BASE+194) | ||
223 | #define __NR_stat64 (__NR_SYSCALL_BASE+195) | ||
224 | #define __NR_lstat64 (__NR_SYSCALL_BASE+196) | ||
225 | #define __NR_fstat64 (__NR_SYSCALL_BASE+197) | ||
226 | #define __NR_lchown32 (__NR_SYSCALL_BASE+198) | ||
227 | #define __NR_getuid32 (__NR_SYSCALL_BASE+199) | ||
228 | #define __NR_getgid32 (__NR_SYSCALL_BASE+200) | ||
229 | #define __NR_geteuid32 (__NR_SYSCALL_BASE+201) | ||
230 | #define __NR_getegid32 (__NR_SYSCALL_BASE+202) | ||
231 | #define __NR_setreuid32 (__NR_SYSCALL_BASE+203) | ||
232 | #define __NR_setregid32 (__NR_SYSCALL_BASE+204) | ||
233 | #define __NR_getgroups32 (__NR_SYSCALL_BASE+205) | ||
234 | #define __NR_setgroups32 (__NR_SYSCALL_BASE+206) | ||
235 | #define __NR_fchown32 (__NR_SYSCALL_BASE+207) | ||
236 | #define __NR_setresuid32 (__NR_SYSCALL_BASE+208) | ||
237 | #define __NR_getresuid32 (__NR_SYSCALL_BASE+209) | ||
238 | #define __NR_setresgid32 (__NR_SYSCALL_BASE+210) | ||
239 | #define __NR_getresgid32 (__NR_SYSCALL_BASE+211) | ||
240 | #define __NR_chown32 (__NR_SYSCALL_BASE+212) | ||
241 | #define __NR_setuid32 (__NR_SYSCALL_BASE+213) | ||
242 | #define __NR_setgid32 (__NR_SYSCALL_BASE+214) | ||
243 | #define __NR_setfsuid32 (__NR_SYSCALL_BASE+215) | ||
244 | #define __NR_setfsgid32 (__NR_SYSCALL_BASE+216) | ||
245 | #define __NR_getdents64 (__NR_SYSCALL_BASE+217) | ||
246 | #define __NR_pivot_root (__NR_SYSCALL_BASE+218) | ||
247 | #define __NR_mincore (__NR_SYSCALL_BASE+219) | ||
248 | #define __NR_madvise (__NR_SYSCALL_BASE+220) | ||
249 | #define __NR_fcntl64 (__NR_SYSCALL_BASE+221) | ||
250 | /* 222 for tux */ | ||
251 | /* 223 is unused */ | ||
252 | #define __NR_gettid (__NR_SYSCALL_BASE+224) | ||
253 | #define __NR_readahead (__NR_SYSCALL_BASE+225) | ||
254 | #define __NR_setxattr (__NR_SYSCALL_BASE+226) | ||
255 | #define __NR_lsetxattr (__NR_SYSCALL_BASE+227) | ||
256 | #define __NR_fsetxattr (__NR_SYSCALL_BASE+228) | ||
257 | #define __NR_getxattr (__NR_SYSCALL_BASE+229) | ||
258 | #define __NR_lgetxattr (__NR_SYSCALL_BASE+230) | ||
259 | #define __NR_fgetxattr (__NR_SYSCALL_BASE+231) | ||
260 | #define __NR_listxattr (__NR_SYSCALL_BASE+232) | ||
261 | #define __NR_llistxattr (__NR_SYSCALL_BASE+233) | ||
262 | #define __NR_flistxattr (__NR_SYSCALL_BASE+234) | ||
263 | #define __NR_removexattr (__NR_SYSCALL_BASE+235) | ||
264 | #define __NR_lremovexattr (__NR_SYSCALL_BASE+236) | ||
265 | #define __NR_fremovexattr (__NR_SYSCALL_BASE+237) | ||
266 | #define __NR_tkill (__NR_SYSCALL_BASE+238) | ||
267 | #define __NR_sendfile64 (__NR_SYSCALL_BASE+239) | ||
268 | #define __NR_futex (__NR_SYSCALL_BASE+240) | ||
269 | #define __NR_sched_setaffinity (__NR_SYSCALL_BASE+241) | ||
270 | #define __NR_sched_getaffinity (__NR_SYSCALL_BASE+242) | ||
271 | #define __NR_io_setup (__NR_SYSCALL_BASE+243) | ||
272 | #define __NR_io_destroy (__NR_SYSCALL_BASE+244) | ||
273 | #define __NR_io_getevents (__NR_SYSCALL_BASE+245) | ||
274 | #define __NR_io_submit (__NR_SYSCALL_BASE+246) | ||
275 | #define __NR_io_cancel (__NR_SYSCALL_BASE+247) | ||
276 | #define __NR_exit_group (__NR_SYSCALL_BASE+248) | ||
277 | #define __NR_lookup_dcookie (__NR_SYSCALL_BASE+249) | ||
278 | #define __NR_epoll_create (__NR_SYSCALL_BASE+250) | ||
279 | #define __NR_epoll_ctl (__NR_SYSCALL_BASE+251) | ||
280 | #define __NR_epoll_wait (__NR_SYSCALL_BASE+252) | ||
281 | #define __NR_remap_file_pages (__NR_SYSCALL_BASE+253) | ||
282 | /* 254 for set_thread_area */ | ||
283 | /* 255 for get_thread_area */ | ||
284 | #define __NR_set_tid_address (__NR_SYSCALL_BASE+256) | ||
285 | #define __NR_timer_create (__NR_SYSCALL_BASE+257) | ||
286 | #define __NR_timer_settime (__NR_SYSCALL_BASE+258) | ||
287 | #define __NR_timer_gettime (__NR_SYSCALL_BASE+259) | ||
288 | #define __NR_timer_getoverrun (__NR_SYSCALL_BASE+260) | ||
289 | #define __NR_timer_delete (__NR_SYSCALL_BASE+261) | ||
290 | #define __NR_clock_settime (__NR_SYSCALL_BASE+262) | ||
291 | #define __NR_clock_gettime (__NR_SYSCALL_BASE+263) | ||
292 | #define __NR_clock_getres (__NR_SYSCALL_BASE+264) | ||
293 | #define __NR_clock_nanosleep (__NR_SYSCALL_BASE+265) | ||
294 | #define __NR_statfs64 (__NR_SYSCALL_BASE+266) | ||
295 | #define __NR_fstatfs64 (__NR_SYSCALL_BASE+267) | ||
296 | #define __NR_tgkill (__NR_SYSCALL_BASE+268) | ||
297 | #define __NR_utimes (__NR_SYSCALL_BASE+269) | ||
298 | #define __NR_arm_fadvise64_64 (__NR_SYSCALL_BASE+270) | ||
299 | #define __NR_pciconfig_iobase (__NR_SYSCALL_BASE+271) | ||
300 | #define __NR_pciconfig_read (__NR_SYSCALL_BASE+272) | ||
301 | #define __NR_pciconfig_write (__NR_SYSCALL_BASE+273) | ||
302 | #define __NR_mq_open (__NR_SYSCALL_BASE+274) | ||
303 | #define __NR_mq_unlink (__NR_SYSCALL_BASE+275) | ||
304 | #define __NR_mq_timedsend (__NR_SYSCALL_BASE+276) | ||
305 | #define __NR_mq_timedreceive (__NR_SYSCALL_BASE+277) | ||
306 | #define __NR_mq_notify (__NR_SYSCALL_BASE+278) | ||
307 | #define __NR_mq_getsetattr (__NR_SYSCALL_BASE+279) | ||
308 | #define __NR_waitid (__NR_SYSCALL_BASE+280) | ||
309 | #define __NR_socket (__NR_SYSCALL_BASE+281) | ||
310 | #define __NR_bind (__NR_SYSCALL_BASE+282) | ||
311 | #define __NR_connect (__NR_SYSCALL_BASE+283) | ||
312 | #define __NR_listen (__NR_SYSCALL_BASE+284) | ||
313 | #define __NR_accept (__NR_SYSCALL_BASE+285) | ||
314 | #define __NR_getsockname (__NR_SYSCALL_BASE+286) | ||
315 | #define __NR_getpeername (__NR_SYSCALL_BASE+287) | ||
316 | #define __NR_socketpair (__NR_SYSCALL_BASE+288) | ||
317 | #define __NR_send (__NR_SYSCALL_BASE+289) | ||
318 | #define __NR_sendto (__NR_SYSCALL_BASE+290) | ||
319 | #define __NR_recv (__NR_SYSCALL_BASE+291) | ||
320 | #define __NR_recvfrom (__NR_SYSCALL_BASE+292) | ||
321 | #define __NR_shutdown (__NR_SYSCALL_BASE+293) | ||
322 | #define __NR_setsockopt (__NR_SYSCALL_BASE+294) | ||
323 | #define __NR_getsockopt (__NR_SYSCALL_BASE+295) | ||
324 | #define __NR_sendmsg (__NR_SYSCALL_BASE+296) | ||
325 | #define __NR_recvmsg (__NR_SYSCALL_BASE+297) | ||
326 | #define __NR_semop (__NR_SYSCALL_BASE+298) | ||
327 | #define __NR_semget (__NR_SYSCALL_BASE+299) | ||
328 | #define __NR_semctl (__NR_SYSCALL_BASE+300) | ||
329 | #define __NR_msgsnd (__NR_SYSCALL_BASE+301) | ||
330 | #define __NR_msgrcv (__NR_SYSCALL_BASE+302) | ||
331 | #define __NR_msgget (__NR_SYSCALL_BASE+303) | ||
332 | #define __NR_msgctl (__NR_SYSCALL_BASE+304) | ||
333 | #define __NR_shmat (__NR_SYSCALL_BASE+305) | ||
334 | #define __NR_shmdt (__NR_SYSCALL_BASE+306) | ||
335 | #define __NR_shmget (__NR_SYSCALL_BASE+307) | ||
336 | #define __NR_shmctl (__NR_SYSCALL_BASE+308) | ||
337 | #define __NR_add_key (__NR_SYSCALL_BASE+309) | ||
338 | #define __NR_request_key (__NR_SYSCALL_BASE+310) | ||
339 | #define __NR_keyctl (__NR_SYSCALL_BASE+311) | ||
340 | #define __NR_semtimedop (__NR_SYSCALL_BASE+312) | ||
341 | #define __NR_vserver (__NR_SYSCALL_BASE+313) | ||
342 | #define __NR_ioprio_set (__NR_SYSCALL_BASE+314) | ||
343 | #define __NR_ioprio_get (__NR_SYSCALL_BASE+315) | ||
344 | #define __NR_inotify_init (__NR_SYSCALL_BASE+316) | ||
345 | #define __NR_inotify_add_watch (__NR_SYSCALL_BASE+317) | ||
346 | #define __NR_inotify_rm_watch (__NR_SYSCALL_BASE+318) | ||
347 | #define __NR_mbind (__NR_SYSCALL_BASE+319) | ||
348 | #define __NR_get_mempolicy (__NR_SYSCALL_BASE+320) | ||
349 | #define __NR_set_mempolicy (__NR_SYSCALL_BASE+321) | ||
350 | #define __NR_openat (__NR_SYSCALL_BASE+322) | ||
351 | #define __NR_mkdirat (__NR_SYSCALL_BASE+323) | ||
352 | #define __NR_mknodat (__NR_SYSCALL_BASE+324) | ||
353 | #define __NR_fchownat (__NR_SYSCALL_BASE+325) | ||
354 | #define __NR_futimesat (__NR_SYSCALL_BASE+326) | ||
355 | #define __NR_fstatat64 (__NR_SYSCALL_BASE+327) | ||
356 | #define __NR_unlinkat (__NR_SYSCALL_BASE+328) | ||
357 | #define __NR_renameat (__NR_SYSCALL_BASE+329) | ||
358 | #define __NR_linkat (__NR_SYSCALL_BASE+330) | ||
359 | #define __NR_symlinkat (__NR_SYSCALL_BASE+331) | ||
360 | #define __NR_readlinkat (__NR_SYSCALL_BASE+332) | ||
361 | #define __NR_fchmodat (__NR_SYSCALL_BASE+333) | ||
362 | #define __NR_faccessat (__NR_SYSCALL_BASE+334) | ||
363 | /* 335 for pselect6 */ | ||
364 | /* 336 for ppoll */ | ||
365 | #define __NR_unshare (__NR_SYSCALL_BASE+337) | ||
366 | #define __NR_set_robust_list (__NR_SYSCALL_BASE+338) | ||
367 | #define __NR_get_robust_list (__NR_SYSCALL_BASE+339) | ||
368 | #define __NR_splice (__NR_SYSCALL_BASE+340) | ||
369 | #define __NR_arm_sync_file_range (__NR_SYSCALL_BASE+341) | ||
370 | #define __NR_sync_file_range2 __NR_arm_sync_file_range | ||
371 | #define __NR_tee (__NR_SYSCALL_BASE+342) | ||
372 | #define __NR_vmsplice (__NR_SYSCALL_BASE+343) | ||
373 | #define __NR_move_pages (__NR_SYSCALL_BASE+344) | ||
374 | #define __NR_getcpu (__NR_SYSCALL_BASE+345) | ||
375 | /* 346 for epoll_pwait */ | ||
376 | #define __NR_kexec_load (__NR_SYSCALL_BASE+347) | ||
377 | #define __NR_utimensat (__NR_SYSCALL_BASE+348) | ||
378 | #define __NR_signalfd (__NR_SYSCALL_BASE+349) | ||
379 | #define __NR_timerfd_create (__NR_SYSCALL_BASE+350) | ||
380 | #define __NR_eventfd (__NR_SYSCALL_BASE+351) | ||
381 | #define __NR_fallocate (__NR_SYSCALL_BASE+352) | ||
382 | #define __NR_timerfd_settime (__NR_SYSCALL_BASE+353) | ||
383 | #define __NR_timerfd_gettime (__NR_SYSCALL_BASE+354) | ||
384 | |||
385 | /* | ||
386 | * The following SWIs are ARM private. | ||
387 | */ | ||
388 | #define __ARM_NR_BASE (__NR_SYSCALL_BASE+0x0f0000) | ||
389 | #define __ARM_NR_breakpoint (__ARM_NR_BASE+1) | ||
390 | #define __ARM_NR_cacheflush (__ARM_NR_BASE+2) | ||
391 | #define __ARM_NR_usr26 (__ARM_NR_BASE+3) | ||
392 | #define __ARM_NR_usr32 (__ARM_NR_BASE+4) | ||
393 | #define __ARM_NR_set_tls (__ARM_NR_BASE+5) | ||
394 | |||
395 | /* | ||
396 | * The following syscalls are obsolete and no longer available for EABI. | ||
397 | */ | ||
398 | #if defined(__ARM_EABI__) && !defined(__KERNEL__) | ||
399 | #undef __NR_time | ||
400 | #undef __NR_umount | ||
401 | #undef __NR_stime | ||
402 | #undef __NR_alarm | ||
403 | #undef __NR_utime | ||
404 | #undef __NR_getrlimit | ||
405 | #undef __NR_select | ||
406 | #undef __NR_readdir | ||
407 | #undef __NR_mmap | ||
408 | #undef __NR_socketcall | ||
409 | #undef __NR_syscall | ||
410 | #undef __NR_ipc | ||
411 | #endif | ||
412 | |||
413 | #ifdef __KERNEL__ | ||
414 | |||
415 | #define __ARCH_WANT_IPC_PARSE_VERSION | ||
416 | #define __ARCH_WANT_STAT64 | ||
417 | #define __ARCH_WANT_SYS_GETHOSTNAME | ||
418 | #define __ARCH_WANT_SYS_PAUSE | ||
419 | #define __ARCH_WANT_SYS_GETPGRP | ||
420 | #define __ARCH_WANT_SYS_LLSEEK | ||
421 | #define __ARCH_WANT_SYS_NICE | ||
422 | #define __ARCH_WANT_SYS_SIGPENDING | ||
423 | #define __ARCH_WANT_SYS_SIGPROCMASK | ||
424 | #define __ARCH_WANT_SYS_RT_SIGACTION | ||
425 | |||
426 | #if !defined(CONFIG_AEABI) || defined(CONFIG_OABI_COMPAT) | ||
427 | #define __ARCH_WANT_SYS_TIME | ||
428 | #define __ARCH_WANT_SYS_OLDUMOUNT | ||
429 | #define __ARCH_WANT_SYS_ALARM | ||
430 | #define __ARCH_WANT_SYS_UTIME | ||
431 | #define __ARCH_WANT_SYS_OLD_GETRLIMIT | ||
432 | #define __ARCH_WANT_OLD_READDIR | ||
433 | #define __ARCH_WANT_SYS_SOCKETCALL | ||
434 | #endif | ||
435 | |||
436 | /* | ||
437 | * "Conditional" syscalls | ||
438 | * | ||
439 | * What we want is __attribute__((weak,alias("sys_ni_syscall"))), | ||
440 | * but it doesn't work on all toolchains, so we just do it by hand | ||
441 | */ | ||
442 | #define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall") | ||
443 | |||
444 | /* | ||
445 | * Unimplemented (or alternatively implemented) syscalls | ||
446 | */ | ||
447 | #define __IGNORE_fadvise64_64 1 | ||
448 | |||
449 | #endif /* __KERNEL__ */ | ||
450 | #endif /* __ASM_ARM_UNISTD_H */ | ||
diff --git a/arch/arm/include/asm/user.h b/arch/arm/include/asm/user.h new file mode 100644 index 000000000000..825c1e7c582d --- /dev/null +++ b/arch/arm/include/asm/user.h | |||
@@ -0,0 +1,84 @@ | |||
1 | #ifndef _ARM_USER_H | ||
2 | #define _ARM_USER_H | ||
3 | |||
4 | #include <asm/page.h> | ||
5 | #include <asm/ptrace.h> | ||
6 | /* Core file format: The core file is written in such a way that gdb | ||
7 | can understand it and provide useful information to the user (under | ||
8 | linux we use the 'trad-core' bfd). There are quite a number of | ||
9 | obstacles to being able to view the contents of the floating point | ||
10 | registers, and until these are solved you will not be able to view the | ||
11 | contents of them. Actually, you can read in the core file and look at | ||
12 | the contents of the user struct to find out what the floating point | ||
13 | registers contain. | ||
14 | The actual file contents are as follows: | ||
15 | UPAGE: 1 page consisting of a user struct that tells gdb what is present | ||
16 | in the file. Directly after this is a copy of the task_struct, which | ||
17 | is currently not used by gdb, but it may come in useful at some point. | ||
18 | All of the registers are stored as part of the upage. The upage should | ||
19 | always be only one page. | ||
20 | DATA: The data area is stored. We use current->end_text to | ||
21 | current->brk to pick up all of the user variables, plus any memory | ||
22 | that may have been malloced. No attempt is made to determine if a page | ||
23 | is demand-zero or if a page is totally unused, we just cover the entire | ||
24 | range. All of the addresses are rounded in such a way that an integral | ||
25 | number of pages is written. | ||
26 | STACK: We need the stack information in order to get a meaningful | ||
27 | backtrace. We need to write the data from (esp) to | ||
28 | current->start_stack, so we round each of these off in order to be able | ||
29 | to write an integer number of pages. | ||
30 | The minimum core file size is 3 pages, or 12288 bytes. | ||
31 | */ | ||
32 | |||
33 | struct user_fp { | ||
34 | struct fp_reg { | ||
35 | unsigned int sign1:1; | ||
36 | unsigned int unused:15; | ||
37 | unsigned int sign2:1; | ||
38 | unsigned int exponent:14; | ||
39 | unsigned int j:1; | ||
40 | unsigned int mantissa1:31; | ||
41 | unsigned int mantissa0:32; | ||
42 | } fpregs[8]; | ||
43 | unsigned int fpsr:32; | ||
44 | unsigned int fpcr:32; | ||
45 | unsigned char ftype[8]; | ||
46 | unsigned int init_flag; | ||
47 | }; | ||
48 | |||
49 | /* When the kernel dumps core, it starts by dumping the user struct - | ||
50 | this will be used by gdb to figure out where the data and stack segments | ||
51 | are within the file, and what virtual addresses to use. */ | ||
52 | struct user{ | ||
53 | /* We start with the registers, to mimic the way that "memory" is returned | ||
54 | from the ptrace(3,...) function. */ | ||
55 | struct pt_regs regs; /* Where the registers are actually stored */ | ||
56 | /* ptrace does not yet supply these. Someday.... */ | ||
57 | int u_fpvalid; /* True if math co-processor being used. */ | ||
58 | /* for this mess. Not yet used. */ | ||
59 | /* The rest of this junk is to help gdb figure out what goes where */ | ||
60 | unsigned long int u_tsize; /* Text segment size (pages). */ | ||
61 | unsigned long int u_dsize; /* Data segment size (pages). */ | ||
62 | unsigned long int u_ssize; /* Stack segment size (pages). */ | ||
63 | unsigned long start_code; /* Starting virtual address of text. */ | ||
64 | unsigned long start_stack; /* Starting virtual address of stack area. | ||
65 | This is actually the bottom of the stack, | ||
66 | the top of the stack is always found in the | ||
67 | esp register. */ | ||
68 | long int signal; /* Signal that caused the core dump. */ | ||
69 | int reserved; /* No longer used */ | ||
70 | unsigned long u_ar0; /* Used by gdb to help find the values for */ | ||
71 | /* the registers. */ | ||
72 | unsigned long magic; /* To uniquely identify a core file */ | ||
73 | char u_comm[32]; /* User command that was responsible */ | ||
74 | int u_debugreg[8]; | ||
75 | struct user_fp u_fp; /* FP state */ | ||
76 | struct user_fp_struct * u_fp0;/* Used by gdb to help find the values for */ | ||
77 | /* the FP registers. */ | ||
78 | }; | ||
79 | #define NBPG PAGE_SIZE | ||
80 | #define UPAGES 1 | ||
81 | #define HOST_TEXT_START_ADDR (u.start_code) | ||
82 | #define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG) | ||
83 | |||
84 | #endif /* _ARM_USER_H */ | ||
diff --git a/arch/arm/include/asm/vfp.h b/arch/arm/include/asm/vfp.h new file mode 100644 index 000000000000..f4ab34fd4f72 --- /dev/null +++ b/arch/arm/include/asm/vfp.h | |||
@@ -0,0 +1,84 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/vfp.h | ||
3 | * | ||
4 | * VFP register definitions. | ||
5 | * First, the standard VFP set. | ||
6 | */ | ||
7 | |||
8 | #define FPSID cr0 | ||
9 | #define FPSCR cr1 | ||
10 | #define MVFR1 cr6 | ||
11 | #define MVFR0 cr7 | ||
12 | #define FPEXC cr8 | ||
13 | #define FPINST cr9 | ||
14 | #define FPINST2 cr10 | ||
15 | |||
16 | /* FPSID bits */ | ||
17 | #define FPSID_IMPLEMENTER_BIT (24) | ||
18 | #define FPSID_IMPLEMENTER_MASK (0xff << FPSID_IMPLEMENTER_BIT) | ||
19 | #define FPSID_SOFTWARE (1<<23) | ||
20 | #define FPSID_FORMAT_BIT (21) | ||
21 | #define FPSID_FORMAT_MASK (0x3 << FPSID_FORMAT_BIT) | ||
22 | #define FPSID_NODOUBLE (1<<20) | ||
23 | #define FPSID_ARCH_BIT (16) | ||
24 | #define FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT) | ||
25 | #define FPSID_PART_BIT (8) | ||
26 | #define FPSID_PART_MASK (0xFF << FPSID_PART_BIT) | ||
27 | #define FPSID_VARIANT_BIT (4) | ||
28 | #define FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT) | ||
29 | #define FPSID_REV_BIT (0) | ||
30 | #define FPSID_REV_MASK (0xF << FPSID_REV_BIT) | ||
31 | |||
32 | /* FPEXC bits */ | ||
33 | #define FPEXC_EX (1 << 31) | ||
34 | #define FPEXC_EN (1 << 30) | ||
35 | #define FPEXC_DEX (1 << 29) | ||
36 | #define FPEXC_FP2V (1 << 28) | ||
37 | #define FPEXC_VV (1 << 27) | ||
38 | #define FPEXC_TFV (1 << 26) | ||
39 | #define FPEXC_LENGTH_BIT (8) | ||
40 | #define FPEXC_LENGTH_MASK (7 << FPEXC_LENGTH_BIT) | ||
41 | #define FPEXC_IDF (1 << 7) | ||
42 | #define FPEXC_IXF (1 << 4) | ||
43 | #define FPEXC_UFF (1 << 3) | ||
44 | #define FPEXC_OFF (1 << 2) | ||
45 | #define FPEXC_DZF (1 << 1) | ||
46 | #define FPEXC_IOF (1 << 0) | ||
47 | #define FPEXC_TRAP_MASK (FPEXC_IDF|FPEXC_IXF|FPEXC_UFF|FPEXC_OFF|FPEXC_DZF|FPEXC_IOF) | ||
48 | |||
49 | /* FPSCR bits */ | ||
50 | #define FPSCR_DEFAULT_NAN (1<<25) | ||
51 | #define FPSCR_FLUSHTOZERO (1<<24) | ||
52 | #define FPSCR_ROUND_NEAREST (0<<22) | ||
53 | #define FPSCR_ROUND_PLUSINF (1<<22) | ||
54 | #define FPSCR_ROUND_MINUSINF (2<<22) | ||
55 | #define FPSCR_ROUND_TOZERO (3<<22) | ||
56 | #define FPSCR_RMODE_BIT (22) | ||
57 | #define FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT) | ||
58 | #define FPSCR_STRIDE_BIT (20) | ||
59 | #define FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT) | ||
60 | #define FPSCR_LENGTH_BIT (16) | ||
61 | #define FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT) | ||
62 | #define FPSCR_IOE (1<<8) | ||
63 | #define FPSCR_DZE (1<<9) | ||
64 | #define FPSCR_OFE (1<<10) | ||
65 | #define FPSCR_UFE (1<<11) | ||
66 | #define FPSCR_IXE (1<<12) | ||
67 | #define FPSCR_IDE (1<<15) | ||
68 | #define FPSCR_IOC (1<<0) | ||
69 | #define FPSCR_DZC (1<<1) | ||
70 | #define FPSCR_OFC (1<<2) | ||
71 | #define FPSCR_UFC (1<<3) | ||
72 | #define FPSCR_IXC (1<<4) | ||
73 | #define FPSCR_IDC (1<<7) | ||
74 | |||
75 | /* MVFR0 bits */ | ||
76 | #define MVFR0_A_SIMD_BIT (0) | ||
77 | #define MVFR0_A_SIMD_MASK (0xf << MVFR0_A_SIMD_BIT) | ||
78 | |||
79 | /* Bit patterns for decoding the packaged operation descriptors */ | ||
80 | #define VFPOPDESC_LENGTH_BIT (9) | ||
81 | #define VFPOPDESC_LENGTH_MASK (0x07 << VFPOPDESC_LENGTH_BIT) | ||
82 | #define VFPOPDESC_UNUSED_BIT (24) | ||
83 | #define VFPOPDESC_UNUSED_MASK (0xFF << VFPOPDESC_UNUSED_BIT) | ||
84 | #define VFPOPDESC_OPDESC_MASK (~(VFPOPDESC_LENGTH_MASK | VFPOPDESC_UNUSED_MASK)) | ||
diff --git a/arch/arm/include/asm/vfpmacros.h b/arch/arm/include/asm/vfpmacros.h new file mode 100644 index 000000000000..422f3cc204a2 --- /dev/null +++ b/arch/arm/include/asm/vfpmacros.h | |||
@@ -0,0 +1,47 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/vfpmacros.h | ||
3 | * | ||
4 | * Assembler-only file containing VFP macros and register definitions. | ||
5 | */ | ||
6 | #include "vfp.h" | ||
7 | |||
8 | @ Macros to allow building with old toolkits (with no VFP support) | ||
9 | .macro VFPFMRX, rd, sysreg, cond | ||
10 | MRC\cond p10, 7, \rd, \sysreg, cr0, 0 @ FMRX \rd, \sysreg | ||
11 | .endm | ||
12 | |||
13 | .macro VFPFMXR, sysreg, rd, cond | ||
14 | MCR\cond p10, 7, \rd, \sysreg, cr0, 0 @ FMXR \sysreg, \rd | ||
15 | .endm | ||
16 | |||
17 | @ read all the working registers back into the VFP | ||
18 | .macro VFPFLDMIA, base, tmp | ||
19 | #if __LINUX_ARM_ARCH__ < 6 | ||
20 | LDC p11, cr0, [\base],#33*4 @ FLDMIAX \base!, {d0-d15} | ||
21 | #else | ||
22 | LDC p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d0-d15} | ||
23 | #endif | ||
24 | #ifdef CONFIG_VFPv3 | ||
25 | VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0 | ||
26 | and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field | ||
27 | cmp \tmp, #2 @ 32 x 64bit registers? | ||
28 | ldceql p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31} | ||
29 | addne \base, \base, #32*4 @ step over unused register space | ||
30 | #endif | ||
31 | .endm | ||
32 | |||
33 | @ write all the working registers out of the VFP | ||
34 | .macro VFPFSTMIA, base, tmp | ||
35 | #if __LINUX_ARM_ARCH__ < 6 | ||
36 | STC p11, cr0, [\base],#33*4 @ FSTMIAX \base!, {d0-d15} | ||
37 | #else | ||
38 | STC p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d0-d15} | ||
39 | #endif | ||
40 | #ifdef CONFIG_VFPv3 | ||
41 | VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0 | ||
42 | and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field | ||
43 | cmp \tmp, #2 @ 32 x 64bit registers? | ||
44 | stceql p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31} | ||
45 | addne \base, \base, #32*4 @ step over unused register space | ||
46 | #endif | ||
47 | .endm | ||
diff --git a/arch/arm/include/asm/vga.h b/arch/arm/include/asm/vga.h new file mode 100644 index 000000000000..1e0b913c3d71 --- /dev/null +++ b/arch/arm/include/asm/vga.h | |||
@@ -0,0 +1,12 @@ | |||
1 | #ifndef ASMARM_VGA_H | ||
2 | #define ASMARM_VGA_H | ||
3 | |||
4 | #include <asm/hardware.h> | ||
5 | #include <asm/io.h> | ||
6 | |||
7 | #define VGA_MAP_MEM(x,s) (PCIMEM_BASE + (x)) | ||
8 | |||
9 | #define vga_readb(x) (*((volatile unsigned char *)x)) | ||
10 | #define vga_writeb(x,y) (*((volatile unsigned char *)y) = (x)) | ||
11 | |||
12 | #endif | ||
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/asm/xor.h new file mode 100644 index 000000000000..7604673dc427 --- /dev/null +++ b/arch/arm/include/asm/xor.h | |||
@@ -0,0 +1,141 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/xor.h | ||
3 | * | ||
4 | * Copyright (C) 2001 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #include <asm-generic/xor.h> | ||
11 | |||
12 | #define __XOR(a1, a2) a1 ^= a2 | ||
13 | |||
14 | #define GET_BLOCK_2(dst) \ | ||
15 | __asm__("ldmia %0, {%1, %2}" \ | ||
16 | : "=r" (dst), "=r" (a1), "=r" (a2) \ | ||
17 | : "0" (dst)) | ||
18 | |||
19 | #define GET_BLOCK_4(dst) \ | ||
20 | __asm__("ldmia %0, {%1, %2, %3, %4}" \ | ||
21 | : "=r" (dst), "=r" (a1), "=r" (a2), "=r" (a3), "=r" (a4) \ | ||
22 | : "0" (dst)) | ||
23 | |||
24 | #define XOR_BLOCK_2(src) \ | ||
25 | __asm__("ldmia %0!, {%1, %2}" \ | ||
26 | : "=r" (src), "=r" (b1), "=r" (b2) \ | ||
27 | : "0" (src)); \ | ||
28 | __XOR(a1, b1); __XOR(a2, b2); | ||
29 | |||
30 | #define XOR_BLOCK_4(src) \ | ||
31 | __asm__("ldmia %0!, {%1, %2, %3, %4}" \ | ||
32 | : "=r" (src), "=r" (b1), "=r" (b2), "=r" (b3), "=r" (b4) \ | ||
33 | : "0" (src)); \ | ||
34 | __XOR(a1, b1); __XOR(a2, b2); __XOR(a3, b3); __XOR(a4, b4) | ||
35 | |||
36 | #define PUT_BLOCK_2(dst) \ | ||
37 | __asm__ __volatile__("stmia %0!, {%2, %3}" \ | ||
38 | : "=r" (dst) \ | ||
39 | : "0" (dst), "r" (a1), "r" (a2)) | ||
40 | |||
41 | #define PUT_BLOCK_4(dst) \ | ||
42 | __asm__ __volatile__("stmia %0!, {%2, %3, %4, %5}" \ | ||
43 | : "=r" (dst) \ | ||
44 | : "0" (dst), "r" (a1), "r" (a2), "r" (a3), "r" (a4)) | ||
45 | |||
46 | static void | ||
47 | xor_arm4regs_2(unsigned long bytes, unsigned long *p1, unsigned long *p2) | ||
48 | { | ||
49 | unsigned int lines = bytes / sizeof(unsigned long) / 4; | ||
50 | register unsigned int a1 __asm__("r4"); | ||
51 | register unsigned int a2 __asm__("r5"); | ||
52 | register unsigned int a3 __asm__("r6"); | ||
53 | register unsigned int a4 __asm__("r7"); | ||
54 | register unsigned int b1 __asm__("r8"); | ||
55 | register unsigned int b2 __asm__("r9"); | ||
56 | register unsigned int b3 __asm__("ip"); | ||
57 | register unsigned int b4 __asm__("lr"); | ||
58 | |||
59 | do { | ||
60 | GET_BLOCK_4(p1); | ||
61 | XOR_BLOCK_4(p2); | ||
62 | PUT_BLOCK_4(p1); | ||
63 | } while (--lines); | ||
64 | } | ||
65 | |||
66 | static void | ||
67 | xor_arm4regs_3(unsigned long bytes, unsigned long *p1, unsigned long *p2, | ||
68 | unsigned long *p3) | ||
69 | { | ||
70 | unsigned int lines = bytes / sizeof(unsigned long) / 4; | ||
71 | register unsigned int a1 __asm__("r4"); | ||
72 | register unsigned int a2 __asm__("r5"); | ||
73 | register unsigned int a3 __asm__("r6"); | ||
74 | register unsigned int a4 __asm__("r7"); | ||
75 | register unsigned int b1 __asm__("r8"); | ||
76 | register unsigned int b2 __asm__("r9"); | ||
77 | register unsigned int b3 __asm__("ip"); | ||
78 | register unsigned int b4 __asm__("lr"); | ||
79 | |||
80 | do { | ||
81 | GET_BLOCK_4(p1); | ||
82 | XOR_BLOCK_4(p2); | ||
83 | XOR_BLOCK_4(p3); | ||
84 | PUT_BLOCK_4(p1); | ||
85 | } while (--lines); | ||
86 | } | ||
87 | |||
88 | static void | ||
89 | xor_arm4regs_4(unsigned long bytes, unsigned long *p1, unsigned long *p2, | ||
90 | unsigned long *p3, unsigned long *p4) | ||
91 | { | ||
92 | unsigned int lines = bytes / sizeof(unsigned long) / 2; | ||
93 | register unsigned int a1 __asm__("r8"); | ||
94 | register unsigned int a2 __asm__("r9"); | ||
95 | register unsigned int b1 __asm__("ip"); | ||
96 | register unsigned int b2 __asm__("lr"); | ||
97 | |||
98 | do { | ||
99 | GET_BLOCK_2(p1); | ||
100 | XOR_BLOCK_2(p2); | ||
101 | XOR_BLOCK_2(p3); | ||
102 | XOR_BLOCK_2(p4); | ||
103 | PUT_BLOCK_2(p1); | ||
104 | } while (--lines); | ||
105 | } | ||
106 | |||
107 | static void | ||
108 | xor_arm4regs_5(unsigned long bytes, unsigned long *p1, unsigned long *p2, | ||
109 | unsigned long *p3, unsigned long *p4, unsigned long *p5) | ||
110 | { | ||
111 | unsigned int lines = bytes / sizeof(unsigned long) / 2; | ||
112 | register unsigned int a1 __asm__("r8"); | ||
113 | register unsigned int a2 __asm__("r9"); | ||
114 | register unsigned int b1 __asm__("ip"); | ||
115 | register unsigned int b2 __asm__("lr"); | ||
116 | |||
117 | do { | ||
118 | GET_BLOCK_2(p1); | ||
119 | XOR_BLOCK_2(p2); | ||
120 | XOR_BLOCK_2(p3); | ||
121 | XOR_BLOCK_2(p4); | ||
122 | XOR_BLOCK_2(p5); | ||
123 | PUT_BLOCK_2(p1); | ||
124 | } while (--lines); | ||
125 | } | ||
126 | |||
127 | static struct xor_block_template xor_block_arm4regs = { | ||
128 | .name = "arm4regs", | ||
129 | .do_2 = xor_arm4regs_2, | ||
130 | .do_3 = xor_arm4regs_3, | ||
131 | .do_4 = xor_arm4regs_4, | ||
132 | .do_5 = xor_arm4regs_5, | ||
133 | }; | ||
134 | |||
135 | #undef XOR_TRY_TEMPLATES | ||
136 | #define XOR_TRY_TEMPLATES \ | ||
137 | do { \ | ||
138 | xor_speed(&xor_block_arm4regs); \ | ||
139 | xor_speed(&xor_block_8regs); \ | ||
140 | xor_speed(&xor_block_32regs); \ | ||
141 | } while (0) | ||
diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S index 7e9c00a8a412..1c3c6ea5f9e7 100644 --- a/arch/arm/kernel/head-common.S +++ b/arch/arm/kernel/head-common.S | |||
@@ -181,7 +181,7 @@ ENTRY(lookup_processor_type) | |||
181 | ldmfd sp!, {r4 - r7, r9, pc} | 181 | ldmfd sp!, {r4 - r7, r9, pc} |
182 | 182 | ||
183 | /* | 183 | /* |
184 | * Look in include/asm-arm/procinfo.h and arch/arm/kernel/arch.[ch] for | 184 | * Look in <asm/procinfo.h> and arch/arm/kernel/arch.[ch] for |
185 | * more information about the __proc_info and __arch_info structures. | 185 | * more information about the __proc_info and __arch_info structures. |
186 | */ | 186 | */ |
187 | .long __proc_info_begin | 187 | .long __proc_info_begin |
diff --git a/arch/arm/lib/getuser.S b/arch/arm/lib/getuser.S index 1dd8ea4f9a9c..2034d4dbe6ad 100644 --- a/arch/arm/lib/getuser.S +++ b/arch/arm/lib/getuser.S | |||
@@ -20,7 +20,7 @@ | |||
20 | * r2, r3 contains the zero-extended value | 20 | * r2, r3 contains the zero-extended value |
21 | * lr corrupted | 21 | * lr corrupted |
22 | * | 22 | * |
23 | * No other registers must be altered. (see include/asm-arm/uaccess.h | 23 | * No other registers must be altered. (see <asm/uaccess.h> |
24 | * for specific ASM register usage). | 24 | * for specific ASM register usage). |
25 | * | 25 | * |
26 | * Note that ADDR_LIMIT is either 0 or 0xc0000000. | 26 | * Note that ADDR_LIMIT is either 0 or 0xc0000000. |
diff --git a/arch/arm/lib/putuser.S b/arch/arm/lib/putuser.S index 8620afe54f72..08ec7dffa52e 100644 --- a/arch/arm/lib/putuser.S +++ b/arch/arm/lib/putuser.S | |||
@@ -20,7 +20,7 @@ | |||
20 | * Outputs: r0 is the error code | 20 | * Outputs: r0 is the error code |
21 | * lr corrupted | 21 | * lr corrupted |
22 | * | 22 | * |
23 | * No other registers must be altered. (see include/asm-arm/uaccess.h | 23 | * No other registers must be altered. (see <asm/uaccess.h> |
24 | * for specific ASM register usage). | 24 | * for specific ASM register usage). |
25 | * | 25 | * |
26 | * Note that ADDR_LIMIT is either 0 or 0xc0000000 | 26 | * Note that ADDR_LIMIT is either 0 or 0xc0000000 |
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c index 303a7ff6bfd2..b81dbf9ffb77 100644 --- a/arch/arm/mm/ioremap.c +++ b/arch/arm/mm/ioremap.c | |||
@@ -259,7 +259,7 @@ remap_area_supersections(unsigned long virt, unsigned long pfn, | |||
259 | * caller shouldn't need to know that small detail. | 259 | * caller shouldn't need to know that small detail. |
260 | * | 260 | * |
261 | * 'flags' are the extra L_PTE_ flags that you want to specify for this | 261 | * 'flags' are the extra L_PTE_ flags that you want to specify for this |
262 | * mapping. See include/asm-arm/proc-armv/pgtable.h for more information. | 262 | * mapping. See <asm/pgtable.h> for more information. |
263 | */ | 263 | */ |
264 | void __iomem * | 264 | void __iomem * |
265 | __arm_ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size, | 265 | __arm_ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size, |
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S index d64f8e6f75ab..eda733d30455 100644 --- a/arch/arm/mm/proc-arm720.S +++ b/arch/arm/mm/proc-arm720.S | |||
@@ -231,7 +231,7 @@ cpu_arm720_name: | |||
231 | .align | 231 | .align |
232 | 232 | ||
233 | /* | 233 | /* |
234 | * See linux/include/asm-arm/procinfo.h for a definition of this structure. | 234 | * See <asm/procinfo.h> for a definition of this structure. |
235 | */ | 235 | */ |
236 | 236 | ||
237 | .section ".proc.info.init", #alloc, #execinstr | 237 | .section ".proc.info.init", #alloc, #execinstr |
diff --git a/arch/arm/nwfpe/fpa11.h b/arch/arm/nwfpe/fpa11.h index 4a4d02c09112..386cbd13eaf4 100644 --- a/arch/arm/nwfpe/fpa11.h +++ b/arch/arm/nwfpe/fpa11.h | |||
@@ -69,7 +69,7 @@ typedef union tagFPREG { | |||
69 | * This structure is exported to user space. Do not re-order. | 69 | * This structure is exported to user space. Do not re-order. |
70 | * Only add new stuff to the end, and do not change the size of | 70 | * Only add new stuff to the end, and do not change the size of |
71 | * any element. Elements of this structure are used by user | 71 | * any element. Elements of this structure are used by user |
72 | * space, and must match struct user_fp in include/asm-arm/user.h. | 72 | * space, and must match struct user_fp in <asm/user.h>. |
73 | * We include the byte offsets below for documentation purposes. | 73 | * We include the byte offsets below for documentation purposes. |
74 | * | 74 | * |
75 | * The size of this structure and FPREG are checked by fpmodule.c | 75 | * The size of this structure and FPREG are checked by fpmodule.c |