Merge branch 'omap2-upstream' into devel

176 files changed, 18960 insertions, 10686 deletions

diff --git a/arch/alpha/kernel/pci_iommu.c b/arch/alpha/kernel/pci_iommu.c
index 4e1c08636edd..dd6e334ab9e1 100644
--- a/arch/alpha/kernel/pci_iommu.c
+++ b/arch/alpha/kernel/pci_iommu.c
@@ -424,11 +424,13 @@ EXPORT_SYMBOL(pci_unmap_page);
    else DMA_ADDRP is undefined.  */
 
 void *
-pci_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_addrp)
+__pci_alloc_consistent(struct pci_dev *pdev, size_t size,
+                       dma_addr_t *dma_addrp, gfp_t gfp)
 {
         void *cpu_addr;
         long order = get_order(size);
-        gfp_t gfp = GFP_ATOMIC;
+
+        gfp &= ~GFP_DMA;
 
 try_again:
         cpu_addr = (void *)__get_free_pages(gfp, order);
@@ -458,7 +460,7 @@ try_again:
 
         return cpu_addr;
 }
-EXPORT_SYMBOL(pci_alloc_consistent);
+EXPORT_SYMBOL(__pci_alloc_consistent);
 
 /* Free and unmap a consistent DMA buffer.  CPU_ADDR and DMA_ADDR must
    be values that were returned from pci_alloc_consistent.  SIZE must
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ac1bef1797e6..a34cc03e727f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -476,6 +476,7 @@ config ARCH_DAVINCI
 config ARCH_OMAP
         bool "TI OMAP"
         select GENERIC_GPIO
+        select HAVE_GPIO_LIB
         select GENERIC_TIME
         select GENERIC_CLOCKEVENTS
         help
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
index 538262241483..5fe9588db077 100644
--- a/arch/arm/common/it8152.c
+++ b/arch/arm/common/it8152.c
@@ -120,6 +120,7 @@ void it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
                           time, when they all three were 0. */
                        bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
                        bits_lp = __raw_readl(IT8152_INTC_LPCNIRR);
+                       bits_ld = __raw_readl(IT8152_INTC_LDCNIRR);
                        if (!(bits_ld | bits_lp | bits_pd))
                                return;
                }
@@ -133,14 +134,14 @@ void it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
 
                bits_lp &= ((1 << IT8152_LP_IRQ_COUNT) - 1);
                while (bits_lp) {
-                       i = __ffs(bits_pd);
+                       i = __ffs(bits_lp);
                        it8152_irq(IT8152_LP_IRQ(i));
                        bits_lp &= ~(1 << i);
                }
 
                bits_ld &= ((1 << IT8152_LD_IRQ_COUNT) - 1);
                while (bits_ld) {
-                       i = __ffs(bits_pd);
+                       i = __ffs(bits_ld);
                        it8152_irq(IT8152_LD_IRQ(i));
                        bits_ld &= ~(1 << i);
                }
diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S
index 95f1c121cb30..30a67a5a40a8 100644
--- a/arch/arm/kernel/calls.S
+++ b/arch/arm/kernel/calls.S
@@ -336,7 +336,7 @@
                 CALL(sys_mknodat)
 /* 325 */       CALL(sys_fchownat)
                 CALL(sys_futimesat)
-                CALL(sys_fstatat64)
+                CALL(ABI(sys_fstatat64,  sys_oabi_fstatat64))
                 CALL(sys_unlinkat)
                 CALL(sys_renameat)
 /* 330 */       CALL(sys_linkat)
diff --git a/arch/arm/kernel/sys_oabi-compat.c b/arch/arm/kernel/sys_oabi-compat.c
index e8b98046895b..96ab5f52949c 100644
--- a/arch/arm/kernel/sys_oabi-compat.c
+++ b/arch/arm/kernel/sys_oabi-compat.c
@@ -25,6 +25,7 @@
  * sys_stat64:
  * sys_lstat64:
  * sys_fstat64:
+ * sys_fstatat64:
  *
  *   struct stat64 has different sizes and some members are shifted
  *   Compatibility wrappers are needed for them and provided below.
@@ -169,6 +170,29 @@ asmlinkage long sys_oabi_fstat64(unsigned long fd,
         return error;
 }
 
+asmlinkage long sys_oabi_fstatat64(int dfd,
+                                   char __user *filename,
+                                   struct oldabi_stat64  __user *statbuf,
+                                   int flag)
+{
+        struct kstat stat;
+        int error = -EINVAL;
+
+        if ((flag & ~AT_SYMLINK_NOFOLLOW) != 0)
+                goto out;
+
+        if (flag & AT_SYMLINK_NOFOLLOW)
+                error = vfs_lstat_fd(dfd, filename, &stat);
+        else
+                error = vfs_stat_fd(dfd, filename, &stat);
+
+        if (!error)
+        error = cp_oldabi_stat64(&stat, statbuf);
+
+out:
+        return error;
+}
+
 struct oabi_flock64 {
         short   l_type;
         short   l_whence;
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 015a66b3ca8e..c06f5254c0f3 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -5,7 +5,8 @@
 # Common support
 obj-y := io.o id.o clock.o irq.o mux.o serial.o devices.o
 
-obj-$(CONFIG_OMAP_MPU_TIMER)            += time.o
+obj-$(CONFIG_OMAP_MPU_TIMER)    += time.o
+obj-$(CONFIG_OMAP_32K_TIMER)    += timer32k.o
 
 # Power Management
 obj-$(CONFIG_PM) += pm.o sleep.o
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 5279e35a8aec..4f9baba7d893 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -32,6 +32,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/i2c.h>
+#include <linux/leds.h>
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
@@ -183,11 +184,80 @@ static struct platform_device *osk5912_devices[] __initdata = {
         &osk5912_mcbsp1_device,
 };
 
+static struct gpio_led tps_leds[] = {
+        /* NOTE:  D9 and D2 have hardware blink support.
+         * Also, D9 requires non-battery power.
+         */
+        { .gpio = OSK_TPS_GPIO_LED_D9, .name = "d9", },
+        { .gpio = OSK_TPS_GPIO_LED_D2, .name = "d2", },
+        { .gpio = OSK_TPS_GPIO_LED_D3, .name = "d3", .active_low = 1,
+                        .default_trigger = "heartbeat", },
+};
+
+static struct gpio_led_platform_data tps_leds_data = {
+        .num_leds       = 3,
+        .leds           = tps_leds,
+};
+
+static struct platform_device osk5912_tps_leds = {
+        .name                   = "leds-gpio",
+        .id                     = 0,
+        .dev.platform_data      = &tps_leds_data,
+};
+
+static int osk_tps_setup(struct i2c_client *client, void *context)
+{
+        /* Set GPIO 1 HIGH to disable VBUS power supply;
+         * OHCI driver powers it up/down as needed.
+         */
+        gpio_request(OSK_TPS_GPIO_USB_PWR_EN, "n_vbus_en");
+        gpio_direction_output(OSK_TPS_GPIO_USB_PWR_EN, 1);
+
+        /* Set GPIO 2 high so LED D3 is off by default */
+        tps65010_set_gpio_out_value(GPIO2, HIGH);
+
+        /* Set GPIO 3 low to take ethernet out of reset */
+        gpio_request(OSK_TPS_GPIO_LAN_RESET, "smc_reset");
+        gpio_direction_output(OSK_TPS_GPIO_LAN_RESET, 0);
+
+        /* GPIO4 is VDD_DSP */
+        gpio_request(OSK_TPS_GPIO_DSP_PWR_EN, "dsp_power");
+        gpio_direction_output(OSK_TPS_GPIO_DSP_PWR_EN, 1);
+        /* REVISIT if DSP support isn't configured, power it off ... */
+
+        /* Let LED1 (D9) blink; leds-gpio may override it */
+        tps65010_set_led(LED1, BLINK);
+
+        /* Set LED2 off by default */
+        tps65010_set_led(LED2, OFF);
+
+        /* Enable LOW_PWR handshake */
+        tps65010_set_low_pwr(ON);
+
+        /* Switch VLDO2 to 3.0V for AIC23 */
+        tps65010_config_vregs1(TPS_LDO2_ENABLE | TPS_VLDO2_3_0V
+                        | TPS_LDO1_ENABLE);
+
+        /* register these three LEDs */
+        osk5912_tps_leds.dev.parent = &client->dev;
+        platform_device_register(&osk5912_tps_leds);
+
+        return 0;
+}
+
+static struct tps65010_board tps_board = {
+        .base           = OSK_TPS_GPIO_BASE,
+        .outmask        = 0x0f,
+        .setup          = osk_tps_setup,
+};
+
 static struct i2c_board_info __initdata osk_i2c_board_info[] = {
         {
                 I2C_BOARD_INFO("tps65010", 0x48),
                 .type           = "tps65010",
                 .irq            = OMAP_GPIO_IRQ(OMAP_MPUIO(1)),
+                .platform_data  = &tps_board,
+
         },
         /* TODO when driver support is ready:
          *  - aic23 audio chip at 0x1a
@@ -198,7 +268,7 @@ static struct i2c_board_info __initdata osk_i2c_board_info[] = {
 
 static void __init osk_init_smc91x(void)
 {
-        if ((omap_request_gpio(0)) < 0) {
+        if ((gpio_request(0, "smc_irq")) < 0) {
                 printk("Error requesting gpio 0 for smc91x irq\n");
                 return;
         }
@@ -210,7 +280,7 @@ static void __init osk_init_smc91x(void)
 static void __init osk_init_cf(void)
 {
         omap_cfg_reg(M7_1610_GPIO62);
-        if ((omap_request_gpio(62)) < 0) {
+        if ((gpio_request(62, "cf_irq")) < 0) {
                 printk("Error requesting gpio 62 for CF irq\n");
                 return;
         }
@@ -334,7 +404,7 @@ static struct platform_device *mistral_devices[] __initdata = {
 
 static int mistral_get_pendown_state(void)
 {
-        return !omap_get_gpio_datain(4);
+        return !gpio_get_value(4);
 }
 
 static const struct ads7846_platform_data mistral_ts_info = {
@@ -396,25 +466,31 @@ static void __init osk_mistral_init(void)
         omap_cfg_reg(W14_1610_CCP_DATAP);
 
         /* CAM_PWDN */
-        if (omap_request_gpio(11) == 0) {
+        if (gpio_request(11, "cam_pwdn") == 0) {
                 omap_cfg_reg(N20_1610_GPIO11);
-                omap_set_gpio_direction(11, 0 /* out */);
-                omap_set_gpio_dataout(11, 0 /* off */);
+                gpio_direction_output(11, 0);
         } else
                 pr_debug("OSK+Mistral: CAM_PWDN is awol\n");
 
 
         /* omap_cfg_reg(P19_1610_GPIO6); */     /* BUSY */
+        gpio_request(6, "ts_busy");
+        gpio_direction_input(6);
+
         omap_cfg_reg(P20_1610_GPIO4);   /* PENIRQ */
+        gpio_request(4, "ts_int");
+        gpio_direction_input(4);
         set_irq_type(OMAP_GPIO_IRQ(4), IRQT_FALLING);
+
         spi_register_board_info(mistral_boardinfo,
                         ARRAY_SIZE(mistral_boardinfo));
 
         /* the sideways button (SW1) is for use as a "wakeup" button */
         omap_cfg_reg(N15_1610_MPUIO2);
-        if (omap_request_gpio(OMAP_MPUIO(2)) == 0) {
+        if (gpio_request(OMAP_MPUIO(2), "wakeup") == 0) {
                 int ret = 0;
-                omap_set_gpio_direction(OMAP_MPUIO(2), 1);
+
+                gpio_direction_input(OMAP_MPUIO(2));
                 set_irq_type(OMAP_GPIO_IRQ(OMAP_MPUIO(2)), IRQT_RISING);
 #ifdef  CONFIG_PM
                 /* share the IRQ in case someone wants to use the
@@ -425,7 +501,7 @@ static void __init osk_mistral_init(void)
                                 IRQF_SHARED, "mistral_wakeup",
                                 &osk_mistral_wake_interrupt);
                 if (ret != 0) {
-                        omap_free_gpio(OMAP_MPUIO(2));
+                        gpio_free(OMAP_MPUIO(2));
                         printk(KERN_ERR "OSK+Mistral: no wakeup irq, %d?\n",
                                 ret);
                 } else
@@ -438,10 +514,8 @@ static void __init osk_mistral_init(void)
          * board, like the touchscreen, EEPROM, and wakeup (!) switch.
          */
         omap_cfg_reg(PWL);
-        if (omap_request_gpio(2) == 0) {
-                omap_set_gpio_direction(2, 0 /* out */);
-                omap_set_gpio_dataout(2, 1 /* on */);
-        }
+        if (gpio_request(2, "lcd_pwr") == 0)
+                gpio_direction_output(2, 1);
 
         platform_add_devices(mistral_devices, ARRAY_SIZE(mistral_devices));
 }
@@ -484,44 +558,6 @@ static void __init osk_map_io(void)
         omap1_map_common_io();
 }
 
-#ifdef CONFIG_TPS65010
-static int __init osk_tps_init(void)
-{
-        if (!machine_is_omap_osk())
-                return 0;
-
-        /* Let LED1 (D9) blink */
-        tps65010_set_led(LED1, BLINK);
-
-        /* Disable LED 2 (D2) */
-        tps65010_set_led(LED2, OFF);
-
-        /* Set GPIO 1 HIGH to disable VBUS power supply;
-         * OHCI driver powers it up/down as needed.
-         */
-        tps65010_set_gpio_out_value(GPIO1, HIGH);
-
-        /* Set GPIO 2 low to turn on LED D3 */
-        tps65010_set_gpio_out_value(GPIO2, HIGH);
-
-        /* Set GPIO 3 low to take ethernet out of reset */
-        tps65010_set_gpio_out_value(GPIO3, LOW);
-
-        /* gpio4 for VDD_DSP */
-        /* FIXME send power to DSP iff it's configured */
-
-        /* Enable LOW_PWR */
-        tps65010_set_low_pwr(ON);
-
-        /* Switch VLDO2 to 3.0V for AIC23 */
-        tps65010_config_vregs1(TPS_LDO2_ENABLE | TPS_VLDO2_3_0V
-                        | TPS_LDO1_ENABLE);
-
-        return 0;
-}
-fs_initcall(osk_tps_init);
-#endif
-
 MACHINE_START(OMAP_OSK, "TI-OSK")
         /* Maintainer: Dirk Behme <dirk.behme@de.bosch.com> */
         .phys_io        = 0xfff00000,
diff --git a/arch/arm/mach-omap1/leds-osk.c b/arch/arm/mach-omap1/leds-osk.c
index 026685ed461a..754383dde807 100644
--- a/arch/arm/mach-omap1/leds-osk.c
+++ b/arch/arm/mach-omap1/leds-osk.c
@@ -1,11 +1,9 @@
 /*
  * linux/arch/arm/mach-omap1/leds-osk.c
  *
- * LED driver for OSK, and optionally Mistral QVGA, boards
+ * LED driver for OSK with optional Mistral QVGA board
  */
 #include <linux/init.h>
-#include <linux/workqueue.h>
-#include <linux/i2c/tps65010.h>
 
 #include <asm/hardware.h>
 #include <asm/leds.h>
@@ -20,49 +18,11 @@
 #define LED_STATE_CLAIMED       (1 << 1)
 static u8 led_state;
 
-#define GREEN_LED               (1 << 0)        /* TPS65010 LED1 */
-#define AMBER_LED               (1 << 1)        /* TPS65010 LED2 */
-#define RED_LED                 (1 << 2)        /* TPS65010 GPIO2 */
 #define TIMER_LED               (1 << 3)        /* Mistral board */
 #define IDLE_LED                (1 << 4)        /* Mistral board */
 static u8 hw_led_state;
 
 
-/* TPS65010 leds are changed using i2c -- from a task context.
- * Using one of these for the "idle" LED would be impractical...
- */
-#define TPS_LEDS        (GREEN_LED | RED_LED | AMBER_LED)
-
-static u8 tps_leds_change;
-
-static void tps_work(struct work_struct *unused)
-{
-        for (;;) {
-                u8      leds;
-
-                local_irq_disable();
-                leds = tps_leds_change;
-                tps_leds_change = 0;
-                local_irq_enable();
-
-                if (!leds)
-                        break;
-
-                /* careful:  the set_led() value is on/off/blink */
-                if (leds & GREEN_LED)
-                        tps65010_set_led(LED1, !!(hw_led_state & GREEN_LED));
-                if (leds & AMBER_LED)
-                        tps65010_set_led(LED2, !!(hw_led_state & AMBER_LED));
-
-                /* the gpio led doesn't have that issue */
-                if (leds & RED_LED)
-                        tps65010_set_gpio_out_value(GPIO2,
-                                        !(hw_led_state & RED_LED));
-        }
-}
-
-static DECLARE_WORK(work, tps_work);
-
 #ifdef  CONFIG_OMAP_OSK_MISTRAL
 
 /* For now, all system indicators require the Mistral board, since that
@@ -112,7 +72,6 @@ void osk_leds_event(led_event_t evt)
         case led_stop:
                 led_state &= ~LED_STATE_ENABLED;
                 hw_led_state = 0;
-                /* NOTE:  work may still be pending!! */
                 break;
 
         case led_claim:
@@ -145,48 +104,11 @@ void osk_leds_event(led_event_t evt)
 
 #endif  /* CONFIG_OMAP_OSK_MISTRAL */
 
-        /* "green" == tps LED1 (leftmost, normally power-good)
-         * works only with DC adapter, not on battery power!
-         */
-        case led_green_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= GREEN_LED;
-                break;
-        case led_green_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~GREEN_LED;
-                break;
-
-        /* "amber" == tps LED2 (middle) */
-        case led_amber_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= AMBER_LED;
-                break;
-        case led_amber_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~AMBER_LED;
-                break;
-
-        /* "red" == LED on tps gpio3 (rightmost) */
-        case led_red_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= RED_LED;
-                break;
-        case led_red_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~RED_LED;
-                break;
-
         default:
                 break;
         }
 
         leds ^= hw_led_state;
-        leds &= TPS_LEDS;
-        if (leds && (led_state & LED_STATE_CLAIMED)) {
-                tps_leds_change |= leds;
-                schedule_work(&work);
-        }
 
 done:
         local_irq_restore(flags);
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c
index 52c70e5fcf65..e207bf7cb853 100644
--- a/arch/arm/mach-omap1/mux.c
+++ b/arch/arm/mach-omap1/mux.c
@@ -3,9 +3,9 @@
  *
  * OMAP1 pin multiplexing configurations
  *
- * Copyright (C) 2003 - 2005 Nokia Corporation
+ * Copyright (C) 2003 - 2008 Nokia Corporation
  *
- * Written by Tony Lindgren <tony.lindgren@nokia.com>
+ * Written by Tony Lindgren
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -32,8 +32,10 @@
 
 #ifdef CONFIG_OMAP_MUX
 
+static struct omap_mux_cfg arch_mux_cfg;
+
 #ifdef CONFIG_ARCH_OMAP730
-struct pin_config __initdata_or_module omap730_pins[] = {
+static struct pin_config __initdata_or_module omap730_pins[] = {
 MUX_CFG_730("E2_730_KBR0",        12,   21,    0,   20,   1, 0)
 MUX_CFG_730("J7_730_KBR1",        12,   25,    0,   24,   1, 0)
 MUX_CFG_730("E1_730_KBR2",        12,   29,    0,   28,   1, 0)
@@ -49,10 +51,14 @@ MUX_CFG_730("AA17_730_USB_DM",     2,   21,    0,   20,   0, 0)
 MUX_CFG_730("W16_730_USB_PU_EN",   2,   25,    0,   24,   0, 0)
 MUX_CFG_730("W17_730_USB_VBUSI",   2,   29,    0,   28,   0, 0)
 };
-#endif
+#define OMAP730_PINS_SZ         ARRAY_SIZE(omap730_pins)
+#else
+#define omap730_pins            NULL
+#define OMAP730_PINS_SZ         0
+#endif  /* CONFIG_ARCH_OMAP730 */
 
 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
-struct pin_config __initdata_or_module omap1xxx_pins[] = {
+static struct pin_config __initdata_or_module omap1xxx_pins[] = {
 /*
  *       description            mux  mode   mux  pull pull  pull  pu_pd  pu  dbg
  *                              reg  offset mode reg  bit   ena   reg
@@ -306,22 +312,136 @@ MUX_CFG("Y12_1610_CCP_CLKP",	 8,   18,    6,   1,  24,   1,    1,     0,  0)
 MUX_CFG("W13_1610_CCP_CLKM",     9,    0,    6,   1,  28,   1,    1,     0,  0)
 MUX_CFG("W14_1610_CCP_DATAP",    9,   24,    6,   2,   4,   1,    2,     0,  0)
 MUX_CFG("Y14_1610_CCP_DATAM",    9,   21,    6,   2,   3,   1,    2,     0,  0)
-
 };
+#define OMAP1XXX_PINS_SZ        ARRAY_SIZE(omap1xxx_pins)
+#else
+#define omap1xxx_pins           NULL
+#define OMAP1XXX_PINS_SZ        0
 #endif  /* CONFIG_ARCH_OMAP15XX || CONFIG_ARCH_OMAP16XX */
 
-int __init omap1_mux_init(void)
+int __init_or_module omap1_cfg_reg(const struct pin_config *cfg)
 {
-
-#ifdef CONFIG_ARCH_OMAP730
-        omap_mux_register(omap730_pins, ARRAY_SIZE(omap730_pins));
+        static DEFINE_SPINLOCK(mux_spin_lock);
+        unsigned long flags;
+        unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
+                pull_orig = 0, pull = 0;
+        unsigned int mask, warn = 0;
+
+        /* Check the mux register in question */
+        if (cfg->mux_reg) {
+                unsigned        tmp1, tmp2;
+
+                spin_lock_irqsave(&mux_spin_lock, flags);
+                reg_orig = omap_readl(cfg->mux_reg);
+
+                /* The mux registers always seem to be 3 bits long */
+                mask = (0x7 << cfg->mask_offset);
+                tmp1 = reg_orig & mask;
+                reg = reg_orig & ~mask;
+
+                tmp2 = (cfg->mask << cfg->mask_offset);
+                reg |= tmp2;
+
+                if (tmp1 != tmp2)
+                        warn = 1;
+
+                omap_writel(reg, cfg->mux_reg);
+                spin_unlock_irqrestore(&mux_spin_lock, flags);
+        }
+
+        /* Check for pull up or pull down selection on 1610 */
+        if (!cpu_is_omap15xx()) {
+                if (cfg->pu_pd_reg && cfg->pull_val) {
+                        spin_lock_irqsave(&mux_spin_lock, flags);
+                        pu_pd_orig = omap_readl(cfg->pu_pd_reg);
+                        mask = 1 << cfg->pull_bit;
+
+                        if (cfg->pu_pd_val) {
+                                if (!(pu_pd_orig & mask))
+                                        warn = 1;
+                                /* Use pull up */
+                                pu_pd = pu_pd_orig | mask;
+                        } else {
+                                if (pu_pd_orig & mask)
+                                        warn = 1;
+                                /* Use pull down */
+                                pu_pd = pu_pd_orig & ~mask;
+                        }
+                        omap_writel(pu_pd, cfg->pu_pd_reg);
+                        spin_unlock_irqrestore(&mux_spin_lock, flags);
+                }
+        }
+
+        /* Check for an associated pull down register */
+        if (cfg->pull_reg) {
+                spin_lock_irqsave(&mux_spin_lock, flags);
+                pull_orig = omap_readl(cfg->pull_reg);
+                mask = 1 << cfg->pull_bit;
+
+                if (cfg->pull_val) {
+                        if (pull_orig & mask)
+                                warn = 1;
+                        /* Low bit = pull enabled */
+                        pull = pull_orig & ~mask;
+                } else {
+                        if (!(pull_orig & mask))
+                                warn = 1;
+                        /* High bit = pull disabled */
+                        pull = pull_orig | mask;
+                }
+
+                omap_writel(pull, cfg->pull_reg);
+                spin_unlock_irqrestore(&mux_spin_lock, flags);
+        }
+
+        if (warn) {
+#ifdef CONFIG_OMAP_MUX_WARNINGS
+                printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
 #endif
-
-#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
-        omap_mux_register(omap1xxx_pins, ARRAY_SIZE(omap1xxx_pins));
+        }
+
+#ifdef CONFIG_OMAP_MUX_DEBUG
+        if (cfg->debug || warn) {
+                printk("MUX: Setting register %s\n", cfg->name);
+                printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
+                       cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
+
+                if (!cpu_is_omap15xx()) {
+                        if (cfg->pu_pd_reg && cfg->pull_val) {
+                                printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
+                                       cfg->pu_pd_name, cfg->pu_pd_reg,
+                                       pu_pd_orig, pu_pd);
+                        }
+                }
+
+                if (cfg->pull_reg)
+                        printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
+                               cfg->pull_name, cfg->pull_reg, pull_orig, pull);
+        }
 #endif
 
+#ifdef CONFIG_OMAP_MUX_ERRORS
+        return warn ? -ETXTBSY : 0;
+#else
         return 0;
+#endif
+}
+
+int __init omap1_mux_init(void)
+{
+        if (cpu_is_omap730()) {
+                arch_mux_cfg.pins       = omap730_pins;
+                arch_mux_cfg.size       = OMAP730_PINS_SZ;
+                arch_mux_cfg.cfg_reg    = omap1_cfg_reg;
+        }
+
+        if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
+                arch_mux_cfg.pins       = omap1xxx_pins;
+                arch_mux_cfg.size       = OMAP1XXX_PINS_SZ;
+                arch_mux_cfg.cfg_reg    = omap1_cfg_reg;
+        }
+
+        return omap_mux_register(&arch_mux_cfg);
 }
 
 #endif
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index a4f8b2055437..5d2b270935a2 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -56,37 +56,6 @@
 #define OMAP_MPU_TIMER_BASE             OMAP_MPU_TIMER1_BASE
 #define OMAP_MPU_TIMER_OFFSET           0x100
 
-/* cycles to nsec conversions taken from arch/i386/kernel/timers/timer_tsc.c,
- * converted to use kHz by Kevin Hilman */
-/* convert from cycles(64bits) => nanoseconds (64bits)
- *  basic equation:
- *              ns = cycles / (freq / ns_per_sec)
- *              ns = cycles * (ns_per_sec / freq)
- *              ns = cycles * (10^9 / (cpu_khz * 10^3))
- *              ns = cycles * (10^6 / cpu_khz)
- *
- *      Then we use scaling math (suggested by george at mvista.com) to get:
- *              ns = cycles * (10^6 * SC / cpu_khz / SC
- *              ns = cycles * cyc2ns_scale / SC
- *
- *      And since SC is a constant power of two, we can convert the div
- *  into a shift.
- *                      -johnstul at us.ibm.com "math is hard, lets go shopping!"
- */
-static unsigned long cyc2ns_scale;
-#define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
-
-static inline void set_cyc2ns_scale(unsigned long cpu_khz)
-{
-        cyc2ns_scale = (1000000 << CYC2NS_SCALE_FACTOR)/cpu_khz;
-}
-
-static inline unsigned long long cycles_2_ns(unsigned long long cyc)
-{
-        return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR;
-}
-
-
 typedef struct {
         u32 cntl;                       /* CNTL_TIMER, R/W */
         u32 load_tim;                   /* LOAD_TIM,   W */
@@ -194,8 +163,6 @@ static struct irqaction omap_mpu_timer1_irq = {
 
 static __init void omap_init_mpu_timer(unsigned long rate)
 {
-        set_cyc2ns_scale(rate / 1000);
-
         setup_irq(INT_TIMER1, &omap_mpu_timer1_irq);
         omap_mpu_timer_start(0, (rate / HZ) - 1, 1);
 
@@ -260,22 +227,6 @@ static void __init omap_init_clocksource(unsigned long rate)
                 printk(err, clocksource_mpu.name);
 }
 
-
-/*
- * Scheduler clock - returns current time in nanosec units.
- */
-unsigned long long sched_clock(void)
-{
-        unsigned long ticks = 0 - omap_mpu_timer_read(1);
-        unsigned long long ticks64;
-
-        ticks64 = omap_mpu_timer2_overflows;
-        ticks64 <<= 32;
-        ticks64 |= ticks;
-
-        return cycles_2_ns(ticks64);
-}
-
 /*
  * ---------------------------------------------------------------------------
  * Timer initialization
diff --git a/arch/arm/plat-omap/timer32k.c b/arch/arm/mach-omap1/timer32k.c
index ea76f1979a3d..fbbdb806c95a 100644
--- a/arch/arm/plat-omap/timer32k.c
+++ b/arch/arm/mach-omap1/timer32k.c
@@ -1,5 +1,5 @@
 /*
- * linux/arch/arm/plat-omap/timer32k.c
+ * linux/arch/arm/mach-omap1/timer32k.c
  *
  * OMAP 32K Timer
  *
@@ -70,8 +70,6 @@ struct sys_timer omap_timer;
 
 #if defined(CONFIG_ARCH_OMAP16XX)
 #define TIMER_32K_SYNCHRONIZED          0xfffbc410
-#elif defined(CONFIG_ARCH_OMAP24XX)
-#define TIMER_32K_SYNCHRONIZED          (OMAP24XX_32KSYNCT_BASE + 0x10)
 #else
 #error OMAP 32KHz timer does not currently work on 15XX!
 #endif
@@ -93,8 +91,6 @@ struct sys_timer omap_timer;
 #define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate)                     \
                                 (((nr_jiffies) * (clock_rate)) / HZ)
 
-#if defined(CONFIG_ARCH_OMAP1)
-
 static inline void omap_32k_timer_write(int val, int reg)
 {
         omap_writew(val, OMAP1_32K_TIMER_BASE + reg);
@@ -120,30 +116,14 @@ static inline void omap_32k_timer_stop(void)
 
 #define omap_32k_timer_ack_irq()
 
-#elif defined(CONFIG_ARCH_OMAP2)
-
-static struct omap_dm_timer *gptimer;
-
-static inline void omap_32k_timer_start(unsigned long load_val)
-{
-        omap_dm_timer_set_load(gptimer, 1, 0xffffffff - load_val);
-        omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
-        omap_dm_timer_start(gptimer);
-}
-
-static inline void omap_32k_timer_stop(void)
+static int omap_32k_timer_set_next_event(unsigned long delta,
+                                         struct clock_event_device *dev)
 {
-        omap_dm_timer_stop(gptimer);
-}
+        omap_32k_timer_start(delta);
 
-static inline void omap_32k_timer_ack_irq(void)
-{
-        u32 status = omap_dm_timer_read_status(gptimer);
-        omap_dm_timer_write_status(gptimer, status);
+        return 0;
 }
 
-#endif
-
 static void omap_32k_timer_set_mode(enum clock_event_mode mode,
                                     struct clock_event_device *evt)
 {
@@ -164,8 +144,9 @@ static void omap_32k_timer_set_mode(enum clock_event_mode mode,
 
 static struct clock_event_device clockevent_32k_timer = {
         .name           = "32k-timer",
-        .features       = CLOCK_EVT_FEAT_PERIODIC,
+        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
         .shift          = 32,
+        .set_next_event = omap_32k_timer_set_next_event,
         .set_mode       = omap_32k_timer_set_mode,
 };
 
@@ -178,32 +159,6 @@ static inline unsigned long omap_32k_sync_timer_read(void)
         return omap_readl(TIMER_32K_SYNCHRONIZED);
 }
 
-/*
- * Rounds down to nearest usec. Note that this will overflow for larger values.
- */
-static inline unsigned long omap_32k_ticks_to_usecs(unsigned long ticks_32k)
-{
-        return (ticks_32k * 5*5*5*5*5*5) >> 9;
-}
-
-/*
- * Rounds down to nearest nsec.
- */
-static inline unsigned long long
-omap_32k_ticks_to_nsecs(unsigned long ticks_32k)
-{
-        return (unsigned long long) ticks_32k * 1000 * 5*5*5*5*5*5 >> 9;
-}
-
-/*
- * Returns current time from boot in nsecs. It's OK for this to wrap
- * around for now, as it's just a relative time stamp.
- */
-unsigned long long sched_clock(void)
-{
-        return omap_32k_ticks_to_nsecs(omap_32k_sync_timer_read());
-}
-
 static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id)
 {
         struct clock_event_device *evt = &clockevent_32k_timer;
@@ -222,22 +177,7 @@ static struct irqaction omap_32k_timer_irq = {
 
 static __init void omap_init_32k_timer(void)
 {
-        if (cpu_class_is_omap1())
-                setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
-
-#ifdef CONFIG_ARCH_OMAP2
-        /* REVISIT: Check 24xx TIOCP_CFG settings after idle works */
-        if (cpu_is_omap24xx()) {
-                gptimer = omap_dm_timer_request_specific(1);
-                BUG_ON(gptimer == NULL);
-
-                omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ);
-                setup_irq(omap_dm_timer_get_irq(gptimer), &omap_32k_timer_irq);
-                omap_dm_timer_set_int_enable(gptimer,
-                        OMAP_TIMER_INT_CAPTURE | OMAP_TIMER_INT_OVERFLOW |
-                        OMAP_TIMER_INT_MATCH);
-        }
-#endif
+        setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
 
         clockevent_32k_timer.mult = div_sc(OMAP_32K_TICKS_PER_SEC,
                                            NSEC_PER_SEC,
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index b05b738d31e6..2feb6870b735 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -3,13 +3,15 @@
 #
 
 # Common support
-obj-y := irq.o id.o io.o sram-fn.o memory.o prcm.o clock.o mux.o devices.o \
-         serial.o gpmc.o
-
-obj-$(CONFIG_OMAP_MPU_TIMER)            += timer-gp.o
+obj-y := irq.o id.o io.o sram-fn.o memory.o control.o prcm.o clock.o mux.o \
+                devices.o serial.o gpmc.o timer-gp.o
 
 # Power Management
-obj-$(CONFIG_PM) += pm.o pm-domain.o sleep.o
+obj-$(CONFIG_PM) += pm.o sleep.o
+
+# Clock framework
+obj-$(CONFIG_ARCH_OMAP2)                += clock24xx.o
+obj-$(CONFIG_ARCH_OMAP3)                += clock34xx.o
 
 # Specific board support
 obj-$(CONFIG_MACH_OMAP_GENERIC)         += board-generic.o
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 64235dee5614..1c12d7c6c7fc 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -33,7 +33,6 @@
 #include <asm/arch/board.h>
 #include <asm/arch/common.h>
 #include <asm/arch/gpmc.h>
-#include "prcm-regs.h"
 
 #include <asm/io.h>
 
@@ -125,15 +124,18 @@ static inline void __init sdp2430_init_smc91x(void)
         int eth_cs;
         unsigned long cs_mem_base;
         unsigned int rate;
-        struct clk *l3ck;
+        struct clk *gpmc_fck;
 
         eth_cs = SDP2430_SMC91X_CS;
 
-        l3ck = clk_get(NULL, "core_l3_ck");
-        if (IS_ERR(l3ck))
-                rate = 100000000;
-        else
-                rate = clk_get_rate(l3ck);
+        gpmc_fck = clk_get(NULL, "gpmc_fck");   /* Always on ENABLE_ON_INIT */
+        if (IS_ERR(gpmc_fck)) {
+                WARN_ON(1);
+                return;
+        }
+
+        clk_enable(gpmc_fck);
+        rate = clk_get_rate(gpmc_fck);
 
         /* Make sure CS1 timings are correct, for 2430 always muxed */
         gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200);
@@ -160,7 +162,7 @@ static inline void __init sdp2430_init_smc91x(void)
 
         if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
                 printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
-                return;
+                goto out;
         }
 
         sdp2430_smc91x_resources[0].start = cs_mem_base + 0x300;
@@ -171,10 +173,13 @@ static inline void __init sdp2430_init_smc91x(void)
                 printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
                         OMAP24XX_ETHR_GPIO_IRQ);
                 gpmc_cs_free(eth_cs);
-                return;
+                goto out;
         }
         omap_set_gpio_direction(OMAP24XX_ETHR_GPIO_IRQ, 1);
 
+out:
+        clk_disable(gpmc_fck);
+        clk_put(gpmc_fck);
 }
 
 static void __init omap_2430sdp_init_irq(void)
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 7846551f0575..a1e1e6765b5b 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -26,6 +26,8 @@
 #include <linux/interrupt.h>
 #include <linux/delay.h>
 #include <linux/leds.h>
+#include <linux/err.h>
+#include <linux/clk.h>
 
 #include <asm/hardware.h>
 #include <asm/mach-types.h>
@@ -39,7 +41,7 @@
 #include <asm/arch/board.h>
 #include <asm/arch/common.h>
 #include <asm/arch/gpmc.h>
-#include "prcm-regs.h"
+#include <asm/arch/control.h>
 
 /* LED & Switch macros */
 #define LED0_GPIO13             13
@@ -187,17 +189,47 @@ static inline void __init apollon_init_smc91x(void)
 {
         unsigned long base;
 
+        unsigned int rate;
+        struct clk *gpmc_fck;
+        int eth_cs;
+
+        gpmc_fck = clk_get(NULL, "gpmc_fck");   /* Always on ENABLE_ON_INIT */
+        if (IS_ERR(gpmc_fck)) {
+                WARN_ON(1);
+                return;
+        }
+
+        clk_enable(gpmc_fck);
+        rate = clk_get_rate(gpmc_fck);
+
+        eth_cs = APOLLON_ETH_CS;
+
         /* Make sure CS1 timings are correct */
-        GPMC_CONFIG1_1 = 0x00011203;
-        GPMC_CONFIG2_1 = 0x001f1f01;
-        GPMC_CONFIG3_1 = 0x00080803;
-        GPMC_CONFIG4_1 = 0x1c091c09;
-        GPMC_CONFIG5_1 = 0x041f1f1f;
-        GPMC_CONFIG6_1 = 0x000004c4;
+        gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200);
+
+        if (rate >= 160000000) {
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
+        } else if (rate >= 130000000) {
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
+        } else {/* rate = 100000000 */
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2);
+        }
 
         if (gpmc_cs_request(APOLLON_ETH_CS, SZ_16M, &base) < 0) {
                 printk(KERN_ERR "Failed to request GPMC CS for smc91x\n");
-                return;
+                goto out;
         }
         apollon_smc91x_resources[0].start = base + 0x300;
         apollon_smc91x_resources[0].end   = base + 0x30f;
@@ -208,9 +240,13 @@ static inline void __init apollon_init_smc91x(void)
                 printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
                         APOLLON_ETHR_GPIO_IRQ);
                 gpmc_cs_free(APOLLON_ETH_CS);
-                return;
+                goto out;
         }
         omap_set_gpio_direction(APOLLON_ETHR_GPIO_IRQ, 1);
+
+out:
+        clk_disable(gpmc_fck);
+        clk_put(gpmc_fck);
 }
 
 static void __init omap_apollon_init_irq(void)
@@ -330,6 +366,8 @@ static void __init apollon_usb_init(void)
 
 static void __init omap_apollon_init(void)
 {
+        u32 v;
+
         apollon_led_init();
         apollon_sw_init();
         apollon_flash_init();
@@ -339,7 +377,9 @@ static void __init omap_apollon_init(void)
         omap_cfg_reg(W19_24XX_SYS_NIRQ);
 
         /* Use Interal loop-back in MMC/SDIO Module Input Clock selection */
-        CONTROL_DEVCONF |= (1 << 24);
+        v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+        v |= (1 << 24);
+        omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
 
         /*
          * Make sure the serial ports are muxed on at this point.
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index f125f432cc3e..d1915f99a5fa 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -19,6 +19,8 @@
 #include <linux/delay.h>
 #include <linux/workqueue.h>
 #include <linux/input.h>
+#include <linux/err.h>
+#include <linux/clk.h>
 
 #include <asm/hardware.h>
 #include <asm/mach-types.h>
@@ -26,6 +28,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 
+#include <asm/arch/control.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/gpioexpander.h>
 #include <asm/arch/mux.h>
@@ -36,10 +39,13 @@
 #include <asm/arch/keypad.h>
 #include <asm/arch/menelaus.h>
 #include <asm/arch/dma.h>
-#include "prcm-regs.h"
+#include <asm/arch/gpmc.h>
 
 #include <asm/io.h>
 
+#define H4_FLASH_CS     0
+#define H4_SMC91X_CS    1
+
 static unsigned int row_gpios[6] = { 88, 89, 124, 11, 6, 96 };
 static unsigned int col_gpios[7] = { 90, 91, 100, 36, 12, 97, 98 };
 
@@ -116,8 +122,6 @@ static struct flash_platform_data h4_flash_data = {
 };
 
 static struct resource h4_flash_resource = {
-        .start          = H4_CS0_BASE,
-        .end            = H4_CS0_BASE + SZ_64M - 1,
         .flags          = IORESOURCE_MEM,
 };
 
@@ -253,21 +257,107 @@ static struct platform_device *h4_devices[] __initdata = {
         &h4_lcd_device,
 };
 
+/* 2420 Sysboot setup (2430 is different) */
+static u32 get_sysboot_value(void)
+{
+        return (omap_ctrl_readl(OMAP24XX_CONTROL_STATUS) &
+                (OMAP2_SYSBOOT_5_MASK | OMAP2_SYSBOOT_4_MASK |
+                 OMAP2_SYSBOOT_3_MASK | OMAP2_SYSBOOT_2_MASK |
+                 OMAP2_SYSBOOT_1_MASK | OMAP2_SYSBOOT_0_MASK));
+}
+
+/* H4-2420's always used muxed mode, H4-2422's always use non-muxed
+ *
+ * Note: OMAP-GIT doesn't correctly do is_cpu_omap2422 and is_cpu_omap2423
+ *  correctly.  The macro needs to look at production_id not just hawkeye.
+ */
+static u32 is_gpmc_muxed(void)
+{
+        u32 mux;
+        mux = get_sysboot_value();
+        if ((mux & 0xF) == 0xd)
+                return 1;       /* NAND config (could be either) */
+        if (mux & 0x2)          /* if mux'ed */
+                return 1;
+        else
+                return 0;
+}
+
 static inline void __init h4_init_debug(void)
 {
+        int eth_cs;
+        unsigned long cs_mem_base;
+        unsigned int muxed, rate;
+        struct clk *gpmc_fck;
+
+        eth_cs  = H4_SMC91X_CS;
+
+        gpmc_fck = clk_get(NULL, "gpmc_fck");   /* Always on ENABLE_ON_INIT */
+        if (IS_ERR(gpmc_fck)) {
+                WARN_ON(1);
+                return;
+        }
+
+        clk_enable(gpmc_fck);
+        rate = clk_get_rate(gpmc_fck);
+        clk_disable(gpmc_fck);
+        clk_put(gpmc_fck);
+
+        if (is_gpmc_muxed())
+                muxed = 0x200;
+        else
+                muxed = 0;
+
         /* Make sure CS1 timings are correct */
-        GPMC_CONFIG1_1 = 0x00011200;
-        GPMC_CONFIG2_1 = 0x001f1f01;
-        GPMC_CONFIG3_1 = 0x00080803;
-        GPMC_CONFIG4_1 = 0x1c091c09;
-        GPMC_CONFIG5_1 = 0x041f1f1f;
-        GPMC_CONFIG6_1 = 0x000004c4;
-        GPMC_CONFIG7_1 = 0x00000f40 | (0x08000000 >> 24);
+        gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1,
+                          0x00011000 | muxed);
+
+        if (rate >= 160000000) {
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
+        } else if (rate >= 130000000) {
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
+        } else {/* rate = 100000000 */
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2);
+        }
+
+        if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
+                printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
+                goto out;
+        }
+
         udelay(100);
 
         omap_cfg_reg(M15_24XX_GPIO92);
         if (debug_card_init(cs_mem_base, OMAP24XX_ETHR_GPIO_IRQ) < 0)
                 gpmc_cs_free(eth_cs);
+
+out:
+        clk_disable(gpmc_fck);
+        clk_put(gpmc_fck);
+}
+
+static void __init h4_init_flash(void)
+{
+        unsigned long base;
+
+        if (gpmc_cs_request(H4_FLASH_CS, SZ_64M, &base) < 0) {
+                printk("Can't request GPMC CS for flash\n");
+                return;
+        }
+        h4_flash_resource.start = base;
+        h4_flash_resource.end   = base + SZ_64M - 1;
 }
 
 static void __init omap_h4_init_irq(void)
@@ -275,6 +365,7 @@ static void __init omap_h4_init_irq(void)
         omap2_init_common_hw();
         omap_init_irq();
         omap_gpio_init();
+        h4_init_flash();
 }
 
 static struct omap_uart_config h4_uart_config __initdata = {
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index e6e85b7b097b..b57ffb5a22a5 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -1,20 +1,19 @@
 /*
  *  linux/arch/arm/mach-omap2/clock.c
  *
- *  Copyright (C) 2005 Texas Instruments Inc.
- *  Richard Woodruff <r-woodruff2@ti.com>
- *  Created for OMAP2.
- *
- *  Cleaned up and modified to use omap shared clock framework by
- *  Tony Lindgren <tony@atomide.com>
+ *  Copyright (C) 2005-2008 Texas Instruments, Inc.
+ *  Copyright (C) 2004-2008 Nokia Corporation
  *
- *  Based on omap1 clock.c, Copyright (C) 2004 - 2005 Nokia corporation
- *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
+ *  Contacts:
+ *  Richard Woodruff <r-woodruff2@ti.com>
+ *  Paul Walmsley
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#undef DEBUG
+
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/device.h>
@@ -22,176 +21,227 @@
 #include <linux/errno.h>
 #include <linux/delay.h>
 #include <linux/clk.h>
+#include <asm/bitops.h>
 
 #include <asm/io.h>
 
 #include <asm/arch/clock.h>
 #include <asm/arch/sram.h>
+#include <asm/arch/cpu.h>
 #include <asm/div64.h>
 
-#include "prcm-regs.h"
 #include "memory.h"
+#include "sdrc.h"
 #include "clock.h"
+#include "prm.h"
+#include "prm-regbits-24xx.h"
+#include "cm.h"
+#include "cm-regbits-24xx.h"
+#include "cm-regbits-34xx.h"
 
-#undef DEBUG
-
-//#define DOWN_VARIABLE_DPLL 1                  /* Experimental */
+#define MAX_CLOCK_ENABLE_WAIT           100000
 
-static struct prcm_config *curr_prcm_set;
-static u32 curr_perf_level = PRCM_FULL_SPEED;
-static struct clk *vclk;
-static struct clk *sclk;
+u8 cpu_mask;
 
 /*-------------------------------------------------------------------------
  * Omap2 specific clock functions
  *-------------------------------------------------------------------------*/
 
-/* Recalculate SYST_CLK */
-static void omap2_sys_clk_recalc(struct clk * clk)
+/**
+ * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
+ * @clk: OMAP clock struct ptr to use
+ *
+ * Given a pointer to a source-selectable struct clk, read the hardware
+ * register and determine what its parent is currently set to.  Update the
+ * clk->parent field with the appropriate clk ptr.
+ */
+void omap2_init_clksel_parent(struct clk *clk)
 {
-        u32 div = PRCM_CLKSRC_CTRL;
-        div &= (1 << 7) | (1 << 6);     /* Test if ext clk divided by 1 or 2 */
-        div >>= clk->rate_offset;
-        clk->rate = (clk->parent->rate / div);
-        propagate_rate(clk);
+        const struct clksel *clks;
+        const struct clksel_rate *clkr;
+        u32 r, found = 0;
+
+        if (!clk->clksel)
+                return;
+
+        r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
+        r >>= __ffs(clk->clksel_mask);
+
+        for (clks = clk->clksel; clks->parent && !found; clks++) {
+                for (clkr = clks->rates; clkr->div && !found; clkr++) {
+                        if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
+                                if (clk->parent != clks->parent) {
+                                        pr_debug("clock: inited %s parent "
+                                                 "to %s (was %s)\n",
+                                                 clk->name, clks->parent->name,
+                                                 ((clk->parent) ?
+                                                  clk->parent->name : "NULL"));
+                                        clk->parent = clks->parent;
+                                };
+                                found = 1;
+                        }
+                }
+        }
+
+        if (!found)
+                printk(KERN_ERR "clock: init parent: could not find "
+                       "regval %0x for clock %s\n", r,  clk->name);
+
+        return;
 }
 
-static u32 omap2_get_dpll_rate(struct clk * tclk)
+/* Returns the DPLL rate */
+u32 omap2_get_dpll_rate(struct clk *clk)
 {
         long long dpll_clk;
-        int dpll_mult, dpll_div, amult;
+        u32 dpll_mult, dpll_div, dpll;
+        const struct dpll_data *dd;
+
+        dd = clk->dpll_data;
+        /* REVISIT: What do we return on error? */
+        if (!dd)
+                return 0;
+
+        dpll = __raw_readl(dd->mult_div1_reg);
+        dpll_mult = dpll & dd->mult_mask;
+        dpll_mult >>= __ffs(dd->mult_mask);
+        dpll_div = dpll & dd->div1_mask;
+        dpll_div >>= __ffs(dd->div1_mask);
 
-        dpll_mult = (CM_CLKSEL1_PLL >> 12) & 0x03ff;    /* 10 bits */
-        dpll_div = (CM_CLKSEL1_PLL >> 8) & 0x0f;        /* 4 bits */
-        dpll_clk = (long long)tclk->parent->rate * dpll_mult;
+        dpll_clk = (long long)clk->parent->rate * dpll_mult;
         do_div(dpll_clk, dpll_div + 1);
-        amult = CM_CLKSEL2_PLL & 0x3;
-        dpll_clk *= amult;
 
         return dpll_clk;
 }
 
-static void omap2_followparent_recalc(struct clk *clk)
-{
-        followparent_recalc(clk);
-}
-
-static void omap2_propagate_rate(struct clk * clk)
+/*
+ * Used for clocks that have the same value as the parent clock,
+ * divided by some factor
+ */
+void omap2_fixed_divisor_recalc(struct clk *clk)
 {
-        if (!(clk->flags & RATE_FIXED))
-                clk->rate = clk->parent->rate;
+        WARN_ON(!clk->fixed_div);
 
-        propagate_rate(clk);
-}
+        clk->rate = clk->parent->rate / clk->fixed_div;
 
-static void omap2_set_osc_ck(int enable)
-{
-        if (enable)
-                PRCM_CLKSRC_CTRL &= ~(0x3 << 3);
-        else
-                PRCM_CLKSRC_CTRL |= 0x3 << 3;
+        if (clk->flags & RATE_PROPAGATES)
+                propagate_rate(clk);
 }
 
-/* Enable an APLL if off */
-static void omap2_clk_fixed_enable(struct clk *clk)
+/**
+ * omap2_wait_clock_ready - wait for clock to enable
+ * @reg: physical address of clock IDLEST register
+ * @mask: value to mask against to determine if the clock is active
+ * @name: name of the clock (for printk)
+ *
+ * Returns 1 if the clock enabled in time, or 0 if it failed to enable
+ * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
+ */
+int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
 {
-        u32 cval, i=0;
+        int i = 0;
+        int ena = 0;
 
-        if (clk->enable_bit == 0xff)                    /* Parent will do it */
-                return;
+        /*
+         * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
+         * 34xx reverses this, just to keep us on our toes
+         */
+        if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) {
+                ena = mask;
+        } else if (cpu_mask & RATE_IN_343X) {
+                ena = 0;
+        }
 
-        cval = CM_CLKEN_PLL;
+        /* Wait for lock */
+        while (((__raw_readl(reg) & mask) != ena) &&
+               (i++ < MAX_CLOCK_ENABLE_WAIT)) {
+                udelay(1);
+        }
 
-        if ((cval & (0x3 << clk->enable_bit)) == (0x3 << clk->enable_bit))
-                return;
+        if (i < MAX_CLOCK_ENABLE_WAIT)
+                pr_debug("Clock %s stable after %d loops\n", name, i);
+        else
+                printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
+                       name, MAX_CLOCK_ENABLE_WAIT);
 
-        cval &= ~(0x3 << clk->enable_bit);
-        cval |= (0x3 << clk->enable_bit);
-        CM_CLKEN_PLL = cval;
 
-        if (clk == &apll96_ck)
-                cval = (1 << 8);
-        else if (clk == &apll54_ck)
-                cval = (1 << 6);
+        return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
+};
 
-        while (!(CM_IDLEST_CKGEN & cval)) {             /* Wait for lock */
-                ++i;
-                udelay(1);
-                if (i == 100000) {
-                        printk(KERN_ERR "Clock %s didn't lock\n", clk->name);
-                        break;
-                }
-        }
-}
 
+/*
+ * Note: We don't need special code here for INVERT_ENABLE
+ * for the time being since INVERT_ENABLE only applies to clocks enabled by
+ * CM_CLKEN_PLL
+ */
 static void omap2_clk_wait_ready(struct clk *clk)
 {
-        unsigned long reg, other_reg, st_reg;
+        void __iomem *reg, *other_reg, *st_reg;
         u32 bit;
-        int i;
-
-        reg = (unsigned long) clk->enable_reg;
-        if (reg == (unsigned long) &CM_FCLKEN1_CORE ||
-            reg == (unsigned long) &CM_FCLKEN2_CORE)
-                other_reg = (reg & ~0xf0) | 0x10;
-        else if (reg == (unsigned long) &CM_ICLKEN1_CORE ||
-                 reg == (unsigned long) &CM_ICLKEN2_CORE)
-                other_reg = (reg & ~0xf0) | 0x00;
+
+        /*
+         * REVISIT: This code is pretty ugly.  It would be nice to generalize
+         * it and pull it into struct clk itself somehow.
+         */
+        reg = clk->enable_reg;
+        if ((((u32)reg & 0xff) >= CM_FCLKEN1) &&
+            (((u32)reg & 0xff) <= OMAP24XX_CM_FCLKEN2))
+                other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x10); /* CM_ICLKEN* */
+        else if ((((u32)reg & 0xff) >= CM_ICLKEN1) &&
+                 (((u32)reg & 0xff) <= OMAP24XX_CM_ICLKEN4))
+                other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x00); /* CM_FCLKEN* */
         else
                 return;
 
+        /* REVISIT: What are the appropriate exclusions for 34XX? */
         /* No check for DSS or cam clocks */
-        if ((reg & 0x0f) == 0) {
-                if (clk->enable_bit <= 1 || clk->enable_bit == 31)
+        if (cpu_is_omap24xx() && ((u32)reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
+                if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
+                    clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT ||
+                    clk->enable_bit == OMAP24XX_EN_CAM_SHIFT)
                         return;
         }
 
+        /* REVISIT: What are the appropriate exclusions for 34XX? */
+        /* OMAP3: ignore DSS-mod clocks */
+        if (cpu_is_omap34xx() &&
+            (((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(OMAP3430_DSS_MOD, 0)))
+                return;
+
         /* Check if both functional and interface clocks
          * are running. */
         bit = 1 << clk->enable_bit;
         if (!(__raw_readl(other_reg) & bit))
                 return;
-        st_reg = (other_reg & ~0xf0) | 0x20;
-        i = 0;
-        while (!(__raw_readl(st_reg) & bit)) {
-                i++;
-                if (i == 100000) {
-                        printk(KERN_ERR "Timeout enabling clock %s\n", clk->name);
-                        break;
-                }
-        }
-        if (i)
-                pr_debug("Clock %s stable after %d loops\n", clk->name, i);
+        st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
+
+        omap2_wait_clock_ready(st_reg, bit, clk->name);
 }
 
 /* Enables clock without considering parent dependencies or use count
  * REVISIT: Maybe change this to use clk->enable like on omap1?
  */
-static int _omap2_clk_enable(struct clk * clk)
+int _omap2_clk_enable(struct clk *clk)
 {
         u32 regval32;
 
-        if (clk->flags & ALWAYS_ENABLED)
+        if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
                 return 0;
 
-        if (unlikely(clk == &osc_ck)) {
-                omap2_set_osc_ck(1);
-                return 0;
-        }
+        if (clk->enable)
+                return clk->enable(clk);
 
         if (unlikely(clk->enable_reg == 0)) {
                 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
                        clk->name);
-                return 0;
-        }
-
-        if (clk->enable_reg == (void __iomem *)&CM_CLKEN_PLL) {
-                omap2_clk_fixed_enable(clk);
-                return 0;
+                return 0; /* REVISIT: -EINVAL */
         }
 
         regval32 = __raw_readl(clk->enable_reg);
-        regval32 |= (1 << clk->enable_bit);
+        if (clk->flags & INVERT_ENABLE)
+                regval32 &= ~(1 << clk->enable_bit);
+        else
+                regval32 |= (1 << clk->enable_bit);
         __raw_writel(regval32, clk->enable_reg);
         wmb();
 
@@ -200,44 +250,48 @@ static int _omap2_clk_enable(struct clk * clk)
         return 0;
 }
 
-/* Stop APLL */
-static void omap2_clk_fixed_disable(struct clk *clk)
-{
-        u32 cval;
-
-        if(clk->enable_bit == 0xff)             /* let parent off do it */
-                return;
-
-        cval = CM_CLKEN_PLL;
-        cval &= ~(0x3 << clk->enable_bit);
-        CM_CLKEN_PLL = cval;
-}
-
 /* Disables clock without considering parent dependencies or use count */
-static void _omap2_clk_disable(struct clk *clk)
+void _omap2_clk_disable(struct clk *clk)
 {
         u32 regval32;
 
-        if (unlikely(clk == &osc_ck)) {
-                omap2_set_osc_ck(0);
+        if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
                 return;
-        }
 
-        if (clk->enable_reg == 0)
+        if (clk->disable) {
+                clk->disable(clk);
                 return;
+        }
 
-        if (clk->enable_reg == (void __iomem *)&CM_CLKEN_PLL) {
-                omap2_clk_fixed_disable(clk);
+        if (clk->enable_reg == 0) {
+                /*
+                 * 'Independent' here refers to a clock which is not
+                 * controlled by its parent.
+                 */
+                printk(KERN_ERR "clock: clk_disable called on independent "
+                       "clock %s which has no enable_reg\n", clk->name);
                 return;
         }
 
         regval32 = __raw_readl(clk->enable_reg);
-        regval32 &= ~(1 << clk->enable_bit);
+        if (clk->flags & INVERT_ENABLE)
+                regval32 |= (1 << clk->enable_bit);
+        else
+                regval32 &= ~(1 << clk->enable_bit);
         __raw_writel(regval32, clk->enable_reg);
         wmb();
 }
 
-static int omap2_clk_enable(struct clk *clk)
+void omap2_clk_disable(struct clk *clk)
+{
+        if (clk->usecount > 0 && !(--clk->usecount)) {
+                _omap2_clk_disable(clk);
+                if (likely((u32)clk->parent))
+                        omap2_clk_disable(clk->parent);
+        }
+}
+
+int omap2_clk_enable(struct clk *clk)
 {
         int ret = 0;
 
@@ -261,519 +315,314 @@ static int omap2_clk_enable(struct clk *clk)
         return ret;
 }
 
-static void omap2_clk_disable(struct clk *clk)
-{
-        if (clk->usecount > 0 && !(--clk->usecount)) {
-                _omap2_clk_disable(clk);
-                if (likely((u32)clk->parent))
-                        omap2_clk_disable(clk->parent);
-        }
-}
-
-/*
- * Uses the current prcm set to tell if a rate is valid.
- * You can go slower, but not faster within a given rate set.
- */
-static u32 omap2_dpll_round_rate(unsigned long target_rate)
-{
-        u32 high, low;
-
-        if ((CM_CLKSEL2_PLL & 0x3) == 1) {      /* DPLL clockout */
-                high = curr_prcm_set->dpll_speed * 2;
-                low = curr_prcm_set->dpll_speed;
-        } else {                                /* DPLL clockout x 2 */
-                high = curr_prcm_set->dpll_speed;
-                low = curr_prcm_set->dpll_speed / 2;
-        }
-
-#ifdef DOWN_VARIABLE_DPLL
-        if (target_rate > high)
-                return high;
-        else
-                return target_rate;
-#else
-        if (target_rate > low)
-                return high;
-        else
-                return low;
-#endif
-
-}
-
 /*
  * Used for clocks that are part of CLKSEL_xyz governed clocks.
  * REVISIT: Maybe change to use clk->enable() functions like on omap1?
  */
-static void omap2_clksel_recalc(struct clk * clk)
+void omap2_clksel_recalc(struct clk *clk)
 {
-        u32 fixed = 0, div = 0;
+        u32 div = 0;
 
-        if (clk == &dpll_ck) {
-                clk->rate = omap2_get_dpll_rate(clk);
-                fixed = 1;
-                div = 0;
-        }
+        pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
 
-        if (clk == &iva1_mpu_int_ifck) {
-                div = 2;
-                fixed = 1;
-        }
-
-        if ((clk == &dss1_fck) && ((CM_CLKSEL1_CORE & (0x1f << 8)) == 0)) {
-                clk->rate = sys_ck.rate;
+        div = omap2_clksel_get_divisor(clk);
+        if (div == 0)
                 return;
-        }
 
-        if (!fixed) {
-                div = omap2_clksel_get_divisor(clk);
-                if (div == 0)
-                        return;
-        }
+        if (unlikely(clk->rate == clk->parent->rate / div))
+                return;
+        clk->rate = clk->parent->rate / div;
 
-        if (div != 0) {
-                if (unlikely(clk->rate == clk->parent->rate / div))
-                        return;
-                clk->rate = clk->parent->rate / div;
-        }
+        pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);
 
         if (unlikely(clk->flags & RATE_PROPAGATES))
                 propagate_rate(clk);
 }
 
-/*
- * Finds best divider value in an array based on the source and target
- * rates. The divider array must be sorted with smallest divider first.
+/**
+ * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
+ * @clk: OMAP struct clk ptr to inspect
+ * @src_clk: OMAP struct clk ptr of the parent clk to search for
+ *
+ * Scan the struct clksel array associated with the clock to find
+ * the element associated with the supplied parent clock address.
+ * Returns a pointer to the struct clksel on success or NULL on error.
  */
-static inline u32 omap2_divider_from_table(u32 size, u32 *div_array,
-                                           u32 src_rate, u32 tgt_rate)
+const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
+                                                struct clk *src_clk)
 {
-        int i, test_rate;
+        const struct clksel *clks;
 
-        if (div_array == NULL)
-                return ~1;
+        if (!clk->clksel)
+                return NULL;
 
-        for (i=0; i < size; i++) {
-                test_rate = src_rate / *div_array;
-                if (test_rate <= tgt_rate)
-                        return *div_array;
-                ++div_array;
+        for (clks = clk->clksel; clks->parent; clks++) {
+                if (clks->parent == src_clk)
+                        break; /* Found the requested parent */
         }
 
-        return ~0;      /* No acceptable divider */
+        if (!clks->parent) {
+                printk(KERN_ERR "clock: Could not find parent clock %s in "
+                       "clksel array of clock %s\n", src_clk->name,
+                       clk->name);
+                return NULL;
+        }
+
+        return clks;
 }
 
-/*
- * Find divisor for the given clock and target rate.
+/**
+ * omap2_clksel_round_rate_div - find divisor for the given clock and rate
+ * @clk: OMAP struct clk to use
+ * @target_rate: desired clock rate
+ * @new_div: ptr to where we should store the divisor
  *
+ * Finds 'best' divider value in an array based on the source and target
+ * rates.  The divider array must be sorted with smallest divider first.
  * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
  * they are only settable as part of virtual_prcm set.
+ *
+ * Returns the rounded clock rate or returns 0xffffffff on error.
  */
-static u32 omap2_clksel_round_rate(struct clk *tclk, u32 target_rate,
-        u32 *new_div)
+u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
+                                u32 *new_div)
 {
-        u32 gfx_div[] = {2, 3, 4};
-        u32 sysclkout_div[] = {1, 2, 4, 8, 16};
-        u32 dss1_div[] = {1, 2, 3, 4, 5, 6, 8, 9, 12, 16};
-        u32 vylnq_div[] = {1, 2, 3, 4, 6, 8, 9, 12, 16, 18};
-        u32 best_div = ~0, asize = 0;
-        u32 *div_array = NULL;
-
-        switch (tclk->flags & SRC_RATE_SEL_MASK) {
-        case CM_GFX_SEL1:
-                asize = 3;
-                div_array = gfx_div;
-                break;
-        case CM_PLL_SEL1:
-                return omap2_dpll_round_rate(target_rate);
-        case CM_SYSCLKOUT_SEL1:
-                asize = 5;
-                div_array = sysclkout_div;
-                break;
-        case CM_CORE_SEL1:
-                if(tclk == &dss1_fck){
-                        if(tclk->parent == &core_ck){
-                                asize = 10;
-                                div_array = dss1_div;
-                        } else {
-                                *new_div = 0; /* fixed clk */
-                                return(tclk->parent->rate);
-                        }
-                } else if((tclk == &vlynq_fck) && cpu_is_omap2420()){
-                        if(tclk->parent == &core_ck){
-                                asize = 10;
-                                div_array = vylnq_div;
-                        } else {
-                                *new_div = 0; /* fixed clk */
-                                return(tclk->parent->rate);
-                        }
-                }
-                break;
+        unsigned long test_rate;
+        const struct clksel *clks;
+        const struct clksel_rate *clkr;
+        u32 last_div = 0;
+
+        printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
+               clk->name, target_rate);
+
+        *new_div = 1;
+
+        clks = omap2_get_clksel_by_parent(clk, clk->parent);
+        if (clks == NULL)
+                return ~0;
+
+        for (clkr = clks->rates; clkr->div; clkr++) {
+                if (!(clkr->flags & cpu_mask))
+                    continue;
+
+                /* Sanity check */
+                if (clkr->div <= last_div)
+                        printk(KERN_ERR "clock: clksel_rate table not sorted "
+                               "for clock %s", clk->name);
+
+                last_div = clkr->div;
+
+                test_rate = clk->parent->rate / clkr->div;
+
+                if (test_rate <= target_rate)
+                        break; /* found it */
         }
 
-        best_div = omap2_divider_from_table(asize, div_array,
-         tclk->parent->rate, target_rate);
-        if (best_div == ~0){
-                *new_div = 1;
-                return best_div; /* signal error */
+        if (!clkr->div) {
+                printk(KERN_ERR "clock: Could not find divisor for target "
+                       "rate %ld for clock %s parent %s\n", target_rate,
+                       clk->name, clk->parent->name);
+                return ~0;
         }
 
-        *new_div = best_div;
-        return (tclk->parent->rate / best_div);
+        *new_div = clkr->div;
+
+        printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
+               (clk->parent->rate / clkr->div));
+
+        return (clk->parent->rate / clkr->div);
 }
 
-/* Given a clock and a rate apply a clock specific rounding function */
-static long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
+/**
+ * omap2_clksel_round_rate - find rounded rate for the given clock and rate
+ * @clk: OMAP struct clk to use
+ * @target_rate: desired clock rate
+ *
+ * Compatibility wrapper for OMAP clock framework
+ * Finds best target rate based on the source clock and possible dividers.
+ * rates. The divider array must be sorted with smallest divider first.
+ * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
+ * they are only settable as part of virtual_prcm set.
+ *
+ * Returns the rounded clock rate or returns 0xffffffff on error.
+ */
+long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
 {
-        u32 new_div = 0;
-        int valid_rate;
+        u32 new_div;
 
-        if (clk->flags & RATE_FIXED)
-                return clk->rate;
+        return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
+}
 
-        if (clk->flags & RATE_CKCTL) {
-                valid_rate = omap2_clksel_round_rate(clk, rate, &new_div);
-                return valid_rate;
-        }
 
+/* Given a clock and a rate apply a clock specific rounding function */
+long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
+{
         if (clk->round_rate != 0)
                 return clk->round_rate(clk, rate);
 
+        if (clk->flags & RATE_FIXED)
+                printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
+                       "on fixed-rate clock %s\n", clk->name);
+
         return clk->rate;
 }
 
-/*
- * Check the DLL lock state, and return tue if running in unlock mode.
- * This is needed to compensate for the shifted DLL value in unlock mode.
+/**
+ * omap2_clksel_to_divisor() - turn clksel field value into integer divider
+ * @clk: OMAP struct clk to use
+ * @field_val: register field value to find
+ *
+ * Given a struct clk of a rate-selectable clksel clock, and a register field
+ * value to search for, find the corresponding clock divisor.  The register
+ * field value should be pre-masked and shifted down so the LSB is at bit 0
+ * before calling.  Returns 0 on error
  */
-static u32 omap2_dll_force_needed(void)
+u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
 {
-        u32 dll_state = SDRC_DLLA_CTRL;         /* dlla and dllb are a set */
+        const struct clksel *clks;
+        const struct clksel_rate *clkr;
 
-        if ((dll_state & (1 << 2)) == (1 << 2))
-                return 1;
-        else
+        clks = omap2_get_clksel_by_parent(clk, clk->parent);
+        if (clks == NULL)
                 return 0;
-}
 
-static u32 omap2_reprogram_sdrc(u32 level, u32 force)
-{
-        u32 slow_dll_ctrl, fast_dll_ctrl, m_type;
-        u32 prev = curr_perf_level, flags;
-
-        if ((curr_perf_level == level) && !force)
-                return prev;
-
-        m_type = omap2_memory_get_type();
-        slow_dll_ctrl = omap2_memory_get_slow_dll_ctrl();
-        fast_dll_ctrl = omap2_memory_get_fast_dll_ctrl();
-
-        if (level == PRCM_HALF_SPEED) {
-                local_irq_save(flags);
-                PRCM_VOLTSETUP = 0xffff;
-                omap2_sram_reprogram_sdrc(PRCM_HALF_SPEED,
-                                          slow_dll_ctrl, m_type);
-                curr_perf_level = PRCM_HALF_SPEED;
-                local_irq_restore(flags);
+        for (clkr = clks->rates; clkr->div; clkr++) {
+                if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
+                        break;
         }
-        if (level == PRCM_FULL_SPEED) {
-                local_irq_save(flags);
-                PRCM_VOLTSETUP = 0xffff;
-                omap2_sram_reprogram_sdrc(PRCM_FULL_SPEED,
-                                          fast_dll_ctrl, m_type);
-                curr_perf_level = PRCM_FULL_SPEED;
-                local_irq_restore(flags);
+
+        if (!clkr->div) {
+                printk(KERN_ERR "clock: Could not find fieldval %d for "
+                       "clock %s parent %s\n", field_val, clk->name,
+                       clk->parent->name);
+                return 0;
         }
 
-        return prev;
+        return clkr->div;
 }
 
-static int omap2_reprogram_dpll(struct clk * clk, unsigned long rate)
+/**
+ * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
+ * @clk: OMAP struct clk to use
+ * @div: integer divisor to search for
+ *
+ * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
+ * find the corresponding register field value.  The return register value is
+ * the value before left-shifting.  Returns 0xffffffff on error
+ */
+u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
 {
-        u32 flags, cur_rate, low, mult, div, valid_rate, done_rate;
-        u32 bypass = 0;
-        struct prcm_config tmpset;
-        int ret = -EINVAL;
+        const struct clksel *clks;
+        const struct clksel_rate *clkr;
 
-        local_irq_save(flags);
-        cur_rate = omap2_get_dpll_rate(&dpll_ck);
-        mult = CM_CLKSEL2_PLL & 0x3;
-
-        if ((rate == (cur_rate / 2)) && (mult == 2)) {
-                omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1);
-        } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
-                omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
-        } else if (rate != cur_rate) {
-                valid_rate = omap2_dpll_round_rate(rate);
-                if (valid_rate != rate)
-                        goto dpll_exit;
-
-                if ((CM_CLKSEL2_PLL & 0x3) == 1)
-                        low = curr_prcm_set->dpll_speed;
-                else
-                        low = curr_prcm_set->dpll_speed / 2;
-
-                tmpset.cm_clksel1_pll = CM_CLKSEL1_PLL;
-                tmpset.cm_clksel1_pll &= ~(0x3FFF << 8);
-                div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
-                tmpset.cm_clksel2_pll = CM_CLKSEL2_PLL;
-                tmpset.cm_clksel2_pll &= ~0x3;
-                if (rate > low) {
-                        tmpset.cm_clksel2_pll |= 0x2;
-                        mult = ((rate / 2) / 1000000);
-                        done_rate = PRCM_FULL_SPEED;
-                } else {
-                        tmpset.cm_clksel2_pll |= 0x1;
-                        mult = (rate / 1000000);
-                        done_rate = PRCM_HALF_SPEED;
-                }
-                tmpset.cm_clksel1_pll |= ((div << 8) | (mult << 12));
-
-                /* Worst case */
-                tmpset.base_sdrc_rfr = V24XX_SDRC_RFR_CTRL_BYPASS;
-
-                if (rate == curr_prcm_set->xtal_speed)  /* If asking for 1-1 */
-                        bypass = 1;
+        /* should never happen */
+        WARN_ON(div == 0);
 
-                omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1); /* For init_mem */
-
-                /* Force dll lock mode */
-                omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
-                               bypass);
+        clks = omap2_get_clksel_by_parent(clk, clk->parent);
+        if (clks == NULL)
+                return 0;
 
-                /* Errata: ret dll entry state */
-                omap2_init_memory_params(omap2_dll_force_needed());
-                omap2_reprogram_sdrc(done_rate, 0);
+        for (clkr = clks->rates; clkr->div; clkr++) {
+                if ((clkr->flags & cpu_mask) && (clkr->div == div))
+                        break;
         }
-        omap2_clksel_recalc(&dpll_ck);
-        ret = 0;
 
-dpll_exit:
-        local_irq_restore(flags);
-        return(ret);
-}
+        if (!clkr->div) {
+                printk(KERN_ERR "clock: Could not find divisor %d for "
+                       "clock %s parent %s\n", div, clk->name,
+                       clk->parent->name);
+                return 0;
+        }
 
-/* Just return the MPU speed */
-static void omap2_mpu_recalc(struct clk * clk)
-{
-        clk->rate = curr_prcm_set->mpu_speed;
+        return clkr->val;
 }
 
-/*
- * Look for a rate equal or less than the target rate given a configuration set.
+/**
+ * omap2_get_clksel - find clksel register addr & field mask for a clk
+ * @clk: struct clk to use
+ * @field_mask: ptr to u32 to store the register field mask
  *
- * What's not entirely clear is "which" field represents the key field.
- * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
- * just uses the ARM rates.
+ * Returns the address of the clksel register upon success or NULL on error.
  */
-static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate)
+void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
 {
-        struct prcm_config * ptr;
-        long highest_rate;
-
-        if (clk != &virt_prcm_set)
-                return -EINVAL;
-
-        highest_rate = -EINVAL;
-
-        for (ptr = rate_table; ptr->mpu_speed; ptr++) {
-                if (ptr->xtal_speed != sys_ck.rate)
-                        continue;
+        if (unlikely((clk->clksel_reg == 0) || (clk->clksel_mask == 0)))
+                return NULL;
 
-                highest_rate = ptr->mpu_speed;
+        *field_mask = clk->clksel_mask;
 
-                /* Can check only after xtal frequency check */
-                if (ptr->mpu_speed <= rate)
-                        break;
-        }
-        return highest_rate;
+        return clk->clksel_reg;
 }
 
-/*
- * omap2_convert_field_to_div() - turn field value into integer divider
+/**
+ * omap2_clksel_get_divisor - get current divider applied to parent clock.
+ * @clk: OMAP struct clk to use.
+ *
+ * Returns the integer divisor upon success or 0 on error.
  */
-static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val)
+u32 omap2_clksel_get_divisor(struct clk *clk)
 {
-        u32 i;
-        u32 clkout_array[] = {1, 2, 4, 8, 16};
+        u32 field_mask, field_val;
+        void __iomem *div_addr;
 
-        if ((div_sel & SRC_RATE_SEL_MASK) == CM_SYSCLKOUT_SEL1) {
-                for (i = 0; i < 5; i++) {
-                        if (field_val == i)
-                                return clkout_array[i];
-                }
-                return ~0;
-        } else
-                return field_val;
+        div_addr = omap2_get_clksel(clk, &field_mask);
+        if (div_addr == 0)
+                return 0;
+
+        field_val = __raw_readl(div_addr) & field_mask;
+        field_val >>= __ffs(field_mask);
+
+        return omap2_clksel_to_divisor(clk, field_val);
 }
 
-/*
- * Returns the CLKSEL divider register value
- * REVISIT: This should be cleaned up to work nicely with void __iomem *
- */
-static u32 omap2_get_clksel(u32 *div_sel, u32 *field_mask,
-                            struct clk *clk)
+int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
 {
-        int ret = ~0;
-        u32 reg_val, div_off;
-        u32 div_addr = 0;
-        u32 mask = ~0;
-
-        div_off = clk->rate_offset;
-
-        switch ((*div_sel & SRC_RATE_SEL_MASK)) {
-        case CM_MPU_SEL1:
-                div_addr = (u32)&CM_CLKSEL_MPU;
-                mask = 0x1f;
-                break;
-        case CM_DSP_SEL1:
-                div_addr = (u32)&CM_CLKSEL_DSP;
-                if (cpu_is_omap2420()) {
-                        if ((div_off == 0) || (div_off == 8))
-                                mask = 0x1f;
-                        else if (div_off == 5)
-                                mask = 0x3;
-                } else if (cpu_is_omap2430()) {
-                        if (div_off == 0)
-                                mask = 0x1f;
-                        else if (div_off == 5)
-                                mask = 0x3;
-                }
-                break;
-        case CM_GFX_SEL1:
-                div_addr = (u32)&CM_CLKSEL_GFX;
-                if (div_off == 0)
-                        mask = 0x7;
-                break;
-        case CM_MODEM_SEL1:
-                div_addr = (u32)&CM_CLKSEL_MDM;
-                if (div_off == 0)
-                        mask = 0xf;
-                break;
-        case CM_SYSCLKOUT_SEL1:
-                div_addr = (u32)&PRCM_CLKOUT_CTRL;
-                if ((div_off == 3) || (div_off == 11))
-                        mask= 0x3;
-                break;
-        case CM_CORE_SEL1:
-                div_addr = (u32)&CM_CLKSEL1_CORE;
-                switch (div_off) {
-                case 0:                                 /* l3 */
-                case 8:                                 /* dss1 */
-                case 15:                                /* vylnc-2420 */
-                case 20:                                /* ssi */
-                        mask = 0x1f; break;
-                case 5:                                 /* l4 */
-                        mask = 0x3; break;
-                case 13:                                /* dss2 */
-                        mask = 0x1; break;
-                case 25:                                /* usb */
-                        mask = 0x7; break;
-                }
-        }
+        u32 field_mask, field_val, reg_val, validrate, new_div = 0;
+        void __iomem *div_addr;
 
-        *field_mask = mask;
+        validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
+        if (validrate != rate)
+                return -EINVAL;
 
-        if (unlikely(mask == ~0))
-                div_addr = 0;
+        div_addr = omap2_get_clksel(clk, &field_mask);
+        if (div_addr == 0)
+                return -EINVAL;
 
-        *div_sel = div_addr;
+        field_val = omap2_divisor_to_clksel(clk, new_div);
+        if (field_val == ~0)
+                return -EINVAL;
 
-        if (unlikely(div_addr == 0))
-                return ret;
+        reg_val = __raw_readl(div_addr);
+        reg_val &= ~field_mask;
+        reg_val |= (field_val << __ffs(field_mask));
+        __raw_writel(reg_val, div_addr);
+        wmb();
 
-        /* Isolate field */
-        reg_val = __raw_readl((void __iomem *)div_addr) & (mask << div_off);
+        clk->rate = clk->parent->rate / new_div;
 
-        /* Normalize back to divider value */
-        reg_val >>= div_off;
+        if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
+                __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL);
+                wmb();
+        }
 
-        return reg_val;
+        return 0;
 }
 
-/*
- * Return divider to be applied to parent clock.
- * Return 0 on error.
- */
-static u32 omap2_clksel_get_divisor(struct clk *clk)
-{
-        int ret = 0;
-        u32 div, div_sel, div_off, field_mask, field_val;
-
-        /* isolate control register */
-        div_sel = (SRC_RATE_SEL_MASK & clk->flags);
-
-        div_off = clk->rate_offset;
-        field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
-        if (div_sel == 0)
-                return ret;
-
-        div_sel = (SRC_RATE_SEL_MASK & clk->flags);
-        div = omap2_clksel_to_divisor(div_sel, field_val);
-
-        return div;
-}
 
 /* Set the clock rate for a clock source */
-static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
-
+int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
 {
         int ret = -EINVAL;
-        void __iomem * reg;
-        u32 div_sel, div_off, field_mask, field_val, reg_val, validrate;
-        u32 new_div = 0;
-
-        if (!(clk->flags & CONFIG_PARTICIPANT) && (clk->flags & RATE_CKCTL)) {
-                if (clk == &dpll_ck)
-                        return omap2_reprogram_dpll(clk, rate);
-
-                /* Isolate control register */
-                div_sel = (SRC_RATE_SEL_MASK & clk->flags);
-                div_off = clk->rate_offset;
-
-                validrate = omap2_clksel_round_rate(clk, rate, &new_div);
-                if (validrate != rate)
-                        return(ret);
 
-                field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
-                if (div_sel == 0)
-                        return ret;
-
-                if (clk->flags & CM_SYSCLKOUT_SEL1) {
-                        switch (new_div) {
-                        case 16:
-                                field_val = 4;
-                                break;
-                        case 8:
-                                field_val = 3;
-                                break;
-                        case 4:
-                                field_val = 2;
-                                break;
-                        case 2:
-                                field_val = 1;
-                                break;
-                        case 1:
-                                field_val = 0;
-                                break;
-                        }
-                } else
-                        field_val = new_div;
+        pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
 
-                reg = (void __iomem *)div_sel;
-
-                reg_val = __raw_readl(reg);
-                reg_val &= ~(field_mask << div_off);
-                reg_val |= (field_val << div_off);
-                __raw_writel(reg_val, reg);
-                wmb();
-                clk->rate = clk->parent->rate / field_val;
+        /* CONFIG_PARTICIPANT clocks are changed only in sets via the
+           rate table mechanism, driven by mpu_speed  */
+        if (clk->flags & CONFIG_PARTICIPANT)
+                return -EINVAL;
 
-                if (clk->flags & DELAYED_APP) {
-                        __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL);
-                        wmb();
-                }
-                ret = 0;
-        } else if (clk->set_rate != 0)
+        /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
+        if (clk->set_rate != 0)
                 ret = clk->set_rate(clk, rate);
 
         if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
@@ -782,242 +631,92 @@ static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
         return ret;
 }
 
-/* Converts encoded control register address into a full address */
-static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset,
-                               struct clk *src_clk, u32 *field_mask)
-{
-        u32 val = ~0, src_reg_addr = 0, mask = 0;
-
-        /* Find target control register.*/
-        switch ((*type_to_addr & SRC_RATE_SEL_MASK)) {
-        case CM_CORE_SEL1:
-                src_reg_addr = (u32)&CM_CLKSEL1_CORE;
-                if (reg_offset == 13) {                 /* DSS2_fclk */
-                        mask = 0x1;
-                        if (src_clk == &sys_ck)
-                                val = 0;
-                        if (src_clk == &func_48m_ck)
-                                val = 1;
-                } else if (reg_offset == 8) {           /* DSS1_fclk */
-                        mask = 0x1f;
-                        if (src_clk == &sys_ck)
-                                val = 0;
-                        else if (src_clk == &core_ck)   /* divided clock */
-                                val = 0x10;             /* rate needs fixing */
-                } else if ((reg_offset == 15) && cpu_is_omap2420()){ /*vlnyq*/
-                        mask = 0x1F;
-                        if(src_clk == &func_96m_ck)
-                                val = 0;
-                        else if (src_clk == &core_ck)
-                                val = 0x10;
-                }
-                break;
-        case CM_CORE_SEL2:
-                src_reg_addr = (u32)&CM_CLKSEL2_CORE;
-                mask = 0x3;
-                if (src_clk == &func_32k_ck)
-                        val = 0x0;
-                if (src_clk == &sys_ck)
-                        val = 0x1;
-                if (src_clk == &alt_ck)
-                        val = 0x2;
-                break;
-        case CM_WKUP_SEL1:
-                src_reg_addr = (u32)&CM_CLKSEL_WKUP;
-                mask = 0x3;
-                if (src_clk == &func_32k_ck)
-                        val = 0x0;
-                if (src_clk == &sys_ck)
-                        val = 0x1;
-                if (src_clk == &alt_ck)
-                        val = 0x2;
-                break;
-        case CM_PLL_SEL1:
-                src_reg_addr = (u32)&CM_CLKSEL1_PLL;
-                mask = 0x1;
-                if (reg_offset == 0x3) {
-                        if (src_clk == &apll96_ck)
-                                val = 0;
-                        if (src_clk == &alt_ck)
-                                val = 1;
-                }
-                else if (reg_offset == 0x5) {
-                        if (src_clk == &apll54_ck)
-                                val = 0;
-                        if (src_clk == &alt_ck)
-                                val = 1;
-                }
-                break;
-        case CM_PLL_SEL2:
-                src_reg_addr = (u32)&CM_CLKSEL2_PLL;
-                mask = 0x3;
-                if (src_clk == &func_32k_ck)
-                        val = 0x0;
-                if (src_clk == &dpll_ck)
-                        val = 0x2;
-                break;
-        case CM_SYSCLKOUT_SEL1:
-                src_reg_addr = (u32)&PRCM_CLKOUT_CTRL;
-                mask = 0x3;
-                if (src_clk == &dpll_ck)
-                        val = 0;
-                if (src_clk == &sys_ck)
-                        val = 1;
-                if (src_clk == &func_96m_ck)
-                        val = 2;
-                if (src_clk == &func_54m_ck)
-                        val = 3;
-                break;
-        }
-
-        if (val == ~0)                  /* Catch errors in offset */
-                *type_to_addr = 0;
-        else
-                *type_to_addr = src_reg_addr;
-        *field_mask = mask;
-
-        return val;
-}
-
-static int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
+/*
+ * Converts encoded control register address into a full address
+ * On error, *src_addr will be returned as 0.
+ */
+static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
+                                      struct clk *src_clk, u32 *field_mask,
+                                      struct clk *clk, u32 *parent_div)
 {
-        void __iomem * reg;
-        u32 src_sel, src_off, field_val, field_mask, reg_val, rate;
-        int ret = -EINVAL;
-
-        if (unlikely(clk->flags & CONFIG_PARTICIPANT))
-                return ret;
-
-        if (clk->flags & SRC_SEL_MASK) {        /* On-chip SEL collection */
-                src_sel = (SRC_RATE_SEL_MASK & clk->flags);
-                src_off = clk->src_offset;
-
-                if (src_sel == 0)
-                        goto set_parent_error;
-
-                field_val = omap2_get_src_field(&src_sel, src_off, new_parent,
-                                                &field_mask);
-
-                reg = (void __iomem *)src_sel;
-
-                if (clk->usecount > 0)
-                        _omap2_clk_disable(clk);
-
-                /* Set new source value (previous dividers if any in effect) */
-                reg_val = __raw_readl(reg) & ~(field_mask << src_off);
-                reg_val |= (field_val << src_off);
-                __raw_writel(reg_val, reg);
-                wmb();
+        const struct clksel *clks;
+        const struct clksel_rate *clkr;
 
-                if (clk->flags & DELAYED_APP) {
-                        __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL);
-                        wmb();
-                }
-                if (clk->usecount > 0)
-                        _omap2_clk_enable(clk);
-
-                clk->parent = new_parent;
+        *parent_div = 0;
+        *src_addr = 0;
 
-                /* SRC_RATE_SEL_MASK clocks follow their parents rates.*/
-                if ((new_parent == &core_ck) && (clk == &dss1_fck))
-                        clk->rate = new_parent->rate / 0x10;
-                else
-                        clk->rate = new_parent->rate;
+        clks = omap2_get_clksel_by_parent(clk, src_clk);
+        if (clks == NULL)
+                return 0;
 
-                if (unlikely(clk->flags & RATE_PROPAGATES))
-                        propagate_rate(clk);
+        for (clkr = clks->rates; clkr->div; clkr++) {
+                if (clkr->flags & (cpu_mask | DEFAULT_RATE))
+                        break; /* Found the default rate for this platform */
+        }
 
+        if (!clkr->div) {
+                printk(KERN_ERR "clock: Could not find default rate for "
+                       "clock %s parent %s\n", clk->name,
+                       src_clk->parent->name);
                 return 0;
-        } else {
-                clk->parent = new_parent;
-                rate = new_parent->rate;
-                omap2_clk_set_rate(clk, rate);
-                ret = 0;
         }
 
- set_parent_error:
-        return ret;
+        /* Should never happen.  Add a clksel mask to the struct clk. */
+        WARN_ON(clk->clksel_mask == 0);
+
+        *field_mask = clk->clksel_mask;
+        *src_addr = clk->clksel_reg;
+        *parent_div = clkr->div;
+
+        return clkr->val;
 }
 
-/* Sets basic clocks based on the specified rate */
-static int omap2_select_table_rate(struct clk * clk, unsigned long rate)
+int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
 {
-        u32 flags, cur_rate, done_rate, bypass = 0;
-        u8 cpu_mask = 0;
-        struct prcm_config *prcm;
-        unsigned long found_speed = 0;
+        void __iomem *src_addr;
+        u32 field_val, field_mask, reg_val, parent_div;
 
-        if (clk != &virt_prcm_set)
+        if (unlikely(clk->flags & CONFIG_PARTICIPANT))
                 return -EINVAL;
 
-        /* FIXME: Change cpu_is_omap2420() to cpu_is_omap242x() */
-        if (cpu_is_omap2420())
-                cpu_mask = RATE_IN_242X;
-        else if (cpu_is_omap2430())
-                cpu_mask = RATE_IN_243X;
-
-        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
-                if (!(prcm->flags & cpu_mask))
-                        continue;
-
-                if (prcm->xtal_speed != sys_ck.rate)
-                        continue;
-
-                if (prcm->mpu_speed <= rate) {
-                        found_speed = prcm->mpu_speed;
-                        break;
-                }
-        }
-
-        if (!found_speed) {
-                printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
-         rate / 1000000);
+        if (!clk->clksel)
                 return -EINVAL;
-        }
-
-        curr_prcm_set = prcm;
-        cur_rate = omap2_get_dpll_rate(&dpll_ck);
-
-        if (prcm->dpll_speed == cur_rate / 2) {
-                omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1);
-        } else if (prcm->dpll_speed == cur_rate * 2) {
-                omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
-        } else if (prcm->dpll_speed != cur_rate) {
-                local_irq_save(flags);
 
-                if (prcm->dpll_speed == prcm->xtal_speed)
-                        bypass = 1;
+        field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
+                                               &field_mask, clk, &parent_div);
+        if (src_addr == 0)
+                return -EINVAL;
 
-                if ((prcm->cm_clksel2_pll & 0x3) == 2)
-                        done_rate = PRCM_FULL_SPEED;
-                else
-                        done_rate = PRCM_HALF_SPEED;
+        if (clk->usecount > 0)
+                _omap2_clk_disable(clk);
 
-                /* MPU divider */
-                CM_CLKSEL_MPU = prcm->cm_clksel_mpu;
+        /* Set new source value (previous dividers if any in effect) */
+        reg_val = __raw_readl(src_addr) & ~field_mask;
+        reg_val |= (field_val << __ffs(field_mask));
+        __raw_writel(reg_val, src_addr);
+        wmb();
 
-                /* dsp + iva1 div(2420), iva2.1(2430) */
-                CM_CLKSEL_DSP = prcm->cm_clksel_dsp;
+        if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
+                __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL);
+                wmb();
+        }
 
-                CM_CLKSEL_GFX = prcm->cm_clksel_gfx;
+        if (clk->usecount > 0)
+                _omap2_clk_enable(clk);
 
-                /* Major subsystem dividers */
-                CM_CLKSEL1_CORE = prcm->cm_clksel1_core;
-                if (cpu_is_omap2430())
-                        CM_CLKSEL_MDM = prcm->cm_clksel_mdm;
+        clk->parent = new_parent;
 
-                /* x2 to enter init_mem */
-                omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
+        /* CLKSEL clocks follow their parents' rates, divided by a divisor */
+        clk->rate = new_parent->rate;
 
-                omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
-                               bypass);
+        if (parent_div > 0)
+                clk->rate /= parent_div;
 
-                omap2_init_memory_params(omap2_dll_force_needed());
-                omap2_reprogram_sdrc(done_rate, 0);
+        pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
+                 clk->name, clk->parent->name, clk->rate);
 
-                local_irq_restore(flags);
-        }
-        omap2_clksel_recalc(&dpll_ck);
+        if (unlikely(clk->flags & RATE_PROPAGATES))
+                propagate_rate(clk);
 
         return 0;
 }
@@ -1027,150 +726,17 @@ static int omap2_select_table_rate(struct clk * clk, unsigned long rate)
  *-------------------------------------------------------------------------*/
 
 #ifdef CONFIG_OMAP_RESET_CLOCKS
-static void __init omap2_clk_disable_unused(struct clk *clk)
+void omap2_clk_disable_unused(struct clk *clk)
 {
-        u32 regval32;
+        u32 regval32, v;
+
+        v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
 
         regval32 = __raw_readl(clk->enable_reg);
-        if ((regval32 & (1 << clk->enable_bit)) == 0)
+        if ((regval32 & (1 << clk->enable_bit)) == v)
                 return;
 
         printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
         _omap2_clk_disable(clk);
 }
-#else
-#define omap2_clk_disable_unused        NULL
 #endif
-
-static struct clk_functions omap2_clk_functions = {
-        .clk_enable             = omap2_clk_enable,
-        .clk_disable            = omap2_clk_disable,
-        .clk_round_rate         = omap2_clk_round_rate,
-        .clk_set_rate           = omap2_clk_set_rate,
-        .clk_set_parent         = omap2_clk_set_parent,
-        .clk_disable_unused     = omap2_clk_disable_unused,
-};
-
-static void __init omap2_get_crystal_rate(struct clk *osc, struct clk *sys)
-{
-        u32 div, aplls, sclk = 13000000;
-
-        aplls = CM_CLKSEL1_PLL;
-        aplls &= ((1 << 23) | (1 << 24) | (1 << 25));
-        aplls >>= 23;                   /* Isolate field, 0,2,3 */
-
-        if (aplls == 0)
-                sclk = 19200000;
-        else if (aplls == 2)
-                sclk = 13000000;
-        else if (aplls == 3)
-                sclk = 12000000;
-
-        div = PRCM_CLKSRC_CTRL;
-        div &= ((1 << 7) | (1 << 6));
-        div >>= sys->rate_offset;
-
-        osc->rate = sclk * div;
-        sys->rate = sclk;
-}
-
-/*
- * Set clocks for bypass mode for reboot to work.
- */
-void omap2_clk_prepare_for_reboot(void)
-{
-        u32 rate;
-
-        if (vclk == NULL || sclk == NULL)
-                return;
-
-        rate = clk_get_rate(sclk);
-        clk_set_rate(vclk, rate);
-}
-
-/*
- * Switch the MPU rate if specified on cmdline.
- * We cannot do this early until cmdline is parsed.
- */
-static int __init omap2_clk_arch_init(void)
-{
-        if (!mpurate)
-                return -EINVAL;
-
-        if (omap2_select_table_rate(&virt_prcm_set, mpurate))
-                printk(KERN_ERR "Could not find matching MPU rate\n");
-
-        propagate_rate(&osc_ck);                /* update main root fast */
-        propagate_rate(&func_32k_ck);           /* update main root slow */
-
-        printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
-               "%ld.%01ld/%ld/%ld MHz\n",
-               (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
-               (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
-
-        return 0;
-}
-arch_initcall(omap2_clk_arch_init);
-
-int __init omap2_clk_init(void)
-{
-        struct prcm_config *prcm;
-        struct clk ** clkp;
-        u32 clkrate;
-
-        clk_init(&omap2_clk_functions);
-        omap2_get_crystal_rate(&osc_ck, &sys_ck);
-
-        for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
-             clkp++) {
-
-                if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
-                        clk_register(*clkp);
-                        continue;
-                }
-
-                if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) {
-                        clk_register(*clkp);
-                        continue;
-                }
-        }
-
-        /* Check the MPU rate set by bootloader */
-        clkrate = omap2_get_dpll_rate(&dpll_ck);
-        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
-                if (prcm->xtal_speed != sys_ck.rate)
-                        continue;
-                if (prcm->dpll_speed <= clkrate)
-                         break;
-        }
-        curr_prcm_set = prcm;
-
-        propagate_rate(&osc_ck);                /* update main root fast */
-        propagate_rate(&func_32k_ck);           /* update main root slow */
-
-        printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
-               "%ld.%01ld/%ld/%ld MHz\n",
-               (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
-               (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
-
-        /*
-         * Only enable those clocks we will need, let the drivers
-         * enable other clocks as necessary
-         */
-        clk_enable(&sync_32k_ick);
-        clk_enable(&omapctrl_ick);
-
-        /* Force the APLLs always active. The clocks are idled
-         * automatically by hardware. */
-        clk_enable(&apll96_ck);
-        clk_enable(&apll54_ck);
-
-        if (cpu_is_omap2430())
-                clk_enable(&sdrc_ick);
-
-        /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
-        vclk = clk_get(NULL, "virt_prcm_set");
-        sclk = clk_get(NULL, "sys_ck");
-
-        return 0;
-}
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 4f791866b910..d5980a9e09a4 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -1,13 +1,12 @@
 /*
- *  linux/arch/arm/mach-omap24xx/clock.h
+ *  linux/arch/arm/mach-omap2/clock.h
  *
- *  Copyright (C) 2005 Texas Instruments Inc.
- *  Richard Woodruff <r-woodruff2@ti.com>
- *  Created for OMAP2.
+ *  Copyright (C) 2005-2008 Texas Instruments, Inc.
+ *  Copyright (C) 2004-2008 Nokia Corporation
  *
- *  Copyright (C) 2004 Nokia corporation
- *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
- *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
+ *  Contacts:
+ *  Richard Woodruff <r-woodruff2@ti.com>
+ *  Paul Walmsley
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -17,2095 +16,53 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
 
-static void omap2_sys_clk_recalc(struct clk * clk);
-static void omap2_clksel_recalc(struct clk * clk);
-static void omap2_followparent_recalc(struct clk * clk);
-static void omap2_propagate_rate(struct clk * clk);
-static void omap2_mpu_recalc(struct clk * clk);
-static int omap2_select_table_rate(struct clk * clk, unsigned long rate);
-static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate);
-static void omap2_clk_disable(struct clk *clk);
-static void omap2_sys_clk_recalc(struct clk * clk);
-static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val);
-static u32 omap2_clksel_get_divisor(struct clk *clk);
-
-
-#define RATE_IN_242X    (1 << 0)
-#define RATE_IN_243X    (1 << 1)
-
-/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
- * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
- * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
- */
-struct prcm_config {
-        unsigned long xtal_speed;       /* crystal rate */
-        unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
-        unsigned long mpu_speed;        /* speed of MPU */
-        unsigned long cm_clksel_mpu;    /* mpu divider */
-        unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
-        unsigned long cm_clksel_gfx;    /* gfx dividers */
-        unsigned long cm_clksel1_core;  /* major subsystem dividers */
-        unsigned long cm_clksel1_pll;   /* m,n */
-        unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
-        unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
-        unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
-        unsigned char flags;
-};
-
-/* Mask for clksel which support parent settign in set_rate */
-#define SRC_SEL_MASK (CM_CORE_SEL1 | CM_CORE_SEL2 | CM_WKUP_SEL1 | \
-                        CM_PLL_SEL1 | CM_PLL_SEL2 | CM_SYSCLKOUT_SEL1)
-
-/* Mask for clksel regs which support rate operations */
-#define SRC_RATE_SEL_MASK (CM_MPU_SEL1 | CM_DSP_SEL1 | CM_GFX_SEL1 | \
-                        CM_MODEM_SEL1 | CM_CORE_SEL1 | CM_CORE_SEL2 | \
-                        CM_WKUP_SEL1 | CM_PLL_SEL1 | CM_PLL_SEL2 | \
-                        CM_SYSCLKOUT_SEL1)
-
-/*
- * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
- * These configurations are characterized by voltage and speed for clocks.
- * The device is only validated for certain combinations. One way to express
- * these combinations is via the 'ratio's' which the clocks operate with
- * respect to each other. These ratio sets are for a given voltage/DPLL
- * setting. All configurations can be described by a DPLL setting and a ratio
- * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
- *
- * 2430 differs from 2420 in that there are no more phase synchronizers used.
- * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
- * 2430 (iva2.1, NOdsp, mdm)
- */
-
-/* Core fields for cm_clksel, not ratio governed */
-#define RX_CLKSEL_DSS1                  (0x10 << 8)
-#define RX_CLKSEL_DSS2                  (0x0 << 13)
-#define RX_CLKSEL_SSI                   (0x5 << 20)
-
-/*-------------------------------------------------------------------------
- * Voltage/DPLL ratios
- *-------------------------------------------------------------------------*/
-
-/* 2430 Ratio's, 2430-Ratio Config 1 */
-#define R1_CLKSEL_L3                    (4 << 0)
-#define R1_CLKSEL_L4                    (2 << 5)
-#define R1_CLKSEL_USB                   (4 << 25)
-#define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
-                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
-                                        R1_CLKSEL_L4 | R1_CLKSEL_L3
-#define R1_CLKSEL_MPU                   (2 << 0)
-#define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
-#define R1_CLKSEL_DSP                   (2 << 0)
-#define R1_CLKSEL_DSP_IF                (2 << 5)
-#define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
-#define R1_CLKSEL_GFX                   (2 << 0)
-#define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
-#define R1_CLKSEL_MDM                   (4 << 0)
-#define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
-
-/* 2430-Ratio Config 2 */
-#define R2_CLKSEL_L3                    (6 << 0)
-#define R2_CLKSEL_L4                    (2 << 5)
-#define R2_CLKSEL_USB                   (2 << 25)
-#define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
-                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
-                                        R2_CLKSEL_L4 | R2_CLKSEL_L3
-#define R2_CLKSEL_MPU                   (2 << 0)
-#define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
-#define R2_CLKSEL_DSP                   (2 << 0)
-#define R2_CLKSEL_DSP_IF                (3 << 5)
-#define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
-#define R2_CLKSEL_GFX                   (2 << 0)
-#define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
-#define R2_CLKSEL_MDM                   (6 << 0)
-#define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
-
-/* 2430-Ratio Bootm (BYPASS) */
-#define RB_CLKSEL_L3                    (1 << 0)
-#define RB_CLKSEL_L4                    (1 << 5)
-#define RB_CLKSEL_USB                   (1 << 25)
-#define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
-                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
-                                        RB_CLKSEL_L4 | RB_CLKSEL_L3
-#define RB_CLKSEL_MPU                   (1 << 0)
-#define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
-#define RB_CLKSEL_DSP                   (1 << 0)
-#define RB_CLKSEL_DSP_IF                (1 << 5)
-#define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
-#define RB_CLKSEL_GFX                   (1 << 0)
-#define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
-#define RB_CLKSEL_MDM                   (1 << 0)
-#define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
-
-/* 2420 Ratio Equivalents */
-#define RXX_CLKSEL_VLYNQ                (0x12 << 15)
-#define RXX_CLKSEL_SSI                  (0x8 << 20)
-
-/* 2420-PRCM III 532MHz core */
-#define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
-#define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
-#define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
-#define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
-                                        RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
-                                        RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
-                                        RIII_CLKSEL_L3
-#define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
-#define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
-#define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
-#define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
-#define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
-#define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
-#define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
-#define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
-                                        RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
-                                        RIII_CLKSEL_DSP
-#define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
-#define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
-
-/* 2420-PRCM II 600MHz core */
-#define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
-#define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
-#define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
-#define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
-                                        RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
-                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
-                                        RII_CLKSEL_L4 | RII_CLKSEL_L3
-#define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
-#define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
-#define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
-#define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
-#define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
-#define RII_CLKSEL_IVA                  (6 << 8)        /* iva1 - 200MHz */
-#define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
-#define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
-                                        RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
-                                        RII_CLKSEL_DSP
-#define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
-#define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
-
-/* 2420-PRCM VII (boot) */
-#define RVII_CLKSEL_L3                  (1 << 0)
-#define RVII_CLKSEL_L4                  (1 << 5)
-#define RVII_CLKSEL_DSS1                (1 << 8)
-#define RVII_CLKSEL_DSS2                (0 << 13)
-#define RVII_CLKSEL_VLYNQ               (1 << 15)
-#define RVII_CLKSEL_SSI                 (1 << 20)
-#define RVII_CLKSEL_USB                 (1 << 25)
-
-#define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
-                                        RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
-                                        RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
-
-#define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
-#define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
+#include <asm/arch/clock.h>
 
-#define RVII_CLKSEL_DSP                 (1 << 0)
-#define RVII_CLKSEL_DSP_IF              (1 << 5)
-#define RVII_SYNC_DSP                   (0 << 7)
-#define RVII_CLKSEL_IVA                 (1 << 8)
-#define RVII_SYNC_IVA                   (0 << 13)
-#define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
-                                        RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
-
-#define RVII_CLKSEL_GFX                 (1 << 0)
-#define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
-
-/*-------------------------------------------------------------------------
- * 2430 Target modes: Along with each configuration the CPU has several
- * modes which goes along with them. Modes mainly are the addition of
- * describe DPLL combinations to go along with a ratio.
- *-------------------------------------------------------------------------*/
-
-/* Hardware governed */
-#define MX_48M_SRC                      (0 << 3)
-#define MX_54M_SRC                      (0 << 5)
-#define MX_APLLS_CLIKIN_12              (3 << 23)
-#define MX_APLLS_CLIKIN_13              (2 << 23)
-#define MX_APLLS_CLIKIN_19_2            (0 << 23)
-
-/*
- * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
- * #2   (ratio1) baseport-target
- * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
- */
-#define M5A_DPLL_MULT_12                (133 << 12)
-#define M5A_DPLL_DIV_12                 (5 << 8)
-#define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
-                                        MX_APLLS_CLIKIN_12
-#define M5A_DPLL_MULT_13                (266 << 12)
-#define M5A_DPLL_DIV_13                 (12 << 8)
-#define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
-                                        MX_APLLS_CLIKIN_13
-#define M5A_DPLL_MULT_19                (180 << 12)
-#define M5A_DPLL_DIV_19                 (12 << 8)
-#define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
-                                        MX_APLLS_CLIKIN_19_2
-/* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
-#define M5B_DPLL_MULT_12                (50 << 12)
-#define M5B_DPLL_DIV_12                 (2 << 8)
-#define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
-                                        MX_APLLS_CLIKIN_12
-#define M5B_DPLL_MULT_13                (200 << 12)
-#define M5B_DPLL_DIV_13                 (12 << 8)
-
-#define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
-                                        MX_APLLS_CLIKIN_13
-#define M5B_DPLL_MULT_19                (125 << 12)
-#define M5B_DPLL_DIV_19                 (31 << 8)
-#define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
-                                        MX_APLLS_CLIKIN_19_2
-/*
- * #4   (ratio2)
- * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
- */
-#define M3_DPLL_MULT_12                 (55 << 12)
-#define M3_DPLL_DIV_12                  (1 << 8)
-#define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
-                                        M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
-                                        MX_APLLS_CLIKIN_12
-#define M3_DPLL_MULT_13                 (330 << 12)
-#define M3_DPLL_DIV_13                  (12 << 8)
-#define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
-                                        M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
-                                        MX_APLLS_CLIKIN_13
-#define M3_DPLL_MULT_19                 (275 << 12)
-#define M3_DPLL_DIV_19                  (15 << 8)
-#define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
-                                        M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
-                                        MX_APLLS_CLIKIN_19_2
-/* boot (boot) */
-#define MB_DPLL_MULT                    (1 << 12)
-#define MB_DPLL_DIV                     (0 << 8)
-#define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
-                                        MB_DPLL_MULT | MX_APLLS_CLIKIN_12
-
-#define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
-                                        MB_DPLL_MULT | MX_APLLS_CLIKIN_13
-
-#define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
-                                        MB_DPLL_MULT | MX_APLLS_CLIKIN_19
-
-/*
- * 2430 - chassis (sedna)
- * 165 (ratio1) same as above #2
- * 150 (ratio1)
- * 133 (ratio2) same as above #4
- * 110 (ratio2) same as above #3
- * 104 (ratio2)
- * boot (boot)
- */
-
-/*
- * 2420 Equivalent - mode registers
- * PRCM II , target DPLL = 2*300MHz = 600MHz
- */
-#define MII_DPLL_MULT_12                (50 << 12)
-#define MII_DPLL_DIV_12                 (1 << 8)
-#define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
-                                        MX_APLLS_CLIKIN_12
-#define MII_DPLL_MULT_13                (300 << 12)
-#define MII_DPLL_DIV_13                 (12 << 8)
-#define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
-                                        MX_APLLS_CLIKIN_13
-
-/* PRCM III target DPLL = 2*266 = 532MHz*/
-#define MIII_DPLL_MULT_12               (133 << 12)
-#define MIII_DPLL_DIV_12                (5 << 8)
-#define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
-                                        MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
-                                        MX_APLLS_CLIKIN_12
-#define MIII_DPLL_MULT_13               (266 << 12)
-#define MIII_DPLL_DIV_13                (12 << 8)
-#define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
-                                        MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
-                                        MX_APLLS_CLIKIN_13
-
-/* PRCM VII (boot bypass) */
-#define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
-#define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
-
-/* High and low operation value */
-#define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
-#define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
-
-/*
- * These represent optimal values for common parts, it won't work for all.
- * As long as you scale down, most parameters are still work, they just
- * become sub-optimal. The RFR value goes in the opposite direction. If you
- * don't adjust it down as your clock period increases the refresh interval
- * will not be met. Setting all parameters for complete worst case may work,
- * but may cut memory performance by 2x. Due to errata the DLLs need to be
- * unlocked and their value needs run time calibration. A dynamic call is
- * need for that as no single right value exists acorss production samples.
- *
- * Only the FULL speed values are given. Current code is such that rate
- * changes must be made at DPLLoutx2. The actual value adjustment for low
- * frequency operation will be handled by omap_set_performance()
- *
- * By having the boot loader boot up in the fastest L4 speed available likely
- * will result in something which you can switch between.
- */
-#define V24XX_SDRC_RFR_CTRL_133MHz      (0x0003de00 | 1)
-#define V24XX_SDRC_RFR_CTRL_100MHz      (0x0002da01 | 1)
-#define V24XX_SDRC_RFR_CTRL_110MHz      (0x0002da01 | 1) /* Need to calc */
-#define V24XX_SDRC_RFR_CTRL_BYPASS      (0x00005000 | 1) /* Need to calc */
-
-/* MPU speed defines */
-#define S12M    12000000
-#define S13M    13000000
-#define S19M    19200000
-#define S26M    26000000
-#define S100M   100000000
-#define S133M   133000000
-#define S150M   150000000
-#define S165M   165000000
-#define S200M   200000000
-#define S266M   266000000
-#define S300M   300000000
-#define S330M   330000000
-#define S400M   400000000
-#define S532M   532000000
-#define S600M   600000000
-#define S660M   660000000
-
-/*-------------------------------------------------------------------------
- * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
- * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
- * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
- * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
- *
- * Filling in table based on H4 boards and 2430-SDPs variants available.
- * There are quite a few more rates combinations which could be defined.
- *
- * When multiple values are defined the start up will try and choose the
- * fastest one. If a 'fast' value is defined, then automatically, the /2
- * one should be included as it can be used.    Generally having more that
- * one fast set does not make sense, as static timings need to be changed
- * to change the set.    The exception is the bypass setting which is
- * availble for low power bypass.
- *
- * Note: This table needs to be sorted, fastest to slowest.
- *-------------------------------------------------------------------------*/
-static struct prcm_config rate_table[] = {
-        /* PRCM II - FAST */
-        {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
-                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
-                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
-                RATE_IN_242X},
-
-        {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
-                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
-                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
-                RATE_IN_242X},
-
-        /* PRCM III - FAST */
-        {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
-                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
-                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
-                RATE_IN_242X},
-
-        {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
-                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
-                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
-                RATE_IN_242X},
-
-        /* PRCM II - SLOW */
-        {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
-                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
-                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
-                RATE_IN_242X},
-
-        {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
-                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
-                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
-                RATE_IN_242X},
-
-        /* PRCM III - SLOW */
-        {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
-                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
-                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
-                RATE_IN_242X},
-
-        {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
-                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
-                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
-                RATE_IN_242X},
-
-        /* PRCM-VII (boot-bypass) */
-        {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
-                RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
-                RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
-                RATE_IN_242X},
-
-        /* PRCM-VII (boot-bypass) */
-        {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
-                RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
-                RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
-                RATE_IN_242X},
-
-        /* PRCM #3 - ratio2 (ES2) - FAST */
-        {S13M, S660M, S330M, R2_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
-                R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
-                R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
-                V24XX_SDRC_RFR_CTRL_110MHz,
-                RATE_IN_243X},
-
-        /* PRCM #5a - ratio1 - FAST */
-        {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
-                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
-                R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
-                V24XX_SDRC_RFR_CTRL_133MHz,
-                RATE_IN_243X},
-
-        /* PRCM #5b - ratio1 - FAST */
-        {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
-                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
-                R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
-                V24XX_SDRC_RFR_CTRL_100MHz,
-                RATE_IN_243X},
-
-        /* PRCM #3 - ratio2 (ES2) - SLOW */
-        {S13M, S330M, S165M, R2_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
-                R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
-                R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
-                V24XX_SDRC_RFR_CTRL_110MHz,
-                RATE_IN_243X},
-
-        /* PRCM #5a - ratio1 - SLOW */
-        {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
-                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
-                R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
-                V24XX_SDRC_RFR_CTRL_133MHz,
-                RATE_IN_243X},
-
-        /* PRCM #5b - ratio1 - SLOW*/
-        {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
-                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
-                R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
-                V24XX_SDRC_RFR_CTRL_100MHz,
-                RATE_IN_243X},
-
-        /* PRCM-boot/bypass */
-        {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
-                RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
-                RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
-                V24XX_SDRC_RFR_CTRL_BYPASS,
-                RATE_IN_243X},
-
-        /* PRCM-boot/bypass */
-        {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
-                RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
-                RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
-                V24XX_SDRC_RFR_CTRL_BYPASS,
-                RATE_IN_243X},
-
-        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-};
-
-/*-------------------------------------------------------------------------
- * 24xx clock tree.
- *
- * NOTE:In many cases here we are assigning a 'default' parent. In many
- *      cases the parent is selectable. The get/set parent calls will also
- *      switch sources.
- *
- *      Many some clocks say always_enabled, but they can be auto idled for
- *      power savings. They will always be available upon clock request.
- *
- *      Several sources are given initial rates which may be wrong, this will
- *      be fixed up in the init func.
- *
- *      Things are broadly separated below by clock domains. It is
- *      noteworthy that most periferals have dependencies on multiple clock
- *      domains. Many get their interface clocks from the L4 domain, but get
- *      functional clocks from fixed sources or other core domain derived
- *      clocks.
- *-------------------------------------------------------------------------*/
-
-/* Base external input clocks */
-static struct clk func_32k_ck = {
-        .name           = "func_32k_ck",
-        .rate           = 32000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | ALWAYS_ENABLED,
-};
-
-/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
-static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
-        .name           = "osc_ck",
-        .rate           = 26000000,             /* fixed up in clock init */
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | RATE_PROPAGATES,
-};
-
-/* With out modem likely 12MHz, with modem likely 13MHz */
-static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
-        .name           = "sys_ck",             /* ~ ref_clk also */
-        .parent         = &osc_ck,
-        .rate           = 13000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
-        .rate_offset    = 6, /* sysclkdiv 1 or 2, already handled or no boot */
-        .recalc         = &omap2_sys_clk_recalc,
-};
-
-static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
-        .name           = "alt_ck",
-        .rate           = 54000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
-        .recalc         = &omap2_propagate_rate,
-};
-
-/*
- * Analog domain root source clocks
- */
-
-/* dpll_ck, is broken out in to special cases through clksel */
-static struct clk dpll_ck = {
-        .name           = "dpll_ck",
-        .parent         = &sys_ck,              /* Can be func_32k also */
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_PROPAGATES | RATE_CKCTL | CM_PLL_SEL1,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk apll96_ck = {
-        .name           = "apll96_ck",
-        .parent         = &sys_ck,
-        .rate           = 96000000,
-        .flags          = CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X |
-                                RATE_FIXED | RATE_PROPAGATES,
-        .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
-        .enable_bit     = 0x2,
-        .recalc         = &omap2_propagate_rate,
-};
-
-static struct clk apll54_ck = {
-        .name           = "apll54_ck",
-        .parent         = &sys_ck,
-        .rate           = 54000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | RATE_PROPAGATES,
-        .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
-        .enable_bit     = 0x6,
-        .recalc         = &omap2_propagate_rate,
-};
+int omap2_clk_enable(struct clk *clk);
+void omap2_clk_disable(struct clk *clk);
+long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
+int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
+int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
 
-/*
- * PRCM digital base sources
- */
-static struct clk func_54m_ck = {
-        .name           = "func_54m_ck",
-        .parent         = &apll54_ck,   /* can also be alt_clk */
-        .rate           = 54000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
-        .src_offset     = 5,
-        .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
-        .enable_bit     = 0xff,
-        .recalc         = &omap2_propagate_rate,
-};
-
-static struct clk core_ck = {
-        .name           = "core_ck",
-        .parent         = &dpll_ck,             /* can also be 32k */
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                ALWAYS_ENABLED | RATE_PROPAGATES,
-        .recalc         = &omap2_propagate_rate,
-};
-
-static struct clk sleep_ck = {          /* sys_clk or 32k */
-        .name           = "sleep_ck",
-        .parent         = &func_32k_ck,
-        .rate           = 32000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .recalc         = &omap2_propagate_rate,
-};
-
-static struct clk func_96m_ck = {
-        .name           = "func_96m_ck",
-        .parent         = &apll96_ck,
-        .rate           = 96000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | RATE_PROPAGATES,
-        .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
-        .enable_bit     = 0xff,
-        .recalc         = &omap2_propagate_rate,
-};
-
-static struct clk func_48m_ck = {
-        .name           = "func_48m_ck",
-        .parent         = &apll96_ck,    /* 96M or Alt */
-        .rate           = 48000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
-        .src_offset     = 3,
-        .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
-        .enable_bit     = 0xff,
-        .recalc         = &omap2_propagate_rate,
-};
-
-static struct clk func_12m_ck = {
-        .name           = "func_12m_ck",
-        .parent         = &func_48m_ck,
-        .rate           = 12000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | RATE_PROPAGATES,
-        .recalc         = &omap2_propagate_rate,
-        .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
-        .enable_bit     = 0xff,
-};
-
-/* Secure timer, only available in secure mode */
-static struct clk wdt1_osc_ck = {
-        .name           = "ck_wdt1_osc",
-        .parent         = &osc_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk sys_clkout = {
-        .name           = "sys_clkout",
-        .parent         = &func_54m_ck,
-        .rate           = 54000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
-        .src_offset     = 0,
-        .enable_reg     = (void __iomem *)&PRCM_CLKOUT_CTRL,
-        .enable_bit     = 7,
-        .rate_offset    = 3,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* In 2430, new in 2420 ES2 */
-static struct clk sys_clkout2 = {
-        .name           = "sys_clkout2",
-        .parent         = &func_54m_ck,
-        .rate           = 54000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
-        .src_offset     = 8,
-        .enable_reg     = (void __iomem *)&PRCM_CLKOUT_CTRL,
-        .enable_bit     = 15,
-        .rate_offset    = 11,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk emul_ck = {
-        .name           = "emul_ck",
-        .parent         = &func_54m_ck,
-        .flags          = CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&PRCM_CLKEMUL_CTRL,
-        .enable_bit     = 0,
-        .recalc         = &omap2_propagate_rate,
-
-};
-
-/*
- * MPU clock domain
- *      Clocks:
- *              MPU_FCLK, MPU_ICLK
- *              INT_M_FCLK, INT_M_I_CLK
- *
- * - Individual clocks are hardware managed.
- * - Base divider comes from: CM_CLKSEL_MPU
- *
- */
-static struct clk mpu_ck = {    /* Control cpu */
-        .name           = "mpu_ck",
-        .parent         = &core_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL |
-                                ALWAYS_ENABLED | CM_MPU_SEL1 | DELAYED_APP |
-                                CONFIG_PARTICIPANT | RATE_PROPAGATES,
-        .rate_offset    = 0,    /* bits 0-4 */
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/*
- * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
- * Clocks:
- *      2430: IVA2.1_FCLK, IVA2.1_ICLK
- *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
- */
-static struct clk iva2_1_fck = {
-        .name           = "iva2_1_fck",
-        .parent         = &core_ck,
-        .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
-                                DELAYED_APP | RATE_PROPAGATES |
-                                CONFIG_PARTICIPANT,
-        .rate_offset    = 0,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN_DSP,
-        .enable_bit     = 0,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk iva2_1_ick = {
-        .name           = "iva2_1_ick",
-        .parent         = &iva2_1_fck,
-        .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
-                                DELAYED_APP | CONFIG_PARTICIPANT,
-        .rate_offset    = 5,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/*
- * Won't be too specific here. The core clock comes into this block
- * it is divided then tee'ed. One branch goes directly to xyz enable
- * controls. The other branch gets further divided by 2 then possibly
- * routed into a synchronizer and out of clocks abc.
- */
-static struct clk dsp_fck = {
-        .name           = "dsp_fck",
-        .parent         = &core_ck,
-        .flags          = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
-                        DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
-        .rate_offset    = 0,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN_DSP,
-        .enable_bit     = 0,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk dsp_ick = {
-        .name           = "dsp_ick",     /* apparently ipi and isp */
-        .parent         = &dsp_fck,
-        .flags          = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
-                                DELAYED_APP | CONFIG_PARTICIPANT,
-        .rate_offset = 5,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN_DSP,
-        .enable_bit     = 1,            /* for ipi */
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk iva1_ifck = {
-        .name           = "iva1_ifck",
-        .parent         = &core_ck,
-        .flags          = CLOCK_IN_OMAP242X | CM_DSP_SEL1 | RATE_CKCTL |
-                        CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP,
-        .rate_offset= 8,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN_DSP,
-        .enable_bit     = 10,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* IVA1 mpu/int/i/f clocks are /2 of parent */
-static struct clk iva1_mpu_int_ifck = {
-        .name           = "iva1_mpu_int_ifck",
-        .parent         = &iva1_ifck,
-        .flags          = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN_DSP,
-        .enable_bit     = 8,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/*
- * L3 clock domain
- * L3 clocks are used for both interface and functional clocks to
- * multiple entities. Some of these clocks are completely managed
- * by hardware, and some others allow software control. Hardware
- * managed ones general are based on directly CLK_REQ signals and
- * various auto idle settings. The functional spec sets many of these
- * as 'tie-high' for their enables.
- *
- * I-CLOCKS:
- *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
- *      CAM, HS-USB.
- * F-CLOCK
- *      SSI.
- *
- * GPMC memories and SDRC have timing and clock sensitive registers which
- * may very well need notification when the clock changes. Currently for low
- * operating points, these are taken care of in sleep.S.
- */
-static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
-        .name           = "core_l3_ck",
-        .parent         = &core_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
-                                DELAYED_APP | CONFIG_PARTICIPANT |
-                                RATE_PROPAGATES,
-        .rate_offset    = 0,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk usb_l4_ick = {        /* FS-USB interface clock */
-        .name           = "usb_l4_ick",
-        .parent         = &core_l3_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP |
-                                CONFIG_PARTICIPANT,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 0,
-        .rate_offset = 25,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/*
- * SSI is in L3 management domain, its direct parent is core not l3,
- * many core power domain entities are grouped into the L3 clock
- * domain.
- * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
- *
- * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
- */
-static struct clk ssi_ssr_sst_fck = {
-        .name           = "ssi_fck",
-        .parent         = &core_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,     /* bit 1 */
-        .enable_bit     = 1,
-        .rate_offset = 20,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/*
- * GFX clock domain
- *      Clocks:
- * GFX_FCLK, GFX_ICLK
- * GFX_CG1(2d), GFX_CG2(3d)
- *
- * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
- * The 2d and 3d clocks run at a hardware determined
- * divided value of fclk.
- *
- */
-static struct clk gfx_3d_fck = {
-        .name           = "gfx_3d_fck",
-        .parent         = &core_l3_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_CKCTL | CM_GFX_SEL1,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN_GFX,
-        .enable_bit     = 2,
-        .rate_offset= 0,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk gfx_2d_fck = {
-        .name           = "gfx_2d_fck",
-        .parent         = &core_l3_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_CKCTL | CM_GFX_SEL1,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN_GFX,
-        .enable_bit     = 1,
-        .rate_offset= 0,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk gfx_ick = {
-        .name           = "gfx_ick",            /* From l3 */
-        .parent         = &core_l3_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_CKCTL,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN_GFX,       /* bit 0 */
-        .enable_bit     = 0,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-/*
- * Modem clock domain (2430)
- *      CLOCKS:
- *              MDM_OSC_CLK
- *              MDM_ICLK
- */
-static struct clk mdm_ick = {           /* used both as a ick and fck */
-        .name           = "mdm_ick",
-        .parent         = &core_ck,
-        .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_MODEM_SEL1 |
-                                DELAYED_APP | CONFIG_PARTICIPANT,
-        .rate_offset    = 0,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN_MDM,
-        .enable_bit     = 0,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk mdm_osc_ck = {
-        .name           = "mdm_osc_ck",
-        .rate           = 26000000,
-        .parent         = &osc_ck,
-        .flags          = CLOCK_IN_OMAP243X | RATE_FIXED,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN_MDM,
-        .enable_bit     = 1,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-/*
- * L4 clock management domain
- *
- * This domain contains lots of interface clocks from the L4 interface, some
- * functional clocks.   Fixed APLL functional source clocks are managed in
- * this domain.
- */
-static struct clk l4_ck = {             /* used both as an ick and fck */
-        .name           = "l4_ck",
-        .parent         = &core_l3_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
-                                DELAYED_APP | RATE_PROPAGATES,
-        .rate_offset    = 5,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk ssi_l4_ick = {
-        .name           = "ssi_l4_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,     /* bit 1 */
-        .enable_bit     = 1,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-/*
- * DSS clock domain
- * CLOCKs:
- * DSS_L4_ICLK, DSS_L3_ICLK,
- * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
- *
- * DSS is both initiator and target.
- */
-static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
-        .name           = "dss_ick",
-        .parent         = &l4_ck,       /* really both l3 and l4 */
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 0,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk dss1_fck = {
-        .name           = "dss1_fck",
-        .parent         = &core_ck,             /* Core or sys */
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 0,
-        .rate_offset    = 8,
-        .src_offset     = 8,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk dss2_fck = {          /* Alt clk used in power management */
-        .name           = "dss2_fck",
-        .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED |
-                                DELAYED_APP,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 1,
-        .src_offset     = 13,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk dss_54m_fck = {       /* Alt clk used in power management */
-        .name           = "dss_54m_fck",        /* 54m tv clk */
-        .parent         = &func_54m_ck,
-        .rate           = 54000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | RATE_PROPAGATES,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 2,
-        .recalc         = &omap2_propagate_rate,
-};
-
-/*
- * CORE power domain ICLK & FCLK defines.
- * Many of the these can have more than one possible parent. Entries
- * here will likely have an L4 interface parent, and may have multiple
- * functional clock parents.
- */
-static struct clk gpt1_ick = {
-        .name           = "gpt1_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,      /* Bit0 */
-        .enable_bit     = 0,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt1_fck = {
-        .name           = "gpt1_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                CM_WKUP_SEL1,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN_WKUP,      /* Bit0 */
-        .enable_bit     = 0,
-        .src_offset     = 0,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt2_ick = {
-        .name           = "gpt2_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,     /* Bit4 */
-        .enable_bit     = 4,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt2_fck = {
-        .name           = "gpt2_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 4,
-        .src_offset     = 2,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt3_ick = {
-        .name           = "gpt3_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,     /* Bit5 */
-        .enable_bit     = 5,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt3_fck = {
-        .name           = "gpt3_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 5,
-        .src_offset     = 4,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt4_ick = {
-        .name           = "gpt4_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,     /* Bit6 */
-        .enable_bit     = 6,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt4_fck = {
-        .name           = "gpt4_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 6,
-        .src_offset     = 6,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt5_ick = {
-        .name           = "gpt5_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* Bit7 */
-        .enable_bit     = 7,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt5_fck = {
-        .name           = "gpt5_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 7,
-        .src_offset     = 8,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt6_ick = {
-        .name           = "gpt6_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_bit     = 8,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* bit8 */
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt6_fck = {
-        .name           = "gpt6_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 8,
-        .src_offset     = 10,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt7_ick = {
-        .name           = "gpt7_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* bit9 */
-        .enable_bit     = 9,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt7_fck = {
-        .name           = "gpt7_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 9,
-        .src_offset     = 12,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt8_ick = {
-        .name           = "gpt8_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* bit10 */
-        .enable_bit     = 10,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt8_fck = {
-        .name           = "gpt8_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 10,
-        .src_offset     = 14,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt9_ick = {
-        .name           = "gpt9_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 11,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt9_fck = {
-        .name           = "gpt9_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                        CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 11,
-        .src_offset     = 16,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt10_ick = {
-        .name           = "gpt10_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 12,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt10_fck = {
-        .name           = "gpt10_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                        CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 12,
-        .src_offset     = 18,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt11_ick = {
-        .name           = "gpt11_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 13,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt11_fck = {
-        .name           = "gpt11_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                        CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 13,
-        .src_offset     = 20,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt12_ick = {
-        .name           = "gpt12_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* bit14 */
-        .enable_bit     = 14,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt12_fck = {
-        .name           = "gpt12_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                        CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 14,
-        .src_offset     = 22,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp1_ick = {
-        .name           = "mcbsp1_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_bit     = 15,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* bit16 */
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp1_fck = {
-        .name           = "mcbsp1_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_bit     = 15,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp2_ick = {
-        .name           = "mcbsp2_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_bit     = 16,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp2_fck = {
-        .name           = "mcbsp2_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_bit     = 16,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp3_ick = {
-        .name           = "mcbsp3_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 3,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp3_fck = {
-        .name           = "mcbsp3_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 3,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp4_ick = {
-        .name           = "mcbsp4_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 4,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp4_fck = {
-        .name           = "mcbsp4_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 4,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp5_ick = {
-        .name           = "mcbsp5_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 5,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp5_fck = {
-        .name           = "mcbsp5_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 5,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcspi1_ick = {
-        .name           = "mcspi_ick",
-        .id             = 1,
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 17,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcspi1_fck = {
-        .name           = "mcspi_fck",
-        .id             = 1,
-        .parent         = &func_48m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 17,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcspi2_ick = {
-        .name           = "mcspi_ick",
-        .id             = 2,
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 18,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcspi2_fck = {
-        .name           = "mcspi_fck",
-        .id             = 2,
-        .parent         = &func_48m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 18,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcspi3_ick = {
-        .name           = "mcspi_ick",
-        .id             = 3,
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 9,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcspi3_fck = {
-        .name           = "mcspi_fck",
-        .id             = 3,
-        .parent         = &func_48m_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 9,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk uart1_ick = {
-        .name           = "uart1_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 21,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk uart1_fck = {
-        .name           = "uart1_fck",
-        .parent         = &func_48m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 21,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk uart2_ick = {
-        .name           = "uart2_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 22,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk uart2_fck = {
-        .name           = "uart2_fck",
-        .parent         = &func_48m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 22,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk uart3_ick = {
-        .name           = "uart3_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 2,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk uart3_fck = {
-        .name           = "uart3_fck",
-        .parent         = &func_48m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 2,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpios_ick = {
-        .name           = "gpios_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
-        .enable_bit     = 2,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpios_fck = {
-        .name           = "gpios_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN_WKUP,
-        .enable_bit     = 2,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mpu_wdt_ick = {
-        .name           = "mpu_wdt_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
-        .enable_bit     = 3,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mpu_wdt_fck = {
-        .name           = "mpu_wdt_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN_WKUP,
-        .enable_bit     = 3,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk sync_32k_ick = {
-        .name           = "sync_32k_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
-        .enable_bit     = 1,
-        .recalc         = &omap2_followparent_recalc,
-};
-static struct clk wdt1_ick = {
-        .name           = "wdt1_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
-        .enable_bit     = 4,
-        .recalc         = &omap2_followparent_recalc,
-};
-static struct clk omapctrl_ick = {
-        .name           = "omapctrl_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
-        .enable_bit     = 5,
-        .recalc         = &omap2_followparent_recalc,
-};
-static struct clk icr_ick = {
-        .name           = "icr_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
-        .enable_bit     = 6,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk cam_ick = {
-        .name           = "cam_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 31,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk cam_fck = {
-        .name           = "cam_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 31,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mailboxes_ick = {
-        .name           = "mailboxes_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 30,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk wdt4_ick = {
-        .name           = "wdt4_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 29,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk wdt4_fck = {
-        .name           = "wdt4_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 29,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk wdt3_ick = {
-        .name           = "wdt3_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 28,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk wdt3_fck = {
-        .name           = "wdt3_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 28,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mspro_ick = {
-        .name           = "mspro_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 27,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mspro_fck = {
-        .name           = "mspro_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 27,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mmc_ick = {
-        .name           = "mmc_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 26,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mmc_fck = {
-        .name           = "mmc_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 26,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk fac_ick = {
-        .name           = "fac_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 25,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk fac_fck = {
-        .name           = "fac_fck",
-        .parent         = &func_12m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 25,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk eac_ick = {
-        .name           = "eac_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 24,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk eac_fck = {
-        .name           = "eac_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 24,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk hdq_ick = {
-        .name           = "hdq_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 23,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk hdq_fck = {
-        .name           = "hdq_fck",
-        .parent         = &func_12m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 23,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk i2c2_ick = {
-        .name           = "i2c_ick",
-        .id             = 2,
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 20,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk i2c2_fck = {
-        .name           = "i2c_fck",
-        .id             = 2,
-        .parent         = &func_12m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 20,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk i2chs2_fck = {
-        .name           = "i2chs2_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 20,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk i2c1_ick = {
-        .name           = "i2c_ick",
-        .id             = 1,
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 19,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk i2c1_fck = {
-        .name           = "i2c_fck",
-        .id             = 1,
-        .parent         = &func_12m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 19,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk i2chs1_fck = {
-        .name           = "i2chs1_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 19,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk vlynq_ick = {
-        .name           = "vlynq_ick",
-        .parent         = &core_l3_ck,
-        .flags          = CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 3,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk vlynq_fck = {
-        .name           = "vlynq_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP242X  | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 3,
-        .src_offset     = 15,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk sdrc_ick = {
-        .name           = "sdrc_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN3_CORE,
-        .enable_bit     = 2,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk des_ick = {
-        .name           = "des_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN4_CORE,
-        .enable_bit     = 0,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk sha_ick = {
-        .name           = "sha_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN4_CORE,
-        .enable_bit     = 1,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk rng_ick = {
-        .name           = "rng_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN4_CORE,
-        .enable_bit     = 2,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk aes_ick = {
-        .name           = "aes_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN4_CORE,
-        .enable_bit     = 3,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk pka_ick = {
-        .name           = "pka_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN4_CORE,
-        .enable_bit     = 4,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk usb_fck = {
-        .name           = "usb_fck",
-        .parent         = &func_48m_ck,
-        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 0,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk usbhs_ick = {
-        .name           = "usbhs_ick",
-        .parent         = &core_l3_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 6,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mmchs1_ick = {
-        .name           = "mmchs1_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 7,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mmchs1_fck = {
-        .name           = "mmchs1_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 7,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mmchs2_ick = {
-        .name           = "mmchs2_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 8,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mmchs2_fck = {
-        .name           = "mmchs2_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 8,
-        .recalc         = &omap2_followparent_recalc,
-};
+#ifdef CONFIG_OMAP_RESET_CLOCKS
+void omap2_clk_disable_unused(struct clk *clk);
+#else
+#define omap2_clk_disable_unused        NULL
+#endif
 
-static struct clk gpio5_ick = {
-        .name           = "gpio5_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 10,
-        .recalc         = &omap2_followparent_recalc,
-};
+void omap2_clksel_recalc(struct clk *clk);
+void omap2_init_clksel_parent(struct clk *clk);
+u32 omap2_clksel_get_divisor(struct clk *clk);
+u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
+                                u32 *new_div);
+u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val);
+u32 omap2_divisor_to_clksel(struct clk *clk, u32 div);
+void omap2_fixed_divisor_recalc(struct clk *clk);
+long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
+int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
+u32 omap2_get_dpll_rate(struct clk *clk);
+int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
 
-static struct clk gpio5_fck = {
-        .name           = "gpio5_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 10,
-        .recalc         = &omap2_followparent_recalc,
-};
+extern u8 cpu_mask;
 
-static struct clk mdm_intc_ick = {
-        .name           = "mdm_intc_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 11,
-        .recalc         = &omap2_followparent_recalc,
+/* clksel_rate data common to 24xx/343x */
+static const struct clksel_rate gpt_32k_rates[] = {
+         { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
+         { .div = 0 }
 };
 
-static struct clk mmchsdb1_fck = {
-        .name           = "mmchsdb1_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 16,
-        .recalc         = &omap2_followparent_recalc,
+static const struct clksel_rate gpt_sys_rates[] = {
+         { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
+         { .div = 0 }
 };
 
-static struct clk mmchsdb2_fck = {
-        .name           = "mmchsdb2_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 17,
-        .recalc         = &omap2_followparent_recalc,
+static const struct clksel_rate gfx_l3_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
+        { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X },
+        { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X },
+        { .div = 0 }
 };
 
-/*
- * This clock is a composite clock which does entire set changes then
- * forces a rebalance. It keys on the MPU speed, but it really could
- * be any key speed part of a set in the rate table.
- *
- * to really change a set, you need memory table sets which get changed
- * in sram, pre-notifiers & post notifiers, changing the top set, without
- * having low level display recalc's won't work... this is why dpm notifiers
- * work, isr's off, walk a list of clocks already _off_ and not messing with
- * the bus.
- *
- * This clock should have no parent. It embodies the entire upper level
- * active set. A parent will mess up some of the init also.
- */
-static struct clk virt_prcm_set = {
-        .name           = "virt_prcm_set",
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
-        .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
-        .recalc         = &omap2_mpu_recalc,    /* sets are keyed on mpu rate */
-        .set_rate       = &omap2_select_table_rate,
-        .round_rate     = &omap2_round_to_table_rate,
-};
-
-static struct clk *onchip_clks[] = {
-        /* external root sources */
-        &func_32k_ck,
-        &osc_ck,
-        &sys_ck,
-        &alt_ck,
-        /* internal analog sources */
-        &dpll_ck,
-        &apll96_ck,
-        &apll54_ck,
-        /* internal prcm root sources */
-        &func_54m_ck,
-        &core_ck,
-        &sleep_ck,
-        &func_96m_ck,
-        &func_48m_ck,
-        &func_12m_ck,
-        &wdt1_osc_ck,
-        &sys_clkout,
-        &sys_clkout2,
-        &emul_ck,
-        /* mpu domain clocks */
-        &mpu_ck,
-        /* dsp domain clocks */
-        &iva2_1_fck,            /* 2430 */
-        &iva2_1_ick,
-        &dsp_ick,               /* 2420 */
-        &dsp_fck,
-        &iva1_ifck,
-        &iva1_mpu_int_ifck,
-        /* GFX domain clocks */
-        &gfx_3d_fck,
-        &gfx_2d_fck,
-        &gfx_ick,
-        /* Modem domain clocks */
-        &mdm_ick,
-        &mdm_osc_ck,
-        /* DSS domain clocks */
-        &dss_ick,
-        &dss1_fck,
-        &dss2_fck,
-        &dss_54m_fck,
-        /* L3 domain clocks */
-        &core_l3_ck,
-        &ssi_ssr_sst_fck,
-        &usb_l4_ick,
-        /* L4 domain clocks */
-        &l4_ck,                 /* used as both core_l4 and wu_l4 */
-        &ssi_l4_ick,
-        /* virtual meta-group clock */
-        &virt_prcm_set,
-        /* general l4 interface ck, multi-parent functional clk */
-        &gpt1_ick,
-        &gpt1_fck,
-        &gpt2_ick,
-        &gpt2_fck,
-        &gpt3_ick,
-        &gpt3_fck,
-        &gpt4_ick,
-        &gpt4_fck,
-        &gpt5_ick,
-        &gpt5_fck,
-        &gpt6_ick,
-        &gpt6_fck,
-        &gpt7_ick,
-        &gpt7_fck,
-        &gpt8_ick,
-        &gpt8_fck,
-        &gpt9_ick,
-        &gpt9_fck,
-        &gpt10_ick,
-        &gpt10_fck,
-        &gpt11_ick,
-        &gpt11_fck,
-        &gpt12_ick,
-        &gpt12_fck,
-        &mcbsp1_ick,
-        &mcbsp1_fck,
-        &mcbsp2_ick,
-        &mcbsp2_fck,
-        &mcbsp3_ick,
-        &mcbsp3_fck,
-        &mcbsp4_ick,
-        &mcbsp4_fck,
-        &mcbsp5_ick,
-        &mcbsp5_fck,
-        &mcspi1_ick,
-        &mcspi1_fck,
-        &mcspi2_ick,
-        &mcspi2_fck,
-        &mcspi3_ick,
-        &mcspi3_fck,
-        &uart1_ick,
-        &uart1_fck,
-        &uart2_ick,
-        &uart2_fck,
-        &uart3_ick,
-        &uart3_fck,
-        &gpios_ick,
-        &gpios_fck,
-        &mpu_wdt_ick,
-        &mpu_wdt_fck,
-        &sync_32k_ick,
-        &wdt1_ick,
-        &omapctrl_ick,
-        &icr_ick,
-        &cam_fck,
-        &cam_ick,
-        &mailboxes_ick,
-        &wdt4_ick,
-        &wdt4_fck,
-        &wdt3_ick,
-        &wdt3_fck,
-        &mspro_ick,
-        &mspro_fck,
-        &mmc_ick,
-        &mmc_fck,
-        &fac_ick,
-        &fac_fck,
-        &eac_ick,
-        &eac_fck,
-        &hdq_ick,
-        &hdq_fck,
-        &i2c1_ick,
-        &i2c1_fck,
-        &i2chs1_fck,
-        &i2c2_ick,
-        &i2c2_fck,
-        &i2chs2_fck,
-        &vlynq_ick,
-        &vlynq_fck,
-        &sdrc_ick,
-        &des_ick,
-        &sha_ick,
-        &rng_ick,
-        &aes_ick,
-        &pka_ick,
-        &usb_fck,
-        &usbhs_ick,
-        &mmchs1_ick,
-        &mmchs1_fck,
-        &mmchs2_ick,
-        &mmchs2_fck,
-        &gpio5_ick,
-        &gpio5_fck,
-        &mdm_intc_ick,
-        &mmchsdb1_fck,
-        &mmchsdb2_fck,
-};
 
 #endif
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
new file mode 100644
index 000000000000..ece32d8acba4
--- /dev/null
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -0,0 +1,539 @@
+/*
+ *  linux/arch/arm/mach-omap2/clock.c
+ *
+ *  Copyright (C) 2005-2008 Texas Instruments, Inc.
+ *  Copyright (C) 2004-2008 Nokia Corporation
+ *
+ *  Contacts:
+ *  Richard Woodruff <r-woodruff2@ti.com>
+ *  Paul Walmsley
+ *
+ *  Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
+ *  Gordon McNutt and RidgeRun, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+
+#include <linux/io.h>
+#include <linux/cpufreq.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/sram.h>
+#include <asm/div64.h>
+#include <asm/bitops.h>
+
+#include "memory.h"
+#include "clock.h"
+#include "clock24xx.h"
+#include "prm.h"
+#include "prm-regbits-24xx.h"
+#include "cm.h"
+#include "cm-regbits-24xx.h"
+
+/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
+#define EN_APLL_STOPPED                 0
+#define EN_APLL_LOCKED                  3
+
+/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
+#define APLLS_CLKIN_19_2MHZ             0
+#define APLLS_CLKIN_13MHZ               2
+#define APLLS_CLKIN_12MHZ               3
+
+/* #define DOWN_VARIABLE_DPLL 1 */              /* Experimental */
+
+static struct prcm_config *curr_prcm_set;
+static struct clk *vclk;
+static struct clk *sclk;
+
+/*-------------------------------------------------------------------------
+ * Omap24xx specific clock functions
+ *-------------------------------------------------------------------------*/
+
+/* This actually returns the rate of core_ck, not dpll_ck. */
+static u32 omap2_get_dpll_rate_24xx(struct clk *tclk)
+{
+        long long dpll_clk;
+        u8 amult;
+
+        dpll_clk = omap2_get_dpll_rate(tclk);
+
+        amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+        amult &= OMAP24XX_CORE_CLK_SRC_MASK;
+        dpll_clk *= amult;
+
+        return dpll_clk;
+}
+
+static int omap2_enable_osc_ck(struct clk *clk)
+{
+        u32 pcc;
+
+        pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
+
+        __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK,
+                      OMAP24XX_PRCM_CLKSRC_CTRL);
+
+        return 0;
+}
+
+static void omap2_disable_osc_ck(struct clk *clk)
+{
+        u32 pcc;
+
+        pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
+
+        __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK,
+                      OMAP24XX_PRCM_CLKSRC_CTRL);
+}
+
+#ifdef OLD_CK
+/* Recalculate SYST_CLK */
+static void omap2_sys_clk_recalc(struct clk * clk)
+{
+        u32 div = PRCM_CLKSRC_CTRL;
+        div &= (1 << 7) | (1 << 6);     /* Test if ext clk divided by 1 or 2 */
+        div >>= clk->rate_offset;
+        clk->rate = (clk->parent->rate / div);
+        propagate_rate(clk);
+}
+#endif  /* OLD_CK */
+
+/* Enable an APLL if off */
+static int omap2_clk_fixed_enable(struct clk *clk)
+{
+        u32 cval, apll_mask;
+
+        apll_mask = EN_APLL_LOCKED << clk->enable_bit;
+
+        cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+
+        if ((cval & apll_mask) == apll_mask)
+                return 0;   /* apll already enabled */
+
+        cval &= ~apll_mask;
+        cval |= apll_mask;
+        cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
+
+        if (clk == &apll96_ck)
+                cval = OMAP24XX_ST_96M_APLL;
+        else if (clk == &apll54_ck)
+                cval = OMAP24XX_ST_54M_APLL;
+
+        omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
+                            clk->name);
+
+        /*
+         * REVISIT: Should we return an error code if omap2_wait_clock_ready()
+         * fails?
+         */
+        return 0;
+}
+
+/* Stop APLL */
+static void omap2_clk_fixed_disable(struct clk *clk)
+{
+        u32 cval;
+
+        cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+        cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
+        cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
+}
+
+/*
+ * Uses the current prcm set to tell if a rate is valid.
+ * You can go slower, but not faster within a given rate set.
+ */
+static u32 omap2_dpll_round_rate(unsigned long target_rate)
+{
+        u32 high, low, core_clk_src;
+
+        core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+        core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
+
+        if (core_clk_src == CORE_CLK_SRC_DPLL) {        /* DPLL clockout */
+                high = curr_prcm_set->dpll_speed * 2;
+                low = curr_prcm_set->dpll_speed;
+        } else {                                /* DPLL clockout x 2 */
+                high = curr_prcm_set->dpll_speed;
+                low = curr_prcm_set->dpll_speed / 2;
+        }
+
+#ifdef DOWN_VARIABLE_DPLL
+        if (target_rate > high)
+                return high;
+        else
+                return target_rate;
+#else
+        if (target_rate > low)
+                return high;
+        else
+                return low;
+#endif
+
+}
+
+static void omap2_dpll_recalc(struct clk *clk)
+{
+        clk->rate = omap2_get_dpll_rate_24xx(clk);
+
+        propagate_rate(clk);
+}
+
+static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate)
+{
+        u32 cur_rate, low, mult, div, valid_rate, done_rate;
+        u32 bypass = 0;
+        struct prcm_config tmpset;
+        const struct dpll_data *dd;
+        unsigned long flags;
+        int ret = -EINVAL;
+
+        local_irq_save(flags);
+        cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
+        mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+        mult &= OMAP24XX_CORE_CLK_SRC_MASK;
+
+        if ((rate == (cur_rate / 2)) && (mult == 2)) {
+                omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
+        } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
+                omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
+        } else if (rate != cur_rate) {
+                valid_rate = omap2_dpll_round_rate(rate);
+                if (valid_rate != rate)
+                        goto dpll_exit;
+
+                if (mult == 1)
+                        low = curr_prcm_set->dpll_speed;
+                else
+                        low = curr_prcm_set->dpll_speed / 2;
+
+                dd = clk->dpll_data;
+                if (!dd)
+                        goto dpll_exit;
+
+                tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
+                tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
+                                           dd->div1_mask);
+                div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
+                tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+                tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
+                if (rate > low) {
+                        tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
+                        mult = ((rate / 2) / 1000000);
+                        done_rate = CORE_CLK_SRC_DPLL_X2;
+                } else {
+                        tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
+                        mult = (rate / 1000000);
+                        done_rate = CORE_CLK_SRC_DPLL;
+                }
+                tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
+                tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
+
+                /* Worst case */
+                tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
+
+                if (rate == curr_prcm_set->xtal_speed)  /* If asking for 1-1 */
+                        bypass = 1;
+
+                omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); /* For init_mem */
+
+                /* Force dll lock mode */
+                omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
+                               bypass);
+
+                /* Errata: ret dll entry state */
+                omap2_init_memory_params(omap2_dll_force_needed());
+                omap2_reprogram_sdrc(done_rate, 0);
+        }
+        omap2_dpll_recalc(&dpll_ck);
+        ret = 0;
+
+dpll_exit:
+        local_irq_restore(flags);
+        return(ret);
+}
+
+/**
+ * omap2_table_mpu_recalc - just return the MPU speed
+ * @clk: virt_prcm_set struct clk
+ *
+ * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
+ */
+static void omap2_table_mpu_recalc(struct clk *clk)
+{
+        clk->rate = curr_prcm_set->mpu_speed;
+}
+
+/*
+ * Look for a rate equal or less than the target rate given a configuration set.
+ *
+ * What's not entirely clear is "which" field represents the key field.
+ * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
+ * just uses the ARM rates.
+ */
+static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
+{
+        struct prcm_config *ptr;
+        long highest_rate;
+
+        if (clk != &virt_prcm_set)
+                return -EINVAL;
+
+        highest_rate = -EINVAL;
+
+        for (ptr = rate_table; ptr->mpu_speed; ptr++) {
+                if (!(ptr->flags & cpu_mask))
+                        continue;
+                if (ptr->xtal_speed != sys_ck.rate)
+                        continue;
+
+                highest_rate = ptr->mpu_speed;
+
+                /* Can check only after xtal frequency check */
+                if (ptr->mpu_speed <= rate)
+                        break;
+        }
+        return highest_rate;
+}
+
+/* Sets basic clocks based on the specified rate */
+static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
+{
+        u32 cur_rate, done_rate, bypass = 0, tmp;
+        struct prcm_config *prcm;
+        unsigned long found_speed = 0;
+        unsigned long flags;
+
+        if (clk != &virt_prcm_set)
+                return -EINVAL;
+
+        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+                if (!(prcm->flags & cpu_mask))
+                        continue;
+
+                if (prcm->xtal_speed != sys_ck.rate)
+                        continue;
+
+                if (prcm->mpu_speed <= rate) {
+                        found_speed = prcm->mpu_speed;
+                        break;
+                }
+        }
+
+        if (!found_speed) {
+                printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
+                       rate / 1000000);
+                return -EINVAL;
+        }
+
+        curr_prcm_set = prcm;
+        cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
+
+        if (prcm->dpll_speed == cur_rate / 2) {
+                omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
+        } else if (prcm->dpll_speed == cur_rate * 2) {
+                omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
+        } else if (prcm->dpll_speed != cur_rate) {
+                local_irq_save(flags);
+
+                if (prcm->dpll_speed == prcm->xtal_speed)
+                        bypass = 1;
+
+                if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
+                    CORE_CLK_SRC_DPLL_X2)
+                        done_rate = CORE_CLK_SRC_DPLL_X2;
+                else
+                        done_rate = CORE_CLK_SRC_DPLL;
+
+                /* MPU divider */
+                cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
+
+                /* dsp + iva1 div(2420), iva2.1(2430) */
+                cm_write_mod_reg(prcm->cm_clksel_dsp,
+                                 OMAP24XX_DSP_MOD, CM_CLKSEL);
+
+                cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
+
+                /* Major subsystem dividers */
+                tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
+                cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1);
+                if (cpu_is_omap2430())
+                        cm_write_mod_reg(prcm->cm_clksel_mdm,
+                                         OMAP2430_MDM_MOD, CM_CLKSEL);
+
+                /* x2 to enter init_mem */
+                omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
+
+                omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
+                               bypass);
+
+                omap2_init_memory_params(omap2_dll_force_needed());
+                omap2_reprogram_sdrc(done_rate, 0);
+
+                local_irq_restore(flags);
+        }
+        omap2_dpll_recalc(&dpll_ck);
+
+        return 0;
+}
+
+static struct clk_functions omap2_clk_functions = {
+        .clk_enable             = omap2_clk_enable,
+        .clk_disable            = omap2_clk_disable,
+        .clk_round_rate         = omap2_clk_round_rate,
+        .clk_set_rate           = omap2_clk_set_rate,
+        .clk_set_parent         = omap2_clk_set_parent,
+        .clk_disable_unused     = omap2_clk_disable_unused,
+};
+
+static u32 omap2_get_apll_clkin(void)
+{
+        u32 aplls, sclk = 0;
+
+        aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
+        aplls &= OMAP24XX_APLLS_CLKIN_MASK;
+        aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
+
+        if (aplls == APLLS_CLKIN_19_2MHZ)
+                sclk = 19200000;
+        else if (aplls == APLLS_CLKIN_13MHZ)
+                sclk = 13000000;
+        else if (aplls == APLLS_CLKIN_12MHZ)
+                sclk = 12000000;
+
+        return sclk;
+}
+
+static u32 omap2_get_sysclkdiv(void)
+{
+        u32 div;
+
+        div = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
+        div &= OMAP_SYSCLKDIV_MASK;
+        div >>= OMAP_SYSCLKDIV_SHIFT;
+
+        return div;
+}
+
+static void omap2_osc_clk_recalc(struct clk *clk)
+{
+        clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv();
+        propagate_rate(clk);
+}
+
+static void omap2_sys_clk_recalc(struct clk *clk)
+{
+        clk->rate = clk->parent->rate / omap2_get_sysclkdiv();
+        propagate_rate(clk);
+}
+
+/*
+ * Set clocks for bypass mode for reboot to work.
+ */
+void omap2_clk_prepare_for_reboot(void)
+{
+        u32 rate;
+
+        if (vclk == NULL || sclk == NULL)
+                return;
+
+        rate = clk_get_rate(sclk);
+        clk_set_rate(vclk, rate);
+}
+
+/*
+ * Switch the MPU rate if specified on cmdline.
+ * We cannot do this early until cmdline is parsed.
+ */
+static int __init omap2_clk_arch_init(void)
+{
+        if (!mpurate)
+                return -EINVAL;
+
+        if (omap2_select_table_rate(&virt_prcm_set, mpurate))
+                printk(KERN_ERR "Could not find matching MPU rate\n");
+
+        recalculate_root_clocks();
+
+        printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
+               "%ld.%01ld/%ld/%ld MHz\n",
+               (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
+               (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
+
+        return 0;
+}
+arch_initcall(omap2_clk_arch_init);
+
+int __init omap2_clk_init(void)
+{
+        struct prcm_config *prcm;
+        struct clk **clkp;
+        u32 clkrate;
+
+        if (cpu_is_omap242x())
+                cpu_mask = RATE_IN_242X;
+        else if (cpu_is_omap2430())
+                cpu_mask = RATE_IN_243X;
+
+        clk_init(&omap2_clk_functions);
+
+        omap2_osc_clk_recalc(&osc_ck);
+        omap2_sys_clk_recalc(&sys_ck);
+
+        for (clkp = onchip_24xx_clks;
+             clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks);
+             clkp++) {
+
+                if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
+                        clk_register(*clkp);
+                        continue;
+                }
+
+                if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) {
+                        clk_register(*clkp);
+                        continue;
+                }
+        }
+
+        /* Check the MPU rate set by bootloader */
+        clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
+        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+                if (!(prcm->flags & cpu_mask))
+                        continue;
+                if (prcm->xtal_speed != sys_ck.rate)
+                        continue;
+                if (prcm->dpll_speed <= clkrate)
+                         break;
+        }
+        curr_prcm_set = prcm;
+
+        recalculate_root_clocks();
+
+        printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
+               "%ld.%01ld/%ld/%ld MHz\n",
+               (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
+               (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
+
+        /*
+         * Only enable those clocks we will need, let the drivers
+         * enable other clocks as necessary
+         */
+        clk_enable_init_clocks();
+
+        /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
+        vclk = clk_get(NULL, "virt_prcm_set");
+        sclk = clk_get(NULL, "sys_ck");
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
new file mode 100644
index 000000000000..88081ed13f96
--- /dev/null
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -0,0 +1,2643 @@
+/*
+ *  linux/arch/arm/mach-omap2/clock24xx.h
+ *
+ *  Copyright (C) 2005-2008 Texas Instruments, Inc.
+ *  Copyright (C) 2004-2008 Nokia Corporation
+ *
+ *  Contacts:
+ *  Richard Woodruff <r-woodruff2@ti.com>
+ *  Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
+#define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
+
+#include "clock.h"
+
+#include "prm.h"
+#include "cm.h"
+#include "prm-regbits-24xx.h"
+#include "cm-regbits-24xx.h"
+#include "sdrc.h"
+
+static void omap2_table_mpu_recalc(struct clk *clk);
+static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
+static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
+static void omap2_sys_clk_recalc(struct clk *clk);
+static void omap2_osc_clk_recalc(struct clk *clk);
+static void omap2_sys_clk_recalc(struct clk *clk);
+static void omap2_dpll_recalc(struct clk *clk);
+static int omap2_clk_fixed_enable(struct clk *clk);
+static void omap2_clk_fixed_disable(struct clk *clk);
+static int omap2_enable_osc_ck(struct clk *clk);
+static void omap2_disable_osc_ck(struct clk *clk);
+static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate);
+
+/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
+ * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
+ * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
+ */
+struct prcm_config {
+        unsigned long xtal_speed;       /* crystal rate */
+        unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
+        unsigned long mpu_speed;        /* speed of MPU */
+        unsigned long cm_clksel_mpu;    /* mpu divider */
+        unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
+        unsigned long cm_clksel_gfx;    /* gfx dividers */
+        unsigned long cm_clksel1_core;  /* major subsystem dividers */
+        unsigned long cm_clksel1_pll;   /* m,n */
+        unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
+        unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
+        unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
+        unsigned char flags;
+};
+
+/*
+ * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
+ * These configurations are characterized by voltage and speed for clocks.
+ * The device is only validated for certain combinations. One way to express
+ * these combinations is via the 'ratio's' which the clocks operate with
+ * respect to each other. These ratio sets are for a given voltage/DPLL
+ * setting. All configurations can be described by a DPLL setting and a ratio
+ * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
+ *
+ * 2430 differs from 2420 in that there are no more phase synchronizers used.
+ * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
+ * 2430 (iva2.1, NOdsp, mdm)
+ */
+
+/* Core fields for cm_clksel, not ratio governed */
+#define RX_CLKSEL_DSS1                  (0x10 << 8)
+#define RX_CLKSEL_DSS2                  (0x0 << 13)
+#define RX_CLKSEL_SSI                   (0x5 << 20)
+
+/*-------------------------------------------------------------------------
+ * Voltage/DPLL ratios
+ *-------------------------------------------------------------------------*/
+
+/* 2430 Ratio's, 2430-Ratio Config 1 */
+#define R1_CLKSEL_L3                    (4 << 0)
+#define R1_CLKSEL_L4                    (2 << 5)
+#define R1_CLKSEL_USB                   (4 << 25)
+#define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
+                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
+                                        R1_CLKSEL_L4 | R1_CLKSEL_L3
+#define R1_CLKSEL_MPU                   (2 << 0)
+#define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
+#define R1_CLKSEL_DSP                   (2 << 0)
+#define R1_CLKSEL_DSP_IF                (2 << 5)
+#define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
+#define R1_CLKSEL_GFX                   (2 << 0)
+#define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
+#define R1_CLKSEL_MDM                   (4 << 0)
+#define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
+
+/* 2430-Ratio Config 2 */
+#define R2_CLKSEL_L3                    (6 << 0)
+#define R2_CLKSEL_L4                    (2 << 5)
+#define R2_CLKSEL_USB                   (2 << 25)
+#define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
+                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
+                                        R2_CLKSEL_L4 | R2_CLKSEL_L3
+#define R2_CLKSEL_MPU                   (2 << 0)
+#define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
+#define R2_CLKSEL_DSP                   (2 << 0)
+#define R2_CLKSEL_DSP_IF                (3 << 5)
+#define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
+#define R2_CLKSEL_GFX                   (2 << 0)
+#define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
+#define R2_CLKSEL_MDM                   (6 << 0)
+#define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
+
+/* 2430-Ratio Bootm (BYPASS) */
+#define RB_CLKSEL_L3                    (1 << 0)
+#define RB_CLKSEL_L4                    (1 << 5)
+#define RB_CLKSEL_USB                   (1 << 25)
+#define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
+                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
+                                        RB_CLKSEL_L4 | RB_CLKSEL_L3
+#define RB_CLKSEL_MPU                   (1 << 0)
+#define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
+#define RB_CLKSEL_DSP                   (1 << 0)
+#define RB_CLKSEL_DSP_IF                (1 << 5)
+#define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
+#define RB_CLKSEL_GFX                   (1 << 0)
+#define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
+#define RB_CLKSEL_MDM                   (1 << 0)
+#define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
+
+/* 2420 Ratio Equivalents */
+#define RXX_CLKSEL_VLYNQ                (0x12 << 15)
+#define RXX_CLKSEL_SSI                  (0x8 << 20)
+
+/* 2420-PRCM III 532MHz core */
+#define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
+#define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
+#define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
+#define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
+                                        RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
+                                        RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
+                                        RIII_CLKSEL_L3
+#define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
+#define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
+#define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
+#define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
+#define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
+#define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
+#define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
+#define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
+                                        RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
+                                        RIII_CLKSEL_DSP
+#define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
+#define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
+
+/* 2420-PRCM II 600MHz core */
+#define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
+#define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
+#define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
+#define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
+                                        RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
+                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
+                                        RII_CLKSEL_L4 | RII_CLKSEL_L3
+#define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
+#define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
+#define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
+#define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
+#define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
+#define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
+#define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
+#define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
+                                        RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
+                                        RII_CLKSEL_DSP
+#define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
+#define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
+
+/* 2420-PRCM I 660MHz core */
+#define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
+#define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
+#define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
+#define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
+                                        RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
+                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
+                                        RI_CLKSEL_L4 | RI_CLKSEL_L3
+#define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
+#define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
+#define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
+#define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
+#define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
+#define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
+#define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
+#define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
+                                        RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
+                                        RI_CLKSEL_DSP
+#define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
+#define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
+
+/* 2420-PRCM VII (boot) */
+#define RVII_CLKSEL_L3                  (1 << 0)
+#define RVII_CLKSEL_L4                  (1 << 5)
+#define RVII_CLKSEL_DSS1                (1 << 8)
+#define RVII_CLKSEL_DSS2                (0 << 13)
+#define RVII_CLKSEL_VLYNQ               (1 << 15)
+#define RVII_CLKSEL_SSI                 (1 << 20)
+#define RVII_CLKSEL_USB                 (1 << 25)
+
+#define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
+                                        RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
+                                        RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
+
+#define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
+#define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
+
+#define RVII_CLKSEL_DSP                 (1 << 0)
+#define RVII_CLKSEL_DSP_IF              (1 << 5)
+#define RVII_SYNC_DSP                   (0 << 7)
+#define RVII_CLKSEL_IVA                 (1 << 8)
+#define RVII_SYNC_IVA                   (0 << 13)
+#define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
+                                        RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
+
+#define RVII_CLKSEL_GFX                 (1 << 0)
+#define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
+
+/*-------------------------------------------------------------------------
+ * 2430 Target modes: Along with each configuration the CPU has several
+ * modes which goes along with them. Modes mainly are the addition of
+ * describe DPLL combinations to go along with a ratio.
+ *-------------------------------------------------------------------------*/
+
+/* Hardware governed */
+#define MX_48M_SRC                      (0 << 3)
+#define MX_54M_SRC                      (0 << 5)
+#define MX_APLLS_CLIKIN_12              (3 << 23)
+#define MX_APLLS_CLIKIN_13              (2 << 23)
+#define MX_APLLS_CLIKIN_19_2            (0 << 23)
+
+/*
+ * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
+ * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
+ */
+#define M5A_DPLL_MULT_12                (133 << 12)
+#define M5A_DPLL_DIV_12                 (5 << 8)
+#define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
+                                        M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
+                                        MX_APLLS_CLIKIN_12
+#define M5A_DPLL_MULT_13                (61 << 12)
+#define M5A_DPLL_DIV_13                 (2 << 8)
+#define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
+                                        M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
+                                        MX_APLLS_CLIKIN_13
+#define M5A_DPLL_MULT_19                (55 << 12)
+#define M5A_DPLL_DIV_19                 (3 << 8)
+#define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
+                                        M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
+                                        MX_APLLS_CLIKIN_19_2
+/* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
+#define M5B_DPLL_MULT_12                (50 << 12)
+#define M5B_DPLL_DIV_12                 (2 << 8)
+#define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
+                                        M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
+                                        MX_APLLS_CLIKIN_12
+#define M5B_DPLL_MULT_13                (200 << 12)
+#define M5B_DPLL_DIV_13                 (12 << 8)
+
+#define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
+                                        M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
+                                        MX_APLLS_CLIKIN_13
+#define M5B_DPLL_MULT_19                (125 << 12)
+#define M5B_DPLL_DIV_19                 (31 << 8)
+#define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
+                                        M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
+                                        MX_APLLS_CLIKIN_19_2
+/*
+ * #4   (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
+ */
+#define M4_DPLL_MULT_12                 (133 << 12)
+#define M4_DPLL_DIV_12                  (3 << 8)
+#define M4_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
+                                        M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
+                                        MX_APLLS_CLIKIN_12
+
+#define M4_DPLL_MULT_13                 (399 << 12)
+#define M4_DPLL_DIV_13                  (12 << 8)
+#define M4_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
+                                        M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
+                                        MX_APLLS_CLIKIN_13
+
+#define M4_DPLL_MULT_19                 (145 << 12)
+#define M4_DPLL_DIV_19                  (6 << 8)
+#define M4_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
+                                        M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
+                                        MX_APLLS_CLIKIN_19_2
+
+/*
+ * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
+ */
+#define M3_DPLL_MULT_12                 (55 << 12)
+#define M3_DPLL_DIV_12                  (1 << 8)
+#define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
+                                        M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
+                                        MX_APLLS_CLIKIN_12
+#define M3_DPLL_MULT_13                 (76 << 12)
+#define M3_DPLL_DIV_13                  (2 << 8)
+#define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
+                                        M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
+                                        MX_APLLS_CLIKIN_13
+#define M3_DPLL_MULT_19                 (17 << 12)
+#define M3_DPLL_DIV_19                  (0 << 8)
+#define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
+                                        M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
+                                        MX_APLLS_CLIKIN_19_2
+
+/*
+ * #2   (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
+ */
+#define M2_DPLL_MULT_12                 (55 << 12)
+#define M2_DPLL_DIV_12                  (1 << 8)
+#define M2_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
+                                        M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
+                                        MX_APLLS_CLIKIN_12
+
+/* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
+ * relock time issue */
+/* Core frequency changed from 330/165 to 329/164 MHz*/
+#define M2_DPLL_MULT_13                 (76 << 12)
+#define M2_DPLL_DIV_13                  (2 << 8)
+#define M2_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
+                                        M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
+                                        MX_APLLS_CLIKIN_13
+
+#define M2_DPLL_MULT_19                 (17 << 12)
+#define M2_DPLL_DIV_19                  (0 << 8)
+#define M2_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
+                                        M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
+                                        MX_APLLS_CLIKIN_19_2
+
+/* boot (boot) */
+#define MB_DPLL_MULT                    (1 << 12)
+#define MB_DPLL_DIV                     (0 << 8)
+#define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
+                                        MB_DPLL_MULT | MX_APLLS_CLIKIN_12
+
+#define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
+                                        MB_DPLL_MULT | MX_APLLS_CLIKIN_13
+
+#define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
+                                        MB_DPLL_MULT | MX_APLLS_CLIKIN_19
+
+/*
+ * 2430 - chassis (sedna)
+ * 165 (ratio1) same as above #2
+ * 150 (ratio1)
+ * 133 (ratio2) same as above #4
+ * 110 (ratio2) same as above #3
+ * 104 (ratio2)
+ * boot (boot)
+ */
+
+/* PRCM I target DPLL = 2*330MHz = 660MHz */
+#define MI_DPLL_MULT_12                 (55 << 12)
+#define MI_DPLL_DIV_12                  (1 << 8)
+#define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
+                                        MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
+                                        MX_APLLS_CLIKIN_12
+
+/*
+ * 2420 Equivalent - mode registers
+ * PRCM II , target DPLL = 2*300MHz = 600MHz
+ */
+#define MII_DPLL_MULT_12                (50 << 12)
+#define MII_DPLL_DIV_12                 (1 << 8)
+#define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
+                                        MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
+                                        MX_APLLS_CLIKIN_12
+#define MII_DPLL_MULT_13                (300 << 12)
+#define MII_DPLL_DIV_13                 (12 << 8)
+#define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
+                                        MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
+                                        MX_APLLS_CLIKIN_13
+
+/* PRCM III target DPLL = 2*266 = 532MHz*/
+#define MIII_DPLL_MULT_12               (133 << 12)
+#define MIII_DPLL_DIV_12                (5 << 8)
+#define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
+                                        MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
+                                        MX_APLLS_CLIKIN_12
+#define MIII_DPLL_MULT_13               (266 << 12)
+#define MIII_DPLL_DIV_13                (12 << 8)
+#define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
+                                        MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
+                                        MX_APLLS_CLIKIN_13
+
+/* PRCM VII (boot bypass) */
+#define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
+#define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
+
+/* High and low operation value */
+#define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
+#define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
+
+/* MPU speed defines */
+#define S12M    12000000
+#define S13M    13000000
+#define S19M    19200000
+#define S26M    26000000
+#define S100M   100000000
+#define S133M   133000000
+#define S150M   150000000
+#define S164M   164000000
+#define S165M   165000000
+#define S199M   199000000
+#define S200M   200000000
+#define S266M   266000000
+#define S300M   300000000
+#define S329M   329000000
+#define S330M   330000000
+#define S399M   399000000
+#define S400M   400000000
+#define S532M   532000000
+#define S600M   600000000
+#define S658M   658000000
+#define S660M   660000000
+#define S798M   798000000
+
+/*-------------------------------------------------------------------------
+ * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
+ * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
+ * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
+ * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
+ *
+ * Filling in table based on H4 boards and 2430-SDPs variants available.
+ * There are quite a few more rates combinations which could be defined.
+ *
+ * When multiple values are defined the start up will try and choose the
+ * fastest one. If a 'fast' value is defined, then automatically, the /2
+ * one should be included as it can be used.    Generally having more that
+ * one fast set does not make sense, as static timings need to be changed
+ * to change the set.    The exception is the bypass setting which is
+ * availble for low power bypass.
+ *
+ * Note: This table needs to be sorted, fastest to slowest.
+ *-------------------------------------------------------------------------*/
+static struct prcm_config rate_table[] = {
+        /* PRCM I - FAST */
+        {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
+                RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
+                RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
+                RATE_IN_242X},
+
+        /* PRCM II - FAST */
+        {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
+                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
+                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
+                RATE_IN_242X},
+
+        {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
+                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
+                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
+                RATE_IN_242X},
+
+        /* PRCM III - FAST */
+        {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
+                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
+                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
+                RATE_IN_242X},
+
+        {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
+                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
+                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
+                RATE_IN_242X},
+
+        /* PRCM II - SLOW */
+        {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
+                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
+                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
+                RATE_IN_242X},
+
+        {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
+                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
+                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
+                RATE_IN_242X},
+
+        /* PRCM III - SLOW */
+        {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
+                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
+                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
+                RATE_IN_242X},
+
+        {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
+                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
+                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
+                RATE_IN_242X},
+
+        /* PRCM-VII (boot-bypass) */
+        {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
+                RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
+                RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
+                RATE_IN_242X},
+
+        /* PRCM-VII (boot-bypass) */
+        {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
+                RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
+                RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
+                RATE_IN_242X},
+
+        /* PRCM #4 - ratio2 (ES2.1) - FAST */
+        {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL,              /* 399MHz ARM */
+                R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
+                R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_133MHz,
+                RATE_IN_243X},
+
+        /* PRCM #2 - ratio1 (ES2) - FAST */
+        {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
+                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+                R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_165MHz,
+                RATE_IN_243X},
+
+        /* PRCM #5a - ratio1 - FAST */
+        {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
+                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+                R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_133MHz,
+                RATE_IN_243X},
+
+        /* PRCM #5b - ratio1 - FAST */
+        {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
+                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+                R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_100MHz,
+                RATE_IN_243X},
+
+        /* PRCM #4 - ratio1 (ES2.1) - SLOW */
+        {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
+                R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
+                R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_133MHz,
+                RATE_IN_243X},
+
+        /* PRCM #2 - ratio1 (ES2) - SLOW */
+        {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
+                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+                R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_165MHz,
+                RATE_IN_243X},
+
+        /* PRCM #5a - ratio1 - SLOW */
+        {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
+                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+                R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_133MHz,
+                RATE_IN_243X},
+
+        /* PRCM #5b - ratio1 - SLOW*/
+        {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
+                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+                R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_100MHz,
+                RATE_IN_243X},
+
+        /* PRCM-boot/bypass */
+        {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
+                RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
+                RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_BYPASS,
+                RATE_IN_243X},
+
+        /* PRCM-boot/bypass */
+        {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
+                RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
+                RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_BYPASS,
+                RATE_IN_243X},
+
+        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+};
+
+/*-------------------------------------------------------------------------
+ * 24xx clock tree.
+ *
+ * NOTE:In many cases here we are assigning a 'default' parent. In many
+ *      cases the parent is selectable. The get/set parent calls will also
+ *      switch sources.
+ *
+ *      Many some clocks say always_enabled, but they can be auto idled for
+ *      power savings. They will always be available upon clock request.
+ *
+ *      Several sources are given initial rates which may be wrong, this will
+ *      be fixed up in the init func.
+ *
+ *      Things are broadly separated below by clock domains. It is
+ *      noteworthy that most periferals have dependencies on multiple clock
+ *      domains. Many get their interface clocks from the L4 domain, but get
+ *      functional clocks from fixed sources or other core domain derived
+ *      clocks.
+ *-------------------------------------------------------------------------*/
+
+/* Base external input clocks */
+static struct clk func_32k_ck = {
+        .name           = "func_32k_ck",
+        .rate           = 32000,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
+        .recalc         = &propagate_rate,
+};
+
+/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
+static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
+        .name           = "osc_ck",
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_PROPAGATES,
+        .enable         = &omap2_enable_osc_ck,
+        .disable        = &omap2_disable_osc_ck,
+        .recalc         = &omap2_osc_clk_recalc,
+};
+
+/* With out modem likely 12MHz, with modem likely 13MHz */
+static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
+        .name           = "sys_ck",             /* ~ ref_clk also */
+        .parent         = &osc_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                ALWAYS_ENABLED | RATE_PROPAGATES,
+        .recalc         = &omap2_sys_clk_recalc,
+};
+
+static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
+        .name           = "alt_ck",
+        .rate           = 54000000,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
+        .recalc         = &propagate_rate,
+};
+
+/*
+ * Analog domain root source clocks
+ */
+
+/* dpll_ck, is broken out in to special cases through clksel */
+/* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
+ * deal with this
+ */
+
+static const struct dpll_data dpll_dd = {
+        .mult_div1_reg          = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
+        .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
+};
+
+static struct clk dpll_ck = {
+        .name           = "dpll_ck",
+        .parent         = &sys_ck,              /* Can be func_32k also */
+        .dpll_data      = &dpll_dd,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap2_dpll_recalc,
+        .set_rate       = &omap2_reprogram_dpll,
+};
+
+static struct clk apll96_ck = {
+        .name           = "apll96_ck",
+        .parent         = &sys_ck,
+        .rate           = 96000000,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
+        .enable         = &omap2_clk_fixed_enable,
+        .disable        = &omap2_clk_fixed_disable,
+        .recalc         = &propagate_rate,
+};
+
+static struct clk apll54_ck = {
+        .name           = "apll54_ck",
+        .parent         = &sys_ck,
+        .rate           = 54000000,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
+        .enable         = &omap2_clk_fixed_enable,
+        .disable        = &omap2_clk_fixed_disable,
+        .recalc         = &propagate_rate,
+};
+
+/*
+ * PRCM digital base sources
+ */
+
+/* func_54m_ck */
+
+static const struct clksel_rate func_54m_apll54_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel_rate func_54m_alt_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel func_54m_clksel[] = {
+        { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
+        { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
+        { .parent = NULL },
+};
+
+static struct clk func_54m_ck = {
+        .name           = "func_54m_ck",
+        .parent         = &apll54_ck,   /* can also be alt_clk */
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_54M_SOURCE,
+        .clksel         = func_54m_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk core_ck = {
+        .name           = "core_ck",
+        .parent         = &dpll_ck,             /* can also be 32k */
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                ALWAYS_ENABLED | RATE_PROPAGATES,
+        .recalc         = &followparent_recalc,
+};
+
+/* func_96m_ck */
+static const struct clksel_rate func_96m_apll96_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel_rate func_96m_alt_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel func_96m_clksel[] = {
+        { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
+        { .parent = &alt_ck,    .rates = func_96m_alt_rates },
+        { .parent = NULL }
+};
+
+/* The parent of this clock is not selectable on 2420. */
+static struct clk func_96m_ck = {
+        .name           = "func_96m_ck",
+        .parent         = &apll96_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP2430_96M_SOURCE,
+        .clksel         = func_96m_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+/* func_48m_ck */
+
+static const struct clksel_rate func_48m_apll96_rates[] = {
+        { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel_rate func_48m_alt_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel func_48m_clksel[] = {
+        { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
+        { .parent = &alt_ck, .rates = func_48m_alt_rates },
+        { .parent = NULL }
+};
+
+static struct clk func_48m_ck = {
+        .name           = "func_48m_ck",
+        .parent         = &apll96_ck,    /* 96M or Alt */
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_48M_SOURCE,
+        .clksel         = func_48m_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static struct clk func_12m_ck = {
+        .name           = "func_12m_ck",
+        .parent         = &func_48m_ck,
+        .fixed_div      = 4,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_fixed_divisor_recalc,
+};
+
+/* Secure timer, only available in secure mode */
+static struct clk wdt1_osc_ck = {
+        .name           = "ck_wdt1_osc",
+        .parent         = &osc_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .recalc         = &followparent_recalc,
+};
+
+/*
+ * The common_clkout* clksel_rate structs are common to
+ * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
+ * sys_clkout2_* are 2420-only, so the
+ * clksel_rate flags fields are inaccurate for those clocks. This is
+ * harmless since access to those clocks are gated by the struct clk
+ * flags fields, which mark them as 2420-only.
+ */
+static const struct clksel_rate common_clkout_src_core_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate common_clkout_src_sys_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate common_clkout_src_96m_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate common_clkout_src_54m_rates[] = {
+        { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel common_clkout_src_clksel[] = {
+        { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
+        { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
+        { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
+        { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
+        { .parent = NULL }
+};
+
+static struct clk sys_clkout_src = {
+        .name           = "sys_clkout_src",
+        .parent         = &func_54m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_PROPAGATES,
+        .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
+        .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
+        .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
+        .clksel         = common_clkout_src_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static const struct clksel_rate common_clkout_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 2, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 8, .val = 3, .flags = RATE_IN_24XX },
+        { .div = 16, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 0 },
+};
+
+static const struct clksel sys_clkout_clksel[] = {
+        { .parent = &sys_clkout_src, .rates = common_clkout_rates },
+        { .parent = NULL }
+};
+
+static struct clk sys_clkout = {
+        .name           = "sys_clkout",
+        .parent         = &sys_clkout_src,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                PARENT_CONTROLS_CLOCK,
+        .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
+        .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
+        .clksel         = sys_clkout_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+/* In 2430, new in 2420 ES2 */
+static struct clk sys_clkout2_src = {
+        .name           = "sys_clkout2_src",
+        .parent         = &func_54m_ck,
+        .flags          = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
+        .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
+        .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
+        .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
+        .clksel         = common_clkout_src_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static const struct clksel sys_clkout2_clksel[] = {
+        { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
+        { .parent = NULL }
+};
+
+/* In 2430, new in 2420 ES2 */
+static struct clk sys_clkout2 = {
+        .name           = "sys_clkout2",
+        .parent         = &sys_clkout2_src,
+        .flags          = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
+        .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
+        .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
+        .clksel         = sys_clkout2_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static struct clk emul_ck = {
+        .name           = "emul_ck",
+        .parent         = &func_54m_ck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP24XX_PRCM_CLKEMUL_CTRL,
+        .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
+        .recalc         = &followparent_recalc,
+
+};
+
+/*
+ * MPU clock domain
+ *      Clocks:
+ *              MPU_FCLK, MPU_ICLK
+ *              INT_M_FCLK, INT_M_I_CLK
+ *
+ * - Individual clocks are hardware managed.
+ * - Base divider comes from: CM_CLKSEL_MPU
+ *
+ */
+static const struct clksel_rate mpu_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_242X },
+        { .div = 6, .val = 6, .flags = RATE_IN_242X },
+        { .div = 8, .val = 8, .flags = RATE_IN_242X },
+        { .div = 0 },
+};
+
+static const struct clksel mpu_clksel[] = {
+        { .parent = &core_ck, .rates = mpu_core_rates },
+        { .parent = NULL }
+};
+
+static struct clk mpu_ck = {    /* Control cpu */
+        .name           = "mpu_ck",
+        .parent         = &core_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                ALWAYS_ENABLED | DELAYED_APP |
+                                CONFIG_PARTICIPANT | RATE_PROPAGATES,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
+        .clksel         = mpu_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+/*
+ * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
+ * Clocks:
+ *      2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
+ *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
+ *
+ * Won't be too specific here. The core clock comes into this block
+ * it is divided then tee'ed. One branch goes directly to xyz enable
+ * controls. The other branch gets further divided by 2 then possibly
+ * routed into a synchronizer and out of clocks abc.
+ */
+static const struct clksel_rate dsp_fck_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 6, .val = 6, .flags = RATE_IN_242X },
+        { .div = 8, .val = 8, .flags = RATE_IN_242X },
+        { .div = 12, .val = 12, .flags = RATE_IN_242X },
+        { .div = 0 },
+};
+
+static const struct clksel dsp_fck_clksel[] = {
+        { .parent = &core_ck, .rates = dsp_fck_core_rates },
+        { .parent = NULL }
+};
+
+static struct clk dsp_fck = {
+        .name           = "dsp_fck",
+        .parent         = &core_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
+                                CONFIG_PARTICIPANT | RATE_PROPAGATES,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
+        .clksel         = dsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+/* DSP interface clock */
+static const struct clksel_rate dsp_irate_ick_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 3, .val = 3, .flags = RATE_IN_243X },
+        { .div = 0 },
+};
+
+static const struct clksel dsp_irate_ick_clksel[] = {
+        { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
+        { .parent = NULL }
+};
+
+/*
+ * This clock does not exist as such in the TRM, but is added to
+ * separate source selection from  XXX
+ */
+static struct clk dsp_irate_ick = {
+        .name           = "dsp_irate_ick",
+        .parent         = &dsp_fck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
+                                CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
+        .clksel         = dsp_irate_ick_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate             = &omap2_clksel_set_rate
+};
+
+/* 2420 only */
+static struct clk dsp_ick = {
+        .name           = "dsp_ick",     /* apparently ipi and isp */
+        .parent         = &dsp_irate_ick,
+        .flags          = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,          /* for ipi */
+};
+
+/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
+static struct clk iva2_1_ick = {
+        .name           = "iva2_1_ick",
+        .parent         = &dsp_irate_ick,
+        .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
+};
+
+static struct clk iva1_ifck = {
+        .name           = "iva1_ifck",
+        .parent         = &core_ck,
+        .flags          = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
+                                RATE_PROPAGATES | DELAYED_APP,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
+        .clksel         = dsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+/* IVA1 mpu/int/i/f clocks are /2 of parent */
+static struct clk iva1_mpu_int_ifck = {
+        .name           = "iva1_mpu_int_ifck",
+        .parent         = &iva1_ifck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
+        .fixed_div      = 2,
+        .recalc         = &omap2_fixed_divisor_recalc,
+};
+
+/*
+ * L3 clock domain
+ * L3 clocks are used for both interface and functional clocks to
+ * multiple entities. Some of these clocks are completely managed
+ * by hardware, and some others allow software control. Hardware
+ * managed ones general are based on directly CLK_REQ signals and
+ * various auto idle settings. The functional spec sets many of these
+ * as 'tie-high' for their enables.
+ *
+ * I-CLOCKS:
+ *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
+ *      CAM, HS-USB.
+ * F-CLOCK
+ *      SSI.
+ *
+ * GPMC memories and SDRC have timing and clock sensitive registers which
+ * may very well need notification when the clock changes. Currently for low
+ * operating points, these are taken care of in sleep.S.
+ */
+static const struct clksel_rate core_l3_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_242X },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 6, .val = 6, .flags = RATE_IN_24XX },
+        { .div = 8, .val = 8, .flags = RATE_IN_242X },
+        { .div = 12, .val = 12, .flags = RATE_IN_242X },
+        { .div = 16, .val = 16, .flags = RATE_IN_242X },
+        { .div = 0 }
+};
+
+static const struct clksel core_l3_clksel[] = {
+        { .parent = &core_ck, .rates = core_l3_core_rates },
+        { .parent = NULL }
+};
+
+static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
+        .name           = "core_l3_ck",
+        .parent         = &core_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                ALWAYS_ENABLED | DELAYED_APP |
+                                CONFIG_PARTICIPANT | RATE_PROPAGATES,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
+        .clksel         = core_l3_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+/* usb_l4_ick */
+static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+
+static const struct clksel usb_l4_ick_clksel[] = {
+        { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
+        { .parent = NULL },
+};
+
+static struct clk usb_l4_ick = {        /* FS-USB interface clock */
+        .name           = "usb_l4_ick",
+        .parent         = &core_l3_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                DELAYED_APP | CONFIG_PARTICIPANT,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP24XX_EN_USB_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
+        .clksel         = usb_l4_ick_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+/*
+ * SSI is in L3 management domain, its direct parent is core not l3,
+ * many core power domain entities are grouped into the L3 clock
+ * domain.
+ * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
+ *
+ * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
+ */
+static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 5, .val = 5, .flags = RATE_IN_243X },
+        { .div = 6, .val = 6, .flags = RATE_IN_242X },
+        { .div = 8, .val = 8, .flags = RATE_IN_242X },
+        { .div = 0 }
+};
+
+static const struct clksel ssi_ssr_sst_fck_clksel[] = {
+        { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
+        { .parent = NULL }
+};
+
+static struct clk ssi_ssr_sst_fck = {
+        .name           = "ssi_fck",
+        .parent         = &core_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                DELAYED_APP,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
+        .clksel         = ssi_ssr_sst_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+/*
+ * GFX clock domain
+ *      Clocks:
+ * GFX_FCLK, GFX_ICLK
+ * GFX_CG1(2d), GFX_CG2(3d)
+ *
+ * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
+ * The 2d and 3d clocks run at a hardware determined
+ * divided value of fclk.
+ *
+ */
+/* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
+
+/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
+static const struct clksel gfx_fck_clksel[] = {
+        { .parent = &core_l3_ck, .rates = gfx_l3_rates },
+        { .parent = NULL },
+};
+
+static struct clk gfx_3d_fck = {
+        .name           = "gfx_3d_fck",
+        .parent         = &core_l3_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_EN_3D_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
+        .clksel         = gfx_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static struct clk gfx_2d_fck = {
+        .name           = "gfx_2d_fck",
+        .parent         = &core_l3_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_EN_2D_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
+        .clksel         = gfx_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static struct clk gfx_ick = {
+        .name           = "gfx_ick",            /* From l3 */
+        .parent         = &core_l3_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP_EN_GFX_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+/*
+ * Modem clock domain (2430)
+ *      CLOCKS:
+ *              MDM_OSC_CLK
+ *              MDM_ICLK
+ * These clocks are usable in chassis mode only.
+ */
+static const struct clksel_rate mdm_ick_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_243X },
+        { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
+        { .div = 6, .val = 6, .flags = RATE_IN_243X },
+        { .div = 9, .val = 9, .flags = RATE_IN_243X },
+        { .div = 0 }
+};
+
+static const struct clksel mdm_ick_clksel[] = {
+        { .parent = &core_ck, .rates = mdm_ick_core_rates },
+        { .parent = NULL }
+};
+
+static struct clk mdm_ick = {           /* used both as a ick and fck */
+        .name           = "mdm_ick",
+        .parent         = &core_ck,
+        .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP2430_CLKSEL_MDM_MASK,
+        .clksel         = mdm_ick_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static struct clk mdm_osc_ck = {
+        .name           = "mdm_osc_ck",
+        .parent         = &osc_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP2430_EN_OSC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+/*
+ * L4 clock management domain
+ *
+ * This domain contains lots of interface clocks from the L4 interface, some
+ * functional clocks.   Fixed APLL functional source clocks are managed in
+ * this domain.
+ */
+static const struct clksel_rate l4_core_l3_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+
+static const struct clksel l4_clksel[] = {
+        { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
+        { .parent = NULL }
+};
+
+static struct clk l4_ck = {             /* used both as an ick and fck */
+        .name           = "l4_ck",
+        .parent         = &core_l3_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
+        .clksel         = l4_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static struct clk ssi_l4_ick = {
+        .name           = "ssi_l4_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+/*
+ * DSS clock domain
+ * CLOCKs:
+ * DSS_L4_ICLK, DSS_L3_ICLK,
+ * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
+ *
+ * DSS is both initiator and target.
+ */
+/* XXX Add RATE_NOT_VALIDATED */
+
+static const struct clksel_rate dss1_fck_sys_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate dss1_fck_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 5, .val = 5, .flags = RATE_IN_24XX },
+        { .div = 6, .val = 6, .flags = RATE_IN_24XX },
+        { .div = 8, .val = 8, .flags = RATE_IN_24XX },
+        { .div = 9, .val = 9, .flags = RATE_IN_24XX },
+        { .div = 12, .val = 12, .flags = RATE_IN_24XX },
+        { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel dss1_fck_clksel[] = {
+        { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
+        { .parent = &core_ck, .rates = dss1_fck_core_rates },
+        { .parent = NULL },
+};
+
+static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
+        .name           = "dss_ick",
+        .parent         = &l4_ck,       /* really both l3 and l4 */
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss1_fck = {
+        .name           = "dss1_fck",
+        .parent         = &core_ck,             /* Core or sys */
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                DELAYED_APP,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
+        .clksel         = dss1_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static const struct clksel_rate dss2_fck_sys_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate dss2_fck_48m_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel dss2_fck_clksel[] = {
+        { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
+        { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
+        { .parent = NULL }
+};
+
+static struct clk dss2_fck = {          /* Alt clk used in power management */
+        .name           = "dss2_fck",
+        .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                DELAYED_APP,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
+        .clksel         = dss2_fck_clksel,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss_54m_fck = {       /* Alt clk used in power management */
+        .name           = "dss_54m_fck",        /* 54m tv clk */
+        .parent         = &func_54m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_TV_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+/*
+ * CORE power domain ICLK & FCLK defines.
+ * Many of the these can have more than one possible parent. Entries
+ * here will likely have an L4 interface parent, and may have multiple
+ * functional clock parents.
+ */
+static const struct clksel_rate gpt_alt_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel omap24xx_gpt_clksel[] = {
+        { .parent = &func_32k_ck, .rates = gpt_32k_rates },
+        { .parent = &sys_ck,      .rates = gpt_sys_rates },
+        { .parent = &alt_ck,      .rates = gpt_alt_rates },
+        { .parent = NULL },
+};
+
+static struct clk gpt1_ick = {
+        .name           = "gpt1_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt1_fck = {
+        .name           = "gpt1_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static struct clk gpt2_ick = {
+        .name           = "gpt2_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt2_fck = {
+        .name           = "gpt2_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt3_ick = {
+        .name           = "gpt3_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt3_fck = {
+        .name           = "gpt3_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt4_ick = {
+        .name           = "gpt4_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt4_fck = {
+        .name           = "gpt4_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt5_ick = {
+        .name           = "gpt5_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt5_fck = {
+        .name           = "gpt5_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt6_ick = {
+        .name           = "gpt6_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt6_fck = {
+        .name           = "gpt6_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt7_ick = {
+        .name           = "gpt7_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt7_fck = {
+        .name           = "gpt7_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt8_ick = {
+        .name           = "gpt8_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt8_fck = {
+        .name           = "gpt8_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt9_ick = {
+        .name           = "gpt9_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt9_fck = {
+        .name           = "gpt9_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt10_ick = {
+        .name           = "gpt10_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt10_fck = {
+        .name           = "gpt10_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt11_ick = {
+        .name           = "gpt11_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt11_fck = {
+        .name           = "gpt11_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt12_ick = {
+        .name           = "gpt12_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt12_fck = {
+        .name           = "gpt12_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk mcbsp1_ick = {
+        .name           = "mcbsp1_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp1_fck = {
+        .name           = "mcbsp1_fck",
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp2_ick = {
+        .name           = "mcbsp2_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp2_fck = {
+        .name           = "mcbsp2_fck",
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp3_ick = {
+        .name           = "mcbsp3_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp3_fck = {
+        .name           = "mcbsp3_fck",
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp4_ick = {
+        .name           = "mcbsp4_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp4_fck = {
+        .name           = "mcbsp4_fck",
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp5_ick = {
+        .name           = "mcbsp5_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp5_fck = {
+        .name           = "mcbsp5_fck",
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi1_ick = {
+        .name           = "mcspi_ick",
+        .id             = 1,
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi1_fck = {
+        .name           = "mcspi_fck",
+        .id             = 1,
+        .parent         = &func_48m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi2_ick = {
+        .name           = "mcspi_ick",
+        .id             = 2,
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi2_fck = {
+        .name           = "mcspi_fck",
+        .id             = 2,
+        .parent         = &func_48m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi3_ick = {
+        .name           = "mcspi_ick",
+        .id             = 3,
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi3_fck = {
+        .name           = "mcspi_fck",
+        .id             = 3,
+        .parent         = &func_48m_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart1_ick = {
+        .name           = "uart1_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart1_fck = {
+        .name           = "uart1_fck",
+        .parent         = &func_48m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart2_ick = {
+        .name           = "uart2_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart2_fck = {
+        .name           = "uart2_fck",
+        .parent         = &func_48m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart3_ick = {
+        .name           = "uart3_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart3_fck = {
+        .name           = "uart3_fck",
+        .parent         = &func_48m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpios_ick = {
+        .name           = "gpios_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpios_fck = {
+        .name           = "gpios_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mpu_wdt_ick = {
+        .name           = "mpu_wdt_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mpu_wdt_fck = {
+        .name           = "mpu_wdt_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sync_32k_ick = {
+        .name           = "sync_32k_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk wdt1_ick = {
+        .name           = "wdt1_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk omapctrl_ick = {
+        .name           = "omapctrl_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk icr_ick = {
+        .name           = "icr_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP2430_EN_ICR_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk cam_ick = {
+        .name           = "cam_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk cam_fck = {
+        .name           = "cam_fck",
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mailboxes_ick = {
+        .name           = "mailboxes_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt4_ick = {
+        .name           = "wdt4_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt4_fck = {
+        .name           = "wdt4_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt3_ick = {
+        .name           = "wdt3_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt3_fck = {
+        .name           = "wdt3_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mspro_ick = {
+        .name           = "mspro_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mspro_fck = {
+        .name           = "mspro_fck",
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmc_ick = {
+        .name           = "mmc_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_MMC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmc_fck = {
+        .name           = "mmc_fck",
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP2420_EN_MMC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk fac_ick = {
+        .name           = "fac_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk fac_fck = {
+        .name           = "fac_fck",
+        .parent         = &func_12m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk eac_ick = {
+        .name           = "eac_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_EAC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk eac_fck = {
+        .name           = "eac_fck",
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP2420_EN_EAC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk hdq_ick = {
+        .name           = "hdq_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk hdq_fck = {
+        .name           = "hdq_fck",
+        .parent         = &func_12m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c2_ick = {
+        .name           = "i2c_ick",
+        .id             = 2,
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c2_fck = {
+        .name           = "i2c_fck",
+        .id             = 2,
+        .parent         = &func_12m_ck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2chs2_fck = {
+        .name           = "i2chs_fck",
+        .id             = 2,
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c1_ick = {
+        .name           = "i2c_ick",
+        .id             = 1,
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c1_fck = {
+        .name           = "i2c_fck",
+        .id             = 1,
+        .parent         = &func_12m_ck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2chs1_fck = {
+        .name           = "i2chs_fck",
+        .id             = 1,
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpmc_fck = {
+        .name           = "gpmc_fck",
+        .parent         = &core_l3_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sdma_fck = {
+        .name           = "sdma_fck",
+        .parent         = &core_l3_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sdma_ick = {
+        .name           = "sdma_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk vlynq_ick = {
+        .name           = "vlynq_ick",
+        .parent         = &core_l3_ck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static const struct clksel_rate vlynq_fck_96m_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate vlynq_fck_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_242X },
+        { .div = 2, .val = 2, .flags = RATE_IN_242X },
+        { .div = 3, .val = 3, .flags = RATE_IN_242X },
+        { .div = 4, .val = 4, .flags = RATE_IN_242X },
+        { .div = 6, .val = 6, .flags = RATE_IN_242X },
+        { .div = 8, .val = 8, .flags = RATE_IN_242X },
+        { .div = 9, .val = 9, .flags = RATE_IN_242X },
+        { .div = 12, .val = 12, .flags = RATE_IN_242X },
+        { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
+        { .div = 18, .val = 18, .flags = RATE_IN_242X },
+        { .div = 0 }
+};
+
+static const struct clksel vlynq_fck_clksel[] = {
+        { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
+        { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
+        { .parent = NULL }
+};
+
+static struct clk vlynq_fck = {
+        .name           = "vlynq_fck",
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP242X | DELAYED_APP,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
+        .clksel         = vlynq_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static struct clk sdrc_ick = {
+        .name           = "sdrc_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk des_ick = {
+        .name           = "des_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_DES_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sha_ick = {
+        .name           = "sha_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk rng_ick = {
+        .name           = "rng_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk aes_ick = {
+        .name           = "aes_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_AES_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk pka_ick = {
+        .name           = "pka_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usb_fck = {
+        .name           = "usb_fck",
+        .parent         = &func_48m_ck,
+        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP24XX_EN_USB_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usbhs_ick = {
+        .name           = "usbhs_ick",
+        .parent         = &core_l3_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs1_ick = {
+        .name           = "mmchs_ick",
+        .id             = 1,
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs1_fck = {
+        .name           = "mmchs_fck",
+        .id             = 1,
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs2_ick = {
+        .name           = "mmchs_ick",
+        .id             = 2,
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs2_fck = {
+        .name           = "mmchs_fck",
+        .id             = 2,
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio5_ick = {
+        .name           = "gpio5_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio5_fck = {
+        .name           = "gpio5_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mdm_intc_ick = {
+        .name           = "mdm_intc_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchsdb1_fck = {
+        .name           = "mmchsdb_fck",
+        .id             = 1,
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchsdb2_fck = {
+        .name           = "mmchsdb_fck",
+        .id             = 2,
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+/*
+ * This clock is a composite clock which does entire set changes then
+ * forces a rebalance. It keys on the MPU speed, but it really could
+ * be any key speed part of a set in the rate table.
+ *
+ * to really change a set, you need memory table sets which get changed
+ * in sram, pre-notifiers & post notifiers, changing the top set, without
+ * having low level display recalc's won't work... this is why dpm notifiers
+ * work, isr's off, walk a list of clocks already _off_ and not messing with
+ * the bus.
+ *
+ * This clock should have no parent. It embodies the entire upper level
+ * active set. A parent will mess up some of the init also.
+ */
+static struct clk virt_prcm_set = {
+        .name           = "virt_prcm_set",
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
+        .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
+        .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
+        .set_rate       = &omap2_select_table_rate,
+        .round_rate     = &omap2_round_to_table_rate,
+};
+
+static struct clk *onchip_24xx_clks[] __initdata = {
+        /* external root sources */
+        &func_32k_ck,
+        &osc_ck,
+        &sys_ck,
+        &alt_ck,
+        /* internal analog sources */
+        &dpll_ck,
+        &apll96_ck,
+        &apll54_ck,
+        /* internal prcm root sources */
+        &func_54m_ck,
+        &core_ck,
+        &func_96m_ck,
+        &func_48m_ck,
+        &func_12m_ck,
+        &wdt1_osc_ck,
+        &sys_clkout_src,
+        &sys_clkout,
+        &sys_clkout2_src,
+        &sys_clkout2,
+        &emul_ck,
+        /* mpu domain clocks */
+        &mpu_ck,
+        /* dsp domain clocks */
+        &dsp_fck,
+        &dsp_irate_ick,
+        &dsp_ick,               /* 242x */
+        &iva2_1_ick,            /* 243x */
+        &iva1_ifck,             /* 242x */
+        &iva1_mpu_int_ifck,     /* 242x */
+        /* GFX domain clocks */
+        &gfx_3d_fck,
+        &gfx_2d_fck,
+        &gfx_ick,
+        /* Modem domain clocks */
+        &mdm_ick,
+        &mdm_osc_ck,
+        /* DSS domain clocks */
+        &dss_ick,
+        &dss1_fck,
+        &dss2_fck,
+        &dss_54m_fck,
+        /* L3 domain clocks */
+        &core_l3_ck,
+        &ssi_ssr_sst_fck,
+        &usb_l4_ick,
+        /* L4 domain clocks */
+        &l4_ck,                 /* used as both core_l4 and wu_l4 */
+        &ssi_l4_ick,
+        /* virtual meta-group clock */
+        &virt_prcm_set,
+        /* general l4 interface ck, multi-parent functional clk */
+        &gpt1_ick,
+        &gpt1_fck,
+        &gpt2_ick,
+        &gpt2_fck,
+        &gpt3_ick,
+        &gpt3_fck,
+        &gpt4_ick,
+        &gpt4_fck,
+        &gpt5_ick,
+        &gpt5_fck,
+        &gpt6_ick,
+        &gpt6_fck,
+        &gpt7_ick,
+        &gpt7_fck,
+        &gpt8_ick,
+        &gpt8_fck,
+        &gpt9_ick,
+        &gpt9_fck,
+        &gpt10_ick,
+        &gpt10_fck,
+        &gpt11_ick,
+        &gpt11_fck,
+        &gpt12_ick,
+        &gpt12_fck,
+        &mcbsp1_ick,
+        &mcbsp1_fck,
+        &mcbsp2_ick,
+        &mcbsp2_fck,
+        &mcbsp3_ick,
+        &mcbsp3_fck,
+        &mcbsp4_ick,
+        &mcbsp4_fck,
+        &mcbsp5_ick,
+        &mcbsp5_fck,
+        &mcspi1_ick,
+        &mcspi1_fck,
+        &mcspi2_ick,
+        &mcspi2_fck,
+        &mcspi3_ick,
+        &mcspi3_fck,
+        &uart1_ick,
+        &uart1_fck,
+        &uart2_ick,
+        &uart2_fck,
+        &uart3_ick,
+        &uart3_fck,
+        &gpios_ick,
+        &gpios_fck,
+        &mpu_wdt_ick,
+        &mpu_wdt_fck,
+        &sync_32k_ick,
+        &wdt1_ick,
+        &omapctrl_ick,
+        &icr_ick,
+        &cam_fck,
+        &cam_ick,
+        &mailboxes_ick,
+        &wdt4_ick,
+        &wdt4_fck,
+        &wdt3_ick,
+        &wdt3_fck,
+        &mspro_ick,
+        &mspro_fck,
+        &mmc_ick,
+        &mmc_fck,
+        &fac_ick,
+        &fac_fck,
+        &eac_ick,
+        &eac_fck,
+        &hdq_ick,
+        &hdq_fck,
+        &i2c1_ick,
+        &i2c1_fck,
+        &i2chs1_fck,
+        &i2c2_ick,
+        &i2c2_fck,
+        &i2chs2_fck,
+        &gpmc_fck,
+        &sdma_fck,
+        &sdma_ick,
+        &vlynq_ick,
+        &vlynq_fck,
+        &sdrc_ick,
+        &des_ick,
+        &sha_ick,
+        &rng_ick,
+        &aes_ick,
+        &pka_ick,
+        &usb_fck,
+        &usbhs_ick,
+        &mmchs1_ick,
+        &mmchs1_fck,
+        &mmchs2_ick,
+        &mmchs2_fck,
+        &gpio5_ick,
+        &gpio5_fck,
+        &mdm_intc_ick,
+        &mmchsdb1_fck,
+        &mmchsdb2_fck,
+};
+
+#endif
+
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
new file mode 100644
index 000000000000..b42bdd6079a5
--- /dev/null
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -0,0 +1,235 @@
+/*
+ * OMAP3-specific clock framework functions
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * Parts of this code are based on code written by
+ * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/sram.h>
+#include <asm/div64.h>
+#include <asm/bitops.h>
+
+#include "memory.h"
+#include "clock.h"
+#include "clock34xx.h"
+#include "prm.h"
+#include "prm-regbits-34xx.h"
+#include "cm.h"
+#include "cm-regbits-34xx.h"
+
+/* CM_CLKEN_PLL*.EN* bit values */
+#define DPLL_LOCKED             0x7
+
+/**
+ * omap3_dpll_recalc - recalculate DPLL rate
+ * @clk: DPLL struct clk
+ *
+ * Recalculate and propagate the DPLL rate.
+ */
+static void omap3_dpll_recalc(struct clk *clk)
+{
+        clk->rate = omap2_get_dpll_rate(clk);
+
+        propagate_rate(clk);
+}
+
+/**
+ * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
+ * @clk: DPLL output struct clk
+ *
+ * Using parent clock DPLL data, look up DPLL state.  If locked, set our
+ * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
+ */
+static void omap3_clkoutx2_recalc(struct clk *clk)
+{
+        const struct dpll_data *dd;
+        u32 v;
+        struct clk *pclk;
+
+        /* Walk up the parents of clk, looking for a DPLL */
+        pclk = clk->parent;
+        while (pclk && !pclk->dpll_data)
+                pclk = pclk->parent;
+
+        /* clk does not have a DPLL as a parent? */
+        WARN_ON(!pclk);
+
+        dd = pclk->dpll_data;
+
+        WARN_ON(!dd->control_reg || !dd->enable_mask);
+
+        v = __raw_readl(dd->control_reg) & dd->enable_mask;
+        v >>= __ffs(dd->enable_mask);
+        if (v != DPLL_LOCKED)
+                clk->rate = clk->parent->rate;
+        else
+                clk->rate = clk->parent->rate * 2;
+
+        if (clk->flags & RATE_PROPAGATES)
+                propagate_rate(clk);
+}
+
+/*
+ * As it is structured now, this will prevent an OMAP2/3 multiboot
+ * kernel from compiling.  This will need further attention.
+ */
+#if defined(CONFIG_ARCH_OMAP3)
+
+static struct clk_functions omap2_clk_functions = {
+        .clk_enable             = omap2_clk_enable,
+        .clk_disable            = omap2_clk_disable,
+        .clk_round_rate         = omap2_clk_round_rate,
+        .clk_set_rate           = omap2_clk_set_rate,
+        .clk_set_parent         = omap2_clk_set_parent,
+        .clk_disable_unused     = omap2_clk_disable_unused,
+};
+
+/*
+ * Set clocks for bypass mode for reboot to work.
+ */
+void omap2_clk_prepare_for_reboot(void)
+{
+        /* REVISIT: Not ready for 343x */
+#if 0
+        u32 rate;
+
+        if (vclk == NULL || sclk == NULL)
+                return;
+
+        rate = clk_get_rate(sclk);
+        clk_set_rate(vclk, rate);
+#endif
+}
+
+/* REVISIT: Move this init stuff out into clock.c */
+
+/*
+ * Switch the MPU rate if specified on cmdline.
+ * We cannot do this early until cmdline is parsed.
+ */
+static int __init omap2_clk_arch_init(void)
+{
+        if (!mpurate)
+                return -EINVAL;
+
+        /* REVISIT: not yet ready for 343x */
+#if 0
+        if (omap2_select_table_rate(&virt_prcm_set, mpurate))
+                printk(KERN_ERR "Could not find matching MPU rate\n");
+#endif
+
+        recalculate_root_clocks();
+
+        printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL3/MPU): "
+               "%ld.%01ld/%ld/%ld MHz\n",
+               (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
+               (core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ;
+
+        return 0;
+}
+arch_initcall(omap2_clk_arch_init);
+
+int __init omap2_clk_init(void)
+{
+        /* struct prcm_config *prcm; */
+        struct clk **clkp;
+        /* u32 clkrate; */
+        u32 cpu_clkflg;
+
+        /* REVISIT: Ultimately this will be used for multiboot */
+#if 0
+        if (cpu_is_omap242x()) {
+                cpu_mask = RATE_IN_242X;
+                cpu_clkflg = CLOCK_IN_OMAP242X;
+                clkp = onchip_24xx_clks;
+        } else if (cpu_is_omap2430()) {
+                cpu_mask = RATE_IN_243X;
+                cpu_clkflg = CLOCK_IN_OMAP243X;
+                clkp = onchip_24xx_clks;
+        }
+#endif
+        if (cpu_is_omap34xx()) {
+                cpu_mask = RATE_IN_343X;
+                cpu_clkflg = CLOCK_IN_OMAP343X;
+                clkp = onchip_34xx_clks;
+
+                /*
+                 * Update this if there are further clock changes between ES2
+                 * and production parts
+                 */
+                if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0)) {
+                        /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
+                        cpu_clkflg |= CLOCK_IN_OMAP3430ES1;
+                } else {
+                        cpu_mask |= RATE_IN_3430ES2;
+                        cpu_clkflg |= CLOCK_IN_OMAP3430ES2;
+                }
+        }
+
+        clk_init(&omap2_clk_functions);
+
+        for (clkp = onchip_34xx_clks;
+             clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks);
+             clkp++) {
+                if ((*clkp)->flags & cpu_clkflg)
+                        clk_register(*clkp);
+        }
+
+        /* REVISIT: Not yet ready for OMAP3 */
+#if 0
+        /* Check the MPU rate set by bootloader */
+        clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
+        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+                if (!(prcm->flags & cpu_mask))
+                        continue;
+                if (prcm->xtal_speed != sys_ck.rate)
+                        continue;
+                if (prcm->dpll_speed <= clkrate)
+                         break;
+        }
+        curr_prcm_set = prcm;
+#endif
+
+        recalculate_root_clocks();
+
+        printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): "
+               "%ld.%01ld/%ld/%ld MHz\n",
+               (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
+               (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
+
+        /*
+         * Only enable those clocks we will need, let the drivers
+         * enable other clocks as necessary
+         */
+        clk_enable_init_clocks();
+
+        /* Avoid sleeping during omap2_clk_prepare_for_reboot() */
+        /* REVISIT: not yet ready for 343x */
+#if 0
+        vclk = clk_get(NULL, "virt_prcm_set");
+        sclk = clk_get(NULL, "sys_ck");
+#endif
+        return 0;
+}
+
+#endif
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
new file mode 100644
index 000000000000..cf4644a94b9b
--- /dev/null
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -0,0 +1,3009 @@
+/*
+ * OMAP3 clock framework
+ *
+ * Virtual clocks are introduced as a convenient tools.
+ * They are sources for other clocks and not supposed
+ * to be requested from drivers directly.
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
+#define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
+
+#include <asm/arch/control.h>
+
+#include "clock.h"
+#include "cm.h"
+#include "cm-regbits-34xx.h"
+#include "prm.h"
+#include "prm-regbits-34xx.h"
+
+static void omap3_dpll_recalc(struct clk *clk);
+static void omap3_clkoutx2_recalc(struct clk *clk);
+
+/*
+ * DPLL1 supplies clock to the MPU.
+ * DPLL2 supplies clock to the IVA2.
+ * DPLL3 supplies CORE domain clocks.
+ * DPLL4 supplies peripheral clocks.
+ * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
+ */
+
+/* PRM CLOCKS */
+
+/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
+static struct clk omap_32k_fck = {
+        .name           = "omap_32k_fck",
+        .rate           = 32768,
+        .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+                                ALWAYS_ENABLED,
+        .recalc         = &propagate_rate,
+};
+
+static struct clk secure_32k_fck = {
+        .name           = "secure_32k_fck",
+        .rate           = 32768,
+        .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+                                ALWAYS_ENABLED,
+        .recalc         = &propagate_rate,
+};
+
+/* Virtual source clocks for osc_sys_ck */
+static struct clk virt_12m_ck = {
+        .name           = "virt_12m_ck",
+        .rate           = 12000000,
+        .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+                                ALWAYS_ENABLED,
+        .recalc         = &propagate_rate,
+};
+
+static struct clk virt_13m_ck = {
+        .name           = "virt_13m_ck",
+        .rate           = 13000000,
+        .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+                                ALWAYS_ENABLED,
+        .recalc         = &propagate_rate,
+};
+
+static struct clk virt_16_8m_ck = {
+        .name           = "virt_16_8m_ck",
+        .rate           = 16800000,
+        .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
+                                ALWAYS_ENABLED,
+        .recalc         = &propagate_rate,
+};
+
+static struct clk virt_19_2m_ck = {
+        .name           = "virt_19_2m_ck",
+        .rate           = 19200000,
+        .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+                                ALWAYS_ENABLED,
+        .recalc         = &propagate_rate,
+};
+
+static struct clk virt_26m_ck = {
+        .name           = "virt_26m_ck",
+        .rate           = 26000000,
+        .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+                                ALWAYS_ENABLED,
+        .recalc         = &propagate_rate,
+};
+
+static struct clk virt_38_4m_ck = {
+        .name           = "virt_38_4m_ck",
+        .rate           = 38400000,
+        .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+                                ALWAYS_ENABLED,
+        .recalc         = &propagate_rate,
+};
+
+static const struct clksel_rate osc_sys_12m_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate osc_sys_13m_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate osc_sys_16_8m_rates[] = {
+        { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate osc_sys_19_2m_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate osc_sys_26m_rates[] = {
+        { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate osc_sys_38_4m_rates[] = {
+        { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel osc_sys_clksel[] = {
+        { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
+        { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
+        { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
+        { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
+        { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
+        { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
+        { .parent = NULL },
+};
+
+/* Oscillator clock */
+/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
+static struct clk osc_sys_ck = {
+        .name           = "osc_sys_ck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP3430_PRM_CLKSEL,
+        .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
+        .clksel         = osc_sys_clksel,
+        /* REVISIT: deal with autoextclkmode? */
+        .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+                                ALWAYS_ENABLED,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate div2_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 0 }
+};
+
+static const struct clksel sys_clksel[] = {
+        { .parent = &osc_sys_ck, .rates = div2_rates },
+        { .parent = NULL }
+};
+
+/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
+/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
+static struct clk sys_ck = {
+        .name           = "sys_ck",
+        .parent         = &osc_sys_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
+        .clksel_mask    = OMAP_SYSCLKDIV_MASK,
+        .clksel         = sys_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk sys_altclk = {
+        .name           = "sys_altclk",
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &propagate_rate,
+};
+
+/* Optional external clock input for some McBSPs */
+static struct clk mcbsp_clks = {
+        .name           = "mcbsp_clks",
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &propagate_rate,
+};
+
+/* PRM EXTERNAL CLOCK OUTPUT */
+
+static struct clk sys_clkout1 = {
+        .name           = "sys_clkout1",
+        .parent         = &osc_sys_ck,
+        .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
+        .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+/* DPLLS */
+
+/* CM CLOCKS */
+
+static const struct clksel_rate dpll_bypass_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate dpll_locked_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate div16_dpll_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 3, .val = 3, .flags = RATE_IN_343X },
+        { .div = 4, .val = 4, .flags = RATE_IN_343X },
+        { .div = 5, .val = 5, .flags = RATE_IN_343X },
+        { .div = 6, .val = 6, .flags = RATE_IN_343X },
+        { .div = 7, .val = 7, .flags = RATE_IN_343X },
+        { .div = 8, .val = 8, .flags = RATE_IN_343X },
+        { .div = 9, .val = 9, .flags = RATE_IN_343X },
+        { .div = 10, .val = 10, .flags = RATE_IN_343X },
+        { .div = 11, .val = 11, .flags = RATE_IN_343X },
+        { .div = 12, .val = 12, .flags = RATE_IN_343X },
+        { .div = 13, .val = 13, .flags = RATE_IN_343X },
+        { .div = 14, .val = 14, .flags = RATE_IN_343X },
+        { .div = 15, .val = 15, .flags = RATE_IN_343X },
+        { .div = 16, .val = 16, .flags = RATE_IN_343X },
+        { .div = 0 }
+};
+
+/* DPLL1 */
+/* MPU clock source */
+/* Type: DPLL */
+static const struct dpll_data dpll1_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
+        .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
+        .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
+        .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
+        .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
+};
+
+static struct clk dpll1_ck = {
+        .name           = "dpll1_ck",
+        .parent         = &sys_ck,
+        .dpll_data      = &dpll1_dd,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap3_dpll_recalc,
+};
+
+/*
+ * This virtual clock provides the CLKOUTX2 output from the DPLL if the
+ * DPLL isn't bypassed.
+ */
+static struct clk dpll1_x2_ck = {
+        .name           = "dpll1_x2_ck",
+        .parent         = &dpll1_ck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
+static const struct clksel div16_dpll1_x2m2_clksel[] = {
+        { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
+        { .parent = NULL }
+};
+
+/*
+ * Does not exist in the TRM - needed to separate the M2 divider from
+ * bypass selection in mpu_ck
+ */
+static struct clk dpll1_x2m2_ck = {
+        .name           = "dpll1_x2m2_ck",
+        .parent         = &dpll1_x2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
+        .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
+        .clksel         = div16_dpll1_x2m2_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* DPLL2 */
+/* IVA2 clock source */
+/* Type: DPLL */
+
+static const struct dpll_data dpll2_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
+        .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
+        .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
+        .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
+        .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
+};
+
+static struct clk dpll2_ck = {
+        .name           = "dpll2_ck",
+        .parent         = &sys_ck,
+        .dpll_data      = &dpll2_dd,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap3_dpll_recalc,
+};
+
+static const struct clksel div16_dpll2_m2x2_clksel[] = {
+        { .parent = &dpll2_ck, .rates = div16_dpll_rates },
+        { .parent = NULL }
+};
+
+/*
+ * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
+ * or CLKOUTX2. CLKOUT seems most plausible.
+ */
+static struct clk dpll2_m2_ck = {
+        .name           = "dpll2_m2_ck",
+        .parent         = &dpll2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
+                                          OMAP3430_CM_CLKSEL2_PLL),
+        .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
+        .clksel         = div16_dpll2_m2x2_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* DPLL3 */
+/* Source clock for all interfaces and for some device fclks */
+/* Type: DPLL */
+static const struct dpll_data dpll3_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
+        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
+        .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
+};
+
+static struct clk dpll3_ck = {
+        .name           = "dpll3_ck",
+        .parent         = &sys_ck,
+        .dpll_data      = &dpll3_dd,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap3_dpll_recalc,
+};
+
+/*
+ * This virtual clock provides the CLKOUTX2 output from the DPLL if the
+ * DPLL isn't bypassed
+ */
+static struct clk dpll3_x2_ck = {
+        .name           = "dpll3_x2_ck",
+        .parent         = &dpll3_ck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel_rate div31_dpll3_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
+        { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
+        { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
+        { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
+        { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
+        { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
+        { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
+        { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
+        { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
+        { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
+        { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
+        { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
+        { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
+        { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
+        { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
+        { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
+        { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
+        { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
+        { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
+        { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
+        { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
+        { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
+        { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
+        { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
+        { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
+        { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
+        { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
+        { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
+        { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
+        { .div = 0 },
+};
+
+static const struct clksel div31_dpll3m2_clksel[] = {
+        { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
+        { .parent = NULL }
+};
+
+/*
+ * DPLL3 output M2
+ * REVISIT: This DPLL output divider must be changed in SRAM, so until
+ * that code is ready, this should remain a 'read-only' clksel clock.
+ */
+static struct clk dpll3_m2_ck = {
+        .name           = "dpll3_m2_ck",
+        .parent         = &dpll3_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
+        .clksel         = div31_dpll3m2_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel core_ck_clksel[] = {
+        { .parent = &sys_ck,      .rates = dpll_bypass_rates },
+        { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk core_ck = {
+        .name           = "core_ck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .clksel_mask    = OMAP3430_ST_CORE_CLK,
+        .clksel         = core_ck_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel dpll3_m2x2_ck_clksel[] = {
+        { .parent = &sys_ck,      .rates = dpll_bypass_rates },
+        { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk dpll3_m2x2_ck = {
+        .name           = "dpll3_m2x2_ck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .clksel_mask    = OMAP3430_ST_CORE_CLK,
+        .clksel         = dpll3_m2x2_ck_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static const struct clksel div16_dpll3_clksel[] = {
+        { .parent = &dpll3_ck, .rates = div16_dpll_rates },
+        { .parent = NULL }
+};
+
+/* This virtual clock is the source for dpll3_m3x2_ck */
+static struct clk dpll3_m3_ck = {
+        .name           = "dpll3_m3_ck",
+        .parent         = &dpll3_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
+        .clksel         = div16_dpll3_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll3_m3x2_ck = {
+        .name           = "dpll3_m3x2_ck",
+        .parent         = &dpll3_m3_ck,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel emu_core_alwon_ck_clksel[] = {
+        { .parent = &sys_ck,        .rates = dpll_bypass_rates },
+        { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk emu_core_alwon_ck = {
+        .name           = "emu_core_alwon_ck",
+        .parent         = &dpll3_m3x2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .clksel_mask    = OMAP3430_ST_CORE_CLK,
+        .clksel         = emu_core_alwon_ck_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* DPLL4 */
+/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
+/* Type: DPLL */
+static const struct dpll_data dpll4_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
+        .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
+        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
+        .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
+};
+
+static struct clk dpll4_ck = {
+        .name           = "dpll4_ck",
+        .parent         = &sys_ck,
+        .dpll_data      = &dpll4_dd,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap3_dpll_recalc,
+};
+
+/*
+ * This virtual clock provides the CLKOUTX2 output from the DPLL if the
+ * DPLL isn't bypassed --
+ * XXX does this serve any downstream clocks?
+ */
+static struct clk dpll4_x2_ck = {
+        .name           = "dpll4_x2_ck",
+        .parent         = &dpll4_ck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel div16_dpll4_clksel[] = {
+        { .parent = &dpll4_ck, .rates = div16_dpll_rates },
+        { .parent = NULL }
+};
+
+/* This virtual clock is the source for dpll4_m2x2_ck */
+static struct clk dpll4_m2_ck = {
+        .name           = "dpll4_m2_ck",
+        .parent         = &dpll4_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
+        .clksel_mask    = OMAP3430_DIV_96M_MASK,
+        .clksel         = div16_dpll4_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m2x2_ck = {
+        .name           = "dpll4_m2x2_ck",
+        .parent         = &dpll4_m2_ck,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel omap_96m_alwon_fck_clksel[] = {
+        { .parent = &sys_ck,        .rates = dpll_bypass_rates },
+        { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk omap_96m_alwon_fck = {
+        .name           = "omap_96m_alwon_fck",
+        .parent         = &dpll4_m2x2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
+        .clksel         = omap_96m_alwon_fck_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                 PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk omap_96m_fck = {
+        .name           = "omap_96m_fck",
+        .parent         = &omap_96m_alwon_fck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static const struct clksel cm_96m_fck_clksel[] = {
+        { .parent = &sys_ck,        .rates = dpll_bypass_rates },
+        { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk cm_96m_fck = {
+        .name           = "cm_96m_fck",
+        .parent         = &dpll4_m2x2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
+        .clksel         = cm_96m_fck_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* This virtual clock is the source for dpll4_m3x2_ck */
+static struct clk dpll4_m3_ck = {
+        .name           = "dpll4_m3_ck",
+        .parent         = &dpll4_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
+        .clksel         = div16_dpll4_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m3x2_ck = {
+        .name           = "dpll4_m3x2_ck",
+        .parent         = &dpll4_m3_ck,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel virt_omap_54m_fck_clksel[] = {
+        { .parent = &sys_ck,        .rates = dpll_bypass_rates },
+        { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk virt_omap_54m_fck = {
+        .name           = "virt_omap_54m_fck",
+        .parent         = &dpll4_m3x2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
+        .clksel         = virt_omap_54m_fck_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate omap_54m_alt_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel omap_54m_clksel[] = {
+        { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
+        { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
+        { .parent = NULL }
+};
+
+static struct clk omap_54m_fck = {
+        .name           = "omap_54m_fck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_SOURCE_54M,
+        .clksel         = omap_54m_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate omap_48m_96md2_rates[] = {
+        { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate omap_48m_alt_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel omap_48m_clksel[] = {
+        { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
+        { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
+        { .parent = NULL }
+};
+
+static struct clk omap_48m_fck = {
+        .name           = "omap_48m_fck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_SOURCE_48M,
+        .clksel         = omap_48m_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk omap_12m_fck = {
+        .name           = "omap_12m_fck",
+        .parent         = &omap_48m_fck,
+        .fixed_div      = 4,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_fixed_divisor_recalc,
+};
+
+/* This virstual clock is the source for dpll4_m4x2_ck */
+static struct clk dpll4_m4_ck = {
+        .name           = "dpll4_m4_ck",
+        .parent         = &dpll4_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
+        .clksel         = div16_dpll4_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m4x2_ck = {
+        .name           = "dpll4_m4x2_ck",
+        .parent         = &dpll4_m4_ck,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+/* This virtual clock is the source for dpll4_m5x2_ck */
+static struct clk dpll4_m5_ck = {
+        .name           = "dpll4_m5_ck",
+        .parent         = &dpll4_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
+        .clksel         = div16_dpll4_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m5x2_ck = {
+        .name           = "dpll4_m5x2_ck",
+        .parent         = &dpll4_m5_ck,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+/* This virtual clock is the source for dpll4_m6x2_ck */
+static struct clk dpll4_m6_ck = {
+        .name           = "dpll4_m6_ck",
+        .parent         = &dpll4_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
+        .clksel         = div16_dpll4_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m6x2_ck = {
+        .name           = "dpll4_m6x2_ck",
+        .parent         = &dpll4_m6_ck,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static struct clk emu_per_alwon_ck = {
+        .name           = "emu_per_alwon_ck",
+        .parent         = &dpll4_m6x2_ck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+/* DPLL5 */
+/* Supplies 120MHz clock, USIM source clock */
+/* Type: DPLL */
+/* 3430ES2 only */
+static const struct dpll_data dpll5_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
+        .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
+        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
+        .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
+        .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
+};
+
+static struct clk dpll5_ck = {
+        .name           = "dpll5_ck",
+        .parent         = &sys_ck,
+        .dpll_data      = &dpll5_dd,
+        .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
+                                ALWAYS_ENABLED,
+        .recalc         = &omap3_dpll_recalc,
+};
+
+static const struct clksel div16_dpll5_clksel[] = {
+        { .parent = &dpll5_ck, .rates = div16_dpll_rates },
+        { .parent = NULL }
+};
+
+static struct clk dpll5_m2_ck = {
+        .name           = "dpll5_m2_ck",
+        .parent         = &dpll5_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
+        .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
+        .clksel         = div16_dpll5_clksel,
+        .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel omap_120m_fck_clksel[] = {
+        { .parent = &sys_ck,      .rates = dpll_bypass_rates },
+        { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk omap_120m_fck = {
+        .name           = "omap_120m_fck",
+        .parent         = &dpll5_m2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
+        .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
+        .clksel         = omap_120m_fck_clksel,
+        .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* CM EXTERNAL CLOCK OUTPUTS */
+
+static const struct clksel_rate clkout2_src_core_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate clkout2_src_sys_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate clkout2_src_96m_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate clkout2_src_54m_rates[] = {
+        { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel clkout2_src_clksel[] = {
+        { .parent = &core_ck,             .rates = clkout2_src_core_rates },
+        { .parent = &sys_ck,              .rates = clkout2_src_sys_rates },
+        { .parent = &omap_96m_alwon_fck,  .rates = clkout2_src_96m_rates },
+        { .parent = &omap_54m_fck,        .rates = clkout2_src_54m_rates },
+        { .parent = NULL }
+};
+
+static struct clk clkout2_src_ck = {
+        .name           = "clkout2_src_ck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
+        .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
+        .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
+        .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
+        .clksel         = clkout2_src_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate sys_clkout2_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 1, .flags = RATE_IN_343X },
+        { .div = 4, .val = 2, .flags = RATE_IN_343X },
+        { .div = 8, .val = 3, .flags = RATE_IN_343X },
+        { .div = 16, .val = 4, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel sys_clkout2_clksel[] = {
+        { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
+        { .parent = NULL },
+};
+
+static struct clk sys_clkout2 = {
+        .name           = "sys_clkout2",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
+        .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
+        .clksel         = sys_clkout2_clksel,
+        .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* CM OUTPUT CLOCKS */
+
+static struct clk corex2_fck = {
+        .name           = "corex2_fck",
+        .parent         = &dpll3_m2x2_ck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+/* DPLL power domain clock controls */
+
+static const struct clksel div2_core_clksel[] = {
+        { .parent = &core_ck, .rates = div2_rates },
+        { .parent = NULL }
+};
+
+/*
+ * REVISIT: Are these in DPLL power domain or CM power domain? docs
+ * may be inconsistent here?
+ */
+static struct clk dpll1_fck = {
+        .name           = "dpll1_fck",
+        .parent         = &core_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
+        .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
+        .clksel         = div2_core_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/*
+ * MPU clksel:
+ * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
+ * derives from the high-frequency bypass clock originating from DPLL3,
+ * called 'dpll1_fck'
+ */
+static const struct clksel mpu_clksel[] = {
+        { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
+        { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk mpu_ck = {
+        .name           = "mpu_ck",
+        .parent         = &dpll1_x2m2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
+        .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
+        .clksel         = mpu_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
+static const struct clksel_rate arm_fck_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 1, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel arm_fck_clksel[] = {
+        { .parent = &mpu_ck, .rates = arm_fck_rates },
+        { .parent = NULL }
+};
+
+static struct clk arm_fck = {
+        .name           = "arm_fck",
+        .parent         = &mpu_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
+        .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
+        .clksel         = arm_fck_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/*
+ * REVISIT: This clock is never specifically defined in the 3430 TRM,
+ * although it is referenced - so this is a guess
+ */
+static struct clk emu_mpu_alwon_ck = {
+        .name           = "emu_mpu_alwon_ck",
+        .parent         = &mpu_ck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dpll2_fck = {
+        .name           = "dpll2_fck",
+        .parent         = &core_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
+        .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
+        .clksel         = div2_core_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/*
+ * IVA2 clksel:
+ * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
+ * derives from the high-frequency bypass clock originating from DPLL3,
+ * called 'dpll2_fck'
+ */
+
+static const struct clksel iva2_clksel[] = {
+        { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
+        { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk iva2_ck = {
+        .name           = "iva2_ck",
+        .parent         = &dpll2_m2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
+                                          OMAP3430_CM_IDLEST_PLL),
+        .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
+        .clksel         = iva2_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* Common interface clocks */
+
+static struct clk l3_ick = {
+        .name           = "l3_ick",
+        .parent         = &core_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
+        .clksel         = div2_core_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel div2_l3_clksel[] = {
+        { .parent = &l3_ick, .rates = div2_rates },
+        { .parent = NULL }
+};
+
+static struct clk l4_ick = {
+        .name           = "l4_ick",
+        .parent         = &l3_ick,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
+        .clksel         = div2_l3_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+
+};
+
+static const struct clksel div2_l4_clksel[] = {
+        { .parent = &l4_ick, .rates = div2_rates },
+        { .parent = NULL }
+};
+
+static struct clk rm_ick = {
+        .name           = "rm_ick",
+        .parent         = &l4_ick,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
+        .clksel         = div2_l4_clksel,
+        .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* GFX power domain */
+
+/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
+
+static const struct clksel gfx_l3_clksel[] = {
+        { .parent = &l3_ick, .rates = gfx_l3_rates },
+        { .parent = NULL }
+};
+
+static struct clk gfx_l3_fck = {
+        .name           = "gfx_l3_fck",
+        .parent         = &l3_ick,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP_EN_GFX_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
+        .clksel         = gfx_l3_clksel,
+        .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gfx_l3_ick = {
+        .name           = "gfx_l3_ick",
+        .parent         = &l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP_EN_GFX_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES1,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gfx_cg1_ck = {
+        .name           = "gfx_cg1_ck",
+        .parent         = &gfx_l3_fck, /* REVISIT: correct? */
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES1,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gfx_cg2_ck = {
+        .name           = "gfx_cg2_ck",
+        .parent         = &gfx_l3_fck, /* REVISIT: correct? */
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES1,
+        .recalc         = &followparent_recalc,
+};
+
+/* SGX power domain - 3430ES2 only */
+
+static const struct clksel_rate sgx_core_rates[] = {
+        { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 4, .val = 1, .flags = RATE_IN_343X },
+        { .div = 6, .val = 2, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel_rate sgx_96m_rates[] = {
+        { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel sgx_clksel[] = {
+        { .parent = &core_ck,    .rates = sgx_core_rates },
+        { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
+        { .parent = NULL },
+};
+
+static struct clk sgx_fck = {
+        .name           = "sgx_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
+        .clksel         = sgx_clksel,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk sgx_ick = {
+        .name           = "sgx_ick",
+        .parent         = &l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+/* CORE power domain */
+
+static struct clk d2d_26m_fck = {
+        .name           = "d2d_26m_fck",
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES1,
+        .recalc         = &followparent_recalc,
+};
+
+static const struct clksel omap343x_gpt_clksel[] = {
+        { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
+        { .parent = &sys_ck,       .rates = gpt_sys_rates },
+        { .parent = NULL}
+};
+
+static struct clk gpt10_fck = {
+        .name           = "gpt10_fck",
+        .parent         = &sys_ck,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt11_fck = {
+        .name           = "gpt11_fck",
+        .parent         = &sys_ck,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk cpefuse_fck = {
+        .name           = "cpefuse_fck",
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+        .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk ts_fck = {
+        .name           = "ts_fck",
+        .parent         = &omap_32k_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+        .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usbtll_fck = {
+        .name           = "usbtll_fck",
+        .parent         = &omap_120m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+        .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+/* CORE 96M FCLK-derived clocks */
+
+static struct clk core_96m_fck = {
+        .name           = "core_96m_fck",
+        .parent         = &omap_96m_fck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs3_fck = {
+        .name           = "mmchs_fck",
+        .id             = 3,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs2_fck = {
+        .name           = "mmchs_fck",
+        .id             = 2,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mspro_fck = {
+        .name           = "mspro_fck",
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs1_fck = {
+        .name           = "mmchs_fck",
+        .id             = 1,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c3_fck = {
+        .name           = "i2c_fck",
+        .id             = 3,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c2_fck = {
+        .name           = "i2c_fck",
+        .id             = 2,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c1_fck = {
+        .name           = "i2c_fck",
+        .id             = 1,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+/*
+ * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
+ * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
+ */
+static const struct clksel_rate common_mcbsp_96m_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel mcbsp_15_clksel[] = {
+        { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
+        { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
+        { .parent = NULL }
+};
+
+static struct clk mcbsp5_fck = {
+        .name           = "mcbsp5_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
+        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+        .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
+        .clksel         = mcbsp_15_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk mcbsp1_fck = {
+        .name           = "mcbsp1_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
+        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+        .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
+        .clksel         = mcbsp_15_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* CORE_48M_FCK-derived clocks */
+
+static struct clk core_48m_fck = {
+        .name           = "core_48m_fck",
+        .parent         = &omap_48m_fck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi4_fck = {
+        .name           = "mcspi_fck",
+        .id             = 4,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi3_fck = {
+        .name           = "mcspi_fck",
+        .id             = 3,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi2_fck = {
+        .name           = "mcspi_fck",
+        .id             = 2,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi1_fck = {
+        .name           = "mcspi_fck",
+        .id             = 1,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart2_fck = {
+        .name           = "uart2_fck",
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_UART2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart1_fck = {
+        .name           = "uart1_fck",
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_UART1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk fshostusb_fck = {
+        .name           = "fshostusb_fck",
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES1,
+        .recalc         = &followparent_recalc,
+};
+
+/* CORE_12M_FCK based clocks */
+
+static struct clk core_12m_fck = {
+        .name           = "core_12m_fck",
+        .parent         = &omap_12m_fck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk hdq_fck = {
+        .name           = "hdq_fck",
+        .parent         = &core_12m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+/* DPLL3-derived clock */
+
+static const struct clksel_rate ssi_ssr_corex2_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 3, .val = 3, .flags = RATE_IN_343X },
+        { .div = 4, .val = 4, .flags = RATE_IN_343X },
+        { .div = 6, .val = 6, .flags = RATE_IN_343X },
+        { .div = 8, .val = 8, .flags = RATE_IN_343X },
+        { .div = 0 }
+};
+
+static const struct clksel ssi_ssr_clksel[] = {
+        { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
+        { .parent = NULL }
+};
+
+static struct clk ssi_ssr_fck = {
+        .name           = "ssi_ssr_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
+        .clksel         = ssi_ssr_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk ssi_sst_fck = {
+        .name           = "ssi_sst_fck",
+        .parent         = &ssi_ssr_fck,
+        .fixed_div      = 2,
+        .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_fixed_divisor_recalc,
+};
+
+
+
+/* CORE_L3_ICK based clocks */
+
+static struct clk core_l3_ick = {
+        .name           = "core_l3_ick",
+        .parent         = &l3_ick,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk hsotgusb_ick = {
+        .name           = "hsotgusb_ick",
+        .parent         = &core_l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sdrc_ick = {
+        .name           = "sdrc_ick",
+        .parent         = &core_l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpmc_fck = {
+        .name           = "gpmc_fck",
+        .parent         = &core_l3_ick,
+        .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
+                                ENABLE_ON_INIT,
+        .recalc         = &followparent_recalc,
+};
+
+/* SECURITY_L3_ICK based clocks */
+
+static struct clk security_l3_ick = {
+        .name           = "security_l3_ick",
+        .parent         = &l3_ick,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk pka_ick = {
+        .name           = "pka_ick",
+        .parent         = &security_l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_PKA_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+/* CORE_L4_ICK based clocks */
+
+static struct clk core_l4_ick = {
+        .name           = "core_l4_ick",
+        .parent         = &l4_ick,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usbtll_ick = {
+        .name           = "usbtll_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs3_ick = {
+        .name           = "mmchs_ick",
+        .id             = 3,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+/* Intersystem Communication Registers - chassis mode only */
+static struct clk icr_ick = {
+        .name           = "icr_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_ICR_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk aes2_ick = {
+        .name           = "aes2_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_AES2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sha12_ick = {
+        .name           = "sha12_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk des2_ick = {
+        .name           = "des2_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_DES2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs2_ick = {
+        .name           = "mmchs_ick",
+        .id             = 2,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs1_ick = {
+        .name           = "mmchs_ick",
+        .id             = 1,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mspro_ick = {
+        .name           = "mspro_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk hdq_ick = {
+        .name           = "hdq_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi4_ick = {
+        .name           = "mcspi_ick",
+        .id             = 4,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi3_ick = {
+        .name           = "mcspi_ick",
+        .id             = 3,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi2_ick = {
+        .name           = "mcspi_ick",
+        .id             = 2,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi1_ick = {
+        .name           = "mcspi_ick",
+        .id             = 1,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c3_ick = {
+        .name           = "i2c_ick",
+        .id             = 3,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c2_ick = {
+        .name           = "i2c_ick",
+        .id             = 2,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c1_ick = {
+        .name           = "i2c_ick",
+        .id             = 1,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart2_ick = {
+        .name           = "uart2_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_UART2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart1_ick = {
+        .name           = "uart1_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_UART1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt11_ick = {
+        .name           = "gpt11_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt10_ick = {
+        .name           = "gpt10_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp5_ick = {
+        .name           = "mcbsp5_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp1_ick = {
+        .name           = "mcbsp1_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk fac_ick = {
+        .name           = "fac_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES1,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mailboxes_ick = {
+        .name           = "mailboxes_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk omapctrl_ick = {
+        .name           = "omapctrl_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
+        .recalc         = &followparent_recalc,
+};
+
+/* SSI_L4_ICK based clocks */
+
+static struct clk ssi_l4_ick = {
+        .name           = "ssi_l4_ick",
+        .parent         = &l4_ick,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk ssi_ick = {
+        .name           = "ssi_ick",
+        .parent         = &ssi_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+/* REVISIT: Technically the TRM claims that this is CORE_CLK based,
+ * but l4_ick makes more sense to me */
+
+static const struct clksel usb_l4_clksel[] = {
+        { .parent = &l4_ick, .rates = div2_rates },
+        { .parent = NULL },
+};
+
+static struct clk usb_l4_ick = {
+        .name           = "usb_l4_ick",
+        .parent         = &l4_ick,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
+        .clksel         = usb_l4_clksel,
+        .flags          = CLOCK_IN_OMAP3430ES1,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
+
+/* SECURITY_L4_ICK2 based clocks */
+
+static struct clk security_l4_ick2 = {
+        .name           = "security_l4_ick2",
+        .parent         = &l4_ick,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk aes1_ick = {
+        .name           = "aes1_ick",
+        .parent         = &security_l4_ick2,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_AES1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk rng_ick = {
+        .name           = "rng_ick",
+        .parent         = &security_l4_ick2,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_RNG_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sha11_ick = {
+        .name           = "sha11_ick",
+        .parent         = &security_l4_ick2,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk des1_ick = {
+        .name           = "des1_ick",
+        .parent         = &security_l4_ick2,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_DES1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+/* DSS */
+static const struct clksel dss1_alwon_fck_clksel[] = {
+        { .parent = &sys_ck,        .rates = dpll_bypass_rates },
+        { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk dss1_alwon_fck = {
+        .name           = "dss1_alwon_fck",
+        .parent         = &dpll4_m4x2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
+        .clksel         = dss1_alwon_fck_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk dss_tv_fck = {
+        .name           = "dss_tv_fck",
+        .parent         = &omap_54m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_TV_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss_96m_fck = {
+        .name           = "dss_96m_fck",
+        .parent         = &omap_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_TV_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss2_alwon_fck = {
+        .name           = "dss2_alwon_fck",
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss_ick = {
+        /* Handles both L3 and L4 clocks */
+        .name           = "dss_ick",
+        .parent         = &l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+/* CAM */
+
+static const struct clksel cam_mclk_clksel[] = {
+        { .parent = &sys_ck,        .rates = dpll_bypass_rates },
+        { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk cam_mclk = {
+        .name           = "cam_mclk",
+        .parent         = &dpll4_m5x2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
+        .clksel         = cam_mclk_clksel,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_CAM_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk cam_l3_ick = {
+        .name           = "cam_l3_ick",
+        .parent         = &l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_CAM_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk cam_l4_ick = {
+        .name           = "cam_l4_ick",
+        .parent         = &l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_CAM_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+/* USBHOST - 3430ES2 only */
+
+static struct clk usbhost_120m_fck = {
+        .name           = "usbhost_120m_fck",
+        .parent         = &omap_120m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usbhost_48m_fck = {
+        .name           = "usbhost_48m_fck",
+        .parent         = &omap_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usbhost_l3_ick = {
+        .name           = "usbhost_l3_ick",
+        .parent         = &l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usbhost_l4_ick = {
+        .name           = "usbhost_l4_ick",
+        .parent         = &l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usbhost_sar_fck = {
+        .name           = "usbhost_sar_fck",
+        .parent         = &osc_sys_ck,
+        .enable_reg     = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
+        .enable_bit     = OMAP3430ES2_SAVEANDRESTORE_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+/* WKUP */
+
+static const struct clksel_rate usim_96m_rates[] = {
+        { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 4,  .val = 4, .flags = RATE_IN_343X },
+        { .div = 8,  .val = 5, .flags = RATE_IN_343X },
+        { .div = 10, .val = 6, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel_rate usim_120m_rates[] = {
+        { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
+        { .div = 16, .val = 9,  .flags = RATE_IN_343X },
+        { .div = 20, .val = 10, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel usim_clksel[] = {
+        { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
+        { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
+        { .parent = &sys_ck,            .rates = div2_rates },
+        { .parent = NULL },
+};
+
+/* 3430ES2 only */
+static struct clk usim_fck = {
+        .name           = "usim_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
+        .clksel         = usim_clksel,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt1_fck = {
+        .name           = "gpt1_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk wkup_32k_fck = {
+        .name           = "wkup_32k_fck",
+        .parent         = &omap_32k_fck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio1_fck = {
+        .name           = "gpio1_fck",
+        .parent         = &wkup_32k_fck,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt2_fck = {
+        .name           = "wdt2_fck",
+        .parent         = &wkup_32k_fck,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wkup_l4_ick = {
+        .name           = "wkup_l4_ick",
+        .parent         = &sys_ck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &followparent_recalc,
+};
+
+/* 3430ES2 only */
+/* Never specifically named in the TRM, so we have to infer a likely name */
+static struct clk usim_ick = {
+        .name           = "usim_ick",
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt2_ick = {
+        .name           = "wdt2_ick",
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt1_ick = {
+        .name           = "wdt1_ick",
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio1_ick = {
+        .name           = "gpio1_ick",
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk omap_32ksync_ick = {
+        .name           = "omap_32ksync_ick",
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt12_ick = {
+        .name           = "gpt12_ick",
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt1_ick = {
+        .name           = "gpt1_ick",
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+
+
+/* PER clock domain */
+
+static struct clk per_96m_fck = {
+        .name           = "per_96m_fck",
+        .parent         = &omap_96m_alwon_fck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk per_48m_fck = {
+        .name           = "per_48m_fck",
+        .parent         = &omap_48m_fck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart3_fck = {
+        .name           = "uart3_fck",
+        .parent         = &per_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_UART3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt2_fck = {
+        .name           = "gpt2_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt3_fck = {
+        .name           = "gpt3_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt4_fck = {
+        .name           = "gpt4_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt5_fck = {
+        .name           = "gpt5_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt6_fck = {
+        .name           = "gpt6_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt7_fck = {
+        .name           = "gpt7_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt8_fck = {
+        .name           = "gpt8_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt9_fck = {
+        .name           = "gpt9_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk per_32k_alwon_fck = {
+        .name           = "per_32k_alwon_fck",
+        .parent         = &omap_32k_fck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio6_fck = {
+        .name           = "gpio6_fck",
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio5_fck = {
+        .name           = "gpio5_fck",
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio4_fck = {
+        .name           = "gpio4_fck",
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio3_fck = {
+        .name           = "gpio3_fck",
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio2_fck = {
+        .name           = "gpio2_fck",
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt3_fck = {
+        .name           = "wdt3_fck",
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk per_l4_ick = {
+        .name           = "per_l4_ick",
+        .parent         = &l4_ick,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio6_ick = {
+        .name           = "gpio6_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio5_ick = {
+        .name           = "gpio5_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio4_ick = {
+        .name           = "gpio4_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio3_ick = {
+        .name           = "gpio3_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio2_ick = {
+        .name           = "gpio2_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt3_ick = {
+        .name           = "wdt3_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart3_ick = {
+        .name           = "uart3_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_UART3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt9_ick = {
+        .name           = "gpt9_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt8_ick = {
+        .name           = "gpt8_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt7_ick = {
+        .name           = "gpt7_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt6_ick = {
+        .name           = "gpt6_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt5_ick = {
+        .name           = "gpt5_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt4_ick = {
+        .name           = "gpt4_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt3_ick = {
+        .name           = "gpt3_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt2_ick = {
+        .name           = "gpt2_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp2_ick = {
+        .name           = "mcbsp2_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp3_ick = {
+        .name           = "mcbsp3_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp4_ick = {
+        .name           = "mcbsp4_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static const struct clksel mcbsp_234_clksel[] = {
+        { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
+        { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
+        { .parent = NULL }
+};
+
+static struct clk mcbsp2_fck = {
+        .name           = "mcbsp2_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
+        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+        .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
+        .clksel         = mcbsp_234_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk mcbsp3_fck = {
+        .name           = "mcbsp3_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
+        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+        .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
+        .clksel         = mcbsp_234_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk mcbsp4_fck = {
+        .name           = "mcbsp4_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
+        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+        .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
+        .clksel         = mcbsp_234_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* EMU clocks */
+
+/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
+
+static const struct clksel_rate emu_src_sys_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel_rate emu_src_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel_rate emu_src_per_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel_rate emu_src_mpu_rates[] = {
+        { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel emu_src_clksel[] = {
+        { .parent = &sys_ck,            .rates = emu_src_sys_rates },
+        { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
+        { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
+        { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
+        { .parent = NULL },
+};
+
+/*
+ * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
+ * to switch the source of some of the EMU clocks.
+ * XXX Are there CLKEN bits for these EMU clks?
+ */
+static struct clk emu_src_ck = {
+        .name           = "emu_src_ck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
+        .clksel         = emu_src_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate pclk_emu_rates[] = {
+        { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 3, .val = 3, .flags = RATE_IN_343X },
+        { .div = 4, .val = 4, .flags = RATE_IN_343X },
+        { .div = 6, .val = 6, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel pclk_emu_clksel[] = {
+        { .parent = &emu_src_ck, .rates = pclk_emu_rates },
+        { .parent = NULL },
+};
+
+static struct clk pclk_fck = {
+        .name           = "pclk_fck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
+        .clksel         = pclk_emu_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate pclkx2_emu_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 3, .val = 3, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel pclkx2_emu_clksel[] = {
+        { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
+        { .parent = NULL },
+};
+
+static struct clk pclkx2_fck = {
+        .name           = "pclkx2_fck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
+        .clksel         = pclkx2_emu_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel atclk_emu_clksel[] = {
+        { .parent = &emu_src_ck, .rates = div2_rates },
+        { .parent = NULL },
+};
+
+static struct clk atclk_fck = {
+        .name           = "atclk_fck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
+        .clksel         = atclk_emu_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk traceclk_src_fck = {
+        .name           = "traceclk_src_fck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
+        .clksel         = emu_src_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate traceclk_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 4, .val = 4, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel traceclk_clksel[] = {
+        { .parent = &traceclk_src_fck, .rates = traceclk_rates },
+        { .parent = NULL },
+};
+
+static struct clk traceclk_fck = {
+        .name           = "traceclk_fck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
+        .clksel         = traceclk_clksel,
+        .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* SR clocks */
+
+/* SmartReflex fclk (VDD1) */
+static struct clk sr1_fck = {
+        .name           = "sr1_fck",
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_SR1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+        .recalc         = &followparent_recalc,
+};
+
+/* SmartReflex fclk (VDD2) */
+static struct clk sr2_fck = {
+        .name           = "sr2_fck",
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_SR2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sr_l4_ick = {
+        .name           = "sr_l4_ick",
+        .parent         = &l4_ick,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+/* SECURE_32K_FCK clocks */
+
+static struct clk gpt12_fck = {
+        .name           = "gpt12_fck",
+        .parent         = &secure_32k_fck,
+        .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt1_fck = {
+        .name           = "wdt1_fck",
+        .parent         = &secure_32k_fck,
+        .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk *onchip_34xx_clks[] __initdata = {
+        &omap_32k_fck,
+        &virt_12m_ck,
+        &virt_13m_ck,
+        &virt_16_8m_ck,
+        &virt_19_2m_ck,
+        &virt_26m_ck,
+        &virt_38_4m_ck,
+        &osc_sys_ck,
+        &sys_ck,
+        &sys_altclk,
+        &mcbsp_clks,
+        &sys_clkout1,
+        &dpll1_ck,
+        &dpll1_x2_ck,
+        &dpll1_x2m2_ck,
+        &dpll2_ck,
+        &dpll2_m2_ck,
+        &dpll3_ck,
+        &core_ck,
+        &dpll3_x2_ck,
+        &dpll3_m2_ck,
+        &dpll3_m2x2_ck,
+        &dpll3_m3_ck,
+        &dpll3_m3x2_ck,
+        &emu_core_alwon_ck,
+        &dpll4_ck,
+        &dpll4_x2_ck,
+        &omap_96m_alwon_fck,
+        &omap_96m_fck,
+        &cm_96m_fck,
+        &virt_omap_54m_fck,
+        &omap_54m_fck,
+        &omap_48m_fck,
+        &omap_12m_fck,
+        &dpll4_m2_ck,
+        &dpll4_m2x2_ck,
+        &dpll4_m3_ck,
+        &dpll4_m3x2_ck,
+        &dpll4_m4_ck,
+        &dpll4_m4x2_ck,
+        &dpll4_m5_ck,
+        &dpll4_m5x2_ck,
+        &dpll4_m6_ck,
+        &dpll4_m6x2_ck,
+        &emu_per_alwon_ck,
+        &dpll5_ck,
+        &dpll5_m2_ck,
+        &omap_120m_fck,
+        &clkout2_src_ck,
+        &sys_clkout2,
+        &corex2_fck,
+        &dpll1_fck,
+        &mpu_ck,
+        &arm_fck,
+        &emu_mpu_alwon_ck,
+        &dpll2_fck,
+        &iva2_ck,
+        &l3_ick,
+        &l4_ick,
+        &rm_ick,
+        &gfx_l3_fck,
+        &gfx_l3_ick,
+        &gfx_cg1_ck,
+        &gfx_cg2_ck,
+        &sgx_fck,
+        &sgx_ick,
+        &d2d_26m_fck,
+        &gpt10_fck,
+        &gpt11_fck,
+        &cpefuse_fck,
+        &ts_fck,
+        &usbtll_fck,
+        &core_96m_fck,
+        &mmchs3_fck,
+        &mmchs2_fck,
+        &mspro_fck,
+        &mmchs1_fck,
+        &i2c3_fck,
+        &i2c2_fck,
+        &i2c1_fck,
+        &mcbsp5_fck,
+        &mcbsp1_fck,
+        &core_48m_fck,
+        &mcspi4_fck,
+        &mcspi3_fck,
+        &mcspi2_fck,
+        &mcspi1_fck,
+        &uart2_fck,
+        &uart1_fck,
+        &fshostusb_fck,
+        &core_12m_fck,
+        &hdq_fck,
+        &ssi_ssr_fck,
+        &ssi_sst_fck,
+        &core_l3_ick,
+        &hsotgusb_ick,
+        &sdrc_ick,
+        &gpmc_fck,
+        &security_l3_ick,
+        &pka_ick,
+        &core_l4_ick,
+        &usbtll_ick,
+        &mmchs3_ick,
+        &icr_ick,
+        &aes2_ick,
+        &sha12_ick,
+        &des2_ick,
+        &mmchs2_ick,
+        &mmchs1_ick,
+        &mspro_ick,
+        &hdq_ick,
+        &mcspi4_ick,
+        &mcspi3_ick,
+        &mcspi2_ick,
+        &mcspi1_ick,
+        &i2c3_ick,
+        &i2c2_ick,
+        &i2c1_ick,
+        &uart2_ick,
+        &uart1_ick,
+        &gpt11_ick,
+        &gpt10_ick,
+        &mcbsp5_ick,
+        &mcbsp1_ick,
+        &fac_ick,
+        &mailboxes_ick,
+        &omapctrl_ick,
+        &ssi_l4_ick,
+        &ssi_ick,
+        &usb_l4_ick,
+        &security_l4_ick2,
+        &aes1_ick,
+        &rng_ick,
+        &sha11_ick,
+        &des1_ick,
+        &dss1_alwon_fck,
+        &dss_tv_fck,
+        &dss_96m_fck,
+        &dss2_alwon_fck,
+        &dss_ick,
+        &cam_mclk,
+        &cam_l3_ick,
+        &cam_l4_ick,
+        &usbhost_120m_fck,
+        &usbhost_48m_fck,
+        &usbhost_l3_ick,
+        &usbhost_l4_ick,
+        &usbhost_sar_fck,
+        &usim_fck,
+        &gpt1_fck,
+        &wkup_32k_fck,
+        &gpio1_fck,
+        &wdt2_fck,
+        &wkup_l4_ick,
+        &usim_ick,
+        &wdt2_ick,
+        &wdt1_ick,
+        &gpio1_ick,
+        &omap_32ksync_ick,
+        &gpt12_ick,
+        &gpt1_ick,
+        &per_96m_fck,
+        &per_48m_fck,
+        &uart3_fck,
+        &gpt2_fck,
+        &gpt3_fck,
+        &gpt4_fck,
+        &gpt5_fck,
+        &gpt6_fck,
+        &gpt7_fck,
+        &gpt8_fck,
+        &gpt9_fck,
+        &per_32k_alwon_fck,
+        &gpio6_fck,
+        &gpio5_fck,
+        &gpio4_fck,
+        &gpio3_fck,
+        &gpio2_fck,
+        &wdt3_fck,
+        &per_l4_ick,
+        &gpio6_ick,
+        &gpio5_ick,
+        &gpio4_ick,
+        &gpio3_ick,
+        &gpio2_ick,
+        &wdt3_ick,
+        &uart3_ick,
+        &gpt9_ick,
+        &gpt8_ick,
+        &gpt7_ick,
+        &gpt6_ick,
+        &gpt5_ick,
+        &gpt4_ick,
+        &gpt3_ick,
+        &gpt2_ick,
+        &mcbsp2_ick,
+        &mcbsp3_ick,
+        &mcbsp4_ick,
+        &mcbsp2_fck,
+        &mcbsp3_fck,
+        &mcbsp4_fck,
+        &emu_src_ck,
+        &pclk_fck,
+        &pclkx2_fck,
+        &atclk_fck,
+        &traceclk_src_fck,
+        &traceclk_fck,
+        &sr1_fck,
+        &sr2_fck,
+        &sr_l4_ick,
+        &secure_32k_fck,
+        &gpt12_fck,
+        &wdt1_fck,
+};
+
+#endif
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
new file mode 100644
index 000000000000..20ac38100678
--- /dev/null
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -0,0 +1,401 @@
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
+
+/*
+ * OMAP24XX Clock Management register bits
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "cm.h"
+
+/* Bits shared between registers */
+
+/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
+#define OMAP24XX_EN_CAM_SHIFT                           31
+#define OMAP24XX_EN_CAM                                 (1 << 31)
+#define OMAP24XX_EN_WDT4_SHIFT                          29
+#define OMAP24XX_EN_WDT4                                (1 << 29)
+#define OMAP2420_EN_WDT3_SHIFT                          28
+#define OMAP2420_EN_WDT3                                (1 << 28)
+#define OMAP24XX_EN_MSPRO_SHIFT                         27
+#define OMAP24XX_EN_MSPRO                               (1 << 27)
+#define OMAP24XX_EN_FAC_SHIFT                           25
+#define OMAP24XX_EN_FAC                                 (1 << 25)
+#define OMAP2420_EN_EAC_SHIFT                           24
+#define OMAP2420_EN_EAC                                 (1 << 24)
+#define OMAP24XX_EN_HDQ_SHIFT                           23
+#define OMAP24XX_EN_HDQ                                 (1 << 23)
+#define OMAP2420_EN_I2C2_SHIFT                          20
+#define OMAP2420_EN_I2C2                                (1 << 20)
+#define OMAP2420_EN_I2C1_SHIFT                          19
+#define OMAP2420_EN_I2C1                                (1 << 19)
+
+/* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */
+#define OMAP2430_EN_MCBSP5_SHIFT                        5
+#define OMAP2430_EN_MCBSP5                              (1 << 5)
+#define OMAP2430_EN_MCBSP4_SHIFT                        4
+#define OMAP2430_EN_MCBSP4                              (1 << 4)
+#define OMAP2430_EN_MCBSP3_SHIFT                        3
+#define OMAP2430_EN_MCBSP3                              (1 << 3)
+#define OMAP24XX_EN_SSI_SHIFT                           1
+#define OMAP24XX_EN_SSI                                 (1 << 1)
+
+/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
+#define OMAP24XX_EN_MPU_WDT_SHIFT                       3
+#define OMAP24XX_EN_MPU_WDT                             (1 << 3)
+
+/* Bits specific to each register */
+
+/* CM_IDLEST_MPU */
+/* 2430 only */
+#define OMAP2430_ST_MPU                                 (1 << 0)
+
+/* CM_CLKSEL_MPU */
+#define OMAP24XX_CLKSEL_MPU_SHIFT                       0
+#define OMAP24XX_CLKSEL_MPU_MASK                        (0x1f << 0)
+
+/* CM_CLKSTCTRL_MPU */
+#define OMAP24XX_AUTOSTATE_MPU                          (1 << 0)
+
+/* CM_FCLKEN1_CORE specific bits*/
+#define OMAP24XX_EN_TV_SHIFT                            2
+#define OMAP24XX_EN_TV                                  (1 << 2)
+#define OMAP24XX_EN_DSS2_SHIFT                          1
+#define OMAP24XX_EN_DSS2                                (1 << 1)
+#define OMAP24XX_EN_DSS1_SHIFT                          0
+#define OMAP24XX_EN_DSS1                                (1 << 0)
+
+/* CM_FCLKEN2_CORE specific bits */
+#define OMAP2430_EN_I2CHS2_SHIFT                        20
+#define OMAP2430_EN_I2CHS2                              (1 << 20)
+#define OMAP2430_EN_I2CHS1_SHIFT                        19
+#define OMAP2430_EN_I2CHS1                              (1 << 19)
+#define OMAP2430_EN_MMCHSDB2_SHIFT                      17
+#define OMAP2430_EN_MMCHSDB2                            (1 << 17)
+#define OMAP2430_EN_MMCHSDB1_SHIFT                      16
+#define OMAP2430_EN_MMCHSDB1                            (1 << 16)
+
+/* CM_ICLKEN1_CORE specific bits */
+#define OMAP24XX_EN_MAILBOXES_SHIFT                     30
+#define OMAP24XX_EN_MAILBOXES                           (1 << 30)
+#define OMAP24XX_EN_DSS_SHIFT                           0
+#define OMAP24XX_EN_DSS                                 (1 << 0)
+
+/* CM_ICLKEN2_CORE specific bits */
+
+/* CM_ICLKEN3_CORE */
+/* 2430 only */
+#define OMAP2430_EN_SDRC_SHIFT                          2
+#define OMAP2430_EN_SDRC                                (1 << 2)
+
+/* CM_ICLKEN4_CORE */
+#define OMAP24XX_EN_PKA_SHIFT                           4
+#define OMAP24XX_EN_PKA                                 (1 << 4)
+#define OMAP24XX_EN_AES_SHIFT                           3
+#define OMAP24XX_EN_AES                                 (1 << 3)
+#define OMAP24XX_EN_RNG_SHIFT                           2
+#define OMAP24XX_EN_RNG                                 (1 << 2)
+#define OMAP24XX_EN_SHA_SHIFT                           1
+#define OMAP24XX_EN_SHA                                 (1 << 1)
+#define OMAP24XX_EN_DES_SHIFT                           0
+#define OMAP24XX_EN_DES                                 (1 << 0)
+
+/* CM_IDLEST1_CORE specific bits */
+#define OMAP24XX_ST_MAILBOXES                           (1 << 30)
+#define OMAP24XX_ST_WDT4                                (1 << 29)
+#define OMAP2420_ST_WDT3                                (1 << 28)
+#define OMAP24XX_ST_MSPRO                               (1 << 27)
+#define OMAP24XX_ST_FAC                                 (1 << 25)
+#define OMAP2420_ST_EAC                                 (1 << 24)
+#define OMAP24XX_ST_HDQ                                 (1 << 23)
+#define OMAP24XX_ST_I2C2                                (1 << 20)
+#define OMAP24XX_ST_I2C1                                (1 << 19)
+#define OMAP24XX_ST_MCBSP2                              (1 << 16)
+#define OMAP24XX_ST_MCBSP1                              (1 << 15)
+#define OMAP24XX_ST_DSS                                 (1 << 0)
+
+/* CM_IDLEST2_CORE */
+#define OMAP2430_ST_MCBSP5                              (1 << 5)
+#define OMAP2430_ST_MCBSP4                              (1 << 4)
+#define OMAP2430_ST_MCBSP3                              (1 << 3)
+#define OMAP24XX_ST_SSI                                 (1 << 1)
+
+/* CM_IDLEST3_CORE */
+/* 2430 only */
+#define OMAP2430_ST_SDRC                                (1 << 2)
+
+/* CM_IDLEST4_CORE */
+#define OMAP24XX_ST_PKA                                 (1 << 4)
+#define OMAP24XX_ST_AES                                 (1 << 3)
+#define OMAP24XX_ST_RNG                                 (1 << 2)
+#define OMAP24XX_ST_SHA                                 (1 << 1)
+#define OMAP24XX_ST_DES                                 (1 << 0)
+
+/* CM_AUTOIDLE1_CORE */
+#define OMAP24XX_AUTO_CAM                               (1 << 31)
+#define OMAP24XX_AUTO_MAILBOXES                         (1 << 30)
+#define OMAP24XX_AUTO_WDT4                              (1 << 29)
+#define OMAP2420_AUTO_WDT3                              (1 << 28)
+#define OMAP24XX_AUTO_MSPRO                             (1 << 27)
+#define OMAP2420_AUTO_MMC                               (1 << 26)
+#define OMAP24XX_AUTO_FAC                               (1 << 25)
+#define OMAP2420_AUTO_EAC                               (1 << 24)
+#define OMAP24XX_AUTO_HDQ                               (1 << 23)
+#define OMAP24XX_AUTO_UART2                             (1 << 22)
+#define OMAP24XX_AUTO_UART1                             (1 << 21)
+#define OMAP24XX_AUTO_I2C2                              (1 << 20)
+#define OMAP24XX_AUTO_I2C1                              (1 << 19)
+#define OMAP24XX_AUTO_MCSPI2                            (1 << 18)
+#define OMAP24XX_AUTO_MCSPI1                            (1 << 17)
+#define OMAP24XX_AUTO_MCBSP2                            (1 << 16)
+#define OMAP24XX_AUTO_MCBSP1                            (1 << 15)
+#define OMAP24XX_AUTO_GPT12                             (1 << 14)
+#define OMAP24XX_AUTO_GPT11                             (1 << 13)
+#define OMAP24XX_AUTO_GPT10                             (1 << 12)
+#define OMAP24XX_AUTO_GPT9                              (1 << 11)
+#define OMAP24XX_AUTO_GPT8                              (1 << 10)
+#define OMAP24XX_AUTO_GPT7                              (1 << 9)
+#define OMAP24XX_AUTO_GPT6                              (1 << 8)
+#define OMAP24XX_AUTO_GPT5                              (1 << 7)
+#define OMAP24XX_AUTO_GPT4                              (1 << 6)
+#define OMAP24XX_AUTO_GPT3                              (1 << 5)
+#define OMAP24XX_AUTO_GPT2                              (1 << 4)
+#define OMAP2420_AUTO_VLYNQ                             (1 << 3)
+#define OMAP24XX_AUTO_DSS                               (1 << 0)
+
+/* CM_AUTOIDLE2_CORE */
+#define OMAP2430_AUTO_MDM_INTC                          (1 << 11)
+#define OMAP2430_AUTO_GPIO5                             (1 << 10)
+#define OMAP2430_AUTO_MCSPI3                            (1 << 9)
+#define OMAP2430_AUTO_MMCHS2                            (1 << 8)
+#define OMAP2430_AUTO_MMCHS1                            (1 << 7)
+#define OMAP2430_AUTO_USBHS                             (1 << 6)
+#define OMAP2430_AUTO_MCBSP5                            (1 << 5)
+#define OMAP2430_AUTO_MCBSP4                            (1 << 4)
+#define OMAP2430_AUTO_MCBSP3                            (1 << 3)
+#define OMAP24XX_AUTO_UART3                             (1 << 2)
+#define OMAP24XX_AUTO_SSI                               (1 << 1)
+#define OMAP24XX_AUTO_USB                               (1 << 0)
+
+/* CM_AUTOIDLE3_CORE */
+#define OMAP24XX_AUTO_SDRC                              (1 << 2)
+#define OMAP24XX_AUTO_GPMC                              (1 << 1)
+#define OMAP24XX_AUTO_SDMA                              (1 << 0)
+
+/* CM_AUTOIDLE4_CORE */
+#define OMAP24XX_AUTO_PKA                               (1 << 4)
+#define OMAP24XX_AUTO_AES                               (1 << 3)
+#define OMAP24XX_AUTO_RNG                               (1 << 2)
+#define OMAP24XX_AUTO_SHA                               (1 << 1)
+#define OMAP24XX_AUTO_DES                               (1 << 0)
+
+/* CM_CLKSEL1_CORE */
+#define OMAP24XX_CLKSEL_USB_SHIFT                       25
+#define OMAP24XX_CLKSEL_USB_MASK                        (0x7 << 25)
+#define OMAP24XX_CLKSEL_SSI_SHIFT                       20
+#define OMAP24XX_CLKSEL_SSI_MASK                        (0x1f << 20)
+#define OMAP2420_CLKSEL_VLYNQ_SHIFT                     15
+#define OMAP2420_CLKSEL_VLYNQ_MASK                      (0x1f << 15)
+#define OMAP24XX_CLKSEL_DSS2_SHIFT                      13
+#define OMAP24XX_CLKSEL_DSS2_MASK                       (0x1 << 13)
+#define OMAP24XX_CLKSEL_DSS1_SHIFT                      8
+#define OMAP24XX_CLKSEL_DSS1_MASK                       (0x1f << 8)
+#define OMAP24XX_CLKSEL_L4_SHIFT                        5
+#define OMAP24XX_CLKSEL_L4_MASK                         (0x3 << 5)
+#define OMAP24XX_CLKSEL_L3_SHIFT                        0
+#define OMAP24XX_CLKSEL_L3_MASK                         (0x1f << 0)
+
+/* CM_CLKSEL2_CORE */
+#define OMAP24XX_CLKSEL_GPT12_SHIFT                     22
+#define OMAP24XX_CLKSEL_GPT12_MASK                      (0x3 << 22)
+#define OMAP24XX_CLKSEL_GPT11_SHIFT                     20
+#define OMAP24XX_CLKSEL_GPT11_MASK                      (0x3 << 20)
+#define OMAP24XX_CLKSEL_GPT10_SHIFT                     18
+#define OMAP24XX_CLKSEL_GPT10_MASK                      (0x3 << 18)
+#define OMAP24XX_CLKSEL_GPT9_SHIFT                      16
+#define OMAP24XX_CLKSEL_GPT9_MASK                       (0x3 << 16)
+#define OMAP24XX_CLKSEL_GPT8_SHIFT                      14
+#define OMAP24XX_CLKSEL_GPT8_MASK                       (0x3 << 14)
+#define OMAP24XX_CLKSEL_GPT7_SHIFT                      12
+#define OMAP24XX_CLKSEL_GPT7_MASK                       (0x3 << 12)
+#define OMAP24XX_CLKSEL_GPT6_SHIFT                      10
+#define OMAP24XX_CLKSEL_GPT6_MASK                       (0x3 << 10)
+#define OMAP24XX_CLKSEL_GPT5_SHIFT                      8
+#define OMAP24XX_CLKSEL_GPT5_MASK                       (0x3 << 8)
+#define OMAP24XX_CLKSEL_GPT4_SHIFT                      6
+#define OMAP24XX_CLKSEL_GPT4_MASK                       (0x3 << 6)
+#define OMAP24XX_CLKSEL_GPT3_SHIFT                      4
+#define OMAP24XX_CLKSEL_GPT3_MASK                       (0x3 << 4)
+#define OMAP24XX_CLKSEL_GPT2_SHIFT                      2
+#define OMAP24XX_CLKSEL_GPT2_MASK                       (0x3 << 2)
+
+/* CM_CLKSTCTRL_CORE */
+#define OMAP24XX_AUTOSTATE_DSS                          (1 << 2)
+#define OMAP24XX_AUTOSTATE_L4                           (1 << 1)
+#define OMAP24XX_AUTOSTATE_L3                           (1 << 0)
+
+/* CM_FCLKEN_GFX */
+#define OMAP24XX_EN_3D_SHIFT                            2
+#define OMAP24XX_EN_3D                                  (1 << 2)
+#define OMAP24XX_EN_2D_SHIFT                            1
+#define OMAP24XX_EN_2D                                  (1 << 1)
+
+/* CM_ICLKEN_GFX specific bits */
+
+/* CM_IDLEST_GFX specific bits */
+
+/* CM_CLKSEL_GFX specific bits */
+
+/* CM_CLKSTCTRL_GFX */
+#define OMAP24XX_AUTOSTATE_GFX                          (1 << 0)
+
+/* CM_FCLKEN_WKUP specific bits */
+
+/* CM_ICLKEN_WKUP specific bits */
+#define OMAP2430_EN_ICR_SHIFT                           6
+#define OMAP2430_EN_ICR                                 (1 << 6)
+#define OMAP24XX_EN_OMAPCTRL_SHIFT                      5
+#define OMAP24XX_EN_OMAPCTRL                            (1 << 5)
+#define OMAP24XX_EN_WDT1_SHIFT                          4
+#define OMAP24XX_EN_WDT1                                (1 << 4)
+#define OMAP24XX_EN_32KSYNC_SHIFT                       1
+#define OMAP24XX_EN_32KSYNC                             (1 << 1)
+
+/* CM_IDLEST_WKUP specific bits */
+#define OMAP2430_ST_ICR                                 (1 << 6)
+#define OMAP24XX_ST_OMAPCTRL                            (1 << 5)
+#define OMAP24XX_ST_WDT1                                (1 << 4)
+#define OMAP24XX_ST_MPU_WDT                             (1 << 3)
+#define OMAP24XX_ST_32KSYNC                             (1 << 1)
+
+/* CM_AUTOIDLE_WKUP */
+#define OMAP24XX_AUTO_OMAPCTRL                          (1 << 5)
+#define OMAP24XX_AUTO_WDT1                              (1 << 4)
+#define OMAP24XX_AUTO_MPU_WDT                           (1 << 3)
+#define OMAP24XX_AUTO_GPIOS                             (1 << 2)
+#define OMAP24XX_AUTO_32KSYNC                           (1 << 1)
+#define OMAP24XX_AUTO_GPT1                              (1 << 0)
+
+/* CM_CLKSEL_WKUP */
+#define OMAP24XX_CLKSEL_GPT1_SHIFT                      0
+#define OMAP24XX_CLKSEL_GPT1_MASK                       (0x3 << 0)
+
+/* CM_CLKEN_PLL */
+#define OMAP24XX_EN_54M_PLL_SHIFT                       6
+#define OMAP24XX_EN_54M_PLL_MASK                        (0x3 << 6)
+#define OMAP24XX_EN_96M_PLL_SHIFT                       2
+#define OMAP24XX_EN_96M_PLL_MASK                        (0x3 << 2)
+#define OMAP24XX_EN_DPLL_SHIFT                          0
+#define OMAP24XX_EN_DPLL_MASK                           (0x3 << 0)
+
+/* CM_IDLEST_CKGEN */
+#define OMAP24XX_ST_54M_APLL                            (1 << 9)
+#define OMAP24XX_ST_96M_APLL                            (1 << 8)
+#define OMAP24XX_ST_54M_CLK                             (1 << 6)
+#define OMAP24XX_ST_12M_CLK                             (1 << 5)
+#define OMAP24XX_ST_48M_CLK                             (1 << 4)
+#define OMAP24XX_ST_96M_CLK                             (1 << 2)
+#define OMAP24XX_ST_CORE_CLK_SHIFT                      0
+#define OMAP24XX_ST_CORE_CLK_MASK                       (0x3 << 0)
+
+/* CM_AUTOIDLE_PLL */
+#define OMAP24XX_AUTO_54M_SHIFT                         6
+#define OMAP24XX_AUTO_54M_MASK                          (0x3 << 6)
+#define OMAP24XX_AUTO_96M_SHIFT                         2
+#define OMAP24XX_AUTO_96M_MASK                          (0x3 << 2)
+#define OMAP24XX_AUTO_DPLL_SHIFT                        0
+#define OMAP24XX_AUTO_DPLL_MASK                         (0x3 << 0)
+
+/* CM_CLKSEL1_PLL */
+#define OMAP2430_MAXDPLLFASTLOCK_SHIFT                  28
+#define OMAP2430_MAXDPLLFASTLOCK_MASK                   (0x7 << 28)
+#define OMAP24XX_APLLS_CLKIN_SHIFT                      23
+#define OMAP24XX_APLLS_CLKIN_MASK                       (0x7 << 23)
+#define OMAP24XX_DPLL_MULT_SHIFT                        12
+#define OMAP24XX_DPLL_MULT_MASK                         (0x3ff << 12)
+#define OMAP24XX_DPLL_DIV_SHIFT                         8
+#define OMAP24XX_DPLL_DIV_MASK                          (0xf << 8)
+#define OMAP24XX_54M_SOURCE_SHIFT                       5
+#define OMAP24XX_54M_SOURCE                             (1 << 5)
+#define OMAP2430_96M_SOURCE_SHIFT                       4
+#define OMAP2430_96M_SOURCE                             (1 << 4)
+#define OMAP24XX_48M_SOURCE_SHIFT                       3
+#define OMAP24XX_48M_SOURCE                             (1 << 3)
+#define OMAP2430_ALTCLK_SOURCE_SHIFT                    0
+#define OMAP2430_ALTCLK_SOURCE_MASK                     (0x7 << 0)
+
+/* CM_CLKSEL2_PLL */
+#define OMAP24XX_CORE_CLK_SRC_SHIFT                     0
+#define OMAP24XX_CORE_CLK_SRC_MASK                      (0x3 << 0)
+
+/* CM_FCLKEN_DSP */
+#define OMAP2420_EN_IVA_COP_SHIFT                       10
+#define OMAP2420_EN_IVA_COP                             (1 << 10)
+#define OMAP2420_EN_IVA_MPU_SHIFT                       8
+#define OMAP2420_EN_IVA_MPU                             (1 << 8)
+#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT             0
+#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP                   (1 << 0)
+
+/* CM_ICLKEN_DSP */
+#define OMAP2420_EN_DSP_IPI_SHIFT                       1
+#define OMAP2420_EN_DSP_IPI                             (1 << 1)
+
+/* CM_IDLEST_DSP */
+#define OMAP2420_ST_IVA                                 (1 << 8)
+#define OMAP2420_ST_IPI                                 (1 << 1)
+#define OMAP24XX_ST_DSP                                 (1 << 0)
+
+/* CM_AUTOIDLE_DSP */
+#define OMAP2420_AUTO_DSP_IPI                           (1 << 1)
+
+/* CM_CLKSEL_DSP */
+#define OMAP2420_SYNC_IVA                               (1 << 13)
+#define OMAP2420_CLKSEL_IVA_SHIFT                       8
+#define OMAP2420_CLKSEL_IVA_MASK                        (0x1f << 8)
+#define OMAP24XX_SYNC_DSP                               (1 << 7)
+#define OMAP24XX_CLKSEL_DSP_IF_SHIFT                    5
+#define OMAP24XX_CLKSEL_DSP_IF_MASK                     (0x3 << 5)
+#define OMAP24XX_CLKSEL_DSP_SHIFT                       0
+#define OMAP24XX_CLKSEL_DSP_MASK                        (0x1f << 0)
+
+/* CM_CLKSTCTRL_DSP */
+#define OMAP2420_AUTOSTATE_IVA                          (1 << 8)
+#define OMAP24XX_AUTOSTATE_DSP                          (1 << 0)
+
+/* CM_FCLKEN_MDM */
+/* 2430 only */
+#define OMAP2430_EN_OSC_SHIFT                           1
+#define OMAP2430_EN_OSC                                 (1 << 1)
+
+/* CM_ICLKEN_MDM */
+/* 2430 only */
+#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT             0
+#define OMAP2430_CM_ICLKEN_MDM_EN_MDM                   (1 << 0)
+
+/* CM_IDLEST_MDM specific bits */
+/* 2430 only */
+
+/* CM_AUTOIDLE_MDM */
+/* 2430 only */
+#define OMAP2430_AUTO_OSC                               (1 << 1)
+#define OMAP2430_AUTO_MDM                               (1 << 0)
+
+/* CM_CLKSEL_MDM */
+/* 2430 only */
+#define OMAP2430_SYNC_MDM                               (1 << 4)
+#define OMAP2430_CLKSEL_MDM_SHIFT                       0
+#define OMAP2430_CLKSEL_MDM_MASK                        (0xf << 0)
+
+/* CM_CLKSTCTRL_MDM */
+/* 2430 only */
+#define OMAP2430_AUTOSTATE_MDM                          (1 << 0)
+
+#endif
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
new file mode 100644
index 000000000000..9249129a5f46
--- /dev/null
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -0,0 +1,673 @@
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
+
+/*
+ * OMAP3430 Clock Management register bits
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "cm.h"
+
+/* Bits shared between registers */
+
+/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
+#define OMAP3430ES2_EN_MMC3_MASK                        (1 << 30)
+#define OMAP3430ES2_EN_MMC3_SHIFT                       30
+#define OMAP3430_EN_MSPRO                               (1 << 23)
+#define OMAP3430_EN_MSPRO_SHIFT                         23
+#define OMAP3430_EN_HDQ                                 (1 << 22)
+#define OMAP3430_EN_HDQ_SHIFT                           22
+#define OMAP3430ES1_EN_FSHOSTUSB                        (1 << 5)
+#define OMAP3430ES1_EN_FSHOSTUSB_SHIFT                  5
+#define OMAP3430ES1_EN_D2D                              (1 << 3)
+#define OMAP3430ES1_EN_D2D_SHIFT                        3
+#define OMAP3430_EN_SSI                                 (1 << 0)
+#define OMAP3430_EN_SSI_SHIFT                           0
+
+/* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */
+#define OMAP3430ES2_EN_USBTLL_SHIFT                     2
+#define OMAP3430ES2_EN_USBTLL_MASK                      (1 << 2)
+
+/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
+#define OMAP3430_EN_WDT2                                (1 << 5)
+#define OMAP3430_EN_WDT2_SHIFT                          5
+
+/* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */
+#define OMAP3430_EN_CAM                                 (1 << 0)
+#define OMAP3430_EN_CAM_SHIFT                           0
+
+/* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */
+#define OMAP3430_EN_WDT3                                (1 << 12)
+#define OMAP3430_EN_WDT3_SHIFT                          12
+
+/* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */
+#define OMAP3430_OVERRIDE_ENABLE                        (1 << 19)
+
+
+/* Bits specific to each register */
+
+/* CM_FCLKEN_IVA2 */
+#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2                 (1 << 0)
+
+/* CM_CLKEN_PLL_IVA2 */
+#define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT               8
+#define OMAP3430_IVA2_DPLL_RAMPTIME_MASK                (0x3 << 8)
+#define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT                4
+#define OMAP3430_IVA2_DPLL_FREQSEL_MASK                 (0xf << 4)
+#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT          3
+#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK           (1 << 3)
+#define OMAP3430_EN_IVA2_DPLL_SHIFT                     0
+#define OMAP3430_EN_IVA2_DPLL_MASK                      (0x7 << 0)
+
+/* CM_IDLEST_IVA2 */
+#define OMAP3430_ST_IVA2                                (1 << 0)
+
+/* CM_IDLEST_PLL_IVA2 */
+#define OMAP3430_ST_IVA2_CLK                            (1 << 0)
+
+/* CM_AUTOIDLE_PLL_IVA2 */
+#define OMAP3430_AUTO_IVA2_DPLL_SHIFT                   0
+#define OMAP3430_AUTO_IVA2_DPLL_MASK                    (0x7 << 0)
+
+/* CM_CLKSEL1_PLL_IVA2 */
+#define OMAP3430_IVA2_CLK_SRC_SHIFT                     19
+#define OMAP3430_IVA2_CLK_SRC_MASK                      (0x3 << 19)
+#define OMAP3430_IVA2_DPLL_MULT_SHIFT                   8
+#define OMAP3430_IVA2_DPLL_MULT_MASK                    (0x7ff << 8)
+#define OMAP3430_IVA2_DPLL_DIV_SHIFT                    0
+#define OMAP3430_IVA2_DPLL_DIV_MASK                     (0x7f << 0)
+
+/* CM_CLKSEL2_PLL_IVA2 */
+#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT             0
+#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK              (0x1f << 0)
+
+/* CM_CLKSTCTRL_IVA2 */
+#define OMAP3430_CLKTRCTRL_IVA2_SHIFT                   0
+#define OMAP3430_CLKTRCTRL_IVA2_MASK                    (0x3 << 0)
+
+/* CM_CLKSTST_IVA2 */
+#define OMAP3430_CLKACTIVITY_IVA2                       (1 << 0)
+
+/* CM_REVISION specific bits */
+
+/* CM_SYSCONFIG specific bits */
+
+/* CM_CLKEN_PLL_MPU */
+#define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT                8
+#define OMAP3430_MPU_DPLL_RAMPTIME_MASK                 (0x3 << 8)
+#define OMAP3430_MPU_DPLL_FREQSEL_SHIFT                 4
+#define OMAP3430_MPU_DPLL_FREQSEL_MASK                  (0xf << 4)
+#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT           3
+#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK            (1 << 3)
+#define OMAP3430_EN_MPU_DPLL_SHIFT                      0
+#define OMAP3430_EN_MPU_DPLL_MASK                       (0x7 << 0)
+
+/* CM_IDLEST_MPU */
+#define OMAP3430_ST_MPU                                 (1 << 0)
+
+/* CM_IDLEST_PLL_MPU */
+#define OMAP3430_ST_MPU_CLK                             (1 << 0)
+#define OMAP3430_ST_IVA2_CLK_MASK                       (1 << 0)
+
+/* CM_IDLEST_PLL_MPU */
+#define OMAP3430_ST_MPU_CLK_MASK                        (1 << 0)
+
+/* CM_AUTOIDLE_PLL_MPU */
+#define OMAP3430_AUTO_MPU_DPLL_SHIFT                    0
+#define OMAP3430_AUTO_MPU_DPLL_MASK                     (0x7 << 0)
+
+/* CM_CLKSEL1_PLL_MPU */
+#define OMAP3430_MPU_CLK_SRC_SHIFT                      19
+#define OMAP3430_MPU_CLK_SRC_MASK                       (0x3 << 19)
+#define OMAP3430_MPU_DPLL_MULT_SHIFT                    8
+#define OMAP3430_MPU_DPLL_MULT_MASK                     (0x7ff << 8)
+#define OMAP3430_MPU_DPLL_DIV_SHIFT                     0
+#define OMAP3430_MPU_DPLL_DIV_MASK                      (0x7f << 0)
+
+/* CM_CLKSEL2_PLL_MPU */
+#define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT              0
+#define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK               (0x1f << 0)
+
+/* CM_CLKSTCTRL_MPU */
+#define OMAP3430_CLKTRCTRL_MPU_SHIFT                    0
+#define OMAP3430_CLKTRCTRL_MPU_MASK                     (0x3 << 0)
+
+/* CM_CLKSTST_MPU */
+#define OMAP3430_CLKACTIVITY_MPU                        (1 << 0)
+
+/* CM_FCLKEN1_CORE specific bits */
+
+/* CM_ICLKEN1_CORE specific bits */
+#define OMAP3430_EN_ICR                                 (1 << 29)
+#define OMAP3430_EN_ICR_SHIFT                           29
+#define OMAP3430_EN_AES2                                (1 << 28)
+#define OMAP3430_EN_AES2_SHIFT                          28
+#define OMAP3430_EN_SHA12                               (1 << 27)
+#define OMAP3430_EN_SHA12_SHIFT                         27
+#define OMAP3430_EN_DES2                                (1 << 26)
+#define OMAP3430_EN_DES2_SHIFT                          26
+#define OMAP3430ES1_EN_FAC                              (1 << 8)
+#define OMAP3430ES1_EN_FAC_SHIFT                        8
+#define OMAP3430_EN_MAILBOXES                           (1 << 7)
+#define OMAP3430_EN_MAILBOXES_SHIFT                     7
+#define OMAP3430_EN_OMAPCTRL                            (1 << 6)
+#define OMAP3430_EN_OMAPCTRL_SHIFT                      6
+#define OMAP3430_EN_SDRC                                (1 << 1)
+#define OMAP3430_EN_SDRC_SHIFT                          1
+
+/* CM_ICLKEN2_CORE */
+#define OMAP3430_EN_PKA                                 (1 << 4)
+#define OMAP3430_EN_PKA_SHIFT                           4
+#define OMAP3430_EN_AES1                                (1 << 3)
+#define OMAP3430_EN_AES1_SHIFT                          3
+#define OMAP3430_EN_RNG                                 (1 << 2)
+#define OMAP3430_EN_RNG_SHIFT                           2
+#define OMAP3430_EN_SHA11                               (1 << 1)
+#define OMAP3430_EN_SHA11_SHIFT                         1
+#define OMAP3430_EN_DES1                                (1 << 0)
+#define OMAP3430_EN_DES1_SHIFT                          0
+
+/* CM_FCLKEN3_CORE specific bits */
+#define OMAP3430ES2_EN_TS_SHIFT                         1
+#define OMAP3430ES2_EN_TS_MASK                          (1 << 1)
+#define OMAP3430ES2_EN_CPEFUSE_SHIFT                    0
+#define OMAP3430ES2_EN_CPEFUSE_MASK                     (1 << 0)
+
+/* CM_IDLEST1_CORE specific bits */
+#define OMAP3430_ST_ICR                                 (1 << 29)
+#define OMAP3430_ST_AES2                                (1 << 28)
+#define OMAP3430_ST_SHA12                               (1 << 27)
+#define OMAP3430_ST_DES2                                (1 << 26)
+#define OMAP3430_ST_MSPRO                               (1 << 23)
+#define OMAP3430_ST_HDQ                                 (1 << 22)
+#define OMAP3430ES1_ST_FAC                              (1 << 8)
+#define OMAP3430ES1_ST_MAILBOXES                        (1 << 7)
+#define OMAP3430_ST_OMAPCTRL                            (1 << 6)
+#define OMAP3430_ST_SDMA                                (1 << 2)
+#define OMAP3430_ST_SDRC                                (1 << 1)
+#define OMAP3430_ST_SSI                                 (1 << 0)
+
+/* CM_IDLEST2_CORE */
+#define OMAP3430_ST_PKA                                 (1 << 4)
+#define OMAP3430_ST_AES1                                (1 << 3)
+#define OMAP3430_ST_RNG                                 (1 << 2)
+#define OMAP3430_ST_SHA11                               (1 << 1)
+#define OMAP3430_ST_DES1                                (1 << 0)
+
+/* CM_IDLEST3_CORE */
+#define OMAP3430ES2_ST_USBTLL_SHIFT                     2
+#define OMAP3430ES2_ST_USBTLL_MASK                      (1 << 2)
+
+/* CM_AUTOIDLE1_CORE */
+#define OMAP3430_AUTO_AES2                              (1 << 28)
+#define OMAP3430_AUTO_AES2_SHIFT                        28
+#define OMAP3430_AUTO_SHA12                             (1 << 27)
+#define OMAP3430_AUTO_SHA12_SHIFT                       27
+#define OMAP3430_AUTO_DES2                              (1 << 26)
+#define OMAP3430_AUTO_DES2_SHIFT                        26
+#define OMAP3430_AUTO_MMC2                              (1 << 25)
+#define OMAP3430_AUTO_MMC2_SHIFT                        25
+#define OMAP3430_AUTO_MMC1                              (1 << 24)
+#define OMAP3430_AUTO_MMC1_SHIFT                        24
+#define OMAP3430_AUTO_MSPRO                             (1 << 23)
+#define OMAP3430_AUTO_MSPRO_SHIFT                       23
+#define OMAP3430_AUTO_HDQ                               (1 << 22)
+#define OMAP3430_AUTO_HDQ_SHIFT                         22
+#define OMAP3430_AUTO_MCSPI4                            (1 << 21)
+#define OMAP3430_AUTO_MCSPI4_SHIFT                      21
+#define OMAP3430_AUTO_MCSPI3                            (1 << 20)
+#define OMAP3430_AUTO_MCSPI3_SHIFT                      20
+#define OMAP3430_AUTO_MCSPI2                            (1 << 19)
+#define OMAP3430_AUTO_MCSPI2_SHIFT                      19
+#define OMAP3430_AUTO_MCSPI1                            (1 << 18)
+#define OMAP3430_AUTO_MCSPI1_SHIFT                      18
+#define OMAP3430_AUTO_I2C3                              (1 << 17)
+#define OMAP3430_AUTO_I2C3_SHIFT                        17
+#define OMAP3430_AUTO_I2C2                              (1 << 16)
+#define OMAP3430_AUTO_I2C2_SHIFT                        16
+#define OMAP3430_AUTO_I2C1                              (1 << 15)
+#define OMAP3430_AUTO_I2C1_SHIFT                        15
+#define OMAP3430_AUTO_UART2                             (1 << 14)
+#define OMAP3430_AUTO_UART2_SHIFT                       14
+#define OMAP3430_AUTO_UART1                             (1 << 13)
+#define OMAP3430_AUTO_UART1_SHIFT                       13
+#define OMAP3430_AUTO_GPT11                             (1 << 12)
+#define OMAP3430_AUTO_GPT11_SHIFT                       12
+#define OMAP3430_AUTO_GPT10                             (1 << 11)
+#define OMAP3430_AUTO_GPT10_SHIFT                       11
+#define OMAP3430_AUTO_MCBSP5                            (1 << 10)
+#define OMAP3430_AUTO_MCBSP5_SHIFT                      10
+#define OMAP3430_AUTO_MCBSP1                            (1 << 9)
+#define OMAP3430_AUTO_MCBSP1_SHIFT                      9
+#define OMAP3430ES1_AUTO_FAC                            (1 << 8)
+#define OMAP3430ES1_AUTO_FAC_SHIFT                      8
+#define OMAP3430_AUTO_MAILBOXES                         (1 << 7)
+#define OMAP3430_AUTO_MAILBOXES_SHIFT                   7
+#define OMAP3430_AUTO_OMAPCTRL                          (1 << 6)
+#define OMAP3430_AUTO_OMAPCTRL_SHIFT                    6
+#define OMAP3430ES1_AUTO_FSHOSTUSB                      (1 << 5)
+#define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT                5
+#define OMAP3430_AUTO_HSOTGUSB                          (1 << 4)
+#define OMAP3430_AUTO_HSOTGUSB_SHIFT                    4
+#define OMAP3430ES1_AUTO_D2D                            (1 << 3)
+#define OMAP3430ES1_AUTO_D2D_SHIFT                      3
+#define OMAP3430_AUTO_SSI                               (1 << 0)
+#define OMAP3430_AUTO_SSI_SHIFT                         0
+
+/* CM_AUTOIDLE2_CORE */
+#define OMAP3430_AUTO_PKA                               (1 << 4)
+#define OMAP3430_AUTO_PKA_SHIFT                         4
+#define OMAP3430_AUTO_AES1                              (1 << 3)
+#define OMAP3430_AUTO_AES1_SHIFT                        3
+#define OMAP3430_AUTO_RNG                               (1 << 2)
+#define OMAP3430_AUTO_RNG_SHIFT                         2
+#define OMAP3430_AUTO_SHA11                             (1 << 1)
+#define OMAP3430_AUTO_SHA11_SHIFT                       1
+#define OMAP3430_AUTO_DES1                              (1 << 0)
+#define OMAP3430_AUTO_DES1_SHIFT                        0
+
+/* CM_AUTOIDLE3_CORE */
+#define OMAP3430ES2_AUTO_USBTLL_SHIFT                   2
+#define OMAP3430ES2_AUTO_USBTLL_MASK                    (1 << 2)
+
+/* CM_CLKSEL_CORE */
+#define OMAP3430_CLKSEL_SSI_SHIFT                       8
+#define OMAP3430_CLKSEL_SSI_MASK                        (0xf << 8)
+#define OMAP3430_CLKSEL_GPT11_MASK                      (1 << 7)
+#define OMAP3430_CLKSEL_GPT11_SHIFT                     7
+#define OMAP3430_CLKSEL_GPT10_MASK                      (1 << 6)
+#define OMAP3430_CLKSEL_GPT10_SHIFT                     6
+#define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT              4
+#define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK               (0x3 << 4)
+#define OMAP3430_CLKSEL_L4_SHIFT                        2
+#define OMAP3430_CLKSEL_L4_MASK                         (0x3 << 2)
+#define OMAP3430_CLKSEL_L3_SHIFT                        0
+#define OMAP3430_CLKSEL_L3_MASK                         (0x3 << 0)
+
+/* CM_CLKSTCTRL_CORE */
+#define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT                 4
+#define OMAP3430ES1_CLKTRCTRL_D2D_MASK                  (0x3 << 4)
+#define OMAP3430_CLKTRCTRL_L4_SHIFT                     2
+#define OMAP3430_CLKTRCTRL_L4_MASK                      (0x3 << 2)
+#define OMAP3430_CLKTRCTRL_L3_SHIFT                     0
+#define OMAP3430_CLKTRCTRL_L3_MASK                      (0x3 << 0)
+
+/* CM_CLKSTST_CORE */
+#define OMAP3430ES1_CLKACTIVITY_D2D                     (1 << 2)
+#define OMAP3430_CLKACTIVITY_L4                         (1 << 1)
+#define OMAP3430_CLKACTIVITY_L3                         (1 << 0)
+
+/* CM_FCLKEN_GFX */
+#define OMAP3430ES1_EN_3D                               (1 << 2)
+#define OMAP3430ES1_EN_3D_SHIFT                         2
+#define OMAP3430ES1_EN_2D                               (1 << 1)
+#define OMAP3430ES1_EN_2D_SHIFT                         1
+
+/* CM_ICLKEN_GFX specific bits */
+
+/* CM_IDLEST_GFX specific bits */
+
+/* CM_CLKSEL_GFX specific bits */
+
+/* CM_SLEEPDEP_GFX specific bits */
+
+/* CM_CLKSTCTRL_GFX */
+#define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT                 0
+#define OMAP3430ES1_CLKTRCTRL_GFX_MASK                  (0x3 << 0)
+
+/* CM_CLKSTST_GFX */
+#define OMAP3430ES1_CLKACTIVITY_GFX                     (1 << 0)
+
+/* CM_FCLKEN_SGX */
+#define OMAP3430ES2_EN_SGX_SHIFT                        1
+#define OMAP3430ES2_EN_SGX_MASK                         (1 << 1)
+
+/* CM_CLKSEL_SGX */
+#define OMAP3430ES2_CLKSEL_SGX_SHIFT                    0
+#define OMAP3430ES2_CLKSEL_SGX_MASK                     (0x7 << 0)
+
+/* CM_FCLKEN_WKUP specific bits */
+#define OMAP3430ES2_EN_USIMOCP_SHIFT                    9
+
+/* CM_ICLKEN_WKUP specific bits */
+#define OMAP3430_EN_WDT1                                (1 << 4)
+#define OMAP3430_EN_WDT1_SHIFT                          4
+#define OMAP3430_EN_32KSYNC                             (1 << 2)
+#define OMAP3430_EN_32KSYNC_SHIFT                       2
+
+/* CM_IDLEST_WKUP specific bits */
+#define OMAP3430_ST_WDT2                                (1 << 5)
+#define OMAP3430_ST_WDT1                                (1 << 4)
+#define OMAP3430_ST_32KSYNC                             (1 << 2)
+
+/* CM_AUTOIDLE_WKUP */
+#define OMAP3430_AUTO_WDT2                              (1 << 5)
+#define OMAP3430_AUTO_WDT2_SHIFT                        5
+#define OMAP3430_AUTO_WDT1                              (1 << 4)
+#define OMAP3430_AUTO_WDT1_SHIFT                        4
+#define OMAP3430_AUTO_GPIO1                             (1 << 3)
+#define OMAP3430_AUTO_GPIO1_SHIFT                       3
+#define OMAP3430_AUTO_32KSYNC                           (1 << 2)
+#define OMAP3430_AUTO_32KSYNC_SHIFT                     2
+#define OMAP3430_AUTO_GPT12                             (1 << 1)
+#define OMAP3430_AUTO_GPT12_SHIFT                       1
+#define OMAP3430_AUTO_GPT1                              (1 << 0)
+#define OMAP3430_AUTO_GPT1_SHIFT                        0
+
+/* CM_CLKSEL_WKUP */
+#define OMAP3430ES2_CLKSEL_USIMOCP_MASK                 (0xf << 3)
+#define OMAP3430_CLKSEL_RM_SHIFT                        1
+#define OMAP3430_CLKSEL_RM_MASK                         (0x3 << 1)
+#define OMAP3430_CLKSEL_GPT1_SHIFT                      0
+#define OMAP3430_CLKSEL_GPT1_MASK                       (1 << 0)
+
+/* CM_CLKEN_PLL */
+#define OMAP3430_PWRDN_EMU_PERIPH_SHIFT                 31
+#define OMAP3430_PWRDN_CAM_SHIFT                        30
+#define OMAP3430_PWRDN_DSS1_SHIFT                       29
+#define OMAP3430_PWRDN_TV_SHIFT                         28
+#define OMAP3430_PWRDN_96M_SHIFT                        27
+#define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT             24
+#define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK              (0x3 << 24)
+#define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT              20
+#define OMAP3430_PERIPH_DPLL_FREQSEL_MASK               (0xf << 20)
+#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT        19
+#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK         (1 << 19)
+#define OMAP3430_EN_PERIPH_DPLL_SHIFT                   16
+#define OMAP3430_EN_PERIPH_DPLL_MASK                    (0x7 << 16)
+#define OMAP3430_PWRDN_EMU_CORE_SHIFT                   12
+#define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT               8
+#define OMAP3430_CORE_DPLL_RAMPTIME_MASK                (0x3 << 8)
+#define OMAP3430_CORE_DPLL_FREQSEL_SHIFT                4
+#define OMAP3430_CORE_DPLL_FREQSEL_MASK                 (0xf << 4)
+#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT          3
+#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK           (1 << 3)
+#define OMAP3430_EN_CORE_DPLL_SHIFT                     0
+#define OMAP3430_EN_CORE_DPLL_MASK                      (0x7 << 0)
+
+/* CM_CLKEN2_PLL */
+#define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT                10
+#define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK          (0x3 << 8)
+#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT          4
+#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK           (0xf << 4)
+#define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT    3
+#define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT               0
+#define OMAP3430ES2_EN_PERIPH2_DPLL_MASK                (0x7 << 0)
+
+/* CM_IDLEST_CKGEN */
+#define OMAP3430_ST_54M_CLK                             (1 << 5)
+#define OMAP3430_ST_12M_CLK                             (1 << 4)
+#define OMAP3430_ST_48M_CLK                             (1 << 3)
+#define OMAP3430_ST_96M_CLK                             (1 << 2)
+#define OMAP3430_ST_PERIPH_CLK                          (1 << 1)
+#define OMAP3430_ST_CORE_CLK                            (1 << 0)
+
+/* CM_IDLEST2_CKGEN */
+#define OMAP3430ES2_ST_120M_CLK_SHIFT                   1
+#define OMAP3430ES2_ST_120M_CLK_MASK                    (1 << 1)
+#define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT                0
+#define OMAP3430ES2_ST_PERIPH2_CLK_MASK                 (1 << 0)
+
+/* CM_AUTOIDLE_PLL */
+#define OMAP3430_AUTO_PERIPH_DPLL_SHIFT                 3
+#define OMAP3430_AUTO_PERIPH_DPLL_MASK                  (0x7 << 3)
+#define OMAP3430_AUTO_CORE_DPLL_SHIFT                   0
+#define OMAP3430_AUTO_CORE_DPLL_MASK                    (0x7 << 0)
+
+/* CM_CLKSEL1_PLL */
+/* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */
+#define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT             27
+#define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK              (0x1f << 27)
+#define OMAP3430_CORE_DPLL_MULT_SHIFT                   16
+#define OMAP3430_CORE_DPLL_MULT_MASK                    (0x7ff << 16)
+#define OMAP3430_CORE_DPLL_DIV_SHIFT                    8
+#define OMAP3430_CORE_DPLL_DIV_MASK                     (0x7f << 8)
+#define OMAP3430_SOURCE_54M                             (1 << 5)
+#define OMAP3430_SOURCE_48M                             (1 << 3)
+
+/* CM_CLKSEL2_PLL */
+#define OMAP3430_PERIPH_DPLL_MULT_SHIFT                 8
+#define OMAP3430_PERIPH_DPLL_MULT_MASK                  (0x7ff << 8)
+#define OMAP3430_PERIPH_DPLL_DIV_SHIFT                  0
+#define OMAP3430_PERIPH_DPLL_DIV_MASK                   (0x7f << 0)
+
+/* CM_CLKSEL3_PLL */
+#define OMAP3430_DIV_96M_SHIFT                          0
+#define OMAP3430_DIV_96M_MASK                           (0x1f << 0)
+
+/* CM_CLKSEL4_PLL */
+#define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT             8
+#define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK              (0x7ff << 8)
+#define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT              0
+#define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK               (0x7f << 0)
+
+/* CM_CLKSEL5_PLL */
+#define OMAP3430ES2_DIV_120M_SHIFT                      0
+#define OMAP3430ES2_DIV_120M_MASK                       (0x1f << 0)
+
+/* CM_CLKOUT_CTRL */
+#define OMAP3430_CLKOUT2_EN_SHIFT                       7
+#define OMAP3430_CLKOUT2_EN                             (1 << 7)
+#define OMAP3430_CLKOUT2_DIV_SHIFT                      3
+#define OMAP3430_CLKOUT2_DIV_MASK                       (0x7 << 3)
+#define OMAP3430_CLKOUT2SOURCE_SHIFT                    0
+#define OMAP3430_CLKOUT2SOURCE_MASK                     (0x3 << 0)
+
+/* CM_FCLKEN_DSS */
+#define OMAP3430_EN_TV                                  (1 << 2)
+#define OMAP3430_EN_TV_SHIFT                            2
+#define OMAP3430_EN_DSS2                                (1 << 1)
+#define OMAP3430_EN_DSS2_SHIFT                          1
+#define OMAP3430_EN_DSS1                                (1 << 0)
+#define OMAP3430_EN_DSS1_SHIFT                          0
+
+/* CM_ICLKEN_DSS */
+#define OMAP3430_CM_ICLKEN_DSS_EN_DSS                   (1 << 0)
+#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT             0
+
+/* CM_IDLEST_DSS */
+#define OMAP3430_ST_DSS                                 (1 << 0)
+
+/* CM_AUTOIDLE_DSS */
+#define OMAP3430_AUTO_DSS                               (1 << 0)
+#define OMAP3430_AUTO_DSS_SHIFT                         0
+
+/* CM_CLKSEL_DSS */
+#define OMAP3430_CLKSEL_TV_SHIFT                        8
+#define OMAP3430_CLKSEL_TV_MASK                         (0x1f << 8)
+#define OMAP3430_CLKSEL_DSS1_SHIFT                      0
+#define OMAP3430_CLKSEL_DSS1_MASK                       (0x1f << 0)
+
+/* CM_SLEEPDEP_DSS specific bits */
+
+/* CM_CLKSTCTRL_DSS */
+#define OMAP3430_CLKTRCTRL_DSS_SHIFT                    0
+#define OMAP3430_CLKTRCTRL_DSS_MASK                     (0x3 << 0)
+
+/* CM_CLKSTST_DSS */
+#define OMAP3430_CLKACTIVITY_DSS                        (1 << 0)
+
+/* CM_FCLKEN_CAM specific bits */
+
+/* CM_ICLKEN_CAM specific bits */
+
+/* CM_IDLEST_CAM */
+#define OMAP3430_ST_CAM                                 (1 << 0)
+
+/* CM_AUTOIDLE_CAM */
+#define OMAP3430_AUTO_CAM                               (1 << 0)
+#define OMAP3430_AUTO_CAM_SHIFT                         0
+
+/* CM_CLKSEL_CAM */
+#define OMAP3430_CLKSEL_CAM_SHIFT                       0
+#define OMAP3430_CLKSEL_CAM_MASK                        (0x1f << 0)
+
+/* CM_SLEEPDEP_CAM specific bits */
+
+/* CM_CLKSTCTRL_CAM */
+#define OMAP3430_CLKTRCTRL_CAM_SHIFT                    0
+#define OMAP3430_CLKTRCTRL_CAM_MASK                     (0x3 << 0)
+
+/* CM_CLKSTST_CAM */
+#define OMAP3430_CLKACTIVITY_CAM                        (1 << 0)
+
+/* CM_FCLKEN_PER specific bits */
+
+/* CM_ICLKEN_PER specific bits */
+
+/* CM_IDLEST_PER */
+#define OMAP3430_ST_WDT3                                (1 << 12)
+#define OMAP3430_ST_MCBSP4                              (1 << 2)
+#define OMAP3430_ST_MCBSP3                              (1 << 1)
+#define OMAP3430_ST_MCBSP2                              (1 << 0)
+
+/* CM_AUTOIDLE_PER */
+#define OMAP3430_AUTO_GPIO6                             (1 << 17)
+#define OMAP3430_AUTO_GPIO6_SHIFT                       17
+#define OMAP3430_AUTO_GPIO5                             (1 << 16)
+#define OMAP3430_AUTO_GPIO5_SHIFT                       16
+#define OMAP3430_AUTO_GPIO4                             (1 << 15)
+#define OMAP3430_AUTO_GPIO4_SHIFT                       15
+#define OMAP3430_AUTO_GPIO3                             (1 << 14)
+#define OMAP3430_AUTO_GPIO3_SHIFT                       14
+#define OMAP3430_AUTO_GPIO2                             (1 << 13)
+#define OMAP3430_AUTO_GPIO2_SHIFT                       13
+#define OMAP3430_AUTO_WDT3                              (1 << 12)
+#define OMAP3430_AUTO_WDT3_SHIFT                        12
+#define OMAP3430_AUTO_UART3                             (1 << 11)
+#define OMAP3430_AUTO_UART3_SHIFT                       11
+#define OMAP3430_AUTO_GPT9                              (1 << 10)
+#define OMAP3430_AUTO_GPT9_SHIFT                        10
+#define OMAP3430_AUTO_GPT8                              (1 << 9)
+#define OMAP3430_AUTO_GPT8_SHIFT                        9
+#define OMAP3430_AUTO_GPT7                              (1 << 8)
+#define OMAP3430_AUTO_GPT7_SHIFT                        8
+#define OMAP3430_AUTO_GPT6                              (1 << 7)
+#define OMAP3430_AUTO_GPT6_SHIFT                        7
+#define OMAP3430_AUTO_GPT5                              (1 << 6)
+#define OMAP3430_AUTO_GPT5_SHIFT                        6
+#define OMAP3430_AUTO_GPT4                              (1 << 5)
+#define OMAP3430_AUTO_GPT4_SHIFT                        5
+#define OMAP3430_AUTO_GPT3                              (1 << 4)
+#define OMAP3430_AUTO_GPT3_SHIFT                        4
+#define OMAP3430_AUTO_GPT2                              (1 << 3)
+#define OMAP3430_AUTO_GPT2_SHIFT                        3
+#define OMAP3430_AUTO_MCBSP4                            (1 << 2)
+#define OMAP3430_AUTO_MCBSP4_SHIFT                      2
+#define OMAP3430_AUTO_MCBSP3                            (1 << 1)
+#define OMAP3430_AUTO_MCBSP3_SHIFT                      1
+#define OMAP3430_AUTO_MCBSP2                            (1 << 0)
+#define OMAP3430_AUTO_MCBSP2_SHIFT                      0
+
+/* CM_CLKSEL_PER */
+#define OMAP3430_CLKSEL_GPT9_MASK                       (1 << 7)
+#define OMAP3430_CLKSEL_GPT9_SHIFT                      7
+#define OMAP3430_CLKSEL_GPT8_MASK                       (1 << 6)
+#define OMAP3430_CLKSEL_GPT8_SHIFT                      6
+#define OMAP3430_CLKSEL_GPT7_MASK                       (1 << 5)
+#define OMAP3430_CLKSEL_GPT7_SHIFT                      5
+#define OMAP3430_CLKSEL_GPT6_MASK                       (1 << 4)
+#define OMAP3430_CLKSEL_GPT6_SHIFT                      4
+#define OMAP3430_CLKSEL_GPT5_MASK                       (1 << 3)
+#define OMAP3430_CLKSEL_GPT5_SHIFT                      3
+#define OMAP3430_CLKSEL_GPT4_MASK                       (1 << 2)
+#define OMAP3430_CLKSEL_GPT4_SHIFT                      2
+#define OMAP3430_CLKSEL_GPT3_MASK                       (1 << 1)
+#define OMAP3430_CLKSEL_GPT3_SHIFT                      1
+#define OMAP3430_CLKSEL_GPT2_MASK                       (1 << 0)
+#define OMAP3430_CLKSEL_GPT2_SHIFT                      0
+
+/* CM_SLEEPDEP_PER specific bits */
+#define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2                (1 << 2)
+
+/* CM_CLKSTCTRL_PER */
+#define OMAP3430_CLKTRCTRL_PER_SHIFT                    0
+#define OMAP3430_CLKTRCTRL_PER_MASK                     (0x3 << 0)
+
+/* CM_CLKSTST_PER */
+#define OMAP3430_CLKACTIVITY_PER                        (1 << 0)
+
+/* CM_CLKSEL1_EMU */
+#define OMAP3430_DIV_DPLL4_SHIFT                        24
+#define OMAP3430_DIV_DPLL4_MASK                         (0x1f << 24)
+#define OMAP3430_DIV_DPLL3_SHIFT                        16
+#define OMAP3430_DIV_DPLL3_MASK                         (0x1f << 16)
+#define OMAP3430_CLKSEL_TRACECLK_SHIFT                  11
+#define OMAP3430_CLKSEL_TRACECLK_MASK                   (0x7 << 11)
+#define OMAP3430_CLKSEL_PCLK_SHIFT                      8
+#define OMAP3430_CLKSEL_PCLK_MASK                       (0x7 << 8)
+#define OMAP3430_CLKSEL_PCLKX2_SHIFT                    6
+#define OMAP3430_CLKSEL_PCLKX2_MASK                     (0x3 << 6)
+#define OMAP3430_CLKSEL_ATCLK_SHIFT                     4
+#define OMAP3430_CLKSEL_ATCLK_MASK                      (0x3 << 4)
+#define OMAP3430_TRACE_MUX_CTRL_SHIFT                   2
+#define OMAP3430_TRACE_MUX_CTRL_MASK                    (0x3 << 2)
+#define OMAP3430_MUX_CTRL_SHIFT                         0
+#define OMAP3430_MUX_CTRL_MASK                          (0x3 << 0)
+
+/* CM_CLKSTCTRL_EMU */
+#define OMAP3430_CLKTRCTRL_EMU_SHIFT                    0
+#define OMAP3430_CLKTRCTRL_EMU_MASK                     (0x3 << 0)
+
+/* CM_CLKSTST_EMU */
+#define OMAP3430_CLKACTIVITY_EMU                        (1 << 0)
+
+/* CM_CLKSEL2_EMU specific bits */
+#define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT               8
+#define OMAP3430_CORE_DPLL_EMU_MULT_MASK                (0x7ff << 8)
+#define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT                0
+#define OMAP3430_CORE_DPLL_EMU_DIV_MASK                 (0x7f << 0)
+
+/* CM_CLKSEL3_EMU specific bits */
+#define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT             8
+#define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK              (0x7ff << 8)
+#define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT              0
+#define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK               (0x7f << 0)
+
+/* CM_POLCTRL */
+#define OMAP3430_CLKOUT2_POL                            (1 << 0)
+
+/* CM_IDLEST_NEON */
+#define OMAP3430_ST_NEON                                (1 << 0)
+
+/* CM_CLKSTCTRL_NEON */
+#define OMAP3430_CLKTRCTRL_NEON_SHIFT                   0
+#define OMAP3430_CLKTRCTRL_NEON_MASK                    (0x3 << 0)
+
+/* CM_FCLKEN_USBHOST */
+#define OMAP3430ES2_EN_USBHOST2_SHIFT                   1
+#define OMAP3430ES2_EN_USBHOST2_MASK                    (1 << 1)
+#define OMAP3430ES2_EN_USBHOST1_SHIFT                   0
+#define OMAP3430ES2_EN_USBHOST1_MASK                    (1 << 0)
+
+/* CM_ICLKEN_USBHOST */
+#define OMAP3430ES2_EN_USBHOST_SHIFT                    0
+#define OMAP3430ES2_EN_USBHOST_MASK                     (1 << 0)
+
+/* CM_IDLEST_USBHOST */
+
+/* CM_AUTOIDLE_USBHOST */
+#define OMAP3430ES2_AUTO_USBHOST_SHIFT                  0
+#define OMAP3430ES2_AUTO_USBHOST_MASK                   (1 << 0)
+
+/* CM_SLEEPDEP_USBHOST */
+#define OMAP3430ES2_EN_MPU_SHIFT                        1
+#define OMAP3430ES2_EN_MPU_MASK                         (1 << 1)
+#define OMAP3430ES2_EN_IVA2_SHIFT                       2
+#define OMAP3430ES2_EN_IVA2_MASK                        (1 << 2)
+
+/* CM_CLKSTCTRL_USBHOST */
+#define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT             0
+#define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK              (3 << 0)
+
+
+
+#endif
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
new file mode 100644
index 000000000000..8489f3029fed
--- /dev/null
+++ b/arch/arm/mach-omap2/cm.h
@@ -0,0 +1,124 @@
+#ifndef __ARCH_ASM_MACH_OMAP2_CM_H
+#define __ARCH_ASM_MACH_OMAP2_CM_H
+
+/*
+ * OMAP2/3 Clock Management (CM) register definitions
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "prcm-common.h"
+
+#ifndef __ASSEMBLER__
+#define OMAP_CM_REGADDR(module, reg)                                    \
+        (void __iomem *)IO_ADDRESS(OMAP2_CM_BASE + (module) + (reg))
+#else
+#define OMAP2420_CM_REGADDR(module, reg)                                \
+                        IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
+#define OMAP2430_CM_REGADDR(module, reg)                                \
+                        IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
+#define OMAP34XX_CM_REGADDR(module, reg)                                \
+                        IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
+#endif
+
+/*
+ * Architecture-specific global CM registers
+ * Use cm_{read,write}_reg() with these registers.
+ * These registers appear once per CM module.
+ */
+
+#define OMAP3430_CM_REVISION            OMAP_CM_REGADDR(OCP_MOD, 0x0000)
+#define OMAP3430_CM_SYSCONFIG           OMAP_CM_REGADDR(OCP_MOD, 0x0010)
+#define OMAP3430_CM_POLCTRL             OMAP_CM_REGADDR(OCP_MOD, 0x009c)
+
+#define OMAP3430_CM_CLKOUT_CTRL         OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
+
+/*
+ * Module specific CM registers from CM_BASE + domain offset
+ * Use cm_{read,write}_mod_reg() with these registers.
+ * These register offsets generally appear in more than one PRCM submodule.
+ */
+
+/* Common between 24xx and 34xx */
+
+#define CM_FCLKEN                                       0x0000
+#define CM_FCLKEN1                                      CM_FCLKEN
+#define CM_CLKEN                                        CM_FCLKEN
+#define CM_ICLKEN                                       0x0010
+#define CM_ICLKEN1                                      CM_ICLKEN
+#define CM_ICLKEN2                                      0x0014
+#define CM_ICLKEN3                                      0x0018
+#define CM_IDLEST                                       0x0020
+#define CM_IDLEST1                                      CM_IDLEST
+#define CM_IDLEST2                                      0x0024
+#define CM_AUTOIDLE                                     0x0030
+#define CM_AUTOIDLE1                                    CM_AUTOIDLE
+#define CM_AUTOIDLE2                                    0x0034
+#define CM_AUTOIDLE3                                    0x0038
+#define CM_CLKSEL                                       0x0040
+#define CM_CLKSEL1                                      CM_CLKSEL
+#define CM_CLKSEL2                                      0x0044
+#define CM_CLKSTCTRL                                    0x0048
+
+
+/* Architecture-specific registers */
+
+#define OMAP24XX_CM_FCLKEN2                             0x0004
+#define OMAP24XX_CM_ICLKEN4                             0x001c
+#define OMAP24XX_CM_AUTOIDLE4                           0x003c
+
+#define OMAP2430_CM_IDLEST3                             0x0028
+
+#define OMAP3430_CM_CLKEN_PLL                           0x0004
+#define OMAP3430ES2_CM_CLKEN2                           0x0004
+#define OMAP3430ES2_CM_FCLKEN3                          0x0008
+#define OMAP3430_CM_IDLEST_PLL                          CM_IDLEST2
+#define OMAP3430_CM_AUTOIDLE_PLL                        CM_AUTOIDLE2
+#define OMAP3430_CM_CLKSEL1                             CM_CLKSEL
+#define OMAP3430_CM_CLKSEL1_PLL                         CM_CLKSEL
+#define OMAP3430_CM_CLKSEL2_PLL                         CM_CLKSEL2
+#define OMAP3430_CM_SLEEPDEP                            CM_CLKSEL2
+#define OMAP3430_CM_CLKSEL3                             CM_CLKSTCTRL
+#define OMAP3430_CM_CLKSTST                             0x004c
+#define OMAP3430ES2_CM_CLKSEL4                          0x004c
+#define OMAP3430ES2_CM_CLKSEL5                          0x0050
+#define OMAP3430_CM_CLKSEL2_EMU                         0x0050
+#define OMAP3430_CM_CLKSEL3_EMU                         0x0054
+
+
+/* Clock management domain register get/set */
+
+#ifndef __ASSEMBLER__
+static inline void cm_write_mod_reg(u32 val, s16 module, s16 idx)
+{
+        __raw_writel(val, OMAP_CM_REGADDR(module, idx));
+}
+
+static inline u32 cm_read_mod_reg(s16 module, s16 idx)
+{
+        return __raw_readl(OMAP_CM_REGADDR(module, idx));
+}
+#endif
+
+/* CM register bits shared between 24XX and 3430 */
+
+/* CM_CLKSEL_GFX */
+#define OMAP_CLKSEL_GFX_SHIFT                           0
+#define OMAP_CLKSEL_GFX_MASK                            (0x7 << 0)
+
+/* CM_ICLKEN_GFX */
+#define OMAP_EN_GFX_SHIFT                               0
+#define OMAP_EN_GFX                                     (1 << 0)
+
+/* CM_IDLEST_GFX */
+#define OMAP_ST_GFX                                     (1 << 0)
+
+
+#endif
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
new file mode 100644
index 000000000000..a5d86a49c213
--- /dev/null
+++ b/arch/arm/mach-omap2/control.c
@@ -0,0 +1,74 @@
+/*
+ * OMAP2/3 System Control Module register access
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/kernel.h>
+
+#include <asm/io.h>
+
+#include <asm/arch/control.h>
+
+static u32 omap2_ctrl_base;
+
+#define OMAP_CTRL_REGADDR(reg)  (void __iomem *)IO_ADDRESS(omap2_ctrl_base \
+                                                                + (reg))
+
+void omap_ctrl_base_set(u32 base)
+{
+        omap2_ctrl_base = base;
+}
+
+u32 omap_ctrl_base_get(void)
+{
+        return omap2_ctrl_base;
+}
+
+u8 omap_ctrl_readb(u16 offset)
+{
+        return __raw_readb(OMAP_CTRL_REGADDR(offset));
+}
+
+u16 omap_ctrl_readw(u16 offset)
+{
+        return __raw_readw(OMAP_CTRL_REGADDR(offset));
+}
+
+u32 omap_ctrl_readl(u16 offset)
+{
+        return __raw_readl(OMAP_CTRL_REGADDR(offset));
+}
+
+void omap_ctrl_writeb(u8 val, u16 offset)
+{
+        pr_debug("omap_ctrl_writeb: writing 0x%0x to 0x%0x\n", val,
+                 (u32)OMAP_CTRL_REGADDR(offset));
+
+        __raw_writeb(val, OMAP_CTRL_REGADDR(offset));
+}
+
+void omap_ctrl_writew(u16 val, u16 offset)
+{
+        pr_debug("omap_ctrl_writew: writing 0x%0x to 0x%0x\n", val,
+                 (u32)OMAP_CTRL_REGADDR(offset));
+
+        __raw_writew(val, OMAP_CTRL_REGADDR(offset));
+}
+
+void omap_ctrl_writel(u32 val, u16 offset)
+{
+        pr_debug("omap_ctrl_writel: writing 0x%0x to 0x%0x\n", val,
+                 (u32)OMAP_CTRL_REGADDR(offset));
+
+        __raw_writel(val, OMAP_CTRL_REGADDR(offset));
+}
+
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 5a4cc2076a7d..02cede295e89 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -69,7 +69,7 @@ static void __iomem *gpmc_base =
 static void __iomem *gpmc_cs_base =
         (void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0;
 
-static struct clk *gpmc_l3_clk;
+static struct clk *gpmc_fck;
 
 static void gpmc_write_reg(int idx, u32 val)
 {
@@ -94,11 +94,10 @@ u32 gpmc_cs_read_reg(int cs, int idx)
         return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx);
 }
 
-/* TODO: Add support for gpmc_fck to clock framework and use it */
 unsigned long gpmc_get_fclk_period(void)
 {
         /* In picoseconds */
-        return 1000000000 / ((clk_get_rate(gpmc_l3_clk)) / 1000);
+        return 1000000000 / ((clk_get_rate(gpmc_fck)) / 1000);
 }
 
 unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
@@ -398,8 +397,11 @@ void __init gpmc_init(void)
 {
         u32 l;
 
-        gpmc_l3_clk = clk_get(NULL, "core_l3_ck");
-        BUG_ON(IS_ERR(gpmc_l3_clk));
+        gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */
+        if (IS_ERR(gpmc_fck))
+                WARN_ON(1);
+        else
+                clk_enable(gpmc_fck);
 
         l = gpmc_read_reg(GPMC_REVISION);
         printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c
index 3e5d8cd4ea4f..12479081881a 100644
--- a/arch/arm/mach-omap2/memory.c
+++ b/arch/arm/mach-omap2/memory.c
@@ -27,11 +27,16 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/sram.h>
 
-#include "prcm-regs.h"
+#include "prm.h"
+
 #include "memory.h"
+#include "sdrc.h"
 
+unsigned long omap2_sdrc_base;
+unsigned long omap2_sms_base;
 
 static struct memory_timings mem_timings;
+static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
 
 u32 omap2_memory_get_slow_dll_ctrl(void)
 {
@@ -48,12 +53,60 @@ u32 omap2_memory_get_type(void)
         return mem_timings.m_type;
 }
 
+/*
+ * Check the DLL lock state, and return tue if running in unlock mode.
+ * This is needed to compensate for the shifted DLL value in unlock mode.
+ */
+u32 omap2_dll_force_needed(void)
+{
+        /* dlla and dllb are a set */
+        u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
+
+        if ((dll_state & (1 << 2)) == (1 << 2))
+                return 1;
+        else
+                return 0;
+}
+
+/*
+ * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
+ * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
+ * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
+ */
+u32 omap2_reprogram_sdrc(u32 level, u32 force)
+{
+        u32 dll_ctrl, m_type;
+        u32 prev = curr_perf_level;
+        unsigned long flags;
+
+        if ((curr_perf_level == level) && !force)
+                return prev;
+
+        if (level == CORE_CLK_SRC_DPLL) {
+                dll_ctrl = omap2_memory_get_slow_dll_ctrl();
+        } else if (level == CORE_CLK_SRC_DPLL_X2) {
+                dll_ctrl = omap2_memory_get_fast_dll_ctrl();
+        } else {
+                return prev;
+        }
+
+        m_type = omap2_memory_get_type();
+
+        local_irq_save(flags);
+        __raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP);
+        omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
+        curr_perf_level = level;
+        local_irq_restore(flags);
+
+        return prev;
+}
+
 void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
 {
         unsigned long dll_cnt;
         u32 fast_dll = 0;
 
-        mem_timings.m_type = !((SDRC_MR_0 & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
+        mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
 
         /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
          * In the case of 2422, its ok to use CS1 instead of CS0.
@@ -73,11 +126,11 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
                 mem_timings.dll_mode = M_LOCK;
 
         if (mem_timings.base_cs == 0) {
-                fast_dll = SDRC_DLLA_CTRL;
-                dll_cnt = SDRC_DLLA_STATUS & 0xff00;
+                fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
+                dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
         } else {
-                fast_dll = SDRC_DLLB_CTRL;
-                dll_cnt = SDRC_DLLB_STATUS & 0xff00;
+                fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
+                dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
         }
         if (force_lock_to_unlock_mode) {
                 fast_dll &= ~0xff00;
@@ -106,14 +159,13 @@ void __init omap2_init_memory(void)
 {
         u32 l;
 
-        l = SMS_SYSCONFIG;
+        l = sms_read_reg(SMS_SYSCONFIG);
         l &= ~(0x3 << 3);
         l |= (0x2 << 3);
-        SMS_SYSCONFIG = l;
+        sms_write_reg(l, SMS_SYSCONFIG);
 
-        l = SDRC_SYSCONFIG;
+        l = sdrc_read_reg(SDRC_SYSCONFIG);
         l &= ~(0x3 << 3);
         l |= (0x2 << 3);
-        SDRC_SYSCONFIG = l;
-
+        sdrc_write_reg(l, SDRC_SYSCONFIG);
 }
diff --git a/arch/arm/mach-omap2/memory.h b/arch/arm/mach-omap2/memory.h
index d212eea83a05..9a280b50a893 100644
--- a/arch/arm/mach-omap2/memory.h
+++ b/arch/arm/mach-omap2/memory.h
@@ -32,3 +32,5 @@ extern void omap2_init_memory_params(u32 force_lock_to_unlock_mode);
 extern u32 omap2_memory_get_slow_dll_ctrl(void);
 extern u32 omap2_memory_get_fast_dll_ctrl(void);
 extern u32 omap2_memory_get_type(void);
+u32 omap2_dll_force_needed(void);
+u32 omap2_reprogram_sdrc(u32 level, u32 force);
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 05750975d746..930770012a75 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -1,11 +1,12 @@
 /*
  * linux/arch/arm/mach-omap2/mux.c
  *
- * OMAP1 pin multiplexing configurations
+ * OMAP2 pin multiplexing configurations
  *
- * Copyright (C) 2003 - 2005 Nokia Corporation
+ * Copyright (C) 2004 - 2008 Texas Instruments Inc.
+ * Copyright (C) 2003 - 2008 Nokia Corporation
  *
- * Written by Tony Lindgren <tony.lindgren@nokia.com>
+ * Written by Tony Lindgren
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -28,13 +29,17 @@
 #include <asm/io.h>
 #include <linux/spinlock.h>
 
+#include <asm/arch/control.h>
 #include <asm/arch/mux.h>
 
 #ifdef CONFIG_OMAP_MUX
 
+static struct omap_mux_cfg arch_mux_cfg;
+
 /* NOTE: See mux.h for the enumeration */
 
-struct pin_config __initdata_or_module omap24xx_pins[] = {
+#ifdef CONFIG_ARCH_OMAP24XX
+static struct pin_config __initdata_or_module omap24xx_pins[] = {
 /*
  *      description                     mux     mux     pull    pull    debug
  *                                      offset  mode    ena     type
@@ -77,7 +82,12 @@ MUX_CFG_24XX("AA12_242X_GPIO17",	0x0e9,	3,	0,	0,	1)
 MUX_CFG_24XX("AA8_242X_GPIO58",         0x0ea,  3,      0,      0,      1)
 MUX_CFG_24XX("Y20_24XX_GPIO60",         0x12c,  3,      0,      0,      1)
 MUX_CFG_24XX("W4__24XX_GPIO74",         0x0f2,  3,      0,      0,      1)
+MUX_CFG_24XX("N15_24XX_GPIO85",         0x103,  3,      0,      0,      1)
 MUX_CFG_24XX("M15_24XX_GPIO92",         0x10a,  3,      0,      0,      1)
+MUX_CFG_24XX("P20_24XX_GPIO93",         0x10b,  3,      0,      0,      1)
+MUX_CFG_24XX("P18_24XX_GPIO95",         0x10d,  3,      0,      0,      1)
+MUX_CFG_24XX("M18_24XX_GPIO96",         0x10e,  3,      0,      0,      1)
+MUX_CFG_24XX("L14_24XX_GPIO97",         0x10f,  3,      0,      0,      1)
 MUX_CFG_24XX("J15_24XX_GPIO99",         0x113,  3,      1,      1,      1)
 MUX_CFG_24XX("V14_24XX_GPIO117",        0x128,  3,      1,      0,      1)
 MUX_CFG_24XX("P14_24XX_GPIO125",        0x140,  3,      1,      1,      1)
@@ -102,9 +112,6 @@ MUX_CFG_24XX("G4_242X_DMAREQ3",		0x073,	2,	0,	0,	1)
 MUX_CFG_24XX("D3_242X_DMAREQ4",         0x072,  2,      0,      0,      1)
 MUX_CFG_24XX("E3_242X_DMAREQ5",         0x071,  2,      0,      0,      1)
 
-/* TSC IRQ */
-MUX_CFG_24XX("P20_24XX_TSC_IRQ",        0x108,  0,      0,      0,      1)
-
 /* UART3 */
 MUX_CFG_24XX("K15_24XX_UART3_TX",       0x118,  0,      0,      0,      1)
 MUX_CFG_24XX("K14_24XX_UART3_RX",       0x119,  0,      0,      0,      1)
@@ -167,12 +174,108 @@ MUX_CFG_24XX("B3__24XX_KBR5",		0x30,	3,	1,	1,	1)
 MUX_CFG_24XX("AA4_24XX_KBC2",           0xe7,   3,      0,      0,      1)
 MUX_CFG_24XX("B13_24XX_KBC6",           0x110,  3,      0,      0,      1)
 
+/* 2430 USB */
+MUX_CFG_24XX("AD9_2430_USB0_PUEN",      0x133,  4,      0,      0,      1)
+MUX_CFG_24XX("Y11_2430_USB0_VP",        0x134,  4,      0,      0,      1)
+MUX_CFG_24XX("AD7_2430_USB0_VM",        0x135,  4,      0,      0,      1)
+MUX_CFG_24XX("AE7_2430_USB0_RCV",       0x136,  4,      0,      0,      1)
+MUX_CFG_24XX("AD4_2430_USB0_TXEN",      0x137,  4,      0,      0,      1)
+MUX_CFG_24XX("AF9_2430_USB0_SE0",       0x138,  4,      0,      0,      1)
+MUX_CFG_24XX("AE6_2430_USB0_DAT",       0x139,  4,      0,      0,      1)
+MUX_CFG_24XX("AD24_2430_USB1_SE0",      0x107,  2,      0,      0,      1)
+MUX_CFG_24XX("AB24_2430_USB1_RCV",      0x108,  2,      0,      0,      1)
+MUX_CFG_24XX("Y25_2430_USB1_TXEN",      0x109,  2,      0,      0,      1)
+MUX_CFG_24XX("AA26_2430_USB1_DAT",      0x10A,  2,      0,      0,      1)
+
+/* 2430 HS-USB */
+MUX_CFG_24XX("AD9_2430_USB0HS_DATA3",   0x133,  0,      0,      0,      1)
+MUX_CFG_24XX("Y11_2430_USB0HS_DATA4",   0x134,  0,      0,      0,      1)
+MUX_CFG_24XX("AD7_2430_USB0HS_DATA5",   0x135,  0,      0,      0,      1)
+MUX_CFG_24XX("AE7_2430_USB0HS_DATA6",   0x136,  0,      0,      0,      1)
+MUX_CFG_24XX("AD4_2430_USB0HS_DATA2",   0x137,  0,      0,      0,      1)
+MUX_CFG_24XX("AF9_2430_USB0HS_DATA0",   0x138,  0,      0,      0,      1)
+MUX_CFG_24XX("AE6_2430_USB0HS_DATA1",   0x139,  0,      0,      0,      1)
+MUX_CFG_24XX("AE8_2430_USB0HS_CLK",     0x13A,  0,      0,      0,      1)
+MUX_CFG_24XX("AD8_2430_USB0HS_DIR",     0x13B,  0,      0,      0,      1)
+MUX_CFG_24XX("AE5_2430_USB0HS_STP",     0x13c,  0,      1,      1,      1)
+MUX_CFG_24XX("AE9_2430_USB0HS_NXT",     0x13D,  0,      0,      0,      1)
+MUX_CFG_24XX("AC7_2430_USB0HS_DATA7",   0x13E,  0,      0,      0,      1)
+
+/* 2430 McBSP */
+MUX_CFG_24XX("AC10_2430_MCBSP2_FSX",    0x012E, 1,      0,      0,      1)
+MUX_CFG_24XX("AD16_2430_MCBSP2_CLX",    0x012F, 1,      0,      0,      1)
+MUX_CFG_24XX("AE13_2430_MCBSP2_DX",     0x0130, 1,      0,      0,      1)
+MUX_CFG_24XX("AD13_2430_MCBSP2_DR",     0x0131, 1,      0,      0,      1)
+MUX_CFG_24XX("AC10_2430_MCBSP2_FSX_OFF",0x012E, 0,      0,      0,      1)
+MUX_CFG_24XX("AD16_2430_MCBSP2_CLX_OFF",0x012F, 0,      0,      0,      1)
+MUX_CFG_24XX("AE13_2430_MCBSP2_DX_OFF", 0x0130, 0,      0,      0,      1)
+MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF", 0x0131, 0,      0,      0,      1)
 };
 
-int __init omap2_mux_init(void)
+#define OMAP24XX_PINS_SZ        ARRAY_SIZE(omap24xx_pins)
+
+#else
+#define omap24xx_pins           NULL
+#define OMAP24XX_PINS_SZ        0
+#endif  /* CONFIG_ARCH_OMAP24XX */
+
+#define OMAP24XX_PULL_ENA       (1 << 3)
+#define OMAP24XX_PULL_UP        (1 << 4)
+
+#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
+void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u8 reg)
 {
-        omap_mux_register(omap24xx_pins, ARRAY_SIZE(omap24xx_pins));
+        u16 orig;
+        u8 warn = 0, debug = 0;
+
+        orig = omap_ctrl_readb(cfg->mux_reg);
+
+#ifdef  CONFIG_OMAP_MUX_DEBUG
+        debug = cfg->debug;
+#endif
+        warn = (orig != reg);
+        if (debug || warn)
+                printk(KERN_WARNING
+                        "MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n",
+                        cfg->name, omap_ctrl_base_get() + cfg->mux_reg,
+                        orig, reg);
+}
+#else
+#define omap2_cfg_debug(x, y)   do {} while (0)
+#endif
+
+#ifdef CONFIG_ARCH_OMAP24XX
+int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
+{
+        static DEFINE_SPINLOCK(mux_spin_lock);
+        unsigned long flags;
+        u8 reg = 0;
+
+        spin_lock_irqsave(&mux_spin_lock, flags);
+        reg |= cfg->mask & 0x7;
+        if (cfg->pull_val)
+                reg |= OMAP24XX_PULL_ENA;
+        if (cfg->pu_pd_val)
+                reg |= OMAP24XX_PULL_UP;
+        omap2_cfg_debug(cfg, reg);
+        omap_ctrl_writeb(reg, cfg->mux_reg);
+        spin_unlock_irqrestore(&mux_spin_lock, flags);
+
         return 0;
 }
+#else
+#define omap24xx_cfg_reg        0
+#endif
+
+int __init omap2_mux_init(void)
+{
+        if (cpu_is_omap24xx()) {
+                arch_mux_cfg.pins       = omap24xx_pins;
+                arch_mux_cfg.size       = OMAP24XX_PINS_SZ;
+                arch_mux_cfg.cfg_reg    = omap24xx_cfg_reg;
+        }
+
+        return omap_mux_register(&arch_mux_cfg);
+}
 
 #endif
diff --git a/arch/arm/mach-omap2/pm-domain.c b/arch/arm/mach-omap2/pm-domain.c
deleted file mode 100644
index 2494091a078b..000000000000
--- a/arch/arm/mach-omap2/pm-domain.c
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * linux/arch/arm/mach-omap2/pm-domain.c
- *
- * Power domain functions for OMAP2
- *
- * Copyright (C) 2006 Nokia Corporation
- * Tony Lindgren <tony@atomide.com>
- *
- * Some code based on earlier OMAP2 sample PM code
- * Copyright (C) 2005 Texas Instruments, Inc.
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-
-#include <asm/io.h>
-
-#include "prcm-regs.h"
-
-/* Power domain offsets */
-#define PM_MPU_OFFSET                   0x100
-#define PM_CORE_OFFSET                  0x200
-#define PM_GFX_OFFSET                   0x300
-#define PM_WKUP_OFFSET                  0x400           /* Autoidle only */
-#define PM_PLL_OFFSET                   0x500           /* Autoidle only */
-#define PM_DSP_OFFSET                   0x800
-#define PM_MDM_OFFSET                   0xc00
-
-/* Power domain wake-up dependency control register */
-#define PM_WKDEP_OFFSET                 0xc8
-#define         EN_MDM                  (1 << 5)
-#define         EN_WKUP                 (1 << 4)
-#define         EN_GFX                  (1 << 3)
-#define         EN_DSP                  (1 << 2)
-#define         EN_MPU                  (1 << 1)
-#define         EN_CORE                 (1 << 0)
-
-/* Core power domain state transition control register */
-#define PM_PWSTCTRL_OFFSET              0xe0
-#define         FORCESTATE              (1 << 18)       /* Only for DSP & GFX */
-#define         MEM4RETSTATE            (1 << 6)
-#define         MEM3RETSTATE            (1 << 5)
-#define         MEM2RETSTATE            (1 << 4)
-#define         MEM1RETSTATE            (1 << 3)
-#define         LOGICRETSTATE           (1 << 2)        /* Logic is retained */
-#define         POWERSTATE_OFF          0x3
-#define         POWERSTATE_RETENTION    0x1
-#define         POWERSTATE_ON           0x0
-
-/* Power domain state register */
-#define PM_PWSTST_OFFSET                0xe4
-
-/* Hardware supervised state transition control register */
-#define CM_CLKSTCTRL_OFFSET             0x48
-#define         AUTOSTAT_MPU            (1 << 0)        /* MPU */
-#define         AUTOSTAT_DSS            (1 << 2)        /* Core */
-#define         AUTOSTAT_L4             (1 << 1)        /* Core */
-#define         AUTOSTAT_L3             (1 << 0)        /* Core */
-#define         AUTOSTAT_GFX            (1 << 0)        /* GFX */
-#define         AUTOSTAT_IVA            (1 << 8)        /* 2420 IVA in DSP domain */
-#define         AUTOSTAT_DSP            (1 << 0)        /* DSP */
-#define         AUTOSTAT_MDM            (1 << 0)        /* MDM */
-
-/* Automatic control of interface clock idling */
-#define CM_AUTOIDLE1_OFFSET             0x30
-#define CM_AUTOIDLE2_OFFSET             0x34            /* Core only */
-#define CM_AUTOIDLE3_OFFSET             0x38            /* Core only */
-#define CM_AUTOIDLE4_OFFSET             0x3c            /* Core only */
-#define         AUTO_54M(x)             (((x) & 0x3) << 6)
-#define         AUTO_96M(x)             (((x) & 0x3) << 2)
-#define         AUTO_DPLL(x)            (((x) & 0x3) << 0)
-#define         AUTO_STOPPED            0x3
-#define         AUTO_BYPASS_FAST        0x2             /* DPLL only */
-#define         AUTO_BYPASS_LOW_POWER   0x1             /* DPLL only */
-#define         AUTO_DISABLED           0x0
-
-/* Voltage control PRCM_VOLTCTRL bits */
-#define         AUTO_EXTVOLT            (1 << 15)
-#define         FORCE_EXTVOLT           (1 << 14)
-#define         SETOFF_LEVEL(x)         (((x) & 0x3) << 12)
-#define         MEMRETCTRL              (1 << 8)
-#define         SETRET_LEVEL(x)         (((x) & 0x3) << 6)
-#define         VOLT_LEVEL(x)           (((x) & 0x3) << 0)
-
-#define OMAP24XX_PRCM_VBASE     IO_ADDRESS(OMAP24XX_PRCM_BASE)
-#define prcm_readl(r)           __raw_readl(OMAP24XX_PRCM_VBASE + (r))
-#define prcm_writel(v, r)       __raw_writel((v), OMAP24XX_PRCM_VBASE + (r))
-
-static u32 pmdomain_get_wakeup_dependencies(int domain_offset)
-{
-        return prcm_readl(domain_offset + PM_WKDEP_OFFSET);
-}
-
-static void pmdomain_set_wakeup_dependencies(u32 state, int domain_offset)
-{
-        prcm_writel(state, domain_offset + PM_WKDEP_OFFSET);
-}
-
-static u32 pmdomain_get_powerstate(int domain_offset)
-{
-        return prcm_readl(domain_offset + PM_PWSTCTRL_OFFSET);
-}
-
-static void pmdomain_set_powerstate(u32 state, int domain_offset)
-{
-        prcm_writel(state, domain_offset + PM_PWSTCTRL_OFFSET);
-}
-
-static u32 pmdomain_get_clock_autocontrol(int domain_offset)
-{
-        return prcm_readl(domain_offset + CM_CLKSTCTRL_OFFSET);
-}
-
-static void pmdomain_set_clock_autocontrol(u32 state, int domain_offset)
-{
-        prcm_writel(state, domain_offset + CM_CLKSTCTRL_OFFSET);
-}
-
-static u32 pmdomain_get_clock_autoidle1(int domain_offset)
-{
-        return prcm_readl(domain_offset + CM_AUTOIDLE1_OFFSET);
-}
-
-/* Core domain only */
-static u32 pmdomain_get_clock_autoidle2(int domain_offset)
-{
-        return prcm_readl(domain_offset + CM_AUTOIDLE2_OFFSET);
-}
-
-/* Core domain only */
-static u32 pmdomain_get_clock_autoidle3(int domain_offset)
-{
-        return prcm_readl(domain_offset + CM_AUTOIDLE3_OFFSET);
-}
-
-/* Core domain only */
-static u32 pmdomain_get_clock_autoidle4(int domain_offset)
-{
-        return prcm_readl(domain_offset + CM_AUTOIDLE4_OFFSET);
-}
-
-static void pmdomain_set_clock_autoidle1(u32 state, int domain_offset)
-{
-        prcm_writel(state, CM_AUTOIDLE1_OFFSET + domain_offset);
-}
-
-/* Core domain only */
-static void pmdomain_set_clock_autoidle2(u32 state, int domain_offset)
-{
-        prcm_writel(state, CM_AUTOIDLE2_OFFSET + domain_offset);
-}
-
-/* Core domain only */
-static void pmdomain_set_clock_autoidle3(u32 state, int domain_offset)
-{
-        prcm_writel(state, CM_AUTOIDLE3_OFFSET + domain_offset);
-}
-
-/* Core domain only */
-static void pmdomain_set_clock_autoidle4(u32 state, int domain_offset)
-{
-        prcm_writel(state, CM_AUTOIDLE4_OFFSET + domain_offset);
-}
-
-/*
- * Configures power management domains to idle clocks automatically.
- */
-void pmdomain_set_autoidle(void)
-{
-        u32 val;
-
-        /* Set PLL auto stop for 54M, 96M & DPLL */
-        pmdomain_set_clock_autoidle1(AUTO_54M(AUTO_STOPPED) |
-                                     AUTO_96M(AUTO_STOPPED) |
-                                     AUTO_DPLL(AUTO_STOPPED), PM_PLL_OFFSET);
-
-        /* External clock input control
-         * REVISIT: Should this be in clock framework?
-         */
-        PRCM_CLKSRC_CTRL |= (0x3 << 3);
-
-        /* Configure number of 32KHz clock cycles for sys_clk */
-        PRCM_CLKSSETUP = 0x00ff;
-
-        /* Configure automatic voltage transition */
-        PRCM_VOLTSETUP = 0;
-        val = PRCM_VOLTCTRL;
-        val &= ~(SETOFF_LEVEL(0x3) | VOLT_LEVEL(0x3));
-        val |= SETOFF_LEVEL(1) | VOLT_LEVEL(1) | AUTO_EXTVOLT;
-        PRCM_VOLTCTRL = val;
-
-        /* Disable emulation tools functional clock */
-        PRCM_CLKEMUL_CTRL = 0x0;
-
-        /* Set core memory retention state */
-        val = pmdomain_get_powerstate(PM_CORE_OFFSET);
-        if (cpu_is_omap2420()) {
-                val &= ~(0x7 << 3);
-                val |= (MEM3RETSTATE | MEM2RETSTATE | MEM1RETSTATE);
-        } else {
-                val &= ~(0xf << 3);
-                val |= (MEM4RETSTATE | MEM3RETSTATE | MEM2RETSTATE |
-                        MEM1RETSTATE);
-        }
-        pmdomain_set_powerstate(val, PM_CORE_OFFSET);
-
-        /* OCP interface smart idle. REVISIT: Enable autoidle bit0 ? */
-        val = SMS_SYSCONFIG;
-        val &= ~(0x3 << 3);
-        val |= (0x2 << 3) | (1 << 0);
-        SMS_SYSCONFIG |= val;
-
-        val = SDRC_SYSCONFIG;
-        val &= ~(0x3 << 3);
-        val |= (0x2 << 3);
-        SDRC_SYSCONFIG = val;
-
-        /* Configure L3 interface for smart idle.
-         * REVISIT: Enable autoidle bit0 ?
-         */
-        val = GPMC_SYSCONFIG;
-        val &= ~(0x3 << 3);
-        val |= (0x2 << 3) | (1 << 0);
-        GPMC_SYSCONFIG = val;
-
-        pmdomain_set_powerstate(LOGICRETSTATE | POWERSTATE_RETENTION,
-                                PM_MPU_OFFSET);
-        pmdomain_set_powerstate(POWERSTATE_RETENTION, PM_CORE_OFFSET);
-        if (!cpu_is_omap2420())
-                pmdomain_set_powerstate(POWERSTATE_RETENTION, PM_MDM_OFFSET);
-
-        /* Assume suspend function has saved the state for DSP and GFX */
-        pmdomain_set_powerstate(FORCESTATE | POWERSTATE_OFF, PM_DSP_OFFSET);
-        pmdomain_set_powerstate(FORCESTATE | POWERSTATE_OFF, PM_GFX_OFFSET);
-
-#if 0
-        /* REVISIT: Internal USB needs special handling */
-        force_standby_usb();
-        if (cpu_is_omap2430())
-                force_hsmmc();
-        sdram_self_refresh_on_idle_req(1);
-#endif
-
-        /* Enable clock auto control for all domains.
-         * Note that CORE domain includes also DSS, L4 & L3.
-         */
-        pmdomain_set_clock_autocontrol(AUTOSTAT_MPU, PM_MPU_OFFSET);
-        pmdomain_set_clock_autocontrol(AUTOSTAT_GFX, PM_GFX_OFFSET);
-        pmdomain_set_clock_autocontrol(AUTOSTAT_DSS | AUTOSTAT_L4 | AUTOSTAT_L3,
-                                       PM_CORE_OFFSET);
-        if (cpu_is_omap2420())
-                pmdomain_set_clock_autocontrol(AUTOSTAT_IVA | AUTOSTAT_DSP,
-                                               PM_DSP_OFFSET);
-        else {
-                pmdomain_set_clock_autocontrol(AUTOSTAT_DSP, PM_DSP_OFFSET);
-                pmdomain_set_clock_autocontrol(AUTOSTAT_MDM, PM_MDM_OFFSET);
-        }
-
-        /* Enable clock autoidle for all domains */
-        pmdomain_set_clock_autoidle1(0x2, PM_DSP_OFFSET);
-        if (cpu_is_omap2420()) {
-                pmdomain_set_clock_autoidle1(0xfffffff9, PM_CORE_OFFSET);
-                pmdomain_set_clock_autoidle2(0x7, PM_CORE_OFFSET);
-                pmdomain_set_clock_autoidle1(0x3f, PM_WKUP_OFFSET);
-        } else {
-                pmdomain_set_clock_autoidle1(0xeafffff1, PM_CORE_OFFSET);
-                pmdomain_set_clock_autoidle2(0xfff, PM_CORE_OFFSET);
-                pmdomain_set_clock_autoidle1(0x7f, PM_WKUP_OFFSET);
-                pmdomain_set_clock_autoidle1(0x3, PM_MDM_OFFSET);
-        }
-        pmdomain_set_clock_autoidle3(0x7, PM_CORE_OFFSET);
-        pmdomain_set_clock_autoidle4(0x1f, PM_CORE_OFFSET);
-}
-
-/*
- * Initializes power domains by removing wake-up dependencies and powering
- * down DSP and GFX. Gets called from PM init. Note that DSP and IVA code
- * must re-enable DSP and GFX when used.
- */
-void __init pmdomain_init(void)
-{
-        /* Remove all domain wakeup dependencies */
-        pmdomain_set_wakeup_dependencies(EN_WKUP | EN_CORE, PM_MPU_OFFSET);
-        pmdomain_set_wakeup_dependencies(0, PM_DSP_OFFSET);
-        pmdomain_set_wakeup_dependencies(0, PM_GFX_OFFSET);
-        pmdomain_set_wakeup_dependencies(EN_WKUP | EN_MPU, PM_CORE_OFFSET);
-        if (cpu_is_omap2430())
-                pmdomain_set_wakeup_dependencies(0, PM_MDM_OFFSET);
-
-        /* Power down DSP and GFX */
-        pmdomain_set_powerstate(POWERSTATE_OFF | FORCESTATE, PM_DSP_OFFSET);
-        pmdomain_set_powerstate(POWERSTATE_OFF | FORCESTATE, PM_GFX_OFFSET);
-}
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index baf7d82b458b..aad781dcf1b1 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -23,6 +23,7 @@
 #include <linux/sysfs.h>
 #include <linux/module.h>
 #include <linux/delay.h>
+#include <linux/clk.h>
 
 #include <asm/io.h>
 #include <asm/irq.h>
@@ -36,8 +37,6 @@
 #include <asm/arch/sram.h>
 #include <asm/arch/pm.h>
 
-#include "prcm-regs.h"
-
 static struct clk *vclk;
 static void (*omap2_sram_idle)(void);
 static void (*omap2_sram_suspend)(int dllctrl, int cpu_rev);
@@ -78,251 +77,8 @@ static int omap2_pm_prepare(void)
         return 0;
 }
 
-#define INT0_WAKE_MASK  (OMAP_IRQ_BIT(INT_24XX_GPIO_BANK1) |    \
-                        OMAP_IRQ_BIT(INT_24XX_GPIO_BANK2) |     \
-                        OMAP_IRQ_BIT(INT_24XX_GPIO_BANK3))
-
-#define INT1_WAKE_MASK  (OMAP_IRQ_BIT(INT_24XX_GPIO_BANK4))
-
-#define INT2_WAKE_MASK  (OMAP_IRQ_BIT(INT_24XX_UART1_IRQ) |     \
-                        OMAP_IRQ_BIT(INT_24XX_UART2_IRQ) |      \
-                        OMAP_IRQ_BIT(INT_24XX_UART3_IRQ))
-
-#define preg(reg)       printk("%s\t(0x%p):\t0x%08x\n", #reg, &reg, reg);
-
-static void omap2_pm_debug(char * desc)
-{
-        printk("%s:\n", desc);
-
-        preg(CM_CLKSTCTRL_MPU);
-        preg(CM_CLKSTCTRL_CORE);
-        preg(CM_CLKSTCTRL_GFX);
-        preg(CM_CLKSTCTRL_DSP);
-        preg(CM_CLKSTCTRL_MDM);
-
-        preg(PM_PWSTCTRL_MPU);
-        preg(PM_PWSTCTRL_CORE);
-        preg(PM_PWSTCTRL_GFX);
-        preg(PM_PWSTCTRL_DSP);
-        preg(PM_PWSTCTRL_MDM);
-
-        preg(PM_PWSTST_MPU);
-        preg(PM_PWSTST_CORE);
-        preg(PM_PWSTST_GFX);
-        preg(PM_PWSTST_DSP);
-        preg(PM_PWSTST_MDM);
-
-        preg(CM_AUTOIDLE1_CORE);
-        preg(CM_AUTOIDLE2_CORE);
-        preg(CM_AUTOIDLE3_CORE);
-        preg(CM_AUTOIDLE4_CORE);
-        preg(CM_AUTOIDLE_WKUP);
-        preg(CM_AUTOIDLE_PLL);
-        preg(CM_AUTOIDLE_DSP);
-        preg(CM_AUTOIDLE_MDM);
-
-        preg(CM_ICLKEN1_CORE);
-        preg(CM_ICLKEN2_CORE);
-        preg(CM_ICLKEN3_CORE);
-        preg(CM_ICLKEN4_CORE);
-        preg(CM_ICLKEN_GFX);
-        preg(CM_ICLKEN_WKUP);
-        preg(CM_ICLKEN_DSP);
-        preg(CM_ICLKEN_MDM);
-
-        preg(CM_IDLEST1_CORE);
-        preg(CM_IDLEST2_CORE);
-        preg(CM_IDLEST3_CORE);
-        preg(CM_IDLEST4_CORE);
-        preg(CM_IDLEST_GFX);
-        preg(CM_IDLEST_WKUP);
-        preg(CM_IDLEST_CKGEN);
-        preg(CM_IDLEST_DSP);
-        preg(CM_IDLEST_MDM);
-
-        preg(RM_RSTST_MPU);
-        preg(RM_RSTST_GFX);
-        preg(RM_RSTST_WKUP);
-        preg(RM_RSTST_DSP);
-        preg(RM_RSTST_MDM);
-
-        preg(PM_WKDEP_MPU);
-        preg(PM_WKDEP_CORE);
-        preg(PM_WKDEP_GFX);
-        preg(PM_WKDEP_DSP);
-        preg(PM_WKDEP_MDM);
-
-        preg(CM_FCLKEN_WKUP);
-        preg(CM_ICLKEN_WKUP);
-        preg(CM_IDLEST_WKUP);
-        preg(CM_AUTOIDLE_WKUP);
-        preg(CM_CLKSEL_WKUP);
-
-        preg(PM_WKEN_WKUP);
-        preg(PM_WKST_WKUP);
-}
-
-static inline void omap2_pm_save_registers(void)
-{
-        /* Save interrupt registers */
-        OMAP24XX_SAVE(INTC_MIR0);
-        OMAP24XX_SAVE(INTC_MIR1);
-        OMAP24XX_SAVE(INTC_MIR2);
-
-        /* Save power control registers */
-        OMAP24XX_SAVE(CM_CLKSTCTRL_MPU);
-        OMAP24XX_SAVE(CM_CLKSTCTRL_CORE);
-        OMAP24XX_SAVE(CM_CLKSTCTRL_GFX);
-        OMAP24XX_SAVE(CM_CLKSTCTRL_DSP);
-        OMAP24XX_SAVE(CM_CLKSTCTRL_MDM);
-
-        /* Save power state registers */
-        OMAP24XX_SAVE(PM_PWSTCTRL_MPU);
-        OMAP24XX_SAVE(PM_PWSTCTRL_CORE);
-        OMAP24XX_SAVE(PM_PWSTCTRL_GFX);
-        OMAP24XX_SAVE(PM_PWSTCTRL_DSP);
-        OMAP24XX_SAVE(PM_PWSTCTRL_MDM);
-
-        /* Save autoidle registers */
-        OMAP24XX_SAVE(CM_AUTOIDLE1_CORE);
-        OMAP24XX_SAVE(CM_AUTOIDLE2_CORE);
-        OMAP24XX_SAVE(CM_AUTOIDLE3_CORE);
-        OMAP24XX_SAVE(CM_AUTOIDLE4_CORE);
-        OMAP24XX_SAVE(CM_AUTOIDLE_WKUP);
-        OMAP24XX_SAVE(CM_AUTOIDLE_PLL);
-        OMAP24XX_SAVE(CM_AUTOIDLE_DSP);
-        OMAP24XX_SAVE(CM_AUTOIDLE_MDM);
-
-        /* Save idle state registers */
-        OMAP24XX_SAVE(CM_IDLEST1_CORE);
-        OMAP24XX_SAVE(CM_IDLEST2_CORE);
-        OMAP24XX_SAVE(CM_IDLEST3_CORE);
-        OMAP24XX_SAVE(CM_IDLEST4_CORE);
-        OMAP24XX_SAVE(CM_IDLEST_GFX);
-        OMAP24XX_SAVE(CM_IDLEST_WKUP);
-        OMAP24XX_SAVE(CM_IDLEST_CKGEN);
-        OMAP24XX_SAVE(CM_IDLEST_DSP);
-        OMAP24XX_SAVE(CM_IDLEST_MDM);
-
-        /* Save clock registers */
-        OMAP24XX_SAVE(CM_FCLKEN1_CORE);
-        OMAP24XX_SAVE(CM_FCLKEN2_CORE);
-        OMAP24XX_SAVE(CM_ICLKEN1_CORE);
-        OMAP24XX_SAVE(CM_ICLKEN2_CORE);
-        OMAP24XX_SAVE(CM_ICLKEN3_CORE);
-        OMAP24XX_SAVE(CM_ICLKEN4_CORE);
-}
-
-static inline void omap2_pm_restore_registers(void)
-{
-        /* Restore clock state registers */
-        OMAP24XX_RESTORE(CM_CLKSTCTRL_MPU);
-        OMAP24XX_RESTORE(CM_CLKSTCTRL_CORE);
-        OMAP24XX_RESTORE(CM_CLKSTCTRL_GFX);
-        OMAP24XX_RESTORE(CM_CLKSTCTRL_DSP);
-        OMAP24XX_RESTORE(CM_CLKSTCTRL_MDM);
-
-        /* Restore power state registers */
-        OMAP24XX_RESTORE(PM_PWSTCTRL_MPU);
-        OMAP24XX_RESTORE(PM_PWSTCTRL_CORE);
-        OMAP24XX_RESTORE(PM_PWSTCTRL_GFX);
-        OMAP24XX_RESTORE(PM_PWSTCTRL_DSP);
-        OMAP24XX_RESTORE(PM_PWSTCTRL_MDM);
-
-        /* Restore idle state registers */
-        OMAP24XX_RESTORE(CM_IDLEST1_CORE);
-        OMAP24XX_RESTORE(CM_IDLEST2_CORE);
-        OMAP24XX_RESTORE(CM_IDLEST3_CORE);
-        OMAP24XX_RESTORE(CM_IDLEST4_CORE);
-        OMAP24XX_RESTORE(CM_IDLEST_GFX);
-        OMAP24XX_RESTORE(CM_IDLEST_WKUP);
-        OMAP24XX_RESTORE(CM_IDLEST_CKGEN);
-        OMAP24XX_RESTORE(CM_IDLEST_DSP);
-        OMAP24XX_RESTORE(CM_IDLEST_MDM);
-
-        /* Restore autoidle registers */
-        OMAP24XX_RESTORE(CM_AUTOIDLE1_CORE);
-        OMAP24XX_RESTORE(CM_AUTOIDLE2_CORE);
-        OMAP24XX_RESTORE(CM_AUTOIDLE3_CORE);
-        OMAP24XX_RESTORE(CM_AUTOIDLE4_CORE);
-        OMAP24XX_RESTORE(CM_AUTOIDLE_WKUP);
-        OMAP24XX_RESTORE(CM_AUTOIDLE_PLL);
-        OMAP24XX_RESTORE(CM_AUTOIDLE_DSP);
-        OMAP24XX_RESTORE(CM_AUTOIDLE_MDM);
-
-        /* Restore clock registers */
-        OMAP24XX_RESTORE(CM_FCLKEN1_CORE);
-        OMAP24XX_RESTORE(CM_FCLKEN2_CORE);
-        OMAP24XX_RESTORE(CM_ICLKEN1_CORE);
-        OMAP24XX_RESTORE(CM_ICLKEN2_CORE);
-        OMAP24XX_RESTORE(CM_ICLKEN3_CORE);
-        OMAP24XX_RESTORE(CM_ICLKEN4_CORE);
-
-        /* REVISIT: Clear interrupts here */
-
-        /* Restore interrupt registers */
-        OMAP24XX_RESTORE(INTC_MIR0);
-        OMAP24XX_RESTORE(INTC_MIR1);
-        OMAP24XX_RESTORE(INTC_MIR2);
-}
-
 static int omap2_pm_suspend(void)
 {
-        int processor_type = 0;
-
-        /* REVISIT: 0x21 or 0x26? */
-        if (cpu_is_omap2420())
-                processor_type = 0x21;
-
-        if (!processor_type)
-                return -ENOTSUPP;
-
-        local_irq_disable();
-        local_fiq_disable();
-
-        omap2_pm_save_registers();
-
-        /* Disable interrupts except for the wake events */
-        INTC_MIR_SET0 = 0xffffffff & ~INT0_WAKE_MASK;
-        INTC_MIR_SET1 = 0xffffffff & ~INT1_WAKE_MASK;
-        INTC_MIR_SET2 = 0xffffffff & ~INT2_WAKE_MASK;
-
-        pmdomain_set_autoidle();
-
-        /* Clear old wake-up events */
-        PM_WKST1_CORE = 0;
-        PM_WKST2_CORE = 0;
-        PM_WKST_WKUP = 0;
-
-        /* Enable wake-up events */
-        PM_WKEN1_CORE = (1 << 22) | (1 << 21);  /* UART1 & 2 */
-        PM_WKEN2_CORE = (1 << 2);               /* UART3 */
-        PM_WKEN_WKUP = (1 << 2) | (1 << 0);     /* GPIO & GPT1 */
-
-        /* Disable clocks except for CM_ICLKEN2_CORE. It gets disabled
-         * in the SRAM suspend code */
-        CM_FCLKEN1_CORE = 0;
-        CM_FCLKEN2_CORE = 0;
-        CM_ICLKEN1_CORE = 0;
-        CM_ICLKEN3_CORE = 0;
-        CM_ICLKEN4_CORE = 0;
-
-        omap2_pm_debug("Status before suspend");
-
-        /* Must wait for serial buffers to clear */
-        mdelay(200);
-
-        /* Jump to SRAM suspend code
-         * REVISIT: When is this SDRC_DLLB_CTRL?
-         */
-        omap2_sram_suspend(SDRC_DLLA_CTRL, processor_type);
-
-        /* Back from sleep */
-        omap2_pm_restore_registers();
-
-        local_fiq_enable();
-        local_irq_enable();
-
         return 0;
 }
 
@@ -357,30 +113,6 @@ static struct platform_suspend_ops omap_pm_ops = {
 
 int __init omap2_pm_init(void)
 {
-        printk("Power Management for TI OMAP.\n");
-
-        vclk = clk_get(NULL, "virt_prcm_set");
-        if (IS_ERR(vclk)) {
-                printk(KERN_ERR "Could not get PM vclk\n");
-                return -ENODEV;
-        }
-
-        /*
-         * We copy the assembler sleep/wakeup routines to SRAM.
-         * These routines need to be in SRAM as that's the only
-         * memory the MPU can see when it wakes up.
-         */
-        omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
-                                         omap24xx_idle_loop_suspend_sz);
-
-        omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
-                                            omap24xx_cpu_suspend_sz);
-
-        suspend_set_ops(&omap_pm_ops);
-        pm_idle = omap2_pm_idle;
-
-        pmdomain_init();
-
         return 0;
 }
 
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
new file mode 100644
index 000000000000..cacb34086e35
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -0,0 +1,317 @@
+#ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
+#define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
+
+/*
+ * OMAP2/3 PRCM base and module definitions
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+
+/* Module offsets from both CM_BASE & PRM_BASE */
+
+/*
+ * Offsets that are the same on 24xx and 34xx
+ *
+ * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is
+ * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2.
+ */
+#define OCP_MOD                                         0x000
+#define MPU_MOD                                         0x100
+#define CORE_MOD                                        0x200
+#define GFX_MOD                                         0x300
+#define WKUP_MOD                                        0x400
+#define PLL_MOD                                         0x500
+
+
+/* Chip-specific module offsets */
+#define OMAP24XX_DSP_MOD                                0x800
+
+#define OMAP2430_MDM_MOD                                0xc00
+
+/* IVA2 module is < base on 3430 */
+#define OMAP3430_IVA2_MOD                               -0x800
+#define OMAP3430ES2_SGX_MOD                             GFX_MOD
+#define OMAP3430_CCR_MOD                                PLL_MOD
+#define OMAP3430_DSS_MOD                                0x600
+#define OMAP3430_CAM_MOD                                0x700
+#define OMAP3430_PER_MOD                                0x800
+#define OMAP3430_EMU_MOD                                0x900
+#define OMAP3430_GR_MOD                                 0xa00
+#define OMAP3430_NEON_MOD                               0xb00
+#define OMAP3430ES2_USBHOST_MOD                         0xc00
+
+
+/* 24XX register bits shared between CM & PRM registers */
+
+/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
+#define OMAP2420_EN_MMC_SHIFT                           26
+#define OMAP2420_EN_MMC                                 (1 << 26)
+#define OMAP24XX_EN_UART2_SHIFT                         22
+#define OMAP24XX_EN_UART2                               (1 << 22)
+#define OMAP24XX_EN_UART1_SHIFT                         21
+#define OMAP24XX_EN_UART1                               (1 << 21)
+#define OMAP24XX_EN_MCSPI2_SHIFT                        18
+#define OMAP24XX_EN_MCSPI2                              (1 << 18)
+#define OMAP24XX_EN_MCSPI1_SHIFT                        17
+#define OMAP24XX_EN_MCSPI1                              (1 << 17)
+#define OMAP24XX_EN_MCBSP2_SHIFT                        16
+#define OMAP24XX_EN_MCBSP2                              (1 << 16)
+#define OMAP24XX_EN_MCBSP1_SHIFT                        15
+#define OMAP24XX_EN_MCBSP1                              (1 << 15)
+#define OMAP24XX_EN_GPT12_SHIFT                         14
+#define OMAP24XX_EN_GPT12                               (1 << 14)
+#define OMAP24XX_EN_GPT11_SHIFT                         13
+#define OMAP24XX_EN_GPT11                               (1 << 13)
+#define OMAP24XX_EN_GPT10_SHIFT                         12
+#define OMAP24XX_EN_GPT10                               (1 << 12)
+#define OMAP24XX_EN_GPT9_SHIFT                          11
+#define OMAP24XX_EN_GPT9                                (1 << 11)
+#define OMAP24XX_EN_GPT8_SHIFT                          10
+#define OMAP24XX_EN_GPT8                                (1 << 10)
+#define OMAP24XX_EN_GPT7_SHIFT                          9
+#define OMAP24XX_EN_GPT7                                (1 << 9)
+#define OMAP24XX_EN_GPT6_SHIFT                          8
+#define OMAP24XX_EN_GPT6                                (1 << 8)
+#define OMAP24XX_EN_GPT5_SHIFT                          7
+#define OMAP24XX_EN_GPT5                                (1 << 7)
+#define OMAP24XX_EN_GPT4_SHIFT                          6
+#define OMAP24XX_EN_GPT4                                (1 << 6)
+#define OMAP24XX_EN_GPT3_SHIFT                          5
+#define OMAP24XX_EN_GPT3                                (1 << 5)
+#define OMAP24XX_EN_GPT2_SHIFT                          4
+#define OMAP24XX_EN_GPT2                                (1 << 4)
+#define OMAP2420_EN_VLYNQ_SHIFT                         3
+#define OMAP2420_EN_VLYNQ                               (1 << 3)
+
+/* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
+#define OMAP2430_EN_GPIO5_SHIFT                         10
+#define OMAP2430_EN_GPIO5                               (1 << 10)
+#define OMAP2430_EN_MCSPI3_SHIFT                        9
+#define OMAP2430_EN_MCSPI3                              (1 << 9)
+#define OMAP2430_EN_MMCHS2_SHIFT                        8
+#define OMAP2430_EN_MMCHS2                              (1 << 8)
+#define OMAP2430_EN_MMCHS1_SHIFT                        7
+#define OMAP2430_EN_MMCHS1                              (1 << 7)
+#define OMAP24XX_EN_UART3_SHIFT                         2
+#define OMAP24XX_EN_UART3                               (1 << 2)
+#define OMAP24XX_EN_USB_SHIFT                           0
+#define OMAP24XX_EN_USB                                 (1 << 0)
+
+/* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
+#define OMAP2430_EN_MDM_INTC_SHIFT                      11
+#define OMAP2430_EN_MDM_INTC                            (1 << 11)
+#define OMAP2430_EN_USBHS_SHIFT                         6
+#define OMAP2430_EN_USBHS                               (1 << 6)
+
+/* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
+#define OMAP2420_ST_MMC                                 (1 << 26)
+#define OMAP24XX_ST_UART2                               (1 << 22)
+#define OMAP24XX_ST_UART1                               (1 << 21)
+#define OMAP24XX_ST_MCSPI2                              (1 << 18)
+#define OMAP24XX_ST_MCSPI1                              (1 << 17)
+#define OMAP24XX_ST_GPT12                               (1 << 14)
+#define OMAP24XX_ST_GPT11                               (1 << 13)
+#define OMAP24XX_ST_GPT10                               (1 << 12)
+#define OMAP24XX_ST_GPT9                                (1 << 11)
+#define OMAP24XX_ST_GPT8                                (1 << 10)
+#define OMAP24XX_ST_GPT7                                (1 << 9)
+#define OMAP24XX_ST_GPT6                                (1 << 8)
+#define OMAP24XX_ST_GPT5                                (1 << 7)
+#define OMAP24XX_ST_GPT4                                (1 << 6)
+#define OMAP24XX_ST_GPT3                                (1 << 5)
+#define OMAP24XX_ST_GPT2                                (1 << 4)
+#define OMAP2420_ST_VLYNQ                               (1 << 3)
+
+/* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
+#define OMAP2430_ST_MDM_INTC                            (1 << 11)
+#define OMAP2430_ST_GPIO5                               (1 << 10)
+#define OMAP2430_ST_MCSPI3                              (1 << 9)
+#define OMAP2430_ST_MMCHS2                              (1 << 8)
+#define OMAP2430_ST_MMCHS1                              (1 << 7)
+#define OMAP2430_ST_USBHS                               (1 << 6)
+#define OMAP24XX_ST_UART3                               (1 << 2)
+#define OMAP24XX_ST_USB                                 (1 << 0)
+
+/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
+#define OMAP24XX_EN_GPIOS_SHIFT                         2
+#define OMAP24XX_EN_GPIOS                               (1 << 2)
+#define OMAP24XX_EN_GPT1_SHIFT                          0
+#define OMAP24XX_EN_GPT1                                (1 << 0)
+
+/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
+#define OMAP24XX_ST_GPIOS                               (1 << 2)
+#define OMAP24XX_ST_GPT1                                (1 << 0)
+
+/* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
+#define OMAP2430_ST_MDM                                 (1 << 0)
+
+
+/* 3430 register bits shared between CM & PRM registers */
+
+/* CM_REVISION, PRM_REVISION shared bits */
+#define OMAP3430_REV_SHIFT                              0
+#define OMAP3430_REV_MASK                               (0xff << 0)
+
+/* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */
+#define OMAP3430_AUTOIDLE                               (1 << 0)
+
+/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
+#define OMAP3430_EN_MMC2                                (1 << 25)
+#define OMAP3430_EN_MMC2_SHIFT                          25
+#define OMAP3430_EN_MMC1                                (1 << 24)
+#define OMAP3430_EN_MMC1_SHIFT                          24
+#define OMAP3430_EN_MCSPI4                              (1 << 21)
+#define OMAP3430_EN_MCSPI4_SHIFT                        21
+#define OMAP3430_EN_MCSPI3                              (1 << 20)
+#define OMAP3430_EN_MCSPI3_SHIFT                        20
+#define OMAP3430_EN_MCSPI2                              (1 << 19)
+#define OMAP3430_EN_MCSPI2_SHIFT                        19
+#define OMAP3430_EN_MCSPI1                              (1 << 18)
+#define OMAP3430_EN_MCSPI1_SHIFT                        18
+#define OMAP3430_EN_I2C3                                (1 << 17)
+#define OMAP3430_EN_I2C3_SHIFT                          17
+#define OMAP3430_EN_I2C2                                (1 << 16)
+#define OMAP3430_EN_I2C2_SHIFT                          16
+#define OMAP3430_EN_I2C1                                (1 << 15)
+#define OMAP3430_EN_I2C1_SHIFT                          15
+#define OMAP3430_EN_UART2                               (1 << 14)
+#define OMAP3430_EN_UART2_SHIFT                         14
+#define OMAP3430_EN_UART1                               (1 << 13)
+#define OMAP3430_EN_UART1_SHIFT                         13
+#define OMAP3430_EN_GPT11                               (1 << 12)
+#define OMAP3430_EN_GPT11_SHIFT                         12
+#define OMAP3430_EN_GPT10                               (1 << 11)
+#define OMAP3430_EN_GPT10_SHIFT                         11
+#define OMAP3430_EN_MCBSP5                              (1 << 10)
+#define OMAP3430_EN_MCBSP5_SHIFT                        10
+#define OMAP3430_EN_MCBSP1                              (1 << 9)
+#define OMAP3430_EN_MCBSP1_SHIFT                        9
+#define OMAP3430_EN_FSHOSTUSB                           (1 << 5)
+#define OMAP3430_EN_FSHOSTUSB_SHIFT                     5
+#define OMAP3430_EN_D2D                                 (1 << 3)
+#define OMAP3430_EN_D2D_SHIFT                           3
+
+/* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
+#define OMAP3430_EN_HSOTGUSB                            (1 << 4)
+#define OMAP3430_EN_HSOTGUSB_SHIFT                              4
+
+/* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
+#define OMAP3430_ST_MMC2                                (1 << 25)
+#define OMAP3430_ST_MMC1                                (1 << 24)
+#define OMAP3430_ST_MCSPI4                              (1 << 21)
+#define OMAP3430_ST_MCSPI3                              (1 << 20)
+#define OMAP3430_ST_MCSPI2                              (1 << 19)
+#define OMAP3430_ST_MCSPI1                              (1 << 18)
+#define OMAP3430_ST_I2C3                                (1 << 17)
+#define OMAP3430_ST_I2C2                                (1 << 16)
+#define OMAP3430_ST_I2C1                                (1 << 15)
+#define OMAP3430_ST_UART2                               (1 << 14)
+#define OMAP3430_ST_UART1                               (1 << 13)
+#define OMAP3430_ST_GPT11                               (1 << 12)
+#define OMAP3430_ST_GPT10                               (1 << 11)
+#define OMAP3430_ST_MCBSP5                              (1 << 10)
+#define OMAP3430_ST_MCBSP1                              (1 << 9)
+#define OMAP3430_ST_FSHOSTUSB                           (1 << 5)
+#define OMAP3430_ST_HSOTGUSB                            (1 << 4)
+#define OMAP3430_ST_D2D                                 (1 << 3)
+
+/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
+#define OMAP3430_EN_GPIO1                               (1 << 3)
+#define OMAP3430_EN_GPIO1_SHIFT                         3
+#define OMAP3430_EN_GPT1                                (1 << 0)
+#define OMAP3430_EN_GPT1_SHIFT                          0
+
+/* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */
+#define OMAP3430_EN_SR2                                 (1 << 7)
+#define OMAP3430_EN_SR2_SHIFT                           7
+#define OMAP3430_EN_SR1                                 (1 << 6)
+#define OMAP3430_EN_SR1_SHIFT                           6
+
+/* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
+#define OMAP3430_EN_GPT12                               (1 << 1)
+#define OMAP3430_EN_GPT12_SHIFT                         1
+
+/* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
+#define OMAP3430_ST_SR2                                 (1 << 7)
+#define OMAP3430_ST_SR1                                 (1 << 6)
+#define OMAP3430_ST_GPIO1                               (1 << 3)
+#define OMAP3430_ST_GPT12                               (1 << 1)
+#define OMAP3430_ST_GPT1                                (1 << 0)
+
+/*
+ * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM,
+ * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX,
+ * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits
+ */
+#define OMAP3430_EN_MPU                                 (1 << 1)
+#define OMAP3430_EN_MPU_SHIFT                           1
+
+/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */
+#define OMAP3430_EN_GPIO6                               (1 << 17)
+#define OMAP3430_EN_GPIO6_SHIFT                         17
+#define OMAP3430_EN_GPIO5                               (1 << 16)
+#define OMAP3430_EN_GPIO5_SHIFT                         16
+#define OMAP3430_EN_GPIO4                               (1 << 15)
+#define OMAP3430_EN_GPIO4_SHIFT                         15
+#define OMAP3430_EN_GPIO3                               (1 << 14)
+#define OMAP3430_EN_GPIO3_SHIFT                         14
+#define OMAP3430_EN_GPIO2                               (1 << 13)
+#define OMAP3430_EN_GPIO2_SHIFT                         13
+#define OMAP3430_EN_UART3                               (1 << 11)
+#define OMAP3430_EN_UART3_SHIFT                         11
+#define OMAP3430_EN_GPT9                                (1 << 10)
+#define OMAP3430_EN_GPT9_SHIFT                          10
+#define OMAP3430_EN_GPT8                                (1 << 9)
+#define OMAP3430_EN_GPT8_SHIFT                          9
+#define OMAP3430_EN_GPT7                                (1 << 8)
+#define OMAP3430_EN_GPT7_SHIFT                          8
+#define OMAP3430_EN_GPT6                                (1 << 7)
+#define OMAP3430_EN_GPT6_SHIFT                          7
+#define OMAP3430_EN_GPT5                                (1 << 6)
+#define OMAP3430_EN_GPT5_SHIFT                          6
+#define OMAP3430_EN_GPT4                                (1 << 5)
+#define OMAP3430_EN_GPT4_SHIFT                          5
+#define OMAP3430_EN_GPT3                                (1 << 4)
+#define OMAP3430_EN_GPT3_SHIFT                          4
+#define OMAP3430_EN_GPT2                                (1 << 3)
+#define OMAP3430_EN_GPT2_SHIFT                          3
+
+/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */
+/* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits
+ * be ST_* bits instead? */
+#define OMAP3430_EN_MCBSP4                              (1 << 2)
+#define OMAP3430_EN_MCBSP4_SHIFT                        2
+#define OMAP3430_EN_MCBSP3                              (1 << 1)
+#define OMAP3430_EN_MCBSP3_SHIFT                        1
+#define OMAP3430_EN_MCBSP2                              (1 << 0)
+#define OMAP3430_EN_MCBSP2_SHIFT                        0
+
+/* CM_IDLEST_PER, PM_WKST_PER shared bits */
+#define OMAP3430_ST_GPIO6                               (1 << 17)
+#define OMAP3430_ST_GPIO5                               (1 << 16)
+#define OMAP3430_ST_GPIO4                               (1 << 15)
+#define OMAP3430_ST_GPIO3                               (1 << 14)
+#define OMAP3430_ST_GPIO2                               (1 << 13)
+#define OMAP3430_ST_UART3                               (1 << 11)
+#define OMAP3430_ST_GPT9                                (1 << 10)
+#define OMAP3430_ST_GPT8                                (1 << 9)
+#define OMAP3430_ST_GPT7                                (1 << 8)
+#define OMAP3430_ST_GPT6                                (1 << 7)
+#define OMAP3430_ST_GPT5                                (1 << 6)
+#define OMAP3430_ST_GPT4                                (1 << 5)
+#define OMAP3430_ST_GPT3                                (1 << 4)
+#define OMAP3430_ST_GPT2                                (1 << 3)
+
+/* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
+#define OMAP3430_EN_CORE                                (1 << 0)
+
+#endif
+
diff --git a/arch/arm/mach-omap2/prcm-regs.h b/arch/arm/mach-omap2/prcm-regs.h
deleted file mode 100644
index 5e1c4b53ee9d..000000000000
--- a/arch/arm/mach-omap2/prcm-regs.h
+++ /dev/null
@@ -1,483 +0,0 @@
-/*
- * linux/arch/arm/mach-omap2/prcm-regs.h
- *
- * OMAP24XX Power Reset and Clock Management (PRCM) registers
- *
- * Copyright (C) 2005 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_H
-#define __ARCH_ARM_MACH_OMAP2_PRCM_H
-
-/* SET_PERFORMANCE_LEVEL PARAMETERS */
-#define PRCM_HALF_SPEED 1
-#define PRCM_FULL_SPEED 2
-
-#ifndef __ASSEMBLER__
-
-#define PRCM_REG32(offset)      __REG32(OMAP24XX_PRCM_BASE + (offset))
-
-#define PRCM_REVISION           PRCM_REG32(0x000)
-#define PRCM_SYSCONFIG          PRCM_REG32(0x010)
-#define PRCM_IRQSTATUS_MPU      PRCM_REG32(0x018)
-#define PRCM_IRQENABLE_MPU      PRCM_REG32(0x01C)
-#define PRCM_VOLTCTRL           PRCM_REG32(0x050)
-#define PRCM_VOLTST             PRCM_REG32(0x054)
-#define PRCM_CLKSRC_CTRL        PRCM_REG32(0x060)
-#define PRCM_CLKOUT_CTRL        PRCM_REG32(0x070)
-#define PRCM_CLKEMUL_CTRL       PRCM_REG32(0x078)
-#define PRCM_CLKCFG_CTRL        PRCM_REG32(0x080)
-#define PRCM_CLKCFG_STATUS      PRCM_REG32(0x084)
-#define PRCM_VOLTSETUP          PRCM_REG32(0x090)
-#define PRCM_CLKSSETUP          PRCM_REG32(0x094)
-#define PRCM_POLCTRL            PRCM_REG32(0x098)
-
-/* GENERAL PURPOSE */
-#define GENERAL_PURPOSE1        PRCM_REG32(0x0B0)
-#define GENERAL_PURPOSE2        PRCM_REG32(0x0B4)
-#define GENERAL_PURPOSE3        PRCM_REG32(0x0B8)
-#define GENERAL_PURPOSE4        PRCM_REG32(0x0BC)
-#define GENERAL_PURPOSE5        PRCM_REG32(0x0C0)
-#define GENERAL_PURPOSE6        PRCM_REG32(0x0C4)
-#define GENERAL_PURPOSE7        PRCM_REG32(0x0C8)
-#define GENERAL_PURPOSE8        PRCM_REG32(0x0CC)
-#define GENERAL_PURPOSE9        PRCM_REG32(0x0D0)
-#define GENERAL_PURPOSE10       PRCM_REG32(0x0D4)
-#define GENERAL_PURPOSE11       PRCM_REG32(0x0D8)
-#define GENERAL_PURPOSE12       PRCM_REG32(0x0DC)
-#define GENERAL_PURPOSE13       PRCM_REG32(0x0E0)
-#define GENERAL_PURPOSE14       PRCM_REG32(0x0E4)
-#define GENERAL_PURPOSE15       PRCM_REG32(0x0E8)
-#define GENERAL_PURPOSE16       PRCM_REG32(0x0EC)
-#define GENERAL_PURPOSE17       PRCM_REG32(0x0F0)
-#define GENERAL_PURPOSE18       PRCM_REG32(0x0F4)
-#define GENERAL_PURPOSE19       PRCM_REG32(0x0F8)
-#define GENERAL_PURPOSE20       PRCM_REG32(0x0FC)
-
-/* MPU */
-#define CM_CLKSEL_MPU           PRCM_REG32(0x140)
-#define CM_CLKSTCTRL_MPU        PRCM_REG32(0x148)
-#define RM_RSTST_MPU            PRCM_REG32(0x158)
-#define PM_WKDEP_MPU            PRCM_REG32(0x1C8)
-#define PM_EVGENCTRL_MPU        PRCM_REG32(0x1D4)
-#define PM_EVEGENONTIM_MPU      PRCM_REG32(0x1D8)
-#define PM_EVEGENOFFTIM_MPU     PRCM_REG32(0x1DC)
-#define PM_PWSTCTRL_MPU         PRCM_REG32(0x1E0)
-#define PM_PWSTST_MPU           PRCM_REG32(0x1E4)
-
-/* CORE */
-#define CM_FCLKEN1_CORE         PRCM_REG32(0x200)
-#define CM_FCLKEN2_CORE         PRCM_REG32(0x204)
-#define CM_FCLKEN3_CORE         PRCM_REG32(0x208)
-#define CM_ICLKEN1_CORE         PRCM_REG32(0x210)
-#define CM_ICLKEN2_CORE         PRCM_REG32(0x214)
-#define CM_ICLKEN3_CORE         PRCM_REG32(0x218)
-#define CM_ICLKEN4_CORE         PRCM_REG32(0x21C)
-#define CM_IDLEST1_CORE         PRCM_REG32(0x220)
-#define CM_IDLEST2_CORE         PRCM_REG32(0x224)
-#define CM_IDLEST3_CORE         PRCM_REG32(0x228)
-#define CM_IDLEST4_CORE         PRCM_REG32(0x22C)
-#define CM_AUTOIDLE1_CORE       PRCM_REG32(0x230)
-#define CM_AUTOIDLE2_CORE       PRCM_REG32(0x234)
-#define CM_AUTOIDLE3_CORE       PRCM_REG32(0x238)
-#define CM_AUTOIDLE4_CORE       PRCM_REG32(0x23C)
-#define CM_CLKSEL1_CORE         PRCM_REG32(0x240)
-#define CM_CLKSEL2_CORE         PRCM_REG32(0x244)
-#define CM_CLKSTCTRL_CORE       PRCM_REG32(0x248)
-#define PM_WKEN1_CORE           PRCM_REG32(0x2A0)
-#define PM_WKEN2_CORE           PRCM_REG32(0x2A4)
-#define PM_WKST1_CORE           PRCM_REG32(0x2B0)
-#define PM_WKST2_CORE           PRCM_REG32(0x2B4)
-#define PM_WKDEP_CORE           PRCM_REG32(0x2C8)
-#define PM_PWSTCTRL_CORE        PRCM_REG32(0x2E0)
-#define PM_PWSTST_CORE          PRCM_REG32(0x2E4)
-
-/* GFX */
-#define CM_FCLKEN_GFX           PRCM_REG32(0x300)
-#define CM_ICLKEN_GFX           PRCM_REG32(0x310)
-#define CM_IDLEST_GFX           PRCM_REG32(0x320)
-#define CM_CLKSEL_GFX           PRCM_REG32(0x340)
-#define CM_CLKSTCTRL_GFX        PRCM_REG32(0x348)
-#define RM_RSTCTRL_GFX          PRCM_REG32(0x350)
-#define RM_RSTST_GFX            PRCM_REG32(0x358)
-#define PM_WKDEP_GFX            PRCM_REG32(0x3C8)
-#define PM_PWSTCTRL_GFX         PRCM_REG32(0x3E0)
-#define PM_PWSTST_GFX           PRCM_REG32(0x3E4)
-
-/* WAKE-UP */
-#define CM_FCLKEN_WKUP          PRCM_REG32(0x400)
-#define CM_ICLKEN_WKUP          PRCM_REG32(0x410)
-#define CM_IDLEST_WKUP          PRCM_REG32(0x420)
-#define CM_AUTOIDLE_WKUP        PRCM_REG32(0x430)
-#define CM_CLKSEL_WKUP          PRCM_REG32(0x440)
-#define RM_RSTCTRL_WKUP         PRCM_REG32(0x450)
-#define RM_RSTTIME_WKUP         PRCM_REG32(0x454)
-#define RM_RSTST_WKUP           PRCM_REG32(0x458)
-#define PM_WKEN_WKUP            PRCM_REG32(0x4A0)
-#define PM_WKST_WKUP            PRCM_REG32(0x4B0)
-
-/* CLOCKS */
-#define CM_CLKEN_PLL            PRCM_REG32(0x500)
-#define CM_IDLEST_CKGEN         PRCM_REG32(0x520)
-#define CM_AUTOIDLE_PLL         PRCM_REG32(0x530)
-#define CM_CLKSEL1_PLL          PRCM_REG32(0x540)
-#define CM_CLKSEL2_PLL          PRCM_REG32(0x544)
-
-/* DSP */
-#define CM_FCLKEN_DSP           PRCM_REG32(0x800)
-#define CM_ICLKEN_DSP           PRCM_REG32(0x810)
-#define CM_IDLEST_DSP           PRCM_REG32(0x820)
-#define CM_AUTOIDLE_DSP         PRCM_REG32(0x830)
-#define CM_CLKSEL_DSP           PRCM_REG32(0x840)
-#define CM_CLKSTCTRL_DSP        PRCM_REG32(0x848)
-#define RM_RSTCTRL_DSP          PRCM_REG32(0x850)
-#define RM_RSTST_DSP            PRCM_REG32(0x858)
-#define PM_WKEN_DSP             PRCM_REG32(0x8A0)
-#define PM_WKDEP_DSP            PRCM_REG32(0x8C8)
-#define PM_PWSTCTRL_DSP         PRCM_REG32(0x8E0)
-#define PM_PWSTST_DSP           PRCM_REG32(0x8E4)
-#define PRCM_IRQSTATUS_DSP      PRCM_REG32(0x8F0)
-#define PRCM_IRQENABLE_DSP      PRCM_REG32(0x8F4)
-
-/* IVA */
-#define PRCM_IRQSTATUS_IVA      PRCM_REG32(0x8F8)
-#define PRCM_IRQENABLE_IVA      PRCM_REG32(0x8FC)
-
-/* Modem on 2430 */
-#define CM_FCLKEN_MDM           PRCM_REG32(0xC00)
-#define CM_ICLKEN_MDM           PRCM_REG32(0xC10)
-#define CM_IDLEST_MDM           PRCM_REG32(0xC20)
-#define CM_AUTOIDLE_MDM         PRCM_REG32(0xC30)
-#define CM_CLKSEL_MDM           PRCM_REG32(0xC40)
-#define CM_CLKSTCTRL_MDM        PRCM_REG32(0xC48)
-#define RM_RSTCTRL_MDM          PRCM_REG32(0xC50)
-#define RM_RSTST_MDM            PRCM_REG32(0xC58)
-#define PM_WKEN_MDM             PRCM_REG32(0xCA0)
-#define PM_WKST_MDM             PRCM_REG32(0xCB0)
-#define PM_WKDEP_MDM            PRCM_REG32(0xCC8)
-#define PM_PWSTCTRL_MDM         PRCM_REG32(0xCE0)
-#define PM_PWSTST_MDM           PRCM_REG32(0xCE4)
-
-#define OMAP24XX_L4_IO_BASE     0x48000000
-
-#define DISP_BASE               (OMAP24XX_L4_IO_BASE + 0x50000)
-#define DISP_REG32(offset)      __REG32(DISP_BASE + (offset))
-
-#define OMAP24XX_GPMC_BASE      (L3_24XX_BASE + 0xa000)
-#define GPMC_REG32(offset)      __REG32(OMAP24XX_GPMC_BASE + (offset))
-
-/* FIXME: Move these to timer code */
-#define GPT1_BASE               (0x48028000)
-#define GPT1_REG32(offset)      __REG32(GPT1_BASE + (offset))
-
-/* Misc sysconfig */
-#define DISPC_SYSCONFIG         DISP_REG32(0x410)
-#define SPI_BASE                (OMAP24XX_L4_IO_BASE + 0x98000)
-#define MCSPI1_SYSCONFIG        __REG32(SPI_BASE + 0x10)
-#define MCSPI2_SYSCONFIG        __REG32(SPI_BASE + 0x2000 + 0x10)
-#define MCSPI3_SYSCONFIG        __REG32(OMAP24XX_L4_IO_BASE + 0xb8010)
-
-#define CAMERA_MMU_SYSCONFIG    __REG32(DISP_BASE + 0x2C10)
-#define CAMERA_DMA_SYSCONFIG    __REG32(DISP_BASE + 0x282C)
-#define SYSTEM_DMA_SYSCONFIG    __REG32(DISP_BASE + 0x602C)
-#define GPMC_SYSCONFIG          GPMC_REG32(0x010)
-#define MAILBOXES_SYSCONFIG     __REG32(OMAP24XX_L4_IO_BASE + 0x94010)
-#define UART1_SYSCONFIG         __REG32(OMAP24XX_L4_IO_BASE + 0x6A054)
-#define UART2_SYSCONFIG         __REG32(OMAP24XX_L4_IO_BASE + 0x6C054)
-#define UART3_SYSCONFIG         __REG32(OMAP24XX_L4_IO_BASE + 0x6E054)
-#define SDRC_SYSCONFIG          __REG32(OMAP24XX_SDRC_BASE + 0x10)
-#define OMAP24XX_SMS_BASE       (L3_24XX_BASE + 0x8000)
-#define SMS_SYSCONFIG           __REG32(OMAP24XX_SMS_BASE + 0x10)
-#define SSI_SYSCONFIG           __REG32(DISP_BASE + 0x8010)
-
-/* rkw - good cannidates for PM_ to start what nm was trying */
-#define OMAP24XX_GPT2           (OMAP24XX_L4_IO_BASE + 0x2A000)
-#define OMAP24XX_GPT3           (OMAP24XX_L4_IO_BASE + 0x78000)
-#define OMAP24XX_GPT4           (OMAP24XX_L4_IO_BASE + 0x7A000)
-#define OMAP24XX_GPT5           (OMAP24XX_L4_IO_BASE + 0x7C000)
-#define OMAP24XX_GPT6           (OMAP24XX_L4_IO_BASE + 0x7E000)
-#define OMAP24XX_GPT7           (OMAP24XX_L4_IO_BASE + 0x80000)
-#define OMAP24XX_GPT8           (OMAP24XX_L4_IO_BASE + 0x82000)
-#define OMAP24XX_GPT9           (OMAP24XX_L4_IO_BASE + 0x84000)
-#define OMAP24XX_GPT10          (OMAP24XX_L4_IO_BASE + 0x86000)
-#define OMAP24XX_GPT11          (OMAP24XX_L4_IO_BASE + 0x88000)
-#define OMAP24XX_GPT12          (OMAP24XX_L4_IO_BASE + 0x8A000)
-
-/* FIXME: Move these to timer code */
-#define GPTIMER1_SYSCONFIG      GPT1_REG32(0x010)
-#define GPTIMER2_SYSCONFIG      __REG32(OMAP24XX_GPT2 + 0x10)
-#define GPTIMER3_SYSCONFIG      __REG32(OMAP24XX_GPT3 + 0x10)
-#define GPTIMER4_SYSCONFIG      __REG32(OMAP24XX_GPT4 + 0x10)
-#define GPTIMER5_SYSCONFIG      __REG32(OMAP24XX_GPT5 + 0x10)
-#define GPTIMER6_SYSCONFIG      __REG32(OMAP24XX_GPT6 + 0x10)
-#define GPTIMER7_SYSCONFIG      __REG32(OMAP24XX_GPT7 + 0x10)
-#define GPTIMER8_SYSCONFIG      __REG32(OMAP24XX_GPT8 + 0x10)
-#define GPTIMER9_SYSCONFIG      __REG32(OMAP24XX_GPT9 + 0x10)
-#define GPTIMER10_SYSCONFIG     __REG32(OMAP24XX_GPT10 + 0x10)
-#define GPTIMER11_SYSCONFIG     __REG32(OMAP24XX_GPT11 + 0x10)
-#define GPTIMER12_SYSCONFIG     __REG32(OMAP24XX_GPT12 + 0x10)
-
-/* FIXME: Move these to gpio code */
-#define OMAP24XX_GPIO_BASE      0x48018000
-#define GPIOX_BASE(X)           (OMAP24XX_GPIO_BASE + (0x2000 * ((X) - 1)))
-
-#define GPIO1_SYSCONFIG         __REG32((GPIOX_BASE(1) + 0x10))
-#define GPIO2_SYSCONFIG         __REG32((GPIOX_BASE(2) + 0x10))
-#define GPIO3_SYSCONFIG         __REG32((GPIOX_BASE(3) + 0x10))
-#define GPIO4_SYSCONFIG         __REG32((GPIOX_BASE(4) + 0x10))
-
-#if defined(CONFIG_ARCH_OMAP243X)
-#define GPIO5_SYSCONFIG         __REG32((OMAP24XX_GPIO5_BASE + 0x10))
-#endif
-
-/* GP TIMER 1 */
-#define GPTIMER1_TISTAT         GPT1_REG32(0x014)
-#define GPTIMER1_TISR           GPT1_REG32(0x018)
-#define GPTIMER1_TIER           GPT1_REG32(0x01C)
-#define GPTIMER1_TWER           GPT1_REG32(0x020)
-#define GPTIMER1_TCLR           GPT1_REG32(0x024)
-#define GPTIMER1_TCRR           GPT1_REG32(0x028)
-#define GPTIMER1_TLDR           GPT1_REG32(0x02C)
-#define GPTIMER1_TTGR           GPT1_REG32(0x030)
-#define GPTIMER1_TWPS           GPT1_REG32(0x034)
-#define GPTIMER1_TMAR           GPT1_REG32(0x038)
-#define GPTIMER1_TCAR1          GPT1_REG32(0x03C)
-#define GPTIMER1_TSICR          GPT1_REG32(0x040)
-#define GPTIMER1_TCAR2          GPT1_REG32(0x044)
-
-/* rkw -- base fix up please... */
-#define GPTIMER3_TISR           __REG32(OMAP24XX_L4_IO_BASE + 0x78018)
-
-/* SDRC */
-#define SDRC_DLLA_CTRL          __REG32(OMAP24XX_SDRC_BASE + 0x060)
-#define SDRC_DLLA_STATUS        __REG32(OMAP24XX_SDRC_BASE + 0x064)
-#define SDRC_DLLB_CTRL          __REG32(OMAP24XX_SDRC_BASE + 0x068)
-#define SDRC_DLLB_STATUS        __REG32(OMAP24XX_SDRC_BASE + 0x06C)
-#define SDRC_POWER              __REG32(OMAP24XX_SDRC_BASE + 0x070)
-#define SDRC_MR_0               __REG32(OMAP24XX_SDRC_BASE + 0x084)
-
-/* GPIO 1 */
-#define GPIO1_BASE              GPIOX_BASE(1)
-#define GPIO1_REG32(offset)     __REG32(GPIO1_BASE + (offset))
-#define GPIO1_IRQENABLE1        GPIO1_REG32(0x01C)
-#define GPIO1_IRQSTATUS1        GPIO1_REG32(0x018)
-#define GPIO1_IRQENABLE2        GPIO1_REG32(0x02C)
-#define GPIO1_IRQSTATUS2        GPIO1_REG32(0x028)
-#define GPIO1_WAKEUPENABLE      GPIO1_REG32(0x020)
-#define GPIO1_RISINGDETECT      GPIO1_REG32(0x048)
-#define GPIO1_DATAIN            GPIO1_REG32(0x038)
-#define GPIO1_OE                GPIO1_REG32(0x034)
-#define GPIO1_DATAOUT           GPIO1_REG32(0x03C)
-
-/* GPIO2 */
-#define GPIO2_BASE              GPIOX_BASE(2)
-#define GPIO2_REG32(offset)     __REG32(GPIO2_BASE + (offset))
-#define GPIO2_IRQENABLE1        GPIO2_REG32(0x01C)
-#define GPIO2_IRQSTATUS1        GPIO2_REG32(0x018)
-#define GPIO2_IRQENABLE2        GPIO2_REG32(0x02C)
-#define GPIO2_IRQSTATUS2        GPIO2_REG32(0x028)
-#define GPIO2_WAKEUPENABLE      GPIO2_REG32(0x020)
-#define GPIO2_RISINGDETECT      GPIO2_REG32(0x048)
-#define GPIO2_DATAIN            GPIO2_REG32(0x038)
-#define GPIO2_OE                GPIO2_REG32(0x034)
-#define GPIO2_DATAOUT           GPIO2_REG32(0x03C)
-#define GPIO2_DEBOUNCENABLE     GPIO2_REG32(0x050)
-#define GPIO2_DEBOUNCINGTIME    GPIO2_REG32(0x054)
-
-/* GPIO 3 */
-#define GPIO3_BASE              GPIOX_BASE(3)
-#define GPIO3_REG32(offset)     __REG32(GPIO3_BASE + (offset))
-#define GPIO3_IRQENABLE1        GPIO3_REG32(0x01C)
-#define GPIO3_IRQSTATUS1        GPIO3_REG32(0x018)
-#define GPIO3_IRQENABLE2        GPIO3_REG32(0x02C)
-#define GPIO3_IRQSTATUS2        GPIO3_REG32(0x028)
-#define GPIO3_WAKEUPENABLE      GPIO3_REG32(0x020)
-#define GPIO3_RISINGDETECT      GPIO3_REG32(0x048)
-#define GPIO3_FALLINGDETECT     GPIO3_REG32(0x04C)
-#define GPIO3_DATAIN            GPIO3_REG32(0x038)
-#define GPIO3_OE                GPIO3_REG32(0x034)
-#define GPIO3_DATAOUT           GPIO3_REG32(0x03C)
-#define GPIO3_DEBOUNCENABLE     GPIO3_REG32(0x050)
-#define GPIO3_DEBOUNCINGTIME    GPIO3_REG32(0x054)
-#define GPIO3_DEBOUNCENABLE     GPIO3_REG32(0x050)
-#define GPIO3_DEBOUNCINGTIME    GPIO3_REG32(0x054)
-
-/* GPIO 4 */
-#define GPIO4_BASE              GPIOX_BASE(4)
-#define GPIO4_REG32(offset)     __REG32(GPIO4_BASE + (offset))
-#define GPIO4_IRQENABLE1        GPIO4_REG32(0x01C)
-#define GPIO4_IRQSTATUS1        GPIO4_REG32(0x018)
-#define GPIO4_IRQENABLE2        GPIO4_REG32(0x02C)
-#define GPIO4_IRQSTATUS2        GPIO4_REG32(0x028)
-#define GPIO4_WAKEUPENABLE      GPIO4_REG32(0x020)
-#define GPIO4_RISINGDETECT      GPIO4_REG32(0x048)
-#define GPIO4_FALLINGDETECT     GPIO4_REG32(0x04C)
-#define GPIO4_DATAIN            GPIO4_REG32(0x038)
-#define GPIO4_OE                GPIO4_REG32(0x034)
-#define GPIO4_DATAOUT           GPIO4_REG32(0x03C)
-#define GPIO4_DEBOUNCENABLE     GPIO4_REG32(0x050)
-#define GPIO4_DEBOUNCINGTIME    GPIO4_REG32(0x054)
-
-#if defined(CONFIG_ARCH_OMAP243X)
-/* GPIO 5 */
-#define GPIO5_REG32(offset)     __REG32((OMAP24XX_GPIO5_BASE + (offset)))
-#define GPIO5_IRQENABLE1        GPIO5_REG32(0x01C)
-#define GPIO5_IRQSTATUS1        GPIO5_REG32(0x018)
-#define GPIO5_IRQENABLE2        GPIO5_REG32(0x02C)
-#define GPIO5_IRQSTATUS2        GPIO5_REG32(0x028)
-#define GPIO5_WAKEUPENABLE      GPIO5_REG32(0x020)
-#define GPIO5_RISINGDETECT      GPIO5_REG32(0x048)
-#define GPIO5_FALLINGDETECT     GPIO5_REG32(0x04C)
-#define GPIO5_DATAIN            GPIO5_REG32(0x038)
-#define GPIO5_OE                GPIO5_REG32(0x034)
-#define GPIO5_DATAOUT           GPIO5_REG32(0x03C)
-#define GPIO5_DEBOUNCENABLE     GPIO5_REG32(0x050)
-#define GPIO5_DEBOUNCINGTIME    GPIO5_REG32(0x054)
-#endif
-
-/* IO CONFIG */
-#define OMAP24XX_CTRL_BASE              (L4_24XX_BASE)
-#define CONTROL_REG32(offset)           __REG32(OMAP24XX_CTRL_BASE + (offset))
-
-#define CONTROL_PADCONF_SPI1_NCS2       CONTROL_REG32(0x104)
-#define CONTROL_PADCONF_SYS_XTALOUT     CONTROL_REG32(0x134)
-#define CONTROL_PADCONF_UART1_RX        CONTROL_REG32(0x0C8)
-#define CONTROL_PADCONF_MCBSP1_DX       CONTROL_REG32(0x10C)
-#define CONTROL_PADCONF_GPMC_NCS4       CONTROL_REG32(0x090)
-#define CONTROL_PADCONF_DSS_D5          CONTROL_REG32(0x0B8)
-#define CONTROL_PADCONF_DSS_D9          CONTROL_REG32(0x0BC)    /* 2420 */
-#define CONTROL_PADCONF_DSS_D13         CONTROL_REG32(0x0C0)
-#define CONTROL_PADCONF_DSS_VSYNC       CONTROL_REG32(0x0CC)
-#define CONTROL_PADCONF_SYS_NIRQW0      CONTROL_REG32(0x0BC)    /* 2430 */
-#define CONTROL_PADCONF_SSI1_FLAG_TX    CONTROL_REG32(0x108)    /* 2430 */
-
-/* CONTROL */
-#define CONTROL_DEVCONF         CONTROL_REG32(0x274)
-#define CONTROL_DEVCONF1        CONTROL_REG32(0x2E8)
-
-/* INTERRUPT CONTROLLER */
-#define INTC_BASE               ((L4_24XX_BASE) + 0xfe000)
-#define INTC_REG32(offset)      __REG32(INTC_BASE + (offset))
-
-#define INTC1_U_BASE            INTC_REG32(0x000)
-#define INTC_MIR0               INTC_REG32(0x084)
-#define INTC_MIR_SET0           INTC_REG32(0x08C)
-#define INTC_MIR_CLEAR0         INTC_REG32(0x088)
-#define INTC_ISR_CLEAR0         INTC_REG32(0x094)
-#define INTC_MIR1               INTC_REG32(0x0A4)
-#define INTC_MIR_SET1           INTC_REG32(0x0AC)
-#define INTC_MIR_CLEAR1         INTC_REG32(0x0A8)
-#define INTC_ISR_CLEAR1         INTC_REG32(0x0B4)
-#define INTC_MIR2               INTC_REG32(0x0C4)
-#define INTC_MIR_SET2           INTC_REG32(0x0CC)
-#define INTC_MIR_CLEAR2         INTC_REG32(0x0C8)
-#define INTC_ISR_CLEAR2         INTC_REG32(0x0D4)
-#define INTC_SIR_IRQ            INTC_REG32(0x040)
-#define INTC_CONTROL            INTC_REG32(0x048)
-#define INTC_ILR11              INTC_REG32(0x12C)       /* PRCM on MPU PIC */
-#define INTC_ILR30              INTC_REG32(0x178)
-#define INTC_ILR31              INTC_REG32(0x17C)
-#define INTC_ILR32              INTC_REG32(0x180)
-#define INTC_ILR37              INTC_REG32(0x194)       /* GPIO4 on MPU PIC */
-#define INTC_SYSCONFIG          INTC_REG32(0x010)       /* GPT1 on MPU PIC */
-
-/* RAM FIREWALL */
-#define RAMFW_BASE              (0x68005000)
-#define RAMFW_REG32(offset)     __REG32(RAMFW_BASE + (offset))
-
-#define RAMFW_REQINFOPERM0      RAMFW_REG32(0x048)
-#define RAMFW_READPERM0         RAMFW_REG32(0x050)
-#define RAMFW_WRITEPERM0        RAMFW_REG32(0x058)
-
-/* GPMC CS1 FPGA ON USER INTERFACE MODULE */
-//#define DEBUG_BOARD_LED_REGISTER 0x04000014
-
-/* GPMC CS0 */
-#define GPMC_CONFIG1_0          GPMC_REG32(0x060)
-#define GPMC_CONFIG2_0          GPMC_REG32(0x064)
-#define GPMC_CONFIG3_0          GPMC_REG32(0x068)
-#define GPMC_CONFIG4_0          GPMC_REG32(0x06C)
-#define GPMC_CONFIG5_0          GPMC_REG32(0x070)
-#define GPMC_CONFIG6_0          GPMC_REG32(0x074)
-#define GPMC_CONFIG7_0          GPMC_REG32(0x078)
-
-/* GPMC CS1 */
-#define GPMC_CONFIG1_1          GPMC_REG32(0x090)
-#define GPMC_CONFIG2_1          GPMC_REG32(0x094)
-#define GPMC_CONFIG3_1          GPMC_REG32(0x098)
-#define GPMC_CONFIG4_1          GPMC_REG32(0x09C)
-#define GPMC_CONFIG5_1          GPMC_REG32(0x0a0)
-#define GPMC_CONFIG6_1          GPMC_REG32(0x0a4)
-#define GPMC_CONFIG7_1          GPMC_REG32(0x0a8)
-
-/* GPMC CS3 */
-#define GPMC_CONFIG1_3          GPMC_REG32(0x0F0)
-#define GPMC_CONFIG2_3          GPMC_REG32(0x0F4)
-#define GPMC_CONFIG3_3          GPMC_REG32(0x0F8)
-#define GPMC_CONFIG4_3          GPMC_REG32(0x0FC)
-#define GPMC_CONFIG5_3          GPMC_REG32(0x100)
-#define GPMC_CONFIG6_3          GPMC_REG32(0x104)
-#define GPMC_CONFIG7_3          GPMC_REG32(0x108)
-
-/* DSS */
-#define DSS_CONTROL             DISP_REG32(0x040)
-#define DISPC_CONTROL           DISP_REG32(0x440)
-#define DISPC_SYSSTATUS         DISP_REG32(0x414)
-#define DISPC_IRQSTATUS         DISP_REG32(0x418)
-#define DISPC_IRQENABLE         DISP_REG32(0x41C)
-#define DISPC_CONFIG            DISP_REG32(0x444)
-#define DISPC_DEFAULT_COLOR0    DISP_REG32(0x44C)
-#define DISPC_DEFAULT_COLOR1    DISP_REG32(0x450)
-#define DISPC_TRANS_COLOR0      DISP_REG32(0x454)
-#define DISPC_TRANS_COLOR1      DISP_REG32(0x458)
-#define DISPC_LINE_NUMBER       DISP_REG32(0x460)
-#define DISPC_TIMING_H          DISP_REG32(0x464)
-#define DISPC_TIMING_V          DISP_REG32(0x468)
-#define DISPC_POL_FREQ          DISP_REG32(0x46C)
-#define DISPC_DIVISOR           DISP_REG32(0x470)
-#define DISPC_SIZE_DIG          DISP_REG32(0x478)
-#define DISPC_SIZE_LCD          DISP_REG32(0x47C)
-#define DISPC_GFX_BA0           DISP_REG32(0x480)
-#define DISPC_GFX_BA1           DISP_REG32(0x484)
-#define DISPC_GFX_POSITION      DISP_REG32(0x488)
-#define DISPC_GFX_SIZE          DISP_REG32(0x48C)
-#define DISPC_GFX_ATTRIBUTES    DISP_REG32(0x4A0)
-#define DISPC_GFX_FIFO_THRESHOLD        DISP_REG32(0x4A4)
-#define DISPC_GFX_ROW_INC       DISP_REG32(0x4AC)
-#define DISPC_GFX_PIXEL_INC     DISP_REG32(0x4B0)
-#define DISPC_GFX_WINDOW_SKIP   DISP_REG32(0x4B4)
-#define DISPC_GFX_TABLE_BA      DISP_REG32(0x4B8)
-#define DISPC_DATA_CYCLE1       DISP_REG32(0x5D4)
-#define DISPC_DATA_CYCLE2       DISP_REG32(0x5D8)
-#define DISPC_DATA_CYCLE3       DISP_REG32(0x5DC)
-
-/* HSUSB Suspend */
-#define HSUSB_CTRL              __REG8(0x480AC001)
-#define USBOTG_POWER            __REG32(0x480AC000)
-
-/* HS MMC */
-#define MMCHS1_SYSCONFIG        __REG32(0x4809C010)
-#define MMCHS2_SYSCONFIG        __REG32(0x480b4010)
-
-#endif  /* __ASSEMBLER__ */
-
-#endif
-
-
-
-
-
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 90f530540c65..b12f423b8595 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -17,19 +17,27 @@
 #include <linux/init.h>
 #include <linux/clk.h>
 
-#include "prcm-regs.h"
+#include <asm/io.h>
+
+#include "prm.h"
+#include "prm-regbits-24xx.h"
 
 extern void omap2_clk_prepare_for_reboot(void);
 
 u32 omap_prcm_get_reset_sources(void)
 {
-        return RM_RSTST_WKUP & 0x7f;
+        return prm_read_mod_reg(WKUP_MOD, RM_RSTST) & 0x7f;
 }
 EXPORT_SYMBOL(omap_prcm_get_reset_sources);
 
 /* Resets clock rates and reboots the system. Only called from system.h */
 void omap_prcm_arch_reset(char mode)
 {
+        u32 wkup;
         omap2_clk_prepare_for_reboot();
-        RM_RSTCTRL_WKUP |= 2;
+
+        if (cpu_is_omap24xx()) {
+                wkup = prm_read_mod_reg(WKUP_MOD, RM_RSTCTRL) | OMAP_RST_DPLL3;
+                prm_write_mod_reg(wkup, WKUP_MOD, RM_RSTCTRL);
+        }
 }
diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h
new file mode 100644
index 000000000000..c6d17a3378ec
--- /dev/null
+++ b/arch/arm/mach-omap2/prm-regbits-24xx.h
@@ -0,0 +1,279 @@
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H
+
+/*
+ * OMAP24XX Power/Reset Management register bits
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "prm.h"
+
+/* Bits shared between registers */
+
+/* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */
+#define OMAP24XX_VOLTTRANS_ST                           (1 << 2)
+#define OMAP24XX_WKUP2_ST                               (1 << 1)
+#define OMAP24XX_WKUP1_ST                               (1 << 0)
+
+/* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */
+#define OMAP24XX_VOLTTRANS_EN                           (1 << 2)
+#define OMAP24XX_WKUP2_EN                               (1 << 1)
+#define OMAP24XX_WKUP1_EN                               (1 << 0)
+
+/* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */
+#define OMAP24XX_EN_MPU                                 (1 << 1)
+#define OMAP24XX_EN_CORE                                (1 << 0)
+
+/*
+ * PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM
+ * shared bits
+ */
+#define OMAP24XX_MEMONSTATE_SHIFT                       10
+#define OMAP24XX_MEMONSTATE_MASK                        (0x3 << 10)
+#define OMAP24XX_MEMRETSTATE                            (1 << 3)
+
+/* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */
+#define OMAP24XX_FORCESTATE                             (1 << 18)
+
+/*
+ * PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP,
+ * PM_PWSTST_MDM shared bits
+ */
+#define OMAP24XX_CLKACTIVITY                            (1 << 19)
+
+/* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */
+#define OMAP24XX_LASTSTATEENTERED_SHIFT                 4
+#define OMAP24XX_LASTSTATEENTERED_MASK                  (0x3 << 4)
+
+/* PM_PWSTST_MPU and PM_PWSTST_DSP shared bits */
+#define OMAP2430_MEMSTATEST_SHIFT                       10
+#define OMAP2430_MEMSTATEST_MASK                        (0x3 << 10)
+
+/* PM_PWSTST_GFX, PM_PWSTST_DSP, PM_PWSTST_MDM shared bits */
+#define OMAP24XX_POWERSTATEST_SHIFT                     0
+#define OMAP24XX_POWERSTATEST_MASK                      (0x3 << 0)
+
+
+/* Bits specific to each register */
+
+/* PRCM_REVISION */
+#define OMAP24XX_REV_SHIFT                              0
+#define OMAP24XX_REV_MASK                               (0xff << 0)
+
+/* PRCM_SYSCONFIG */
+#define OMAP24XX_AUTOIDLE                               (1 << 0)
+
+/* PRCM_IRQSTATUS_MPU specific bits */
+#define OMAP2430_DPLL_RECAL_ST                          (1 << 6)
+#define OMAP24XX_TRANSITION_ST                          (1 << 5)
+#define OMAP24XX_EVGENOFF_ST                            (1 << 4)
+#define OMAP24XX_EVGENON_ST                             (1 << 3)
+
+/* PRCM_IRQENABLE_MPU specific bits */
+#define OMAP2430_DPLL_RECAL_EN                          (1 << 6)
+#define OMAP24XX_TRANSITION_EN                          (1 << 5)
+#define OMAP24XX_EVGENOFF_EN                            (1 << 4)
+#define OMAP24XX_EVGENON_EN                             (1 << 3)
+
+/* PRCM_VOLTCTRL */
+#define OMAP24XX_AUTO_EXTVOLT                           (1 << 15)
+#define OMAP24XX_FORCE_EXTVOLT                          (1 << 14)
+#define OMAP24XX_SETOFF_LEVEL_SHIFT                     12
+#define OMAP24XX_SETOFF_LEVEL_MASK                      (0x3 << 12)
+#define OMAP24XX_MEMRETCTRL                             (1 << 8)
+#define OMAP24XX_SETRET_LEVEL_SHIFT                     6
+#define OMAP24XX_SETRET_LEVEL_MASK                      (0x3 << 6)
+#define OMAP24XX_VOLT_LEVEL_SHIFT                       0
+#define OMAP24XX_VOLT_LEVEL_MASK                        (0x3 << 0)
+
+/* PRCM_VOLTST */
+#define OMAP24XX_ST_VOLTLEVEL_SHIFT                     0
+#define OMAP24XX_ST_VOLTLEVEL_MASK                      (0x3 << 0)
+
+/* PRCM_CLKSRC_CTRL specific bits */
+
+/* PRCM_CLKOUT_CTRL */
+#define OMAP2420_CLKOUT2_EN_SHIFT                       15
+#define OMAP2420_CLKOUT2_EN                             (1 << 15)
+#define OMAP2420_CLKOUT2_DIV_SHIFT                      11
+#define OMAP2420_CLKOUT2_DIV_MASK                       (0x7 << 11)
+#define OMAP2420_CLKOUT2_SOURCE_SHIFT                   8
+#define OMAP2420_CLKOUT2_SOURCE_MASK                    (0x3 << 8)
+#define OMAP24XX_CLKOUT_EN_SHIFT                        7
+#define OMAP24XX_CLKOUT_EN                              (1 << 7)
+#define OMAP24XX_CLKOUT_DIV_SHIFT                       3
+#define OMAP24XX_CLKOUT_DIV_MASK                        (0x7 << 3)
+#define OMAP24XX_CLKOUT_SOURCE_SHIFT                    0
+#define OMAP24XX_CLKOUT_SOURCE_MASK                     (0x3 << 0)
+
+/* PRCM_CLKEMUL_CTRL */
+#define OMAP24XX_EMULATION_EN_SHIFT                     0
+#define OMAP24XX_EMULATION_EN                           (1 << 0)
+
+/* PRCM_CLKCFG_CTRL */
+#define OMAP24XX_VALID_CONFIG                           (1 << 0)
+
+/* PRCM_CLKCFG_STATUS */
+#define OMAP24XX_CONFIG_STATUS                          (1 << 0)
+
+/* PRCM_VOLTSETUP specific bits */
+
+/* PRCM_CLKSSETUP specific bits */
+
+/* PRCM_POLCTRL */
+#define OMAP2420_CLKOUT2_POL                            (1 << 10)
+#define OMAP24XX_CLKOUT_POL                             (1 << 9)
+#define OMAP24XX_CLKREQ_POL                             (1 << 8)
+#define OMAP2430_USE_POWEROK                            (1 << 2)
+#define OMAP2430_POWEROK_POL                            (1 << 1)
+#define OMAP24XX_EXTVOL_POL                             (1 << 0)
+
+/* RM_RSTST_MPU specific bits */
+/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */
+
+/* PM_WKDEP_MPU specific bits */
+#define OMAP2430_PM_WKDEP_MPU_EN_MDM                    (1 << 5)
+#define OMAP24XX_PM_WKDEP_MPU_EN_DSP                    (1 << 2)
+
+/* PM_EVGENCTRL_MPU specific bits */
+
+/* PM_EVEGENONTIM_MPU specific bits */
+
+/* PM_EVEGENOFFTIM_MPU specific bits */
+
+/* PM_PWSTCTRL_MPU specific bits */
+#define OMAP2430_FORCESTATE                             (1 << 18)
+
+/* PM_PWSTST_MPU specific bits */
+/* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */
+
+/* PM_WKEN1_CORE specific bits */
+
+/* PM_WKEN2_CORE specific bits */
+
+/* PM_WKST1_CORE specific bits*/
+
+/* PM_WKST2_CORE specific bits */
+
+/* PM_WKDEP_CORE specific bits*/
+#define OMAP2430_PM_WKDEP_CORE_EN_MDM                   (1 << 5)
+#define OMAP24XX_PM_WKDEP_CORE_EN_GFX                   (1 << 3)
+#define OMAP24XX_PM_WKDEP_CORE_EN_DSP                   (1 << 2)
+
+/* PM_PWSTCTRL_CORE specific bits */
+#define OMAP24XX_MEMORYCHANGE                           (1 << 20)
+#define OMAP24XX_MEM3ONSTATE_SHIFT                      14
+#define OMAP24XX_MEM3ONSTATE_MASK                       (0x3 << 14)
+#define OMAP24XX_MEM2ONSTATE_SHIFT                      12
+#define OMAP24XX_MEM2ONSTATE_MASK                       (0x3 << 12)
+#define OMAP24XX_MEM1ONSTATE_SHIFT                      10
+#define OMAP24XX_MEM1ONSTATE_MASK                       (0x3 << 10)
+#define OMAP24XX_MEM3RETSTATE                           (1 << 5)
+#define OMAP24XX_MEM2RETSTATE                           (1 << 4)
+#define OMAP24XX_MEM1RETSTATE                           (1 << 3)
+
+/* PM_PWSTST_CORE specific bits */
+#define OMAP24XX_MEM3STATEST_SHIFT                      14
+#define OMAP24XX_MEM3STATEST_MASK                       (0x3 << 14)
+#define OMAP24XX_MEM2STATEST_SHIFT                      12
+#define OMAP24XX_MEM2STATEST_MASK                       (0x3 << 12)
+#define OMAP24XX_MEM1STATEST_SHIFT                      10
+#define OMAP24XX_MEM1STATEST_MASK                       (0x3 << 10)
+
+/* RM_RSTCTRL_GFX */
+#define OMAP24XX_GFX_RST                                (1 << 0)
+
+/* RM_RSTST_GFX specific bits */
+#define OMAP24XX_GFX_SW_RST                             (1 << 4)
+
+/* PM_PWSTCTRL_GFX specific bits */
+
+/* PM_WKDEP_GFX specific bits */
+/* 2430 often calls EN_WAKEUP "EN_WKUP" */
+
+/* RM_RSTCTRL_WKUP specific bits */
+
+/* RM_RSTTIME_WKUP specific bits */
+
+/* RM_RSTST_WKUP specific bits */
+/* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */
+#define OMAP24XX_EXTWMPU_RST                            (1 << 6)
+#define OMAP24XX_SECU_WD_RST                            (1 << 5)
+#define OMAP24XX_MPU_WD_RST                             (1 << 4)
+#define OMAP24XX_SECU_VIOL_RST                          (1 << 3)
+
+/* PM_WKEN_WKUP specific bits */
+
+/* PM_WKST_WKUP specific bits */
+
+/* RM_RSTCTRL_DSP */
+#define OMAP2420_RST_IVA                                (1 << 8)
+#define OMAP24XX_RST2_DSP                               (1 << 1)
+#define OMAP24XX_RST1_DSP                               (1 << 0)
+
+/* RM_RSTST_DSP specific bits */
+/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */
+#define OMAP2420_IVA_SW_RST                             (1 << 8)
+#define OMAP24XX_DSP_SW_RST2                            (1 << 5)
+#define OMAP24XX_DSP_SW_RST1                            (1 << 4)
+
+/* PM_WKDEP_DSP specific bits */
+
+/* PM_PWSTCTRL_DSP specific bits */
+/* 2430 only: MEMONSTATE, MEMRETSTATE */
+#define OMAP2420_MEMIONSTATE_SHIFT                      12
+#define OMAP2420_MEMIONSTATE_MASK                       (0x3 << 12)
+#define OMAP2420_MEMIRETSTATE                           (1 << 4)
+
+/* PM_PWSTST_DSP specific bits */
+/* MEMSTATEST is 2430 only */
+#define OMAP2420_MEMISTATEST_SHIFT                      12
+#define OMAP2420_MEMISTATEST_MASK                       (0x3 << 12)
+
+/* PRCM_IRQSTATUS_DSP specific bits */
+
+/* PRCM_IRQENABLE_DSP specific bits */
+
+/* RM_RSTCTRL_MDM */
+/* 2430 only */
+#define OMAP2430_PWRON1_MDM                             (1 << 1)
+#define OMAP2430_RST1_MDM                               (1 << 0)
+
+/* RM_RSTST_MDM specific bits */
+/* 2430 only */
+#define OMAP2430_MDM_SECU_VIOL                          (1 << 6)
+#define OMAP2430_MDM_SW_PWRON1                          (1 << 5)
+#define OMAP2430_MDM_SW_RST1                            (1 << 4)
+
+/* PM_WKEN_MDM */
+/* 2430 only */
+#define OMAP2430_PM_WKEN_MDM_EN_MDM                     (1 << 0)
+
+/* PM_WKST_MDM specific bits */
+/* 2430 only */
+
+/* PM_WKDEP_MDM specific bits */
+/* 2430 only */
+
+/* PM_PWSTCTRL_MDM specific bits */
+/* 2430 only */
+#define OMAP2430_KILLDOMAINWKUP                         (1 << 19)
+
+/* PM_PWSTST_MDM specific bits */
+/* 2430 only */
+
+/* PRCM_IRQSTATUS_IVA */
+/* 2420 only */
+
+/* PRCM_IRQENABLE_IVA */
+/* 2420 only */
+
+#endif
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
new file mode 100644
index 000000000000..b4686bc345ca
--- /dev/null
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -0,0 +1,582 @@
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
+
+/*
+ * OMAP3430 Power/Reset Management register bits
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "prm.h"
+
+/* Shared register bits */
+
+/* PRM_VC_CMD_VAL_0, PRM_VC_CMD_VAL_1 shared bits */
+#define OMAP3430_ON_SHIFT                               24
+#define OMAP3430_ON_MASK                                (0xff << 24)
+#define OMAP3430_ONLP_SHIFT                             16
+#define OMAP3430_ONLP_MASK                              (0xff << 16)
+#define OMAP3430_RET_SHIFT                              8
+#define OMAP3430_RET_MASK                               (0xff << 8)
+#define OMAP3430_OFF_SHIFT                              0
+#define OMAP3430_OFF_MASK                               (0xff << 0)
+
+/* PRM_VP1_CONFIG, PRM_VP2_CONFIG shared bits */
+#define OMAP3430_ERROROFFSET_SHIFT                      24
+#define OMAP3430_ERROROFFSET_MASK                       (0xff << 24)
+#define OMAP3430_ERRORGAIN_SHIFT                        16
+#define OMAP3430_ERRORGAIN_MASK                         (0xff << 16)
+#define OMAP3430_INITVOLTAGE_SHIFT                      8
+#define OMAP3430_INITVOLTAGE_MASK                       (0xff << 8)
+#define OMAP3430_TIMEOUTEN                              (1 << 3)
+#define OMAP3430_INITVDD                                (1 << 2)
+#define OMAP3430_FORCEUPDATE                            (1 << 1)
+#define OMAP3430_VPENABLE                               (1 << 0)
+
+/* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */
+#define OMAP3430_SMPSWAITTIMEMIN_SHIFT                  8
+#define OMAP3430_SMPSWAITTIMEMIN_MASK                   (0xffff << 8)
+#define OMAP3430_VSTEPMIN_SHIFT                         0
+#define OMAP3430_VSTEPMIN_MASK                          (0xff << 0)
+
+/* PRM_VP1_VSTEPMAX, PRM_VP2_VSTEPMAX shared bits */
+#define OMAP3430_SMPSWAITTIMEMAX_SHIFT                  8
+#define OMAP3430_SMPSWAITTIMEMAX_MASK                   (0xffff << 8)
+#define OMAP3430_VSTEPMAX_SHIFT                         0
+#define OMAP3430_VSTEPMAX_MASK                          (0xff << 0)
+
+/* PRM_VP1_VLIMITTO, PRM_VP2_VLIMITTO shared bits */
+#define OMAP3430_VDDMAX_SHIFT                           24
+#define OMAP3430_VDDMAX_MASK                            (0xff << 24)
+#define OMAP3430_VDDMIN_SHIFT                           16
+#define OMAP3430_VDDMIN_MASK                            (0xff << 16)
+#define OMAP3430_TIMEOUT_SHIFT                          0
+#define OMAP3430_TIMEOUT_MASK                           (0xffff << 0)
+
+/* PRM_VP1_VOLTAGE, PRM_VP2_VOLTAGE shared bits */
+#define OMAP3430_VPVOLTAGE_SHIFT                        0
+#define OMAP3430_VPVOLTAGE_MASK                         (0xff << 0)
+
+/* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */
+#define OMAP3430_VPINIDLE                               (1 << 0)
+
+/* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */
+#define OMAP3430_EN_PER                                 (1 << 7)
+
+/* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */
+#define OMAP3430_MEMORYCHANGE                           (1 << 3)
+
+/* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */
+#define OMAP3430_LOGICSTATEST                           (1 << 2)
+
+/* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */
+#define OMAP3430_LASTLOGICSTATEENTERED                          (1 << 2)
+
+/*
+ * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE,
+ * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM,
+ * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits
+ */
+#define OMAP3430_LASTPOWERSTATEENTERED_SHIFT                    0
+#define OMAP3430_LASTPOWERSTATEENTERED_MASK                     (0x3 << 0)
+
+/* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */
+#define OMAP3430_WKUP_ST                                (1 << 0)
+
+/* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */
+#define OMAP3430_WKUP_EN                                        (1 << 0)
+
+/* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */
+#define OMAP3430_GRPSEL_MMC2                            (1 << 25)
+#define OMAP3430_GRPSEL_MMC1                            (1 << 24)
+#define OMAP3430_GRPSEL_MCSPI4                          (1 << 21)
+#define OMAP3430_GRPSEL_MCSPI3                          (1 << 20)
+#define OMAP3430_GRPSEL_MCSPI2                          (1 << 19)
+#define OMAP3430_GRPSEL_MCSPI1                          (1 << 18)
+#define OMAP3430_GRPSEL_I2C3                            (1 << 17)
+#define OMAP3430_GRPSEL_I2C2                            (1 << 16)
+#define OMAP3430_GRPSEL_I2C1                            (1 << 15)
+#define OMAP3430_GRPSEL_UART2                           (1 << 14)
+#define OMAP3430_GRPSEL_UART1                           (1 << 13)
+#define OMAP3430_GRPSEL_GPT11                           (1 << 12)
+#define OMAP3430_GRPSEL_GPT10                           (1 << 11)
+#define OMAP3430_GRPSEL_MCBSP5                          (1 << 10)
+#define OMAP3430_GRPSEL_MCBSP1                          (1 << 9)
+#define OMAP3430_GRPSEL_HSOTGUSB                        (1 << 4)
+#define OMAP3430_GRPSEL_D2D                             (1 << 3)
+
+/*
+ * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM,
+ * PM_PWSTCTRL_PER shared bits
+ */
+#define OMAP3430_MEMONSTATE_SHIFT                       16
+#define OMAP3430_MEMONSTATE_MASK                        (0x3 << 16)
+#define OMAP3430_MEMRETSTATE                            (1 << 8)
+
+/* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */
+#define OMAP3430_GRPSEL_GPIO6                           (1 << 17)
+#define OMAP3430_GRPSEL_GPIO5                           (1 << 16)
+#define OMAP3430_GRPSEL_GPIO4                           (1 << 15)
+#define OMAP3430_GRPSEL_GPIO3                           (1 << 14)
+#define OMAP3430_GRPSEL_GPIO2                           (1 << 13)
+#define OMAP3430_GRPSEL_UART3                           (1 << 11)
+#define OMAP3430_GRPSEL_GPT9                            (1 << 10)
+#define OMAP3430_GRPSEL_GPT8                            (1 << 9)
+#define OMAP3430_GRPSEL_GPT7                            (1 << 8)
+#define OMAP3430_GRPSEL_GPT6                            (1 << 7)
+#define OMAP3430_GRPSEL_GPT5                            (1 << 6)
+#define OMAP3430_GRPSEL_GPT4                            (1 << 5)
+#define OMAP3430_GRPSEL_GPT3                            (1 << 4)
+#define OMAP3430_GRPSEL_GPT2                            (1 << 3)
+#define OMAP3430_GRPSEL_MCBSP4                          (1 << 2)
+#define OMAP3430_GRPSEL_MCBSP3                          (1 << 1)
+#define OMAP3430_GRPSEL_MCBSP2                          (1 << 0)
+
+/* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */
+#define OMAP3430_GRPSEL_IO                              (1 << 8)
+#define OMAP3430_GRPSEL_SR2                             (1 << 7)
+#define OMAP3430_GRPSEL_SR1                             (1 << 6)
+#define OMAP3430_GRPSEL_GPIO1                           (1 << 3)
+#define OMAP3430_GRPSEL_GPT12                           (1 << 1)
+#define OMAP3430_GRPSEL_GPT1                            (1 << 0)
+
+/* Bits specific to each register */
+
+/* RM_RSTCTRL_IVA2 */
+#define OMAP3430_RST3_IVA2                              (1 << 2)
+#define OMAP3430_RST2_IVA2                              (1 << 1)
+#define OMAP3430_RST1_IVA2                              (1 << 0)
+
+/* RM_RSTST_IVA2 specific bits */
+#define OMAP3430_EMULATION_VSEQ_RST                     (1 << 13)
+#define OMAP3430_EMULATION_VHWA_RST                     (1 << 12)
+#define OMAP3430_EMULATION_IVA2_RST                     (1 << 11)
+#define OMAP3430_IVA2_SW_RST3                           (1 << 10)
+#define OMAP3430_IVA2_SW_RST2                           (1 << 9)
+#define OMAP3430_IVA2_SW_RST1                           (1 << 8)
+
+/* PM_WKDEP_IVA2 specific bits */
+
+/* PM_PWSTCTRL_IVA2 specific bits */
+#define OMAP3430_L2FLATMEMONSTATE_SHIFT                 22
+#define OMAP3430_L2FLATMEMONSTATE_MASK                  (0x3 << 22)
+#define OMAP3430_SHAREDL2CACHEFLATONSTATE_SHIFT         20
+#define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK          (0x3 << 20)
+#define OMAP3430_L1FLATMEMONSTATE_SHIFT                 18
+#define OMAP3430_L1FLATMEMONSTATE_MASK                  (0x3 << 18)
+#define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT         16
+#define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK          (0x3 << 16)
+#define OMAP3430_L2FLATMEMRETSTATE                      (1 << 11)
+#define OMAP3430_SHAREDL2CACHEFLATRETSTATE              (1 << 10)
+#define OMAP3430_L1FLATMEMRETSTATE                      (1 << 9)
+#define OMAP3430_SHAREDL1CACHEFLATRETSTATE              (1 << 8)
+
+/* PM_PWSTST_IVA2 specific bits */
+#define OMAP3430_L2FLATMEMSTATEST_SHIFT                 10
+#define OMAP3430_L2FLATMEMSTATEST_MASK                  (0x3 << 10)
+#define OMAP3430_SHAREDL2CACHEFLATSTATEST_SHIFT         8
+#define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK          (0x3 << 8)
+#define OMAP3430_L1FLATMEMSTATEST_SHIFT                 6
+#define OMAP3430_L1FLATMEMSTATEST_MASK                  (0x3 << 6)
+#define OMAP3430_SHAREDL1CACHEFLATSTATEST_SHIFT         4
+#define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK          (0x3 << 4)
+
+/* PM_PREPWSTST_IVA2 specific bits */
+#define OMAP3430_LASTL2FLATMEMSTATEENTERED_SHIFT                10
+#define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK                 (0x3 << 10)
+#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_SHIFT        8
+#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK         (0x3 << 8)
+#define OMAP3430_LASTL1FLATMEMSTATEENTERED_SHIFT                6
+#define OMAP3430_LASTL1FLATMEMSTATEENTERED_MASK                 (0x3 << 6)
+#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_SHIFT        4
+#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK         (0x3 << 4)
+
+/* PRM_IRQSTATUS_IVA2 specific bits */
+#define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST        (1 << 2)
+#define OMAP3430_FORCEWKUP_ST                           (1 << 1)
+
+/* PRM_IRQENABLE_IVA2 specific bits */
+#define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN          (1 << 2)
+#define OMAP3430_FORCEWKUP_EN                                   (1 << 1)
+
+/* PRM_REVISION specific bits */
+
+/* PRM_SYSCONFIG specific bits */
+
+/* PRM_IRQSTATUS_MPU specific bits */
+#define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT            25
+#define OMAP3430ES2_SND_PERIPH_DPLL_ST                  (1 << 25)
+#define OMAP3430_VC_TIMEOUTERR_ST                       (1 << 24)
+#define OMAP3430_VC_RAERR_ST                            (1 << 23)
+#define OMAP3430_VC_SAERR_ST                            (1 << 22)
+#define OMAP3430_VP2_TRANXDONE_ST                       (1 << 21)
+#define OMAP3430_VP2_EQVALUE_ST                         (1 << 20)
+#define OMAP3430_VP2_NOSMPSACK_ST                       (1 << 19)
+#define OMAP3430_VP2_MAXVDD_ST                          (1 << 18)
+#define OMAP3430_VP2_MINVDD_ST                          (1 << 17)
+#define OMAP3430_VP2_OPPCHANGEDONE_ST                   (1 << 16)
+#define OMAP3430_VP1_TRANXDONE_ST                       (1 << 15)
+#define OMAP3430_VP1_EQVALUE_ST                         (1 << 14)
+#define OMAP3430_VP1_NOSMPSACK_ST                       (1 << 13)
+#define OMAP3430_VP1_MAXVDD_ST                          (1 << 12)
+#define OMAP3430_VP1_MINVDD_ST                          (1 << 11)
+#define OMAP3430_VP1_OPPCHANGEDONE_ST                   (1 << 10)
+#define OMAP3430_IO_ST                                  (1 << 9)
+#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST         (1 << 8)
+#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT   8
+#define OMAP3430_MPU_DPLL_ST                            (1 << 7)
+#define OMAP3430_MPU_DPLL_ST_SHIFT                      7
+#define OMAP3430_PERIPH_DPLL_ST                         (1 << 6)
+#define OMAP3430_PERIPH_DPLL_ST_SHIFT                   6
+#define OMAP3430_CORE_DPLL_ST                           (1 << 5)
+#define OMAP3430_CORE_DPLL_ST_SHIFT                     5
+#define OMAP3430_TRANSITION_ST                          (1 << 4)
+#define OMAP3430_EVGENOFF_ST                            (1 << 3)
+#define OMAP3430_EVGENON_ST                             (1 << 2)
+#define OMAP3430_FS_USB_WKUP_ST                         (1 << 1)
+
+/* PRM_IRQENABLE_MPU specific bits */
+#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT              25
+#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN                    (1 << 25)
+#define OMAP3430_VC_TIMEOUTERR_EN                               (1 << 24)
+#define OMAP3430_VC_RAERR_EN                                    (1 << 23)
+#define OMAP3430_VC_SAERR_EN                                    (1 << 22)
+#define OMAP3430_VP2_TRANXDONE_EN                               (1 << 21)
+#define OMAP3430_VP2_EQVALUE_EN                                 (1 << 20)
+#define OMAP3430_VP2_NOSMPSACK_EN                               (1 << 19)
+#define OMAP3430_VP2_MAXVDD_EN                                  (1 << 18)
+#define OMAP3430_VP2_MINVDD_EN                                  (1 << 17)
+#define OMAP3430_VP2_OPPCHANGEDONE_EN                           (1 << 16)
+#define OMAP3430_VP1_TRANXDONE_EN                               (1 << 15)
+#define OMAP3430_VP1_EQVALUE_EN                                 (1 << 14)
+#define OMAP3430_VP1_NOSMPSACK_EN                               (1 << 13)
+#define OMAP3430_VP1_MAXVDD_EN                                  (1 << 12)
+#define OMAP3430_VP1_MINVDD_EN                                  (1 << 11)
+#define OMAP3430_VP1_OPPCHANGEDONE_EN                           (1 << 10)
+#define OMAP3430_IO_EN                                          (1 << 9)
+#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN           (1 << 8)
+#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT     8
+#define OMAP3430_MPU_DPLL_RECAL_EN                              (1 << 7)
+#define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT                        7
+#define OMAP3430_PERIPH_DPLL_RECAL_EN                           (1 << 6)
+#define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT                     6
+#define OMAP3430_CORE_DPLL_RECAL_EN                             (1 << 5)
+#define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT                       5
+#define OMAP3430_TRANSITION_EN                                  (1 << 4)
+#define OMAP3430_EVGENOFF_EN                                    (1 << 3)
+#define OMAP3430_EVGENON_EN                                     (1 << 2)
+#define OMAP3430_FS_USB_WKUP_EN                                 (1 << 1)
+
+/* RM_RSTST_MPU specific bits */
+#define OMAP3430_EMULATION_MPU_RST                      (1 << 11)
+
+/* PM_WKDEP_MPU specific bits */
+#define OMAP3430_PM_WKDEP_MPU_EN_DSS                    (1 << 5)
+#define OMAP3430_PM_WKDEP_MPU_EN_IVA2                   (1 << 2)
+
+/* PM_EVGENCTRL_MPU */
+#define OMAP3430_OFFLOADMODE_SHIFT                      3
+#define OMAP3430_OFFLOADMODE_MASK                       (0x3 << 3)
+#define OMAP3430_ONLOADMODE_SHIFT                       1
+#define OMAP3430_ONLOADMODE_MASK                        (0x3 << 1)
+#define OMAP3430_ENABLE                                 (1 << 0)
+
+/* PM_EVGENONTIM_MPU */
+#define OMAP3430_ONTIMEVAL_SHIFT                        0
+#define OMAP3430_ONTIMEVAL_MASK                         (0xffffffff << 0)
+
+/* PM_EVGENOFFTIM_MPU */
+#define OMAP3430_OFFTIMEVAL_SHIFT                       0
+#define OMAP3430_OFFTIMEVAL_MASK                        (0xffffffff << 0)
+
+/* PM_PWSTCTRL_MPU specific bits */
+#define OMAP3430_L2CACHEONSTATE_SHIFT                   16
+#define OMAP3430_L2CACHEONSTATE_MASK                    (0x3 << 16)
+#define OMAP3430_L2CACHERETSTATE                        (1 << 8)
+#define OMAP3430_LOGICL1CACHERETSTATE                   (1 << 2)
+
+/* PM_PWSTST_MPU specific bits */
+#define OMAP3430_L2CACHESTATEST_SHIFT                   6
+#define OMAP3430_L2CACHESTATEST_MASK                    (0x3 << 6)
+#define OMAP3430_LOGICL1CACHESTATEST                    (1 << 2)
+
+/* PM_PREPWSTST_MPU specific bits */
+#define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT          6
+#define OMAP3430_LASTL2CACHESTATEENTERED_MASK           (0x3 << 6)
+#define OMAP3430_LASTLOGICL1CACHESTATEENTERED           (1 << 2)
+
+/* RM_RSTCTRL_CORE */
+#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON              (1 << 1)
+#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST                   (1 << 0)
+
+/* RM_RSTST_CORE specific bits */
+#define OMAP3430_MODEM_SECURITY_VIOL_RST                (1 << 10)
+#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON        (1 << 9)
+#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST             (1 << 8)
+
+/* PM_WKEN1_CORE specific bits */
+
+/* PM_MPUGRPSEL1_CORE specific bits */
+#define OMAP3430_GRPSEL_FSHOSTUSB                       (1 << 5)
+
+/* PM_IVA2GRPSEL1_CORE specific bits */
+
+/* PM_WKST1_CORE specific bits */
+
+/* PM_PWSTCTRL_CORE specific bits */
+#define OMAP3430_MEM2ONSTATE_SHIFT                      18
+#define OMAP3430_MEM2ONSTATE_MASK                       (0x3 << 18)
+#define OMAP3430_MEM1ONSTATE_SHIFT                      16
+#define OMAP3430_MEM1ONSTATE_MASK                       (0x3 << 16)
+#define OMAP3430_MEM2RETSTATE                           (1 << 9)
+#define OMAP3430_MEM1RETSTATE                           (1 << 8)
+
+/* PM_PWSTST_CORE specific bits */
+#define OMAP3430_MEM2STATEST_SHIFT                      6
+#define OMAP3430_MEM2STATEST_MASK                       (0x3 << 6)
+#define OMAP3430_MEM1STATEST_SHIFT                      4
+#define OMAP3430_MEM1STATEST_MASK                       (0x3 << 4)
+
+/* PM_PREPWSTST_CORE specific bits */
+#define OMAP3430_LASTMEM2STATEENTERED_SHIFT             6
+#define OMAP3430_LASTMEM2STATEENTERED_MASK              (0x3 << 6)
+#define OMAP3430_LASTMEM1STATEENTERED_SHIFT             4
+#define OMAP3430_LASTMEM1STATEENTERED_MASK              (0x3 << 4)
+
+/* RM_RSTST_GFX specific bits */
+
+/* PM_WKDEP_GFX specific bits */
+#define OMAP3430_PM_WKDEP_GFX_EN_IVA2                   (1 << 2)
+
+/* PM_PWSTCTRL_GFX specific bits */
+
+/* PM_PWSTST_GFX specific bits */
+
+/* PM_PREPWSTST_GFX specific bits */
+
+/* PM_WKEN_WKUP specific bits */
+#define OMAP3430_EN_IO                                  (1 << 8)
+
+/* PM_MPUGRPSEL_WKUP specific bits */
+
+/* PM_IVA2GRPSEL_WKUP specific bits */
+
+/* PM_WKST_WKUP specific bits */
+#define OMAP3430_ST_IO                                  (1 << 8)
+
+/* PRM_CLKSEL */
+#define OMAP3430_SYS_CLKIN_SEL_SHIFT                    0
+#define OMAP3430_SYS_CLKIN_SEL_MASK                     (0x7 << 0)
+
+/* PRM_CLKOUT_CTRL */
+#define OMAP3430_CLKOUT_EN                              (1 << 7)
+#define OMAP3430_CLKOUT_EN_SHIFT                        7
+
+/* RM_RSTST_DSS specific bits */
+
+/* PM_WKEN_DSS */
+#define OMAP3430_PM_WKEN_DSS_EN_DSS                     (1 << 0)
+
+/* PM_WKDEP_DSS specific bits */
+#define OMAP3430_PM_WKDEP_DSS_EN_IVA2                   (1 << 2)
+
+/* PM_PWSTCTRL_DSS specific bits */
+
+/* PM_PWSTST_DSS specific bits */
+
+/* PM_PREPWSTST_DSS specific bits */
+
+/* RM_RSTST_CAM specific bits */
+
+/* PM_WKDEP_CAM specific bits */
+#define OMAP3430_PM_WKDEP_CAM_EN_IVA2                   (1 << 2)
+
+/* PM_PWSTCTRL_CAM specific bits */
+
+/* PM_PWSTST_CAM specific bits */
+
+/* PM_PREPWSTST_CAM specific bits */
+
+/* PM_PWSTCTRL_USBHOST specific bits */
+#define OMAP3430ES2_SAVEANDRESTORE_SHIFT                (1 << 4)
+
+/* RM_RSTST_PER specific bits */
+
+/* PM_WKEN_PER specific bits */
+
+/* PM_MPUGRPSEL_PER specific bits */
+
+/* PM_IVA2GRPSEL_PER specific bits */
+
+/* PM_WKST_PER specific bits */
+
+/* PM_WKDEP_PER specific bits */
+#define OMAP3430_PM_WKDEP_PER_EN_IVA2                   (1 << 2)
+
+/* PM_PWSTCTRL_PER specific bits */
+
+/* PM_PWSTST_PER specific bits */
+
+/* PM_PREPWSTST_PER specific bits */
+
+/* RM_RSTST_EMU specific bits */
+
+/* PM_PWSTST_EMU specific bits */
+
+/* PRM_VC_SMPS_SA */
+#define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT               16
+#define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK                (0x7f << 16)
+#define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT               0
+#define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK                (0x7f << 0)
+
+/* PRM_VC_SMPS_VOL_RA */
+#define OMAP3430_VOLRA1_SHIFT                           16
+#define OMAP3430_VOLRA1_MASK                            (0xff << 16)
+#define OMAP3430_VOLRA0_SHIFT                           0
+#define OMAP3430_VOLRA0_MASK                            (0xff << 0)
+
+/* PRM_VC_SMPS_CMD_RA */
+#define OMAP3430_CMDRA1_SHIFT                           16
+#define OMAP3430_CMDRA1_MASK                            (0xff << 16)
+#define OMAP3430_CMDRA0_SHIFT                           0
+#define OMAP3430_CMDRA0_MASK                            (0xff << 0)
+
+/* PRM_VC_CMD_VAL_0 specific bits */
+
+/* PRM_VC_CMD_VAL_1 specific bits */
+
+/* PRM_VC_CH_CONF */
+#define OMAP3430_CMD1                                   (1 << 20)
+#define OMAP3430_RACEN1                                 (1 << 19)
+#define OMAP3430_RAC1                                   (1 << 18)
+#define OMAP3430_RAV1                                   (1 << 17)
+#define OMAP3430_PRM_VC_CH_CONF_SA1                     (1 << 16)
+#define OMAP3430_CMD0                                   (1 << 4)
+#define OMAP3430_RACEN0                                 (1 << 3)
+#define OMAP3430_RAC0                                   (1 << 2)
+#define OMAP3430_RAV0                                   (1 << 1)
+#define OMAP3430_PRM_VC_CH_CONF_SA0                     (1 << 0)
+
+/* PRM_VC_I2C_CFG */
+#define OMAP3430_HSMASTER                               (1 << 5)
+#define OMAP3430_SREN                                   (1 << 4)
+#define OMAP3430_HSEN                                   (1 << 3)
+#define OMAP3430_MCODE_SHIFT                            0
+#define OMAP3430_MCODE_MASK                             (0x7 << 0)
+
+/* PRM_VC_BYPASS_VAL */
+#define OMAP3430_VALID                                  (1 << 24)
+#define OMAP3430_DATA_SHIFT                             16
+#define OMAP3430_DATA_MASK                              (0xff << 16)
+#define OMAP3430_REGADDR_SHIFT                          8
+#define OMAP3430_REGADDR_MASK                           (0xff << 8)
+#define OMAP3430_SLAVEADDR_SHIFT                        0
+#define OMAP3430_SLAVEADDR_MASK                         (0x7f << 0)
+
+/* PRM_RSTCTRL */
+#define OMAP3430_RST_DPLL3                              (1 << 2)
+#define OMAP3430_RST_GS                                 (1 << 1)
+
+/* PRM_RSTTIME */
+#define OMAP3430_RSTTIME2_SHIFT                         8
+#define OMAP3430_RSTTIME2_MASK                          (0x1f << 8)
+#define OMAP3430_RSTTIME1_SHIFT                         0
+#define OMAP3430_RSTTIME1_MASK                          (0xff << 0)
+
+/* PRM_RSTST */
+#define OMAP3430_ICECRUSHER_RST                         (1 << 10)
+#define OMAP3430_ICEPICK_RST                            (1 << 9)
+#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST               (1 << 8)
+#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST               (1 << 7)
+#define OMAP3430_EXTERNAL_WARM_RST                      (1 << 6)
+#define OMAP3430_SECURE_WD_RST                          (1 << 5)
+#define OMAP3430_MPU_WD_RST                             (1 << 4)
+#define OMAP3430_SECURITY_VIOL_RST                      (1 << 3)
+#define OMAP3430_GLOBAL_SW_RST                          (1 << 1)
+#define OMAP3430_GLOBAL_COLD_RST                        (1 << 0)
+
+/* PRM_VOLTCTRL */
+#define OMAP3430_SEL_VMODE                              (1 << 4)
+#define OMAP3430_SEL_OFF                                (1 << 3)
+#define OMAP3430_AUTO_OFF                               (1 << 2)
+#define OMAP3430_AUTO_RET                               (1 << 1)
+#define OMAP3430_AUTO_SLEEP                             (1 << 0)
+
+/* PRM_SRAM_PCHARGE */
+#define OMAP3430_PCHARGE_TIME_SHIFT                     0
+#define OMAP3430_PCHARGE_TIME_MASK                      (0xff << 0)
+
+/* PRM_CLKSRC_CTRL */
+#define OMAP3430_SYSCLKDIV_SHIFT                        6
+#define OMAP3430_SYSCLKDIV_MASK                         (0x3 << 6)
+#define OMAP3430_AUTOEXTCLKMODE_SHIFT                   3
+#define OMAP3430_AUTOEXTCLKMODE_MASK                    (0x3 << 3)
+#define OMAP3430_SYSCLKSEL_SHIFT                        0
+#define OMAP3430_SYSCLKSEL_MASK                         (0x3 << 0)
+
+/* PRM_VOLTSETUP1 */
+#define OMAP3430_SETUP_TIME2_SHIFT                      16
+#define OMAP3430_SETUP_TIME2_MASK                       (0xffff << 16)
+#define OMAP3430_SETUP_TIME1_SHIFT                      0
+#define OMAP3430_SETUP_TIME1_MASK                       (0xffff << 0)
+
+/* PRM_VOLTOFFSET */
+#define OMAP3430_OFFSET_TIME_SHIFT                      0
+#define OMAP3430_OFFSET_TIME_MASK                       (0xffff << 0)
+
+/* PRM_CLKSETUP */
+#define OMAP3430_SETUP_TIME_SHIFT                       0
+#define OMAP3430_SETUP_TIME_MASK                        (0xffff << 0)
+
+/* PRM_POLCTRL */
+#define OMAP3430_OFFMODE_POL                            (1 << 3)
+#define OMAP3430_CLKOUT_POL                             (1 << 2)
+#define OMAP3430_CLKREQ_POL                             (1 << 1)
+#define OMAP3430_EXTVOL_POL                             (1 << 0)
+
+/* PRM_VOLTSETUP2 */
+#define OMAP3430_OFFMODESETUPTIME_SHIFT                 0
+#define OMAP3430_OFFMODESETUPTIME_MASK                  (0xffff << 0)
+
+/* PRM_VP1_CONFIG specific bits */
+
+/* PRM_VP1_VSTEPMIN specific bits */
+
+/* PRM_VP1_VSTEPMAX specific bits */
+
+/* PRM_VP1_VLIMITTO specific bits */
+
+/* PRM_VP1_VOLTAGE specific bits */
+
+/* PRM_VP1_STATUS specific bits */
+
+/* PRM_VP2_CONFIG specific bits */
+
+/* PRM_VP2_VSTEPMIN specific bits */
+
+/* PRM_VP2_VSTEPMAX specific bits */
+
+/* PRM_VP2_VLIMITTO specific bits */
+
+/* PRM_VP2_VOLTAGE specific bits */
+
+/* PRM_VP2_STATUS specific bits */
+
+/* RM_RSTST_NEON specific bits */
+
+/* PM_WKDEP_NEON specific bits */
+
+/* PM_PWSTCTRL_NEON specific bits */
+
+/* PM_PWSTST_NEON specific bits */
+
+/* PM_PREPWSTST_NEON specific bits */
+
+#endif
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
new file mode 100644
index 000000000000..ab7649afd891
--- /dev/null
+++ b/arch/arm/mach-omap2/prm.h
@@ -0,0 +1,316 @@
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_H
+
+/*
+ * OMAP2/3 Power/Reset Management (PRM) register definitions
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "prcm-common.h"
+
+#ifndef __ASSEMBLER__
+#define OMAP_PRM_REGADDR(module, reg)                                   \
+        (void __iomem *)IO_ADDRESS(OMAP2_PRM_BASE + (module) + (reg))
+#else
+#define OMAP2420_PRM_REGADDR(module, reg)                               \
+                        IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
+#define OMAP2430_PRM_REGADDR(module, reg)                               \
+                        IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
+#define OMAP34XX_PRM_REGADDR(module, reg)                               \
+                        IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
+#endif
+
+/*
+ * Architecture-specific global PRM registers
+ * Use prm_{read,write}_reg() with these registers.
+ *
+ * With a few exceptions, these are the register names beginning with
+ * PRCM_* on 24xx, and PRM_* on 34xx.  (The exceptions are the
+ * IRQSTATUS and IRQENABLE bits.)
+ *
+ */
+
+#define OMAP24XX_PRCM_REVISION          OMAP_PRM_REGADDR(OCP_MOD, 0x0000)
+#define OMAP24XX_PRCM_SYSCONFIG         OMAP_PRM_REGADDR(OCP_MOD, 0x0010)
+
+#define OMAP24XX_PRCM_IRQSTATUS_MPU     OMAP_PRM_REGADDR(OCP_MOD, 0x0018)
+#define OMAP24XX_PRCM_IRQENABLE_MPU     OMAP_PRM_REGADDR(OCP_MOD, 0x001c)
+
+#define OMAP24XX_PRCM_VOLTCTRL          OMAP_PRM_REGADDR(OCP_MOD, 0x0050)
+#define OMAP24XX_PRCM_VOLTST            OMAP_PRM_REGADDR(OCP_MOD, 0x0054)
+#define OMAP24XX_PRCM_CLKSRC_CTRL       OMAP_PRM_REGADDR(OCP_MOD, 0x0060)
+#define OMAP24XX_PRCM_CLKOUT_CTRL       OMAP_PRM_REGADDR(OCP_MOD, 0x0070)
+#define OMAP24XX_PRCM_CLKEMUL_CTRL      OMAP_PRM_REGADDR(OCP_MOD, 0x0078)
+#define OMAP24XX_PRCM_CLKCFG_CTRL       OMAP_PRM_REGADDR(OCP_MOD, 0x0080)
+#define OMAP24XX_PRCM_CLKCFG_STATUS     OMAP_PRM_REGADDR(OCP_MOD, 0x0084)
+#define OMAP24XX_PRCM_VOLTSETUP         OMAP_PRM_REGADDR(OCP_MOD, 0x0090)
+#define OMAP24XX_PRCM_CLKSSETUP         OMAP_PRM_REGADDR(OCP_MOD, 0x0094)
+#define OMAP24XX_PRCM_POLCTRL           OMAP_PRM_REGADDR(OCP_MOD, 0x0098)
+
+#define OMAP3430_PRM_REVISION           OMAP_PRM_REGADDR(OCP_MOD, 0x0004)
+#define OMAP3430_PRM_SYSCONFIG          OMAP_PRM_REGADDR(OCP_MOD, 0x0014)
+
+#define OMAP3430_PRM_IRQSTATUS_MPU      OMAP_PRM_REGADDR(OCP_MOD, 0x0018)
+#define OMAP3430_PRM_IRQENABLE_MPU      OMAP_PRM_REGADDR(OCP_MOD, 0x001c)
+
+
+#define OMAP3430_PRM_VC_SMPS_SA         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
+#define OMAP3430_PRM_VC_SMPS_VOL_RA     OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
+#define OMAP3430_PRM_VC_SMPS_CMD_RA     OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
+#define OMAP3430_PRM_VC_CMD_VAL_0       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
+#define OMAP3430_PRM_VC_CMD_VAL_1       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
+#define OMAP3430_PRM_VC_CH_CONF         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
+#define OMAP3430_PRM_VC_I2C_CFG         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
+#define OMAP3430_PRM_VC_BYPASS_VAL      OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
+#define OMAP3430_PRM_RSTCTRL            OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
+#define OMAP3430_PRM_RSTTIME            OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
+#define OMAP3430_PRM_RSTST              OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
+#define OMAP3430_PRM_VOLTCTRL           OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
+#define OMAP3430_PRM_SRAM_PCHARGE       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
+#define OMAP3430_PRM_CLKSRC_CTRL        OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
+#define OMAP3430_PRM_VOLTSETUP1         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
+#define OMAP3430_PRM_VOLTOFFSET         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
+#define OMAP3430_PRM_CLKSETUP           OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
+#define OMAP3430_PRM_POLCTRL            OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
+#define OMAP3430_PRM_VOLTSETUP2         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
+#define OMAP3430_PRM_VP1_CONFIG         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
+#define OMAP3430_PRM_VP1_VSTEPMIN       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
+#define OMAP3430_PRM_VP1_VSTEPMAX       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
+#define OMAP3430_PRM_VP1_VLIMITTO       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
+#define OMAP3430_PRM_VP1_VOLTAGE        OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
+#define OMAP3430_PRM_VP1_STATUS         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
+#define OMAP3430_PRM_VP2_CONFIG         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
+#define OMAP3430_PRM_VP2_VSTEPMIN       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
+#define OMAP3430_PRM_VP2_VSTEPMAX       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
+#define OMAP3430_PRM_VP2_VLIMITTO       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
+#define OMAP3430_PRM_VP2_VOLTAGE        OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
+#define OMAP3430_PRM_VP2_STATUS         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
+
+#define OMAP3430_PRM_CLKSEL             OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
+#define OMAP3430_PRM_CLKOUT_CTRL        OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
+
+/*
+ * Module specific PRM registers from PRM_BASE + domain offset
+ *
+ * Use prm_{read,write}_mod_reg() with these registers.
+ *
+ * With a few exceptions, these are the register names beginning with
+ * {PM,RM}_* on both architectures.  (The exceptions are the IRQSTATUS
+ * and IRQENABLE bits.)
+ *
+ */
+
+/* Registers appearing on both 24xx and 34xx */
+
+#define RM_RSTCTRL                                      0x0050
+#define RM_RSTTIME                                      0x0054
+#define RM_RSTST                                        0x0058
+
+#define PM_WKEN                                         0x00a0
+#define PM_WKEN1                                        PM_WKEN
+#define PM_WKST                                         0x00b0
+#define PM_WKST1                                        PM_WKST
+#define PM_WKDEP                                        0x00c8
+#define PM_EVGENCTRL                                    0x00d4
+#define PM_EVGENONTIM                                   0x00d8
+#define PM_EVGENOFFTIM                                  0x00dc
+#define PM_PWSTCTRL                                     0x00e0
+#define PM_PWSTST                                       0x00e4
+
+#define OMAP3430_PM_MPUGRPSEL                           0x00a4
+#define OMAP3430_PM_MPUGRPSEL1                          OMAP3430_PM_MPUGRPSEL
+
+#define OMAP3430_PM_IVAGRPSEL                           0x00a8
+#define OMAP3430_PM_IVAGRPSEL1                          OMAP3430_PM_IVAGRPSEL
+
+#define OMAP3430_PM_PREPWSTST                           0x00e8
+
+#define OMAP3430_PRM_IRQSTATUS_IVA2                     0x00f8
+#define OMAP3430_PRM_IRQENABLE_IVA2                     0x00fc
+
+
+/* Architecture-specific registers */
+
+#define OMAP24XX_PM_WKEN2                               0x00a4
+#define OMAP24XX_PM_WKST2                               0x00b4
+
+#define OMAP24XX_PRCM_IRQSTATUS_DSP                     0x00f0  /* IVA mod */
+#define OMAP24XX_PRCM_IRQENABLE_DSP                     0x00f4  /* IVA mod */
+#define OMAP24XX_PRCM_IRQSTATUS_IVA                     0x00f8
+#define OMAP24XX_PRCM_IRQENABLE_IVA                     0x00fc
+
+#ifndef __ASSEMBLER__
+
+/* Power/reset management domain register get/set */
+
+static inline void prm_write_mod_reg(u32 val, s16 module, s16 idx)
+{
+        __raw_writel(val, OMAP_PRM_REGADDR(module, idx));
+}
+
+static inline u32 prm_read_mod_reg(s16 module, s16 idx)
+{
+        return __raw_readl(OMAP_PRM_REGADDR(module, idx));
+}
+
+#endif
+
+/*
+ * Bits common to specific registers
+ *
+ * The 3430 register and bit names are generally used,
+ * since they tend to make more sense
+ */
+
+/* PM_EVGENONTIM_MPU */
+/* Named PM_EVEGENONTIM_MPU on the 24XX */
+#define OMAP_ONTIMEVAL_SHIFT                            0
+#define OMAP_ONTIMEVAL_MASK                             (0xffffffff << 0)
+
+/* PM_EVGENOFFTIM_MPU */
+/* Named PM_EVEGENOFFTIM_MPU on the 24XX */
+#define OMAP_OFFTIMEVAL_SHIFT                           0
+#define OMAP_OFFTIMEVAL_MASK                            (0xffffffff << 0)
+
+/* PRM_CLKSETUP and PRCM_VOLTSETUP */
+/* Named PRCM_CLKSSETUP on the 24XX */
+#define OMAP_SETUP_TIME_SHIFT                           0
+#define OMAP_SETUP_TIME_MASK                            (0xffff << 0)
+
+/* PRM_CLKSRC_CTRL */
+/* Named PRCM_CLKSRC_CTRL on the 24XX */
+#define OMAP_SYSCLKDIV_SHIFT                            6
+#define OMAP_SYSCLKDIV_MASK                             (0x3 << 6)
+#define OMAP_AUTOEXTCLKMODE_SHIFT                       3
+#define OMAP_AUTOEXTCLKMODE_MASK                        (0x3 << 3)
+#define OMAP_SYSCLKSEL_SHIFT                            0
+#define OMAP_SYSCLKSEL_MASK                             (0x3 << 0)
+
+/* PM_EVGENCTRL_MPU */
+#define OMAP_OFFLOADMODE_SHIFT                          3
+#define OMAP_OFFLOADMODE_MASK                           (0x3 << 3)
+#define OMAP_ONLOADMODE_SHIFT                           1
+#define OMAP_ONLOADMODE_MASK                            (0x3 << 1)
+#define OMAP_ENABLE                                     (1 << 0)
+
+/* PRM_RSTTIME */
+/* Named RM_RSTTIME_WKUP on the 24xx */
+#define OMAP_RSTTIME2_SHIFT                             8
+#define OMAP_RSTTIME2_MASK                              (0x1f << 8)
+#define OMAP_RSTTIME1_SHIFT                             0
+#define OMAP_RSTTIME1_MASK                              (0xff << 0)
+
+
+/* PRM_RSTCTRL */
+/* Named RM_RSTCTRL_WKUP on the 24xx */
+/* 2420 calls RST_DPLL3 'RST_DPLL' */
+#define OMAP_RST_DPLL3                                  (1 << 2)
+#define OMAP_RST_GS                                     (1 << 1)
+
+
+/*
+ * Bits common to module-shared registers
+ *
+ * Not all registers of a particular type support all of these bits -
+ * check TRM if you are unsure
+ */
+
+/*
+ * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
+ *
+ * 2430: PM_PWSTST_MDM
+ *
+ * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
+ *       PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
+ *       PM_PWSTST_NEON
+ */
+#define OMAP_INTRANSITION                               (1 << 20)
+
+
+/*
+ * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP
+ *
+ * 2430: PM_PWSTST_MDM
+ *
+ * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
+ *       PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
+ *       PM_PWSTST_NEON
+ */
+#define OMAP_POWERSTATEST_SHIFT                         0
+#define OMAP_POWERSTATEST_MASK                          (0x3 << 0)
+
+/*
+ * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
+ *       called 'COREWKUP_RST'
+ *
+ * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
+ *       RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
+ */
+#define OMAP_COREDOMAINWKUP_RST                         (1 << 3)
+
+/*
+ * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
+ *
+ * 2430: RM_RSTST_MDM
+ *
+ * 3430: RM_RSTST_CORE, RM_RSTST_EMU
+ */
+#define OMAP_DOMAINWKUP_RST                             (1 << 2)
+
+/*
+ * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
+ *       On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
+ *
+ * 2430: RM_RSTST_MDM
+ *
+ * 3430: RM_RSTST_CORE, RM_RSTST_EMU
+ */
+#define OMAP_GLOBALWARM_RST                             (1 << 1)
+#define OMAP_GLOBALCOLD_RST                             (1 << 0)
+
+/*
+ * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
+ *       2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
+ *
+ * 2430: PM_WKDEP_MDM
+ *
+ * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
+ *       PM_WKDEP_PER
+ */
+#define OMAP_EN_WKUP                                    (1 << 4)
+
+/*
+ * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
+ *       PM_PWSTCTRL_DSP
+ *
+ * 2430: PM_PWSTCTRL_MDM
+ *
+ * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
+ *       PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
+ *       PM_PWSTCTRL_NEON
+ */
+#define OMAP_LOGICRETSTATE                              (1 << 2)
+
+/*
+ * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
+ *       PM_PWSTCTRL_DSP, PM_PWSTST_MPU
+ *
+ * 2430: PM_PWSTCTRL_MDM shared bits
+ *
+ * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE,
+ *       PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
+ *       PM_PWSTCTRL_NEON shared bits
+ */
+#define OMAP_POWERSTATE_SHIFT                           0
+#define OMAP_POWERSTATE_MASK                            (0x3 << 0)
+
+
+#endif
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h
new file mode 100644
index 000000000000..d7f23bc9550a
--- /dev/null
+++ b/arch/arm/mach-omap2/sdrc.h
@@ -0,0 +1,58 @@
+#ifndef __ARCH_ARM_MACH_OMAP2_SDRC_H
+#define __ARCH_ARM_MACH_OMAP2_SDRC_H
+
+/*
+ * OMAP2 SDRC register definitions
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <asm/arch/sdrc.h>
+
+#ifndef __ASSEMBLER__
+extern unsigned long omap2_sdrc_base;
+extern unsigned long omap2_sms_base;
+
+#define OMAP_SDRC_REGADDR(reg)                                          \
+                (void __iomem *)IO_ADDRESS(omap2_sdrc_base + (reg))
+#define OMAP_SMS_REGADDR(reg)                                           \
+                (void __iomem *)IO_ADDRESS(omap2_sms_base + (reg))
+
+/* SDRC global register get/set */
+
+static inline void sdrc_write_reg(u32 val, u16 reg)
+{
+        __raw_writel(val, OMAP_SDRC_REGADDR(reg));
+}
+
+static inline u32 sdrc_read_reg(u16 reg)
+{
+        return __raw_readl(OMAP_SDRC_REGADDR(reg));
+}
+
+/* SMS global register get/set */
+
+static inline void sms_write_reg(u32 val, u16 reg)
+{
+        __raw_writel(val, OMAP_SMS_REGADDR(reg));
+}
+
+static inline u32 sms_read_reg(u16 reg)
+{
+        return __raw_readl(OMAP_SMS_REGADDR(reg));
+}
+#else
+#define OMAP242X_SDRC_REGADDR(reg)      IO_ADDRESS(OMAP2420_SDRC_BASE + (reg))
+#define OMAP243X_SDRC_REGADDR(reg)      IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
+#define OMAP34XX_SDRC_REGADDR(reg)      IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
+#endif  /* __ASSEMBLER__ */
+
+#endif
diff --git a/arch/arm/mach-omap2/sleep.S b/arch/arm/mach-omap2/sleep.S
index 16247d557853..46ccb9b8b583 100644
--- a/arch/arm/mach-omap2/sleep.S
+++ b/arch/arm/mach-omap2/sleep.S
@@ -26,19 +26,10 @@
 #include <asm/arch/io.h>
 #include <asm/arch/pm.h>
 
-#define A_32KSYNC_CR_V          IO_ADDRESS(OMAP_TIMER32K_BASE+0x10)
-#define A_PRCM_VOLTCTRL_V       IO_ADDRESS(OMAP24XX_PRCM_BASE+0x50)
-#define A_PRCM_CLKCFG_CTRL_V    IO_ADDRESS(OMAP24XX_PRCM_BASE+0x80)
-#define A_CM_CLKEN_PLL_V        IO_ADDRESS(OMAP24XX_PRCM_BASE+0x500)
-#define A_CM_IDLEST_CKGEN_V     IO_ADDRESS(OMAP24XX_PRCM_BASE+0x520)
-#define A_CM_CLKSEL1_PLL_V      IO_ADDRESS(OMAP24XX_PRCM_BASE+0x540)
-#define A_CM_CLKSEL2_PLL_V      IO_ADDRESS(OMAP24XX_PRCM_BASE+0x544)
+#include "sdrc.h"
 
-#define A_SDRC_DLLA_CTRL_V      IO_ADDRESS(OMAP24XX_SDRC_BASE+0x60)
-#define A_SDRC_POWER_V          IO_ADDRESS(OMAP24XX_SDRC_BASE+0x70)
-#define A_SDRC_RFR_CTRL_V       IO_ADDRESS(OMAP24XX_SDRC_BASE+0xA4)
+/* First address of reserved address space?  apparently valid for OMAP2 & 3 */
 #define A_SDRC0_V               (0xC0000000)
-#define A_SDRC_MANUAL_V         IO_ADDRESS(OMAP24XX_SDRC_BASE+0xA8)
 
         .text
 
@@ -126,17 +117,11 @@ loop2:
         ldmfd   sp!, {r0 - r12, pc}     @ restore regs and return
 
 A_SDRC_POWER:
-        .word A_SDRC_POWER_V
+        .word OMAP242X_SDRC_REGADDR(SDRC_POWER)
 A_SDRC0:
         .word A_SDRC0_V
-A_CM_CLKSEL2_PLL_S:
-        .word A_CM_CLKSEL2_PLL_V
-A_CM_CLKEN_PLL:
-        .word A_CM_CLKEN_PLL_V
 A_SDRC_DLLA_CTRL_S:
-        .word A_SDRC_DLLA_CTRL_V
-A_SDRC_MANUAL_S:
-        .word A_SDRC_MANUAL_V
+        .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
 
 ENTRY(omap24xx_cpu_suspend_sz)
         .word   . - omap24xx_cpu_suspend
diff --git a/arch/arm/mach-omap2/sram-fn.S b/arch/arm/mach-omap2/sram-fn.S
index b27576690f8d..4a9e49140716 100644
--- a/arch/arm/mach-omap2/sram-fn.S
+++ b/arch/arm/mach-omap2/sram-fn.S
@@ -27,19 +27,11 @@
 #include <asm/arch/io.h>
 #include <asm/hardware.h>
 
-#include "prcm-regs.h"
+#include "sdrc.h"
+#include "prm.h"
+#include "cm.h"
 
-#define TIMER_32KSYNCT_CR_V     IO_ADDRESS(OMAP24XX_32KSYNCT_BASE + 0x010)
-
-#define CM_CLKSEL2_PLL_V        IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x544)
-#define PRCM_VOLTCTRL_V         IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x050)
-#define PRCM_CLKCFG_CTRL_V      IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x080)
-#define CM_CLKEN_PLL_V          IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x500)
-#define CM_IDLEST_CKGEN_V       IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x520)
-#define CM_CLKSEL1_PLL_V        IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x540)
-
-#define SDRC_DLLA_CTRL_V        IO_ADDRESS(OMAP24XX_SDRC_BASE + 0x060)
-#define SDRC_RFR_CTRL_V         IO_ADDRESS(OMAP24XX_SDRC_BASE + 0x0a4)
+#define TIMER_32KSYNCT_CR_V     IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
 
         .text
 
@@ -131,11 +123,11 @@ volt_delay:
 
 /* relative load constants */
 cm_clksel2_pll:
-        .word CM_CLKSEL2_PLL_V
+        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
 sdrc_dlla_ctrl:
-        .word SDRC_DLLA_CTRL_V
+        .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
 prcm_voltctrl:
-        .word PRCM_VOLTCTRL_V
+        .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x50)
 prcm_mask_val:
         .word 0xFFFF3FFC
 timer_32ksynct_cr:
@@ -225,13 +217,13 @@ volt_delay_c:
         mov     pc, lr                  @ back to caller
 
 ddr_cm_clksel2_pll:
-        .word CM_CLKSEL2_PLL_V
+        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
 ddr_sdrc_dlla_ctrl:
-        .word SDRC_DLLA_CTRL_V
+        .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
 ddr_sdrc_rfr_ctrl:
-        .word SDRC_RFR_CTRL_V
+        .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
 ddr_prcm_voltctrl:
-        .word PRCM_VOLTCTRL_V
+        .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x50)
 ddr_prcm_mask_val:
         .word 0xFFFF3FFC
 ddr_timer_32ksynct:
@@ -316,17 +308,17 @@ wait_dll_lock:
         ldmfd   sp!, {r0-r12, pc}       @ restore regs and return
 
 set_config:
-        .word PRCM_CLKCFG_CTRL_V
+        .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x80)
 pll_ctl:
-        .word CM_CLKEN_PLL_V
+        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_FCLKEN1)
 pll_stat:
-        .word CM_IDLEST_CKGEN_V
+        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_IDLEST1)
 pll_div:
-        .word CM_CLKSEL1_PLL_V
+        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL)
 sdrc_rfr:
-        .word SDRC_RFR_CTRL_V
+        .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
 dlla_ctrl:
-        .word SDRC_DLLA_CTRL_V
+        .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
 
 ENTRY(sram_set_prcm_sz)
         .word   . - sram_set_prcm
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index 3234deedb946..78d05f203fff 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -3,6 +3,11 @@
  *
  * OMAP2 GP timer support.
  *
+ * Update to use new clocksource/clockevent layers
+ * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *
+ * Original driver:
  * Copyright (C) 2005 Nokia Corporation
  * Author: Paul Mundt <paul.mundt@nokia.com>
  *         Juha Yrjölä <juha.yrjola@nokia.com>
@@ -25,24 +30,23 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/irq.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
 
 #include <asm/mach/time.h>
 #include <asm/arch/dmtimer.h>
 
 static struct omap_dm_timer *gptimer;
-
-static inline void omap2_gp_timer_start(unsigned long load_val)
-{
-        omap_dm_timer_set_load(gptimer, 1, 0xffffffff - load_val);
-        omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
-        omap_dm_timer_start(gptimer);
-}
+static struct clock_event_device clockevent_gpt;
 
 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
 {
-        omap_dm_timer_write_status(gptimer, OMAP_TIMER_INT_OVERFLOW);
-        timer_tick();
+        struct omap_dm_timer *gpt = (struct omap_dm_timer *)dev_id;
+        struct clock_event_device *evt = &clockevent_gpt;
+
+        omap_dm_timer_write_status(gpt, OMAP_TIMER_INT_OVERFLOW);
 
+        evt->event_handler(evt);
         return IRQ_HANDLED;
 }
 
@@ -52,20 +56,138 @@ static struct irqaction omap2_gp_timer_irq = {
         .handler        = omap2_gp_timer_interrupt,
 };
 
-static void __init omap2_gp_timer_init(void)
+static int omap2_gp_timer_set_next_event(unsigned long cycles,
+                                         struct clock_event_device *evt)
 {
-        u32 tick_period;
+        omap_dm_timer_set_load(gptimer, 0, 0xffffffff - cycles);
+        omap_dm_timer_start(gptimer);
+
+        return 0;
+}
+
+static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
+                                    struct clock_event_device *evt)
+{
+        u32 period;
+
+        omap_dm_timer_stop(gptimer);
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
+                period -= 1;
+
+                omap_dm_timer_set_load(gptimer, 1, 0xffffffff - period);
+                omap_dm_timer_start(gptimer);
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+                break;
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_RESUME:
+                break;
+        }
+}
+
+static struct clock_event_device clockevent_gpt = {
+        .name           = "gp timer",
+        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+        .shift          = 32,
+        .set_next_event = omap2_gp_timer_set_next_event,
+        .set_mode       = omap2_gp_timer_set_mode,
+};
+
+static void __init omap2_gp_clockevent_init(void)
+{
+        u32 tick_rate;
 
-        omap_dm_timer_init();
         gptimer = omap_dm_timer_request_specific(1);
         BUG_ON(gptimer == NULL);
 
+#if defined(CONFIG_OMAP_32K_TIMER)
+        omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ);
+#else
         omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_SYS_CLK);
-        tick_period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
-        tick_period -= 1;
+#endif
+        tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer));
 
+        omap2_gp_timer_irq.dev_id = (void *)gptimer;
         setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq);
-        omap2_gp_timer_start(tick_period);
+        omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
+
+        clockevent_gpt.mult = div_sc(tick_rate, NSEC_PER_SEC,
+                                     clockevent_gpt.shift);
+        clockevent_gpt.max_delta_ns =
+                clockevent_delta2ns(0xffffffff, &clockevent_gpt);
+        clockevent_gpt.min_delta_ns =
+                clockevent_delta2ns(1, &clockevent_gpt);
+
+        clockevent_gpt.cpumask = cpumask_of_cpu(0);
+        clockevents_register_device(&clockevent_gpt);
+}
+
+#ifdef CONFIG_OMAP_32K_TIMER
+/* 
+ * When 32k-timer is enabled, don't use GPTimer for clocksource
+ * instead, just leave default clocksource which uses the 32k
+ * sync counter.  See clocksource setup in see plat-omap/common.c. 
+ */
+
+static inline void __init omap2_gp_clocksource_init(void) {}
+#else
+/*
+ * clocksource
+ */
+static struct omap_dm_timer *gpt_clocksource;
+static cycle_t clocksource_read_cycles(void)
+{
+        return (cycle_t)omap_dm_timer_read_counter(gpt_clocksource);
+}
+
+static struct clocksource clocksource_gpt = {
+        .name           = "gp timer",
+        .rating         = 300,
+        .read           = clocksource_read_cycles,
+        .mask           = CLOCKSOURCE_MASK(32),
+        .shift          = 24,
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+/* Setup free-running counter for clocksource */
+static void __init omap2_gp_clocksource_init(void)
+{
+        static struct omap_dm_timer *gpt;
+        u32 tick_rate, tick_period;
+        static char err1[] __initdata = KERN_ERR
+                "%s: failed to request dm-timer\n";
+        static char err2[] __initdata = KERN_ERR
+                "%s: can't register clocksource!\n";
+
+        gpt = omap_dm_timer_request();
+        if (!gpt)
+                printk(err1, clocksource_gpt.name);
+        gpt_clocksource = gpt;
+
+        omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK);
+        tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt));
+        tick_period = (tick_rate / HZ) - 1;
+
+        omap_dm_timer_set_load(gpt, 1, 0);
+        omap_dm_timer_start(gpt);
+
+        clocksource_gpt.mult =
+                clocksource_khz2mult(tick_rate/1000, clocksource_gpt.shift);
+        if (clocksource_register(&clocksource_gpt))
+                printk(err2, clocksource_gpt.name);
+}
+#endif
+
+static void __init omap2_gp_timer_init(void)
+{
+        omap_dm_timer_init();
+
+        omap2_gp_clockevent_init();
+        omap2_gp_clocksource_init();
 }
 
 struct sys_timer omap_timer = {
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 8f56c255d1ee..bc639a30d6d1 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -9,8 +9,6 @@ obj-m :=
 obj-n :=
 obj-  :=
 
-obj-$(CONFIG_OMAP_32K_TIMER)    += timer32k.o
-
 # OCPI interconnect support for 1710, 1610 and 5912
 obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
 
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 0a603242f367..32a533ba9ada 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -304,6 +304,23 @@ void propagate_rate(struct clk * tclk)
         }
 }
 
+/**
+ * recalculate_root_clocks - recalculate and propagate all root clocks
+ *
+ * Recalculates all root clocks (clocks with no parent), which if the
+ * clock's .recalc is set correctly, should also propagate their rates.
+ * Called at init.
+ */
+void recalculate_root_clocks(void)
+{
+        struct clk *clkp;
+
+        list_for_each_entry(clkp, &clocks, node) {
+                if (unlikely(!clkp->parent) && likely((u32)clkp->recalc))
+                        clkp->recalc(clkp);
+        }
+}
+
 int clk_register(struct clk *clk)
 {
         if (clk == NULL || IS_ERR(clk))
@@ -358,6 +375,30 @@ void clk_allow_idle(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_allow_idle);
 
+void clk_enable_init_clocks(void)
+{
+        struct clk *clkp;
+
+        list_for_each_entry(clkp, &clocks, node) {
+                if (clkp->flags & ENABLE_ON_INIT)
+                        clk_enable(clkp);
+        }
+}
+EXPORT_SYMBOL(clk_enable_init_clocks);
+
+#ifdef CONFIG_CPU_FREQ
+void clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&clockfw_lock, flags);
+        if (arch_clock->clk_init_cpufreq_table)
+                arch_clock->clk_init_cpufreq_table(table);
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+}
+EXPORT_SYMBOL(clk_init_cpufreq_table);
+#endif
+
 /*-------------------------------------------------------------------------*/
 
 #ifdef CONFIG_OMAP_RESET_CLOCKS
@@ -396,3 +437,4 @@ int __init clk_init(struct clk_functions * custom_clocks)
 
         return 0;
 }
+
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 4f0f9c4e938e..bd1cef2c3c14 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -27,11 +27,16 @@
 #include <asm/setup.h>
 
 #include <asm/arch/board.h>
+#include <asm/arch/control.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/fpga.h>
 
 #include <asm/arch/clock.h>
 
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+# include "../mach-omap2/sdrc.h"
+#endif
+
 #define NO_LENGTH_CHECK 0xffffffff
 
 unsigned char omap_bootloader_tag[512];
@@ -171,8 +176,8 @@ console_initcall(omap_add_serial_console);
 
 #if defined(CONFIG_ARCH_OMAP16XX)
 #define TIMER_32K_SYNCHRONIZED          0xfffbc410
-#elif defined(CONFIG_ARCH_OMAP24XX)
-#define TIMER_32K_SYNCHRONIZED          (OMAP24XX_32KSYNCT_BASE + 0x10)
+#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#define TIMER_32K_SYNCHRONIZED          (OMAP2_32KSYNCT_BASE + 0x10)
 #endif
 
 #ifdef  TIMER_32K_SYNCHRONIZED
@@ -193,12 +198,35 @@ static struct clocksource clocksource_32k = {
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
+/*
+ * Rounds down to nearest nsec.
+ */
+unsigned long long omap_32k_ticks_to_nsecs(unsigned long ticks_32k)
+{
+        return cyc2ns(&clocksource_32k, ticks_32k);
+}
+
+/*
+ * Returns current time from boot in nsecs. It's OK for this to wrap
+ * around for now, as it's just a relative time stamp.
+ */
+unsigned long long sched_clock(void)
+{
+        return omap_32k_ticks_to_nsecs(omap_32k_read());
+}
+
 static int __init omap_init_clocksource_32k(void)
 {
         static char err[] __initdata = KERN_ERR
                         "%s: can't register clocksource!\n";
 
-        if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
+        if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
+                struct clk *sync_32k_ick;
+
+                sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
+                if (sync_32k_ick)
+                        clk_enable(sync_32k_ick);
+
                 clocksource_32k.mult = clocksource_hz2mult(32768,
                                             clocksource_32k.shift);
 
@@ -210,3 +238,33 @@ static int __init omap_init_clocksource_32k(void)
 arch_initcall(omap_init_clocksource_32k);
 
 #endif  /* TIMER_32K_SYNCHRONIZED */
+
+/* Global address base setup code */
+
+#if defined(CONFIG_ARCH_OMAP2420)
+void __init omap2_set_globals_242x(void)
+{
+        omap2_sdrc_base = OMAP2420_SDRC_BASE;
+        omap2_sms_base = OMAP2420_SMS_BASE;
+        omap_ctrl_base_set(OMAP2420_CTRL_BASE);
+}
+#endif
+
+#if defined(CONFIG_ARCH_OMAP2430)
+void __init omap2_set_globals_243x(void)
+{
+        omap2_sdrc_base = OMAP243X_SDRC_BASE;
+        omap2_sms_base = OMAP243X_SMS_BASE;
+        omap_ctrl_base_set(OMAP243X_CTRL_BASE);
+}
+#endif
+
+#if defined(CONFIG_ARCH_OMAP3430)
+void __init omap2_set_globals_343x(void)
+{
+        omap2_sdrc_base = OMAP343X_SDRC_BASE;
+        omap2_sms_base = OMAP343X_SMS_BASE;
+        omap_ctrl_base_set(OMAP343X_CTRL_BASE);
+}
+#endif
+
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 8c78e4e57b5c..1903a3491ee9 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -136,7 +136,6 @@ struct gpio_bank {
         u16 irq;
         u16 virtual_irq_start;
         int method;
-        u32 reserved_map;
 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
         u32 suspend_wakeup;
         u32 saved_wakeup;
@@ -149,7 +148,9 @@ struct gpio_bank {
         u32 saved_fallingdetect;
         u32 saved_risingdetect;
 #endif
+        u32 level_mask;
         spinlock_t lock;
+        struct gpio_chip chip;
 };
 
 #define METHOD_MPUIO            0
@@ -538,10 +539,9 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
                         bank->enabled_non_wakeup_gpios &= ~gpio_bit;
         }
 
-        /*
-         * FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only
-         * level triggering requested.
-         */
+        bank->level_mask =
+                __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
+                __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
 }
 #endif
 
@@ -652,6 +652,12 @@ static int gpio_irq_type(unsigned irq, unsigned type)
                 irq_desc[irq].status |= type;
         }
         spin_unlock_irqrestore(&bank->lock, flags);
+
+        if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
+                __set_irq_handler_unlocked(irq, handle_level_irq);
+        else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
+                __set_irq_handler_unlocked(irq, handle_edge_irq);
+
         return retval;
 }
 
@@ -903,19 +909,17 @@ int omap_request_gpio(int gpio)
 {
         struct gpio_bank *bank;
         unsigned long flags;
+        int status;
 
         if (check_gpio(gpio) < 0)
                 return -EINVAL;
 
+        status = gpio_request(gpio, NULL);
+        if (status < 0)
+                return status;
+
         bank = get_gpio_bank(gpio);
         spin_lock_irqsave(&bank->lock, flags);
-        if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
-                printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
-                dump_stack();
-                spin_unlock_irqrestore(&bank->lock, flags);
-                return -1;
-        }
-        bank->reserved_map |= (1 << get_gpio_index(gpio));
 
         /* Set trigger to none. You need to enable the desired trigger with
          * request_irq() or set_irq_type().
@@ -945,10 +949,11 @@ void omap_free_gpio(int gpio)
                 return;
         bank = get_gpio_bank(gpio);
         spin_lock_irqsave(&bank->lock, flags);
-        if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
+        if (unlikely(!gpiochip_is_requested(&bank->chip,
+                                get_gpio_index(gpio)))) {
+                spin_unlock_irqrestore(&bank->lock, flags);
                 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
                 dump_stack();
-                spin_unlock_irqrestore(&bank->lock, flags);
                 return;
         }
 #ifdef CONFIG_ARCH_OMAP16XX
@@ -965,9 +970,9 @@ void omap_free_gpio(int gpio)
                 __raw_writel(1 << get_gpio_index(gpio), reg);
         }
 #endif
-        bank->reserved_map &= ~(1 << get_gpio_index(gpio));
         _reset_gpio(bank, gpio);
         spin_unlock_irqrestore(&bank->lock, flags);
+        gpio_free(gpio);
 }
 
 /*
@@ -1022,12 +1027,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
                         isr &= 0x0000ffff;
 
                 if (cpu_class_is_omap2()) {
-                        level_mask =
-                                __raw_readl(bank->base +
-                                        OMAP24XX_GPIO_LEVELDETECT0) |
-                                __raw_readl(bank->base +
-                                        OMAP24XX_GPIO_LEVELDETECT1);
-                        level_mask &= enabled;
+                        level_mask = bank->level_mask & enabled;
                 }
 
                 /* clear edge sensitive interrupts before handler(s) are
@@ -1052,51 +1052,13 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
                 gpio_irq = bank->virtual_irq_start;
                 for (; isr != 0; isr >>= 1, gpio_irq++) {
                         struct irq_desc *d;
-                        int irq_mask;
+
                         if (!(isr & 1))
                                 continue;
                         d = irq_desc + gpio_irq;
-                        /* Don't run the handler if it's already running
-                         * or was disabled lazely.
-                         */
-                        if (unlikely((d->depth ||
-                                      (d->status & IRQ_INPROGRESS)))) {
-                                irq_mask = 1 <<
-                                        (gpio_irq - bank->virtual_irq_start);
-                                /* The unmasking will be done by
-                                 * enable_irq in case it is disabled or
-                                 * after returning from the handler if
-                                 * it's already running.
-                                 */
-                                _enable_gpio_irqbank(bank, irq_mask, 0);
-                                if (!d->depth) {
-                                        /* Level triggered interrupts
-                                         * won't ever be reentered
-                                         */
-                                        BUG_ON(level_mask & irq_mask);
-                                        d->status |= IRQ_PENDING;
-                                }
-                                continue;
-                        }
 
                         desc_handle_irq(gpio_irq, d);
-
-                        if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
-                                irq_mask = 1 <<
-                                        (gpio_irq - bank->virtual_irq_start);
-                                d->status &= ~IRQ_PENDING;
-                                _enable_gpio_irqbank(bank, irq_mask, 1);
-                                retrigger |= irq_mask;
-                        }
                 }
-
-                if (cpu_class_is_omap2()) {
-                        /* clear level sensitive interrupts after handler(s) */
-                        _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
-                        _clear_gpio_irqbank(bank, isr_saved & level_mask);
-                        _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
-                }
-
         }
         /* if bank has any level sensitive GPIO pin interrupt
         configured, we must unmask the bank interrupt only after
@@ -1135,6 +1097,14 @@ static void gpio_unmask_irq(unsigned int irq)
 {
         unsigned int gpio = irq - IH_GPIO_BASE;
         struct gpio_bank *bank = get_irq_chip_data(irq);
+        unsigned int irq_mask = 1 << get_gpio_index(gpio);
+
+        /* For level-triggered GPIOs, the clearing must be done after
+         * the HW source is cleared, thus after the handler has run */
+        if (bank->level_mask & irq_mask) {
+                _set_gpio_irqenable(bank, gpio, 0);
+                _clear_gpio_irqstatus(bank, gpio);
+        }
 
         _set_gpio_irqenable(bank, gpio, 1);
 }
@@ -1266,6 +1236,53 @@ static inline void mpuio_init(void) {}
 
 /*---------------------------------------------------------------------*/
 
+/* REVISIT these are stupid implementations!  replace by ones that
+ * don't switch on METHOD_* and which mostly avoid spinlocks
+ */
+
+static int gpio_input(struct gpio_chip *chip, unsigned offset)
+{
+        struct gpio_bank *bank;
+        unsigned long flags;
+
+        bank = container_of(chip, struct gpio_bank, chip);
+        spin_lock_irqsave(&bank->lock, flags);
+        _set_gpio_direction(bank, offset, 1);
+        spin_unlock_irqrestore(&bank->lock, flags);
+        return 0;
+}
+
+static int gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        return omap_get_gpio_datain(chip->base + offset);
+}
+
+static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
+{
+        struct gpio_bank *bank;
+        unsigned long flags;
+
+        bank = container_of(chip, struct gpio_bank, chip);
+        spin_lock_irqsave(&bank->lock, flags);
+        _set_gpio_dataout(bank, offset, value);
+        _set_gpio_direction(bank, offset, 0);
+        spin_unlock_irqrestore(&bank->lock, flags);
+        return 0;
+}
+
+static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+        struct gpio_bank *bank;
+        unsigned long flags;
+
+        bank = container_of(chip, struct gpio_bank, chip);
+        spin_lock_irqsave(&bank->lock, flags);
+        _set_gpio_dataout(bank, offset, value);
+        spin_unlock_irqrestore(&bank->lock, flags);
+}
+
+/*---------------------------------------------------------------------*/
+
 static int initialized;
 #if !defined(CONFIG_ARCH_OMAP3)
 static struct clk * gpio_ick;
@@ -1293,6 +1310,7 @@ static struct lock_class_key gpio_lock_class;
 static int __init _omap_gpio_init(void)
 {
         int i;
+        int gpio = 0;
         struct gpio_bank *bank;
 #if defined(CONFIG_ARCH_OMAP3)
         char clk_name[11];
@@ -1423,7 +1441,6 @@ static int __init _omap_gpio_init(void)
                 int j, gpio_count = 16;
 
                 bank = &gpio_bank[i];
-                bank->reserved_map = 0;
                 bank->base = IO_ADDRESS(bank->base);
                 spin_lock_init(&bank->lock);
                 if (bank_is_mpuio(bank))
@@ -1461,6 +1478,26 @@ static int __init _omap_gpio_init(void)
                         gpio_count = 32;
                 }
 #endif
+
+                /* REVISIT eventually switch from OMAP-specific gpio structs
+                 * over to the generic ones
+                 */
+                bank->chip.direction_input = gpio_input;
+                bank->chip.get = gpio_get;
+                bank->chip.direction_output = gpio_output;
+                bank->chip.set = gpio_set;
+                if (bank_is_mpuio(bank)) {
+                        bank->chip.label = "mpuio";
+                        bank->chip.base = OMAP_MPUIO(0);
+                } else {
+                        bank->chip.label = "gpio";
+                        bank->chip.base = gpio;
+                        gpio += gpio_count;
+                }
+                bank->chip.ngpio = gpio_count;
+
+                gpiochip_add(&bank->chip);
+
                 for (j = bank->virtual_irq_start;
                      j < bank->virtual_irq_start + gpio_count; j++) {
                         lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
@@ -1757,8 +1794,10 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
 
                 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
                         unsigned        irq, value, is_in, irqstat;
+                        const char      *label;
 
-                        if (!(bank->reserved_map & mask))
+                        label = gpiochip_is_requested(&bank->chip, j);
+                        if (!label)
                                 continue;
 
                         irq = bank->virtual_irq_start + j;
@@ -1766,13 +1805,16 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
                         is_in = gpio_is_input(bank, mask);
 
                         if (bank_is_mpuio(bank))
-                                seq_printf(s, "MPUIO %2d: ", j);
+                                seq_printf(s, "MPUIO %2d ", j);
                         else
-                                seq_printf(s, "GPIO %3d: ", gpio);
-                        seq_printf(s, "%s %s",
+                                seq_printf(s, "GPIO %3d ", gpio);
+                        seq_printf(s, "(%10s): %s %s",
+                                        label,
                                         is_in ? "in " : "out",
                                         value ? "hi"  : "lo");
 
+/* FIXME for at least omap2, show pullup/pulldown state */
+
                         irqstat = irq_desc[irq].status;
                         if (is_in && ((bank->suspend_wakeup & mask)
                                         || irqstat & IRQ_TYPE_SENSE_MASK)) {
@@ -1795,10 +1837,10 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
                                         trigger = "high";
                                         break;
                                 case IRQ_TYPE_NONE:
-                                        trigger = "(unspecified)";
+                                        trigger = "(?)";
                                         break;
                                 }
-                                seq_printf(s, ", irq-%d %s%s",
+                                seq_printf(s, ", irq-%d %-8s%s",
                                                 irq, trigger,
                                                 (bank->suspend_wakeup & mask)
                                                         ? " wakeup" : "");
diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c
index 75211f20ccb3..6f3f459731c8 100644
--- a/arch/arm/plat-omap/mux.c
+++ b/arch/arm/plat-omap/mux.c
@@ -3,9 +3,9 @@
  *
  * Utility to set the Omap MUX and PULL_DWN registers from a table in mux.h
  *
- * Copyright (C) 2003 - 2005 Nokia Corporation
+ * Copyright (C) 2003 - 2008 Nokia Corporation
  *
- * Written by Tony Lindgren <tony.lindgren@nokia.com>
+ * Written by Tony Lindgren
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -32,21 +32,17 @@
 
 #ifdef CONFIG_OMAP_MUX
 
-#define OMAP24XX_L4_BASE        0x48000000
-#define OMAP24XX_PULL_ENA       (1 << 3)
-#define OMAP24XX_PULL_UP        (1 << 4)
+static struct omap_mux_cfg *mux_cfg;
 
-static struct pin_config * pin_table;
-static unsigned long pin_table_sz;
-
-extern struct pin_config * omap730_pins;
-extern struct pin_config * omap1xxx_pins;
-extern struct pin_config * omap24xx_pins;
-
-int __init omap_mux_register(struct pin_config * pins, unsigned long size)
+int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg)
 {
-        pin_table = pins;
-        pin_table_sz = size;
+        if (!arch_mux_cfg || !arch_mux_cfg->pins || arch_mux_cfg->size == 0
+                        || !arch_mux_cfg->cfg_reg) {
+                printk(KERN_ERR "Invalid pin table\n");
+                return -EINVAL;
+        }
+
+        mux_cfg = arch_mux_cfg;
 
         return 0;
 }
@@ -56,152 +52,26 @@ int __init omap_mux_register(struct pin_config * pins, unsigned long size)
  */
 int __init_or_module omap_cfg_reg(const unsigned long index)
 {
-        static DEFINE_SPINLOCK(mux_spin_lock);
-
-        unsigned long flags;
-        struct pin_config *cfg;
-        unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
-                pull_orig = 0, pull = 0;
-        unsigned int mask, warn = 0;
+        struct pin_config *reg;
 
-        if (!pin_table)
-                BUG();
+        if (mux_cfg == NULL) {
+                printk(KERN_ERR "Pin mux table not initialized\n");
+                return -ENODEV;
+        }
 
-        if (index >= pin_table_sz) {
+        if (index >= mux_cfg->size) {
                 printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
-                       index, pin_table_sz);
+                       index, mux_cfg->size);
                 dump_stack();
                 return -ENODEV;
         }
 
-        cfg = (struct pin_config *)&pin_table[index];
-        if (cpu_is_omap24xx()) {
-                u8 reg = 0;
-
-                reg |= cfg->mask & 0x7;
-                if (cfg->pull_val)
-                        reg |= OMAP24XX_PULL_ENA;
-                if(cfg->pu_pd_val)
-                        reg |= OMAP24XX_PULL_UP;
-#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
-                {
-                        u8 orig = omap_readb(OMAP24XX_L4_BASE + cfg->mux_reg);
-                        u8 debug = 0;
-
-#ifdef  CONFIG_OMAP_MUX_DEBUG
-                        debug = cfg->debug;
-#endif
-                        warn = (orig != reg);
-                        if (debug || warn)
-                                printk("MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n",
-                                                cfg->name,
-                                                OMAP24XX_L4_BASE + cfg->mux_reg,
-                                                orig, reg);
-                }
-#endif
-                omap_writeb(reg, OMAP24XX_L4_BASE + cfg->mux_reg);
+        reg = (struct pin_config *)&mux_cfg->pins[index];
 
-                return 0;
-        }
-
-        /* Check the mux register in question */
-        if (cfg->mux_reg) {
-                unsigned        tmp1, tmp2;
-
-                spin_lock_irqsave(&mux_spin_lock, flags);
-                reg_orig = omap_readl(cfg->mux_reg);
-
-                /* The mux registers always seem to be 3 bits long */
-                mask = (0x7 << cfg->mask_offset);
-                tmp1 = reg_orig & mask;
-                reg = reg_orig & ~mask;
-
-                tmp2 = (cfg->mask << cfg->mask_offset);
-                reg |= tmp2;
-
-                if (tmp1 != tmp2)
-                        warn = 1;
-
-                omap_writel(reg, cfg->mux_reg);
-                spin_unlock_irqrestore(&mux_spin_lock, flags);
-        }
-
-        /* Check for pull up or pull down selection on 1610 */
-        if (!cpu_is_omap15xx()) {
-                if (cfg->pu_pd_reg && cfg->pull_val) {
-                        spin_lock_irqsave(&mux_spin_lock, flags);
-                        pu_pd_orig = omap_readl(cfg->pu_pd_reg);
-                        mask = 1 << cfg->pull_bit;
-
-                        if (cfg->pu_pd_val) {
-                                if (!(pu_pd_orig & mask))
-                                        warn = 1;
-                                /* Use pull up */
-                                pu_pd = pu_pd_orig | mask;
-                        } else {
-                                if (pu_pd_orig & mask)
-                                        warn = 1;
-                                /* Use pull down */
-                                pu_pd = pu_pd_orig & ~mask;
-                        }
-                        omap_writel(pu_pd, cfg->pu_pd_reg);
-                        spin_unlock_irqrestore(&mux_spin_lock, flags);
-                }
-        }
-
-        /* Check for an associated pull down register */
-        if (cfg->pull_reg) {
-                spin_lock_irqsave(&mux_spin_lock, flags);
-                pull_orig = omap_readl(cfg->pull_reg);
-                mask = 1 << cfg->pull_bit;
-
-                if (cfg->pull_val) {
-                        if (pull_orig & mask)
-                                warn = 1;
-                        /* Low bit = pull enabled */
-                        pull = pull_orig & ~mask;
-                } else {
-                        if (!(pull_orig & mask))
-                                warn = 1;
-                        /* High bit = pull disabled */
-                        pull = pull_orig | mask;
-                }
-
-                omap_writel(pull, cfg->pull_reg);
-                spin_unlock_irqrestore(&mux_spin_lock, flags);
-        }
-
-        if (warn) {
-#ifdef CONFIG_OMAP_MUX_WARNINGS
-                printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
-#endif
-        }
-
-#ifdef CONFIG_OMAP_MUX_DEBUG
-        if (cfg->debug || warn) {
-                printk("MUX: Setting register %s\n", cfg->name);
-                printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
-                       cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
-
-                if (!cpu_is_omap15xx()) {
-                        if (cfg->pu_pd_reg && cfg->pull_val) {
-                                printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
-                                       cfg->pu_pd_name, cfg->pu_pd_reg,
-                                       pu_pd_orig, pu_pd);
-                        }
-                }
-
-                if (cfg->pull_reg)
-                        printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
-                               cfg->pull_name, cfg->pull_reg, pull_orig, pull);
-        }
-#endif
+        if (!mux_cfg->cfg_reg)
+                return -ENODEV;
 
-#ifdef CONFIG_OMAP_MUX_ERRORS
-        return warn ? -ETXTBSY : 0;
-#else
-        return 0;
-#endif
+        return mux_cfg->cfg_reg(reg);
 }
 EXPORT_SYMBOL(omap_cfg_reg);
 #else
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index a5aedf964b88..a619475c4b76 100644
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -33,6 +33,7 @@
 #include <asm/system.h>
 #include <asm/hardware.h>
 
+#include <asm/arch/control.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/usb.h>
 #include <asm/arch/board.h>
@@ -76,7 +77,7 @@
 
 /*-------------------------------------------------------------------------*/
 
-#ifdef  CONFIG_ARCH_OMAP_OTG
+#if     defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_USB_MUSB_OTG)
 
 static struct otg_transceiver *xceiv;
 
@@ -110,12 +111,48 @@ EXPORT_SYMBOL(otg_set_transceiver);
 
 #if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP15XX)
 
+static void omap2_usb_devconf_clear(u8 port, u32 mask)
+{
+        u32 r;
+
+        r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+        r &= ~USBTXWRMODEI(port, mask);
+        omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
+}
+
+static void omap2_usb_devconf_set(u8 port, u32 mask)
+{
+        u32 r;
+
+        r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+        r |= USBTXWRMODEI(port, mask);
+        omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
+}
+
+static void omap2_usb2_disable_5pinbitll(void)
+{
+        u32 r;
+
+        r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+        r &= ~(USBTXWRMODEI(2, USB_BIDIR_TLL) | USBT2TLL5PI);
+        omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
+}
+
+static void omap2_usb2_enable_5pinunitll(void)
+{
+        u32 r;
+
+        r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+        r |= USBTXWRMODEI(2, USB_UNIDIR_TLL) | USBT2TLL5PI;
+        omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
+}
+
 static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
 {
         u32     syscon1 = 0;
 
         if (cpu_is_omap24xx())
-                CONTROL_DEVCONF_REG &= ~USBT0WRMODEI(USB_BIDIR_TLL);
+                omap2_usb_devconf_clear(0, USB_BIDIR_TLL);
 
         if (nwires == 0) {
                 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
@@ -187,19 +224,19 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
         case 3:
                 syscon1 = 2;
                 if (cpu_is_omap24xx())
-                        CONTROL_DEVCONF_REG |= USBT0WRMODEI(USB_BIDIR);
+                        omap2_usb_devconf_set(0, USB_BIDIR);
                 break;
         case 4:
                 syscon1 = 1;
                 if (cpu_is_omap24xx())
-                        CONTROL_DEVCONF_REG |= USBT0WRMODEI(USB_BIDIR);
+                        omap2_usb_devconf_set(0, USB_BIDIR);
                 break;
         case 6:
                 syscon1 = 3;
                 if (cpu_is_omap24xx()) {
                         omap_cfg_reg(J19_24XX_USB0_VP);
                         omap_cfg_reg(K20_24XX_USB0_VM);
-                        CONTROL_DEVCONF_REG |= USBT0WRMODEI(USB_UNIDIR);
+                        omap2_usb_devconf_set(0, USB_UNIDIR);
                 } else {
                         omap_cfg_reg(AA9_USB0_VP);
                         omap_cfg_reg(R9_USB0_VM);
@@ -220,7 +257,7 @@ static u32 __init omap_usb1_init(unsigned nwires)
         if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6)
                 USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB1_UNI_R;
         if (cpu_is_omap24xx())
-                CONTROL_DEVCONF_REG &= ~USBT1WRMODEI(USB_BIDIR_TLL);
+                omap2_usb_devconf_clear(1, USB_BIDIR_TLL);
 
         if (nwires == 0)
                 return 0;
@@ -261,17 +298,17 @@ static u32 __init omap_usb1_init(unsigned nwires)
                  * this TLL link is not using DP/DM
                  */
                 syscon1 = 1;
-                CONTROL_DEVCONF_REG |= USBT1WRMODEI(USB_BIDIR_TLL);
+                omap2_usb_devconf_set(1, USB_BIDIR_TLL);
                 break;
         case 3:
                 syscon1 = 2;
                 if (cpu_is_omap24xx())
-                        CONTROL_DEVCONF_REG |= USBT1WRMODEI(USB_BIDIR);
+                        omap2_usb_devconf_set(1, USB_BIDIR);
                 break;
         case 4:
                 syscon1 = 1;
                 if (cpu_is_omap24xx())
-                        CONTROL_DEVCONF_REG |= USBT1WRMODEI(USB_BIDIR);
+                        omap2_usb_devconf_set(1, USB_BIDIR);
                 break;
         case 6:
                 if (cpu_is_omap24xx())
@@ -295,8 +332,7 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
         u32     syscon1 = 0;
 
         if (cpu_is_omap24xx()) {
-                CONTROL_DEVCONF_REG &= ~(USBT2WRMODEI(USB_BIDIR_TLL)
-                                        | USBT2TLL5PI);
+                omap2_usb2_disable_5pinbitll();
                 alt_pingroup = 0;
         }
 
@@ -343,17 +379,17 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
                  * this TLL link is not using DP/DM
                  */
                 syscon1 = 1;
-                CONTROL_DEVCONF_REG |= USBT2WRMODEI(USB_BIDIR_TLL);
+                omap2_usb_devconf_set(2, USB_BIDIR_TLL);
                 break;
         case 3:
                 syscon1 = 2;
                 if (cpu_is_omap24xx())
-                        CONTROL_DEVCONF_REG |= USBT2WRMODEI(USB_BIDIR);
+                        omap2_usb_devconf_set(2, USB_BIDIR);
                 break;
         case 4:
                 syscon1 = 1;
                 if (cpu_is_omap24xx())
-                        CONTROL_DEVCONF_REG |= USBT2WRMODEI(USB_BIDIR);
+                        omap2_usb_devconf_set(2, USB_BIDIR);
                 break;
         case 5:
                 if (!cpu_is_omap24xx())
@@ -364,8 +400,7 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
                  * set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED}
                  */
                 syscon1 = 3;
-                CONTROL_DEVCONF_REG |= USBT2WRMODEI(USB_UNIDIR_TLL)
-                                        | USBT2TLL5PI;
+                omap2_usb2_enable_5pinunitll();
                 break;
         case 6:
                 if (cpu_is_omap24xx())
diff --git a/arch/avr32/kernel/setup.c b/arch/avr32/kernel/setup.c
index e66a07a928cd..2687b730e2d0 100644
--- a/arch/avr32/kernel/setup.c
+++ b/arch/avr32/kernel/setup.c
@@ -163,6 +163,7 @@ add_reserved_region(resource_size_t start, resource_size_t end,
         new->start = start;
         new->end = end;
         new->name = name;
+        new->sibling = next;
         new->flags = IORESOURCE_MEM;
 
         *pprev = new;
diff --git a/arch/avr32/kernel/traps.c b/arch/avr32/kernel/traps.c
index cf6f686d9b0b..b835c4c01368 100644
--- a/arch/avr32/kernel/traps.c
+++ b/arch/avr32/kernel/traps.c
@@ -178,6 +178,7 @@ static int do_cop_absent(u32 insn)
         return 0;
 }
 
+#ifdef CONFIG_BUG
 int is_valid_bugaddr(unsigned long pc)
 {
         unsigned short opcode;
@@ -189,6 +190,7 @@ int is_valid_bugaddr(unsigned long pc)
 
         return opcode == AVR32_BUG_OPCODE;
 }
+#endif
 
 asmlinkage void do_illegal_opcode(unsigned long ecr, struct pt_regs *regs)
 {
@@ -197,6 +199,7 @@ asmlinkage void do_illegal_opcode(unsigned long ecr, struct pt_regs *regs)
         void __user *pc;
         long code;
 
+#ifdef CONFIG_BUG
         if (!user_mode(regs) && (ecr == ECR_ILLEGAL_OPCODE)) {
                 enum bug_trap_type type;
 
@@ -211,6 +214,7 @@ asmlinkage void do_illegal_opcode(unsigned long ecr, struct pt_regs *regs)
                         die("Kernel BUG", regs, SIGKILL);
                 }
         }
+#endif
 
         local_irq_enable();
 
diff --git a/arch/frv/kernel/entry-table.S b/arch/frv/kernel/entry-table.S
index d3b9253d862a..bf35f33e48c9 100644
--- a/arch/frv/kernel/entry-table.S
+++ b/arch/frv/kernel/entry-table.S
@@ -316,8 +316,14 @@ __trap_fixup_kernel_data_tlb_miss:
         .section        .trap.vector
         .org            TBR_TT_TRAP0 >> 2
         .long           system_call
-        .rept           126
+        .rept           119
         .long           __entry_unsupported_trap
         .endr
+
+        # userspace atomic op emulation, traps 120-126
+        .rept           7
+        .long           __entry_atomic_op
+        .endr
+        
         .org            TBR_TT_BREAK >> 2
         .long           __entry_debug_exception
diff --git a/arch/frv/kernel/entry.S b/arch/frv/kernel/entry.S
index f36d7f4a7c25..b8a4b94779b1 100644
--- a/arch/frv/kernel/entry.S
+++ b/arch/frv/kernel/entry.S
@@ -656,6 +656,26 @@ __entry_debug_exception:
 
 ###############################################################################
 #
+# handle atomic operation emulation for userspace
+#
+###############################################################################
+        .globl          __entry_atomic_op
+__entry_atomic_op:
+        LEDS            0x6012
+        sethi.p         %hi(atomic_operation),gr5
+        setlo           %lo(atomic_operation),gr5
+        movsg           esfr1,gr8
+        movsg           epcr0,gr9
+        movsg           esr0,gr10
+
+        # now that we've accessed the exception regs, we can enable exceptions
+        movsg           psr,gr4
+        ori             gr4,#PSR_ET,gr4
+        movgs           gr4,psr
+        jmpl            @(gr5,gr0)      ; call atomic_operation(esfr1,epcr0,esr0)
+
+###############################################################################
+#
 # handle media exception
 #
 ###############################################################################
diff --git a/arch/frv/kernel/head.inc b/arch/frv/kernel/head.inc
index d424cd2eb213..bff66628b99a 100644
--- a/arch/frv/kernel/head.inc
+++ b/arch/frv/kernel/head.inc
@@ -46,5 +46,5 @@
 #ifdef CONFIG_MMU
 __sdram_base = 0x00000000               /* base address to which SDRAM relocated */
 #else
-__sdram_base = 0xc0000000               /* base address to which SDRAM relocated */
+__sdram_base = __page_offset            /* base address to which SDRAM relocated */
 #endif
diff --git a/arch/frv/kernel/switch_to.S b/arch/frv/kernel/switch_to.S
index b5275fa9cd0d..b06668670fcc 100644
--- a/arch/frv/kernel/switch_to.S
+++ b/arch/frv/kernel/switch_to.S
@@ -102,13 +102,6 @@ __switch_to:
         movgs           gr14,lr
         bar
 
-        srli            gr15,#28,gr5
-        subicc          gr5,#0xc,gr0,icc0
-        beq             icc0,#0,111f
-        break
-        nop
-111:
-
         # jump to __switch_back or ret_from_fork as appropriate
         # - move prev to GR8
         movgs           gr4,psr
diff --git a/arch/frv/kernel/traps.c b/arch/frv/kernel/traps.c
index 2e6098c85578..2f7e66877f3b 100644
--- a/arch/frv/kernel/traps.c
+++ b/arch/frv/kernel/traps.c
@@ -102,6 +102,233 @@ asmlinkage void illegal_instruction(unsigned long esfr1, unsigned long epcr0, un
 
 /*****************************************************************************/
 /*
+ * handle atomic operations with errors
+ * - arguments in gr8, gr9, gr10
+ * - original memory value placed in gr5
+ * - replacement memory value placed in gr9
+ */
+asmlinkage void atomic_operation(unsigned long esfr1, unsigned long epcr0,
+                                 unsigned long esr0)
+{
+        static DEFINE_SPINLOCK(atomic_op_lock);
+        unsigned long x, y, z, *p;
+        mm_segment_t oldfs;
+        siginfo_t info;
+        int ret;
+
+        y = 0;
+        z = 0;
+
+        oldfs = get_fs();
+        if (!user_mode(__frame))
+                set_fs(KERNEL_DS);
+
+        switch (__frame->tbr & TBR_TT) {
+                /* TIRA gr0,#120
+                 * u32 __atomic_user_cmpxchg32(u32 *ptr, u32 test, u32 new)
+                 */
+        case TBR_TT_ATOMIC_CMPXCHG32:
+                p = (unsigned long *) __frame->gr8;
+                x = __frame->gr9;
+                y = __frame->gr10;
+
+                for (;;) {
+                        ret = get_user(z, p);
+                        if (ret < 0)
+                                goto error;
+
+                        if (z != x)
+                                goto done;
+
+                        spin_lock_irq(&atomic_op_lock);
+
+                        if (__get_user(z, p) == 0) {
+                                if (z != x)
+                                        goto done2;
+
+                                if (__put_user(y, p) == 0)
+                                        goto done2;
+                                goto error2;
+                        }
+
+                        spin_unlock_irq(&atomic_op_lock);
+                }
+
+                /* TIRA gr0,#121
+                 * u32 __atomic_kernel_xchg32(void *v, u32 new)
+                 */
+        case TBR_TT_ATOMIC_XCHG32:
+                p = (unsigned long *) __frame->gr8;
+                y = __frame->gr9;
+
+                for (;;) {
+                        ret = get_user(z, p);
+                        if (ret < 0)
+                                goto error;
+
+                        spin_lock_irq(&atomic_op_lock);
+
+                        if (__get_user(z, p) == 0) {
+                                if (__put_user(y, p) == 0)
+                                        goto done2;
+                                goto error2;
+                        }
+
+                        spin_unlock_irq(&atomic_op_lock);
+                }
+
+                /* TIRA gr0,#122
+                 * ulong __atomic_kernel_XOR_return(ulong i, ulong *v)
+                 */
+        case TBR_TT_ATOMIC_XOR:
+                p = (unsigned long *) __frame->gr8;
+                x = __frame->gr9;
+
+                for (;;) {
+                        ret = get_user(z, p);
+                        if (ret < 0)
+                                goto error;
+
+                        spin_lock_irq(&atomic_op_lock);
+
+                        if (__get_user(z, p) == 0) {
+                                y = x ^ z;
+                                if (__put_user(y, p) == 0)
+                                        goto done2;
+                                goto error2;
+                        }
+
+                        spin_unlock_irq(&atomic_op_lock);
+                }
+
+                /* TIRA gr0,#123
+                 * ulong __atomic_kernel_OR_return(ulong i, ulong *v)
+                 */
+        case TBR_TT_ATOMIC_OR:
+                p = (unsigned long *) __frame->gr8;
+                x = __frame->gr9;
+
+                for (;;) {
+                        ret = get_user(z, p);
+                        if (ret < 0)
+                                goto error;
+
+                        spin_lock_irq(&atomic_op_lock);
+
+                        if (__get_user(z, p) == 0) {
+                                y = x ^ z;
+                                if (__put_user(y, p) == 0)
+                                        goto done2;
+                                goto error2;
+                        }
+
+                        spin_unlock_irq(&atomic_op_lock);
+                }
+
+                /* TIRA gr0,#124
+                 * ulong __atomic_kernel_AND_return(ulong i, ulong *v)
+                 */
+        case TBR_TT_ATOMIC_AND:
+                p = (unsigned long *) __frame->gr8;
+                x = __frame->gr9;
+
+                for (;;) {
+                        ret = get_user(z, p);
+                        if (ret < 0)
+                                goto error;
+
+                        spin_lock_irq(&atomic_op_lock);
+
+                        if (__get_user(z, p) == 0) {
+                                y = x & z;
+                                if (__put_user(y, p) == 0)
+                                        goto done2;
+                                goto error2;
+                        }
+
+                        spin_unlock_irq(&atomic_op_lock);
+                }
+
+                /* TIRA gr0,#125
+                 * int __atomic_user_sub_return(atomic_t *v, int i)
+                 */
+        case TBR_TT_ATOMIC_SUB:
+                p = (unsigned long *) __frame->gr8;
+                x = __frame->gr9;
+
+                for (;;) {
+                        ret = get_user(z, p);
+                        if (ret < 0)
+                                goto error;
+
+                        spin_lock_irq(&atomic_op_lock);
+
+                        if (__get_user(z, p) == 0) {
+                                y = z - x;
+                                if (__put_user(y, p) == 0)
+                                        goto done2;
+                                goto error2;
+                        }
+
+                        spin_unlock_irq(&atomic_op_lock);
+                }
+
+                /* TIRA gr0,#126
+                 * int __atomic_user_add_return(atomic_t *v, int i)
+                 */
+        case TBR_TT_ATOMIC_ADD:
+                p = (unsigned long *) __frame->gr8;
+                x = __frame->gr9;
+
+                for (;;) {
+                        ret = get_user(z, p);
+                        if (ret < 0)
+                                goto error;
+
+                        spin_lock_irq(&atomic_op_lock);
+
+                        if (__get_user(z, p) == 0) {
+                                y = z + x;
+                                if (__put_user(y, p) == 0)
+                                        goto done2;
+                                goto error2;
+                        }
+
+                        spin_unlock_irq(&atomic_op_lock);
+                }
+
+        default:
+                BUG();
+        }
+
+done2:
+        spin_unlock_irq(&atomic_op_lock);
+done:
+        if (!user_mode(__frame))
+                set_fs(oldfs);
+        __frame->gr5 = z;
+        __frame->gr9 = y;
+        return;
+
+error2:
+        spin_unlock_irq(&atomic_op_lock);
+error:
+        if (!user_mode(__frame))
+                set_fs(oldfs);
+        __frame->pc -= 4;
+
+        die_if_kernel("-- Atomic Op Error --\n");
+
+        info.si_signo   = SIGSEGV;
+        info.si_code    = SEGV_ACCERR;
+        info.si_errno   = 0;
+        info.si_addr    = (void *) __frame->pc;
+
+        force_sig_info(info.si_signo, &info, current);
+}
+
+/*****************************************************************************/
+/*
  *
  */
 asmlinkage void media_exception(unsigned long msr0, unsigned long msr1)
diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile
index 2cba605cb59d..b15173f28a23 100644
--- a/arch/m68k/Makefile
+++ b/arch/m68k/Makefile
@@ -13,6 +13,8 @@
 # Copyright (C) 1994 by Hamish Macdonald
 #
 
+KBUILD_DEFCONFIG := amiga_defconfig
+
 # override top level makefile
 AS += -m68020
 LDFLAGS := -m m68kelf
diff --git a/arch/m68k/configs/amiga_defconfig b/arch/m68k/configs/amiga_defconfig
index 5649fbae430e..e41958371367 100644
--- a/arch/m68k/configs/amiga_defconfig
+++ b/arch/m68k/configs/amiga_defconfig
@@ -1,63 +1,111 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc6-m68k
-# Tue Jun  7 20:34:23 2005
+# Linux kernel version: 2.6.25-rc8
+# Wed Apr  2 20:46:06 2008
 #
 CONFIG_M68K=y
 CONFIG_MMU=y
-CONFIG_UID16=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_TIME_LOW_RES=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_NO_IOPORT=y
+# CONFIG_NO_DMA is not set
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_HZ=100
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
-CONFIG_CLEAN_COMPILE=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION="-amiga"
+CONFIG_LOCALVERSION_AUTO=y
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_BSD_PROCESS_ACCT=y
 # CONFIG_BSD_PROCESS_ACCT_V3 is not set
-CONFIG_SYSCTL=y
-CONFIG_AUDIT=y
-CONFIG_HOTPLUG=y
-CONFIG_KOBJECT_UEVENT=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_COMPAT_BRK is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+# CONFIG_HAVE_OPROFILE is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_OBSOLETE_MODPARM=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+CONFIG_BLK_DEV_BSG=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
 
 #
 # Platform dependent setup
@@ -80,10 +128,24 @@ CONFIG_M68030=y
 CONFIG_M68040=y
 CONFIG_M68060=y
 CONFIG_MMU_MOTOROLA=y
-CONFIG_M68KFPU_EMU=y
-CONFIG_M68KFPU_EMU_EXTRAPREC=y
-# CONFIG_M68KFPU_EMU_ONLY is not set
+# CONFIG_M68KFPU_EMU is not set
 # CONFIG_ADVANCED is not set
+CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
+CONFIG_NODES_SHIFT=3
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_FLATMEM_MANUAL is not set
+CONFIG_DISCONTIGMEM_MANUAL=y
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_DISCONTIGMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_NEED_MULTIPLE_NODES=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
 
 #
 # General setup
@@ -97,47 +159,288 @@ CONFIG_AMIGA_PCMCIA=y
 CONFIG_PROC_HARDWARE=y
 CONFIG_ISA=y
 CONFIG_GENERIC_ISA_DMA=y
+CONFIG_ZONE_DMA=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 CONFIG_ZORRO_NAMES=y
 
 #
-# Device Drivers
+# Networking
 #
+CONFIG_NET=y
 
 #
-# Generic Driver Options
+# Networking options
 #
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
-# CONFIG_DEBUG_DRIVER is not set
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+CONFIG_XFRM_MIGRATE=y
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_NET_KEY=y
+CONFIG_NET_KEY_MIGRATE=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE=m
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_INET_LRO=m
+CONFIG_INET_DIAG=m
+CONFIG_INET_TCP_DIAG=m
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IP_VS is not set
+CONFIG_IPV6=m
+CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+# CONFIG_IPV6_MIP6 is not set
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_TUNNEL=m
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+CONFIG_NF_CT_PROTO_GRE=m
+CONFIG_NF_CT_PROTO_SCTP=m
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+# CONFIG_NF_CT_NETLINK is not set
+CONFIG_NETFILTER_XTABLES=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_RATEEST=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
 
 #
-# Memory Technology Devices (MTD)
+# IP: Netfilter Configuration
 #
-# CONFIG_MTD is not set
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_RECENT=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_MATCH_ADDRTYPE=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_NF_NAT_SNMP_BASIC=m
+CONFIG_NF_NAT_PROTO_GRE=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+CONFIG_NF_NAT_TFTP=m
+CONFIG_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+CONFIG_NF_NAT_SIP=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV6=m
+CONFIG_IP6_NF_QUEUE=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_HL=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_TARGET_HL=m
+CONFIG_IP6_NF_RAW=m
+CONFIG_IP_DCCP=m
+CONFIG_INET_DCCP_DIAG=m
+CONFIG_IP_DCCP_ACKVEC=y
+
+#
+# DCCP CCIDs Configuration (EXPERIMENTAL)
+#
+CONFIG_IP_DCCP_CCID2=m
+# CONFIG_IP_DCCP_CCID2_DEBUG is not set
+CONFIG_IP_DCCP_CCID3=m
+# CONFIG_IP_DCCP_CCID3_DEBUG is not set
+CONFIG_IP_DCCP_CCID3_RTO=100
+CONFIG_IP_DCCP_TFRC_LIB=m
+CONFIG_IP_SCTP=m
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+CONFIG_ATALK=m
+# CONFIG_DEV_APPLETALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+CONFIG_NET_CLS_ROUTE=y
 
 #
-# Parallel port support
+# Network testing
 #
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=m
+CONFIG_IEEE80211_CRYPT_CCMP=m
+CONFIG_IEEE80211_CRYPT_TKIP=m
+CONFIG_IEEE80211_SOFTMAC=m
+# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=m
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=m
+# CONFIG_MTD is not set
 CONFIG_PARPORT=m
 # CONFIG_PARPORT_PC is not set
-CONFIG_PARPORT_NOT_PC=y
 CONFIG_PARPORT_AMIGA=m
 CONFIG_PARPORT_MFC3=m
 # CONFIG_PARPORT_GSC is not set
+# CONFIG_PARPORT_AX88796 is not set
 CONFIG_PARPORT_1284=y
-
-#
-# Plug and Play support
-#
+CONFIG_PARPORT_NOT_PC=y
 # CONFIG_PNP is not set
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
 CONFIG_AMIGA_FLOPPY=y
 CONFIG_AMIGA_Z2RAM=y
-# CONFIG_PARIDE is not set
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_CRYPTOLOOP=m
@@ -145,56 +448,66 @@ CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_BLK_DEV_XIP is not set
 CONFIG_CDROM_PKTCDVD=m
 CONFIG_CDROM_PKTCDVD_BUFFERS=8
 # CONFIG_CDROM_PKTCDVD_WCACHE is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
 CONFIG_ATA_OVER_ETH=m
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
 CONFIG_IDE=y
 CONFIG_BLK_DEV_IDE=y
 
 #
-# Please see Documentation/ide.txt for help/info on IDE drives
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
 #
 # CONFIG_BLK_DEV_IDE_SATA is not set
 CONFIG_BLK_DEV_IDEDISK=y
 # CONFIG_IDEDISK_MULTI_MODE is not set
 CONFIG_BLK_DEV_IDECD=y
-CONFIG_BLK_DEV_IDETAPE=m
+CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
+# CONFIG_BLK_DEV_IDETAPE is not set
 CONFIG_BLK_DEV_IDEFLOPPY=m
 # CONFIG_BLK_DEV_IDESCSI is not set
 # CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
 
 #
 # IDE chipset support/bugfixes
 #
-CONFIG_IDE_GENERIC=y
-# CONFIG_IDE_ARM is not set
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
 CONFIG_BLK_DEV_GAYLE=y
 CONFIG_BLK_DEV_IDEDOUBLER=y
 CONFIG_BLK_DEV_BUDDHA=y
-# CONFIG_IDE_CHIPSETS is not set
+
+#
+# Other IDE chipsets support
+#
+
+#
+# Note: most of these also require special kernel boot parameters
+#
+# CONFIG_BLK_DEV_4DRIVES is not set
+# CONFIG_BLK_DEV_ALI14XX is not set
+# CONFIG_BLK_DEV_DTC2278 is not set
+# CONFIG_BLK_DEV_HT6560B is not set
+# CONFIG_BLK_DEV_QD65XX is not set
+# CONFIG_BLK_DEV_UMC8672 is not set
 # CONFIG_BLK_DEV_IDEDMA is not set
-# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_IDE_ARCH_OBSOLETE_INIT is not set
 # CONFIG_BLK_DEV_HD is not set
 
 #
 # SCSI device support
 #
+CONFIG_RAID_ATTRS=m
 CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=m
+# CONFIG_SCSI_NETLINK is not set
 CONFIG_SCSI_PROC_FS=y
 
 #
@@ -206,6 +519,7 @@ CONFIG_CHR_DEV_OSST=m
 CONFIG_BLK_DEV_SR=y
 CONFIG_BLK_DEV_SR_VENDOR=y
 CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
 
 #
 # Some SCSI devices (e.g. CD jukebox) support multiple LUNs
@@ -213,30 +527,34 @@ CONFIG_CHR_DEV_SG=m
 # CONFIG_SCSI_MULTI_LUN is not set
 CONFIG_SCSI_CONSTANTS=y
 # CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
 
 #
-# SCSI Transport Attributes
+# SCSI Transports
 #
-# CONFIG_SCSI_SPI_ATTRS is not set
+CONFIG_SCSI_SPI_ATTRS=y
 # CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-
-#
-# SCSI low-level drivers
-#
+CONFIG_SCSI_ISCSI_ATTRS=m
+CONFIG_SCSI_SAS_ATTRS=m
+CONFIG_SCSI_SAS_LIBSAS=m
+CONFIG_SCSI_SAS_HOST_SMP=y
+# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
+CONFIG_SCSI_SRP_ATTRS=m
+CONFIG_SCSI_SRP_TGT_ATTRS=y
+CONFIG_SCSI_LOWLEVEL=y
+CONFIG_ISCSI_TCP=m
 # CONFIG_SCSI_AHA152X is not set
 # CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_ADVANSYS is not set
 # CONFIG_SCSI_IN2000 is not set
-# CONFIG_SCSI_SATA is not set
 # CONFIG_SCSI_DTC3280 is not set
 # CONFIG_SCSI_FUTURE_DOMAIN is not set
 # CONFIG_SCSI_GENERIC_NCR5380 is not set
 # CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
-# CONFIG_SCSI_PPA is not set
-# CONFIG_SCSI_IMM is not set
 # CONFIG_SCSI_NCR53C406A is not set
+CONFIG_53C700_BE_BUS=y
 # CONFIG_SCSI_PAS16 is not set
-# CONFIG_SCSI_PSI240I is not set
 # CONFIG_SCSI_QLOGIC_FAS is not set
 # CONFIG_SCSI_SYM53C416 is not set
 # CONFIG_SCSI_T128 is not set
@@ -244,243 +562,42 @@ CONFIG_SCSI_CONSTANTS=y
 CONFIG_A3000_SCSI=y
 CONFIG_A2091_SCSI=y
 CONFIG_GVP11_SCSI=y
-CONFIG_CYBERSTORM_SCSI=y
-CONFIG_CYBERSTORMII_SCSI=y
-CONFIG_BLZ2060_SCSI=y
-CONFIG_BLZ1230_SCSI=y
-CONFIG_FASTLANE_SCSI=y
-CONFIG_OKTAGON_SCSI=y
-
-#
-# Old CD-ROM drivers (not SCSI, not IDE)
-#
-# CONFIG_CD_NO_IDESCSI is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
+CONFIG_SCSI_A4000T=y
+CONFIG_SCSI_ZORRO7XX=y
 CONFIG_MD=y
 CONFIG_BLK_DEV_MD=m
 CONFIG_MD_LINEAR=m
 CONFIG_MD_RAID0=m
 CONFIG_MD_RAID1=m
 # CONFIG_MD_RAID10 is not set
-CONFIG_MD_RAID5=m
-CONFIG_MD_RAID6=m
+CONFIG_MD_RAID456=m
+CONFIG_MD_RAID5_RESHAPE=y
 CONFIG_MD_MULTIPATH=m
 # CONFIG_MD_FAULTY is not set
 CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
 CONFIG_DM_CRYPT=m
 CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_MIRROR=m
 CONFIG_DM_ZERO=m
 CONFIG_DM_MULTIPATH=m
 CONFIG_DM_MULTIPATH_EMC=m
-
-#
-# Fusion MPT device support
-#
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Networking support
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-# CONFIG_IP_PNP is not set
-CONFIG_NET_IPIP=m
-CONFIG_NET_IPGRE=m
-# CONFIG_ARPD is not set
-CONFIG_SYN_COOKIES=y
-CONFIG_INET_AH=m
-CONFIG_INET_ESP=m
-CONFIG_INET_IPCOMP=m
-CONFIG_INET_TUNNEL=m
-CONFIG_IP_TCPDIAG=m
-CONFIG_IP_TCPDIAG_IPV6=y
-
-#
-# IP: Virtual Server Configuration
-#
-# CONFIG_IP_VS is not set
-CONFIG_IPV6=m
-CONFIG_IPV6_PRIVACY=y
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_IPCOMP=m
-CONFIG_INET6_TUNNEL=m
-CONFIG_IPV6_TUNNEL=m
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
-
-#
-# IP: Netfilter Configuration
-#
-CONFIG_IP_NF_CONNTRACK=m
-# CONFIG_IP_NF_CT_ACCT is not set
-CONFIG_IP_NF_CONNTRACK_MARK=y
-# CONFIG_IP_NF_CT_PROTO_SCTP is not set
-CONFIG_IP_NF_FTP=m
-CONFIG_IP_NF_IRC=m
-CONFIG_IP_NF_TFTP=m
-CONFIG_IP_NF_AMANDA=m
-CONFIG_IP_NF_QUEUE=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_LIMIT=m
-CONFIG_IP_NF_MATCH_IPRANGE=m
-CONFIG_IP_NF_MATCH_MAC=m
-CONFIG_IP_NF_MATCH_PKTTYPE=m
-CONFIG_IP_NF_MATCH_MARK=m
-CONFIG_IP_NF_MATCH_MULTIPORT=m
-CONFIG_IP_NF_MATCH_TOS=m
-CONFIG_IP_NF_MATCH_RECENT=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_DSCP=m
-CONFIG_IP_NF_MATCH_AH_ESP=m
-CONFIG_IP_NF_MATCH_LENGTH=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_MATCH_TCPMSS=m
-CONFIG_IP_NF_MATCH_HELPER=m
-CONFIG_IP_NF_MATCH_STATE=m
-CONFIG_IP_NF_MATCH_CONNTRACK=m
-CONFIG_IP_NF_MATCH_OWNER=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
-CONFIG_IP_NF_MATCH_REALM=m
-# CONFIG_IP_NF_MATCH_SCTP is not set
-# CONFIG_IP_NF_MATCH_COMMENT is not set
-CONFIG_IP_NF_MATCH_CONNMARK=m
-CONFIG_IP_NF_MATCH_HASHLIMIT=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_LOG=m
-CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_IP_NF_TARGET_TCPMSS=m
-CONFIG_IP_NF_NAT=m
-CONFIG_IP_NF_NAT_NEEDED=y
-CONFIG_IP_NF_TARGET_MASQUERADE=m
-CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_SAME=m
-CONFIG_IP_NF_NAT_SNMP_BASIC=m
-CONFIG_IP_NF_NAT_IRC=m
-CONFIG_IP_NF_NAT_FTP=m
-CONFIG_IP_NF_NAT_TFTP=m
-CONFIG_IP_NF_NAT_AMANDA=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_TOS=m
-CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_DSCP=m
-CONFIG_IP_NF_TARGET_MARK=m
-CONFIG_IP_NF_TARGET_CLASSIFY=m
-CONFIG_IP_NF_TARGET_CONNMARK=m
-# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_TARGET_NOTRACK=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
-
-#
-# IPv6: Netfilter Configuration (EXPERIMENTAL)
-#
-CONFIG_IP6_NF_QUEUE=m
-CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_MATCH_LIMIT=m
-CONFIG_IP6_NF_MATCH_MAC=m
-CONFIG_IP6_NF_MATCH_RT=m
-CONFIG_IP6_NF_MATCH_OPTS=m
-CONFIG_IP6_NF_MATCH_FRAG=m
-CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_MULTIPORT=m
-CONFIG_IP6_NF_MATCH_OWNER=m
-CONFIG_IP6_NF_MATCH_MARK=m
-CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_MATCH_AHESP=m
-CONFIG_IP6_NF_MATCH_LENGTH=m
-CONFIG_IP6_NF_MATCH_EUI64=m
-CONFIG_IP6_NF_FILTER=m
-CONFIG_IP6_NF_TARGET_LOG=m
-CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_TARGET_MARK=m
-CONFIG_IP6_NF_RAW=m
-CONFIG_XFRM=y
-CONFIG_XFRM_USER=m
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-CONFIG_IP_SCTP=m
-# CONFIG_SCTP_DBG_MSG is not set
-# CONFIG_SCTP_DBG_OBJCNT is not set
-# CONFIG_SCTP_HMAC_NONE is not set
-# CONFIG_SCTP_HMAC_SHA1 is not set
-CONFIG_SCTP_HMAC_MD5=y
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-CONFIG_LLC=m
-# CONFIG_LLC2 is not set
-CONFIG_IPX=m
-# CONFIG_IPX_INTERN is not set
-CONFIG_ATALK=m
-# CONFIG_DEV_APPLETALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-CONFIG_NET_CLS_ROUTE=y
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-CONFIG_NETPOLL=y
-# CONFIG_NETPOLL_RX is not set
-# CONFIG_NETPOLL_TRAP is not set
-CONFIG_NET_POLL_CONTROLLER=y
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
+CONFIG_DM_MULTIPATH_RDAC=m
+CONFIG_DM_MULTIPATH_HP=m
+# CONFIG_DM_DELAY is not set
+CONFIG_DM_UEVENT=y
 CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
 CONFIG_DUMMY=m
 # CONFIG_BONDING is not set
+CONFIG_MACVLAN=m
 CONFIG_EQUALIZER=m
 # CONFIG_TUN is not set
-
-#
-# ARCnet devices
-#
+CONFIG_VETH=m
 # CONFIG_ARCNET is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
+# CONFIG_PHYLIB is not set
 CONFIG_NET_ETHERNET=y
-CONFIG_MII=m
+# CONFIG_MII is not set
 CONFIG_ARIADNE=m
 CONFIG_A2065=m
 CONFIG_HYDRA=m
@@ -493,32 +610,24 @@ CONFIG_APNE=m
 # CONFIG_DEPCA is not set
 # CONFIG_HP100 is not set
 # CONFIG_NET_ISA is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
 # CONFIG_NET_PCI is not set
+# CONFIG_B44 is not set
 # CONFIG_NET_POCKET is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
-#
-
-#
-# Token Ring devices
-#
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
 # CONFIG_TR is not set
 
 #
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# Wan interfaces
+# Wireless LAN
 #
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 # CONFIG_WAN is not set
-CONFIG_PLIP=m
+# CONFIG_PLIP is not set
 CONFIG_PPP=m
 # CONFIG_PPP_MULTILINK is not set
 CONFIG_PPP_FILTER=y
@@ -526,28 +635,28 @@ CONFIG_PPP_ASYNC=m
 CONFIG_PPP_SYNC_TTY=m
 CONFIG_PPP_DEFLATE=m
 CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
 CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
 CONFIG_SLIP=m
 CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLHC=m
 CONFIG_SLIP_SMART=y
 CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_SHAPER=m
 CONFIG_NETCONSOLE=m
-
-#
-# ISDN subsystem
-#
+CONFIG_NETCONSOLE_DYNAMIC=y
+CONFIG_NETPOLL=y
+# CONFIG_NETPOLL_TRAP is not set
+CONFIG_NET_POLL_CONTROLLER=y
 # CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
 # CONFIG_PHONE is not set
 
 #
 # Input device support
 #
 CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=m
+# CONFIG_INPUT_POLLDEV is not set
 
 #
 # Userland interfaces
@@ -557,7 +666,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 
@@ -570,6 +678,7 @@ CONFIG_INPUT_KEYBOARD=y
 # CONFIG_KEYBOARD_LKKBD is not set
 # CONFIG_KEYBOARD_XTKBD is not set
 # CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
 CONFIG_KEYBOARD_AMIGA=y
 CONFIG_INPUT_MOUSE=y
 # CONFIG_MOUSE_PS2 is not set
@@ -577,7 +686,7 @@ CONFIG_INPUT_MOUSE=y
 # CONFIG_MOUSE_INPORT is not set
 # CONFIG_MOUSE_LOGIBM is not set
 # CONFIG_MOUSE_PC110PAD is not set
-CONFIG_MOUSE_AMIGA=y
+CONFIG_MOUSE_AMIGA=m
 # CONFIG_MOUSE_VSXXXAA is not set
 CONFIG_INPUT_JOYSTICK=y
 # CONFIG_JOYSTICK_ANALOG is not set
@@ -603,16 +712,16 @@ CONFIG_INPUT_JOYSTICK=y
 # CONFIG_JOYSTICK_TURBOGRAFX is not set
 CONFIG_JOYSTICK_AMIGA=m
 # CONFIG_JOYSTICK_JOYDUMP is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_M68K_BEEP=m
+# CONFIG_INPUT_UINPUT is not set
 
 #
 # Hardware I/O ports
 #
-CONFIG_SERIO=m
-CONFIG_SERIO_SERPORT=m
-# CONFIG_SERIO_PARKBD is not set
-# CONFIG_SERIO_RAW is not set
+# CONFIG_SERIO is not set
 # CONFIG_GAMEPORT is not set
 
 #
@@ -621,6 +730,7 @@ CONFIG_SERIO_SERPORT=m
 CONFIG_VT=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 CONFIG_A2232=m
 
@@ -638,94 +748,102 @@ CONFIG_LEGACY_PTY_COUNT=256
 CONFIG_PRINTER=m
 # CONFIG_LP_CONSOLE is not set
 # CONFIG_PPDEV is not set
-# CONFIG_TIPAR is not set
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
+# CONFIG_HW_RANDOM is not set
 CONFIG_GEN_RTC=m
 CONFIG_GEN_RTC_X=y
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
-
-#
-# Ftape, the floppy tape device driver
-#
-# CONFIG_DRM is not set
 # CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
-
-#
-# I2C support
-#
+# CONFIG_TCG_TPM is not set
 # CONFIG_I2C is not set
 
 #
-# Dallas's 1-wire bus
+# SPI support
 #
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
 # CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
 
 #
-# Misc devices
+# Sonics Silicon Backplane
 #
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
-# Multimedia devices
+# Multifunction device drivers
 #
-# CONFIG_VIDEO_DEV is not set
+# CONFIG_MFD_SM501 is not set
 
 #
-# Digital Video Broadcasting Devices
+# Multimedia devices
 #
-# CONFIG_DVB is not set
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
 
 #
 # Graphics support
 #
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_SOFT_CURSOR=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
-CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
 # CONFIG_FB_TILEBLITTING is not set
-CONFIG_FB_CIRRUS=m
+
+#
+# Frame buffer hardware drivers
+#
+CONFIG_FB_CIRRUS=y
 CONFIG_FB_AMIGA=y
 CONFIG_FB_AMIGA_OCS=y
 CONFIG_FB_AMIGA_ECS=y
 CONFIG_FB_AMIGA_AGA=y
 CONFIG_FB_FM2=y
+# CONFIG_FB_UVESA is not set
 # CONFIG_FB_S1D13XXX is not set
 # CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
 #
 CONFIG_DUMMY_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
 # CONFIG_FONTS is not set
 CONFIG_FONT_8x8=y
 CONFIG_FONT_8x16=y
 CONFIG_FONT_PEARL_8x8=y
-
-#
-# Logo configuration
-#
 CONFIG_LOGO=y
 CONFIG_LOGO_LINUX_MONO=y
 CONFIG_LOGO_LINUX_VGA16=y
 CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
 # Sound
@@ -733,27 +851,21 @@ CONFIG_LOGO_LINUX_CLUT224=y
 CONFIG_SOUND=m
 CONFIG_DMASOUND_PAULA=m
 CONFIG_DMASOUND=m
-
-#
-# USB support
-#
-# CONFIG_USB_ARCH_HAS_HCD is not set
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=m
+# CONFIG_HID_DEBUG is not set
+CONFIG_HIDRAW=y
+# CONFIG_USB_SUPPORT is not set
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_RTC_CLASS is not set
+# CONFIG_AUXDISPLAY is not set
 
 #
-# InfiniBand support
+# Userspace I/O
 #
-# CONFIG_INFINIBAND is not set
+# CONFIG_UIO is not set
 
 #
 # Character devices
@@ -768,10 +880,11 @@ CONFIG_MULTIFACE_III_TTY=m
 #
 CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4DEV_FS is not set
 CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
 CONFIG_REISERFS_FS=m
 # CONFIG_REISERFS_CHECK is not set
 # CONFIG_REISERFS_PROC_INFO is not set
@@ -782,25 +895,29 @@ CONFIG_JFS_FS=m
 # CONFIG_JFS_DEBUG is not set
 # CONFIG_JFS_STATISTICS is not set
 CONFIG_FS_POSIX_ACL=y
-
-#
-# XFS support
-#
 CONFIG_XFS_FS=m
-CONFIG_XFS_EXPORT=y
-# CONFIG_XFS_RT is not set
 # CONFIG_XFS_QUOTA is not set
 # CONFIG_XFS_SECURITY is not set
 # CONFIG_XFS_POSIX_ACL is not set
-CONFIG_MINIX_FS=y
-# CONFIG_ROMFS_FS is not set
+# CONFIG_XFS_RT is not set
+CONFIG_GFS2_FS=m
+CONFIG_GFS2_FS_LOCKING_NOLOCK=m
+CONFIG_GFS2_FS_LOCKING_DLM=m
+CONFIG_OCFS2_FS=m
+# CONFIG_OCFS2_DEBUG_MASKLOG is not set
+# CONFIG_OCFS2_DEBUG_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
 CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
 # CONFIG_QFMT_V1 is not set
 # CONFIG_QFMT_V2 is not set
 CONFIG_QUOTACTL=y
-CONFIG_DNOTIFY=y
 CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
+CONFIG_FUSE_FS=m
 
 #
 # CD-ROM/DVD Filesystems
@@ -808,7 +925,6 @@ CONFIG_AUTOFS4_FS=m
 CONFIG_ISO9660_FS=y
 CONFIG_JOLIET=y
 CONFIG_ZISOFS=y
-CONFIG_ZISOFS_FS=y
 CONFIG_UDF_FS=m
 CONFIG_UDF_NLS=y
 
@@ -827,19 +943,18 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 #
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
 CONFIG_SYSFS=y
-# CONFIG_DEVFS_FS is not set
-# CONFIG_DEVPTS_FS_XATTR is not set
 CONFIG_TMPFS=y
-# CONFIG_TMPFS_XATTR is not set
+# CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
+CONFIG_CONFIGFS_FS=m
 
 #
 # Miscellaneous filesystems
 #
 # CONFIG_ADFS_FS is not set
-CONFIG_AFFS_FS=y
+CONFIG_AFFS_FS=m
 CONFIG_HFS_FS=m
 CONFIG_HFSPLUS_FS=m
 # CONFIG_BEFS_FS is not set
@@ -847,43 +962,39 @@ CONFIG_HFSPLUS_FS=m
 # CONFIG_EFS_FS is not set
 CONFIG_CRAMFS=m
 # CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=y
 CONFIG_HPFS_FS=m
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 CONFIG_SYSV_FS=m
 CONFIG_UFS_FS=m
 # CONFIG_UFS_FS_WRITE is not set
-
-#
-# Network File Systems
-#
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
 # CONFIG_NFS_DIRECTIO is not set
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
-CONFIG_NFSD_V4=y
+# CONFIG_NFSD_V3_ACL is not set
+# CONFIG_NFSD_V4 is not set
 CONFIG_NFSD_TCP=y
 CONFIG_LOCKD=m
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=m
+CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=m
 CONFIG_SUNRPC_GSS=m
+CONFIG_SUNRPC_BIND34=y
 CONFIG_RPCSEC_GSS_KRB5=m
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
 CONFIG_SMB_NLS_DEFAULT=y
 CONFIG_SMB_NLS_REMOTE="cp437"
 # CONFIG_CIFS is not set
-CONFIG_NCP_FS=m
-# CONFIG_NCPFS_PACKET_SIGNING is not set
-# CONFIG_NCPFS_IOCTL_LOCKING is not set
-# CONFIG_NCPFS_STRONG is not set
-CONFIG_NCPFS_NFS_NS=y
-CONFIG_NCPFS_OS2_NS=y
-# CONFIG_NCPFS_SMALLDOS is not set
-CONFIG_NCPFS_NLS=y
-# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_NCP_FS is not set
 CONFIG_CODA_FS=m
 # CONFIG_CODA_FS_OLD_API is not set
 # CONFIG_AFS_FS is not set
@@ -894,10 +1005,6 @@ CONFIG_CODA_FS=m
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_AMIGA_PARTITION=y
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=y
@@ -938,35 +1045,42 @@ CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
 CONFIG_NLS_UTF8=m
+CONFIG_DLM=m
+# CONFIG_DLM_DEBUG is not set
 
 #
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
-CONFIG_DEBUG_KERNEL=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_MAGIC_SYSRQ=y
-CONFIG_LOG_BUF_SHIFT=16
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_INFO is not set
+# CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
-# CONFIG_FRAME_POINTER is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_SAMPLES is not set
 
 #
 # Security options
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_XOR_BLOCKS=m
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_XOR=m
 CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_SEQIV=m
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
 CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=m
 CONFIG_CRYPTO_NULL=m
 CONFIG_CRYPTO_MD4=m
 CONFIG_CRYPTO_MD5=m
@@ -975,9 +1089,21 @@ CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
 CONFIG_CRYPTO_WP512=m
 CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_XTS=m
+CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_CRYPTD=m
 CONFIG_CRYPTO_DES=m
+CONFIG_CRYPTO_FCRYPT=m
 CONFIG_CRYPTO_BLOWFISH=m
 CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
 CONFIG_CRYPTO_SERPENT=m
 CONFIG_CRYPTO_AES=m
 CONFIG_CRYPTO_CAST5=m
@@ -986,20 +1112,35 @@ CONFIG_CRYPTO_TEA=m
 CONFIG_CRYPTO_ARC4=m
 CONFIG_CRYPTO_KHAZAD=m
 CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SALSA20=m
 CONFIG_CRYPTO_DEFLATE=m
 CONFIG_CRYPTO_MICHAEL_MIC=m
 CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_CAMELLIA=m
 CONFIG_CRYPTO_TEST=m
-
-#
-# Hardware crypto devices
-#
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_LZO=m
+# CONFIG_CRYPTO_HW is not set
 
 #
 # Library routines
 #
+CONFIG_BITREVERSE=y
 CONFIG_CRC_CCITT=m
+CONFIG_CRC16=m
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 CONFIG_LIBCRC32C=m
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=m
+CONFIG_LZO_COMPRESS=m
+CONFIG_LZO_DECOMPRESS=m
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_DMA=y
diff --git a/arch/m68k/configs/apollo_defconfig b/arch/m68k/configs/apollo_defconfig
index 63024b0b7ac3..e61196cd7fa5 100644
--- a/arch/m68k/configs/apollo_defconfig
+++ b/arch/m68k/configs/apollo_defconfig
@@ -1,63 +1,111 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc6-m68k
-# Tue Jun  7 20:34:27 2005
+# Linux kernel version: 2.6.25-rc8
+# Wed Apr  2 20:46:07 2008
 #
 CONFIG_M68K=y
 CONFIG_MMU=y
-CONFIG_UID16=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_TIME_LOW_RES=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_NO_IOPORT=y
+# CONFIG_NO_DMA is not set
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_HZ=100
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
-CONFIG_CLEAN_COMPILE=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION="-apollo"
+CONFIG_LOCALVERSION_AUTO=y
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_BSD_PROCESS_ACCT=y
 # CONFIG_BSD_PROCESS_ACCT_V3 is not set
-CONFIG_SYSCTL=y
-CONFIG_AUDIT=y
-CONFIG_HOTPLUG=y
-CONFIG_KOBJECT_UEVENT=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_COMPAT_BRK is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+# CONFIG_HAVE_OPROFILE is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_OBSOLETE_MODPARM=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+CONFIG_BLK_DEV_BSG=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
 
 #
 # Platform dependent setup
@@ -80,10 +128,24 @@ CONFIG_M68030=y
 CONFIG_M68040=y
 CONFIG_M68060=y
 CONFIG_MMU_MOTOROLA=y
-CONFIG_M68KFPU_EMU=y
-CONFIG_M68KFPU_EMU_EXTRAPREC=y
-# CONFIG_M68KFPU_EMU_ONLY is not set
+# CONFIG_M68KFPU_EMU is not set
 # CONFIG_ADVANCED is not set
+CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
+CONFIG_NODES_SHIFT=3
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_FLATMEM_MANUAL is not set
+CONFIG_DISCONTIGMEM_MANUAL=y
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_DISCONTIGMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_NEED_MULTIPLE_NODES=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
 
 #
 # General setup
@@ -93,134 +155,11 @@ CONFIG_BINFMT_AOUT=m
 CONFIG_BINFMT_MISC=m
 CONFIG_HEARTBEAT=y
 CONFIG_PROC_HARDWARE=y
+CONFIG_ZONE_DMA=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 
 #
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
-# CONFIG_DEBUG_DRIVER is not set
-
-#
-# Memory Technology Devices (MTD)
-#
-# CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_CDROM_PKTCDVD_BUFFERS=8
-# CONFIG_CDROM_PKTCDVD_WCACHE is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_ATA_OVER_ETH=m
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-CONFIG_SCSI=y
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=m
-# CONFIG_CHR_DEV_OSST is not set
-CONFIG_BLK_DEV_SR=y
-CONFIG_BLK_DEV_SR_VENDOR=y
-CONFIG_CHR_DEV_SG=m
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-# CONFIG_SCSI_MULTI_LUN is not set
-CONFIG_SCSI_CONSTANTS=y
-# CONFIG_SCSI_LOGGING is not set
-
-#
-# SCSI Transport Attributes
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-
-#
-# SCSI low-level drivers
-#
-# CONFIG_SCSI_SATA is not set
-# CONFIG_SCSI_DEBUG is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-# CONFIG_MD_RAID10 is not set
-CONFIG_MD_RAID5=m
-CONFIG_MD_RAID6=m
-CONFIG_MD_MULTIPATH=m
-# CONFIG_MD_FAULTY is not set
-CONFIG_BLK_DEV_DM=m
-CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
-CONFIG_DM_MIRROR=m
-CONFIG_DM_ZERO=m
-CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_EMC=m
-
-#
-# Fusion MPT device support
-#
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Networking support
+# Networking
 #
 CONFIG_NET=y
 
@@ -230,10 +169,17 @@ CONFIG_NET=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+CONFIG_XFRM_MIGRATE=y
+# CONFIG_XFRM_STATISTICS is not set
 CONFIG_NET_KEY=y
+CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
 # CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
@@ -245,145 +191,199 @@ CONFIG_SYN_COOKIES=y
 CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
 CONFIG_INET_TUNNEL=m
-CONFIG_IP_TCPDIAG=m
-CONFIG_IP_TCPDIAG_IPV6=y
-
-#
-# IP: Virtual Server Configuration
-#
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_INET_LRO=m
+CONFIG_INET_DIAG=m
+CONFIG_INET_TCP_DIAG=m
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
 # CONFIG_IP_VS is not set
 CONFIG_IPV6=m
 CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
 CONFIG_INET6_AH=m
 CONFIG_INET6_ESP=m
 CONFIG_INET6_IPCOMP=m
+# CONFIG_IPV6_MIP6 is not set
+CONFIG_INET6_XFRM_TUNNEL=m
 CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
+CONFIG_IPV6_SIT=m
 CONFIG_IPV6_TUNNEL=m
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_NETWORK_SECMARK is not set
 CONFIG_NETFILTER=y
 # CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+CONFIG_NF_CT_PROTO_GRE=m
+CONFIG_NF_CT_PROTO_SCTP=m
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+# CONFIG_NF_CT_NETLINK is not set
+CONFIG_NETFILTER_XTABLES=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_RATEEST=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
 
 #
 # IP: Netfilter Configuration
 #
-CONFIG_IP_NF_CONNTRACK=m
-# CONFIG_IP_NF_CT_ACCT is not set
-CONFIG_IP_NF_CONNTRACK_MARK=y
-# CONFIG_IP_NF_CT_PROTO_SCTP is not set
-CONFIG_IP_NF_FTP=m
-CONFIG_IP_NF_IRC=m
-CONFIG_IP_NF_TFTP=m
-CONFIG_IP_NF_AMANDA=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
 CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_LIMIT=m
-CONFIG_IP_NF_MATCH_IPRANGE=m
-CONFIG_IP_NF_MATCH_MAC=m
-CONFIG_IP_NF_MATCH_PKTTYPE=m
-CONFIG_IP_NF_MATCH_MARK=m
-CONFIG_IP_NF_MATCH_MULTIPORT=m
-CONFIG_IP_NF_MATCH_TOS=m
 CONFIG_IP_NF_MATCH_RECENT=m
 CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_DSCP=m
-CONFIG_IP_NF_MATCH_AH_ESP=m
-CONFIG_IP_NF_MATCH_LENGTH=m
+CONFIG_IP_NF_MATCH_AH=m
 CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_MATCH_TCPMSS=m
-CONFIG_IP_NF_MATCH_HELPER=m
-CONFIG_IP_NF_MATCH_STATE=m
-CONFIG_IP_NF_MATCH_CONNTRACK=m
-CONFIG_IP_NF_MATCH_OWNER=m
 CONFIG_IP_NF_MATCH_ADDRTYPE=m
-CONFIG_IP_NF_MATCH_REALM=m
-# CONFIG_IP_NF_MATCH_SCTP is not set
-# CONFIG_IP_NF_MATCH_COMMENT is not set
-CONFIG_IP_NF_MATCH_CONNMARK=m
-CONFIG_IP_NF_MATCH_HASHLIMIT=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
 CONFIG_IP_NF_TARGET_LOG=m
 CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_IP_NF_TARGET_TCPMSS=m
-CONFIG_IP_NF_NAT=m
-CONFIG_IP_NF_NAT_NEEDED=y
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
 CONFIG_IP_NF_TARGET_MASQUERADE=m
 CONFIG_IP_NF_TARGET_REDIRECT=m
 CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_SAME=m
-CONFIG_IP_NF_NAT_SNMP_BASIC=m
-CONFIG_IP_NF_NAT_IRC=m
-CONFIG_IP_NF_NAT_FTP=m
-CONFIG_IP_NF_NAT_TFTP=m
-CONFIG_IP_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_SNMP_BASIC=m
+CONFIG_NF_NAT_PROTO_GRE=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+CONFIG_NF_NAT_TFTP=m
+CONFIG_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+CONFIG_NF_NAT_SIP=m
 CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_TOS=m
 CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_DSCP=m
-CONFIG_IP_NF_TARGET_MARK=m
-CONFIG_IP_NF_TARGET_CLASSIFY=m
-CONFIG_IP_NF_TARGET_CONNMARK=m
-# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
 CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_TARGET_NOTRACK=m
 CONFIG_IP_NF_ARPTABLES=m
 CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
 
 #
-# IPv6: Netfilter Configuration (EXPERIMENTAL)
+# IPv6: Netfilter Configuration
 #
+CONFIG_NF_CONNTRACK_IPV6=m
 CONFIG_IP6_NF_QUEUE=m
 CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_MATCH_LIMIT=m
-CONFIG_IP6_NF_MATCH_MAC=m
 CONFIG_IP6_NF_MATCH_RT=m
 CONFIG_IP6_NF_MATCH_OPTS=m
 CONFIG_IP6_NF_MATCH_FRAG=m
 CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_MULTIPORT=m
-CONFIG_IP6_NF_MATCH_OWNER=m
-CONFIG_IP6_NF_MATCH_MARK=m
 CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_MATCH_AHESP=m
-CONFIG_IP6_NF_MATCH_LENGTH=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_MH=m
 CONFIG_IP6_NF_MATCH_EUI64=m
 CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_TARGET_MARK=m
+CONFIG_IP6_NF_TARGET_HL=m
 CONFIG_IP6_NF_RAW=m
-CONFIG_XFRM=y
-CONFIG_XFRM_USER=m
+CONFIG_IP_DCCP=m
+CONFIG_INET_DCCP_DIAG=m
+CONFIG_IP_DCCP_ACKVEC=y
 
 #
-# SCTP Configuration (EXPERIMENTAL)
+# DCCP CCIDs Configuration (EXPERIMENTAL)
 #
+CONFIG_IP_DCCP_CCID2=m
+# CONFIG_IP_DCCP_CCID2_DEBUG is not set
+CONFIG_IP_DCCP_CCID3=m
+# CONFIG_IP_DCCP_CCID3_DEBUG is not set
+CONFIG_IP_DCCP_CCID3_RTO=100
+CONFIG_IP_DCCP_TFRC_LIB=m
 CONFIG_IP_SCTP=m
 # CONFIG_SCTP_DBG_MSG is not set
 # CONFIG_SCTP_DBG_OBJCNT is not set
 # CONFIG_SCTP_HMAC_NONE is not set
 # CONFIG_SCTP_HMAC_SHA1 is not set
 CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 CONFIG_LLC=m
 # CONFIG_LLC2 is not set
-CONFIG_IPX=m
-# CONFIG_IPX_INTERN is not set
+# CONFIG_IPX is not set
 CONFIG_ATALK=m
 # CONFIG_DEV_APPLETALK is not set
 # CONFIG_X25 is not set
 # CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 CONFIG_NET_CLS_ROUTE=y
 
@@ -391,46 +391,154 @@ CONFIG_NET_CLS_ROUTE=y
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
-CONFIG_NETPOLL=y
-# CONFIG_NETPOLL_RX is not set
-# CONFIG_NETPOLL_TRAP is not set
-CONFIG_NET_POLL_CONTROLLER=y
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=m
-# CONFIG_BONDING is not set
-CONFIG_EQUALIZER=m
-# CONFIG_TUN is not set
+# CONFIG_AF_RXRPC is not set
 
 #
-# Ethernet (10 or 100Mbit)
+# Wireless
 #
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=m
-CONFIG_APOLLO_ELPLUS=y
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=m
+CONFIG_IEEE80211_CRYPT_CCMP=m
+CONFIG_IEEE80211_CRYPT_TKIP=m
+CONFIG_IEEE80211_SOFTMAC=m
+# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
-# Ethernet (1000 Mbit)
+# Device Drivers
 #
 
 #
-# Ethernet (10000 Mbit)
+# Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=m
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=m
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+CONFIG_ATA_OVER_ETH=m
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
 
 #
-# Token Ring devices
+# SCSI device support
 #
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=m
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
 
 #
-# Wireless LAN (non-hamradio)
+# SCSI support type (disk, tape, CD-ROM)
 #
-# CONFIG_NET_RADIO is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_ST=m
+CONFIG_CHR_DEV_OSST=m
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_DEV_SR_VENDOR=y
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+CONFIG_SCSI_CONSTANTS=y
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=m
+CONFIG_SCSI_SAS_ATTRS=m
+CONFIG_SCSI_SAS_LIBSAS=m
+CONFIG_SCSI_SAS_HOST_SMP=y
+# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
+CONFIG_SCSI_SRP_ATTRS=m
+CONFIG_SCSI_SRP_TGT_ATTRS=y
+CONFIG_SCSI_LOWLEVEL=y
+CONFIG_ISCSI_TCP=m
+# CONFIG_SCSI_DEBUG is not set
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+# CONFIG_MD_RAID10 is not set
+CONFIG_MD_RAID456=m
+CONFIG_MD_RAID5_RESHAPE=y
+CONFIG_MD_MULTIPATH=m
+# CONFIG_MD_FAULTY is not set
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_ZERO=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_MULTIPATH_EMC=m
+CONFIG_DM_MULTIPATH_RDAC=m
+CONFIG_DM_MULTIPATH_HP=m
+# CONFIG_DM_DELAY is not set
+CONFIG_DM_UEVENT=y
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+CONFIG_DUMMY=m
+# CONFIG_BONDING is not set
+CONFIG_MACVLAN=m
+CONFIG_EQUALIZER=m
+# CONFIG_TUN is not set
+CONFIG_VETH=m
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+CONFIG_APOLLO_ELPLUS=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
 
 #
-# Wan interfaces
+# Wireless LAN
 #
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 # CONFIG_WAN is not set
 CONFIG_PPP=m
 # CONFIG_PPP_MULTILINK is not set
@@ -439,28 +547,28 @@ CONFIG_PPP_ASYNC=m
 CONFIG_PPP_SYNC_TTY=m
 CONFIG_PPP_DEFLATE=m
 CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
 CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
 CONFIG_SLIP=m
 CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLHC=m
 CONFIG_SLIP_SMART=y
 CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_SHAPER=m
 CONFIG_NETCONSOLE=m
-
-#
-# ISDN subsystem
-#
+CONFIG_NETCONSOLE_DYNAMIC=y
+CONFIG_NETPOLL=y
+# CONFIG_NETPOLL_TRAP is not set
+CONFIG_NET_POLL_CONTROLLER=y
 # CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
 # CONFIG_PHONE is not set
 
 #
 # Input device support
 #
 CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=m
+# CONFIG_INPUT_POLLDEV is not set
 
 #
 # Userland interfaces
@@ -470,7 +578,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 
@@ -483,11 +590,19 @@ CONFIG_INPUT_KEYBOARD=y
 # CONFIG_KEYBOARD_LKKBD is not set
 # CONFIG_KEYBOARD_XTKBD is not set
 # CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
 CONFIG_INPUT_MOUSE=y
 CONFIG_MOUSE_PS2=m
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
 CONFIG_MOUSE_SERIAL=m
 # CONFIG_MOUSE_VSXXXAA is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 
@@ -495,7 +610,7 @@ CONFIG_MOUSE_SERIAL=m
 # Hardware I/O ports
 #
 CONFIG_SERIO=m
-CONFIG_SERIO_SERPORT=m
+# CONFIG_SERIO_SERPORT is not set
 CONFIG_SERIO_LIBPS2=m
 # CONFIG_SERIO_RAW is not set
 # CONFIG_GAMEPORT is not set
@@ -506,6 +621,7 @@ CONFIG_SERIO_LIBPS2=m
 CONFIG_VT=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -519,90 +635,114 @@ CONFIG_HW_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
-CONFIG_GEN_RTC=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_GEN_RTC=m
 CONFIG_GEN_RTC_X=y
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
-
-#
-# Ftape, the floppy tape device driver
-#
-# CONFIG_DRM is not set
 # CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
 
 #
-# TPM devices
+# SPI support
 #
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
 
 #
-# I2C support
+# Sonics Silicon Backplane
 #
-# CONFIG_I2C is not set
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
-# Dallas's 1-wire bus
+# Multifunction device drivers
 #
-# CONFIG_W1 is not set
+# CONFIG_MFD_SM501 is not set
 
 #
-# Misc devices
+# Multimedia devices
 #
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
 
 #
-# Multimedia devices
+# Graphics support
 #
-# CONFIG_VIDEO_DEV is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+# CONFIG_FB_CFB_COPYAREA is not set
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
 
 #
-# Digital Video Broadcasting Devices
+# Frame buffer hardware drivers
 #
-# CONFIG_DVB is not set
+CONFIG_FB_APOLLO=y
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
-# Graphics support
+# Display device support
 #
-# CONFIG_FB is not set
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
 #
 CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+# CONFIG_LOGO_LINUX_VGA16 is not set
+# CONFIG_LOGO_LINUX_CLUT224 is not set
 
 #
 # Sound
 #
 # CONFIG_SOUND is not set
-
-#
-# USB support
-#
-# CONFIG_USB_ARCH_HAS_HCD is not set
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=m
+# CONFIG_HID_DEBUG is not set
+CONFIG_HIDRAW=y
+# CONFIG_USB_SUPPORT is not set
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_RTC_CLASS is not set
 
 #
-# InfiniBand support
+# Userspace I/O
 #
-# CONFIG_INFINIBAND is not set
+# CONFIG_UIO is not set
 
 #
 # Character devices
@@ -615,10 +755,11 @@ CONFIG_SERIAL_CONSOLE=y
 #
 CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4DEV_FS is not set
 CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
 CONFIG_REISERFS_FS=m
 # CONFIG_REISERFS_CHECK is not set
 # CONFIG_REISERFS_PROC_INFO is not set
@@ -629,25 +770,29 @@ CONFIG_JFS_FS=m
 # CONFIG_JFS_DEBUG is not set
 # CONFIG_JFS_STATISTICS is not set
 CONFIG_FS_POSIX_ACL=y
-
-#
-# XFS support
-#
 CONFIG_XFS_FS=m
-CONFIG_XFS_EXPORT=y
-# CONFIG_XFS_RT is not set
 # CONFIG_XFS_QUOTA is not set
 # CONFIG_XFS_SECURITY is not set
 # CONFIG_XFS_POSIX_ACL is not set
-CONFIG_MINIX_FS=y
-# CONFIG_ROMFS_FS is not set
+# CONFIG_XFS_RT is not set
+CONFIG_GFS2_FS=m
+CONFIG_GFS2_FS_LOCKING_NOLOCK=m
+CONFIG_GFS2_FS_LOCKING_DLM=m
+CONFIG_OCFS2_FS=m
+# CONFIG_OCFS2_DEBUG_MASKLOG is not set
+# CONFIG_OCFS2_DEBUG_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
 CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
 # CONFIG_QFMT_V1 is not set
 # CONFIG_QFMT_V2 is not set
 CONFIG_QUOTACTL=y
-CONFIG_DNOTIFY=y
 CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
+CONFIG_FUSE_FS=m
 
 #
 # CD-ROM/DVD Filesystems
@@ -655,7 +800,6 @@ CONFIG_AUTOFS4_FS=m
 CONFIG_ISO9660_FS=y
 CONFIG_JOLIET=y
 CONFIG_ZISOFS=y
-CONFIG_ZISOFS_FS=y
 CONFIG_UDF_FS=m
 CONFIG_UDF_NLS=y
 
@@ -674,13 +818,12 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 #
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
 CONFIG_SYSFS=y
-# CONFIG_DEVFS_FS is not set
-# CONFIG_DEVPTS_FS_XATTR is not set
 CONFIG_TMPFS=y
-# CONFIG_TMPFS_XATTR is not set
+# CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
+CONFIG_CONFIGFS_FS=m
 
 #
 # Miscellaneous filesystems
@@ -694,44 +837,40 @@ CONFIG_HFSPLUS_FS=m
 # CONFIG_EFS_FS is not set
 CONFIG_CRAMFS=m
 # CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=y
 CONFIG_HPFS_FS=m
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 CONFIG_SYSV_FS=m
 CONFIG_UFS_FS=m
 # CONFIG_UFS_FS_WRITE is not set
-
-#
-# Network File Systems
-#
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
 # CONFIG_NFS_DIRECTIO is not set
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
-CONFIG_NFSD_V4=y
+# CONFIG_NFSD_V3_ACL is not set
+# CONFIG_NFSD_V4 is not set
 CONFIG_NFSD_TCP=y
 CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=m
+CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
+CONFIG_SUNRPC_BIND34=y
 CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
 CONFIG_SMB_NLS_DEFAULT=y
 CONFIG_SMB_NLS_REMOTE="cp437"
 # CONFIG_CIFS is not set
-CONFIG_NCP_FS=m
-# CONFIG_NCPFS_PACKET_SIGNING is not set
-# CONFIG_NCPFS_IOCTL_LOCKING is not set
-# CONFIG_NCPFS_STRONG is not set
-CONFIG_NCPFS_NFS_NS=y
-CONFIG_NCPFS_OS2_NS=y
-# CONFIG_NCPFS_SMALLDOS is not set
-CONFIG_NCPFS_NLS=y
-# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_NCP_FS is not set
 CONFIG_CODA_FS=m
 # CONFIG_CODA_FS_OLD_API is not set
 # CONFIG_AFS_FS is not set
@@ -741,10 +880,6 @@ CONFIG_CODA_FS=m
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=y
@@ -785,35 +920,42 @@ CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
 CONFIG_NLS_UTF8=m
+CONFIG_DLM=m
+# CONFIG_DLM_DEBUG is not set
 
 #
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
-CONFIG_DEBUG_KERNEL=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_MAGIC_SYSRQ=y
-CONFIG_LOG_BUF_SHIFT=16
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_INFO is not set
+# CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
-# CONFIG_FRAME_POINTER is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_SAMPLES is not set
 
 #
 # Security options
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_XOR_BLOCKS=m
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_XOR=m
 CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_SEQIV=m
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
 CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=m
 CONFIG_CRYPTO_NULL=m
 CONFIG_CRYPTO_MD4=m
 CONFIG_CRYPTO_MD5=y
@@ -822,9 +964,21 @@ CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
 CONFIG_CRYPTO_WP512=m
 CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_XTS=m
+CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_CRYPTD=m
 CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
 CONFIG_CRYPTO_BLOWFISH=m
 CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
 CONFIG_CRYPTO_SERPENT=m
 CONFIG_CRYPTO_AES=m
 CONFIG_CRYPTO_CAST5=m
@@ -833,20 +987,35 @@ CONFIG_CRYPTO_TEA=m
 CONFIG_CRYPTO_ARC4=m
 CONFIG_CRYPTO_KHAZAD=m
 CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SALSA20=m
 CONFIG_CRYPTO_DEFLATE=m
 CONFIG_CRYPTO_MICHAEL_MIC=m
 CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_CAMELLIA=m
 CONFIG_CRYPTO_TEST=m
-
-#
-# Hardware crypto devices
-#
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_LZO=m
+# CONFIG_CRYPTO_HW is not set
 
 #
 # Library routines
 #
+CONFIG_BITREVERSE=y
 CONFIG_CRC_CCITT=m
+CONFIG_CRC16=m
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 CONFIG_LIBCRC32C=m
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=m
+CONFIG_LZO_COMPRESS=m
+CONFIG_LZO_DECOMPRESS=m
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_DMA=y
diff --git a/arch/m68k/configs/atari_defconfig b/arch/m68k/configs/atari_defconfig
index 6433da2d2ce2..ba7f971bb026 100644
--- a/arch/m68k/configs/atari_defconfig
+++ b/arch/m68k/configs/atari_defconfig
@@ -1,63 +1,111 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc6-m68k
-# Tue Jun  7 20:34:32 2005
+# Linux kernel version: 2.6.25-rc8
+# Wed Apr  2 20:46:09 2008
 #
 CONFIG_M68K=y
 CONFIG_MMU=y
-CONFIG_UID16=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_TIME_LOW_RES=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_NO_IOPORT=y
+# CONFIG_NO_DMA is not set
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_HZ=100
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
-CONFIG_CLEAN_COMPILE=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION="-atari"
+CONFIG_LOCALVERSION_AUTO=y
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_BSD_PROCESS_ACCT=y
 # CONFIG_BSD_PROCESS_ACCT_V3 is not set
-CONFIG_SYSCTL=y
-CONFIG_AUDIT=y
-CONFIG_HOTPLUG=y
-CONFIG_KOBJECT_UEVENT=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_COMPAT_BRK is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+# CONFIG_HAVE_OPROFILE is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_OBSOLETE_MODPARM=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+CONFIG_BLK_DEV_BSG=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
 
 #
 # Platform dependent setup
@@ -80,10 +128,24 @@ CONFIG_M68030=y
 CONFIG_M68040=y
 CONFIG_M68060=y
 CONFIG_MMU_MOTOROLA=y
-CONFIG_M68KFPU_EMU=y
-CONFIG_M68KFPU_EMU_EXTRAPREC=y
-# CONFIG_M68KFPU_EMU_ONLY is not set
+# CONFIG_M68KFPU_EMU is not set
 # CONFIG_ADVANCED is not set
+CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
+CONFIG_NODES_SHIFT=3
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_FLATMEM_MANUAL is not set
+CONFIG_DISCONTIGMEM_MANUAL=y
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_DISCONTIGMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_NEED_MULTIPLE_NODES=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
 
 #
 # General setup
@@ -94,166 +156,11 @@ CONFIG_BINFMT_MISC=m
 CONFIG_STRAM_PROC=y
 CONFIG_HEARTBEAT=y
 CONFIG_PROC_HARDWARE=y
+CONFIG_ZONE_DMA=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 
 #
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
-# CONFIG_DEBUG_DRIVER is not set
-
-#
-# Memory Technology Devices (MTD)
-#
-# CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
-CONFIG_PARPORT=m
-# CONFIG_PARPORT_PC is not set
-CONFIG_PARPORT_NOT_PC=y
-CONFIG_PARPORT_ATARI=m
-# CONFIG_PARPORT_GSC is not set
-CONFIG_PARPORT_1284=y
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
-CONFIG_ATARI_FLOPPY=y
-# CONFIG_PARIDE is not set
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_CDROM_PKTCDVD_BUFFERS=8
-# CONFIG_CDROM_PKTCDVD_WCACHE is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_ATA_OVER_ETH=m
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-CONFIG_IDE=y
-CONFIG_BLK_DEV_IDE=y
-
-#
-# Please see Documentation/ide.txt for help/info on IDE drives
-#
-# CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_BLK_DEV_IDEDISK=y
-# CONFIG_IDEDISK_MULTI_MODE is not set
-CONFIG_BLK_DEV_IDECD=y
-CONFIG_BLK_DEV_IDETAPE=m
-CONFIG_BLK_DEV_IDEFLOPPY=m
-# CONFIG_BLK_DEV_IDESCSI is not set
-# CONFIG_IDE_TASK_IOCTL is not set
-
-#
-# IDE chipset support/bugfixes
-#
-CONFIG_IDE_GENERIC=y
-# CONFIG_IDE_ARM is not set
-CONFIG_BLK_DEV_FALCON_IDE=y
-# CONFIG_BLK_DEV_IDEDMA is not set
-# CONFIG_IDEDMA_AUTO is not set
-# CONFIG_BLK_DEV_HD is not set
-
-#
-# SCSI device support
-#
-CONFIG_SCSI=y
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=m
-# CONFIG_CHR_DEV_OSST is not set
-CONFIG_BLK_DEV_SR=y
-CONFIG_BLK_DEV_SR_VENDOR=y
-CONFIG_CHR_DEV_SG=m
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-# CONFIG_SCSI_MULTI_LUN is not set
-CONFIG_SCSI_CONSTANTS=y
-# CONFIG_SCSI_LOGGING is not set
-
-#
-# SCSI Transport Attributes
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-
-#
-# SCSI low-level drivers
-#
-# CONFIG_SCSI_SATA is not set
-# CONFIG_SCSI_PPA is not set
-# CONFIG_SCSI_IMM is not set
-# CONFIG_SCSI_DEBUG is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-# CONFIG_MD_RAID10 is not set
-CONFIG_MD_RAID5=m
-CONFIG_MD_RAID6=m
-CONFIG_MD_MULTIPATH=m
-# CONFIG_MD_FAULTY is not set
-CONFIG_BLK_DEV_DM=m
-CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
-CONFIG_DM_MIRROR=m
-CONFIG_DM_ZERO=m
-CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_EMC=m
-
-#
-# Fusion MPT device support
-#
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Networking support
+# Networking
 #
 CONFIG_NET=y
 
@@ -263,10 +170,17 @@ CONFIG_NET=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+CONFIG_XFRM_MIGRATE=y
+# CONFIG_XFRM_STATISTICS is not set
 CONFIG_NET_KEY=y
+CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
 # CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
 # CONFIG_IP_PNP is not set
 CONFIG_NET_IPIP=m
 CONFIG_NET_IPGRE=m
@@ -275,145 +189,199 @@ CONFIG_SYN_COOKIES=y
 CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
 CONFIG_INET_TUNNEL=m
-CONFIG_IP_TCPDIAG=m
-CONFIG_IP_TCPDIAG_IPV6=y
-
-#
-# IP: Virtual Server Configuration
-#
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_INET_LRO=m
+CONFIG_INET_DIAG=m
+CONFIG_INET_TCP_DIAG=m
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
 # CONFIG_IP_VS is not set
 CONFIG_IPV6=m
 CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
 CONFIG_INET6_AH=m
 CONFIG_INET6_ESP=m
 CONFIG_INET6_IPCOMP=m
+# CONFIG_IPV6_MIP6 is not set
+CONFIG_INET6_XFRM_TUNNEL=m
 CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
+CONFIG_IPV6_SIT=m
 CONFIG_IPV6_TUNNEL=m
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_NETWORK_SECMARK is not set
 CONFIG_NETFILTER=y
 # CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+CONFIG_NF_CT_PROTO_GRE=m
+CONFIG_NF_CT_PROTO_SCTP=m
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+# CONFIG_NF_CT_NETLINK is not set
+CONFIG_NETFILTER_XTABLES=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_RATEEST=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
 
 #
 # IP: Netfilter Configuration
 #
-CONFIG_IP_NF_CONNTRACK=m
-# CONFIG_IP_NF_CT_ACCT is not set
-CONFIG_IP_NF_CONNTRACK_MARK=y
-# CONFIG_IP_NF_CT_PROTO_SCTP is not set
-CONFIG_IP_NF_FTP=m
-CONFIG_IP_NF_IRC=m
-CONFIG_IP_NF_TFTP=m
-CONFIG_IP_NF_AMANDA=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
 CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_LIMIT=m
-CONFIG_IP_NF_MATCH_IPRANGE=m
-CONFIG_IP_NF_MATCH_MAC=m
-CONFIG_IP_NF_MATCH_PKTTYPE=m
-CONFIG_IP_NF_MATCH_MARK=m
-CONFIG_IP_NF_MATCH_MULTIPORT=m
-CONFIG_IP_NF_MATCH_TOS=m
 CONFIG_IP_NF_MATCH_RECENT=m
 CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_DSCP=m
-CONFIG_IP_NF_MATCH_AH_ESP=m
-CONFIG_IP_NF_MATCH_LENGTH=m
+CONFIG_IP_NF_MATCH_AH=m
 CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_MATCH_TCPMSS=m
-CONFIG_IP_NF_MATCH_HELPER=m
-CONFIG_IP_NF_MATCH_STATE=m
-CONFIG_IP_NF_MATCH_CONNTRACK=m
-CONFIG_IP_NF_MATCH_OWNER=m
 CONFIG_IP_NF_MATCH_ADDRTYPE=m
-CONFIG_IP_NF_MATCH_REALM=m
-# CONFIG_IP_NF_MATCH_SCTP is not set
-# CONFIG_IP_NF_MATCH_COMMENT is not set
-CONFIG_IP_NF_MATCH_CONNMARK=m
-CONFIG_IP_NF_MATCH_HASHLIMIT=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
 CONFIG_IP_NF_TARGET_LOG=m
 CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_IP_NF_TARGET_TCPMSS=m
-CONFIG_IP_NF_NAT=m
-CONFIG_IP_NF_NAT_NEEDED=y
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
 CONFIG_IP_NF_TARGET_MASQUERADE=m
 CONFIG_IP_NF_TARGET_REDIRECT=m
 CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_SAME=m
-CONFIG_IP_NF_NAT_SNMP_BASIC=m
-CONFIG_IP_NF_NAT_IRC=m
-CONFIG_IP_NF_NAT_FTP=m
-CONFIG_IP_NF_NAT_TFTP=m
-CONFIG_IP_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_SNMP_BASIC=m
+CONFIG_NF_NAT_PROTO_GRE=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+CONFIG_NF_NAT_TFTP=m
+CONFIG_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+CONFIG_NF_NAT_SIP=m
 CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_TOS=m
 CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_DSCP=m
-CONFIG_IP_NF_TARGET_MARK=m
-CONFIG_IP_NF_TARGET_CLASSIFY=m
-CONFIG_IP_NF_TARGET_CONNMARK=m
-# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
 CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_TARGET_NOTRACK=m
 CONFIG_IP_NF_ARPTABLES=m
 CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
 
 #
-# IPv6: Netfilter Configuration (EXPERIMENTAL)
+# IPv6: Netfilter Configuration
 #
+CONFIG_NF_CONNTRACK_IPV6=m
 CONFIG_IP6_NF_QUEUE=m
 CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_MATCH_LIMIT=m
-CONFIG_IP6_NF_MATCH_MAC=m
 CONFIG_IP6_NF_MATCH_RT=m
 CONFIG_IP6_NF_MATCH_OPTS=m
 CONFIG_IP6_NF_MATCH_FRAG=m
 CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_MULTIPORT=m
-CONFIG_IP6_NF_MATCH_OWNER=m
-CONFIG_IP6_NF_MATCH_MARK=m
 CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_MATCH_AHESP=m
-CONFIG_IP6_NF_MATCH_LENGTH=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_MH=m
 CONFIG_IP6_NF_MATCH_EUI64=m
 CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_TARGET_MARK=m
+CONFIG_IP6_NF_TARGET_HL=m
 CONFIG_IP6_NF_RAW=m
-CONFIG_XFRM=y
-CONFIG_XFRM_USER=m
+CONFIG_IP_DCCP=m
+CONFIG_INET_DCCP_DIAG=m
+CONFIG_IP_DCCP_ACKVEC=y
 
 #
-# SCTP Configuration (EXPERIMENTAL)
+# DCCP CCIDs Configuration (EXPERIMENTAL)
 #
+CONFIG_IP_DCCP_CCID2=m
+# CONFIG_IP_DCCP_CCID2_DEBUG is not set
+CONFIG_IP_DCCP_CCID3=m
+# CONFIG_IP_DCCP_CCID3_DEBUG is not set
+CONFIG_IP_DCCP_CCID3_RTO=100
+CONFIG_IP_DCCP_TFRC_LIB=m
 CONFIG_IP_SCTP=m
 # CONFIG_SCTP_DBG_MSG is not set
 # CONFIG_SCTP_DBG_OBJCNT is not set
 # CONFIG_SCTP_HMAC_NONE is not set
 # CONFIG_SCTP_HMAC_SHA1 is not set
 CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 CONFIG_LLC=m
 # CONFIG_LLC2 is not set
-CONFIG_IPX=m
-# CONFIG_IPX_INTERN is not set
+# CONFIG_IPX is not set
 CONFIG_ATALK=m
 # CONFIG_DEV_APPLETALK is not set
 # CONFIG_X25 is not set
 # CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 CONFIG_NET_CLS_ROUTE=y
 
@@ -421,46 +389,189 @@ CONFIG_NET_CLS_ROUTE=y
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
-CONFIG_NETPOLL=y
-# CONFIG_NETPOLL_RX is not set
-# CONFIG_NETPOLL_TRAP is not set
-CONFIG_NET_POLL_CONTROLLER=y
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=m
-# CONFIG_BONDING is not set
-CONFIG_EQUALIZER=m
-# CONFIG_TUN is not set
+# CONFIG_AF_RXRPC is not set
 
 #
-# Ethernet (10 or 100Mbit)
+# Wireless
 #
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=m
-CONFIG_ATARILANCE=m
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=m
+CONFIG_IEEE80211_CRYPT_CCMP=m
+CONFIG_IEEE80211_CRYPT_TKIP=m
+CONFIG_IEEE80211_SOFTMAC=m
+# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=m
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=m
+# CONFIG_MTD is not set
+CONFIG_PARPORT=m
+CONFIG_PARPORT_ATARI=m
+# CONFIG_PARPORT_GSC is not set
+# CONFIG_PARPORT_AX88796 is not set
+CONFIG_PARPORT_1284=y
+CONFIG_PARPORT_NOT_PC=y
+CONFIG_BLK_DEV=y
+CONFIG_ATARI_FLOPPY=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+CONFIG_ATA_OVER_ETH=m
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+CONFIG_BLK_DEV_IDECD=y
+CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
+# CONFIG_BLK_DEV_IDETAPE is not set
+CONFIG_BLK_DEV_IDEFLOPPY=m
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
 
 #
-# Ethernet (1000 Mbit)
+# IDE chipset support/bugfixes
 #
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
+CONFIG_BLK_DEV_FALCON_IDE=y
+# CONFIG_BLK_DEV_IDEDMA is not set
+# CONFIG_IDE_ARCH_OBSOLETE_INIT is not set
+# CONFIG_BLK_DEV_HD is not set
 
 #
-# Ethernet (10000 Mbit)
+# SCSI device support
 #
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=m
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
 
 #
-# Token Ring devices
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_ST=m
+CONFIG_CHR_DEV_OSST=m
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_DEV_SR_VENDOR=y
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
 #
+# CONFIG_SCSI_MULTI_LUN is not set
+CONFIG_SCSI_CONSTANTS=y
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
 
 #
-# Wireless LAN (non-hamradio)
+# SCSI Transports
 #
-# CONFIG_NET_RADIO is not set
+CONFIG_SCSI_SPI_ATTRS=y
+# CONFIG_SCSI_FC_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=m
+CONFIG_SCSI_SAS_ATTRS=m
+CONFIG_SCSI_SAS_LIBSAS=m
+CONFIG_SCSI_SAS_HOST_SMP=y
+# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
+CONFIG_SCSI_SRP_ATTRS=m
+CONFIG_SCSI_SRP_TGT_ATTRS=y
+CONFIG_SCSI_LOWLEVEL=y
+CONFIG_ISCSI_TCP=m
+# CONFIG_SCSI_DEBUG is not set
+CONFIG_ATARI_SCSI=y
+# CONFIG_ATARI_SCSI_TOSHIBA_DELAY is not set
+# CONFIG_ATARI_SCSI_RESET_BOOT is not set
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+# CONFIG_MD_RAID10 is not set
+CONFIG_MD_RAID456=m
+CONFIG_MD_RAID5_RESHAPE=y
+CONFIG_MD_MULTIPATH=m
+# CONFIG_MD_FAULTY is not set
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_ZERO=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_MULTIPATH_EMC=m
+CONFIG_DM_MULTIPATH_RDAC=m
+CONFIG_DM_MULTIPATH_HP=m
+# CONFIG_DM_DELAY is not set
+CONFIG_DM_UEVENT=y
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+CONFIG_DUMMY=m
+# CONFIG_BONDING is not set
+CONFIG_MACVLAN=m
+CONFIG_EQUALIZER=m
+# CONFIG_TUN is not set
+CONFIG_VETH=m
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=m
+CONFIG_ATARILANCE=m
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NET_POCKET is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
 
 #
-# Wan interfaces
+# Wireless LAN
 #
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 # CONFIG_WAN is not set
 # CONFIG_PLIP is not set
 CONFIG_PPP=m
@@ -470,28 +581,28 @@ CONFIG_PPP_ASYNC=m
 CONFIG_PPP_SYNC_TTY=m
 CONFIG_PPP_DEFLATE=m
 CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
 CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
 CONFIG_SLIP=m
 CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLHC=m
 CONFIG_SLIP_SMART=y
 CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_SHAPER=m
 CONFIG_NETCONSOLE=m
-
-#
-# ISDN subsystem
-#
+CONFIG_NETCONSOLE_DYNAMIC=y
+CONFIG_NETPOLL=y
+# CONFIG_NETPOLL_TRAP is not set
+CONFIG_NET_POLL_CONTROLLER=y
 # CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
 # CONFIG_PHONE is not set
 
 #
 # Input device support
 #
 CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=m
+# CONFIG_INPUT_POLLDEV is not set
 
 #
 # Userland interfaces
@@ -501,7 +612,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 
@@ -509,26 +619,37 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # Input Device Drivers
 #
 CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_ATKBD is not set
 # CONFIG_KEYBOARD_SUNKBD is not set
 # CONFIG_KEYBOARD_LKKBD is not set
 # CONFIG_KEYBOARD_XTKBD is not set
 # CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_ATARI_KBD_CORE=y
+CONFIG_KEYBOARD_ATARI=y
 CONFIG_INPUT_MOUSE=y
 CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
 # CONFIG_MOUSE_SERIAL is not set
+CONFIG_MOUSE_ATARI=m
 # CONFIG_MOUSE_VSXXXAA is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_M68K_BEEP=m
-CONFIG_INPUT_UINPUT=m
+# CONFIG_INPUT_UINPUT is not set
 
 #
 # Hardware I/O ports
 #
 CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_SERPORT is not set
 # CONFIG_SERIO_PARKBD is not set
 CONFIG_SERIO_LIBPS2=y
 # CONFIG_SERIO_RAW is not set
@@ -540,6 +661,7 @@ CONFIG_SERIO_LIBPS2=y
 CONFIG_VT=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -556,86 +678,97 @@ CONFIG_LEGACY_PTY_COUNT=256
 CONFIG_PRINTER=m
 # CONFIG_LP_CONSOLE is not set
 # CONFIG_PPDEV is not set
-# CONFIG_TIPAR is not set
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
+# CONFIG_HW_RANDOM is not set
 CONFIG_NVRAM=y
-CONFIG_GEN_RTC=y
+CONFIG_GEN_RTC=m
 CONFIG_GEN_RTC_X=y
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
-
-#
-# Ftape, the floppy tape device driver
-#
-# CONFIG_DRM is not set
 # CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
-
-#
-# I2C support
-#
+# CONFIG_TCG_TPM is not set
 # CONFIG_I2C is not set
 
 #
-# Dallas's 1-wire bus
+# SPI support
 #
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
 # CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
 
 #
-# Misc devices
+# Sonics Silicon Backplane
 #
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
-# Multimedia devices
+# Multifunction device drivers
 #
-# CONFIG_VIDEO_DEV is not set
+# CONFIG_MFD_SM501 is not set
 
 #
-# Digital Video Broadcasting Devices
+# Multimedia devices
 #
-# CONFIG_DVB is not set
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
 
 #
 # Graphics support
 #
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 CONFIG_FB=y
-# CONFIG_FB_CFB_FILLRECT is not set
-# CONFIG_FB_CFB_COPYAREA is not set
-# CONFIG_FB_CFB_IMAGEBLIT is not set
-# CONFIG_FB_SOFT_CURSOR is not set
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
-CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
 # CONFIG_FB_TILEBLITTING is not set
-# CONFIG_FB_ATY is not set
+
+#
+# Frame buffer hardware drivers
+#
+CONFIG_FB_ATARI=y
+# CONFIG_FB_UVESA is not set
 # CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_ATY is not set
 # CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
 #
 CONFIG_DUMMY_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
 # CONFIG_FONTS is not set
 CONFIG_FONT_8x8=y
 CONFIG_FONT_8x16=y
-
-#
-# Logo configuration
-#
-# CONFIG_LOGO is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
 
 #
 # Sound
@@ -643,27 +776,21 @@ CONFIG_FONT_8x16=y
 CONFIG_SOUND=m
 CONFIG_DMASOUND_ATARI=m
 CONFIG_DMASOUND=m
-
-#
-# USB support
-#
-# CONFIG_USB_ARCH_HAS_HCD is not set
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=m
+# CONFIG_HID_DEBUG is not set
+CONFIG_HIDRAW=y
+# CONFIG_USB_SUPPORT is not set
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_RTC_CLASS is not set
+# CONFIG_AUXDISPLAY is not set
 
 #
-# InfiniBand support
+# Userspace I/O
 #
-# CONFIG_INFINIBAND is not set
+# CONFIG_UIO is not set
 
 #
 # Character devices
@@ -680,38 +807,44 @@ CONFIG_ATARI_DSP56K=m
 #
 CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4DEV_FS is not set
 CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
 CONFIG_REISERFS_FS=m
 # CONFIG_REISERFS_CHECK is not set
-CONFIG_REISERFS_PROC_INFO=y
+# CONFIG_REISERFS_PROC_INFO is not set
 # CONFIG_REISERFS_FS_XATTR is not set
 CONFIG_JFS_FS=m
 # CONFIG_JFS_POSIX_ACL is not set
 # CONFIG_JFS_SECURITY is not set
 # CONFIG_JFS_DEBUG is not set
 # CONFIG_JFS_STATISTICS is not set
-
-#
-# XFS support
-#
+CONFIG_FS_POSIX_ACL=y
 CONFIG_XFS_FS=m
-CONFIG_XFS_EXPORT=y
-# CONFIG_XFS_RT is not set
 # CONFIG_XFS_QUOTA is not set
 # CONFIG_XFS_SECURITY is not set
 # CONFIG_XFS_POSIX_ACL is not set
-CONFIG_MINIX_FS=y
-# CONFIG_ROMFS_FS is not set
+# CONFIG_XFS_RT is not set
+CONFIG_GFS2_FS=m
+CONFIG_GFS2_FS_LOCKING_NOLOCK=m
+CONFIG_GFS2_FS_LOCKING_DLM=m
+CONFIG_OCFS2_FS=m
+# CONFIG_OCFS2_DEBUG_MASKLOG is not set
+# CONFIG_OCFS2_DEBUG_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
 CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
 # CONFIG_QFMT_V1 is not set
 # CONFIG_QFMT_V2 is not set
 CONFIG_QUOTACTL=y
-CONFIG_DNOTIFY=y
 CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
+CONFIG_FUSE_FS=m
 
 #
 # CD-ROM/DVD Filesystems
@@ -719,7 +852,6 @@ CONFIG_AUTOFS4_FS=m
 CONFIG_ISO9660_FS=y
 CONFIG_JOLIET=y
 CONFIG_ZISOFS=y
-CONFIG_ZISOFS_FS=y
 CONFIG_UDF_FS=m
 CONFIG_UDF_NLS=y
 
@@ -738,13 +870,12 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 #
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
 CONFIG_SYSFS=y
-# CONFIG_DEVFS_FS is not set
-# CONFIG_DEVPTS_FS_XATTR is not set
 CONFIG_TMPFS=y
-# CONFIG_TMPFS_XATTR is not set
+# CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
+CONFIG_CONFIGFS_FS=m
 
 #
 # Miscellaneous filesystems
@@ -758,42 +889,38 @@ CONFIG_HFSPLUS_FS=m
 # CONFIG_EFS_FS is not set
 CONFIG_CRAMFS=m
 # CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=y
 CONFIG_HPFS_FS=m
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 CONFIG_SYSV_FS=m
 CONFIG_UFS_FS=m
 # CONFIG_UFS_FS_WRITE is not set
-
-#
-# Network File Systems
-#
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
 # CONFIG_NFS_DIRECTIO is not set
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
 # CONFIG_NFSD_V4 is not set
 CONFIG_NFSD_TCP=y
 CONFIG_LOCKD=m
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=m
+CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=m
+CONFIG_SUNRPC_BIND34=y
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
 CONFIG_SMB_NLS_DEFAULT=y
 CONFIG_SMB_NLS_REMOTE="cp437"
 # CONFIG_CIFS is not set
-CONFIG_NCP_FS=m
-# CONFIG_NCPFS_PACKET_SIGNING is not set
-# CONFIG_NCPFS_IOCTL_LOCKING is not set
-# CONFIG_NCPFS_STRONG is not set
-CONFIG_NCPFS_NFS_NS=y
-CONFIG_NCPFS_OS2_NS=y
-# CONFIG_NCPFS_SMALLDOS is not set
-CONFIG_NCPFS_NLS=y
-# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_NCP_FS is not set
 CONFIG_CODA_FS=m
 # CONFIG_CODA_FS_OLD_API is not set
 # CONFIG_AFS_FS is not set
@@ -804,10 +931,6 @@ CONFIG_CODA_FS=m
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_ATARI_PARTITION=y
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=y
@@ -848,35 +971,42 @@ CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
 CONFIG_NLS_UTF8=m
+CONFIG_DLM=m
+# CONFIG_DLM_DEBUG is not set
 
 #
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
-CONFIG_DEBUG_KERNEL=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_MAGIC_SYSRQ=y
-CONFIG_LOG_BUF_SHIFT=16
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_INFO is not set
+# CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
-# CONFIG_FRAME_POINTER is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_SAMPLES is not set
 
 #
 # Security options
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_XOR_BLOCKS=m
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_XOR=m
 CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_SEQIV=m
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
 CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=m
 CONFIG_CRYPTO_NULL=m
 CONFIG_CRYPTO_MD4=m
 CONFIG_CRYPTO_MD5=m
@@ -885,9 +1015,21 @@ CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
 CONFIG_CRYPTO_WP512=m
 CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_XTS=m
+CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_CRYPTD=m
 CONFIG_CRYPTO_DES=m
+CONFIG_CRYPTO_FCRYPT=m
 CONFIG_CRYPTO_BLOWFISH=m
 CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
 CONFIG_CRYPTO_SERPENT=m
 CONFIG_CRYPTO_AES=m
 CONFIG_CRYPTO_CAST5=m
@@ -896,20 +1038,35 @@ CONFIG_CRYPTO_TEA=m
 CONFIG_CRYPTO_ARC4=m
 CONFIG_CRYPTO_KHAZAD=m
 CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SALSA20=m
 CONFIG_CRYPTO_DEFLATE=m
 CONFIG_CRYPTO_MICHAEL_MIC=m
 CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_CAMELLIA=m
 CONFIG_CRYPTO_TEST=m
-
-#
-# Hardware crypto devices
-#
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_LZO=m
+# CONFIG_CRYPTO_HW is not set
 
 #
 # Library routines
 #
+CONFIG_BITREVERSE=y
 CONFIG_CRC_CCITT=m
+CONFIG_CRC16=y
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 CONFIG_LIBCRC32C=m
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=m
+CONFIG_LZO_COMPRESS=m
+CONFIG_LZO_DECOMPRESS=m
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_DMA=y
diff --git a/arch/m68k/configs/bvme6000_defconfig b/arch/m68k/configs/bvme6000_defconfig
index da2a23a21463..ed98eff708c4 100644
--- a/arch/m68k/configs/bvme6000_defconfig
+++ b/arch/m68k/configs/bvme6000_defconfig
@@ -1,63 +1,111 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc6-m68k
-# Tue Jun  7 20:34:37 2005
+# Linux kernel version: 2.6.25-rc8
+# Wed Apr  2 20:46:10 2008
 #
 CONFIG_M68K=y
 CONFIG_MMU=y
-CONFIG_UID16=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_TIME_LOW_RES=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_NO_IOPORT=y
+# CONFIG_NO_DMA is not set
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_HZ=100
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
-CONFIG_CLEAN_COMPILE=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION="-bvme6000"
+CONFIG_LOCALVERSION_AUTO=y
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_BSD_PROCESS_ACCT=y
 # CONFIG_BSD_PROCESS_ACCT_V3 is not set
-CONFIG_SYSCTL=y
-CONFIG_AUDIT=y
-CONFIG_HOTPLUG=y
-CONFIG_KOBJECT_UEVENT=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_COMPAT_BRK is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+# CONFIG_HAVE_OPROFILE is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_OBSOLETE_MODPARM=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+CONFIG_BLK_DEV_BSG=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
 
 #
 # Platform dependent setup
@@ -85,6 +133,22 @@ CONFIG_M68060=y
 CONFIG_MMU_MOTOROLA=y
 # CONFIG_M68KFPU_EMU is not set
 # CONFIG_ADVANCED is not set
+CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
+CONFIG_NODES_SHIFT=3
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_FLATMEM_MANUAL is not set
+CONFIG_DISCONTIGMEM_MANUAL=y
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_DISCONTIGMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_NEED_MULTIPLE_NODES=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
 
 #
 # General setup
@@ -93,134 +157,11 @@ CONFIG_BINFMT_ELF=y
 CONFIG_BINFMT_AOUT=m
 CONFIG_BINFMT_MISC=m
 CONFIG_PROC_HARDWARE=y
+CONFIG_ZONE_DMA=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 
 #
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
-# CONFIG_DEBUG_DRIVER is not set
-
-#
-# Memory Technology Devices (MTD)
-#
-# CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_CDROM_PKTCDVD_BUFFERS=8
-# CONFIG_CDROM_PKTCDVD_WCACHE is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_ATA_OVER_ETH=m
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-CONFIG_SCSI=y
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=m
-# CONFIG_CHR_DEV_OSST is not set
-CONFIG_BLK_DEV_SR=y
-CONFIG_BLK_DEV_SR_VENDOR=y
-CONFIG_CHR_DEV_SG=m
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-# CONFIG_SCSI_MULTI_LUN is not set
-CONFIG_SCSI_CONSTANTS=y
-# CONFIG_SCSI_LOGGING is not set
-
-#
-# SCSI Transport Attributes
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-
-#
-# SCSI low-level drivers
-#
-# CONFIG_SCSI_SATA is not set
-# CONFIG_SCSI_DEBUG is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-# CONFIG_MD_RAID10 is not set
-CONFIG_MD_RAID5=m
-CONFIG_MD_RAID6=m
-CONFIG_MD_MULTIPATH=m
-# CONFIG_MD_FAULTY is not set
-CONFIG_BLK_DEV_DM=m
-CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
-CONFIG_DM_MIRROR=m
-CONFIG_DM_ZERO=m
-CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_EMC=m
-
-#
-# Fusion MPT device support
-#
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Networking support
+# Networking
 #
 CONFIG_NET=y
 
@@ -230,10 +171,17 @@ CONFIG_NET=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+CONFIG_XFRM_MIGRATE=y
+# CONFIG_XFRM_STATISTICS is not set
 CONFIG_NET_KEY=y
+CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
 # CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
@@ -245,126 +193,186 @@ CONFIG_SYN_COOKIES=y
 CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
 CONFIG_INET_TUNNEL=m
-CONFIG_IP_TCPDIAG=m
-CONFIG_IP_TCPDIAG_IPV6=y
-
-#
-# IP: Virtual Server Configuration
-#
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_INET_LRO=m
+CONFIG_INET_DIAG=m
+CONFIG_INET_TCP_DIAG=m
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
 # CONFIG_IP_VS is not set
 CONFIG_IPV6=m
 CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
 CONFIG_INET6_AH=m
 CONFIG_INET6_ESP=m
 CONFIG_INET6_IPCOMP=m
+# CONFIG_IPV6_MIP6 is not set
+CONFIG_INET6_XFRM_TUNNEL=m
 CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
+CONFIG_IPV6_SIT=m
 CONFIG_IPV6_TUNNEL=m
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_NETWORK_SECMARK is not set
 CONFIG_NETFILTER=y
 # CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+CONFIG_NF_CT_PROTO_GRE=m
+CONFIG_NF_CT_PROTO_SCTP=m
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+# CONFIG_NF_CT_NETLINK is not set
+CONFIG_NETFILTER_XTABLES=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_RATEEST=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
 
 #
 # IP: Netfilter Configuration
 #
-CONFIG_IP_NF_CONNTRACK=m
-# CONFIG_IP_NF_CT_ACCT is not set
-CONFIG_IP_NF_CONNTRACK_MARK=y
-# CONFIG_IP_NF_CT_PROTO_SCTP is not set
-CONFIG_IP_NF_FTP=m
-CONFIG_IP_NF_IRC=m
-CONFIG_IP_NF_TFTP=m
-CONFIG_IP_NF_AMANDA=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
 CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_LIMIT=m
-CONFIG_IP_NF_MATCH_IPRANGE=m
-CONFIG_IP_NF_MATCH_MAC=m
-CONFIG_IP_NF_MATCH_PKTTYPE=m
-CONFIG_IP_NF_MATCH_MARK=m
-CONFIG_IP_NF_MATCH_MULTIPORT=m
-CONFIG_IP_NF_MATCH_TOS=m
 CONFIG_IP_NF_MATCH_RECENT=m
 CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_DSCP=m
-CONFIG_IP_NF_MATCH_AH_ESP=m
-CONFIG_IP_NF_MATCH_LENGTH=m
+CONFIG_IP_NF_MATCH_AH=m
 CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_MATCH_TCPMSS=m
-CONFIG_IP_NF_MATCH_HELPER=m
-CONFIG_IP_NF_MATCH_STATE=m
-CONFIG_IP_NF_MATCH_CONNTRACK=m
-CONFIG_IP_NF_MATCH_OWNER=m
 CONFIG_IP_NF_MATCH_ADDRTYPE=m
-CONFIG_IP_NF_MATCH_REALM=m
-# CONFIG_IP_NF_MATCH_SCTP is not set
-# CONFIG_IP_NF_MATCH_COMMENT is not set
-CONFIG_IP_NF_MATCH_CONNMARK=m
-CONFIG_IP_NF_MATCH_HASHLIMIT=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
 CONFIG_IP_NF_TARGET_LOG=m
 CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_IP_NF_TARGET_TCPMSS=m
-CONFIG_IP_NF_NAT=m
-CONFIG_IP_NF_NAT_NEEDED=y
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
 CONFIG_IP_NF_TARGET_MASQUERADE=m
 CONFIG_IP_NF_TARGET_REDIRECT=m
 CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_SAME=m
-CONFIG_IP_NF_NAT_SNMP_BASIC=m
-CONFIG_IP_NF_NAT_IRC=m
-CONFIG_IP_NF_NAT_FTP=m
-CONFIG_IP_NF_NAT_TFTP=m
-CONFIG_IP_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_SNMP_BASIC=m
+CONFIG_NF_NAT_PROTO_GRE=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+CONFIG_NF_NAT_TFTP=m
+CONFIG_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+CONFIG_NF_NAT_SIP=m
 CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_TOS=m
 CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_DSCP=m
-CONFIG_IP_NF_TARGET_MARK=m
-CONFIG_IP_NF_TARGET_CLASSIFY=m
-CONFIG_IP_NF_TARGET_CONNMARK=m
-# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
 CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_TARGET_NOTRACK=m
 CONFIG_IP_NF_ARPTABLES=m
 CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
 
 #
-# IPv6: Netfilter Configuration (EXPERIMENTAL)
+# IPv6: Netfilter Configuration
 #
+CONFIG_NF_CONNTRACK_IPV6=m
 CONFIG_IP6_NF_QUEUE=m
 CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_MATCH_LIMIT=m
-CONFIG_IP6_NF_MATCH_MAC=m
 CONFIG_IP6_NF_MATCH_RT=m
 CONFIG_IP6_NF_MATCH_OPTS=m
 CONFIG_IP6_NF_MATCH_FRAG=m
 CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_MULTIPORT=m
-CONFIG_IP6_NF_MATCH_OWNER=m
-CONFIG_IP6_NF_MATCH_MARK=m
 CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_MATCH_AHESP=m
-CONFIG_IP6_NF_MATCH_LENGTH=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_MH=m
 CONFIG_IP6_NF_MATCH_EUI64=m
 CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_TARGET_MARK=m
+CONFIG_IP6_NF_TARGET_HL=m
 CONFIG_IP6_NF_RAW=m
-CONFIG_XFRM=y
-CONFIG_XFRM_USER=m
+CONFIG_IP_DCCP=m
+CONFIG_INET_DCCP_DIAG=m
+CONFIG_IP_DCCP_ACKVEC=y
 
 #
-# SCTP Configuration (EXPERIMENTAL)
+# DCCP CCIDs Configuration (EXPERIMENTAL)
 #
+CONFIG_IP_DCCP_CCID2=m
+# CONFIG_IP_DCCP_CCID2_DEBUG is not set
+CONFIG_IP_DCCP_CCID3=m
+# CONFIG_IP_DCCP_CCID3_DEBUG is not set
+CONFIG_IP_DCCP_CCID3_RTO=100
+CONFIG_IP_DCCP_TFRC_LIB=m
 CONFIG_IP_SCTP=m
 # CONFIG_SCTP_DBG_MSG is not set
 # CONFIG_SCTP_DBG_OBJCNT is not set
 # CONFIG_SCTP_HMAC_NONE is not set
 # CONFIG_SCTP_HMAC_SHA1 is not set
 CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
 # CONFIG_VLAN_8021Q is not set
@@ -376,13 +384,8 @@ CONFIG_ATALK=m
 # CONFIG_DEV_APPLETALK is not set
 # CONFIG_X25 is not set
 # CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 CONFIG_NET_CLS_ROUTE=y
 
@@ -390,76 +393,186 @@ CONFIG_NET_CLS_ROUTE=y
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
-CONFIG_NETPOLL=y
-# CONFIG_NETPOLL_RX is not set
-# CONFIG_NETPOLL_TRAP is not set
-CONFIG_NET_POLL_CONTROLLER=y
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=m
-# CONFIG_BONDING is not set
-CONFIG_EQUALIZER=m
-# CONFIG_TUN is not set
+# CONFIG_AF_RXRPC is not set
 
 #
-# Ethernet (10 or 100Mbit)
+# Wireless
 #
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=m
-CONFIG_BVME6000_NET=y
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=m
+CONFIG_IEEE80211_CRYPT_CCMP=m
+CONFIG_IEEE80211_CRYPT_TKIP=m
+CONFIG_IEEE80211_SOFTMAC=m
+# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
-# Ethernet (1000 Mbit)
+# Device Drivers
 #
 
 #
-# Ethernet (10000 Mbit)
+# Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=m
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=m
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+CONFIG_ATA_OVER_ETH=m
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
 
 #
-# Token Ring devices
+# SCSI device support
 #
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=m
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
 
 #
-# Wireless LAN (non-hamradio)
+# SCSI support type (disk, tape, CD-ROM)
 #
-# CONFIG_NET_RADIO is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_ST=m
+CONFIG_CHR_DEV_OSST=m
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_DEV_SR_VENDOR=y
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+CONFIG_SCSI_CONSTANTS=y
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+CONFIG_SCSI_SPI_ATTRS=y
+# CONFIG_SCSI_FC_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=m
+CONFIG_SCSI_SAS_ATTRS=m
+CONFIG_SCSI_SAS_LIBSAS=m
+CONFIG_SCSI_SAS_HOST_SMP=y
+# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
+CONFIG_SCSI_SRP_ATTRS=m
+CONFIG_SCSI_SRP_TGT_ATTRS=y
+CONFIG_SCSI_LOWLEVEL=y
+CONFIG_ISCSI_TCP=m
+CONFIG_53C700_BE_BUS=y
+# CONFIG_SCSI_DEBUG is not set
+CONFIG_BVME6000_SCSI=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+# CONFIG_MD_RAID10 is not set
+CONFIG_MD_RAID456=m
+CONFIG_MD_RAID5_RESHAPE=y
+CONFIG_MD_MULTIPATH=m
+# CONFIG_MD_FAULTY is not set
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_ZERO=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_MULTIPATH_EMC=m
+CONFIG_DM_MULTIPATH_RDAC=m
+CONFIG_DM_MULTIPATH_HP=m
+# CONFIG_DM_DELAY is not set
+CONFIG_DM_UEVENT=y
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+CONFIG_DUMMY=m
+# CONFIG_BONDING is not set
+CONFIG_MACVLAN=m
+CONFIG_EQUALIZER=m
+# CONFIG_TUN is not set
+CONFIG_VETH=m
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+CONFIG_BVME6000_NET=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
 
 #
-# Wan interfaces
+# Wireless LAN
 #
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 # CONFIG_WAN is not set
 CONFIG_PPP=m
 # CONFIG_PPP_MULTILINK is not set
-# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_FILTER=y
 CONFIG_PPP_ASYNC=m
 CONFIG_PPP_SYNC_TTY=m
 CONFIG_PPP_DEFLATE=m
 CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
 CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
 CONFIG_SLIP=m
 CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLHC=m
 CONFIG_SLIP_SMART=y
 CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_SHAPER=m
 CONFIG_NETCONSOLE=m
-
-#
-# ISDN subsystem
-#
+CONFIG_NETCONSOLE_DYNAMIC=y
+CONFIG_NETPOLL=y
+# CONFIG_NETPOLL_TRAP is not set
+CONFIG_NET_POLL_CONTROLLER=y
 # CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
 # CONFIG_PHONE is not set
 
 #
 # Input device support
 #
 CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=m
+# CONFIG_INPUT_POLLDEV is not set
 
 #
 # Userland interfaces
@@ -469,7 +582,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 
@@ -482,11 +594,19 @@ CONFIG_INPUT_KEYBOARD=y
 # CONFIG_KEYBOARD_LKKBD is not set
 # CONFIG_KEYBOARD_XTKBD is not set
 # CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
 CONFIG_INPUT_MOUSE=y
 CONFIG_MOUSE_PS2=m
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
 CONFIG_MOUSE_SERIAL=m
 # CONFIG_MOUSE_VSXXXAA is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 
@@ -494,7 +614,7 @@ CONFIG_MOUSE_SERIAL=m
 # Hardware I/O ports
 #
 CONFIG_SERIO=m
-CONFIG_SERIO_SERPORT=m
+# CONFIG_SERIO_SERPORT is not set
 CONFIG_SERIO_LIBPS2=m
 # CONFIG_SERIO_RAW is not set
 # CONFIG_GAMEPORT is not set
@@ -505,6 +625,7 @@ CONFIG_SERIO_LIBPS2=m
 CONFIG_VT=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -518,59 +639,56 @@ CONFIG_HW_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
+# CONFIG_HW_RANDOM is not set
 CONFIG_GEN_RTC=m
 CONFIG_GEN_RTC_X=y
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
-
-#
-# Ftape, the floppy tape device driver
-#
-# CONFIG_DRM is not set
 # CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
 
 #
-# TPM devices
-#
-
-#
-# I2C support
+# SPI support
 #
-# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
 
 #
-# Dallas's 1-wire bus
+# Sonics Silicon Backplane
 #
-# CONFIG_W1 is not set
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
-# Misc devices
+# Multifunction device drivers
 #
+# CONFIG_MFD_SM501 is not set
 
 #
 # Multimedia devices
 #
 # CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
 
 #
-# Digital Video Broadcasting Devices
+# Graphics support
 #
-# CONFIG_DVB is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
-# Graphics support
+# Display device support
 #
-# CONFIG_FB is not set
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
@@ -581,27 +699,20 @@ CONFIG_DUMMY_CONSOLE=y
 # Sound
 #
 # CONFIG_SOUND is not set
-
-#
-# USB support
-#
-# CONFIG_USB_ARCH_HAS_HCD is not set
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=m
+# CONFIG_HID_DEBUG is not set
+CONFIG_HIDRAW=y
+# CONFIG_USB_SUPPORT is not set
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_RTC_CLASS is not set
 
 #
-# InfiniBand support
+# Userspace I/O
 #
-# CONFIG_INFINIBAND is not set
+# CONFIG_UIO is not set
 
 #
 # Character devices
@@ -614,10 +725,11 @@ CONFIG_SERIAL_CONSOLE=y
 #
 CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4DEV_FS is not set
 CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
 CONFIG_REISERFS_FS=m
 # CONFIG_REISERFS_CHECK is not set
 # CONFIG_REISERFS_PROC_INFO is not set
@@ -628,25 +740,29 @@ CONFIG_JFS_FS=m
 # CONFIG_JFS_DEBUG is not set
 # CONFIG_JFS_STATISTICS is not set
 CONFIG_FS_POSIX_ACL=y
-
-#
-# XFS support
-#
 CONFIG_XFS_FS=m
-CONFIG_XFS_EXPORT=y
-# CONFIG_XFS_RT is not set
 # CONFIG_XFS_QUOTA is not set
 # CONFIG_XFS_SECURITY is not set
 # CONFIG_XFS_POSIX_ACL is not set
-CONFIG_MINIX_FS=y
-# CONFIG_ROMFS_FS is not set
+# CONFIG_XFS_RT is not set
+CONFIG_GFS2_FS=m
+CONFIG_GFS2_FS_LOCKING_NOLOCK=m
+CONFIG_GFS2_FS_LOCKING_DLM=m
+CONFIG_OCFS2_FS=m
+# CONFIG_OCFS2_DEBUG_MASKLOG is not set
+# CONFIG_OCFS2_DEBUG_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
 CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
 # CONFIG_QFMT_V1 is not set
 # CONFIG_QFMT_V2 is not set
 CONFIG_QUOTACTL=y
-CONFIG_DNOTIFY=y
 CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
+CONFIG_FUSE_FS=m
 
 #
 # CD-ROM/DVD Filesystems
@@ -654,7 +770,6 @@ CONFIG_AUTOFS4_FS=m
 CONFIG_ISO9660_FS=y
 CONFIG_JOLIET=y
 CONFIG_ZISOFS=y
-CONFIG_ZISOFS_FS=y
 CONFIG_UDF_FS=m
 CONFIG_UDF_NLS=y
 
@@ -673,13 +788,12 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 #
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
 CONFIG_SYSFS=y
-# CONFIG_DEVFS_FS is not set
-# CONFIG_DEVPTS_FS_XATTR is not set
 CONFIG_TMPFS=y
-# CONFIG_TMPFS_XATTR is not set
+# CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
+CONFIG_CONFIGFS_FS=m
 
 #
 # Miscellaneous filesystems
@@ -693,44 +807,40 @@ CONFIG_HFSPLUS_FS=m
 # CONFIG_EFS_FS is not set
 CONFIG_CRAMFS=m
 # CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=y
 CONFIG_HPFS_FS=m
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 CONFIG_SYSV_FS=m
 CONFIG_UFS_FS=m
 # CONFIG_UFS_FS_WRITE is not set
-
-#
-# Network File Systems
-#
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
 # CONFIG_NFS_DIRECTIO is not set
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
-CONFIG_NFSD_V4=y
+# CONFIG_NFSD_V3_ACL is not set
+# CONFIG_NFSD_V4 is not set
 CONFIG_NFSD_TCP=y
 CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=m
+CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
+CONFIG_SUNRPC_BIND34=y
 CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
 CONFIG_SMB_NLS_DEFAULT=y
 CONFIG_SMB_NLS_REMOTE="cp437"
 # CONFIG_CIFS is not set
-CONFIG_NCP_FS=m
-# CONFIG_NCPFS_PACKET_SIGNING is not set
-# CONFIG_NCPFS_IOCTL_LOCKING is not set
-# CONFIG_NCPFS_STRONG is not set
-CONFIG_NCPFS_NFS_NS=y
-CONFIG_NCPFS_OS2_NS=y
-# CONFIG_NCPFS_SMALLDOS is not set
-CONFIG_NCPFS_NLS=y
-# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_NCP_FS is not set
 CONFIG_CODA_FS=m
 # CONFIG_CODA_FS_OLD_API is not set
 # CONFIG_AFS_FS is not set
@@ -740,10 +850,7 @@ CONFIG_CODA_FS=m
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
+CONFIG_SYSV68_PARTITION=y
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=y
@@ -784,35 +891,42 @@ CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
 CONFIG_NLS_UTF8=m
+CONFIG_DLM=m
+# CONFIG_DLM_DEBUG is not set
 
 #
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
-CONFIG_DEBUG_KERNEL=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_MAGIC_SYSRQ=y
-CONFIG_LOG_BUF_SHIFT=16
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_INFO is not set
+# CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
-# CONFIG_FRAME_POINTER is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_SAMPLES is not set
 
 #
 # Security options
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_XOR_BLOCKS=m
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_XOR=m
 CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_SEQIV=m
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
 CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=m
 CONFIG_CRYPTO_NULL=m
 CONFIG_CRYPTO_MD4=m
 CONFIG_CRYPTO_MD5=y
@@ -821,9 +935,21 @@ CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
 CONFIG_CRYPTO_WP512=m
 CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_XTS=m
+CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_CRYPTD=m
 CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
 CONFIG_CRYPTO_BLOWFISH=m
 CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
 CONFIG_CRYPTO_SERPENT=m
 CONFIG_CRYPTO_AES=m
 CONFIG_CRYPTO_CAST5=m
@@ -832,20 +958,35 @@ CONFIG_CRYPTO_TEA=m
 CONFIG_CRYPTO_ARC4=m
 CONFIG_CRYPTO_KHAZAD=m
 CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SALSA20=m
 CONFIG_CRYPTO_DEFLATE=m
 CONFIG_CRYPTO_MICHAEL_MIC=m
 CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_CAMELLIA=m
 CONFIG_CRYPTO_TEST=m
-
-#
-# Hardware crypto devices
-#
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_LZO=m
+# CONFIG_CRYPTO_HW is not set
 
 #
 # Library routines
 #
+CONFIG_BITREVERSE=m
 CONFIG_CRC_CCITT=m
+CONFIG_CRC16=m
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=m
+# CONFIG_CRC7 is not set
 CONFIG_LIBCRC32C=m
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=m
+CONFIG_LZO_COMPRESS=m
+CONFIG_LZO_DECOMPRESS=m
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_DMA=y
diff --git a/arch/m68k/configs/hp300_defconfig b/arch/m68k/configs/hp300_defconfig
index 51251883adf8..38b68c70e567 100644
--- a/arch/m68k/configs/hp300_defconfig
+++ b/arch/m68k/configs/hp300_defconfig
@@ -1,63 +1,111 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc6-m68k
-# Tue Jun  7 20:34:41 2005
+# Linux kernel version: 2.6.25-rc8
+# Wed Apr  2 20:46:12 2008
 #
 CONFIG_M68K=y
 CONFIG_MMU=y
-CONFIG_UID16=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_TIME_LOW_RES=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_NO_IOPORT=y
+# CONFIG_NO_DMA is not set
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_HZ=100
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
-CONFIG_CLEAN_COMPILE=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION="-hp300"
+CONFIG_LOCALVERSION_AUTO=y
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_BSD_PROCESS_ACCT=y
 # CONFIG_BSD_PROCESS_ACCT_V3 is not set
-CONFIG_SYSCTL=y
-CONFIG_AUDIT=y
-CONFIG_HOTPLUG=y
-CONFIG_KOBJECT_UEVENT=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_COMPAT_BRK is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+# CONFIG_HAVE_OPROFILE is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_OBSOLETE_MODPARM=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+CONFIG_BLK_DEV_BSG=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
 
 #
 # Platform dependent setup
@@ -81,10 +129,24 @@ CONFIG_M68030=y
 CONFIG_M68040=y
 CONFIG_M68060=y
 CONFIG_MMU_MOTOROLA=y
-CONFIG_M68KFPU_EMU=y
-CONFIG_M68KFPU_EMU_EXTRAPREC=y
-# CONFIG_M68KFPU_EMU_ONLY is not set
+# CONFIG_M68KFPU_EMU is not set
 # CONFIG_ADVANCED is not set
+CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
+CONFIG_NODES_SHIFT=3
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_FLATMEM_MANUAL is not set
+CONFIG_DISCONTIGMEM_MANUAL=y
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_DISCONTIGMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_NEED_MULTIPLE_NODES=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
 
 #
 # General setup
@@ -94,134 +156,11 @@ CONFIG_BINFMT_AOUT=m
 CONFIG_BINFMT_MISC=m
 CONFIG_HEARTBEAT=y
 CONFIG_PROC_HARDWARE=y
+CONFIG_ZONE_DMA=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 
 #
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
-# CONFIG_DEBUG_DRIVER is not set
-
-#
-# Memory Technology Devices (MTD)
-#
-# CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_CDROM_PKTCDVD_BUFFERS=8
-# CONFIG_CDROM_PKTCDVD_WCACHE is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_ATA_OVER_ETH=m
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-CONFIG_SCSI=y
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=m
-# CONFIG_CHR_DEV_OSST is not set
-CONFIG_BLK_DEV_SR=y
-CONFIG_BLK_DEV_SR_VENDOR=y
-CONFIG_CHR_DEV_SG=m
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-# CONFIG_SCSI_MULTI_LUN is not set
-CONFIG_SCSI_CONSTANTS=y
-# CONFIG_SCSI_LOGGING is not set
-
-#
-# SCSI Transport Attributes
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-
-#
-# SCSI low-level drivers
-#
-# CONFIG_SCSI_SATA is not set
-# CONFIG_SCSI_DEBUG is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-# CONFIG_MD_RAID10 is not set
-CONFIG_MD_RAID5=m
-CONFIG_MD_RAID6=m
-CONFIG_MD_MULTIPATH=m
-# CONFIG_MD_FAULTY is not set
-CONFIG_BLK_DEV_DM=m
-CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
-CONFIG_DM_MIRROR=m
-CONFIG_DM_ZERO=m
-CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_EMC=m
-
-#
-# Fusion MPT device support
-#
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Networking support
+# Networking
 #
 CONFIG_NET=y
 
@@ -231,10 +170,17 @@ CONFIG_NET=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+CONFIG_XFRM_MIGRATE=y
+# CONFIG_XFRM_STATISTICS is not set
 CONFIG_NET_KEY=y
+CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
 # CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
@@ -246,145 +192,199 @@ CONFIG_SYN_COOKIES=y
 CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
 CONFIG_INET_TUNNEL=m
-CONFIG_IP_TCPDIAG=m
-CONFIG_IP_TCPDIAG_IPV6=y
-
-#
-# IP: Virtual Server Configuration
-#
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_INET_LRO=m
+CONFIG_INET_DIAG=m
+CONFIG_INET_TCP_DIAG=m
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
 # CONFIG_IP_VS is not set
 CONFIG_IPV6=m
 CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
 CONFIG_INET6_AH=m
 CONFIG_INET6_ESP=m
 CONFIG_INET6_IPCOMP=m
+# CONFIG_IPV6_MIP6 is not set
+CONFIG_INET6_XFRM_TUNNEL=m
 CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
+CONFIG_IPV6_SIT=m
 CONFIG_IPV6_TUNNEL=m
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_NETWORK_SECMARK is not set
 CONFIG_NETFILTER=y
 # CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+CONFIG_NF_CT_PROTO_GRE=m
+CONFIG_NF_CT_PROTO_SCTP=m
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+# CONFIG_NF_CT_NETLINK is not set
+CONFIG_NETFILTER_XTABLES=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_RATEEST=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
 
 #
 # IP: Netfilter Configuration
 #
-CONFIG_IP_NF_CONNTRACK=m
-# CONFIG_IP_NF_CT_ACCT is not set
-CONFIG_IP_NF_CONNTRACK_MARK=y
-# CONFIG_IP_NF_CT_PROTO_SCTP is not set
-CONFIG_IP_NF_FTP=m
-CONFIG_IP_NF_IRC=m
-CONFIG_IP_NF_TFTP=m
-CONFIG_IP_NF_AMANDA=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
 CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_LIMIT=m
-CONFIG_IP_NF_MATCH_IPRANGE=m
-CONFIG_IP_NF_MATCH_MAC=m
-CONFIG_IP_NF_MATCH_PKTTYPE=m
-CONFIG_IP_NF_MATCH_MARK=m
-CONFIG_IP_NF_MATCH_MULTIPORT=m
-CONFIG_IP_NF_MATCH_TOS=m
 CONFIG_IP_NF_MATCH_RECENT=m
 CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_DSCP=m
-CONFIG_IP_NF_MATCH_AH_ESP=m
-CONFIG_IP_NF_MATCH_LENGTH=m
+CONFIG_IP_NF_MATCH_AH=m
 CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_MATCH_TCPMSS=m
-CONFIG_IP_NF_MATCH_HELPER=m
-CONFIG_IP_NF_MATCH_STATE=m
-CONFIG_IP_NF_MATCH_CONNTRACK=m
-CONFIG_IP_NF_MATCH_OWNER=m
 CONFIG_IP_NF_MATCH_ADDRTYPE=m
-CONFIG_IP_NF_MATCH_REALM=m
-# CONFIG_IP_NF_MATCH_SCTP is not set
-# CONFIG_IP_NF_MATCH_COMMENT is not set
-CONFIG_IP_NF_MATCH_CONNMARK=m
-CONFIG_IP_NF_MATCH_HASHLIMIT=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
 CONFIG_IP_NF_TARGET_LOG=m
 CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_IP_NF_TARGET_TCPMSS=m
-CONFIG_IP_NF_NAT=m
-CONFIG_IP_NF_NAT_NEEDED=y
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
 CONFIG_IP_NF_TARGET_MASQUERADE=m
 CONFIG_IP_NF_TARGET_REDIRECT=m
 CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_SAME=m
-CONFIG_IP_NF_NAT_SNMP_BASIC=m
-CONFIG_IP_NF_NAT_IRC=m
-CONFIG_IP_NF_NAT_FTP=m
-CONFIG_IP_NF_NAT_TFTP=m
-CONFIG_IP_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_SNMP_BASIC=m
+CONFIG_NF_NAT_PROTO_GRE=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+CONFIG_NF_NAT_TFTP=m
+CONFIG_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+CONFIG_NF_NAT_SIP=m
 CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_TOS=m
 CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_DSCP=m
-CONFIG_IP_NF_TARGET_MARK=m
-CONFIG_IP_NF_TARGET_CLASSIFY=m
-CONFIG_IP_NF_TARGET_CONNMARK=m
-# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
 CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_TARGET_NOTRACK=m
 CONFIG_IP_NF_ARPTABLES=m
 CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
 
 #
-# IPv6: Netfilter Configuration (EXPERIMENTAL)
+# IPv6: Netfilter Configuration
 #
+CONFIG_NF_CONNTRACK_IPV6=m
 CONFIG_IP6_NF_QUEUE=m
 CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_MATCH_LIMIT=m
-CONFIG_IP6_NF_MATCH_MAC=m
 CONFIG_IP6_NF_MATCH_RT=m
 CONFIG_IP6_NF_MATCH_OPTS=m
 CONFIG_IP6_NF_MATCH_FRAG=m
 CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_MULTIPORT=m
-CONFIG_IP6_NF_MATCH_OWNER=m
-CONFIG_IP6_NF_MATCH_MARK=m
 CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_MATCH_AHESP=m
-CONFIG_IP6_NF_MATCH_LENGTH=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_MH=m
 CONFIG_IP6_NF_MATCH_EUI64=m
 CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_TARGET_MARK=m
+CONFIG_IP6_NF_TARGET_HL=m
 CONFIG_IP6_NF_RAW=m
-CONFIG_XFRM=y
-CONFIG_XFRM_USER=m
+CONFIG_IP_DCCP=m
+CONFIG_INET_DCCP_DIAG=m
+CONFIG_IP_DCCP_ACKVEC=y
 
 #
-# SCTP Configuration (EXPERIMENTAL)
+# DCCP CCIDs Configuration (EXPERIMENTAL)
 #
+CONFIG_IP_DCCP_CCID2=m
+# CONFIG_IP_DCCP_CCID2_DEBUG is not set
+CONFIG_IP_DCCP_CCID3=m
+# CONFIG_IP_DCCP_CCID3_DEBUG is not set
+CONFIG_IP_DCCP_CCID3_RTO=100
+CONFIG_IP_DCCP_TFRC_LIB=m
 CONFIG_IP_SCTP=m
 # CONFIG_SCTP_DBG_MSG is not set
 # CONFIG_SCTP_DBG_OBJCNT is not set
 # CONFIG_SCTP_HMAC_NONE is not set
 # CONFIG_SCTP_HMAC_SHA1 is not set
 CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 CONFIG_LLC=m
 # CONFIG_LLC2 is not set
-CONFIG_IPX=m
-# CONFIG_IPX_INTERN is not set
+# CONFIG_IPX is not set
 CONFIG_ATALK=m
 # CONFIG_DEV_APPLETALK is not set
 # CONFIG_X25 is not set
 # CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 CONFIG_NET_CLS_ROUTE=y
 
@@ -392,46 +392,154 @@ CONFIG_NET_CLS_ROUTE=y
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
-CONFIG_NETPOLL=y
-# CONFIG_NETPOLL_RX is not set
-# CONFIG_NETPOLL_TRAP is not set
-CONFIG_NET_POLL_CONTROLLER=y
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=m
-# CONFIG_BONDING is not set
-CONFIG_EQUALIZER=m
-# CONFIG_TUN is not set
+# CONFIG_AF_RXRPC is not set
 
 #
-# Ethernet (10 or 100Mbit)
+# Wireless
 #
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=m
-CONFIG_HPLANCE=y
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=m
+CONFIG_IEEE80211_CRYPT_CCMP=m
+CONFIG_IEEE80211_CRYPT_TKIP=m
+CONFIG_IEEE80211_SOFTMAC=m
+# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
-# Ethernet (1000 Mbit)
+# Device Drivers
 #
 
 #
-# Ethernet (10000 Mbit)
+# Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=m
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=m
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+CONFIG_ATA_OVER_ETH=m
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
 
 #
-# Token Ring devices
+# SCSI device support
 #
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=m
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
 
 #
-# Wireless LAN (non-hamradio)
+# SCSI support type (disk, tape, CD-ROM)
 #
-# CONFIG_NET_RADIO is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_ST=m
+CONFIG_CHR_DEV_OSST=m
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_DEV_SR_VENDOR=y
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+CONFIG_SCSI_CONSTANTS=y
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=m
+CONFIG_SCSI_SAS_ATTRS=m
+CONFIG_SCSI_SAS_LIBSAS=m
+CONFIG_SCSI_SAS_HOST_SMP=y
+# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
+CONFIG_SCSI_SRP_ATTRS=m
+CONFIG_SCSI_SRP_TGT_ATTRS=y
+CONFIG_SCSI_LOWLEVEL=y
+CONFIG_ISCSI_TCP=m
+# CONFIG_SCSI_DEBUG is not set
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+# CONFIG_MD_RAID10 is not set
+CONFIG_MD_RAID456=m
+CONFIG_MD_RAID5_RESHAPE=y
+CONFIG_MD_MULTIPATH=m
+# CONFIG_MD_FAULTY is not set
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_ZERO=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_MULTIPATH_EMC=m
+CONFIG_DM_MULTIPATH_RDAC=m
+CONFIG_DM_MULTIPATH_HP=m
+# CONFIG_DM_DELAY is not set
+CONFIG_DM_UEVENT=y
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+CONFIG_DUMMY=m
+# CONFIG_BONDING is not set
+CONFIG_MACVLAN=m
+CONFIG_EQUALIZER=m
+# CONFIG_TUN is not set
+CONFIG_VETH=m
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+CONFIG_HPLANCE=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
 
 #
-# Wan interfaces
+# Wireless LAN
 #
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 # CONFIG_WAN is not set
 CONFIG_PPP=m
 # CONFIG_PPP_MULTILINK is not set
@@ -440,28 +548,28 @@ CONFIG_PPP_ASYNC=m
 CONFIG_PPP_SYNC_TTY=m
 CONFIG_PPP_DEFLATE=m
 CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
 CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
 CONFIG_SLIP=m
 CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLHC=m
 CONFIG_SLIP_SMART=y
 CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_SHAPER=m
 CONFIG_NETCONSOLE=m
-
-#
-# ISDN subsystem
-#
+CONFIG_NETCONSOLE_DYNAMIC=y
+CONFIG_NETPOLL=y
+# CONFIG_NETPOLL_TRAP is not set
+CONFIG_NET_POLL_CONTROLLER=y
 # CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
 # CONFIG_PHONE is not set
 
 #
 # Input device support
 #
 CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=m
+# CONFIG_INPUT_POLLDEV is not set
 
 #
 # Userland interfaces
@@ -471,7 +579,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 
@@ -484,19 +591,35 @@ CONFIG_INPUT_KEYBOARD=y
 # CONFIG_KEYBOARD_LKKBD is not set
 # CONFIG_KEYBOARD_XTKBD is not set
 # CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_HIL_OLD=y
+CONFIG_KEYBOARD_HIL=y
 CONFIG_INPUT_MOUSE=y
 CONFIG_MOUSE_PS2=m
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
 CONFIG_MOUSE_SERIAL=m
 # CONFIG_MOUSE_VSXXXAA is not set
+CONFIG_MOUSE_HIL=m
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_M68K_BEEP is not set
+# CONFIG_INPUT_UINPUT is not set
+CONFIG_HP_SDC_RTC=m
 
 #
 # Hardware I/O ports
 #
-CONFIG_SERIO=m
-CONFIG_SERIO_SERPORT=m
+CONFIG_SERIO=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_HP_SDC=y
+CONFIG_HIL_MLC=y
 CONFIG_SERIO_LIBPS2=m
 # CONFIG_SERIO_RAW is not set
 # CONFIG_GAMEPORT is not set
@@ -507,6 +630,7 @@ CONFIG_SERIO_LIBPS2=m
 CONFIG_VT=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -520,90 +644,114 @@ CONFIG_HW_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
-CONFIG_GEN_RTC=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_GEN_RTC=m
 CONFIG_GEN_RTC_X=y
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
-
-#
-# Ftape, the floppy tape device driver
-#
-# CONFIG_DRM is not set
 # CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
 
 #
-# TPM devices
+# SPI support
 #
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
 
 #
-# I2C support
+# Sonics Silicon Backplane
 #
-# CONFIG_I2C is not set
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
-# Dallas's 1-wire bus
+# Multifunction device drivers
 #
-# CONFIG_W1 is not set
+# CONFIG_MFD_SM501 is not set
 
 #
-# Misc devices
+# Multimedia devices
 #
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
 
 #
-# Multimedia devices
+# Graphics support
 #
-# CONFIG_VIDEO_DEV is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+# CONFIG_FB_CFB_COPYAREA is not set
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
 
 #
-# Digital Video Broadcasting Devices
+# Frame buffer hardware drivers
 #
-# CONFIG_DVB is not set
+CONFIG_FB_HP300=y
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
-# Graphics support
+# Display device support
 #
-# CONFIG_FB is not set
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
 #
 CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO_LINUX_CLUT224=y
 
 #
 # Sound
 #
 # CONFIG_SOUND is not set
-
-#
-# USB support
-#
-# CONFIG_USB_ARCH_HAS_HCD is not set
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=m
+# CONFIG_HID_DEBUG is not set
+CONFIG_HIDRAW=y
+# CONFIG_USB_SUPPORT is not set
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_RTC_CLASS is not set
 
 #
-# InfiniBand support
+# Userspace I/O
 #
-# CONFIG_INFINIBAND is not set
+# CONFIG_UIO is not set
 
 #
 # Character devices
@@ -614,10 +762,11 @@ CONFIG_DUMMY_CONSOLE=y
 #
 CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4DEV_FS is not set
 CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
 CONFIG_REISERFS_FS=m
 # CONFIG_REISERFS_CHECK is not set
 # CONFIG_REISERFS_PROC_INFO is not set
@@ -628,25 +777,29 @@ CONFIG_JFS_FS=m
 # CONFIG_JFS_DEBUG is not set
 # CONFIG_JFS_STATISTICS is not set
 CONFIG_FS_POSIX_ACL=y
-
-#
-# XFS support
-#
 CONFIG_XFS_FS=m
-CONFIG_XFS_EXPORT=y
-# CONFIG_XFS_RT is not set
 # CONFIG_XFS_QUOTA is not set
 # CONFIG_XFS_SECURITY is not set
 # CONFIG_XFS_POSIX_ACL is not set
-CONFIG_MINIX_FS=y
-# CONFIG_ROMFS_FS is not set
+# CONFIG_XFS_RT is not set
+CONFIG_GFS2_FS=m
+CONFIG_GFS2_FS_LOCKING_NOLOCK=m
+CONFIG_GFS2_FS_LOCKING_DLM=m
+CONFIG_OCFS2_FS=m
+# CONFIG_OCFS2_DEBUG_MASKLOG is not set
+# CONFIG_OCFS2_DEBUG_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
 CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
 # CONFIG_QFMT_V1 is not set
 # CONFIG_QFMT_V2 is not set
 CONFIG_QUOTACTL=y
-CONFIG_DNOTIFY=y
 CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
+CONFIG_FUSE_FS=m
 
 #
 # CD-ROM/DVD Filesystems
@@ -654,7 +807,6 @@ CONFIG_AUTOFS4_FS=m
 CONFIG_ISO9660_FS=y
 CONFIG_JOLIET=y
 CONFIG_ZISOFS=y
-CONFIG_ZISOFS_FS=y
 CONFIG_UDF_FS=m
 CONFIG_UDF_NLS=y
 
@@ -673,13 +825,12 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 #
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
 CONFIG_SYSFS=y
-# CONFIG_DEVFS_FS is not set
-# CONFIG_DEVPTS_FS_XATTR is not set
 CONFIG_TMPFS=y
-# CONFIG_TMPFS_XATTR is not set
+# CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
+CONFIG_CONFIGFS_FS=m
 
 #
 # Miscellaneous filesystems
@@ -693,44 +844,40 @@ CONFIG_HFSPLUS_FS=m
 # CONFIG_EFS_FS is not set
 CONFIG_CRAMFS=m
 # CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=y
 CONFIG_HPFS_FS=m
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 CONFIG_SYSV_FS=m
 CONFIG_UFS_FS=m
 # CONFIG_UFS_FS_WRITE is not set
-
-#
-# Network File Systems
-#
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
 # CONFIG_NFS_DIRECTIO is not set
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
-CONFIG_NFSD_V4=y
+# CONFIG_NFSD_V3_ACL is not set
+# CONFIG_NFSD_V4 is not set
 CONFIG_NFSD_TCP=y
 CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=m
+CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
+CONFIG_SUNRPC_BIND34=y
 CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
 CONFIG_SMB_NLS_DEFAULT=y
 CONFIG_SMB_NLS_REMOTE="cp437"
 # CONFIG_CIFS is not set
-CONFIG_NCP_FS=m
-# CONFIG_NCPFS_PACKET_SIGNING is not set
-# CONFIG_NCPFS_IOCTL_LOCKING is not set
-# CONFIG_NCPFS_STRONG is not set
-CONFIG_NCPFS_NFS_NS=y
-CONFIG_NCPFS_OS2_NS=y
-# CONFIG_NCPFS_SMALLDOS is not set
-CONFIG_NCPFS_NLS=y
-# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_NCP_FS is not set
 CONFIG_CODA_FS=m
 # CONFIG_CODA_FS_OLD_API is not set
 # CONFIG_AFS_FS is not set
@@ -740,10 +887,6 @@ CONFIG_CODA_FS=m
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=y
@@ -784,35 +927,42 @@ CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
 CONFIG_NLS_UTF8=m
+CONFIG_DLM=m
+# CONFIG_DLM_DEBUG is not set
 
 #
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
-CONFIG_DEBUG_KERNEL=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_MAGIC_SYSRQ=y
-CONFIG_LOG_BUF_SHIFT=16
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_INFO is not set
+# CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
-# CONFIG_FRAME_POINTER is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_SAMPLES is not set
 
 #
 # Security options
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_XOR_BLOCKS=m
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_XOR=m
 CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_SEQIV=m
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
 CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=m
 CONFIG_CRYPTO_NULL=m
 CONFIG_CRYPTO_MD4=m
 CONFIG_CRYPTO_MD5=y
@@ -821,9 +971,21 @@ CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
 CONFIG_CRYPTO_WP512=m
 CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_XTS=m
+CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_CRYPTD=m
 CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
 CONFIG_CRYPTO_BLOWFISH=m
 CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
 CONFIG_CRYPTO_SERPENT=m
 CONFIG_CRYPTO_AES=m
 CONFIG_CRYPTO_CAST5=m
@@ -832,20 +994,35 @@ CONFIG_CRYPTO_TEA=m
 CONFIG_CRYPTO_ARC4=m
 CONFIG_CRYPTO_KHAZAD=m
 CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SALSA20=m
 CONFIG_CRYPTO_DEFLATE=m
 CONFIG_CRYPTO_MICHAEL_MIC=m
 CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_CAMELLIA=m
 CONFIG_CRYPTO_TEST=m
-
-#
-# Hardware crypto devices
-#
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_LZO=m
+# CONFIG_CRYPTO_HW is not set
 
 #
 # Library routines
 #
+CONFIG_BITREVERSE=y
 CONFIG_CRC_CCITT=m
+CONFIG_CRC16=m
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 CONFIG_LIBCRC32C=m
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=m
+CONFIG_LZO_COMPRESS=m
+CONFIG_LZO_DECOMPRESS=m
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_DMA=y
diff --git a/arch/m68k/configs/mac_defconfig b/arch/m68k/configs/mac_defconfig
index ff9dffa5b860..738bca695a88 100644
--- a/arch/m68k/configs/mac_defconfig
+++ b/arch/m68k/configs/mac_defconfig
@@ -1,63 +1,111 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc6-m68k
-# Tue Jun  7 20:34:45 2005
+# Linux kernel version: 2.6.25-rc8
+# Wed Apr  2 20:46:14 2008
 #
 CONFIG_M68K=y
 CONFIG_MMU=y
-CONFIG_UID16=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_TIME_LOW_RES=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_NO_IOPORT=y
+# CONFIG_NO_DMA is not set
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_HZ=100
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
-CONFIG_CLEAN_COMPILE=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION="-mac"
+CONFIG_LOCALVERSION_AUTO=y
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_BSD_PROCESS_ACCT=y
 # CONFIG_BSD_PROCESS_ACCT_V3 is not set
-CONFIG_SYSCTL=y
-CONFIG_AUDIT=y
-CONFIG_HOTPLUG=y
-CONFIG_KOBJECT_UEVENT=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_COMPAT_BRK is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+# CONFIG_HAVE_OPROFILE is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_OBSOLETE_MODPARM=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+CONFIG_BLK_DEV_BSG=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
 
 #
 # Platform dependent setup
@@ -82,10 +130,24 @@ CONFIG_M68030=y
 CONFIG_M68040=y
 # CONFIG_M68060 is not set
 CONFIG_MMU_MOTOROLA=y
-CONFIG_M68KFPU_EMU=y
-CONFIG_M68KFPU_EMU_EXTRAPREC=y
-# CONFIG_M68KFPU_EMU_ONLY is not set
+# CONFIG_M68KFPU_EMU is not set
 # CONFIG_ADVANCED is not set
+CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
+CONFIG_NODES_SHIFT=3
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_FLATMEM_MANUAL is not set
+CONFIG_DISCONTIGMEM_MANUAL=y
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_DISCONTIGMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_NEED_MULTIPLE_NODES=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
 
 #
 # General setup
@@ -95,171 +157,11 @@ CONFIG_BINFMT_AOUT=m
 CONFIG_BINFMT_MISC=m
 # CONFIG_HEARTBEAT is not set
 CONFIG_PROC_HARDWARE=y
+CONFIG_ZONE_DMA=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 
 #
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
-# CONFIG_DEBUG_DRIVER is not set
-
-#
-# Memory Technology Devices (MTD)
-#
-# CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_CDROM_PKTCDVD_BUFFERS=8
-# CONFIG_CDROM_PKTCDVD_WCACHE is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_ATA_OVER_ETH=m
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-CONFIG_IDE=y
-CONFIG_BLK_DEV_IDE=y
-
-#
-# Please see Documentation/ide.txt for help/info on IDE drives
-#
-# CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_BLK_DEV_IDEDISK=y
-# CONFIG_IDEDISK_MULTI_MODE is not set
-CONFIG_BLK_DEV_IDECD=y
-CONFIG_BLK_DEV_IDETAPE=m
-CONFIG_BLK_DEV_IDEFLOPPY=m
-# CONFIG_BLK_DEV_IDESCSI is not set
-# CONFIG_IDE_TASK_IOCTL is not set
-
-#
-# IDE chipset support/bugfixes
-#
-CONFIG_IDE_GENERIC=y
-# CONFIG_IDE_ARM is not set
-CONFIG_BLK_DEV_MAC_IDE=y
-# CONFIG_BLK_DEV_IDEDMA is not set
-# CONFIG_IDEDMA_AUTO is not set
-# CONFIG_BLK_DEV_HD is not set
-
-#
-# SCSI device support
-#
-CONFIG_SCSI=y
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=m
-CONFIG_CHR_DEV_OSST=m
-CONFIG_BLK_DEV_SR=y
-CONFIG_BLK_DEV_SR_VENDOR=y
-CONFIG_CHR_DEV_SG=m
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-# CONFIG_SCSI_MULTI_LUN is not set
-CONFIG_SCSI_CONSTANTS=y
-# CONFIG_SCSI_LOGGING is not set
-
-#
-# SCSI Transport Attributes
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-
-#
-# SCSI low-level drivers
-#
-# CONFIG_SCSI_SATA is not set
-# CONFIG_SCSI_DEBUG is not set
-CONFIG_MAC_SCSI=y
-CONFIG_SCSI_MAC_ESP=y
-
-#
-# Multi-device support (RAID and LVM)
-#
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-# CONFIG_MD_RAID10 is not set
-CONFIG_MD_RAID5=m
-CONFIG_MD_RAID6=m
-CONFIG_MD_MULTIPATH=m
-# CONFIG_MD_FAULTY is not set
-CONFIG_BLK_DEV_DM=m
-CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
-CONFIG_DM_MIRROR=m
-CONFIG_DM_ZERO=m
-CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_EMC=m
-
-#
-# Fusion MPT device support
-#
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Macintosh device drivers
-#
-CONFIG_ADB=y
-CONFIG_ADB_MACII=y
-CONFIG_ADB_MACIISI=y
-CONFIG_ADB_IOP=y
-CONFIG_ADB_PMU68K=y
-CONFIG_ADB_CUDA=y
-CONFIG_INPUT_ADBHID=y
-CONFIG_MAC_EMUMOUSEBTN=y
-
-#
-# Networking support
+# Networking
 #
 CONFIG_NET=y
 
@@ -269,10 +171,17 @@ CONFIG_NET=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+CONFIG_XFRM_MIGRATE=y
+# CONFIG_XFRM_STATISTICS is not set
 CONFIG_NET_KEY=y
+CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
 # CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
 # CONFIG_IP_PNP is not set
 CONFIG_NET_IPIP=m
 CONFIG_NET_IPGRE=m
@@ -281,148 +190,202 @@ CONFIG_SYN_COOKIES=y
 CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
 CONFIG_INET_TUNNEL=m
-CONFIG_IP_TCPDIAG=m
-CONFIG_IP_TCPDIAG_IPV6=y
-
-#
-# IP: Virtual Server Configuration
-#
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_INET_LRO=m
+CONFIG_INET_DIAG=m
+CONFIG_INET_TCP_DIAG=m
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
 # CONFIG_IP_VS is not set
 CONFIG_IPV6=m
 CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
 CONFIG_INET6_AH=m
 CONFIG_INET6_ESP=m
 CONFIG_INET6_IPCOMP=m
+# CONFIG_IPV6_MIP6 is not set
+CONFIG_INET6_XFRM_TUNNEL=m
 CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
+CONFIG_IPV6_SIT=m
 CONFIG_IPV6_TUNNEL=m
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_NETWORK_SECMARK is not set
 CONFIG_NETFILTER=y
 # CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+CONFIG_NF_CT_PROTO_GRE=m
+CONFIG_NF_CT_PROTO_SCTP=m
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+# CONFIG_NF_CT_NETLINK is not set
+CONFIG_NETFILTER_XTABLES=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_RATEEST=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
 
 #
 # IP: Netfilter Configuration
 #
-CONFIG_IP_NF_CONNTRACK=m
-# CONFIG_IP_NF_CT_ACCT is not set
-CONFIG_IP_NF_CONNTRACK_MARK=y
-# CONFIG_IP_NF_CT_PROTO_SCTP is not set
-CONFIG_IP_NF_FTP=m
-CONFIG_IP_NF_IRC=m
-CONFIG_IP_NF_TFTP=m
-CONFIG_IP_NF_AMANDA=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
 CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_LIMIT=m
-CONFIG_IP_NF_MATCH_IPRANGE=m
-CONFIG_IP_NF_MATCH_MAC=m
-CONFIG_IP_NF_MATCH_PKTTYPE=m
-CONFIG_IP_NF_MATCH_MARK=m
-CONFIG_IP_NF_MATCH_MULTIPORT=m
-CONFIG_IP_NF_MATCH_TOS=m
 CONFIG_IP_NF_MATCH_RECENT=m
 CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_DSCP=m
-CONFIG_IP_NF_MATCH_AH_ESP=m
-CONFIG_IP_NF_MATCH_LENGTH=m
+CONFIG_IP_NF_MATCH_AH=m
 CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_MATCH_TCPMSS=m
-CONFIG_IP_NF_MATCH_HELPER=m
-CONFIG_IP_NF_MATCH_STATE=m
-CONFIG_IP_NF_MATCH_CONNTRACK=m
-CONFIG_IP_NF_MATCH_OWNER=m
 CONFIG_IP_NF_MATCH_ADDRTYPE=m
-CONFIG_IP_NF_MATCH_REALM=m
-# CONFIG_IP_NF_MATCH_SCTP is not set
-# CONFIG_IP_NF_MATCH_COMMENT is not set
-CONFIG_IP_NF_MATCH_CONNMARK=m
-CONFIG_IP_NF_MATCH_HASHLIMIT=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
 CONFIG_IP_NF_TARGET_LOG=m
 CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_IP_NF_TARGET_TCPMSS=m
-CONFIG_IP_NF_NAT=m
-CONFIG_IP_NF_NAT_NEEDED=y
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
 CONFIG_IP_NF_TARGET_MASQUERADE=m
 CONFIG_IP_NF_TARGET_REDIRECT=m
 CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_SAME=m
-CONFIG_IP_NF_NAT_SNMP_BASIC=m
-CONFIG_IP_NF_NAT_IRC=m
-CONFIG_IP_NF_NAT_FTP=m
-CONFIG_IP_NF_NAT_TFTP=m
-CONFIG_IP_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_SNMP_BASIC=m
+CONFIG_NF_NAT_PROTO_GRE=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+CONFIG_NF_NAT_TFTP=m
+CONFIG_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+CONFIG_NF_NAT_SIP=m
 CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_TOS=m
 CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_DSCP=m
-CONFIG_IP_NF_TARGET_MARK=m
-CONFIG_IP_NF_TARGET_CLASSIFY=m
-CONFIG_IP_NF_TARGET_CONNMARK=m
-# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
 CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_TARGET_NOTRACK=m
 CONFIG_IP_NF_ARPTABLES=m
 CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
 
 #
-# IPv6: Netfilter Configuration (EXPERIMENTAL)
+# IPv6: Netfilter Configuration
 #
+CONFIG_NF_CONNTRACK_IPV6=m
 CONFIG_IP6_NF_QUEUE=m
 CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_MATCH_LIMIT=m
-CONFIG_IP6_NF_MATCH_MAC=m
 CONFIG_IP6_NF_MATCH_RT=m
 CONFIG_IP6_NF_MATCH_OPTS=m
 CONFIG_IP6_NF_MATCH_FRAG=m
 CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_MULTIPORT=m
-CONFIG_IP6_NF_MATCH_OWNER=m
-CONFIG_IP6_NF_MATCH_MARK=m
 CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_MATCH_AHESP=m
-CONFIG_IP6_NF_MATCH_LENGTH=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_MH=m
 CONFIG_IP6_NF_MATCH_EUI64=m
 CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_TARGET_MARK=m
+CONFIG_IP6_NF_TARGET_HL=m
 CONFIG_IP6_NF_RAW=m
-CONFIG_XFRM=y
-CONFIG_XFRM_USER=m
+CONFIG_IP_DCCP=m
+CONFIG_INET_DCCP_DIAG=m
+CONFIG_IP_DCCP_ACKVEC=y
 
 #
-# SCTP Configuration (EXPERIMENTAL)
+# DCCP CCIDs Configuration (EXPERIMENTAL)
 #
+CONFIG_IP_DCCP_CCID2=m
+# CONFIG_IP_DCCP_CCID2_DEBUG is not set
+CONFIG_IP_DCCP_CCID3=m
+# CONFIG_IP_DCCP_CCID3_DEBUG is not set
+CONFIG_IP_DCCP_CCID3_RTO=100
+CONFIG_IP_DCCP_TFRC_LIB=m
 CONFIG_IP_SCTP=m
 # CONFIG_SCTP_DBG_MSG is not set
 # CONFIG_SCTP_DBG_OBJCNT is not set
 # CONFIG_SCTP_HMAC_NONE is not set
 # CONFIG_SCTP_HMAC_SHA1 is not set
 CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 CONFIG_LLC=m
 # CONFIG_LLC2 is not set
-CONFIG_IPX=m
-# CONFIG_IPX_INTERN is not set
+# CONFIG_IPX is not set
 CONFIG_ATALK=m
-CONFIG_DEV_APPLETALK=y
+CONFIG_DEV_APPLETALK=m
 CONFIG_IPDDP=m
 CONFIG_IPDDP_ENCAP=y
 CONFIG_IPDDP_DECAP=y
 # CONFIG_X25 is not set
 # CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 CONFIG_NET_CLS_ROUTE=y
 
@@ -430,80 +393,223 @@ CONFIG_NET_CLS_ROUTE=y
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
-CONFIG_NETPOLL=y
-# CONFIG_NETPOLL_RX is not set
-# CONFIG_NETPOLL_TRAP is not set
-CONFIG_NET_POLL_CONTROLLER=y
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=m
-# CONFIG_BONDING is not set
-CONFIG_EQUALIZER=m
-# CONFIG_TUN is not set
+# CONFIG_AF_RXRPC is not set
 
 #
-# Ethernet (10 or 100Mbit)
+# Wireless
 #
-CONFIG_NET_ETHERNET=y
-# CONFIG_MII is not set
-CONFIG_MAC8390=y
-CONFIG_MAC89x0=y
-CONFIG_MACSONIC=y
-CONFIG_MACMACE=y
-# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=m
+CONFIG_IEEE80211_CRYPT_CCMP=m
+CONFIG_IEEE80211_CRYPT_TKIP=m
+CONFIG_IEEE80211_SOFTMAC=m
+# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=m
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=m
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+CONFIG_ATA_OVER_ETH=m
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
 
 #
-# Ethernet (1000 Mbit)
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+CONFIG_BLK_DEV_IDECD=y
+CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
+# CONFIG_BLK_DEV_IDETAPE is not set
+CONFIG_BLK_DEV_IDEFLOPPY=m
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
+
+#
+# IDE chipset support/bugfixes
 #
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
+CONFIG_BLK_DEV_MAC_IDE=y
+# CONFIG_BLK_DEV_IDEDMA is not set
+# CONFIG_IDE_ARCH_OBSOLETE_INIT is not set
+# CONFIG_BLK_DEV_HD is not set
 
 #
-# Ethernet (10000 Mbit)
+# SCSI device support
 #
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=m
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
 
 #
-# Token Ring devices
+# SCSI support type (disk, tape, CD-ROM)
 #
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_ST=m
+CONFIG_CHR_DEV_OSST=m
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_DEV_SR_VENDOR=y
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
 
 #
-# Wireless LAN (non-hamradio)
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
 #
-# CONFIG_NET_RADIO is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+CONFIG_SCSI_CONSTANTS=y
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
 
 #
-# Wan interfaces
+# SCSI Transports
 #
+CONFIG_SCSI_SPI_ATTRS=y
+# CONFIG_SCSI_FC_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=m
+CONFIG_SCSI_SAS_ATTRS=m
+CONFIG_SCSI_SAS_LIBSAS=m
+CONFIG_SCSI_SAS_HOST_SMP=y
+# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
+CONFIG_SCSI_SRP_ATTRS=m
+CONFIG_SCSI_SRP_TGT_ATTRS=y
+CONFIG_SCSI_LOWLEVEL=y
+CONFIG_ISCSI_TCP=m
+# CONFIG_SCSI_DEBUG is not set
+CONFIG_MAC_SCSI=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+# CONFIG_MD_RAID10 is not set
+CONFIG_MD_RAID456=m
+CONFIG_MD_RAID5_RESHAPE=y
+CONFIG_MD_MULTIPATH=m
+# CONFIG_MD_FAULTY is not set
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_ZERO=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_MULTIPATH_EMC=m
+CONFIG_DM_MULTIPATH_RDAC=m
+CONFIG_DM_MULTIPATH_HP=m
+# CONFIG_DM_DELAY is not set
+CONFIG_DM_UEVENT=y
+CONFIG_MACINTOSH_DRIVERS=y
+CONFIG_ADB=y
+CONFIG_ADB_MACII=y
+CONFIG_ADB_MACIISI=y
+CONFIG_ADB_IOP=y
+CONFIG_ADB_PMU68K=y
+CONFIG_ADB_CUDA=y
+CONFIG_INPUT_ADBHID=y
+CONFIG_MAC_EMUMOUSEBTN=y
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+CONFIG_DUMMY=m
+# CONFIG_BONDING is not set
+CONFIG_MACVLAN=m
+CONFIG_EQUALIZER=m
+# CONFIG_TUN is not set
+CONFIG_VETH=m
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+CONFIG_MAC8390=y
+CONFIG_MAC89x0=m
+CONFIG_MACSONIC=m
+CONFIG_MACMACE=y
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 # CONFIG_WAN is not set
 CONFIG_PPP=m
 # CONFIG_PPP_MULTILINK is not set
 CONFIG_PPP_FILTER=y
-# CONFIG_PPP_ASYNC is not set
-# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
 CONFIG_PPP_DEFLATE=m
 CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
 CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
 CONFIG_SLIP=m
 CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLHC=m
 CONFIG_SLIP_SMART=y
 CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_SHAPER=m
 CONFIG_NETCONSOLE=m
-
-#
-# ISDN subsystem
-#
+CONFIG_NETCONSOLE_DYNAMIC=y
+CONFIG_NETPOLL=y
+# CONFIG_NETPOLL_TRAP is not set
+CONFIG_NET_POLL_CONTROLLER=y
 # CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
 # CONFIG_PHONE is not set
 
 #
 # Input device support
 #
 CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=m
+# CONFIG_INPUT_POLLDEV is not set
 
 #
 # Userland interfaces
@@ -513,7 +619,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 
@@ -526,19 +631,29 @@ CONFIG_INPUT_KEYBOARD=y
 # CONFIG_KEYBOARD_LKKBD is not set
 # CONFIG_KEYBOARD_XTKBD is not set
 # CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
 CONFIG_INPUT_MOUSE=y
 CONFIG_MOUSE_PS2=m
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
 CONFIG_MOUSE_SERIAL=m
 # CONFIG_MOUSE_VSXXXAA is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_M68K_BEEP=m
+# CONFIG_INPUT_UINPUT is not set
 
 #
 # Hardware I/O ports
 #
 CONFIG_SERIO=m
-CONFIG_SERIO_SERPORT=m
+# CONFIG_SERIO_SERPORT is not set
 CONFIG_SERIO_LIBPS2=m
 # CONFIG_SERIO_RAW is not set
 # CONFIG_GAMEPORT is not set
@@ -549,6 +664,7 @@ CONFIG_SERIO_LIBPS2=m
 CONFIG_VT=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -562,116 +678,117 @@ CONFIG_HW_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
+# CONFIG_HW_RANDOM is not set
 CONFIG_GEN_RTC=m
 CONFIG_GEN_RTC_X=y
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
-
-#
-# Ftape, the floppy tape device driver
-#
-# CONFIG_DRM is not set
 # CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
-
-#
-# I2C support
-#
+# CONFIG_TCG_TPM is not set
 # CONFIG_I2C is not set
 
 #
-# Dallas's 1-wire bus
+# SPI support
 #
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
 # CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
 
 #
-# Misc devices
+# Sonics Silicon Backplane
 #
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
-# Multimedia devices
+# Multifunction device drivers
 #
-# CONFIG_VIDEO_DEV is not set
+# CONFIG_MFD_SM501 is not set
 
 #
-# Digital Video Broadcasting Devices
+# Multimedia devices
 #
-# CONFIG_DVB is not set
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
 
 #
 # Graphics support
 #
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_SOFT_CURSOR=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
 CONFIG_FB_MACMODES=y
-CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
 # CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
 CONFIG_FB_VALKYRIE=y
 CONFIG_FB_MAC=y
+# CONFIG_FB_UVESA is not set
 # CONFIG_FB_S1D13XXX is not set
 # CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
 #
 CONFIG_DUMMY_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
 # CONFIG_FONTS is not set
 CONFIG_FONT_8x8=y
 CONFIG_FONT_8x16=y
 CONFIG_FONT_6x11=y
-
-#
-# Logo configuration
-#
 CONFIG_LOGO=y
 CONFIG_LOGO_LINUX_MONO=y
 CONFIG_LOGO_LINUX_VGA16=y
 CONFIG_LOGO_LINUX_CLUT224=y
 CONFIG_LOGO_MAC_CLUT224=y
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
 # Sound
 #
 # CONFIG_SOUND is not set
-
-#
-# USB support
-#
-# CONFIG_USB_ARCH_HAS_HCD is not set
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=m
+# CONFIG_HID_DEBUG is not set
+CONFIG_HIDRAW=y
+# CONFIG_USB_SUPPORT is not set
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_RTC_CLASS is not set
 
 #
-# InfiniBand support
+# Userspace I/O
 #
-# CONFIG_INFINIBAND is not set
+# CONFIG_UIO is not set
 
 #
 # Character devices
@@ -685,10 +802,11 @@ CONFIG_SERIAL_CONSOLE=y
 #
 CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4DEV_FS is not set
 CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
 CONFIG_REISERFS_FS=m
 # CONFIG_REISERFS_CHECK is not set
 # CONFIG_REISERFS_PROC_INFO is not set
@@ -699,25 +817,29 @@ CONFIG_JFS_FS=m
 # CONFIG_JFS_DEBUG is not set
 # CONFIG_JFS_STATISTICS is not set
 CONFIG_FS_POSIX_ACL=y
-
-#
-# XFS support
-#
 CONFIG_XFS_FS=m
-CONFIG_XFS_EXPORT=y
-# CONFIG_XFS_RT is not set
 # CONFIG_XFS_QUOTA is not set
 # CONFIG_XFS_SECURITY is not set
 # CONFIG_XFS_POSIX_ACL is not set
-CONFIG_MINIX_FS=y
-# CONFIG_ROMFS_FS is not set
+# CONFIG_XFS_RT is not set
+CONFIG_GFS2_FS=m
+CONFIG_GFS2_FS_LOCKING_NOLOCK=m
+CONFIG_GFS2_FS_LOCKING_DLM=m
+CONFIG_OCFS2_FS=m
+# CONFIG_OCFS2_DEBUG_MASKLOG is not set
+# CONFIG_OCFS2_DEBUG_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
 CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
 # CONFIG_QFMT_V1 is not set
 # CONFIG_QFMT_V2 is not set
 CONFIG_QUOTACTL=y
-CONFIG_DNOTIFY=y
 CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
+CONFIG_FUSE_FS=m
 
 #
 # CD-ROM/DVD Filesystems
@@ -725,7 +847,6 @@ CONFIG_AUTOFS4_FS=m
 CONFIG_ISO9660_FS=y
 CONFIG_JOLIET=y
 CONFIG_ZISOFS=y
-CONFIG_ZISOFS_FS=y
 CONFIG_UDF_FS=m
 CONFIG_UDF_NLS=y
 
@@ -744,13 +865,12 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 #
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
 CONFIG_SYSFS=y
-# CONFIG_DEVFS_FS is not set
-# CONFIG_DEVPTS_FS_XATTR is not set
 CONFIG_TMPFS=y
-# CONFIG_TMPFS_XATTR is not set
+# CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
+CONFIG_CONFIGFS_FS=m
 
 #
 # Miscellaneous filesystems
@@ -764,43 +884,39 @@ CONFIG_HFSPLUS_FS=y
 # CONFIG_EFS_FS is not set
 CONFIG_CRAMFS=m
 # CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=y
 CONFIG_HPFS_FS=m
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 CONFIG_SYSV_FS=m
 CONFIG_UFS_FS=m
 # CONFIG_UFS_FS_WRITE is not set
-
-#
-# Network File Systems
-#
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
 # CONFIG_NFS_DIRECTIO is not set
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
-CONFIG_NFSD_V4=y
+# CONFIG_NFSD_V3_ACL is not set
+# CONFIG_NFSD_V4 is not set
 CONFIG_NFSD_TCP=y
 CONFIG_LOCKD=m
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=m
+CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=m
 CONFIG_SUNRPC_GSS=m
+CONFIG_SUNRPC_BIND34=y
 CONFIG_RPCSEC_GSS_KRB5=m
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
 CONFIG_SMB_NLS_DEFAULT=y
 CONFIG_SMB_NLS_REMOTE="cp437"
 # CONFIG_CIFS is not set
-CONFIG_NCP_FS=m
-# CONFIG_NCPFS_PACKET_SIGNING is not set
-# CONFIG_NCPFS_IOCTL_LOCKING is not set
-# CONFIG_NCPFS_STRONG is not set
-CONFIG_NCPFS_NFS_NS=y
-CONFIG_NCPFS_OS2_NS=y
-# CONFIG_NCPFS_SMALLDOS is not set
-CONFIG_NCPFS_NLS=y
-# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_NCP_FS is not set
 CONFIG_CODA_FS=m
 # CONFIG_CODA_FS_OLD_API is not set
 # CONFIG_AFS_FS is not set
@@ -808,27 +924,9 @@ CONFIG_CODA_FS=m
 #
 # Partition Types
 #
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-CONFIG_AMIGA_PARTITION=y
-CONFIG_ATARI_PARTITION=y
+# CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MAC_PARTITION=y
 CONFIG_MSDOS_PARTITION=y
-CONFIG_BSD_DISKLABEL=y
-CONFIG_MINIX_SUBPARTITION=y
-CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_UNIXWARE_DISKLABEL=y
-CONFIG_LDM_PARTITION=y
-CONFIG_LDM_DEBUG=y
-# CONFIG_SGI_PARTITION is not set
-# CONFIG_ULTRIX_PARTITION is not set
-CONFIG_SUN_PARTITION=y
-# CONFIG_EFI_PARTITION is not set
-
-#
-# Native Language Support
-#
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=y
@@ -869,46 +967,65 @@ CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
 CONFIG_NLS_UTF8=y
+CONFIG_DLM=m
+# CONFIG_DLM_DEBUG is not set
 
 #
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
-CONFIG_DEBUG_KERNEL=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_MAGIC_SYSRQ=y
-CONFIG_LOG_BUF_SHIFT=16
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_INFO is not set
+# CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
-# CONFIG_FRAME_POINTER is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_SAMPLES is not set
 
 #
 # Security options
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_XOR_BLOCKS=m
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_XOR=m
 CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_SEQIV=m
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
 CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=m
 CONFIG_CRYPTO_NULL=m
 CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MD5=m
 CONFIG_CRYPTO_SHA1=m
 CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
 CONFIG_CRYPTO_WP512=m
 CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_XTS=m
+CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_CRYPTD=m
 CONFIG_CRYPTO_DES=m
+CONFIG_CRYPTO_FCRYPT=m
 CONFIG_CRYPTO_BLOWFISH=m
 CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
 CONFIG_CRYPTO_SERPENT=m
 CONFIG_CRYPTO_AES=m
 CONFIG_CRYPTO_CAST5=m
@@ -917,20 +1034,35 @@ CONFIG_CRYPTO_TEA=m
 CONFIG_CRYPTO_ARC4=m
 CONFIG_CRYPTO_KHAZAD=m
 CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SALSA20=m
 CONFIG_CRYPTO_DEFLATE=m
 CONFIG_CRYPTO_MICHAEL_MIC=m
 CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_CAMELLIA=m
 CONFIG_CRYPTO_TEST=m
-
-#
-# Hardware crypto devices
-#
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_LZO=m
+# CONFIG_CRYPTO_HW is not set
 
 #
 # Library routines
 #
+CONFIG_BITREVERSE=y
 CONFIG_CRC_CCITT=m
+CONFIG_CRC16=m
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 CONFIG_LIBCRC32C=m
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=m
+CONFIG_LZO_COMPRESS=m
+CONFIG_LZO_DECOMPRESS=m
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_DMA=y
diff --git a/arch/m68k/configs/mvme147_defconfig b/arch/m68k/configs/mvme147_defconfig
index f0d5534f6830..f40b1724254b 100644
--- a/arch/m68k/configs/mvme147_defconfig
+++ b/arch/m68k/configs/mvme147_defconfig
@@ -1,63 +1,111 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc6-m68k
-# Tue Jun  7 20:34:50 2005
+# Linux kernel version: 2.6.25-rc8
+# Wed Apr  2 20:46:17 2008
 #
 CONFIG_M68K=y
 CONFIG_MMU=y
-CONFIG_UID16=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_TIME_LOW_RES=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_NO_IOPORT=y
+# CONFIG_NO_DMA is not set
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_HZ=100
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
-CONFIG_CLEAN_COMPILE=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION="-mvme147"
+CONFIG_LOCALVERSION_AUTO=y
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_BSD_PROCESS_ACCT=y
 # CONFIG_BSD_PROCESS_ACCT_V3 is not set
-CONFIG_SYSCTL=y
-CONFIG_AUDIT=y
-CONFIG_HOTPLUG=y
-CONFIG_KOBJECT_UEVENT=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_COMPAT_BRK is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+# CONFIG_HAVE_OPROFILE is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_OBSOLETE_MODPARM=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+CONFIG_BLK_DEV_BSG=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
 
 #
 # Platform dependent setup
@@ -85,6 +133,22 @@ CONFIG_M68030=y
 CONFIG_MMU_MOTOROLA=y
 # CONFIG_M68KFPU_EMU is not set
 # CONFIG_ADVANCED is not set
+CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
+CONFIG_NODES_SHIFT=3
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_FLATMEM_MANUAL is not set
+CONFIG_DISCONTIGMEM_MANUAL=y
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_DISCONTIGMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_NEED_MULTIPLE_NODES=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
 
 #
 # General setup
@@ -93,135 +157,11 @@ CONFIG_BINFMT_ELF=y
 CONFIG_BINFMT_AOUT=m
 CONFIG_BINFMT_MISC=m
 CONFIG_PROC_HARDWARE=y
+CONFIG_ZONE_DMA=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 
 #
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
-# CONFIG_DEBUG_DRIVER is not set
-
-#
-# Memory Technology Devices (MTD)
-#
-# CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_CDROM_PKTCDVD_BUFFERS=8
-# CONFIG_CDROM_PKTCDVD_WCACHE is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_ATA_OVER_ETH=m
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-CONFIG_SCSI=y
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=m
-# CONFIG_CHR_DEV_OSST is not set
-CONFIG_BLK_DEV_SR=y
-CONFIG_BLK_DEV_SR_VENDOR=y
-CONFIG_CHR_DEV_SG=m
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-# CONFIG_SCSI_MULTI_LUN is not set
-CONFIG_SCSI_CONSTANTS=y
-# CONFIG_SCSI_LOGGING is not set
-
-#
-# SCSI Transport Attributes
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-
-#
-# SCSI low-level drivers
-#
-# CONFIG_SCSI_SATA is not set
-# CONFIG_SCSI_DEBUG is not set
-CONFIG_MVME147_SCSI=y
-
-#
-# Multi-device support (RAID and LVM)
-#
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-# CONFIG_MD_RAID10 is not set
-CONFIG_MD_RAID5=m
-CONFIG_MD_RAID6=m
-CONFIG_MD_MULTIPATH=m
-# CONFIG_MD_FAULTY is not set
-CONFIG_BLK_DEV_DM=m
-CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
-CONFIG_DM_MIRROR=m
-CONFIG_DM_ZERO=m
-CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_EMC=m
-
-#
-# Fusion MPT device support
-#
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Networking support
+# Networking
 #
 CONFIG_NET=y
 
@@ -231,10 +171,17 @@ CONFIG_NET=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+CONFIG_XFRM_MIGRATE=y
+# CONFIG_XFRM_STATISTICS is not set
 CONFIG_NET_KEY=y
+CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
 # CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
@@ -246,145 +193,199 @@ CONFIG_SYN_COOKIES=y
 CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
 CONFIG_INET_TUNNEL=m
-CONFIG_IP_TCPDIAG=m
-CONFIG_IP_TCPDIAG_IPV6=y
-
-#
-# IP: Virtual Server Configuration
-#
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_INET_LRO=m
+CONFIG_INET_DIAG=m
+CONFIG_INET_TCP_DIAG=m
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
 # CONFIG_IP_VS is not set
 CONFIG_IPV6=m
 CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
 CONFIG_INET6_AH=m
 CONFIG_INET6_ESP=m
 CONFIG_INET6_IPCOMP=m
+# CONFIG_IPV6_MIP6 is not set
+CONFIG_INET6_XFRM_TUNNEL=m
 CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
+CONFIG_IPV6_SIT=m
 CONFIG_IPV6_TUNNEL=m
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_NETWORK_SECMARK is not set
 CONFIG_NETFILTER=y
 # CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+CONFIG_NF_CT_PROTO_GRE=m
+CONFIG_NF_CT_PROTO_SCTP=m
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+# CONFIG_NF_CT_NETLINK is not set
+CONFIG_NETFILTER_XTABLES=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_RATEEST=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
 
 #
 # IP: Netfilter Configuration
 #
-CONFIG_IP_NF_CONNTRACK=m
-# CONFIG_IP_NF_CT_ACCT is not set
-CONFIG_IP_NF_CONNTRACK_MARK=y
-# CONFIG_IP_NF_CT_PROTO_SCTP is not set
-CONFIG_IP_NF_FTP=m
-CONFIG_IP_NF_IRC=m
-CONFIG_IP_NF_TFTP=m
-CONFIG_IP_NF_AMANDA=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
 CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_LIMIT=m
-CONFIG_IP_NF_MATCH_IPRANGE=m
-CONFIG_IP_NF_MATCH_MAC=m
-CONFIG_IP_NF_MATCH_PKTTYPE=m
-CONFIG_IP_NF_MATCH_MARK=m
-CONFIG_IP_NF_MATCH_MULTIPORT=m
-CONFIG_IP_NF_MATCH_TOS=m
 CONFIG_IP_NF_MATCH_RECENT=m
 CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_DSCP=m
-CONFIG_IP_NF_MATCH_AH_ESP=m
-CONFIG_IP_NF_MATCH_LENGTH=m
+CONFIG_IP_NF_MATCH_AH=m
 CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_MATCH_TCPMSS=m
-CONFIG_IP_NF_MATCH_HELPER=m
-CONFIG_IP_NF_MATCH_STATE=m
-CONFIG_IP_NF_MATCH_CONNTRACK=m
-CONFIG_IP_NF_MATCH_OWNER=m
 CONFIG_IP_NF_MATCH_ADDRTYPE=m
-CONFIG_IP_NF_MATCH_REALM=m
-# CONFIG_IP_NF_MATCH_SCTP is not set
-# CONFIG_IP_NF_MATCH_COMMENT is not set
-CONFIG_IP_NF_MATCH_CONNMARK=m
-CONFIG_IP_NF_MATCH_HASHLIMIT=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
 CONFIG_IP_NF_TARGET_LOG=m
 CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_IP_NF_TARGET_TCPMSS=m
-CONFIG_IP_NF_NAT=m
-CONFIG_IP_NF_NAT_NEEDED=y
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
 CONFIG_IP_NF_TARGET_MASQUERADE=m
 CONFIG_IP_NF_TARGET_REDIRECT=m
 CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_SAME=m
-CONFIG_IP_NF_NAT_SNMP_BASIC=m
-CONFIG_IP_NF_NAT_IRC=m
-CONFIG_IP_NF_NAT_FTP=m
-CONFIG_IP_NF_NAT_TFTP=m
-CONFIG_IP_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_SNMP_BASIC=m
+CONFIG_NF_NAT_PROTO_GRE=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+CONFIG_NF_NAT_TFTP=m
+CONFIG_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+CONFIG_NF_NAT_SIP=m
 CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_TOS=m
 CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_DSCP=m
-CONFIG_IP_NF_TARGET_MARK=m
-CONFIG_IP_NF_TARGET_CLASSIFY=m
-CONFIG_IP_NF_TARGET_CONNMARK=m
-# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
 CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_TARGET_NOTRACK=m
 CONFIG_IP_NF_ARPTABLES=m
 CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
 
 #
-# IPv6: Netfilter Configuration (EXPERIMENTAL)
+# IPv6: Netfilter Configuration
 #
+CONFIG_NF_CONNTRACK_IPV6=m
 CONFIG_IP6_NF_QUEUE=m
 CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_MATCH_LIMIT=m
-CONFIG_IP6_NF_MATCH_MAC=m
 CONFIG_IP6_NF_MATCH_RT=m
 CONFIG_IP6_NF_MATCH_OPTS=m
 CONFIG_IP6_NF_MATCH_FRAG=m
 CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_MULTIPORT=m
-CONFIG_IP6_NF_MATCH_OWNER=m
-CONFIG_IP6_NF_MATCH_MARK=m
 CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_MATCH_AHESP=m
-CONFIG_IP6_NF_MATCH_LENGTH=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_MH=m
 CONFIG_IP6_NF_MATCH_EUI64=m
 CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_TARGET_MARK=m
+CONFIG_IP6_NF_TARGET_HL=m
 CONFIG_IP6_NF_RAW=m
-CONFIG_XFRM=y
-CONFIG_XFRM_USER=m
+CONFIG_IP_DCCP=m
+CONFIG_INET_DCCP_DIAG=m
+CONFIG_IP_DCCP_ACKVEC=y
 
 #
-# SCTP Configuration (EXPERIMENTAL)
+# DCCP CCIDs Configuration (EXPERIMENTAL)
 #
+CONFIG_IP_DCCP_CCID2=m
+# CONFIG_IP_DCCP_CCID2_DEBUG is not set
+CONFIG_IP_DCCP_CCID3=m
+# CONFIG_IP_DCCP_CCID3_DEBUG is not set
+CONFIG_IP_DCCP_CCID3_RTO=100
+CONFIG_IP_DCCP_TFRC_LIB=m
 CONFIG_IP_SCTP=m
 # CONFIG_SCTP_DBG_MSG is not set
 # CONFIG_SCTP_DBG_OBJCNT is not set
 # CONFIG_SCTP_HMAC_NONE is not set
 # CONFIG_SCTP_HMAC_SHA1 is not set
 CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 CONFIG_LLC=m
 # CONFIG_LLC2 is not set
-CONFIG_IPX=m
-# CONFIG_IPX_INTERN is not set
+# CONFIG_IPX is not set
 CONFIG_ATALK=m
 # CONFIG_DEV_APPLETALK is not set
 # CONFIG_X25 is not set
 # CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 CONFIG_NET_CLS_ROUTE=y
 
@@ -392,46 +393,155 @@ CONFIG_NET_CLS_ROUTE=y
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
-CONFIG_NETPOLL=y
-# CONFIG_NETPOLL_RX is not set
-# CONFIG_NETPOLL_TRAP is not set
-CONFIG_NET_POLL_CONTROLLER=y
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=m
-# CONFIG_BONDING is not set
-CONFIG_EQUALIZER=m
-# CONFIG_TUN is not set
+# CONFIG_AF_RXRPC is not set
 
 #
-# Ethernet (10 or 100Mbit)
+# Wireless
 #
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=m
-CONFIG_MVME147_NET=y
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=m
+CONFIG_IEEE80211_CRYPT_CCMP=m
+CONFIG_IEEE80211_CRYPT_TKIP=m
+CONFIG_IEEE80211_SOFTMAC=m
+# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
-# Ethernet (1000 Mbit)
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=m
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=m
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+CONFIG_ATA_OVER_ETH=m
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
 #
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=m
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
 
 #
-# Ethernet (10000 Mbit)
+# SCSI support type (disk, tape, CD-ROM)
 #
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_ST=m
+CONFIG_CHR_DEV_OSST=m
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_DEV_SR_VENDOR=y
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
 
 #
-# Token Ring devices
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
 #
+# CONFIG_SCSI_MULTI_LUN is not set
+CONFIG_SCSI_CONSTANTS=y
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
 
 #
-# Wireless LAN (non-hamradio)
+# SCSI Transports
 #
-# CONFIG_NET_RADIO is not set
+CONFIG_SCSI_SPI_ATTRS=y
+# CONFIG_SCSI_FC_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=m
+CONFIG_SCSI_SAS_ATTRS=m
+CONFIG_SCSI_SAS_LIBSAS=m
+CONFIG_SCSI_SAS_HOST_SMP=y
+# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
+CONFIG_SCSI_SRP_ATTRS=m
+CONFIG_SCSI_SRP_TGT_ATTRS=y
+CONFIG_SCSI_LOWLEVEL=y
+CONFIG_ISCSI_TCP=m
+# CONFIG_SCSI_DEBUG is not set
+CONFIG_MVME147_SCSI=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+# CONFIG_MD_RAID10 is not set
+CONFIG_MD_RAID456=m
+CONFIG_MD_RAID5_RESHAPE=y
+CONFIG_MD_MULTIPATH=m
+# CONFIG_MD_FAULTY is not set
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_ZERO=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_MULTIPATH_EMC=m
+CONFIG_DM_MULTIPATH_RDAC=m
+CONFIG_DM_MULTIPATH_HP=m
+# CONFIG_DM_DELAY is not set
+CONFIG_DM_UEVENT=y
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+CONFIG_DUMMY=m
+# CONFIG_BONDING is not set
+CONFIG_MACVLAN=m
+CONFIG_EQUALIZER=m
+# CONFIG_TUN is not set
+CONFIG_VETH=m
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+CONFIG_MVME147_NET=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
 
 #
-# Wan interfaces
+# Wireless LAN
 #
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 # CONFIG_WAN is not set
 CONFIG_PPP=m
 # CONFIG_PPP_MULTILINK is not set
@@ -440,28 +550,28 @@ CONFIG_PPP_ASYNC=m
 CONFIG_PPP_SYNC_TTY=m
 CONFIG_PPP_DEFLATE=m
 CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
 CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
 CONFIG_SLIP=m
 CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLHC=m
 CONFIG_SLIP_SMART=y
 CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_SHAPER=m
 CONFIG_NETCONSOLE=m
-
-#
-# ISDN subsystem
-#
+CONFIG_NETCONSOLE_DYNAMIC=y
+CONFIG_NETPOLL=y
+# CONFIG_NETPOLL_TRAP is not set
+CONFIG_NET_POLL_CONTROLLER=y
 # CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
 # CONFIG_PHONE is not set
 
 #
 # Input device support
 #
 CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=m
+# CONFIG_INPUT_POLLDEV is not set
 
 #
 # Userland interfaces
@@ -471,7 +581,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 
@@ -484,11 +593,19 @@ CONFIG_INPUT_KEYBOARD=y
 # CONFIG_KEYBOARD_LKKBD is not set
 # CONFIG_KEYBOARD_XTKBD is not set
 # CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
 CONFIG_INPUT_MOUSE=y
 CONFIG_MOUSE_PS2=m
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
 CONFIG_MOUSE_SERIAL=m
 # CONFIG_MOUSE_VSXXXAA is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 
@@ -496,7 +613,7 @@ CONFIG_MOUSE_SERIAL=m
 # Hardware I/O ports
 #
 CONFIG_SERIO=m
-CONFIG_SERIO_SERPORT=m
+# CONFIG_SERIO_SERPORT is not set
 CONFIG_SERIO_LIBPS2=m
 # CONFIG_SERIO_RAW is not set
 # CONFIG_GAMEPORT is not set
@@ -507,6 +624,7 @@ CONFIG_SERIO_LIBPS2=m
 CONFIG_VT=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -520,112 +638,80 @@ CONFIG_HW_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
+# CONFIG_HW_RANDOM is not set
 CONFIG_GEN_RTC=m
 CONFIG_GEN_RTC_X=y
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
-
-#
-# Ftape, the floppy tape device driver
-#
-# CONFIG_DRM is not set
 # CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
 
 #
-# TPM devices
-#
-
-#
-# I2C support
+# SPI support
 #
-# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
 
 #
-# Dallas's 1-wire bus
+# Sonics Silicon Backplane
 #
-# CONFIG_W1 is not set
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
-# Misc devices
+# Multifunction device drivers
 #
+# CONFIG_MFD_SM501 is not set
 
 #
 # Multimedia devices
 #
 # CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
 
 #
-# Digital Video Broadcasting Devices
+# Graphics support
 #
-# CONFIG_DVB is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
-# Graphics support
+# Display device support
 #
-CONFIG_FB=y
-# CONFIG_FB_CFB_FILLRECT is not set
-# CONFIG_FB_CFB_COPYAREA is not set
-# CONFIG_FB_CFB_IMAGEBLIT is not set
-# CONFIG_FB_SOFT_CURSOR is not set
-# CONFIG_FB_MACMODES is not set
-CONFIG_FB_MODE_HELPERS=y
-# CONFIG_FB_TILEBLITTING is not set
-# CONFIG_FB_S1D13XXX is not set
-# CONFIG_FB_VIRTUAL is not set
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
 #
 CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FONTS is not set
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-
-#
-# Logo configuration
-#
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_MONO=y
-CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
 # Sound
 #
 # CONFIG_SOUND is not set
-
-#
-# USB support
-#
-# CONFIG_USB_ARCH_HAS_HCD is not set
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=m
+# CONFIG_HID_DEBUG is not set
+CONFIG_HIDRAW=y
+# CONFIG_USB_SUPPORT is not set
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_RTC_CLASS is not set
 
 #
-# InfiniBand support
+# Userspace I/O
 #
-# CONFIG_INFINIBAND is not set
+# CONFIG_UIO is not set
 
 #
 # Character devices
@@ -638,10 +724,11 @@ CONFIG_SERIAL_CONSOLE=y
 #
 CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4DEV_FS is not set
 CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
 CONFIG_REISERFS_FS=m
 # CONFIG_REISERFS_CHECK is not set
 # CONFIG_REISERFS_PROC_INFO is not set
@@ -652,25 +739,29 @@ CONFIG_JFS_FS=m
 # CONFIG_JFS_DEBUG is not set
 # CONFIG_JFS_STATISTICS is not set
 CONFIG_FS_POSIX_ACL=y
-
-#
-# XFS support
-#
 CONFIG_XFS_FS=m
-CONFIG_XFS_EXPORT=y
-# CONFIG_XFS_RT is not set
 # CONFIG_XFS_QUOTA is not set
 # CONFIG_XFS_SECURITY is not set
 # CONFIG_XFS_POSIX_ACL is not set
-CONFIG_MINIX_FS=y
-# CONFIG_ROMFS_FS is not set
+# CONFIG_XFS_RT is not set
+CONFIG_GFS2_FS=m
+CONFIG_GFS2_FS_LOCKING_NOLOCK=m
+CONFIG_GFS2_FS_LOCKING_DLM=m
+CONFIG_OCFS2_FS=m
+# CONFIG_OCFS2_DEBUG_MASKLOG is not set
+# CONFIG_OCFS2_DEBUG_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
 CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
 # CONFIG_QFMT_V1 is not set
 # CONFIG_QFMT_V2 is not set
 CONFIG_QUOTACTL=y
-CONFIG_DNOTIFY=y
 CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
+CONFIG_FUSE_FS=m
 
 #
 # CD-ROM/DVD Filesystems
@@ -678,7 +769,6 @@ CONFIG_AUTOFS4_FS=m
 CONFIG_ISO9660_FS=y
 CONFIG_JOLIET=y
 CONFIG_ZISOFS=y
-CONFIG_ZISOFS_FS=y
 CONFIG_UDF_FS=m
 CONFIG_UDF_NLS=y
 
@@ -697,15 +787,12 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 #
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
 CONFIG_SYSFS=y
-CONFIG_DEVFS_FS=y
-# CONFIG_DEVFS_MOUNT is not set
-# CONFIG_DEVFS_DEBUG is not set
-# CONFIG_DEVPTS_FS_XATTR is not set
 CONFIG_TMPFS=y
-# CONFIG_TMPFS_XATTR is not set
+# CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
+CONFIG_CONFIGFS_FS=m
 
 #
 # Miscellaneous filesystems
@@ -719,44 +806,40 @@ CONFIG_HFSPLUS_FS=m
 # CONFIG_EFS_FS is not set
 CONFIG_CRAMFS=m
 # CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=y
 CONFIG_HPFS_FS=m
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 CONFIG_SYSV_FS=m
 CONFIG_UFS_FS=m
 # CONFIG_UFS_FS_WRITE is not set
-
-#
-# Network File Systems
-#
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
 # CONFIG_NFS_DIRECTIO is not set
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
-CONFIG_NFSD_V4=y
+# CONFIG_NFSD_V3_ACL is not set
+# CONFIG_NFSD_V4 is not set
 CONFIG_NFSD_TCP=y
 CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=m
+CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
+CONFIG_SUNRPC_BIND34=y
 CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
 CONFIG_SMB_NLS_DEFAULT=y
 CONFIG_SMB_NLS_REMOTE="cp437"
 # CONFIG_CIFS is not set
-CONFIG_NCP_FS=m
-# CONFIG_NCPFS_PACKET_SIGNING is not set
-# CONFIG_NCPFS_IOCTL_LOCKING is not set
-# CONFIG_NCPFS_STRONG is not set
-# CONFIG_NCPFS_NFS_NS is not set
-# CONFIG_NCPFS_OS2_NS is not set
-# CONFIG_NCPFS_SMALLDOS is not set
-CONFIG_NCPFS_NLS=y
-# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_NCP_FS is not set
 CONFIG_CODA_FS=m
 # CONFIG_CODA_FS_OLD_API is not set
 # CONFIG_AFS_FS is not set
@@ -766,10 +849,7 @@ CONFIG_CODA_FS=m
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
+CONFIG_SYSV68_PARTITION=y
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=y
@@ -810,35 +890,42 @@ CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
 CONFIG_NLS_UTF8=m
+CONFIG_DLM=m
+# CONFIG_DLM_DEBUG is not set
 
 #
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
-CONFIG_DEBUG_KERNEL=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_MAGIC_SYSRQ=y
-CONFIG_LOG_BUF_SHIFT=16
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_INFO is not set
+# CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
-# CONFIG_FRAME_POINTER is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_SAMPLES is not set
 
 #
 # Security options
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_XOR_BLOCKS=m
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_XOR=m
 CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_SEQIV=m
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
 CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=m
 CONFIG_CRYPTO_NULL=m
 CONFIG_CRYPTO_MD4=m
 CONFIG_CRYPTO_MD5=y
@@ -847,9 +934,21 @@ CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
 CONFIG_CRYPTO_WP512=m
 CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_XTS=m
+CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_CRYPTD=m
 CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
 CONFIG_CRYPTO_BLOWFISH=m
 CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
 CONFIG_CRYPTO_SERPENT=m
 CONFIG_CRYPTO_AES=m
 CONFIG_CRYPTO_CAST5=m
@@ -858,20 +957,35 @@ CONFIG_CRYPTO_TEA=m
 CONFIG_CRYPTO_ARC4=m
 CONFIG_CRYPTO_KHAZAD=m
 CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SALSA20=m
 CONFIG_CRYPTO_DEFLATE=m
 CONFIG_CRYPTO_MICHAEL_MIC=m
 CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_CAMELLIA=m
 CONFIG_CRYPTO_TEST=m
-
-#
-# Hardware crypto devices
-#
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_LZO=m
+# CONFIG_CRYPTO_HW is not set
 
 #
 # Library routines
 #
+CONFIG_BITREVERSE=y
 CONFIG_CRC_CCITT=m
+CONFIG_CRC16=m
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 CONFIG_LIBCRC32C=m
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=m
+CONFIG_LZO_COMPRESS=m
+CONFIG_LZO_DECOMPRESS=m
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_DMA=y
diff --git a/arch/m68k/configs/mvme16x_defconfig b/arch/m68k/configs/mvme16x_defconfig
index 1d5c46ff3c81..e9ccc774334e 100644
--- a/arch/m68k/configs/mvme16x_defconfig
+++ b/arch/m68k/configs/mvme16x_defconfig
@@ -1,63 +1,111 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc6-m68k
-# Tue Jun  7 20:34:53 2005
+# Linux kernel version: 2.6.25-rc8
+# Wed Apr  2 20:46:19 2008
 #
 CONFIG_M68K=y
 CONFIG_MMU=y
-CONFIG_UID16=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_TIME_LOW_RES=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_NO_IOPORT=y
+# CONFIG_NO_DMA is not set
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_HZ=100
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
-CONFIG_CLEAN_COMPILE=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION="-mvme16x"
+CONFIG_LOCALVERSION_AUTO=y
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_BSD_PROCESS_ACCT=y
 # CONFIG_BSD_PROCESS_ACCT_V3 is not set
-CONFIG_SYSCTL=y
-CONFIG_AUDIT=y
-CONFIG_HOTPLUG=y
-CONFIG_KOBJECT_UEVENT=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_COMPAT_BRK is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+# CONFIG_HAVE_OPROFILE is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_OBSOLETE_MODPARM=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+CONFIG_BLK_DEV_BSG=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
 
 #
 # Platform dependent setup
@@ -85,6 +133,22 @@ CONFIG_M68060=y
 CONFIG_MMU_MOTOROLA=y
 # CONFIG_M68KFPU_EMU is not set
 # CONFIG_ADVANCED is not set
+CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
+CONFIG_NODES_SHIFT=3
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_FLATMEM_MANUAL is not set
+CONFIG_DISCONTIGMEM_MANUAL=y
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_DISCONTIGMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_NEED_MULTIPLE_NODES=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
 
 #
 # General setup
@@ -93,134 +157,11 @@ CONFIG_BINFMT_ELF=y
 CONFIG_BINFMT_AOUT=m
 CONFIG_BINFMT_MISC=m
 CONFIG_PROC_HARDWARE=y
+CONFIG_ZONE_DMA=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 
 #
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
-# CONFIG_DEBUG_DRIVER is not set
-
-#
-# Memory Technology Devices (MTD)
-#
-# CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_CDROM_PKTCDVD_BUFFERS=8
-# CONFIG_CDROM_PKTCDVD_WCACHE is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_ATA_OVER_ETH=m
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-CONFIG_SCSI=y
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=m
-# CONFIG_CHR_DEV_OSST is not set
-CONFIG_BLK_DEV_SR=y
-CONFIG_BLK_DEV_SR_VENDOR=y
-CONFIG_CHR_DEV_SG=m
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-# CONFIG_SCSI_MULTI_LUN is not set
-CONFIG_SCSI_CONSTANTS=y
-# CONFIG_SCSI_LOGGING is not set
-
-#
-# SCSI Transport Attributes
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-
-#
-# SCSI low-level drivers
-#
-# CONFIG_SCSI_SATA is not set
-# CONFIG_SCSI_DEBUG is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-# CONFIG_MD_RAID10 is not set
-CONFIG_MD_RAID5=m
-CONFIG_MD_RAID6=m
-CONFIG_MD_MULTIPATH=m
-# CONFIG_MD_FAULTY is not set
-CONFIG_BLK_DEV_DM=m
-CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
-CONFIG_DM_MIRROR=m
-CONFIG_DM_ZERO=m
-CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_EMC=m
-
-#
-# Fusion MPT device support
-#
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Networking support
+# Networking
 #
 CONFIG_NET=y
 
@@ -230,10 +171,17 @@ CONFIG_NET=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+CONFIG_XFRM_MIGRATE=y
+# CONFIG_XFRM_STATISTICS is not set
 CONFIG_NET_KEY=y
+CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
 # CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
@@ -245,145 +193,199 @@ CONFIG_SYN_COOKIES=y
 CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
 CONFIG_INET_TUNNEL=m
-CONFIG_IP_TCPDIAG=m
-CONFIG_IP_TCPDIAG_IPV6=y
-
-#
-# IP: Virtual Server Configuration
-#
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_INET_LRO=m
+CONFIG_INET_DIAG=m
+CONFIG_INET_TCP_DIAG=m
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
 # CONFIG_IP_VS is not set
 CONFIG_IPV6=m
 CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
 CONFIG_INET6_AH=m
 CONFIG_INET6_ESP=m
 CONFIG_INET6_IPCOMP=m
+# CONFIG_IPV6_MIP6 is not set
+CONFIG_INET6_XFRM_TUNNEL=m
 CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
+CONFIG_IPV6_SIT=m
 CONFIG_IPV6_TUNNEL=m
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_NETWORK_SECMARK is not set
 CONFIG_NETFILTER=y
 # CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+CONFIG_NF_CT_PROTO_GRE=m
+CONFIG_NF_CT_PROTO_SCTP=m
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+# CONFIG_NF_CT_NETLINK is not set
+CONFIG_NETFILTER_XTABLES=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_RATEEST=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
 
 #
 # IP: Netfilter Configuration
 #
-CONFIG_IP_NF_CONNTRACK=m
-# CONFIG_IP_NF_CT_ACCT is not set
-CONFIG_IP_NF_CONNTRACK_MARK=y
-# CONFIG_IP_NF_CT_PROTO_SCTP is not set
-CONFIG_IP_NF_FTP=m
-CONFIG_IP_NF_IRC=m
-CONFIG_IP_NF_TFTP=m
-CONFIG_IP_NF_AMANDA=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
 CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_LIMIT=m
-CONFIG_IP_NF_MATCH_IPRANGE=m
-CONFIG_IP_NF_MATCH_MAC=m
-CONFIG_IP_NF_MATCH_PKTTYPE=m
-CONFIG_IP_NF_MATCH_MARK=m
-CONFIG_IP_NF_MATCH_MULTIPORT=m
-CONFIG_IP_NF_MATCH_TOS=m
 CONFIG_IP_NF_MATCH_RECENT=m
 CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_DSCP=m
-CONFIG_IP_NF_MATCH_AH_ESP=m
-CONFIG_IP_NF_MATCH_LENGTH=m
+CONFIG_IP_NF_MATCH_AH=m
 CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_MATCH_TCPMSS=m
-CONFIG_IP_NF_MATCH_HELPER=m
-CONFIG_IP_NF_MATCH_STATE=m
-CONFIG_IP_NF_MATCH_CONNTRACK=m
-CONFIG_IP_NF_MATCH_OWNER=m
 CONFIG_IP_NF_MATCH_ADDRTYPE=m
-CONFIG_IP_NF_MATCH_REALM=m
-# CONFIG_IP_NF_MATCH_SCTP is not set
-# CONFIG_IP_NF_MATCH_COMMENT is not set
-CONFIG_IP_NF_MATCH_CONNMARK=m
-CONFIG_IP_NF_MATCH_HASHLIMIT=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
 CONFIG_IP_NF_TARGET_LOG=m
 CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_IP_NF_TARGET_TCPMSS=m
-CONFIG_IP_NF_NAT=m
-CONFIG_IP_NF_NAT_NEEDED=y
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
 CONFIG_IP_NF_TARGET_MASQUERADE=m
 CONFIG_IP_NF_TARGET_REDIRECT=m
 CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_SAME=m
-CONFIG_IP_NF_NAT_SNMP_BASIC=m
-CONFIG_IP_NF_NAT_IRC=m
-CONFIG_IP_NF_NAT_FTP=m
-CONFIG_IP_NF_NAT_TFTP=m
-CONFIG_IP_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_SNMP_BASIC=m
+CONFIG_NF_NAT_PROTO_GRE=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+CONFIG_NF_NAT_TFTP=m
+CONFIG_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+CONFIG_NF_NAT_SIP=m
 CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_TOS=m
 CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_DSCP=m
-CONFIG_IP_NF_TARGET_MARK=m
-CONFIG_IP_NF_TARGET_CLASSIFY=m
-CONFIG_IP_NF_TARGET_CONNMARK=m
-# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
 CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_TARGET_NOTRACK=m
 CONFIG_IP_NF_ARPTABLES=m
 CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
 
 #
-# IPv6: Netfilter Configuration (EXPERIMENTAL)
+# IPv6: Netfilter Configuration
 #
+CONFIG_NF_CONNTRACK_IPV6=m
 CONFIG_IP6_NF_QUEUE=m
 CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_MATCH_LIMIT=m
-CONFIG_IP6_NF_MATCH_MAC=m
 CONFIG_IP6_NF_MATCH_RT=m
 CONFIG_IP6_NF_MATCH_OPTS=m
 CONFIG_IP6_NF_MATCH_FRAG=m
 CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_MULTIPORT=m
-CONFIG_IP6_NF_MATCH_OWNER=m
-CONFIG_IP6_NF_MATCH_MARK=m
 CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_MATCH_AHESP=m
-CONFIG_IP6_NF_MATCH_LENGTH=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_MH=m
 CONFIG_IP6_NF_MATCH_EUI64=m
 CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_TARGET_MARK=m
+CONFIG_IP6_NF_TARGET_HL=m
 CONFIG_IP6_NF_RAW=m
-CONFIG_XFRM=y
-CONFIG_XFRM_USER=m
+CONFIG_IP_DCCP=m
+CONFIG_INET_DCCP_DIAG=m
+CONFIG_IP_DCCP_ACKVEC=y
 
 #
-# SCTP Configuration (EXPERIMENTAL)
+# DCCP CCIDs Configuration (EXPERIMENTAL)
 #
+CONFIG_IP_DCCP_CCID2=m
+# CONFIG_IP_DCCP_CCID2_DEBUG is not set
+CONFIG_IP_DCCP_CCID3=m
+# CONFIG_IP_DCCP_CCID3_DEBUG is not set
+CONFIG_IP_DCCP_CCID3_RTO=100
+CONFIG_IP_DCCP_TFRC_LIB=m
 CONFIG_IP_SCTP=m
 # CONFIG_SCTP_DBG_MSG is not set
 # CONFIG_SCTP_DBG_OBJCNT is not set
 # CONFIG_SCTP_HMAC_NONE is not set
 # CONFIG_SCTP_HMAC_SHA1 is not set
 CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 CONFIG_LLC=m
 # CONFIG_LLC2 is not set
-CONFIG_IPX=m
-# CONFIG_IPX_INTERN is not set
+# CONFIG_IPX is not set
 CONFIG_ATALK=m
 # CONFIG_DEV_APPLETALK is not set
 # CONFIG_X25 is not set
 # CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 CONFIG_NET_CLS_ROUTE=y
 
@@ -391,46 +393,156 @@ CONFIG_NET_CLS_ROUTE=y
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
-CONFIG_NETPOLL=y
-# CONFIG_NETPOLL_RX is not set
-# CONFIG_NETPOLL_TRAP is not set
-CONFIG_NET_POLL_CONTROLLER=y
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=m
-# CONFIG_BONDING is not set
-CONFIG_EQUALIZER=m
-# CONFIG_TUN is not set
+# CONFIG_AF_RXRPC is not set
 
 #
-# Ethernet (10 or 100Mbit)
+# Wireless
 #
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=m
-CONFIG_MVME16x_NET=y
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=m
+CONFIG_IEEE80211_CRYPT_CCMP=m
+CONFIG_IEEE80211_CRYPT_TKIP=m
+CONFIG_IEEE80211_SOFTMAC=m
+# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
-# Ethernet (1000 Mbit)
+# Device Drivers
 #
 
 #
-# Ethernet (10000 Mbit)
+# Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=m
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=m
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+CONFIG_ATA_OVER_ETH=m
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=m
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
 
 #
-# Token Ring devices
+# SCSI support type (disk, tape, CD-ROM)
 #
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_ST=m
+CONFIG_CHR_DEV_OSST=m
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_DEV_SR_VENDOR=y
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
 
 #
-# Wireless LAN (non-hamradio)
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
 #
-# CONFIG_NET_RADIO is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+CONFIG_SCSI_CONSTANTS=y
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
 
 #
-# Wan interfaces
+# SCSI Transports
+#
+CONFIG_SCSI_SPI_ATTRS=y
+# CONFIG_SCSI_FC_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=m
+CONFIG_SCSI_SAS_ATTRS=m
+CONFIG_SCSI_SAS_LIBSAS=m
+CONFIG_SCSI_SAS_HOST_SMP=y
+# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
+CONFIG_SCSI_SRP_ATTRS=m
+CONFIG_SCSI_SRP_TGT_ATTRS=y
+CONFIG_SCSI_LOWLEVEL=y
+CONFIG_ISCSI_TCP=m
+CONFIG_53C700_BE_BUS=y
+# CONFIG_SCSI_DEBUG is not set
+CONFIG_MVME16x_SCSI=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+# CONFIG_MD_RAID10 is not set
+CONFIG_MD_RAID456=m
+CONFIG_MD_RAID5_RESHAPE=y
+CONFIG_MD_MULTIPATH=m
+# CONFIG_MD_FAULTY is not set
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_ZERO=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_MULTIPATH_EMC=m
+CONFIG_DM_MULTIPATH_RDAC=m
+CONFIG_DM_MULTIPATH_HP=m
+# CONFIG_DM_DELAY is not set
+CONFIG_DM_UEVENT=y
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+CONFIG_DUMMY=m
+# CONFIG_BONDING is not set
+CONFIG_MACVLAN=m
+CONFIG_EQUALIZER=m
+# CONFIG_TUN is not set
+CONFIG_VETH=m
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+CONFIG_MVME16x_NET=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
 #
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 # CONFIG_WAN is not set
 CONFIG_PPP=m
 # CONFIG_PPP_MULTILINK is not set
@@ -439,28 +551,28 @@ CONFIG_PPP_ASYNC=m
 CONFIG_PPP_SYNC_TTY=m
 CONFIG_PPP_DEFLATE=m
 CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
 CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
 CONFIG_SLIP=m
 CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLHC=m
 CONFIG_SLIP_SMART=y
 CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_SHAPER=m
 CONFIG_NETCONSOLE=m
-
-#
-# ISDN subsystem
-#
+CONFIG_NETCONSOLE_DYNAMIC=y
+CONFIG_NETPOLL=y
+# CONFIG_NETPOLL_TRAP is not set
+CONFIG_NET_POLL_CONTROLLER=y
 # CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
 # CONFIG_PHONE is not set
 
 #
 # Input device support
 #
 CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=m
+# CONFIG_INPUT_POLLDEV is not set
 
 #
 # Userland interfaces
@@ -470,7 +582,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 
@@ -483,11 +594,19 @@ CONFIG_INPUT_KEYBOARD=y
 # CONFIG_KEYBOARD_LKKBD is not set
 # CONFIG_KEYBOARD_XTKBD is not set
 # CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
 CONFIG_INPUT_MOUSE=y
 CONFIG_MOUSE_PS2=m
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
 CONFIG_MOUSE_SERIAL=m
 # CONFIG_MOUSE_VSXXXAA is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 
@@ -495,7 +614,7 @@ CONFIG_MOUSE_SERIAL=m
 # Hardware I/O ports
 #
 CONFIG_SERIO=m
-CONFIG_SERIO_SERPORT=m
+# CONFIG_SERIO_SERPORT is not set
 CONFIG_SERIO_LIBPS2=m
 # CONFIG_SERIO_RAW is not set
 # CONFIG_GAMEPORT is not set
@@ -506,6 +625,7 @@ CONFIG_SERIO_LIBPS2=m
 CONFIG_VT=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -519,116 +639,85 @@ CONFIG_HW_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
+# CONFIG_HW_RANDOM is not set
 CONFIG_GEN_RTC=m
 CONFIG_GEN_RTC_X=y
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
-
-#
-# Ftape, the floppy tape device driver
-#
-# CONFIG_DRM is not set
 # CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
 
 #
-# TPM devices
+# SPI support
 #
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
 
 #
-# I2C support
+# Sonics Silicon Backplane
 #
-# CONFIG_I2C is not set
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
-# Dallas's 1-wire bus
-#
-# CONFIG_W1 is not set
-
-#
-# Misc devices
+# Multifunction device drivers
 #
+# CONFIG_MFD_SM501 is not set
 
 #
 # Multimedia devices
 #
 # CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
 
 #
-# Digital Video Broadcasting Devices
+# Graphics support
 #
-# CONFIG_DVB is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
-# Graphics support
+# Display device support
 #
-CONFIG_FB=y
-# CONFIG_FB_CFB_FILLRECT is not set
-# CONFIG_FB_CFB_COPYAREA is not set
-# CONFIG_FB_CFB_IMAGEBLIT is not set
-# CONFIG_FB_SOFT_CURSOR is not set
-# CONFIG_FB_MACMODES is not set
-CONFIG_FB_MODE_HELPERS=y
-# CONFIG_FB_TILEBLITTING is not set
-# CONFIG_FB_S1D13XXX is not set
-# CONFIG_FB_VIRTUAL is not set
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
 #
 CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FONTS is not set
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-
-#
-# Logo configuration
-#
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_MONO=y
-CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
 # Sound
 #
 # CONFIG_SOUND is not set
-
-#
-# USB support
-#
-# CONFIG_USB_ARCH_HAS_HCD is not set
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=m
+# CONFIG_HID_DEBUG is not set
+CONFIG_HIDRAW=y
+# CONFIG_USB_SUPPORT is not set
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_RTC_CLASS is not set
 
 #
-# InfiniBand support
+# Userspace I/O
 #
-# CONFIG_INFINIBAND is not set
+# CONFIG_UIO is not set
 
 #
 # Character devices
 #
+CONFIG_SERIAL167=y
 CONFIG_MVME162_SCC=y
 CONFIG_SERIAL_CONSOLE=y
 
@@ -637,10 +726,11 @@ CONFIG_SERIAL_CONSOLE=y
 #
 CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4DEV_FS is not set
 CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
 CONFIG_REISERFS_FS=m
 # CONFIG_REISERFS_CHECK is not set
 # CONFIG_REISERFS_PROC_INFO is not set
@@ -651,25 +741,29 @@ CONFIG_JFS_FS=m
 # CONFIG_JFS_DEBUG is not set
 # CONFIG_JFS_STATISTICS is not set
 CONFIG_FS_POSIX_ACL=y
-
-#
-# XFS support
-#
 CONFIG_XFS_FS=m
-CONFIG_XFS_EXPORT=y
-# CONFIG_XFS_RT is not set
 # CONFIG_XFS_QUOTA is not set
 # CONFIG_XFS_SECURITY is not set
 # CONFIG_XFS_POSIX_ACL is not set
-CONFIG_MINIX_FS=y
-# CONFIG_ROMFS_FS is not set
+# CONFIG_XFS_RT is not set
+CONFIG_GFS2_FS=m
+CONFIG_GFS2_FS_LOCKING_NOLOCK=m
+CONFIG_GFS2_FS_LOCKING_DLM=m
+CONFIG_OCFS2_FS=m
+# CONFIG_OCFS2_DEBUG_MASKLOG is not set
+# CONFIG_OCFS2_DEBUG_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
 CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
 # CONFIG_QFMT_V1 is not set
 # CONFIG_QFMT_V2 is not set
 CONFIG_QUOTACTL=y
-CONFIG_DNOTIFY=y
 CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
+CONFIG_FUSE_FS=m
 
 #
 # CD-ROM/DVD Filesystems
@@ -677,7 +771,6 @@ CONFIG_AUTOFS4_FS=m
 CONFIG_ISO9660_FS=y
 CONFIG_JOLIET=y
 CONFIG_ZISOFS=y
-CONFIG_ZISOFS_FS=y
 CONFIG_UDF_FS=m
 CONFIG_UDF_NLS=y
 
@@ -696,15 +789,12 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 #
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
 CONFIG_SYSFS=y
-CONFIG_DEVFS_FS=y
-# CONFIG_DEVFS_MOUNT is not set
-# CONFIG_DEVFS_DEBUG is not set
-# CONFIG_DEVPTS_FS_XATTR is not set
 CONFIG_TMPFS=y
-# CONFIG_TMPFS_XATTR is not set
+# CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
+CONFIG_CONFIGFS_FS=m
 
 #
 # Miscellaneous filesystems
@@ -718,44 +808,40 @@ CONFIG_HFSPLUS_FS=m
 # CONFIG_EFS_FS is not set
 CONFIG_CRAMFS=m
 # CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=y
 CONFIG_HPFS_FS=m
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 CONFIG_SYSV_FS=m
 CONFIG_UFS_FS=m
 # CONFIG_UFS_FS_WRITE is not set
-
-#
-# Network File Systems
-#
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
 # CONFIG_NFS_DIRECTIO is not set
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
-CONFIG_NFSD_V4=y
+# CONFIG_NFSD_V3_ACL is not set
+# CONFIG_NFSD_V4 is not set
 CONFIG_NFSD_TCP=y
 CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=m
+CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
+CONFIG_SUNRPC_BIND34=y
 CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
 CONFIG_SMB_NLS_DEFAULT=y
 CONFIG_SMB_NLS_REMOTE="cp437"
 # CONFIG_CIFS is not set
-CONFIG_NCP_FS=m
-# CONFIG_NCPFS_PACKET_SIGNING is not set
-# CONFIG_NCPFS_IOCTL_LOCKING is not set
-# CONFIG_NCPFS_STRONG is not set
-# CONFIG_NCPFS_NFS_NS is not set
-# CONFIG_NCPFS_OS2_NS is not set
-# CONFIG_NCPFS_SMALLDOS is not set
-CONFIG_NCPFS_NLS=y
-# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_NCP_FS is not set
 CONFIG_CODA_FS=m
 # CONFIG_CODA_FS_OLD_API is not set
 # CONFIG_AFS_FS is not set
@@ -765,10 +851,7 @@ CONFIG_CODA_FS=m
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
+CONFIG_SYSV68_PARTITION=y
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=y
@@ -809,35 +892,42 @@ CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
 CONFIG_NLS_UTF8=m
+CONFIG_DLM=m
+# CONFIG_DLM_DEBUG is not set
 
 #
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
-CONFIG_DEBUG_KERNEL=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_MAGIC_SYSRQ=y
-CONFIG_LOG_BUF_SHIFT=16
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_INFO is not set
+# CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
-# CONFIG_FRAME_POINTER is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_SAMPLES is not set
 
 #
 # Security options
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_XOR_BLOCKS=m
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_XOR=m
 CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_SEQIV=m
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
 CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=m
 CONFIG_CRYPTO_NULL=m
 CONFIG_CRYPTO_MD4=m
 CONFIG_CRYPTO_MD5=y
@@ -846,9 +936,21 @@ CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
 CONFIG_CRYPTO_WP512=m
 CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_XTS=m
+CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_CRYPTD=m
 CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
 CONFIG_CRYPTO_BLOWFISH=m
 CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
 CONFIG_CRYPTO_SERPENT=m
 CONFIG_CRYPTO_AES=m
 CONFIG_CRYPTO_CAST5=m
@@ -857,20 +959,35 @@ CONFIG_CRYPTO_TEA=m
 CONFIG_CRYPTO_ARC4=m
 CONFIG_CRYPTO_KHAZAD=m
 CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SALSA20=m
 CONFIG_CRYPTO_DEFLATE=m
 CONFIG_CRYPTO_MICHAEL_MIC=m
 CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_CAMELLIA=m
 CONFIG_CRYPTO_TEST=m
-
-#
-# Hardware crypto devices
-#
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_LZO=m
+# CONFIG_CRYPTO_HW is not set
 
 #
 # Library routines
 #
+CONFIG_BITREVERSE=y
 CONFIG_CRC_CCITT=m
+CONFIG_CRC16=m
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 CONFIG_LIBCRC32C=m
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=m
+CONFIG_LZO_COMPRESS=m
+CONFIG_LZO_DECOMPRESS=m
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_DMA=y
diff --git a/arch/m68k/configs/q40_defconfig b/arch/m68k/configs/q40_defconfig
index 856238634d42..165658fe73eb 100644
--- a/arch/m68k/configs/q40_defconfig
+++ b/arch/m68k/configs/q40_defconfig
@@ -1,63 +1,112 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc6-m68k
-# Tue Jun  7 20:34:58 2005
+# Linux kernel version: 2.6.25-rc8
+# Wed Apr  2 20:46:20 2008
 #
 CONFIG_M68K=y
 CONFIG_MMU=y
-CONFIG_UID16=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_TIME_LOW_RES=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_NO_IOPORT=y
+# CONFIG_NO_DMA is not set
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_HZ=100
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
-CONFIG_CLEAN_COMPILE=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION="-q40"
+CONFIG_LOCALVERSION_AUTO=y
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_BSD_PROCESS_ACCT=y
 # CONFIG_BSD_PROCESS_ACCT_V3 is not set
-CONFIG_SYSCTL=y
-CONFIG_AUDIT=y
-CONFIG_HOTPLUG=y
-CONFIG_KOBJECT_UEVENT=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_COMPAT_BRK is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+# CONFIG_HAVE_OPROFILE is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_OBSOLETE_MODPARM=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+CONFIG_BLK_DEV_BSG=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
 
 #
 # Platform dependent setup
@@ -80,10 +129,24 @@ CONFIG_Q40=y
 CONFIG_M68040=y
 CONFIG_M68060=y
 CONFIG_MMU_MOTOROLA=y
-CONFIG_M68KFPU_EMU=y
-CONFIG_M68KFPU_EMU_EXTRAPREC=y
-# CONFIG_M68KFPU_EMU_ONLY is not set
+# CONFIG_M68KFPU_EMU is not set
 # CONFIG_ADVANCED is not set
+CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
+CONFIG_NODES_SHIFT=3
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_FLATMEM_MANUAL is not set
+CONFIG_DISCONTIGMEM_MANUAL=y
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_DISCONTIGMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_NEED_MULTIPLE_NODES=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
 
 #
 # General setup
@@ -91,41 +154,282 @@ CONFIG_M68KFPU_EMU_EXTRAPREC=y
 CONFIG_BINFMT_ELF=y
 CONFIG_BINFMT_AOUT=m
 CONFIG_BINFMT_MISC=m
-# CONFIG_HEARTBEAT is not set
+CONFIG_HEARTBEAT=y
 CONFIG_PROC_HARDWARE=y
 CONFIG_ISA=y
 CONFIG_GENERIC_ISA_DMA=y
+CONFIG_ZONE_DMA=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 
 #
-# Device Drivers
+# Networking
 #
+CONFIG_NET=y
 
 #
-# Generic Driver Options
+# Networking options
 #
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
-# CONFIG_DEBUG_DRIVER is not set
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+CONFIG_XFRM_MIGRATE=y
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_NET_KEY=y
+CONFIG_NET_KEY_MIGRATE=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE=m
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_INET_LRO=m
+CONFIG_INET_DIAG=m
+CONFIG_INET_TCP_DIAG=m
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IP_VS is not set
+CONFIG_IPV6=m
+CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+# CONFIG_IPV6_MIP6 is not set
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_TUNNEL=m
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+CONFIG_NF_CT_PROTO_GRE=m
+CONFIG_NF_CT_PROTO_SCTP=m
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+# CONFIG_NF_CT_NETLINK is not set
+CONFIG_NETFILTER_XTABLES=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_RATEEST=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
 
 #
-# Memory Technology Devices (MTD)
+# IP: Netfilter Configuration
 #
-# CONFIG_MTD is not set
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_RECENT=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_MATCH_ADDRTYPE=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_NF_NAT_SNMP_BASIC=m
+CONFIG_NF_NAT_PROTO_GRE=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+CONFIG_NF_NAT_TFTP=m
+CONFIG_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+CONFIG_NF_NAT_SIP=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
 
 #
-# Parallel port support
+# IPv6: Netfilter Configuration
 #
-# CONFIG_PARPORT is not set
+CONFIG_NF_CONNTRACK_IPV6=m
+CONFIG_IP6_NF_QUEUE=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_HL=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_TARGET_HL=m
+CONFIG_IP6_NF_RAW=m
+CONFIG_IP_DCCP=m
+CONFIG_INET_DCCP_DIAG=m
+CONFIG_IP_DCCP_ACKVEC=y
 
 #
-# Plug and Play support
+# DCCP CCIDs Configuration (EXPERIMENTAL)
 #
-# CONFIG_PNP is not set
+CONFIG_IP_DCCP_CCID2=m
+# CONFIG_IP_DCCP_CCID2_DEBUG is not set
+CONFIG_IP_DCCP_CCID3=m
+# CONFIG_IP_DCCP_CCID3_DEBUG is not set
+CONFIG_IP_DCCP_CCID3_RTO=100
+CONFIG_IP_DCCP_TFRC_LIB=m
+CONFIG_IP_SCTP=m
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+CONFIG_ATALK=m
+# CONFIG_DEV_APPLETALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+CONFIG_NET_CLS_ROUTE=y
 
 #
-# Block devices
+# Network testing
 #
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=m
+CONFIG_IEEE80211_CRYPT_CCMP=m
+CONFIG_IEEE80211_CRYPT_TKIP=m
+CONFIG_IEEE80211_SOFTMAC=m
+# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=m
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=m
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+# CONFIG_PNP is not set
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_FD is not set
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=y
@@ -134,54 +438,64 @@ CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_BLK_DEV_XIP is not set
 CONFIG_CDROM_PKTCDVD=m
 CONFIG_CDROM_PKTCDVD_BUFFERS=8
 # CONFIG_CDROM_PKTCDVD_WCACHE is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
 CONFIG_ATA_OVER_ETH=m
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
 CONFIG_IDE=y
 CONFIG_BLK_DEV_IDE=y
 
 #
-# Please see Documentation/ide.txt for help/info on IDE drives
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
 #
 # CONFIG_BLK_DEV_IDE_SATA is not set
 CONFIG_BLK_DEV_IDEDISK=y
 # CONFIG_IDEDISK_MULTI_MODE is not set
 CONFIG_BLK_DEV_IDECD=y
-CONFIG_BLK_DEV_IDETAPE=m
+CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
+# CONFIG_BLK_DEV_IDETAPE is not set
 CONFIG_BLK_DEV_IDEFLOPPY=m
 # CONFIG_BLK_DEV_IDESCSI is not set
 # CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
 
 #
 # IDE chipset support/bugfixes
 #
-CONFIG_IDE_GENERIC=y
-# CONFIG_IDE_ARM is not set
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
 CONFIG_BLK_DEV_Q40IDE=y
-# CONFIG_IDE_CHIPSETS is not set
+
+#
+# Other IDE chipsets support
+#
+
+#
+# Note: most of these also require special kernel boot parameters
+#
+# CONFIG_BLK_DEV_4DRIVES is not set
+# CONFIG_BLK_DEV_ALI14XX is not set
+# CONFIG_BLK_DEV_DTC2278 is not set
+# CONFIG_BLK_DEV_HT6560B is not set
+# CONFIG_BLK_DEV_QD65XX is not set
+# CONFIG_BLK_DEV_UMC8672 is not set
 # CONFIG_BLK_DEV_IDEDMA is not set
-# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_IDE_ARCH_OBSOLETE_INIT is not set
 # CONFIG_BLK_DEV_HD is not set
 
 #
 # SCSI device support
 #
+CONFIG_RAID_ATTRS=m
 CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=m
+# CONFIG_SCSI_NETLINK is not set
 CONFIG_SCSI_PROC_FS=y
 
 #
@@ -189,10 +503,11 @@ CONFIG_SCSI_PROC_FS=y
 #
 CONFIG_BLK_DEV_SD=y
 CONFIG_CHR_DEV_ST=m
-# CONFIG_CHR_DEV_OSST is not set
+CONFIG_CHR_DEV_OSST=m
 CONFIG_BLK_DEV_SR=y
 CONFIG_BLK_DEV_SR_VENDOR=y
 CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
 
 #
 # Some SCSI devices (e.g. CD jukebox) support multiple LUNs
@@ -200,266 +515,71 @@ CONFIG_CHR_DEV_SG=m
 # CONFIG_SCSI_MULTI_LUN is not set
 CONFIG_SCSI_CONSTANTS=y
 # CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
 
 #
-# SCSI Transport Attributes
+# SCSI Transports
 #
 # CONFIG_SCSI_SPI_ATTRS is not set
 # CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-
-#
-# SCSI low-level drivers
-#
+CONFIG_SCSI_ISCSI_ATTRS=m
+CONFIG_SCSI_SAS_ATTRS=m
+CONFIG_SCSI_SAS_LIBSAS=m
+CONFIG_SCSI_SAS_HOST_SMP=y
+# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
+CONFIG_SCSI_SRP_ATTRS=m
+CONFIG_SCSI_SRP_TGT_ATTRS=y
+CONFIG_SCSI_LOWLEVEL=y
+CONFIG_ISCSI_TCP=m
 # CONFIG_SCSI_AHA152X is not set
 # CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_ADVANSYS is not set
 # CONFIG_SCSI_IN2000 is not set
-# CONFIG_SCSI_SATA is not set
 # CONFIG_SCSI_DTC3280 is not set
 # CONFIG_SCSI_FUTURE_DOMAIN is not set
 # CONFIG_SCSI_GENERIC_NCR5380 is not set
 # CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
 # CONFIG_SCSI_NCR53C406A is not set
 # CONFIG_SCSI_PAS16 is not set
-# CONFIG_SCSI_PSI240I is not set
 # CONFIG_SCSI_QLOGIC_FAS is not set
 # CONFIG_SCSI_SYM53C416 is not set
 # CONFIG_SCSI_T128 is not set
 # CONFIG_SCSI_DEBUG is not set
-
-#
-# Old CD-ROM drivers (not SCSI, not IDE)
-#
-# CONFIG_CD_NO_IDESCSI is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
 CONFIG_MD=y
 CONFIG_BLK_DEV_MD=m
 CONFIG_MD_LINEAR=m
 CONFIG_MD_RAID0=m
 CONFIG_MD_RAID1=m
 # CONFIG_MD_RAID10 is not set
-CONFIG_MD_RAID5=m
-CONFIG_MD_RAID6=m
+CONFIG_MD_RAID456=m
+CONFIG_MD_RAID5_RESHAPE=y
 CONFIG_MD_MULTIPATH=m
 # CONFIG_MD_FAULTY is not set
 CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
 CONFIG_DM_CRYPT=m
 CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_MIRROR=m
 CONFIG_DM_ZERO=m
 CONFIG_DM_MULTIPATH=m
 CONFIG_DM_MULTIPATH_EMC=m
-
-#
-# Fusion MPT device support
-#
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Networking support
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_NET_IPIP=m
-CONFIG_NET_IPGRE=m
-# CONFIG_ARPD is not set
-CONFIG_SYN_COOKIES=y
-CONFIG_INET_AH=m
-CONFIG_INET_ESP=m
-CONFIG_INET_IPCOMP=m
-CONFIG_INET_TUNNEL=m
-CONFIG_IP_TCPDIAG=m
-CONFIG_IP_TCPDIAG_IPV6=y
-
-#
-# IP: Virtual Server Configuration
-#
-# CONFIG_IP_VS is not set
-CONFIG_IPV6=m
-CONFIG_IPV6_PRIVACY=y
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_IPCOMP=m
-CONFIG_INET6_TUNNEL=m
-CONFIG_IPV6_TUNNEL=m
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
-
-#
-# IP: Netfilter Configuration
-#
-CONFIG_IP_NF_CONNTRACK=m
-# CONFIG_IP_NF_CT_ACCT is not set
-CONFIG_IP_NF_CONNTRACK_MARK=y
-# CONFIG_IP_NF_CT_PROTO_SCTP is not set
-CONFIG_IP_NF_FTP=m
-CONFIG_IP_NF_IRC=m
-CONFIG_IP_NF_TFTP=m
-CONFIG_IP_NF_AMANDA=m
-CONFIG_IP_NF_QUEUE=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_LIMIT=m
-CONFIG_IP_NF_MATCH_IPRANGE=m
-CONFIG_IP_NF_MATCH_MAC=m
-CONFIG_IP_NF_MATCH_PKTTYPE=m
-CONFIG_IP_NF_MATCH_MARK=m
-CONFIG_IP_NF_MATCH_MULTIPORT=m
-CONFIG_IP_NF_MATCH_TOS=m
-CONFIG_IP_NF_MATCH_RECENT=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_DSCP=m
-CONFIG_IP_NF_MATCH_AH_ESP=m
-CONFIG_IP_NF_MATCH_LENGTH=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_MATCH_TCPMSS=m
-CONFIG_IP_NF_MATCH_HELPER=m
-CONFIG_IP_NF_MATCH_STATE=m
-CONFIG_IP_NF_MATCH_CONNTRACK=m
-CONFIG_IP_NF_MATCH_OWNER=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
-CONFIG_IP_NF_MATCH_REALM=m
-# CONFIG_IP_NF_MATCH_SCTP is not set
-# CONFIG_IP_NF_MATCH_COMMENT is not set
-CONFIG_IP_NF_MATCH_CONNMARK=m
-CONFIG_IP_NF_MATCH_HASHLIMIT=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_LOG=m
-CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_IP_NF_TARGET_TCPMSS=m
-CONFIG_IP_NF_NAT=m
-CONFIG_IP_NF_NAT_NEEDED=y
-CONFIG_IP_NF_TARGET_MASQUERADE=m
-CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_SAME=m
-CONFIG_IP_NF_NAT_SNMP_BASIC=m
-CONFIG_IP_NF_NAT_IRC=m
-CONFIG_IP_NF_NAT_FTP=m
-CONFIG_IP_NF_NAT_TFTP=m
-CONFIG_IP_NF_NAT_AMANDA=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_TOS=m
-CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_DSCP=m
-CONFIG_IP_NF_TARGET_MARK=m
-CONFIG_IP_NF_TARGET_CLASSIFY=m
-CONFIG_IP_NF_TARGET_CONNMARK=m
-# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_TARGET_NOTRACK=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
-
-#
-# IPv6: Netfilter Configuration (EXPERIMENTAL)
-#
-CONFIG_IP6_NF_QUEUE=m
-CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_MATCH_LIMIT=m
-CONFIG_IP6_NF_MATCH_MAC=m
-CONFIG_IP6_NF_MATCH_RT=m
-CONFIG_IP6_NF_MATCH_OPTS=m
-CONFIG_IP6_NF_MATCH_FRAG=m
-CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_MULTIPORT=m
-CONFIG_IP6_NF_MATCH_OWNER=m
-CONFIG_IP6_NF_MATCH_MARK=m
-CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_MATCH_AHESP=m
-CONFIG_IP6_NF_MATCH_LENGTH=m
-CONFIG_IP6_NF_MATCH_EUI64=m
-CONFIG_IP6_NF_FILTER=m
-CONFIG_IP6_NF_TARGET_LOG=m
-CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_TARGET_MARK=m
-CONFIG_IP6_NF_RAW=m
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-CONFIG_IP_SCTP=m
-# CONFIG_SCTP_DBG_MSG is not set
-# CONFIG_SCTP_DBG_OBJCNT is not set
-# CONFIG_SCTP_HMAC_NONE is not set
-# CONFIG_SCTP_HMAC_SHA1 is not set
-CONFIG_SCTP_HMAC_MD5=y
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-CONFIG_LLC=m
-# CONFIG_LLC2 is not set
-CONFIG_IPX=m
-# CONFIG_IPX_INTERN is not set
-CONFIG_ATALK=m
-# CONFIG_DEV_APPLETALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-CONFIG_NET_CLS_ROUTE=y
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-CONFIG_NETPOLL=y
-# CONFIG_NETPOLL_RX is not set
-# CONFIG_NETPOLL_TRAP is not set
-CONFIG_NET_POLL_CONTROLLER=y
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
+CONFIG_DM_MULTIPATH_RDAC=m
+CONFIG_DM_MULTIPATH_HP=m
+# CONFIG_DM_DELAY is not set
+CONFIG_DM_UEVENT=y
 CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
 CONFIG_DUMMY=m
 # CONFIG_BONDING is not set
+CONFIG_MACVLAN=m
 CONFIG_EQUALIZER=m
 # CONFIG_TUN is not set
-
-#
-# ARCnet devices
-#
+CONFIG_VETH=m
 # CONFIG_ARCNET is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
+# CONFIG_PHYLIB is not set
 CONFIG_NET_ETHERNET=y
-CONFIG_MII=m
+# CONFIG_MII is not set
 # CONFIG_NET_VENDOR_3COM is not set
 # CONFIG_NET_VENDOR_SMC is not set
 # CONFIG_NET_VENDOR_RACAL is not set
@@ -468,30 +588,21 @@ CONFIG_MII=m
 # CONFIG_HP100 is not set
 # CONFIG_NET_ISA is not set
 CONFIG_NE2000=m
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
 # CONFIG_NET_PCI is not set
-# CONFIG_NET_POCKET is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
-#
-
-#
-# Token Ring devices
-#
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
 # CONFIG_TR is not set
 
 #
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# Wan interfaces
+# Wireless LAN
 #
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 # CONFIG_WAN is not set
 CONFIG_PPP=m
 # CONFIG_PPP_MULTILINK is not set
@@ -500,28 +611,28 @@ CONFIG_PPP_ASYNC=m
 CONFIG_PPP_SYNC_TTY=m
 CONFIG_PPP_DEFLATE=m
 CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
 CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
 CONFIG_SLIP=m
 CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLHC=m
 CONFIG_SLIP_SMART=y
 CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_SHAPER=m
 CONFIG_NETCONSOLE=m
-
-#
-# ISDN subsystem
-#
+CONFIG_NETCONSOLE_DYNAMIC=y
+CONFIG_NETPOLL=y
+# CONFIG_NETPOLL_TRAP is not set
+CONFIG_NET_POLL_CONTROLLER=y
 # CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
 # CONFIG_PHONE is not set
 
 #
 # Input device support
 #
 CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=m
+# CONFIG_INPUT_POLLDEV is not set
 
 #
 # Userland interfaces
@@ -531,7 +642,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 
@@ -544,22 +654,32 @@ CONFIG_INPUT_KEYBOARD=y
 # CONFIG_KEYBOARD_LKKBD is not set
 # CONFIG_KEYBOARD_XTKBD is not set
 # CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
 CONFIG_INPUT_MOUSE=y
 CONFIG_MOUSE_PS2=m
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
 CONFIG_MOUSE_SERIAL=m
 # CONFIG_MOUSE_INPORT is not set
 # CONFIG_MOUSE_LOGIBM is not set
 # CONFIG_MOUSE_PC110PAD is not set
 # CONFIG_MOUSE_VSXXXAA is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_M68K_BEEP=m
+# CONFIG_INPUT_UINPUT is not set
 
 #
 # Hardware I/O ports
 #
 CONFIG_SERIO=m
-CONFIG_SERIO_SERPORT=m
+# CONFIG_SERIO_SERPORT is not set
 CONFIG_SERIO_Q40KBD=m
 CONFIG_SERIO_LIBPS2=m
 # CONFIG_SERIO_RAW is not set
@@ -571,6 +691,7 @@ CONFIG_SERIO_LIBPS2=m
 CONFIG_VT=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -584,115 +705,117 @@ CONFIG_HW_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
+# CONFIG_HW_RANDOM is not set
 CONFIG_GEN_RTC=m
 CONFIG_GEN_RTC_X=y
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
-
-#
-# Ftape, the floppy tape device driver
-#
-# CONFIG_DRM is not set
 # CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
-
-#
-# I2C support
-#
+# CONFIG_TCG_TPM is not set
 # CONFIG_I2C is not set
 
 #
-# Dallas's 1-wire bus
+# SPI support
 #
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
 # CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
 
 #
-# Misc devices
+# Sonics Silicon Backplane
 #
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
-# Multimedia devices
+# Multifunction device drivers
 #
-# CONFIG_VIDEO_DEV is not set
+# CONFIG_MFD_SM501 is not set
 
 #
-# Digital Video Broadcasting Devices
+# Multimedia devices
 #
-# CONFIG_DVB is not set
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
 
 #
 # Graphics support
 #
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_SOFT_CURSOR=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
-CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
 # CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
 CONFIG_FB_Q40=y
+# CONFIG_FB_UVESA is not set
 # CONFIG_FB_S1D13XXX is not set
 # CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
 #
 CONFIG_DUMMY_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
 # CONFIG_FONTS is not set
 CONFIG_FONT_8x8=y
 CONFIG_FONT_8x16=y
-
-#
-# Logo configuration
-#
 CONFIG_LOGO=y
 CONFIG_LOGO_LINUX_MONO=y
 CONFIG_LOGO_LINUX_VGA16=y
 CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
 # Sound
 #
-CONFIG_SOUND=y
-CONFIG_DMASOUND_Q40=y
-CONFIG_DMASOUND=y
-
-#
-# USB support
-#
-# CONFIG_USB_ARCH_HAS_HCD is not set
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
+CONFIG_SOUND=m
+CONFIG_DMASOUND_Q40=m
+CONFIG_DMASOUND=m
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=m
+# CONFIG_HID_DEBUG is not set
+CONFIG_HIDRAW=y
+# CONFIG_USB_SUPPORT is not set
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_RTC_CLASS is not set
 
 #
-# InfiniBand support
+# Userspace I/O
 #
-# CONFIG_INFINIBAND is not set
+# CONFIG_UIO is not set
 
 #
 # Character devices
@@ -703,10 +826,11 @@ CONFIG_DMASOUND=y
 #
 CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4DEV_FS is not set
 CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
 CONFIG_REISERFS_FS=m
 # CONFIG_REISERFS_CHECK is not set
 # CONFIG_REISERFS_PROC_INFO is not set
@@ -717,25 +841,29 @@ CONFIG_JFS_FS=m
 # CONFIG_JFS_DEBUG is not set
 # CONFIG_JFS_STATISTICS is not set
 CONFIG_FS_POSIX_ACL=y
-
-#
-# XFS support
-#
 CONFIG_XFS_FS=m
-CONFIG_XFS_EXPORT=y
-# CONFIG_XFS_RT is not set
 # CONFIG_XFS_QUOTA is not set
 # CONFIG_XFS_SECURITY is not set
 # CONFIG_XFS_POSIX_ACL is not set
-CONFIG_MINIX_FS=y
-# CONFIG_ROMFS_FS is not set
+# CONFIG_XFS_RT is not set
+CONFIG_GFS2_FS=m
+CONFIG_GFS2_FS_LOCKING_NOLOCK=m
+CONFIG_GFS2_FS_LOCKING_DLM=m
+CONFIG_OCFS2_FS=m
+# CONFIG_OCFS2_DEBUG_MASKLOG is not set
+# CONFIG_OCFS2_DEBUG_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
 CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
 # CONFIG_QFMT_V1 is not set
 # CONFIG_QFMT_V2 is not set
 CONFIG_QUOTACTL=y
-CONFIG_DNOTIFY=y
 CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
+CONFIG_FUSE_FS=m
 
 #
 # CD-ROM/DVD Filesystems
@@ -743,7 +871,6 @@ CONFIG_AUTOFS4_FS=m
 CONFIG_ISO9660_FS=y
 CONFIG_JOLIET=y
 CONFIG_ZISOFS=y
-CONFIG_ZISOFS_FS=y
 CONFIG_UDF_FS=m
 CONFIG_UDF_NLS=y
 
@@ -762,13 +889,12 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 #
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
 CONFIG_SYSFS=y
-# CONFIG_DEVFS_FS is not set
-# CONFIG_DEVPTS_FS_XATTR is not set
 CONFIG_TMPFS=y
-# CONFIG_TMPFS_XATTR is not set
+# CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
+CONFIG_CONFIGFS_FS=m
 
 #
 # Miscellaneous filesystems
@@ -782,44 +908,39 @@ CONFIG_HFSPLUS_FS=m
 # CONFIG_EFS_FS is not set
 CONFIG_CRAMFS=m
 # CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=y
 CONFIG_HPFS_FS=m
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 CONFIG_SYSV_FS=m
 CONFIG_UFS_FS=m
-CONFIG_UFS_FS_WRITE=y
-
-#
-# Network File Systems
-#
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
 # CONFIG_NFS_DIRECTIO is not set
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
-CONFIG_NFSD_V4=y
+# CONFIG_NFSD_V3_ACL is not set
+# CONFIG_NFSD_V4 is not set
 CONFIG_NFSD_TCP=y
-CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=m
+CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
+CONFIG_SUNRPC_BIND34=y
 CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
 CONFIG_SMB_NLS_DEFAULT=y
 CONFIG_SMB_NLS_REMOTE="cp437"
 # CONFIG_CIFS is not set
-CONFIG_NCP_FS=m
-# CONFIG_NCPFS_PACKET_SIGNING is not set
-# CONFIG_NCPFS_IOCTL_LOCKING is not set
-# CONFIG_NCPFS_STRONG is not set
-# CONFIG_NCPFS_NFS_NS is not set
-# CONFIG_NCPFS_OS2_NS is not set
-# CONFIG_NCPFS_SMALLDOS is not set
-CONFIG_NCPFS_NLS=y
-# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_NCP_FS is not set
 CONFIG_CODA_FS=m
 # CONFIG_CODA_FS_OLD_API is not set
 # CONFIG_AFS_FS is not set
@@ -829,10 +950,6 @@ CONFIG_CODA_FS=m
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=y
@@ -873,35 +990,42 @@ CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
 CONFIG_NLS_UTF8=m
+CONFIG_DLM=m
+# CONFIG_DLM_DEBUG is not set
 
 #
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
-CONFIG_DEBUG_KERNEL=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_MAGIC_SYSRQ=y
-CONFIG_LOG_BUF_SHIFT=16
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_INFO is not set
+# CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
-# CONFIG_FRAME_POINTER is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_SAMPLES is not set
 
 #
 # Security options
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_XOR_BLOCKS=m
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_XOR=m
 CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_SEQIV=m
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
 CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=m
 CONFIG_CRYPTO_NULL=m
 CONFIG_CRYPTO_MD4=m
 CONFIG_CRYPTO_MD5=y
@@ -910,9 +1034,21 @@ CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
 CONFIG_CRYPTO_WP512=m
 CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_XTS=m
+CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_CRYPTD=m
 CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
 CONFIG_CRYPTO_BLOWFISH=m
 CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
 CONFIG_CRYPTO_SERPENT=m
 CONFIG_CRYPTO_AES=m
 CONFIG_CRYPTO_CAST5=m
@@ -921,20 +1057,35 @@ CONFIG_CRYPTO_TEA=m
 CONFIG_CRYPTO_ARC4=m
 CONFIG_CRYPTO_KHAZAD=m
 CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SALSA20=m
 CONFIG_CRYPTO_DEFLATE=m
 CONFIG_CRYPTO_MICHAEL_MIC=m
 CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_CAMELLIA=m
 CONFIG_CRYPTO_TEST=m
-
-#
-# Hardware crypto devices
-#
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_LZO=m
+# CONFIG_CRYPTO_HW is not set
 
 #
 # Library routines
 #
+CONFIG_BITREVERSE=y
 CONFIG_CRC_CCITT=m
+CONFIG_CRC16=m
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 CONFIG_LIBCRC32C=m
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=m
+CONFIG_LZO_COMPRESS=m
+CONFIG_LZO_DECOMPRESS=m
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_DMA=y
diff --git a/arch/m68k/configs/sun3_defconfig b/arch/m68k/configs/sun3_defconfig
index af903b5c5708..bd2b9c4927c4 100644
--- a/arch/m68k/configs/sun3_defconfig
+++ b/arch/m68k/configs/sun3_defconfig
@@ -1,63 +1,111 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc6-m68k
-# Tue Jun  7 20:35:02 2005
+# Linux kernel version: 2.6.25-rc8
+# Wed Apr  2 20:46:22 2008
 #
 CONFIG_M68K=y
 CONFIG_MMU=y
-CONFIG_UID16=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_TIME_LOW_RES=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_NO_IOPORT=y
+CONFIG_NO_DMA=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_HZ=100
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
-CONFIG_CLEAN_COMPILE=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION="-sun3"
+CONFIG_LOCALVERSION_AUTO=y
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_BSD_PROCESS_ACCT=y
 # CONFIG_BSD_PROCESS_ACCT_V3 is not set
-CONFIG_SYSCTL=y
-CONFIG_AUDIT=y
-CONFIG_HOTPLUG=y
-CONFIG_KOBJECT_UEVENT=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_COMPAT_BRK is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+# CONFIG_HAVE_OPROFILE is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_OBSOLETE_MODPARM=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+CONFIG_BLK_DEV_BSG=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
 
 #
 # Platform dependent setup
@@ -69,10 +117,24 @@ CONFIG_SUN3=y
 #
 CONFIG_M68020=y
 CONFIG_MMU_SUN3=y
-CONFIG_M68KFPU_EMU=y
-CONFIG_M68KFPU_EMU_EXTRAPREC=y
-# CONFIG_M68KFPU_EMU_ONLY is not set
+# CONFIG_M68KFPU_EMU is not set
 # CONFIG_ADVANCED is not set
+CONFIG_SINGLE_MEMORY_CHUNK=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_NEED_MULTIPLE_NODES=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
 
 #
 # General setup
@@ -81,134 +143,11 @@ CONFIG_BINFMT_ELF=y
 CONFIG_BINFMT_AOUT=m
 CONFIG_BINFMT_MISC=m
 CONFIG_PROC_HARDWARE=y
+CONFIG_ZONE_DMA=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 
 #
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
-# CONFIG_DEBUG_DRIVER is not set
-
-#
-# Memory Technology Devices (MTD)
-#
-# CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_CDROM_PKTCDVD_BUFFERS=8
-# CONFIG_CDROM_PKTCDVD_WCACHE is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_ATA_OVER_ETH=m
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-CONFIG_SCSI=y
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=m
-# CONFIG_CHR_DEV_OSST is not set
-CONFIG_BLK_DEV_SR=y
-CONFIG_BLK_DEV_SR_VENDOR=y
-CONFIG_CHR_DEV_SG=m
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-# CONFIG_SCSI_MULTI_LUN is not set
-CONFIG_SCSI_CONSTANTS=y
-# CONFIG_SCSI_LOGGING is not set
-
-#
-# SCSI Transport Attributes
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-
-#
-# SCSI low-level drivers
-#
-# CONFIG_SCSI_SATA is not set
-# CONFIG_SCSI_DEBUG is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-# CONFIG_MD_RAID10 is not set
-CONFIG_MD_RAID5=m
-CONFIG_MD_RAID6=m
-CONFIG_MD_MULTIPATH=m
-# CONFIG_MD_FAULTY is not set
-CONFIG_BLK_DEV_DM=m
-CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
-CONFIG_DM_MIRROR=m
-CONFIG_DM_ZERO=m
-CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_EMC=m
-
-#
-# Fusion MPT device support
-#
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Networking support
+# Networking
 #
 CONFIG_NET=y
 
@@ -218,10 +157,17 @@ CONFIG_NET=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+CONFIG_XFRM_MIGRATE=y
+# CONFIG_XFRM_STATISTICS is not set
 CONFIG_NET_KEY=y
+CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
 # CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
@@ -233,145 +179,199 @@ CONFIG_SYN_COOKIES=y
 CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
 CONFIG_INET_TUNNEL=m
-CONFIG_IP_TCPDIAG=m
-CONFIG_IP_TCPDIAG_IPV6=y
-
-#
-# IP: Virtual Server Configuration
-#
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_INET_LRO=m
+CONFIG_INET_DIAG=m
+CONFIG_INET_TCP_DIAG=m
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
 # CONFIG_IP_VS is not set
 CONFIG_IPV6=m
 CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
 CONFIG_INET6_AH=m
 CONFIG_INET6_ESP=m
 CONFIG_INET6_IPCOMP=m
+# CONFIG_IPV6_MIP6 is not set
+CONFIG_INET6_XFRM_TUNNEL=m
 CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
+CONFIG_IPV6_SIT=m
 CONFIG_IPV6_TUNNEL=m
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_NETWORK_SECMARK is not set
 CONFIG_NETFILTER=y
 # CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+CONFIG_NF_CT_PROTO_GRE=m
+CONFIG_NF_CT_PROTO_SCTP=m
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+# CONFIG_NF_CT_NETLINK is not set
+CONFIG_NETFILTER_XTABLES=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_RATEEST=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
 
 #
 # IP: Netfilter Configuration
 #
-CONFIG_IP_NF_CONNTRACK=m
-# CONFIG_IP_NF_CT_ACCT is not set
-CONFIG_IP_NF_CONNTRACK_MARK=y
-# CONFIG_IP_NF_CT_PROTO_SCTP is not set
-CONFIG_IP_NF_FTP=m
-CONFIG_IP_NF_IRC=m
-CONFIG_IP_NF_TFTP=m
-CONFIG_IP_NF_AMANDA=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
 CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_LIMIT=m
-CONFIG_IP_NF_MATCH_IPRANGE=m
-CONFIG_IP_NF_MATCH_MAC=m
-CONFIG_IP_NF_MATCH_PKTTYPE=m
-CONFIG_IP_NF_MATCH_MARK=m
-CONFIG_IP_NF_MATCH_MULTIPORT=m
-CONFIG_IP_NF_MATCH_TOS=m
 CONFIG_IP_NF_MATCH_RECENT=m
 CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_DSCP=m
-CONFIG_IP_NF_MATCH_AH_ESP=m
-CONFIG_IP_NF_MATCH_LENGTH=m
+CONFIG_IP_NF_MATCH_AH=m
 CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_MATCH_TCPMSS=m
-CONFIG_IP_NF_MATCH_HELPER=m
-CONFIG_IP_NF_MATCH_STATE=m
-CONFIG_IP_NF_MATCH_CONNTRACK=m
-CONFIG_IP_NF_MATCH_OWNER=m
 CONFIG_IP_NF_MATCH_ADDRTYPE=m
-CONFIG_IP_NF_MATCH_REALM=m
-# CONFIG_IP_NF_MATCH_SCTP is not set
-# CONFIG_IP_NF_MATCH_COMMENT is not set
-CONFIG_IP_NF_MATCH_CONNMARK=m
-CONFIG_IP_NF_MATCH_HASHLIMIT=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
 CONFIG_IP_NF_TARGET_LOG=m
 CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_IP_NF_TARGET_TCPMSS=m
-CONFIG_IP_NF_NAT=m
-CONFIG_IP_NF_NAT_NEEDED=y
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
 CONFIG_IP_NF_TARGET_MASQUERADE=m
 CONFIG_IP_NF_TARGET_REDIRECT=m
 CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_SAME=m
-CONFIG_IP_NF_NAT_SNMP_BASIC=m
-CONFIG_IP_NF_NAT_IRC=m
-CONFIG_IP_NF_NAT_FTP=m
-CONFIG_IP_NF_NAT_TFTP=m
-CONFIG_IP_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_SNMP_BASIC=m
+CONFIG_NF_NAT_PROTO_GRE=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+CONFIG_NF_NAT_TFTP=m
+CONFIG_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+CONFIG_NF_NAT_SIP=m
 CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_TOS=m
 CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_DSCP=m
-CONFIG_IP_NF_TARGET_MARK=m
-CONFIG_IP_NF_TARGET_CLASSIFY=m
-CONFIG_IP_NF_TARGET_CONNMARK=m
-# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
 CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_TARGET_NOTRACK=m
 CONFIG_IP_NF_ARPTABLES=m
 CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
 
 #
-# IPv6: Netfilter Configuration (EXPERIMENTAL)
+# IPv6: Netfilter Configuration
 #
+CONFIG_NF_CONNTRACK_IPV6=m
 CONFIG_IP6_NF_QUEUE=m
 CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_MATCH_LIMIT=m
-CONFIG_IP6_NF_MATCH_MAC=m
 CONFIG_IP6_NF_MATCH_RT=m
 CONFIG_IP6_NF_MATCH_OPTS=m
 CONFIG_IP6_NF_MATCH_FRAG=m
 CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_MULTIPORT=m
-CONFIG_IP6_NF_MATCH_OWNER=m
-CONFIG_IP6_NF_MATCH_MARK=m
 CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_MATCH_AHESP=m
-CONFIG_IP6_NF_MATCH_LENGTH=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_MH=m
 CONFIG_IP6_NF_MATCH_EUI64=m
 CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_TARGET_MARK=m
+CONFIG_IP6_NF_TARGET_HL=m
 CONFIG_IP6_NF_RAW=m
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
+CONFIG_IP_DCCP=m
+CONFIG_INET_DCCP_DIAG=m
+CONFIG_IP_DCCP_ACKVEC=y
 
 #
-# SCTP Configuration (EXPERIMENTAL)
+# DCCP CCIDs Configuration (EXPERIMENTAL)
 #
+CONFIG_IP_DCCP_CCID2=m
+# CONFIG_IP_DCCP_CCID2_DEBUG is not set
+CONFIG_IP_DCCP_CCID3=m
+# CONFIG_IP_DCCP_CCID3_DEBUG is not set
+CONFIG_IP_DCCP_CCID3_RTO=100
+CONFIG_IP_DCCP_TFRC_LIB=m
 CONFIG_IP_SCTP=m
 # CONFIG_SCTP_DBG_MSG is not set
 # CONFIG_SCTP_DBG_OBJCNT is not set
 # CONFIG_SCTP_HMAC_NONE is not set
 # CONFIG_SCTP_HMAC_SHA1 is not set
 CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 CONFIG_LLC=m
 # CONFIG_LLC2 is not set
-CONFIG_IPX=m
-# CONFIG_IPX_INTERN is not set
+# CONFIG_IPX is not set
 CONFIG_ATALK=m
 # CONFIG_DEV_APPLETALK is not set
 # CONFIG_X25 is not set
 # CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 CONFIG_NET_CLS_ROUTE=y
 
@@ -379,47 +379,156 @@ CONFIG_NET_CLS_ROUTE=y
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
-CONFIG_NETPOLL=y
-# CONFIG_NETPOLL_RX is not set
-# CONFIG_NETPOLL_TRAP is not set
-CONFIG_NET_POLL_CONTROLLER=y
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=m
-# CONFIG_BONDING is not set
-CONFIG_EQUALIZER=m
-# CONFIG_TUN is not set
+# CONFIG_AF_RXRPC is not set
 
 #
-# Ethernet (10 or 100Mbit)
+# Wireless
 #
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=m
-CONFIG_SUN3LANCE=y
-CONFIG_SUN3_82586=y
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=m
+CONFIG_IEEE80211_CRYPT_CCMP=m
+CONFIG_IEEE80211_CRYPT_TKIP=m
+CONFIG_IEEE80211_SOFTMAC=m
+# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
-# Ethernet (1000 Mbit)
+# Device Drivers
 #
 
 #
-# Ethernet (10000 Mbit)
+# Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=m
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=m
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+CONFIG_ATA_OVER_ETH=m
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
 
 #
-# Token Ring devices
+# SCSI device support
 #
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+# CONFIG_SCSI_DMA is not set
+CONFIG_SCSI_TGT=m
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
 
 #
-# Wireless LAN (non-hamradio)
+# SCSI support type (disk, tape, CD-ROM)
 #
-# CONFIG_NET_RADIO is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_ST=m
+CONFIG_CHR_DEV_OSST=m
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_DEV_SR_VENDOR=y
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
 
 #
-# Wan interfaces
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
 #
+# CONFIG_SCSI_MULTI_LUN is not set
+CONFIG_SCSI_CONSTANTS=y
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+CONFIG_SCSI_SPI_ATTRS=y
+# CONFIG_SCSI_FC_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=m
+CONFIG_SCSI_SAS_ATTRS=m
+CONFIG_SCSI_SAS_LIBSAS=m
+CONFIG_SCSI_SAS_HOST_SMP=y
+# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
+CONFIG_SCSI_SRP_ATTRS=m
+CONFIG_SCSI_SRP_TGT_ATTRS=y
+CONFIG_SCSI_LOWLEVEL=y
+CONFIG_ISCSI_TCP=m
+# CONFIG_SCSI_DEBUG is not set
+CONFIG_SUN3_SCSI=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+# CONFIG_MD_RAID10 is not set
+CONFIG_MD_RAID456=m
+CONFIG_MD_RAID5_RESHAPE=y
+CONFIG_MD_MULTIPATH=m
+# CONFIG_MD_FAULTY is not set
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_ZERO=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_MULTIPATH_EMC=m
+CONFIG_DM_MULTIPATH_RDAC=m
+CONFIG_DM_MULTIPATH_HP=m
+# CONFIG_DM_DELAY is not set
+CONFIG_DM_UEVENT=y
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+CONFIG_DUMMY=m
+# CONFIG_BONDING is not set
+CONFIG_MACVLAN=m
+CONFIG_EQUALIZER=m
+# CONFIG_TUN is not set
+CONFIG_VETH=m
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+CONFIG_SUN3LANCE=y
+CONFIG_SUN3_82586=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 # CONFIG_WAN is not set
 CONFIG_PPP=m
 # CONFIG_PPP_MULTILINK is not set
@@ -428,28 +537,28 @@ CONFIG_PPP_ASYNC=m
 CONFIG_PPP_SYNC_TTY=m
 CONFIG_PPP_DEFLATE=m
 CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
 CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
 CONFIG_SLIP=m
 CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLHC=m
 CONFIG_SLIP_SMART=y
 CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_SHAPER=m
 CONFIG_NETCONSOLE=m
-
-#
-# ISDN subsystem
-#
+CONFIG_NETCONSOLE_DYNAMIC=y
+CONFIG_NETPOLL=y
+# CONFIG_NETPOLL_TRAP is not set
+CONFIG_NET_POLL_CONTROLLER=y
 # CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
 # CONFIG_PHONE is not set
 
 #
 # Input device support
 #
 CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=m
+# CONFIG_INPUT_POLLDEV is not set
 
 #
 # Userland interfaces
@@ -459,7 +568,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 
@@ -472,11 +580,19 @@ CONFIG_KEYBOARD_SUNKBD=y
 # CONFIG_KEYBOARD_LKKBD is not set
 # CONFIG_KEYBOARD_XTKBD is not set
 # CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
 CONFIG_INPUT_MOUSE=y
 CONFIG_MOUSE_PS2=m
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
 CONFIG_MOUSE_SERIAL=m
 # CONFIG_MOUSE_VSXXXAA is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 
@@ -484,7 +600,7 @@ CONFIG_MOUSE_SERIAL=m
 # Hardware I/O ports
 #
 CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=m
+# CONFIG_SERIO_SERPORT is not set
 CONFIG_SERIO_LIBPS2=m
 # CONFIG_SERIO_RAW is not set
 # CONFIG_GAMEPORT is not set
@@ -495,6 +611,7 @@ CONFIG_SERIO_LIBPS2=m
 CONFIG_VT=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -508,112 +625,113 @@ CONFIG_HW_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
-CONFIG_GEN_RTC=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_GEN_RTC=m
 CONFIG_GEN_RTC_X=y
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
-
-#
-# Ftape, the floppy tape device driver
-#
-# CONFIG_DRM is not set
 # CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
-
-#
-# I2C support
-#
+# CONFIG_TCG_TPM is not set
 # CONFIG_I2C is not set
 
 #
-# Dallas's 1-wire bus
+# SPI support
 #
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
 # CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
 
 #
-# Misc devices
+# Sonics Silicon Backplane
 #
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
-# Multimedia devices
+# Multifunction device drivers
 #
-# CONFIG_VIDEO_DEV is not set
+# CONFIG_MFD_SM501 is not set
 
 #
-# Digital Video Broadcasting Devices
+# Multimedia devices
 #
-# CONFIG_DVB is not set
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
 
 #
 # Graphics support
 #
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
 # CONFIG_FB_CFB_FILLRECT is not set
 # CONFIG_FB_CFB_COPYAREA is not set
 # CONFIG_FB_CFB_IMAGEBLIT is not set
-# CONFIG_FB_SOFT_CURSOR is not set
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
-CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
 # CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_UVESA is not set
 # CONFIG_FB_S1D13XXX is not set
 # CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
 #
 CONFIG_DUMMY_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
 # CONFIG_FONTS is not set
 CONFIG_FONT_8x8=y
 CONFIG_FONT_8x16=y
-
-#
-# Logo configuration
-#
 CONFIG_LOGO=y
 CONFIG_LOGO_LINUX_MONO=y
 CONFIG_LOGO_LINUX_VGA16=y
 CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
 # Sound
 #
 # CONFIG_SOUND is not set
-
-#
-# USB support
-#
-# CONFIG_USB_ARCH_HAS_HCD is not set
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=m
+# CONFIG_HID_DEBUG is not set
+CONFIG_HIDRAW=y
+# CONFIG_USB_SUPPORT is not set
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_RTC_CLASS is not set
 
 #
-# InfiniBand support
+# Userspace I/O
 #
-# CONFIG_INFINIBAND is not set
+# CONFIG_UIO is not set
 
 #
 # Character devices
@@ -624,10 +742,11 @@ CONFIG_LOGO_LINUX_CLUT224=y
 #
 CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4DEV_FS is not set
 CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
 CONFIG_REISERFS_FS=m
 # CONFIG_REISERFS_CHECK is not set
 # CONFIG_REISERFS_PROC_INFO is not set
@@ -638,25 +757,29 @@ CONFIG_JFS_FS=m
 # CONFIG_JFS_DEBUG is not set
 # CONFIG_JFS_STATISTICS is not set
 CONFIG_FS_POSIX_ACL=y
-
-#
-# XFS support
-#
 CONFIG_XFS_FS=m
-CONFIG_XFS_EXPORT=y
-# CONFIG_XFS_RT is not set
 # CONFIG_XFS_QUOTA is not set
 # CONFIG_XFS_SECURITY is not set
 # CONFIG_XFS_POSIX_ACL is not set
-CONFIG_MINIX_FS=y
-# CONFIG_ROMFS_FS is not set
+# CONFIG_XFS_RT is not set
+CONFIG_GFS2_FS=m
+CONFIG_GFS2_FS_LOCKING_NOLOCK=m
+CONFIG_GFS2_FS_LOCKING_DLM=m
+CONFIG_OCFS2_FS=m
+# CONFIG_OCFS2_DEBUG_MASKLOG is not set
+# CONFIG_OCFS2_DEBUG_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
 CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
 # CONFIG_QFMT_V1 is not set
 # CONFIG_QFMT_V2 is not set
 CONFIG_QUOTACTL=y
-CONFIG_DNOTIFY=y
 CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
+CONFIG_FUSE_FS=m
 
 #
 # CD-ROM/DVD Filesystems
@@ -664,7 +787,6 @@ CONFIG_AUTOFS4_FS=m
 CONFIG_ISO9660_FS=y
 CONFIG_JOLIET=y
 CONFIG_ZISOFS=y
-CONFIG_ZISOFS_FS=y
 CONFIG_UDF_FS=m
 CONFIG_UDF_NLS=y
 
@@ -683,15 +805,12 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 #
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
 CONFIG_SYSFS=y
-CONFIG_DEVFS_FS=y
-CONFIG_DEVFS_MOUNT=y
-# CONFIG_DEVFS_DEBUG is not set
-# CONFIG_DEVPTS_FS_XATTR is not set
 CONFIG_TMPFS=y
-# CONFIG_TMPFS_XATTR is not set
+# CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
+CONFIG_CONFIGFS_FS=m
 
 #
 # Miscellaneous filesystems
@@ -705,44 +824,40 @@ CONFIG_HFSPLUS_FS=m
 # CONFIG_EFS_FS is not set
 CONFIG_CRAMFS=m
 # CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=y
 CONFIG_HPFS_FS=m
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 CONFIG_SYSV_FS=m
 CONFIG_UFS_FS=m
-CONFIG_UFS_FS_WRITE=y
-
-#
-# Network File Systems
-#
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
 # CONFIG_NFS_DIRECTIO is not set
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
-CONFIG_NFSD_V4=y
+# CONFIG_NFSD_V3_ACL is not set
+# CONFIG_NFSD_V4 is not set
 CONFIG_NFSD_TCP=y
 CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=m
+CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
+CONFIG_SUNRPC_BIND34=y
 CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
 CONFIG_SMB_NLS_DEFAULT=y
 CONFIG_SMB_NLS_REMOTE="cp437"
 # CONFIG_CIFS is not set
-CONFIG_NCP_FS=m
-# CONFIG_NCPFS_PACKET_SIGNING is not set
-# CONFIG_NCPFS_IOCTL_LOCKING is not set
-# CONFIG_NCPFS_STRONG is not set
-# CONFIG_NCPFS_NFS_NS is not set
-# CONFIG_NCPFS_OS2_NS is not set
-# CONFIG_NCPFS_SMALLDOS is not set
-CONFIG_NCPFS_NLS=y
-# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_NCP_FS is not set
 CONFIG_CODA_FS=m
 # CONFIG_CODA_FS_OLD_API is not set
 # CONFIG_AFS_FS is not set
@@ -753,10 +868,6 @@ CONFIG_CODA_FS=m
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
 CONFIG_SUN_PARTITION=y
-
-#
-# Native Language Support
-#
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=y
@@ -797,35 +908,42 @@ CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
 CONFIG_NLS_UTF8=m
+CONFIG_DLM=m
+# CONFIG_DLM_DEBUG is not set
 
 #
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
-CONFIG_DEBUG_KERNEL=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_MAGIC_SYSRQ=y
-CONFIG_LOG_BUF_SHIFT=16
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_INFO is not set
+# CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
-# CONFIG_FRAME_POINTER is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_SAMPLES is not set
 
 #
 # Security options
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_XOR_BLOCKS=m
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_XOR=m
 CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_SEQIV=m
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
 CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=m
 CONFIG_CRYPTO_NULL=m
 CONFIG_CRYPTO_MD4=m
 CONFIG_CRYPTO_MD5=y
@@ -834,9 +952,21 @@ CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
 CONFIG_CRYPTO_WP512=m
 CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_XTS=m
+CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_CRYPTD=m
 CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
 CONFIG_CRYPTO_BLOWFISH=m
 CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
 CONFIG_CRYPTO_SERPENT=m
 CONFIG_CRYPTO_AES=m
 CONFIG_CRYPTO_CAST5=m
@@ -845,20 +975,34 @@ CONFIG_CRYPTO_TEA=m
 CONFIG_CRYPTO_ARC4=m
 CONFIG_CRYPTO_KHAZAD=m
 CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SALSA20=m
 CONFIG_CRYPTO_DEFLATE=m
 CONFIG_CRYPTO_MICHAEL_MIC=m
 CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_CAMELLIA=m
 CONFIG_CRYPTO_TEST=m
-
-#
-# Hardware crypto devices
-#
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_LZO=m
+# CONFIG_CRYPTO_HW is not set
 
 #
 # Library routines
 #
+CONFIG_BITREVERSE=y
 CONFIG_CRC_CCITT=m
+CONFIG_CRC16=m
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 CONFIG_LIBCRC32C=m
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=m
+CONFIG_LZO_COMPRESS=m
+CONFIG_LZO_DECOMPRESS=m
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
diff --git a/arch/m68k/configs/sun3x_defconfig b/arch/m68k/configs/sun3x_defconfig
index 997143b7928a..f18154f1ef1f 100644
--- a/arch/m68k/configs/sun3x_defconfig
+++ b/arch/m68k/configs/sun3x_defconfig
@@ -1,63 +1,111 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc6-m68k
-# Tue Jun  7 20:35:06 2005
+# Linux kernel version: 2.6.25-rc8
+# Wed Apr  2 20:46:23 2008
 #
 CONFIG_M68K=y
 CONFIG_MMU=y
-CONFIG_UID16=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_TIME_LOW_RES=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_NO_IOPORT=y
+# CONFIG_NO_DMA is not set
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_HZ=100
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
-CONFIG_CLEAN_COMPILE=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION="-sun3x"
+CONFIG_LOCALVERSION_AUTO=y
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_BSD_PROCESS_ACCT=y
 # CONFIG_BSD_PROCESS_ACCT_V3 is not set
-CONFIG_SYSCTL=y
-CONFIG_AUDIT=y
-CONFIG_HOTPLUG=y
-CONFIG_KOBJECT_UEVENT=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_COMPAT_BRK is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+# CONFIG_HAVE_OPROFILE is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_OBSOLETE_MODPARM=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+CONFIG_BLK_DEV_BSG=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
 
 #
 # Platform dependent setup
@@ -80,10 +128,24 @@ CONFIG_M68030=y
 # CONFIG_M68040 is not set
 # CONFIG_M68060 is not set
 CONFIG_MMU_MOTOROLA=y
-CONFIG_M68KFPU_EMU=y
-CONFIG_M68KFPU_EMU_EXTRAPREC=y
-# CONFIG_M68KFPU_EMU_ONLY is not set
+# CONFIG_M68KFPU_EMU is not set
 # CONFIG_ADVANCED is not set
+CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
+CONFIG_NODES_SHIFT=3
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_FLATMEM_MANUAL is not set
+CONFIG_DISCONTIGMEM_MANUAL=y
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_DISCONTIGMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_NEED_MULTIPLE_NODES=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
 
 #
 # General setup
@@ -92,135 +154,11 @@ CONFIG_BINFMT_ELF=y
 CONFIG_BINFMT_AOUT=m
 CONFIG_BINFMT_MISC=m
 CONFIG_PROC_HARDWARE=y
+CONFIG_ZONE_DMA=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 
 #
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
-# CONFIG_DEBUG_DRIVER is not set
-
-#
-# Memory Technology Devices (MTD)
-#
-# CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_CDROM_PKTCDVD_BUFFERS=8
-# CONFIG_CDROM_PKTCDVD_WCACHE is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_ATA_OVER_ETH=m
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-CONFIG_SCSI=y
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=m
-# CONFIG_CHR_DEV_OSST is not set
-CONFIG_BLK_DEV_SR=y
-CONFIG_BLK_DEV_SR_VENDOR=y
-CONFIG_CHR_DEV_SG=m
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-# CONFIG_SCSI_MULTI_LUN is not set
-CONFIG_SCSI_CONSTANTS=y
-# CONFIG_SCSI_LOGGING is not set
-
-#
-# SCSI Transport Attributes
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-
-#
-# SCSI low-level drivers
-#
-# CONFIG_SCSI_SATA is not set
-# CONFIG_SCSI_DEBUG is not set
-CONFIG_SUN3X_ESP=y
-
-#
-# Multi-device support (RAID and LVM)
-#
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-# CONFIG_MD_RAID10 is not set
-CONFIG_MD_RAID5=m
-CONFIG_MD_RAID6=m
-CONFIG_MD_MULTIPATH=m
-# CONFIG_MD_FAULTY is not set
-CONFIG_BLK_DEV_DM=m
-CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
-CONFIG_DM_MIRROR=m
-CONFIG_DM_ZERO=m
-CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_EMC=m
-
-#
-# Fusion MPT device support
-#
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Networking support
+# Networking
 #
 CONFIG_NET=y
 
@@ -230,10 +168,17 @@ CONFIG_NET=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+CONFIG_XFRM_MIGRATE=y
+# CONFIG_XFRM_STATISTICS is not set
 CONFIG_NET_KEY=y
+CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
 # CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
@@ -245,145 +190,199 @@ CONFIG_SYN_COOKIES=y
 CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
 CONFIG_INET_TUNNEL=m
-CONFIG_IP_TCPDIAG=m
-CONFIG_IP_TCPDIAG_IPV6=y
-
-#
-# IP: Virtual Server Configuration
-#
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_INET_LRO=m
+CONFIG_INET_DIAG=m
+CONFIG_INET_TCP_DIAG=m
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
 # CONFIG_IP_VS is not set
 CONFIG_IPV6=m
 CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
 CONFIG_INET6_AH=m
 CONFIG_INET6_ESP=m
 CONFIG_INET6_IPCOMP=m
+# CONFIG_IPV6_MIP6 is not set
+CONFIG_INET6_XFRM_TUNNEL=m
 CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
+CONFIG_IPV6_SIT=m
 CONFIG_IPV6_TUNNEL=m
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_NETWORK_SECMARK is not set
 CONFIG_NETFILTER=y
 # CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+CONFIG_NF_CT_PROTO_GRE=m
+CONFIG_NF_CT_PROTO_SCTP=m
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+# CONFIG_NF_CT_NETLINK is not set
+CONFIG_NETFILTER_XTABLES=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_RATEEST=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
 
 #
 # IP: Netfilter Configuration
 #
-CONFIG_IP_NF_CONNTRACK=m
-# CONFIG_IP_NF_CT_ACCT is not set
-CONFIG_IP_NF_CONNTRACK_MARK=y
-# CONFIG_IP_NF_CT_PROTO_SCTP is not set
-CONFIG_IP_NF_FTP=m
-CONFIG_IP_NF_IRC=m
-CONFIG_IP_NF_TFTP=m
-CONFIG_IP_NF_AMANDA=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
 CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_LIMIT=m
-CONFIG_IP_NF_MATCH_IPRANGE=m
-CONFIG_IP_NF_MATCH_MAC=m
-CONFIG_IP_NF_MATCH_PKTTYPE=m
-CONFIG_IP_NF_MATCH_MARK=m
-CONFIG_IP_NF_MATCH_MULTIPORT=m
-CONFIG_IP_NF_MATCH_TOS=m
 CONFIG_IP_NF_MATCH_RECENT=m
 CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_DSCP=m
-CONFIG_IP_NF_MATCH_AH_ESP=m
-CONFIG_IP_NF_MATCH_LENGTH=m
+CONFIG_IP_NF_MATCH_AH=m
 CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_MATCH_TCPMSS=m
-CONFIG_IP_NF_MATCH_HELPER=m
-CONFIG_IP_NF_MATCH_STATE=m
-CONFIG_IP_NF_MATCH_CONNTRACK=m
-CONFIG_IP_NF_MATCH_OWNER=m
 CONFIG_IP_NF_MATCH_ADDRTYPE=m
-CONFIG_IP_NF_MATCH_REALM=m
-# CONFIG_IP_NF_MATCH_SCTP is not set
-# CONFIG_IP_NF_MATCH_COMMENT is not set
-CONFIG_IP_NF_MATCH_CONNMARK=m
-CONFIG_IP_NF_MATCH_HASHLIMIT=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
 CONFIG_IP_NF_TARGET_LOG=m
 CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_IP_NF_TARGET_TCPMSS=m
-CONFIG_IP_NF_NAT=m
-CONFIG_IP_NF_NAT_NEEDED=y
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
 CONFIG_IP_NF_TARGET_MASQUERADE=m
 CONFIG_IP_NF_TARGET_REDIRECT=m
 CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_SAME=m
-CONFIG_IP_NF_NAT_SNMP_BASIC=m
-CONFIG_IP_NF_NAT_IRC=m
-CONFIG_IP_NF_NAT_FTP=m
-CONFIG_IP_NF_NAT_TFTP=m
-CONFIG_IP_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_SNMP_BASIC=m
+CONFIG_NF_NAT_PROTO_GRE=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+CONFIG_NF_NAT_TFTP=m
+CONFIG_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+CONFIG_NF_NAT_SIP=m
 CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_TOS=m
 CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_DSCP=m
-CONFIG_IP_NF_TARGET_MARK=m
-CONFIG_IP_NF_TARGET_CLASSIFY=m
-CONFIG_IP_NF_TARGET_CONNMARK=m
-# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
 CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_TARGET_NOTRACK=m
 CONFIG_IP_NF_ARPTABLES=m
 CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
 
 #
-# IPv6: Netfilter Configuration (EXPERIMENTAL)
+# IPv6: Netfilter Configuration
 #
+CONFIG_NF_CONNTRACK_IPV6=m
 CONFIG_IP6_NF_QUEUE=m
 CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_MATCH_LIMIT=m
-CONFIG_IP6_NF_MATCH_MAC=m
 CONFIG_IP6_NF_MATCH_RT=m
 CONFIG_IP6_NF_MATCH_OPTS=m
 CONFIG_IP6_NF_MATCH_FRAG=m
 CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_MULTIPORT=m
-CONFIG_IP6_NF_MATCH_OWNER=m
-CONFIG_IP6_NF_MATCH_MARK=m
 CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_MATCH_AHESP=m
-CONFIG_IP6_NF_MATCH_LENGTH=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_MH=m
 CONFIG_IP6_NF_MATCH_EUI64=m
 CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_TARGET_MARK=m
+CONFIG_IP6_NF_TARGET_HL=m
 CONFIG_IP6_NF_RAW=m
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
+CONFIG_IP_DCCP=m
+CONFIG_INET_DCCP_DIAG=m
+CONFIG_IP_DCCP_ACKVEC=y
 
 #
-# SCTP Configuration (EXPERIMENTAL)
+# DCCP CCIDs Configuration (EXPERIMENTAL)
 #
+CONFIG_IP_DCCP_CCID2=m
+# CONFIG_IP_DCCP_CCID2_DEBUG is not set
+CONFIG_IP_DCCP_CCID3=m
+# CONFIG_IP_DCCP_CCID3_DEBUG is not set
+CONFIG_IP_DCCP_CCID3_RTO=100
+CONFIG_IP_DCCP_TFRC_LIB=m
 CONFIG_IP_SCTP=m
 # CONFIG_SCTP_DBG_MSG is not set
 # CONFIG_SCTP_DBG_OBJCNT is not set
 # CONFIG_SCTP_HMAC_NONE is not set
 # CONFIG_SCTP_HMAC_SHA1 is not set
 CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 CONFIG_LLC=m
 # CONFIG_LLC2 is not set
-CONFIG_IPX=m
-# CONFIG_IPX_INTERN is not set
+# CONFIG_IPX is not set
 CONFIG_ATALK=m
 # CONFIG_DEV_APPLETALK is not set
 # CONFIG_X25 is not set
 # CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 CONFIG_NET_CLS_ROUTE=y
 
@@ -391,46 +390,155 @@ CONFIG_NET_CLS_ROUTE=y
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
-CONFIG_NETPOLL=y
-# CONFIG_NETPOLL_RX is not set
-# CONFIG_NETPOLL_TRAP is not set
-CONFIG_NET_POLL_CONTROLLER=y
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=m
-# CONFIG_BONDING is not set
-CONFIG_EQUALIZER=m
-# CONFIG_TUN is not set
+# CONFIG_AF_RXRPC is not set
 
 #
-# Ethernet (10 or 100Mbit)
+# Wireless
 #
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=m
-CONFIG_SUN3LANCE=y
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=m
+CONFIG_IEEE80211_CRYPT_CCMP=m
+CONFIG_IEEE80211_CRYPT_TKIP=m
+CONFIG_IEEE80211_SOFTMAC=m
+# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
-# Ethernet (1000 Mbit)
+# Device Drivers
 #
 
 #
-# Ethernet (10000 Mbit)
+# Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=m
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=m
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+CONFIG_ATA_OVER_ETH=m
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
 
 #
-# Token Ring devices
+# SCSI device support
 #
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=m
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
 
 #
-# Wireless LAN (non-hamradio)
+# SCSI support type (disk, tape, CD-ROM)
 #
-# CONFIG_NET_RADIO is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_ST=m
+CONFIG_CHR_DEV_OSST=m
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_DEV_SR_VENDOR=y
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
 
 #
-# Wan interfaces
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
 #
+# CONFIG_SCSI_MULTI_LUN is not set
+CONFIG_SCSI_CONSTANTS=y
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+CONFIG_SCSI_SPI_ATTRS=y
+# CONFIG_SCSI_FC_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=m
+CONFIG_SCSI_SAS_ATTRS=m
+CONFIG_SCSI_SAS_LIBSAS=m
+CONFIG_SCSI_SAS_HOST_SMP=y
+# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
+CONFIG_SCSI_SRP_ATTRS=m
+CONFIG_SCSI_SRP_TGT_ATTRS=y
+CONFIG_SCSI_LOWLEVEL=y
+CONFIG_ISCSI_TCP=m
+# CONFIG_SCSI_DEBUG is not set
+CONFIG_SUN3X_ESP=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+# CONFIG_MD_RAID10 is not set
+CONFIG_MD_RAID456=m
+CONFIG_MD_RAID5_RESHAPE=y
+CONFIG_MD_MULTIPATH=m
+# CONFIG_MD_FAULTY is not set
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_ZERO=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_MULTIPATH_EMC=m
+CONFIG_DM_MULTIPATH_RDAC=m
+CONFIG_DM_MULTIPATH_HP=m
+# CONFIG_DM_DELAY is not set
+CONFIG_DM_UEVENT=y
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+CONFIG_DUMMY=m
+# CONFIG_BONDING is not set
+CONFIG_MACVLAN=m
+CONFIG_EQUALIZER=m
+# CONFIG_TUN is not set
+CONFIG_VETH=m
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+CONFIG_SUN3LANCE=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 # CONFIG_WAN is not set
 CONFIG_PPP=m
 # CONFIG_PPP_MULTILINK is not set
@@ -439,28 +547,28 @@ CONFIG_PPP_ASYNC=m
 CONFIG_PPP_SYNC_TTY=m
 CONFIG_PPP_DEFLATE=m
 CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
 CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
 CONFIG_SLIP=m
 CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLHC=m
 CONFIG_SLIP_SMART=y
 CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_SHAPER=m
 CONFIG_NETCONSOLE=m
-
-#
-# ISDN subsystem
-#
+CONFIG_NETCONSOLE_DYNAMIC=y
+CONFIG_NETPOLL=y
+# CONFIG_NETPOLL_TRAP is not set
+CONFIG_NET_POLL_CONTROLLER=y
 # CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
 # CONFIG_PHONE is not set
 
 #
 # Input device support
 #
 CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=m
+# CONFIG_INPUT_POLLDEV is not set
 
 #
 # Userland interfaces
@@ -470,7 +578,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 
@@ -483,11 +590,19 @@ CONFIG_KEYBOARD_SUNKBD=y
 # CONFIG_KEYBOARD_LKKBD is not set
 # CONFIG_KEYBOARD_XTKBD is not set
 # CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
 CONFIG_INPUT_MOUSE=y
 CONFIG_MOUSE_PS2=m
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
 CONFIG_MOUSE_SERIAL=m
 # CONFIG_MOUSE_VSXXXAA is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 
@@ -495,7 +610,7 @@ CONFIG_MOUSE_SERIAL=m
 # Hardware I/O ports
 #
 CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=m
+# CONFIG_SERIO_SERPORT is not set
 CONFIG_SERIO_LIBPS2=m
 # CONFIG_SERIO_RAW is not set
 # CONFIG_GAMEPORT is not set
@@ -506,6 +621,7 @@ CONFIG_SERIO_LIBPS2=m
 CONFIG_VT=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -519,112 +635,113 @@ CONFIG_HW_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
-CONFIG_GEN_RTC=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_GEN_RTC=m
 CONFIG_GEN_RTC_X=y
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
-
-#
-# Ftape, the floppy tape device driver
-#
-# CONFIG_DRM is not set
 # CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
-
-#
-# I2C support
-#
+# CONFIG_TCG_TPM is not set
 # CONFIG_I2C is not set
 
 #
-# Dallas's 1-wire bus
+# SPI support
 #
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
 # CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
 
 #
-# Misc devices
+# Sonics Silicon Backplane
 #
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
-# Multimedia devices
+# Multifunction device drivers
 #
-# CONFIG_VIDEO_DEV is not set
+# CONFIG_MFD_SM501 is not set
 
 #
-# Digital Video Broadcasting Devices
+# Multimedia devices
 #
-# CONFIG_DVB is not set
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
 
 #
 # Graphics support
 #
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
 # CONFIG_FB_CFB_FILLRECT is not set
 # CONFIG_FB_CFB_COPYAREA is not set
 # CONFIG_FB_CFB_IMAGEBLIT is not set
-# CONFIG_FB_SOFT_CURSOR is not set
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
-CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
 # CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_UVESA is not set
 # CONFIG_FB_S1D13XXX is not set
 # CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
 #
 CONFIG_DUMMY_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
 # CONFIG_FONTS is not set
 CONFIG_FONT_8x8=y
 CONFIG_FONT_8x16=y
-
-#
-# Logo configuration
-#
 CONFIG_LOGO=y
 CONFIG_LOGO_LINUX_MONO=y
 CONFIG_LOGO_LINUX_VGA16=y
 CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
 # Sound
 #
 # CONFIG_SOUND is not set
-
-#
-# USB support
-#
-# CONFIG_USB_ARCH_HAS_HCD is not set
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=m
+# CONFIG_HID_DEBUG is not set
+CONFIG_HIDRAW=y
+# CONFIG_USB_SUPPORT is not set
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_RTC_CLASS is not set
 
 #
-# InfiniBand support
+# Userspace I/O
 #
-# CONFIG_INFINIBAND is not set
+# CONFIG_UIO is not set
 
 #
 # Character devices
@@ -635,10 +752,11 @@ CONFIG_LOGO_LINUX_CLUT224=y
 #
 CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4DEV_FS is not set
 CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
 CONFIG_REISERFS_FS=m
 # CONFIG_REISERFS_CHECK is not set
 # CONFIG_REISERFS_PROC_INFO is not set
@@ -649,25 +767,29 @@ CONFIG_JFS_FS=m
 # CONFIG_JFS_DEBUG is not set
 # CONFIG_JFS_STATISTICS is not set
 CONFIG_FS_POSIX_ACL=y
-
-#
-# XFS support
-#
 CONFIG_XFS_FS=m
-CONFIG_XFS_EXPORT=y
-# CONFIG_XFS_RT is not set
 # CONFIG_XFS_QUOTA is not set
 # CONFIG_XFS_SECURITY is not set
 # CONFIG_XFS_POSIX_ACL is not set
-CONFIG_MINIX_FS=y
-# CONFIG_ROMFS_FS is not set
+# CONFIG_XFS_RT is not set
+CONFIG_GFS2_FS=m
+CONFIG_GFS2_FS_LOCKING_NOLOCK=m
+CONFIG_GFS2_FS_LOCKING_DLM=m
+CONFIG_OCFS2_FS=m
+# CONFIG_OCFS2_DEBUG_MASKLOG is not set
+# CONFIG_OCFS2_DEBUG_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
 CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
 # CONFIG_QFMT_V1 is not set
 # CONFIG_QFMT_V2 is not set
 CONFIG_QUOTACTL=y
-CONFIG_DNOTIFY=y
 CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
+CONFIG_FUSE_FS=m
 
 #
 # CD-ROM/DVD Filesystems
@@ -675,7 +797,6 @@ CONFIG_AUTOFS4_FS=m
 CONFIG_ISO9660_FS=y
 CONFIG_JOLIET=y
 CONFIG_ZISOFS=y
-CONFIG_ZISOFS_FS=y
 CONFIG_UDF_FS=m
 CONFIG_UDF_NLS=y
 
@@ -694,15 +815,12 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 #
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
 CONFIG_SYSFS=y
-CONFIG_DEVFS_FS=y
-CONFIG_DEVFS_MOUNT=y
-# CONFIG_DEVFS_DEBUG is not set
-# CONFIG_DEVPTS_FS_XATTR is not set
 CONFIG_TMPFS=y
-# CONFIG_TMPFS_XATTR is not set
+# CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
+CONFIG_CONFIGFS_FS=m
 
 #
 # Miscellaneous filesystems
@@ -716,44 +834,40 @@ CONFIG_HFSPLUS_FS=m
 # CONFIG_EFS_FS is not set
 CONFIG_CRAMFS=m
 # CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=y
 CONFIG_HPFS_FS=m
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 CONFIG_SYSV_FS=m
 CONFIG_UFS_FS=m
-CONFIG_UFS_FS_WRITE=y
-
-#
-# Network File Systems
-#
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
 # CONFIG_NFS_DIRECTIO is not set
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
-CONFIG_NFSD_V4=y
+# CONFIG_NFSD_V3_ACL is not set
+# CONFIG_NFSD_V4 is not set
 CONFIG_NFSD_TCP=y
 CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=m
+CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
+CONFIG_SUNRPC_BIND34=y
 CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
 CONFIG_SMB_NLS_DEFAULT=y
 CONFIG_SMB_NLS_REMOTE="cp437"
 # CONFIG_CIFS is not set
-CONFIG_NCP_FS=m
-# CONFIG_NCPFS_PACKET_SIGNING is not set
-# CONFIG_NCPFS_IOCTL_LOCKING is not set
-# CONFIG_NCPFS_STRONG is not set
-# CONFIG_NCPFS_NFS_NS is not set
-# CONFIG_NCPFS_OS2_NS is not set
-# CONFIG_NCPFS_SMALLDOS is not set
-CONFIG_NCPFS_NLS=y
-# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_NCP_FS is not set
 CONFIG_CODA_FS=m
 # CONFIG_CODA_FS_OLD_API is not set
 # CONFIG_AFS_FS is not set
@@ -764,10 +878,6 @@ CONFIG_CODA_FS=m
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
 CONFIG_SUN_PARTITION=y
-
-#
-# Native Language Support
-#
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=y
@@ -808,35 +918,42 @@ CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
 CONFIG_NLS_UTF8=m
+CONFIG_DLM=m
+# CONFIG_DLM_DEBUG is not set
 
 #
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
-CONFIG_DEBUG_KERNEL=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_MAGIC_SYSRQ=y
-CONFIG_LOG_BUF_SHIFT=16
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_INFO is not set
+# CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
-# CONFIG_FRAME_POINTER is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_SAMPLES is not set
 
 #
 # Security options
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_XOR_BLOCKS=m
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_XOR=m
 CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_SEQIV=m
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
 CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=m
 CONFIG_CRYPTO_NULL=m
 CONFIG_CRYPTO_MD4=m
 CONFIG_CRYPTO_MD5=y
@@ -845,9 +962,21 @@ CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
 CONFIG_CRYPTO_WP512=m
 CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_XTS=m
+CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_CRYPTD=m
 CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
 CONFIG_CRYPTO_BLOWFISH=m
 CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
 CONFIG_CRYPTO_SERPENT=m
 CONFIG_CRYPTO_AES=m
 CONFIG_CRYPTO_CAST5=m
@@ -856,20 +985,35 @@ CONFIG_CRYPTO_TEA=m
 CONFIG_CRYPTO_ARC4=m
 CONFIG_CRYPTO_KHAZAD=m
 CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SALSA20=m
 CONFIG_CRYPTO_DEFLATE=m
 CONFIG_CRYPTO_MICHAEL_MIC=m
 CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_CAMELLIA=m
 CONFIG_CRYPTO_TEST=m
-
-#
-# Hardware crypto devices
-#
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_LZO=m
+# CONFIG_CRYPTO_HW is not set
 
 #
 # Library routines
 #
+CONFIG_BITREVERSE=y
 CONFIG_CRC_CCITT=m
+CONFIG_CRC16=m
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 CONFIG_LIBCRC32C=m
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=m
+CONFIG_LZO_COMPRESS=m
+CONFIG_LZO_DECOMPRESS=m
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_DMA=y
diff --git a/arch/m68k/defconfig b/arch/m68k/defconfig
deleted file mode 100644
index 7d935e48a9a8..000000000000
--- a/arch/m68k/defconfig
+++ /dev/null
@@ -1,657 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc6-m68k
-# Tue Jun  7 20:34:17 2005
-#
-CONFIG_M68K=y
-CONFIG_MMU=y
-CONFIG_UID16=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-
-#
-# Code maturity level options
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_CLEAN_COMPILE=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-CONFIG_SYSCTL=y
-# CONFIG_AUDIT is not set
-# CONFIG_HOTPLUG is not set
-CONFIG_KOBJECT_UEVENT=y
-# CONFIG_IKCONFIG is not set
-# CONFIG_EMBEDDED is not set
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-
-#
-# Loadable module support
-#
-# CONFIG_MODULES is not set
-
-#
-# Platform dependent setup
-#
-# CONFIG_SUN3 is not set
-CONFIG_AMIGA=y
-# CONFIG_ATARI is not set
-# CONFIG_MAC is not set
-# CONFIG_APOLLO is not set
-# CONFIG_VME is not set
-# CONFIG_HP300 is not set
-# CONFIG_SUN3X is not set
-# CONFIG_Q40 is not set
-
-#
-# Processor type
-#
-CONFIG_M68020=y
-CONFIG_M68030=y
-CONFIG_M68040=y
-# CONFIG_M68060 is not set
-CONFIG_MMU_MOTOROLA=y
-# CONFIG_M68KFPU_EMU is not set
-# CONFIG_ADVANCED is not set
-
-#
-# General setup
-#
-CONFIG_BINFMT_ELF=y
-CONFIG_BINFMT_AOUT=y
-# CONFIG_BINFMT_MISC is not set
-CONFIG_ZORRO=y
-# CONFIG_AMIGA_PCMCIA is not set
-# CONFIG_HEARTBEAT is not set
-CONFIG_PROC_HARDWARE=y
-# CONFIG_ZORRO_NAMES is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
-
-#
-# Memory Technology Devices (MTD)
-#
-# CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
-CONFIG_AMIGA_FLOPPY=y
-# CONFIG_AMIGA_Z2RAM is not set
-# CONFIG_BLK_DEV_COW_COMMON is not set
-# CONFIG_BLK_DEV_LOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_CDROM_PKTCDVD=y
-CONFIG_CDROM_PKTCDVD_BUFFERS=8
-# CONFIG_CDROM_PKTCDVD_WCACHE is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-# CONFIG_ATA_OVER_ETH is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-CONFIG_SCSI=y
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=y
-# CONFIG_CHR_DEV_OSST is not set
-CONFIG_BLK_DEV_SR=y
-# CONFIG_BLK_DEV_SR_VENDOR is not set
-# CONFIG_CHR_DEV_SG is not set
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-# CONFIG_SCSI_MULTI_LUN is not set
-CONFIG_SCSI_CONSTANTS=y
-# CONFIG_SCSI_LOGGING is not set
-
-#
-# SCSI Transport Attributes
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-
-#
-# SCSI low-level drivers
-#
-# CONFIG_SCSI_SATA is not set
-# CONFIG_SCSI_DEBUG is not set
-CONFIG_A3000_SCSI=y
-CONFIG_A2091_SCSI=y
-CONFIG_GVP11_SCSI=y
-# CONFIG_CYBERSTORM_SCSI is not set
-# CONFIG_CYBERSTORMII_SCSI is not set
-# CONFIG_BLZ2060_SCSI is not set
-# CONFIG_BLZ1230_SCSI is not set
-# CONFIG_FASTLANE_SCSI is not set
-# CONFIG_OKTAGON_SCSI is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-# CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Networking support
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-CONFIG_UNIX=y
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-# CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_IP_TCPDIAG=y
-# CONFIG_IP_TCPDIAG_IPV6 is not set
-# CONFIG_IPV6 is not set
-# CONFIG_NETFILTER is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-# CONFIG_NET_CLS_ROUTE is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
-# CONFIG_NET_ETHERNET is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
-#
-
-#
-# Token Ring devices
-#
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# Wan interfaces
-#
-# CONFIG_WAN is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
-# CONFIG_NETCONSOLE is not set
-
-#
-# ISDN subsystem
-#
-# CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
-# CONFIG_INPUT_EVDEV is not set
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ATKBD=y
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_AMIGA is not set
-CONFIG_INPUT_MOUSE=y
-CONFIG_MOUSE_PS2=y
-# CONFIG_MOUSE_SERIAL is not set
-# CONFIG_MOUSE_AMIGA is not set
-# CONFIG_MOUSE_VSXXXAA is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=y
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_SERIO_RAW is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-# CONFIG_A2232 is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
-# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
-# CONFIG_GEN_RTC is not set
-# CONFIG_DTLK is not set
-# CONFIG_R3964 is not set
-
-#
-# Ftape, the floppy tape device driver
-#
-# CONFIG_DRM is not set
-# CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
-
-#
-# I2C support
-#
-# CONFIG_I2C is not set
-
-#
-# Dallas's 1-wire bus
-#
-# CONFIG_W1 is not set
-
-#
-# Misc devices
-#
-
-#
-# Multimedia devices
-#
-# CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
-
-#
-# Graphics support
-#
-CONFIG_FB=y
-# CONFIG_FB_CFB_FILLRECT is not set
-# CONFIG_FB_CFB_COPYAREA is not set
-# CONFIG_FB_CFB_IMAGEBLIT is not set
-CONFIG_FB_SOFT_CURSOR=y
-# CONFIG_FB_MACMODES is not set
-CONFIG_FB_MODE_HELPERS=y
-# CONFIG_FB_TILEBLITTING is not set
-# CONFIG_FB_CIRRUS is not set
-CONFIG_FB_AMIGA=y
-CONFIG_FB_AMIGA_OCS=y
-CONFIG_FB_AMIGA_ECS=y
-CONFIG_FB_AMIGA_AGA=y
-# CONFIG_FB_FM2 is not set
-# CONFIG_FB_S1D13XXX is not set
-# CONFIG_FB_VIRTUAL is not set
-
-#
-# Console display driver support
-#
-CONFIG_DUMMY_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE is not set
-
-#
-# Logo configuration
-#
-# CONFIG_LOGO is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Sound
-#
-# CONFIG_SOUND is not set
-
-#
-# USB support
-#
-# CONFIG_USB_ARCH_HAS_HCD is not set
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
-# CONFIG_MMC is not set
-
-#
-# InfiniBand support
-#
-# CONFIG_INFINIBAND is not set
-
-#
-# Character devices
-#
-CONFIG_AMIGA_BUILTIN_SERIAL=y
-# CONFIG_MULTIFACE_III_TTY is not set
-# CONFIG_GVPIOEXT is not set
-# CONFIG_SERIAL_CONSOLE is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT3_FS is not set
-# CONFIG_JBD is not set
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-
-#
-# XFS support
-#
-# CONFIG_XFS_FS is not set
-CONFIG_MINIX_FS=y
-# CONFIG_ROMFS_FS is not set
-# CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
-CONFIG_MSDOS_FS=y
-# CONFIG_VFAT_FS is not set
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
-CONFIG_SYSFS=y
-# CONFIG_DEVFS_FS is not set
-# CONFIG_DEVPTS_FS_XATTR is not set
-# CONFIG_TMPFS is not set
-# CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
-CONFIG_NFS_FS=y
-# CONFIG_NFS_V3 is not set
-# CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
-# CONFIG_NFSD is not set
-CONFIG_LOCKD=y
-CONFIG_SUNRPC=y
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-# CONFIG_SMB_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_AMIGA_PARTITION=y
-CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
-CONFIG_NLS_CODEPAGE_437=y
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-# CONFIG_NLS_ISO8859_1 is not set
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-# CONFIG_NLS_UTF8 is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-# CONFIG_DEBUG_KERNEL is not set
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_DEBUG_BUGVERBOSE=y
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-# CONFIG_CRYPTO is not set
-
-#
-# Hardware crypto devices
-#
-
-#
-# Library routines
-#
-# CONFIG_CRC_CCITT is not set
-CONFIG_CRC32=y
-# CONFIG_LIBCRC32C is not set
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 72097dacabd3..1c62381f5c23 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -482,10 +482,13 @@ endif
 # be 16kb aligned or the handling of the current variable will break.
 # Simplified: what IP22 does at 128MB+ in ksegN, IP28 does at 512MB+ in xkphys
 #
-#core-$(CONFIG_SGI_IP28)                += arch/mips/sgi-ip22/ arch/mips/arc/arc_con.o
+ifdef CONFIG_SGI_IP28
+  ifeq ($(call cc-option-yn,-mr10k-cache-barrier=1), n)
+      $(error gcc doesn't support needed option -mr10k-cache-barrier=1)
+  endif
+endif
 core-$(CONFIG_SGI_IP28)         += arch/mips/sgi-ip22/
 cflags-$(CONFIG_SGI_IP28)       += -mr10k-cache-barrier=1 -Iinclude/asm-mips/mach-ip28
-#cflags-$(CONFIG_SGI_IP28)      += -Iinclude/asm-mips/mach-ip28
 load-$(CONFIG_SGI_IP28)         += 0xa800000020004000
 
 #
diff --git a/arch/mips/au1000/common/cputable.c b/arch/mips/au1000/common/cputable.c
index d8df5fdb045f..5c0d35d6e22a 100644
--- a/arch/mips/au1000/common/cputable.c
+++ b/arch/mips/au1000/common/cputable.c
@@ -22,24 +22,24 @@ struct cpu_spec* cur_cpu_spec[NR_CPUS];
 /* With some thought, we can probably use the mask to reduce the
  * size of the table.
  */
-struct cpu_spec cpu_specs[] = {
-    { 0xffffffff, 0x00030100, "Au1000 DA", 1, 0 },
-    { 0xffffffff, 0x00030201, "Au1000 HA", 1, 0 },
-    { 0xffffffff, 0x00030202, "Au1000 HB", 1, 0 },
-    { 0xffffffff, 0x00030203, "Au1000 HC", 1, 1 },
-    { 0xffffffff, 0x00030204, "Au1000 HD", 1, 1 },
-    { 0xffffffff, 0x01030200, "Au1500 AB", 1, 1 },
-    { 0xffffffff, 0x01030201, "Au1500 AC", 0, 1 },
-    { 0xffffffff, 0x01030202, "Au1500 AD", 0, 1 },
-    { 0xffffffff, 0x02030200, "Au1100 AB", 1, 1 },
-    { 0xffffffff, 0x02030201, "Au1100 BA", 1, 1 },
-    { 0xffffffff, 0x02030202, "Au1100 BC", 1, 1 },
-    { 0xffffffff, 0x02030203, "Au1100 BD", 0, 1 },
-    { 0xffffffff, 0x02030204, "Au1100 BE", 0, 1 },
-    { 0xffffffff, 0x03030200, "Au1550 AA", 0, 1 },
-    { 0xffffffff, 0x04030200, "Au1200 AB", 0, 0 },
-    { 0xffffffff, 0x04030201, "Au1200 AC", 1, 0 },
-    { 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0 },
+struct cpu_spec cpu_specs[] = {
+        { 0xffffffff, 0x00030100, "Au1000 DA", 1, 0, 1 },
+        { 0xffffffff, 0x00030201, "Au1000 HA", 1, 0, 1 },
+        { 0xffffffff, 0x00030202, "Au1000 HB", 1, 0, 1 },
+        { 0xffffffff, 0x00030203, "Au1000 HC", 1, 1, 0 },
+        { 0xffffffff, 0x00030204, "Au1000 HD", 1, 1, 0 },
+        { 0xffffffff, 0x01030200, "Au1500 AB", 1, 1, 0 },
+        { 0xffffffff, 0x01030201, "Au1500 AC", 0, 1, 0 },
+        { 0xffffffff, 0x01030202, "Au1500 AD", 0, 1, 0 },
+        { 0xffffffff, 0x02030200, "Au1100 AB", 1, 1, 0 },
+        { 0xffffffff, 0x02030201, "Au1100 BA", 1, 1, 0 },
+        { 0xffffffff, 0x02030202, "Au1100 BC", 1, 1, 0 },
+        { 0xffffffff, 0x02030203, "Au1100 BD", 0, 1, 0 },
+        { 0xffffffff, 0x02030204, "Au1100 BE", 0, 1, 0 },
+        { 0xffffffff, 0x03030200, "Au1550 AA", 0, 1, 0 },
+        { 0xffffffff, 0x04030200, "Au1200 AB", 0, 0, 0 },
+        { 0xffffffff, 0x04030201, "Au1200 AC", 1, 0, 0 },
+        { 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0, 0 }
 };
 
 void
diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/au1000/common/setup.c
index d885e3848ec6..9e4ab80caab6 100644
--- a/arch/mips/au1000/common/setup.c
+++ b/arch/mips/au1000/common/setup.c
@@ -57,7 +57,7 @@ void __init plat_mem_setup(void)
 {
         struct  cpu_spec *sp;
         char *argptr;
-        unsigned long prid, cpupll, bclk = 1;
+        unsigned long prid, cpufreq, bclk = 1;
 
         set_cpuspec();
         sp = cur_cpu_spec[0];
@@ -65,8 +65,15 @@ void __init plat_mem_setup(void)
         board_setup();  /* board specific setup */
 
         prid = read_c0_prid();
-        cpupll = (au_readl(0xB1900060) & 0x3F) * 12;
-        printk("(PRId %08lx) @ %ldMHZ\n", prid, cpupll);
+        if (sp->cpu_pll_wo)
+#ifdef CONFIG_SOC_AU1000_FREQUENCY
+                cpufreq = CONFIG_SOC_AU1000_FREQUENCY / 1000000;
+#else
+                cpufreq = 396;
+#endif
+        else
+                cpufreq = (au_readl(SYS_CPUPLL) & 0x3F) * 12;
+        printk(KERN_INFO "(PRID %08lx) @ %ld MHz\n", prid, cpufreq);
 
         bclk = sp->cpu_bclk;
         if (bclk)
diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c
index f113b512d7b1..e122bbc6cd88 100644
--- a/arch/mips/au1000/common/time.c
+++ b/arch/mips/au1000/common/time.c
@@ -209,18 +209,22 @@ unsigned long cal_r4koff(void)
                 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
                 au_writel(0, SYS_TOYWRITE);
                 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
+        } else
+                no_au1xxx_32khz = 1;
 
-                cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) *
-                        AU1000_SRC_CLK;
-        }
-        else {
-                /* The 32KHz oscillator isn't running, so assume there
-                 * isn't one and grab the processor speed from the PLL.
-                 * NOTE: some old silicon doesn't allow reading the PLL.
-                 */
+        /*
+         * On early Au1000, sys_cpupll was write-only. Since these
+         * silicon versions of Au1000 are not sold by AMD, we don't bend
+         * over backwards trying to determine the frequency.
+         */
+        if (cur_cpu_spec[0]->cpu_pll_wo)
+#ifdef CONFIG_SOC_AU1000_FREQUENCY
+                cpu_speed = CONFIG_SOC_AU1000_FREQUENCY;
+#else
+                cpu_speed = 396000000;
+#endif
+        else
                 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
-                no_au1xxx_32khz = 1;
-        }
         mips_hpt_frequency = cpu_speed;
         // Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16)
         set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16));
diff --git a/arch/mips/au1000/xxs1500/board_setup.c b/arch/mips/au1000/xxs1500/board_setup.c
index a9237f41933d..b2e413e597a8 100644
--- a/arch/mips/au1000/xxs1500/board_setup.c
+++ b/arch/mips/au1000/xxs1500/board_setup.c
@@ -33,11 +33,10 @@
 #include <asm/cpu.h>
 #include <asm/bootinfo.h>
 #include <asm/irq.h>
-#include <asm/keyboard.h>
 #include <asm/mipsregs.h>
 #include <asm/reboot.h>
 #include <asm/pgtable.h>
-#include <asm/au1000.h>
+#include <asm/mach-au1x00/au1000.h>
 
 void board_reset(void)
 {
diff --git a/arch/mips/au1000/xxs1500/irqmap.c b/arch/mips/au1000/xxs1500/irqmap.c
index 389349295d70..a343da134334 100644
--- a/arch/mips/au1000/xxs1500/irqmap.c
+++ b/arch/mips/au1000/xxs1500/irqmap.c
@@ -45,7 +45,7 @@
 #include <asm/io.h>
 #include <asm/mipsregs.h>
 #include <asm/system.h>
-#include <asm/au1000.h>
+#include <asm/mach-au1x00/au1000.h>
 
 struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
         { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0},
diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig
index abf70d74e9d7..3b42cea2e402 100644
--- a/arch/mips/configs/bigsur_defconfig
+++ b/arch/mips/configs/bigsur_defconfig
@@ -1,58 +1,48 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.20
-# Tue Feb 20 21:47:22 2007
+# Linux kernel version: 2.6.25-rc7
+# Mon Mar 31 08:11:19 2008
 #
 CONFIG_MIPS=y
 
 #
 # Machine selection
 #
-CONFIG_ZONE_DMA=y
-# CONFIG_MIPS_MTX1 is not set
-# CONFIG_MIPS_BOSPORUS is not set
-# CONFIG_MIPS_PB1000 is not set
-# CONFIG_MIPS_PB1100 is not set
-# CONFIG_MIPS_PB1500 is not set
-# CONFIG_MIPS_PB1550 is not set
-# CONFIG_MIPS_PB1200 is not set
-# CONFIG_MIPS_DB1000 is not set
-# CONFIG_MIPS_DB1100 is not set
-# CONFIG_MIPS_DB1500 is not set
-# CONFIG_MIPS_DB1550 is not set
-# CONFIG_MIPS_DB1200 is not set
-# CONFIG_MIPS_MIRAGE is not set
+# CONFIG_MACH_ALCHEMY is not set
 # CONFIG_BASLER_EXCITE is not set
+# CONFIG_BCM47XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_LEMOTE_FULONG is not set
 # CONFIG_MIPS_ATLAS is not set
 # CONFIG_MIPS_MALTA is not set
 # CONFIG_MIPS_SEAD is not set
-# CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
-# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MIPS_XXS1500 is not set
+# CONFIG_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_MACH_VR41XX is not set
+# CONFIG_PMC_MSP is not set
 # CONFIG_PMC_YOSEMITE is not set
-# CONFIG_MARKEINS is not set
 # CONFIG_SGI_IP22 is not set
 # CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
 # CONFIG_SGI_IP32 is not set
-CONFIG_SIBYTE_BIGSUR=y
-# CONFIG_SIBYTE_SWARM is not set
-# CONFIG_SIBYTE_SENTOSA is not set
-# CONFIG_SIBYTE_RHONE is not set
-# CONFIG_SIBYTE_CARMEL is not set
-# CONFIG_SIBYTE_LITTLESUR is not set
 # CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
 # CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+CONFIG_SIBYTE_BIGSUR=y
 # CONFIG_SNI_RM is not set
 # CONFIG_TOSHIBA_JMR3927 is not set
 # CONFIG_TOSHIBA_RBTX4927 is not set
 # CONFIG_TOSHIBA_RBTX4938 is not set
+# CONFIG_WR_PPMC is not set
 CONFIG_SIBYTE_BCM1x80=y
 CONFIG_SIBYTE_SB1xxx_SOC=y
 # CONFIG_CPU_SB1_PASS_1 is not set
@@ -68,9 +58,11 @@ CONFIG_SIBYTE_CFE=y
 # CONFIG_SIBYTE_CFE_CONSOLE is not set
 # CONFIG_SIBYTE_BUS_WATCHER is not set
 # CONFIG_SIBYTE_TBPROF is not set
+CONFIG_SIBYTE_HAS_ZBUS_PROFILING=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
@@ -81,11 +73,17 @@ CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
 # CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
 CONFIG_CEVT_BCM1480=y
 CONFIG_CSRC_BCM1480=y
+CONFIG_CFE=y
 CONFIG_DMA_COHERENT=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_HOTPLUG_CPU is not set
+# CONFIG_NO_IOPORT is not set
 CONFIG_CPU_BIG_ENDIAN=y
 # CONFIG_CPU_LITTLE_ENDIAN is not set
 CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
 CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
 CONFIG_SWAP_IO_SPACE=y
 CONFIG_BOOT_ELF32=y
 CONFIG_MIPS_L1_CACHE_SHIFT=5
@@ -93,10 +91,6 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
 #
 # CPU selection
 #
-CONFIG_TICK_ONESHOT=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 # CONFIG_CPU_LOONGSON2 is not set
 # CONFIG_CPU_MIPS32_R1 is not set
 # CONFIG_CPU_MIPS32_R2 is not set
@@ -137,14 +131,15 @@ CONFIG_PAGE_SIZE_4KB=y
 CONFIG_MIPS_MT_DISABLED=y
 # CONFIG_MIPS_MT_SMP is not set
 # CONFIG_MIPS_MT_SMTC is not set
-# CONFIG_MIPS_VPE_LOADER is not set
 CONFIG_CPU_HAS_LLSC=y
 CONFIG_CPU_HAS_SYNC=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_IRQ_PER_CPU=y
 CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
 CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
@@ -152,13 +147,19 @@ CONFIG_FLATMEM_MANUAL=y
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 # CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
 CONFIG_SPLIT_PTLOCK_CPUS=4
 CONFIG_RESOURCES_64BIT=y
-CONFIG_ZONE_DMA_FLAG=1
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
 CONFIG_SMP=y
 CONFIG_SYS_SUPPORTS_SMP=y
 CONFIG_NR_CPUS_DEFAULT_4=y
 CONFIG_NR_CPUS=4
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 # CONFIG_HZ_48 is not set
 # CONFIG_HZ_100 is not set
 # CONFIG_HZ_128 is not set
@@ -171,38 +172,45 @@ CONFIG_HZ=1000
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
-# CONFIG_PREEMPT_BKL is not set
 # CONFIG_KEXEC is not set
+CONFIG_SECCOMP=y
 CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_LOCK_KERNEL=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
 CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
-# CONFIG_AUDIT is not set
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_AUDIT=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
-# CONFIG_CPUSETS is not set
+CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
 CONFIG_SYSFS_DEPRECATED=y
-# CONFIG_RELAY is not set
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SYSCTL=y
@@ -211,24 +219,33 @@ CONFIG_EMBEDDED=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
-# CONFIG_HOTPLUG is not set
+CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_SLAB=y
 CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
@@ -236,12 +253,10 @@ CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SRCVERSION_ALL=y
 CONFIG_KMOD=y
 CONFIG_STOP_MACHINE=y
-
-#
-# Block layer
-#
 CONFIG_BLOCK=y
 # CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_BLOCK_COMPAT=y
 
 #
 # IO Schedulers
@@ -255,6 +270,7 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
 
 #
 # Bus options (PCI, PCMCIA, EISA, ISA, TC)
@@ -262,23 +278,19 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 CONFIG_HW_HAS_PCI=y
 CONFIG_PCI=y
 CONFIG_PCI_DOMAINS=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
 CONFIG_PCI_DEBUG=y
 CONFIG_MMU=y
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-
-#
-# PCI Hotplug Support
-#
+CONFIG_ZONE_DMA32=y
+# CONFIG_PCCARD is not set
+# CONFIG_HOTPLUG_PCI is not set
 
 #
 # Executable file formats
 #
 CONFIG_BINFMT_ELF=y
 # CONFIG_BINFMT_MISC is not set
-# CONFIG_BUILD_ELF64 is not set
 CONFIG_MIPS32_COMPAT=y
 CONFIG_COMPAT=y
 CONFIG_SYSVIPC_COMPAT=y
@@ -292,7 +304,6 @@ CONFIG_BINFMT_ELF32=y
 CONFIG_PM=y
 # CONFIG_PM_LEGACY is not set
 # CONFIG_PM_DEBUG is not set
-# CONFIG_PM_SYSFS_DEPRECATED is not set
 
 #
 # Networking
@@ -302,7 +313,6 @@ CONFIG_NET=y
 #
 # Networking options
 #
-# CONFIG_NETDEBUG is not set
 CONFIG_PACKET=y
 CONFIG_PACKET_MMAP=y
 CONFIG_UNIX=y
@@ -310,10 +320,11 @@ CONFIG_XFRM=y
 CONFIG_XFRM_USER=m
 # CONFIG_XFRM_SUB_POLICY is not set
 CONFIG_XFRM_MIGRATE=y
+# CONFIG_XFRM_STATISTICS is not set
 CONFIG_NET_KEY=y
 CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
+CONFIG_IP_MULTICAST=y
 # CONFIG_IP_ADVANCED_ROUTER is not set
 CONFIG_IP_FIB_HASH=y
 CONFIG_IP_PNP=y
@@ -322,41 +333,141 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_IP_PNP_RARP is not set
 # CONFIG_NET_IPIP is not set
 # CONFIG_NET_IPGRE is not set
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
 # CONFIG_ARPD is not set
 # CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
 CONFIG_INET_XFRM_MODE_TRANSPORT=m
 CONFIG_INET_XFRM_MODE_TUNNEL=m
 CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=y
 CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 CONFIG_TCP_MD5SIG=y
-# CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
+CONFIG_IP_VS=m
+# CONFIG_IP_VS_DEBUG is not set
+CONFIG_IP_VS_TAB_BITS=12
+
+#
+# IPVS transport protocol load balancing support
+#
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+
+#
+# IPVS scheduler
+#
+CONFIG_IP_VS_RR=m
+CONFIG_IP_VS_WRR=m
+CONFIG_IP_VS_LC=m
+CONFIG_IP_VS_WLC=m
+CONFIG_IP_VS_LBLC=m
+CONFIG_IP_VS_LBLCR=m
+CONFIG_IP_VS_DH=m
+CONFIG_IP_VS_SH=m
+CONFIG_IP_VS_SED=m
+CONFIG_IP_VS_NQ=m
+
+#
+# IPVS application helper
+#
+CONFIG_IP_VS_FTP=m
+CONFIG_IPV6=m
+CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+CONFIG_IPV6_MIP6=m
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_TUNNEL=m
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
 CONFIG_NETWORK_SECMARK=y
-# CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+# CONFIG_NETFILTER_ADVANCED is not set
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_SECMARK=y
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CT_NETLINK=m
+CONFIG_NETFILTER_XTABLES=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_SECMARK=m
+CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+# CONFIG_NF_NAT_TFTP is not set
+# CONFIG_NF_NAT_AMANDA is not set
+# CONFIG_NF_NAT_PPTP is not set
+# CONFIG_NF_NAT_H323 is not set
+CONFIG_NF_NAT_SIP=m
+CONFIG_IP_NF_MANGLE=m
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV6=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_MANGLE=m
 # CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
+CONFIG_IP_SCTP=m
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
@@ -369,10 +480,6 @@ CONFIG_NETWORK_SECMARK=y
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 
 #
@@ -380,9 +487,21 @@ CONFIG_NETWORK_SECMARK=y
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_FIB_RULES=y
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -391,85 +510,70 @@ CONFIG_NETWORK_SECMARK=y
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=m
 # CONFIG_DEBUG_DRIVER is not set
 # CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
 # CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
 # CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
 # CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-# CONFIG_PNPACPI is not set
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_CPQ_DA is not set
 # CONFIG_BLK_CPQ_CISS_DA is not set
 # CONFIG_BLK_DEV_DAC960 is not set
 # CONFIG_BLK_DEV_UMEM is not set
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=m
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_CRYPTOLOOP=m
 CONFIG_BLK_DEV_NBD=m
 # CONFIG_BLK_DEV_SX8 is not set
 # CONFIG_BLK_DEV_RAM is not set
-CONFIG_BLK_DEV_INITRD=y
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
-
-#
-# Misc devices
-#
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+# CONFIG_EEPROM_93CX6 is not set
 CONFIG_SGI_IOC4=m
 # CONFIG_TIFM_CORE is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
 CONFIG_IDE=y
 CONFIG_IDE_MAX_HWIFS=4
 CONFIG_BLK_DEV_IDE=y
 
 #
-# Please see Documentation/ide.txt for help/info on IDE drives
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
 #
 # CONFIG_BLK_DEV_IDE_SATA is not set
 CONFIG_BLK_DEV_IDEDISK=y
 # CONFIG_IDEDISK_MULTI_MODE is not set
 CONFIG_BLK_DEV_IDECD=y
+CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
 CONFIG_BLK_DEV_IDETAPE=y
 CONFIG_BLK_DEV_IDEFLOPPY=y
+# CONFIG_BLK_DEV_IDESCSI is not set
 # CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
 
 #
 # IDE chipset support/bugfixes
 #
 CONFIG_IDE_GENERIC=y
+# CONFIG_BLK_DEV_PLATFORM is not set
+CONFIG_BLK_DEV_IDEDMA_SFF=y
+
+#
+# PCI IDE chipsets support
+#
 CONFIG_BLK_DEV_IDEPCI=y
-# CONFIG_IDEPCI_SHARE_IRQ is not set
+CONFIG_IDEPCI_PCIBUS_ORDER=y
 # CONFIG_BLK_DEV_OFFBOARD is not set
 CONFIG_BLK_DEV_GENERIC=y
 # CONFIG_BLK_DEV_OPTI621 is not set
 CONFIG_BLK_DEV_IDEDMA_PCI=y
-# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
-# CONFIG_IDEDMA_PCI_AUTO is not set
 # CONFIG_BLK_DEV_AEC62XX is not set
 # CONFIG_BLK_DEV_ALI15X3 is not set
 # CONFIG_BLK_DEV_AMD74XX is not set
@@ -495,87 +599,196 @@ CONFIG_BLK_DEV_IT8213=m
 # CONFIG_BLK_DEV_VIA82CXXX is not set
 CONFIG_BLK_DEV_TC86C001=m
 # CONFIG_BLK_DEV_IDE_SWARM is not set
-# CONFIG_IDE_ARM is not set
 CONFIG_BLK_DEV_IDEDMA=y
-# CONFIG_IDEDMA_IVB is not set
-# CONFIG_IDEDMA_AUTO is not set
+CONFIG_IDE_ARCH_OBSOLETE_INIT=y
 # CONFIG_BLK_DEV_HD is not set
 
 #
 # SCSI device support
 #
 # CONFIG_RAID_ATTRS is not set
-# CONFIG_SCSI is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
 # CONFIG_SCSI_NETLINK is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
-# CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_MVSAS is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_SRP is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+# CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_SVW is not set
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_SIL is not set
+CONFIG_SATA_SIL24=y
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_PDC2027X is not set
+CONFIG_PATA_SIL680=y
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+# CONFIG_PATA_PLATFORM is not set
 # CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
 # CONFIG_FUSION is not set
 
 #
 # IEEE 1394 (FireWire) support
 #
+# CONFIG_FIREWIRE is not set
 # CONFIG_IEEE1394 is not set
-
-#
-# I2O device support
-#
 # CONFIG_I2O is not set
-
-#
-# Network device support
-#
 CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-
-#
-# ARCnet devices
-#
+# CONFIG_VETH is not set
 # CONFIG_ARCNET is not set
-
-#
-# PHY device support
-#
-# CONFIG_PHYLIB is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
+# CONFIG_AX88796 is not set
 # CONFIG_HAPPYMEAL is not set
 # CONFIG_SUNGEM is not set
 # CONFIG_CASSINI is not set
 # CONFIG_NET_VENDOR_3COM is not set
 # CONFIG_DM9000 is not set
-
-#
-# Tulip family network device support
-#
 # CONFIG_NET_TULIP is not set
 # CONFIG_HP100 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
 # CONFIG_NET_PCI is not set
-
-#
-# Ethernet (1000 Mbit)
-#
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
 # CONFIG_ACENIC is not set
 # CONFIG_DL2K is not set
 # CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_E1000E_ENABLED is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
 # CONFIG_NS83820 is not set
 # CONFIG_HAMACHI is not set
 # CONFIG_YELLOWFIN is not set
@@ -585,52 +798,53 @@ CONFIG_SB1250_MAC=y
 # CONFIG_SKGE is not set
 # CONFIG_SKY2 is not set
 # CONFIG_SK98LIN is not set
+# CONFIG_VIA_VELOCITY is not set
 # CONFIG_TIGON3 is not set
 # CONFIG_BNX2 is not set
 # CONFIG_QLA3XXX is not set
 # CONFIG_ATL1 is not set
-
-#
-# Ethernet (10000 Mbit)
-#
+CONFIG_NETDEV_10000=y
 # CONFIG_CHELSIO_T1 is not set
 CONFIG_CHELSIO_T3=m
+# CONFIG_IXGBE is not set
 # CONFIG_IXGB is not set
 # CONFIG_S2IO is not set
 # CONFIG_MYRI10GE is not set
 CONFIG_NETXEN_NIC=m
-
-#
-# Token Ring devices
-#
+# CONFIG_NIU is not set
+# CONFIG_MLX4_CORE is not set
+# CONFIG_TEHUTI is not set
+# CONFIG_BNX2X is not set
 # CONFIG_TR is not set
 
 #
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# Wan interfaces
+# Wireless LAN
 #
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 # CONFIG_WAN is not set
 # CONFIG_FDDI is not set
 # CONFIG_HIPPI is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
+CONFIG_PPP=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
+CONFIG_SLIP=m
+CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLHC=m
+CONFIG_SLIP_SMART=y
+CONFIG_SLIP_MODE_SLIP6=y
+# CONFIG_NET_FC is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
 # CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
 # CONFIG_PHONE is not set
 
 #
@@ -660,17 +874,16 @@ CONFIG_SERIAL_NONSTANDARD=y
 # CONFIG_DIGIEPCA is not set
 # CONFIG_MOXA_INTELLIO is not set
 # CONFIG_MOXA_SMARTIO is not set
-CONFIG_MOXA_SMARTIO_NEW=m
 # CONFIG_ISI is not set
 # CONFIG_SYNCLINKMP is not set
 # CONFIG_SYNCLINK_GT is not set
 # CONFIG_N_HDLC is not set
+# CONFIG_RISCOM8 is not set
 # CONFIG_SPECIALIX is not set
 # CONFIG_SX is not set
 # CONFIG_RIO is not set
 # CONFIG_STALDRV is not set
-CONFIG_SERIAL_SB1250_DUART=y
-CONFIG_SERIAL_SB1250_DUART_CONSOLE=y
+# CONFIG_NOZOMI is not set
 
 #
 # Serial drivers
@@ -680,39 +893,24 @@ CONFIG_SERIAL_SB1250_DUART_CONSOLE=y
 #
 # Non-8250 serial port support
 #
+CONFIG_SERIAL_SB1250_DUART=y
+CONFIG_SERIAL_SB1250_DUART_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_JSM is not set
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
 # CONFIG_HW_RANDOM is not set
 # CONFIG_RTC is not set
-CONFIG_GEN_RTC=y
-# CONFIG_GEN_RTC_X is not set
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
-# CONFIG_DRM is not set
 # CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
 # CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
+CONFIG_DEVPORT=y
 CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=y
 
 #
@@ -736,29 +934,30 @@ CONFIG_I2C_CHARDEV=y
 # CONFIG_I2C_NFORCE2 is not set
 # CONFIG_I2C_OCORES is not set
 # CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_PASEMI is not set
 # CONFIG_I2C_PROSAVAGE is not set
 # CONFIG_I2C_SAVAGE4 is not set
 CONFIG_I2C_SIBYTE=y
+# CONFIG_I2C_SIMTEC is not set
 # CONFIG_I2C_SIS5595 is not set
 # CONFIG_I2C_SIS630 is not set
 # CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_TAOS_EVM is not set
 # CONFIG_I2C_STUB is not set
 # CONFIG_I2C_VIA is not set
 # CONFIG_I2C_VIAPRO is not set
 # CONFIG_I2C_VOODOO3 is not set
-# CONFIG_I2C_PCA_ISA is not set
 
 #
 # Miscellaneous I2C Chip support
 #
-CONFIG_SENSORS_DS1337=y
-CONFIG_SENSORS_DS1374=y
+# CONFIG_DS1682 is not set
 CONFIG_SENSORS_EEPROM=y
 CONFIG_SENSORS_PCF8574=y
-CONFIG_SENSORS_PCA9539=y
+# CONFIG_PCF8575 is not set
 CONFIG_SENSORS_PCF8591=y
+# CONFIG_TPS65010 is not set
 CONFIG_SENSORS_MAX6875=y
+# CONFIG_SENSORS_TSL2550 is not set
 CONFIG_I2C_DEBUG_CORE=y
 CONFIG_I2C_DEBUG_ALGO=y
 CONFIG_I2C_DEBUG_BUS=y
@@ -769,43 +968,49 @@ CONFIG_I2C_DEBUG_CHIP=y
 #
 # CONFIG_SPI is not set
 # CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
 
 #
-# Dallas's 1-wire bus
+# Sonics Silicon Backplane
 #
-# CONFIG_W1 is not set
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
-# Hardware Monitoring support
+# Multifunction device drivers
 #
-# CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
+# CONFIG_MFD_SM501 is not set
 
 #
 # Multimedia devices
 #
 # CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
 
 #
 # Graphics support
 #
-# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 # CONFIG_FB is not set
 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
-# Sound
+# Display device support
 #
-# CONFIG_SOUND is not set
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
-# USB support
+# Sound
 #
+# CONFIG_SOUND is not set
+CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
 CONFIG_USB_ARCH_HAS_EHCI=y
@@ -814,104 +1019,73 @@ CONFIG_USB_ARCH_HAS_EHCI=y
 #
 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
 #
-
-#
-# USB Gadget Support
-#
 # CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
 # CONFIG_MMC is not set
-
-#
-# LED devices
-#
+# CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
-
-#
-# LED drivers
-#
-
-#
-# LED Triggers
-#
-
-#
-# InfiniBand support
-#
 # CONFIG_INFINIBAND is not set
-
-#
-# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
-#
-
-#
-# Real Time Clock
-#
+CONFIG_RTC_LIB=y
 # CONFIG_RTC_CLASS is not set
 
 #
-# DMA Engine support
-#
-# CONFIG_DMA_ENGINE is not set
-
-#
-# DMA Clients
-#
-
-#
-# DMA Devices
-#
-
-#
-# Auxiliary Display support
-#
-
-#
-# Virtualization
+# Userspace I/O
 #
+# CONFIG_UIO is not set
 
 #
 # File systems
 #
-CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS=m
 CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
+# CONFIG_EXT2_FS_POSIX_ACL is not set
+# CONFIG_EXT2_FS_SECURITY is not set
 # CONFIG_EXT2_FS_XIP is not set
-# CONFIG_EXT3_FS is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
 # CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
 CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
-CONFIG_FS_POSIX_ACL=y
+# CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
 # CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=m
+CONFIG_QUOTACTL=y
+CONFIG_AUTOFS_FS=m
+CONFIG_AUTOFS4_FS=m
+CONFIG_FUSE_FS=m
 
 #
 # CD-ROM/DVD Filesystems
 #
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
 
 #
 # DOS/FAT/NT Filesystems
 #
-# CONFIG_MSDOS_FS is not set
-# CONFIG_VFAT_FS is not set
-# CONFIG_NTFS_FS is not set
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_NTFS_FS=m
+# CONFIG_NTFS_DEBUG is not set
+CONFIG_NTFS_RW=y
 
 #
 # Pseudo filesystems
@@ -923,7 +1097,6 @@ CONFIG_SYSFS=y
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
 CONFIG_CONFIGFS_FS=m
 
 #
@@ -939,14 +1112,13 @@ CONFIG_CONFIGFS_FS=m
 # CONFIG_EFS_FS is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
@@ -958,6 +1130,7 @@ CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
@@ -965,37 +1138,61 @@ CONFIG_SUNRPC=y
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
-# CONFIG_NLS is not set
-
-#
-# Distributed Lock Manager
-#
+CONFIG_NLS=m
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=m
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=m
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_UTF8=m
 CONFIG_DLM=m
-CONFIG_DLM_TCP=y
-# CONFIG_DLM_SCTP is not set
 # CONFIG_DLM_DEBUG is not set
 
 #
-# Profiling support
-#
-# CONFIG_PROFILING is not set
-
-#
 # Kernel hacking
 #
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_MAGIC_SYSRQ=y
 # CONFIG_UNUSED_SYMBOLS is not set
@@ -1003,8 +1200,8 @@ CONFIG_MAGIC_SYSRQ=y
 # CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_SHIRQ is not set
-CONFIG_LOG_BUF_SHIFT=16
 CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
 # CONFIG_DEBUG_SLAB is not set
@@ -1014,15 +1211,19 @@ CONFIG_DETECT_SOFTLOCKUP=y
 CONFIG_DEBUG_MUTEXES=y
 # CONFIG_DEBUG_LOCK_ALLOC is not set
 # CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
 # CONFIG_DEBUG_INFO is not set
 # CONFIG_DEBUG_VM is not set
 # CONFIG_DEBUG_LIST is not set
-CONFIG_FORCED_INLINING=y
+# CONFIG_DEBUG_SG is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
-CONFIG_CROSSCOMPILE=y
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
 CONFIG_CMDLINE=""
 # CONFIG_DEBUG_STACK_USAGE is not set
 # CONFIG_SB1XXX_CORELIS is not set
@@ -1034,23 +1235,22 @@ CONFIG_CMDLINE=""
 CONFIG_KEYS=y
 CONFIG_KEYS_DEBUG_PROC_KEYS=y
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
 CONFIG_CRYPTO=y
 CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_SEQIV=m
 CONFIG_CRYPTO_HASH=y
 CONFIG_CRYPTO_MANAGER=y
 CONFIG_CRYPTO_HMAC=y
 CONFIG_CRYPTO_XCBC=m
 CONFIG_CRYPTO_NULL=y
-CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD4=m
 CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
 CONFIG_CRYPTO_WP512=m
 CONFIG_CRYPTO_TGR192=m
 CONFIG_CRYPTO_GF128MUL=m
@@ -1058,39 +1258,50 @@ CONFIG_CRYPTO_ECB=m
 CONFIG_CRYPTO_CBC=m
 CONFIG_CRYPTO_PCBC=m
 CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_XTS=m
+CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_CCM=m
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_DES=m
 CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_BLOWFISH=y
-CONFIG_CRYPTO_TWOFISH=y
-CONFIG_CRYPTO_TWOFISH_COMMON=y
-CONFIG_CRYPTO_SERPENT=y
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+CONFIG_CRYPTO_SERPENT=m
 CONFIG_CRYPTO_AES=m
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
 CONFIG_CRYPTO_TEA=m
-# CONFIG_CRYPTO_ARC4 is not set
+CONFIG_CRYPTO_ARC4=m
 CONFIG_CRYPTO_KHAZAD=m
 CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_MICHAEL_MIC=y
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SALSA20=m
+CONFIG_CRYPTO_DEFLATE=m
+CONFIG_CRYPTO_MICHAEL_MIC=m
 # CONFIG_CRYPTO_CRC32C is not set
 CONFIG_CRYPTO_CAMELLIA=m
 # CONFIG_CRYPTO_TEST is not set
-
-#
-# Hardware crypto devices
-#
+CONFIG_CRYPTO_AUTHENC=m
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
-# CONFIG_CRC_CCITT is not set
+CONFIG_CRC_CCITT=m
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
-# CONFIG_LIBCRC32C is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=m
+CONFIG_AUDIT_GENERIC=y
+CONFIG_ZLIB_INFLATE=m
+CONFIG_ZLIB_DEFLATE=m
 CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/mips/kernel/gdb-stub.c b/arch/mips/kernel/gdb-stub.c
index 3191afa29ad8..25f4eab8ea9c 100644
--- a/arch/mips/kernel/gdb-stub.c
+++ b/arch/mips/kernel/gdb-stub.c
@@ -139,7 +139,6 @@
 #include <asm/system.h>
 #include <asm/gdb-stub.h>
 #include <asm/inst.h>
-#include <asm/smp.h>
 
 /*
  * external low-level support routines
@@ -656,6 +655,7 @@ void set_async_breakpoint(unsigned long *epc)
         *epc = (unsigned long)async_breakpoint;
 }
 
+#ifdef CONFIG_SMP
 static void kgdb_wait(void *arg)
 {
         unsigned flags;
@@ -668,6 +668,7 @@ static void kgdb_wait(void *arg)
 
         local_irq_restore(flags);
 }
+#endif
 
 /*
  * GDB stub needs to call kgdb_wait on all processor with interrupts
diff --git a/arch/mips/kernel/i8253.c b/arch/mips/kernel/i8253.c
index fc4aa07b6d35..38fa1a194bf4 100644
--- a/arch/mips/kernel/i8253.c
+++ b/arch/mips/kernel/i8253.c
@@ -15,6 +15,7 @@
 #include <asm/time.h>
 
 DEFINE_SPINLOCK(i8253_lock);
+EXPORT_SYMBOL(i8253_lock);
 
 /*
  * Initialize the PIT timer.
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index 9f85d4cecc5b..b45a7093ca2d 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -157,6 +157,6 @@ void __init time_init(void)
 {
         plat_time_init();
 
-        if (mips_clockevent_init() || !cpu_has_mfc0_count_bug())
+        if (!mips_clockevent_init() || !cpu_has_mfc0_count_bug())
                 init_mips_clocksource();
 }
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index eed2dc4273e0..39804c584edd 100644
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -262,13 +262,21 @@ void dump_mtregs(void)
 /* Find some VPE program space  */
 static void *alloc_progmem(unsigned long len)
 {
+        void *addr;
+
 #ifdef CONFIG_MIPS_VPE_LOADER_TOM
-        /* this means you must tell linux to use less memory than you physically have */
-        return pfn_to_kaddr(max_pfn);
+        /*
+         * This means you must tell Linux to use less memory than you
+         * physically have, for example by passing a mem= boot argument.
+         */
+        addr = pfn_to_kaddr(max_pfn);
+        memset(addr, 0, len);
 #else
-        // simple grab some mem for now
-        return kmalloc(len, GFP_KERNEL);
+        /* simple grab some mem for now */
+        addr = kzalloc(len, GFP_KERNEL);
 #endif
+
+        return addr;
 }
 
 static void release_progmem(void *ptr)
@@ -884,9 +892,10 @@ static int vpe_elfload(struct vpe * v)
         }
 
         v->load_addr = alloc_progmem(mod.core_size);
-        memset(v->load_addr, 0, mod.core_size);
+        if (!v->load_addr)
+                return -ENOMEM;
 
-        printk("VPE loader: loading to %p\n", v->load_addr);
+        pr_info("VPE loader: loading to %p\n", v->load_addr);
 
         if (relocate) {
                 for (i = 0; i < hdr->e_shnum; i++) {
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 6496925b5e29..77aefb4ebedd 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -361,6 +361,16 @@ static inline int has_valid_asid(const struct mm_struct *mm)
 #endif
 }
 
+static void r4k__flush_cache_vmap(void)
+{
+        r4k_blast_dcache();
+}
+
+static void r4k__flush_cache_vunmap(void)
+{
+        r4k_blast_dcache();
+}
+
 static inline void local_r4k_flush_cache_range(void * args)
 {
         struct vm_area_struct *vma = args;
@@ -1281,6 +1291,10 @@ void __cpuinit r4k_cache_init(void)
                                         PAGE_SIZE - 1);
         else
                 shm_align_mask = PAGE_SIZE-1;
+
+        __flush_cache_vmap      = r4k__flush_cache_vmap;
+        __flush_cache_vunmap    = r4k__flush_cache_vunmap;
+
         flush_cache_all         = cache_noop;
         __flush_cache_all       = r4k___flush_cache_all;
         flush_cache_mm          = r4k_flush_cache_mm;
diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c
index b09d56981d53..a9f7f1f5e9b4 100644
--- a/arch/mips/mm/c-tx39.c
+++ b/arch/mips/mm/c-tx39.c
@@ -122,6 +122,16 @@ static inline void tx39_blast_icache(void)
         local_irq_restore(flags);
 }
 
+static void tx39__flush_cache_vmap(void)
+{
+        tx39_blast_dcache();
+}
+
+static void tx39__flush_cache_vunmap(void)
+{
+        tx39_blast_dcache();
+}
+
 static inline void tx39_flush_cache_all(void)
 {
         if (!cpu_has_dc_aliases)
@@ -344,6 +354,8 @@ void __cpuinit tx39_cache_init(void)
         switch (current_cpu_type()) {
         case CPU_TX3912:
                 /* TX39/H core (writethru direct-map cache) */
+                __flush_cache_vmap      = tx39__flush_cache_vmap;
+                __flush_cache_vunmap    = tx39__flush_cache_vunmap;
                 flush_cache_all = tx39h_flush_icache_all;
                 __flush_cache_all       = tx39h_flush_icache_all;
                 flush_cache_mm          = (void *) tx39h_flush_icache_all;
@@ -369,6 +381,9 @@ void __cpuinit tx39_cache_init(void)
                 write_c0_wired(0);      /* set 8 on reset... */
                 /* board-dependent init code may set WBON */
 
+                __flush_cache_vmap      = tx39__flush_cache_vmap;
+                __flush_cache_vunmap    = tx39__flush_cache_vunmap;
+
                 flush_cache_all = tx39_flush_cache_all;
                 __flush_cache_all = tx39___flush_cache_all;
                 flush_cache_mm = tx39_flush_cache_mm;
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 51ab1faa027d..f5903679ee6a 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -30,6 +30,9 @@ void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page,
         unsigned long pfn);
 void (*flush_icache_range)(unsigned long start, unsigned long end);
 
+void (*__flush_cache_vmap)(void);
+void (*__flush_cache_vunmap)(void);
+
 /* MIPS specific cache operations */
 void (*flush_cache_sigtramp)(unsigned long addr);
 void (*local_flush_data_cache_page)(void * addr);
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 3a93d4ce2703..382738ca8a0b 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -307,6 +307,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
         case CPU_R12000:
         case CPU_R14000:
         case CPU_4KC:
+        case CPU_4KEC:
         case CPU_SB1:
         case CPU_SB1A:
         case CPU_4KSC:
diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c
index ab68c4318a30..87e2c8f54e2d 100644
--- a/arch/mips/pci/pci-bcm1480.c
+++ b/arch/mips/pci/pci-bcm1480.c
@@ -185,8 +185,8 @@ static struct resource bcm1480_mem_resource = {
 
 static struct resource bcm1480_io_resource = {
         .name   = "BCM1480 PCI I/O",
-        .start  = 0x2c000000UL,
-        .end    = 0x2dffffffUL,
+        .start  = A_BCM1480_PHYS_PCI_IO_MATCH_BYTES,
+        .end    = A_BCM1480_PHYS_PCI_IO_MATCH_BYTES + 0x1ffffffUL,
         .flags  = IORESOURCE_IO,
 };
 
@@ -194,6 +194,7 @@ struct pci_controller bcm1480_controller = {
         .pci_ops        = &bcm1480_pci_ops,
         .mem_resource   = &bcm1480_mem_resource,
         .io_resource    = &bcm1480_io_resource,
+        .io_offset      = A_BCM1480_PHYS_PCI_IO_MATCH_BYTES,
 };
 
 
@@ -251,6 +252,7 @@ static int __init bcm1480_pcibios_init(void)
 
         bcm1480_controller.io_map_base = (unsigned long)
                 ioremap(A_BCM1480_PHYS_PCI_IO_MATCH_BYTES, 65536);
+        bcm1480_controller.io_map_base -= bcm1480_controller.io_offset;
         set_io_port_base(bcm1480_controller.io_map_base);
         isa_slot_offset = (unsigned long)
                 ioremap(A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES, 1024*1024);
diff --git a/arch/mips/pci/pci-bcm1480ht.c b/arch/mips/pci/pci-bcm1480ht.c
index 005e7fecab08..f54f45412b0b 100644
--- a/arch/mips/pci/pci-bcm1480ht.c
+++ b/arch/mips/pci/pci-bcm1480ht.c
@@ -180,8 +180,8 @@ static struct resource bcm1480ht_mem_resource = {
 
 static struct resource bcm1480ht_io_resource = {
         .name   = "BCM1480 HT I/O",
-        .start  = 0x00000000UL,
-        .end    = 0x01ffffffUL,
+        .start  = A_BCM1480_PHYS_HT_IO_MATCH_BYTES,
+        .end    = A_BCM1480_PHYS_HT_IO_MATCH_BYTES + 0x01ffffffUL,
         .flags  = IORESOURCE_IO,
 };
 
@@ -191,29 +191,22 @@ struct pci_controller bcm1480ht_controller = {
         .io_resource    = &bcm1480ht_io_resource,
         .index          = 1,
         .get_busno      = bcm1480ht_pcibios_get_busno,
+        .io_offset      = A_BCM1480_PHYS_HT_IO_MATCH_BYTES,
 };
 
 static int __init bcm1480ht_pcibios_init(void)
 {
-        uint32_t cmdreg;
-
         ht_cfg_space = ioremap(A_BCM1480_PHYS_HT_CFG_MATCH_BITS, 16*1024*1024);
 
-        /*
-         * See if the PCI bus has been configured by the firmware.
-         */
-        cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0),
-                                     PCI_COMMAND));
-        if (!(cmdreg & PCI_COMMAND_MASTER)) {
-                printk("HT: Skipping HT probe. Bus is not initialized.\n");
-                iounmap(ht_cfg_space);
-                return 1; /* XXX */
-        }
+        /* CFE doesn't always init all HT paths, so we always scan */
         bcm1480ht_bus_status |= PCI_BUS_ENABLED;
 
         ht_eoi_space = (unsigned long)
                 ioremap(A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES,
                         4 * 1024 * 1024);
+        bcm1480ht_controller.io_map_base = (unsigned long)
+                ioremap(A_BCM1480_PHYS_HT_IO_MATCH_BYTES, 65536);
+        bcm1480ht_controller.io_map_base -= bcm1480ht_controller.io_offset;
 
         register_pci_controller(&bcm1480ht_controller);
 
diff --git a/arch/powerpc/boot/dts/cm5200.dts b/arch/powerpc/boot/dts/cm5200.dts
index 30737eafe68e..c6ca6319e4f7 100644
--- a/arch/powerpc/boot/dts/cm5200.dts
+++ b/arch/powerpc/boot/dts/cm5200.dts
@@ -212,13 +212,30 @@
                 ethernet@3000 {
                         device_type = "network";
                         compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
-                        reg = <3000 800>;
+                        reg = <3000 400>;
                         local-mac-address = [ 00 00 00 00 00 00 ];
                         interrupts = <2 5 0>;
                         interrupt-parent = <&mpc5200_pic>;
+                        phy-handle = <&phy0>;
+                };
+
+                mdio@3000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
+                        reg = <3000 400>;       // fec range, since we need to setup fec interrupts
+                        interrupts = <2 5 0>;   // these are for "mii command finished", not link changes & co.
+                        interrupt-parent = <&mpc5200_pic>;
+
+                        phy0: ethernet-phy@0 {
+                                device_type = "ethernet-phy";
+                                reg = <0>;
+                        };
                 };
 
                 i2c@3d40 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                         compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
                         reg = <3d40 40>;
                         interrupts = <2 10 0>;
@@ -231,4 +248,22 @@
                         reg = <8000 4000>;
                 };
         };
+
+        lpb {
+                model = "fsl,lpb";
+                compatible = "fsl,lpb";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                ranges = <0 0 fc000000 2000000>;
+
+                // 16-bit flash device at LocalPlus Bus CS0
+                flash@0,0 {
+                        compatible = "cfi-flash";
+                        reg = <0 0 2000000>;
+                        bank-width = <2>;
+                        device-width = <2>;
+                        #size-cells = <1>;
+                        #address-cells = <1>;
+                };
+        };
 };
diff --git a/arch/powerpc/boot/dts/lite5200.dts b/arch/powerpc/boot/dts/lite5200.dts
index 0d701c1bf539..09b4e16154d6 100644
--- a/arch/powerpc/boot/dts/lite5200.dts
+++ b/arch/powerpc/boot/dts/lite5200.dts
@@ -258,6 +258,21 @@
                         local-mac-address = [ 00 00 00 00 00 00 ];
                         interrupts = <2 5 0>;
                         interrupt-parent = <&mpc5200_pic>;
+                        phy-handle = <&phy0>;
+                };
+
+                mdio@3000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,mpc5200-mdio";
+                        reg = <3000 400>;       // fec range, since we need to setup fec interrupts
+                        interrupts = <2 5 0>;   // these are for "mii command finished", not link changes & co.
+                        interrupt-parent = <&mpc5200_pic>;
+
+                        phy0:ethernet-phy@1 {
+                                device_type = "ethernet-phy";
+                                reg = <1>;
+                        };
                 };
 
                 ata@3a00 {
diff --git a/arch/powerpc/boot/dts/motionpro.dts b/arch/powerpc/boot/dts/motionpro.dts
index 76951ab038ee..2b0dde058f8e 100644
--- a/arch/powerpc/boot/dts/motionpro.dts
+++ b/arch/powerpc/boot/dts/motionpro.dts
@@ -148,7 +148,6 @@
                         interrupt-parent = <&mpc5200_pic>;
                 };
 
-
                 spi@f00 {
                         compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
                         reg = <f00 20>;
@@ -209,10 +208,25 @@
                 ethernet@3000 {
                         device_type = "network";
                         compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
-                        reg = <3000 800>;
+                        reg = <3000 400>;
                         local-mac-address = [ 00 00 00 00 00 00 ];
                         interrupts = <2 5 0>;
                         interrupt-parent = <&mpc5200_pic>;
+                        phy-handle = <&phy0>;
+                };
+
+                mdio@3000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
+                        reg = <3000 400>;       // fec range, since we need to setup fec interrupts
+                        interrupts = <2 5 0>;   // these are for "mii command finished", not link changes & co.
+                        interrupt-parent = <&mpc5200_pic>;
+
+                        phy0: ethernet-phy@2 {
+                                device_type = "ethernet-phy";
+                                reg = <2>;
+                        };
                 };
 
                 ata@3a00 {
@@ -223,11 +237,19 @@
                 };
 
                 i2c@3d40 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                         compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
                         reg = <3d40 40>;
                         interrupts = <2 10 0>;
                         interrupt-parent = <&mpc5200_pic>;
                         fsl5200-clocking;
+
+                        rtc@68 {
+                                device_type = "rtc";
+                                compatible = "dallas,ds1339";
+                                reg = <68>;
+                        };
                 };
 
                 sram@8000 {
@@ -240,7 +262,8 @@
                 compatible = "fsl,lpb";
                 #address-cells = <2>;
                 #size-cells = <1>;
-                ranges = <1 0 50000000 00010000
+                ranges = <0 0 ff000000 01000000
+                          1 0 50000000 00010000
                           2 0 50010000 00010000
                           3 0 50020000 00010000>;
 
@@ -271,31 +294,15 @@
                         compatible = "promess,pro_module_dio";
                         reg = <3 800 2>;
                 };
-        };
 
-        pci@f0000d00 {
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
-                device_type = "pci";
-                compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
-                reg = <f0000d00 100>;
-                interrupt-map-mask = <f800 0 0 7>;
-                interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
-                                 c000 0 0 2 &mpc5200_pic 1 1 3
-                                 c000 0 0 3 &mpc5200_pic 1 2 3
-                                 c000 0 0 4 &mpc5200_pic 1 3 3
-
-                                 c800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
-                                 c800 0 0 2 &mpc5200_pic 1 2 3
-                                 c800 0 0 3 &mpc5200_pic 1 3 3
-                                 c800 0 0 4 &mpc5200_pic 0 0 3>;
-                clock-frequency = <0>; // From boot loader
-                interrupts = <2 8 0 2 9 0 2 a 0>;
-                interrupt-parent = <&mpc5200_pic>;
-                bus-range = <0 0>;
-                ranges = <42000000 0 80000000 80000000 0 20000000
-                          02000000 0 a0000000 a0000000 0 10000000
-                          01000000 0 00000000 b0000000 0 01000000>;
+                // 16-bit flash device at LocalPlus Bus CS0
+                flash@0,0 {
+                        compatible = "cfi-flash";
+                        reg = <0 0 01000000>;
+                        bank-width = <2>;
+                        device-width = <2>;
+                        #size-cells = <1>;
+                        #address-cells = <1>;
+                };
         };
 };
diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/boot/dts/mpc8377_mds.dts
index 49c05e97386c..eac8e1b59496 100644
--- a/arch/powerpc/boot/dts/mpc8377_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8377_mds.dts
@@ -255,14 +255,14 @@
                 };
 
                 sata@18000 {
-                        compatible = "fsl,mpc8379-sata";
+                        compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
                         reg = <0x18000 0x1000>;
                         interrupts = <44 0x8>;
                         interrupt-parent = <&ipic>;
                 };
 
                 sata@19000 {
-                        compatible = "fsl,mpc8379-sata";
+                        compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
                         reg = <0x19000 0x1000>;
                         interrupts = <45 0x8>;
                         interrupt-parent = <&ipic>;
diff --git a/arch/powerpc/boot/dts/mpc8377_rdb.dts b/arch/powerpc/boot/dts/mpc8377_rdb.dts
index 440aa4dfab0c..5bc09ad016f5 100644
--- a/arch/powerpc/boot/dts/mpc8377_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8377_rdb.dts
@@ -143,7 +143,6 @@
                         mode = "cpu";
                 };
 
-                /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
                 usb@23000 {
                         compatible = "fsl-usb2-dr";
                         reg = <0x23000 0x1000>;
@@ -151,7 +150,7 @@
                         #size-cells = <0>;
                         interrupt-parent = <&ipic>;
                         interrupts = <38 0x8>;
-                        phy_type = "utmi";
+                        phy_type = "ulpi";
                 };
 
                 mdio@24520 {
diff --git a/arch/powerpc/boot/dts/mpc8378_rdb.dts b/arch/powerpc/boot/dts/mpc8378_rdb.dts
index 92711534b179..711f9a30f9ab 100644
--- a/arch/powerpc/boot/dts/mpc8378_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8378_rdb.dts
@@ -143,7 +143,6 @@
                         mode = "cpu";
                 };
 
-                /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
                 usb@23000 {
                         compatible = "fsl-usb2-dr";
                         reg = <0x23000 0x1000>;
@@ -151,7 +150,7 @@
                         #size-cells = <0>;
                         interrupt-parent = <&ipic>;
                         interrupts = <38 0x8>;
-                        phy_type = "utmi";
+                        phy_type = "ulpi";
                 };
 
                 mdio@24520 {
diff --git a/arch/powerpc/boot/dts/mpc8379_mds.dts b/arch/powerpc/boot/dts/mpc8379_mds.dts
index fdb4a9255b24..6f78a9fd9826 100644
--- a/arch/powerpc/boot/dts/mpc8379_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8379_mds.dts
@@ -255,28 +255,28 @@
                 };
 
                 sata@18000 {
-                        compatible = "fsl,mpc8379-sata";
+                        compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
                         reg = <0x18000 0x1000>;
                         interrupts = <44 0x8>;
                         interrupt-parent = <&ipic>;
                 };
 
                 sata@19000 {
-                        compatible = "fsl,mpc8379-sata";
+                        compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
                         reg = <0x19000 0x1000>;
                         interrupts = <45 0x8>;
                         interrupt-parent = <&ipic>;
                 };
 
                 sata@1a000 {
-                        compatible = "fsl,mpc8379-sata";
+                        compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
                         reg = <0x1a000 0x1000>;
                         interrupts = <46 0x8>;
                         interrupt-parent = <&ipic>;
                 };
 
                 sata@1b000 {
-                        compatible = "fsl,mpc8379-sata";
+                        compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
                         reg = <0x1b000 0x1000>;
                         interrupts = <47 0x8>;
                         interrupt-parent = <&ipic>;
diff --git a/arch/powerpc/boot/dts/mpc8379_rdb.dts b/arch/powerpc/boot/dts/mpc8379_rdb.dts
index 0dda2fc558f8..c11ceb7d3299 100644
--- a/arch/powerpc/boot/dts/mpc8379_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8379_rdb.dts
@@ -143,7 +143,6 @@
                         mode = "cpu";
                 };
 
-                /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
                 usb@23000 {
                         compatible = "fsl-usb2-dr";
                         reg = <0x23000 0x1000>;
@@ -151,7 +150,7 @@
                         #size-cells = <0>;
                         interrupt-parent = <&ipic>;
                         interrupts = <38 0x8>;
-                        phy_type = "utmi";
+                        phy_type = "ulpi";
                 };
 
                 mdio@24520 {
diff --git a/arch/powerpc/boot/dts/tqm5200.dts b/arch/powerpc/boot/dts/tqm5200.dts
index c86464f007da..65bcea6a0173 100644
--- a/arch/powerpc/boot/dts/tqm5200.dts
+++ b/arch/powerpc/boot/dts/tqm5200.dts
@@ -127,10 +127,25 @@
                 ethernet@3000 {
                         device_type = "network";
                         compatible = "fsl,mpc5200-fec";
-                        reg = <3000 800>;
+                        reg = <3000 400>;
                         local-mac-address = [ 00 00 00 00 00 00 ];
                         interrupts = <2 5 0>;
                         interrupt-parent = <&mpc5200_pic>;
+                        phy-handle = <&phy0>;
+                };
+
+                mdio@3000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
+                        reg = <3000 400>;       // fec range, since we need to setup fec interrupts
+                        interrupts = <2 5 0>;   // these are for "mii command finished", not link changes & co.
+                        interrupt-parent = <&mpc5200_pic>;
+
+                        phy0: ethernet-phy@0 {
+                                device_type = "ethernet-phy";
+                                reg = <0>;
+                        };
                 };
 
                 ata@3a00 {
@@ -141,11 +156,19 @@
                 };
 
                 i2c@3d40 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                         compatible = "fsl,mpc5200-i2c","fsl-i2c";
                         reg = <3d40 40>;
                         interrupts = <2 10 0>;
                         interrupt-parent = <&mpc5200_pic>;
                         fsl5200-clocking;
+
+                         rtc@68 {
+                                device_type = "rtc";
+                                compatible = "dallas,ds1307";
+                                reg = <68>;
+                        };
                 };
 
                 sram@8000 {
@@ -154,6 +177,23 @@
                 };
         };
 
+        lpb {
+                model = "fsl,lpb";
+                compatible = "fsl,lpb";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                ranges = <0 0 fc000000 02000000>;
+
+                flash@0,0 {
+                        compatible = "cfi-flash";
+                        reg = <0 0 02000000>;
+                        bank-width = <4>;
+                        device-width = <2>;
+                        #size-cells = <1>;
+                        #address-cells = <1>;
+                };
+        };
+
         pci@f0000d00 {
                 #interrupt-cells = <1>;
                 #size-cells = <2>;
diff --git a/arch/powerpc/configs/mpc832x_mds_defconfig b/arch/powerpc/configs/mpc832x_mds_defconfig
index 79d228f84c5a..50cceda8994f 100644
--- a/arch/powerpc/configs/mpc832x_mds_defconfig
+++ b/arch/powerpc/configs/mpc832x_mds_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.25-rc6
-# Mon Mar 24 08:48:16 2008
+# Linux kernel version: 2.6.25-rc7
+# Mon Mar 31 11:36:51 2008
 #
 # CONFIG_PPC64 is not set
 
@@ -628,8 +628,7 @@ CONFIG_LEGACY_PTY_COUNT=256
 # CONFIG_IPMI_HANDLER is not set
 CONFIG_HW_RANDOM=y
 # CONFIG_NVRAM is not set
-CONFIG_GEN_RTC=y
-# CONFIG_GEN_RTC_X is not set
+# CONFIG_GEN_RTC is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
 # CONFIG_RAW_DRIVER is not set
@@ -824,10 +823,6 @@ CONFIG_USB_ARCH_HAS_EHCI=y
 # CONFIG_EDAC is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
-
-#
-# Conflicting RTC option has been selected, check GEN_RTC and RTC
-#
 CONFIG_RTC_HCTOSYS=y
 CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
 # CONFIG_RTC_DEBUG is not set
diff --git a/arch/powerpc/configs/mpc834x_mds_defconfig b/arch/powerpc/configs/mpc834x_mds_defconfig
index 9360144942f1..b4e82c0e2be7 100644
--- a/arch/powerpc/configs/mpc834x_mds_defconfig
+++ b/arch/powerpc/configs/mpc834x_mds_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.25-rc6
-# Mon Mar 24 08:48:20 2008
+# Linux kernel version: 2.6.25-rc7
+# Mon Mar 31 11:36:56 2008
 #
 # CONFIG_PPC64 is not set
 
@@ -571,8 +571,7 @@ CONFIG_LEGACY_PTY_COUNT=256
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
 # CONFIG_NVRAM is not set
-CONFIG_GEN_RTC=y
-# CONFIG_GEN_RTC_X is not set
+# CONFIG_GEN_RTC is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
 # CONFIG_RAW_DRIVER is not set
@@ -767,10 +766,6 @@ CONFIG_USB_ARCH_HAS_EHCI=y
 # CONFIG_EDAC is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
-
-#
-# Conflicting RTC option has been selected, check GEN_RTC and RTC
-#
 CONFIG_RTC_HCTOSYS=y
 CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
 # CONFIG_RTC_DEBUG is not set
diff --git a/arch/powerpc/configs/mpc836x_mds_defconfig b/arch/powerpc/configs/mpc836x_mds_defconfig
index 7c8b06046d5d..d50a96eddcdc 100644
--- a/arch/powerpc/configs/mpc836x_mds_defconfig
+++ b/arch/powerpc/configs/mpc836x_mds_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.25-rc6
-# Mon Mar 24 08:48:21 2008
+# Linux kernel version: 2.6.25-rc7
+# Mon Mar 31 11:36:57 2008
 #
 # CONFIG_PPC64 is not set
 
@@ -626,8 +626,7 @@ CONFIG_LEGACY_PTY_COUNT=256
 # CONFIG_IPMI_HANDLER is not set
 CONFIG_HW_RANDOM=y
 # CONFIG_NVRAM is not set
-CONFIG_GEN_RTC=y
-# CONFIG_GEN_RTC_X is not set
+# CONFIG_GEN_RTC is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
 # CONFIG_RAW_DRIVER is not set
@@ -822,10 +821,6 @@ CONFIG_USB_ARCH_HAS_EHCI=y
 # CONFIG_EDAC is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
-
-#
-# Conflicting RTC option has been selected, check GEN_RTC and RTC
-#
 CONFIG_RTC_HCTOSYS=y
 CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
 # CONFIG_RTC_DEBUG is not set
diff --git a/arch/powerpc/configs/mpc837x_rdb_defconfig b/arch/powerpc/configs/mpc837x_rdb_defconfig
index 44093a0eaf88..a6331769d88f 100644
--- a/arch/powerpc/configs/mpc837x_rdb_defconfig
+++ b/arch/powerpc/configs/mpc837x_rdb_defconfig
@@ -684,7 +684,29 @@ CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 # CONFIG_USB_ARCH_HAS_OHCI is not set
 CONFIG_USB_ARCH_HAS_EHCI=y
-# CONFIG_USB is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+CONFIG_USB_EHCI_FSL=y
+CONFIG_USB_EHCI_HCD_PPC_OF=y
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
 
 #
 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
diff --git a/arch/powerpc/configs/mpc83xx_defconfig b/arch/powerpc/configs/mpc83xx_defconfig
index 1f6cf68e89f8..029d2dab7deb 100644
--- a/arch/powerpc/configs/mpc83xx_defconfig
+++ b/arch/powerpc/configs/mpc83xx_defconfig
@@ -690,7 +690,29 @@ CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 # CONFIG_USB_ARCH_HAS_OHCI is not set
 CONFIG_USB_ARCH_HAS_EHCI=y
-# CONFIG_USB is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+CONFIG_USB_EHCI_FSL=y
+CONFIG_USB_EHCI_HCD_PPC_OF=y
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
 
 #
 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
diff --git a/arch/powerpc/configs/mpc8544_ds_defconfig b/arch/powerpc/configs/mpc8544_ds_defconfig
index c75b6aee76d1..418bcdb5f919 100644
--- a/arch/powerpc/configs/mpc8544_ds_defconfig
+++ b/arch/powerpc/configs/mpc8544_ds_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.25-rc6
-# Mon Mar 24 08:48:26 2008
+# Linux kernel version: 2.6.25-rc7
+# Mon Mar 31 11:37:03 2008
 #
 # CONFIG_PPC64 is not set
 
@@ -742,8 +742,7 @@ CONFIG_LEGACY_PTY_COUNT=256
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_NVRAM=y
-CONFIG_GEN_RTC=y
-CONFIG_GEN_RTC_X=y
+# CONFIG_GEN_RTC is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
 # CONFIG_RAW_DRIVER is not set
@@ -1209,10 +1208,6 @@ CONFIG_USB_MON=y
 # CONFIG_EDAC is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
-
-#
-# Conflicting RTC option has been selected, check GEN_RTC and RTC
-#
 CONFIG_RTC_HCTOSYS=y
 CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
 # CONFIG_RTC_DEBUG is not set
diff --git a/arch/powerpc/configs/mpc8568mds_defconfig b/arch/powerpc/configs/mpc8568mds_defconfig
index e7da4b96cdeb..2b866b385607 100644
--- a/arch/powerpc/configs/mpc8568mds_defconfig
+++ b/arch/powerpc/configs/mpc8568mds_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.25-rc6
-# Mon Mar 24 08:48:28 2008
+# Linux kernel version: 2.6.25-rc7
+# Mon Mar 31 11:37:05 2008
 #
 # CONFIG_PPC64 is not set
 
@@ -629,8 +629,7 @@ CONFIG_LEGACY_PTY_COUNT=256
 # CONFIG_IPMI_HANDLER is not set
 CONFIG_HW_RANDOM=y
 # CONFIG_NVRAM is not set
-CONFIG_GEN_RTC=y
-# CONFIG_GEN_RTC_X is not set
+# CONFIG_GEN_RTC is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
 # CONFIG_RAW_DRIVER is not set
@@ -825,10 +824,6 @@ CONFIG_USB_ARCH_HAS_EHCI=y
 # CONFIG_EDAC is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
-
-#
-# Conflicting RTC option has been selected, check GEN_RTC and RTC
-#
 CONFIG_RTC_HCTOSYS=y
 CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
 # CONFIG_RTC_DEBUG is not set
diff --git a/arch/powerpc/configs/mpc8572_ds_defconfig b/arch/powerpc/configs/mpc8572_ds_defconfig
index 460afe99c653..53aa6f3173a5 100644
--- a/arch/powerpc/configs/mpc8572_ds_defconfig
+++ b/arch/powerpc/configs/mpc8572_ds_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.25-rc6
-# Mon Mar 24 08:48:29 2008
+# Linux kernel version: 2.6.25-rc7
+# Mon Mar 31 11:37:06 2008
 #
 # CONFIG_PPC64 is not set
 
@@ -742,8 +742,7 @@ CONFIG_LEGACY_PTY_COUNT=256
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_NVRAM=y
-CONFIG_GEN_RTC=y
-CONFIG_GEN_RTC_X=y
+# CONFIG_GEN_RTC is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
 # CONFIG_RAW_DRIVER is not set
@@ -1209,10 +1208,6 @@ CONFIG_USB_MON=y
 # CONFIG_EDAC is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
-
-#
-# Conflicting RTC option has been selected, check GEN_RTC and RTC
-#
 CONFIG_RTC_HCTOSYS=y
 CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
 # CONFIG_RTC_DEBUG is not set
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index 615e4c1bf735..2075722911bb 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.25-rc6
-# Mon Mar 24 08:48:31 2008
+# Linux kernel version: 2.6.25-rc7
+# Mon Mar 31 11:37:08 2008
 #
 # CONFIG_PPC64 is not set
 
@@ -750,8 +750,7 @@ CONFIG_LEGACY_PTY_COUNT=256
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_NVRAM=y
-CONFIG_GEN_RTC=y
-CONFIG_GEN_RTC_X=y
+# CONFIG_GEN_RTC is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
 # CONFIG_RAW_DRIVER is not set
@@ -1217,10 +1216,6 @@ CONFIG_USB_MON=y
 # CONFIG_EDAC is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
-
-#
-# Conflicting RTC option has been selected, check GEN_RTC and RTC
-#
 CONFIG_RTC_HCTOSYS=y
 CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
 # CONFIG_RTC_DEBUG is not set
diff --git a/arch/powerpc/configs/mpc8641_hpcn_defconfig b/arch/powerpc/configs/mpc8641_hpcn_defconfig
index 994e76817967..d01dcdb70bd7 100644
--- a/arch/powerpc/configs/mpc8641_hpcn_defconfig
+++ b/arch/powerpc/configs/mpc8641_hpcn_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.25-rc6
-# Mon Mar 24 08:48:34 2008
+# Linux kernel version: 2.6.25-rc7
+# Mon Mar 31 11:37:11 2008
 #
 # CONFIG_PPC64 is not set
 
@@ -736,8 +736,7 @@ CONFIG_LEGACY_PTY_COUNT=256
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_NVRAM=y
-CONFIG_GEN_RTC=y
-CONFIG_GEN_RTC_X=y
+# CONFIG_GEN_RTC is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
 # CONFIG_RAW_DRIVER is not set
@@ -1203,10 +1202,6 @@ CONFIG_USB_MON=y
 # CONFIG_EDAC is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
-
-#
-# Conflicting RTC option has been selected, check GEN_RTC and RTC
-#
 CONFIG_RTC_HCTOSYS=y
 CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
 # CONFIG_RTC_DEBUG is not set
diff --git a/arch/powerpc/configs/pasemi_defconfig b/arch/powerpc/configs/pasemi_defconfig
index 797f0dfebde2..09f306248f2e 100644
--- a/arch/powerpc/configs/pasemi_defconfig
+++ b/arch/powerpc/configs/pasemi_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.24-rc6
-# Tue Jan 15 10:26:10 2008
+# Linux kernel version: 2.6.25-rc6
+# Tue Mar 25 10:25:48 2008
 #
 CONFIG_PPC64=y
 
@@ -27,6 +27,7 @@ CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_TIME_VSYSCALL=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_HARDIRQS=y
+CONFIG_HAVE_SETUP_PER_CPU_AREA=y
 CONFIG_IRQ_PER_CPU=y
 CONFIG_RWSEM_XCHGADD_ALGORITHM=y
 CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -67,17 +68,19 @@ CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
 # CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=17
 # CONFIG_CGROUPS is not set
-CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_FAIR_USER_SCHED=y
-# CONFIG_FAIR_CGROUP_SCHED is not set
+# CONFIG_GROUP_SCHED is not set
 CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -91,11 +94,13 @@ CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_VM_EVENT_COUNTERS=y
@@ -103,6 +108,15 @@ CONFIG_SLUB_DEBUG=y
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+# CONFIG_MARKERS is not set
+CONFIG_OPROFILE=y
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
@@ -130,6 +144,7 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
 
 #
 # Platform support
@@ -140,8 +155,8 @@ CONFIG_PPC_MULTIPLATFORM=y
 # CONFIG_PPC_86xx is not set
 # CONFIG_PPC_PSERIES is not set
 # CONFIG_PPC_ISERIES is not set
-# CONFIG_PPC_MPC52xx is not set
-# CONFIG_PPC_MPC5200 is not set
+# CONFIG_PPC_MPC512x is not set
+# CONFIG_PPC_MPC5121 is not set
 # CONFIG_PPC_PMAC is not set
 # CONFIG_PPC_MAPLE is not set
 CONFIG_PPC_PASEMI=y
@@ -159,6 +174,7 @@ CONFIG_PPC_PASEMI_MDIO=y
 # CONFIG_PPC_IBM_CELL_BLADE is not set
 # CONFIG_PQ2ADS is not set
 CONFIG_PPC_NATIVE=y
+# CONFIG_IPIC is not set
 CONFIG_MPIC=y
 # CONFIG_MPIC_WEIRD is not set
 # CONFIG_PPC_I8259 is not set
@@ -189,7 +205,6 @@ CONFIG_CPU_FREQ_GOV_ONDEMAND=y
 # CPU Frequency drivers
 #
 CONFIG_PPC_PASEMI_CPUFREQ=y
-# CONFIG_CPM2 is not set
 # CONFIG_FSL_ULI1575 is not set
 
 #
@@ -204,16 +219,20 @@ CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 # CONFIG_HZ_300 is not set
 CONFIG_HZ_1000=y
 CONFIG_HZ=1000
+# CONFIG_SCHED_HRTICK is not set
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
-# CONFIG_PREEMPT_BKL is not set
 CONFIG_BINFMT_ELF=y
+CONFIG_COMPAT_BINFMT_ELF=y
 # CONFIG_BINFMT_MISC is not set
 CONFIG_FORCE_MAX_ZONEORDER=9
 CONFIG_HUGETLB_PAGE_SIZE_VARIABLE=y
 CONFIG_IOMMU_VMERGE=y
+CONFIG_IOMMU_HELPER=y
 CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_HAS_WALK_MEMORY=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
 # CONFIG_KEXEC is not set
 # CONFIG_CRASH_DUMP is not set
 # CONFIG_IRQ_ALL_CPUS is not set
@@ -236,12 +255,12 @@ CONFIG_ZONE_DMA_FLAG=1
 CONFIG_BOUNCE=y
 CONFIG_PPC_HAS_HASH_64K=y
 CONFIG_PPC_64K_PAGES=y
+# CONFIG_PPC_SUBPAGE_PROT is not set
 # CONFIG_SCHED_SMT is not set
 CONFIG_PROC_DEVICETREE=y
 # CONFIG_CMDLINE_BOOL is not set
 # CONFIG_PM is not set
 # CONFIG_SECCOMP is not set
-# CONFIG_WANT_DEVICE_TREE is not set
 CONFIG_ISA_DMA_API=y
 
 #
@@ -290,6 +309,7 @@ CONFIG_XFRM=y
 CONFIG_XFRM_USER=y
 # CONFIG_XFRM_SUB_POLICY is not set
 # CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
 CONFIG_NET_KEY=y
 # CONFIG_NET_KEY_MIGRATE is not set
 CONFIG_INET=y
@@ -346,6 +366,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
@@ -441,8 +462,10 @@ CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
 # CONFIG_MTD_NAND_CAFE is not set
+CONFIG_MTD_NAND_PASEMI=y
 # CONFIG_MTD_NAND_PLATFORM is not set
 # CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_NAND_FSL_ELBC is not set
 # CONFIG_MTD_ONENAND is not set
 
 #
@@ -465,7 +488,7 @@ CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
 CONFIG_MISC_DEVICES=y
@@ -473,11 +496,13 @@ CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
 # CONFIG_SGI_IOC4 is not set
 # CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
 CONFIG_IDE=y
 CONFIG_BLK_DEV_IDE=y
 
 #
-# Please see Documentation/ide.txt for help/info on IDE drives
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
 #
 # CONFIG_BLK_DEV_IDE_SATA is not set
 CONFIG_BLK_DEV_IDEDISK=y
@@ -485,6 +510,7 @@ CONFIG_IDEDISK_MULTI_MODE=y
 # CONFIG_BLK_DEV_IDECS is not set
 # CONFIG_BLK_DEV_DELKIN is not set
 CONFIG_BLK_DEV_IDECD=y
+CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
 # CONFIG_BLK_DEV_IDETAPE is not set
 # CONFIG_BLK_DEV_IDEFLOPPY is not set
 CONFIG_BLK_DEV_IDESCSI=y
@@ -500,7 +526,6 @@ CONFIG_IDE_PROC_FS=y
 #
 # PCI IDE chipsets support
 #
-# CONFIG_IDEPCI_PCIBUS_ORDER is not set
 # CONFIG_BLK_DEV_GENERIC is not set
 # CONFIG_BLK_DEV_OPTI621 is not set
 # CONFIG_BLK_DEV_AEC62XX is not set
@@ -528,7 +553,6 @@ CONFIG_IDE_PROC_FS=y
 # CONFIG_BLK_DEV_TRM290 is not set
 # CONFIG_BLK_DEV_VIA82CXXX is not set
 # CONFIG_BLK_DEV_TC86C001 is not set
-# CONFIG_IDE_ARM is not set
 # CONFIG_BLK_DEV_IDEDMA is not set
 CONFIG_IDE_ARCH_OBSOLETE_INIT=y
 # CONFIG_BLK_DEV_HD is not set
@@ -593,6 +617,7 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_SCSI_IPS is not set
 # CONFIG_SCSI_INITIO is not set
 # CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_MVSAS is not set
 # CONFIG_SCSI_STEX is not set
 # CONFIG_SCSI_SYM53C8XX_2 is not set
 # CONFIG_SCSI_IPR is not set
@@ -646,6 +671,7 @@ CONFIG_ATA_GENERIC=y
 # CONFIG_PATA_MPIIX is not set
 # CONFIG_PATA_OLDPIIX is not set
 # CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
 # CONFIG_PATA_NS87410 is not set
 # CONFIG_PATA_NS87415 is not set
 # CONFIG_PATA_OPTI is not set
@@ -699,7 +725,6 @@ CONFIG_DUMMY=y
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
 # CONFIG_VETH is not set
-# CONFIG_IP1000 is not set
 # CONFIG_ARCNET is not set
 CONFIG_PHYLIB=y
 
@@ -715,6 +740,7 @@ CONFIG_MARVELL_PHY=y
 # CONFIG_SMSC_PHY is not set
 # CONFIG_BROADCOM_PHY is not set
 # CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
 # CONFIG_FIXED_PHY is not set
 # CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
@@ -742,6 +768,7 @@ CONFIG_NET_PCI=y
 # CONFIG_NE2K_PCI is not set
 # CONFIG_8139CP is not set
 # CONFIG_8139TOO is not set
+# CONFIG_R6040 is not set
 # CONFIG_SIS900 is not set
 # CONFIG_EPIC100 is not set
 # CONFIG_SUNDANCE is not set
@@ -754,6 +781,9 @@ CONFIG_E1000=y
 CONFIG_E1000_NAPI=y
 # CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
 # CONFIG_E1000E is not set
+# CONFIG_E1000E_ENABLED is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
 # CONFIG_NS83820 is not set
 # CONFIG_HAMACHI is not set
 # CONFIG_YELLOWFIN is not set
@@ -779,6 +809,7 @@ CONFIG_NETDEV_10000=y
 CONFIG_PASEMI_MAC=y
 # CONFIG_MLX4_CORE is not set
 # CONFIG_TEHUTI is not set
+# CONFIG_BNX2X is not set
 # CONFIG_TR is not set
 
 #
@@ -802,7 +833,6 @@ CONFIG_PASEMI_MAC=y
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
 # CONFIG_NET_FC is not set
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
@@ -861,6 +891,7 @@ CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 # CONFIG_VT_HW_CONSOLE_BINDING is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
 
 #
 # Serial drivers
@@ -886,8 +917,7 @@ CONFIG_LEGACY_PTY_COUNT=4
 # CONFIG_IPMI_HANDLER is not set
 CONFIG_HW_RANDOM=y
 CONFIG_HW_RANDOM_PASEMI=y
-CONFIG_GEN_RTC=y
-CONFIG_GEN_RTC_X=y
+# CONFIG_GEN_RTC is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
 
@@ -897,6 +927,7 @@ CONFIG_GEN_RTC_X=y
 # CONFIG_SYNCLINK_CS is not set
 # CONFIG_CARDMAN_4000 is not set
 # CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
 CONFIG_RAW_DRIVER=y
 CONFIG_MAX_RAW_DEVS=256
 # CONFIG_HANGCHECK_TIMER is not set
@@ -944,13 +975,12 @@ CONFIG_I2C_PASEMI=y
 #
 # Miscellaneous I2C Chip support
 #
-# CONFIG_SENSORS_DS1337 is not set
-# CONFIG_SENSORS_DS1374 is not set
 # CONFIG_DS1682 is not set
 CONFIG_SENSORS_EEPROM=y
 # CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_PCF8575 is not set
 # CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_TPS65010 is not set
 # CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
@@ -975,6 +1005,7 @@ CONFIG_HWMON_VID=y
 # CONFIG_SENSORS_ADM1031 is not set
 # CONFIG_SENSORS_ADM9240 is not set
 # CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
 # CONFIG_SENSORS_ATXP1 is not set
 # CONFIG_SENSORS_DS1621 is not set
 # CONFIG_SENSORS_I5K_AMB is not set
@@ -1004,6 +1035,7 @@ CONFIG_SENSORS_LM90=y
 # CONFIG_SENSORS_SMSC47M1 is not set
 # CONFIG_SENSORS_SMSC47M192 is not set
 # CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
 # CONFIG_SENSORS_THMC50 is not set
 # CONFIG_SENSORS_VIA686A is not set
 # CONFIG_SENSORS_VT1211 is not set
@@ -1013,9 +1045,11 @@ CONFIG_SENSORS_LM90=y
 # CONFIG_SENSORS_W83792D is not set
 # CONFIG_SENSORS_W83793 is not set
 # CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
 # CONFIG_SENSORS_W83627HF is not set
 # CONFIG_SENSORS_W83627EHF is not set
 # CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
 # CONFIG_WATCHDOG is not set
 
 #
@@ -1183,6 +1217,7 @@ CONFIG_SND_VERBOSE_PROCFS=y
 # CONFIG_SND_BT87X is not set
 # CONFIG_SND_CA0106 is not set
 # CONFIG_SND_CMIPCI is not set
+# CONFIG_SND_OXYGEN is not set
 # CONFIG_SND_CS4281 is not set
 # CONFIG_SND_CS46XX is not set
 # CONFIG_SND_CS5530 is not set
@@ -1208,6 +1243,7 @@ CONFIG_SND_VERBOSE_PROCFS=y
 # CONFIG_SND_HDA_INTEL is not set
 # CONFIG_SND_HDSP is not set
 # CONFIG_SND_HDSPM is not set
+# CONFIG_SND_HIFIER is not set
 # CONFIG_SND_ICE1712 is not set
 # CONFIG_SND_ICE1724 is not set
 # CONFIG_SND_INTEL8X0 is not set
@@ -1225,6 +1261,7 @@ CONFIG_SND_VERBOSE_PROCFS=y
 # CONFIG_SND_TRIDENT is not set
 # CONFIG_SND_VIA82XX is not set
 # CONFIG_SND_VIA82XX_MODEM is not set
+# CONFIG_SND_VIRTUOSO is not set
 # CONFIG_SND_VX222 is not set
 # CONFIG_SND_YMFPCI is not set
 
@@ -1259,6 +1296,10 @@ CONFIG_SND_USB_USX2Y=y
 #
 
 #
+# ALSA SoC audio for Freescale SOCs
+#
+
+#
 # Open Sound System
 #
 # CONFIG_SOUND_PRIME is not set
@@ -1280,6 +1321,7 @@ CONFIG_USB_ARCH_HAS_OHCI=y
 CONFIG_USB_ARCH_HAS_EHCI=y
 CONFIG_USB=y
 # CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
 
 #
 # Miscellaneous USB options
@@ -1293,17 +1335,14 @@ CONFIG_USB_DEVICEFS=y
 # USB Host Controller Drivers
 #
 CONFIG_USB_EHCI_HCD=y
-# CONFIG_USB_EHCI_SPLIT_ISO is not set
 # CONFIG_USB_EHCI_ROOT_HUB_TT is not set
 # CONFIG_USB_EHCI_TT_NEWSCHED is not set
+CONFIG_USB_EHCI_HCD_PPC_OF=y
 # CONFIG_USB_ISP116X_HCD is not set
 CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_PPC_OF=y
-CONFIG_USB_OHCI_HCD_PPC_OF_BE=y
-# CONFIG_USB_OHCI_HCD_PPC_OF_LE is not set
-CONFIG_USB_OHCI_HCD_PCI=y
-CONFIG_USB_OHCI_BIG_ENDIAN_DESC=y
-CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y
+# CONFIG_USB_OHCI_HCD_PPC_OF is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
 CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 CONFIG_USB_UHCI_HCD=y
 CONFIG_USB_SL811_HCD=y
@@ -1348,10 +1387,6 @@ CONFIG_USB_LIBUSUAL=y
 #
 # USB port drivers
 #
-
-#
-# USB Serial Converter support
-#
 # CONFIG_USB_SERIAL is not set
 
 #
@@ -1377,16 +1412,9 @@ CONFIG_USB_LIBUSUAL=y
 # CONFIG_USB_TRANCEVIBRATOR is not set
 # CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_TEST is not set
-
-#
-# USB DSL modem support
-#
-
-#
-# USB Gadget Support
-#
 # CONFIG_USB_GADGET is not set
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
 # CONFIG_INFINIBAND is not set
 CONFIG_EDAC=y
@@ -1425,6 +1453,7 @@ CONFIG_RTC_DRV_DS1307=y
 # CONFIG_RTC_DRV_PCF8563 is not set
 # CONFIG_RTC_DRV_PCF8583 is not set
 # CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
 
 #
 # SPI RTC drivers
@@ -1434,9 +1463,10 @@ CONFIG_RTC_DRV_DS1307=y
 # Platform RTC drivers
 #
 # CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1511 is not set
 # CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
 # CONFIG_RTC_DRV_M48T59 is not set
 # CONFIG_RTC_DRV_V3020 is not set
@@ -1444,6 +1474,7 @@ CONFIG_RTC_DRV_DS1307=y
 #
 # on-CPU RTC drivers
 #
+# CONFIG_DMADEVICES is not set
 
 #
 # Userspace I/O
@@ -1471,12 +1502,10 @@ CONFIG_FS_POSIX_ACL=y
 # CONFIG_XFS_FS is not set
 # CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
 CONFIG_AUTOFS_FS=y
 CONFIG_AUTOFS4_FS=y
 # CONFIG_FUSE_FS is not set
@@ -1536,8 +1565,10 @@ CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
@@ -1629,7 +1660,6 @@ CONFIG_NLS_ISO8859_1=y
 # CONFIG_NLS_KOI8_U is not set
 # CONFIG_NLS_UTF8 is not set
 # CONFIG_DLM is not set
-# CONFIG_UCC_SLOW is not set
 
 #
 # Library routines
@@ -1647,11 +1677,6 @@ CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
-CONFIG_INSTRUMENTATION=y
-CONFIG_PROFILING=y
-CONFIG_OPROFILE=y
-# CONFIG_KPROBES is not set
-# CONFIG_MARKERS is not set
 
 #
 # Kernel hacking
@@ -1670,6 +1695,7 @@ CONFIG_DETECT_SOFTLOCKUP=y
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
 # CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
 # CONFIG_DEBUG_RT_MUTEXES is not set
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
@@ -1682,9 +1708,9 @@ CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_VM is not set
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
-# CONFIG_FORCED_INLINING is not set
 # CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
 # CONFIG_FAULT_INJECTION is not set
 # CONFIG_SAMPLES is not set
 # CONFIG_DEBUG_STACKOVERFLOW is not set
@@ -1710,7 +1736,9 @@ CONFIG_ASYNC_MEMCPY=y
 CONFIG_ASYNC_XOR=y
 CONFIG_CRYPTO=y
 CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=y
 CONFIG_CRYPTO_BLKCIPHER=y
+# CONFIG_CRYPTO_SEQIV is not set
 CONFIG_CRYPTO_HASH=y
 CONFIG_CRYPTO_MANAGER=y
 CONFIG_CRYPTO_HMAC=y
@@ -1729,6 +1757,9 @@ CONFIG_CRYPTO_CBC=y
 # CONFIG_CRYPTO_PCBC is not set
 # CONFIG_CRYPTO_LRW is not set
 # CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_CCM is not set
 # CONFIG_CRYPTO_CRYPTD is not set
 CONFIG_CRYPTO_DES=y
 # CONFIG_CRYPTO_FCRYPT is not set
@@ -1743,11 +1774,14 @@ CONFIG_CRYPTO_AES=y
 # CONFIG_CRYPTO_KHAZAD is not set
 # CONFIG_CRYPTO_ANUBIS is not set
 # CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SALSA20 is not set
 # CONFIG_CRYPTO_DEFLATE is not set
 # CONFIG_CRYPTO_MICHAEL_MIC is not set
 # CONFIG_CRYPTO_CRC32C is not set
 # CONFIG_CRYPTO_CAMELLIA is not set
 # CONFIG_CRYPTO_TEST is not set
-# CONFIG_CRYPTO_AUTHENC is not set
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_LZO is not set
 CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
 # CONFIG_PPC_CLOCK is not set
diff --git a/arch/powerpc/configs/prpmc2800_defconfig b/arch/powerpc/configs/prpmc2800_defconfig
index f53d55bbdd7c..f9121685f11a 100644
--- a/arch/powerpc/configs/prpmc2800_defconfig
+++ b/arch/powerpc/configs/prpmc2800_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.25-rc6
-# Mon Mar 24 08:48:37 2008
+# Linux kernel version: 2.6.25-rc7
+# Mon Mar 31 11:37:15 2008
 #
 # CONFIG_PPC64 is not set
 
@@ -855,8 +855,7 @@ CONFIG_LEGACY_PTY_COUNT=256
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
 # CONFIG_NVRAM is not set
-CONFIG_GEN_RTC=y
-# CONFIG_GEN_RTC_X is not set
+# CONFIG_GEN_RTC is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
 # CONFIG_RAW_DRIVER is not set
@@ -1129,10 +1128,6 @@ CONFIG_USB_MON=y
 # CONFIG_EDAC is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
-
-#
-# Conflicting RTC option has been selected, check GEN_RTC and RTC
-#
 CONFIG_RTC_HCTOSYS=y
 CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
 # CONFIG_RTC_DEBUG is not set
diff --git a/arch/powerpc/configs/storcenter_defconfig b/arch/powerpc/configs/storcenter_defconfig
index 8fc85747a0a7..fdbfd39a3aca 100644
--- a/arch/powerpc/configs/storcenter_defconfig
+++ b/arch/powerpc/configs/storcenter_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.25-rc6
-# Mon Mar 24 08:48:41 2008
+# Linux kernel version: 2.6.25-rc7
+# Mon Mar 31 11:37:19 2008
 #
 # CONFIG_PPC64 is not set
 
@@ -717,8 +717,7 @@ CONFIG_LEGACY_PTY_COUNT=256
 # CONFIG_IPMI_HANDLER is not set
 CONFIG_HW_RANDOM=m
 CONFIG_NVRAM=y
-CONFIG_GEN_RTC=y
-# CONFIG_GEN_RTC_X is not set
+# CONFIG_GEN_RTC is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
 # CONFIG_RAW_DRIVER is not set
@@ -931,10 +930,6 @@ CONFIG_USB_STORAGE=y
 # CONFIG_EDAC is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
-
-#
-# Conflicting RTC option has been selected, check GEN_RTC and RTC
-#
 CONFIG_RTC_HCTOSYS=y
 CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
 # CONFIG_RTC_DEBUG is not set
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index 11b4f6d9ffce..d3aee08e6814 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -1387,12 +1387,14 @@ __secondary_start:
 #ifdef CONFIG_PPC_ISERIES
 BEGIN_FW_FTR_SECTION
         ori     r4,r4,MSR_EE
+        li      r8,1
+        stb     r8,PACAHARDIRQEN(r13)
 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
 #endif
 BEGIN_FW_FTR_SECTION
-        stb     r7,PACASOFTIRQEN(r13)
         stb     r7,PACAHARDIRQEN(r13)
 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
+        stb     r7,PACASOFTIRQEN(r13)
 
         mtspr   SPRN_SRR0,r3
         mtspr   SPRN_SRR1,r4
@@ -1520,15 +1522,14 @@ _INIT_GLOBAL(start_here_common)
 #ifdef CONFIG_PPC_ISERIES
 BEGIN_FW_FTR_SECTION
         mfmsr   r5
-        ori     r5,r5,MSR_EE            /* Hard Enabled */
+        ori     r5,r5,MSR_EE            /* Hard Enabled on iSeries*/
         mtmsrd  r5
+        li      r5,1
 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
 #endif
-BEGIN_FW_FTR_SECTION
-        stb     r5,PACAHARDIRQEN(r13)
-END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
+        stb     r5,PACAHARDIRQEN(r13)   /* Hard Disabled on others */
 
-        bl .start_kernel
+        bl      .start_kernel
 
         /* Not reached */
         BUG_OPCODE
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index b0e5deb4274f..292163f5b39a 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -143,7 +143,6 @@ void local_irq_restore(unsigned long en)
                  */
                 if (local_paca->lppaca_ptr->int_dword.any_int)
                         iseries_handle_interrupts();
-                return;
         }
 
         /*
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 59311ec0d422..4ec605521504 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -241,8 +241,12 @@ void discard_lazy_cpu_state(void)
 }
 #endif /* CONFIG_SMP */
 
+static DEFINE_PER_CPU(unsigned long, current_dabr);
+
 int set_dabr(unsigned long dabr)
 {
+        __get_cpu_var(current_dabr) = dabr;
+
 #ifdef CONFIG_PPC_MERGE         /* XXX for now */
         if (ppc_md.set_dabr)
                 return ppc_md.set_dabr(dabr);
@@ -259,8 +263,6 @@ int set_dabr(unsigned long dabr)
 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
 #endif
 
-static DEFINE_PER_CPU(unsigned long, current_dabr);
-
 struct task_struct *__switch_to(struct task_struct *prev,
         struct task_struct *new)
 {
@@ -325,10 +327,8 @@ struct task_struct *__switch_to(struct task_struct *prev,
 
 #endif /* CONFIG_SMP */
 
-        if (unlikely(__get_cpu_var(current_dabr) != new->thread.dabr)) {
+        if (unlikely(__get_cpu_var(current_dabr) != new->thread.dabr))
                 set_dabr(new->thread.dabr);
-                __get_cpu_var(current_dabr) = new->thread.dabr;
-        }
 
         new_thread = &new->thread;
         old_thread = &current->thread;
diff --git a/arch/powerpc/kernel/rtas_flash.c b/arch/powerpc/kernel/rtas_flash.c
index f2276593f416..538baf46f15f 100644
--- a/arch/powerpc/kernel/rtas_flash.c
+++ b/arch/powerpc/kernel/rtas_flash.c
@@ -356,7 +356,7 @@ static int rtas_excl_open(struct inode *inode, struct file *file)
 
         /* Enforce exclusive open with use count of PDE */
         spin_lock(&flash_file_open_lock);
-        if (atomic_read(&dp->count) > 1) {
+        if (atomic_read(&dp->count) > 2) {
                 spin_unlock(&flash_file_open_lock);
                 return -EBUSY;
         }
diff --git a/arch/powerpc/mm/hash_low_32.S b/arch/powerpc/mm/hash_low_32.S
index 7f830a4888d6..e10d76a860d3 100644
--- a/arch/powerpc/mm/hash_low_32.S
+++ b/arch/powerpc/mm/hash_low_32.S
@@ -44,6 +44,9 @@ mmu_hash_lock:
 #ifdef CONFIG_SMP
         .text
 _GLOBAL(hash_page_sync)
+        mfmsr   r10
+        rlwinm  r0,r10,0,17,15          /* clear bit 16 (MSR_EE) */
+        mtmsr   r0
         lis     r8,mmu_hash_lock@h
         ori     r8,r8,mmu_hash_lock@l
         lis     r0,0x0fff
@@ -60,8 +63,9 @@ _GLOBAL(hash_page_sync)
         eieio
         li      r0,0
         stw     r0,0(r8)
-        blr     
-#endif
+        mtmsr   r10
+        blr
+#endif /* CONFIG_SMP */
 
 /*
  * Load a PTE into the hash table, if possible.
diff --git a/arch/powerpc/oprofile/cell/vma_map.c b/arch/powerpc/oprofile/cell/vma_map.c
index 76ec1d16aef7..9a932177e70e 100644
--- a/arch/powerpc/oprofile/cell/vma_map.c
+++ b/arch/powerpc/oprofile/cell/vma_map.c
@@ -92,7 +92,7 @@ vma_map_add(struct vma_to_fileoffset_map *map, unsigned int vma,
  * A pointer to the first vma_map in the generated list
  * of vma_maps is returned.  */
 struct vma_to_fileoffset_map *create_vma_map(const struct spu *aSpu,
-                                             unsigned long spu_elf_start)
+                                             unsigned long __spu_elf_start)
 {
         static const unsigned char expected[EI_PAD] = {
                 [EI_MAG0] = ELFMAG0,
@@ -107,9 +107,11 @@ struct vma_to_fileoffset_map *create_vma_map(const struct spu *aSpu,
 
         int grd_val;
         struct vma_to_fileoffset_map *map = NULL;
+        void __user *spu_elf_start = (void __user *)__spu_elf_start;
         struct spu_overlay_info ovly;
         unsigned int overlay_tbl_offset = -1;
-        unsigned long phdr_start, shdr_start;
+        Elf32_Phdr __user *phdr_start;
+        Elf32_Shdr __user *shdr_start;
         Elf32_Ehdr ehdr;
         Elf32_Phdr phdr;
         Elf32_Shdr shdr, shdr_str;
@@ -121,12 +123,12 @@ struct vma_to_fileoffset_map *create_vma_map(const struct spu *aSpu,
         unsigned int ovly_buf_table_sym = 0;
         unsigned int ovly_table_end_sym = 0;
         unsigned int ovly_buf_table_end_sym = 0;
-        unsigned long ovly_table;
+        struct spu_overlay_info __user *ovly_table;
         unsigned int n_ovlys;
 
         /* Get and validate ELF header.  */
 
-        if (copy_from_user(&ehdr, (void *) spu_elf_start, sizeof (ehdr)))
+        if (copy_from_user(&ehdr, spu_elf_start, sizeof (ehdr)))
                 goto fail;
 
         if (memcmp(ehdr.e_ident, expected, EI_PAD) != 0) {
@@ -152,9 +154,7 @@ struct vma_to_fileoffset_map *create_vma_map(const struct spu *aSpu,
 
         /* Traverse program headers.  */
         for (i = 0; i < ehdr.e_phnum; i++) {
-                if (copy_from_user(&phdr,
-                                   (void *) (phdr_start + i * sizeof(phdr)),
-                                   sizeof(phdr)))
+                if (copy_from_user(&phdr, phdr_start + i, sizeof(phdr)))
                         goto fail;
 
                 if (phdr.p_type != PT_LOAD)
@@ -171,9 +171,7 @@ struct vma_to_fileoffset_map *create_vma_map(const struct spu *aSpu,
         pr_debug("SPU_PROF: Created non-overlay maps\n");
         /* Traverse section table and search for overlay-related symbols.  */
         for (i = 0; i < ehdr.e_shnum; i++) {
-                if (copy_from_user(&shdr,
-                                   (void *) (shdr_start + i * sizeof(shdr)),
-                                   sizeof(shdr)))
+                if (copy_from_user(&shdr, shdr_start + i, sizeof(shdr)))
                         goto fail;
 
                 if (shdr.sh_type != SHT_SYMTAB)
@@ -182,8 +180,7 @@ struct vma_to_fileoffset_map *create_vma_map(const struct spu *aSpu,
                         continue;
 
                 if (copy_from_user(&shdr_str,
-                                   (void *) (shdr_start + shdr.sh_link *
-                                             sizeof(shdr)),
+                                   shdr_start + shdr.sh_link,
                                    sizeof(shdr)))
                         goto fail;
 
@@ -191,15 +188,15 @@ struct vma_to_fileoffset_map *create_vma_map(const struct spu *aSpu,
                         goto fail;;
 
                 for (j = 0; j < shdr.sh_size / sizeof (sym); j++) {
-                        if (copy_from_user(&sym, (void *) (spu_elf_start +
-                                                       shdr.sh_offset + j *
-                                                           sizeof (sym)),
+                        if (copy_from_user(&sym, spu_elf_start +
+                                                 shdr.sh_offset +
+                                                 j * sizeof (sym),
                                            sizeof (sym)))
                                 goto fail;
 
-                        if (copy_from_user(name, (void *)
-                                           (spu_elf_start + shdr_str.sh_offset +
-                                            sym.st_name),
+                        if (copy_from_user(name, 
+                                           spu_elf_start + shdr_str.sh_offset +
+                                           sym.st_name,
                                            20))
                                 goto fail;
 
@@ -245,9 +242,7 @@ struct vma_to_fileoffset_map *create_vma_map(const struct spu *aSpu,
 
         /* Traverse overlay table.  */
         for (i = 0; i < n_ovlys; i++) {
-                if (copy_from_user(&ovly, (void *)
-                                   (ovly_table + i * sizeof (ovly)),
-                                   sizeof (ovly)))
+                if (copy_from_user(&ovly, ovly_table + i, sizeof (ovly)))
                         goto fail;
 
                 /* The ovly.vma/size/offset arguments are analogous to the same
diff --git a/arch/powerpc/platforms/pseries/xics.c b/arch/powerpc/platforms/pseries/xics.c
index ca52b587166d..a977f200db89 100644
--- a/arch/powerpc/platforms/pseries/xics.c
+++ b/arch/powerpc/platforms/pseries/xics.c
@@ -763,7 +763,7 @@ void xics_request_IPIs(void)
 }
 #endif /* CONFIG_SMP */
 
-void xics_teardown_cpu()
+void xics_teardown_cpu(void)
 {
         int cpu = smp_processor_id();
 
diff --git a/arch/powerpc/sysdev/cpm2.c b/arch/powerpc/sysdev/cpm2.c
index 7be711232124..dd066bb1d562 100644
--- a/arch/powerpc/sysdev/cpm2.c
+++ b/arch/powerpc/sysdev/cpm2.c
@@ -240,6 +240,7 @@ int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode)
         case CPM_CLK_SCC1:
                 reg = &im_cpmux->cmx_scr;
                 shift = 24;
+                break;
         case CPM_CLK_SCC2:
                 reg = &im_cpmux->cmx_scr;
                 shift = 16;
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 12720489e458..8d2cd1de5726 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -72,9 +72,6 @@ config SYS_SUPPORTS_NUMA
 config SYS_SUPPORTS_PCI
         bool
 
-config ARCH_MAY_HAVE_PC_FDC
-        bool
-
 config STACKTRACE_SUPPORT
         def_bool y
 
diff --git a/arch/sh/boot/Makefile b/arch/sh/boot/Makefile
index 3dda24daa0a8..89b408620dcb 100644
--- a/arch/sh/boot/Makefile
+++ b/arch/sh/boot/Makefile
@@ -44,7 +44,7 @@ KERNEL_ENTRY	:= $(shell /bin/bash -c 'printf "0x%08x" \
 
 quiet_cmd_uimage = UIMAGE  $@
       cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A sh -O linux -T kernel \
-                   -C none -a $(KERNEL_LOAD) -e $(KERNEL_ENTRY) \
+                   -C gzip -a $(KERNEL_LOAD) -e $(KERNEL_ENTRY) \
                    -n 'Linux-$(KERNELRELEASE)' -d $< $@
 
 $(obj)/uImage: $(obj)/vmlinux.bin.gz FORCE
diff --git a/arch/sh/kernel/cpu/sh2a/fpu.c b/arch/sh/kernel/cpu/sh2a/fpu.c
index ff99562456fb..5627c0b3ffa8 100644
--- a/arch/sh/kernel/cpu/sh2a/fpu.c
+++ b/arch/sh/kernel/cpu/sh2a/fpu.c
@@ -13,6 +13,7 @@
 #include <linux/signal.h>
 #include <asm/processor.h>
 #include <asm/io.h>
+#include <asm/fpu.h>
 
 /* The PR (precision) bit in the FP Status Register must be clear when
  * an frchg instruction is executed, otherwise the instruction is undefined.
diff --git a/arch/sh/kernel/cpu/sh4/fpu.c b/arch/sh/kernel/cpu/sh4/fpu.c
index 817f9939cda6..8020796139f1 100644
--- a/arch/sh/kernel/cpu/sh4/fpu.c
+++ b/arch/sh/kernel/cpu/sh4/fpu.c
@@ -16,6 +16,7 @@
 #include <asm/cpu/fpu.h>
 #include <asm/processor.h>
 #include <asm/system.h>
+#include <asm/fpu.h>
 
 /* The PR (precision) bit in the FP Status Register must be clear when
  * an frchg instruction is executed, otherwise the instruction is undefined.
diff --git a/arch/sh/kernel/cpu/sh5/fpu.c b/arch/sh/kernel/cpu/sh5/fpu.c
index 30b76a94abf2..dd4f51ffb50e 100644
--- a/arch/sh/kernel/cpu/sh5/fpu.c
+++ b/arch/sh/kernel/cpu/sh5/fpu.c
@@ -17,6 +17,7 @@
 #include <asm/processor.h>
 #include <asm/user.h>
 #include <asm/io.h>
+#include <asm/fpu.h>
 
 /*
  * Initially load the FPU with signalling NANS.  This bit pattern
diff --git a/arch/sh/kernel/dump_task.c b/arch/sh/kernel/dump_task.c
index 4a8a4083ff0b..1db7ce0f25d4 100644
--- a/arch/sh/kernel/dump_task.c
+++ b/arch/sh/kernel/dump_task.c
@@ -1,5 +1,6 @@
 #include <linux/elfcore.h>
 #include <linux/sched.h>
+#include <asm/fpu.h>
 
 /*
  * Capture the user space registers if the task is not running (in user space)
diff --git a/arch/sh/kernel/process_32.c b/arch/sh/kernel/process_32.c
index 9ab1926b9d10..b98e37a1f54c 100644
--- a/arch/sh/kernel/process_32.c
+++ b/arch/sh/kernel/process_32.c
@@ -25,6 +25,7 @@
 #include <asm/pgalloc.h>
 #include <asm/system.h>
 #include <asm/ubc.h>
+#include <asm/fpu.h>
 
 static int hlt_counter;
 int ubc_usercnt = 0;
diff --git a/arch/sh/kernel/signal_32.c b/arch/sh/kernel/signal_32.c
index f6b5fbfe75c4..f311551d9a05 100644
--- a/arch/sh/kernel/signal_32.c
+++ b/arch/sh/kernel/signal_32.c
@@ -29,6 +29,7 @@
 #include <asm/uaccess.h>
 #include <asm/pgtable.h>
 #include <asm/cacheflush.h>
+#include <asm/fpu.h>
 
 #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
 
diff --git a/arch/sparc/kernel/ptrace.c b/arch/sparc/kernel/ptrace.c
index 5b54f11f4e59..7f44ae69b29e 100644
--- a/arch/sparc/kernel/ptrace.c
+++ b/arch/sparc/kernel/ptrace.c
@@ -325,7 +325,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
         const struct user_regset_view *view;
         int ret;
 
-        view = task_user_regset_view(child);
+        view = task_user_regset_view(current);
 
         switch(request) {
         case PTRACE_GETREGS: {
diff --git a/arch/sparc64/defconfig b/arch/sparc64/defconfig
index 250958d1e3cb..9d4bd2229493 100644
--- a/arch/sparc64/defconfig
+++ b/arch/sparc64/defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.25-rc1
-# Sun Feb 17 22:44:12 2008
+# Linux kernel version: 2.6.25-rc3
+# Wed Mar 26 04:33:35 2008
 #
 CONFIG_SPARC=y
 CONFIG_SPARC64=y
@@ -55,9 +55,11 @@ CONFIG_POSIX_MQUEUE=y
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=18
 # CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
 CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_FAIR_USER_SCHED=y
-# CONFIG_FAIR_CGROUP_SCHED is not set
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_RELAY=y
 CONFIG_NAMESPACES=y
@@ -482,6 +484,7 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_SCSI_IPS is not set
 # CONFIG_SCSI_INITIO is not set
 # CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_MVSAS is not set
 # CONFIG_SCSI_STEX is not set
 # CONFIG_SCSI_SYM53C8XX_2 is not set
 # CONFIG_SCSI_QLOGIC_1280 is not set
@@ -810,6 +813,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_ADM1031 is not set
 # CONFIG_SENSORS_ADM9240 is not set
 # CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
 # CONFIG_SENSORS_ATXP1 is not set
 # CONFIG_SENSORS_DS1621 is not set
 # CONFIG_SENSORS_I5K_AMB is not set
diff --git a/arch/sparc64/kernel/cpu.c b/arch/sparc64/kernel/cpu.c
index dd5d28e3d798..0097c08dc600 100644
--- a/arch/sparc64/kernel/cpu.c
+++ b/arch/sparc64/kernel/cpu.c
@@ -15,6 +15,8 @@
 #include <asm/spitfire.h>
 #include <asm/oplib.h>
 
+#include "entry.h"
+
 DEFINE_PER_CPU(cpuinfo_sparc, __cpu_data) = { 0 };
 
 struct cpu_iu_info {
@@ -65,8 +67,6 @@ static struct cpu_iu_info linux_sparc_chips[] = {
 char *sparc_cpu_type;
 char *sparc_fpu_type;
 
-unsigned int fsr_storage;
-
 static void __init sun4v_cpu_probe(void)
 {
         switch (sun4v_chip_type) {
@@ -94,8 +94,10 @@ void __init cpu_probe(void)
         unsigned long ver, fpu_vers, manuf, impl, fprs;
         int i;
         
-        if (tlb_type == hypervisor)
-                return sun4v_cpu_probe();
+        if (tlb_type == hypervisor) {
+                sun4v_cpu_probe();
+                return;
+        }
 
         fprs = fprs_read();
         fprs_write(FPRS_FEF);
diff --git a/arch/sparc64/kernel/entry.S b/arch/sparc64/kernel/entry.S
index 6be4d2d2904e..49eca4b1cf25 100644
--- a/arch/sparc64/kernel/entry.S
+++ b/arch/sparc64/kernel/entry.S
@@ -1705,6 +1705,36 @@ __flushw_user:
 2:      retl
          nop
 
+        /* Flush %fp and %i7 to the stack for all register
+         * windows active inside of the cpu.  This allows
+         * show_stack_trace() to avoid using an expensive
+         * 'flushw'.
+         */
+        .globl          stack_trace_flush
+        .type           stack_trace_flush,#function
+stack_trace_flush:
+        rdpr            %pstate, %o0
+        wrpr            %o0, PSTATE_IE, %pstate
+
+        rdpr            %cwp, %g1
+        rdpr            %canrestore, %g2
+        sub             %g1, 1, %g3
+
+1:      brz,pn          %g2, 2f
+         sub            %g2, 1, %g2
+        wrpr            %g3, %cwp
+        stx             %fp, [%sp + STACK_BIAS + RW_V9_I6]
+        stx             %i7, [%sp + STACK_BIAS + RW_V9_I7]
+        ba,pt           %xcc, 1b
+         sub            %g3, 1, %g3
+
+2:      wrpr            %g1, %cwp
+        wrpr            %o0, %pstate
+
+        retl
+         nop
+        .size           stack_trace_flush,.-stack_trace_flush
+
 #ifdef CONFIG_SMP
         .globl          hard_smp_processor_id
 hard_smp_processor_id:
diff --git a/arch/sparc64/kernel/entry.h b/arch/sparc64/kernel/entry.h
new file mode 100644
index 000000000000..4a91e9c6d31b
--- /dev/null
+++ b/arch/sparc64/kernel/entry.h
@@ -0,0 +1,196 @@
+#ifndef _ENTRY_H
+#define _ENTRY_H
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+
+extern char *sparc_cpu_type;
+extern char *sparc_fpu_type;
+
+extern void __init per_cpu_patch(void);
+extern void __init sun4v_patch(void);
+extern void __init boot_cpu_id_too_large(int cpu);
+extern unsigned int dcache_parity_tl1_occurred;
+extern unsigned int icache_parity_tl1_occurred;
+
+extern asmlinkage void update_perfctrs(void);
+extern asmlinkage void sparc_breakpoint(struct pt_regs *regs);
+extern void timer_interrupt(int irq, struct pt_regs *regs);
+
+extern void do_notify_resume(struct pt_regs *regs,
+                             unsigned long orig_i0,
+                             int restart_syscall,
+                             unsigned long thread_info_flags);
+
+extern asmlinkage void syscall_trace(struct pt_regs *regs,
+                                     int syscall_exit_p);
+
+extern void bad_trap_tl1(struct pt_regs *regs, long lvl);
+
+extern void do_fpe_common(struct pt_regs *regs);
+extern void do_fpieee(struct pt_regs *regs);
+extern void do_fpother(struct pt_regs *regs);
+extern void do_tof(struct pt_regs *regs);
+extern void do_div0(struct pt_regs *regs);
+extern void do_illegal_instruction(struct pt_regs *regs);
+extern void mem_address_unaligned(struct pt_regs *regs,
+                                  unsigned long sfar,
+                                  unsigned long sfsr);
+extern void sun4v_do_mna(struct pt_regs *regs,
+                         unsigned long addr,
+                         unsigned long type_ctx);
+extern void do_privop(struct pt_regs *regs);
+extern void do_privact(struct pt_regs *regs);
+extern void do_cee(struct pt_regs *regs);
+extern void do_cee_tl1(struct pt_regs *regs);
+extern void do_dae_tl1(struct pt_regs *regs);
+extern void do_iae_tl1(struct pt_regs *regs);
+extern void do_div0_tl1(struct pt_regs *regs);
+extern void do_fpdis_tl1(struct pt_regs *regs);
+extern void do_fpieee_tl1(struct pt_regs *regs);
+extern void do_fpother_tl1(struct pt_regs *regs);
+extern void do_ill_tl1(struct pt_regs *regs);
+extern void do_irq_tl1(struct pt_regs *regs);
+extern void do_lddfmna_tl1(struct pt_regs *regs);
+extern void do_stdfmna_tl1(struct pt_regs *regs);
+extern void do_paw(struct pt_regs *regs);
+extern void do_paw_tl1(struct pt_regs *regs);
+extern void do_vaw(struct pt_regs *regs);
+extern void do_vaw_tl1(struct pt_regs *regs);
+extern void do_tof_tl1(struct pt_regs *regs);
+extern void do_getpsr(struct pt_regs *regs);
+
+extern void spitfire_insn_access_exception(struct pt_regs *regs,
+                                           unsigned long sfsr,
+                                           unsigned long sfar);
+extern void spitfire_insn_access_exception_tl1(struct pt_regs *regs,
+                                               unsigned long sfsr,
+                                               unsigned long sfar);
+extern void spitfire_data_access_exception(struct pt_regs *regs,
+                                           unsigned long sfsr,
+                                           unsigned long sfar);
+extern void spitfire_data_access_exception_tl1(struct pt_regs *regs,
+                                               unsigned long sfsr,
+                                               unsigned long sfar);
+extern void spitfire_access_error(struct pt_regs *regs,
+                                  unsigned long status_encoded,
+                                  unsigned long afar);
+
+extern void cheetah_fecc_handler(struct pt_regs *regs,
+                                 unsigned long afsr,
+                                 unsigned long afar);
+extern void cheetah_cee_handler(struct pt_regs *regs,
+                                unsigned long afsr,
+                                unsigned long afar);
+extern void cheetah_deferred_handler(struct pt_regs *regs,
+                                     unsigned long afsr,
+                                     unsigned long afar);
+extern void cheetah_plus_parity_error(int type, struct pt_regs *regs);
+
+extern void sun4v_insn_access_exception(struct pt_regs *regs,
+                                        unsigned long addr,
+                                        unsigned long type_ctx);
+extern void sun4v_insn_access_exception_tl1(struct pt_regs *regs,
+                                            unsigned long addr,
+                                            unsigned long type_ctx);
+extern void sun4v_data_access_exception(struct pt_regs *regs,
+                                        unsigned long addr,
+                                        unsigned long type_ctx);
+extern void sun4v_data_access_exception_tl1(struct pt_regs *regs,
+                                            unsigned long addr,
+                                            unsigned long type_ctx);
+extern void sun4v_resum_error(struct pt_regs *regs,
+                              unsigned long offset);
+extern void sun4v_resum_overflow(struct pt_regs *regs);
+extern void sun4v_nonresum_error(struct pt_regs *regs,
+                                 unsigned long offset);
+extern void sun4v_nonresum_overflow(struct pt_regs *regs);
+
+extern unsigned long sun4v_err_itlb_vaddr;
+extern unsigned long sun4v_err_itlb_ctx;
+extern unsigned long sun4v_err_itlb_pte;
+extern unsigned long sun4v_err_itlb_error;
+
+extern void sun4v_itlb_error_report(struct pt_regs *regs, int tl);
+
+extern unsigned long sun4v_err_dtlb_vaddr;
+extern unsigned long sun4v_err_dtlb_ctx;
+extern unsigned long sun4v_err_dtlb_pte;
+extern unsigned long sun4v_err_dtlb_error;
+
+extern void sun4v_dtlb_error_report(struct pt_regs *regs, int tl);
+extern void hypervisor_tlbop_error(unsigned long err,
+                                   unsigned long op);
+extern void hypervisor_tlbop_error_xcall(unsigned long err,
+                                         unsigned long op);
+
+/* WARNING: The error trap handlers in assembly know the precise
+ *          layout of the following structure.
+ *
+ * C-level handlers in traps.c use this information to log the
+ * error and then determine how to recover (if possible).
+ */
+struct cheetah_err_info {
+/*0x00*/u64 afsr;
+/*0x08*/u64 afar;
+
+        /* D-cache state */
+/*0x10*/u64 dcache_data[4];     /* The actual data      */
+/*0x30*/u64 dcache_index;       /* D-cache index        */
+/*0x38*/u64 dcache_tag;         /* D-cache tag/valid    */
+/*0x40*/u64 dcache_utag;        /* D-cache microtag     */
+/*0x48*/u64 dcache_stag;        /* D-cache snooptag     */
+
+        /* I-cache state */
+/*0x50*/u64 icache_data[8];     /* The actual insns + predecode */
+/*0x90*/u64 icache_index;       /* I-cache index        */
+/*0x98*/u64 icache_tag;         /* I-cache phys tag     */
+/*0xa0*/u64 icache_utag;        /* I-cache microtag     */
+/*0xa8*/u64 icache_stag;        /* I-cache snooptag     */
+/*0xb0*/u64 icache_upper;       /* I-cache upper-tag    */
+/*0xb8*/u64 icache_lower;       /* I-cache lower-tag    */
+
+        /* E-cache state */
+/*0xc0*/u64 ecache_data[4];     /* 32 bytes from staging registers */
+/*0xe0*/u64 ecache_index;       /* E-cache index        */
+/*0xe8*/u64 ecache_tag;         /* E-cache tag/state    */
+
+/*0xf0*/u64 __pad[32 - 30];
+};
+#define CHAFSR_INVALID          ((u64)-1L)
+
+/* This is allocated at boot time based upon the largest hardware
+ * cpu ID in the system.  We allocate two entries per cpu, one for
+ * TL==0 logging and one for TL >= 1 logging.
+ */
+extern struct cheetah_err_info *cheetah_error_log;
+
+/* UPA nodes send interrupt packet to UltraSparc with first data reg
+ * value low 5 (7 on Starfire) bits holding the IRQ identifier being
+ * delivered.  We must translate this into a non-vector IRQ so we can
+ * set the softint on this cpu.
+ *
+ * To make processing these packets efficient and race free we use
+ * an array of irq buckets below.  The interrupt vector handler in
+ * entry.S feeds incoming packets into per-cpu pil-indexed lists.
+ *
+ * If you make changes to ino_bucket, please update hand coded assembler
+ * of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S
+ */
+struct ino_bucket {
+/*0x00*/unsigned long __irq_chain_pa;
+
+        /* Virtual interrupt number assigned to this INO.  */
+/*0x08*/unsigned int __virt_irq;
+/*0x0c*/unsigned int __pad;
+};
+
+extern struct ino_bucket *ivector_table;
+extern unsigned long ivector_table_pa;
+
+extern void handler_irq(int irq, struct pt_regs *regs);
+extern void init_irqwork_curcpu(void);
+extern void __cpuinit sun4v_register_mondo_queues(int this_cpu);
+
+#endif /* _ENTRY_H */
diff --git a/arch/sparc64/kernel/iommu.c b/arch/sparc64/kernel/iommu.c
index fbaab3497bfd..756fa24eeefa 100644
--- a/arch/sparc64/kernel/iommu.c
+++ b/arch/sparc64/kernel/iommu.c
@@ -516,9 +516,11 @@ static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist,
         unsigned long flags, handle, prot, ctx;
         dma_addr_t dma_next = 0, dma_addr;
         unsigned int max_seg_size;
+        unsigned long seg_boundary_size;
         int outcount, incount, i;
         struct strbuf *strbuf;
         struct iommu *iommu;
+        unsigned long base_shift;
 
         BUG_ON(direction == DMA_NONE);
 
@@ -549,8 +551,11 @@ static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist,
         outs->dma_length = 0;
 
         max_seg_size = dma_get_max_seg_size(dev);
+        seg_boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
+                                  IO_PAGE_SIZE) >> IO_PAGE_SHIFT;
+        base_shift = iommu->page_table_map_base >> IO_PAGE_SHIFT;
         for_each_sg(sglist, s, nelems, i) {
-                unsigned long paddr, npages, entry, slen;
+                unsigned long paddr, npages, entry, out_entry = 0, slen;
                 iopte_t *base;
 
                 slen = s->length;
@@ -593,7 +598,9 @@ static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist,
                          * - allocated dma_addr isn't contiguous to previous allocation
                          */
                         if ((dma_addr != dma_next) ||
-                            (outs->dma_length + s->length > max_seg_size)) {
+                            (outs->dma_length + s->length > max_seg_size) ||
+                            (is_span_boundary(out_entry, base_shift,
+                                              seg_boundary_size, outs, s))) {
                                 /* Can't merge: create a new segment */
                                 segstart = s;
                                 outcount++;
@@ -607,6 +614,7 @@ static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist,
                         /* This is a new segment, fill entries */
                         outs->dma_address = dma_addr;
                         outs->dma_length = slen;
+                        out_entry = entry;
                 }
 
                 /* Calculate next page pointer for contiguous check */
@@ -626,7 +634,7 @@ static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist,
 iommu_map_failed:
         for_each_sg(sglist, s, nelems, i) {
                 if (s->dma_length != 0) {
-                        unsigned long vaddr, npages, entry, i;
+                        unsigned long vaddr, npages, entry, j;
                         iopte_t *base;
 
                         vaddr = s->dma_address & IO_PAGE_MASK;
@@ -637,8 +645,8 @@ iommu_map_failed:
                                 >> IO_PAGE_SHIFT;
                         base = iommu->page_table + entry;
 
-                        for (i = 0; i < npages; i++)
-                                iopte_make_dummy(iommu, base + i);
+                        for (j = 0; j < npages; j++)
+                                iopte_make_dummy(iommu, base + j);
 
                         s->dma_address = DMA_ERROR_CODE;
                         s->dma_length = 0;
@@ -803,7 +811,7 @@ static void dma_4u_sync_sg_for_cpu(struct device *dev,
         spin_unlock_irqrestore(&iommu->lock, flags);
 }
 
-const struct dma_ops sun4u_dma_ops = {
+static const struct dma_ops sun4u_dma_ops = {
         .alloc_coherent         = dma_4u_alloc_coherent,
         .free_coherent          = dma_4u_free_coherent,
         .map_single             = dma_4u_map_single,
diff --git a/arch/sparc64/kernel/iommu_common.h b/arch/sparc64/kernel/iommu_common.h
index 0713bd58499c..f3575a614fa2 100644
--- a/arch/sparc64/kernel/iommu_common.h
+++ b/arch/sparc64/kernel/iommu_common.h
@@ -12,6 +12,7 @@
 #include <linux/mm.h>
 #include <linux/scatterlist.h>
 #include <linux/device.h>
+#include <linux/iommu-helper.h>
 
 #include <asm/iommu.h>
 #include <asm/scatterlist.h>
@@ -45,17 +46,16 @@ static inline unsigned long iommu_num_pages(unsigned long vaddr,
         return npages;
 }
 
-static inline unsigned long calc_npages(struct scatterlist *sglist, int nelems)
+static inline int is_span_boundary(unsigned long entry,
+                                   unsigned long shift,
+                                   unsigned long boundary_size,
+                                   struct scatterlist *outs,
+                                   struct scatterlist *sg)
 {
-        unsigned long i, npages = 0;
-        struct scatterlist *sg;
+        unsigned long paddr = SG_ENT_PHYS_ADDRESS(outs);
+        int nr = iommu_num_pages(paddr, outs->dma_length + sg->length);
 
-        for_each_sg(sglist, sg, nelems, i) {
-                unsigned long paddr = SG_ENT_PHYS_ADDRESS(sg);
-                npages += iommu_num_pages(paddr, sg->length);
-        }
-
-        return npages;
+        return iommu_is_span_boundary(entry, nr, shift, boundary_size);
 }
 
 extern unsigned long iommu_range_alloc(struct device *dev,
diff --git a/arch/sparc64/kernel/irq.c b/arch/sparc64/kernel/irq.c
index 5ec06c8c7fea..eb88bd6e674e 100644
--- a/arch/sparc64/kernel/irq.c
+++ b/arch/sparc64/kernel/irq.c
@@ -44,27 +44,10 @@
 #include <asm/hypervisor.h>
 #include <asm/cacheflush.h>
 
-/* UPA nodes send interrupt packet to UltraSparc with first data reg
- * value low 5 (7 on Starfire) bits holding the IRQ identifier being
- * delivered.  We must translate this into a non-vector IRQ so we can
- * set the softint on this cpu.
- *
- * To make processing these packets efficient and race free we use
- * an array of irq buckets below.  The interrupt vector handler in
- * entry.S feeds incoming packets into per-cpu pil-indexed lists.
- *
- * If you make changes to ino_bucket, please update hand coded assembler
- * of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S
- */
-struct ino_bucket {
-/*0x00*/unsigned long __irq_chain_pa;
-
-        /* Virtual interrupt number assigned to this INO.  */
-/*0x08*/unsigned int __virt_irq;
-/*0x0c*/unsigned int __pad;
-};
+#include "entry.h"
 
 #define NUM_IVECS       (IMAP_INR + 1)
+
 struct ino_bucket *ivector_table;
 unsigned long ivector_table_pa;
 
diff --git a/arch/sparc64/kernel/pci_sun4v.c b/arch/sparc64/kernel/pci_sun4v.c
index ddca6c6c0b49..01839706bd52 100644
--- a/arch/sparc64/kernel/pci_sun4v.c
+++ b/arch/sparc64/kernel/pci_sun4v.c
@@ -335,8 +335,10 @@ static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
         unsigned long flags, handle, prot;
         dma_addr_t dma_next = 0, dma_addr;
         unsigned int max_seg_size;
+        unsigned long seg_boundary_size;
         int outcount, incount, i;
         struct iommu *iommu;
+        unsigned long base_shift;
         long err;
 
         BUG_ON(direction == DMA_NONE);
@@ -362,8 +364,11 @@ static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
         iommu_batch_start(dev, prot, ~0UL);
 
         max_seg_size = dma_get_max_seg_size(dev);
+        seg_boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
+                                  IO_PAGE_SIZE) >> IO_PAGE_SHIFT;
+        base_shift = iommu->page_table_map_base >> IO_PAGE_SHIFT;
         for_each_sg(sglist, s, nelems, i) {
-                unsigned long paddr, npages, entry, slen;
+                unsigned long paddr, npages, entry, out_entry = 0, slen;
 
                 slen = s->length;
                 /* Sanity check */
@@ -406,7 +411,9 @@ static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
                          * - allocated dma_addr isn't contiguous to previous allocation
                          */
                         if ((dma_addr != dma_next) ||
-                            (outs->dma_length + s->length > max_seg_size)) {
+                            (outs->dma_length + s->length > max_seg_size) ||
+                            (is_span_boundary(out_entry, base_shift,
+                                              seg_boundary_size, outs, s))) {
                                 /* Can't merge: create a new segment */
                                 segstart = s;
                                 outcount++;
@@ -420,6 +427,7 @@ static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
                         /* This is a new segment, fill entries */
                         outs->dma_address = dma_addr;
                         outs->dma_length = slen;
+                        out_entry = entry;
                 }
 
                 /* Calculate next page pointer for contiguous check */
diff --git a/arch/sparc64/kernel/ptrace.c b/arch/sparc64/kernel/ptrace.c
index 9a1ba1fe859d..e9fc0aa2da38 100644
--- a/arch/sparc64/kernel/ptrace.c
+++ b/arch/sparc64/kernel/ptrace.c
@@ -35,6 +35,9 @@
 #include <asm/spitfire.h>
 #include <asm/page.h>
 #include <asm/cpudata.h>
+#include <asm/cacheflush.h>
+
+#include "entry.h"
 
 /* #define ALLOW_INIT_TRACING */
 
@@ -67,6 +70,8 @@ void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
         if (tlb_type == hypervisor)
                 return;
 
+        preempt_disable();
+
 #ifdef DCACHE_ALIASING_POSSIBLE
         /* If bit 13 of the kernel address we used to access the
          * user page is the same as the virtual address that page
@@ -105,6 +110,87 @@ void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
                 for (; start < end; start += icache_line_size)
                         flushi(start);
         }
+
+        preempt_enable();
+}
+
+static int get_from_target(struct task_struct *target, unsigned long uaddr,
+                           void *kbuf, int len)
+{
+        if (target == current) {
+                if (copy_from_user(kbuf, (void __user *) uaddr, len))
+                        return -EFAULT;
+        } else {
+                int len2 = access_process_vm(target, uaddr, kbuf, len, 0);
+                if (len2 != len)
+                        return -EFAULT;
+        }
+        return 0;
+}
+
+static int set_to_target(struct task_struct *target, unsigned long uaddr,
+                         void *kbuf, int len)
+{
+        if (target == current) {
+                if (copy_to_user((void __user *) uaddr, kbuf, len))
+                        return -EFAULT;
+        } else {
+                int len2 = access_process_vm(target, uaddr, kbuf, len, 1);
+                if (len2 != len)
+                        return -EFAULT;
+        }
+        return 0;
+}
+
+static int regwindow64_get(struct task_struct *target,
+                           const struct pt_regs *regs,
+                           struct reg_window *wbuf)
+{
+        unsigned long rw_addr = regs->u_regs[UREG_I6];
+
+        if (test_tsk_thread_flag(current, TIF_32BIT)) {
+                struct reg_window32 win32;
+                int i;
+
+                if (get_from_target(target, rw_addr, &win32, sizeof(win32)))
+                        return -EFAULT;
+                for (i = 0; i < 8; i++)
+                        wbuf->locals[i] = win32.locals[i];
+                for (i = 0; i < 8; i++)
+                        wbuf->ins[i] = win32.ins[i];
+        } else {
+                rw_addr += STACK_BIAS;
+                if (get_from_target(target, rw_addr, wbuf, sizeof(*wbuf)))
+                        return -EFAULT;
+        }
+
+        return 0;
+}
+
+static int regwindow64_set(struct task_struct *target,
+                           const struct pt_regs *regs,
+                           struct reg_window *wbuf)
+{
+        unsigned long rw_addr = regs->u_regs[UREG_I6];
+
+        if (test_tsk_thread_flag(current, TIF_32BIT)) {
+                struct reg_window32 win32;
+                int i;
+
+                for (i = 0; i < 8; i++)
+                        win32.locals[i] = wbuf->locals[i];
+                for (i = 0; i < 8; i++)
+                        win32.ins[i] = wbuf->ins[i];
+
+                if (set_to_target(target, rw_addr, &win32, sizeof(win32)))
+                        return -EFAULT;
+        } else {
+                rw_addr += STACK_BIAS;
+                if (set_to_target(target, rw_addr, wbuf, sizeof(*wbuf)))
+                        return -EFAULT;
+        }
+
+        return 0;
 }
 
 enum sparc_regset {
@@ -126,16 +212,13 @@ static int genregs64_get(struct task_struct *target,
         ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
                                   regs->u_regs,
                                   0, 16 * sizeof(u64));
-        if (!ret) {
-                unsigned long __user *reg_window = (unsigned long __user *)
-                        (regs->u_regs[UREG_I6] + STACK_BIAS);
-                unsigned long window[16];
+        if (!ret && count && pos < (32 * sizeof(u64))) {
+                struct reg_window window;
 
-                if (copy_from_user(window, reg_window, sizeof(window)))
+                if (regwindow64_get(target, regs, &window))
                         return -EFAULT;
-
                 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
-                                          window,
+                                          &window,
                                           16 * sizeof(u64),
                                           32 * sizeof(u64));
         }
@@ -157,10 +240,11 @@ static int genregs64_get(struct task_struct *target,
                                           36 * sizeof(u64));
         }
 
-        if (!ret)
+        if (!ret) {
                 ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
                                                36 * sizeof(u64), -1);
 
+        }
         return ret;
 }
 
@@ -178,20 +262,19 @@ static int genregs64_set(struct task_struct *target,
         ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
                                  regs->u_regs,
                                  0, 16 * sizeof(u64));
-        if (!ret && count > 0) {
-                unsigned long __user *reg_window = (unsigned long __user *)
-                        (regs->u_regs[UREG_I6] + STACK_BIAS);
-                unsigned long window[16];
+        if (!ret && count && pos < (32 * sizeof(u64))) {
+                struct reg_window window;
 
-                if (copy_from_user(window, reg_window, sizeof(window)))
+                if (regwindow64_get(target, regs, &window))
                         return -EFAULT;
 
                 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
-                                         window,
+                                         &window,
                                          16 * sizeof(u64),
                                          32 * sizeof(u64));
+
                 if (!ret &&
-                    copy_to_user(reg_window, window, sizeof(window)))
+                    regwindow64_set(target, regs, &window))
                         return -EFAULT;
         }
 
@@ -382,6 +465,7 @@ static const struct user_regset_view user_sparc64_view = {
         .regsets = sparc64_regsets, .n = ARRAY_SIZE(sparc64_regsets)
 };
 
+#ifdef CONFIG_COMPAT
 static int genregs32_get(struct task_struct *target,
                          const struct user_regset *regset,
                          unsigned int pos, unsigned int count,
@@ -404,9 +488,22 @@ static int genregs32_get(struct task_struct *target,
                         *k++ = regs->u_regs[pos++];
 
                 reg_window = (compat_ulong_t __user *) regs->u_regs[UREG_I6];
-                for (; count > 0 && pos < 32; count--) {
-                        if (get_user(*k++, &reg_window[pos++]))
-                                return -EFAULT;
+                if (target == current) {
+                        for (; count > 0 && pos < 32; count--) {
+                                if (get_user(*k++, &reg_window[pos++]))
+                                        return -EFAULT;
+                        }
+                } else {
+                        for (; count > 0 && pos < 32; count--) {
+                                if (access_process_vm(target,
+                                                      (unsigned long)
+                                                      &reg_window[pos],
+                                                      k, sizeof(*k), 0)
+                                    != sizeof(*k))
+                                        return -EFAULT;
+                                k++;
+                                pos++;
+                        }
                 }
         } else {
                 for (; count > 0 && pos < 16; count--) {
@@ -415,10 +512,28 @@ static int genregs32_get(struct task_struct *target,
                 }
 
                 reg_window = (compat_ulong_t __user *) regs->u_regs[UREG_I6];
-                for (; count > 0 && pos < 32; count--) {
-                        if (get_user(reg, &reg_window[pos++]) ||
-                            put_user(reg, u++))
-                                return -EFAULT;
+                if (target == current) {
+                        for (; count > 0 && pos < 32; count--) {
+                                if (get_user(reg, &reg_window[pos++]) ||
+                                    put_user(reg, u++))
+                                        return -EFAULT;
+                        }
+                } else {
+                        for (; count > 0 && pos < 32; count--) {
+                                if (access_process_vm(target,
+                                                      (unsigned long)
+                                                      &reg_window[pos],
+                                                      &reg, sizeof(reg), 0)
+                                    != sizeof(reg))
+                                        return -EFAULT;
+                                if (access_process_vm(target,
+                                                      (unsigned long) u,
+                                                      &reg, sizeof(reg), 1)
+                                    != sizeof(reg))
+                                        return -EFAULT;
+                                pos++;
+                                u++;
+                        }
                 }
         }
         while (count > 0) {
@@ -480,9 +595,23 @@ static int genregs32_set(struct task_struct *target,
                         regs->u_regs[pos++] = *k++;
 
                 reg_window = (compat_ulong_t __user *) regs->u_regs[UREG_I6];
-                for (; count > 0 && pos < 32; count--) {
-                        if (put_user(*k++, &reg_window[pos++]))
-                                return -EFAULT;
+                if (target == current) {
+                        for (; count > 0 && pos < 32; count--) {
+                                if (put_user(*k++, &reg_window[pos++]))
+                                        return -EFAULT;
+                        }
+                } else {
+                        for (; count > 0 && pos < 32; count--) {
+                                if (access_process_vm(target,
+                                                      (unsigned long)
+                                                      &reg_window[pos],
+                                                      (void *) k,
+                                                      sizeof(*k), 1)
+                                    != sizeof(*k))
+                                        return -EFAULT;
+                                k++;
+                                pos++;
+                        }
                 }
         } else {
                 for (; count > 0 && pos < 16; count--) {
@@ -492,10 +621,29 @@ static int genregs32_set(struct task_struct *target,
                 }
 
                 reg_window = (compat_ulong_t __user *) regs->u_regs[UREG_I6];
-                for (; count > 0 && pos < 32; count--) {
-                        if (get_user(reg, u++) ||
-                            put_user(reg, &reg_window[pos++]))
-                                return -EFAULT;
+                if (target == current) {
+                        for (; count > 0 && pos < 32; count--) {
+                                if (get_user(reg, u++) ||
+                                    put_user(reg, &reg_window[pos++]))
+                                        return -EFAULT;
+                        }
+                } else {
+                        for (; count > 0 && pos < 32; count--) {
+                                if (access_process_vm(target,
+                                                      (unsigned long)
+                                                      u,
+                                                      &reg, sizeof(reg), 0)
+                                    != sizeof(reg))
+                                        return -EFAULT;
+                                if (access_process_vm(target,
+                                                      (unsigned long)
+                                                      &reg_window[pos],
+                                                      &reg, sizeof(reg), 1)
+                                    != sizeof(reg))
+                                        return -EFAULT;
+                                pos++;
+                                u++;
+                        }
                 }
         }
         while (count > 0) {
@@ -676,14 +824,18 @@ static const struct user_regset_view user_sparc32_view = {
         .name = "sparc", .e_machine = EM_SPARC,
         .regsets = sparc32_regsets, .n = ARRAY_SIZE(sparc32_regsets)
 };
+#endif /* CONFIG_COMPAT */
 
 const struct user_regset_view *task_user_regset_view(struct task_struct *task)
 {
+#ifdef CONFIG_COMPAT
         if (test_tsk_thread_flag(task, TIF_32BIT))
                 return &user_sparc32_view;
+#endif
         return &user_sparc64_view;
 }
 
+#ifdef CONFIG_COMPAT
 struct compat_fps {
         unsigned int regs[32];
         unsigned int fsr;
@@ -699,7 +851,7 @@ struct compat_fps {
 long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
                         compat_ulong_t caddr, compat_ulong_t cdata)
 {
-        const struct user_regset_view *view = task_user_regset_view(child);
+        const struct user_regset_view *view = task_user_regset_view(current);
         compat_ulong_t caddr2 = task_pt_regs(current)->u_regs[UREG_I4];
         struct pt_regs32 __user *pregs;
         struct compat_fps __user *fps;
@@ -798,6 +950,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
 
         return ret;
 }
+#endif /* CONFIG_COMPAT */
 
 struct fps {
         unsigned int regs[64];
@@ -806,12 +959,15 @@ struct fps {
 
 long arch_ptrace(struct task_struct *child, long request, long addr, long data)
 {
-        const struct user_regset_view *view = task_user_regset_view(child);
-        struct pt_regs __user *pregs = (struct pt_regs __user *) addr;
+        const struct user_regset_view *view = task_user_regset_view(current);
         unsigned long addr2 = task_pt_regs(current)->u_regs[UREG_I4];
-        struct fps __user *fps = (struct fps __user *) addr;
+        struct pt_regs __user *pregs;
+        struct fps __user *fps;
         int ret;
 
+        pregs = (struct pt_regs __user *) (unsigned long) addr;
+        fps = (struct fps __user *) (unsigned long) addr;
+
         switch (request) {
         case PTRACE_PEEKUSR:
                 ret = (addr != 0) ? -EIO : 0;
diff --git a/arch/sparc64/kernel/setup.c b/arch/sparc64/kernel/setup.c
index d036dbe72864..6acb4c51cfe4 100644
--- a/arch/sparc64/kernel/setup.c
+++ b/arch/sparc64/kernel/setup.c
@@ -51,6 +51,8 @@
 #include <net/ipconfig.h>
 #endif
 
+#include "entry.h"
+
 /* Used to synchronize accesses to NatSemi SUPER I/O chip configure
  * operations in asm/ns87303.h
  */
@@ -335,9 +337,6 @@ void __init setup_arch(char **cmdline_p)
 
 /* BUFFER is PAGE_SIZE bytes long. */
 
-extern char *sparc_cpu_type;
-extern char *sparc_fpu_type;
-
 extern void smp_info(struct seq_file *);
 extern void smp_bogo(struct seq_file *);
 extern void mmu_info(struct seq_file *);
diff --git a/arch/sparc64/kernel/signal.c b/arch/sparc64/kernel/signal.c
index fb13775b3682..9d51956e8e2f 100644
--- a/arch/sparc64/kernel/signal.c
+++ b/arch/sparc64/kernel/signal.c
@@ -32,6 +32,9 @@
 #include <asm/siginfo.h>
 #include <asm/visasm.h>
 
+#include "entry.h"
+#include "systbls.h"
+
 #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
 
 /* {set, get}context() needed for 64-bit SparcLinux userland. */
@@ -354,7 +357,7 @@ static int invalid_frame_pointer(void __user *fp, int fplen)
 static inline int
 save_fpu_state(struct pt_regs *regs, __siginfo_fpu_t __user *fpu)
 {
-        unsigned long *fpregs = (unsigned long *)(regs+1);
+        unsigned long *fpregs = current_thread_info()->fpregs;
         unsigned long fprs;
         int err = 0;
         
diff --git a/arch/sparc64/kernel/smp.c b/arch/sparc64/kernel/smp.c
index 5a1126b363a4..59f020d69d4c 100644
--- a/arch/sparc64/kernel/smp.c
+++ b/arch/sparc64/kernel/smp.c
@@ -1,6 +1,6 @@
 /* smp.c: Sparc64 SMP support.
  *
- * Copyright (C) 1997, 2007 David S. Miller (davem@davemloft.net)
+ * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
  */
 
 #include <linux/module.h>
@@ -30,6 +30,7 @@
 #include <asm/cpudata.h>
 #include <asm/hvtramp.h>
 #include <asm/io.h>
+#include <asm/timer.h>
 
 #include <asm/irq.h>
 #include <asm/irq_regs.h>
diff --git a/arch/sparc64/kernel/stacktrace.c b/arch/sparc64/kernel/stacktrace.c
index 47f92a59be18..84d39e873e88 100644
--- a/arch/sparc64/kernel/stacktrace.c
+++ b/arch/sparc64/kernel/stacktrace.c
@@ -2,13 +2,15 @@
 #include <linux/stacktrace.h>
 #include <linux/thread_info.h>
 #include <asm/ptrace.h>
+#include <asm/stacktrace.h>
 
 void save_stack_trace(struct stack_trace *trace)
 {
         unsigned long ksp, fp, thread_base;
         struct thread_info *tp = task_thread_info(current);
 
-        flushw_all();
+        stack_trace_flush();
+
         __asm__ __volatile__(
                 "mov    %%fp, %0"
                 : "=r" (ksp)
diff --git a/arch/sparc64/kernel/sys_sparc.c b/arch/sparc64/kernel/sys_sparc.c
index 134d801579f9..f952745d0f3d 100644
--- a/arch/sparc64/kernel/sys_sparc.c
+++ b/arch/sparc64/kernel/sys_sparc.c
@@ -1,5 +1,4 @@
-/* $Id: sys_sparc.c,v 1.57 2002/02/09 19:49:30 davem Exp $
- * linux/arch/sparc64/kernel/sys_sparc.c
+/* linux/arch/sparc64/kernel/sys_sparc.c
  *
  * This file contains various random system calls that
  * have a non-standard calling sequence on the Linux/sparc
@@ -30,6 +29,9 @@
 #include <asm/perfctr.h>
 #include <asm/unistd.h>
 
+#include "entry.h"
+#include "systbls.h"
+
 /* #define DEBUG_UNIMP_SYSCALL */
 
 asmlinkage unsigned long sys_getpagesize(void)
@@ -445,7 +447,8 @@ asmlinkage long sys_ipc(unsigned int call, int first, unsigned long second,
                         goto out;
                 case SEMTIMEDOP:
                         err = sys_semtimedop(first, ptr, (unsigned)second,
-                                (const struct timespec __user *) fifth);
+                                (const struct timespec __user *)
+                                             (unsigned long) fifth);
                         goto out;
                 case SEMGET:
                         err = sys_semget(first, (int)second, (int)third);
@@ -788,7 +791,7 @@ asmlinkage long sys_utrap_install(utrap_entry_t type,
         } else {
                 if ((utrap_handler_t)current_thread_info()->utraps[type] != new_p &&
                     current_thread_info()->utraps[0] > 1) {
-                        long *p = current_thread_info()->utraps;
+                        unsigned long *p = current_thread_info()->utraps;
 
                         current_thread_info()->utraps =
                                 kmalloc((UT_TRAP_INSTRUCTION_31+1)*sizeof(long),
@@ -816,7 +819,8 @@ asmlinkage long sys_utrap_install(utrap_entry_t type,
         return 0;
 }
 
-long sparc_memory_ordering(unsigned long model, struct pt_regs *regs)
+asmlinkage long sparc_memory_ordering(unsigned long model,
+                                      struct pt_regs *regs)
 {
         if (model >= 3)
                 return -EINVAL;
diff --git a/arch/sparc64/kernel/systbls.h b/arch/sparc64/kernel/systbls.h
new file mode 100644
index 000000000000..8a0d20a35d0c
--- /dev/null
+++ b/arch/sparc64/kernel/systbls.h
@@ -0,0 +1,53 @@
+#ifndef _SYSTBLS_H
+#define _SYSTBLS_H
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/utsname.h>
+#include <asm/utrap.h>
+#include <asm/signal.h>
+
+extern asmlinkage unsigned long sys_getpagesize(void);
+extern asmlinkage unsigned long sparc_brk(unsigned long brk);
+extern asmlinkage long sparc_pipe(struct pt_regs *regs);
+extern asmlinkage long sys_ipc(unsigned int call, int first,
+                               unsigned long second,
+                               unsigned long third,
+                               void __user *ptr, long fifth);
+extern asmlinkage long sparc64_newuname(struct new_utsname __user *name);
+extern asmlinkage long sparc64_personality(unsigned long personality);
+extern asmlinkage unsigned long sys_mmap(unsigned long addr, unsigned long len,
+                                         unsigned long prot, unsigned long flags,
+                                         unsigned long fd, unsigned long off);
+extern asmlinkage long sys64_munmap(unsigned long addr, size_t len);
+extern asmlinkage unsigned long sys64_mremap(unsigned long addr,
+                                             unsigned long old_len,
+                                             unsigned long new_len,
+                                             unsigned long flags,
+                                             unsigned long new_addr);
+extern asmlinkage unsigned long c_sys_nis_syscall(struct pt_regs *regs);
+extern asmlinkage long sys_getdomainname(char __user *name, int len);
+extern asmlinkage long solaris_syscall(struct pt_regs *regs);
+extern asmlinkage long sunos_syscall(struct pt_regs *regs);
+extern asmlinkage long sys_utrap_install(utrap_entry_t type,
+                                         utrap_handler_t new_p,
+                                         utrap_handler_t new_d,
+                                         utrap_handler_t __user *old_p,
+                                         utrap_handler_t __user *old_d);
+extern asmlinkage long sparc_memory_ordering(unsigned long model,
+                                             struct pt_regs *regs);
+extern asmlinkage long sys_rt_sigaction(int sig,
+                                        const struct sigaction __user *act,
+                                        struct sigaction __user *oact,
+                                        void __user *restorer,
+                                        size_t sigsetsize);
+extern asmlinkage long sys_perfctr(int opcode, unsigned long arg0,
+                                   unsigned long arg1, unsigned long arg2);
+
+extern asmlinkage void sparc64_set_context(struct pt_regs *regs);
+extern asmlinkage void sparc64_get_context(struct pt_regs *regs);
+extern asmlinkage long sys_sigpause(unsigned int set);
+extern asmlinkage long sys_sigsuspend(old_sigset_t set);
+extern void do_rt_sigreturn(struct pt_regs *regs);
+
+#endif /* _SYSTBLS_H */
diff --git a/arch/sparc64/kernel/time.c b/arch/sparc64/kernel/time.c
index d204f1ab1d4c..e5d238970c7e 100644
--- a/arch/sparc64/kernel/time.c
+++ b/arch/sparc64/kernel/time.c
@@ -1,7 +1,6 @@
-/* $Id: time.c,v 1.42 2002/01/23 14:33:55 davem Exp $
- * time.c: UltraSparc timer and TOD clock support.
+/* time.c: UltraSparc timer and TOD clock support.
  *
- * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright (C) 1997, 2008 David S. Miller (davem@davemloft.net)
  * Copyright (C) 1998 Eddie C. Dost   (ecd@skynet.be)
  *
  * Based largely on code which is:
@@ -48,6 +47,8 @@
 #include <asm/uaccess.h>
 #include <asm/irq_regs.h>
 
+#include "entry.h"
+
 DEFINE_SPINLOCK(mostek_lock);
 DEFINE_SPINLOCK(rtc_lock);
 void __iomem *mstk48t02_regs = NULL;
@@ -508,6 +509,37 @@ static int __init has_low_battery(void)
         return (data1 == data2);        /* Was the write blocked? */
 }
 
+static void __init mostek_set_system_time(void __iomem *mregs)
+{
+        unsigned int year, mon, day, hour, min, sec;
+        u8 tmp;
+
+        spin_lock_irq(&mostek_lock);
+
+        /* Traditional Mostek chip. */
+        tmp = mostek_read(mregs + MOSTEK_CREG);
+        tmp |= MSTK_CREG_READ;
+        mostek_write(mregs + MOSTEK_CREG, tmp);
+
+        sec = MSTK_REG_SEC(mregs);
+        min = MSTK_REG_MIN(mregs);
+        hour = MSTK_REG_HOUR(mregs);
+        day = MSTK_REG_DOM(mregs);
+        mon = MSTK_REG_MONTH(mregs);
+        year = MSTK_CVT_YEAR( MSTK_REG_YEAR(mregs) );
+
+        xtime.tv_sec = mktime(year, mon, day, hour, min, sec);
+        xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ);
+        set_normalized_timespec(&wall_to_monotonic,
+                                -xtime.tv_sec, -xtime.tv_nsec);
+
+        tmp = mostek_read(mregs + MOSTEK_CREG);
+        tmp &= ~MSTK_CREG_READ;
+        mostek_write(mregs + MOSTEK_CREG, tmp);
+
+        spin_unlock_irq(&mostek_lock);
+}
+
 /* Probe for the real time clock chip. */
 static void __init set_system_time(void)
 {
@@ -520,7 +552,6 @@ static void __init set_system_time(void)
         unsigned long dregs = 0UL;
         void __iomem *bregs = 0UL;
 #endif
-        u8 tmp;
 
         if (!mregs && !dregs && !bregs) {
                 prom_printf("Something wrong, clock regs not mapped yet.\n");
@@ -528,20 +559,11 @@ static void __init set_system_time(void)
         }               
 
         if (mregs) {
-                spin_lock_irq(&mostek_lock);
-
-                /* Traditional Mostek chip. */
-                tmp = mostek_read(mregs + MOSTEK_CREG);
-                tmp |= MSTK_CREG_READ;
-                mostek_write(mregs + MOSTEK_CREG, tmp);
+                mostek_set_system_time(mregs);
+                return;
+        }
 
-                sec = MSTK_REG_SEC(mregs);
-                min = MSTK_REG_MIN(mregs);
-                hour = MSTK_REG_HOUR(mregs);
-                day = MSTK_REG_DOM(mregs);
-                mon = MSTK_REG_MONTH(mregs);
-                year = MSTK_CVT_YEAR( MSTK_REG_YEAR(mregs) );
-        } else if (bregs) {
+        if (bregs) {
                 unsigned char val = readb(bregs + 0x0e);
                 unsigned int century;
 
@@ -596,14 +618,6 @@ static void __init set_system_time(void)
         xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ);
         set_normalized_timespec(&wall_to_monotonic,
                                 -xtime.tv_sec, -xtime.tv_nsec);
-
-        if (mregs) {
-                tmp = mostek_read(mregs + MOSTEK_CREG);
-                tmp &= ~MSTK_CREG_READ;
-                mostek_write(mregs + MOSTEK_CREG, tmp);
-
-                spin_unlock_irq(&mostek_lock);
-        }
 }
 
 /* davem suggests we keep this within the 4M locked kernel image */
@@ -1027,7 +1041,7 @@ void __init time_init(void)
         setup_clockevent_multiplier(clock);
 
         sparc64_clockevent.max_delta_ns =
-                clockevent_delta2ns(0x7fffffffffffffff, &sparc64_clockevent);
+                clockevent_delta2ns(0x7fffffffffffffffUL, &sparc64_clockevent);
         sparc64_clockevent.min_delta_ns =
                 clockevent_delta2ns(0xF, &sparc64_clockevent);
 
diff --git a/arch/sparc64/kernel/traps.c b/arch/sparc64/kernel/traps.c
index 007f5317c0de..96da847023f3 100644
--- a/arch/sparc64/kernel/traps.c
+++ b/arch/sparc64/kernel/traps.c
@@ -42,6 +42,7 @@
 #endif
 #include <asm/prom.h>
 
+#include "entry.h"
 
 /* When an irrecoverable trap occurs at tl > 0, the trap entry
  * code logs the trap state registers at every level in the trap
@@ -77,11 +78,6 @@ static void dump_tl1_traplog(struct tl1_traplog *p)
         }
 }
 
-void do_call_debug(struct pt_regs *regs) 
-{ 
-        notify_die(DIE_CALL, "debug call", regs, 0, 255, SIGINT); 
-}
-
 void bad_trap(struct pt_regs *regs, long lvl)
 {
         char buffer[32];
@@ -550,41 +546,6 @@ static unsigned long ecache_flush_physbase;
 static unsigned long ecache_flush_linesize;
 static unsigned long ecache_flush_size;
 
-/* WARNING: The error trap handlers in assembly know the precise
- *          layout of the following structure.
- *
- * C-level handlers below use this information to log the error
- * and then determine how to recover (if possible).
- */
-struct cheetah_err_info {
-/*0x00*/u64 afsr;
-/*0x08*/u64 afar;
-
-        /* D-cache state */
-/*0x10*/u64 dcache_data[4];     /* The actual data      */
-/*0x30*/u64 dcache_index;       /* D-cache index        */
-/*0x38*/u64 dcache_tag;         /* D-cache tag/valid    */
-/*0x40*/u64 dcache_utag;        /* D-cache microtag     */
-/*0x48*/u64 dcache_stag;        /* D-cache snooptag     */
-
-        /* I-cache state */
-/*0x50*/u64 icache_data[8];     /* The actual insns + predecode */
-/*0x90*/u64 icache_index;       /* I-cache index        */
-/*0x98*/u64 icache_tag;         /* I-cache phys tag     */
-/*0xa0*/u64 icache_utag;        /* I-cache microtag     */
-/*0xa8*/u64 icache_stag;        /* I-cache snooptag     */
-/*0xb0*/u64 icache_upper;       /* I-cache upper-tag    */
-/*0xb8*/u64 icache_lower;       /* I-cache lower-tag    */
-
-        /* E-cache state */
-/*0xc0*/u64 ecache_data[4];     /* 32 bytes from staging registers */
-/*0xe0*/u64 ecache_index;       /* E-cache index        */
-/*0xe8*/u64 ecache_tag;         /* E-cache tag/state    */
-
-/*0xf0*/u64 __pad[32 - 30];
-};
-#define CHAFSR_INVALID          ((u64)-1L)
-
 /* This table is ordered in priority of errors and matches the
  * AFAR overwrite policy as well.
  */
@@ -758,10 +719,6 @@ static struct afsr_error_table __jalapeno_error_table[] = {
 static struct afsr_error_table *cheetah_error_table;
 static unsigned long cheetah_afsr_errors;
 
-/* This is allocated at boot time based upon the largest hardware
- * cpu ID in the system.  We allocate two entries per cpu, one for
- * TL==0 logging and one for TL >= 1 logging.
- */
 struct cheetah_err_info *cheetah_error_log;
 
 static inline struct cheetah_err_info *cheetah_get_error_log(unsigned long afsr)
@@ -2102,7 +2059,7 @@ void do_div0(struct pt_regs *regs)
         force_sig_info(SIGFPE, &info, current);
 }
 
-void instruction_dump (unsigned int *pc)
+static void instruction_dump(unsigned int *pc)
 {
         int i;
 
@@ -2115,7 +2072,7 @@ void instruction_dump (unsigned int *pc)
         printk("\n");
 }
 
-static void user_instruction_dump (unsigned int __user *pc)
+static void user_instruction_dump(unsigned int __user *pc)
 {
         int i;
         unsigned int buf[9];
diff --git a/arch/sparc64/mm/init.c b/arch/sparc64/mm/init.c
index 466fd6cffac9..f37078d96407 100644
--- a/arch/sparc64/mm/init.c
+++ b/arch/sparc64/mm/init.c
@@ -46,6 +46,7 @@
 #include <asm/prom.h>
 #include <asm/sstate.h>
 #include <asm/mdesc.h>
+#include <asm/cpudata.h>
 
 #define MAX_PHYS_ADDRESS        (1UL << 42UL)
 #define KPTE_BITMAP_CHUNK_SZ    (256UL * 1024UL * 1024UL)
@@ -1273,10 +1274,6 @@ void __cpuinit sun4v_ktsb_register(void)
 
 /* paging_init() sets up the page tables */
 
-extern void cheetah_ecache_flush_init(void);
-extern void sun4v_patch_tlb_handlers(void);
-
-extern void cpu_probe(void);
 extern void central_probe(void);
 
 static unsigned long last_valid_pfn;
diff --git a/arch/sparc64/mm/tlb.c b/arch/sparc64/mm/tlb.c
index 3f10fc921b00..ae24919cba7c 100644
--- a/arch/sparc64/mm/tlb.c
+++ b/arch/sparc64/mm/tlb.c
@@ -23,9 +23,7 @@ DEFINE_PER_CPU(struct mmu_gather, mmu_gathers) = { 0, };
 
 void flush_tlb_pending(void)
 {
-        struct mmu_gather *mp = &__get_cpu_var(mmu_gathers);
-
-        preempt_disable();
+        struct mmu_gather *mp = &get_cpu_var(mmu_gathers);
 
         if (mp->tlb_nr) {
                 flush_tsb_user(mp);
@@ -42,7 +40,7 @@ void flush_tlb_pending(void)
                 mp->tlb_nr = 0;
         }
 
-        preempt_enable();
+        put_cpu_var(mmu_gathers);
 }
 
 void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, pte_t *ptep, pte_t orig)
diff --git a/arch/um/drivers/net_kern.c b/arch/um/drivers/net_kern.c
index 1e8f41a99511..1d43bdfc20c4 100644
--- a/arch/um/drivers/net_kern.c
+++ b/arch/um/drivers/net_kern.c
@@ -256,11 +256,7 @@ static struct net_device_stats *uml_net_get_stats(struct net_device *dev)
 
 static void uml_net_set_multicast_list(struct net_device *dev)
 {
-        if (dev->flags & IFF_PROMISC)
-                return;
-        else if (dev->mc_count)
-                dev->flags |= IFF_ALLMULTI;
-        else dev->flags &= ~IFF_ALLMULTI;
+        return;
 }
 
 static void uml_net_tx_timeout(struct net_device *dev)
diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index 45d79ea890ae..5fed98ca0e1f 100644
--- a/arch/x86/kernel/alternative.c
+++ b/arch/x86/kernel/alternative.c
@@ -65,7 +65,8 @@ __setup("noreplace-paravirt", setup_noreplace_paravirt);
    get them easily into strings. */
 asm("\t.section .rodata, \"a\"\nintelnops: "
         GENERIC_NOP1 GENERIC_NOP2 GENERIC_NOP3 GENERIC_NOP4 GENERIC_NOP5 GENERIC_NOP6
-        GENERIC_NOP7 GENERIC_NOP8);
+        GENERIC_NOP7 GENERIC_NOP8
+    "\t.previous");
 extern const unsigned char intelnops[];
 static const unsigned char *const intel_nops[ASM_NOP_MAX+1] = {
         NULL,
@@ -83,7 +84,8 @@ static const unsigned char *const intel_nops[ASM_NOP_MAX+1] = {
 #ifdef K8_NOP1
 asm("\t.section .rodata, \"a\"\nk8nops: "
         K8_NOP1 K8_NOP2 K8_NOP3 K8_NOP4 K8_NOP5 K8_NOP6
-        K8_NOP7 K8_NOP8);
+        K8_NOP7 K8_NOP8
+    "\t.previous");
 extern const unsigned char k8nops[];
 static const unsigned char *const k8_nops[ASM_NOP_MAX+1] = {
         NULL,
@@ -101,7 +103,8 @@ static const unsigned char *const k8_nops[ASM_NOP_MAX+1] = {
 #ifdef K7_NOP1
 asm("\t.section .rodata, \"a\"\nk7nops: "
         K7_NOP1 K7_NOP2 K7_NOP3 K7_NOP4 K7_NOP5 K7_NOP6
-        K7_NOP7 K7_NOP8);
+        K7_NOP7 K7_NOP8
+    "\t.previous");
 extern const unsigned char k7nops[];
 static const unsigned char *const k7_nops[ASM_NOP_MAX+1] = {
         NULL,
@@ -119,7 +122,8 @@ static const unsigned char *const k7_nops[ASM_NOP_MAX+1] = {
 #ifdef P6_NOP1
 asm("\t.section .rodata, \"a\"\np6nops: "
         P6_NOP1 P6_NOP2 P6_NOP3 P6_NOP4 P6_NOP5 P6_NOP6
-        P6_NOP7 P6_NOP8);
+        P6_NOP7 P6_NOP8
+    "\t.previous");
 extern const unsigned char p6nops[];
 static const unsigned char *const p6_nops[ASM_NOP_MAX+1] = {
         NULL,
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index 027e5c003b16..170d2f5523b2 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -143,14 +143,6 @@ static void __init check_config(void)
 #endif
 
 /*
- * If we configured ourselves for a TSC, we'd better have one!
- */
-#ifdef CONFIG_X86_TSC
-        if (!cpu_has_tsc)
-                panic("Kernel compiled for Pentium+, requires TSC feature!");
-#endif
-
-/*
  * If we were told we had a good local APIC, check for buggy Pentia,
  * i.e. all B steppings and the C2 stepping of P54C when using their
  * integrated APIC (see 11AP erratum in "Pentium Processor
diff --git a/arch/x86/kernel/cpu/cpufreq/speedstep-smi.c b/arch/x86/kernel/cpu/cpufreq/speedstep-smi.c
index f2b5a621d27b..8a85c93bd62a 100644
--- a/arch/x86/kernel/cpu/cpufreq/speedstep-smi.c
+++ b/arch/x86/kernel/cpu/cpufreq/speedstep-smi.c
@@ -63,7 +63,7 @@ static struct cpufreq_frequency_table speedstep_freqs[] = {
  */
 static int speedstep_smi_ownership (void)
 {
-        u32 command, result, magic;
+        u32 command, result, magic, dummy;
         u32 function = GET_SPEEDSTEP_OWNER;
         unsigned char magic_data[] = "Copyright (c) 1999 Intel Corporation";
 
@@ -73,8 +73,11 @@ static int speedstep_smi_ownership (void)
         dprintk("trying to obtain ownership with command %x at port %x\n", command, smi_port);
 
         __asm__ __volatile__(
+                "push %%ebp\n"
                 "out %%al, (%%dx)\n"
-                : "=D" (result)
+                "pop %%ebp\n"
+                : "=D" (result), "=a" (dummy), "=b" (dummy), "=c" (dummy), "=d" (dummy),
+                        "=S" (dummy)
                 : "a" (command), "b" (function), "c" (0), "d" (smi_port),
                         "D" (0), "S" (magic)
                 : "memory"
@@ -96,7 +99,7 @@ static int speedstep_smi_ownership (void)
  */
 static int speedstep_smi_get_freqs (unsigned int *low, unsigned int *high)
 {
-        u32 command, result = 0, edi, high_mhz, low_mhz;
+        u32 command, result = 0, edi, high_mhz, low_mhz, dummy;
         u32 state=0;
         u32 function = GET_SPEEDSTEP_FREQS;
 
@@ -109,10 +112,12 @@ static int speedstep_smi_get_freqs (unsigned int *low, unsigned int *high)
 
         dprintk("trying to determine frequencies with command %x at port %x\n", command, smi_port);
 
-        __asm__ __volatile__("movl $0, %%edi\n"
+        __asm__ __volatile__(
+                "push %%ebp\n"
                 "out %%al, (%%dx)\n"
-                : "=a" (result), "=b" (high_mhz), "=c" (low_mhz), "=d" (state), "=D" (edi)
-                : "a" (command), "b" (function), "c" (state), "d" (smi_port), "S" (0)
+                "pop %%ebp"
+                : "=a" (result), "=b" (high_mhz), "=c" (low_mhz), "=d" (state), "=D" (edi), "=S" (dummy)
+                : "a" (command), "b" (function), "c" (state), "d" (smi_port), "S" (0), "D" (0)
         );
 
         dprintk("result %x, low_freq %u, high_freq %u\n", result, low_mhz, high_mhz);
@@ -135,16 +140,18 @@ static int speedstep_smi_get_freqs (unsigned int *low, unsigned int *high)
 static int speedstep_get_state (void)
 {
         u32 function=GET_SPEEDSTEP_STATE;
-        u32 result, state, edi, command;
+        u32 result, state, edi, command, dummy;
 
         command = (smi_sig & 0xffffff00) | (smi_cmd & 0xff);
 
         dprintk("trying to determine current setting with command %x at port %x\n", command, smi_port);
 
-        __asm__ __volatile__("movl $0, %%edi\n"
+        __asm__ __volatile__(
+                "push %%ebp\n"
                 "out %%al, (%%dx)\n"
-                : "=a" (result), "=b" (state), "=D" (edi)
-                : "a" (command), "b" (function), "c" (0), "d" (smi_port), "S" (0)
+                "pop %%ebp\n"
+                : "=a" (result), "=b" (state), "=D" (edi), "=c" (dummy), "=d" (dummy), "=S" (dummy)
+                : "a" (command), "b" (function), "c" (0), "d" (smi_port), "S" (0), "D" (0)
         );
 
         dprintk("state is %x, result is %x\n", state, result);
@@ -160,7 +167,7 @@ static int speedstep_get_state (void)
  */
 static void speedstep_set_state (unsigned int state)
 {
-        unsigned int result = 0, command, new_state;
+        unsigned int result = 0, command, new_state, dummy;
         unsigned long flags;
         unsigned int function=SET_SPEEDSTEP_STATE;
         unsigned int retry = 0;
@@ -182,10 +189,12 @@ static void speedstep_set_state (unsigned int state)
                 }
                 retry++;
                 __asm__ __volatile__(
-                        "movl $0, %%edi\n"
+                        "push %%ebp\n"
                         "out %%al, (%%dx)\n"
-                        : "=b" (new_state), "=D" (result)
-                        : "a" (command), "b" (function), "c" (state), "d" (smi_port), "S" (0)
+                        "pop %%ebp"
+                        : "=b" (new_state), "=D" (result), "=c" (dummy), "=a" (dummy),
+                                "=d" (dummy), "=S" (dummy)
+                        : "a" (command), "b" (function), "c" (state), "d" (smi_port), "S" (0), "D" (0)
                         );
         } while ((new_state != state) && (retry <= SMI_TRIES));
 
@@ -195,7 +204,7 @@ static void speedstep_set_state (unsigned int state)
         if (new_state == state) {
                 dprintk("change to %u MHz succeeded after %u tries with result %u\n", (speedstep_freqs[new_state].frequency / 1000), retry, result);
         } else {
-                printk(KERN_ERR "cpufreq: change failed with new_state %u and result %u\n", new_state, result);
+                printk(KERN_ERR "cpufreq: change to state %u failed with new_state %u and result %u\n", state, new_state, result);
         }
 
         return;
diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c
index 103d61a59b19..3e18db4cefee 100644
--- a/arch/x86/kernel/cpu/mtrr/generic.c
+++ b/arch/x86/kernel/cpu/mtrr/generic.c
@@ -176,12 +176,13 @@ static inline void k8_enable_fixed_iorrs(void)
 }
 
 /**
- * Checks and updates an fixed-range MTRR if it differs from the value it
- * should have. If K8 extentions are wanted, update the K8 SYSCFG MSR also.
- * see AMD publication no. 24593, chapter 7.8.1, page 233 for more information
- * \param msr MSR address of the MTTR which should be checked and updated
- * \param changed pointer which indicates whether the MTRR needed to be changed
- * \param msrwords pointer to the MSR values which the MSR should have
+ * set_fixed_range - checks & updates a fixed-range MTRR if it differs from the value it should have
+ * @msr: MSR address of the MTTR which should be checked and updated
+ * @changed: pointer which indicates whether the MTRR needed to be changed
+ * @msrwords: pointer to the MSR values which the MSR should have
+ *
+ * If K8 extentions are wanted, update the K8 SYSCFG MSR also.
+ * See AMD publication no. 24593, chapter 7.8.1, page 233 for more information.
  */
 static void set_fixed_range(int msr, bool *changed, unsigned int *msrwords)
 {
@@ -199,12 +200,15 @@ static void set_fixed_range(int msr, bool *changed, unsigned int *msrwords)
         }
 }
 
+/**
+ * generic_get_free_region - Get a free MTRR.
+ * @base: The starting (base) address of the region.
+ * @size: The size (in bytes) of the region.
+ * @replace_reg: mtrr index to be replaced; set to invalid value if none.
+ *
+ * Returns: The index of the region on success, else negative on error.
+ */
 int generic_get_free_region(unsigned long base, unsigned long size, int replace_reg)
-/*  [SUMMARY] Get a free MTRR.
-    <base> The starting (base) address of the region.
-    <size> The size (in bytes) of the region.
-    [RETURNS] The index of the region on success, else -1 on error.
-*/
 {
         int i, max;
         mtrr_type ltype;
@@ -249,8 +253,8 @@ static void generic_get_mtrr(unsigned int reg, unsigned long *base,
 }
 
 /**
- * Checks and updates the fixed-range MTRRs if they differ from the saved set
- * \param frs pointer to fixed-range MTRR values, saved by get_fixed_ranges()
+ * set_fixed_ranges - checks & updates the fixed-range MTRRs if they differ from the saved set
+ * @frs: pointer to fixed-range MTRR values, saved by get_fixed_ranges()
  */
 static int set_fixed_ranges(mtrr_type * frs)
 {
@@ -294,13 +298,13 @@ static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr)
 
 static u32 deftype_lo, deftype_hi;
 
+/**
+ * set_mtrr_state - Set the MTRR state for this CPU.
+ *
+ * NOTE: The CPU must already be in a safe state for MTRR changes.
+ * RETURNS: 0 if no changes made, else a mask indicating what was changed.
+ */
 static unsigned long set_mtrr_state(void)
-/*  [SUMMARY] Set the MTRR state for this CPU.
-    <state> The MTRR state information to read.
-    <ctxt> Some relevant CPU context.
-    [NOTE] The CPU must already be in a safe state for MTRR changes.
-    [RETURNS] 0 if no changes made, else a mask indication what was changed.
-*/
 {
         unsigned int i;
         unsigned long change_mask = 0;
diff --git a/arch/x86/kernel/cpu/perfctr-watchdog.c b/arch/x86/kernel/cpu/perfctr-watchdog.c
index 9b838324b818..b943e10ad814 100644
--- a/arch/x86/kernel/cpu/perfctr-watchdog.c
+++ b/arch/x86/kernel/cpu/perfctr-watchdog.c
@@ -652,9 +652,6 @@ static void probe_nmi_watchdog(void)
                         wd_ops = &p6_wd_ops;
                         break;
                 case 15:
-                        if (boot_cpu_data.x86_model > 0x4)
-                                return;
-
                         wd_ops = &p4_wd_ops;
                         break;
                 default:
@@ -670,8 +667,10 @@ int lapic_watchdog_init(unsigned nmi_hz)
 {
         if (!wd_ops) {
                 probe_nmi_watchdog();
-                if (!wd_ops)
+                if (!wd_ops) {
+                        printk(KERN_INFO "NMI watchdog: CPU not supported\n");
                         return -1;
+                }
 
                 if (!wd_ops->reserve()) {
                         printk(KERN_ERR
diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c
index 235fd6c77504..36652ea1a265 100644
--- a/arch/x86/kernel/hpet.c
+++ b/arch/x86/kernel/hpet.c
@@ -133,13 +133,16 @@ static void hpet_reserve_platform_timers(unsigned long id)
 #ifdef CONFIG_HPET_EMULATE_RTC
         hpet_reserve_timer(&hd, 1);
 #endif
+
         hd.hd_irq[0] = HPET_LEGACY_8254;
         hd.hd_irq[1] = HPET_LEGACY_RTC;
 
-       for (i = 2; i < nrtimers; timer++, i++)
-               hd.hd_irq[i] = (timer->hpet_config & Tn_INT_ROUTE_CNF_MASK) >>
-                       Tn_INT_ROUTE_CNF_SHIFT;
+        for (i = 2; i < nrtimers; timer++, i++)
+                hd.hd_irq[i] = (timer->hpet_config & Tn_INT_ROUTE_CNF_MASK) >>
+                        Tn_INT_ROUTE_CNF_SHIFT;
+
         hpet_alloc(&hd);
+
 }
 #else
 static void hpet_reserve_platform_timers(unsigned long id) { }
diff --git a/arch/x86/kernel/io_delay.c b/arch/x86/kernel/io_delay.c
index c706a3061553..5921e5f0a640 100644
--- a/arch/x86/kernel/io_delay.c
+++ b/arch/x86/kernel/io_delay.c
@@ -78,6 +78,14 @@ static struct dmi_system_id __initdata io_delay_0xed_port_dmi_table[] = {
         },
         {
                 .callback       = dmi_io_delay_0xed_port,
+                .ident          = "HP Pavilion dv6000",
+                .matches        = {
+                        DMI_MATCH(DMI_BOARD_VENDOR, "Quanta"),
+                        DMI_MATCH(DMI_BOARD_NAME, "30B8")
+                }
+        },
+        {
+                .callback       = dmi_io_delay_0xed_port,
                 .ident          = "HP Pavilion tx1000",
                 .matches        = {
                         DMI_MATCH(DMI_BOARD_VENDOR, "Quanta"),
diff --git a/arch/x86/kernel/machine_kexec_64.c b/arch/x86/kernel/machine_kexec_64.c
index 236d2f8f7ddc..576a03db4511 100644
--- a/arch/x86/kernel/machine_kexec_64.c
+++ b/arch/x86/kernel/machine_kexec_64.c
@@ -233,6 +233,7 @@ NORET_TYPE void machine_kexec(struct kimage *image)
 
 void arch_crash_save_vmcoreinfo(void)
 {
+        VMCOREINFO_SYMBOL(phys_base);
         VMCOREINFO_SYMBOL(init_level4_pgt);
 
 #ifdef CONFIG_NUMA
diff --git a/arch/x86/kernel/mfgpt_32.c b/arch/x86/kernel/mfgpt_32.c
index 027fc067b399..b402c0f3f192 100644
--- a/arch/x86/kernel/mfgpt_32.c
+++ b/arch/x86/kernel/mfgpt_32.c
@@ -30,6 +30,7 @@
 
 #include <linux/kernel.h>
 #include <linux/interrupt.h>
+#include <linux/module.h>
 #include <asm/geode.h>
 
 static struct mfgpt_timer_t {
diff --git a/arch/x86/kernel/pci-gart_64.c b/arch/x86/kernel/pci-gart_64.c
index faf3229f8fb3..700e4647dd30 100644
--- a/arch/x86/kernel/pci-gart_64.c
+++ b/arch/x86/kernel/pci-gart_64.c
@@ -615,8 +615,8 @@ static __init int init_k8_gatt(struct agp_kern_info *info)
 
  nommu:
         /* Should not happen anymore */
-        printk(KERN_ERR "PCI-DMA: More than 4GB of RAM and no IOMMU\n"
-               KERN_ERR "PCI-DMA: 32bit PCI IO may malfunction.\n");
+        printk(KERN_WARNING "PCI-DMA: More than 4GB of RAM and no IOMMU\n"
+               KERN_WARNING "falling back to iommu=soft.\n");
         return -1;
 }
 
@@ -692,9 +692,9 @@ void __init gart_iommu_init(void)
             !gart_iommu_aperture ||
             (no_agp && init_k8_gatt(&info) < 0)) {
                 if (end_pfn > MAX_DMA32_PFN) {
-                        printk(KERN_ERR "WARNING more than 4GB of memory "
-                                        "but GART IOMMU not available.\n"
-                               KERN_ERR "WARNING 32bit PCI may malfunction.\n");
+                        printk(KERN_WARNING "More than 4GB of memory "
+                                          "but GART IOMMU not available.\n"
+                               KERN_WARNING "falling back to iommu=soft.\n");
                 }
                 return;
         }
diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c
index be3c7a299f02..43930e73f657 100644
--- a/arch/x86/kernel/process_32.c
+++ b/arch/x86/kernel/process_32.c
@@ -82,7 +82,6 @@ unsigned long thread_saved_pc(struct task_struct *tsk)
  */
 void (*pm_idle)(void);
 EXPORT_SYMBOL(pm_idle);
-static DEFINE_PER_CPU(unsigned int, cpu_idle_state);
 
 void disable_hlt(void)
 {
@@ -190,9 +189,6 @@ void cpu_idle(void)
                 while (!need_resched()) {
                         void (*idle)(void);
 
-                        if (__get_cpu_var(cpu_idle_state))
-                                __get_cpu_var(cpu_idle_state) = 0;
-
                         check_pgt_cache();
                         rmb();
                         idle = pm_idle;
@@ -220,40 +216,19 @@ static void do_nothing(void *unused)
 {
 }
 
+/*
+ * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
+ * pm_idle and update to new pm_idle value. Required while changing pm_idle
+ * handler on SMP systems.
+ *
+ * Caller must have changed pm_idle to the new value before the call. Old
+ * pm_idle value will not be used by any CPU after the return of this function.
+ */
 void cpu_idle_wait(void)
 {
-        unsigned int cpu, this_cpu = get_cpu();
-        cpumask_t map, tmp = current->cpus_allowed;
-
-        set_cpus_allowed(current, cpumask_of_cpu(this_cpu));
-        put_cpu();
-
-        cpus_clear(map);
-        for_each_online_cpu(cpu) {
-                per_cpu(cpu_idle_state, cpu) = 1;
-                cpu_set(cpu, map);
-        }
-
-        __get_cpu_var(cpu_idle_state) = 0;
-
-        wmb();
-        do {
-                ssleep(1);
-                for_each_online_cpu(cpu) {
-                        if (cpu_isset(cpu, map) && !per_cpu(cpu_idle_state, cpu))
-                                cpu_clear(cpu, map);
-                }
-                cpus_and(map, map, cpu_online_map);
-                /*
-                 * We waited 1 sec, if a CPU still did not call idle
-                 * it may be because it is in idle and not waking up
-                 * because it has nothing to do.
-                 * Give all the remaining CPUS a kick.
-                 */
-                smp_call_function_mask(map, do_nothing, NULL, 0);
-        } while (!cpus_empty(map));
-
-        set_cpus_allowed(current, tmp);
+        smp_mb();
+        /* kick all the CPUs so that they exit out of pm_idle */
+        smp_call_function(do_nothing, NULL, 0, 1);
 }
 EXPORT_SYMBOL_GPL(cpu_idle_wait);
 
diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index 3baf9b9f4c87..46c4c546b499 100644
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -63,7 +63,6 @@ EXPORT_SYMBOL(boot_option_idle_override);
  */
 void (*pm_idle)(void);
 EXPORT_SYMBOL(pm_idle);
-static DEFINE_PER_CPU(unsigned int, cpu_idle_state);
 
 static ATOMIC_NOTIFIER_HEAD(idle_notifier);
 
@@ -173,9 +172,6 @@ void cpu_idle(void)
                 while (!need_resched()) {
                         void (*idle)(void);
 
-                        if (__get_cpu_var(cpu_idle_state))
-                                __get_cpu_var(cpu_idle_state) = 0;
-
                         rmb();
                         idle = pm_idle;
                         if (!idle)
@@ -207,40 +203,19 @@ static void do_nothing(void *unused)
 {
 }
 
+/*
+ * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
+ * pm_idle and update to new pm_idle value. Required while changing pm_idle
+ * handler on SMP systems.
+ *
+ * Caller must have changed pm_idle to the new value before the call. Old
+ * pm_idle value will not be used by any CPU after the return of this function.
+ */
 void cpu_idle_wait(void)
 {
-        unsigned int cpu, this_cpu = get_cpu();
-        cpumask_t map, tmp = current->cpus_allowed;
-
-        set_cpus_allowed(current, cpumask_of_cpu(this_cpu));
-        put_cpu();
-
-        cpus_clear(map);
-        for_each_online_cpu(cpu) {
-                per_cpu(cpu_idle_state, cpu) = 1;
-                cpu_set(cpu, map);
-        }
-
-        __get_cpu_var(cpu_idle_state) = 0;
-
-        wmb();
-        do {
-                ssleep(1);
-                for_each_online_cpu(cpu) {
-                        if (cpu_isset(cpu, map) && !per_cpu(cpu_idle_state, cpu))
-                                cpu_clear(cpu, map);
-                }
-                cpus_and(map, map, cpu_online_map);
-                /*
-                 * We waited 1 sec, if a CPU still did not call idle
-                 * it may be because it is in idle and not waking up
-                 * because it has nothing to do.
-                 * Give all the remaining CPUS a kick.
-                 */
-                smp_call_function_mask(map, do_nothing, 0, 0);
-        } while (!cpus_empty(map));
-
-        set_cpus_allowed(current, tmp);
+        smp_mb();
+        /* kick all the CPUs so that they exit out of pm_idle */
+        smp_call_function(do_nothing, NULL, 0, 1);
 }
 EXPORT_SYMBOL_GPL(cpu_idle_wait);
 
diff --git a/arch/x86/kernel/ptrace.c b/arch/x86/kernel/ptrace.c
index d5904eef1d31..eb92ccbb3502 100644
--- a/arch/x86/kernel/ptrace.c
+++ b/arch/x86/kernel/ptrace.c
@@ -600,21 +600,6 @@ static int ptrace_bts_read_record(struct task_struct *child,
         return sizeof(ret);
 }
 
-static int ptrace_bts_write_record(struct task_struct *child,
-                                   const struct bts_struct *in)
-{
-        int retval;
-
-        if (!child->thread.ds_area_msr)
-                return -ENXIO;
-
-        retval = ds_write_bts((void *)child->thread.ds_area_msr, in);
-        if (retval)
-                return retval;
-
-        return sizeof(*in);
-}
-
 static int ptrace_bts_clear(struct task_struct *child)
 {
         if (!child->thread.ds_area_msr)
@@ -657,75 +642,6 @@ static int ptrace_bts_drain(struct task_struct *child,
         return end;
 }
 
-static int ptrace_bts_realloc(struct task_struct *child,
-                              int size, int reduce_size)
-{
-        unsigned long rlim, vm;
-        int ret, old_size;
-
-        if (size < 0)
-                return -EINVAL;
-
-        old_size = ds_get_bts_size((void *)child->thread.ds_area_msr);
-        if (old_size < 0)
-                return old_size;
-
-        ret = ds_free((void **)&child->thread.ds_area_msr);
-        if (ret < 0)
-                goto out;
-
-        size >>= PAGE_SHIFT;
-        old_size >>= PAGE_SHIFT;
-
-        current->mm->total_vm  -= old_size;
-        current->mm->locked_vm -= old_size;
-
-        if (size == 0)
-                goto out;
-
-        rlim = current->signal->rlim[RLIMIT_AS].rlim_cur >> PAGE_SHIFT;
-        vm = current->mm->total_vm  + size;
-        if (rlim < vm) {
-                ret = -ENOMEM;
-
-                if (!reduce_size)
-                        goto out;
-
-                size = rlim - current->mm->total_vm;
-                if (size <= 0)
-                        goto out;
-        }
-
-        rlim = current->signal->rlim[RLIMIT_MEMLOCK].rlim_cur >> PAGE_SHIFT;
-        vm = current->mm->locked_vm  + size;
-        if (rlim < vm) {
-                ret = -ENOMEM;
-
-                if (!reduce_size)
-                        goto out;
-
-                size = rlim - current->mm->locked_vm;
-                if (size <= 0)
-                        goto out;
-        }
-
-        ret = ds_allocate((void **)&child->thread.ds_area_msr,
-                          size << PAGE_SHIFT);
-        if (ret < 0)
-                goto out;
-
-        current->mm->total_vm  += size;
-        current->mm->locked_vm += size;
-
-out:
-        if (child->thread.ds_area_msr)
-                set_tsk_thread_flag(child, TIF_DS_AREA_MSR);
-        else
-                clear_tsk_thread_flag(child, TIF_DS_AREA_MSR);
-
-        return ret;
-}
-
 static int ptrace_bts_config(struct task_struct *child,
                              long cfg_size,
                              const struct ptrace_bts_config __user *ucfg)
@@ -828,6 +744,91 @@ static int ptrace_bts_status(struct task_struct *child,
         return sizeof(cfg);
 }
 
+
+static int ptrace_bts_write_record(struct task_struct *child,
+                                   const struct bts_struct *in)
+{
+        int retval;
+
+        if (!child->thread.ds_area_msr)
+                return -ENXIO;
+
+        retval = ds_write_bts((void *)child->thread.ds_area_msr, in);
+        if (retval)
+                return retval;
+
+        return sizeof(*in);
+}
+
+static int ptrace_bts_realloc(struct task_struct *child,
+                              int size, int reduce_size)
+{
+        unsigned long rlim, vm;
+        int ret, old_size;
+
+        if (size < 0)
+                return -EINVAL;
+
+        old_size = ds_get_bts_size((void *)child->thread.ds_area_msr);
+        if (old_size < 0)
+                return old_size;
+
+        ret = ds_free((void **)&child->thread.ds_area_msr);
+        if (ret < 0)
+                goto out;
+
+        size >>= PAGE_SHIFT;
+        old_size >>= PAGE_SHIFT;
+
+        current->mm->total_vm  -= old_size;
+        current->mm->locked_vm -= old_size;
+
+        if (size == 0)
+                goto out;
+
+        rlim = current->signal->rlim[RLIMIT_AS].rlim_cur >> PAGE_SHIFT;
+        vm = current->mm->total_vm  + size;
+        if (rlim < vm) {
+                ret = -ENOMEM;
+
+                if (!reduce_size)
+                        goto out;
+
+                size = rlim - current->mm->total_vm;
+                if (size <= 0)
+                        goto out;
+        }
+
+        rlim = current->signal->rlim[RLIMIT_MEMLOCK].rlim_cur >> PAGE_SHIFT;
+        vm = current->mm->locked_vm  + size;
+        if (rlim < vm) {
+                ret = -ENOMEM;
+
+                if (!reduce_size)
+                        goto out;
+
+                size = rlim - current->mm->locked_vm;
+                if (size <= 0)
+                        goto out;
+        }
+
+        ret = ds_allocate((void **)&child->thread.ds_area_msr,
+                          size << PAGE_SHIFT);
+        if (ret < 0)
+                goto out;
+
+        current->mm->total_vm  += size;
+        current->mm->locked_vm += size;
+
+out:
+        if (child->thread.ds_area_msr)
+                set_tsk_thread_flag(child, TIF_DS_AREA_MSR);
+        else
+                clear_tsk_thread_flag(child, TIF_DS_AREA_MSR);
+
+        return ret;
+}
+
 void ptrace_bts_take_timestamp(struct task_struct *tsk,
                                enum bts_qualifier qualifier)
 {
diff --git a/arch/x86/kernel/setup_32.c b/arch/x86/kernel/setup_32.c
index a1d7071a51c9..2b3e5d45176b 100644
--- a/arch/x86/kernel/setup_32.c
+++ b/arch/x86/kernel/setup_32.c
@@ -406,8 +406,6 @@ static unsigned long __init setup_memory(void)
          */
         min_low_pfn = PFN_UP(init_pg_tables_end);
 
-        find_max_pfn();
-
         max_low_pfn = find_max_low_pfn();
 
 #ifdef CONFIG_HIGHMEM
@@ -764,12 +762,13 @@ void __init setup_arch(char **cmdline_p)
         if (efi_enabled)
                 efi_init();
 
-        max_low_pfn = setup_memory();
-
         /* update e820 for memory not covered by WB MTRRs */
+        find_max_pfn();
         mtrr_bp_init();
         if (mtrr_trim_uncached_memory(max_pfn))
-                max_low_pfn = setup_memory();
+                find_max_pfn();
+
+        max_low_pfn = setup_memory();
 
 #ifdef CONFIG_VMI
         /*
diff --git a/arch/x86/kernel/setup_64.c b/arch/x86/kernel/setup_64.c
index 7637dc91c79b..f4f7ecfb898c 100644
--- a/arch/x86/kernel/setup_64.c
+++ b/arch/x86/kernel/setup_64.c
@@ -801,7 +801,7 @@ static void __cpuinit srat_detect_node(void)
         /* Don't do the funky fallback heuristics the AMD version employs
            for now. */
         node = apicid_to_node[apicid];
-        if (node == NUMA_NO_NODE)
+        if (node == NUMA_NO_NODE || !node_online(node))
                 node = first_node(node_online_map);
         numa_set_node(cpu, node);
 
diff --git a/arch/x86/kernel/step.c b/arch/x86/kernel/step.c
index 9d406cdc847f..071ff4798236 100644
--- a/arch/x86/kernel/step.c
+++ b/arch/x86/kernel/step.c
@@ -140,6 +140,9 @@ static int enable_single_step(struct task_struct *child)
  */
 static void write_debugctlmsr(struct task_struct *child, unsigned long val)
 {
+        if (child->thread.debugctlmsr == val)
+                return;
+
         child->thread.debugctlmsr = val;
 
         if (child != current)
@@ -165,11 +168,11 @@ static void enable_step(struct task_struct *child, bool block)
                 write_debugctlmsr(child,
                                   child->thread.debugctlmsr | DEBUGCTLMSR_BTF);
         } else {
-            write_debugctlmsr(child,
-                              child->thread.debugctlmsr & ~DEBUGCTLMSR_BTF);
+                write_debugctlmsr(child,
+                                  child->thread.debugctlmsr & ~DEBUGCTLMSR_BTF);
 
-            if (!child->thread.debugctlmsr)
-                    clear_tsk_thread_flag(child, TIF_DEBUGCTLMSR);
+                if (!child->thread.debugctlmsr)
+                        clear_tsk_thread_flag(child, TIF_DEBUGCTLMSR);
         }
 }
 
diff --git a/arch/x86/kernel/tls.c b/arch/x86/kernel/tls.c
index 022bcaa3b42e..ab6bf375a307 100644
--- a/arch/x86/kernel/tls.c
+++ b/arch/x86/kernel/tls.c
@@ -92,7 +92,7 @@ int do_set_thread_area(struct task_struct *p, int idx,
 asmlinkage int sys_set_thread_area(struct user_desc __user *u_info)
 {
         int ret = do_set_thread_area(current, -1, u_info, 1);
-        prevent_tail_call(ret);
+        asmlinkage_protect(1, ret, u_info);
         return ret;
 }
 
@@ -142,7 +142,7 @@ int do_get_thread_area(struct task_struct *p, int idx,
 asmlinkage int sys_get_thread_area(struct user_desc __user *u_info)
 {
         int ret = do_get_thread_area(current, -1, u_info);
-        prevent_tail_call(ret);
+        asmlinkage_protect(1, ret, u_info);
         return ret;
 }
 
diff --git a/arch/x86/kernel/tsc_32.c b/arch/x86/kernel/tsc_32.c
index f14cfd9d1f94..c2241e04ea5f 100644
--- a/arch/x86/kernel/tsc_32.c
+++ b/arch/x86/kernel/tsc_32.c
@@ -256,9 +256,7 @@ time_cpufreq_notifier(struct notifier_block *nb, unsigned long val, void *data)
                                                 ref_freq, freq->new);
                         if (!(freq->flags & CPUFREQ_CONST_LOOPS)) {
                                 tsc_khz = cpu_khz;
-                                preempt_disable();
-                                set_cyc2ns_scale(cpu_khz, smp_processor_id());
-                                preempt_enable();
+                                set_cyc2ns_scale(cpu_khz, freq->cpu);
                                 /*
                                  * TSC based sched_clock turns
                                  * to junk w/ cpufreq
diff --git a/arch/x86/kernel/tsc_64.c b/arch/x86/kernel/tsc_64.c
index 947554ddabb6..d3bebaaad842 100644
--- a/arch/x86/kernel/tsc_64.c
+++ b/arch/x86/kernel/tsc_64.c
@@ -148,9 +148,7 @@ static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
                         mark_tsc_unstable("cpufreq changes");
         }
 
-        preempt_disable();
-        set_cyc2ns_scale(tsc_khz_ref, smp_processor_id());
-        preempt_enable();
+        set_cyc2ns_scale(tsc_khz_ref, freq->cpu);
 
         return 0;
 }
diff --git a/arch/x86/lguest/boot.c b/arch/x86/lguest/boot.c
index a104c532ff70..3335b4595efd 100644
--- a/arch/x86/lguest/boot.c
+++ b/arch/x86/lguest/boot.c
@@ -10,21 +10,19 @@
  * (such as the example in Documentation/lguest/lguest.c) is called the
  * Launcher.
  *
- * Secondly, we only run specially modified Guests, not normal kernels.  When
- * you set CONFIG_LGUEST to 'y' or 'm', this automatically sets
- * CONFIG_LGUEST_GUEST=y, which compiles this file into the kernel so it knows
- * how to be a Guest.  This means that you can use the same kernel you boot
- * normally (ie. as a Host) as a Guest.
+ * Secondly, we only run specially modified Guests, not normal kernels: setting
+ * CONFIG_LGUEST_GUEST to "y" compiles this file into the kernel so it knows
+ * how to be a Guest at boot time.  This means that you can use the same kernel
+ * you boot normally (ie. as a Host) as a Guest.
  *
  * These Guests know that they cannot do privileged operations, such as disable
  * interrupts, and that they have to ask the Host to do such things explicitly.
  * This file consists of all the replacements for such low-level native
  * hardware operations: these special Guest versions call the Host.
  *
- * So how does the kernel know it's a Guest?  The Guest starts at a special
- * entry point marked with a magic string, which sets up a few things then
- * calls here.  We replace the native functions various "paravirt" structures
- * with our Guest versions, then boot like normal. :*/
+ * So how does the kernel know it's a Guest?  We'll see that later, but let's
+ * just say that we end up here where we replace the native functions various
+ * "paravirt" structures with our Guest versions, then boot like normal. :*/
 
 /*
  * Copyright (C) 2006, Rusty Russell <rusty@rustcorp.com.au> IBM Corporation.
@@ -134,7 +132,7 @@ static void async_hcall(unsigned long call, unsigned long arg1,
  * lguest_leave_lazy_mode().
  *
  * So, when we're in lazy mode, we call async_hcall() to store the call for
- * future processing. */
+ * future processing: */
 static void lazy_hcall(unsigned long call,
                        unsigned long arg1,
                        unsigned long arg2,
@@ -147,7 +145,7 @@ static void lazy_hcall(unsigned long call,
 }
 
 /* When lazy mode is turned off reset the per-cpu lazy mode variable and then
- * issue a hypercall to flush any stored calls. */
+ * issue the do-nothing hypercall to flush any stored calls. */
 static void lguest_leave_lazy_mode(void)
 {
         paravirt_leave_lazy(paravirt_get_lazy_mode());
@@ -164,7 +162,7 @@ static void lguest_leave_lazy_mode(void)
  *
  * So instead we keep an "irq_enabled" field inside our "struct lguest_data",
  * which the Guest can update with a single instruction.  The Host knows to
- * check there when it wants to deliver an interrupt.
+ * check there before it tries to deliver an interrupt.
  */
 
 /* save_flags() is expected to return the processor state (ie. "flags").  The
@@ -196,10 +194,15 @@ static void irq_enable(void)
 /*M:003 Note that we don't check for outstanding interrupts when we re-enable
  * them (or when we unmask an interrupt).  This seems to work for the moment,
  * since interrupts are rare and we'll just get the interrupt on the next timer
- * tick, but when we turn on CONFIG_NO_HZ, we should revisit this.  One way
+ * tick, but now we can run with CONFIG_NO_HZ, we should revisit this.  One way
  * would be to put the "irq_enabled" field in a page by itself, and have the
  * Host write-protect it when an interrupt comes in when irqs are disabled.
- * There will then be a page fault as soon as interrupts are re-enabled. :*/
+ * There will then be a page fault as soon as interrupts are re-enabled.
+ *
+ * A better method is to implement soft interrupt disable generally for x86:
+ * instead of disabling interrupts, we set a flag.  If an interrupt does come
+ * in, we then disable them for real.  This is uncommon, so we could simply use
+ * a hypercall for interrupt control and not worry about efficiency. :*/
 
 /*G:034
  * The Interrupt Descriptor Table (IDT).
@@ -212,6 +215,10 @@ static void irq_enable(void)
 static void lguest_write_idt_entry(gate_desc *dt,
                                    int entrynum, const gate_desc *g)
 {
+        /* The gate_desc structure is 8 bytes long: we hand it to the Host in
+         * two 32-bit chunks.  The whole 32-bit kernel used to hand descriptors
+         * around like this; typesafety wasn't a big concern in Linux's early
+         * years. */
         u32 *desc = (u32 *)g;
         /* Keep the local copy up to date. */
         native_write_idt_entry(dt, entrynum, g);
@@ -243,7 +250,8 @@ static void lguest_load_idt(const struct desc_ptr *desc)
  *
  * This is the opposite of the IDT code where we have a LOAD_IDT_ENTRY
  * hypercall and use that repeatedly to load a new IDT.  I don't think it
- * really matters, but wouldn't it be nice if they were the same?
+ * really matters, but wouldn't it be nice if they were the same?  Wouldn't
+ * it be even better if you were the one to send the patch to fix it?
  */
 static void lguest_load_gdt(const struct desc_ptr *desc)
 {
@@ -298,9 +306,9 @@ static void lguest_load_tr_desc(void)
 
 /* The "cpuid" instruction is a way of querying both the CPU identity
  * (manufacturer, model, etc) and its features.  It was introduced before the
- * Pentium in 1993 and keeps getting extended by both Intel and AMD.  As you
- * might imagine, after a decade and a half this treatment, it is now a giant
- * ball of hair.  Its entry in the current Intel manual runs to 28 pages.
+ * Pentium in 1993 and keeps getting extended by both Intel, AMD and others.
+ * As you might imagine, after a decade and a half this treatment, it is now a
+ * giant ball of hair.  Its entry in the current Intel manual runs to 28 pages.
  *
  * This instruction even it has its own Wikipedia entry.  The Wikipedia entry
  * has been translated into 4 languages.  I am not making this up!
@@ -594,17 +602,17 @@ static unsigned long lguest_get_wallclock(void)
         return lguest_data.time.tv_sec;
 }
 
-/* The TSC is a Time Stamp Counter.  The Host tells us what speed it runs at,
- * or 0 if it's unusable as a reliable clock source.  This matches what we want
- * here: if we return 0 from this function, the x86 TSC clock will not register
- * itself. */
+/* The TSC is an Intel thing called the Time Stamp Counter.  The Host tells us
+ * what speed it runs at, or 0 if it's unusable as a reliable clock source.
+ * This matches what we want here: if we return 0 from this function, the x86
+ * TSC clock will give up and not register itself. */
 static unsigned long lguest_cpu_khz(void)
 {
         return lguest_data.tsc_khz;
 }
 
-/* If we can't use the TSC, the kernel falls back to our "lguest_clock", where
- * we read the time value given to us by the Host. */
+/* If we can't use the TSC, the kernel falls back to our lower-priority
+ * "lguest_clock", where we read the time value given to us by the Host. */
 static cycle_t lguest_clock_read(void)
 {
         unsigned long sec, nsec;
@@ -648,12 +656,16 @@ static struct clocksource lguest_clock = {
 static int lguest_clockevent_set_next_event(unsigned long delta,
                                            struct clock_event_device *evt)
 {
+        /* FIXME: I don't think this can ever happen, but James tells me he had
+         * to put this code in.  Maybe we should remove it now.  Anyone? */
         if (delta < LG_CLOCK_MIN_DELTA) {
                 if (printk_ratelimit())
                         printk(KERN_DEBUG "%s: small delta %lu ns\n",
                                __FUNCTION__, delta);
                 return -ETIME;
         }
+
+        /* Please wake us this far in the future. */
         hcall(LHCALL_SET_CLOCKEVENT, delta, 0, 0);
         return 0;
 }
@@ -738,7 +750,7 @@ static void lguest_time_init(void)
  * will not tolerate us trying to use that), the stack pointer, and the number
  * of pages in the stack. */
 static void lguest_load_sp0(struct tss_struct *tss,
-                                     struct thread_struct *thread)
+                            struct thread_struct *thread)
 {
         lazy_hcall(LHCALL_SET_STACK, __KERNEL_DS|0x1, thread->sp0,
                    THREAD_SIZE/PAGE_SIZE);
@@ -786,9 +798,8 @@ static void lguest_safe_halt(void)
         hcall(LHCALL_HALT, 0, 0, 0);
 }
 
-/* Perhaps CRASH isn't the best name for this hypercall, but we use it to get a
- * message out when we're crashing as well as elegant termination like powering
- * off.
+/* The SHUTDOWN hypercall takes a string to describe what's happening, and
+ * an argument which says whether this to restart (reboot) the Guest or not.
  *
  * Note that the Host always prefers that the Guest speak in physical addresses
  * rather than virtual addresses, so we use __pa() here. */
@@ -816,8 +827,9 @@ static struct notifier_block paniced = {
 /* Setting up memory is fairly easy. */
 static __init char *lguest_memory_setup(void)
 {
-        /* We do this here and not earlier because lockcheck barfs if we do it
-         * before start_kernel() */
+        /* We do this here and not earlier because lockcheck used to barf if we
+         * did it before start_kernel().  I think we fixed that, so it'd be
+         * nice to move it back to lguest_init.  Patch welcome... */
         atomic_notifier_chain_register(&panic_notifier_list, &paniced);
 
         /* The Linux bootloader header contains an "e820" memory map: the
@@ -850,12 +862,19 @@ static __init int early_put_chars(u32 vtermno, const char *buf, int count)
         return len;
 }
 
+/* Rebooting also tells the Host we're finished, but the RESTART flag tells the
+ * Launcher to reboot us. */
+static void lguest_restart(char *reason)
+{
+        hcall(LHCALL_SHUTDOWN, __pa(reason), LGUEST_SHUTDOWN_RESTART, 0);
+}
+
 /*G:050
  * Patching (Powerfully Placating Performance Pedants)
  *
- * We have already seen that pv_ops structures let us replace simple
- * native instructions with calls to the appropriate back end all throughout
- * the kernel.  This allows the same kernel to run as a Guest and as a native
+ * We have already seen that pv_ops structures let us replace simple native
+ * instructions with calls to the appropriate back end all throughout the
+ * kernel.  This allows the same kernel to run as a Guest and as a native
  * kernel, but it's slow because of all the indirect branches.
  *
  * Remember that David Wheeler quote about "Any problem in computer science can
@@ -908,14 +927,9 @@ static unsigned lguest_patch(u8 type, u16 clobber, void *ibuf,
         return insn_len;
 }
 
-static void lguest_restart(char *reason)
-{
-        hcall(LHCALL_SHUTDOWN, __pa(reason), LGUEST_SHUTDOWN_RESTART, 0);
-}
-
-/*G:030 Once we get to lguest_init(), we know we're a Guest.  The pv_ops
- * structures in the kernel provide points for (almost) every routine we have
- * to override to avoid privileged instructions. */
+/*G:030 Once we get to lguest_init(), we know we're a Guest.  The various
+ * pv_ops structures in the kernel provide points for (almost) every routine we
+ * have to override to avoid privileged instructions. */
 __init void lguest_init(void)
 {
         /* We're under lguest, paravirt is enabled, and we're running at
@@ -1003,9 +1017,9 @@ __init void lguest_init(void)
          * the normal data segment to get through booting. */
         asm volatile ("mov %0, %%fs" : : "r" (__KERNEL_DS) : "memory");
 
-        /* The Host uses the top of the Guest's virtual address space for the
-         * Host<->Guest Switcher, and it tells us how big that is in
-         * lguest_data.reserve_mem, set up on the LGUEST_INIT hypercall. */
+        /* The Host<->Guest Switcher lives at the top of our address space, and
+         * the Host told us how big it is when we made LGUEST_INIT hypercall:
+         * it put the answer in lguest_data.reserve_mem  */
         reserve_top_address(lguest_data.reserve_mem);
 
         /* If we don't initialize the lock dependency checker now, it crashes
@@ -1027,6 +1041,7 @@ __init void lguest_init(void)
         /* Math is always hard! */
         new_cpu_data.hard_math = 1;
 
+        /* We don't have features.  We have puppies!  Puppies! */
 #ifdef CONFIG_X86_MCE
         mce_disabled = 1;
 #endif
@@ -1044,10 +1059,11 @@ __init void lguest_init(void)
         virtio_cons_early_init(early_put_chars);
 
         /* Last of all, we set the power management poweroff hook to point to
-         * the Guest routine to power off. */
+         * the Guest routine to power off, and the reboot hook to our restart
+         * routine. */
         pm_power_off = lguest_power_off;
-
         machine_ops.restart = lguest_restart;
+
         /* Now we're set up, call start_kernel() in init/main.c and we proceed
          * to boot as normal.  It never returns. */
         start_kernel();
diff --git a/arch/x86/lguest/i386_head.S b/arch/x86/lguest/i386_head.S
index 95b6fbcded63..5c7cef34c9e7 100644
--- a/arch/x86/lguest/i386_head.S
+++ b/arch/x86/lguest/i386_head.S
@@ -5,13 +5,20 @@
 #include <asm/thread_info.h>
 #include <asm/processor-flags.h>
 
-/*G:020 This is where we begin: head.S notes that the boot header's platform
- * type field is "1" (lguest), so calls us here.
+/*G:020 Our story starts with the kernel booting into startup_32 in
+ * arch/x86/kernel/head_32.S.  It expects a boot header, which is created by
+ * the bootloader (the Launcher in our case).
+ *
+ * The startup_32 function does very little: it clears the uninitialized global
+ * C variables which we expect to be zero (ie. BSS) and then copies the boot
+ * header and kernel command line somewhere safe.  Finally it checks the
+ * 'hardware_subarch' field.  This was introduced in 2.6.24 for lguest and Xen:
+ * if it's set to '1' (lguest's assigned number), then it calls us here.
  *
  * WARNING: be very careful here!  We're running at addresses equal to physical
  * addesses (around 0), not above PAGE_OFFSET as most code expectes
  * (eg. 0xC0000000).  Jumps are relative, so they're OK, but we can't touch any
- * data.
+ * data without remembering to subtract __PAGE_OFFSET!
  *
  * The .section line puts this code in .init.text so it will be discarded after
  * boot. */
@@ -24,7 +31,7 @@ ENTRY(lguest_entry)
         int $LGUEST_TRAP_ENTRY
 
         /* The Host put the toplevel pagetable in lguest_data.pgdir.  The movsl
-         * instruction uses %esi implicitly as the source for the copy we'
+         * instruction uses %esi implicitly as the source for the copy we're
          * about to do. */
         movl lguest_data - __PAGE_OFFSET + LGUEST_DATA_pgdir, %esi
 
diff --git a/arch/x86/mach-rdc321x/gpio.c b/arch/x86/mach-rdc321x/gpio.c
index 031269163bd6..247f33d3a407 100644
--- a/arch/x86/mach-rdc321x/gpio.c
+++ b/arch/x86/mach-rdc321x/gpio.c
@@ -1,91 +1,194 @@
 /*
- *  Copyright (C) 2007, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
- *      RDC321x architecture specific GPIO support
+ *  GPIO support for RDC SoC R3210/R8610
+ *
+ *  Copyright (C) 2007, Florian Fainelli <florian@openwrt.org>
+ *  Copyright (C) 2008, Volker Weiss <dev@tintuc.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
  */
 
-#include <linux/autoconf.h>
-#include <linux/init.h>
+
+#include <linux/spinlock.h>
 #include <linux/io.h>
 #include <linux/types.h>
 #include <linux/module.h>
-#include <linux/delay.h>
 
+#include <asm/gpio.h>
 #include <asm/mach-rdc321x/rdc321x_defs.h>
 
-static inline int rdc_gpio_is_valid(unsigned gpio)
+
+/* spin lock to protect our private copy of GPIO data register plus
+   the access to PCI conf registers. */
+static DEFINE_SPINLOCK(gpio_lock);
+
+/* copy of GPIO data registers */
+static u32 gpio_data_reg1;
+static u32 gpio_data_reg2;
+
+static u32 gpio_request_data[2];
+
+
+static inline void rdc321x_conf_write(unsigned addr, u32 value)
 {
-        return (gpio <= RDC_MAX_GPIO);
+        outl((1 << 31) | (7 << 11) | addr, RDC3210_CFGREG_ADDR);
+        outl(value, RDC3210_CFGREG_DATA);
 }
 
-static unsigned int rdc_gpio_read(unsigned gpio)
+static inline void rdc321x_conf_or(unsigned addr, u32 value)
 {
-        unsigned int val;
-
-        val = 0x80000000 | (7 << 11) | ((gpio&0x20?0x84:0x48));
-        outl(val, RDC3210_CFGREG_ADDR);
-        udelay(10);
-        val = inl(RDC3210_CFGREG_DATA);
-        val |= (0x1 << (gpio & 0x1F));
-        outl(val, RDC3210_CFGREG_DATA);
-        udelay(10);
-        val = 0x80000000 | (7 << 11) | ((gpio&0x20?0x88:0x4C));
-        outl(val, RDC3210_CFGREG_ADDR);
-        udelay(10);
-        val = inl(RDC3210_CFGREG_DATA);
-
-        return val;
+        outl((1 << 31) | (7 << 11) | addr, RDC3210_CFGREG_ADDR);
+        value |= inl(RDC3210_CFGREG_DATA);
+        outl(value, RDC3210_CFGREG_DATA);
 }
 
-static void rdc_gpio_write(unsigned int val)
+static inline u32 rdc321x_conf_read(unsigned addr)
 {
-        if (val) {
-                outl(val, RDC3210_CFGREG_DATA);
-                udelay(10);
-        }
+        outl((1 << 31) | (7 << 11) | addr, RDC3210_CFGREG_ADDR);
+
+        return inl(RDC3210_CFGREG_DATA);
 }
 
-int rdc_gpio_get_value(unsigned gpio)
+/* configure pin as GPIO */
+static void rdc321x_configure_gpio(unsigned gpio)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&gpio_lock, flags);
+        rdc321x_conf_or(gpio < 32
+                ? RDC321X_GPIO_CTRL_REG1 : RDC321X_GPIO_CTRL_REG2,
+                1 << (gpio & 0x1f));
+        spin_unlock_irqrestore(&gpio_lock, flags);
+}
+
+/* initially setup the 2 copies of the gpio data registers.
+   This function must be called by the platform setup code. */
+void __init rdc321x_gpio_setup()
+{
+        /* this might not be, what others (BIOS, bootloader, etc.)
+           wrote to these registers before, but it's a good guess. Still
+           better than just using 0xffffffff. */
+
+        gpio_data_reg1 = rdc321x_conf_read(RDC321X_GPIO_DATA_REG1);
+        gpio_data_reg2 = rdc321x_conf_read(RDC321X_GPIO_DATA_REG2);
+}
+
+/* determine, if gpio number is valid */
+static inline int rdc321x_is_gpio(unsigned gpio)
+{
+        return gpio <= RDC321X_MAX_GPIO;
+}
+
+/* request GPIO */
+int rdc_gpio_request(unsigned gpio, const char *label)
 {
-        if (rdc_gpio_is_valid(gpio))
-                return (int)rdc_gpio_read(gpio);
-        else
+        unsigned long flags;
+
+        if (!rdc321x_is_gpio(gpio))
                 return -EINVAL;
+
+        spin_lock_irqsave(&gpio_lock, flags);
+        if (gpio_request_data[(gpio & 0x20) ? 1 : 0] & (1 << (gpio & 0x1f)))
+                goto inuse;
+        gpio_request_data[(gpio & 0x20) ? 1 : 0] |= (1 << (gpio & 0x1f));
+        spin_unlock_irqrestore(&gpio_lock, flags);
+
+        return 0;
+inuse:
+        spin_unlock_irqrestore(&gpio_lock, flags);
+        return -EINVAL;
 }
-EXPORT_SYMBOL(rdc_gpio_get_value);
+EXPORT_SYMBOL(rdc_gpio_request);
 
-void rdc_gpio_set_value(unsigned gpio, int value)
+/* release previously-claimed GPIO */
+void rdc_gpio_free(unsigned gpio)
 {
-        unsigned int val;
+        unsigned long flags;
 
-        if (!rdc_gpio_is_valid(gpio))
+        if (!rdc321x_is_gpio(gpio))
                 return;
 
-        val = rdc_gpio_read(gpio);
+        spin_lock_irqsave(&gpio_lock, flags);
+        gpio_request_data[(gpio & 0x20) ? 1 : 0] &= ~(1 << (gpio & 0x1f));
+        spin_unlock_irqrestore(&gpio_lock, flags);
+}
+EXPORT_SYMBOL(rdc_gpio_free);
+
+/* read GPIO pin */
+int rdc_gpio_get_value(unsigned gpio)
+{
+        u32 reg;
+        unsigned long flags;
+
+        spin_lock_irqsave(&gpio_lock, flags);
+        reg = rdc321x_conf_read(gpio < 32
+                ? RDC321X_GPIO_DATA_REG1 : RDC321X_GPIO_DATA_REG2);
+        spin_unlock_irqrestore(&gpio_lock, flags);
 
-        if (value)
-                val &= ~(0x1 << (gpio & 0x1F));
-        else
-                val |= (0x1 << (gpio & 0x1F));
+        return (1 << (gpio & 0x1f)) & reg ? 1 : 0;
+}
+EXPORT_SYMBOL(rdc_gpio_get_value);
 
-        rdc_gpio_write(val);
+/* set GPIO pin to value */
+void rdc_gpio_set_value(unsigned gpio, int value)
+{
+        unsigned long flags;
+        u32 reg;
+
+        reg = 1 << (gpio & 0x1f);
+        if (gpio < 32) {
+                spin_lock_irqsave(&gpio_lock, flags);
+                if (value)
+                        gpio_data_reg1 |= reg;
+                else
+                        gpio_data_reg1 &= ~reg;
+                rdc321x_conf_write(RDC321X_GPIO_DATA_REG1, gpio_data_reg1);
+                spin_unlock_irqrestore(&gpio_lock, flags);
+        } else {
+                spin_lock_irqsave(&gpio_lock, flags);
+                if (value)
+                        gpio_data_reg2 |= reg;
+                else
+                        gpio_data_reg2 &= ~reg;
+                rdc321x_conf_write(RDC321X_GPIO_DATA_REG2, gpio_data_reg2);
+                spin_unlock_irqrestore(&gpio_lock, flags);
+        }
 }
 EXPORT_SYMBOL(rdc_gpio_set_value);
 
+/* configure GPIO pin as input */
 int rdc_gpio_direction_input(unsigned gpio)
 {
+        if (!rdc321x_is_gpio(gpio))
+                return -EINVAL;
+
+        rdc321x_configure_gpio(gpio);
+
         return 0;
 }
 EXPORT_SYMBOL(rdc_gpio_direction_input);
 
+/* configure GPIO pin as output and set value */
 int rdc_gpio_direction_output(unsigned gpio, int value)
 {
+        if (!rdc321x_is_gpio(gpio))
+                return -EINVAL;
+
+        gpio_set_value(gpio, value);
+        rdc321x_configure_gpio(gpio);
+
         return 0;
 }
 EXPORT_SYMBOL(rdc_gpio_direction_output);
-
-
diff --git a/arch/x86/mach-rdc321x/platform.c b/arch/x86/mach-rdc321x/platform.c
index dda6024a5862..a037041817c7 100644
--- a/arch/x86/mach-rdc321x/platform.c
+++ b/arch/x86/mach-rdc321x/platform.c
@@ -62,6 +62,8 @@ static struct platform_device *rdc321x_devs[] = {
 
 static int __init rdc_board_setup(void)
 {
+        rdc321x_gpio_setup();
+
         return platform_add_devices(rdc321x_devs, ARRAY_SIZE(rdc321x_devs));
 }
 
diff --git a/arch/x86/mm/discontig_32.c b/arch/x86/mm/discontig_32.c
index c394ca0720b8..8e25e06ff730 100644
--- a/arch/x86/mm/discontig_32.c
+++ b/arch/x86/mm/discontig_32.c
@@ -324,7 +324,6 @@ unsigned long __init setup_memory(void)
          * this space and use it to adjust the boundary between ZONE_NORMAL
          * and ZONE_HIGHMEM.
          */
-        find_max_pfn();
         get_memcfg_numa();
 
         kva_pages = calculate_numa_remap_pages();
diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c
index fdc667422df9..ec08d8389850 100644
--- a/arch/x86/mm/fault.c
+++ b/arch/x86/mm/fault.c
@@ -91,12 +91,10 @@ static int is_prefetch(struct pt_regs *regs, unsigned long addr,
         int prefetch = 0;
         unsigned char *max_instr;
 
-#ifdef CONFIG_X86_32
-        if (!(__supported_pte_mask & _PAGE_NX))
-                return 0;
-#endif
-
-        /* If it was a exec fault on NX page, ignore */
+        /*
+         * If it was a exec (instruction fetch) fault on NX page, then
+         * do not ignore the fault:
+         */
         if (error_code & PF_INSTR)
                 return 0;
 
diff --git a/arch/x86/mm/highmem_32.c b/arch/x86/mm/highmem_32.c
index 3d936f232704..9cf33d3ee5bc 100644
--- a/arch/x86/mm/highmem_32.c
+++ b/arch/x86/mm/highmem_32.c
@@ -73,15 +73,15 @@ void *kmap_atomic_prot(struct page *page, enum km_type type, pgprot_t prot)
 {
         enum fixed_addresses idx;
         unsigned long vaddr;
-        /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */
-
-        debug_kmap_atomic_prot(type);
 
+        /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */
         pagefault_disable();
 
         if (!PageHighMem(page))
                 return page_address(page);
 
+        debug_kmap_atomic_prot(type);
+
         idx = type + KM_TYPE_NR*smp_processor_id();
         vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
         BUG_ON(!pte_none(*(kmap_pte-idx)));
diff --git a/arch/x86/mm/hugetlbpage.c b/arch/x86/mm/hugetlbpage.c
index 4fbafb4bc2f0..0b3d567e686d 100644
--- a/arch/x86/mm/hugetlbpage.c
+++ b/arch/x86/mm/hugetlbpage.c
@@ -178,7 +178,7 @@ follow_huge_addr(struct mm_struct *mm, unsigned long address, int write)
 
         page = &pte_page(*pte)[vpfn % (HPAGE_SIZE/PAGE_SIZE)];
 
-        WARN_ON(!PageCompound(page));
+        WARN_ON(!PageHead(page));
 
         return page;
 }
diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c
index 4afaba0ed722..794895c6dcc9 100644
--- a/arch/x86/mm/ioremap.c
+++ b/arch/x86/mm/ioremap.c
@@ -137,7 +137,11 @@ static void __iomem *__ioremap(resource_size_t phys_addr, unsigned long size,
         switch (mode) {
         case IOR_MODE_UNCACHED:
         default:
-                prot = PAGE_KERNEL_NOCACHE;
+                /*
+                 * FIXME: we will use UC MINUS for now, as video fb drivers
+                 * depend on it. Upcoming ioremap_wc() will fix this behavior.
+                 */
+                prot = PAGE_KERNEL_UC_MINUS;
                 break;
         case IOR_MODE_CACHED:
                 prot = PAGE_KERNEL;
diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c
index 14e48b5a94ba..7b79f6be4e7d 100644
--- a/arch/x86/mm/pageattr.c
+++ b/arch/x86/mm/pageattr.c
@@ -771,7 +771,7 @@ static inline int change_page_attr_clear(unsigned long addr, int numpages,
 int set_memory_uc(unsigned long addr, int numpages)
 {
         return change_page_attr_set(addr, numpages,
-                                    __pgprot(_PAGE_PCD | _PAGE_PWT));
+                                    __pgprot(_PAGE_PCD));
 }
 EXPORT_SYMBOL(set_memory_uc);
 
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index 8b9ee27805fd..27ee26aedf94 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -95,7 +95,7 @@ struct shared_info *HYPERVISOR_shared_info = (void *)&dummy_shared_info;
  *
  * 0: not available, 1: available
  */
-static int have_vcpu_info_placement = 0;
+static int have_vcpu_info_placement = 1;
 
 static void __init xen_vcpu_setup(int cpu)
 {
@@ -103,6 +103,7 @@ static void __init xen_vcpu_setup(int cpu)
         int err;
         struct vcpu_info *vcpup;
 
+        BUG_ON(HYPERVISOR_shared_info == &dummy_shared_info);
         per_cpu(xen_vcpu, cpu) = &HYPERVISOR_shared_info->vcpu_info[cpu];
 
         if (!have_vcpu_info_placement)
@@ -666,10 +667,10 @@ static void xen_release_pt_init(u32 pfn)
         make_lowmem_page_readwrite(__va(PFN_PHYS(pfn)));
 }
 
-static void pin_pagetable_pfn(unsigned level, unsigned long pfn)
+static void pin_pagetable_pfn(unsigned cmd, unsigned long pfn)
 {
         struct mmuext_op op;
-        op.cmd = level;
+        op.cmd = cmd;
         op.arg1.mfn = pfn_to_mfn(pfn);
         if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF))
                 BUG();
@@ -686,7 +687,8 @@ static void xen_alloc_ptpage(struct mm_struct *mm, u32 pfn, unsigned level)
 
                 if (!PageHighMem(page)) {
                         make_lowmem_page_readonly(__va(PFN_PHYS(pfn)));
-                        pin_pagetable_pfn(level, pfn);
+                        if (level == PT_PTE)
+                                pin_pagetable_pfn(MMUEXT_PIN_L1_TABLE, pfn);
                 } else
                         /* make sure there are no stray mappings of
                            this page */
@@ -696,27 +698,39 @@ static void xen_alloc_ptpage(struct mm_struct *mm, u32 pfn, unsigned level)
 
 static void xen_alloc_pt(struct mm_struct *mm, u32 pfn)
 {
-        xen_alloc_ptpage(mm, pfn, MMUEXT_PIN_L1_TABLE);
+        xen_alloc_ptpage(mm, pfn, PT_PTE);
 }
 
 static void xen_alloc_pd(struct mm_struct *mm, u32 pfn)
 {
-        xen_alloc_ptpage(mm, pfn, MMUEXT_PIN_L2_TABLE);
+        xen_alloc_ptpage(mm, pfn, PT_PMD);
 }
 
 /* This should never happen until we're OK to use struct page */
-static void xen_release_pt(u32 pfn)
+static void xen_release_ptpage(u32 pfn, unsigned level)
 {
         struct page *page = pfn_to_page(pfn);
 
         if (PagePinned(page)) {
                 if (!PageHighMem(page)) {
-                        pin_pagetable_pfn(MMUEXT_UNPIN_TABLE, pfn);
+                        if (level == PT_PTE)
+                                pin_pagetable_pfn(MMUEXT_UNPIN_TABLE, pfn);
                         make_lowmem_page_readwrite(__va(PFN_PHYS(pfn)));
                 }
+                ClearPagePinned(page);
         }
 }
 
+static void xen_release_pt(u32 pfn)
+{
+        xen_release_ptpage(pfn, PT_PTE);
+}
+
+static void xen_release_pd(u32 pfn)
+{
+        xen_release_ptpage(pfn, PT_PMD);
+}
+
 #ifdef CONFIG_HIGHPTE
 static void *xen_kmap_atomic_pte(struct page *page, enum km_type type)
 {
@@ -805,33 +819,43 @@ static __init void xen_pagetable_setup_start(pgd_t *base)
                           PFN_DOWN(__pa(xen_start_info->pt_base)));
 }
 
-static __init void xen_pagetable_setup_done(pgd_t *base)
+static __init void setup_shared_info(void)
 {
-        /* This will work as long as patching hasn't happened yet
-           (which it hasn't) */
-        pv_mmu_ops.alloc_pt = xen_alloc_pt;
-        pv_mmu_ops.alloc_pd = xen_alloc_pd;
-        pv_mmu_ops.release_pt = xen_release_pt;
-        pv_mmu_ops.release_pd = xen_release_pt;
-        pv_mmu_ops.set_pte = xen_set_pte;
-
         if (!xen_feature(XENFEAT_auto_translated_physmap)) {
+                unsigned long addr = fix_to_virt(FIX_PARAVIRT_BOOTMAP);
+
                 /*
                  * Create a mapping for the shared info page.
                  * Should be set_fixmap(), but shared_info is a machine
                  * address with no corresponding pseudo-phys address.
                  */
-                set_pte_mfn(fix_to_virt(FIX_PARAVIRT_BOOTMAP),
+                set_pte_mfn(addr,
                             PFN_DOWN(xen_start_info->shared_info),
                             PAGE_KERNEL);
 
-                HYPERVISOR_shared_info =
-                        (struct shared_info *)fix_to_virt(FIX_PARAVIRT_BOOTMAP);
-
+                HYPERVISOR_shared_info = (struct shared_info *)addr;
         } else
                 HYPERVISOR_shared_info =
                         (struct shared_info *)__va(xen_start_info->shared_info);
 
+#ifndef CONFIG_SMP
+        /* In UP this is as good a place as any to set up shared info */
+        xen_setup_vcpu_info_placement();
+#endif
+}
+
+static __init void xen_pagetable_setup_done(pgd_t *base)
+{
+        /* This will work as long as patching hasn't happened yet
+           (which it hasn't) */
+        pv_mmu_ops.alloc_pt = xen_alloc_pt;
+        pv_mmu_ops.alloc_pd = xen_alloc_pd;
+        pv_mmu_ops.release_pt = xen_release_pt;
+        pv_mmu_ops.release_pd = xen_release_pd;
+        pv_mmu_ops.set_pte = xen_set_pte;
+
+        setup_shared_info();
+
         /* Actually pin the pagetable down, but we can't set PG_pinned
            yet because the page structures don't exist yet. */
         {
@@ -1182,15 +1206,9 @@ asmlinkage void __init xen_start_kernel(void)
         x86_write_percpu(xen_cr3, __pa(pgd));
         x86_write_percpu(xen_current_cr3, __pa(pgd));
 
-#ifdef CONFIG_SMP
         /* Don't do the full vcpu_info placement stuff until we have a
-           possible map. */
+           possible map and a non-dummy shared_info. */
         per_cpu(xen_vcpu, 0) = &HYPERVISOR_shared_info->vcpu_info[0];
-#else
-        /* May as well do it now, since there's no good time to call
-           it later on UP. */
-        xen_setup_vcpu_info_placement();
-#endif
 
         pv_info.kernel_rpl = 1;
         if (xen_feature(XENFEAT_supervisor_mode_kernel))
diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c
index 0144395448ae..2a054ef2a3da 100644
--- a/arch/x86/xen/mmu.c
+++ b/arch/x86/xen/mmu.c
@@ -310,13 +310,6 @@ pgd_t xen_make_pgd(unsigned long pgd)
 }
 #endif  /* CONFIG_X86_PAE */
 
-enum pt_level {
-        PT_PGD,
-        PT_PUD,
-        PT_PMD,
-        PT_PTE
-};
-
 /*
   (Yet another) pagetable walker.  This one is intended for pinning a
   pagetable.  This means that it walks a pagetable and calls the
diff --git a/arch/x86/xen/mmu.h b/arch/x86/xen/mmu.h
index c9ff27f3ac3a..b5e189b1519d 100644
--- a/arch/x86/xen/mmu.h
+++ b/arch/x86/xen/mmu.h
@@ -3,6 +3,13 @@
 #include <linux/linkage.h>
 #include <asm/page.h>
 
+enum pt_level {
+        PT_PGD,
+        PT_PUD,
+        PT_PMD,
+        PT_PTE
+};
+
 /*
  * Page-directory addresses above 4GB do not fit into architectural %cr3.
  * When accessing %cr3, or equivalent field in vcpu_guest_context, guests
diff --git a/arch/x86/xen/xen-asm.S b/arch/x86/xen/xen-asm.S
index 1a43b60c0c62..6b7190449d07 100644
--- a/arch/x86/xen/xen-asm.S
+++ b/arch/x86/xen/xen-asm.S
@@ -33,12 +33,17 @@
         events, then enter the hypervisor to get them handled.
  */
 ENTRY(xen_irq_enable_direct)
-        /* Clear mask and test pending */
-        andw $0x00ff, PER_CPU_VAR(xen_vcpu_info)+XEN_vcpu_info_pending
+        /* Unmask events */
+        movb $0, PER_CPU_VAR(xen_vcpu_info)+XEN_vcpu_info_mask
+
         /* Preempt here doesn't matter because that will deal with
            any pending interrupts.  The pending check may end up being
            run on the wrong CPU, but that doesn't hurt. */
+
+        /* Test for pending */
+        testb $0xff, PER_CPU_VAR(xen_vcpu_info)+XEN_vcpu_info_pending
         jz 1f
+
 2:      call check_events
 1:
 ENDPATCH(xen_irq_enable_direct)