Merge branch 's3c-moves2' of git://aeryn.fluff.org.uk/bjdooks/linux into devel

31 files changed, 747 insertions, 30 deletions

diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c
index 17d4674ecb47..552b4c778fdc 100644
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c2410/dma.c
@@ -24,12 +24,12 @@
 
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
-#include <asm/plat-s3c/regs-ac97.h>
+#include <plat/regs-ac97.h>
 #include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <mach/regs-sdi.h>
 #include <asm/plat-s3c24xx/regs-iis.h>
-#include <asm/plat-s3c24xx/regs-spi.h>
+#include <plat/regs-spi.h>
 
 static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
         [DMACH_XD0] = {
diff --git a/arch/arm/mach-s3c2410/include/mach/system-reset.h b/arch/arm/mach-s3c2410/include/mach/system-reset.h
index 43535a0e7186..7613d0a384ba 100644
--- a/arch/arm/mach-s3c2410/include/mach/system-reset.h
+++ b/arch/arm/mach-s3c2410/include/mach/system-reset.h
@@ -13,7 +13,7 @@
 #include <mach/hardware.h>
 #include <linux/io.h>
 
-#include <asm/plat-s3c/regs-watchdog.h>
+#include <plat/regs-watchdog.h>
 #include <mach/regs-clock.h>
 
 #include <linux/clk.h>
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 8db9c700e3c2..c04c24444e0d 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -44,8 +44,8 @@
 #include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 
-#include <asm/plat-s3c/nand.h>
-#include <asm/plat-s3c/iic.h>
+#include <plat/nand.h>
+#include <plat/iic.h>
 #include <mach/fb.h>
 
 #include <linux/mtd/mtd.h>
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 98716d0108e9..32d550fcff4d 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -38,7 +38,7 @@
 #include <mach/h1940.h>
 #include <mach/h1940-latch.h>
 #include <mach/fb.h>
-#include <asm/plat-s3c24xx/udc.h>
+#include <plat/udc.h>
 
 #include <plat/clock.h>
 #include <plat/devs.h>
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 82505517846c..7a7c45d28fe7 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -40,14 +40,14 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
 
-#include <asm/plat-s3c/iic.h>
+#include <plat/iic.h>
 #include <plat/regs-serial.h>
 
 #include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/s3c2410.h>
-#include <asm/plat-s3c24xx/udc.h>
+#include <plat/udc.h>
 
 static struct map_desc n30_iodesc[] __initdata = {
         /* nothing here yet */
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index 661807e14e8a..ef868472f6a4 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -50,8 +50,8 @@
 #include <mach/leds-gpio.h>
 #include <plat/regs-serial.h>
 #include <mach/fb.h>
-#include <asm/plat-s3c/nand.h>
-#include <asm/plat-s3c24xx/udc.h>
+#include <plat/nand.h>
+#include <plat/udc.h>
 #include <mach/spi.h>
 #include <mach/spi-gpio.h>
 
diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c
index b5e6a35321d8..919856c9433f 100644
--- a/arch/arm/mach-s3c2412/dma.c
+++ b/arch/arm/mach-s3c2412/dma.c
@@ -25,13 +25,13 @@
 
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
-#include <asm/plat-s3c/regs-ac97.h>
+#include <plat/regs-ac97.h>
 #include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <mach/regs-sdi.h>
 #include <asm/plat-s3c24xx/regs-s3c2412-iis.h>
 #include <asm/plat-s3c24xx/regs-iis.h>
-#include <asm/plat-s3c24xx/regs-spi.h>
+#include <plat/regs-spi.h>
 
 #define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID }
 
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c
index b08f18c8c47a..25ff1ec9f8ad 100644
--- a/arch/arm/mach-s3c2412/mach-jive.c
+++ b/arch/arm/mach-s3c2412/mach-jive.c
@@ -31,8 +31,8 @@
 #include <asm/mach/irq.h>
 
 #include <plat/regs-serial.h>
-#include <asm/plat-s3c/nand.h>
-#include <asm/plat-s3c/iic.h>
+#include <plat/nand.h>
+#include <plat/iic.h>
 
 #include <mach/regs-power.h>
 #include <mach/regs-gpio.h>
@@ -52,7 +52,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
-#include <asm/plat-s3c24xx/udc.h>
+#include <plat/udc.h>
 
 static struct map_desc jive_iodesc[] __initdata = {
 };
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c
index c719b5a740a9..8fd17b8d5679 100644
--- a/arch/arm/mach-s3c2412/mach-smdk2413.c
+++ b/arch/arm/mach-s3c2412/mach-smdk2413.c
@@ -37,7 +37,7 @@
 #include <mach/regs-lcd.h>
 
 #include <mach/idle.h>
-#include <asm/plat-s3c24xx/udc.h>
+#include <plat/udc.h>
 #include <mach/fb.h>
 
 #include <plat/s3c2410.h>
diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c
index 4cfa19ad9be0..da32a6cb17ae 100644
--- a/arch/arm/mach-s3c2412/mach-vstms.c
+++ b/arch/arm/mach-s3c2412/mach-vstms.c
@@ -39,7 +39,7 @@
 #include <mach/idle.h>
 #include <mach/fb.h>
 
-#include <asm/plat-s3c/nand.h>
+#include <plat/nand.h>
 
 #include <plat/s3c2410.h>
 #include <plat/s3c2412.h>
diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c
index 313759c3da69..a086818e117e 100644
--- a/arch/arm/mach-s3c2412/s3c2412.c
+++ b/arch/arm/mach-s3c2412/s3c2412.c
@@ -39,7 +39,7 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-gpioj.h>
 #include <mach/regs-dsc.h>
-#include <asm/plat-s3c24xx/regs-spi.h>
+#include <plat/regs-spi.h>
 #include <mach/regs-s3c2412.h>
 
 #include <plat/s3c2412.h>
diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c2440/dma.c
index f33baad69d01..5b5ee0b8f4e0 100644
--- a/arch/arm/mach-s3c2440/dma.c
+++ b/arch/arm/mach-s3c2440/dma.c
@@ -24,12 +24,12 @@
 
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
-#include <asm/plat-s3c/regs-ac97.h>
+#include <plat/regs-ac97.h>
 #include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <mach/regs-sdi.h>
 #include <asm/plat-s3c24xx/regs-iis.h>
-#include <asm/plat-s3c24xx/regs-spi.h>
+#include <plat/regs-spi.h>
 
 static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
         [DMACH_XD0] = {
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
index e2beca470484..334379bdfc6e 100644
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -39,7 +39,7 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
-#include <asm/plat-s3c/nand.h>
+#include <plat/nand.h>
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c
index 66876c6f2f1c..07b42a0207d1 100644
--- a/arch/arm/mach-s3c2440/mach-at2440evb.c
+++ b/arch/arm/mach-s3c2440/mach-at2440evb.c
@@ -35,7 +35,7 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
-#include <asm/plat-s3c/nand.h>
+#include <plat/nand.h>
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index 2361d606abc5..884a3c7ae75f 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -37,7 +37,7 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
-#include <asm/plat-s3c/nand.h>
+#include <plat/nand.h>
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
index 4d14c7cff892..fbd081de592f 100644
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -42,7 +42,7 @@
 #include <mach/regs-lcd.h>
 
 #include <mach/h1940.h>
-#include <asm/plat-s3c/nand.h>
+#include <plat/nand.h>
 #include <mach/fb.h>
 
 #include <plat/clock.h>
diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c2443/dma.c
index 2a685ce22eed..2a58a4d5aa5a 100644
--- a/arch/arm/mach-s3c2443/dma.c
+++ b/arch/arm/mach-s3c2443/dma.c
@@ -25,12 +25,12 @@
 
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
-#include <asm/plat-s3c/regs-ac97.h>
+#include <plat/regs-ac97.h>
 #include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <mach/regs-sdi.h>
 #include <asm/plat-s3c24xx/regs-iis.h>
-#include <asm/plat-s3c24xx/regs-spi.h>
+#include <plat/regs-spi.h>
 
 #define MAP(x) { \
                 [0]     = (x) | DMA_CH_VALID,   \
diff --git a/arch/arm/plat-s3c/include/plat/iic.h b/arch/arm/plat-s3c/include/plat/iic.h
new file mode 100644
index 000000000000..5106acaa1d0e
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/iic.h
@@ -0,0 +1,33 @@
+/* arch/arm/mach-s3c2410/include/mach/iic.h
+ *
+ * Copyright (c) 2004 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - I2C Controller platfrom_device info
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_IIC_H
+#define __ASM_ARCH_IIC_H __FILE__
+
+#define S3C_IICFLG_FILTER       (1<<0)  /* enable s3c2440 filter */
+
+/* Notes:
+ *      1) All frequencies are expressed in Hz
+ *      2) A value of zero is `do not care`
+*/
+
+struct s3c2410_platform_i2c {
+        int             bus_num;        /* bus number to use */
+        unsigned int    flags;
+        unsigned int    slave_addr;     /* slave address for controller */
+        unsigned long   bus_freq;       /* standard bus frequency */
+        unsigned long   max_freq;       /* max frequency for the bus */
+        unsigned long   min_freq;       /* min frequency for the bus */
+        unsigned int    sda_delay;      /* pclks (s3c2440 only) */
+};
+
+#endif /* __ASM_ARCH_IIC_H */
diff --git a/arch/arm/plat-s3c/include/plat/nand.h b/arch/arm/plat-s3c/include/plat/nand.h
new file mode 100644
index 000000000000..f4dcd14af059
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/nand.h
@@ -0,0 +1,50 @@
+/* arch/arm/mach-s3c2410/include/mach/nand.h
+ *
+ * Copyright (c) 2004 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - NAND device controller platfrom_device info
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* struct s3c2410_nand_set
+ *
+ * define an set of one or more nand chips registered with an unique mtd
+ *
+ * nr_chips      = number of chips in this set
+ * nr_partitions = number of partitions pointed to be partitoons (or zero)
+ * name          = name of set (optional)
+ * nr_map        = map for low-layer logical to physical chip numbers (option)
+ * partitions    = mtd partition list
+*/
+
+struct s3c2410_nand_set {
+        unsigned int            disable_ecc : 1;
+
+        int                     nr_chips;
+        int                     nr_partitions;
+        char                    *name;
+        int                     *nr_map;
+        struct mtd_partition    *partitions;
+        struct nand_ecclayout   *ecc_layout;
+};
+
+struct s3c2410_platform_nand {
+        /* timing information for controller, all times in nanoseconds */
+
+        int     tacls;  /* time for active CLE/ALE to nWE/nOE */
+        int     twrph0; /* active time for nWE/nOE */
+        int     twrph1; /* time for release CLE/ALE from nWE/nOE inactive */
+
+        unsigned int    ignore_unset_ecc : 1;
+
+        int                     nr_sets;
+        struct s3c2410_nand_set *sets;
+
+        void                    (*select_chip)(struct s3c2410_nand_set *,
+                                               int chip);
+};
+
diff --git a/arch/arm/plat-s3c/include/plat/regs-ac97.h b/arch/arm/plat-s3c/include/plat/regs-ac97.h
new file mode 100644
index 000000000000..c3878f7acb83
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-ac97.h
@@ -0,0 +1,67 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-ac97.h
+ *
+ * Copyright (c) 2006 Simtec Electronics <linux@simtec.co.uk>
+ *              http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2440 AC97 Controller
+*/
+
+#ifndef __ASM_ARCH_REGS_AC97_H
+#define __ASM_ARCH_REGS_AC97_H __FILE__
+
+#define S3C_AC97_GLBCTRL                                (0x00)
+
+#define S3C_AC97_GLBCTRL_CODECREADYIE                   (1<<22)
+#define S3C_AC97_GLBCTRL_PCMOUTURIE                     (1<<21)
+#define S3C_AC97_GLBCTRL_PCMINORIE                      (1<<20)
+#define S3C_AC97_GLBCTRL_MICINORIE                      (1<<19)
+#define S3C_AC97_GLBCTRL_PCMOUTTIE                      (1<<18)
+#define S3C_AC97_GLBCTRL_PCMINTIE                       (1<<17)
+#define S3C_AC97_GLBCTRL_MICINTIE                       (1<<16)
+#define S3C_AC97_GLBCTRL_PCMOUTTM_OFF                   (0<<12)
+#define S3C_AC97_GLBCTRL_PCMOUTTM_PIO                   (1<<12)
+#define S3C_AC97_GLBCTRL_PCMOUTTM_DMA                   (2<<12)
+#define S3C_AC97_GLBCTRL_PCMOUTTM_MASK                  (3<<12)
+#define S3C_AC97_GLBCTRL_PCMINTM_OFF                    (0<<10)
+#define S3C_AC97_GLBCTRL_PCMINTM_PIO                    (1<<10)
+#define S3C_AC97_GLBCTRL_PCMINTM_DMA                    (2<<10)
+#define S3C_AC97_GLBCTRL_PCMINTM_MASK                   (3<<10)
+#define S3C_AC97_GLBCTRL_MICINTM_OFF                    (0<<8)
+#define S3C_AC97_GLBCTRL_MICINTM_PIO                    (1<<8)
+#define S3C_AC97_GLBCTRL_MICINTM_DMA                    (2<<8)
+#define S3C_AC97_GLBCTRL_MICINTM_MASK                   (3<<8)
+#define S3C_AC97_GLBCTRL_TRANSFERDATAENABLE             (1<<3)
+#define S3C_AC97_GLBCTRL_ACLINKON                       (1<<2)
+#define S3C_AC97_GLBCTRL_WARMRESET                      (1<<1)
+#define S3C_AC97_GLBCTRL_COLDRESET                      (1<<0)
+
+#define S3C_AC97_GLBSTAT                                (0x04)
+
+#define S3C_AC97_GLBSTAT_CODECREADY                     (1<<22)
+#define S3C_AC97_GLBSTAT_PCMOUTUR                       (1<<21)
+#define S3C_AC97_GLBSTAT_PCMINORI                       (1<<20)
+#define S3C_AC97_GLBSTAT_MICINORI                       (1<<19)
+#define S3C_AC97_GLBSTAT_PCMOUTTI                       (1<<18)
+#define S3C_AC97_GLBSTAT_PCMINTI                        (1<<17)
+#define S3C_AC97_GLBSTAT_MICINTI                        (1<<16)
+#define S3C_AC97_GLBSTAT_MAINSTATE_IDLE                 (0<<0)
+#define S3C_AC97_GLBSTAT_MAINSTATE_INIT                 (1<<0)
+#define S3C_AC97_GLBSTAT_MAINSTATE_READY                (2<<0)
+#define S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE               (3<<0)
+#define S3C_AC97_GLBSTAT_MAINSTATE_LP                   (4<<0)
+#define S3C_AC97_GLBSTAT_MAINSTATE_WARM                 (5<<0)
+
+#define S3C_AC97_CODEC_CMD                              (0x08)
+
+#define S3C_AC97_CODEC_CMD_READ                         (1<<23)
+
+#define S3C_AC97_STAT                                   (0x0c)
+#define S3C_AC97_PCM_ADDR                               (0x10)
+#define S3C_AC97_PCM_DATA                               (0x18)
+#define S3C_AC97_MIC_DATA                               (0x1C)
+
+#endif /* __ASM_ARCH_REGS_AC97_H */
diff --git a/arch/arm/plat-s3c/include/plat/regs-iic.h b/arch/arm/plat-s3c/include/plat/regs-iic.h
new file mode 100644
index 000000000000..2f7c17de8ac8
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-iic.h
@@ -0,0 +1,56 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-iic.h
+ *
+ * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
+ *              http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 I2C Controller
+*/
+
+#ifndef __ASM_ARCH_REGS_IIC_H
+#define __ASM_ARCH_REGS_IIC_H __FILE__
+
+/* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
+
+#define S3C2410_IICREG(x) (x)
+
+#define S3C2410_IICCON    S3C2410_IICREG(0x00)
+#define S3C2410_IICSTAT   S3C2410_IICREG(0x04)
+#define S3C2410_IICADD    S3C2410_IICREG(0x08)
+#define S3C2410_IICDS     S3C2410_IICREG(0x0C)
+#define S3C2440_IICLC     S3C2410_IICREG(0x10)
+
+#define S3C2410_IICCON_ACKEN            (1<<7)
+#define S3C2410_IICCON_TXDIV_16         (0<<6)
+#define S3C2410_IICCON_TXDIV_512        (1<<6)
+#define S3C2410_IICCON_IRQEN            (1<<5)
+#define S3C2410_IICCON_IRQPEND          (1<<4)
+#define S3C2410_IICCON_SCALE(x)         ((x)&15)
+#define S3C2410_IICCON_SCALEMASK        (0xf)
+
+#define S3C2410_IICSTAT_MASTER_RX       (2<<6)
+#define S3C2410_IICSTAT_MASTER_TX       (3<<6)
+#define S3C2410_IICSTAT_SLAVE_RX        (0<<6)
+#define S3C2410_IICSTAT_SLAVE_TX        (1<<6)
+#define S3C2410_IICSTAT_MODEMASK        (3<<6)
+
+#define S3C2410_IICSTAT_START           (1<<5)
+#define S3C2410_IICSTAT_BUSBUSY         (1<<5)
+#define S3C2410_IICSTAT_TXRXEN          (1<<4)
+#define S3C2410_IICSTAT_ARBITR          (1<<3)
+#define S3C2410_IICSTAT_ASSLAVE         (1<<2)
+#define S3C2410_IICSTAT_ADDR0           (1<<1)
+#define S3C2410_IICSTAT_LASTBIT         (1<<0)
+
+#define S3C2410_IICLC_SDA_DELAY0        (0 << 0)
+#define S3C2410_IICLC_SDA_DELAY5        (1 << 0)
+#define S3C2410_IICLC_SDA_DELAY10       (2 << 0)
+#define S3C2410_IICLC_SDA_DELAY15       (3 << 0)
+#define S3C2410_IICLC_SDA_DELAY_MASK    (3 << 0)
+
+#define S3C2410_IICLC_FILTER_ON         (1<<2)
+
+#endif /* __ASM_ARCH_REGS_IIC_H */
diff --git a/arch/arm/plat-s3c/include/plat/regs-nand.h b/arch/arm/plat-s3c/include/plat/regs-nand.h
new file mode 100644
index 000000000000..b2caa4bca270
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-nand.h
@@ -0,0 +1,123 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-nand.h
+ *
+ * Copyright (c) 2004,2005 Simtec Electronics <linux@simtec.co.uk>
+ *                    http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 NAND register definitions
+*/
+
+#ifndef __ASM_ARM_REGS_NAND
+#define __ASM_ARM_REGS_NAND
+
+
+#define S3C2410_NFREG(x) (x)
+
+#define S3C2410_NFCONF  S3C2410_NFREG(0x00)
+#define S3C2410_NFCMD   S3C2410_NFREG(0x04)
+#define S3C2410_NFADDR  S3C2410_NFREG(0x08)
+#define S3C2410_NFDATA  S3C2410_NFREG(0x0C)
+#define S3C2410_NFSTAT  S3C2410_NFREG(0x10)
+#define S3C2410_NFECC   S3C2410_NFREG(0x14)
+
+#define S3C2440_NFCONT   S3C2410_NFREG(0x04)
+#define S3C2440_NFCMD    S3C2410_NFREG(0x08)
+#define S3C2440_NFADDR   S3C2410_NFREG(0x0C)
+#define S3C2440_NFDATA   S3C2410_NFREG(0x10)
+#define S3C2440_NFECCD0  S3C2410_NFREG(0x14)
+#define S3C2440_NFECCD1  S3C2410_NFREG(0x18)
+#define S3C2440_NFECCD   S3C2410_NFREG(0x1C)
+#define S3C2440_NFSTAT   S3C2410_NFREG(0x20)
+#define S3C2440_NFESTAT0 S3C2410_NFREG(0x24)
+#define S3C2440_NFESTAT1 S3C2410_NFREG(0x28)
+#define S3C2440_NFMECC0  S3C2410_NFREG(0x2C)
+#define S3C2440_NFMECC1  S3C2410_NFREG(0x30)
+#define S3C2440_NFSECC   S3C2410_NFREG(0x34)
+#define S3C2440_NFSBLK   S3C2410_NFREG(0x38)
+#define S3C2440_NFEBLK   S3C2410_NFREG(0x3C)
+
+#define S3C2412_NFSBLK          S3C2410_NFREG(0x20)
+#define S3C2412_NFEBLK          S3C2410_NFREG(0x24)
+#define S3C2412_NFSTAT          S3C2410_NFREG(0x28)
+#define S3C2412_NFMECC_ERR0     S3C2410_NFREG(0x2C)
+#define S3C2412_NFMECC_ERR1     S3C2410_NFREG(0x30)
+#define S3C2412_NFMECC0         S3C2410_NFREG(0x34)
+#define S3C2412_NFMECC1         S3C2410_NFREG(0x38)
+#define S3C2412_NFSECC          S3C2410_NFREG(0x3C)
+
+#define S3C2410_NFCONF_EN          (1<<15)
+#define S3C2410_NFCONF_512BYTE     (1<<14)
+#define S3C2410_NFCONF_4STEP       (1<<13)
+#define S3C2410_NFCONF_INITECC     (1<<12)
+#define S3C2410_NFCONF_nFCE        (1<<11)
+#define S3C2410_NFCONF_TACLS(x)    ((x)<<8)
+#define S3C2410_NFCONF_TWRPH0(x)   ((x)<<4)
+#define S3C2410_NFCONF_TWRPH1(x)   ((x)<<0)
+
+#define S3C2410_NFSTAT_BUSY        (1<<0)
+
+#define S3C2440_NFCONF_BUSWIDTH_8       (0<<0)
+#define S3C2440_NFCONF_BUSWIDTH_16      (1<<0)
+#define S3C2440_NFCONF_ADVFLASH         (1<<3)
+#define S3C2440_NFCONF_TACLS(x)         ((x)<<12)
+#define S3C2440_NFCONF_TWRPH0(x)        ((x)<<8)
+#define S3C2440_NFCONF_TWRPH1(x)        ((x)<<4)
+
+#define S3C2440_NFCONT_LOCKTIGHT        (1<<13)
+#define S3C2440_NFCONT_SOFTLOCK         (1<<12)
+#define S3C2440_NFCONT_ILLEGALACC_EN    (1<<10)
+#define S3C2440_NFCONT_RNBINT_EN        (1<<9)
+#define S3C2440_NFCONT_RN_FALLING       (1<<8)
+#define S3C2440_NFCONT_SPARE_ECCLOCK    (1<<6)
+#define S3C2440_NFCONT_MAIN_ECCLOCK     (1<<5)
+#define S3C2440_NFCONT_INITECC          (1<<4)
+#define S3C2440_NFCONT_nFCE             (1<<1)
+#define S3C2440_NFCONT_ENABLE           (1<<0)
+
+#define S3C2440_NFSTAT_READY            (1<<0)
+#define S3C2440_NFSTAT_nCE              (1<<1)
+#define S3C2440_NFSTAT_RnB_CHANGE       (1<<2)
+#define S3C2440_NFSTAT_ILLEGAL_ACCESS   (1<<3)
+
+#define S3C2412_NFCONF_NANDBOOT         (1<<31)
+#define S3C2412_NFCONF_ECCCLKCON        (1<<30)
+#define S3C2412_NFCONF_ECC_MLC          (1<<24)
+#define S3C2412_NFCONF_TACLS_MASK       (7<<12) /* 1 extra bit of Tacls */
+
+#define S3C2412_NFCONT_ECC4_DIRWR       (1<<18)
+#define S3C2412_NFCONT_LOCKTIGHT        (1<<17)
+#define S3C2412_NFCONT_SOFTLOCK         (1<<16)
+#define S3C2412_NFCONT_ECC4_ENCINT      (1<<13)
+#define S3C2412_NFCONT_ECC4_DECINT      (1<<12)
+#define S3C2412_NFCONT_MAIN_ECC_LOCK    (1<<7)
+#define S3C2412_NFCONT_INIT_MAIN_ECC    (1<<5)
+#define S3C2412_NFCONT_nFCE1            (1<<2)
+#define S3C2412_NFCONT_nFCE0            (1<<1)
+
+#define S3C2412_NFSTAT_ECC_ENCDONE      (1<<7)
+#define S3C2412_NFSTAT_ECC_DECDONE      (1<<6)
+#define S3C2412_NFSTAT_ILLEGAL_ACCESS   (1<<5)
+#define S3C2412_NFSTAT_RnB_CHANGE       (1<<4)
+#define S3C2412_NFSTAT_nFCE1            (1<<3)
+#define S3C2412_NFSTAT_nFCE0            (1<<2)
+#define S3C2412_NFSTAT_Res1             (1<<1)
+#define S3C2412_NFSTAT_READY            (1<<0)
+
+#define S3C2412_NFECCERR_SERRDATA(x)    (((x) >> 21) & 0xf)
+#define S3C2412_NFECCERR_SERRBIT(x)     (((x) >> 18) & 0x7)
+#define S3C2412_NFECCERR_MERRDATA(x)    (((x) >> 7) & 0x3ff)
+#define S3C2412_NFECCERR_MERRBIT(x)     (((x) >> 4) & 0x7)
+#define S3C2412_NFECCERR_SPARE_ERR(x)   (((x) >> 2) & 0x3)
+#define S3C2412_NFECCERR_MAIN_ERR(x)    (((x) >> 2) & 0x3)
+#define S3C2412_NFECCERR_NONE           (0)
+#define S3C2412_NFECCERR_1BIT           (1)
+#define S3C2412_NFECCERR_MULTIBIT       (2)
+#define S3C2412_NFECCERR_ECCAREA        (3)
+
+
+
+#endif /* __ASM_ARM_REGS_NAND */
+
diff --git a/arch/arm/plat-s3c/include/plat/regs-rtc.h b/arch/arm/plat-s3c/include/plat/regs-rtc.h
new file mode 100644
index 000000000000..d5837cf8e402
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-rtc.h
@@ -0,0 +1,61 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-rtc.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *                    http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 Internal RTC register definition
+*/
+
+#ifndef __ASM_ARCH_REGS_RTC_H
+#define __ASM_ARCH_REGS_RTC_H __FILE__
+
+#define S3C2410_RTCREG(x) (x)
+
+#define S3C2410_RTCCON        S3C2410_RTCREG(0x40)
+#define S3C2410_RTCCON_RTCEN  (1<<0)
+#define S3C2410_RTCCON_CLKSEL (1<<1)
+#define S3C2410_RTCCON_CNTSEL (1<<2)
+#define S3C2410_RTCCON_CLKRST (1<<3)
+
+#define S3C2410_TICNT         S3C2410_RTCREG(0x44)
+#define S3C2410_TICNT_ENABLE  (1<<7)
+
+#define S3C2410_RTCALM        S3C2410_RTCREG(0x50)
+#define S3C2410_RTCALM_ALMEN  (1<<6)
+#define S3C2410_RTCALM_YEAREN (1<<5)
+#define S3C2410_RTCALM_MONEN  (1<<4)
+#define S3C2410_RTCALM_DAYEN  (1<<3)
+#define S3C2410_RTCALM_HOUREN (1<<2)
+#define S3C2410_RTCALM_MINEN  (1<<1)
+#define S3C2410_RTCALM_SECEN  (1<<0)
+
+#define S3C2410_RTCALM_ALL \
+  S3C2410_RTCALM_ALMEN | S3C2410_RTCALM_YEAREN | S3C2410_RTCALM_MONEN |\
+  S3C2410_RTCALM_DAYEN | S3C2410_RTCALM_HOUREN | S3C2410_RTCALM_MINEN |\
+  S3C2410_RTCALM_SECEN
+
+
+#define S3C2410_ALMSEC        S3C2410_RTCREG(0x54)
+#define S3C2410_ALMMIN        S3C2410_RTCREG(0x58)
+#define S3C2410_ALMHOUR       S3C2410_RTCREG(0x5c)
+
+#define S3C2410_ALMDATE       S3C2410_RTCREG(0x60)
+#define S3C2410_ALMMON        S3C2410_RTCREG(0x64)
+#define S3C2410_ALMYEAR       S3C2410_RTCREG(0x68)
+
+#define S3C2410_RTCRST        S3C2410_RTCREG(0x6c)
+
+#define S3C2410_RTCSEC        S3C2410_RTCREG(0x70)
+#define S3C2410_RTCMIN        S3C2410_RTCREG(0x74)
+#define S3C2410_RTCHOUR       S3C2410_RTCREG(0x78)
+#define S3C2410_RTCDATE       S3C2410_RTCREG(0x7c)
+#define S3C2410_RTCDAY        S3C2410_RTCREG(0x80)
+#define S3C2410_RTCMON        S3C2410_RTCREG(0x84)
+#define S3C2410_RTCYEAR       S3C2410_RTCREG(0x88)
+
+
+#endif /* __ASM_ARCH_REGS_RTC_H */
diff --git a/arch/arm/plat-s3c/include/plat/regs-watchdog.h b/arch/arm/plat-s3c/include/plat/regs-watchdog.h
new file mode 100644
index 000000000000..4938492470f7
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-watchdog.h
@@ -0,0 +1,41 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-watchdog.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *                    http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 Watchdog timer control
+*/
+
+
+#ifndef __ASM_ARCH_REGS_WATCHDOG_H
+#define __ASM_ARCH_REGS_WATCHDOG_H
+
+#define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG)
+
+#define S3C2410_WTCON      S3C_WDOGREG(0x00)
+#define S3C2410_WTDAT      S3C_WDOGREG(0x04)
+#define S3C2410_WTCNT      S3C_WDOGREG(0x08)
+
+/* the watchdog can either generate a reset pulse, or an
+ * interrupt.
+ */
+
+#define S3C2410_WTCON_RSTEN   (0x01)
+#define S3C2410_WTCON_INTEN   (1<<2)
+#define S3C2410_WTCON_ENABLE  (1<<5)
+
+#define S3C2410_WTCON_DIV16   (0<<3)
+#define S3C2410_WTCON_DIV32   (1<<3)
+#define S3C2410_WTCON_DIV64   (2<<3)
+#define S3C2410_WTCON_DIV128  (3<<3)
+
+#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
+#define S3C2410_WTCON_PRESCALE_MASK (0xff00)
+
+#endif /* __ASM_ARCH_REGS_WATCHDOG_H */
+
+
diff --git a/arch/arm/plat-s3c/include/plat/uncompress.h b/arch/arm/plat-s3c/include/plat/uncompress.h
index 4df006b9cc10..8a8a927292e0 100644
--- a/arch/arm/plat-s3c/include/plat/uncompress.h
+++ b/arch/arm/plat-s3c/include/plat/uncompress.h
@@ -28,7 +28,7 @@ static void arch_detect_cpu(void);
 /* defines for UART registers */
 
 #include <plat/regs-serial.h>
-#include <asm/plat-s3c/regs-watchdog.h>
+#include <plat/regs-watchdog.h>
 
 /* working in physical space... */
 #undef S3C2410_WDOGREG
diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c
index 3098736c65d9..3d4837021ac7 100644
--- a/arch/arm/plat-s3c24xx/common-smdk.c
+++ b/arch/arm/plat-s3c24xx/common-smdk.c
@@ -38,7 +38,7 @@
 #include <mach/regs-gpio.h>
 #include <mach/leds-gpio.h>
 
-#include <asm/plat-s3c/nand.h>
+#include <plat/nand.h>
 
 #include <plat/common-smdk.h>
 #include <plat/devs.h>
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
index e93f8bf6d338..adf535aaf43a 100644
--- a/arch/arm/plat-s3c24xx/devs.c
+++ b/arch/arm/plat-s3c24xx/devs.c
@@ -29,11 +29,11 @@
 #include <asm/irq.h>
 
 #include <plat/regs-serial.h>
-#include <asm/plat-s3c24xx/udc.h>
+#include <plat/udc.h>
 
 #include <plat/devs.h>
 #include <plat/cpu.h>
-#include <asm/plat-s3c24xx/regs-spi.h>
+#include <plat/regs-spi.h>
 
 /* Serial port registrations */
 
diff --git a/arch/arm/plat-s3c24xx/include/plat/mci.h b/arch/arm/plat-s3c24xx/include/plat/mci.h
new file mode 100644
index 000000000000..2d0852ac3b27
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/mci.h
@@ -0,0 +1,15 @@
+#ifndef _ARCH_MCI_H
+#define _ARCH_MCI_H
+
+struct s3c24xx_mci_pdata {
+        unsigned int    wprotect_invert : 1;
+        unsigned int    detect_invert : 1;   /* set => detect active high. */
+
+        unsigned int    gpio_detect;
+        unsigned int    gpio_wprotect;
+        unsigned long   ocr_avail;
+        void            (*set_power)(unsigned char power_mode,
+                                     unsigned short vdd);
+};
+
+#endif /* _ARCH_NCI_H */
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-spi.h b/arch/arm/plat-s3c24xx/include/plat/regs-spi.h
new file mode 100644
index 000000000000..2b35479ee35c
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/regs-spi.h
@@ -0,0 +1,82 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-spi.h
+ *
+ * Copyright (c) 2004 Fetron GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 SPI register definition
+*/
+
+#ifndef __ASM_ARCH_REGS_SPI_H
+#define __ASM_ARCH_REGS_SPI_H
+
+#define S3C2410_SPI1    (0x20)
+#define S3C2412_SPI1    (0x100)
+
+#define S3C2410_SPCON   (0x00)
+
+#define S3C2412_SPCON_RXFIFO_RB2        (0<<14)
+#define S3C2412_SPCON_RXFIFO_RB4        (1<<14)
+#define S3C2412_SPCON_RXFIFO_RB12       (2<<14)
+#define S3C2412_SPCON_RXFIFO_RB14       (3<<14)
+#define S3C2412_SPCON_TXFIFO_RB2        (0<<12)
+#define S3C2412_SPCON_TXFIFO_RB4        (1<<12)
+#define S3C2412_SPCON_TXFIFO_RB12       (2<<12)
+#define S3C2412_SPCON_TXFIFO_RB14       (3<<12)
+#define S3C2412_SPCON_RXFIFO_RESET      (1<<11) /* RxFIFO reset */
+#define S3C2412_SPCON_TXFIFO_RESET      (1<<10) /* TxFIFO reset */
+#define S3C2412_SPCON_RXFIFO_EN         (1<<9)  /* RxFIFO Enable */
+#define S3C2412_SPCON_TXFIFO_EN         (1<<8)  /* TxFIFO Enable */
+
+#define S3C2412_SPCON_DIRC_RX     (1<<7)
+
+#define S3C2410_SPCON_SMOD_DMA    (2<<5)        /* DMA mode */
+#define S3C2410_SPCON_SMOD_INT    (1<<5)        /* interrupt mode */
+#define S3C2410_SPCON_SMOD_POLL   (0<<5)        /* polling mode */
+#define S3C2410_SPCON_ENSCK       (1<<4)        /* Enable SCK */
+#define S3C2410_SPCON_MSTR        (1<<3)        /* Master/Slave select
+                                                   0: slave, 1: master */
+#define S3C2410_SPCON_CPOL_HIGH   (1<<2)        /* Clock polarity select */
+#define S3C2410_SPCON_CPOL_LOW    (0<<2)        /* Clock polarity select */
+
+#define S3C2410_SPCON_CPHA_FMTB   (1<<1)        /* Clock Phase Select */
+#define S3C2410_SPCON_CPHA_FMTA   (0<<1)        /* Clock Phase Select */
+
+#define S3C2410_SPCON_TAGD        (1<<0)        /* Tx auto garbage data mode */
+
+
+#define S3C2410_SPSTA    (0x04)
+
+#define S3C2412_SPSTA_RXFIFO_AE         (1<<11)
+#define S3C2412_SPSTA_TXFIFO_AE         (1<<10)
+#define S3C2412_SPSTA_RXFIFO_ERROR      (1<<9)
+#define S3C2412_SPSTA_TXFIFO_ERROR      (1<<8)
+#define S3C2412_SPSTA_RXFIFO_FIFO       (1<<7)
+#define S3C2412_SPSTA_RXFIFO_EMPTY      (1<<6)
+#define S3C2412_SPSTA_TXFIFO_NFULL      (1<<5)
+#define S3C2412_SPSTA_TXFIFO_EMPTY      (1<<4)
+
+#define S3C2410_SPSTA_DCOL        (1<<2)        /* Data Collision Error */
+#define S3C2410_SPSTA_MULD        (1<<1)        /* Multi Master Error */
+#define S3C2410_SPSTA_READY       (1<<0)        /* Data Tx/Rx ready */
+#define S3C2412_SPSTA_READY_ORG   (1<<3)
+
+#define S3C2410_SPPIN    (0x08)
+
+#define S3C2410_SPPIN_ENMUL       (1<<2)        /* Multi Master Error detect */
+#define S3C2410_SPPIN_RESERVED    (1<<1)
+#define S3C2400_SPPIN_nCS         (1<<1)        /* SPI Card Select */
+#define S3C2410_SPPIN_KEEP        (1<<0)        /* Master Out keep */
+
+#define S3C2410_SPPRE    (0x0C)
+#define S3C2410_SPTDAT   (0x10)
+#define S3C2410_SPRDAT   (0x14)
+
+#define S3C2412_TXFIFO   (0x18)
+#define S3C2412_RXFIFO   (0x18)
+#define S3C2412_SPFIC    (0x24)
+
+
+#endif /* __ASM_ARCH_REGS_SPI_H */
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-udc.h b/arch/arm/plat-s3c24xx/include/plat/regs-udc.h
new file mode 100644
index 000000000000..f0dd4a41b37b
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/regs-udc.h
@@ -0,0 +1,153 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-udc.h
+ *
+ * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
+ *
+ * This include file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+*/
+
+#ifndef __ASM_ARCH_REGS_UDC_H
+#define __ASM_ARCH_REGS_UDC_H
+
+#define S3C2410_USBDREG(x) (x)
+
+#define S3C2410_UDC_FUNC_ADDR_REG       S3C2410_USBDREG(0x0140)
+#define S3C2410_UDC_PWR_REG             S3C2410_USBDREG(0x0144)
+#define S3C2410_UDC_EP_INT_REG          S3C2410_USBDREG(0x0148)
+
+#define S3C2410_UDC_USB_INT_REG         S3C2410_USBDREG(0x0158)
+#define S3C2410_UDC_EP_INT_EN_REG       S3C2410_USBDREG(0x015c)
+
+#define S3C2410_UDC_USB_INT_EN_REG      S3C2410_USBDREG(0x016c)
+
+#define S3C2410_UDC_FRAME_NUM1_REG      S3C2410_USBDREG(0x0170)
+#define S3C2410_UDC_FRAME_NUM2_REG      S3C2410_USBDREG(0x0174)
+
+#define S3C2410_UDC_EP0_FIFO_REG        S3C2410_USBDREG(0x01c0)
+#define S3C2410_UDC_EP1_FIFO_REG        S3C2410_USBDREG(0x01c4)
+#define S3C2410_UDC_EP2_FIFO_REG        S3C2410_USBDREG(0x01c8)
+#define S3C2410_UDC_EP3_FIFO_REG        S3C2410_USBDREG(0x01cc)
+#define S3C2410_UDC_EP4_FIFO_REG        S3C2410_USBDREG(0x01d0)
+
+#define S3C2410_UDC_EP1_DMA_CON         S3C2410_USBDREG(0x0200)
+#define S3C2410_UDC_EP1_DMA_UNIT        S3C2410_USBDREG(0x0204)
+#define S3C2410_UDC_EP1_DMA_FIFO        S3C2410_USBDREG(0x0208)
+#define S3C2410_UDC_EP1_DMA_TTC_L       S3C2410_USBDREG(0x020c)
+#define S3C2410_UDC_EP1_DMA_TTC_M       S3C2410_USBDREG(0x0210)
+#define S3C2410_UDC_EP1_DMA_TTC_H       S3C2410_USBDREG(0x0214)
+
+#define S3C2410_UDC_EP2_DMA_CON         S3C2410_USBDREG(0x0218)
+#define S3C2410_UDC_EP2_DMA_UNIT        S3C2410_USBDREG(0x021c)
+#define S3C2410_UDC_EP2_DMA_FIFO        S3C2410_USBDREG(0x0220)
+#define S3C2410_UDC_EP2_DMA_TTC_L       S3C2410_USBDREG(0x0224)
+#define S3C2410_UDC_EP2_DMA_TTC_M       S3C2410_USBDREG(0x0228)
+#define S3C2410_UDC_EP2_DMA_TTC_H       S3C2410_USBDREG(0x022c)
+
+#define S3C2410_UDC_EP3_DMA_CON         S3C2410_USBDREG(0x0240)
+#define S3C2410_UDC_EP3_DMA_UNIT        S3C2410_USBDREG(0x0244)
+#define S3C2410_UDC_EP3_DMA_FIFO        S3C2410_USBDREG(0x0248)
+#define S3C2410_UDC_EP3_DMA_TTC_L       S3C2410_USBDREG(0x024c)
+#define S3C2410_UDC_EP3_DMA_TTC_M       S3C2410_USBDREG(0x0250)
+#define S3C2410_UDC_EP3_DMA_TTC_H       S3C2410_USBDREG(0x0254)
+
+#define S3C2410_UDC_EP4_DMA_CON         S3C2410_USBDREG(0x0258)
+#define S3C2410_UDC_EP4_DMA_UNIT        S3C2410_USBDREG(0x025c)
+#define S3C2410_UDC_EP4_DMA_FIFO        S3C2410_USBDREG(0x0260)
+#define S3C2410_UDC_EP4_DMA_TTC_L       S3C2410_USBDREG(0x0264)
+#define S3C2410_UDC_EP4_DMA_TTC_M       S3C2410_USBDREG(0x0268)
+#define S3C2410_UDC_EP4_DMA_TTC_H       S3C2410_USBDREG(0x026c)
+
+#define S3C2410_UDC_INDEX_REG           S3C2410_USBDREG(0x0178)
+
+/* indexed registers */
+
+#define S3C2410_UDC_MAXP_REG            S3C2410_USBDREG(0x0180)
+
+#define S3C2410_UDC_EP0_CSR_REG         S3C2410_USBDREG(0x0184)
+
+#define S3C2410_UDC_IN_CSR1_REG         S3C2410_USBDREG(0x0184)
+#define S3C2410_UDC_IN_CSR2_REG         S3C2410_USBDREG(0x0188)
+
+#define S3C2410_UDC_OUT_CSR1_REG        S3C2410_USBDREG(0x0190)
+#define S3C2410_UDC_OUT_CSR2_REG        S3C2410_USBDREG(0x0194)
+#define S3C2410_UDC_OUT_FIFO_CNT1_REG   S3C2410_USBDREG(0x0198)
+#define S3C2410_UDC_OUT_FIFO_CNT2_REG   S3C2410_USBDREG(0x019c)
+
+#define S3C2410_UDC_FUNCADDR_UPDATE     (1<<7)
+
+#define S3C2410_UDC_PWR_ISOUP           (1<<7) // R/W
+#define S3C2410_UDC_PWR_RESET           (1<<3) // R
+#define S3C2410_UDC_PWR_RESUME          (1<<2) // R/W
+#define S3C2410_UDC_PWR_SUSPEND         (1<<1) // R
+#define S3C2410_UDC_PWR_ENSUSPEND       (1<<0) // R/W
+
+#define S3C2410_UDC_PWR_DEFAULT         0x00
+
+#define S3C2410_UDC_INT_EP4             (1<<4) // R/W (clear only)
+#define S3C2410_UDC_INT_EP3             (1<<3) // R/W (clear only)
+#define S3C2410_UDC_INT_EP2             (1<<2) // R/W (clear only)
+#define S3C2410_UDC_INT_EP1             (1<<1) // R/W (clear only)
+#define S3C2410_UDC_INT_EP0             (1<<0) // R/W (clear only)
+
+#define S3C2410_UDC_USBINT_RESET        (1<<2) // R/W (clear only)
+#define S3C2410_UDC_USBINT_RESUME       (1<<1) // R/W (clear only)
+#define S3C2410_UDC_USBINT_SUSPEND      (1<<0) // R/W (clear only)
+
+#define S3C2410_UDC_INTE_EP4            (1<<4) // R/W
+#define S3C2410_UDC_INTE_EP3            (1<<3) // R/W
+#define S3C2410_UDC_INTE_EP2            (1<<2) // R/W
+#define S3C2410_UDC_INTE_EP1            (1<<1) // R/W
+#define S3C2410_UDC_INTE_EP0            (1<<0) // R/W
+
+#define S3C2410_UDC_USBINTE_RESET       (1<<2) // R/W
+#define S3C2410_UDC_USBINTE_SUSPEND     (1<<0) // R/W
+
+
+#define S3C2410_UDC_INDEX_EP0           (0x00)
+#define S3C2410_UDC_INDEX_EP1           (0x01) // ??
+#define S3C2410_UDC_INDEX_EP2           (0x02) // ??
+#define S3C2410_UDC_INDEX_EP3           (0x03) // ??
+#define S3C2410_UDC_INDEX_EP4           (0x04) // ??
+
+#define S3C2410_UDC_ICSR1_CLRDT         (1<<6) // R/W
+#define S3C2410_UDC_ICSR1_SENTSTL       (1<<5) // R/W (clear only)
+#define S3C2410_UDC_ICSR1_SENDSTL       (1<<4) // R/W
+#define S3C2410_UDC_ICSR1_FFLUSH        (1<<3) // W   (set only)
+#define S3C2410_UDC_ICSR1_UNDRUN        (1<<2) // R/W (clear only)
+#define S3C2410_UDC_ICSR1_PKTRDY        (1<<0) // R/W (set only)
+
+#define S3C2410_UDC_ICSR2_AUTOSET       (1<<7) // R/W
+#define S3C2410_UDC_ICSR2_ISO           (1<<6) // R/W
+#define S3C2410_UDC_ICSR2_MODEIN        (1<<5) // R/W
+#define S3C2410_UDC_ICSR2_DMAIEN        (1<<4) // R/W
+
+#define S3C2410_UDC_OCSR1_CLRDT         (1<<7) // R/W
+#define S3C2410_UDC_OCSR1_SENTSTL       (1<<6) // R/W (clear only)
+#define S3C2410_UDC_OCSR1_SENDSTL       (1<<5) // R/W
+#define S3C2410_UDC_OCSR1_FFLUSH        (1<<4) // R/W
+#define S3C2410_UDC_OCSR1_DERROR        (1<<3) // R
+#define S3C2410_UDC_OCSR1_OVRRUN        (1<<2) // R/W (clear only)
+#define S3C2410_UDC_OCSR1_PKTRDY        (1<<0) // R/W (clear only)
+
+#define S3C2410_UDC_OCSR2_AUTOCLR       (1<<7) // R/W
+#define S3C2410_UDC_OCSR2_ISO           (1<<6) // R/W
+#define S3C2410_UDC_OCSR2_DMAIEN        (1<<5) // R/W
+
+#define S3C2410_UDC_EP0_CSR_OPKRDY      (1<<0)
+#define S3C2410_UDC_EP0_CSR_IPKRDY      (1<<1)
+#define S3C2410_UDC_EP0_CSR_SENTSTL     (1<<2)
+#define S3C2410_UDC_EP0_CSR_DE          (1<<3)
+#define S3C2410_UDC_EP0_CSR_SE          (1<<4)
+#define S3C2410_UDC_EP0_CSR_SENDSTL     (1<<5)
+#define S3C2410_UDC_EP0_CSR_SOPKTRDY    (1<<6)
+#define S3C2410_UDC_EP0_CSR_SSE (1<<7)
+
+#define S3C2410_UDC_MAXP_8              (1<<0)
+#define S3C2410_UDC_MAXP_16             (1<<1)
+#define S3C2410_UDC_MAXP_32             (1<<2)
+#define S3C2410_UDC_MAXP_64             (1<<3)
+
+
+#endif
diff --git a/arch/arm/plat-s3c24xx/include/plat/udc.h b/arch/arm/plat-s3c24xx/include/plat/udc.h
new file mode 100644
index 000000000000..546bb4008f49
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/udc.h
@@ -0,0 +1,36 @@
+/* arch/arm/mach-s3c2410/include/mach/udc.h
+ *
+ * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *
+ *  Changelog:
+ *      14-Mar-2005     RTP     Created file
+ *      02-Aug-2005     RTP     File rename
+ *      07-Sep-2005     BJD     Minor cleanups, changed cmd to enum
+ *      18-Jan-2007     HMW     Add per-platform vbus_draw function
+*/
+
+#ifndef __ASM_ARM_ARCH_UDC_H
+#define __ASM_ARM_ARCH_UDC_H
+
+enum s3c2410_udc_cmd_e {
+        S3C2410_UDC_P_ENABLE    = 1,    /* Pull-up enable        */
+        S3C2410_UDC_P_DISABLE   = 2,    /* Pull-up disable       */
+        S3C2410_UDC_P_RESET     = 3,    /* UDC reset, in case of */
+};
+
+struct s3c2410_udc_mach_info {
+        void    (*udc_command)(enum s3c2410_udc_cmd_e);
+        void    (*vbus_draw)(unsigned int ma);
+        unsigned int vbus_pin;
+        unsigned char vbus_pin_inverted;
+};
+
+extern void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *);
+
+#endif /* __ASM_ARM_ARCH_UDC_H */