Merge branch 'ioat-md-accel-for-linus' of git://lost.foo-projects.org/~dwillia2/git/iop

* 'ioat-md-accel-for-linus' of git://lost.foo-projects.org/~dwillia2/git/iop: (28 commits)
  ioatdma: add the unisys "i/oat" pci vendor/device id
  ARM: Add drivers/dma to arch/arm/Kconfig
  iop3xx: surface the iop3xx DMA and AAU units to the iop-adma driver
  iop13xx: surface the iop13xx adma units to the iop-adma driver
  dmaengine: driver for the iop32x, iop33x, and iop13xx raid engines
  md: remove raid5 compute_block and compute_parity5
  md: handle_stripe5 - request io processing in raid5_run_ops
  md: handle_stripe5 - add request/completion logic for async expand ops
  md: handle_stripe5 - add request/completion logic for async read ops
  md: handle_stripe5 - add request/completion logic for async check ops
  md: handle_stripe5 - add request/completion logic for async compute ops
  md: handle_stripe5 - add request/completion logic for async write ops
  md: common infrastructure for running operations with raid5_run_ops
  md: raid5_run_ops - run stripe operations outside sh->lock
  raid5: replace custom debug PRINTKs with standard pr_debug
  raid5: refactor handle_stripe5 and handle_stripe6 (v3)
  async_tx: add the async_tx api
  xor: make 'xor_blocks' a library routine for use with async_tx
  dmaengine: make clients responsible for managing channels
  dmaengine: refactor dmaengine around dma_async_tx_descriptor
  ...

10 files changed, 445 insertions, 3 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b53e1d4bc486..a44c6da9bf83 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1042,6 +1042,8 @@ source "drivers/mmc/Kconfig"
 
 source "drivers/rtc/Kconfig"
 
+source "drivers/dma/Kconfig"
+
 endmenu
 
 source "fs/Kconfig"
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c
index bc4871553f6a..bfe0c87e3397 100644
--- a/arch/arm/mach-iop13xx/setup.c
+++ b/arch/arm/mach-iop13xx/setup.c
@@ -25,6 +25,7 @@
 #include <asm/hardware.h>
 #include <asm/irq.h>
 #include <asm/io.h>
+#include <asm/hardware/iop_adma.h>
 
 #define IOP13XX_UART_XTAL 33334000
 #define IOP13XX_SETUP_DEBUG 0
@@ -236,19 +237,143 @@ static unsigned long iq8134x_probe_flash_size(void)
 }
 #endif
 
+/* ADMA Channels */
+static struct resource iop13xx_adma_0_resources[] = {
+        [0] = {
+                .start = IOP13XX_ADMA_PHYS_BASE(0),
+                .end = IOP13XX_ADMA_UPPER_PA(0),
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_IOP13XX_ADMA0_EOT,
+                .end = IRQ_IOP13XX_ADMA0_EOT,
+                .flags = IORESOURCE_IRQ
+        },
+        [2] = {
+                .start = IRQ_IOP13XX_ADMA0_EOC,
+                .end = IRQ_IOP13XX_ADMA0_EOC,
+                .flags = IORESOURCE_IRQ
+        },
+        [3] = {
+                .start = IRQ_IOP13XX_ADMA0_ERR,
+                .end = IRQ_IOP13XX_ADMA0_ERR,
+                .flags = IORESOURCE_IRQ
+        }
+};
+
+static struct resource iop13xx_adma_1_resources[] = {
+        [0] = {
+                .start = IOP13XX_ADMA_PHYS_BASE(1),
+                .end = IOP13XX_ADMA_UPPER_PA(1),
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_IOP13XX_ADMA1_EOT,
+                .end = IRQ_IOP13XX_ADMA1_EOT,
+                .flags = IORESOURCE_IRQ
+        },
+        [2] = {
+                .start = IRQ_IOP13XX_ADMA1_EOC,
+                .end = IRQ_IOP13XX_ADMA1_EOC,
+                .flags = IORESOURCE_IRQ
+        },
+        [3] = {
+                .start = IRQ_IOP13XX_ADMA1_ERR,
+                .end = IRQ_IOP13XX_ADMA1_ERR,
+                .flags = IORESOURCE_IRQ
+        }
+};
+
+static struct resource iop13xx_adma_2_resources[] = {
+        [0] = {
+                .start = IOP13XX_ADMA_PHYS_BASE(2),
+                .end = IOP13XX_ADMA_UPPER_PA(2),
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_IOP13XX_ADMA2_EOT,
+                .end = IRQ_IOP13XX_ADMA2_EOT,
+                .flags = IORESOURCE_IRQ
+        },
+        [2] = {
+                .start = IRQ_IOP13XX_ADMA2_EOC,
+                .end = IRQ_IOP13XX_ADMA2_EOC,
+                .flags = IORESOURCE_IRQ
+        },
+        [3] = {
+                .start = IRQ_IOP13XX_ADMA2_ERR,
+                .end = IRQ_IOP13XX_ADMA2_ERR,
+                .flags = IORESOURCE_IRQ
+        }
+};
+
+static u64 iop13xx_adma_dmamask = DMA_64BIT_MASK;
+static struct iop_adma_platform_data iop13xx_adma_0_data = {
+        .hw_id = 0,
+        .pool_size = PAGE_SIZE,
+};
+
+static struct iop_adma_platform_data iop13xx_adma_1_data = {
+        .hw_id = 1,
+        .pool_size = PAGE_SIZE,
+};
+
+static struct iop_adma_platform_data iop13xx_adma_2_data = {
+        .hw_id = 2,
+        .pool_size = PAGE_SIZE,
+};
+
+/* The ids are fixed up later in iop13xx_platform_init */
+static struct platform_device iop13xx_adma_0_channel = {
+        .name = "iop-adma",
+        .id = 0,
+        .num_resources = 4,
+        .resource = iop13xx_adma_0_resources,
+        .dev = {
+                .dma_mask = &iop13xx_adma_dmamask,
+                .coherent_dma_mask = DMA_64BIT_MASK,
+                .platform_data = (void *) &iop13xx_adma_0_data,
+        },
+};
+
+static struct platform_device iop13xx_adma_1_channel = {
+        .name = "iop-adma",
+        .id = 0,
+        .num_resources = 4,
+        .resource = iop13xx_adma_1_resources,
+        .dev = {
+                .dma_mask = &iop13xx_adma_dmamask,
+                .coherent_dma_mask = DMA_64BIT_MASK,
+                .platform_data = (void *) &iop13xx_adma_1_data,
+        },
+};
+
+static struct platform_device iop13xx_adma_2_channel = {
+        .name = "iop-adma",
+        .id = 0,
+        .num_resources = 4,
+        .resource = iop13xx_adma_2_resources,
+        .dev = {
+                .dma_mask = &iop13xx_adma_dmamask,
+                .coherent_dma_mask = DMA_64BIT_MASK,
+                .platform_data = (void *) &iop13xx_adma_2_data,
+        },
+};
+
 void __init iop13xx_map_io(void)
 {
         /* Initialize the Static Page Table maps */
         iotable_init(iop13xx_std_desc, ARRAY_SIZE(iop13xx_std_desc));
 }
 
-static int init_uart = 0;
-static int init_i2c = 0;
+static int init_uart;
+static int init_i2c;
+static int init_adma;
 
 void __init iop13xx_platform_init(void)
 {
         int i;
-        u32 uart_idx, i2c_idx, plat_idx;
+        u32 uart_idx, i2c_idx, adma_idx, plat_idx;
         struct platform_device *iop13xx_devices[IQ81340_MAX_PLAT_DEVICES];
 
         /* set the bases so we can read the device id */
@@ -294,6 +419,12 @@ void __init iop13xx_platform_init(void)
                 }
         }
 
+        if (init_adma == IOP13XX_INIT_ADMA_DEFAULT) {
+                init_adma |= IOP13XX_INIT_ADMA_0;
+                init_adma |= IOP13XX_INIT_ADMA_1;
+                init_adma |= IOP13XX_INIT_ADMA_2;
+        }
+
         plat_idx = 0;
         uart_idx = 0;
         i2c_idx = 0;
@@ -332,6 +463,56 @@ void __init iop13xx_platform_init(void)
                 }
         }
 
+        /* initialize adma channel ids and capabilities */
+        adma_idx = 0;
+        for (i = 0; i < IQ81340_NUM_ADMA; i++) {
+                struct iop_adma_platform_data *plat_data;
+                if ((init_adma & (1 << i)) && IOP13XX_SETUP_DEBUG)
+                        printk(KERN_INFO
+                                "Adding adma%d to platform device list\n", i);
+                switch (init_adma & (1 << i)) {
+                case IOP13XX_INIT_ADMA_0:
+                        iop13xx_adma_0_channel.id = adma_idx++;
+                        iop13xx_devices[plat_idx++] = &iop13xx_adma_0_channel;
+                        plat_data = &iop13xx_adma_0_data;
+                        dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
+                        dma_cap_set(DMA_XOR, plat_data->cap_mask);
+                        dma_cap_set(DMA_DUAL_XOR, plat_data->cap_mask);
+                        dma_cap_set(DMA_ZERO_SUM, plat_data->cap_mask);
+                        dma_cap_set(DMA_MEMSET, plat_data->cap_mask);
+                        dma_cap_set(DMA_MEMCPY_CRC32C, plat_data->cap_mask);
+                        dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
+                        break;
+                case IOP13XX_INIT_ADMA_1:
+                        iop13xx_adma_1_channel.id = adma_idx++;
+                        iop13xx_devices[plat_idx++] = &iop13xx_adma_1_channel;
+                        plat_data = &iop13xx_adma_1_data;
+                        dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
+                        dma_cap_set(DMA_XOR, plat_data->cap_mask);
+                        dma_cap_set(DMA_DUAL_XOR, plat_data->cap_mask);
+                        dma_cap_set(DMA_ZERO_SUM, plat_data->cap_mask);
+                        dma_cap_set(DMA_MEMSET, plat_data->cap_mask);
+                        dma_cap_set(DMA_MEMCPY_CRC32C, plat_data->cap_mask);
+                        dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
+                        break;
+                case IOP13XX_INIT_ADMA_2:
+                        iop13xx_adma_2_channel.id = adma_idx++;
+                        iop13xx_devices[plat_idx++] = &iop13xx_adma_2_channel;
+                        plat_data = &iop13xx_adma_2_data;
+                        dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
+                        dma_cap_set(DMA_XOR, plat_data->cap_mask);
+                        dma_cap_set(DMA_DUAL_XOR, plat_data->cap_mask);
+                        dma_cap_set(DMA_ZERO_SUM, plat_data->cap_mask);
+                        dma_cap_set(DMA_MEMSET, plat_data->cap_mask);
+                        dma_cap_set(DMA_MEMCPY_CRC32C, plat_data->cap_mask);
+                        dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
+                        dma_cap_set(DMA_PQ_XOR, plat_data->cap_mask);
+                        dma_cap_set(DMA_PQ_UPDATE, plat_data->cap_mask);
+                        dma_cap_set(DMA_PQ_ZERO_SUM, plat_data->cap_mask);
+                        break;
+                }
+        }
+
 #ifdef CONFIG_MTD_PHYSMAP
         iq8134x_flash_resource.end = iq8134x_flash_resource.start +
                                 iq8134x_probe_flash_size() - 1;
@@ -399,5 +580,35 @@ static int __init iop13xx_init_i2c_setup(char *str)
         return 1;
 }
 
+static int __init iop13xx_init_adma_setup(char *str)
+{
+        if (str)        {
+                while (*str != '\0') {
+                        switch (*str) {
+                        case '0':
+                                init_adma |= IOP13XX_INIT_ADMA_0;
+                                break;
+                        case '1':
+                                init_adma |= IOP13XX_INIT_ADMA_1;
+                                break;
+                        case '2':
+                                init_adma |= IOP13XX_INIT_ADMA_2;
+                                break;
+                        case ',':
+                        case '=':
+                                break;
+                        default:
+                                PRINTK("\"iop13xx_init_adma\" malformed"
+                                            " at character: \'%c\'", *str);
+                                *(str + 1) = '\0';
+                                init_adma = IOP13XX_INIT_ADMA_DEFAULT;
+                        }
+                        str++;
+                }
+        }
+        return 1;
+}
+
+__setup("iop13xx_init_adma", iop13xx_init_adma_setup);
 __setup("iop13xx_init_uart", iop13xx_init_uart_setup);
 __setup("iop13xx_init_i2c", iop13xx_init_i2c_setup);
diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c
index 5776fd884115..2b086ab2668c 100644
--- a/arch/arm/mach-iop32x/glantank.c
+++ b/arch/arm/mach-iop32x/glantank.c
@@ -180,6 +180,8 @@ static void __init glantank_init_machine(void)
         platform_device_register(&iop3xx_i2c1_device);
         platform_device_register(&glantank_flash_device);
         platform_device_register(&glantank_serial_device);
+        platform_device_register(&iop3xx_dma_0_channel);
+        platform_device_register(&iop3xx_dma_1_channel);
 
         pm_power_off = glantank_power_off;
 }
diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c
index d4eefbea1fe6..98cfa1cd6bdb 100644
--- a/arch/arm/mach-iop32x/iq31244.c
+++ b/arch/arm/mach-iop32x/iq31244.c
@@ -298,9 +298,14 @@ static void __init iq31244_init_machine(void)
         platform_device_register(&iop3xx_i2c1_device);
         platform_device_register(&iq31244_flash_device);
         platform_device_register(&iq31244_serial_device);
+        platform_device_register(&iop3xx_dma_0_channel);
+        platform_device_register(&iop3xx_dma_1_channel);
 
         if (is_ep80219())
                 pm_power_off = ep80219_power_off;
+
+        if (!is_80219())
+                platform_device_register(&iop3xx_aau_channel);
 }
 
 static int __init force_ep80219_setup(char *str)
diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c
index 8d9f49164a84..18ad29f213b2 100644
--- a/arch/arm/mach-iop32x/iq80321.c
+++ b/arch/arm/mach-iop32x/iq80321.c
@@ -181,6 +181,9 @@ static void __init iq80321_init_machine(void)
         platform_device_register(&iop3xx_i2c1_device);
         platform_device_register(&iq80321_flash_device);
         platform_device_register(&iq80321_serial_device);
+        platform_device_register(&iop3xx_dma_0_channel);
+        platform_device_register(&iop3xx_dma_1_channel);
+        platform_device_register(&iop3xx_aau_channel);
 }
 
 MACHINE_START(IQ80321, "Intel IQ80321")
diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c
index d55005d64781..390a97d39e5a 100644
--- a/arch/arm/mach-iop32x/n2100.c
+++ b/arch/arm/mach-iop32x/n2100.c
@@ -245,6 +245,8 @@ static void __init n2100_init_machine(void)
         platform_device_register(&iop3xx_i2c0_device);
         platform_device_register(&n2100_flash_device);
         platform_device_register(&n2100_serial_device);
+        platform_device_register(&iop3xx_dma_0_channel);
+        platform_device_register(&iop3xx_dma_1_channel);
 
         pm_power_off = n2100_power_off;
 
diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c
index 2b063180687a..433188ebff2a 100644
--- a/arch/arm/mach-iop33x/iq80331.c
+++ b/arch/arm/mach-iop33x/iq80331.c
@@ -136,6 +136,9 @@ static void __init iq80331_init_machine(void)
         platform_device_register(&iop33x_uart0_device);
         platform_device_register(&iop33x_uart1_device);
         platform_device_register(&iq80331_flash_device);
+        platform_device_register(&iop3xx_dma_0_channel);
+        platform_device_register(&iop3xx_dma_1_channel);
+        platform_device_register(&iop3xx_aau_channel);
 }
 
 MACHINE_START(IQ80331, "Intel IQ80331")
diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c
index 7889ce3cb08e..416c09564cc6 100644
--- a/arch/arm/mach-iop33x/iq80332.c
+++ b/arch/arm/mach-iop33x/iq80332.c
@@ -136,6 +136,9 @@ static void __init iq80332_init_machine(void)
         platform_device_register(&iop33x_uart0_device);
         platform_device_register(&iop33x_uart1_device);
         platform_device_register(&iq80332_flash_device);
+        platform_device_register(&iop3xx_dma_0_channel);
+        platform_device_register(&iop3xx_dma_1_channel);
+        platform_device_register(&iop3xx_aau_channel);
 }
 
 MACHINE_START(IQ80332, "Intel IQ80332")
diff --git a/arch/arm/plat-iop/Makefile b/arch/arm/plat-iop/Makefile
index 4d2b1da3cd82..36bff0325959 100644
--- a/arch/arm/plat-iop/Makefile
+++ b/arch/arm/plat-iop/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_IOP32X) += setup.o
 obj-$(CONFIG_ARCH_IOP32X) += time.o
 obj-$(CONFIG_ARCH_IOP32X) += io.o
 obj-$(CONFIG_ARCH_IOP32X) += cp6.o
+obj-$(CONFIG_ARCH_IOP32X) += adma.o
 
 # IOP33X
 obj-$(CONFIG_ARCH_IOP33X) += gpio.o
@@ -21,6 +22,7 @@ obj-$(CONFIG_ARCH_IOP33X) += setup.o
 obj-$(CONFIG_ARCH_IOP33X) += time.o
 obj-$(CONFIG_ARCH_IOP33X) += io.o
 obj-$(CONFIG_ARCH_IOP33X) += cp6.o
+obj-$(CONFIG_ARCH_IOP33X) += adma.o
 
 # IOP13XX
 obj-$(CONFIG_ARCH_IOP13XX) += cp6.o
diff --git a/arch/arm/plat-iop/adma.c b/arch/arm/plat-iop/adma.c
new file mode 100644
index 000000000000..53c5e9a52eb1
--- /dev/null
+++ b/arch/arm/plat-iop/adma.c
@@ -0,0 +1,209 @@
+/*
+ * platform device definitions for the iop3xx dma/xor engines
+ * Copyright © 2006, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+#include <linux/platform_device.h>
+#include <asm/hardware/iop3xx.h>
+#include <linux/dma-mapping.h>
+#include <asm/arch/adma.h>
+#include <asm/hardware/iop_adma.h>
+
+#ifdef CONFIG_ARCH_IOP32X
+#define IRQ_DMA0_EOT IRQ_IOP32X_DMA0_EOT
+#define IRQ_DMA0_EOC IRQ_IOP32X_DMA0_EOC
+#define IRQ_DMA0_ERR IRQ_IOP32X_DMA0_ERR
+
+#define IRQ_DMA1_EOT IRQ_IOP32X_DMA1_EOT
+#define IRQ_DMA1_EOC IRQ_IOP32X_DMA1_EOC
+#define IRQ_DMA1_ERR IRQ_IOP32X_DMA1_ERR
+
+#define IRQ_AA_EOT IRQ_IOP32X_AA_EOT
+#define IRQ_AA_EOC IRQ_IOP32X_AA_EOC
+#define IRQ_AA_ERR IRQ_IOP32X_AA_ERR
+#endif
+#ifdef CONFIG_ARCH_IOP33X
+#define IRQ_DMA0_EOT IRQ_IOP33X_DMA0_EOT
+#define IRQ_DMA0_EOC IRQ_IOP33X_DMA0_EOC
+#define IRQ_DMA0_ERR IRQ_IOP33X_DMA0_ERR
+
+#define IRQ_DMA1_EOT IRQ_IOP33X_DMA1_EOT
+#define IRQ_DMA1_EOC IRQ_IOP33X_DMA1_EOC
+#define IRQ_DMA1_ERR IRQ_IOP33X_DMA1_ERR
+
+#define IRQ_AA_EOT IRQ_IOP33X_AA_EOT
+#define IRQ_AA_EOC IRQ_IOP33X_AA_EOC
+#define IRQ_AA_ERR IRQ_IOP33X_AA_ERR
+#endif
+/* AAU and DMA Channels */
+static struct resource iop3xx_dma_0_resources[] = {
+        [0] = {
+                .start = IOP3XX_DMA_PHYS_BASE(0),
+                .end = IOP3XX_DMA_UPPER_PA(0),
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_DMA0_EOT,
+                .end = IRQ_DMA0_EOT,
+                .flags = IORESOURCE_IRQ
+        },
+        [2] = {
+                .start = IRQ_DMA0_EOC,
+                .end = IRQ_DMA0_EOC,
+                .flags = IORESOURCE_IRQ
+        },
+        [3] = {
+                .start = IRQ_DMA0_ERR,
+                .end = IRQ_DMA0_ERR,
+                .flags = IORESOURCE_IRQ
+        }
+};
+
+static struct resource iop3xx_dma_1_resources[] = {
+        [0] = {
+                .start = IOP3XX_DMA_PHYS_BASE(1),
+                .end = IOP3XX_DMA_UPPER_PA(1),
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_DMA1_EOT,
+                .end = IRQ_DMA1_EOT,
+                .flags = IORESOURCE_IRQ
+        },
+        [2] = {
+                .start = IRQ_DMA1_EOC,
+                .end = IRQ_DMA1_EOC,
+                .flags = IORESOURCE_IRQ
+        },
+        [3] = {
+                .start = IRQ_DMA1_ERR,
+                .end = IRQ_DMA1_ERR,
+                .flags = IORESOURCE_IRQ
+        }
+};
+
+
+static struct resource iop3xx_aau_resources[] = {
+        [0] = {
+                .start = IOP3XX_AAU_PHYS_BASE,
+                .end = IOP3XX_AAU_UPPER_PA,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_AA_EOT,
+                .end = IRQ_AA_EOT,
+                .flags = IORESOURCE_IRQ
+        },
+        [2] = {
+                .start = IRQ_AA_EOC,
+                .end = IRQ_AA_EOC,
+                .flags = IORESOURCE_IRQ
+        },
+        [3] = {
+                .start = IRQ_AA_ERR,
+                .end = IRQ_AA_ERR,
+                .flags = IORESOURCE_IRQ
+        }
+};
+
+static u64 iop3xx_adma_dmamask = DMA_32BIT_MASK;
+
+static struct iop_adma_platform_data iop3xx_dma_0_data = {
+        .hw_id = DMA0_ID,
+        .pool_size = PAGE_SIZE,
+};
+
+static struct iop_adma_platform_data iop3xx_dma_1_data = {
+        .hw_id = DMA1_ID,
+        .pool_size = PAGE_SIZE,
+};
+
+static struct iop_adma_platform_data iop3xx_aau_data = {
+        .hw_id = AAU_ID,
+        .pool_size = 3 * PAGE_SIZE,
+};
+
+struct platform_device iop3xx_dma_0_channel = {
+        .name = "iop-adma",
+        .id = 0,
+        .num_resources = 4,
+        .resource = iop3xx_dma_0_resources,
+        .dev = {
+                .dma_mask = &iop3xx_adma_dmamask,
+                .coherent_dma_mask = DMA_64BIT_MASK,
+                .platform_data = (void *) &iop3xx_dma_0_data,
+        },
+};
+
+struct platform_device iop3xx_dma_1_channel = {
+        .name = "iop-adma",
+        .id = 1,
+        .num_resources = 4,
+        .resource = iop3xx_dma_1_resources,
+        .dev = {
+                .dma_mask = &iop3xx_adma_dmamask,
+                .coherent_dma_mask = DMA_64BIT_MASK,
+                .platform_data = (void *) &iop3xx_dma_1_data,
+        },
+};
+
+struct platform_device iop3xx_aau_channel = {
+        .name = "iop-adma",
+        .id = 2,
+        .num_resources = 4,
+        .resource = iop3xx_aau_resources,
+        .dev = {
+                .dma_mask = &iop3xx_adma_dmamask,
+                .coherent_dma_mask = DMA_64BIT_MASK,
+                .platform_data = (void *) &iop3xx_aau_data,
+        },
+};
+
+static int __init iop3xx_adma_cap_init(void)
+{
+        #ifdef CONFIG_ARCH_IOP32X /* the 32x DMA does not perform CRC32C */
+        dma_cap_set(DMA_MEMCPY, iop3xx_dma_0_data.cap_mask);
+        dma_cap_set(DMA_INTERRUPT, iop3xx_dma_0_data.cap_mask);
+        #else
+        dma_cap_set(DMA_MEMCPY, iop3xx_dma_0_data.cap_mask);
+        dma_cap_set(DMA_MEMCPY_CRC32C, iop3xx_dma_0_data.cap_mask);
+        dma_cap_set(DMA_INTERRUPT, iop3xx_dma_0_data.cap_mask);
+        #endif
+
+        #ifdef CONFIG_ARCH_IOP32X /* the 32x DMA does not perform CRC32C */
+        dma_cap_set(DMA_MEMCPY, iop3xx_dma_1_data.cap_mask);
+        dma_cap_set(DMA_INTERRUPT, iop3xx_dma_1_data.cap_mask);
+        #else
+        dma_cap_set(DMA_MEMCPY, iop3xx_dma_1_data.cap_mask);
+        dma_cap_set(DMA_MEMCPY_CRC32C, iop3xx_dma_1_data.cap_mask);
+        dma_cap_set(DMA_INTERRUPT, iop3xx_dma_1_data.cap_mask);
+        #endif
+
+        #ifdef CONFIG_ARCH_IOP32X /* the 32x AAU does not perform zero sum */
+        dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask);
+        dma_cap_set(DMA_MEMSET, iop3xx_aau_data.cap_mask);
+        dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask);
+        #else
+        dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask);
+        dma_cap_set(DMA_ZERO_SUM, iop3xx_aau_data.cap_mask);
+        dma_cap_set(DMA_MEMSET, iop3xx_aau_data.cap_mask);
+        dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask);
+        #endif
+
+        return 0;
+}
+
+arch_initcall(iop3xx_adma_cap_init);