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authorDave Jones <davej@redhat.com>2009-10-14 16:31:39 -0400
committerJesse Barnes <jbarnes@virtuousgeek.org>2009-11-04 11:47:12 -0500
commit76b1a87b217927f905f4b01c586452b2a1d33913 (patch)
tree02a0f0e1a94cdb5507e441a7ff655e9c772d97d4 /arch
parent98e724c791924c0dfc5b1dcf053ed3841cc89c78 (diff)
x86/PCI: Use generic cacheline sizing instead of per-vendor tests.
Instead of the PCI code needing to have code to determine the cacheline size of each processor, use the data the cpu identification code should have already determined during early boot. (The vendor checks are also incomplete, and don't take into account modern CPUs) I've been carrying a variant of this code in Fedora for a while, that prints debug information. There are a number of cases where we are currently setting the PCI cacheline size to 32 bytes, when the CPU cacheline size is 64 bytes. With this patch, we set them both the same. Signed-off-by: Dave Jones <davej@redhat.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/x86/pci/common.c18
1 files changed, 11 insertions, 7 deletions
diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c
index fbeec31316cf..d2552c68e94d 100644
--- a/arch/x86/pci/common.c
+++ b/arch/x86/pci/common.c
@@ -420,15 +420,19 @@ int __init pcibios_init(void)
420 } 420 }
421 421
422 /* 422 /*
423 * Assume PCI cacheline size of 32 bytes for all x86s except K7/K8 423 * Set PCI cacheline size to that of the CPU if the CPU has reported it.
424 * and P4. It's also good for 386/486s (which actually have 16) 424 * (For older CPUs that don't support cpuid, we se it to 32 bytes
425 * It's also good for 386/486s (which actually have 16)
425 * as quite a few PCI devices do not support smaller values. 426 * as quite a few PCI devices do not support smaller values.
426 */ 427 */
427 pci_dfl_cache_line_size = 32 >> 2; 428 if (c->x86_clflush_size > 0) {
428 if (c->x86 >= 6 && c->x86_vendor == X86_VENDOR_AMD) 429 pci_dfl_cache_line_size = c->x86_clflush_size >> 2;
429 pci_dfl_cache_line_size = 64 >> 2; /* K7 & K8 */ 430 printk(KERN_DEBUG "PCI: pci_cache_line_size set to %d bytes\n",
430 else if (c->x86 > 6 && c->x86_vendor == X86_VENDOR_INTEL) 431 pci_dfl_cache_line_size << 2);
431 pci_dfl_cache_line_size = 128 >> 2; /* P4 */ 432 } else {
433 pci_dfl_cache_line_size = 32 >> 2;
434 printk(KERN_DEBUG "PCI: Unknown cacheline size. Setting to 32 bytes\n");
435 }
432 436
433 pcibios_resource_survey(); 437 pcibios_resource_survey();
434 438