Merge branch 'x86/irq' into x86/devel

Conflicts:

	arch/x86/kernel/i8259.c
	arch/x86/kernel/irqinit_64.c

Signed-off-by: Ingo Molnar <mingo@elte.hu>

11 files changed, 275 insertions, 186 deletions

diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
index 33c5216fd3e1..ff1a7b49a460 100644
--- a/arch/x86/kernel/acpi/boot.c
+++ b/arch/x86/kernel/acpi/boot.c
@@ -514,8 +514,6 @@ int acpi_register_gsi(u32 gsi, int triggering, int polarity)
          * Make sure all (legacy) PCI IRQs are set as level-triggered.
          */
         if (acpi_irq_model == ACPI_IRQ_MODEL_PIC) {
-                extern void eisa_set_level_irq(unsigned int irq);
-
                 if (triggering == ACPI_LEVEL_SENSITIVE)
                         eisa_set_level_irq(gsi);
         }
diff --git a/arch/x86/kernel/apic_32.c b/arch/x86/kernel/apic_32.c
index 45d8da405ad9..ce4538ebb7fe 100644
--- a/arch/x86/kernel/apic_32.c
+++ b/arch/x86/kernel/apic_32.c
@@ -70,6 +70,10 @@ static int local_apic_timer_disabled;
 int local_apic_timer_c2_ok;
 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
 
+int first_system_vector = 0xfe;
+
+char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
+
 /*
  * Debug level, exported for io_apic.c
  */
@@ -1351,13 +1355,13 @@ void __init smp_intr_init(void)
          * The reschedule interrupt is a CPU-to-CPU reschedule-helper
          * IPI, driven by wakeup.
          */
-        set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
+        alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
 
         /* IPI for invalidation */
-        set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
+        alloc_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
 
         /* IPI for generic function call */
-        set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
+        alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
 }
 #endif
 
@@ -1370,15 +1374,15 @@ void __init apic_intr_init(void)
         smp_intr_init();
 #endif
         /* self generated IPI for local APIC timer */
-        set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
+        alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
 
         /* IPI vectors for APIC spurious and error interrupts */
-        set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
-        set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
+        alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
+        alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
 
         /* thermal monitor LVT interrupt */
 #ifdef CONFIG_X86_MCE_P4THERMAL
-        set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
+        alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
 #endif
 }
 
diff --git a/arch/x86/kernel/entry_32.S b/arch/x86/kernel/entry_32.S
index c778e4fa55a2..159a1c76d2bd 100644
--- a/arch/x86/kernel/entry_32.S
+++ b/arch/x86/kernel/entry_32.S
@@ -51,7 +51,7 @@
 #include <asm/percpu.h>
 #include <asm/dwarf2.h>
 #include <asm/processor-flags.h>
-#include "irq_vectors.h"
+#include <asm/irq_vectors.h>
 
 /*
  * We use macros for low-level operations which need to be overridden
diff --git a/arch/x86/kernel/genx2apic_uv_x.c b/arch/x86/kernel/genx2apic_uv_x.c
index ebf13908a743..45e84acca8a9 100644
--- a/arch/x86/kernel/genx2apic_uv_x.c
+++ b/arch/x86/kernel/genx2apic_uv_x.c
@@ -5,7 +5,7 @@
  *
  * SGI UV APIC functions (note: not an Intel compatible APIC)
  *
- * Copyright (C) 2007 Silicon Graphics, Inc. All rights reserved.
+ * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/threads.h>
@@ -55,37 +55,37 @@ static cpumask_t uv_vector_allocation_domain(int cpu)
 int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
 {
         unsigned long val;
-        int nasid;
+        int pnode;
 
-        nasid = uv_apicid_to_nasid(phys_apicid);
+        pnode = uv_apicid_to_pnode(phys_apicid);
         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
             (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
             APIC_DM_INIT;
-        uv_write_global_mmr64(nasid, UVH_IPI_INT, val);
+        uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
         mdelay(10);
 
         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
             (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
             APIC_DM_STARTUP;
-        uv_write_global_mmr64(nasid, UVH_IPI_INT, val);
+        uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
         return 0;
 }
 
 static void uv_send_IPI_one(int cpu, int vector)
 {
         unsigned long val, apicid, lapicid;
-        int nasid;
+        int pnode;
 
         apicid = per_cpu(x86_cpu_to_apicid, cpu); /* ZZZ - cache node-local ? */
         lapicid = apicid & 0x3f;                /* ZZZ macro needed */
-        nasid = uv_apicid_to_nasid(apicid);
+        pnode = uv_apicid_to_pnode(apicid);
         val =
             (1UL << UVH_IPI_INT_SEND_SHFT) | (lapicid <<
                                               UVH_IPI_INT_APIC_ID_SHFT) |
             (vector << UVH_IPI_INT_VECTOR_SHFT);
-        uv_write_global_mmr64(nasid, UVH_IPI_INT, val);
+        uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 }
 
 static void uv_send_IPI_mask(cpumask_t mask, int vector)
@@ -159,39 +159,81 @@ struct genapic apic_x2apic_uv_x = {
         .phys_pkg_id = phys_pkg_id,     /* Fixme ZZZ */
 };
 
-static __cpuinit void set_x2apic_extra_bits(int nasid)
+static __cpuinit void set_x2apic_extra_bits(int pnode)
 {
-        __get_cpu_var(x2apic_extra_bits) = ((nasid >> 1) << 6);
+        __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
 }
 
 /*
  * Called on boot cpu.
  */
+static __init int boot_pnode_to_blade(int pnode)
+{
+        int blade;
+
+        for (blade = 0; blade < uv_num_possible_blades(); blade++)
+                if (pnode == uv_blade_info[blade].pnode)
+                        return blade;
+        BUG();
+}
+
+struct redir_addr {
+        unsigned long redirect;
+        unsigned long alias;
+};
+
+#define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
+
+static __initdata struct redir_addr redir_addrs[] = {
+        {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
+        {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
+        {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
+};
+
+static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
+{
+        union uvh_si_alias0_overlay_config_u alias;
+        union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
+                alias.v = uv_read_local_mmr(redir_addrs[i].alias);
+                if (alias.s.base == 0) {
+                        *size = (1UL << alias.s.m_alias);
+                        redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
+                        *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
+                        return;
+                }
+        }
+        BUG();
+}
+
 static __init void uv_system_init(void)
 {
         union uvh_si_addr_map_config_u m_n_config;
-        int bytes, nid, cpu, lcpu, nasid, last_nasid, blade;
-        unsigned long mmr_base;
+        union uvh_node_id_u node_id;
+        unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
+        int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
+        unsigned long mmr_base, present;
 
         m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
+        m_val = m_n_config.s.m_skt;
+        n_val = m_n_config.s.n_skt;
         mmr_base =
             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
             ~UV_MMR_ENABLE;
         printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
 
-        last_nasid = -1;
-        for_each_possible_cpu(cpu) {
-                nid = cpu_to_node(cpu);
-                nasid = uv_apicid_to_nasid(per_cpu(x86_cpu_to_apicid, cpu));
-                if (nasid != last_nasid)
-                        uv_possible_blades++;
-                last_nasid = nasid;
-        }
+        for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
+                uv_possible_blades +=
+                  hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
         printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
 
         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
         uv_blade_info = alloc_bootmem_pages(bytes);
 
+        get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
+
         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
         uv_node_to_blade = alloc_bootmem_pages(bytes);
         memset(uv_node_to_blade, 255, bytes);
@@ -200,43 +242,56 @@ static __init void uv_system_init(void)
         uv_cpu_to_blade = alloc_bootmem_pages(bytes);
         memset(uv_cpu_to_blade, 255, bytes);
 
-        last_nasid = -1;
-        blade = -1;
-        lcpu = -1;
-        for_each_possible_cpu(cpu) {
-                nid = cpu_to_node(cpu);
-                nasid = uv_apicid_to_nasid(per_cpu(x86_cpu_to_apicid, cpu));
-                if (nasid != last_nasid) {
-                        blade++;
-                        lcpu = -1;
-                        uv_blade_info[blade].nr_posible_cpus = 0;
+        blade = 0;
+        for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
+                present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
+                for (j = 0; j < 64; j++) {
+                        if (!test_bit(j, &present))
+                                continue;
+                        uv_blade_info[blade].pnode = (i * 64 + j);
+                        uv_blade_info[blade].nr_possible_cpus = 0;
                         uv_blade_info[blade].nr_online_cpus = 0;
+                        blade++;
                 }
-                last_nasid = nasid;
-                lcpu++;
+        }
 
-                uv_cpu_hub_info(cpu)->m_val = m_n_config.s.m_skt;
-                uv_cpu_hub_info(cpu)->n_val = m_n_config.s.n_skt;
+        node_id.v = uv_read_local_mmr(UVH_NODE_ID);
+        gnode_upper = (((unsigned long)node_id.s.node_id) &
+                       ~((1 << n_val) - 1)) << m_val;
+
+        for_each_present_cpu(cpu) {
+                nid = cpu_to_node(cpu);
+                pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
+                blade = boot_pnode_to_blade(pnode);
+                lcpu = uv_blade_info[blade].nr_possible_cpus;
+                uv_blade_info[blade].nr_possible_cpus++;
+
+                uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
+                uv_cpu_hub_info(cpu)->lowmem_remap_top =
+                                        lowmem_redir_base + lowmem_redir_size;
+                uv_cpu_hub_info(cpu)->m_val = m_val;
+                uv_cpu_hub_info(cpu)->n_val = m_val;
                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
-                uv_cpu_hub_info(cpu)->local_nasid = nasid;
-                uv_cpu_hub_info(cpu)->gnode_upper =
-                    nasid & ~((1 << uv_hub_info->n_val) - 1);
+                uv_cpu_hub_info(cpu)->pnode = pnode;
+                uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
+                uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
+                uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
                 uv_cpu_hub_info(cpu)->coherency_domain_number = 0;/* ZZZ */
-                uv_blade_info[blade].nasid = nasid;
-                uv_blade_info[blade].nr_posible_cpus++;
                 uv_node_to_blade[nid] = blade;
                 uv_cpu_to_blade[cpu] = blade;
 
-                printk(KERN_DEBUG "UV cpu %d, apicid 0x%x, nasid %d, nid %d\n",
-                       cpu, per_cpu(x86_cpu_to_apicid, cpu), nasid, nid);
-                printk(KERN_DEBUG "UV   lcpu %d, blade %d\n", lcpu, blade);
+                printk(KERN_DEBUG "UV cpu %d, apicid 0x%x, pnode %d, nid %d, "
+                        "lcpu %d, blade %d\n",
+                        cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
+                        lcpu, blade);
         }
 }
 
 /*
  * Called on each cpu to initialize the per_cpu UV data area.
+ *      ZZZ hotplug not supported yet
  */
 void __cpuinit uv_cpu_init(void)
 {
@@ -246,5 +301,5 @@ void __cpuinit uv_cpu_init(void)
         uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
 
         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
-                set_x2apic_extra_bits(uv_hub_info->local_nasid);
+                set_x2apic_extra_bits(uv_hub_info->pnode);
 }
diff --git a/arch/x86/kernel/i8259.c b/arch/x86/kernel/i8259.c
index 7a0fda8f01b5..dc92b49d9204 100644
--- a/arch/x86/kernel/i8259.c
+++ b/arch/x86/kernel/i8259.c
@@ -297,34 +297,28 @@ void init_8259A(int auto_eoi)
          * outb_pic - this has to work on a wide range of PC hardware.
          */
         outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
-#ifndef CONFIG_X86_64
-        outb_pic(0x20 + 0, PIC_MASTER_IMR);     /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
-        outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); /* 8259A-1 (the master) has a slave on IR2 */
-#else /* CONFIG_X86_64 */
-        /* ICW2: 8259A-1 IR0-7 mapped to 0x30-0x37 */
+
+        /* ICW2: 8259A-1 IR0-7 mapped to 0x30-0x37 on x86-64,
+                               to 0x20-0x27 on i386 */
         outb_pic(IRQ0_VECTOR, PIC_MASTER_IMR);
+
         /* 8259A-1 (the master) has a slave on IR2 */
-        outb_pic(0x04, PIC_MASTER_IMR);
-#endif /* CONFIG_X86_64 */
+        outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);
+
         if (auto_eoi)   /* master does Auto EOI */
                 outb_pic(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
         else            /* master expects normal EOI */
                 outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
 
         outb_pic(0x11, PIC_SLAVE_CMD);  /* ICW1: select 8259A-2 init */
-#ifndef CONFIG_X86_64
-        outb_pic(0x20 + 8, PIC_SLAVE_IMR);      /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
-        outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);        /* 8259A-2 is a slave on master's IR2 */
-        outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
-#else /* CONFIG_X86_64 */
-        /* ICW2: 8259A-2 IR0-7 mapped to 0x38-0x3f */
+
+        /* ICW2: 8259A-2 IR0-7 mapped to IRQ8_VECTOR */
         outb_pic(IRQ8_VECTOR, PIC_SLAVE_IMR);
         /* 8259A-2 is a slave on master's IR2 */
         outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);
         /* (slave's support for AEOI in flat mode is to be investigated) */
         outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR);
 
-#endif /* CONFIG_X86_64 */
         if (auto_eoi)
                 /*
                  * In AEOI mode we just have to mask the interrupt
diff --git a/arch/x86/kernel/io_apic_32.c b/arch/x86/kernel/io_apic_32.c
index d4f9df2b022a..dac47d61d2be 100644
--- a/arch/x86/kernel/io_apic_32.c
+++ b/arch/x86/kernel/io_apic_32.c
@@ -1174,7 +1174,7 @@ static int __assign_irq_vector(int irq)
         offset = current_offset;
 next:
         vector += 8;
-        if (vector >= FIRST_SYSTEM_VECTOR) {
+        if (vector >= first_system_vector) {
                 offset = (offset + 1) % 8;
                 vector = FIRST_DEVICE_VECTOR + offset;
         }
@@ -2280,7 +2280,7 @@ void __init setup_IO_APIC(void)
         int i;
 
         /* Reserve all the system vectors. */
-        for (i = FIRST_SYSTEM_VECTOR; i < NR_VECTORS; i++)
+        for (i = first_system_vector; i < NR_VECTORS; i++)
                 set_bit(i, used_vectors);
 
         enable_IO_APIC();
diff --git a/arch/x86/kernel/io_apic_64.c b/arch/x86/kernel/io_apic_64.c
index e5ef60303562..78a3866ab367 100644
--- a/arch/x86/kernel/io_apic_64.c
+++ b/arch/x86/kernel/io_apic_64.c
@@ -82,6 +82,10 @@ static struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
 
 static int assign_irq_vector(int irq, cpumask_t mask);
 
+int first_system_vector = 0xfe;
+
+char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
+
 #define __apicdebuginit  __init
 
 int sis_apic_bug; /* not actually supported, dummy for compile */
@@ -737,7 +741,7 @@ static int __assign_irq_vector(int irq, cpumask_t mask)
                 offset = current_offset;
 next:
                 vector += 8;
-                if (vector >= FIRST_SYSTEM_VECTOR) {
+                if (vector >= first_system_vector) {
                         /* If we run out of vectors on large boxen, must share them. */
                         offset = (offset + 1) % 8;
                         vector = FIRST_DEVICE_VECTOR + offset;
diff --git a/arch/x86/kernel/irq_32.c b/arch/x86/kernel/irq_32.c
index 468acd04aa2e..47a6f6f12478 100644
--- a/arch/x86/kernel/irq_32.c
+++ b/arch/x86/kernel/irq_32.c
@@ -48,6 +48,29 @@ void ack_bad_irq(unsigned int irq)
 #endif
 }
 
+#ifdef CONFIG_DEBUG_STACKOVERFLOW
+/* Debugging check for stack overflow: is there less than 1KB free? */
+static int check_stack_overflow(void)
+{
+        long sp;
+
+        __asm__ __volatile__("andl %%esp,%0" :
+                             "=r" (sp) : "0" (THREAD_SIZE - 1));
+
+        return sp < (sizeof(struct thread_info) + STACK_WARN);
+}
+
+static void print_stack_overflow(void)
+{
+        printk(KERN_WARNING "low stack detected by irq handler\n");
+        dump_stack();
+}
+
+#else
+static inline int check_stack_overflow(void) { return 0; }
+static inline void print_stack_overflow(void) { }
+#endif
+
 #ifdef CONFIG_4KSTACKS
 /*
  * per-CPU IRQ handling contexts (thread information and stack)
@@ -59,48 +82,29 @@ union irq_ctx {
 
 static union irq_ctx *hardirq_ctx[NR_CPUS] __read_mostly;
 static union irq_ctx *softirq_ctx[NR_CPUS] __read_mostly;
-#endif
 
-/*
- * do_IRQ handles all normal device IRQ's (the special
- * SMP cross-CPU interrupts have their own specific
- * handlers).
- */
-unsigned int do_IRQ(struct pt_regs *regs)
-{       
-        struct pt_regs *old_regs;
-        /* high bit used in ret_from_ code */
-        int irq = ~regs->orig_ax;
-        struct irq_desc *desc = irq_desc + irq;
-#ifdef CONFIG_4KSTACKS
-        union irq_ctx *curctx, *irqctx;
-        u32 *isp;
-#endif
+static char softirq_stack[NR_CPUS * THREAD_SIZE]
+                __attribute__((__section__(".bss.page_aligned")));
 
-        if (unlikely((unsigned)irq >= NR_IRQS)) {
-                printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
-                                        __func__, irq);
-                BUG();
-        }
+static char hardirq_stack[NR_CPUS * THREAD_SIZE]
+                __attribute__((__section__(".bss.page_aligned")));
 
-        old_regs = set_irq_regs(regs);
-        irq_enter();
-#ifdef CONFIG_DEBUG_STACKOVERFLOW
-        /* Debugging check for stack overflow: is there less than 1KB free? */
-        {
-                long sp;
-
-                __asm__ __volatile__("andl %%esp,%0" :
-                                        "=r" (sp) : "0" (THREAD_SIZE - 1));
-                if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) {
-                        printk("do_IRQ: stack overflow: %ld\n",
-                                sp - sizeof(struct thread_info));
-                        dump_stack();
-                }
-        }
-#endif
+static void call_on_stack(void *func, void *stack)
+{
+        asm volatile("xchgl     %%ebx,%%esp     \n"
+                     "call      *%%edi          \n"
+                     "movl      %%ebx,%%esp     \n"
+                     : "=b" (stack)
+                     : "0" (stack),
+                       "D"(func)
+                     : "memory", "cc", "edx", "ecx", "eax");
+}
 
-#ifdef CONFIG_4KSTACKS
+static inline int
+execute_on_irq_stack(int overflow, struct irq_desc *desc, int irq)
+{
+        union irq_ctx *curctx, *irqctx;
+        u32 *isp, arg1, arg2;
 
         curctx = (union irq_ctx *) current_thread_info();
         irqctx = hardirq_ctx[smp_processor_id()];
@@ -111,52 +115,39 @@ unsigned int do_IRQ(struct pt_regs *regs)
          * handler) we can't do that and just have to keep using the
          * current stack (which is the irq stack already after all)
          */
-        if (curctx != irqctx) {
-                int arg1, arg2, bx;
+        if (unlikely(curctx == irqctx))
+                return 0;
 
-                /* build the stack frame on the IRQ stack */
-                isp = (u32*) ((char*)irqctx + sizeof(*irqctx));
-                irqctx->tinfo.task = curctx->tinfo.task;
-                irqctx->tinfo.previous_esp = current_stack_pointer;
+        /* build the stack frame on the IRQ stack */
+        isp = (u32 *) ((char*)irqctx + sizeof(*irqctx));
+        irqctx->tinfo.task = curctx->tinfo.task;
+        irqctx->tinfo.previous_esp = current_stack_pointer;
 
-                /*
-                 * Copy the softirq bits in preempt_count so that the
-                 * softirq checks work in the hardirq context.
-                 */
-                irqctx->tinfo.preempt_count =
-                        (irqctx->tinfo.preempt_count & ~SOFTIRQ_MASK) |
-                        (curctx->tinfo.preempt_count & SOFTIRQ_MASK);
-
-                asm volatile(
-                        "       xchgl  %%ebx,%%esp    \n"
-                        "       call   *%%edi         \n"
-                        "       movl   %%ebx,%%esp    \n"
-                        : "=a" (arg1), "=d" (arg2), "=b" (bx)
-                        :  "0" (irq),   "1" (desc),  "2" (isp),
-                           "D" (desc->handle_irq)
-                        : "memory", "cc", "ecx"
-                );
-        } else
-#endif
-                desc->handle_irq(irq, desc);
-
-        irq_exit();
-        set_irq_regs(old_regs);
+        /*
+         * Copy the softirq bits in preempt_count so that the
+         * softirq checks work in the hardirq context.
+         */
+        irqctx->tinfo.preempt_count =
+                (irqctx->tinfo.preempt_count & ~SOFTIRQ_MASK) |
+                (curctx->tinfo.preempt_count & SOFTIRQ_MASK);
+
+        if (unlikely(overflow))
+                call_on_stack(print_stack_overflow, isp);
+
+        asm volatile("xchgl     %%ebx,%%esp     \n"
+                     "call      *%%edi          \n"
+                     "movl      %%ebx,%%esp     \n"
+                     : "=a" (arg1), "=d" (arg2), "=b" (isp)
+                     :  "0" (irq),   "1" (desc),  "2" (isp),
+                        "D" (desc->handle_irq)
+                     : "memory", "cc", "ecx");
         return 1;
 }
 
-#ifdef CONFIG_4KSTACKS
-
-static char softirq_stack[NR_CPUS * THREAD_SIZE]
-                __attribute__((__section__(".bss.page_aligned")));
-
-static char hardirq_stack[NR_CPUS * THREAD_SIZE]
-                __attribute__((__section__(".bss.page_aligned")));
-
 /*
  * allocate per-cpu stacks for hardirq and for softirq processing
  */
-void irq_ctx_init(int cpu)
+void __cpuinit irq_ctx_init(int cpu)
 {
         union irq_ctx *irqctx;
 
@@ -164,25 +155,25 @@ void irq_ctx_init(int cpu)
                 return;
 
         irqctx = (union irq_ctx*) &hardirq_stack[cpu*THREAD_SIZE];
-        irqctx->tinfo.task              = NULL;
-        irqctx->tinfo.exec_domain       = NULL;
-        irqctx->tinfo.cpu               = cpu;
-        irqctx->tinfo.preempt_count     = HARDIRQ_OFFSET;
-        irqctx->tinfo.addr_limit        = MAKE_MM_SEG(0);
+        irqctx->tinfo.task              = NULL;
+        irqctx->tinfo.exec_domain       = NULL;
+        irqctx->tinfo.cpu               = cpu;
+        irqctx->tinfo.preempt_count     = HARDIRQ_OFFSET;
+        irqctx->tinfo.addr_limit        = MAKE_MM_SEG(0);
 
         hardirq_ctx[cpu] = irqctx;
 
         irqctx = (union irq_ctx*) &softirq_stack[cpu*THREAD_SIZE];
-        irqctx->tinfo.task              = NULL;
-        irqctx->tinfo.exec_domain       = NULL;
-        irqctx->tinfo.cpu               = cpu;
-        irqctx->tinfo.preempt_count     = 0;
-        irqctx->tinfo.addr_limit        = MAKE_MM_SEG(0);
+        irqctx->tinfo.task              = NULL;
+        irqctx->tinfo.exec_domain       = NULL;
+        irqctx->tinfo.cpu               = cpu;
+        irqctx->tinfo.preempt_count     = 0;
+        irqctx->tinfo.addr_limit        = MAKE_MM_SEG(0);
 
         softirq_ctx[cpu] = irqctx;
 
-        printk("CPU %u irqstacks, hard=%p soft=%p\n",
-                cpu,hardirq_ctx[cpu],softirq_ctx[cpu]);
+        printk(KERN_DEBUG "CPU %u irqstacks, hard=%p soft=%p\n",
+               cpu,hardirq_ctx[cpu],softirq_ctx[cpu]);
 }
 
 void irq_ctx_exit(int cpu)
@@ -211,25 +202,56 @@ asmlinkage void do_softirq(void)
                 /* build the stack frame on the softirq stack */
                 isp = (u32*) ((char*)irqctx + sizeof(*irqctx));
 
-                asm volatile(
-                        "       xchgl   %%ebx,%%esp     \n"
-                        "       call    __do_softirq    \n"
-                        "       movl    %%ebx,%%esp     \n"
-                        : "=b"(isp)
-                        : "0"(isp)
-                        : "memory", "cc", "edx", "ecx", "eax"
-                );
+                call_on_stack(__do_softirq, isp);
                 /*
                  * Shouldnt happen, we returned above if in_interrupt():
-                 */
+                 */
                 WARN_ON_ONCE(softirq_count());
         }
 
         local_irq_restore(flags);
 }
+
+#else
+static inline int
+execute_on_irq_stack(int overflow, struct irq_desc *desc, int irq) { return 0; }
 #endif
 
 /*
+ * do_IRQ handles all normal device IRQ's (the special
+ * SMP cross-CPU interrupts have their own specific
+ * handlers).
+ */
+unsigned int do_IRQ(struct pt_regs *regs)
+{
+        struct pt_regs *old_regs;
+        /* high bit used in ret_from_ code */
+        int overflow, irq = ~regs->orig_ax;
+        struct irq_desc *desc = irq_desc + irq;
+
+        if (unlikely((unsigned)irq >= NR_IRQS)) {
+                printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
+                                        __func__, irq);
+                BUG();
+        }
+
+        old_regs = set_irq_regs(regs);
+        irq_enter();
+
+        overflow = check_stack_overflow();
+
+        if (!execute_on_irq_stack(overflow, desc, irq)) {
+                if (unlikely(overflow))
+                        print_stack_overflow();
+                desc->handle_irq(irq, desc);
+        }
+
+        irq_exit();
+        set_irq_regs(old_regs);
+        return 1;
+}
+
+/*
  * Interrupt statistics:
  */
 
diff --git a/arch/x86/kernel/irqinit_64.c b/arch/x86/kernel/irqinit_64.c
index 64bc0f14285f..31f49e8f46a7 100644
--- a/arch/x86/kernel/irqinit_64.c
+++ b/arch/x86/kernel/irqinit_64.c
@@ -34,6 +34,20 @@
  * interrupt-controller happy.
  */
 
+#define IRQ_NAME2(nr) nr##_interrupt(void)
+#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr)
+
+/*
+ *      SMP has a few special interrupts for IPI messages
+ */
+
+#define BUILD_IRQ(nr)                           \
+        asmlinkage void IRQ_NAME(nr);           \
+        asm("\n.p2align\n"                      \
+            "IRQ" #nr "_interrupt:\n\t"         \
+            "push $~(" #nr ") ; "               \
+            "jmp common_interrupt");
+
 #define BI(x,y) \
         BUILD_IRQ(x##y)
 
@@ -170,33 +184,33 @@ void __init native_init_IRQ(void)
          * The reschedule interrupt is a CPU-to-CPU reschedule-helper
          * IPI, driven by wakeup.
          */
-        set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
+        alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
 
         /* IPIs for invalidation */
-        set_intr_gate(INVALIDATE_TLB_VECTOR_START+0, invalidate_interrupt0);
-        set_intr_gate(INVALIDATE_TLB_VECTOR_START+1, invalidate_interrupt1);
-        set_intr_gate(INVALIDATE_TLB_VECTOR_START+2, invalidate_interrupt2);
-        set_intr_gate(INVALIDATE_TLB_VECTOR_START+3, invalidate_interrupt3);
-        set_intr_gate(INVALIDATE_TLB_VECTOR_START+4, invalidate_interrupt4);
-        set_intr_gate(INVALIDATE_TLB_VECTOR_START+5, invalidate_interrupt5);
-        set_intr_gate(INVALIDATE_TLB_VECTOR_START+6, invalidate_interrupt6);
-        set_intr_gate(INVALIDATE_TLB_VECTOR_START+7, invalidate_interrupt7);
+        alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+0, invalidate_interrupt0);
+        alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+1, invalidate_interrupt1);
+        alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+2, invalidate_interrupt2);
+        alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+3, invalidate_interrupt3);
+        alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+4, invalidate_interrupt4);
+        alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+5, invalidate_interrupt5);
+        alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+6, invalidate_interrupt6);
+        alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+7, invalidate_interrupt7);
 
         /* IPI for generic function call */
-        set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
+        alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
 
         /* Low priority IPI to cleanup after moving an irq */
         set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt);
 #endif
-        set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
-        set_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt);
+        alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
+        alloc_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt);
 
         /* self generated IPI for local APIC timer */
-        set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
+        alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
 
         /* IPI vectors for APIC spurious and error interrupts */
-        set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
-        set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
+        alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
+        alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
 
         if (!acpi_ioapic)
                 setup_irq(2, &irq2);
diff --git a/arch/x86/kernel/vmiclock_32.c b/arch/x86/kernel/vmiclock_32.c
index a2b030780aa9..ba7d19e102b1 100644
--- a/arch/x86/kernel/vmiclock_32.c
+++ b/arch/x86/kernel/vmiclock_32.c
@@ -33,8 +33,7 @@
 #include <asm/apic.h>
 #include <asm/timer.h>
 #include <asm/i8253.h>
-
-#include <irq_vectors.h>
+#include <asm/irq_vectors.h>
 
 #define VMI_ONESHOT  (VMI_ALARM_IS_ONESHOT  | VMI_CYCLES_REAL | vmi_get_alarm_wiring())
 #define VMI_PERIODIC (VMI_ALARM_IS_PERIODIC | VMI_CYCLES_REAL | vmi_get_alarm_wiring())
diff --git a/arch/x86/mach-visws/visws_apic.c b/arch/x86/mach-visws/visws_apic.c
index cef9cb1d15ac..d8b2cfd85d92 100644
--- a/arch/x86/mach-visws/visws_apic.c
+++ b/arch/x86/mach-visws/visws_apic.c
@@ -21,10 +21,9 @@
 #include <asm/io.h>
 #include <asm/apic.h>
 #include <asm/i8259.h>
+#include <asm/irq_vectors.h>
 
 #include "cobalt.h"
-#include "irq_vectors.h"
-
 
 static DEFINE_SPINLOCK(cobalt_lock);