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authorWu Zhangjin <wuzhangjin@gmail.com>2009-11-09 11:06:12 -0500
committerRalf Baechle <ralf@linux-mips.org>2009-12-16 20:57:12 -0500
commit22c21003a91b543d82e87ef2e5195b888b5b9575 (patch)
treec3d9b444e0014939e3ea73e8cf6db1a6b565024d /arch
parent21a41faa4d59716dac0169a48565109b9e5bf0ea (diff)
MIPS: Lemote 2F: Add basic CS5536 VSM support
Lemote Loongson 2F family machines use CS5536 as their south bridge and need these lowlevel interfaces to access the devices on CS5536. Virtualize the legacy devices on CS5536 as PCI devices. This way users can access the CS5536 PCI config space directly as a normal multi-function PCI 2.2 device. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: zhangfx@lemote.com Cc: yanh@lemote.com Cc: huhb@lemote.com Cc: Nicholas Mc Guire <hofrat@hofr.at> Cc: Arnaud Patard <apatard@mandriva.com> Cc: loongson-dev@googlegroups.com Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/include/asm/mach-loongson/cs5536/cs5536.h305
-rw-r--r--arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h153
-rw-r--r--arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h31
-rw-r--r--arch/mips/loongson/Kconfig3
-rw-r--r--arch/mips/loongson/common/Makefile6
-rw-r--r--arch/mips/loongson/common/cs5536/Makefile8
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_acc.c140
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_ehci.c158
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_ide.c179
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_isa.c316
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_ohci.c147
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_pci.c87
12 files changed, 1533 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h
new file mode 100644
index 000000000000..021f77ca59ec
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h
@@ -0,0 +1,305 @@
1/*
2 * The header file of cs5536 sourth bridge.
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu <liujl@lemote.com>
6 */
7
8#ifndef _CS5536_H
9#define _CS5536_H
10
11#include <linux/types.h>
12
13extern void _rdmsr(u32 msr, u32 *hi, u32 *lo);
14extern void _wrmsr(u32 msr, u32 hi, u32 lo);
15
16/*
17 * MSR module base
18 */
19#define CS5536_SB_MSR_BASE (0x00000000)
20#define CS5536_GLIU_MSR_BASE (0x10000000)
21#define CS5536_ILLEGAL_MSR_BASE (0x20000000)
22#define CS5536_USB_MSR_BASE (0x40000000)
23#define CS5536_IDE_MSR_BASE (0x60000000)
24#define CS5536_DIVIL_MSR_BASE (0x80000000)
25#define CS5536_ACC_MSR_BASE (0xa0000000)
26#define CS5536_UNUSED_MSR_BASE (0xc0000000)
27#define CS5536_GLCP_MSR_BASE (0xe0000000)
28
29#define SB_MSR_REG(offset) (CS5536_SB_MSR_BASE | (offset))
30#define GLIU_MSR_REG(offset) (CS5536_GLIU_MSR_BASE | (offset))
31#define ILLEGAL_MSR_REG(offset) (CS5536_ILLEGAL_MSR_BASE | (offset))
32#define USB_MSR_REG(offset) (CS5536_USB_MSR_BASE | (offset))
33#define IDE_MSR_REG(offset) (CS5536_IDE_MSR_BASE | (offset))
34#define DIVIL_MSR_REG(offset) (CS5536_DIVIL_MSR_BASE | (offset))
35#define ACC_MSR_REG(offset) (CS5536_ACC_MSR_BASE | (offset))
36#define UNUSED_MSR_REG(offset) (CS5536_UNUSED_MSR_BASE | (offset))
37#define GLCP_MSR_REG(offset) (CS5536_GLCP_MSR_BASE | (offset))
38
39/*
40 * BAR SPACE OF VIRTUAL PCI :
41 * range for pci probe use, length is the actual size.
42 */
43/* IO space for all DIVIL modules */
44#define CS5536_IRQ_RANGE 0xffffffe0 /* USERD FOR PCI PROBE */
45#define CS5536_IRQ_LENGTH 0x20 /* THE REGS ACTUAL LENGTH */
46#define CS5536_SMB_RANGE 0xfffffff8
47#define CS5536_SMB_LENGTH 0x08
48#define CS5536_GPIO_RANGE 0xffffff00
49#define CS5536_GPIO_LENGTH 0x100
50#define CS5536_MFGPT_RANGE 0xffffffc0
51#define CS5536_MFGPT_LENGTH 0x40
52#define CS5536_ACPI_RANGE 0xffffffe0
53#define CS5536_ACPI_LENGTH 0x20
54#define CS5536_PMS_RANGE 0xffffff80
55#define CS5536_PMS_LENGTH 0x80
56/* IO space for IDE */
57#define CS5536_IDE_RANGE 0xfffffff0
58#define CS5536_IDE_LENGTH 0x10
59/* IO space for ACC */
60#define CS5536_ACC_RANGE 0xffffff80
61#define CS5536_ACC_LENGTH 0x80
62/* MEM space for ALL USB modules */
63#define CS5536_OHCI_RANGE 0xfffff000
64#define CS5536_OHCI_LENGTH 0x1000
65#define CS5536_EHCI_RANGE 0xfffff000
66#define CS5536_EHCI_LENGTH 0x1000
67
68/*
69 * PCI MSR ACCESS
70 */
71#define PCI_MSR_CTRL 0xF0
72#define PCI_MSR_ADDR 0xF4
73#define PCI_MSR_DATA_LO 0xF8
74#define PCI_MSR_DATA_HI 0xFC
75
76/**************** MSR *****************************/
77
78/*
79 * GLIU STANDARD MSR
80 */
81#define GLIU_CAP 0x00
82#define GLIU_CONFIG 0x01
83#define GLIU_SMI 0x02
84#define GLIU_ERROR 0x03
85#define GLIU_PM 0x04
86#define GLIU_DIAG 0x05
87
88/*
89 * GLIU SPEC. MSR
90 */
91#define GLIU_P2D_BM0 0x20
92#define GLIU_P2D_BM1 0x21
93#define GLIU_P2D_BM2 0x22
94#define GLIU_P2D_BMK0 0x23
95#define GLIU_P2D_BMK1 0x24
96#define GLIU_P2D_BM3 0x25
97#define GLIU_P2D_BM4 0x26
98#define GLIU_COH 0x80
99#define GLIU_PAE 0x81
100#define GLIU_ARB 0x82
101#define GLIU_ASMI 0x83
102#define GLIU_AERR 0x84
103#define GLIU_DEBUG 0x85
104#define GLIU_PHY_CAP 0x86
105#define GLIU_NOUT_RESP 0x87
106#define GLIU_NOUT_WDATA 0x88
107#define GLIU_WHOAMI 0x8B
108#define GLIU_SLV_DIS 0x8C
109#define GLIU_IOD_BM0 0xE0
110#define GLIU_IOD_BM1 0xE1
111#define GLIU_IOD_BM2 0xE2
112#define GLIU_IOD_BM3 0xE3
113#define GLIU_IOD_BM4 0xE4
114#define GLIU_IOD_BM5 0xE5
115#define GLIU_IOD_BM6 0xE6
116#define GLIU_IOD_BM7 0xE7
117#define GLIU_IOD_BM8 0xE8
118#define GLIU_IOD_BM9 0xE9
119#define GLIU_IOD_SC0 0xEA
120#define GLIU_IOD_SC1 0xEB
121#define GLIU_IOD_SC2 0xEC
122#define GLIU_IOD_SC3 0xED
123#define GLIU_IOD_SC4 0xEE
124#define GLIU_IOD_SC5 0xEF
125#define GLIU_IOD_SC6 0xF0
126#define GLIU_IOD_SC7 0xF1
127
128/*
129 * SB STANDARD
130 */
131#define SB_CAP 0x00
132#define SB_CONFIG 0x01
133#define SB_SMI 0x02
134#define SB_ERROR 0x03
135#define SB_MAR_ERR_EN 0x00000001
136#define SB_TAR_ERR_EN 0x00000002
137#define SB_RSVD_BIT1 0x00000004
138#define SB_EXCEP_ERR_EN 0x00000008
139#define SB_SYSE_ERR_EN 0x00000010
140#define SB_PARE_ERR_EN 0x00000020
141#define SB_TAS_ERR_EN 0x00000040
142#define SB_MAR_ERR_FLAG 0x00010000
143#define SB_TAR_ERR_FLAG 0x00020000
144#define SB_RSVD_BIT2 0x00040000
145#define SB_EXCEP_ERR_FLAG 0x00080000
146#define SB_SYSE_ERR_FLAG 0x00100000
147#define SB_PARE_ERR_FLAG 0x00200000
148#define SB_TAS_ERR_FLAG 0x00400000
149#define SB_PM 0x04
150#define SB_DIAG 0x05
151
152/*
153 * SB SPEC.
154 */
155#define SB_CTRL 0x10
156#define SB_R0 0x20
157#define SB_R1 0x21
158#define SB_R2 0x22
159#define SB_R3 0x23
160#define SB_R4 0x24
161#define SB_R5 0x25
162#define SB_R6 0x26
163#define SB_R7 0x27
164#define SB_R8 0x28
165#define SB_R9 0x29
166#define SB_R10 0x2A
167#define SB_R11 0x2B
168#define SB_R12 0x2C
169#define SB_R13 0x2D
170#define SB_R14 0x2E
171#define SB_R15 0x2F
172
173/*
174 * GLCP STANDARD
175 */
176#define GLCP_CAP 0x00
177#define GLCP_CONFIG 0x01
178#define GLCP_SMI 0x02
179#define GLCP_ERROR 0x03
180#define GLCP_PM 0x04
181#define GLCP_DIAG 0x05
182
183/*
184 * GLCP SPEC.
185 */
186#define GLCP_CLK_DIS_DELAY 0x08
187#define GLCP_PM_CLK_DISABLE 0x09
188#define GLCP_GLB_PM 0x0B
189#define GLCP_DBG_OUT 0x0C
190#define GLCP_RSVD1 0x0D
191#define GLCP_SOFT_COM 0x0E
192#define SOFT_BAR_SMB_FLAG 0x00000001
193#define SOFT_BAR_GPIO_FLAG 0x00000002
194#define SOFT_BAR_MFGPT_FLAG 0x00000004
195#define SOFT_BAR_IRQ_FLAG 0x00000008
196#define SOFT_BAR_PMS_FLAG 0x00000010
197#define SOFT_BAR_ACPI_FLAG 0x00000020
198#define SOFT_BAR_IDE_FLAG 0x00000400
199#define SOFT_BAR_ACC_FLAG 0x00000800
200#define SOFT_BAR_OHCI_FLAG 0x00001000
201#define SOFT_BAR_EHCI_FLAG 0x00002000
202#define GLCP_RSVD2 0x0F
203#define GLCP_CLK_OFF 0x10
204#define GLCP_CLK_ACTIVE 0x11
205#define GLCP_CLK_DISABLE 0x12
206#define GLCP_CLK4ACK 0x13
207#define GLCP_SYS_RST 0x14
208#define GLCP_RSVD3 0x15
209#define GLCP_DBG_CLK_CTRL 0x16
210#define GLCP_CHIP_REV_ID 0x17
211
212/* PIC */
213#define PIC_YSEL_LOW 0x20
214#define PIC_YSEL_LOW_USB_SHIFT 8
215#define PIC_YSEL_LOW_ACC_SHIFT 16
216#define PIC_YSEL_LOW_FLASH_SHIFT 24
217#define PIC_YSEL_HIGH 0x21
218#define PIC_ZSEL_LOW 0x22
219#define PIC_ZSEL_HIGH 0x23
220#define PIC_IRQM_PRIM 0x24
221#define PIC_IRQM_LPC 0x25
222#define PIC_XIRR_STS_LOW 0x26
223#define PIC_XIRR_STS_HIGH 0x27
224#define PCI_SHDW 0x34
225
226/*
227 * DIVIL STANDARD
228 */
229#define DIVIL_CAP 0x00
230#define DIVIL_CONFIG 0x01
231#define DIVIL_SMI 0x02
232#define DIVIL_ERROR 0x03
233#define DIVIL_PM 0x04
234#define DIVIL_DIAG 0x05
235
236/*
237 * DIVIL SPEC.
238 */
239#define DIVIL_LBAR_IRQ 0x08
240#define DIVIL_LBAR_KEL 0x09
241#define DIVIL_LBAR_SMB 0x0B
242#define DIVIL_LBAR_GPIO 0x0C
243#define DIVIL_LBAR_MFGPT 0x0D
244#define DIVIL_LBAR_ACPI 0x0E
245#define DIVIL_LBAR_PMS 0x0F
246#define DIVIL_LEG_IO 0x14
247#define DIVIL_BALL_OPTS 0x15
248#define DIVIL_SOFT_IRQ 0x16
249#define DIVIL_SOFT_RESET 0x17
250
251/* MFGPT */
252#define MFGPT_IRQ 0x28
253
254/*
255 * IDE STANDARD
256 */
257#define IDE_CAP 0x00
258#define IDE_CONFIG 0x01
259#define IDE_SMI 0x02
260#define IDE_ERROR 0x03
261#define IDE_PM 0x04
262#define IDE_DIAG 0x05
263
264/*
265 * IDE SPEC.
266 */
267#define IDE_IO_BAR 0x08
268#define IDE_CFG 0x10
269#define IDE_DTC 0x12
270#define IDE_CAST 0x13
271#define IDE_ETC 0x14
272#define IDE_INTERNAL_PM 0x15
273
274/*
275 * ACC STANDARD
276 */
277#define ACC_CAP 0x00
278#define ACC_CONFIG 0x01
279#define ACC_SMI 0x02
280#define ACC_ERROR 0x03
281#define ACC_PM 0x04
282#define ACC_DIAG 0x05
283
284/*
285 * USB STANDARD
286 */
287#define USB_CAP 0x00
288#define USB_CONFIG 0x01
289#define USB_SMI 0x02
290#define USB_ERROR 0x03
291#define USB_PM 0x04
292#define USB_DIAG 0x05
293
294/*
295 * USB SPEC.
296 */
297#define USB_OHCI 0x08
298#define USB_EHCI 0x09
299
300/****************** NATIVE ***************************/
301/* GPIO : I/O SPACE; REG : 32BITS */
302#define GPIOL_OUT_VAL 0x00
303#define GPIOL_OUT_EN 0x04
304
305#endif /* _CS5536_H */
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h
new file mode 100644
index 000000000000..0dca9c89ee7c
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h
@@ -0,0 +1,153 @@
1/*
2 * the definition file of cs5536 Virtual Support Module(VSM).
3 * pci configuration space can be accessed through the VSM, so
4 * there is no need of the MSR read/write now, except the spec.
5 * MSR registers which are not implemented yet.
6 *
7 * Copyright (C) 2007 Lemote Inc.
8 * Author : jlliu, liujl@lemote.com
9 */
10
11#ifndef _CS5536_PCI_H
12#define _CS5536_PCI_H
13
14#include <linux/types.h>
15#include <linux/pci_regs.h>
16
17extern void cs5536_pci_conf_write4(int function, int reg, u32 value);
18extern u32 cs5536_pci_conf_read4(int function, int reg);
19
20#define CS5536_ACC_INTR 9
21#define CS5536_IDE_INTR 14
22#define CS5536_USB_INTR 11
23#define CS5536_MFGPT_INTR 5
24#define CS5536_UART1_INTR 4
25#define CS5536_UART2_INTR 3
26
27/************** PCI BUS DEVICE FUNCTION ***************/
28
29/*
30 * PCI bus device function
31 */
32#define PCI_BUS_CS5536 0
33#define PCI_IDSEL_CS5536 14
34
35/********** STANDARD PCI-2.2 EXPANSION ****************/
36
37/*
38 * PCI configuration space
39 * we have to virtualize the PCI configure space head, so we should
40 * define the necessary IDs and some others.
41 */
42
43/* CONFIG of PCI VENDOR ID*/
44#define CFG_PCI_VENDOR_ID(mod_dev_id, sys_vendor_id) \
45 (((mod_dev_id) << 16) | (sys_vendor_id))
46
47/* VENDOR ID */
48#define CS5536_VENDOR_ID 0x1022
49
50/* DEVICE ID */
51#define CS5536_ISA_DEVICE_ID 0x2090
52#define CS5536_IDE_DEVICE_ID 0x209a
53#define CS5536_ACC_DEVICE_ID 0x2093
54#define CS5536_OHCI_DEVICE_ID 0x2094
55#define CS5536_EHCI_DEVICE_ID 0x2095
56
57/* CLASS CODE : CLASS SUB-CLASS INTERFACE */
58#define CS5536_ISA_CLASS_CODE 0x060100
59#define CS5536_IDE_CLASS_CODE 0x010180
60#define CS5536_ACC_CLASS_CODE 0x040100
61#define CS5536_OHCI_CLASS_CODE 0x0C0310
62#define CS5536_EHCI_CLASS_CODE 0x0C0320
63
64/* BHLC : BIST HEADER-TYPE LATENCY-TIMER CACHE-LINE-SIZE */
65
66#define CFG_PCI_CACHE_LINE_SIZE(header_type, latency_timer) \
67 ((PCI_NONE_BIST << 24) | ((header_type) << 16) \
68 | ((latency_timer) << 8) | PCI_NORMAL_CACHE_LINE_SIZE);
69
70#define PCI_NONE_BIST 0x00 /* RO not implemented yet. */
71#define PCI_BRIDGE_HEADER_TYPE 0x80 /* RO */
72#define PCI_NORMAL_HEADER_TYPE 0x00
73#define PCI_NORMAL_LATENCY_TIMER 0x00
74#define PCI_NORMAL_CACHE_LINE_SIZE 0x08 /* RW */
75
76/* BAR */
77#define PCI_BAR0_REG 0x10
78#define PCI_BAR1_REG 0x14
79#define PCI_BAR2_REG 0x18
80#define PCI_BAR3_REG 0x1c
81#define PCI_BAR4_REG 0x20
82#define PCI_BAR5_REG 0x24
83#define PCI_BAR_COUNT 6
84#define PCI_BAR_RANGE_MASK 0xFFFFFFFF
85
86/* CARDBUS CIS POINTER */
87#define PCI_CARDBUS_CIS_POINTER 0x00000000
88
89/* SUBSYSTEM VENDOR ID */
90#define CS5536_SUB_VENDOR_ID CS5536_VENDOR_ID
91
92/* SUBSYSTEM ID */
93#define CS5536_ISA_SUB_ID CS5536_ISA_DEVICE_ID
94#define CS5536_IDE_SUB_ID CS5536_IDE_DEVICE_ID
95#define CS5536_ACC_SUB_ID CS5536_ACC_DEVICE_ID
96#define CS5536_OHCI_SUB_ID CS5536_OHCI_DEVICE_ID
97#define CS5536_EHCI_SUB_ID CS5536_EHCI_DEVICE_ID
98
99/* EXPANSION ROM BAR */
100#define PCI_EXPANSION_ROM_BAR 0x00000000
101
102/* CAPABILITIES POINTER */
103#define PCI_CAPLIST_POINTER 0x00000000
104#define PCI_CAPLIST_USB_POINTER 0x40
105/* INTERRUPT */
106
107#define CFG_PCI_INTERRUPT_LINE(pin, mod_intr) \
108 ((PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | \
109 ((pin) << 8) | (mod_intr))
110
111#define PCI_MAX_LATENCY 0x40
112#define PCI_MIN_GRANT 0x00
113#define PCI_DEFAULT_PIN 0x01
114
115/*********** EXPANSION PCI REG ************************/
116
117/*
118 * ISA EXPANSION
119 */
120#define PCI_UART1_INT_REG 0x50
121#define PCI_UART2_INT_REG 0x54
122#define PCI_ISA_FIXUP_REG 0x58
123
124/*
125 * IDE EXPANSION
126 */
127#define PCI_IDE_CFG_REG 0x40
128#define CS5536_IDE_FLASH_SIGNATURE 0xDEADBEEF
129#define PCI_IDE_DTC_REG 0x48
130#define PCI_IDE_CAST_REG 0x4C
131#define PCI_IDE_ETC_REG 0x50
132#define PCI_IDE_PM_REG 0x54
133#define PCI_IDE_INT_REG 0x60
134
135/*
136 * ACC EXPANSION
137 */
138#define PCI_ACC_INT_REG 0x50
139
140/*
141 * OHCI EXPANSION : INTTERUPT IS IMPLEMENTED BY THE OHCI
142 */
143#define PCI_OHCI_PM_REG 0x40
144#define PCI_OHCI_INT_REG 0x50
145
146/*
147 * EHCI EXPANSION
148 */
149#define PCI_EHCI_LEGSMIEN_REG 0x50
150#define PCI_EHCI_LEGSMISTS_REG 0x54
151#define PCI_EHCI_FLADJ_REG 0x60
152
153#endif /* _CS5536_PCI_H_ */
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h
new file mode 100644
index 000000000000..6305bea7e18e
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h
@@ -0,0 +1,31 @@
1/*
2 * the read/write interfaces for Virtual Support Module(VSM)
3 *
4 * Copyright (C) 2009 Lemote, Inc.
5 * Author: Wu Zhangjin <wuzj@lemote.com>
6 */
7
8#ifndef _CS5536_VSM_H
9#define _CS5536_VSM_H
10
11#include <linux/types.h>
12
13typedef void (*cs5536_pci_vsm_write)(int reg, u32 value);
14typedef u32 (*cs5536_pci_vsm_read)(int reg);
15
16#define DECLARE_CS5536_MODULE(name) \
17extern void pci_##name##_write_reg(int reg, u32 value); \
18extern u32 pci_##name##_read_reg(int reg);
19
20/* ide module */
21DECLARE_CS5536_MODULE(ide)
22/* acc module */
23DECLARE_CS5536_MODULE(acc)
24/* ohci module */
25DECLARE_CS5536_MODULE(ohci)
26/* isa module */
27DECLARE_CS5536_MODULE(isa)
28/* ehci module */
29DECLARE_CS5536_MODULE(ehci)
30
31#endif /* _CS5536_VSM_H */
diff --git a/arch/mips/loongson/Kconfig b/arch/mips/loongson/Kconfig
index 3100237b3f10..a214127895f2 100644
--- a/arch/mips/loongson/Kconfig
+++ b/arch/mips/loongson/Kconfig
@@ -58,3 +58,6 @@ config LEMOTE_MACH2F
58 These family machines include fuloong2f mini PC, yeeloong2f notebook, 58 These family machines include fuloong2f mini PC, yeeloong2f notebook,
59 LingLoong allinone PC and so forth. 59 LingLoong allinone PC and so forth.
60endchoice 60endchoice
61
62config CS5536
63 bool
diff --git a/arch/mips/loongson/common/Makefile b/arch/mips/loongson/common/Makefile
index be6adf7eb825..a82527fdfb65 100644
--- a/arch/mips/loongson/common/Makefile
+++ b/arch/mips/loongson/common/Makefile
@@ -10,3 +10,9 @@ obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \
10# 10#
11obj-$(CONFIG_EARLY_PRINTK) += early_printk.o 11obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
12obj-$(CONFIG_SERIAL_8250) += serial.o 12obj-$(CONFIG_SERIAL_8250) += serial.o
13
14#
15# Enable CS5536 Virtual Support Module(VSM) to virtulize the PCI configure
16# space
17#
18obj-$(CONFIG_CS5536) += cs5536/
diff --git a/arch/mips/loongson/common/cs5536/Makefile b/arch/mips/loongson/common/cs5536/Makefile
new file mode 100644
index 000000000000..31657ee037d8
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/Makefile
@@ -0,0 +1,8 @@
1#
2# Makefile for CS5536 support.
3#
4
5obj-$(CONFIG_CS5536) += cs5536_pci.o cs5536_ide.o cs5536_acc.o cs5536_ohci.o \
6 cs5536_isa.o cs5536_ehci.o
7
8EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/loongson/common/cs5536/cs5536_acc.c b/arch/mips/loongson/common/cs5536/cs5536_acc.c
new file mode 100644
index 000000000000..b49485f187e0
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_acc.c
@@ -0,0 +1,140 @@
1/*
2 * the ACC Virtual Support Module of AMD CS5536
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu, liujl@lemote.com
6 *
7 * Copyright (C) 2009 Lemote, Inc.
8 * Author: Wu Zhangjin, wuzj@lemote.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <cs5536/cs5536.h>
17#include <cs5536/cs5536_pci.h>
18
19void pci_acc_write_reg(int reg, u32 value)
20{
21 u32 hi = 0, lo = value;
22
23 switch (reg) {
24 case PCI_COMMAND:
25 _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
26 if (value & PCI_COMMAND_MASTER)
27 lo |= (0x03 << 8);
28 else
29 lo &= ~(0x03 << 8);
30 _wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo);
31 break;
32 case PCI_STATUS:
33 if (value & PCI_STATUS_PARITY) {
34 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
35 if (lo & SB_PARE_ERR_FLAG) {
36 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
37 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
38 }
39 }
40 break;
41 case PCI_BAR0_REG:
42 if (value == PCI_BAR_RANGE_MASK) {
43 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
44 lo |= SOFT_BAR_ACC_FLAG;
45 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
46 } else if (value & 0x01) {
47 value &= 0xfffffffc;
48 hi = 0xA0000000 | ((value & 0x000ff000) >> 12);
49 lo = 0x000fff80 | ((value & 0x00000fff) << 20);
50 _wrmsr(GLIU_MSR_REG(GLIU_IOD_BM1), hi, lo);
51 }
52 break;
53 case PCI_ACC_INT_REG:
54 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
55 /* disable all the usb interrupt in PIC */
56 lo &= ~(0xf << PIC_YSEL_LOW_ACC_SHIFT);
57 if (value) /* enable all the acc interrupt in PIC */
58 lo |= (CS5536_ACC_INTR << PIC_YSEL_LOW_ACC_SHIFT);
59 _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
60 break;
61 default:
62 break;
63 }
64}
65
66u32 pci_acc_read_reg(int reg)
67{
68 u32 hi, lo;
69 u32 conf_data = 0;
70
71 switch (reg) {
72 case PCI_VENDOR_ID:
73 conf_data =
74 CFG_PCI_VENDOR_ID(CS5536_ACC_DEVICE_ID, CS5536_VENDOR_ID);
75 break;
76 case PCI_COMMAND:
77 _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo);
78 if (((lo & 0xfff00000) || (hi & 0x000000ff))
79 && ((hi & 0xf0000000) == 0xa0000000))
80 conf_data |= PCI_COMMAND_IO;
81 _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
82 if ((lo & 0x300) == 0x300)
83 conf_data |= PCI_COMMAND_MASTER;
84 break;
85 case PCI_STATUS:
86 conf_data |= PCI_STATUS_66MHZ;
87 conf_data |= PCI_STATUS_FAST_BACK;
88 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
89 if (lo & SB_PARE_ERR_FLAG)
90 conf_data |= PCI_STATUS_PARITY;
91 conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
92 break;
93 case PCI_CLASS_REVISION:
94 _rdmsr(ACC_MSR_REG(ACC_CAP), &hi, &lo);
95 conf_data = lo & 0x000000ff;
96 conf_data |= (CS5536_ACC_CLASS_CODE << 8);
97 break;
98 case PCI_CACHE_LINE_SIZE:
99 conf_data =
100 CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
101 PCI_NORMAL_LATENCY_TIMER);
102 break;
103 case PCI_BAR0_REG:
104 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
105 if (lo & SOFT_BAR_ACC_FLAG) {
106 conf_data = CS5536_ACC_RANGE |
107 PCI_BASE_ADDRESS_SPACE_IO;
108 lo &= ~SOFT_BAR_ACC_FLAG;
109 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
110 } else {
111 _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo);
112 conf_data = (hi & 0x000000ff) << 12;
113 conf_data |= (lo & 0xfff00000) >> 20;
114 conf_data |= 0x01;
115 conf_data &= ~0x02;
116 }
117 break;
118 case PCI_CARDBUS_CIS:
119 conf_data = PCI_CARDBUS_CIS_POINTER;
120 break;
121 case PCI_SUBSYSTEM_VENDOR_ID:
122 conf_data =
123 CFG_PCI_VENDOR_ID(CS5536_ACC_SUB_ID, CS5536_SUB_VENDOR_ID);
124 break;
125 case PCI_ROM_ADDRESS:
126 conf_data = PCI_EXPANSION_ROM_BAR;
127 break;
128 case PCI_CAPABILITY_LIST:
129 conf_data = PCI_CAPLIST_USB_POINTER;
130 break;
131 case PCI_INTERRUPT_LINE:
132 conf_data =
133 CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_ACC_INTR);
134 break;
135 default:
136 break;
137 }
138
139 return conf_data;
140}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_ehci.c b/arch/mips/loongson/common/cs5536/cs5536_ehci.c
new file mode 100644
index 000000000000..74f9c59d36af
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_ehci.c
@@ -0,0 +1,158 @@
1/*
2 * the EHCI Virtual Support Module of AMD CS5536
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu, liujl@lemote.com
6 *
7 * Copyright (C) 2009 Lemote, Inc.
8 * Author: Wu Zhangjin, wuzj@lemote.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <cs5536/cs5536.h>
17#include <cs5536/cs5536_pci.h>
18
19void pci_ehci_write_reg(int reg, u32 value)
20{
21 u32 hi = 0, lo = value;
22
23 switch (reg) {
24 case PCI_COMMAND:
25 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
26 if (value & PCI_COMMAND_MASTER)
27 hi |= PCI_COMMAND_MASTER;
28 else
29 hi &= ~PCI_COMMAND_MASTER;
30
31 if (value & PCI_COMMAND_MEMORY)
32 hi |= PCI_COMMAND_MEMORY;
33 else
34 hi &= ~PCI_COMMAND_MEMORY;
35 _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
36 break;
37 case PCI_STATUS:
38 if (value & PCI_STATUS_PARITY) {
39 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
40 if (lo & SB_PARE_ERR_FLAG) {
41 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
42 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
43 }
44 }
45 break;
46 case PCI_BAR0_REG:
47 if (value == PCI_BAR_RANGE_MASK) {
48 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
49 lo |= SOFT_BAR_EHCI_FLAG;
50 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
51 } else if ((value & 0x01) == 0x00) {
52 _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
53
54 value &= 0xfffffff0;
55 hi = 0x40000000 | ((value & 0xff000000) >> 24);
56 lo = 0x000fffff | ((value & 0x00fff000) << 8);
57 _wrmsr(GLIU_MSR_REG(GLIU_P2D_BM4), hi, lo);
58 }
59 break;
60 case PCI_EHCI_LEGSMIEN_REG:
61 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
62 hi &= 0x003f0000;
63 hi |= (value & 0x3f) << 16;
64 _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
65 break;
66 case PCI_EHCI_FLADJ_REG:
67 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
68 hi &= ~0x00003f00;
69 hi |= value & 0x00003f00;
70 _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
71 break;
72 default:
73 break;
74 }
75}
76
77u32 pci_ehci_read_reg(int reg)
78{
79 u32 conf_data = 0;
80 u32 hi, lo;
81
82 switch (reg) {
83 case PCI_VENDOR_ID:
84 conf_data =
85 CFG_PCI_VENDOR_ID(CS5536_EHCI_DEVICE_ID, CS5536_VENDOR_ID);
86 break;
87 case PCI_COMMAND:
88 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
89 if (hi & PCI_COMMAND_MASTER)
90 conf_data |= PCI_COMMAND_MASTER;
91 if (hi & PCI_COMMAND_MEMORY)
92 conf_data |= PCI_COMMAND_MEMORY;
93 break;
94 case PCI_STATUS:
95 conf_data |= PCI_STATUS_66MHZ;
96 conf_data |= PCI_STATUS_FAST_BACK;
97 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
98 if (lo & SB_PARE_ERR_FLAG)
99 conf_data |= PCI_STATUS_PARITY;
100 conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
101 break;
102 case PCI_CLASS_REVISION:
103 _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo);
104 conf_data = lo & 0x000000ff;
105 conf_data |= (CS5536_EHCI_CLASS_CODE << 8);
106 break;
107 case PCI_CACHE_LINE_SIZE:
108 conf_data =
109 CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
110 PCI_NORMAL_LATENCY_TIMER);
111 break;
112 case PCI_BAR0_REG:
113 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
114 if (lo & SOFT_BAR_EHCI_FLAG) {
115 conf_data = CS5536_EHCI_RANGE |
116 PCI_BASE_ADDRESS_SPACE_MEMORY;
117 lo &= ~SOFT_BAR_EHCI_FLAG;
118 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
119 } else {
120 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
121 conf_data = lo & 0xfffff000;
122 }
123 break;
124 case PCI_CARDBUS_CIS:
125 conf_data = PCI_CARDBUS_CIS_POINTER;
126 break;
127 case PCI_SUBSYSTEM_VENDOR_ID:
128 conf_data =
129 CFG_PCI_VENDOR_ID(CS5536_EHCI_SUB_ID, CS5536_SUB_VENDOR_ID);
130 break;
131 case PCI_ROM_ADDRESS:
132 conf_data = PCI_EXPANSION_ROM_BAR;
133 break;
134 case PCI_CAPABILITY_LIST:
135 conf_data = PCI_CAPLIST_USB_POINTER;
136 break;
137 case PCI_INTERRUPT_LINE:
138 conf_data =
139 CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR);
140 break;
141 case PCI_EHCI_LEGSMIEN_REG:
142 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
143 conf_data = (hi & 0x003f0000) >> 16;
144 break;
145 case PCI_EHCI_LEGSMISTS_REG:
146 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
147 conf_data = (hi & 0x3f000000) >> 24;
148 break;
149 case PCI_EHCI_FLADJ_REG:
150 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
151 conf_data = hi & 0x00003f00;
152 break;
153 default:
154 break;
155 }
156
157 return conf_data;
158}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_ide.c b/arch/mips/loongson/common/cs5536/cs5536_ide.c
new file mode 100644
index 000000000000..3f61594b3884
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_ide.c
@@ -0,0 +1,179 @@
1/*
2 * the IDE Virtual Support Module of AMD CS5536
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu, liujl@lemote.com
6 *
7 * Copyright (C) 2009 Lemote, Inc.
8 * Author: Wu Zhangjin, wuzj@lemote.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <cs5536/cs5536.h>
17#include <cs5536/cs5536_pci.h>
18
19void pci_ide_write_reg(int reg, u32 value)
20{
21 u32 hi = 0, lo = value;
22
23 switch (reg) {
24 case PCI_COMMAND:
25 _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
26 if (value & PCI_COMMAND_MASTER)
27 lo |= (0x03 << 4);
28 else
29 lo &= ~(0x03 << 4);
30 _wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo);
31 break;
32 case PCI_STATUS:
33 if (value & PCI_STATUS_PARITY) {
34 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
35 if (lo & SB_PARE_ERR_FLAG) {
36 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
37 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
38 }
39 }
40 break;
41 case PCI_CACHE_LINE_SIZE:
42 value &= 0x0000ff00;
43 _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
44 hi &= 0xffffff00;
45 hi |= (value >> 8);
46 _wrmsr(SB_MSR_REG(SB_CTRL), hi, lo);
47 break;
48 case PCI_BAR4_REG:
49 if (value == PCI_BAR_RANGE_MASK) {
50 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
51 lo |= SOFT_BAR_IDE_FLAG;
52 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
53 } else if (value & 0x01) {
54 lo = (value & 0xfffffff0) | 0x1;
55 _wrmsr(IDE_MSR_REG(IDE_IO_BAR), hi, lo);
56
57 value &= 0xfffffffc;
58 hi = 0x60000000 | ((value & 0x000ff000) >> 12);
59 lo = 0x000ffff0 | ((value & 0x00000fff) << 20);
60 _wrmsr(GLIU_MSR_REG(GLIU_IOD_BM2), hi, lo);
61 }
62 break;
63 case PCI_IDE_CFG_REG:
64 if (value == CS5536_IDE_FLASH_SIGNATURE) {
65 _rdmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), &hi, &lo);
66 lo |= 0x01;
67 _wrmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), hi, lo);
68 } else
69 _wrmsr(IDE_MSR_REG(IDE_CFG), hi, lo);
70 break;
71 case PCI_IDE_DTC_REG:
72 _wrmsr(IDE_MSR_REG(IDE_DTC), hi, lo);
73 break;
74 case PCI_IDE_CAST_REG:
75 _wrmsr(IDE_MSR_REG(IDE_CAST), hi, lo);
76 break;
77 case PCI_IDE_ETC_REG:
78 _wrmsr(IDE_MSR_REG(IDE_ETC), hi, lo);
79 break;
80 case PCI_IDE_PM_REG:
81 _wrmsr(IDE_MSR_REG(IDE_INTERNAL_PM), hi, lo);
82 break;
83 default:
84 break;
85 }
86}
87
88u32 pci_ide_read_reg(int reg)
89{
90 u32 conf_data = 0;
91 u32 hi, lo;
92
93 switch (reg) {
94 case PCI_VENDOR_ID:
95 conf_data =
96 CFG_PCI_VENDOR_ID(CS5536_IDE_DEVICE_ID, CS5536_VENDOR_ID);
97 break;
98 case PCI_COMMAND:
99 _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo);
100 if (lo & 0xfffffff0)
101 conf_data |= PCI_COMMAND_IO;
102 _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
103 if ((lo & 0x30) == 0x30)
104 conf_data |= PCI_COMMAND_MASTER;
105 break;
106 case PCI_STATUS:
107 conf_data |= PCI_STATUS_66MHZ;
108 conf_data |= PCI_STATUS_FAST_BACK;
109 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
110 if (lo & SB_PARE_ERR_FLAG)
111 conf_data |= PCI_STATUS_PARITY;
112 conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
113 break;
114 case PCI_CLASS_REVISION:
115 _rdmsr(IDE_MSR_REG(IDE_CAP), &hi, &lo);
116 conf_data = lo & 0x000000ff;
117 conf_data |= (CS5536_IDE_CLASS_CODE << 8);
118 break;
119 case PCI_CACHE_LINE_SIZE:
120 _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
121 hi &= 0x000000f8;
122 conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, hi);
123 break;
124 case PCI_BAR4_REG:
125 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
126 if (lo & SOFT_BAR_IDE_FLAG) {
127 conf_data = CS5536_IDE_RANGE |
128 PCI_BASE_ADDRESS_SPACE_IO;
129 lo &= ~SOFT_BAR_IDE_FLAG;
130 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
131 } else {
132 _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo);
133 conf_data = lo & 0xfffffff0;
134 conf_data |= 0x01;
135 conf_data &= ~0x02;
136 }
137 break;
138 case PCI_CARDBUS_CIS:
139 conf_data = PCI_CARDBUS_CIS_POINTER;
140 break;
141 case PCI_SUBSYSTEM_VENDOR_ID:
142 conf_data =
143 CFG_PCI_VENDOR_ID(CS5536_IDE_SUB_ID, CS5536_SUB_VENDOR_ID);
144 break;
145 case PCI_ROM_ADDRESS:
146 conf_data = PCI_EXPANSION_ROM_BAR;
147 break;
148 case PCI_CAPABILITY_LIST:
149 conf_data = PCI_CAPLIST_POINTER;
150 break;
151 case PCI_INTERRUPT_LINE:
152 conf_data =
153 CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_IDE_INTR);
154 break;
155 case PCI_IDE_CFG_REG:
156 _rdmsr(IDE_MSR_REG(IDE_CFG), &hi, &lo);
157 conf_data = lo;
158 break;
159 case PCI_IDE_DTC_REG:
160 _rdmsr(IDE_MSR_REG(IDE_DTC), &hi, &lo);
161 conf_data = lo;
162 break;
163 case PCI_IDE_CAST_REG:
164 _rdmsr(IDE_MSR_REG(IDE_CAST), &hi, &lo);
165 conf_data = lo;
166 break;
167 case PCI_IDE_ETC_REG:
168 _rdmsr(IDE_MSR_REG(IDE_ETC), &hi, &lo);
169 conf_data = lo;
170 case PCI_IDE_PM_REG:
171 _rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM), &hi, &lo);
172 conf_data = lo;
173 break;
174 default:
175 break;
176 }
177
178 return conf_data;
179}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_isa.c b/arch/mips/loongson/common/cs5536/cs5536_isa.c
new file mode 100644
index 000000000000..b6f17f538e48
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_isa.c
@@ -0,0 +1,316 @@
1/*
2 * the ISA Virtual Support Module of AMD CS5536
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu, liujl@lemote.com
6 *
7 * Copyright (C) 2009 Lemote, Inc.
8 * Author: Wu Zhangjin, wuzj@lemote.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <cs5536/cs5536.h>
17#include <cs5536/cs5536_pci.h>
18
19/* common variables for PCI_ISA_READ/WRITE_BAR */
20static const u32 divil_msr_reg[6] = {
21 DIVIL_MSR_REG(DIVIL_LBAR_SMB), DIVIL_MSR_REG(DIVIL_LBAR_GPIO),
22 DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), DIVIL_MSR_REG(DIVIL_LBAR_IRQ),
23 DIVIL_MSR_REG(DIVIL_LBAR_PMS), DIVIL_MSR_REG(DIVIL_LBAR_ACPI),
24};
25
26static const u32 soft_bar_flag[6] = {
27 SOFT_BAR_SMB_FLAG, SOFT_BAR_GPIO_FLAG, SOFT_BAR_MFGPT_FLAG,
28 SOFT_BAR_IRQ_FLAG, SOFT_BAR_PMS_FLAG, SOFT_BAR_ACPI_FLAG,
29};
30
31static const u32 sb_msr_reg[6] = {
32 SB_MSR_REG(SB_R0), SB_MSR_REG(SB_R1), SB_MSR_REG(SB_R2),
33 SB_MSR_REG(SB_R3), SB_MSR_REG(SB_R4), SB_MSR_REG(SB_R5),
34};
35
36static const u32 bar_space_range[6] = {
37 CS5536_SMB_RANGE, CS5536_GPIO_RANGE, CS5536_MFGPT_RANGE,
38 CS5536_IRQ_RANGE, CS5536_PMS_RANGE, CS5536_ACPI_RANGE,
39};
40
41static const int bar_space_len[6] = {
42 CS5536_SMB_LENGTH, CS5536_GPIO_LENGTH, CS5536_MFGPT_LENGTH,
43 CS5536_IRQ_LENGTH, CS5536_PMS_LENGTH, CS5536_ACPI_LENGTH,
44};
45
46/*
47 * enable the divil module bar space.
48 *
49 * For all the DIVIL module LBAR, you should control the DIVIL LBAR reg
50 * and the RCONFx(0~5) reg to use the modules.
51 */
52static void divil_lbar_enable(void)
53{
54 u32 hi, lo;
55 int offset;
56
57 /*
58 * The DIVIL IRQ is not used yet. and make the RCONF0 reserved.
59 */
60
61 for (offset = DIVIL_LBAR_SMB; offset <= DIVIL_LBAR_PMS; offset++) {
62 _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo);
63 hi |= 0x01;
64 _wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), hi, lo);
65 }
66}
67
68/*
69 * disable the divil module bar space.
70 */
71static void divil_lbar_disable(void)
72{
73 u32 hi, lo;
74 int offset;
75
76 for (offset = DIVIL_LBAR_SMB; offset <= DIVIL_LBAR_PMS; offset++) {
77 _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo);
78 hi &= ~0x01;
79 _wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), hi, lo);
80 }
81}
82
83/*
84 * BAR write: write value to the n BAR
85 */
86
87void pci_isa_write_bar(int n, u32 value)
88{
89 u32 hi = 0, lo = value;
90
91 if (value == PCI_BAR_RANGE_MASK) {
92 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
93 lo |= soft_bar_flag[n];
94 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
95 } else if (value & 0x01) {
96 /* NATIVE reg */
97 hi = 0x0000f001;
98 lo &= bar_space_range[n];
99 _wrmsr(divil_msr_reg[n], hi, lo);
100
101 /* RCONFx is 4bytes in units for I/O space */
102 hi = ((value & 0x000ffffc) << 12) |
103 ((bar_space_len[n] - 4) << 12) | 0x01;
104 lo = ((value & 0x000ffffc) << 12) | 0x01;
105 _wrmsr(sb_msr_reg[n], hi, lo);
106 }
107}
108
109/*
110 * BAR read: read the n BAR
111 */
112
113u32 pci_isa_read_bar(int n)
114{
115 u32 conf_data = 0;
116 u32 hi, lo;
117
118 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
119 if (lo & soft_bar_flag[n]) {
120 conf_data = bar_space_range[n] | PCI_BASE_ADDRESS_SPACE_IO;
121 lo &= ~soft_bar_flag[n];
122 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
123 } else {
124 _rdmsr(divil_msr_reg[n], &hi, &lo);
125 conf_data = lo & bar_space_range[n];
126 conf_data |= 0x01;
127 conf_data &= ~0x02;
128 }
129 return conf_data;
130}
131
132/*
133 * isa_write: ISA write transfer
134 *
135 * We assume that this is not a bus master transfer.
136 */
137void pci_isa_write_reg(int reg, u32 value)
138{
139 u32 hi = 0, lo = value;
140 u32 temp;
141
142 switch (reg) {
143 case PCI_COMMAND:
144 if (value & PCI_COMMAND_IO)
145 divil_lbar_enable();
146 else
147 divil_lbar_disable();
148 break;
149 case PCI_STATUS:
150 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
151 temp = lo & 0x0000ffff;
152 if ((value & PCI_STATUS_SIG_TARGET_ABORT) &&
153 (lo & SB_TAS_ERR_EN))
154 temp |= SB_TAS_ERR_FLAG;
155
156 if ((value & PCI_STATUS_REC_TARGET_ABORT) &&
157 (lo & SB_TAR_ERR_EN))
158 temp |= SB_TAR_ERR_FLAG;
159
160 if ((value & PCI_STATUS_REC_MASTER_ABORT)
161 && (lo & SB_MAR_ERR_EN))
162 temp |= SB_MAR_ERR_FLAG;
163
164 if ((value & PCI_STATUS_DETECTED_PARITY)
165 && (lo & SB_PARE_ERR_EN))
166 temp |= SB_PARE_ERR_FLAG;
167
168 lo = temp;
169 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
170 break;
171 case PCI_CACHE_LINE_SIZE:
172 value &= 0x0000ff00;
173 _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
174 hi &= 0xffffff00;
175 hi |= (value >> 8);
176 _wrmsr(SB_MSR_REG(SB_CTRL), hi, lo);
177 break;
178 case PCI_BAR0_REG:
179 pci_isa_write_bar(0, value);
180 break;
181 case PCI_BAR1_REG:
182 pci_isa_write_bar(1, value);
183 break;
184 case PCI_BAR2_REG:
185 pci_isa_write_bar(2, value);
186 break;
187 case PCI_BAR3_REG:
188 pci_isa_write_bar(3, value);
189 break;
190 case PCI_BAR4_REG:
191 pci_isa_write_bar(4, value);
192 break;
193 case PCI_BAR5_REG:
194 pci_isa_write_bar(5, value);
195 break;
196 case PCI_UART1_INT_REG:
197 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo);
198 /* disable uart1 interrupt in PIC */
199 lo &= ~(0xf << 24);
200 if (value) /* enable uart1 interrupt in PIC */
201 lo |= (CS5536_UART1_INTR << 24);
202 _wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo);
203 break;
204 case PCI_UART2_INT_REG:
205 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo);
206 /* disable uart2 interrupt in PIC */
207 lo &= ~(0xf << 28);
208 if (value) /* enable uart2 interrupt in PIC */
209 lo |= (CS5536_UART2_INTR << 28);
210 _wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo);
211 break;
212 case PCI_ISA_FIXUP_REG:
213 if (value) {
214 /* enable the TARGET ABORT/MASTER ABORT etc. */
215 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
216 lo |= 0x00000063;
217 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
218 }
219
220 default:
221 /* ALL OTHER PCI CONFIG SPACE HEADER IS NOT IMPLEMENTED. */
222 break;
223 }
224}
225
226/*
227 * isa_read: ISA read transfers
228 *
229 * We assume that this is not a bus master transfer.
230 */
231u32 pci_isa_read_reg(int reg)
232{
233 u32 conf_data = 0;
234 u32 hi, lo;
235
236 switch (reg) {
237 case PCI_VENDOR_ID:
238 conf_data =
239 CFG_PCI_VENDOR_ID(CS5536_ISA_DEVICE_ID, CS5536_VENDOR_ID);
240 break;
241 case PCI_COMMAND:
242 /* we just check the first LBAR for the IO enable bit, */
243 /* maybe we should changed later. */
244 _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), &hi, &lo);
245 if (hi & 0x01)
246 conf_data |= PCI_COMMAND_IO;
247 break;
248 case PCI_STATUS:
249 conf_data |= PCI_STATUS_66MHZ;
250 conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
251 conf_data |= PCI_STATUS_FAST_BACK;
252
253 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
254 if (lo & SB_TAS_ERR_FLAG)
255 conf_data |= PCI_STATUS_SIG_TARGET_ABORT;
256 if (lo & SB_TAR_ERR_FLAG)
257 conf_data |= PCI_STATUS_REC_TARGET_ABORT;
258 if (lo & SB_MAR_ERR_FLAG)
259 conf_data |= PCI_STATUS_REC_MASTER_ABORT;
260 if (lo & SB_PARE_ERR_FLAG)
261 conf_data |= PCI_STATUS_DETECTED_PARITY;
262 break;
263 case PCI_CLASS_REVISION:
264 _rdmsr(GLCP_MSR_REG(GLCP_CHIP_REV_ID), &hi, &lo);
265 conf_data = lo & 0x000000ff;
266 conf_data |= (CS5536_ISA_CLASS_CODE << 8);
267 break;
268 case PCI_CACHE_LINE_SIZE:
269 _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
270 hi &= 0x000000f8;
271 conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_BRIDGE_HEADER_TYPE, hi);
272 break;
273 /*
274 * we only use the LBAR of DIVIL, no RCONF used.
275 * all of them are IO space.
276 */
277 case PCI_BAR0_REG:
278 return pci_isa_read_bar(0);
279 break;
280 case PCI_BAR1_REG:
281 return pci_isa_read_bar(1);
282 break;
283 case PCI_BAR2_REG:
284 return pci_isa_read_bar(2);
285 break;
286 case PCI_BAR3_REG:
287 break;
288 case PCI_BAR4_REG:
289 return pci_isa_read_bar(4);
290 break;
291 case PCI_BAR5_REG:
292 return pci_isa_read_bar(5);
293 break;
294 case PCI_CARDBUS_CIS:
295 conf_data = PCI_CARDBUS_CIS_POINTER;
296 break;
297 case PCI_SUBSYSTEM_VENDOR_ID:
298 conf_data =
299 CFG_PCI_VENDOR_ID(CS5536_ISA_SUB_ID, CS5536_SUB_VENDOR_ID);
300 break;
301 case PCI_ROM_ADDRESS:
302 conf_data = PCI_EXPANSION_ROM_BAR;
303 break;
304 case PCI_CAPABILITY_LIST:
305 conf_data = PCI_CAPLIST_POINTER;
306 break;
307 case PCI_INTERRUPT_LINE:
308 /* no interrupt used here */
309 conf_data = CFG_PCI_INTERRUPT_LINE(0x00, 0x00);
310 break;
311 default:
312 break;
313 }
314
315 return conf_data;
316}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_ohci.c b/arch/mips/loongson/common/cs5536/cs5536_ohci.c
new file mode 100644
index 000000000000..8fdb02b6e90f
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_ohci.c
@@ -0,0 +1,147 @@
1/*
2 * the OHCI Virtual Support Module of AMD CS5536
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu, liujl@lemote.com
6 *
7 * Copyright (C) 2009 Lemote, Inc.
8 * Author: Wu Zhangjin, wuzj@lemote.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <cs5536/cs5536.h>
17#include <cs5536/cs5536_pci.h>
18
19void pci_ohci_write_reg(int reg, u32 value)
20{
21 u32 hi = 0, lo = value;
22
23 switch (reg) {
24 case PCI_COMMAND:
25 _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
26 if (value & PCI_COMMAND_MASTER)
27 hi |= PCI_COMMAND_MASTER;
28 else
29 hi &= ~PCI_COMMAND_MASTER;
30
31 if (value & PCI_COMMAND_MEMORY)
32 hi |= PCI_COMMAND_MEMORY;
33 else
34 hi &= ~PCI_COMMAND_MEMORY;
35 _wrmsr(USB_MSR_REG(USB_OHCI), hi, lo);
36 break;
37 case PCI_STATUS:
38 if (value & PCI_STATUS_PARITY) {
39 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
40 if (lo & SB_PARE_ERR_FLAG) {
41 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
42 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
43 }
44 }
45 break;
46 case PCI_BAR0_REG:
47 if (value == PCI_BAR_RANGE_MASK) {
48 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
49 lo |= SOFT_BAR_OHCI_FLAG;
50 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
51 } else if ((value & 0x01) == 0x00) {
52 _wrmsr(USB_MSR_REG(USB_OHCI), hi, lo);
53
54 value &= 0xfffffff0;
55 hi = 0x40000000 | ((value & 0xff000000) >> 24);
56 lo = 0x000fffff | ((value & 0x00fff000) << 8);
57 _wrmsr(GLIU_MSR_REG(GLIU_P2D_BM3), hi, lo);
58 }
59 break;
60 case PCI_OHCI_INT_REG:
61 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
62 lo &= ~(0xf << PIC_YSEL_LOW_USB_SHIFT);
63 if (value) /* enable all the usb interrupt in PIC */
64 lo |= (CS5536_USB_INTR << PIC_YSEL_LOW_USB_SHIFT);
65 _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
66 break;
67 default:
68 break;
69 }
70}
71
72u32 pci_ohci_read_reg(int reg)
73{
74 u32 conf_data = 0;
75 u32 hi, lo;
76
77 switch (reg) {
78 case PCI_VENDOR_ID:
79 conf_data =
80 CFG_PCI_VENDOR_ID(CS5536_OHCI_DEVICE_ID, CS5536_VENDOR_ID);
81 break;
82 case PCI_COMMAND:
83 _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
84 if (hi & PCI_COMMAND_MASTER)
85 conf_data |= PCI_COMMAND_MASTER;
86 if (hi & PCI_COMMAND_MEMORY)
87 conf_data |= PCI_COMMAND_MEMORY;
88 break;
89 case PCI_STATUS:
90 conf_data |= PCI_STATUS_66MHZ;
91 conf_data |= PCI_STATUS_FAST_BACK;
92 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
93 if (lo & SB_PARE_ERR_FLAG)
94 conf_data |= PCI_STATUS_PARITY;
95 conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
96 break;
97 case PCI_CLASS_REVISION:
98 _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo);
99 conf_data = lo & 0x000000ff;
100 conf_data |= (CS5536_OHCI_CLASS_CODE << 8);
101 break;
102 case PCI_CACHE_LINE_SIZE:
103 conf_data =
104 CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
105 PCI_NORMAL_LATENCY_TIMER);
106 break;
107 case PCI_BAR0_REG:
108 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
109 if (lo & SOFT_BAR_OHCI_FLAG) {
110 conf_data = CS5536_OHCI_RANGE |
111 PCI_BASE_ADDRESS_SPACE_MEMORY;
112 lo &= ~SOFT_BAR_OHCI_FLAG;
113 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
114 } else {
115 _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
116 conf_data = lo & 0xffffff00;
117 conf_data &= ~0x0000000f; /* 32bit mem */
118 }
119 break;
120 case PCI_CARDBUS_CIS:
121 conf_data = PCI_CARDBUS_CIS_POINTER;
122 break;
123 case PCI_SUBSYSTEM_VENDOR_ID:
124 conf_data =
125 CFG_PCI_VENDOR_ID(CS5536_OHCI_SUB_ID, CS5536_SUB_VENDOR_ID);
126 break;
127 case PCI_ROM_ADDRESS:
128 conf_data = PCI_EXPANSION_ROM_BAR;
129 break;
130 case PCI_CAPABILITY_LIST:
131 conf_data = PCI_CAPLIST_USB_POINTER;
132 break;
133 case PCI_INTERRUPT_LINE:
134 conf_data =
135 CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR);
136 break;
137 case PCI_OHCI_INT_REG:
138 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
139 if ((lo & 0x00000f00) == CS5536_USB_INTR)
140 conf_data = 1;
141 break;
142 default:
143 break;
144 }
145
146 return conf_data;
147}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_pci.c b/arch/mips/loongson/common/cs5536/cs5536_pci.c
new file mode 100644
index 000000000000..e23f3d7d2c1d
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_pci.c
@@ -0,0 +1,87 @@
1/*
2 * read/write operation to the PCI config space of CS5536
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu, liujl@lemote.com
6 *
7 * Copyright (C) 2009 Lemote, Inc.
8 * Author: Wu Zhangjin, wuzj@lemote.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * the Virtual Support Module(VSM) for virtulizing the PCI
16 * configure space are defined in cs5536_modulename.c respectively,
17 *
18 * after this virtulizing, user can access the PCI configure space
19 * directly as a normal multi-function PCI device which follows
20 * the PCI-2.2 spec.
21 */
22
23#include <linux/types.h>
24#include <cs5536/cs5536_vsm.h>
25
26enum {
27 CS5536_FUNC_START = -1,
28 CS5536_ISA_FUNC,
29 reserved_func,
30 CS5536_IDE_FUNC,
31 CS5536_ACC_FUNC,
32 CS5536_OHCI_FUNC,
33 CS5536_EHCI_FUNC,
34 CS5536_FUNC_END,
35};
36
37static const cs5536_pci_vsm_write vsm_conf_write[] = {
38 [CS5536_ISA_FUNC] pci_isa_write_reg,
39 [reserved_func] NULL,
40 [CS5536_IDE_FUNC] pci_ide_write_reg,
41 [CS5536_ACC_FUNC] pci_acc_write_reg,
42 [CS5536_OHCI_FUNC] pci_ohci_write_reg,
43 [CS5536_EHCI_FUNC] pci_ehci_write_reg,
44};
45
46static const cs5536_pci_vsm_read vsm_conf_read[] = {
47 [CS5536_ISA_FUNC] pci_isa_read_reg,
48 [reserved_func] NULL,
49 [CS5536_IDE_FUNC] pci_ide_read_reg,
50 [CS5536_ACC_FUNC] pci_acc_read_reg,
51 [CS5536_OHCI_FUNC] pci_ohci_read_reg,
52 [CS5536_EHCI_FUNC] pci_ehci_read_reg,
53};
54
55/*
56 * write to PCI config space and transfer it to MSR write.
57 */
58void cs5536_pci_conf_write4(int function, int reg, u32 value)
59{
60 if ((function <= CS5536_FUNC_START) || (function >= CS5536_FUNC_END))
61 return;
62 if ((reg < 0) || (reg > 0x100) || ((reg & 0x03) != 0))
63 return;
64
65 if (vsm_conf_write[function] != NULL)
66 vsm_conf_write[function](reg, value);
67}
68
69/*
70 * read PCI config space and transfer it to MSR access.
71 */
72u32 cs5536_pci_conf_read4(int function, int reg)
73{
74 u32 data = 0;
75
76 if ((function <= CS5536_FUNC_START) || (function >= CS5536_FUNC_END))
77 return 0;
78 if ((reg < 0) || ((reg & 0x03) != 0))
79 return 0;
80 if (reg > 0x100)
81 return 0xffffffff;
82
83 if (vsm_conf_read[function] != NULL)
84 data = vsm_conf_read[function](reg);
85
86 return data;
87}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-22 06:49:31 -0500