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authorHumphrey Bucknell <hbucknell@saitek.com>2008-08-29 11:27:00 -0400
committerHaavard Skinnemoen <haavard.skinnemoen@atmel.com>2008-09-01 07:04:09 -0400
commit84c4f2f21a8e6e6d4bdfff95bf5ddc7925df4e01 (patch)
treee18e4dff39c14edca1f0dcb084bdb0762107dfbd /arch
parent9e3f544d792fd2ff7e31ca4a72e5194f1491ed14 (diff)
avr32: pm_standby low-power ram bug fix
The value stored into the SDRAMC LPR register should be the current value of the register with the Self-refresh value set in the lower bit field. The bug involved only the Self-refresh value being written to the register, thus over writing any low-power ram settings. Signed-off-by: Humphrey Bucknell <hbucknell@saitek.com> Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/avr32/mach-at32ap/pm-at32ap700x.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/avr32/mach-at32ap/pm-at32ap700x.S b/arch/avr32/mach-at32ap/pm-at32ap700x.S
index 5be4de65b209..17503b0ed6c9 100644
--- a/arch/avr32/mach-at32ap/pm-at32ap700x.S
+++ b/arch/avr32/mach-at32ap/pm-at32ap700x.S
@@ -134,7 +134,7 @@ pm_standby:
134 mov r11, SDRAMC_LPR_LPCB_SELF_RFR 134 mov r11, SDRAMC_LPR_LPCB_SELF_RFR
135 bfins r10, r11, 0, 2 /* LPCB <- self Refresh */ 135 bfins r10, r11, 0, 2 /* LPCB <- self Refresh */
136 sync 0 /* flush write buffer */ 136 sync 0 /* flush write buffer */
137 st.w r12[SDRAMC_LPR], r11 /* put SDRAM in self-refresh mode */ 137 st.w r12[SDRAMC_LPR], r10 /* put SDRAM in self-refresh mode */
138 ld.w r11, r12[SDRAMC_LPR] 138 ld.w r11, r12[SDRAMC_LPR]
139 unmask_interrupts 139 unmask_interrupts
140 sleep CPU_SLEEP_FROZEN 140 sleep CPU_SLEEP_FROZEN