diff options
| author | Robert Richter <robert.richter@amd.com> | 2010-04-13 16:23:11 -0400 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2010-05-07 05:31:00 -0400 |
| commit | c1726f343b3bfc2ee037e191907c632a31903021 (patch) | |
| tree | da77ad3da17ac80df0af1473d1dd91beff33548f /arch | |
| parent | 4261e0e0efd9e04b6c69e0773c3cf4d6f337c416 (diff) | |
perf, x86: Move x86_setup_perfctr()
Move x86_setup_perfctr(), no other changes made.
Signed-off-by: Robert Richter <robert.richter@amd.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
LKML-Reference: <1271190201-25705-3-git-send-email-robert.richter@amd.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86/kernel/cpu/perf_event.c | 120 |
1 files changed, 59 insertions, 61 deletions
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c index 801441a54245..3d3bceb9e830 100644 --- a/arch/x86/kernel/cpu/perf_event.c +++ b/arch/x86/kernel/cpu/perf_event.c | |||
| @@ -426,7 +426,65 @@ set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr) | |||
| 426 | return 0; | 426 | return 0; |
| 427 | } | 427 | } |
| 428 | 428 | ||
| 429 | static int x86_setup_perfctr(struct perf_event *event); | 429 | static int x86_setup_perfctr(struct perf_event *event) |
| 430 | { | ||
| 431 | struct perf_event_attr *attr = &event->attr; | ||
| 432 | struct hw_perf_event *hwc = &event->hw; | ||
| 433 | u64 config; | ||
| 434 | |||
| 435 | if (!hwc->sample_period) { | ||
| 436 | hwc->sample_period = x86_pmu.max_period; | ||
| 437 | hwc->last_period = hwc->sample_period; | ||
| 438 | atomic64_set(&hwc->period_left, hwc->sample_period); | ||
| 439 | } else { | ||
| 440 | /* | ||
| 441 | * If we have a PMU initialized but no APIC | ||
| 442 | * interrupts, we cannot sample hardware | ||
| 443 | * events (user-space has to fall back and | ||
| 444 | * sample via a hrtimer based software event): | ||
| 445 | */ | ||
| 446 | if (!x86_pmu.apic) | ||
| 447 | return -EOPNOTSUPP; | ||
| 448 | } | ||
| 449 | |||
| 450 | if (attr->type == PERF_TYPE_RAW) | ||
| 451 | return 0; | ||
| 452 | |||
| 453 | if (attr->type == PERF_TYPE_HW_CACHE) | ||
| 454 | return set_ext_hw_attr(hwc, attr); | ||
| 455 | |||
| 456 | if (attr->config >= x86_pmu.max_events) | ||
| 457 | return -EINVAL; | ||
| 458 | |||
| 459 | /* | ||
| 460 | * The generic map: | ||
| 461 | */ | ||
| 462 | config = x86_pmu.event_map(attr->config); | ||
| 463 | |||
| 464 | if (config == 0) | ||
| 465 | return -ENOENT; | ||
| 466 | |||
| 467 | if (config == -1LL) | ||
| 468 | return -EINVAL; | ||
| 469 | |||
| 470 | /* | ||
| 471 | * Branch tracing: | ||
| 472 | */ | ||
| 473 | if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) && | ||
| 474 | (hwc->sample_period == 1)) { | ||
| 475 | /* BTS is not supported by this architecture. */ | ||
| 476 | if (!x86_pmu.bts) | ||
| 477 | return -EOPNOTSUPP; | ||
| 478 | |||
| 479 | /* BTS is currently only allowed for user-mode. */ | ||
| 480 | if (!attr->exclude_kernel) | ||
| 481 | return -EOPNOTSUPP; | ||
| 482 | } | ||
| 483 | |||
| 484 | hwc->config |= config; | ||
| 485 | |||
| 486 | return 0; | ||
| 487 | } | ||
| 430 | 488 | ||
| 431 | static int x86_pmu_hw_config(struct perf_event *event) | 489 | static int x86_pmu_hw_config(struct perf_event *event) |
| 432 | { | 490 | { |
| @@ -493,66 +551,6 @@ static int __hw_perf_event_init(struct perf_event *event) | |||
| 493 | return x86_setup_perfctr(event); | 551 | return x86_setup_perfctr(event); |
| 494 | } | 552 | } |
| 495 | 553 | ||
| 496 | static int x86_setup_perfctr(struct perf_event *event) | ||
| 497 | { | ||
| 498 | struct perf_event_attr *attr = &event->attr; | ||
| 499 | struct hw_perf_event *hwc = &event->hw; | ||
| 500 | u64 config; | ||
| 501 | |||
| 502 | if (!hwc->sample_period) { | ||
| 503 | hwc->sample_period = x86_pmu.max_period; | ||
| 504 | hwc->last_period = hwc->sample_period; | ||
| 505 | atomic64_set(&hwc->period_left, hwc->sample_period); | ||
| 506 | } else { | ||
| 507 | /* | ||
| 508 | * If we have a PMU initialized but no APIC | ||
| 509 | * interrupts, we cannot sample hardware | ||
| 510 | * events (user-space has to fall back and | ||
| 511 | * sample via a hrtimer based software event): | ||
| 512 | */ | ||
| 513 | if (!x86_pmu.apic) | ||
| 514 | return -EOPNOTSUPP; | ||
| 515 | } | ||
| 516 | |||
| 517 | if (attr->type == PERF_TYPE_RAW) | ||
| 518 | return 0; | ||
| 519 | |||
| 520 | if (attr->type == PERF_TYPE_HW_CACHE) | ||
| 521 | return set_ext_hw_attr(hwc, attr); | ||
| 522 | |||
| 523 | if (attr->config >= x86_pmu.max_events) | ||
| 524 | return -EINVAL; | ||
| 525 | |||
| 526 | /* | ||
| 527 | * The generic map: | ||
| 528 | */ | ||
| 529 | config = x86_pmu.event_map(attr->config); | ||
| 530 | |||
| 531 | if (config == 0) | ||
| 532 | return -ENOENT; | ||
| 533 | |||
| 534 | if (config == -1LL) | ||
| 535 | return -EINVAL; | ||
| 536 | |||
| 537 | /* | ||
| 538 | * Branch tracing: | ||
| 539 | */ | ||
| 540 | if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) && | ||
| 541 | (hwc->sample_period == 1)) { | ||
| 542 | /* BTS is not supported by this architecture. */ | ||
| 543 | if (!x86_pmu.bts) | ||
| 544 | return -EOPNOTSUPP; | ||
| 545 | |||
| 546 | /* BTS is currently only allowed for user-mode. */ | ||
| 547 | if (!attr->exclude_kernel) | ||
| 548 | return -EOPNOTSUPP; | ||
| 549 | } | ||
| 550 | |||
| 551 | hwc->config |= config; | ||
| 552 | |||
| 553 | return 0; | ||
| 554 | } | ||
| 555 | |||
| 556 | static void x86_pmu_disable_all(void) | 554 | static void x86_pmu_disable_all(void) |
| 557 | { | 555 | { |
| 558 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | 556 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |