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authorMike Frysinger <vapier.adi@gmail.com>2008-08-06 05:23:50 -0400
committerBryan Wu <cooloney@kernel.org>2008-08-06 05:23:50 -0400
commit17e89bcfa12f71b840361da07fe6c2f9c48d0605 (patch)
treec5ab94b397bcdfc5ffe0363f24ff83e012e8801a /arch
parent67618fd8748a5d83f6bdcd578c8e748c3f47c4d4 (diff)
Blackfin arch: unify the duplicated portions of __start and split mach-specific pieces into _mach_early_start where they will be easier to trim over time
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/blackfin/mach-bf527/head.S132
-rw-r--r--arch/blackfin/mach-bf533/head.S131
-rw-r--r--arch/blackfin/mach-bf537/head.S132
-rw-r--r--arch/blackfin/mach-bf548/head.S133
-rw-r--r--arch/blackfin/mach-bf561/head.S136
-rw-r--r--arch/blackfin/mach-common/head.S131
6 files changed, 146 insertions, 649 deletions
diff --git a/arch/blackfin/mach-bf527/head.S b/arch/blackfin/mach-bf527/head.S
index 9173dcecd158..af20183d0d94 100644
--- a/arch/blackfin/mach-bf527/head.S
+++ b/arch/blackfin/mach-bf527/head.S
@@ -30,93 +30,16 @@
30#include <linux/linkage.h> 30#include <linux/linkage.h>
31#include <linux/init.h> 31#include <linux/init.h>
32#include <asm/blackfin.h> 32#include <asm/blackfin.h>
33#include <asm/trace.h>
34
35#ifdef CONFIG_BFIN_KERNEL_CLOCK 33#ifdef CONFIG_BFIN_KERNEL_CLOCK
36#include <asm/mach-common/clocks.h> 34#include <asm/mach-common/clocks.h>
37#include <asm/mach/mem_init.h> 35#include <asm/mach/mem_init.h>
38#endif 36#endif
39 37
40.extern ___bss_stop
41.extern ___bss_start
42.extern _bf53x_relocate_l1_mem 38.extern _bf53x_relocate_l1_mem
43 39
44#define INITIAL_STACK 0xFFB01000
45
46__INIT 40__INIT
47 41
48ENTRY(__start) 42ENTRY(_mach_early_start)
49 /* R0: argument of command line string, passed from uboot, save it */
50 R7 = R0;
51 /* Enable Cycle Counter and Nesting Of Interrupts */
52#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
53 R0 = SYSCFG_SNEN;
54#else
55 R0 = SYSCFG_SNEN | SYSCFG_CCEN;
56#endif
57 SYSCFG = R0;
58 R0 = 0;
59
60 /* Clear Out All the data and pointer Registers */
61 R1 = R0;
62 R2 = R0;
63 R3 = R0;
64 R4 = R0;
65 R5 = R0;
66 R6 = R0;
67
68 P0 = R0;
69 P1 = R0;
70 P2 = R0;
71 P3 = R0;
72 P4 = R0;
73 P5 = R0;
74
75 LC0 = r0;
76 LC1 = r0;
77 L0 = r0;
78 L1 = r0;
79 L2 = r0;
80 L3 = r0;
81
82 /* Clear Out All the DAG Registers */
83 B0 = r0;
84 B1 = r0;
85 B2 = r0;
86 B3 = r0;
87
88 I0 = r0;
89 I1 = r0;
90 I2 = r0;
91 I3 = r0;
92
93 M0 = r0;
94 M1 = r0;
95 M2 = r0;
96 M3 = r0;
97
98 trace_buffer_init(p0,r0);
99 P0 = R1;
100 R0 = R1;
101
102 /* Turn off the icache */
103 p0.l = LO(IMEM_CONTROL);
104 p0.h = HI(IMEM_CONTROL);
105 R1 = [p0];
106 R0 = ~ENICPLB;
107 R0 = R0 & R1;
108 [p0] = R0;
109 SSYNC;
110
111 /* Turn off the dcache */
112 p0.l = LO(DMEM_CONTROL);
113 p0.h = HI(DMEM_CONTROL);
114 R1 = [p0];
115 R0 = ~ENDCPLB;
116 R0 = R0 & R1;
117 [p0] = R0;
118 SSYNC;
119
120#if defined(CONFIG_BF527) 43#if defined(CONFIG_BF527)
121 p0.h = hi(EMAC_SYSTAT); 44 p0.h = hi(EMAC_SYSTAT);
122 p0.l = lo(EMAC_SYSTAT); 45 p0.l = lo(EMAC_SYSTAT);
@@ -152,57 +75,8 @@ ENTRY(__start)
152 w[p0] = r0.L; /* To enable UART clock */ 75 w[p0] = r0.L; /* To enable UART clock */
153 ssync; 76 ssync;
154 77
155 /* Initialize stack pointer */ 78 rts;
156 sp.l = lo(INITIAL_STACK); 79ENDPROC(_mach_early_start)
157 sp.h = hi(INITIAL_STACK);
158 fp = sp;
159 usp = sp;
160
161#ifdef CONFIG_EARLY_PRINTK
162 SP += -12;
163 call _init_early_exception_vectors;
164 SP += 12;
165#endif
166
167 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
168 call _bf53x_relocate_l1_mem;
169#ifdef CONFIG_BFIN_KERNEL_CLOCK
170 call _start_dma_code;
171#endif
172
173 /* This section keeps the processor in supervisor mode
174 * during kernel boot. Switches to user mode at end of boot.
175 * See page 3-9 of Hardware Reference manual for documentation.
176 */
177
178 /* EVT15 = _real_start */
179
180 p0.l = lo(EVT15);
181 p0.h = hi(EVT15);
182 p1.l = _real_start;
183 p1.h = _real_start;
184 [p0] = p1;
185 csync;
186
187 p0.l = lo(IMASK);
188 p0.h = hi(IMASK);
189 p1.l = IMASK_IVG15;
190 p1.h = 0x0;
191 [p0] = p1;
192 csync;
193
194 raise 15;
195 p0.l = .LWAIT_HERE;
196 p0.h = .LWAIT_HERE;
197 reti = p0;
198#if ANOMALY_05000281
199 nop; nop; nop;
200#endif
201 rti;
202
203.LWAIT_HERE:
204 jump .LWAIT_HERE;
205ENDPROC(__start)
206 80
207__FINIT 81__FINIT
208 82
diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S
index 7f0a7a0c6fd6..6603967367ec 100644
--- a/arch/blackfin/mach-bf533/head.S
+++ b/arch/blackfin/mach-bf533/head.S
@@ -30,74 +30,16 @@
30#include <linux/linkage.h> 30#include <linux/linkage.h>
31#include <linux/init.h> 31#include <linux/init.h>
32#include <asm/blackfin.h> 32#include <asm/blackfin.h>
33#include <asm/trace.h>
34#ifdef CONFIG_BFIN_KERNEL_CLOCK 33#ifdef CONFIG_BFIN_KERNEL_CLOCK
35#include <asm/mach-common/clocks.h> 34#include <asm/mach-common/clocks.h>
36#include <asm/mach/mem_init.h> 35#include <asm/mach/mem_init.h>
37#endif 36#endif
38 37
39.extern ___bss_stop
40.extern ___bss_start
41.extern _bf53x_relocate_l1_mem 38.extern _bf53x_relocate_l1_mem
42 39
43#define INITIAL_STACK 0xFFB01000
44
45__INIT 40__INIT
46 41
47ENTRY(__start) 42ENTRY(_mach_early_start)
48 /* R0: argument of command line string, passed from uboot, save it */
49 R7 = R0;
50 /* Enable Cycle Counter and Nesting Of Interrupts */
51#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
52 R0 = SYSCFG_SNEN;
53#else
54 R0 = SYSCFG_SNEN | SYSCFG_CCEN;
55#endif
56 SYSCFG = R0;
57 R0 = 0;
58
59 /* Clear Out All the data and pointer Registers */
60 R1 = R0;
61 R2 = R0;
62 R3 = R0;
63 R4 = R0;
64 R5 = R0;
65 R6 = R0;
66
67 P0 = R0;
68 P1 = R0;
69 P2 = R0;
70 P3 = R0;
71 P4 = R0;
72 P5 = R0;
73
74 LC0 = r0;
75 LC1 = r0;
76 L0 = r0;
77 L1 = r0;
78 L2 = r0;
79 L3 = r0;
80
81 /* Clear Out All the DAG Registers */
82 B0 = r0;
83 B1 = r0;
84 B2 = r0;
85 B3 = r0;
86
87 I0 = r0;
88 I1 = r0;
89 I2 = r0;
90 I3 = r0;
91
92 M0 = r0;
93 M1 = r0;
94 M2 = r0;
95 M3 = r0;
96
97 trace_buffer_init(p0,r0);
98 P0 = R1;
99 R0 = R1;
100
101 p0.h = hi(FIO_MASKA_C); 43 p0.h = hi(FIO_MASKA_C);
102 p0.l = lo(FIO_MASKA_C); 44 p0.l = lo(FIO_MASKA_C);
103 r0 = 0xFFFF(Z); 45 r0 = 0xFFFF(Z);
@@ -110,24 +52,6 @@ ENTRY(__start)
110 w[p0] = r0.L; /* Disable all interrupts */ 52 w[p0] = r0.L; /* Disable all interrupts */
111 ssync; 53 ssync;
112 54
113 /* Turn off the icache */
114 p0.l = LO(IMEM_CONTROL);
115 p0.h = HI(IMEM_CONTROL);
116 R1 = [p0];
117 R0 = ~ENICPLB;
118 R0 = R0 & R1;
119 [p0] = R0;
120 SSYNC;
121
122 /* Turn off the dcache */
123 p0.l = LO(DMEM_CONTROL);
124 p0.h = HI(DMEM_CONTROL);
125 R1 = [p0];
126 R0 = ~ENDCPLB;
127 R0 = R0 & R1;
128 [p0] = R0;
129 SSYNC;
130
131 /* Initialise UART - when booting from u-boot, the UART is not disabled 55 /* Initialise UART - when booting from u-boot, the UART is not disabled
132 * so if we dont initalize here, our serial console gets hosed */ 56 * so if we dont initalize here, our serial console gets hosed */
133 p0.h = hi(BFIN_UART_LCR); 57 p0.h = hi(BFIN_UART_LCR);
@@ -154,57 +78,8 @@ ENTRY(__start)
154 w[p0] = r0.L; /* To enable UART clock */ 78 w[p0] = r0.L; /* To enable UART clock */
155 ssync; 79 ssync;
156 80
157 /* Initialize stack pointer */ 81 rts;
158 sp.l = lo(INITIAL_STACK); 82ENDPROC(_mach_early_start)
159 sp.h = hi(INITIAL_STACK);
160 fp = sp;
161 usp = sp;
162
163#ifdef CONFIG_EARLY_PRINTK
164 SP += -12;
165 call _init_early_exception_vectors;
166 SP += 12;
167#endif
168
169 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
170 call _bf53x_relocate_l1_mem;
171#ifdef CONFIG_BFIN_KERNEL_CLOCK
172 call _start_dma_code;
173#endif
174
175 /* This section keeps the processor in supervisor mode
176 * during kernel boot. Switches to user mode at end of boot.
177 * See page 3-9 of Hardware Reference manual for documentation.
178 */
179
180 /* EVT15 = _real_start */
181
182 p0.l = lo(EVT15);
183 p0.h = hi(EVT15);
184 p1.l = _real_start;
185 p1.h = _real_start;
186 [p0] = p1;
187 csync;
188
189 p0.l = lo(IMASK);
190 p0.h = hi(IMASK);
191 p1.l = IMASK_IVG15;
192 p1.h = 0x0;
193 [p0] = p1;
194 csync;
195
196 raise 15;
197 p0.l = .LWAIT_HERE;
198 p0.h = .LWAIT_HERE;
199 reti = p0;
200#if ANOMALY_05000281
201 nop; nop; nop;
202#endif
203 rti;
204
205.LWAIT_HERE:
206 jump .LWAIT_HERE;
207ENDPROC(__start)
208 83
209__FINIT 84__FINIT
210 85
diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S
index c062acb04836..6a02e472587a 100644
--- a/arch/blackfin/mach-bf537/head.S
+++ b/arch/blackfin/mach-bf537/head.S
@@ -30,93 +30,16 @@
30#include <linux/linkage.h> 30#include <linux/linkage.h>
31#include <linux/init.h> 31#include <linux/init.h>
32#include <asm/blackfin.h> 32#include <asm/blackfin.h>
33#include <asm/trace.h>
34
35#ifdef CONFIG_BFIN_KERNEL_CLOCK 33#ifdef CONFIG_BFIN_KERNEL_CLOCK
36#include <asm/mach-common/clocks.h> 34#include <asm/mach-common/clocks.h>
37#include <asm/mach/mem_init.h> 35#include <asm/mach/mem_init.h>
38#endif 36#endif
39 37
40.extern ___bss_stop
41.extern ___bss_start
42.extern _bf53x_relocate_l1_mem 38.extern _bf53x_relocate_l1_mem
43 39
44#define INITIAL_STACK 0xFFB01000
45
46__INIT 40__INIT
47 41
48ENTRY(__start) 42ENTRY(_mach_early_start)
49 /* R0: argument of command line string, passed from uboot, save it */
50 R7 = R0;
51 /* Enable Cycle Counter and Nesting Of Interrupts */
52#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
53 R0 = SYSCFG_SNEN;
54#else
55 R0 = SYSCFG_SNEN | SYSCFG_CCEN;
56#endif
57 SYSCFG = R0;
58 R0 = 0;
59
60 /* Clear Out All the data and pointer Registers */
61 R1 = R0;
62 R2 = R0;
63 R3 = R0;
64 R4 = R0;
65 R5 = R0;
66 R6 = R0;
67
68 P0 = R0;
69 P1 = R0;
70 P2 = R0;
71 P3 = R0;
72 P4 = R0;
73 P5 = R0;
74
75 LC0 = r0;
76 LC1 = r0;
77 L0 = r0;
78 L1 = r0;
79 L2 = r0;
80 L3 = r0;
81
82 /* Clear Out All the DAG Registers */
83 B0 = r0;
84 B1 = r0;
85 B2 = r0;
86 B3 = r0;
87
88 I0 = r0;
89 I1 = r0;
90 I2 = r0;
91 I3 = r0;
92
93 M0 = r0;
94 M1 = r0;
95 M2 = r0;
96 M3 = r0;
97
98 trace_buffer_init(p0,r0);
99 P0 = R1;
100 R0 = R1;
101
102 /* Turn off the icache */
103 p0.l = LO(IMEM_CONTROL);
104 p0.h = HI(IMEM_CONTROL);
105 R1 = [p0];
106 R0 = ~ENICPLB;
107 R0 = R0 & R1;
108 [p0] = R0;
109 SSYNC;
110
111 /* Turn off the dcache */
112 p0.l = LO(DMEM_CONTROL);
113 p0.h = HI(DMEM_CONTROL);
114 R1 = [p0];
115 R0 = ~ENDCPLB;
116 R0 = R0 & R1;
117 [p0] = R0;
118 SSYNC;
119
120 /* Initialise General-Purpose I/O Modules on BF537 */ 43 /* Initialise General-Purpose I/O Modules on BF537 */
121 p0.h = hi(BFIN_PORT_MUX); 44 p0.h = hi(BFIN_PORT_MUX);
122 p0.l = lo(BFIN_PORT_MUX); 45 p0.l = lo(BFIN_PORT_MUX);
@@ -166,57 +89,8 @@ ENTRY(__start)
166 w[p0] = r0.L; /* To enable UART clock */ 89 w[p0] = r0.L; /* To enable UART clock */
167 ssync; 90 ssync;
168 91
169 /* Initialize stack pointer */ 92 rts;
170 sp.l = lo(INITIAL_STACK); 93ENDPROC(_mach_early_start)
171 sp.h = hi(INITIAL_STACK);
172 fp = sp;
173 usp = sp;
174
175#ifdef CONFIG_EARLY_PRINTK
176 SP += -12;
177 call _init_early_exception_vectors;
178 SP += 12;
179#endif
180
181 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
182 call _bf53x_relocate_l1_mem;
183#ifdef CONFIG_BFIN_KERNEL_CLOCK
184 call _start_dma_code;
185#endif
186
187 /* This section keeps the processor in supervisor mode
188 * during kernel boot. Switches to user mode at end of boot.
189 * See page 3-9 of Hardware Reference manual for documentation.
190 */
191
192 /* EVT15 = _real_start */
193
194 p0.l = lo(EVT15);
195 p0.h = hi(EVT15);
196 p1.l = _real_start;
197 p1.h = _real_start;
198 [p0] = p1;
199 csync;
200
201 p0.l = lo(IMASK);
202 p0.h = hi(IMASK);
203 p1.l = IMASK_IVG15;
204 p1.h = 0x0;
205 [p0] = p1;
206 csync;
207
208 raise 15;
209 p0.l = .LWAIT_HERE;
210 p0.h = .LWAIT_HERE;
211 reti = p0;
212#if ANOMALY_05000281
213 nop; nop; nop;
214#endif
215 rti;
216
217.LWAIT_HERE:
218 jump .LWAIT_HERE;
219ENDPROC(__start)
220 94
221__FINIT 95__FINIT
222 96
diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S
index 832a8d7212ac..cf94e1e222b8 100644
--- a/arch/blackfin/mach-bf548/head.S
+++ b/arch/blackfin/mach-bf548/head.S
@@ -30,145 +30,18 @@
30#include <linux/linkage.h> 30#include <linux/linkage.h>
31#include <linux/init.h> 31#include <linux/init.h>
32#include <asm/blackfin.h> 32#include <asm/blackfin.h>
33#include <asm/trace.h>
34#ifdef CONFIG_BFIN_KERNEL_CLOCK 33#ifdef CONFIG_BFIN_KERNEL_CLOCK
35#include <asm/mach-common/clocks.h> 34#include <asm/mach-common/clocks.h>
36#include <asm/mach/mem_init.h> 35#include <asm/mach/mem_init.h>
37#endif 36#endif
38 37
39.extern ___bss_stop
40.extern ___bss_start
41.extern _bf53x_relocate_l1_mem 38.extern _bf53x_relocate_l1_mem
42 39
43#define INITIAL_STACK 0xFFB01000
44
45__INIT 40__INIT
46 41
47ENTRY(__start) 42ENTRY(_mach_early_start)
48 /* R0: argument of command line string, passed from uboot, save it */ 43 rts;
49 R7 = R0; 44ENDPROC(_mach_early_start)
50 /* Enable Cycle Counter and Nesting Of Interrupts */
51#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
52 R0 = SYSCFG_SNEN;
53#else
54 R0 = SYSCFG_SNEN | SYSCFG_CCEN;
55#endif
56 SYSCFG = R0;
57 R0 = 0;
58
59 /* Clear Out All the data and pointer Registers*/
60 R1 = R0;
61 R2 = R0;
62 R3 = R0;
63 R4 = R0;
64 R5 = R0;
65 R6 = R0;
66
67 P0 = R0;
68 P1 = R0;
69 P2 = R0;
70 P3 = R0;
71 P4 = R0;
72 P5 = R0;
73
74 LC0 = r0;
75 LC1 = r0;
76 L0 = r0;
77 L1 = r0;
78 L2 = r0;
79 L3 = r0;
80
81 /* Clear Out All the DAG Registers*/
82 B0 = r0;
83 B1 = r0;
84 B2 = r0;
85 B3 = r0;
86
87 I0 = r0;
88 I1 = r0;
89 I2 = r0;
90 I3 = r0;
91
92 M0 = r0;
93 M1 = r0;
94 M2 = r0;
95 M3 = r0;
96
97 trace_buffer_init(p0,r0);
98 P0 = R1;
99 R0 = R1;
100
101 /* Turn off the icache */
102 p0.l = LO(IMEM_CONTROL);
103 p0.h = HI(IMEM_CONTROL);
104 R1 = [p0];
105 R0 = ~ENICPLB;
106 R0 = R0 & R1;
107 [p0] = R0;
108 SSYNC;
109
110 /* Turn off the dcache */
111 p0.l = LO(DMEM_CONTROL);
112 p0.h = HI(DMEM_CONTROL);
113 R1 = [p0];
114 R0 = ~ENDCPLB;
115 R0 = R0 & R1;
116 [p0] = R0;
117 SSYNC;
118
119 /* Initialize stack pointer */
120 SP.L = LO(INITIAL_STACK);
121 SP.H = HI(INITIAL_STACK);
122 FP = SP;
123 USP = SP;
124
125#ifdef CONFIG_EARLY_PRINTK
126 SP += -12;
127 call _init_early_exception_vectors;
128 SP += 12;
129#endif
130
131 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
132 call _bf53x_relocate_l1_mem;
133#ifdef CONFIG_BFIN_KERNEL_CLOCK
134 call _start_dma_code;
135#endif
136
137 /* This section keeps the processor in supervisor mode
138 * during kernel boot. Switches to user mode at end of boot.
139 * See page 3-9 of Hardware Reference manual for documentation.
140 */
141
142 /* EVT15 = _real_start */
143
144 p0.l = lo(EVT15);
145 p0.h = hi(EVT15);
146 p1.l = _real_start;
147 p1.h = _real_start;
148 [p0] = p1;
149 csync;
150
151 p0.l = lo(IMASK);
152 p0.h = hi(IMASK);
153 p1.l = IMASK_IVG15;
154 p1.h = 0x0;
155 [p0] = p1;
156 csync;
157
158 raise 15;
159 p0.l = .LWAIT_HERE;
160 p0.h = .LWAIT_HERE;
161 reti = p0;
162#if ANOMALY_05000281
163 nop;
164 nop;
165 nop;
166#endif
167 rti;
168
169.LWAIT_HERE:
170 jump .LWAIT_HERE;
171ENDPROC(__start)
172 45
173__FINIT 46__FINIT
174 47
diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S
index c541b312c25d..fe6f979947c6 100644
--- a/arch/blackfin/mach-bf561/head.S
+++ b/arch/blackfin/mach-bf561/head.S
@@ -30,93 +30,16 @@
30#include <linux/linkage.h> 30#include <linux/linkage.h>
31#include <linux/init.h> 31#include <linux/init.h>
32#include <asm/blackfin.h> 32#include <asm/blackfin.h>
33#include <asm/trace.h> 33#ifdef CONFIG_BFIN_KERNEL_CLOCK
34
35#if CONFIG_BFIN_KERNEL_CLOCK
36#include <asm/mach-common/clocks.h> 34#include <asm/mach-common/clocks.h>
37#include <asm/mach/mem_init.h> 35#include <asm/mach/mem_init.h>
38#endif 36#endif
39 37
40.extern ___bss_stop
41.extern ___bss_start
42.extern _bf53x_relocate_l1_mem 38.extern _bf53x_relocate_l1_mem
43 39
44#define INITIAL_STACK 0xFFB01000
45
46__INIT 40__INIT
47 41
48ENTRY(__start) 42ENTRY(_mach_early_start)
49 /* R0: argument of command line string, passed from uboot, save it */
50 R7 = R0;
51 /* Enable Cycle Counter and Nesting Of Interrupts */
52#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
53 R0 = SYSCFG_SNEN;
54#else
55 R0 = SYSCFG_SNEN | SYSCFG_CCEN;
56#endif
57 SYSCFG = R0;
58 R0 = 0;
59
60 /* Clear Out All the data and pointer Registers */
61 R1 = R0;
62 R2 = R0;
63 R3 = R0;
64 R4 = R0;
65 R5 = R0;
66 R6 = R0;
67
68 P0 = R0;
69 P1 = R0;
70 P2 = R0;
71 P3 = R0;
72 P4 = R0;
73 P5 = R0;
74
75 LC0 = r0;
76 LC1 = r0;
77 L0 = r0;
78 L1 = r0;
79 L2 = r0;
80 L3 = r0;
81
82 /* Clear Out All the DAG Registers */
83 B0 = r0;
84 B1 = r0;
85 B2 = r0;
86 B3 = r0;
87
88 I0 = r0;
89 I1 = r0;
90 I2 = r0;
91 I3 = r0;
92
93 M0 = r0;
94 M1 = r0;
95 M2 = r0;
96 M3 = r0;
97
98 trace_buffer_init(p0,r0);
99 P0 = R1;
100 R0 = R1;
101
102 /* Turn off the icache */
103 p0.l = LO(IMEM_CONTROL);
104 p0.h = HI(IMEM_CONTROL);
105 R1 = [p0];
106 R0 = ~ENICPLB;
107 R0 = R0 & R1;
108 [p0] = R0;
109 SSYNC;
110
111 /* Turn off the dcache */
112 p0.l = LO(DMEM_CONTROL);
113 p0.h = HI(DMEM_CONTROL);
114 R1 = [p0];
115 R0 = ~ENDCPLB;
116 R0 = R0 & R1;
117 [p0] = R0;
118 SSYNC;
119
120 /* Initialise UART - when booting from u-boot, the UART is not disabled 43 /* Initialise UART - when booting from u-boot, the UART is not disabled
121 * so if we dont initalize here, our serial console gets hosed */ 44 * so if we dont initalize here, our serial console gets hosed */
122 p0.h = hi(BFIN_UART_LCR); 45 p0.h = hi(BFIN_UART_LCR);
@@ -143,62 +66,13 @@ ENTRY(__start)
143 w[p0] = r0.L; /* To enable UART clock */ 66 w[p0] = r0.L; /* To enable UART clock */
144 ssync; 67 ssync;
145 68
146 /* Initialize stack pointer */ 69 rts;
147 sp.l = lo(INITIAL_STACK); 70ENDPROC(_mach_early_start)
148 sp.h = hi(INITIAL_STACK);
149 fp = sp;
150 usp = sp;
151
152#ifdef CONFIG_EARLY_PRINTK
153 SP += -12;
154 call _init_early_exception_vectors;
155 SP += 12;
156#endif
157
158 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
159 call _bf53x_relocate_l1_mem;
160#if CONFIG_BFIN_KERNEL_CLOCK
161 call _start_dma_code;
162#endif
163
164 /* This section keeps the processor in supervisor mode
165 * during kernel boot. Switches to user mode at end of boot.
166 * See page 3-9 of Hardware Reference manual for documentation.
167 */
168
169 /* EVT15 = _real_start */
170
171 p0.l = lo(EVT15);
172 p0.h = hi(EVT15);
173 p1.l = _real_start;
174 p1.h = _real_start;
175 [p0] = p1;
176 csync;
177
178 p0.l = lo(IMASK);
179 p0.h = hi(IMASK);
180 p1.l = IMASK_IVG15;
181 p1.h = 0x0;
182 [p0] = p1;
183 csync;
184
185 raise 15;
186 p0.l = .LWAIT_HERE;
187 p0.h = .LWAIT_HERE;
188 reti = p0;
189#if ANOMALY_05000281
190 nop; nop; nop;
191#endif
192 rti;
193
194.LWAIT_HERE:
195 jump .LWAIT_HERE;
196ENDPROC(__start)
197 71
198__FINIT 72__FINIT
199 73
200.section .l1.text 74.section .l1.text
201#if CONFIG_BFIN_KERNEL_CLOCK 75#ifdef CONFIG_BFIN_KERNEL_CLOCK
202ENTRY(_start_dma_code) 76ENTRY(_start_dma_code)
203 p0.h = hi(SICA_IWR0); 77 p0.h = hi(SICA_IWR0);
204 p0.l = lo(SICA_IWR0); 78 p0.l = lo(SICA_IWR0);
diff --git a/arch/blackfin/mach-common/head.S b/arch/blackfin/mach-common/head.S
index 6a989a031ed6..2c69ad49894e 100644
--- a/arch/blackfin/mach-common/head.S
+++ b/arch/blackfin/mach-common/head.S
@@ -14,13 +14,140 @@
14#include <asm/thread_info.h> 14#include <asm/thread_info.h>
15#include <asm/trace.h> 15#include <asm/trace.h>
16 16
17__INIT
18
19#define INITIAL_STACK (L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
20
21ENTRY(__start)
22 /* R0: argument of command line string, passed from uboot, save it */
23 R7 = R0;
24 /* Enable Cycle Counter and Nesting Of Interrupts */
25#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
26 R0 = SYSCFG_SNEN;
27#else
28 R0 = SYSCFG_SNEN | SYSCFG_CCEN;
29#endif
30 SYSCFG = R0;
31 R0 = 0;
32
33 /* Clear Out All the data and pointer Registers */
34 R1 = R0;
35 R2 = R0;
36 R3 = R0;
37 R4 = R0;
38 R5 = R0;
39 R6 = R0;
40
41 P0 = R0;
42 P1 = R0;
43 P2 = R0;
44 P3 = R0;
45 P4 = R0;
46 P5 = R0;
47
48 LC0 = r0;
49 LC1 = r0;
50 L0 = r0;
51 L1 = r0;
52 L2 = r0;
53 L3 = r0;
54
55 /* Clear Out All the DAG Registers */
56 B0 = r0;
57 B1 = r0;
58 B2 = r0;
59 B3 = r0;
60
61 I0 = r0;
62 I1 = r0;
63 I2 = r0;
64 I3 = r0;
65
66 M0 = r0;
67 M1 = r0;
68 M2 = r0;
69 M3 = r0;
70
71 trace_buffer_init(p0,r0);
72 P0 = R1;
73 R0 = R1;
74
75 /* Turn off the icache */
76 p0.l = LO(IMEM_CONTROL);
77 p0.h = HI(IMEM_CONTROL);
78 R1 = [p0];
79 R0 = ~ENICPLB;
80 R0 = R0 & R1;
81 [p0] = R0;
82 SSYNC;
83
84 /* Turn off the dcache */
85 p0.l = LO(DMEM_CONTROL);
86 p0.h = HI(DMEM_CONTROL);
87 R1 = [p0];
88 R0 = ~ENDCPLB;
89 R0 = R0 & R1;
90 [p0] = R0;
91 SSYNC;
92
93 /* Let each Blackfin family do its own thing */
94 call _mach_early_start;
95
96 /* Initialize stack pointer */
97 sp.l = lo(INITIAL_STACK);
98 sp.h = hi(INITIAL_STACK);
99 fp = sp;
100 usp = sp;
101
102#ifdef CONFIG_EARLY_PRINTK
103 call _init_early_exception_vectors;
104#endif
105
106 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
107 call _bf53x_relocate_l1_mem;
108#ifdef CONFIG_BFIN_KERNEL_CLOCK
109 call _start_dma_code;
110#endif
111
112 /* This section keeps the processor in supervisor mode
113 * during kernel boot. Switches to user mode at end of boot.
114 * See page 3-9 of Hardware Reference manual for documentation.
115 */
116
117 /* EVT15 = _real_start */
118
119 p0.l = lo(EVT15);
120 p0.h = hi(EVT15);
121 p1.l = _real_start;
122 p1.h = _real_start;
123 [p0] = p1;
124 csync;
125
126 p0.l = lo(IMASK);
127 p0.h = hi(IMASK);
128 p1.l = IMASK_IVG15;
129 p1.h = 0x0;
130 [p0] = p1;
131 csync;
132
133 raise 15;
134 p0.l = .LWAIT_HERE;
135 p0.h = .LWAIT_HERE;
136 reti = p0;
137#if ANOMALY_05000281
138 nop; nop; nop;
139#endif
140 rti;
141
142.LWAIT_HERE:
143 jump .LWAIT_HERE;
144ENDPROC(__start)
145
17/* A little BF561 glue ... */ 146/* A little BF561 glue ... */
18#ifndef WDOG_CTL 147#ifndef WDOG_CTL
19# define WDOG_CTL WDOGA_CTL 148# define WDOG_CTL WDOGA_CTL
20#endif 149#endif
21 150
22__INIT
23
24ENTRY(_real_start) 151ENTRY(_real_start)
25 /* Enable nested interrupts */ 152 /* Enable nested interrupts */
26 [--sp] = reti; 153 [--sp] = reti;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-24 13:50:59 -0500