diff options
author | Peter Zijlstra <peterz@infradead.org> | 2009-03-05 14:34:21 -0500 |
---|---|---|
committer | Ingo Molnar <mingo@elte.hu> | 2009-03-05 14:37:21 -0500 |
commit | b5e8acf66ff5db707c7e08df49fdf6b415878442 (patch) | |
tree | 79ee6e9ad1f772ebadb65307e719f980bb0bde43 /arch | |
parent | b0f3f28e0f14eb335f67bfaae33ce8b8d74fd58b (diff) |
perfcounters: IRQ and NMI support on AMD CPUs, fix
The BKGD suggests that counter width on AMD CPUs is 48 for all
existing models (it certainly is for mine).
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/x86/kernel/cpu/perf_counter.c | 16 |
1 files changed, 2 insertions, 14 deletions
diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c index 6ebe9abf6aef..f5853718d4d3 100644 --- a/arch/x86/kernel/cpu/perf_counter.c +++ b/arch/x86/kernel/cpu/perf_counter.c | |||
@@ -959,20 +959,8 @@ static struct pmc_x86_ops *pmc_amd_init(void) | |||
959 | 959 | ||
960 | nr_counters_generic = 4; | 960 | nr_counters_generic = 4; |
961 | nr_counters_fixed = 0; | 961 | nr_counters_fixed = 0; |
962 | counter_value_mask = ~0ULL; | 962 | counter_value_mask = 0x0000FFFFFFFFFFFFULL; |
963 | 963 | counter_value_bits = 48; | |
964 | rdmsrl(MSR_K7_PERFCTR0, old); | ||
965 | wrmsrl(MSR_K7_PERFCTR0, counter_value_mask); | ||
966 | /* | ||
967 | * read the truncated mask | ||
968 | */ | ||
969 | rdmsrl(MSR_K7_PERFCTR0, counter_value_mask); | ||
970 | wrmsrl(MSR_K7_PERFCTR0, old); | ||
971 | |||
972 | bits = 32 + fls(counter_value_mask >> 32); | ||
973 | if (bits == 32) | ||
974 | bits = fls((u32)counter_value_mask); | ||
975 | counter_value_bits = bits; | ||
976 | 964 | ||
977 | pr_info("AMD Performance Monitoring support detected.\n"); | 965 | pr_info("AMD Performance Monitoring support detected.\n"); |
978 | 966 | ||