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authorKeshavamurthy, Anil S <anil.s.keshavamurthy@intel.com>2007-10-21 19:41:47 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-10-22 11:13:18 -0400
commita9c55b3ba8c3552d22155951e661767b3d424053 (patch)
tree5f33d8c8215063f17e37414cb99bc477e3dbda6b /arch
parent994a65e25df85abc465cfee495557200e8205f9e (diff)
Intel IOMMU: clflush_cache_range now takes size param
Introduce the size param for clflush_cache_range(). Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Cc: Andi Kleen <ak@suse.de> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Muli Ben-Yehuda <muli@il.ibm.com> Cc: "Siddha, Suresh B" <suresh.b.siddha@intel.com> Cc: Arjan van de Ven <arjan@infradead.org> Cc: Ashok Raj <ashok.raj@intel.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Christoph Lameter <clameter@sgi.com> Cc: Greg KH <greg@kroah.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@elte.hu> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/x86/mm/pageattr_64.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/x86/mm/pageattr_64.c b/arch/x86/mm/pageattr_64.c
index c7b7dfe1d405..c40afbaaf93d 100644
--- a/arch/x86/mm/pageattr_64.c
+++ b/arch/x86/mm/pageattr_64.c
@@ -61,10 +61,10 @@ static struct page *split_large_page(unsigned long address, pgprot_t prot,
61 return base; 61 return base;
62} 62}
63 63
64static void cache_flush_page(void *adr) 64void clflush_cache_range(void *adr, int size)
65{ 65{
66 int i; 66 int i;
67 for (i = 0; i < PAGE_SIZE; i += boot_cpu_data.x86_clflush_size) 67 for (i = 0; i < size; i += boot_cpu_data.x86_clflush_size)
68 clflush(adr+i); 68 clflush(adr+i);
69} 69}
70 70
@@ -80,7 +80,7 @@ static void flush_kernel_map(void *arg)
80 asm volatile("wbinvd" ::: "memory"); 80 asm volatile("wbinvd" ::: "memory");
81 else list_for_each_entry(pg, l, lru) { 81 else list_for_each_entry(pg, l, lru) {
82 void *adr = page_address(pg); 82 void *adr = page_address(pg);
83 cache_flush_page(adr); 83 clflush_cache_range(adr, PAGE_SIZE);
84 } 84 }
85 __flush_tlb_all(); 85 __flush_tlb_all();
86} 86}