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authorAl Viro <viro@ftp.linux.org.uk>2006-09-22 20:37:41 -0400
committerPaul Mackerras <paulus@samba.org>2006-09-26 01:41:02 -0400
commit8c42ec2c99502f8a81076f24f57775b9c646351a (patch)
tree64939c09e604671d729673b544a83342620faf89 /arch
parent62034f03380a64c0144b6721f4a2aa55d65346c1 (diff)
[POWERPC] maple/pci iomem annotations
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/platforms/maple/pci.c60
1 files changed, 30 insertions, 30 deletions
diff --git a/arch/powerpc/platforms/maple/pci.c b/arch/powerpc/platforms/maple/pci.c
index c3aa46b8e2b9..1b827618e05f 100644
--- a/arch/powerpc/platforms/maple/pci.c
+++ b/arch/powerpc/platforms/maple/pci.c
@@ -96,14 +96,14 @@ static unsigned long u3_agp_cfa1(u8 bus, u8 devfn, u8 off)
96 1UL; 96 1UL;
97} 97}
98 98
99static unsigned long u3_agp_cfg_access(struct pci_controller* hose, 99static volatile void __iomem *u3_agp_cfg_access(struct pci_controller* hose,
100 u8 bus, u8 dev_fn, u8 offset) 100 u8 bus, u8 dev_fn, u8 offset)
101{ 101{
102 unsigned int caddr; 102 unsigned int caddr;
103 103
104 if (bus == hose->first_busno) { 104 if (bus == hose->first_busno) {
105 if (dev_fn < (11 << 3)) 105 if (dev_fn < (11 << 3))
106 return 0; 106 return NULL;
107 caddr = u3_agp_cfa0(dev_fn, offset); 107 caddr = u3_agp_cfa0(dev_fn, offset);
108 } else 108 } else
109 caddr = u3_agp_cfa1(bus, dev_fn, offset); 109 caddr = u3_agp_cfa1(bus, dev_fn, offset);
@@ -114,14 +114,14 @@ static unsigned long u3_agp_cfg_access(struct pci_controller* hose,
114 } while (in_le32(hose->cfg_addr) != caddr); 114 } while (in_le32(hose->cfg_addr) != caddr);
115 115
116 offset &= 0x07; 116 offset &= 0x07;
117 return ((unsigned long)hose->cfg_data) + offset; 117 return hose->cfg_data + offset;
118} 118}
119 119
120static int u3_agp_read_config(struct pci_bus *bus, unsigned int devfn, 120static int u3_agp_read_config(struct pci_bus *bus, unsigned int devfn,
121 int offset, int len, u32 *val) 121 int offset, int len, u32 *val)
122{ 122{
123 struct pci_controller *hose; 123 struct pci_controller *hose;
124 unsigned long addr; 124 volatile void __iomem *addr;
125 125
126 hose = pci_bus_to_host(bus); 126 hose = pci_bus_to_host(bus);
127 if (hose == NULL) 127 if (hose == NULL)
@@ -136,13 +136,13 @@ static int u3_agp_read_config(struct pci_bus *bus, unsigned int devfn,
136 */ 136 */
137 switch (len) { 137 switch (len) {
138 case 1: 138 case 1:
139 *val = in_8((u8 *)addr); 139 *val = in_8(addr);
140 break; 140 break;
141 case 2: 141 case 2:
142 *val = in_le16((u16 *)addr); 142 *val = in_le16(addr);
143 break; 143 break;
144 default: 144 default:
145 *val = in_le32((u32 *)addr); 145 *val = in_le32(addr);
146 break; 146 break;
147 } 147 }
148 return PCIBIOS_SUCCESSFUL; 148 return PCIBIOS_SUCCESSFUL;
@@ -152,7 +152,7 @@ static int u3_agp_write_config(struct pci_bus *bus, unsigned int devfn,
152 int offset, int len, u32 val) 152 int offset, int len, u32 val)
153{ 153{
154 struct pci_controller *hose; 154 struct pci_controller *hose;
155 unsigned long addr; 155 volatile void __iomem *addr;
156 156
157 hose = pci_bus_to_host(bus); 157 hose = pci_bus_to_host(bus);
158 if (hose == NULL) 158 if (hose == NULL)
@@ -167,16 +167,16 @@ static int u3_agp_write_config(struct pci_bus *bus, unsigned int devfn,
167 */ 167 */
168 switch (len) { 168 switch (len) {
169 case 1: 169 case 1:
170 out_8((u8 *)addr, val); 170 out_8(addr, val);
171 (void) in_8((u8 *)addr); 171 (void) in_8(addr);
172 break; 172 break;
173 case 2: 173 case 2:
174 out_le16((u16 *)addr, val); 174 out_le16(addr, val);
175 (void) in_le16((u16 *)addr); 175 (void) in_le16(addr);
176 break; 176 break;
177 default: 177 default:
178 out_le32((u32 *)addr, val); 178 out_le32(addr, val);
179 (void) in_le32((u32 *)addr); 179 (void) in_le32(addr);
180 break; 180 break;
181 } 181 }
182 return PCIBIOS_SUCCESSFUL; 182 return PCIBIOS_SUCCESSFUL;
@@ -198,22 +198,22 @@ static unsigned long u3_ht_cfa1(u8 bus, u8 devfn, u8 off)
198 return u3_ht_cfa0(devfn, off) + (bus << 16) + 0x01000000UL; 198 return u3_ht_cfa0(devfn, off) + (bus << 16) + 0x01000000UL;
199} 199}
200 200
201static unsigned long u3_ht_cfg_access(struct pci_controller* hose, 201static volatile void __iomem *u3_ht_cfg_access(struct pci_controller* hose,
202 u8 bus, u8 devfn, u8 offset) 202 u8 bus, u8 devfn, u8 offset)
203{ 203{
204 if (bus == hose->first_busno) { 204 if (bus == hose->first_busno) {
205 if (PCI_SLOT(devfn) == 0) 205 if (PCI_SLOT(devfn) == 0)
206 return 0; 206 return NULL;
207 return ((unsigned long)hose->cfg_data) + u3_ht_cfa0(devfn, offset); 207 return hose->cfg_data + u3_ht_cfa0(devfn, offset);
208 } else 208 } else
209 return ((unsigned long)hose->cfg_data) + u3_ht_cfa1(bus, devfn, offset); 209 return hose->cfg_data + u3_ht_cfa1(bus, devfn, offset);
210} 210}
211 211
212static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, 212static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
213 int offset, int len, u32 *val) 213 int offset, int len, u32 *val)
214{ 214{
215 struct pci_controller *hose; 215 struct pci_controller *hose;
216 unsigned long addr; 216 volatile void __iomem *addr;
217 217
218 hose = pci_bus_to_host(bus); 218 hose = pci_bus_to_host(bus);
219 if (hose == NULL) 219 if (hose == NULL)
@@ -232,13 +232,13 @@ static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
232 */ 232 */
233 switch (len) { 233 switch (len) {
234 case 1: 234 case 1:
235 *val = in_8((u8 *)addr); 235 *val = in_8(addr);
236 break; 236 break;
237 case 2: 237 case 2:
238 *val = in_le16((u16 *)addr); 238 *val = in_le16(addr);
239 break; 239 break;
240 default: 240 default:
241 *val = in_le32((u32 *)addr); 241 *val = in_le32(addr);
242 break; 242 break;
243 } 243 }
244 return PCIBIOS_SUCCESSFUL; 244 return PCIBIOS_SUCCESSFUL;
@@ -248,7 +248,7 @@ static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
248 int offset, int len, u32 val) 248 int offset, int len, u32 val)
249{ 249{
250 struct pci_controller *hose; 250 struct pci_controller *hose;
251 unsigned long addr; 251 volatile void __iomem *addr;
252 252
253 hose = pci_bus_to_host(bus); 253 hose = pci_bus_to_host(bus);
254 if (hose == NULL) 254 if (hose == NULL)
@@ -266,16 +266,16 @@ static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
266 */ 266 */
267 switch (len) { 267 switch (len) {
268 case 1: 268 case 1:
269 out_8((u8 *)addr, val); 269 out_8(addr, val);
270 (void) in_8((u8 *)addr); 270 (void) in_8(addr);
271 break; 271 break;
272 case 2: 272 case 2:
273 out_le16((u16 *)addr, val); 273 out_le16(addr, val);
274 (void) in_le16((u16 *)addr); 274 (void) in_le16(addr);
275 break; 275 break;
276 default: 276 default:
277 out_le32((u32 *)addr, val); 277 out_le32(addr, val);
278 (void) in_le32((u32 *)addr); 278 (void) in_le32(addr);
279 break; 279 break;
280 } 280 }
281 return PCIBIOS_SUCCESSFUL; 281 return PCIBIOS_SUCCESSFUL;
@@ -315,7 +315,7 @@ static void __init setup_u3_ht(struct pci_controller* hose)
315 * the reg address cell, we shall fix that by killing struct 315 * the reg address cell, we shall fix that by killing struct
316 * reg_property and using some accessor functions instead 316 * reg_property and using some accessor functions instead
317 */ 317 */
318 hose->cfg_data = (volatile unsigned char *)ioremap(0xf2000000, 0x02000000); 318 hose->cfg_data = ioremap(0xf2000000, 0x02000000);
319 319
320 hose->first_busno = 0; 320 hose->first_busno = 0;
321 hose->last_busno = 0xef; 321 hose->last_busno = 0xef;