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authorTrond Myklebust <Trond.Myklebust@netapp.com>2006-06-20 08:59:45 -0400
committerTrond Myklebust <Trond.Myklebust@netapp.com>2006-06-20 08:59:45 -0400
commitd59bf96cdde5b874a57bfd1425faa45da915d0b7 (patch)
tree351a40b72514d620e5bebea2de38c26f23277ffc /arch
parent28df955a2ad484d602314b30183ea8496a9aa34a (diff)
parent25f42b6af09e34c3f92107b36b5aa6edc2fdba2f (diff)
Merge branch 'master' of /home/trondmy/kernel/linux-2.6/
Diffstat (limited to 'arch')
-rw-r--r--arch/alpha/Kconfig2
-rw-r--r--arch/arm/mach-imx/irq.c2
-rw-r--r--arch/arm/mach-integrator/integrator_cp.c5
-rw-r--r--arch/arm/mach-pxa/spitz.c1
-rw-r--r--arch/arm/mach-sa1100/neponset.c8
-rw-r--r--arch/arm/mach-versatile/core.c5
-rw-r--r--arch/i386/kernel/cpu/cpufreq/acpi-cpufreq.c20
-rw-r--r--arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c11
-rw-r--r--arch/i386/kernel/cpu/cpufreq/longhaul.c20
-rw-r--r--arch/i386/kernel/cpu/cpufreq/longrun.c1
-rw-r--r--arch/i386/kernel/cpu/cpufreq/powernow-k7.c13
-rw-r--r--arch/i386/kernel/cpu/cpufreq/powernow-k8.c344
-rw-r--r--arch/i386/kernel/cpu/cpufreq/powernow-k8.h40
-rw-r--r--arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c12
-rw-r--r--arch/mips/Kconfig244
-rw-r--r--arch/mips/Makefile37
-rw-r--r--arch/mips/au1000/common/au1xxx_irqmap.c4
-rw-r--r--arch/mips/au1000/common/pci.c16
-rw-r--r--arch/mips/au1000/common/setup.c6
-rw-r--r--arch/mips/au1000/common/time.c9
-rw-r--r--arch/mips/au1000/csb250/irqmap.c4
-rw-r--r--arch/mips/au1000/db1x00/irqmap.c4
-rw-r--r--arch/mips/au1000/hydrogen3/irqmap.c4
-rw-r--r--arch/mips/au1000/mtx-1/irqmap.c4
-rw-r--r--arch/mips/au1000/pb1000/irqmap.c4
-rw-r--r--arch/mips/au1000/pb1100/irqmap.c4
-rw-r--r--arch/mips/au1000/pb1200/irqmap.c4
-rw-r--r--arch/mips/au1000/pb1500/irqmap.c4
-rw-r--r--arch/mips/au1000/pb1550/irqmap.c4
-rw-r--r--arch/mips/au1000/xxs1500/irqmap.c4
-rw-r--r--arch/mips/basler/excite/Makefile9
-rw-r--r--arch/mips/basler/excite/excite_dbg_io.c122
-rw-r--r--arch/mips/basler/excite/excite_device.c404
-rw-r--r--arch/mips/basler/excite/excite_flashtest.c294
-rw-r--r--arch/mips/basler/excite/excite_fpga.h80
-rw-r--r--arch/mips/basler/excite/excite_iodev.c183
-rw-r--r--arch/mips/basler/excite/excite_iodev.h10
-rw-r--r--arch/mips/basler/excite/excite_irq.c129
-rw-r--r--arch/mips/basler/excite/excite_procfs.c81
-rw-r--r--arch/mips/basler/excite/excite_prom.c148
-rw-r--r--arch/mips/basler/excite/excite_setup.c307
-rw-r--r--arch/mips/cobalt/console.c5
-rw-r--r--arch/mips/cobalt/setup.c43
-rw-r--r--arch/mips/configs/atlas_defconfig11
-rw-r--r--arch/mips/configs/bigsur_defconfig11
-rw-r--r--arch/mips/configs/capcella_defconfig11
-rw-r--r--arch/mips/configs/cobalt_defconfig11
-rw-r--r--arch/mips/configs/db1000_defconfig11
-rw-r--r--arch/mips/configs/db1100_defconfig11
-rw-r--r--arch/mips/configs/db1200_defconfig11
-rw-r--r--arch/mips/configs/db1500_defconfig11
-rw-r--r--arch/mips/configs/db1550_defconfig11
-rw-r--r--arch/mips/configs/ddb5477_defconfig11
-rw-r--r--arch/mips/configs/decstation_defconfig13
-rw-r--r--arch/mips/configs/e55_defconfig11
-rw-r--r--arch/mips/configs/emma2rh_defconfig1207
-rw-r--r--arch/mips/configs/ev64120_defconfig11
-rw-r--r--arch/mips/configs/ev96100_defconfig11
-rw-r--r--arch/mips/configs/excite_defconfig1220
-rw-r--r--arch/mips/configs/ip22_defconfig11
-rw-r--r--arch/mips/configs/ip27_defconfig13
-rw-r--r--arch/mips/configs/ip32_defconfig11
-rw-r--r--arch/mips/configs/it8172_defconfig11
-rw-r--r--arch/mips/configs/ivr_defconfig11
-rw-r--r--arch/mips/configs/jaguar-atx_defconfig11
-rw-r--r--arch/mips/configs/jmr3927_defconfig11
-rw-r--r--arch/mips/configs/lasat200_defconfig11
-rw-r--r--arch/mips/configs/malta_defconfig11
-rw-r--r--arch/mips/configs/mipssim_defconfig11
-rw-r--r--arch/mips/configs/mpc30x_defconfig11
-rw-r--r--arch/mips/configs/ocelot_3_defconfig11
-rw-r--r--arch/mips/configs/ocelot_c_defconfig11
-rw-r--r--arch/mips/configs/ocelot_defconfig11
-rw-r--r--arch/mips/configs/ocelot_g_defconfig11
-rw-r--r--arch/mips/configs/pb1100_defconfig11
-rw-r--r--arch/mips/configs/pb1500_defconfig11
-rw-r--r--arch/mips/configs/pb1550_defconfig11
-rw-r--r--arch/mips/configs/pnx8550-jbs_defconfig11
-rw-r--r--arch/mips/configs/pnx8550-v2pci_defconfig11
-rw-r--r--arch/mips/configs/qemu_defconfig11
-rw-r--r--arch/mips/configs/rbhma4500_defconfig11
-rw-r--r--arch/mips/configs/rm200_defconfig11
-rw-r--r--arch/mips/configs/sb1250-swarm_defconfig11
-rw-r--r--arch/mips/configs/sead_defconfig11
-rw-r--r--arch/mips/configs/tb0226_defconfig11
-rw-r--r--arch/mips/configs/tb0229_defconfig11
-rw-r--r--arch/mips/configs/tb0287_defconfig11
-rw-r--r--arch/mips/configs/workpad_defconfig11
-rw-r--r--arch/mips/configs/wrppmc_defconfig (renamed from arch/mips/configs/ddb5476_defconfig)359
-rw-r--r--arch/mips/configs/yosemite_defconfig11
-rw-r--r--arch/mips/ddb5xxx/common/prom.c8
-rw-r--r--arch/mips/ddb5xxx/ddb5074/Makefile8
-rw-r--r--arch/mips/ddb5xxx/ddb5074/irq.c169
-rw-r--r--arch/mips/ddb5xxx/ddb5074/nile4_pic.c286
-rw-r--r--arch/mips/ddb5xxx/ddb5074/setup.c234
-rw-r--r--arch/mips/ddb5xxx/ddb5476/Makefile9
-rw-r--r--arch/mips/ddb5xxx/ddb5476/dbg_io.c136
-rw-r--r--arch/mips/ddb5xxx/ddb5476/irq.c165
-rw-r--r--arch/mips/ddb5xxx/ddb5476/nile4_pic.c190
-rw-r--r--arch/mips/ddb5xxx/ddb5476/setup.c296
-rw-r--r--arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c109
-rw-r--r--arch/mips/ddb5xxx/ddb5477/setup.c2
-rw-r--r--arch/mips/dec/setup.c2
-rw-r--r--arch/mips/dec/time.c2
-rw-r--r--arch/mips/defconfig11
-rw-r--r--arch/mips/emma2rh/common/Makefile13
-rw-r--r--arch/mips/emma2rh/common/irq.c108
-rw-r--r--arch/mips/emma2rh/common/irq_emma2rh.c134
-rw-r--r--arch/mips/emma2rh/common/prom.c77
-rw-r--r--arch/mips/emma2rh/markeins/Makefile13
-rw-r--r--arch/mips/emma2rh/markeins/irq.c134
-rw-r--r--arch/mips/emma2rh/markeins/irq_markeins.c197
-rw-r--r--arch/mips/emma2rh/markeins/led.c60
-rw-r--r--arch/mips/emma2rh/markeins/platform.c170
-rw-r--r--arch/mips/emma2rh/markeins/setup.c182
-rw-r--r--arch/mips/galileo-boards/ev96100/setup.c2
-rw-r--r--arch/mips/gt64120/ev64120/setup.c2
-rw-r--r--arch/mips/gt64120/momenco_ocelot/setup.c2
-rw-r--r--arch/mips/gt64120/wrppmc/Makefile14
-rw-r--r--arch/mips/gt64120/wrppmc/int-handler.S59
-rw-r--r--arch/mips/gt64120/wrppmc/irq.c63
-rw-r--r--arch/mips/gt64120/wrppmc/pci.c53
-rw-r--r--arch/mips/gt64120/wrppmc/reset.c50
-rw-r--r--arch/mips/gt64120/wrppmc/setup.c173
-rw-r--r--arch/mips/gt64120/wrppmc/time.c57
-rw-r--r--arch/mips/ite-boards/generic/it8172_setup.c76
-rw-r--r--arch/mips/jazz/setup.c2
-rw-r--r--arch/mips/jmr3927/rbhma3100/setup.c61
-rw-r--r--arch/mips/kernel/Makefile2
-rw-r--r--arch/mips/kernel/apm.c605
-rw-r--r--arch/mips/kernel/asm-offsets.c66
-rw-r--r--arch/mips/kernel/branch.c2
-rw-r--r--arch/mips/kernel/i8259.c4
-rw-r--r--arch/mips/kernel/irixsig.c2
-rw-r--r--arch/mips/kernel/ptrace.c26
-rw-r--r--arch/mips/kernel/ptrace32.c16
-rw-r--r--arch/mips/kernel/r4k_switch.S13
-rw-r--r--arch/mips/kernel/setup.c56
-rw-r--r--arch/mips/kernel/traps.c9
-rw-r--r--arch/mips/lasat/setup.c2
-rw-r--r--arch/mips/lib/Makefile3
-rw-r--r--arch/mips/lib/ashldi3.c29
-rw-r--r--arch/mips/lib/ashrdi3.c31
-rw-r--r--arch/mips/lib/libgcc.h26
-rw-r--r--arch/mips/lib/lshrdi3.c29
-rw-r--r--arch/mips/math-emu/cp1emu.c15
-rw-r--r--arch/mips/math-emu/ieee754.h2
-rw-r--r--arch/mips/math-emu/kernel_linkage.c24
-rw-r--r--arch/mips/mips-boards/atlas/atlas_setup.c2
-rw-r--r--arch/mips/mips-boards/generic/memory.c9
-rw-r--r--arch/mips/mips-boards/malta/malta_setup.c12
-rw-r--r--arch/mips/mips-boards/malta/malta_smp.c19
-rw-r--r--arch/mips/mips-boards/sead/sead_setup.c2
-rw-r--r--arch/mips/mips-boards/sim/sim_setup.c2
-rw-r--r--arch/mips/mips-boards/sim/sim_smp.c21
-rw-r--r--arch/mips/mm/tlb-r4k.c1
-rw-r--r--arch/mips/momentum/jaguar_atx/setup.c2
-rw-r--r--arch/mips/momentum/ocelot_3/setup.c2
-rw-r--r--arch/mips/momentum/ocelot_c/setup.c2
-rw-r--r--arch/mips/momentum/ocelot_g/setup.c2
-rw-r--r--arch/mips/pci/Makefile7
-rw-r--r--arch/mips/pci/fixup-ddb5074.c21
-rw-r--r--arch/mips/pci/fixup-emma2rh.c102
-rw-r--r--arch/mips/pci/fixup-excite.c36
-rw-r--r--arch/mips/pci/fixup-wrppmc.c37
-rw-r--r--arch/mips/pci/ops-bridge.c306
-rw-r--r--arch/mips/pci/ops-ddb5074.c271
-rw-r--r--arch/mips/pci/ops-ddb5476.c286
-rw-r--r--arch/mips/pci/ops-emma2rh.c186
-rw-r--r--arch/mips/pci/ops-it8172.c34
-rw-r--r--arch/mips/pci/ops-sni.c12
-rw-r--r--arch/mips/pci/ops-titan.c25
-rw-r--r--arch/mips/pci/pci-ddb5074.c79
-rw-r--r--arch/mips/pci/pci-ddb5476.c93
-rw-r--r--arch/mips/pci/pci-ddb5477.c32
-rw-r--r--arch/mips/pci/pci-emma2rh.c90
-rw-r--r--arch/mips/pci/pci-excite.c149
-rw-r--r--arch/mips/pci/pci-ip27.c295
-rw-r--r--arch/mips/pci/pci-jmr3927.c16
-rw-r--r--arch/mips/pci/pci-ocelot.c8
-rw-r--r--arch/mips/pci/pci-yosemite.c10
-rw-r--r--arch/mips/pci/pci.c5
-rw-r--r--arch/mips/philips/pnx8550/common/pci.c16
-rw-r--r--arch/mips/philips/pnx8550/common/setup.c27
-rw-r--r--arch/mips/pmc-sierra/yosemite/setup.c2
-rw-r--r--arch/mips/qemu/Makefile2
-rw-r--r--arch/mips/qemu/q-reset.c34
-rw-r--r--arch/mips/qemu/q-setup.c6
-rw-r--r--arch/mips/sgi-ip22/ip22-setup.c2
-rw-r--r--arch/mips/sgi-ip27/Kconfig38
-rw-r--r--arch/mips/sgi-ip27/ip27-init.c4
-rw-r--r--arch/mips/sgi-ip27/ip27-irq.c2
-rw-r--r--arch/mips/sgi-ip27/ip27-timer.c61
-rw-r--r--arch/mips/sgi-ip32/ip32-setup.c2
-rw-r--r--arch/mips/sibyte/bcm1480/time.c17
-rw-r--r--arch/mips/sibyte/sb1250/irq.c8
-rw-r--r--arch/mips/sibyte/swarm/setup.c4
-rw-r--r--arch/mips/sni/Makefile1
-rw-r--r--arch/mips/sni/setup.c135
-rw-r--r--arch/mips/sni/sniprom.c158
-rw-r--r--arch/mips/tx4927/common/tx4927_setup.c2
-rw-r--r--arch/mips/tx4938/common/setup.c2
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/setup.c5
-rw-r--r--arch/mips/vr41xx/Kconfig7
-rw-r--r--arch/mips/vr41xx/common/init.c2
-rw-r--r--arch/powerpc/kernel/prom_init.c10
-rw-r--r--arch/powerpc/kernel/signal_32.c11
-rw-r--r--arch/powerpc/kernel/signal_64.c2
-rw-r--r--arch/powerpc/mm/hash_native_64.c4
-rw-r--r--arch/powerpc/platforms/cell/setup.c11
-rw-r--r--arch/powerpc/platforms/pseries/setup.c8
-rw-r--r--arch/sparc/kernel/smp.c11
-rw-r--r--arch/sparc64/kernel/pci_sun4v.c124
-rw-r--r--arch/sparc64/kernel/smp.c35
-rw-r--r--arch/sparc64/kernel/sparc64_ksyms.c1
-rw-r--r--arch/sparc64/kernel/traps.c11
216 files changed, 9562 insertions, 3599 deletions
diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig
index 8290b69da202..213c7850d5fb 100644
--- a/arch/alpha/Kconfig
+++ b/arch/alpha/Kconfig
@@ -453,7 +453,7 @@ config ALPHA_IRONGATE
453 453
454config GENERIC_HWEIGHT 454config GENERIC_HWEIGHT
455 bool 455 bool
456 default y if !ALPHA_EV6 && !ALPHA_EV67 456 default y if !ALPHA_EV67
457 457
458config ALPHA_AVANTI 458config ALPHA_AVANTI
459 bool 459 bool
diff --git a/arch/arm/mach-imx/irq.c b/arch/arm/mach-imx/irq.c
index eeb8a6d4a399..a5de5f1da9f2 100644
--- a/arch/arm/mach-imx/irq.c
+++ b/arch/arm/mach-imx/irq.c
@@ -127,7 +127,7 @@ static void
127imx_gpio_ack_irq(unsigned int irq) 127imx_gpio_ack_irq(unsigned int irq)
128{ 128{
129 DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, irq); 129 DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, irq);
130 ISR(IRQ_TO_REG(irq)) |= 1 << ((irq - IRQ_GPIOA(0)) % 32); 130 ISR(IRQ_TO_REG(irq)) = 1 << ((irq - IRQ_GPIOA(0)) % 32);
131} 131}
132 132
133static void 133static void
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index a0724f2b24ce..9f55f5ae1044 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -232,8 +232,6 @@ static void __init intcp_init_irq(void)
232 for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) { 232 for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) {
233 if (i == 11) 233 if (i == 11)
234 i = 22; 234 i = 22;
235 if (i == IRQ_CP_CPPLDINT)
236 i++;
237 if (i == 29) 235 if (i == 29)
238 break; 236 break;
239 set_irq_chip(i, &pic_chip); 237 set_irq_chip(i, &pic_chip);
@@ -259,8 +257,7 @@ static void __init intcp_init_irq(void)
259 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 257 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
260 } 258 }
261 259
262 set_irq_handler(IRQ_CP_CPPLDINT, sic_handle_irq); 260 set_irq_chained_handler(IRQ_CP_CPPLDINT, sic_handle_irq);
263 pic_unmask_irq(IRQ_CP_CPPLDINT);
264} 261}
265 262
266/* 263/*
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 19b372df544a..44bcb8097c7a 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -371,6 +371,7 @@ static int spitz_ohci_init(struct device *dev)
371static struct pxaohci_platform_data spitz_ohci_platform_data = { 371static struct pxaohci_platform_data spitz_ohci_platform_data = {
372 .port_mode = PMM_NPS_MODE, 372 .port_mode = PMM_NPS_MODE,
373 .init = spitz_ohci_init, 373 .init = spitz_ohci_init,
374 .power_budget = 150,
374}; 375};
375 376
376 377
diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c
index 9e02bc3712a0..af6d2775cf82 100644
--- a/arch/arm/mach-sa1100/neponset.c
+++ b/arch/arm/mach-sa1100/neponset.c
@@ -59,6 +59,14 @@ neponset_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *reg
59 if (irr & (IRR_ETHERNET | IRR_USAR)) { 59 if (irr & (IRR_ETHERNET | IRR_USAR)) {
60 desc->chip->mask(irq); 60 desc->chip->mask(irq);
61 61
62 /*
63 * Ack the interrupt now to prevent re-entering
64 * this neponset handler. Again, this is safe
65 * since we'll check the IRR register prior to
66 * leaving.
67 */
68 desc->chip->ack(irq);
69
62 if (irr & IRR_ETHERNET) { 70 if (irr & IRR_ETHERNET) {
63 d = irq_desc + IRQ_NEPONSET_SMC9196; 71 d = irq_desc + IRQ_NEPONSET_SMC9196;
64 desc_handle_irq(IRQ_NEPONSET_SMC9196, d, regs); 72 desc_handle_irq(IRQ_NEPONSET_SMC9196, d, regs);
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 799697d32dec..cebd48a3dae4 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -112,10 +112,9 @@ void __init versatile_init_irq(void)
112{ 112{
113 unsigned int i; 113 unsigned int i;
114 114
115 vic_init(VA_VIC_BASE, IRQ_VIC_START, ~(1 << 31)); 115 vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0);
116 116
117 set_irq_handler(IRQ_VICSOURCE31, sic_handle_irq); 117 set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
118 enable_irq(IRQ_VICSOURCE31);
119 118
120 /* Do second interrupt controller */ 119 /* Do second interrupt controller */
121 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR); 120 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
diff --git a/arch/i386/kernel/cpu/cpufreq/acpi-cpufreq.c b/arch/i386/kernel/cpu/cpufreq/acpi-cpufreq.c
index 3852d0a4c1b5..1a7bdcef1926 100644
--- a/arch/i386/kernel/cpu/cpufreq/acpi-cpufreq.c
+++ b/arch/i386/kernel/cpu/cpufreq/acpi-cpufreq.c
@@ -104,7 +104,7 @@ acpi_processor_set_performance (
104{ 104{
105 u16 port = 0; 105 u16 port = 0;
106 u8 bit_width = 0; 106 u8 bit_width = 0;
107 int ret = 0; 107 int ret;
108 u32 value = 0; 108 u32 value = 0;
109 int i = 0; 109 int i = 0;
110 struct cpufreq_freqs cpufreq_freqs; 110 struct cpufreq_freqs cpufreq_freqs;
@@ -195,7 +195,6 @@ acpi_processor_set_performance (
195 udelay(10); 195 udelay(10);
196 } 196 }
197 } else { 197 } else {
198 i = 0;
199 value = (u32) data->acpi_data.states[state].status; 198 value = (u32) data->acpi_data.states[state].status;
200 } 199 }
201 200
@@ -444,14 +443,15 @@ static struct freq_attr* acpi_cpufreq_attr[] = {
444}; 443};
445 444
446static struct cpufreq_driver acpi_cpufreq_driver = { 445static struct cpufreq_driver acpi_cpufreq_driver = {
447 .verify = acpi_cpufreq_verify, 446 .verify = acpi_cpufreq_verify,
448 .target = acpi_cpufreq_target, 447 .target = acpi_cpufreq_target,
449 .init = acpi_cpufreq_cpu_init, 448 .init = acpi_cpufreq_cpu_init,
450 .exit = acpi_cpufreq_cpu_exit, 449 .exit = acpi_cpufreq_cpu_exit,
451 .resume = acpi_cpufreq_resume, 450 .resume = acpi_cpufreq_resume,
452 .name = "acpi-cpufreq", 451 .name = "acpi-cpufreq",
453 .owner = THIS_MODULE, 452 .owner = THIS_MODULE,
454 .attr = acpi_cpufreq_attr, 453 .attr = acpi_cpufreq_attr,
454 .flags = CPUFREQ_STICKY,
455}; 455};
456 456
457 457
diff --git a/arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c b/arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c
index f275e0d4aee5..0d49d73d1b71 100644
--- a/arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c
+++ b/arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * (C) 2004 Sebastian Witt <se.witt@gmx.net> 2 * (C) 2004-2006 Sebastian Witt <se.witt@gmx.net>
3 * 3 *
4 * Licensed under the terms of the GNU GPL License version 2. 4 * Licensed under the terms of the GNU GPL License version 2.
5 * Based upon reverse engineered information 5 * Based upon reverse engineered information
@@ -90,7 +90,7 @@ static int nforce2_calc_pll(unsigned int fsb)
90 90
91 /* Try to calculate multiplier and divider up to 4 times */ 91 /* Try to calculate multiplier and divider up to 4 times */
92 while (((mul == 0) || (div == 0)) && (tried <= 3)) { 92 while (((mul == 0) || (div == 0)) && (tried <= 3)) {
93 for (xdiv = 1; xdiv <= 0x80; xdiv++) 93 for (xdiv = 2; xdiv <= 0x80; xdiv++)
94 for (xmul = 1; xmul <= 0xfe; xmul++) 94 for (xmul = 1; xmul <= 0xfe; xmul++)
95 if (nforce2_calc_fsb(NFORCE2_PLL(xmul, xdiv)) == 95 if (nforce2_calc_fsb(NFORCE2_PLL(xmul, xdiv)) ==
96 fsb + tried) { 96 fsb + tried) {
@@ -117,8 +117,7 @@ static void nforce2_write_pll(int pll)
117 int temp; 117 int temp;
118 118
119 /* Set the pll addr. to 0x00 */ 119 /* Set the pll addr. to 0x00 */
120 temp = 0x00; 120 pci_write_config_dword(nforce2_chipset_dev, NFORCE2_PLLADR, 0);
121 pci_write_config_dword(nforce2_chipset_dev, NFORCE2_PLLADR, temp);
122 121
123 /* Now write the value in all 64 registers */ 122 /* Now write the value in all 64 registers */
124 for (temp = 0; temp <= 0x3f; temp++) 123 for (temp = 0; temp <= 0x3f; temp++)
@@ -266,7 +265,7 @@ static int nforce2_target(struct cpufreq_policy *policy,
266 if (freqs.old == freqs.new) 265 if (freqs.old == freqs.new)
267 return 0; 266 return 0;
268 267
269 dprintk(KERN_INFO "cpufreq: Old CPU frequency %d kHz, new %d kHz\n", 268 dprintk("Old CPU frequency %d kHz, new %d kHz\n",
270 freqs.old, freqs.new); 269 freqs.old, freqs.new);
271 270
272 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); 271 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
@@ -278,7 +277,7 @@ static int nforce2_target(struct cpufreq_policy *policy,
278 printk(KERN_ERR "cpufreq: Changing FSB to %d failed\n", 277 printk(KERN_ERR "cpufreq: Changing FSB to %d failed\n",
279 target_fsb); 278 target_fsb);
280 else 279 else
281 dprintk(KERN_INFO "cpufreq: Changed FSB successfully to %d\n", 280 dprintk("Changed FSB successfully to %d\n",
282 target_fsb); 281 target_fsb);
283 282
284 /* Enable IRQs */ 283 /* Enable IRQs */
diff --git a/arch/i386/kernel/cpu/cpufreq/longhaul.c b/arch/i386/kernel/cpu/cpufreq/longhaul.c
index 8ef38544453c..146f607e9c44 100644
--- a/arch/i386/kernel/cpu/cpufreq/longhaul.c
+++ b/arch/i386/kernel/cpu/cpufreq/longhaul.c
@@ -77,13 +77,17 @@ static char speedbuffer[8];
77 77
78static char *print_speed(int speed) 78static char *print_speed(int speed)
79{ 79{
80 if (speed > 1000) { 80 if (speed < 1000) {
81 if (speed%1000 == 0) 81 snprintf(speedbuffer, sizeof(speedbuffer),"%dMHz", speed);
82 sprintf (speedbuffer, "%dGHz", speed/1000); 82 return speedbuffer;
83 else 83 }
84 sprintf (speedbuffer, "%d.%dGHz", speed/1000, (speed%1000)/100); 84
85 } else 85 if (speed%1000 == 0)
86 sprintf (speedbuffer, "%dMHz", speed); 86 snprintf(speedbuffer, sizeof(speedbuffer),
87 "%dGHz", speed/1000);
88 else
89 snprintf(speedbuffer, sizeof(speedbuffer),
90 "%d.%dGHz", speed/1000, (speed%1000)/100);
87 91
88 return speedbuffer; 92 return speedbuffer;
89} 93}
@@ -675,7 +679,7 @@ static int __init longhaul_init(void)
675 679
676static void __exit longhaul_exit(void) 680static void __exit longhaul_exit(void)
677{ 681{
678 int i=0; 682 int i;
679 683
680 for (i=0; i < numscales; i++) { 684 for (i=0; i < numscales; i++) {
681 if (clock_ratio[i] == maxmult) { 685 if (clock_ratio[i] == maxmult) {
diff --git a/arch/i386/kernel/cpu/cpufreq/longrun.c b/arch/i386/kernel/cpu/cpufreq/longrun.c
index e3868de4dc2e..b2689514295a 100644
--- a/arch/i386/kernel/cpu/cpufreq/longrun.c
+++ b/arch/i386/kernel/cpu/cpufreq/longrun.c
@@ -223,7 +223,6 @@ static unsigned int __init longrun_determine_freqs(unsigned int *low_freq,
223 /* set to 0 to try_hi perf_pctg */ 223 /* set to 0 to try_hi perf_pctg */
224 msr_lo &= 0xFFFFFF80; 224 msr_lo &= 0xFFFFFF80;
225 msr_hi &= 0xFFFFFF80; 225 msr_hi &= 0xFFFFFF80;
226 msr_lo |= 0;
227 msr_hi |= try_hi; 226 msr_hi |= try_hi;
228 wrmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi); 227 wrmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi);
229 228
diff --git a/arch/i386/kernel/cpu/cpufreq/powernow-k7.c b/arch/i386/kernel/cpu/cpufreq/powernow-k7.c
index 2bf4237cb94e..694d4793bf6a 100644
--- a/arch/i386/kernel/cpu/cpufreq/powernow-k7.c
+++ b/arch/i386/kernel/cpu/cpufreq/powernow-k7.c
@@ -452,23 +452,23 @@ static int powernow_decode_bios (int maxfid, int startvid)
452 452
453 pst = (struct pst_s *) p; 453 pst = (struct pst_s *) p;
454 454
455 for (i = 0 ; i <psb->numpst; i++) { 455 for (j=0; j<psb->numpst; j++) {
456 pst = (struct pst_s *) p; 456 pst = (struct pst_s *) p;
457 number_scales = pst->numpstates; 457 number_scales = pst->numpstates;
458 458
459 if ((etuple == pst->cpuid) && check_fsb(pst->fsbspeed) && 459 if ((etuple == pst->cpuid) && check_fsb(pst->fsbspeed) &&
460 (maxfid==pst->maxfid) && (startvid==pst->startvid)) 460 (maxfid==pst->maxfid) && (startvid==pst->startvid))
461 { 461 {
462 dprintk ("PST:%d (@%p)\n", i, pst); 462 dprintk ("PST:%d (@%p)\n", j, pst);
463 dprintk (" cpuid: 0x%x fsb: %d maxFID: 0x%x startvid: 0x%x\n", 463 dprintk (" cpuid: 0x%x fsb: %d maxFID: 0x%x startvid: 0x%x\n",
464 pst->cpuid, pst->fsbspeed, pst->maxfid, pst->startvid); 464 pst->cpuid, pst->fsbspeed, pst->maxfid, pst->startvid);
465 465
466 ret = get_ranges ((char *) pst + sizeof (struct pst_s)); 466 ret = get_ranges ((char *) pst + sizeof (struct pst_s));
467 return ret; 467 return ret;
468
469 } else { 468 } else {
469 unsigned int k;
470 p = (char *) pst + sizeof (struct pst_s); 470 p = (char *) pst + sizeof (struct pst_s);
471 for (j=0 ; j < number_scales; j++) 471 for (k=0; k<number_scales; k++)
472 p+=2; 472 p+=2;
473 } 473 }
474 } 474 }
@@ -581,10 +581,7 @@ static int __init powernow_cpu_init (struct cpufreq_policy *policy)
581 581
582 rdmsrl (MSR_K7_FID_VID_STATUS, fidvidstatus.val); 582 rdmsrl (MSR_K7_FID_VID_STATUS, fidvidstatus.val);
583 583
584 /* recalibrate cpu_khz */ 584 recalibrate_cpu_khz();
585 result = recalibrate_cpu_khz();
586 if (result)
587 return result;
588 585
589 fsb = (10 * cpu_khz) / fid_codes[fidvidstatus.bits.CFID]; 586 fsb = (10 * cpu_khz) / fid_codes[fidvidstatus.bits.CFID];
590 if (!fsb) { 587 if (!fsb) {
diff --git a/arch/i386/kernel/cpu/cpufreq/powernow-k8.c b/arch/i386/kernel/cpu/cpufreq/powernow-k8.c
index 71fffa174425..b4277f58f40c 100644
--- a/arch/i386/kernel/cpu/cpufreq/powernow-k8.c
+++ b/arch/i386/kernel/cpu/cpufreq/powernow-k8.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * (c) 2003, 2004, 2005 Advanced Micro Devices, Inc. 2 * (c) 2003-2006 Advanced Micro Devices, Inc.
3 * Your use of this code is subject to the terms and conditions of the 3 * Your use of this code is subject to the terms and conditions of the
4 * GNU general public license version 2. See "COPYING" or 4 * GNU general public license version 2. See "COPYING" or
5 * http://www.gnu.org/licenses/gpl.html 5 * http://www.gnu.org/licenses/gpl.html
@@ -14,13 +14,13 @@
14 * Based upon datasheets & sample CPUs kindly provided by AMD. 14 * Based upon datasheets & sample CPUs kindly provided by AMD.
15 * 15 *
16 * Valuable input gratefully received from Dave Jones, Pavel Machek, 16 * Valuable input gratefully received from Dave Jones, Pavel Machek,
17 * Dominik Brodowski, and others. 17 * Dominik Brodowski, Jacob Shin, and others.
18 * Originally developed by Paul Devriendt. 18 * Originally developed by Paul Devriendt.
19 * Processor information obtained from Chapter 9 (Power and Thermal Management) 19 * Processor information obtained from Chapter 9 (Power and Thermal Management)
20 * of the "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD 20 * of the "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD
21 * Opteron Processors" available for download from www.amd.com 21 * Opteron Processors" available for download from www.amd.com
22 * 22 *
23 * Tables for specific CPUs can be infrerred from 23 * Tables for specific CPUs can be inferred from
24 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/30430.pdf 24 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/30430.pdf
25 */ 25 */
26 26
@@ -46,7 +46,7 @@
46 46
47#define PFX "powernow-k8: " 47#define PFX "powernow-k8: "
48#define BFX PFX "BIOS error: " 48#define BFX PFX "BIOS error: "
49#define VERSION "version 1.60.2" 49#define VERSION "version 2.00.00"
50#include "powernow-k8.h" 50#include "powernow-k8.h"
51 51
52/* serialize freq changes */ 52/* serialize freq changes */
@@ -54,6 +54,8 @@ static DEFINE_MUTEX(fidvid_mutex);
54 54
55static struct powernow_k8_data *powernow_data[NR_CPUS]; 55static struct powernow_k8_data *powernow_data[NR_CPUS];
56 56
57static int cpu_family = CPU_OPTERON;
58
57#ifndef CONFIG_SMP 59#ifndef CONFIG_SMP
58static cpumask_t cpu_core_map[1]; 60static cpumask_t cpu_core_map[1];
59#endif 61#endif
@@ -64,16 +66,36 @@ static u32 find_freq_from_fid(u32 fid)
64 return 800 + (fid * 100); 66 return 800 + (fid * 100);
65} 67}
66 68
69
67/* Return a frequency in KHz, given an input fid */ 70/* Return a frequency in KHz, given an input fid */
68static u32 find_khz_freq_from_fid(u32 fid) 71static u32 find_khz_freq_from_fid(u32 fid)
69{ 72{
70 return 1000 * find_freq_from_fid(fid); 73 return 1000 * find_freq_from_fid(fid);
71} 74}
72 75
73/* Return a voltage in miliVolts, given an input vid */ 76/* Return a frequency in MHz, given an input fid and did */
74static u32 find_millivolts_from_vid(struct powernow_k8_data *data, u32 vid) 77static u32 find_freq_from_fiddid(u32 fid, u32 did)
78{
79 return 100 * (fid + 0x10) >> did;
80}
81
82static u32 find_khz_freq_from_fiddid(u32 fid, u32 did)
75{ 83{
76 return 1550-vid*25; 84 return 1000 * find_freq_from_fiddid(fid, did);
85}
86
87static u32 find_fid_from_pstate(u32 pstate)
88{
89 u32 hi, lo;
90 rdmsr(MSR_PSTATE_DEF_BASE + pstate, lo, hi);
91 return lo & HW_PSTATE_FID_MASK;
92}
93
94static u32 find_did_from_pstate(u32 pstate)
95{
96 u32 hi, lo;
97 rdmsr(MSR_PSTATE_DEF_BASE + pstate, lo, hi);
98 return (lo & HW_PSTATE_DID_MASK) >> HW_PSTATE_DID_SHIFT;
77} 99}
78 100
79/* Return the vco fid for an input fid 101/* Return the vco fid for an input fid
@@ -98,6 +120,9 @@ static int pending_bit_stuck(void)
98{ 120{
99 u32 lo, hi; 121 u32 lo, hi;
100 122
123 if (cpu_family)
124 return 0;
125
101 rdmsr(MSR_FIDVID_STATUS, lo, hi); 126 rdmsr(MSR_FIDVID_STATUS, lo, hi);
102 return lo & MSR_S_LO_CHANGE_PENDING ? 1 : 0; 127 return lo & MSR_S_LO_CHANGE_PENDING ? 1 : 0;
103} 128}
@@ -111,6 +136,14 @@ static int query_current_values_with_pending_wait(struct powernow_k8_data *data)
111 u32 lo, hi; 136 u32 lo, hi;
112 u32 i = 0; 137 u32 i = 0;
113 138
139 if (cpu_family) {
140 rdmsr(MSR_PSTATE_STATUS, lo, hi);
141 i = lo & HW_PSTATE_MASK;
142 rdmsr(MSR_PSTATE_DEF_BASE + i, lo, hi);
143 data->currfid = lo & HW_PSTATE_FID_MASK;
144 data->currdid = (lo & HW_PSTATE_DID_MASK) >> HW_PSTATE_DID_SHIFT;
145 return 0;
146 }
114 do { 147 do {
115 if (i++ > 10000) { 148 if (i++ > 10000) {
116 dprintk("detected change pending stuck\n"); 149 dprintk("detected change pending stuck\n");
@@ -175,7 +208,7 @@ static int write_new_fid(struct powernow_k8_data *data, u32 fid)
175 do { 208 do {
176 wrmsr(MSR_FIDVID_CTL, lo, data->plllock * PLL_LOCK_CONVERSION); 209 wrmsr(MSR_FIDVID_CTL, lo, data->plllock * PLL_LOCK_CONVERSION);
177 if (i++ > 100) { 210 if (i++ > 100) {
178 printk(KERN_ERR PFX "internal error - pending bit very stuck - no further pstate changes possible\n"); 211 printk(KERN_ERR PFX "Hardware error - pending bit very stuck - no further pstate changes possible\n");
179 return 1; 212 return 1;
180 } 213 }
181 } while (query_current_values_with_pending_wait(data)); 214 } while (query_current_values_with_pending_wait(data));
@@ -255,7 +288,15 @@ static int decrease_vid_code_by_step(struct powernow_k8_data *data, u32 reqvid,
255 return 0; 288 return 0;
256} 289}
257 290
258/* Change the fid and vid, by the 3 phases. */ 291/* Change hardware pstate by single MSR write */
292static int transition_pstate(struct powernow_k8_data *data, u32 pstate)
293{
294 wrmsr(MSR_PSTATE_CTRL, pstate, 0);
295 data->currfid = find_fid_from_pstate(pstate);
296 return 0;
297}
298
299/* Change Opteron/Athlon64 fid and vid, by the 3 phases. */
259static int transition_fid_vid(struct powernow_k8_data *data, u32 reqfid, u32 reqvid) 300static int transition_fid_vid(struct powernow_k8_data *data, u32 reqfid, u32 reqvid)
260{ 301{
261 if (core_voltage_pre_transition(data, reqvid)) 302 if (core_voltage_pre_transition(data, reqvid))
@@ -474,26 +515,35 @@ static int check_supported_cpu(unsigned int cpu)
474 goto out; 515 goto out;
475 516
476 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE); 517 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
477 if ((eax & CPUID_XFAM) != CPUID_XFAM_K8) 518 if (((eax & CPUID_XFAM) != CPUID_XFAM_K8) &&
519 ((eax & CPUID_XFAM) < CPUID_XFAM_10H))
478 goto out; 520 goto out;
479 521
480 if (((eax & CPUID_USE_XFAM_XMOD) != CPUID_USE_XFAM_XMOD) || 522 if ((eax & CPUID_XFAM) == CPUID_XFAM_K8) {
481 ((eax & CPUID_XMOD) > CPUID_XMOD_REV_G)) { 523 if (((eax & CPUID_USE_XFAM_XMOD) != CPUID_USE_XFAM_XMOD) ||
482 printk(KERN_INFO PFX "Processor cpuid %x not supported\n", eax); 524 ((eax & CPUID_XMOD) > CPUID_XMOD_REV_G)) {
483 goto out; 525 printk(KERN_INFO PFX "Processor cpuid %x not supported\n", eax);
484 } 526 goto out;
527 }
485 528
486 eax = cpuid_eax(CPUID_GET_MAX_CAPABILITIES); 529 eax = cpuid_eax(CPUID_GET_MAX_CAPABILITIES);
487 if (eax < CPUID_FREQ_VOLT_CAPABILITIES) { 530 if (eax < CPUID_FREQ_VOLT_CAPABILITIES) {
488 printk(KERN_INFO PFX 531 printk(KERN_INFO PFX
489 "No frequency change capabilities detected\n"); 532 "No frequency change capabilities detected\n");
490 goto out; 533 goto out;
491 } 534 }
492 535
493 cpuid(CPUID_FREQ_VOLT_CAPABILITIES, &eax, &ebx, &ecx, &edx); 536 cpuid(CPUID_FREQ_VOLT_CAPABILITIES, &eax, &ebx, &ecx, &edx);
494 if ((edx & P_STATE_TRANSITION_CAPABLE) != P_STATE_TRANSITION_CAPABLE) { 537 if ((edx & P_STATE_TRANSITION_CAPABLE) != P_STATE_TRANSITION_CAPABLE) {
495 printk(KERN_INFO PFX "Power state transitions not supported\n"); 538 printk(KERN_INFO PFX "Power state transitions not supported\n");
496 goto out; 539 goto out;
540 }
541 } else { /* must be a HW Pstate capable processor */
542 cpuid(CPUID_FREQ_VOLT_CAPABILITIES, &eax, &ebx, &ecx, &edx);
543 if ((edx & USE_HW_PSTATE) == USE_HW_PSTATE)
544 cpu_family = CPU_HW_PSTATE;
545 else
546 goto out;
497 } 547 }
498 548
499 rc = 1; 549 rc = 1;
@@ -547,12 +597,18 @@ static void print_basics(struct powernow_k8_data *data)
547{ 597{
548 int j; 598 int j;
549 for (j = 0; j < data->numps; j++) { 599 for (j = 0; j < data->numps; j++) {
550 if (data->powernow_table[j].frequency != CPUFREQ_ENTRY_INVALID) 600 if (data->powernow_table[j].frequency != CPUFREQ_ENTRY_INVALID) {
551 printk(KERN_INFO PFX " %d : fid 0x%x (%d MHz), vid 0x%x (%d mV)\n", j, 601 if (cpu_family) {
602 printk(KERN_INFO PFX " %d : fid 0x%x gid 0x%x (%d MHz)\n", j, (data->powernow_table[j].index & 0xff00) >> 8,
603 (data->powernow_table[j].index & 0xff0000) >> 16,
604 data->powernow_table[j].frequency/1000);
605 } else {
606 printk(KERN_INFO PFX " %d : fid 0x%x (%d MHz), vid 0x%x\n", j,
552 data->powernow_table[j].index & 0xff, 607 data->powernow_table[j].index & 0xff,
553 data->powernow_table[j].frequency/1000, 608 data->powernow_table[j].frequency/1000,
554 data->powernow_table[j].index >> 8, 609 data->powernow_table[j].index >> 8);
555 find_millivolts_from_vid(data, data->powernow_table[j].index >> 8)); 610 }
611 }
556 } 612 }
557 if (data->batps) 613 if (data->batps)
558 printk(KERN_INFO PFX "Only %d pstates on battery\n", data->batps); 614 printk(KERN_INFO PFX "Only %d pstates on battery\n", data->batps);
@@ -702,7 +758,7 @@ static int find_psb_table(struct powernow_k8_data *data)
702#ifdef CONFIG_X86_POWERNOW_K8_ACPI 758#ifdef CONFIG_X86_POWERNOW_K8_ACPI
703static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index) 759static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index)
704{ 760{
705 if (!data->acpi_data.state_count) 761 if (!data->acpi_data.state_count || cpu_family)
706 return; 762 return;
707 763
708 data->irt = (data->acpi_data.states[index].control >> IRT_SHIFT) & IRT_MASK; 764 data->irt = (data->acpi_data.states[index].control >> IRT_SHIFT) & IRT_MASK;
@@ -715,9 +771,8 @@ static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned
715 771
716static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data) 772static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data)
717{ 773{
718 int i;
719 int cntlofreq = 0;
720 struct cpufreq_frequency_table *powernow_table; 774 struct cpufreq_frequency_table *powernow_table;
775 int ret_val;
721 776
722 if (acpi_processor_register_performance(&data->acpi_data, data->cpu)) { 777 if (acpi_processor_register_performance(&data->acpi_data, data->cpu)) {
723 dprintk("register performance failed: bad ACPI data\n"); 778 dprintk("register performance failed: bad ACPI data\n");
@@ -746,6 +801,85 @@ static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data)
746 goto err_out; 801 goto err_out;
747 } 802 }
748 803
804 if (cpu_family)
805 ret_val = fill_powernow_table_pstate(data, powernow_table);
806 else
807 ret_val = fill_powernow_table_fidvid(data, powernow_table);
808 if (ret_val)
809 goto err_out_mem;
810
811 powernow_table[data->acpi_data.state_count].frequency = CPUFREQ_TABLE_END;
812 powernow_table[data->acpi_data.state_count].index = 0;
813 data->powernow_table = powernow_table;
814
815 /* fill in data */
816 data->numps = data->acpi_data.state_count;
817 print_basics(data);
818 powernow_k8_acpi_pst_values(data, 0);
819
820 /* notify BIOS that we exist */
821 acpi_processor_notify_smm(THIS_MODULE);
822
823 return 0;
824
825err_out_mem:
826 kfree(powernow_table);
827
828err_out:
829 acpi_processor_unregister_performance(&data->acpi_data, data->cpu);
830
831 /* data->acpi_data.state_count informs us at ->exit() whether ACPI was used */
832 data->acpi_data.state_count = 0;
833
834 return -ENODEV;
835}
836
837static int fill_powernow_table_pstate(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table)
838{
839 int i;
840
841 for (i = 0; i < data->acpi_data.state_count; i++) {
842 u32 index;
843 u32 hi = 0, lo = 0;
844 u32 fid;
845 u32 did;
846
847 index = data->acpi_data.states[i].control & HW_PSTATE_MASK;
848 if (index > MAX_HW_PSTATE) {
849 printk(KERN_ERR PFX "invalid pstate %d - bad value %d.\n", i, index);
850 printk(KERN_ERR PFX "Please report to BIOS manufacturer\n");
851 }
852 rdmsr(MSR_PSTATE_DEF_BASE + index, lo, hi);
853 if (!(hi & HW_PSTATE_VALID_MASK)) {
854 dprintk("invalid pstate %d, ignoring\n", index);
855 powernow_table[i].frequency = CPUFREQ_ENTRY_INVALID;
856 continue;
857 }
858
859 fid = lo & HW_PSTATE_FID_MASK;
860 did = (lo & HW_PSTATE_DID_MASK) >> HW_PSTATE_DID_SHIFT;
861
862 dprintk(" %d : fid 0x%x, did 0x%x\n", index, fid, did);
863
864 powernow_table[i].index = index | (fid << HW_FID_INDEX_SHIFT) | (did << HW_DID_INDEX_SHIFT);
865
866 powernow_table[i].frequency = find_khz_freq_from_fiddid(fid, did);
867
868 if (powernow_table[i].frequency != (data->acpi_data.states[i].core_frequency * 1000)) {
869 printk(KERN_INFO PFX "invalid freq entries %u kHz vs. %u kHz\n",
870 powernow_table[i].frequency,
871 (unsigned int) (data->acpi_data.states[i].core_frequency * 1000));
872 powernow_table[i].frequency = CPUFREQ_ENTRY_INVALID;
873 continue;
874 }
875 }
876 return 0;
877}
878
879static int fill_powernow_table_fidvid(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table)
880{
881 int i;
882 int cntlofreq = 0;
749 for (i = 0; i < data->acpi_data.state_count; i++) { 883 for (i = 0; i < data->acpi_data.state_count; i++) {
750 u32 fid; 884 u32 fid;
751 u32 vid; 885 u32 vid;
@@ -786,7 +920,7 @@ static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data)
786 if ((powernow_table[i].frequency != powernow_table[cntlofreq].frequency) || 920 if ((powernow_table[i].frequency != powernow_table[cntlofreq].frequency) ||
787 (powernow_table[i].index != powernow_table[cntlofreq].index)) { 921 (powernow_table[i].index != powernow_table[cntlofreq].index)) {
788 printk(KERN_ERR PFX "Too many lo freq table entries\n"); 922 printk(KERN_ERR PFX "Too many lo freq table entries\n");
789 goto err_out_mem; 923 return 1;
790 } 924 }
791 925
792 dprintk("double low frequency table entry, ignoring it.\n"); 926 dprintk("double low frequency table entry, ignoring it.\n");
@@ -804,31 +938,7 @@ static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data)
804 continue; 938 continue;
805 } 939 }
806 } 940 }
807
808 powernow_table[data->acpi_data.state_count].frequency = CPUFREQ_TABLE_END;
809 powernow_table[data->acpi_data.state_count].index = 0;
810 data->powernow_table = powernow_table;
811
812 /* fill in data */
813 data->numps = data->acpi_data.state_count;
814 print_basics(data);
815 powernow_k8_acpi_pst_values(data, 0);
816
817 /* notify BIOS that we exist */
818 acpi_processor_notify_smm(THIS_MODULE);
819
820 return 0; 941 return 0;
821
822err_out_mem:
823 kfree(powernow_table);
824
825err_out:
826 acpi_processor_unregister_performance(&data->acpi_data, data->cpu);
827
828 /* data->acpi_data.state_count informs us at ->exit() whether ACPI was used */
829 data->acpi_data.state_count = 0;
830
831 return -ENODEV;
832} 942}
833 943
834static void powernow_k8_cpu_exit_acpi(struct powernow_k8_data *data) 944static void powernow_k8_cpu_exit_acpi(struct powernow_k8_data *data)
@@ -844,20 +954,20 @@ static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned
844#endif /* CONFIG_X86_POWERNOW_K8_ACPI */ 954#endif /* CONFIG_X86_POWERNOW_K8_ACPI */
845 955
846/* Take a frequency, and issue the fid/vid transition command */ 956/* Take a frequency, and issue the fid/vid transition command */
847static int transition_frequency(struct powernow_k8_data *data, unsigned int index) 957static int transition_frequency_fidvid(struct powernow_k8_data *data, unsigned int index)
848{ 958{
849 u32 fid; 959 u32 fid = 0;
850 u32 vid; 960 u32 vid = 0;
851 int res, i; 961 int res, i;
852 struct cpufreq_freqs freqs; 962 struct cpufreq_freqs freqs;
853 963
854 dprintk("cpu %d transition to index %u\n", smp_processor_id(), index); 964 dprintk("cpu %d transition to index %u\n", smp_processor_id(), index);
855 965
966 /* fid/vid correctness check for k8 */
856 /* fid are the lower 8 bits of the index we stored into 967 /* fid are the lower 8 bits of the index we stored into
857 * the cpufreq frequency table in find_psb_table, vid are 968 * the cpufreq frequency table in find_psb_table, vid
858 * the upper 8 bits. 969 * are the upper 8 bits.
859 */ 970 */
860
861 fid = data->powernow_table[index].index & 0xFF; 971 fid = data->powernow_table[index].index & 0xFF;
862 vid = (data->powernow_table[index].index & 0xFF00) >> 8; 972 vid = (data->powernow_table[index].index & 0xFF00) >> 8;
863 973
@@ -881,22 +991,58 @@ static int transition_frequency(struct powernow_k8_data *data, unsigned int inde
881 991
882 dprintk("cpu %d, changing to fid 0x%x, vid 0x%x\n", 992 dprintk("cpu %d, changing to fid 0x%x, vid 0x%x\n",
883 smp_processor_id(), fid, vid); 993 smp_processor_id(), fid, vid);
884
885 freqs.cpu = data->cpu;
886 freqs.old = find_khz_freq_from_fid(data->currfid); 994 freqs.old = find_khz_freq_from_fid(data->currfid);
887 freqs.new = find_khz_freq_from_fid(fid); 995 freqs.new = find_khz_freq_from_fid(fid);
888 for_each_cpu_mask(i, cpu_core_map[data->cpu]) { 996
997 for_each_cpu_mask(i, *(data->available_cores)) {
889 freqs.cpu = i; 998 freqs.cpu = i;
890 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); 999 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
891 } 1000 }
892 1001
893 res = transition_fid_vid(data, fid, vid); 1002 res = transition_fid_vid(data, fid, vid);
894
895 freqs.new = find_khz_freq_from_fid(data->currfid); 1003 freqs.new = find_khz_freq_from_fid(data->currfid);
896 for_each_cpu_mask(i, cpu_core_map[data->cpu]) { 1004
1005 for_each_cpu_mask(i, *(data->available_cores)) {
897 freqs.cpu = i; 1006 freqs.cpu = i;
898 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); 1007 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
899 } 1008 }
1009 return res;
1010}
1011
1012/* Take a frequency, and issue the hardware pstate transition command */
1013static int transition_frequency_pstate(struct powernow_k8_data *data, unsigned int index)
1014{
1015 u32 fid = 0;
1016 u32 did = 0;
1017 u32 pstate = 0;
1018 int res, i;
1019 struct cpufreq_freqs freqs;
1020
1021 dprintk("cpu %d transition to index %u\n", smp_processor_id(), index);
1022
1023 /* get fid did for hardware pstate transition */
1024 pstate = index & HW_PSTATE_MASK;
1025 if (pstate > MAX_HW_PSTATE)
1026 return 0;
1027 fid = (index & HW_FID_INDEX_MASK) >> HW_FID_INDEX_SHIFT;
1028 did = (index & HW_DID_INDEX_MASK) >> HW_DID_INDEX_SHIFT;
1029 freqs.old = find_khz_freq_from_fiddid(data->currfid, data->currdid);
1030 freqs.new = find_khz_freq_from_fiddid(fid, did);
1031
1032 for_each_cpu_mask(i, *(data->available_cores)) {
1033 freqs.cpu = i;
1034 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
1035 }
1036
1037 res = transition_pstate(data, pstate);
1038 data->currfid = find_fid_from_pstate(pstate);
1039 data->currdid = find_did_from_pstate(pstate);
1040 freqs.new = find_khz_freq_from_fiddid(data->currfid, data->currdid);
1041
1042 for_each_cpu_mask(i, *(data->available_cores)) {
1043 freqs.cpu = i;
1044 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
1045 }
900 return res; 1046 return res;
901} 1047}
902 1048
@@ -933,18 +1079,21 @@ static int powernowk8_target(struct cpufreq_policy *pol, unsigned targfreq, unsi
933 dprintk("targ: cpu %d, %d kHz, min %d, max %d, relation %d\n", 1079 dprintk("targ: cpu %d, %d kHz, min %d, max %d, relation %d\n",
934 pol->cpu, targfreq, pol->min, pol->max, relation); 1080 pol->cpu, targfreq, pol->min, pol->max, relation);
935 1081
936 if (query_current_values_with_pending_wait(data)) { 1082 if (query_current_values_with_pending_wait(data))
937 ret = -EIO;
938 goto err_out; 1083 goto err_out;
939 }
940 1084
941 dprintk("targ: curr fid 0x%x, vid 0x%x\n", 1085 if (cpu_family)
1086 dprintk("targ: curr fid 0x%x, did 0x%x\n",
1087 data->currfid, data->currvid);
1088 else {
1089 dprintk("targ: curr fid 0x%x, vid 0x%x\n",
942 data->currfid, data->currvid); 1090 data->currfid, data->currvid);
943 1091
944 if ((checkvid != data->currvid) || (checkfid != data->currfid)) { 1092 if ((checkvid != data->currvid) || (checkfid != data->currfid)) {
945 printk(KERN_INFO PFX 1093 printk(KERN_INFO PFX
946 "error - out of sync, fix 0x%x 0x%x, vid 0x%x 0x%x\n", 1094 "error - out of sync, fix 0x%x 0x%x, vid 0x%x 0x%x\n",
947 checkfid, data->currfid, checkvid, data->currvid); 1095 checkfid, data->currfid, checkvid, data->currvid);
1096 }
948 } 1097 }
949 1098
950 if (cpufreq_frequency_table_target(pol, data->powernow_table, targfreq, relation, &newstate)) 1099 if (cpufreq_frequency_table_target(pol, data->powernow_table, targfreq, relation, &newstate))
@@ -954,7 +1103,11 @@ static int powernowk8_target(struct cpufreq_policy *pol, unsigned targfreq, unsi
954 1103
955 powernow_k8_acpi_pst_values(data, newstate); 1104 powernow_k8_acpi_pst_values(data, newstate);
956 1105
957 if (transition_frequency(data, newstate)) { 1106 if (cpu_family)
1107 ret = transition_frequency_pstate(data, newstate);
1108 else
1109 ret = transition_frequency_fidvid(data, newstate);
1110 if (ret) {
958 printk(KERN_ERR PFX "transition frequency failed\n"); 1111 printk(KERN_ERR PFX "transition frequency failed\n");
959 ret = 1; 1112 ret = 1;
960 mutex_unlock(&fidvid_mutex); 1113 mutex_unlock(&fidvid_mutex);
@@ -962,7 +1115,10 @@ static int powernowk8_target(struct cpufreq_policy *pol, unsigned targfreq, unsi
962 } 1115 }
963 mutex_unlock(&fidvid_mutex); 1116 mutex_unlock(&fidvid_mutex);
964 1117
965 pol->cur = find_khz_freq_from_fid(data->currfid); 1118 if (cpu_family)
1119 pol->cur = find_khz_freq_from_fiddid(data->currfid, data->currdid);
1120 else
1121 pol->cur = find_khz_freq_from_fid(data->currfid);
966 ret = 0; 1122 ret = 0;
967 1123
968err_out: 1124err_out:
@@ -1007,14 +1163,13 @@ static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol)
1007 * Use the PSB BIOS structure. This is only availabe on 1163 * Use the PSB BIOS structure. This is only availabe on
1008 * an UP version, and is deprecated by AMD. 1164 * an UP version, and is deprecated by AMD.
1009 */ 1165 */
1010
1011 if ((num_online_cpus() != 1) || (num_possible_cpus() != 1)) { 1166 if ((num_online_cpus() != 1) || (num_possible_cpus() != 1)) {
1012 printk(KERN_ERR PFX "MP systems not supported by PSB BIOS structure\n"); 1167 printk(KERN_ERR PFX "MP systems not supported by PSB BIOS structure\n");
1013 kfree(data); 1168 kfree(data);
1014 return -ENODEV; 1169 return -ENODEV;
1015 } 1170 }
1016 if (pol->cpu != 0) { 1171 if (pol->cpu != 0) {
1017 printk(KERN_ERR PFX "init not cpu 0\n"); 1172 printk(KERN_ERR PFX "No _PSS objects for CPU other than CPU0\n");
1018 kfree(data); 1173 kfree(data);
1019 return -ENODEV; 1174 return -ENODEV;
1020 } 1175 }
@@ -1042,20 +1197,28 @@ static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol)
1042 if (query_current_values_with_pending_wait(data)) 1197 if (query_current_values_with_pending_wait(data))
1043 goto err_out; 1198 goto err_out;
1044 1199
1045 fidvid_msr_init(); 1200 if (!cpu_family)
1201 fidvid_msr_init();
1046 1202
1047 /* run on any CPU again */ 1203 /* run on any CPU again */
1048 set_cpus_allowed(current, oldmask); 1204 set_cpus_allowed(current, oldmask);
1049 1205
1050 pol->governor = CPUFREQ_DEFAULT_GOVERNOR; 1206 pol->governor = CPUFREQ_DEFAULT_GOVERNOR;
1051 pol->cpus = cpu_core_map[pol->cpu]; 1207 if (cpu_family)
1208 pol->cpus = cpumask_of_cpu(pol->cpu);
1209 else
1210 pol->cpus = cpu_core_map[pol->cpu];
1211 data->available_cores = &(pol->cpus);
1052 1212
1053 /* Take a crude guess here. 1213 /* Take a crude guess here.
1054 * That guess was in microseconds, so multiply with 1000 */ 1214 * That guess was in microseconds, so multiply with 1000 */
1055 pol->cpuinfo.transition_latency = (((data->rvo + 8) * data->vstable * VST_UNITS_20US) 1215 pol->cpuinfo.transition_latency = (((data->rvo + 8) * data->vstable * VST_UNITS_20US)
1056 + (3 * (1 << data->irt) * 10)) * 1000; 1216 + (3 * (1 << data->irt) * 10)) * 1000;
1057 1217
1058 pol->cur = find_khz_freq_from_fid(data->currfid); 1218 if (cpu_family)
1219 pol->cur = find_khz_freq_from_fiddid(data->currfid, data->currdid);
1220 else
1221 pol->cur = find_khz_freq_from_fid(data->currfid);
1059 dprintk("policy current frequency %d kHz\n", pol->cur); 1222 dprintk("policy current frequency %d kHz\n", pol->cur);
1060 1223
1061 /* min/max the cpu is capable of */ 1224 /* min/max the cpu is capable of */
@@ -1069,8 +1232,12 @@ static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol)
1069 1232
1070 cpufreq_frequency_table_get_attr(data->powernow_table, pol->cpu); 1233 cpufreq_frequency_table_get_attr(data->powernow_table, pol->cpu);
1071 1234
1072 printk("cpu_init done, current fid 0x%x, vid 0x%x\n", 1235 if (cpu_family)
1073 data->currfid, data->currvid); 1236 dprintk("cpu_init done, current fid 0x%x, did 0x%x\n",
1237 data->currfid, data->currdid);
1238 else
1239 dprintk("cpu_init done, current fid 0x%x, vid 0x%x\n",
1240 data->currfid, data->currvid);
1074 1241
1075 powernow_data[pol->cpu] = data; 1242 powernow_data[pol->cpu] = data;
1076 1243
@@ -1156,8 +1323,9 @@ static int __cpuinit powernowk8_init(void)
1156 } 1323 }
1157 1324
1158 if (supported_cpus == num_online_cpus()) { 1325 if (supported_cpus == num_online_cpus()) {
1159 printk(KERN_INFO PFX "Found %d AMD Athlon 64 / Opteron " 1326 printk(KERN_INFO PFX "Found %d %s "
1160 "processors (" VERSION ")\n", supported_cpus); 1327 "processors (" VERSION ")\n", supported_cpus,
1328 boot_cpu_data.x86_model_id);
1161 return cpufreq_register_driver(&cpufreq_amd64_driver); 1329 return cpufreq_register_driver(&cpufreq_amd64_driver);
1162 } 1330 }
1163 1331
diff --git a/arch/i386/kernel/cpu/cpufreq/powernow-k8.h b/arch/i386/kernel/cpu/cpufreq/powernow-k8.h
index 79a7c5c87edc..bf8ad9e43da3 100644
--- a/arch/i386/kernel/cpu/cpufreq/powernow-k8.h
+++ b/arch/i386/kernel/cpu/cpufreq/powernow-k8.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * (c) 2003, 2004, 2005 Advanced Micro Devices, Inc. 2 * (c) 2003-2006 Advanced Micro Devices, Inc.
3 * Your use of this code is subject to the terms and conditions of the 3 * Your use of this code is subject to the terms and conditions of the
4 * GNU general public license version 2. See "COPYING" or 4 * GNU general public license version 2. See "COPYING" or
5 * http://www.gnu.org/licenses/gpl.html 5 * http://www.gnu.org/licenses/gpl.html
@@ -21,8 +21,8 @@ struct powernow_k8_data {
21 u32 plllock; /* pll lock time, units 1 us */ 21 u32 plllock; /* pll lock time, units 1 us */
22 u32 exttype; /* extended interface = 1 */ 22 u32 exttype; /* extended interface = 1 */
23 23
24 /* keep track of the current fid / vid */ 24 /* keep track of the current fid / vid or did */
25 u32 currvid, currfid; 25 u32 currvid, currfid, currdid;
26 26
27 /* the powernow_table includes all frequency and vid/fid pairings: 27 /* the powernow_table includes all frequency and vid/fid pairings:
28 * fid are the lower 8 bits of the index, vid are the upper 8 bits. 28 * fid are the lower 8 bits of the index, vid are the upper 8 bits.
@@ -34,6 +34,10 @@ struct powernow_k8_data {
34 * used to determine valid frequency/vid/fid states */ 34 * used to determine valid frequency/vid/fid states */
35 struct acpi_processor_performance acpi_data; 35 struct acpi_processor_performance acpi_data;
36#endif 36#endif
37 /* we need to keep track of associated cores, but let cpufreq
38 * handle hotplug events - so just point at cpufreq pol->cpus
39 * structure */
40 cpumask_t *available_cores;
37}; 41};
38 42
39 43
@@ -43,6 +47,7 @@ struct powernow_k8_data {
43#define CPUID_XFAM_K8 0 47#define CPUID_XFAM_K8 0
44#define CPUID_XMOD 0x000f0000 /* extended model */ 48#define CPUID_XMOD 0x000f0000 /* extended model */
45#define CPUID_XMOD_REV_G 0x00060000 49#define CPUID_XMOD_REV_G 0x00060000
50#define CPUID_XFAM_10H 0x00100000 /* family 0x10 */
46#define CPUID_USE_XFAM_XMOD 0x00000f00 51#define CPUID_USE_XFAM_XMOD 0x00000f00
47#define CPUID_GET_MAX_CAPABILITIES 0x80000000 52#define CPUID_GET_MAX_CAPABILITIES 0x80000000
48#define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007 53#define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007
@@ -79,6 +84,32 @@ struct powernow_k8_data {
79#define MSR_S_HI_CURRENT_VID 0x0000003f 84#define MSR_S_HI_CURRENT_VID 0x0000003f
80#define MSR_C_HI_STP_GNT_BENIGN 0x00000001 85#define MSR_C_HI_STP_GNT_BENIGN 0x00000001
81 86
87
88/* Hardware Pstate _PSS and MSR definitions */
89#define USE_HW_PSTATE 0x00000080
90#define HW_PSTATE_FID_MASK 0x0000003f
91#define HW_PSTATE_DID_MASK 0x000001c0
92#define HW_PSTATE_DID_SHIFT 6
93#define HW_PSTATE_MASK 0x00000007
94#define HW_PSTATE_VALID_MASK 0x80000000
95#define HW_FID_INDEX_SHIFT 8
96#define HW_FID_INDEX_MASK 0x0000ff00
97#define HW_DID_INDEX_SHIFT 16
98#define HW_DID_INDEX_MASK 0x00ff0000
99#define HW_WATTS_MASK 0xff
100#define HW_PWR_DVR_MASK 0x300
101#define HW_PWR_DVR_SHIFT 8
102#define HW_PWR_MAX_MULT 3
103#define MAX_HW_PSTATE 8 /* hw pstate supports up to 8 */
104#define MSR_PSTATE_DEF_BASE 0xc0010064 /* base of Pstate MSRs */
105#define MSR_PSTATE_STATUS 0xc0010063 /* Pstate Status MSR */
106#define MSR_PSTATE_CTRL 0xc0010062 /* Pstate control MSR */
107
108/* define the two driver architectures */
109#define CPU_OPTERON 0
110#define CPU_HW_PSTATE 1
111
112
82/* 113/*
83 * There are restrictions frequencies have to follow: 114 * There are restrictions frequencies have to follow:
84 * - only 1 entry in the low fid table ( <=1.4GHz ) 115 * - only 1 entry in the low fid table ( <=1.4GHz )
@@ -182,6 +213,9 @@ static int core_frequency_transition(struct powernow_k8_data *data, u32 reqfid);
182 213
183static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index); 214static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index);
184 215
216static int fill_powernow_table_pstate(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table);
217static int fill_powernow_table_fidvid(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table);
218
185#ifdef CONFIG_SMP 219#ifdef CONFIG_SMP
186static inline void define_siblings(int cpu, cpumask_t cpu_sharedcore_mask[]) 220static inline void define_siblings(int cpu, cpumask_t cpu_sharedcore_mask[])
187{ 221{
diff --git a/arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c b/arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c
index b0ff9075708c..ce54ff12c15d 100644
--- a/arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c
+++ b/arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c
@@ -250,7 +250,7 @@ static int centrino_cpu_init_table(struct cpufreq_policy *policy)
250 250
251 if (model->cpu_id == NULL) { 251 if (model->cpu_id == NULL) {
252 /* No match at all */ 252 /* No match at all */
253 dprintk(KERN_INFO PFX "no support for CPU model \"%s\": " 253 dprintk("no support for CPU model \"%s\": "
254 "send /proc/cpuinfo to " MAINTAINER "\n", 254 "send /proc/cpuinfo to " MAINTAINER "\n",
255 cpu->x86_model_id); 255 cpu->x86_model_id);
256 return -ENOENT; 256 return -ENOENT;
@@ -258,10 +258,10 @@ static int centrino_cpu_init_table(struct cpufreq_policy *policy)
258 258
259 if (model->op_points == NULL) { 259 if (model->op_points == NULL) {
260 /* Matched a non-match */ 260 /* Matched a non-match */
261 dprintk(KERN_INFO PFX "no table support for CPU model \"%s\"\n", 261 dprintk("no table support for CPU model \"%s\"\n",
262 cpu->x86_model_id); 262 cpu->x86_model_id);
263#ifndef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI 263#ifndef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
264 dprintk(KERN_INFO PFX "try compiling with CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI enabled\n"); 264 dprintk("try compiling with CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI enabled\n");
265#endif 265#endif
266 return -ENOENT; 266 return -ENOENT;
267 } 267 }
@@ -368,7 +368,7 @@ static int centrino_cpu_init_acpi(struct cpufreq_policy *policy)
368 368
369 /* register with ACPI core */ 369 /* register with ACPI core */
370 if (acpi_processor_register_performance(&p, cpu)) { 370 if (acpi_processor_register_performance(&p, cpu)) {
371 dprintk(KERN_INFO PFX "obtaining ACPI data failed\n"); 371 dprintk("obtaining ACPI data failed\n");
372 return -EIO; 372 return -EIO;
373 } 373 }
374 374
@@ -465,7 +465,7 @@ static int centrino_cpu_init_acpi(struct cpufreq_policy *policy)
465 kfree(centrino_model[cpu]); 465 kfree(centrino_model[cpu]);
466 err_unreg: 466 err_unreg:
467 acpi_processor_unregister_performance(&p, cpu); 467 acpi_processor_unregister_performance(&p, cpu);
468 dprintk(KERN_INFO PFX "invalid ACPI data\n"); 468 dprintk("invalid ACPI data\n");
469 return (result); 469 return (result);
470} 470}
471#else 471#else
@@ -499,7 +499,7 @@ static int centrino_cpu_init(struct cpufreq_policy *policy)
499 centrino_cpu[policy->cpu] = &cpu_ids[i]; 499 centrino_cpu[policy->cpu] = &cpu_ids[i];
500 500
501 if (!centrino_cpu[policy->cpu]) { 501 if (!centrino_cpu[policy->cpu]) {
502 dprintk(KERN_INFO PFX "found unsupported CPU with " 502 dprintk("found unsupported CPU with "
503 "Enhanced SpeedStep: send /proc/cpuinfo to " 503 "Enhanced SpeedStep: send /proc/cpuinfo to "
504 MAINTAINER "\n"); 504 MAINTAINER "\n");
505 return -ENODEV; 505 return -ENODEV;
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index e8ff09fe73d9..35e038a974c6 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -119,6 +119,32 @@ config MIPS_MIRAGE
119 select SYS_HAS_CPU_MIPS32_R1 119 select SYS_HAS_CPU_MIPS32_R1
120 select SYS_SUPPORTS_LITTLE_ENDIAN 120 select SYS_SUPPORTS_LITTLE_ENDIAN
121 121
122config BASLER_EXCITE
123 bool "Basler eXcite smart camera support"
124 select DMA_COHERENT
125 select HW_HAS_PCI
126 select IRQ_CPU
127 select IRQ_CPU_RM7K
128 select IRQ_CPU_RM9K
129 select SERIAL_RM9000
130 select SYS_HAS_CPU_RM9000
131 select SYS_SUPPORTS_32BIT_KERNEL
132 select SYS_SUPPORTS_64BIT_KERNEL
133 select SYS_SUPPORTS_BIG_ENDIAN
134 help
135 The eXcite is a smart camera platform manufactured by
136 Basler Vision Technologies AG
137
138config BASLER_EXCITE_PROTOTYPE
139 bool "Support for pre-release units"
140 depends on BASLER_EXCITE
141 default n
142 help
143 Pre-series (prototype) units are different from later ones in
144 some ways. Select this option if you have one of these. Please
145 note that a kernel built with this option selected will not be
146 able to run on normal units.
147
122config MIPS_COBALT 148config MIPS_COBALT
123 bool "Cobalt Server" 149 bool "Cobalt Server"
124 select DMA_NONCOHERENT 150 select DMA_NONCOHERENT
@@ -142,6 +168,9 @@ config MACH_DECSTATION
142 select SYS_SUPPORTS_32BIT_KERNEL 168 select SYS_SUPPORTS_32BIT_KERNEL
143 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL 169 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
144 select SYS_SUPPORTS_LITTLE_ENDIAN 170 select SYS_SUPPORTS_LITTLE_ENDIAN
171 select SYS_SUPPORTS_128HZ
172 select SYS_SUPPORTS_256HZ
173 select SYS_SUPPORTS_1024HZ
145 help 174 help
146 This enables support for DEC's MIPS based workstations. For details 175 This enables support for DEC's MIPS based workstations. For details
147 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the 176 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
@@ -239,6 +268,7 @@ config MACH_JAZZ
239 select SYS_HAS_CPU_R4X00 268 select SYS_HAS_CPU_R4X00
240 select SYS_SUPPORTS_32BIT_KERNEL 269 select SYS_SUPPORTS_32BIT_KERNEL
241 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL 270 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
271 select SYS_SUPPORTS_100HZ
242 help 272 help
243 This a family of machines based on the MIPS R4030 chipset which was 273 This a family of machines based on the MIPS R4030 chipset which was
244 used by several vendors to build RISC/os and Windows NT workstations. 274 used by several vendors to build RISC/os and Windows NT workstations.
@@ -327,6 +357,27 @@ config MIPS_SEAD
327 This enables support for the MIPS Technologies SEAD evaluation 357 This enables support for the MIPS Technologies SEAD evaluation
328 board. 358 board.
329 359
360config WR_PPMC
361 bool "Support for Wind River PPMC board"
362 select IRQ_CPU
363 select BOOT_ELF32
364 select DMA_NONCOHERENT
365 select HW_HAS_PCI
366 select MIPS_GT64120
367 select SWAP_IO_SPACE
368 select SYS_HAS_CPU_MIPS32_R1
369 select SYS_HAS_CPU_MIPS32_R2
370 select SYS_HAS_CPU_MIPS64_R1
371 select SYS_HAS_CPU_NEVADA
372 select SYS_HAS_CPU_RM7000
373 select SYS_SUPPORTS_32BIT_KERNEL
374 select SYS_SUPPORTS_64BIT_KERNEL
375 select SYS_SUPPORTS_BIG_ENDIAN
376 select SYS_SUPPORTS_LITTLE_ENDIAN
377 help
378 This enables support for the Wind River MIPS32 4KC PPMC evaluation
379 board, which is based on GT64120 bridge chip.
380
330config MIPS_SIM 381config MIPS_SIM
331 bool 'MIPS simulator (MIPSsim)' 382 bool 'MIPS simulator (MIPSsim)'
332 select DMA_NONCOHERENT 383 select DMA_NONCOHERENT
@@ -438,53 +489,16 @@ config MIPS_XXS1500
438 489
439config PNX8550_V2PCI 490config PNX8550_V2PCI
440 bool "Philips PNX8550 based Viper2-PCI board" 491 bool "Philips PNX8550 based Viper2-PCI board"
492 depends on BROKEN
441 select PNX8550 493 select PNX8550
442 select SYS_SUPPORTS_LITTLE_ENDIAN 494 select SYS_SUPPORTS_LITTLE_ENDIAN
443 495
444config PNX8550_JBS 496config PNX8550_JBS
445 bool "Philips PNX8550 based JBS board" 497 bool "Philips PNX8550 based JBS board"
498 depends on BROKEN
446 select PNX8550 499 select PNX8550
447 select SYS_SUPPORTS_LITTLE_ENDIAN 500 select SYS_SUPPORTS_LITTLE_ENDIAN
448 501
449config DDB5074
450 bool "NEC DDB Vrc-5074 (EXPERIMENTAL)"
451 depends on EXPERIMENTAL
452 select DDB5XXX_COMMON
453 select DMA_NONCOHERENT
454 select HAVE_STD_PC_SERIAL_PORT
455 select HW_HAS_PCI
456 select IRQ_CPU
457 select I8259
458 select ISA
459 select SYS_HAS_CPU_R5000
460 select SYS_SUPPORTS_32BIT_KERNEL
461 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
462 select SYS_SUPPORTS_LITTLE_ENDIAN
463 help
464 This enables support for the VR5000-based NEC DDB Vrc-5074
465 evaluation board.
466
467config DDB5476
468 bool "NEC DDB Vrc-5476"
469 select DDB5XXX_COMMON
470 select DMA_NONCOHERENT
471 select HAVE_STD_PC_SERIAL_PORT
472 select HW_HAS_PCI
473 select IRQ_CPU
474 select I8259
475 select ISA
476 select SYS_HAS_CPU_R5432
477 select SYS_SUPPORTS_32BIT_KERNEL
478 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
479 select SYS_SUPPORTS_LITTLE_ENDIAN
480 help
481 This enables support for the R5432-based NEC DDB Vrc-5476
482 evaluation board.
483
484 Features : kernel debugging, serial terminal, NFS root fs, on-board
485 ether port USB, AC97, PCI, PCI VGA card & framebuffer console,
486 IDE controller, PS2 keyboard, PS2 mouse, etc.
487
488config DDB5477 502config DDB5477
489 bool "NEC DDB Vrc-5477" 503 bool "NEC DDB Vrc-5477"
490 select DDB5XXX_COMMON 504 select DDB5XXX_COMMON
@@ -546,6 +560,20 @@ config QEMU
546 simulate actual MIPS hardware platforms. More information on Qemu 560 simulate actual MIPS hardware platforms. More information on Qemu
547 can be found at http://www.linux-mips.org/wiki/Qemu. 561 can be found at http://www.linux-mips.org/wiki/Qemu.
548 562
563config MARKEINS
564 bool "Support for NEC EMMA2RH Mark-eins"
565 select DMA_NONCOHERENT
566 select HW_HAS_PCI
567 select IRQ_CPU
568 select SWAP_IO_SPACE
569 select SYS_SUPPORTS_32BIT_KERNEL
570 select SYS_SUPPORTS_BIG_ENDIAN
571 select SYS_SUPPORTS_LITTLE_ENDIAN
572 select SYS_HAS_CPU_R5000
573 help
574 This enables support for the R5432-based NEC Mark-eins
575 boards with R5500 CPU.
576
549config SGI_IP22 577config SGI_IP22
550 bool "SGI IP22 (Indy/Indigo2)" 578 bool "SGI IP22 (Indy/Indigo2)"
551 select ARC 579 select ARC
@@ -555,6 +583,7 @@ config SGI_IP22
555 select HW_HAS_EISA 583 select HW_HAS_EISA
556 select IP22_CPU_SCACHE 584 select IP22_CPU_SCACHE
557 select IRQ_CPU 585 select IRQ_CPU
586 select NO_ISA if ISA
558 select SWAP_IO_SPACE 587 select SWAP_IO_SPACE
559 select SYS_HAS_CPU_R4X00 588 select SYS_HAS_CPU_R4X00
560 select SYS_HAS_CPU_R5000 589 select SYS_HAS_CPU_R5000
@@ -577,6 +606,7 @@ config SGI_IP27
577 select SYS_HAS_CPU_R10000 606 select SYS_HAS_CPU_R10000
578 select SYS_SUPPORTS_64BIT_KERNEL 607 select SYS_SUPPORTS_64BIT_KERNEL
579 select SYS_SUPPORTS_BIG_ENDIAN 608 select SYS_SUPPORTS_BIG_ENDIAN
609 select SYS_SUPPORTS_NUMA
580 help 610 help
581 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics 611 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
582 workstations. To compile a Linux kernel that runs on these, say Y 612 workstations. To compile a Linux kernel that runs on these, say Y
@@ -707,8 +737,8 @@ config SIBYTE_CRHONE
707 737
708config SNI_RM200_PCI 738config SNI_RM200_PCI
709 bool "SNI RM200 PCI" 739 bool "SNI RM200 PCI"
710 select ARC 740 select ARC if CPU_LITTLE_ENDIAN
711 select ARC32 741 select ARC32 if CPU_LITTLE_ENDIAN
712 select ARCH_MAY_HAVE_PC_FDC 742 select ARCH_MAY_HAVE_PC_FDC
713 select BOOT_ELF32 743 select BOOT_ELF32
714 select DMA_NONCOHERENT 744 select DMA_NONCOHERENT
@@ -719,10 +749,13 @@ config SNI_RM200_PCI
719 select I8253 749 select I8253
720 select I8259 750 select I8259
721 select ISA 751 select ISA
752 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
722 select SYS_HAS_CPU_R4X00 753 select SYS_HAS_CPU_R4X00
754 select SYS_HAS_CPU_R5000
755 select R5000_CPU_SCACHE
723 select SYS_SUPPORTS_32BIT_KERNEL 756 select SYS_SUPPORTS_32BIT_KERNEL
724 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL 757 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
725 select SYS_SUPPORTS_BIG_ENDIAN if EXPERIMENTAL 758 select SYS_SUPPORTS_BIG_ENDIAN
726 select SYS_SUPPORTS_HIGHMEM 759 select SYS_SUPPORTS_HIGHMEM
727 select SYS_SUPPORTS_LITTLE_ENDIAN 760 select SYS_SUPPORTS_LITTLE_ENDIAN
728 help 761 help
@@ -979,6 +1012,11 @@ config SOC_PNX8550
979config SWAP_IO_SPACE 1012config SWAP_IO_SPACE
980 bool 1013 bool
981 1014
1015config EMMA2RH
1016 bool
1017 depends on MARKEINS
1018 default y
1019
982# 1020#
983# Unfortunately not all GT64120 systems run the chip at the same clock. 1021# Unfortunately not all GT64120 systems run the chip at the same clock.
984# As the user for the clock rate and try to minimize the available options. 1022# As the user for the clock rate and try to minimize the available options.
@@ -1607,6 +1645,28 @@ config ARCH_FLATMEM_ENABLE
1607 def_bool y 1645 def_bool y
1608 depends on !NUMA 1646 depends on !NUMA
1609 1647
1648config ARCH_DISCONTIGMEM_ENABLE
1649 bool
1650 default y if SGI_IP27
1651 help
1652 Say Y to upport efficient handling of discontiguous physical memory,
1653 for architectures which are either NUMA (Non-Uniform Memory Access)
1654 or have huge holes in the physical address space for other reasons.
1655 See <file:Documentation/vm/numa> for more.
1656
1657config NUMA
1658 bool "NUMA Support"
1659 depends on SYS_SUPPORTS_NUMA
1660 help
1661 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
1662 Access). This option improves performance on systems with more
1663 than two nodes; on two node systems it is generally better to
1664 leave it disabled; on single node systems disable this option
1665 disabled.
1666
1667config SYS_SUPPORTS_NUMA
1668 bool
1669
1610config NODES_SHIFT 1670config NODES_SHIFT
1611 int 1671 int
1612 default "6" 1672 default "6"
@@ -1651,6 +1711,77 @@ config NR_CPUS
1651 This is purely to save memory - each supported CPU adds 1711 This is purely to save memory - each supported CPU adds
1652 approximately eight kilobytes to the kernel image. 1712 approximately eight kilobytes to the kernel image.
1653 1713
1714#
1715# Timer Interrupt Frequency Configuration
1716#
1717
1718choice
1719 prompt "Timer frequency"
1720 default HZ_250
1721 help
1722 Allows the configuration of the timer frequency.
1723
1724 config HZ_48
1725 bool "48 HZ" if SYS_SUPPORTS_48HZ
1726
1727 config HZ_100
1728 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
1729
1730 config HZ_128
1731 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
1732
1733 config HZ_250
1734 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
1735
1736 config HZ_256
1737 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
1738
1739 config HZ_1000
1740 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
1741
1742 config HZ_1024
1743 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
1744
1745endchoice
1746
1747config SYS_SUPPORTS_48HZ
1748 bool
1749
1750config SYS_SUPPORTS_100HZ
1751 bool
1752
1753config SYS_SUPPORTS_128HZ
1754 bool
1755
1756config SYS_SUPPORTS_250HZ
1757 bool
1758
1759config SYS_SUPPORTS_256HZ
1760 bool
1761
1762config SYS_SUPPORTS_1000HZ
1763 bool
1764
1765config SYS_SUPPORTS_1024HZ
1766 bool
1767
1768config SYS_SUPPORTS_ARBIT_HZ
1769 bool
1770 default y if !SYS_SUPPORTS_48HZ && !SYS_SUPPORTS_100HZ && \
1771 !SYS_SUPPORTS_128HZ && !SYS_SUPPORTS_250HZ && \
1772 !SYS_SUPPORTS_256HZ && !SYS_SUPPORTS_1000HZ && \
1773 !SYS_SUPPORTS_1024HZ
1774
1775config HZ
1776 int
1777 default 48 if HZ_48
1778 default 100 if HZ_100
1779 default 128 if HZ_128
1780 default 250 if HZ_250
1781 default 256 if HZ_256
1782 default 1000 if HZ_1000
1783 default 1024 if HZ_1024
1784
1654source "kernel/Kconfig.preempt" 1785source "kernel/Kconfig.preempt"
1655 1786
1656config RTC_DS1742 1787config RTC_DS1742
@@ -1710,6 +1841,9 @@ source "drivers/pci/Kconfig"
1710config ISA 1841config ISA
1711 bool 1842 bool
1712 1843
1844config NO_ISA
1845 bool
1846
1713config EISA 1847config EISA
1714 bool "EISA support" 1848 bool "EISA support"
1715 depends on HW_HAS_EISA 1849 depends on HW_HAS_EISA
@@ -1840,6 +1974,32 @@ config PM
1840 bool "Power Management support (EXPERIMENTAL)" 1974 bool "Power Management support (EXPERIMENTAL)"
1841 depends on EXPERIMENTAL && SOC_AU1X00 1975 depends on EXPERIMENTAL && SOC_AU1X00
1842 1976
1977config APM
1978 tristate "Advanced Power Management Emulation"
1979 depends on PM
1980 ---help---
1981 APM is a BIOS specification for saving power using several different
1982 techniques. This is mostly useful for battery powered systems with
1983 APM compliant BIOSes. If you say Y here, the system time will be
1984 reset after a RESUME operation, the /proc/apm device will provide
1985 battery status information, and user-space programs will receive
1986 notification of APM "events" (e.g. battery status change).
1987
1988 In order to use APM, you will need supporting software. For location
1989 and more information, read <file:Documentation/pm.txt> and the
1990 Battery Powered Linux mini-HOWTO, available from
1991 <http://www.tldp.org/docs.html#howto>.
1992
1993 This driver does not spin down disk drives (see the hdparm(8)
1994 manpage ("man 8 hdparm") for that), and it doesn't turn off
1995 VESA-compliant "green" monitors.
1996
1997 Generally, if you don't have a battery in your machine, there isn't
1998 much point in using this driver and you should say N. If you get
1999 random kernel OOPSes or reboots that don't seem to be related to
2000 anything, try disabling/enabling this option (or disabling/enabling
2001 APM in your BIOS).
2002
1843endmenu 2003endmenu
1844 2004
1845source "net/Kconfig" 2005source "net/Kconfig"
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 133900aca992..d5930148495a 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -83,6 +83,8 @@ cflags-y += -msoft-float
83LDFLAGS_vmlinux += -G 0 -static -n -nostdlib 83LDFLAGS_vmlinux += -G 0 -static -n -nostdlib
84MODFLAGS += -mlong-calls 84MODFLAGS += -mlong-calls
85 85
86cflags-y += -ffreestanding
87
86# 88#
87# We explicitly add the endianness specifier if needed, this allows 89# We explicitly add the endianness specifier if needed, this allows
88# to compile kernels with a toolchain for the other endianness. We 90# to compile kernels with a toolchain for the other endianness. We
@@ -285,6 +287,13 @@ cflags-$(CONFIG_MIPS_EV96100) += -Iinclude/asm-mips/mach-ev96100
285load-$(CONFIG_MIPS_EV96100) += 0xffffffff80100000 287load-$(CONFIG_MIPS_EV96100) += 0xffffffff80100000
286 288
287# 289#
290# Wind River PPMC Board (4KC + GT64120)
291#
292core-$(CONFIG_WR_PPMC) += arch/mips/gt64120/wrppmc/
293cflags-$(CONFIG_WR_PPMC) += -Iinclude/asm-mips/mach-wrppmc
294load-$(CONFIG_WR_PPMC) += 0xffffffff80100000
295
296#
288# Globespan IVR eval board with QED 5231 CPU 297# Globespan IVR eval board with QED 5231 CPU
289# 298#
290core-$(CONFIG_ITE_BOARD_GEN) += arch/mips/ite-boards/generic/ 299core-$(CONFIG_ITE_BOARD_GEN) += arch/mips/ite-boards/generic/
@@ -379,6 +388,13 @@ cflags-$(CONFIG_MOMENCO_OCELOT_3) += -Iinclude/asm-mips/mach-ocelot3
379load-$(CONFIG_MOMENCO_OCELOT_3) += 0xffffffff80100000 388load-$(CONFIG_MOMENCO_OCELOT_3) += 0xffffffff80100000
380 389
381# 390#
391# Basler eXcite
392#
393core-$(CONFIG_BASLER_EXCITE) += arch/mips/basler/excite/
394cflags-$(CONFIG_BASLER_EXCITE) += -Iinclude/asm-mips/mach-excite
395load-$(CONFIG_BASLER_EXCITE) += 0x80100000
396
397#
382# Momentum Jaguar ATX 398# Momentum Jaguar ATX
383# 399#
384core-$(CONFIG_MOMENCO_JAGUAR_ATX) += arch/mips/momentum/jaguar_atx/ 400core-$(CONFIG_MOMENCO_JAGUAR_ATX) += arch/mips/momentum/jaguar_atx/
@@ -395,18 +411,6 @@ load-$(CONFIG_MOMENCO_JAGUAR_ATX) += 0xffffffff80100000
395core-$(CONFIG_DDB5XXX_COMMON) += arch/mips/ddb5xxx/common/ 411core-$(CONFIG_DDB5XXX_COMMON) += arch/mips/ddb5xxx/common/
396 412
397# 413#
398# NEC DDB Vrc-5074
399#
400core-$(CONFIG_DDB5074) += arch/mips/ddb5xxx/ddb5074/
401load-$(CONFIG_DDB5074) += 0xffffffff80080000
402
403#
404# NEC DDB Vrc-5476
405#
406core-$(CONFIG_DDB5476) += arch/mips/ddb5xxx/ddb5476/
407load-$(CONFIG_DDB5476) += 0xffffffff80080000
408
409#
410# NEC DDB Vrc-5477 414# NEC DDB Vrc-5477
411# 415#
412core-$(CONFIG_DDB5477) += arch/mips/ddb5xxx/ddb5477/ 416core-$(CONFIG_DDB5477) += arch/mips/ddb5xxx/ddb5477/
@@ -468,6 +472,15 @@ libs-$(CONFIG_PNX8550_JBS) += arch/mips/philips/pnx8550/jbs/
468#cflags-$(CONFIG_PNX8550_JBS) += -Iinclude/asm-mips/mach-pnx8550 472#cflags-$(CONFIG_PNX8550_JBS) += -Iinclude/asm-mips/mach-pnx8550
469load-$(CONFIG_PNX8550_JBS) += 0xffffffff80060000 473load-$(CONFIG_PNX8550_JBS) += 0xffffffff80060000
470 474
475# NEC EMMA2RH boards
476#
477core-$(CONFIG_EMMA2RH) += arch/mips/emma2rh/common/
478cflags-$(CONFIG_EMMA2RH) += -Iinclude/asm-mips/mach-emma2rh
479
480# NEC EMMA2RH Mark-eins
481core-$(CONFIG_MARKEINS) += arch/mips/emma2rh/markeins/
482load-$(CONFIG_MARKEINS) += 0xffffffff88100000
483
471# 484#
472# SGI IP22 (Indy/Indigo2) 485# SGI IP22 (Indy/Indigo2)
473# 486#
diff --git a/arch/mips/au1000/common/au1xxx_irqmap.c b/arch/mips/au1000/common/au1xxx_irqmap.c
index 0b2c03c52319..5a1e3687cafa 100644
--- a/arch/mips/au1000/common/au1xxx_irqmap.c
+++ b/arch/mips/au1000/common/au1xxx_irqmap.c
@@ -55,7 +55,7 @@
55 * Careful if you change match 2 request! 55 * Careful if you change match 2 request!
56 * The interrupt handler is called directly from the low level dispatch code. 56 * The interrupt handler is called directly from the low level dispatch code.
57 */ 57 */
58au1xxx_irq_map_t au1xxx_ic0_map[] = { 58au1xxx_irq_map_t __initdata au1xxx_ic0_map[] = {
59 59
60#if defined(CONFIG_SOC_AU1000) 60#if defined(CONFIG_SOC_AU1000)
61 { AU1000_UART0_INT, INTC_INT_HIGH_LEVEL, 0}, 61 { AU1000_UART0_INT, INTC_INT_HIGH_LEVEL, 0},
@@ -220,5 +220,5 @@ au1xxx_irq_map_t au1xxx_ic0_map[] = {
220 220
221}; 221};
222 222
223int au1xxx_ic0_nr_irqs = sizeof(au1xxx_ic0_map)/sizeof(au1xxx_irq_map_t); 223int __initdata au1xxx_ic0_nr_irqs = ARRAY_SIZE(au1xxx_ic0_map);
224 224
diff --git a/arch/mips/au1000/common/pci.c b/arch/mips/au1000/common/pci.c
index 4e5a6e1a9a6e..b1392abac809 100644
--- a/arch/mips/au1000/common/pci.c
+++ b/arch/mips/au1000/common/pci.c
@@ -40,17 +40,17 @@
40 40
41/* TBD */ 41/* TBD */
42static struct resource pci_io_resource = { 42static struct resource pci_io_resource = {
43 "pci IO space", 43 .start = PCI_IO_START,
44 (u32)PCI_IO_START, 44 .end = PCI_IO_END,
45 (u32)PCI_IO_END, 45 .name = "PCI IO space",
46 IORESOURCE_IO 46 .flags = IORESOURCE_IO
47}; 47};
48 48
49static struct resource pci_mem_resource = { 49static struct resource pci_mem_resource = {
50 "pci memory space", 50 .start = PCI_MEM_START,
51 (u32)PCI_MEM_START, 51 .end = PCI_MEM_END,
52 (u32)PCI_MEM_END, 52 .name = "PCI memory space",
53 IORESOURCE_MEM 53 .flags = IORESOURCE_MEM
54}; 54};
55 55
56extern struct pci_ops au1x_pci_ops; 56extern struct pci_ops au1x_pci_ops;
diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/au1000/common/setup.c
index 307e98c29ddc..97165b6b3894 100644
--- a/arch/mips/au1000/common/setup.c
+++ b/arch/mips/au1000/common/setup.c
@@ -49,17 +49,13 @@ extern void __init board_setup(void);
49extern void au1000_restart(char *); 49extern void au1000_restart(char *);
50extern void au1000_halt(void); 50extern void au1000_halt(void);
51extern void au1000_power_off(void); 51extern void au1000_power_off(void);
52extern struct resource ioport_resource;
53extern struct resource iomem_resource;
54extern void (*board_time_init)(void);
55extern void au1x_time_init(void); 52extern void au1x_time_init(void);
56extern void (*board_timer_setup)(struct irqaction *irq);
57extern void au1x_timer_setup(struct irqaction *irq); 53extern void au1x_timer_setup(struct irqaction *irq);
58extern void au1xxx_time_init(void); 54extern void au1xxx_time_init(void);
59extern void au1xxx_timer_setup(struct irqaction *irq); 55extern void au1xxx_timer_setup(struct irqaction *irq);
60extern void set_cpuspec(void); 56extern void set_cpuspec(void);
61 57
62void __init plat_setup(void) 58void __init plat_mem_setup(void)
63{ 59{
64 struct cpu_spec *sp; 60 struct cpu_spec *sp;
65 char *argptr; 61 char *argptr;
diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c
index f74d66a58a21..842e1b5ac4a1 100644
--- a/arch/mips/au1000/common/time.c
+++ b/arch/mips/au1000/common/time.c
@@ -50,10 +50,6 @@
50#include <linux/mc146818rtc.h> 50#include <linux/mc146818rtc.h>
51#include <linux/timex.h> 51#include <linux/timex.h>
52 52
53extern void do_softirq(void);
54extern volatile unsigned long wall_jiffies;
55unsigned long missed_heart_beats = 0;
56
57static unsigned long r4k_offset; /* Amount to increment compare reg each time */ 53static unsigned long r4k_offset; /* Amount to increment compare reg each time */
58static unsigned long r4k_cur; /* What counter should be at next timer irq */ 54static unsigned long r4k_cur; /* What counter should be at next timer irq */
59int no_au1xxx_32khz; 55int no_au1xxx_32khz;
@@ -388,10 +384,9 @@ static unsigned long do_fast_pm_gettimeoffset(void)
388} 384}
389#endif 385#endif
390 386
391void au1xxx_timer_setup(struct irqaction *irq) 387void __init au1xxx_timer_setup(struct irqaction *irq)
392{ 388{
393 unsigned int est_freq; 389 unsigned int est_freq;
394 extern unsigned long (*do_gettimeoffset)(void);
395 390
396 printk("calculating r4koff... "); 391 printk("calculating r4koff... ");
397 r4k_offset = cal_r4koff(); 392 r4k_offset = cal_r4koff();
diff --git a/arch/mips/au1000/csb250/irqmap.c b/arch/mips/au1000/csb250/irqmap.c
index 5cb1166be35c..57d60401905e 100644
--- a/arch/mips/au1000/csb250/irqmap.c
+++ b/arch/mips/au1000/csb250/irqmap.c
@@ -47,7 +47,7 @@
47#include <asm/system.h> 47#include <asm/system.h>
48#include <asm/au1000.h> 48#include <asm/au1000.h>
49 49
50au1xxx_irq_map_t au1xxx_irq_map[] = { 50au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
51 51
52 { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0}, 52 { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0},
53 { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 }, 53 { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 },
@@ -57,4 +57,4 @@ au1xxx_irq_map_t au1xxx_irq_map[] = {
57 { AU1500_GPIO_207, INTC_INT_LOW_LEVEL, 0 }, 57 { AU1500_GPIO_207, INTC_INT_LOW_LEVEL, 0 },
58}; 58};
59 59
60int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t); 60int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
diff --git a/arch/mips/au1000/db1x00/irqmap.c b/arch/mips/au1000/db1x00/irqmap.c
index f63024a9893a..0138c5b7c860 100644
--- a/arch/mips/au1000/db1x00/irqmap.c
+++ b/arch/mips/au1000/db1x00/irqmap.c
@@ -80,7 +80,7 @@ char irq_tab_alchemy[][5] __initdata = {
80#endif 80#endif
81 81
82 82
83au1xxx_irq_map_t au1xxx_irq_map[] = { 83au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
84 84
85#ifndef CONFIG_MIPS_MIRAGE 85#ifndef CONFIG_MIPS_MIRAGE
86#ifdef CONFIG_MIPS_DB1550 86#ifdef CONFIG_MIPS_DB1550
@@ -101,4 +101,4 @@ au1xxx_irq_map_t au1xxx_irq_map[] = {
101 101
102}; 102};
103 103
104int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t); 104int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
diff --git a/arch/mips/au1000/hydrogen3/irqmap.c b/arch/mips/au1000/hydrogen3/irqmap.c
index 6eacaa0daa49..14e1ed37cf6b 100644
--- a/arch/mips/au1000/hydrogen3/irqmap.c
+++ b/arch/mips/au1000/hydrogen3/irqmap.c
@@ -47,10 +47,10 @@
47#include <asm/system.h> 47#include <asm/system.h>
48#include <asm/au1000.h> 48#include <asm/au1000.h>
49 49
50au1xxx_irq_map_t au1xxx_irq_map[] = { 50au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
51 51
52 /* { AU1500_GPIO_205, INTC_INT_LOW_LEVEL, 0 }, */ 52 /* { AU1500_GPIO_205, INTC_INT_LOW_LEVEL, 0 }, */
53 { AU1000_GPIO_21, INTC_INT_LOW_LEVEL, 0 }, 53 { AU1000_GPIO_21, INTC_INT_LOW_LEVEL, 0 },
54}; 54};
55 55
56int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t); 56int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
diff --git a/arch/mips/au1000/mtx-1/irqmap.c b/arch/mips/au1000/mtx-1/irqmap.c
index f9a0a8b9def2..4693a4eb2b82 100644
--- a/arch/mips/au1000/mtx-1/irqmap.c
+++ b/arch/mips/au1000/mtx-1/irqmap.c
@@ -58,7 +58,7 @@ char irq_tab_alchemy[][5] __initdata = {
58 [7] = { -1, INTD, INTC, INTX, INTX}, /* IDSEL 07 - AdapterD-Slot1 (bottom) */ 58 [7] = { -1, INTD, INTC, INTX, INTX}, /* IDSEL 07 - AdapterD-Slot1 (bottom) */
59}; 59};
60 60
61au1xxx_irq_map_t au1xxx_irq_map[] = { 61au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
62 { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0}, 62 { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0},
63 { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 }, 63 { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 },
64 { AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 }, 64 { AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 },
@@ -66,4 +66,4 @@ au1xxx_irq_map_t au1xxx_irq_map[] = {
66 { AU1500_GPIO_205, INTC_INT_LOW_LEVEL, 0 }, 66 { AU1500_GPIO_205, INTC_INT_LOW_LEVEL, 0 },
67}; 67};
68 68
69int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t); 69int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
diff --git a/arch/mips/au1000/pb1000/irqmap.c b/arch/mips/au1000/pb1000/irqmap.c
index a3c460e3c23e..156500ba467f 100644
--- a/arch/mips/au1000/pb1000/irqmap.c
+++ b/arch/mips/au1000/pb1000/irqmap.c
@@ -47,8 +47,8 @@
47#include <asm/system.h> 47#include <asm/system.h>
48#include <asm/mach-au1x00/au1000.h> 48#include <asm/mach-au1x00/au1000.h>
49 49
50au1xxx_irq_map_t au1xxx_irq_map[] = { 50au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
51 { AU1000_GPIO_15, INTC_INT_LOW_LEVEL, 0 }, 51 { AU1000_GPIO_15, INTC_INT_LOW_LEVEL, 0 },
52}; 52};
53 53
54int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t); 54int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
diff --git a/arch/mips/au1000/pb1100/irqmap.c b/arch/mips/au1000/pb1100/irqmap.c
index 43be7158b9ab..d986916221b7 100644
--- a/arch/mips/au1000/pb1100/irqmap.c
+++ b/arch/mips/au1000/pb1100/irqmap.c
@@ -47,11 +47,11 @@
47#include <asm/system.h> 47#include <asm/system.h>
48#include <asm/mach-au1x00/au1000.h> 48#include <asm/mach-au1x00/au1000.h>
49 49
50au1xxx_irq_map_t au1xxx_irq_map[] = { 50au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
51 { AU1000_GPIO_9, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card Fully_Interted# 51 { AU1000_GPIO_9, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card Fully_Interted#
52 { AU1000_GPIO_10, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card STSCHG# 52 { AU1000_GPIO_10, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card STSCHG#
53 { AU1000_GPIO_11, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card IRQ# 53 { AU1000_GPIO_11, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card IRQ#
54 { AU1000_GPIO_13, INTC_INT_LOW_LEVEL, 0 }, // DC_IRQ# 54 { AU1000_GPIO_13, INTC_INT_LOW_LEVEL, 0 }, // DC_IRQ#
55}; 55};
56 56
57int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t); 57int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
diff --git a/arch/mips/au1000/pb1200/irqmap.c b/arch/mips/au1000/pb1200/irqmap.c
index 59e70e5cf325..bacc0c6bfe67 100644
--- a/arch/mips/au1000/pb1200/irqmap.c
+++ b/arch/mips/au1000/pb1200/irqmap.c
@@ -55,11 +55,11 @@
55#define PB1200_INT_END DB1200_INT_END 55#define PB1200_INT_END DB1200_INT_END
56#endif 56#endif
57 57
58au1xxx_irq_map_t au1xxx_irq_map[] = { 58au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
59 { AU1000_GPIO_7, INTC_INT_LOW_LEVEL, 0 }, // This is exteranl interrupt cascade 59 { AU1000_GPIO_7, INTC_INT_LOW_LEVEL, 0 }, // This is exteranl interrupt cascade
60}; 60};
61 61
62int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t); 62int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
63 63
64/* 64/*
65 * Support for External interrupts on the PbAu1200 Development platform. 65 * Support for External interrupts on the PbAu1200 Development platform.
diff --git a/arch/mips/au1000/pb1500/irqmap.c b/arch/mips/au1000/pb1500/irqmap.c
index 8cb76c2edb5e..409d1612bb63 100644
--- a/arch/mips/au1000/pb1500/irqmap.c
+++ b/arch/mips/au1000/pb1500/irqmap.c
@@ -52,7 +52,7 @@ char irq_tab_alchemy[][5] __initdata = {
52 [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */ 52 [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */
53}; 53};
54 54
55au1xxx_irq_map_t au1xxx_irq_map[] = { 55au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
56 { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0}, 56 { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0},
57 { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 }, 57 { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 },
58 { AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 }, 58 { AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 },
@@ -60,4 +60,4 @@ au1xxx_irq_map_t au1xxx_irq_map[] = {
60 { AU1500_GPIO_205, INTC_INT_LOW_LEVEL, 0 }, 60 { AU1500_GPIO_205, INTC_INT_LOW_LEVEL, 0 },
61}; 61};
62 62
63int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t); 63int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
diff --git a/arch/mips/au1000/pb1550/irqmap.c b/arch/mips/au1000/pb1550/irqmap.c
index 47c7a1c19f4b..24a9d186cf5a 100644
--- a/arch/mips/au1000/pb1550/irqmap.c
+++ b/arch/mips/au1000/pb1550/irqmap.c
@@ -52,9 +52,9 @@ char irq_tab_alchemy[][5] __initdata = {
52 [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot 1 (right) */ 52 [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot 1 (right) */
53}; 53};
54 54
55au1xxx_irq_map_t au1xxx_irq_map[] = { 55au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
56 { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 }, 56 { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 },
57 { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 }, 57 { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 },
58}; 58};
59 59
60int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t); 60int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
diff --git a/arch/mips/au1000/xxs1500/irqmap.c b/arch/mips/au1000/xxs1500/irqmap.c
index 52f2f7daeb05..3844c6429e27 100644
--- a/arch/mips/au1000/xxs1500/irqmap.c
+++ b/arch/mips/au1000/xxs1500/irqmap.c
@@ -47,7 +47,7 @@
47#include <asm/system.h> 47#include <asm/system.h>
48#include <asm/au1000.h> 48#include <asm/au1000.h>
49 49
50au1xxx_irq_map_t au1xxx_irq_map[] = { 50au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
51 { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0}, 51 { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0},
52 { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 }, 52 { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 },
53 { AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 }, 53 { AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 },
@@ -63,4 +63,4 @@ au1xxx_irq_map_t au1xxx_irq_map[] = {
63 { AU1000_GPIO_5, INTC_INT_LOW_LEVEL, 0 }, 63 { AU1000_GPIO_5, INTC_INT_LOW_LEVEL, 0 },
64}; 64};
65 65
66int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t); 66int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
diff --git a/arch/mips/basler/excite/Makefile b/arch/mips/basler/excite/Makefile
new file mode 100644
index 000000000000..519142c2e4ef
--- /dev/null
+++ b/arch/mips/basler/excite/Makefile
@@ -0,0 +1,9 @@
1#
2# Makefile for Basler eXcite
3#
4
5obj-$(CONFIG_BASLER_EXCITE) += excite_irq.o excite_prom.o excite_setup.o \
6 excite_device.o excite_procfs.o
7
8obj-$(CONFIG_KGDB) += excite_dbg_io.o
9obj-m += excite_iodev.o
diff --git a/arch/mips/basler/excite/excite_dbg_io.c b/arch/mips/basler/excite/excite_dbg_io.c
new file mode 100644
index 000000000000..83f6bddf578b
--- /dev/null
+++ b/arch/mips/basler/excite/excite_dbg_io.c
@@ -0,0 +1,122 @@
1/*
2 * Copyright (C) 2004 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/config.h>
21#include <linux/linkage.h>
22#include <linux/init.h>
23#include <linux/kernel.h>
24#include <asm/gdb-stub.h>
25#include <asm/rm9k-ocd.h>
26#include <excite.h>
27
28#if defined(CONFIG_SERIAL_8250) && CONFIG_SERIAL_8250_NR_UARTS > 1
29#error Debug port used by serial driver
30#endif
31
32#define UART_CLK 25000000
33#define BASE_BAUD (UART_CLK / 16)
34#define REGISTER_BASE_0 0x0208UL
35#define REGISTER_BASE_1 0x0238UL
36
37#define REGISTER_BASE_DBG REGISTER_BASE_1
38
39#define CPRR 0x0004
40#define UACFG 0x0200
41#define UAINTS 0x0204
42#define UARBR (REGISTER_BASE_DBG + 0x0000)
43#define UATHR (REGISTER_BASE_DBG + 0x0004)
44#define UADLL (REGISTER_BASE_DBG + 0x0008)
45#define UAIER (REGISTER_BASE_DBG + 0x000c)
46#define UADLH (REGISTER_BASE_DBG + 0x0010)
47#define UAIIR (REGISTER_BASE_DBG + 0x0014)
48#define UAFCR (REGISTER_BASE_DBG + 0x0018)
49#define UALCR (REGISTER_BASE_DBG + 0x001c)
50#define UAMCR (REGISTER_BASE_DBG + 0x0020)
51#define UALSR (REGISTER_BASE_DBG + 0x0024)
52#define UAMSR (REGISTER_BASE_DBG + 0x0028)
53#define UASCR (REGISTER_BASE_DBG + 0x002c)
54
55#define PARITY_NONE 0
56#define PARITY_ODD 0x08
57#define PARITY_EVEN 0x18
58#define PARITY_MARK 0x28
59#define PARITY_SPACE 0x38
60
61#define DATA_5BIT 0x0
62#define DATA_6BIT 0x1
63#define DATA_7BIT 0x2
64#define DATA_8BIT 0x3
65
66#define STOP_1BIT 0x0
67#define STOP_2BIT 0x4
68
69#define BAUD_DBG 57600
70#define PARITY_DBG PARITY_NONE
71#define DATA_DBG DATA_8BIT
72#define STOP_DBG STOP_1BIT
73
74/* Initialize the serial port for KGDB debugging */
75void __init excite_kgdb_init(void)
76{
77 const u32 divisor = BASE_BAUD / BAUD_DBG;
78
79 /* Take the UART out of reset */
80 titan_writel(0x00ff1cff, CPRR);
81 titan_writel(0x00000000, UACFG);
82 titan_writel(0x00000002, UACFG);
83
84 titan_writel(0x0, UALCR);
85 titan_writel(0x0, UAIER);
86
87 /* Disable FIFOs */
88 titan_writel(0x00, UAFCR);
89
90 titan_writel(0x80, UALCR);
91 titan_writel(divisor & 0xff, UADLL);
92 titan_writel((divisor & 0xff00) >> 8, UADLH);
93 titan_writel(0x0, UALCR);
94
95 titan_writel(DATA_DBG | PARITY_DBG | STOP_DBG, UALCR);
96
97 /* Enable receiver interrupt */
98 titan_readl(UARBR);
99 titan_writel(0x1, UAIER);
100}
101
102int getDebugChar(void)
103{
104 while (!(titan_readl(UALSR) & 0x1));
105 return titan_readl(UARBR);
106}
107
108int putDebugChar(int data)
109{
110 while (!(titan_readl(UALSR) & 0x20));
111 titan_writel(data, UATHR);
112 return 1;
113}
114
115/* KGDB interrupt handler */
116asmlinkage void excite_kgdb_inthdl(struct pt_regs *regs)
117{
118 if (unlikely(
119 ((titan_readl(UAIIR) & 0x7) == 4)
120 && ((titan_readl(UARBR) & 0xff) == 0x3)))
121 set_async_breakpoint(&regs->cp0_epc);
122}
diff --git a/arch/mips/basler/excite/excite_device.c b/arch/mips/basler/excite/excite_device.c
new file mode 100644
index 000000000000..34ec76716fa0
--- /dev/null
+++ b/arch/mips/basler/excite/excite_device.c
@@ -0,0 +1,404 @@
1/*
2 * Copyright (C) 2004 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/config.h>
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/platform_device.h>
24#include <linux/ioport.h>
25#include <linux/err.h>
26#include <linux/jiffies.h>
27#include <linux/sched.h>
28#include <asm/types.h>
29#include <asm/rm9k-ocd.h>
30
31#include <excite.h>
32#include <rm9k_eth.h>
33#include <rm9k_wdt.h>
34#include <rm9k_xicap.h>
35#include <excite_nandflash.h>
36
37#include "excite_iodev.h"
38
39#define RM9K_GE_UNIT 0
40#define XICAP_UNIT 0
41#define NAND_UNIT 0
42
43#define DLL_TIMEOUT 3 /* seconds */
44
45
46#define RINIT(__start__, __end__, __name__, __parent__) { \
47 .name = __name__ "_0", \
48 .start = (__start__), \
49 .end = (__end__), \
50 .flags = 0, \
51 .parent = (__parent__) \
52}
53
54#define RINIT_IRQ(__irq__, __name__) { \
55 .name = __name__ "_0", \
56 .start = (__irq__), \
57 .end = (__irq__), \
58 .flags = IORESOURCE_IRQ, \
59 .parent = NULL \
60}
61
62
63
64enum {
65 slice_xicap,
66 slice_eth
67};
68
69
70
71static struct resource
72 excite_ctr_resource = {
73 .name = "GPI counters",
74 .start = 0,
75 .end = 5,
76 .flags = 0,
77 .parent = NULL,
78 .sibling = NULL,
79 .child = NULL
80 },
81 excite_gpislice_resource = {
82 .name = "GPI slices",
83 .start = 0,
84 .end = 1,
85 .flags = 0,
86 .parent = NULL,
87 .sibling = NULL,
88 .child = NULL
89 },
90 excite_mdio_channel_resource = {
91 .name = "MDIO channels",
92 .start = 0,
93 .end = 1,
94 .flags = 0,
95 .parent = NULL,
96 .sibling = NULL,
97 .child = NULL
98 },
99 excite_fifomem_resource = {
100 .name = "FIFO memory",
101 .start = 0,
102 .end = 767,
103 .flags = 0,
104 .parent = NULL,
105 .sibling = NULL,
106 .child = NULL
107 },
108 excite_scram_resource = {
109 .name = "Scratch RAM",
110 .start = EXCITE_PHYS_SCRAM,
111 .end = EXCITE_PHYS_SCRAM + EXCITE_SIZE_SCRAM - 1,
112 .flags = IORESOURCE_MEM,
113 .parent = NULL,
114 .sibling = NULL,
115 .child = NULL
116 },
117 excite_fpga_resource = {
118 .name = "System FPGA",
119 .start = EXCITE_PHYS_FPGA,
120 .end = EXCITE_PHYS_FPGA + EXCITE_SIZE_FPGA - 1,
121 .flags = IORESOURCE_MEM,
122 .parent = NULL,
123 .sibling = NULL,
124 .child = NULL
125 },
126 excite_nand_resource = {
127 .name = "NAND flash control",
128 .start = EXCITE_PHYS_NAND,
129 .end = EXCITE_PHYS_NAND + EXCITE_SIZE_NAND - 1,
130 .flags = IORESOURCE_MEM,
131 .parent = NULL,
132 .sibling = NULL,
133 .child = NULL
134 },
135 excite_titan_resource = {
136 .name = "TITAN registers",
137 .start = EXCITE_PHYS_TITAN,
138 .end = EXCITE_PHYS_TITAN + EXCITE_SIZE_TITAN - 1,
139 .flags = IORESOURCE_MEM,
140 .parent = NULL,
141 .sibling = NULL,
142 .child = NULL
143 };
144
145
146
147static void adjust_resources(struct resource *res, unsigned int n)
148{
149 struct resource *p;
150 const unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM
151 | IORESOURCE_IRQ | IORESOURCE_DMA;
152
153 for (p = res; p < res + n; p++) {
154 const struct resource * const parent = p->parent;
155 if (parent) {
156 p->start += parent->start;
157 p->end += parent->start;
158 p->flags = parent->flags & mask;
159 }
160 }
161}
162
163
164
165#if defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE)
166static struct resource xicap_rsrc[] = {
167 RINIT(0x4840, 0x486f, XICAP_RESOURCE_FIFO_RX, &excite_titan_resource),
168 RINIT(0x4940, 0x494b, XICAP_RESOURCE_FIFO_TX, &excite_titan_resource),
169 RINIT(0x5040, 0x5127, XICAP_RESOURCE_XDMA, &excite_titan_resource),
170 RINIT(0x1000, 0x112f, XICAP_RESOURCE_PKTPROC, &excite_titan_resource),
171 RINIT(0x1100, 0x110f, XICAP_RESOURCE_PKT_STREAM, &excite_fpga_resource),
172 RINIT(0x0800, 0x0bff, XICAP_RESOURCE_DMADESC, &excite_scram_resource),
173 RINIT(slice_xicap, slice_xicap, XICAP_RESOURCE_GPI_SLICE, &excite_gpislice_resource),
174 RINIT(0x0100, 0x02ff, XICAP_RESOURCE_FIFO_BLK, &excite_fifomem_resource),
175 RINIT_IRQ(TITAN_IRQ, XICAP_RESOURCE_IRQ)
176};
177
178static struct platform_device xicap_pdev = {
179 .name = XICAP_NAME,
180 .id = XICAP_UNIT,
181 .num_resources = ARRAY_SIZE(xicap_rsrc),
182 .resource = xicap_rsrc
183};
184
185/*
186 * Create a platform device for the GPI port that receives the
187 * image data from the embedded camera.
188 */
189static int __init xicap_devinit(void)
190{
191 unsigned long tend;
192 u32 reg;
193 int retval;
194
195 adjust_resources(xicap_rsrc, ARRAY_SIZE(xicap_rsrc));
196
197 /* Power up the slice and configure it. */
198 reg = titan_readl(CPTC1R);
199 reg &= ~(0x11100 << slice_xicap);
200 titan_writel(reg, CPTC1R);
201
202 /* Enable slice & DLL. */
203 reg= titan_readl(CPRR);
204 reg &= ~(0x00030003 << (slice_xicap * 2));
205 titan_writel(reg, CPRR);
206
207 /* Wait for DLLs to lock */
208 tend = jiffies + DLL_TIMEOUT * HZ;
209 while (time_before(jiffies, tend)) {
210 if (!(~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))))
211 break;
212 yield();
213 }
214
215 if (~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))) {
216 printk(KERN_ERR "%s: DLL not locked after %u seconds\n",
217 xicap_pdev.name, DLL_TIMEOUT);
218 retval = -ETIME;
219 } else {
220 /* Register platform device */
221 retval = platform_device_register(&xicap_pdev);
222 }
223
224 return retval;
225}
226
227device_initcall(xicap_devinit);
228#endif /* defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE) */
229
230
231
232#if defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE)
233static struct resource wdt_rsrc[] = {
234 RINIT(0, 0, WDT_RESOURCE_COUNTER, &excite_ctr_resource),
235 RINIT(0x0084, 0x008f, WDT_RESOURCE_REGS, &excite_titan_resource),
236 RINIT_IRQ(TITAN_IRQ, WDT_RESOURCE_IRQ)
237};
238
239static struct platform_device wdt_pdev = {
240 .name = WDT_NAME,
241 .id = -1,
242 .num_resources = ARRAY_SIZE(wdt_rsrc),
243 .resource = wdt_rsrc
244};
245
246/*
247 * Create a platform device for the GPI port that receives the
248 * image data from the embedded camera.
249 */
250static int __init wdt_devinit(void)
251{
252 adjust_resources(wdt_rsrc, ARRAY_SIZE(wdt_rsrc));
253 return platform_device_register(&wdt_pdev);
254}
255
256device_initcall(wdt_devinit);
257#endif /* defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE) */
258
259
260
261static struct resource excite_nandflash_rsrc[] = {
262 RINIT(0x2000, 0x201f, EXCITE_NANDFLASH_RESOURCE_REGS, &excite_nand_resource)
263};
264
265static struct platform_device excite_nandflash_pdev = {
266 .name = "excite_nand",
267 .id = NAND_UNIT,
268 .num_resources = ARRAY_SIZE(excite_nandflash_rsrc),
269 .resource = excite_nandflash_rsrc
270};
271
272/*
273 * Create a platform device for the access to the nand-flash
274 * port
275 */
276static int __init excite_nandflash_devinit(void)
277{
278 adjust_resources(excite_nandflash_rsrc, ARRAY_SIZE(excite_nandflash_rsrc));
279
280 /* nothing to be done here */
281
282 /* Register platform device */
283 return platform_device_register(&excite_nandflash_pdev);
284}
285
286device_initcall(excite_nandflash_devinit);
287
288
289
290static struct resource iodev_rsrc[] = {
291 RINIT_IRQ(FPGA1_IRQ, IODEV_RESOURCE_IRQ)
292};
293
294static struct platform_device io_pdev = {
295 .name = IODEV_NAME,
296 .id = -1,
297 .num_resources = ARRAY_SIZE(iodev_rsrc),
298 .resource = iodev_rsrc
299};
300
301/*
302 * Create a platform device for the external I/O ports.
303 */
304static int __init io_devinit(void)
305{
306 adjust_resources(iodev_rsrc, ARRAY_SIZE(iodev_rsrc));
307 return platform_device_register(&io_pdev);
308}
309
310device_initcall(io_devinit);
311
312
313
314
315#if defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE)
316static struct resource rm9k_ge_rsrc[] = {
317 RINIT(0x2200, 0x27ff, RM9K_GE_RESOURCE_MAC, &excite_titan_resource),
318 RINIT(0x1800, 0x1fff, RM9K_GE_RESOURCE_MSTAT, &excite_titan_resource),
319 RINIT(0x2000, 0x212f, RM9K_GE_RESOURCE_PKTPROC, &excite_titan_resource),
320 RINIT(0x5140, 0x5227, RM9K_GE_RESOURCE_XDMA, &excite_titan_resource),
321 RINIT(0x4870, 0x489f, RM9K_GE_RESOURCE_FIFO_RX, &excite_titan_resource),
322 RINIT(0x494c, 0x4957, RM9K_GE_RESOURCE_FIFO_TX, &excite_titan_resource),
323 RINIT(0x0000, 0x007f, RM9K_GE_RESOURCE_FIFOMEM_RX, &excite_fifomem_resource),
324 RINIT(0x0080, 0x00ff, RM9K_GE_RESOURCE_FIFOMEM_TX, &excite_fifomem_resource),
325 RINIT(0x0180, 0x019f, RM9K_GE_RESOURCE_PHY, &excite_titan_resource),
326 RINIT(0x0000, 0x03ff, RM9K_GE_RESOURCE_DMADESC_RX, &excite_scram_resource),
327 RINIT(0x0400, 0x07ff, RM9K_GE_RESOURCE_DMADESC_TX, &excite_scram_resource),
328 RINIT(slice_eth, slice_eth, RM9K_GE_RESOURCE_GPI_SLICE, &excite_gpislice_resource),
329 RINIT(0, 0, RM9K_GE_RESOURCE_MDIO_CHANNEL, &excite_mdio_channel_resource),
330 RINIT_IRQ(TITAN_IRQ, RM9K_GE_RESOURCE_IRQ_MAIN),
331 RINIT_IRQ(PHY_IRQ, RM9K_GE_RESOURCE_IRQ_PHY)
332};
333
334static struct platform_device rm9k_ge_pdev = {
335 .name = RM9K_GE_NAME,
336 .id = RM9K_GE_UNIT,
337 .num_resources = ARRAY_SIZE(rm9k_ge_rsrc),
338 .resource = rm9k_ge_rsrc
339};
340
341
342
343/*
344 * Create a platform device for the Ethernet port.
345 */
346static int __init rm9k_ge_devinit(void)
347{
348 u32 reg;
349
350 adjust_resources(rm9k_ge_rsrc, ARRAY_SIZE(rm9k_ge_rsrc));
351
352 /* Power up the slice and configure it. */
353 reg = titan_readl(CPTC1R);
354 reg &= ~(0x11000 << slice_eth);
355 reg |= 0x100 << slice_eth;
356 titan_writel(reg, CPTC1R);
357
358 /* Take the MAC out of reset, reset the DLLs. */
359 reg = titan_readl(CPRR);
360 reg &= ~(0x00030000 << (slice_eth * 2));
361 reg |= 0x3 << (slice_eth * 2);
362 titan_writel(reg, CPRR);
363
364 return platform_device_register(&rm9k_ge_pdev);
365}
366
367device_initcall(rm9k_ge_devinit);
368#endif /* defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE) */
369
370
371
372static int __init excite_setup_devs(void)
373{
374 int res;
375 u32 reg;
376
377 /* Enable xdma and fifo interrupts */
378 reg = titan_readl(0x0050);
379 titan_writel(reg | 0x18000000, 0x0050);
380
381 res = request_resource(&iomem_resource, &excite_titan_resource);
382 if (res)
383 return res;
384 res = request_resource(&iomem_resource, &excite_scram_resource);
385 if (res)
386 return res;
387 res = request_resource(&iomem_resource, &excite_fpga_resource);
388 if (res)
389 return res;
390 res = request_resource(&iomem_resource, &excite_nand_resource);
391 if (res)
392 return res;
393 excite_fpga_resource.flags = excite_fpga_resource.parent->flags &
394 ( IORESOURCE_IO | IORESOURCE_MEM
395 | IORESOURCE_IRQ | IORESOURCE_DMA);
396 excite_nand_resource.flags = excite_nand_resource.parent->flags &
397 ( IORESOURCE_IO | IORESOURCE_MEM
398 | IORESOURCE_IRQ | IORESOURCE_DMA);
399
400 return 0;
401}
402
403arch_initcall(excite_setup_devs);
404
diff --git a/arch/mips/basler/excite/excite_flashtest.c b/arch/mips/basler/excite/excite_flashtest.c
new file mode 100644
index 000000000000..f0024a8e3294
--- /dev/null
+++ b/arch/mips/basler/excite/excite_flashtest.c
@@ -0,0 +1,294 @@
1/*
2* Copyright (C) 2005 by Basler Vision Technologies AG
3* Author: Thies Moeller <thies.moeller@baslerweb.com>
4*
5* This program is free software; you can redistribute it and/or modify
6* it under the terms of the GNU General Public License as published by
7* the Free Software Foundation; either version 2 of the License, or
8* (at your option) any later version.
9*
10* This program is distributed in the hope that it will be useful,
11* but WITHOUT ANY WARRANTY; without even the implied warranty of
12* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13* GNU General Public License for more details.
14*
15* You should have received a copy of the GNU General Public License
16* along with this program; if not, write to the Free Software
17* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18*/
19
20#include <linux/module.h>
21#include <linux/types.h>
22#include <linux/init.h>
23#include <linux/kernel.h>
24#include <linux/string.h>
25#include <linux/ioport.h>
26#include <linux/device.h>
27#include <linux/delay.h>
28#include <linux/err.h>
29#include <linux/kernel.h>
30
31#include <excite.h>
32
33#include <asm/io.h>
34
35#include <linux/mtd/mtd.h>
36#include <linux/mtd/nand.h>
37#include <linux/mtd/nand_ecc.h>
38#include <linux/mtd/partitions.h>
39#include <asm/rm9k-ocd.h> // for ocd_write
40#include <linux/workqueue.h> // for queue
41
42#include "excite_nandflash.h"
43#include "nandflash.h"
44
45#define PFX "excite flashtest: "
46typedef void __iomem *io_reg_t;
47
48#define io_readb(__a__) __raw_readb((__a__))
49#define io_writeb(__v__, __a__) __raw_writeb((__v__), (__a__))
50
51
52
53static inline const struct resource *excite_nandflash_get_resource(
54 struct platform_device *d, unsigned long flags, const char *basename)
55{
56 const char fmt[] = "%s_%u";
57 char buf[80];
58
59 if (unlikely(snprintf(buf, sizeof buf, fmt, basename, d->id) >= sizeof buf))
60 return NULL;
61
62 return platform_get_resource_byname(d, flags, buf);
63}
64
65static inline io_reg_t
66excite_nandflash_map_regs(struct platform_device *d, const char *basename)
67{
68 void *result = NULL;
69 const struct resource *const r =
70 excite_nandflash_get_resource(d, IORESOURCE_MEM, basename);
71 if (r)
72 result = ioremap_nocache(r->start, r->end + 1 - r->start);
73 return result;
74}
75
76/* controller and mtd information */
77
78struct excite_nandflash_drvdata {
79 struct mtd_info board_mtd;
80 struct nand_chip board_chip;
81 io_reg_t regs;
82};
83
84
85/* command and control functions */
86static void excite_nandflash_hwcontrol(struct mtd_info *mtd, int cmd)
87{
88 struct nand_chip *this = mtd->priv;
89 io_reg_t regs = container_of(mtd,struct excite_nandflash_drvdata,board_mtd)->regs;
90
91 switch (cmd) {
92 /* Select the command latch */
93 case NAND_CTL_SETCLE: this->IO_ADDR_W = regs + EXCITE_NANDFLASH_CMD;
94 break;
95 /* Deselect the command latch */
96 case NAND_CTL_CLRCLE: this->IO_ADDR_W = regs + EXCITE_NANDFLASH_DATA;
97 break;
98 /* Select the address latch */
99 case NAND_CTL_SETALE: this->IO_ADDR_W = regs + EXCITE_NANDFLASH_ADDR;
100 break;
101 /* Deselect the address latch */
102 case NAND_CTL_CLRALE: this->IO_ADDR_W = regs + EXCITE_NANDFLASH_DATA;
103 break;
104 /* Select the chip -- not used */
105 case NAND_CTL_SETNCE:
106 break;
107 /* Deselect the chip -- not used */
108 case NAND_CTL_CLRNCE:
109 break;
110 }
111
112 this->IO_ADDR_R = this->IO_ADDR_W;
113}
114
115/* excite_nandflash_devready()
116 *
117 * returns 0 if the nand is busy, 1 if it is ready
118 */
119static int excite_nandflash_devready(struct mtd_info *mtd)
120{
121 struct excite_nandflash_drvdata *drvdata =
122 container_of(mtd, struct excite_nandflash_drvdata, board_mtd);
123
124 return io_readb(drvdata->regs + EXCITE_NANDFLASH_STATUS);
125}
126
127/* device management functions */
128
129/* excite_nandflash_remove
130 *
131 * called by device layer to remove the driver
132 * the binding to the mtd and all allocated
133 * resources are released
134 */
135static int excite_nandflash_remove(struct device *dev)
136{
137 struct excite_nandflash_drvdata *this = dev_get_drvdata(dev);
138
139 pr_info(PFX "remove");
140
141 dev_set_drvdata(dev, NULL);
142
143 if (this == NULL) {
144 pr_debug(PFX "call remove without private data!!");
145 return 0;
146 }
147
148
149 /* free the common resources */
150 if (this->regs != NULL) {
151 iounmap(this->regs);
152 this->regs = NULL;
153 }
154
155 kfree(this);
156
157 return 0;
158}
159
160static int elapsed;
161
162void my_workqueue_handler(void *arg)
163{
164 elapsed = 1;
165}
166
167DECLARE_WORK(sigElapsed, my_workqueue_handler, 0);
168
169
170/* excite_nandflash_probe
171 *
172 * called by device layer when it finds a device matching
173 * one our driver can handled. This code checks to see if
174 * it can allocate all necessary resources then calls the
175 * nand layer to look for devices
176*/
177static int excite_nandflash_probe(struct device *dev)
178{
179 struct platform_device *pdev = to_platform_device(dev);
180
181 struct excite_nandflash_drvdata *drvdata; /* private driver data */
182 struct nand_chip *board_chip; /* private flash chip data */
183 struct mtd_info *board_mtd; /* mtd info for this board */
184
185 int err = 0;
186 int count = 0;
187 struct timeval tv,endtv;
188 unsigned int dt;
189
190 pr_info(PFX "probe dev: (%p)\n", dev);
191
192 pr_info(PFX "adjust LB timing\n");
193 ocd_writel(0x00000330, LDP2);
194
195 drvdata = kmalloc(sizeof(*drvdata), GFP_KERNEL);
196 if (unlikely(!drvdata)) {
197 printk(KERN_ERR PFX "no memory for drvdata\n");
198 err = -ENOMEM;
199 goto mem_error;
200 }
201
202 /* Initialize structures */
203 memset(drvdata, 0, sizeof(*drvdata));
204
205 /* bind private data into driver */
206 dev_set_drvdata(dev, drvdata);
207
208 /* allocate and map the resource */
209 drvdata->regs =
210 excite_nandflash_map_regs(pdev, EXCITE_NANDFLASH_RESOURCE_REGS);
211
212 if (unlikely(!drvdata->regs)) {
213 printk(KERN_ERR PFX "cannot reserve register region\n");
214 err = -ENXIO;
215 goto io_error;
216 }
217
218 /* initialise our chip */
219 board_chip = &drvdata->board_chip;
220
221 board_chip->IO_ADDR_R = drvdata->regs + EXCITE_NANDFLASH_DATA;
222 board_chip->IO_ADDR_W = drvdata->regs + EXCITE_NANDFLASH_DATA;
223
224 board_chip->hwcontrol = excite_nandflash_hwcontrol;
225 board_chip->dev_ready = excite_nandflash_devready;
226
227 board_chip->chip_delay = 25;
228 #if 0
229 /* TODO: speedup the initial scan */
230 board_chip->options = NAND_USE_FLASH_BBT;
231 #endif
232 board_chip->eccmode = NAND_ECC_SOFT;
233
234 /* link chip to mtd */
235 board_mtd = &drvdata->board_mtd;
236 board_mtd->priv = board_chip;
237
238
239 pr_info(PFX "FlashTest\n");
240 elapsed = 0;
241/* schedule_delayed_work(&sigElapsed, 1*HZ);
242 while (!elapsed) {
243 io_readb(drvdata->regs + EXCITE_NANDFLASH_STATUS);
244 count++;
245 }
246 pr_info(PFX "reads in 1 sec --> %d\n",count);
247*/
248 do_gettimeofday(&tv);
249 for (count = 0 ; count < 1000000; count ++) {
250 io_readb(drvdata->regs + EXCITE_NANDFLASH_STATUS);
251 }
252 do_gettimeofday(&endtv);
253 dt = (endtv.tv_sec - tv.tv_sec) * 1000000 + endtv.tv_usec - tv.tv_usec;
254 pr_info(PFX "%8d us timeval\n",dt);
255 pr_info(PFX "EndFlashTest\n");
256
257/* return with error to unload everything
258*/
259io_error:
260 iounmap(drvdata->regs);
261
262mem_error:
263 kfree(drvdata);
264
265 if (err == 0)
266 err = -EINVAL;
267 return err;
268}
269
270static struct device_driver excite_nandflash_driver = {
271 .name = "excite_nand",
272 .bus = &platform_bus_type,
273 .probe = excite_nandflash_probe,
274 .remove = excite_nandflash_remove,
275};
276
277static int __init excite_nandflash_init(void)
278{
279 pr_info(PFX "register Driver (Rev: $Revision:$)\n");
280 return driver_register(&excite_nandflash_driver);
281}
282
283static void __exit excite_nandflash_exit(void)
284{
285 driver_unregister(&excite_nandflash_driver);
286 pr_info(PFX "Driver unregistered");
287}
288
289module_init(excite_nandflash_init);
290module_exit(excite_nandflash_exit);
291
292MODULE_AUTHOR("Thies Moeller <thies.moeller@baslerweb.com>");
293MODULE_DESCRIPTION("Basler eXcite NAND-Flash driver");
294MODULE_LICENSE("GPL");
diff --git a/arch/mips/basler/excite/excite_fpga.h b/arch/mips/basler/excite/excite_fpga.h
new file mode 100644
index 000000000000..38fcda703a0b
--- /dev/null
+++ b/arch/mips/basler/excite/excite_fpga.h
@@ -0,0 +1,80 @@
1#ifndef EXCITE_FPGA_H_INCLUDED
2#define EXCITE_FPGA_H_INCLUDED
3
4
5/**
6 * Adress alignment of the individual FPGA bytes.
7 * The address arrangement of the individual bytes of the FPGA is two
8 * byte aligned at the embedded MK2 platform.
9 */
10#ifdef EXCITE_CCI_FPGA_MK2
11typedef unsigned char excite_cci_fpga_align_t __attribute__ ((aligned(2)));
12#else
13typedef unsigned char excite_cci_fpga_align_t;
14#endif
15
16
17/**
18 * Size of Dual Ported RAM.
19 */
20#define EXCITE_DPR_SIZE 263
21
22
23/**
24 * Size of Reserved Status Fields in Dual Ported RAM.
25 */
26#define EXCITE_DPR_STATUS_SIZE 7
27
28
29
30/**
31 * FPGA.
32 * Hardware register layout of the FPGA interface. The FPGA must accessed
33 * byte wise solely.
34 * @see EXCITE_CCI_DPR_MK2
35 */
36typedef struct excite_fpga {
37
38 /**
39 * Dual Ported RAM.
40 */
41 excite_cci_fpga_align_t dpr[EXCITE_DPR_SIZE];
42
43 /**
44 * Status.
45 */
46 excite_cci_fpga_align_t status[EXCITE_DPR_STATUS_SIZE];
47
48#ifdef EXCITE_CCI_FPGA_MK2
49 /**
50 * RM9000 Interrupt.
51 * Write access initiates interrupt at the RM9000 (MIPS) processor of the eXcite.
52 */
53 excite_cci_fpga_align_t rm9k_int;
54#else
55 /**
56 * MK2 Interrupt.
57 * Write access initiates interrupt at the ARM processor of the MK2.
58 */
59 excite_cci_fpga_align_t mk2_int;
60
61 excite_cci_fpga_align_t gap[0x1000-0x10f];
62
63 /**
64 * IRQ Source/Acknowledge.
65 */
66 excite_cci_fpga_align_t rm9k_irq_src;
67
68 /**
69 * IRQ Mask.
70 * Set bits enable the related interrupt.
71 */
72 excite_cci_fpga_align_t rm9k_irq_mask;
73#endif
74
75
76} excite_fpga;
77
78
79
80#endif /* ndef EXCITE_FPGA_H_INCLUDED */
diff --git a/arch/mips/basler/excite/excite_iodev.c b/arch/mips/basler/excite/excite_iodev.c
new file mode 100644
index 000000000000..91121e523043
--- /dev/null
+++ b/arch/mips/basler/excite/excite_iodev.c
@@ -0,0 +1,183 @@
1/*
2 * Copyright (C) 2005 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/config.h>
21#include <linux/compiler.h>
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/sched.h>
25#include <linux/wait.h>
26#include <linux/poll.h>
27#include <linux/interrupt.h>
28#include <linux/platform_device.h>
29#include <linux/miscdevice.h>
30
31#include "excite_iodev.h"
32
33
34
35static const struct resource *iodev_get_resource(struct platform_device *, const char *, unsigned int);
36static int __init iodev_probe(struct device *);
37static int __exit iodev_remove(struct device *);
38static int iodev_open(struct inode *, struct file *);
39static int iodev_release(struct inode *, struct file *);
40static ssize_t iodev_read(struct file *, char __user *, size_t s, loff_t *);
41static unsigned int iodev_poll(struct file *, struct poll_table_struct *);
42static irqreturn_t iodev_irqhdl(int, void *, struct pt_regs *);
43
44
45
46static const char iodev_name[] = "iodev";
47static unsigned int iodev_irq;
48static DECLARE_WAIT_QUEUE_HEAD(wq);
49
50
51
52static struct file_operations fops =
53{
54 .owner = THIS_MODULE,
55 .open = iodev_open,
56 .release = iodev_release,
57 .read = iodev_read,
58 .poll = iodev_poll
59};
60
61static struct miscdevice miscdev =
62{
63 .minor = MISC_DYNAMIC_MINOR,
64 .name = iodev_name,
65 .fops = &fops
66};
67
68static struct device_driver iodev_driver =
69{
70 .name = (char *) iodev_name,
71 .bus = &platform_bus_type,
72 .owner = THIS_MODULE,
73 .probe = iodev_probe,
74 .remove = __exit_p(iodev_remove)
75};
76
77
78
79static const struct resource *
80iodev_get_resource(struct platform_device *pdv, const char *name,
81 unsigned int type)
82{
83 char buf[80];
84 if (snprintf(buf, sizeof buf, "%s_0", name) >= sizeof buf)
85 return NULL;
86 return platform_get_resource_byname(pdv, type, buf);
87}
88
89
90
91/* No hotplugging on the platform bus - use __init */
92static int __init iodev_probe(struct device *dev)
93{
94 struct platform_device * const pdv = to_platform_device(dev);
95 const struct resource * const ri =
96 iodev_get_resource(pdv, IODEV_RESOURCE_IRQ, IORESOURCE_IRQ);
97
98 if (unlikely(!ri))
99 return -ENXIO;
100
101 iodev_irq = ri->start;
102 return misc_register(&miscdev);
103}
104
105
106
107static int __exit iodev_remove(struct device *dev)
108{
109 return misc_deregister(&miscdev);
110}
111
112
113
114static int iodev_open(struct inode *i, struct file *f)
115{
116 return request_irq(iodev_irq, iodev_irqhdl, SA_INTERRUPT,
117 iodev_name, &miscdev);
118}
119
120
121
122static int iodev_release(struct inode *i, struct file *f)
123{
124 free_irq(iodev_irq, &miscdev);
125 return 0;
126}
127
128
129
130
131static ssize_t
132iodev_read(struct file *f, char __user *d, size_t s, loff_t *o)
133{
134 ssize_t ret;
135 DEFINE_WAIT(w);
136
137 prepare_to_wait(&wq, &w, TASK_INTERRUPTIBLE);
138 if (!signal_pending(current))
139 schedule();
140 ret = signal_pending(current) ? -ERESTARTSYS : 0;
141 finish_wait(&wq, &w);
142 return ret;
143}
144
145
146static unsigned int iodev_poll(struct file *f, struct poll_table_struct *p)
147{
148 poll_wait(f, &wq, p);
149 return POLLOUT | POLLWRNORM;
150}
151
152
153
154
155static irqreturn_t iodev_irqhdl(int irq, void *ctxt, struct pt_regs *regs)
156{
157 wake_up(&wq);
158 return IRQ_HANDLED;
159}
160
161
162
163static int __init iodev_init_module(void)
164{
165 return driver_register(&iodev_driver);
166}
167
168
169
170static void __exit iodev_cleanup_module(void)
171{
172 driver_unregister(&iodev_driver);
173}
174
175module_init(iodev_init_module);
176module_exit(iodev_cleanup_module);
177
178
179
180MODULE_AUTHOR("Thomas Koeller <thomas.koeller@baslerweb.com>");
181MODULE_DESCRIPTION("Basler eXcite i/o interrupt handler");
182MODULE_VERSION("0.0");
183MODULE_LICENSE("GPL");
diff --git a/arch/mips/basler/excite/excite_iodev.h b/arch/mips/basler/excite/excite_iodev.h
new file mode 100644
index 000000000000..cbfbb5d2ee62
--- /dev/null
+++ b/arch/mips/basler/excite/excite_iodev.h
@@ -0,0 +1,10 @@
1#ifndef __EXCITE_IODEV_H__
2#define __EXCITE_IODEV_H__
3
4/* Device name */
5#define IODEV_NAME "iodev"
6
7/* Resource names */
8#define IODEV_RESOURCE_IRQ "excite_iodev_irq"
9
10#endif /* __EXCITE_IODEV_H__ */
diff --git a/arch/mips/basler/excite/excite_irq.c b/arch/mips/basler/excite/excite_irq.c
new file mode 100644
index 000000000000..511ad8730f54
--- /dev/null
+++ b/arch/mips/basler/excite/excite_irq.c
@@ -0,0 +1,129 @@
1/*
2 * Copyright (C) by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslereb.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/errno.h>
21#include <linux/init.h>
22#include <linux/kernel_stat.h>
23#include <linux/module.h>
24#include <linux/signal.h>
25#include <linux/sched.h>
26#include <linux/types.h>
27#include <linux/interrupt.h>
28#include <linux/ioport.h>
29#include <linux/timex.h>
30#include <linux/slab.h>
31#include <linux/random.h>
32#include <asm/bitops.h>
33#include <asm/bootinfo.h>
34#include <asm/io.h>
35#include <asm/irq.h>
36#include <asm/irq_cpu.h>
37#include <asm/mipsregs.h>
38#include <asm/system.h>
39#include <asm/rm9k-ocd.h>
40
41#include <excite.h>
42
43extern asmlinkage void excite_handle_int(void);
44
45/*
46 * Initialize the interrupt handler
47 */
48void __init arch_init_irq(void)
49{
50 mips_cpu_irq_init(0);
51 rm7k_cpu_irq_init(8);
52 rm9k_cpu_irq_init(12);
53
54#ifdef CONFIG_KGDB
55 excite_kgdb_init();
56#endif
57}
58
59asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
60{
61 const u32
62 interrupts = read_c0_cause() >> 8,
63 mask = ((read_c0_status() >> 8) & 0x000000ff) |
64 (read_c0_intcontrol() & 0x0000ff00),
65 pending = interrupts & mask;
66 u32 msgintflags, msgintmask, msgint;
67
68 /* process timer interrupt */
69 if (pending & (1 << TIMER_IRQ)) {
70 do_IRQ(TIMER_IRQ, regs);
71 return;
72 }
73
74 /* Process PCI interrupts */
75#if USB_IRQ < 10
76 msgintflags = ocd_readl(INTP0Status0 + (USB_MSGINT / 0x20 * 0x10));
77 msgintmask = ocd_readl(INTP0Mask0 + (USB_MSGINT / 0x20 * 0x10));
78 msgint = msgintflags & msgintmask & (0x1 << (USB_MSGINT % 0x20));
79 if ((pending & (1 << USB_IRQ)) && msgint) {
80#else
81 if (pending & (1 << USB_IRQ)) {
82#endif
83 do_IRQ(USB_IRQ, regs);
84 return;
85 }
86
87 /* Process TITAN interrupts */
88 msgintflags = ocd_readl(INTP0Status0 + (TITAN_MSGINT / 0x20 * 0x10));
89 msgintmask = ocd_readl(INTP0Mask0 + (TITAN_MSGINT / 0x20 * 0x10));
90 msgint = msgintflags & msgintmask & (0x1 << (TITAN_MSGINT % 0x20));
91 if ((pending & (1 << TITAN_IRQ)) && msgint) {
92 ocd_writel(msgint, INTP0Clear0 + (TITAN_MSGINT / 0x20 * 0x10));
93#if defined(CONFIG_KGDB)
94 excite_kgdb_inthdl(regs);
95#endif
96 do_IRQ(TITAN_IRQ, regs);
97 return;
98 }
99
100 /* Process FPGA line #0 interrupts */
101 msgintflags = ocd_readl(INTP0Status0 + (FPGA0_MSGINT / 0x20 * 0x10));
102 msgintmask = ocd_readl(INTP0Mask0 + (FPGA0_MSGINT / 0x20 * 0x10));
103 msgint = msgintflags & msgintmask & (0x1 << (FPGA0_MSGINT % 0x20));
104 if ((pending & (1 << FPGA0_IRQ)) && msgint) {
105 do_IRQ(FPGA0_IRQ, regs);
106 return;
107 }
108
109 /* Process FPGA line #1 interrupts */
110 msgintflags = ocd_readl(INTP0Status0 + (FPGA1_MSGINT / 0x20 * 0x10));
111 msgintmask = ocd_readl(INTP0Mask0 + (FPGA1_MSGINT / 0x20 * 0x10));
112 msgint = msgintflags & msgintmask & (0x1 << (FPGA1_MSGINT % 0x20));
113 if ((pending & (1 << FPGA1_IRQ)) && msgint) {
114 do_IRQ(FPGA1_IRQ, regs);
115 return;
116 }
117
118 /* Process PHY interrupts */
119 msgintflags = ocd_readl(INTP0Status0 + (PHY_MSGINT / 0x20 * 0x10));
120 msgintmask = ocd_readl(INTP0Mask0 + (PHY_MSGINT / 0x20 * 0x10));
121 msgint = msgintflags & msgintmask & (0x1 << (PHY_MSGINT % 0x20));
122 if ((pending & (1 << PHY_IRQ)) && msgint) {
123 do_IRQ(PHY_IRQ, regs);
124 return;
125 }
126
127 /* Process spurious interrupts */
128 spurious_interrupt(regs);
129}
diff --git a/arch/mips/basler/excite/excite_procfs.c b/arch/mips/basler/excite/excite_procfs.c
new file mode 100644
index 000000000000..c62be0341fb8
--- /dev/null
+++ b/arch/mips/basler/excite/excite_procfs.c
@@ -0,0 +1,81 @@
1/*
2 * Copyright (C) 2004, 2005 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 *
5 * Procfs support for Basler eXcite
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/config.h>
23#include <linux/proc_fs.h>
24#include <linux/stat.h>
25#include <asm/page.h>
26#include <asm/io.h>
27#include <asm/system.h>
28#include <asm/rm9k-ocd.h>
29
30#include <excite.h>
31
32static int excite_get_unit_id(char *buf, char **addr, off_t offs, int size)
33{
34 const int len = snprintf(buf, PAGE_SIZE, "%06x", unit_id);
35 const int w = len - offs;
36 *addr = buf + offs;
37 return w < size ? w : size;
38}
39
40static int
41excite_bootrom_read(char *page, char **start, off_t off, int count,
42 int *eof, void *data)
43{
44 void __iomem * src;
45
46 if (off >= EXCITE_SIZE_BOOTROM) {
47 *eof = 1;
48 return 0;
49 }
50
51 if ((off + count) > EXCITE_SIZE_BOOTROM)
52 count = EXCITE_SIZE_BOOTROM - off;
53
54 src = ioremap(EXCITE_PHYS_BOOTROM + off, count);
55 if (src) {
56 memcpy_fromio(page, src, count);
57 iounmap(src);
58 *start = page;
59 } else {
60 count = -ENOMEM;
61 }
62
63 return count;
64}
65
66void excite_procfs_init(void)
67{
68 /* Create & populate /proc/excite */
69 struct proc_dir_entry * const pdir = proc_mkdir("excite", &proc_root);
70 if (pdir) {
71 struct proc_dir_entry * e;
72
73 e = create_proc_info_entry("unit_id", S_IRUGO, pdir,
74 excite_get_unit_id);
75 if (e) e->size = 6;
76
77 e = create_proc_read_entry("bootrom", S_IRUGO, pdir,
78 excite_bootrom_read, NULL);
79 if (e) e->size = EXCITE_SIZE_BOOTROM;
80 }
81}
diff --git a/arch/mips/basler/excite/excite_prom.c b/arch/mips/basler/excite/excite_prom.c
new file mode 100644
index 000000000000..84724b270753
--- /dev/null
+++ b/arch/mips/basler/excite/excite_prom.c
@@ -0,0 +1,148 @@
1/*
2 * Copyright (C) 2004, 2005 by Thomas Koeller (thomas.koeller@baslerweb.com)
3 * Based on the PMC-Sierra Yosemite board support by Ralf Baechle and
4 * Manish Lachwani.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/config.h>
22#include <linux/init.h>
23#include <linux/sched.h>
24#include <linux/mm.h>
25#include <linux/delay.h>
26#include <linux/smp.h>
27#include <linux/module.h>
28#include <asm/io.h>
29#include <asm/pgtable.h>
30#include <asm/processor.h>
31#include <asm/reboot.h>
32#include <asm/system.h>
33#include <asm/bootinfo.h>
34#include <asm/string.h>
35
36#include <excite.h>
37
38/* This struct is used by Redboot to pass arguments to the kernel */
39typedef struct
40{
41 char *name;
42 char *val;
43} t_env_var;
44
45struct parmblock {
46 t_env_var memsize;
47 t_env_var modetty0;
48 t_env_var ethaddr;
49 t_env_var env_end;
50 char *argv[2];
51 char text[0];
52};
53
54static unsigned int prom_argc;
55static const char ** prom_argv;
56static const t_env_var * prom_env;
57
58static void prom_halt(void) __attribute__((noreturn));
59static void prom_exit(void) __attribute__((noreturn));
60
61
62
63const char *get_system_type(void)
64{
65 return "Basler eXcite";
66}
67
68/*
69 * Halt the system
70 */
71static void prom_halt(void)
72{
73 printk(KERN_NOTICE "\n** System halted.\n");
74 while (1)
75 asm volatile (
76 "\t.set\tmips3\n"
77 "\twait\n"
78 "\t.set\tmips0\n"
79 );
80}
81
82/*
83 * Reset the CPU and re-enter Redboot
84 */
85static void prom_exit(void)
86{
87 unsigned int i;
88 volatile unsigned char * const flg =
89 (volatile unsigned char *) (EXCITE_ADDR_FPGA + EXCITE_FPGA_DPR);
90
91 /* Clear the watchdog reset flag, set the reboot flag */
92 *flg &= ~0x01;
93 *flg |= 0x80;
94
95 for (i = 0; i < 10; i++) {
96 *(volatile unsigned char *) (EXCITE_ADDR_FPGA + EXCITE_FPGA_SYSCTL) = 0x02;
97 iob();
98 mdelay(1000);
99 }
100
101 printk(KERN_NOTICE "Reset failed\n");
102 prom_halt();
103}
104
105static const char __init *prom_getenv(char *name)
106{
107 const t_env_var * p;
108 for (p = prom_env; p->name != NULL; p++)
109 if(strcmp(name, p->name) == 0)
110 break;
111 return p->val;
112}
113
114/*
115 * Init routine which accepts the variables from Redboot
116 */
117void __init prom_init(void)
118{
119 const struct parmblock * const pb = (struct parmblock *) fw_arg2;
120
121 prom_argc = fw_arg0;
122 prom_argv = (const char **) fw_arg1;
123 prom_env = &pb->memsize;
124
125 /* Callbacks for halt, restart */
126 _machine_restart = (void (*)(char *)) prom_exit;
127 _machine_halt = prom_halt;
128
129#ifdef CONFIG_32BIT
130 /* copy command line */
131 strcpy(arcs_cmdline, prom_argv[1]);
132 memsize = simple_strtol(prom_getenv("memsize"), NULL, 16);
133 strcpy(modetty, prom_getenv("modetty0"));
134#endif /* CONFIG_32BIT */
135
136#ifdef CONFIG_64BIT
137# error 64 bit support not implemented
138#endif /* CONFIG_64BIT */
139
140 mips_machgroup = MACH_GROUP_TITAN;
141 mips_machtype = MACH_TITAN_EXCITE;
142}
143
144/* This is called from free_initmem(), so we need to provide it */
145void __init prom_free_prom_memory(void)
146{
147 /* Nothing to do */
148}
diff --git a/arch/mips/basler/excite/excite_setup.c b/arch/mips/basler/excite/excite_setup.c
new file mode 100644
index 000000000000..005b025605e6
--- /dev/null
+++ b/arch/mips/basler/excite/excite_setup.c
@@ -0,0 +1,307 @@
1/*
2 * Copyright (C) 2004, 2005 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 * Based on the PMC-Sierra Yosemite board support by Ralf Baechle and
5 * Manish Lachwani.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/config.h>
23#include <linux/types.h>
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/string.h>
27#include <linux/tty.h>
28#include <linux/serial_core.h>
29#include <linux/serial.h>
30#include <linux/ioport.h>
31#include <linux/spinlock.h>
32#include <asm/bootinfo.h>
33#include <asm/mipsregs.h>
34#include <asm/pgtable-32.h>
35#include <asm/io.h>
36#include <asm/time.h>
37#include <asm/rm9k-ocd.h>
38
39#include <excite.h>
40
41#define TITAN_UART_CLK 25000000
42
43#if 1
44/* normal serial port assignment */
45#define REGBASE_SER0 0x0208
46#define REGBASE_SER1 0x0238
47#define MASK_SER0 0x1
48#define MASK_SER1 0x2
49#else
50/* serial ports swapped */
51#define REGBASE_SER0 0x0238
52#define REGBASE_SER1 0x0208
53#define MASK_SER0 0x2
54#define MASK_SER1 0x1
55#endif
56
57unsigned long memsize;
58char modetty[30];
59unsigned int titan_irq = TITAN_IRQ;
60static void __iomem * ctl_regs;
61u32 unit_id;
62
63volatile void __iomem * const ocd_base = (void *) (EXCITE_ADDR_OCD);
64volatile void __iomem * const titan_base = (void *) (EXCITE_ADDR_TITAN);
65
66/* Protect access to shared GPI registers */
67spinlock_t titan_lock = SPIN_LOCK_UNLOCKED;
68int titan_irqflags;
69
70
71static void excite_timer_init(void)
72{
73 const u32 modebit5 = ocd_readl(0x00e4);
74 unsigned int
75 mult = ((modebit5 >> 11) & 0x1f) + 2,
76 div = ((modebit5 >> 16) & 0x1f) + 2;
77
78 if (div == 33) div = 1;
79 mips_hpt_frequency = EXCITE_CPU_EXT_CLOCK * mult / div / 2;
80}
81
82static void excite_timer_setup(struct irqaction *irq)
83{
84 /* The eXcite platform uses the alternate timer interrupt */
85 set_c0_intcontrol(0x80);
86 setup_irq(TIMER_IRQ, irq);
87}
88
89static int __init excite_init_console(void)
90{
91#if defined(CONFIG_SERIAL_8250)
92 static __initdata char serr[] =
93 KERN_ERR "Serial port #%u setup failed\n";
94 struct uart_port up;
95
96 /* Take the DUART out of reset */
97 titan_writel(0x00ff1cff, CPRR);
98
99#if defined(CONFIG_KGDB) || (CONFIG_SERIAL_8250_NR_UARTS > 1)
100 /* Enable both ports */
101 titan_writel(MASK_SER0 | MASK_SER1, UACFG);
102#else
103 /* Enable port #0 only */
104 titan_writel(MASK_SER0, UACFG);
105#endif /* defined(CONFIG_KGDB) */
106
107 /*
108 * Set up serial port #0. Do not use autodetection; the result is
109 * not what we want.
110 */
111 memset(&up, 0, sizeof(up));
112 up.membase = (char *) titan_addr(REGBASE_SER0);
113 up.irq = TITAN_IRQ;
114 up.uartclk = TITAN_UART_CLK;
115 up.regshift = 0;
116 up.iotype = UPIO_MEM32;
117 up.type = PORT_RM9000;
118 up.flags = UPF_SHARE_IRQ;
119 up.line = 0;
120 if (early_serial_setup(&up))
121 printk(serr, up.line);
122
123#if CONFIG_SERIAL_8250_NR_UARTS > 1
124 /* And now for port #1. */
125 up.membase = (char *) titan_addr(REGBASE_SER1);
126 up.line = 1;
127 if (early_serial_setup(&up))
128 printk(serr, up.line);
129#endif /* CONFIG_SERIAL_8250_NR_UARTS > 1 */
130#else
131 /* Leave the DUART in reset */
132 titan_writel(0x00ff3cff, CPRR);
133#endif /* defined(CONFIG_SERIAL_8250) */
134
135 return 0;
136}
137
138static int __init excite_platform_init(void)
139{
140 unsigned int i;
141 unsigned char buf[3];
142 u8 reg;
143 void __iomem * dpr;
144
145 /* BIU buffer allocations */
146 ocd_writel(8, CPURSLMT); /* CPU */
147 titan_writel(4, CPGRWL); /* GPI / Ethernet */
148
149 /* Map control registers located in FPGA */
150 ctl_regs = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_SYSCTL, 16);
151 if (!ctl_regs)
152 panic("eXcite: failed to map platform control registers\n");
153 memcpy_fromio(buf, ctl_regs + 2, ARRAY_SIZE(buf));
154 unit_id = buf[0] | (buf[1] << 8) | (buf[2] << 16);
155
156 /* Clear the reboot flag */
157 dpr = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_DPR, 1);
158 reg = __raw_readb(dpr);
159 __raw_writeb(reg & 0x7f, dpr);
160 iounmap(dpr);
161
162 /* Interrupt controller setup */
163 for (i = INTP0Status0; i < INTP0Status0 + 0x80; i += 0x10) {
164 ocd_writel(0x00000000, i + 0x04);
165 ocd_writel(0xffffffff, i + 0x0c);
166 }
167 ocd_writel(0x2, NMICONFIG);
168
169 ocd_writel(0x1 << (TITAN_MSGINT % 0x20),
170 INTP0Mask0 + (0x10 * (TITAN_MSGINT / 0x20)));
171 ocd_writel((0x1 << (FPGA0_MSGINT % 0x20))
172 | ocd_readl(INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20))),
173 INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20)));
174 ocd_writel((0x1 << (FPGA1_MSGINT % 0x20))
175 | ocd_readl(INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20))),
176 INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20)));
177 ocd_writel((0x1 << (PHY_MSGINT % 0x20))
178 | ocd_readl(INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20))),
179 INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20)));
180#if USB_IRQ < 10
181 ocd_writel((0x1 << (USB_MSGINT % 0x20))
182 | ocd_readl(INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20))),
183 INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20)));
184#endif
185 /* Enable the packet FIFO, XDMA and XDMA arbiter */
186 titan_writel(0x00ff18ff, CPRR);
187
188 /*
189 * Set up the PADMUX. Power down all ethernet slices,
190 * they will be powered up and configured at device startup.
191 */
192 titan_writel(0x00878206, CPTC1R);
193 titan_writel(0x00001100, CPTC0R); /* latch PADMUX, enable WCIMODE */
194
195 /* Reset and enable the FIFO block */
196 titan_writel(0x00000001, SDRXFCIE);
197 titan_writel(0x00000001, SDTXFCIE);
198 titan_writel(0x00000100, SDRXFCIE);
199 titan_writel(0x00000000, SDTXFCIE);
200
201 /*
202 * Initialize the common interrupt shared by all components of
203 * the GPI/Ethernet subsystem.
204 */
205 titan_writel((EXCITE_PHYS_OCD >> 12), CPCFG0);
206 titan_writel(TITAN_MSGINT, CPCFG1);
207
208 /*
209 * XDMA configuration.
210 * In order for the XDMA to be sharable among multiple drivers,
211 * the setup must be done here in the platform. The reason is that
212 * this setup can only be done while the XDMA is in reset. If this
213 * were done in a driver, it would interrupt all other drivers
214 * using the XDMA.
215 */
216 titan_writel(0x80021dff, GXCFG); /* XDMA reset */
217 titan_writel(0x00000000, CPXCISRA);
218 titan_writel(0x00000000, CPXCISRB); /* clear pending interrupts */
219#if defined (CONFIG_HIGHMEM)
220# error change for HIGHMEM support!
221#else
222 titan_writel(0x00000000, GXDMADRPFX); /* buffer address prefix */
223#endif
224 titan_writel(0, GXDMA_DESCADR);
225
226 for (i = 0x5040; i <= 0x5300; i += 0x0040)
227 titan_writel(0x80080000, i); /* reset channel */
228
229 titan_writel((0x1 << 29) /* no sparse tx descr. */
230 | (0x1 << 28) /* no sparse rx descr. */
231 | (0x1 << 23) | (0x1 << 24) /* descriptor coherency */
232 | (0x1 << 21) | (0x1 << 22) /* data coherency */
233 | (0x1 << 17)
234 | 0x1dff,
235 GXCFG);
236
237#if defined(CONFIG_SMP)
238# error No SMP support
239#else
240 /* All interrupts go to core #0 only. */
241 titan_writel(0x1f007fff, CPDST0A);
242 titan_writel(0x00000000, CPDST0B);
243 titan_writel(0x0000ff3f, CPDST1A);
244 titan_writel(0x00000000, CPDST1B);
245 titan_writel(0x00ffffff, CPXDSTA);
246 titan_writel(0x00000000, CPXDSTB);
247#endif
248
249 /* Enable DUART interrupts, disable everything else. */
250 titan_writel(0x04000000, CPGIG0ER);
251 titan_writel(0x000000c0, CPGIG1ER);
252
253 excite_procfs_init();
254 return 0;
255}
256
257void __init plat_setup(void)
258{
259 volatile u32 * const boot_ocd_base = (u32 *) 0xbf7fc000;
260
261 /* Announce RAM to system */
262 add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
263
264 /* Set up timer initialization hooks */
265 board_time_init = excite_timer_init;
266 board_timer_setup = excite_timer_setup;
267
268 /* Set up the peripheral address map */
269 *(boot_ocd_base + (LKB9 / sizeof (u32))) = 0;
270 *(boot_ocd_base + (LKB10 / sizeof (u32))) = 0;
271 *(boot_ocd_base + (LKB11 / sizeof (u32))) = 0;
272 *(boot_ocd_base + (LKB12 / sizeof (u32))) = 0;
273 wmb();
274 *(boot_ocd_base + (LKB0 / sizeof (u32))) = EXCITE_PHYS_OCD >> 4;
275 wmb();
276
277 ocd_writel((EXCITE_PHYS_TITAN >> 4) | 0x1UL, LKB5);
278 ocd_writel(((EXCITE_SIZE_TITAN >> 4) & 0x7fffff00) - 0x100, LKM5);
279 ocd_writel((EXCITE_PHYS_SCRAM >> 4) | 0x1UL, LKB13);
280 ocd_writel(((EXCITE_SIZE_SCRAM >> 4) & 0xffffff00) - 0x100, LKM13);
281
282 /* Local bus slot #0 */
283 ocd_writel(0x00040510, LDP0);
284 ocd_writel((EXCITE_PHYS_BOOTROM >> 4) | 0x1UL, LKB9);
285 ocd_writel(((EXCITE_SIZE_BOOTROM >> 4) & 0x03ffff00) - 0x100, LKM9);
286
287 /* Local bus slot #2 */
288 ocd_writel(0x00000330, LDP2);
289 ocd_writel((EXCITE_PHYS_FPGA >> 4) | 0x1, LKB11);
290 ocd_writel(((EXCITE_SIZE_FPGA >> 4) - 0x100) & 0x03ffff00, LKM11);
291
292 /* Local bus slot #3 */
293 ocd_writel(0x00123413, LDP3);
294 ocd_writel((EXCITE_PHYS_NAND >> 4) | 0x1, LKB12);
295 ocd_writel(((EXCITE_SIZE_NAND >> 4) - 0x100) & 0x03ffff00, LKM12);
296}
297
298
299
300console_initcall(excite_init_console);
301arch_initcall(excite_platform_init);
302
303EXPORT_SYMBOL(titan_lock);
304EXPORT_SYMBOL(titan_irqflags);
305EXPORT_SYMBOL(titan_irq);
306EXPORT_SYMBOL(ocd_base);
307EXPORT_SYMBOL(titan_base);
diff --git a/arch/mips/cobalt/console.c b/arch/mips/cobalt/console.c
index 45c2d27c7564..300797d5f558 100644
--- a/arch/mips/cobalt/console.c
+++ b/arch/mips/cobalt/console.c
@@ -41,3 +41,8 @@ void __init cobalt_early_console(void)
41 41
42 printk("Cobalt: early console registered\n"); 42 printk("Cobalt: early console registered\n");
43} 43}
44
45void __init disable_early_printk(void)
46{
47 unregister_console(&cons_info);
48}
diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c
index 4f9ea1210023..ca719d6398bd 100644
--- a/arch/mips/cobalt/setup.c
+++ b/arch/mips/cobalt/setup.c
@@ -68,19 +68,46 @@ static void __init cobalt_timer_setup(struct irqaction *irq)
68extern struct pci_ops gt64111_pci_ops; 68extern struct pci_ops gt64111_pci_ops;
69 69
70static struct resource cobalt_mem_resource = { 70static struct resource cobalt_mem_resource = {
71 "PCI memory", GT64111_MEM_BASE, GT64111_MEM_END, IORESOURCE_MEM 71 .start = GT64111_MEM_BASE,
72 .end = GT64111_MEM_END,
73 .name = "PCI memory",
74 .flags = IORESOURCE_MEM
72}; 75};
73 76
74static struct resource cobalt_io_resource = { 77static struct resource cobalt_io_resource = {
75 "PCI I/O", 0x1000, 0xffff, IORESOURCE_IO 78 .start = 0x1000,
79 .end = 0xffff,
80 .name = "PCI I/O",
81 .flags = IORESOURCE_IO
76}; 82};
77 83
78static struct resource cobalt_io_resources[] = { 84static struct resource cobalt_io_resources[] = {
79 { "dma1", 0x00, 0x1f, IORESOURCE_BUSY }, 85 {
80 { "timer", 0x40, 0x5f, IORESOURCE_BUSY }, 86 .start = 0x00,
81 { "keyboard", 0x60, 0x6f, IORESOURCE_BUSY }, 87 .end = 0x1f,
82 { "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY }, 88 .name = "dma1",
83 { "dma2", 0xc0, 0xdf, IORESOURCE_BUSY }, 89 .flags = IORESOURCE_BUSY
90 }, {
91 .start = 0x40,
92 .end = 0x5f,
93 .name = "timer",
94 .flags = IORESOURCE_BUSY
95 }, {
96 .start = 0x60,
97 .end = 0x6f,
98 .name = "keyboard",
99 .flags = IORESOURCE_BUSY
100 }, {
101 .start = 0x80,
102 .end = 0x8f,
103 .name = "dma page reg",
104 .flags = IORESOURCE_BUSY
105 }, {
106 .start = 0xc0,
107 .end = 0xdf,
108 .name = "dma2",
109 .flags = IORESOURCE_BUSY
110 },
84}; 111};
85 112
86#define COBALT_IO_RESOURCES (sizeof(cobalt_io_resources)/sizeof(struct resource)) 113#define COBALT_IO_RESOURCES (sizeof(cobalt_io_resources)/sizeof(struct resource))
@@ -93,7 +120,7 @@ static struct pci_controller cobalt_pci_controller = {
93 .io_offset = 0 - GT64111_IO_BASE 120 .io_offset = 0 - GT64111_IO_BASE
94}; 121};
95 122
96void __init plat_setup(void) 123void __init plat_mem_setup(void)
97{ 124{
98 static struct uart_port uart; 125 static struct uart_port uart;
99 unsigned int devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0); 126 unsigned int devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0);
diff --git a/arch/mips/configs/atlas_defconfig b/arch/mips/configs/atlas_defconfig
index 4b080bcb258f..0cc1b3c51959 100644
--- a/arch/mips/configs/atlas_defconfig
+++ b/arch/mips/configs/atlas_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS_ATLAS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -143,6 +141,15 @@ CONFIG_FLATMEM=y
143CONFIG_FLAT_NODE_MEM_MAP=y 141CONFIG_FLAT_NODE_MEM_MAP=y
144# CONFIG_SPARSEMEM_STATIC is not set 142# CONFIG_SPARSEMEM_STATIC is not set
145CONFIG_SPLIT_PTLOCK_CPUS=4 143CONFIG_SPLIT_PTLOCK_CPUS=4
144# CONFIG_HZ_48 is not set
145CONFIG_HZ_100=y
146# CONFIG_HZ_128 is not set
147# CONFIG_HZ_250 is not set
148# CONFIG_HZ_256 is not set
149# CONFIG_HZ_1000 is not set
150# CONFIG_HZ_1024 is not set
151CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
152CONFIG_HZ=100
146CONFIG_PREEMPT_NONE=y 153CONFIG_PREEMPT_NONE=y
147# CONFIG_PREEMPT_VOLUNTARY is not set 154# CONFIG_PREEMPT_VOLUNTARY is not set
148# CONFIG_PREEMPT is not set 155# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig
index d85cda58d650..dabf90a94b21 100644
--- a/arch/mips/configs/bigsur_defconfig
+++ b/arch/mips/configs/bigsur_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -145,6 +143,15 @@ CONFIG_FLATMEM=y
145CONFIG_FLAT_NODE_MEM_MAP=y 143CONFIG_FLAT_NODE_MEM_MAP=y
146# CONFIG_SPARSEMEM_STATIC is not set 144# CONFIG_SPARSEMEM_STATIC is not set
147CONFIG_SPLIT_PTLOCK_CPUS=4 145CONFIG_SPLIT_PTLOCK_CPUS=4
146# CONFIG_HZ_48 is not set
147# CONFIG_HZ_100 is not set
148# CONFIG_HZ_128 is not set
149# CONFIG_HZ_250 is not set
150# CONFIG_HZ_256 is not set
151CONFIG_HZ_1000=y
152# CONFIG_HZ_1024 is not set
153CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
154CONFIG_HZ=1000
148CONFIG_SMP=y 155CONFIG_SMP=y
149CONFIG_NR_CPUS=4 156CONFIG_NR_CPUS=4
150CONFIG_PREEMPT_NONE=y 157CONFIG_PREEMPT_NONE=y
diff --git a/arch/mips/configs/capcella_defconfig b/arch/mips/configs/capcella_defconfig
index ca0af1683a00..aeb7be804799 100644
--- a/arch/mips/configs/capcella_defconfig
+++ b/arch/mips/configs/capcella_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47CONFIG_MACH_VR41XX=y 45CONFIG_MACH_VR41XX=y
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -132,6 +130,15 @@ CONFIG_FLATMEM=y
132CONFIG_FLAT_NODE_MEM_MAP=y 130CONFIG_FLAT_NODE_MEM_MAP=y
133# CONFIG_SPARSEMEM_STATIC is not set 131# CONFIG_SPARSEMEM_STATIC is not set
134CONFIG_SPLIT_PTLOCK_CPUS=4 132CONFIG_SPLIT_PTLOCK_CPUS=4
133# CONFIG_HZ_48 is not set
134# CONFIG_HZ_100 is not set
135# CONFIG_HZ_128 is not set
136# CONFIG_HZ_250 is not set
137# CONFIG_HZ_256 is not set
138CONFIG_HZ_1000=y
139# CONFIG_HZ_1024 is not set
140CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
141CONFIG_HZ=1000
135CONFIG_PREEMPT_NONE=y 142CONFIG_PREEMPT_NONE=y
136# CONFIG_PREEMPT_VOLUNTARY is not set 143# CONFIG_PREEMPT_VOLUNTARY is not set
137# CONFIG_PREEMPT is not set 144# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig
index 7d269e609282..d680d3e17112 100644
--- a/arch/mips/configs/cobalt_defconfig
+++ b/arch/mips/configs/cobalt_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS_COBALT=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -129,6 +127,15 @@ CONFIG_FLATMEM=y
129CONFIG_FLAT_NODE_MEM_MAP=y 127CONFIG_FLAT_NODE_MEM_MAP=y
130# CONFIG_SPARSEMEM_STATIC is not set 128# CONFIG_SPARSEMEM_STATIC is not set
131CONFIG_SPLIT_PTLOCK_CPUS=4 129CONFIG_SPLIT_PTLOCK_CPUS=4
130# CONFIG_HZ_48 is not set
131# CONFIG_HZ_100 is not set
132# CONFIG_HZ_128 is not set
133# CONFIG_HZ_250 is not set
134# CONFIG_HZ_256 is not set
135CONFIG_HZ_1000=y
136# CONFIG_HZ_1024 is not set
137CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
138CONFIG_HZ=1000
132CONFIG_PREEMPT_NONE=y 139CONFIG_PREEMPT_NONE=y
133# CONFIG_PREEMPT_VOLUNTARY is not set 140# CONFIG_PREEMPT_VOLUNTARY is not set
134# CONFIG_PREEMPT is not set 141# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig
index 579b665e3339..6a7aa401462f 100644
--- a/arch/mips/configs/db1000_defconfig
+++ b/arch/mips/configs/db1000_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS_DB1000=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -130,6 +128,15 @@ CONFIG_FLATMEM=y
130CONFIG_FLAT_NODE_MEM_MAP=y 128CONFIG_FLAT_NODE_MEM_MAP=y
131# CONFIG_SPARSEMEM_STATIC is not set 129# CONFIG_SPARSEMEM_STATIC is not set
132CONFIG_SPLIT_PTLOCK_CPUS=4 130CONFIG_SPLIT_PTLOCK_CPUS=4
131# CONFIG_HZ_48 is not set
132# CONFIG_HZ_100 is not set
133# CONFIG_HZ_128 is not set
134# CONFIG_HZ_250 is not set
135# CONFIG_HZ_256 is not set
136CONFIG_HZ_1000=y
137# CONFIG_HZ_1024 is not set
138CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
139CONFIG_HZ=1000
133CONFIG_PREEMPT_NONE=y 140CONFIG_PREEMPT_NONE=y
134# CONFIG_PREEMPT_VOLUNTARY is not set 141# CONFIG_PREEMPT_VOLUNTARY is not set
135# CONFIG_PREEMPT is not set 142# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig
index e5eb53867422..5c2da563e528 100644
--- a/arch/mips/configs/db1100_defconfig
+++ b/arch/mips/configs/db1100_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS_DB1100=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -130,6 +128,15 @@ CONFIG_FLATMEM=y
130CONFIG_FLAT_NODE_MEM_MAP=y 128CONFIG_FLAT_NODE_MEM_MAP=y
131# CONFIG_SPARSEMEM_STATIC is not set 129# CONFIG_SPARSEMEM_STATIC is not set
132CONFIG_SPLIT_PTLOCK_CPUS=4 130CONFIG_SPLIT_PTLOCK_CPUS=4
131# CONFIG_HZ_48 is not set
132# CONFIG_HZ_100 is not set
133# CONFIG_HZ_128 is not set
134# CONFIG_HZ_250 is not set
135# CONFIG_HZ_256 is not set
136CONFIG_HZ_1000=y
137# CONFIG_HZ_1024 is not set
138CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
139CONFIG_HZ=1000
133CONFIG_PREEMPT_NONE=y 140CONFIG_PREEMPT_NONE=y
134# CONFIG_PREEMPT_VOLUNTARY is not set 141# CONFIG_PREEMPT_VOLUNTARY is not set
135# CONFIG_PREEMPT is not set 142# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig
index a43fb2329fd5..85ef90ce0944 100644
--- a/arch/mips/configs/db1200_defconfig
+++ b/arch/mips/configs/db1200_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS_DB1200=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -130,6 +128,15 @@ CONFIG_FLATMEM=y
130CONFIG_FLAT_NODE_MEM_MAP=y 128CONFIG_FLAT_NODE_MEM_MAP=y
131# CONFIG_SPARSEMEM_STATIC is not set 129# CONFIG_SPARSEMEM_STATIC is not set
132CONFIG_SPLIT_PTLOCK_CPUS=4 130CONFIG_SPLIT_PTLOCK_CPUS=4
131# CONFIG_HZ_48 is not set
132# CONFIG_HZ_100 is not set
133# CONFIG_HZ_128 is not set
134# CONFIG_HZ_250 is not set
135# CONFIG_HZ_256 is not set
136CONFIG_HZ_1000=y
137# CONFIG_HZ_1024 is not set
138CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
139CONFIG_HZ=1000
133CONFIG_PREEMPT_NONE=y 140CONFIG_PREEMPT_NONE=y
134# CONFIG_PREEMPT_VOLUNTARY is not set 141# CONFIG_PREEMPT_VOLUNTARY is not set
135# CONFIG_PREEMPT is not set 142# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig
index ad632d87c4ef..6f757d8a5a6c 100644
--- a/arch/mips/configs/db1500_defconfig
+++ b/arch/mips/configs/db1500_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS_DB1500=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -132,6 +130,15 @@ CONFIG_FLATMEM=y
132CONFIG_FLAT_NODE_MEM_MAP=y 130CONFIG_FLAT_NODE_MEM_MAP=y
133# CONFIG_SPARSEMEM_STATIC is not set 131# CONFIG_SPARSEMEM_STATIC is not set
134CONFIG_SPLIT_PTLOCK_CPUS=4 132CONFIG_SPLIT_PTLOCK_CPUS=4
133# CONFIG_HZ_48 is not set
134# CONFIG_HZ_100 is not set
135# CONFIG_HZ_128 is not set
136# CONFIG_HZ_250 is not set
137# CONFIG_HZ_256 is not set
138CONFIG_HZ_1000=y
139# CONFIG_HZ_1024 is not set
140CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
141CONFIG_HZ=1000
135CONFIG_PREEMPT_NONE=y 142CONFIG_PREEMPT_NONE=y
136# CONFIG_PREEMPT_VOLUNTARY is not set 143# CONFIG_PREEMPT_VOLUNTARY is not set
137# CONFIG_PREEMPT is not set 144# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig
index 8130e23dc255..da4c7e811bef 100644
--- a/arch/mips/configs/db1550_defconfig
+++ b/arch/mips/configs/db1550_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS_DB1550=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -131,6 +129,15 @@ CONFIG_FLATMEM=y
131CONFIG_FLAT_NODE_MEM_MAP=y 129CONFIG_FLAT_NODE_MEM_MAP=y
132# CONFIG_SPARSEMEM_STATIC is not set 130# CONFIG_SPARSEMEM_STATIC is not set
133CONFIG_SPLIT_PTLOCK_CPUS=4 131CONFIG_SPLIT_PTLOCK_CPUS=4
132# CONFIG_HZ_48 is not set
133# CONFIG_HZ_100 is not set
134# CONFIG_HZ_128 is not set
135# CONFIG_HZ_250 is not set
136# CONFIG_HZ_256 is not set
137CONFIG_HZ_1000=y
138# CONFIG_HZ_1024 is not set
139CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
140CONFIG_HZ=1000
134CONFIG_PREEMPT_NONE=y 141CONFIG_PREEMPT_NONE=y
135# CONFIG_PREEMPT_VOLUNTARY is not set 142# CONFIG_PREEMPT_VOLUNTARY is not set
136# CONFIG_PREEMPT is not set 143# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/ddb5477_defconfig b/arch/mips/configs/ddb5477_defconfig
index 8c911b671415..c1c6bfee970e 100644
--- a/arch/mips/configs/ddb5477_defconfig
+++ b/arch/mips/configs/ddb5477_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46CONFIG_DDB5477=y 44CONFIG_DDB5477=y
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -129,6 +127,15 @@ CONFIG_FLATMEM=y
129CONFIG_FLAT_NODE_MEM_MAP=y 127CONFIG_FLAT_NODE_MEM_MAP=y
130# CONFIG_SPARSEMEM_STATIC is not set 128# CONFIG_SPARSEMEM_STATIC is not set
131CONFIG_SPLIT_PTLOCK_CPUS=4 129CONFIG_SPLIT_PTLOCK_CPUS=4
130# CONFIG_HZ_48 is not set
131# CONFIG_HZ_100 is not set
132# CONFIG_HZ_128 is not set
133# CONFIG_HZ_250 is not set
134# CONFIG_HZ_256 is not set
135CONFIG_HZ_1000=y
136# CONFIG_HZ_1024 is not set
137CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
138CONFIG_HZ=1000
132CONFIG_PREEMPT_NONE=y 139CONFIG_PREEMPT_NONE=y
133# CONFIG_PREEMPT_VOLUNTARY is not set 140# CONFIG_PREEMPT_VOLUNTARY is not set
134# CONFIG_PREEMPT is not set 141# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig
index d838496e114f..d5d0d3faae94 100644
--- a/arch/mips/configs/decstation_defconfig
+++ b/arch/mips/configs/decstation_defconfig
@@ -41,8 +41,6 @@ CONFIG_MACH_DECSTATION=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -128,6 +126,17 @@ CONFIG_FLATMEM=y
128CONFIG_FLAT_NODE_MEM_MAP=y 126CONFIG_FLAT_NODE_MEM_MAP=y
129# CONFIG_SPARSEMEM_STATIC is not set 127# CONFIG_SPARSEMEM_STATIC is not set
130CONFIG_SPLIT_PTLOCK_CPUS=4 128CONFIG_SPLIT_PTLOCK_CPUS=4
129# CONFIG_HZ_48 is not set
130# CONFIG_HZ_100 is not set
131CONFIG_HZ_128=y
132# CONFIG_HZ_250 is not set
133# CONFIG_HZ_256 is not set
134# CONFIG_HZ_1000 is not set
135# CONFIG_HZ_1024 is not set
136CONFIG_SYS_SUPPORTS_128HZ=y
137CONFIG_SYS_SUPPORTS_256HZ=y
138CONFIG_SYS_SUPPORTS_1024HZ=y
139CONFIG_HZ=128
131CONFIG_PREEMPT_NONE=y 140CONFIG_PREEMPT_NONE=y
132# CONFIG_PREEMPT_VOLUNTARY is not set 141# CONFIG_PREEMPT_VOLUNTARY is not set
133# CONFIG_PREEMPT is not set 142# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/e55_defconfig b/arch/mips/configs/e55_defconfig
index 0760f4318910..439677ba751c 100644
--- a/arch/mips/configs/e55_defconfig
+++ b/arch/mips/configs/e55_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47CONFIG_MACH_VR41XX=y 45CONFIG_MACH_VR41XX=y
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -130,6 +128,15 @@ CONFIG_FLATMEM=y
130CONFIG_FLAT_NODE_MEM_MAP=y 128CONFIG_FLAT_NODE_MEM_MAP=y
131# CONFIG_SPARSEMEM_STATIC is not set 129# CONFIG_SPARSEMEM_STATIC is not set
132CONFIG_SPLIT_PTLOCK_CPUS=4 130CONFIG_SPLIT_PTLOCK_CPUS=4
131# CONFIG_HZ_48 is not set
132# CONFIG_HZ_100 is not set
133# CONFIG_HZ_128 is not set
134# CONFIG_HZ_250 is not set
135# CONFIG_HZ_256 is not set
136CONFIG_HZ_1000=y
137# CONFIG_HZ_1024 is not set
138CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
139CONFIG_HZ=1000
133CONFIG_PREEMPT_NONE=y 140CONFIG_PREEMPT_NONE=y
134# CONFIG_PREEMPT_VOLUNTARY is not set 141# CONFIG_PREEMPT_VOLUNTARY is not set
135# CONFIG_PREEMPT is not set 142# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/emma2rh_defconfig b/arch/mips/configs/emma2rh_defconfig
new file mode 100644
index 000000000000..01f29f44f3e8
--- /dev/null
+++ b/arch/mips/configs/emma2rh_defconfig
@@ -0,0 +1,1207 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.17
4# Sun Jun 18 13:46:53 2006
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11# CONFIG_MIPS_MTX1 is not set
12# CONFIG_MIPS_BOSPORUS is not set
13# CONFIG_MIPS_PB1000 is not set
14# CONFIG_MIPS_PB1100 is not set
15# CONFIG_MIPS_PB1500 is not set
16# CONFIG_MIPS_PB1550 is not set
17# CONFIG_MIPS_PB1200 is not set
18# CONFIG_MIPS_DB1000 is not set
19# CONFIG_MIPS_DB1100 is not set
20# CONFIG_MIPS_DB1500 is not set
21# CONFIG_MIPS_DB1550 is not set
22# CONFIG_MIPS_DB1200 is not set
23# CONFIG_MIPS_MIRAGE is not set
24# CONFIG_MIPS_COBALT is not set
25# CONFIG_MACH_DECSTATION is not set
26# CONFIG_MIPS_EV64120 is not set
27# CONFIG_MIPS_EV96100 is not set
28# CONFIG_MIPS_IVR is not set
29# CONFIG_MIPS_ITE8172 is not set
30# CONFIG_MACH_JAZZ is not set
31# CONFIG_LASAT is not set
32# CONFIG_MIPS_ATLAS is not set
33# CONFIG_MIPS_MALTA is not set
34# CONFIG_MIPS_SEAD is not set
35# CONFIG_WR_PPMC is not set
36# CONFIG_MIPS_SIM is not set
37# CONFIG_MOMENCO_JAGUAR_ATX is not set
38# CONFIG_MOMENCO_OCELOT is not set
39# CONFIG_MOMENCO_OCELOT_3 is not set
40# CONFIG_MOMENCO_OCELOT_C is not set
41# CONFIG_MOMENCO_OCELOT_G is not set
42# CONFIG_MIPS_XXS1500 is not set
43# CONFIG_PNX8550_V2PCI is not set
44# CONFIG_PNX8550_JBS is not set
45# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set
48# CONFIG_QEMU is not set
49CONFIG_MARKEINS=y
50# CONFIG_SGI_IP22 is not set
51# CONFIG_SGI_IP27 is not set
52# CONFIG_SGI_IP32 is not set
53# CONFIG_SIBYTE_BIGSUR is not set
54# CONFIG_SIBYTE_SWARM is not set
55# CONFIG_SIBYTE_SENTOSA is not set
56# CONFIG_SIBYTE_RHONE is not set
57# CONFIG_SIBYTE_CARMEL is not set
58# CONFIG_SIBYTE_PTSWARM is not set
59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set
63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set
66CONFIG_RWSEM_GENERIC_SPINLOCK=y
67CONFIG_GENERIC_FIND_NEXT_BIT=y
68CONFIG_GENERIC_HWEIGHT=y
69CONFIG_GENERIC_CALIBRATE_DELAY=y
70CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
71CONFIG_DMA_NONCOHERENT=y
72CONFIG_DMA_NEED_PCI_MAP_STATE=y
73CONFIG_CPU_BIG_ENDIAN=y
74# CONFIG_CPU_LITTLE_ENDIAN is not set
75CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
76CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
77CONFIG_IRQ_CPU=y
78CONFIG_SWAP_IO_SPACE=y
79CONFIG_EMMA2RH=y
80CONFIG_MIPS_L1_CACHE_SHIFT=5
81
82#
83# CPU selection
84#
85# CONFIG_CPU_MIPS32_R1 is not set
86# CONFIG_CPU_MIPS32_R2 is not set
87# CONFIG_CPU_MIPS64_R1 is not set
88# CONFIG_CPU_MIPS64_R2 is not set
89# CONFIG_CPU_R3000 is not set
90# CONFIG_CPU_TX39XX is not set
91# CONFIG_CPU_VR41XX is not set
92# CONFIG_CPU_R4300 is not set
93# CONFIG_CPU_R4X00 is not set
94# CONFIG_CPU_TX49XX is not set
95CONFIG_CPU_R5000=y
96# CONFIG_CPU_R5432 is not set
97# CONFIG_CPU_R6000 is not set
98# CONFIG_CPU_NEVADA is not set
99# CONFIG_CPU_R8000 is not set
100# CONFIG_CPU_R10000 is not set
101# CONFIG_CPU_RM7000 is not set
102# CONFIG_CPU_RM9000 is not set
103# CONFIG_CPU_SB1 is not set
104CONFIG_SYS_HAS_CPU_R5000=y
105CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
106CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
107CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
108
109#
110# Kernel type
111#
112CONFIG_32BIT=y
113# CONFIG_64BIT is not set
114CONFIG_PAGE_SIZE_4KB=y
115# CONFIG_PAGE_SIZE_8KB is not set
116# CONFIG_PAGE_SIZE_16KB is not set
117# CONFIG_PAGE_SIZE_64KB is not set
118CONFIG_MIPS_MT_DISABLED=y
119# CONFIG_MIPS_MT_SMTC is not set
120# CONFIG_MIPS_MT_SMP is not set
121# CONFIG_MIPS_VPE_LOADER is not set
122# CONFIG_64BIT_PHYS_ADDR is not set
123CONFIG_CPU_HAS_LLSC=y
124CONFIG_CPU_HAS_SYNC=y
125CONFIG_GENERIC_HARDIRQS=y
126CONFIG_GENERIC_IRQ_PROBE=y
127CONFIG_ARCH_FLATMEM_ENABLE=y
128CONFIG_SELECT_MEMORY_MODEL=y
129CONFIG_FLATMEM_MANUAL=y
130# CONFIG_DISCONTIGMEM_MANUAL is not set
131# CONFIG_SPARSEMEM_MANUAL is not set
132CONFIG_FLATMEM=y
133CONFIG_FLAT_NODE_MEM_MAP=y
134# CONFIG_SPARSEMEM_STATIC is not set
135CONFIG_SPLIT_PTLOCK_CPUS=4
136# CONFIG_HZ_48 is not set
137# CONFIG_HZ_100 is not set
138# CONFIG_HZ_128 is not set
139# CONFIG_HZ_250 is not set
140# CONFIG_HZ_256 is not set
141CONFIG_HZ_1000=y
142# CONFIG_HZ_1024 is not set
143CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
144CONFIG_HZ=1000
145# CONFIG_PREEMPT_NONE is not set
146# CONFIG_PREEMPT_VOLUNTARY is not set
147CONFIG_PREEMPT=y
148CONFIG_PREEMPT_BKL=y
149
150#
151# Code maturity level options
152#
153CONFIG_EXPERIMENTAL=y
154CONFIG_BROKEN_ON_SMP=y
155CONFIG_LOCK_KERNEL=y
156CONFIG_INIT_ENV_ARG_LIMIT=32
157
158#
159# General setup
160#
161CONFIG_LOCALVERSION=""
162CONFIG_LOCALVERSION_AUTO=y
163CONFIG_SWAP=y
164CONFIG_SYSVIPC=y
165CONFIG_POSIX_MQUEUE=y
166CONFIG_BSD_PROCESS_ACCT=y
167# CONFIG_BSD_PROCESS_ACCT_V3 is not set
168CONFIG_SYSCTL=y
169# CONFIG_AUDIT is not set
170CONFIG_IKCONFIG=y
171CONFIG_IKCONFIG_PROC=y
172# CONFIG_RELAY is not set
173CONFIG_INITRAMFS_SOURCE=""
174# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
175CONFIG_EMBEDDED=y
176CONFIG_KALLSYMS=y
177# CONFIG_KALLSYMS_EXTRA_PASS is not set
178CONFIG_HOTPLUG=y
179CONFIG_PRINTK=y
180CONFIG_BUG=y
181CONFIG_ELF_CORE=y
182CONFIG_BASE_FULL=y
183CONFIG_FUTEX=y
184CONFIG_EPOLL=y
185CONFIG_SHMEM=y
186CONFIG_SLAB=y
187# CONFIG_TINY_SHMEM is not set
188CONFIG_BASE_SMALL=0
189# CONFIG_SLOB is not set
190CONFIG_OBSOLETE_INTERMODULE=y
191
192#
193# Loadable module support
194#
195CONFIG_MODULES=y
196CONFIG_MODULE_UNLOAD=y
197CONFIG_MODULE_FORCE_UNLOAD=y
198CONFIG_MODVERSIONS=y
199# CONFIG_MODULE_SRCVERSION_ALL is not set
200CONFIG_KMOD=y
201
202#
203# Block layer
204#
205CONFIG_LBD=y
206# CONFIG_BLK_DEV_IO_TRACE is not set
207# CONFIG_LSF is not set
208
209#
210# IO Schedulers
211#
212CONFIG_IOSCHED_NOOP=y
213CONFIG_IOSCHED_AS=y
214CONFIG_IOSCHED_DEADLINE=y
215CONFIG_IOSCHED_CFQ=y
216CONFIG_DEFAULT_AS=y
217# CONFIG_DEFAULT_DEADLINE is not set
218# CONFIG_DEFAULT_CFQ is not set
219# CONFIG_DEFAULT_NOOP is not set
220CONFIG_DEFAULT_IOSCHED="anticipatory"
221
222#
223# Bus options (PCI, PCMCIA, EISA, ISA, TC)
224#
225CONFIG_HW_HAS_PCI=y
226CONFIG_PCI=y
227CONFIG_MMU=y
228
229#
230# PCCARD (PCMCIA/CardBus) support
231#
232# CONFIG_PCCARD is not set
233
234#
235# PCI Hotplug Support
236#
237# CONFIG_HOTPLUG_PCI is not set
238
239#
240# Executable file formats
241#
242CONFIG_BINFMT_ELF=y
243# CONFIG_BINFMT_MISC is not set
244CONFIG_TRAD_SIGNALS=y
245
246#
247# Networking
248#
249CONFIG_NET=y
250
251#
252# Networking options
253#
254# CONFIG_NETDEBUG is not set
255CONFIG_PACKET=y
256CONFIG_PACKET_MMAP=y
257CONFIG_UNIX=y
258CONFIG_XFRM=y
259# CONFIG_XFRM_USER is not set
260CONFIG_NET_KEY=y
261CONFIG_INET=y
262CONFIG_IP_MULTICAST=y
263CONFIG_IP_ADVANCED_ROUTER=y
264CONFIG_ASK_IP_FIB_HASH=y
265# CONFIG_IP_FIB_TRIE is not set
266CONFIG_IP_FIB_HASH=y
267CONFIG_IP_MULTIPLE_TABLES=y
268# CONFIG_IP_ROUTE_FWMARK is not set
269CONFIG_IP_ROUTE_MULTIPATH=y
270# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set
271CONFIG_IP_ROUTE_VERBOSE=y
272CONFIG_IP_PNP=y
273# CONFIG_IP_PNP_DHCP is not set
274CONFIG_IP_PNP_BOOTP=y
275# CONFIG_IP_PNP_RARP is not set
276# CONFIG_NET_IPIP is not set
277# CONFIG_NET_IPGRE is not set
278# CONFIG_IP_MROUTE is not set
279# CONFIG_ARPD is not set
280CONFIG_SYN_COOKIES=y
281# CONFIG_INET_AH is not set
282# CONFIG_INET_ESP is not set
283# CONFIG_INET_IPCOMP is not set
284# CONFIG_INET_XFRM_TUNNEL is not set
285# CONFIG_INET_TUNNEL is not set
286CONFIG_INET_DIAG=y
287CONFIG_INET_TCP_DIAG=y
288# CONFIG_TCP_CONG_ADVANCED is not set
289CONFIG_TCP_CONG_BIC=y
290
291#
292# IP: Virtual Server Configuration
293#
294# CONFIG_IP_VS is not set
295CONFIG_IPV6=m
296# CONFIG_IPV6_PRIVACY is not set
297# CONFIG_IPV6_ROUTER_PREF is not set
298# CONFIG_INET6_AH is not set
299# CONFIG_INET6_ESP is not set
300# CONFIG_INET6_IPCOMP is not set
301# CONFIG_INET6_XFRM_TUNNEL is not set
302# CONFIG_INET6_TUNNEL is not set
303# CONFIG_IPV6_TUNNEL is not set
304CONFIG_NETFILTER=y
305# CONFIG_NETFILTER_DEBUG is not set
306
307#
308# Core Netfilter Configuration
309#
310# CONFIG_NETFILTER_NETLINK is not set
311# CONFIG_NF_CONNTRACK is not set
312# CONFIG_NETFILTER_XTABLES is not set
313
314#
315# IP: Netfilter Configuration
316#
317# CONFIG_IP_NF_CONNTRACK is not set
318# CONFIG_IP_NF_QUEUE is not set
319
320#
321# IPv6: Netfilter Configuration (EXPERIMENTAL)
322#
323# CONFIG_IP6_NF_QUEUE is not set
324
325#
326# DCCP Configuration (EXPERIMENTAL)
327#
328# CONFIG_IP_DCCP is not set
329
330#
331# SCTP Configuration (EXPERIMENTAL)
332#
333CONFIG_IP_SCTP=m
334# CONFIG_SCTP_DBG_MSG is not set
335# CONFIG_SCTP_DBG_OBJCNT is not set
336# CONFIG_SCTP_HMAC_NONE is not set
337# CONFIG_SCTP_HMAC_SHA1 is not set
338CONFIG_SCTP_HMAC_MD5=y
339
340#
341# TIPC Configuration (EXPERIMENTAL)
342#
343# CONFIG_TIPC is not set
344# CONFIG_ATM is not set
345# CONFIG_BRIDGE is not set
346# CONFIG_VLAN_8021Q is not set
347# CONFIG_DECNET is not set
348# CONFIG_LLC2 is not set
349# CONFIG_IPX is not set
350# CONFIG_ATALK is not set
351# CONFIG_X25 is not set
352# CONFIG_LAPB is not set
353# CONFIG_NET_DIVERT is not set
354# CONFIG_ECONET is not set
355# CONFIG_WAN_ROUTER is not set
356
357#
358# QoS and/or fair queueing
359#
360# CONFIG_NET_SCHED is not set
361
362#
363# Network testing
364#
365# CONFIG_NET_PKTGEN is not set
366# CONFIG_HAMRADIO is not set
367# CONFIG_IRDA is not set
368# CONFIG_BT is not set
369# CONFIG_IEEE80211 is not set
370
371#
372# Device Drivers
373#
374
375#
376# Generic Driver Options
377#
378CONFIG_STANDALONE=y
379CONFIG_PREVENT_FIRMWARE_BUILD=y
380# CONFIG_FW_LOADER is not set
381
382#
383# Connector - unified userspace <-> kernelspace linker
384#
385# CONFIG_CONNECTOR is not set
386
387#
388# Memory Technology Devices (MTD)
389#
390CONFIG_MTD=y
391# CONFIG_MTD_DEBUG is not set
392# CONFIG_MTD_CONCAT is not set
393CONFIG_MTD_PARTITIONS=y
394# CONFIG_MTD_REDBOOT_PARTS is not set
395CONFIG_MTD_CMDLINE_PARTS=y
396
397#
398# User Modules And Translation Layers
399#
400CONFIG_MTD_CHAR=y
401CONFIG_MTD_BLOCK=y
402# CONFIG_FTL is not set
403# CONFIG_NFTL is not set
404# CONFIG_INFTL is not set
405# CONFIG_RFD_FTL is not set
406
407#
408# RAM/ROM/Flash chip drivers
409#
410CONFIG_MTD_CFI=y
411# CONFIG_MTD_JEDECPROBE is not set
412CONFIG_MTD_GEN_PROBE=y
413# CONFIG_MTD_CFI_ADV_OPTIONS is not set
414CONFIG_MTD_MAP_BANK_WIDTH_1=y
415CONFIG_MTD_MAP_BANK_WIDTH_2=y
416CONFIG_MTD_MAP_BANK_WIDTH_4=y
417# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
418# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
419# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
420CONFIG_MTD_CFI_I1=y
421CONFIG_MTD_CFI_I2=y
422# CONFIG_MTD_CFI_I4 is not set
423# CONFIG_MTD_CFI_I8 is not set
424# CONFIG_MTD_CFI_INTELEXT is not set
425CONFIG_MTD_CFI_AMDSTD=y
426# CONFIG_MTD_CFI_STAA is not set
427CONFIG_MTD_CFI_UTIL=y
428# CONFIG_MTD_RAM is not set
429# CONFIG_MTD_ROM is not set
430# CONFIG_MTD_ABSENT is not set
431# CONFIG_MTD_OBSOLETE_CHIPS is not set
432
433#
434# Mapping drivers for chip access
435#
436# CONFIG_MTD_COMPLEX_MAPPINGS is not set
437CONFIG_MTD_PHYSMAP=y
438CONFIG_MTD_PHYSMAP_START=0x1e000000
439CONFIG_MTD_PHYSMAP_LEN=0x02000000
440CONFIG_MTD_PHYSMAP_BANKWIDTH=2
441# CONFIG_MTD_PLATRAM is not set
442
443#
444# Self-contained MTD device drivers
445#
446# CONFIG_MTD_PMC551 is not set
447# CONFIG_MTD_SLRAM is not set
448# CONFIG_MTD_PHRAM is not set
449# CONFIG_MTD_MTDRAM is not set
450# CONFIG_MTD_BLOCK2MTD is not set
451
452#
453# Disk-On-Chip Device Drivers
454#
455# CONFIG_MTD_DOC2000 is not set
456# CONFIG_MTD_DOC2001 is not set
457# CONFIG_MTD_DOC2001PLUS is not set
458
459#
460# NAND Flash Device Drivers
461#
462# CONFIG_MTD_NAND is not set
463
464#
465# OneNAND Flash Device Drivers
466#
467# CONFIG_MTD_ONENAND is not set
468
469#
470# Parallel port support
471#
472# CONFIG_PARPORT is not set
473
474#
475# Plug and Play support
476#
477
478#
479# Block devices
480#
481# CONFIG_BLK_CPQ_DA is not set
482# CONFIG_BLK_CPQ_CISS_DA is not set
483# CONFIG_BLK_DEV_DAC960 is not set
484# CONFIG_BLK_DEV_UMEM is not set
485# CONFIG_BLK_DEV_COW_COMMON is not set
486CONFIG_BLK_DEV_LOOP=m
487CONFIG_BLK_DEV_CRYPTOLOOP=m
488# CONFIG_BLK_DEV_NBD is not set
489# CONFIG_BLK_DEV_SX8 is not set
490# CONFIG_BLK_DEV_RAM is not set
491# CONFIG_BLK_DEV_INITRD is not set
492# CONFIG_CDROM_PKTCDVD is not set
493# CONFIG_ATA_OVER_ETH is not set
494
495#
496# ATA/ATAPI/MFM/RLL support
497#
498# CONFIG_IDE is not set
499
500#
501# SCSI device support
502#
503# CONFIG_RAID_ATTRS is not set
504CONFIG_SCSI=m
505# CONFIG_SCSI_PROC_FS is not set
506
507#
508# SCSI support type (disk, tape, CD-ROM)
509#
510CONFIG_BLK_DEV_SD=m
511# CONFIG_CHR_DEV_ST is not set
512# CONFIG_CHR_DEV_OSST is not set
513# CONFIG_BLK_DEV_SR is not set
514CONFIG_CHR_DEV_SG=m
515# CONFIG_CHR_DEV_SCH is not set
516
517#
518# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
519#
520# CONFIG_SCSI_MULTI_LUN is not set
521# CONFIG_SCSI_CONSTANTS is not set
522# CONFIG_SCSI_LOGGING is not set
523
524#
525# SCSI Transport Attributes
526#
527# CONFIG_SCSI_SPI_ATTRS is not set
528# CONFIG_SCSI_FC_ATTRS is not set
529# CONFIG_SCSI_ISCSI_ATTRS is not set
530# CONFIG_SCSI_SAS_ATTRS is not set
531
532#
533# SCSI low-level drivers
534#
535# CONFIG_ISCSI_TCP is not set
536# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
537# CONFIG_SCSI_3W_9XXX is not set
538# CONFIG_SCSI_ACARD is not set
539# CONFIG_SCSI_AACRAID is not set
540# CONFIG_SCSI_AIC7XXX is not set
541# CONFIG_SCSI_AIC7XXX_OLD is not set
542# CONFIG_SCSI_AIC79XX is not set
543# CONFIG_SCSI_DPT_I2O is not set
544# CONFIG_MEGARAID_NEWGEN is not set
545# CONFIG_MEGARAID_LEGACY is not set
546# CONFIG_MEGARAID_SAS is not set
547# CONFIG_SCSI_SATA is not set
548# CONFIG_SCSI_DMX3191D is not set
549# CONFIG_SCSI_FUTURE_DOMAIN is not set
550# CONFIG_SCSI_IPS is not set
551# CONFIG_SCSI_INITIO is not set
552# CONFIG_SCSI_INIA100 is not set
553# CONFIG_SCSI_SYM53C8XX_2 is not set
554# CONFIG_SCSI_IPR is not set
555# CONFIG_SCSI_QLOGIC_1280 is not set
556# CONFIG_SCSI_QLA_FC is not set
557# CONFIG_SCSI_LPFC is not set
558# CONFIG_SCSI_DC395x is not set
559# CONFIG_SCSI_DC390T is not set
560# CONFIG_SCSI_NSP32 is not set
561# CONFIG_SCSI_DEBUG is not set
562
563#
564# Multi-device support (RAID and LVM)
565#
566# CONFIG_MD is not set
567
568#
569# Fusion MPT device support
570#
571# CONFIG_FUSION is not set
572# CONFIG_FUSION_SPI is not set
573# CONFIG_FUSION_FC is not set
574# CONFIG_FUSION_SAS is not set
575
576#
577# IEEE 1394 (FireWire) support
578#
579# CONFIG_IEEE1394 is not set
580
581#
582# I2O device support
583#
584# CONFIG_I2O is not set
585
586#
587# Network device support
588#
589CONFIG_NETDEVICES=y
590# CONFIG_DUMMY is not set
591# CONFIG_BONDING is not set
592# CONFIG_EQUALIZER is not set
593CONFIG_TUN=m
594
595#
596# ARCnet devices
597#
598# CONFIG_ARCNET is not set
599
600#
601# PHY device support
602#
603# CONFIG_PHYLIB is not set
604
605#
606# Ethernet (10 or 100Mbit)
607#
608CONFIG_NET_ETHERNET=y
609CONFIG_MII=y
610# CONFIG_HAPPYMEAL is not set
611# CONFIG_SUNGEM is not set
612# CONFIG_CASSINI is not set
613# CONFIG_NET_VENDOR_3COM is not set
614# CONFIG_DM9000 is not set
615
616#
617# Tulip family network device support
618#
619# CONFIG_NET_TULIP is not set
620# CONFIG_HP100 is not set
621CONFIG_NET_PCI=y
622# CONFIG_PCNET32 is not set
623# CONFIG_AMD8111_ETH is not set
624# CONFIG_ADAPTEC_STARFIRE is not set
625# CONFIG_B44 is not set
626# CONFIG_FORCEDETH is not set
627# CONFIG_DGRS is not set
628# CONFIG_EEPRO100 is not set
629# CONFIG_E100 is not set
630# CONFIG_FEALNX is not set
631CONFIG_NATSEMI=y
632# CONFIG_NE2K_PCI is not set
633# CONFIG_8139CP is not set
634# CONFIG_8139TOO is not set
635# CONFIG_SIS900 is not set
636# CONFIG_EPIC100 is not set
637# CONFIG_SUNDANCE is not set
638# CONFIG_TLAN is not set
639# CONFIG_VIA_RHINE is not set
640# CONFIG_LAN_SAA9730 is not set
641
642#
643# Ethernet (1000 Mbit)
644#
645# CONFIG_ACENIC is not set
646# CONFIG_DL2K is not set
647# CONFIG_E1000 is not set
648# CONFIG_NS83820 is not set
649# CONFIG_HAMACHI is not set
650# CONFIG_YELLOWFIN is not set
651# CONFIG_R8169 is not set
652# CONFIG_SIS190 is not set
653# CONFIG_SKGE is not set
654# CONFIG_SKY2 is not set
655# CONFIG_SK98LIN is not set
656# CONFIG_VIA_VELOCITY is not set
657# CONFIG_TIGON3 is not set
658# CONFIG_BNX2 is not set
659
660#
661# Ethernet (10000 Mbit)
662#
663# CONFIG_CHELSIO_T1 is not set
664# CONFIG_IXGB is not set
665# CONFIG_S2IO is not set
666
667#
668# Token Ring devices
669#
670# CONFIG_TR is not set
671
672#
673# Wireless LAN (non-hamradio)
674#
675# CONFIG_NET_RADIO is not set
676
677#
678# Wan interfaces
679#
680# CONFIG_WAN is not set
681# CONFIG_FDDI is not set
682# CONFIG_HIPPI is not set
683CONFIG_PPP=m
684# CONFIG_PPP_MULTILINK is not set
685# CONFIG_PPP_FILTER is not set
686CONFIG_PPP_ASYNC=m
687CONFIG_PPP_SYNC_TTY=m
688CONFIG_PPP_DEFLATE=m
689# CONFIG_PPP_BSDCOMP is not set
690# CONFIG_PPP_MPPE is not set
691# CONFIG_PPPOE is not set
692# CONFIG_SLIP is not set
693# CONFIG_NET_FC is not set
694# CONFIG_SHAPER is not set
695# CONFIG_NETCONSOLE is not set
696# CONFIG_NETPOLL is not set
697# CONFIG_NET_POLL_CONTROLLER is not set
698
699#
700# ISDN subsystem
701#
702# CONFIG_ISDN is not set
703
704#
705# Telephony Support
706#
707# CONFIG_PHONE is not set
708
709#
710# Input device support
711#
712CONFIG_INPUT=y
713
714#
715# Userland interfaces
716#
717# CONFIG_INPUT_MOUSEDEV is not set
718# CONFIG_INPUT_JOYDEV is not set
719# CONFIG_INPUT_TSDEV is not set
720CONFIG_INPUT_EVDEV=m
721# CONFIG_INPUT_EVBUG is not set
722
723#
724# Input Device Drivers
725#
726# CONFIG_INPUT_KEYBOARD is not set
727# CONFIG_INPUT_MOUSE is not set
728# CONFIG_INPUT_JOYSTICK is not set
729# CONFIG_INPUT_TOUCHSCREEN is not set
730# CONFIG_INPUT_MISC is not set
731
732#
733# Hardware I/O ports
734#
735# CONFIG_SERIO is not set
736# CONFIG_GAMEPORT is not set
737
738#
739# Character devices
740#
741# CONFIG_VT is not set
742# CONFIG_SERIAL_NONSTANDARD is not set
743
744#
745# Serial drivers
746#
747CONFIG_SERIAL_8250=y
748CONFIG_SERIAL_8250_CONSOLE=y
749CONFIG_SERIAL_8250_PCI=y
750CONFIG_SERIAL_8250_NR_UARTS=4
751CONFIG_SERIAL_8250_RUNTIME_UARTS=4
752# CONFIG_SERIAL_8250_EXTENDED is not set
753
754#
755# Non-8250 serial port support
756#
757CONFIG_SERIAL_CORE=y
758CONFIG_SERIAL_CORE_CONSOLE=y
759# CONFIG_SERIAL_JSM is not set
760CONFIG_UNIX98_PTYS=y
761CONFIG_LEGACY_PTYS=y
762CONFIG_LEGACY_PTY_COUNT=256
763
764#
765# IPMI
766#
767# CONFIG_IPMI_HANDLER is not set
768
769#
770# Watchdog Cards
771#
772# CONFIG_WATCHDOG is not set
773CONFIG_RTC=m
774CONFIG_GEN_RTC=m
775CONFIG_GEN_RTC_X=y
776# CONFIG_DTLK is not set
777# CONFIG_R3964 is not set
778# CONFIG_APPLICOM is not set
779
780#
781# Ftape, the floppy tape device driver
782#
783# CONFIG_DRM is not set
784# CONFIG_RAW_DRIVER is not set
785
786#
787# TPM devices
788#
789# CONFIG_TCG_TPM is not set
790# CONFIG_TELCLOCK is not set
791
792#
793# I2C support
794#
795CONFIG_I2C=y
796CONFIG_I2C_CHARDEV=y
797
798#
799# I2C Algorithms
800#
801# CONFIG_I2C_ALGOBIT is not set
802# CONFIG_I2C_ALGOPCF is not set
803# CONFIG_I2C_ALGOPCA is not set
804
805#
806# I2C Hardware Bus support
807#
808# CONFIG_I2C_ALI1535 is not set
809# CONFIG_I2C_ALI1563 is not set
810# CONFIG_I2C_ALI15X3 is not set
811# CONFIG_I2C_AMD756 is not set
812# CONFIG_I2C_AMD8111 is not set
813# CONFIG_I2C_I801 is not set
814# CONFIG_I2C_I810 is not set
815# CONFIG_I2C_PIIX4 is not set
816# CONFIG_I2C_NFORCE2 is not set
817# CONFIG_I2C_PARPORT_LIGHT is not set
818# CONFIG_I2C_PROSAVAGE is not set
819# CONFIG_I2C_SAVAGE4 is not set
820# CONFIG_I2C_SIS5595 is not set
821# CONFIG_I2C_SIS630 is not set
822# CONFIG_I2C_SIS96X is not set
823# CONFIG_I2C_STUB is not set
824# CONFIG_I2C_VIA is not set
825# CONFIG_I2C_VIAPRO is not set
826# CONFIG_I2C_VOODOO3 is not set
827# CONFIG_I2C_PCA_ISA is not set
828
829#
830# Miscellaneous I2C Chip support
831#
832# CONFIG_SENSORS_DS1337 is not set
833# CONFIG_SENSORS_DS1374 is not set
834# CONFIG_SENSORS_EEPROM is not set
835# CONFIG_SENSORS_PCF8574 is not set
836# CONFIG_SENSORS_PCA9539 is not set
837# CONFIG_SENSORS_PCF8591 is not set
838# CONFIG_SENSORS_MAX6875 is not set
839CONFIG_I2C_DEBUG_CORE=y
840# CONFIG_I2C_DEBUG_ALGO is not set
841CONFIG_I2C_DEBUG_BUS=y
842# CONFIG_I2C_DEBUG_CHIP is not set
843
844#
845# SPI support
846#
847# CONFIG_SPI is not set
848# CONFIG_SPI_MASTER is not set
849
850#
851# Dallas's 1-wire bus
852#
853# CONFIG_W1 is not set
854
855#
856# Hardware Monitoring support
857#
858CONFIG_HWMON=y
859# CONFIG_HWMON_VID is not set
860# CONFIG_SENSORS_ADM1021 is not set
861# CONFIG_SENSORS_ADM1025 is not set
862# CONFIG_SENSORS_ADM1026 is not set
863# CONFIG_SENSORS_ADM1031 is not set
864# CONFIG_SENSORS_ADM9240 is not set
865# CONFIG_SENSORS_ASB100 is not set
866# CONFIG_SENSORS_ATXP1 is not set
867# CONFIG_SENSORS_DS1621 is not set
868# CONFIG_SENSORS_F71805F is not set
869# CONFIG_SENSORS_FSCHER is not set
870# CONFIG_SENSORS_FSCPOS is not set
871# CONFIG_SENSORS_GL518SM is not set
872# CONFIG_SENSORS_GL520SM is not set
873# CONFIG_SENSORS_IT87 is not set
874# CONFIG_SENSORS_LM63 is not set
875# CONFIG_SENSORS_LM75 is not set
876# CONFIG_SENSORS_LM77 is not set
877# CONFIG_SENSORS_LM78 is not set
878# CONFIG_SENSORS_LM80 is not set
879# CONFIG_SENSORS_LM83 is not set
880# CONFIG_SENSORS_LM85 is not set
881# CONFIG_SENSORS_LM87 is not set
882# CONFIG_SENSORS_LM90 is not set
883# CONFIG_SENSORS_LM92 is not set
884# CONFIG_SENSORS_MAX1619 is not set
885# CONFIG_SENSORS_PC87360 is not set
886# CONFIG_SENSORS_SIS5595 is not set
887# CONFIG_SENSORS_SMSC47M1 is not set
888# CONFIG_SENSORS_SMSC47B397 is not set
889# CONFIG_SENSORS_VIA686A is not set
890# CONFIG_SENSORS_VT8231 is not set
891# CONFIG_SENSORS_W83781D is not set
892# CONFIG_SENSORS_W83792D is not set
893# CONFIG_SENSORS_W83L785TS is not set
894# CONFIG_SENSORS_W83627HF is not set
895# CONFIG_SENSORS_W83627EHF is not set
896# CONFIG_HWMON_DEBUG_CHIP is not set
897
898#
899# Misc devices
900#
901
902#
903# Multimedia devices
904#
905# CONFIG_VIDEO_DEV is not set
906CONFIG_VIDEO_V4L2=y
907
908#
909# Digital Video Broadcasting Devices
910#
911# CONFIG_DVB is not set
912
913#
914# Graphics support
915#
916# CONFIG_FB is not set
917
918#
919# Sound
920#
921# CONFIG_SOUND is not set
922
923#
924# USB support
925#
926CONFIG_USB_ARCH_HAS_HCD=y
927CONFIG_USB_ARCH_HAS_OHCI=y
928CONFIG_USB_ARCH_HAS_EHCI=y
929# CONFIG_USB is not set
930
931#
932# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
933#
934
935#
936# USB Gadget Support
937#
938# CONFIG_USB_GADGET is not set
939
940#
941# MMC/SD Card support
942#
943# CONFIG_MMC is not set
944
945#
946# LED devices
947#
948# CONFIG_NEW_LEDS is not set
949
950#
951# LED drivers
952#
953
954#
955# LED Triggers
956#
957
958#
959# InfiniBand support
960#
961# CONFIG_INFINIBAND is not set
962
963#
964# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
965#
966
967#
968# Real Time Clock
969#
970# CONFIG_RTC_CLASS is not set
971
972#
973# File systems
974#
975CONFIG_EXT2_FS=y
976CONFIG_EXT2_FS_XATTR=y
977CONFIG_EXT2_FS_POSIX_ACL=y
978CONFIG_EXT2_FS_SECURITY=y
979# CONFIG_EXT2_FS_XIP is not set
980CONFIG_EXT3_FS=m
981CONFIG_EXT3_FS_XATTR=y
982# CONFIG_EXT3_FS_POSIX_ACL is not set
983# CONFIG_EXT3_FS_SECURITY is not set
984CONFIG_JBD=m
985# CONFIG_JBD_DEBUG is not set
986CONFIG_FS_MBCACHE=y
987# CONFIG_REISERFS_FS is not set
988# CONFIG_JFS_FS is not set
989CONFIG_FS_POSIX_ACL=y
990CONFIG_XFS_FS=m
991CONFIG_XFS_EXPORT=y
992# CONFIG_XFS_QUOTA is not set
993# CONFIG_XFS_SECURITY is not set
994# CONFIG_XFS_POSIX_ACL is not set
995# CONFIG_XFS_RT is not set
996# CONFIG_OCFS2_FS is not set
997# CONFIG_MINIX_FS is not set
998# CONFIG_ROMFS_FS is not set
999CONFIG_INOTIFY=y
1000# CONFIG_QUOTA is not set
1001# CONFIG_DNOTIFY is not set
1002# CONFIG_AUTOFS_FS is not set
1003CONFIG_AUTOFS4_FS=m
1004# CONFIG_FUSE_FS is not set
1005
1006#
1007# CD-ROM/DVD Filesystems
1008#
1009# CONFIG_ISO9660_FS is not set
1010# CONFIG_UDF_FS is not set
1011
1012#
1013# DOS/FAT/NT Filesystems
1014#
1015CONFIG_FAT_FS=y
1016CONFIG_MSDOS_FS=y
1017CONFIG_VFAT_FS=y
1018CONFIG_FAT_DEFAULT_CODEPAGE=437
1019CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1020CONFIG_NTFS_FS=m
1021# CONFIG_NTFS_DEBUG is not set
1022# CONFIG_NTFS_RW is not set
1023
1024#
1025# Pseudo filesystems
1026#
1027CONFIG_PROC_FS=y
1028CONFIG_PROC_KCORE=y
1029CONFIG_SYSFS=y
1030CONFIG_TMPFS=y
1031# CONFIG_HUGETLB_PAGE is not set
1032CONFIG_RAMFS=y
1033# CONFIG_CONFIGFS_FS is not set
1034
1035#
1036# Miscellaneous filesystems
1037#
1038# CONFIG_ADFS_FS is not set
1039# CONFIG_AFFS_FS is not set
1040# CONFIG_HFS_FS is not set
1041# CONFIG_HFSPLUS_FS is not set
1042# CONFIG_BEFS_FS is not set
1043# CONFIG_BFS_FS is not set
1044# CONFIG_EFS_FS is not set
1045# CONFIG_JFFS_FS is not set
1046CONFIG_JFFS2_FS=y
1047CONFIG_JFFS2_FS_DEBUG=0
1048CONFIG_JFFS2_FS_WRITEBUFFER=y
1049# CONFIG_JFFS2_SUMMARY is not set
1050CONFIG_JFFS2_COMPRESSION_OPTIONS=y
1051CONFIG_JFFS2_ZLIB=y
1052CONFIG_JFFS2_RTIME=y
1053# CONFIG_JFFS2_RUBIN is not set
1054# CONFIG_JFFS2_CMODE_NONE is not set
1055CONFIG_JFFS2_CMODE_PRIORITY=y
1056# CONFIG_JFFS2_CMODE_SIZE is not set
1057CONFIG_CRAMFS=y
1058# CONFIG_VXFS_FS is not set
1059# CONFIG_HPFS_FS is not set
1060# CONFIG_QNX4FS_FS is not set
1061# CONFIG_SYSV_FS is not set
1062# CONFIG_UFS_FS is not set
1063
1064#
1065# Network File Systems
1066#
1067CONFIG_NFS_FS=y
1068CONFIG_NFS_V3=y
1069# CONFIG_NFS_V3_ACL is not set
1070CONFIG_NFS_V4=y
1071CONFIG_NFS_DIRECTIO=y
1072CONFIG_NFSD=m
1073CONFIG_NFSD_V3=y
1074# CONFIG_NFSD_V3_ACL is not set
1075# CONFIG_NFSD_V4 is not set
1076CONFIG_NFSD_TCP=y
1077CONFIG_ROOT_NFS=y
1078CONFIG_LOCKD=y
1079CONFIG_LOCKD_V4=y
1080CONFIG_EXPORTFS=m
1081CONFIG_NFS_COMMON=y
1082CONFIG_SUNRPC=y
1083CONFIG_SUNRPC_GSS=y
1084CONFIG_RPCSEC_GSS_KRB5=y
1085# CONFIG_RPCSEC_GSS_SPKM3 is not set
1086CONFIG_SMB_FS=m
1087# CONFIG_SMB_NLS_DEFAULT is not set
1088# CONFIG_CIFS is not set
1089# CONFIG_NCP_FS is not set
1090# CONFIG_CODA_FS is not set
1091# CONFIG_AFS_FS is not set
1092# CONFIG_9P_FS is not set
1093
1094#
1095# Partition Types
1096#
1097# CONFIG_PARTITION_ADVANCED is not set
1098CONFIG_MSDOS_PARTITION=y
1099
1100#
1101# Native Language Support
1102#
1103CONFIG_NLS=y
1104CONFIG_NLS_DEFAULT=""
1105CONFIG_NLS_CODEPAGE_437=m
1106# CONFIG_NLS_CODEPAGE_737 is not set
1107# CONFIG_NLS_CODEPAGE_775 is not set
1108# CONFIG_NLS_CODEPAGE_850 is not set
1109# CONFIG_NLS_CODEPAGE_852 is not set
1110# CONFIG_NLS_CODEPAGE_855 is not set
1111# CONFIG_NLS_CODEPAGE_857 is not set
1112# CONFIG_NLS_CODEPAGE_860 is not set
1113# CONFIG_NLS_CODEPAGE_861 is not set
1114# CONFIG_NLS_CODEPAGE_862 is not set
1115# CONFIG_NLS_CODEPAGE_863 is not set
1116# CONFIG_NLS_CODEPAGE_864 is not set
1117# CONFIG_NLS_CODEPAGE_865 is not set
1118# CONFIG_NLS_CODEPAGE_866 is not set
1119# CONFIG_NLS_CODEPAGE_869 is not set
1120# CONFIG_NLS_CODEPAGE_936 is not set
1121# CONFIG_NLS_CODEPAGE_950 is not set
1122# CONFIG_NLS_CODEPAGE_932 is not set
1123# CONFIG_NLS_CODEPAGE_949 is not set
1124# CONFIG_NLS_CODEPAGE_874 is not set
1125# CONFIG_NLS_ISO8859_8 is not set
1126# CONFIG_NLS_CODEPAGE_1250 is not set
1127# CONFIG_NLS_CODEPAGE_1251 is not set
1128CONFIG_NLS_ASCII=m
1129CONFIG_NLS_ISO8859_1=m
1130# CONFIG_NLS_ISO8859_2 is not set
1131# CONFIG_NLS_ISO8859_3 is not set
1132# CONFIG_NLS_ISO8859_4 is not set
1133# CONFIG_NLS_ISO8859_5 is not set
1134# CONFIG_NLS_ISO8859_6 is not set
1135# CONFIG_NLS_ISO8859_7 is not set
1136# CONFIG_NLS_ISO8859_9 is not set
1137# CONFIG_NLS_ISO8859_13 is not set
1138# CONFIG_NLS_ISO8859_14 is not set
1139# CONFIG_NLS_ISO8859_15 is not set
1140# CONFIG_NLS_KOI8_R is not set
1141# CONFIG_NLS_KOI8_U is not set
1142CONFIG_NLS_UTF8=m
1143
1144#
1145# Profiling support
1146#
1147# CONFIG_PROFILING is not set
1148
1149#
1150# Kernel hacking
1151#
1152# CONFIG_PRINTK_TIME is not set
1153# CONFIG_MAGIC_SYSRQ is not set
1154# CONFIG_DEBUG_KERNEL is not set
1155CONFIG_LOG_BUF_SHIFT=14
1156# CONFIG_DEBUG_FS is not set
1157CONFIG_CROSSCOMPILE=y
1158CONFIG_CMDLINE="console=ttyS0,115200 mem=192m ip=bootp root=/dev/nfs rw"
1159
1160#
1161# Security options
1162#
1163# CONFIG_KEYS is not set
1164# CONFIG_SECURITY is not set
1165
1166#
1167# Cryptographic options
1168#
1169CONFIG_CRYPTO=y
1170CONFIG_CRYPTO_HMAC=y
1171# CONFIG_CRYPTO_NULL is not set
1172# CONFIG_CRYPTO_MD4 is not set
1173CONFIG_CRYPTO_MD5=y
1174# CONFIG_CRYPTO_SHA1 is not set
1175# CONFIG_CRYPTO_SHA256 is not set
1176# CONFIG_CRYPTO_SHA512 is not set
1177# CONFIG_CRYPTO_WP512 is not set
1178# CONFIG_CRYPTO_TGR192 is not set
1179CONFIG_CRYPTO_DES=y
1180# CONFIG_CRYPTO_BLOWFISH is not set
1181# CONFIG_CRYPTO_TWOFISH is not set
1182# CONFIG_CRYPTO_SERPENT is not set
1183# CONFIG_CRYPTO_AES is not set
1184# CONFIG_CRYPTO_CAST5 is not set
1185# CONFIG_CRYPTO_CAST6 is not set
1186# CONFIG_CRYPTO_TEA is not set
1187# CONFIG_CRYPTO_ARC4 is not set
1188# CONFIG_CRYPTO_KHAZAD is not set
1189# CONFIG_CRYPTO_ANUBIS is not set
1190# CONFIG_CRYPTO_DEFLATE is not set
1191# CONFIG_CRYPTO_MICHAEL_MIC is not set
1192# CONFIG_CRYPTO_CRC32C is not set
1193# CONFIG_CRYPTO_TEST is not set
1194
1195#
1196# Hardware crypto devices
1197#
1198
1199#
1200# Library routines
1201#
1202CONFIG_CRC_CCITT=m
1203# CONFIG_CRC16 is not set
1204CONFIG_CRC32=y
1205# CONFIG_LIBCRC32C is not set
1206CONFIG_ZLIB_INFLATE=y
1207CONFIG_ZLIB_DEFLATE=y
diff --git a/arch/mips/configs/ev64120_defconfig b/arch/mips/configs/ev64120_defconfig
index 7067f608b22c..5248a1d8131d 100644
--- a/arch/mips/configs/ev64120_defconfig
+++ b/arch/mips/configs/ev64120_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS_EV64120=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -131,6 +129,15 @@ CONFIG_FLATMEM=y
131CONFIG_FLAT_NODE_MEM_MAP=y 129CONFIG_FLAT_NODE_MEM_MAP=y
132# CONFIG_SPARSEMEM_STATIC is not set 130# CONFIG_SPARSEMEM_STATIC is not set
133CONFIG_SPLIT_PTLOCK_CPUS=4 131CONFIG_SPLIT_PTLOCK_CPUS=4
132# CONFIG_HZ_48 is not set
133# CONFIG_HZ_100 is not set
134# CONFIG_HZ_128 is not set
135# CONFIG_HZ_250 is not set
136# CONFIG_HZ_256 is not set
137CONFIG_HZ_1000=y
138# CONFIG_HZ_1024 is not set
139CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
140CONFIG_HZ=1000
134CONFIG_PREEMPT_NONE=y 141CONFIG_PREEMPT_NONE=y
135# CONFIG_PREEMPT_VOLUNTARY is not set 142# CONFIG_PREEMPT_VOLUNTARY is not set
136# CONFIG_PREEMPT is not set 143# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/ev96100_defconfig b/arch/mips/configs/ev96100_defconfig
index 00b56ed0e638..4858491ce669 100644
--- a/arch/mips/configs/ev96100_defconfig
+++ b/arch/mips/configs/ev96100_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS_EV96100=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -135,6 +133,15 @@ CONFIG_FLATMEM=y
135CONFIG_FLAT_NODE_MEM_MAP=y 133CONFIG_FLAT_NODE_MEM_MAP=y
136# CONFIG_SPARSEMEM_STATIC is not set 134# CONFIG_SPARSEMEM_STATIC is not set
137CONFIG_SPLIT_PTLOCK_CPUS=4 135CONFIG_SPLIT_PTLOCK_CPUS=4
136# CONFIG_HZ_48 is not set
137# CONFIG_HZ_100 is not set
138# CONFIG_HZ_128 is not set
139# CONFIG_HZ_250 is not set
140# CONFIG_HZ_256 is not set
141CONFIG_HZ_1000=y
142# CONFIG_HZ_1024 is not set
143CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
144CONFIG_HZ=1000
138CONFIG_PREEMPT_NONE=y 145CONFIG_PREEMPT_NONE=y
139# CONFIG_PREEMPT_VOLUNTARY is not set 146# CONFIG_PREEMPT_VOLUNTARY is not set
140# CONFIG_PREEMPT is not set 147# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/excite_defconfig b/arch/mips/configs/excite_defconfig
new file mode 100644
index 000000000000..f2ce64cb41a8
--- /dev/null
+++ b/arch/mips/configs/excite_defconfig
@@ -0,0 +1,1220 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.16-rc4
4# Thu Feb 23 13:15:27 2006
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11# CONFIG_MIPS_MTX1 is not set
12# CONFIG_MIPS_BOSPORUS is not set
13# CONFIG_MIPS_PB1000 is not set
14# CONFIG_MIPS_PB1100 is not set
15# CONFIG_MIPS_PB1500 is not set
16# CONFIG_MIPS_PB1550 is not set
17# CONFIG_MIPS_PB1200 is not set
18# CONFIG_MIPS_DB1000 is not set
19# CONFIG_MIPS_DB1100 is not set
20# CONFIG_MIPS_DB1500 is not set
21# CONFIG_MIPS_DB1550 is not set
22# CONFIG_MIPS_DB1200 is not set
23# CONFIG_MIPS_MIRAGE is not set
24# CONFIG_MIPS_COBALT is not set
25# CONFIG_MACH_DECSTATION is not set
26# CONFIG_MIPS_EV64120 is not set
27# CONFIG_MIPS_EV96100 is not set
28# CONFIG_MIPS_IVR is not set
29# CONFIG_MIPS_ITE8172 is not set
30# CONFIG_MACH_JAZZ is not set
31# CONFIG_LASAT is not set
32# CONFIG_MIPS_ATLAS is not set
33# CONFIG_MIPS_MALTA is not set
34# CONFIG_MIPS_SEAD is not set
35# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set
44CONFIG_BASLER_EXCITE=y
45# CONFIG_BASLER_EXCITE_PROTOTYPE is not set
46# CONFIG_DDB5074 is not set
47# CONFIG_DDB5476 is not set
48# CONFIG_DDB5477 is not set
49# CONFIG_MACH_VR41XX is not set
50# CONFIG_PMC_YOSEMITE is not set
51# CONFIG_QEMU is not set
52# CONFIG_SGI_IP22 is not set
53# CONFIG_SGI_IP27 is not set
54# CONFIG_SGI_IP32 is not set
55# CONFIG_SIBYTE_BIGSUR is not set
56# CONFIG_SIBYTE_SWARM is not set
57# CONFIG_SIBYTE_SENTOSA is not set
58# CONFIG_SIBYTE_RHONE is not set
59# CONFIG_SIBYTE_CARMEL is not set
60# CONFIG_SIBYTE_PTSWARM is not set
61# CONFIG_SIBYTE_LITTLESUR is not set
62# CONFIG_SIBYTE_CRHINE is not set
63# CONFIG_SIBYTE_CRHONE is not set
64# CONFIG_SNI_RM200_PCI is not set
65# CONFIG_TOSHIBA_JMR3927 is not set
66# CONFIG_TOSHIBA_RBTX4927 is not set
67# CONFIG_TOSHIBA_RBTX4938 is not set
68CONFIG_RWSEM_GENERIC_SPINLOCK=y
69CONFIG_GENERIC_CALIBRATE_DELAY=y
70CONFIG_DMA_COHERENT=y
71CONFIG_SERIAL_RM9000=y
72CONFIG_CPU_BIG_ENDIAN=y
73# CONFIG_CPU_LITTLE_ENDIAN is not set
74CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
75CONFIG_IRQ_CPU=y
76CONFIG_IRQ_CPU_RM7K=y
77CONFIG_IRQ_CPU_RM9K=y
78CONFIG_MIPS_L1_CACHE_SHIFT=5
79
80#
81# CPU selection
82#
83# CONFIG_CPU_MIPS32_R1 is not set
84# CONFIG_CPU_MIPS32_R2 is not set
85# CONFIG_CPU_MIPS64_R1 is not set
86# CONFIG_CPU_MIPS64_R2 is not set
87# CONFIG_CPU_R3000 is not set
88# CONFIG_CPU_TX39XX is not set
89# CONFIG_CPU_VR41XX is not set
90# CONFIG_CPU_R4300 is not set
91# CONFIG_CPU_R4X00 is not set
92# CONFIG_CPU_TX49XX is not set
93# CONFIG_CPU_R5000 is not set
94# CONFIG_CPU_R5432 is not set
95# CONFIG_CPU_R6000 is not set
96# CONFIG_CPU_NEVADA is not set
97# CONFIG_CPU_R8000 is not set
98# CONFIG_CPU_R10000 is not set
99# CONFIG_CPU_RM7000 is not set
100CONFIG_CPU_RM9000=y
101# CONFIG_CPU_SB1 is not set
102CONFIG_SYS_HAS_CPU_RM9000=y
103CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
104CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
105CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
106CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
107
108#
109# Kernel type
110#
111CONFIG_32BIT=y
112# CONFIG_64BIT is not set
113CONFIG_PAGE_SIZE_4KB=y
114# CONFIG_PAGE_SIZE_8KB is not set
115# CONFIG_PAGE_SIZE_16KB is not set
116# CONFIG_PAGE_SIZE_64KB is not set
117CONFIG_CPU_HAS_PREFETCH=y
118# CONFIG_MIPS_MT is not set
119# CONFIG_64BIT_PHYS_ADDR is not set
120# CONFIG_CPU_ADVANCED is not set
121CONFIG_CPU_HAS_LLSC=y
122CONFIG_CPU_HAS_SYNC=y
123CONFIG_GENERIC_HARDIRQS=y
124CONFIG_GENERIC_IRQ_PROBE=y
125CONFIG_CPU_SUPPORTS_HIGHMEM=y
126CONFIG_ARCH_FLATMEM_ENABLE=y
127CONFIG_SELECT_MEMORY_MODEL=y
128CONFIG_FLATMEM_MANUAL=y
129# CONFIG_DISCONTIGMEM_MANUAL is not set
130# CONFIG_SPARSEMEM_MANUAL is not set
131CONFIG_FLATMEM=y
132CONFIG_FLAT_NODE_MEM_MAP=y
133# CONFIG_SPARSEMEM_STATIC is not set
134CONFIG_SPLIT_PTLOCK_CPUS=4
135# CONFIG_HZ_48 is not set
136# CONFIG_HZ_100 is not set
137# CONFIG_HZ_128 is not set
138# CONFIG_HZ_250 is not set
139# CONFIG_HZ_256 is not set
140CONFIG_HZ_1000=y
141# CONFIG_HZ_1024 is not set
142CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
143CONFIG_HZ=1000
144# CONFIG_SMP is not set
145# CONFIG_PREEMPT_NONE is not set
146# CONFIG_PREEMPT_VOLUNTARY is not set
147CONFIG_PREEMPT=y
148CONFIG_PREEMPT_BKL=y
149
150#
151# Code maturity level options
152#
153CONFIG_EXPERIMENTAL=y
154CONFIG_BROKEN_ON_SMP=y
155CONFIG_LOCK_KERNEL=y
156CONFIG_INIT_ENV_ARG_LIMIT=32
157
158#
159# General setup
160#
161CONFIG_LOCALVERSION=""
162# CONFIG_LOCALVERSION_AUTO is not set
163CONFIG_SWAP=y
164CONFIG_SYSVIPC=y
165CONFIG_POSIX_MQUEUE=y
166# CONFIG_BSD_PROCESS_ACCT is not set
167CONFIG_SYSCTL=y
168# CONFIG_AUDIT is not set
169# CONFIG_IKCONFIG is not set
170CONFIG_INITRAMFS_SOURCE=""
171CONFIG_CC_OPTIMIZE_FOR_SIZE=y
172CONFIG_EMBEDDED=y
173CONFIG_KALLSYMS=y
174# CONFIG_KALLSYMS_EXTRA_PASS is not set
175CONFIG_HOTPLUG=y
176CONFIG_PRINTK=y
177CONFIG_BUG=y
178CONFIG_ELF_CORE=y
179CONFIG_BASE_FULL=y
180CONFIG_FUTEX=y
181CONFIG_EPOLL=y
182CONFIG_SHMEM=y
183CONFIG_CC_ALIGN_FUNCTIONS=0
184CONFIG_CC_ALIGN_LABELS=0
185CONFIG_CC_ALIGN_LOOPS=0
186CONFIG_CC_ALIGN_JUMPS=0
187CONFIG_SLAB=y
188# CONFIG_TINY_SHMEM is not set
189CONFIG_BASE_SMALL=0
190# CONFIG_SLOB is not set
191
192#
193# Loadable module support
194#
195CONFIG_MODULES=y
196CONFIG_MODULE_UNLOAD=y
197# CONFIG_MODULE_FORCE_UNLOAD is not set
198CONFIG_OBSOLETE_MODPARM=y
199# CONFIG_MODVERSIONS is not set
200# CONFIG_MODULE_SRCVERSION_ALL is not set
201CONFIG_KMOD=y
202
203#
204# Block layer
205#
206# CONFIG_LBD is not set
207
208#
209# IO Schedulers
210#
211CONFIG_IOSCHED_NOOP=y
212CONFIG_IOSCHED_AS=y
213CONFIG_IOSCHED_DEADLINE=y
214CONFIG_IOSCHED_CFQ=y
215CONFIG_DEFAULT_AS=y
216# CONFIG_DEFAULT_DEADLINE is not set
217# CONFIG_DEFAULT_CFQ is not set
218# CONFIG_DEFAULT_NOOP is not set
219CONFIG_DEFAULT_IOSCHED="anticipatory"
220
221#
222# Bus options (PCI, PCMCIA, EISA, ISA, TC)
223#
224CONFIG_HW_HAS_PCI=y
225CONFIG_PCI=y
226# CONFIG_PCI_LEGACY_PROC is not set
227CONFIG_MMU=y
228
229#
230# PCCARD (PCMCIA/CardBus) support
231#
232# CONFIG_PCCARD is not set
233
234#
235# PCI Hotplug Support
236#
237# CONFIG_HOTPLUG_PCI is not set
238
239#
240# Executable file formats
241#
242CONFIG_BINFMT_ELF=y
243# CONFIG_BINFMT_MISC is not set
244CONFIG_TRAD_SIGNALS=y
245
246#
247# Networking
248#
249CONFIG_NET=y
250
251#
252# Networking options
253#
254# CONFIG_NETDEBUG is not set
255CONFIG_PACKET=y
256CONFIG_PACKET_MMAP=y
257CONFIG_UNIX=y
258# CONFIG_NET_KEY is not set
259CONFIG_INET=y
260# CONFIG_IP_MULTICAST is not set
261# CONFIG_IP_ADVANCED_ROUTER is not set
262CONFIG_IP_FIB_HASH=y
263CONFIG_IP_PNP=y
264CONFIG_IP_PNP_DHCP=y
265# CONFIG_IP_PNP_BOOTP is not set
266# CONFIG_IP_PNP_RARP is not set
267# CONFIG_NET_IPIP is not set
268# CONFIG_NET_IPGRE is not set
269# CONFIG_ARPD is not set
270# CONFIG_SYN_COOKIES is not set
271# CONFIG_INET_AH is not set
272# CONFIG_INET_ESP is not set
273# CONFIG_INET_IPCOMP is not set
274# CONFIG_INET_TUNNEL is not set
275CONFIG_INET_DIAG=y
276CONFIG_INET_TCP_DIAG=y
277# CONFIG_TCP_CONG_ADVANCED is not set
278CONFIG_TCP_CONG_BIC=y
279# CONFIG_IPV6 is not set
280# CONFIG_NETFILTER is not set
281
282#
283# DCCP Configuration (EXPERIMENTAL)
284#
285# CONFIG_IP_DCCP is not set
286
287#
288# SCTP Configuration (EXPERIMENTAL)
289#
290# CONFIG_IP_SCTP is not set
291
292#
293# TIPC Configuration (EXPERIMENTAL)
294#
295# CONFIG_TIPC is not set
296# CONFIG_ATM is not set
297# CONFIG_BRIDGE is not set
298# CONFIG_VLAN_8021Q is not set
299# CONFIG_DECNET is not set
300# CONFIG_LLC2 is not set
301# CONFIG_IPX is not set
302# CONFIG_ATALK is not set
303# CONFIG_X25 is not set
304# CONFIG_LAPB is not set
305# CONFIG_NET_DIVERT is not set
306# CONFIG_ECONET is not set
307# CONFIG_WAN_ROUTER is not set
308
309#
310# QoS and/or fair queueing
311#
312# CONFIG_NET_SCHED is not set
313
314#
315# Network testing
316#
317# CONFIG_NET_PKTGEN is not set
318# CONFIG_HAMRADIO is not set
319# CONFIG_IRDA is not set
320# CONFIG_BT is not set
321# CONFIG_IEEE80211 is not set
322
323#
324# Device Drivers
325#
326
327#
328# Generic Driver Options
329#
330CONFIG_STANDALONE=y
331CONFIG_PREVENT_FIRMWARE_BUILD=y
332# CONFIG_FW_LOADER is not set
333
334#
335# Connector - unified userspace <-> kernelspace linker
336#
337# CONFIG_CONNECTOR is not set
338
339#
340# Memory Technology Devices (MTD)
341#
342CONFIG_MTD=y
343# CONFIG_MTD_DEBUG is not set
344# CONFIG_MTD_CONCAT is not set
345CONFIG_MTD_PARTITIONS=y
346# CONFIG_MTD_REDBOOT_PARTS is not set
347# CONFIG_MTD_CMDLINE_PARTS is not set
348
349#
350# User Modules And Translation Layers
351#
352CONFIG_MTD_CHAR=y
353CONFIG_MTD_BLOCK=y
354# CONFIG_FTL is not set
355# CONFIG_NFTL is not set
356# CONFIG_INFTL is not set
357# CONFIG_RFD_FTL is not set
358
359#
360# RAM/ROM/Flash chip drivers
361#
362# CONFIG_MTD_CFI is not set
363# CONFIG_MTD_JEDECPROBE is not set
364CONFIG_MTD_MAP_BANK_WIDTH_1=y
365CONFIG_MTD_MAP_BANK_WIDTH_2=y
366CONFIG_MTD_MAP_BANK_WIDTH_4=y
367# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
368# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
369# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
370CONFIG_MTD_CFI_I1=y
371CONFIG_MTD_CFI_I2=y
372# CONFIG_MTD_CFI_I4 is not set
373# CONFIG_MTD_CFI_I8 is not set
374# CONFIG_MTD_RAM is not set
375# CONFIG_MTD_ROM is not set
376# CONFIG_MTD_ABSENT is not set
377# CONFIG_MTD_OBSOLETE_CHIPS is not set
378
379#
380# Mapping drivers for chip access
381#
382# CONFIG_MTD_COMPLEX_MAPPINGS is not set
383# CONFIG_MTD_PLATRAM is not set
384
385#
386# Self-contained MTD device drivers
387#
388# CONFIG_MTD_PMC551 is not set
389# CONFIG_MTD_SLRAM is not set
390# CONFIG_MTD_PHRAM is not set
391# CONFIG_MTD_MTDRAM is not set
392# CONFIG_MTD_BLKMTD is not set
393# CONFIG_MTD_BLOCK2MTD is not set
394
395#
396# Disk-On-Chip Device Drivers
397#
398# CONFIG_MTD_DOC2000 is not set
399# CONFIG_MTD_DOC2001 is not set
400# CONFIG_MTD_DOC2001PLUS is not set
401
402#
403# NAND Flash Device Drivers
404#
405CONFIG_MTD_NAND=y
406CONFIG_MTD_NAND_VERIFY_WRITE=y
407CONFIG_MTD_NAND_IDS=y
408# CONFIG_MTD_NAND_DISKONCHIP is not set
409CONFIG_MTD_NAND_BASLER_EXCITE=y
410# CONFIG_MTD_NAND_BASLER_EXCITE_RDNBY is not set
411# CONFIG_MTD_NAND_BASLER_EXCITE_PERF is not set
412# CONFIG_MTD_NAND_NANDSIM is not set
413
414#
415# OneNAND Flash Device Drivers
416#
417# CONFIG_MTD_ONENAND is not set
418
419#
420# Parallel port support
421#
422# CONFIG_PARPORT is not set
423
424#
425# Plug and Play support
426#
427
428#
429# Block devices
430#
431# CONFIG_BLK_CPQ_DA is not set
432# CONFIG_BLK_CPQ_CISS_DA is not set
433# CONFIG_BLK_DEV_DAC960 is not set
434# CONFIG_BLK_DEV_UMEM is not set
435# CONFIG_BLK_DEV_COW_COMMON is not set
436CONFIG_BLK_DEV_LOOP=m
437# CONFIG_BLK_DEV_CRYPTOLOOP is not set
438# CONFIG_BLK_DEV_NBD is not set
439# CONFIG_BLK_DEV_SX8 is not set
440# CONFIG_BLK_DEV_UB is not set
441# CONFIG_BLK_DEV_RAM is not set
442CONFIG_BLK_DEV_RAM_COUNT=16
443# CONFIG_CDROM_PKTCDVD is not set
444# CONFIG_ATA_OVER_ETH is not set
445
446#
447# ATA/ATAPI/MFM/RLL support
448#
449# CONFIG_IDE is not set
450
451#
452# SCSI device support
453#
454# CONFIG_RAID_ATTRS is not set
455CONFIG_SCSI=y
456# CONFIG_SCSI_PROC_FS is not set
457
458#
459# SCSI support type (disk, tape, CD-ROM)
460#
461CONFIG_BLK_DEV_SD=y
462# CONFIG_CHR_DEV_ST is not set
463# CONFIG_CHR_DEV_OSST is not set
464# CONFIG_BLK_DEV_SR is not set
465# CONFIG_CHR_DEV_SG is not set
466# CONFIG_CHR_DEV_SCH is not set
467
468#
469# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
470#
471# CONFIG_SCSI_MULTI_LUN is not set
472# CONFIG_SCSI_CONSTANTS is not set
473# CONFIG_SCSI_LOGGING is not set
474
475#
476# SCSI Transport Attributes
477#
478# CONFIG_SCSI_SPI_ATTRS is not set
479# CONFIG_SCSI_FC_ATTRS is not set
480# CONFIG_SCSI_ISCSI_ATTRS is not set
481# CONFIG_SCSI_SAS_ATTRS is not set
482
483#
484# SCSI low-level drivers
485#
486# CONFIG_ISCSI_TCP is not set
487# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
488# CONFIG_SCSI_3W_9XXX is not set
489# CONFIG_SCSI_ACARD is not set
490# CONFIG_SCSI_AACRAID is not set
491# CONFIG_SCSI_AIC7XXX is not set
492# CONFIG_SCSI_AIC7XXX_OLD is not set
493# CONFIG_SCSI_AIC79XX is not set
494# CONFIG_SCSI_DPT_I2O is not set
495# CONFIG_MEGARAID_NEWGEN is not set
496# CONFIG_MEGARAID_LEGACY is not set
497# CONFIG_MEGARAID_SAS is not set
498# CONFIG_SCSI_SATA is not set
499# CONFIG_SCSI_DMX3191D is not set
500# CONFIG_SCSI_FUTURE_DOMAIN is not set
501# CONFIG_SCSI_IPS is not set
502# CONFIG_SCSI_INITIO is not set
503# CONFIG_SCSI_INIA100 is not set
504# CONFIG_SCSI_SYM53C8XX_2 is not set
505# CONFIG_SCSI_IPR is not set
506# CONFIG_SCSI_QLOGIC_FC is not set
507# CONFIG_SCSI_QLOGIC_1280 is not set
508# CONFIG_SCSI_QLA_FC is not set
509# CONFIG_SCSI_LPFC is not set
510# CONFIG_SCSI_DC395x is not set
511# CONFIG_SCSI_DC390T is not set
512# CONFIG_SCSI_NSP32 is not set
513# CONFIG_SCSI_DEBUG is not set
514
515#
516# Multi-device support (RAID and LVM)
517#
518# CONFIG_MD is not set
519
520#
521# Fusion MPT device support
522#
523# CONFIG_FUSION is not set
524# CONFIG_FUSION_SPI is not set
525# CONFIG_FUSION_FC is not set
526# CONFIG_FUSION_SAS is not set
527
528#
529# IEEE 1394 (FireWire) support
530#
531# CONFIG_IEEE1394 is not set
532
533#
534# I2O device support
535#
536# CONFIG_I2O is not set
537
538#
539# Network device support
540#
541CONFIG_NETDEVICES=y
542# CONFIG_DUMMY is not set
543# CONFIG_BONDING is not set
544# CONFIG_EQUALIZER is not set
545# CONFIG_TUN is not set
546
547#
548# ARCnet devices
549#
550# CONFIG_ARCNET is not set
551
552#
553# PHY device support
554#
555
556#
557# Ethernet (10 or 100Mbit)
558#
559# CONFIG_NET_ETHERNET is not set
560
561#
562# Ethernet (1000 Mbit)
563#
564# CONFIG_ACENIC is not set
565# CONFIG_DL2K is not set
566# CONFIG_E1000 is not set
567# CONFIG_NS83820 is not set
568# CONFIG_HAMACHI is not set
569# CONFIG_YELLOWFIN is not set
570# CONFIG_R8169 is not set
571# CONFIG_SIS190 is not set
572# CONFIG_SKGE is not set
573# CONFIG_SKY2 is not set
574# CONFIG_SK98LIN is not set
575# CONFIG_TIGON3 is not set
576# CONFIG_BNX2 is not set
577# CONFIG_TITAN_GE is not set
578CONFIG_RM9K_GE=m
579
580#
581# Ethernet (10000 Mbit)
582#
583# CONFIG_CHELSIO_T1 is not set
584# CONFIG_IXGB is not set
585# CONFIG_S2IO is not set
586
587#
588# Token Ring devices
589#
590# CONFIG_TR is not set
591
592#
593# Wireless LAN (non-hamradio)
594#
595# CONFIG_NET_RADIO is not set
596
597#
598# Wan interfaces
599#
600# CONFIG_WAN is not set
601# CONFIG_FDDI is not set
602# CONFIG_HIPPI is not set
603# CONFIG_PPP is not set
604# CONFIG_SLIP is not set
605# CONFIG_NET_FC is not set
606# CONFIG_SHAPER is not set
607# CONFIG_NETCONSOLE is not set
608# CONFIG_NETPOLL is not set
609# CONFIG_NET_POLL_CONTROLLER is not set
610
611#
612# ISDN subsystem
613#
614# CONFIG_ISDN is not set
615
616#
617# Telephony Support
618#
619# CONFIG_PHONE is not set
620
621#
622# Input device support
623#
624CONFIG_INPUT=y
625
626#
627# Userland interfaces
628#
629CONFIG_INPUT_MOUSEDEV=m
630CONFIG_INPUT_MOUSEDEV_PSAUX=y
631CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
632CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
633# CONFIG_INPUT_JOYDEV is not set
634# CONFIG_INPUT_TSDEV is not set
635CONFIG_INPUT_EVDEV=m
636# CONFIG_INPUT_EVBUG is not set
637
638#
639# Input Device Drivers
640#
641# CONFIG_INPUT_KEYBOARD is not set
642# CONFIG_INPUT_MOUSE is not set
643# CONFIG_INPUT_JOYSTICK is not set
644# CONFIG_INPUT_TOUCHSCREEN is not set
645# CONFIG_INPUT_MISC is not set
646
647#
648# Hardware I/O ports
649#
650# CONFIG_SERIO is not set
651# CONFIG_GAMEPORT is not set
652
653#
654# Character devices
655#
656CONFIG_VT=y
657CONFIG_VT_CONSOLE=y
658CONFIG_HW_CONSOLE=y
659# CONFIG_SERIAL_NONSTANDARD is not set
660
661#
662# Serial drivers
663#
664CONFIG_SERIAL_8250=y
665CONFIG_SERIAL_8250_CONSOLE=y
666CONFIG_SERIAL_8250_NR_UARTS=2
667CONFIG_SERIAL_8250_RUNTIME_UARTS=2
668CONFIG_SERIAL_8250_EXTENDED=y
669# CONFIG_SERIAL_8250_MANY_PORTS is not set
670CONFIG_SERIAL_8250_SHARE_IRQ=y
671# CONFIG_SERIAL_8250_DETECT_IRQ is not set
672# CONFIG_SERIAL_8250_RSA is not set
673
674#
675# Non-8250 serial port support
676#
677CONFIG_SERIAL_CORE=y
678CONFIG_SERIAL_CORE_CONSOLE=y
679# CONFIG_SERIAL_JSM is not set
680CONFIG_UNIX98_PTYS=y
681# CONFIG_LEGACY_PTYS is not set
682
683#
684# IPMI
685#
686# CONFIG_IPMI_HANDLER is not set
687
688#
689# Watchdog Cards
690#
691CONFIG_WATCHDOG=y
692# CONFIG_WATCHDOG_NOWAYOUT is not set
693
694#
695# Watchdog Device Drivers
696#
697# CONFIG_SOFT_WATCHDOG is not set
698CONFIG_WDT_RM9K_GPI=m
699
700#
701# PCI-based Watchdog Cards
702#
703# CONFIG_PCIPCWATCHDOG is not set
704# CONFIG_WDTPCI is not set
705
706#
707# USB-based Watchdog Cards
708#
709# CONFIG_USBPCWATCHDOG is not set
710# CONFIG_RTC is not set
711# CONFIG_GEN_RTC is not set
712# CONFIG_DTLK is not set
713# CONFIG_R3964 is not set
714# CONFIG_APPLICOM is not set
715
716#
717# Ftape, the floppy tape device driver
718#
719# CONFIG_DRM is not set
720# CONFIG_RAW_DRIVER is not set
721
722#
723# TPM devices
724#
725# CONFIG_TCG_TPM is not set
726# CONFIG_TELCLOCK is not set
727
728#
729# I2C support
730#
731# CONFIG_I2C is not set
732
733#
734# SPI support
735#
736# CONFIG_SPI is not set
737# CONFIG_SPI_MASTER is not set
738
739#
740# Dallas's 1-wire bus
741#
742# CONFIG_W1 is not set
743
744#
745# Hardware Monitoring support
746#
747# CONFIG_HWMON is not set
748# CONFIG_HWMON_VID is not set
749
750#
751# Misc devices
752#
753
754#
755# Multimedia Capabilities Port drivers
756#
757
758#
759# Multimedia devices
760#
761# CONFIG_VIDEO_DEV is not set
762
763#
764# Digital Video Broadcasting Devices
765#
766# CONFIG_DVB is not set
767
768#
769# Graphics support
770#
771CONFIG_FB=y
772CONFIG_FB_CFB_FILLRECT=y
773CONFIG_FB_CFB_COPYAREA=y
774CONFIG_FB_CFB_IMAGEBLIT=y
775# CONFIG_FB_MACMODES is not set
776# CONFIG_FB_MODE_HELPERS is not set
777# CONFIG_FB_TILEBLITTING is not set
778# CONFIG_FB_CIRRUS is not set
779# CONFIG_FB_PM2 is not set
780# CONFIG_FB_CYBER2000 is not set
781# CONFIG_FB_ASILIANT is not set
782# CONFIG_FB_IMSTT is not set
783# CONFIG_FB_S1D13XXX is not set
784# CONFIG_FB_NVIDIA is not set
785# CONFIG_FB_RIVA is not set
786# CONFIG_FB_MATROX is not set
787# CONFIG_FB_RADEON_OLD is not set
788# CONFIG_FB_RADEON is not set
789# CONFIG_FB_ATY128 is not set
790# CONFIG_FB_ATY is not set
791# CONFIG_FB_SAVAGE is not set
792# CONFIG_FB_SIS is not set
793# CONFIG_FB_NEOMAGIC is not set
794# CONFIG_FB_KYRO is not set
795# CONFIG_FB_3DFX is not set
796# CONFIG_FB_VOODOO1 is not set
797# CONFIG_FB_SMIVGX is not set
798# CONFIG_FB_TRIDENT is not set
799# CONFIG_FB_VIRTUAL is not set
800CONFIG_FB_DD=y
801
802#
803# Console display driver support
804#
805# CONFIG_VGA_CONSOLE is not set
806CONFIG_DUMMY_CONSOLE=y
807CONFIG_FRAMEBUFFER_CONSOLE=m
808# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
809# CONFIG_FONTS is not set
810CONFIG_FONT_8x8=y
811CONFIG_FONT_8x16=y
812
813#
814# Logo configuration
815#
816# CONFIG_LOGO is not set
817# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
818
819#
820# Sound
821#
822# CONFIG_SOUND is not set
823
824#
825# USB support
826#
827CONFIG_USB_ARCH_HAS_HCD=y
828CONFIG_USB_ARCH_HAS_OHCI=y
829CONFIG_USB=y
830# CONFIG_USB_DEBUG is not set
831
832#
833# Miscellaneous USB options
834#
835CONFIG_USB_DEVICEFS=y
836# CONFIG_USB_BANDWIDTH is not set
837# CONFIG_USB_DYNAMIC_MINORS is not set
838# CONFIG_USB_OTG is not set
839
840#
841# USB Host Controller Drivers
842#
843CONFIG_USB_EHCI_HCD=y
844# CONFIG_USB_EHCI_SPLIT_ISO is not set
845# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
846# CONFIG_USB_ISP116X_HCD is not set
847CONFIG_USB_OHCI_HCD=y
848# CONFIG_USB_OHCI_BIG_ENDIAN is not set
849CONFIG_USB_OHCI_LITTLE_ENDIAN=y
850# CONFIG_USB_UHCI_HCD is not set
851# CONFIG_USB_SL811_HCD is not set
852
853#
854# USB Device Class drivers
855#
856# CONFIG_USB_ACM is not set
857# CONFIG_USB_PRINTER is not set
858
859#
860# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
861#
862
863#
864# may also be needed; see USB_STORAGE Help for more information
865#
866CONFIG_USB_STORAGE=y
867# CONFIG_USB_STORAGE_DEBUG is not set
868# CONFIG_USB_STORAGE_DATAFAB is not set
869# CONFIG_USB_STORAGE_FREECOM is not set
870# CONFIG_USB_STORAGE_DPCM is not set
871# CONFIG_USB_STORAGE_USBAT is not set
872# CONFIG_USB_STORAGE_SDDR09 is not set
873# CONFIG_USB_STORAGE_SDDR55 is not set
874# CONFIG_USB_STORAGE_JUMPSHOT is not set
875# CONFIG_USB_STORAGE_ALAUDA is not set
876# CONFIG_USB_STORAGE_ONETOUCH is not set
877# CONFIG_USB_LIBUSUAL is not set
878
879#
880# USB Input Devices
881#
882CONFIG_USB_HID=m
883CONFIG_USB_HIDINPUT=y
884# CONFIG_USB_HIDINPUT_POWERBOOK is not set
885# CONFIG_HID_FF is not set
886# CONFIG_USB_HIDDEV is not set
887
888#
889# USB HID Boot Protocol drivers
890#
891# CONFIG_USB_KBD is not set
892# CONFIG_USB_MOUSE is not set
893# CONFIG_USB_AIPTEK is not set
894# CONFIG_USB_WACOM is not set
895# CONFIG_USB_ACECAD is not set
896# CONFIG_USB_KBTAB is not set
897# CONFIG_USB_POWERMATE is not set
898# CONFIG_USB_MTOUCH is not set
899# CONFIG_USB_ITMTOUCH is not set
900# CONFIG_USB_EGALAX is not set
901# CONFIG_USB_YEALINK is not set
902# CONFIG_USB_XPAD is not set
903# CONFIG_USB_ATI_REMOTE is not set
904# CONFIG_USB_ATI_REMOTE2 is not set
905# CONFIG_USB_KEYSPAN_REMOTE is not set
906# CONFIG_USB_APPLETOUCH is not set
907
908#
909# USB Imaging devices
910#
911# CONFIG_USB_MDC800 is not set
912# CONFIG_USB_MICROTEK is not set
913
914#
915# USB Multimedia devices
916#
917# CONFIG_USB_DABUSB is not set
918
919#
920# Video4Linux support is needed for USB Multimedia device support
921#
922
923#
924# USB Network Adapters
925#
926# CONFIG_USB_CATC is not set
927# CONFIG_USB_KAWETH is not set
928# CONFIG_USB_PEGASUS is not set
929# CONFIG_USB_RTL8150 is not set
930# CONFIG_USB_USBNET is not set
931# CONFIG_USB_MON is not set
932
933#
934# USB port drivers
935#
936
937#
938# USB Serial Converter support
939#
940# CONFIG_USB_SERIAL is not set
941
942#
943# USB Miscellaneous drivers
944#
945# CONFIG_USB_EMI62 is not set
946# CONFIG_USB_EMI26 is not set
947# CONFIG_USB_AUERSWALD is not set
948# CONFIG_USB_RIO500 is not set
949CONFIG_USB_ARTTFT=m
950# CONFIG_USB_ARTTOUCH is not set
951# CONFIG_USB_LEGOTOWER is not set
952# CONFIG_USB_LCD is not set
953# CONFIG_USB_LED is not set
954# CONFIG_USB_CYTHERM is not set
955# CONFIG_USB_PHIDGETKIT is not set
956# CONFIG_USB_PHIDGETSERVO is not set
957# CONFIG_USB_IDMOUSE is not set
958# CONFIG_USB_SISUSBVGA is not set
959# CONFIG_USB_LD is not set
960# CONFIG_USB_TEST is not set
961
962#
963# USB DSL modem support
964#
965
966#
967# USB Gadget Support
968#
969# CONFIG_USB_GADGET is not set
970
971#
972# MMC/SD Card support
973#
974# CONFIG_MMC is not set
975
976#
977# InfiniBand support
978#
979# CONFIG_INFINIBAND is not set
980
981#
982# SN Devices
983#
984
985#
986# EDAC - error detection and reporting (RAS)
987#
988
989#
990# eXcite frame capture support
991#
992CONFIG_EXCITE_FCAP=m
993CONFIG_EXCITE_FCAP_GPI=m
994
995#
996# File systems
997#
998CONFIG_EXT2_FS=y
999# CONFIG_EXT2_FS_XATTR is not set
1000# CONFIG_EXT2_FS_XIP is not set
1001# CONFIG_EXT3_FS is not set
1002# CONFIG_REISERFS_FS is not set
1003# CONFIG_JFS_FS is not set
1004# CONFIG_FS_POSIX_ACL is not set
1005# CONFIG_XFS_FS is not set
1006# CONFIG_OCFS2_FS is not set
1007# CONFIG_MINIX_FS is not set
1008# CONFIG_ROMFS_FS is not set
1009CONFIG_INOTIFY=y
1010# CONFIG_QUOTA is not set
1011# CONFIG_DNOTIFY is not set
1012# CONFIG_AUTOFS_FS is not set
1013# CONFIG_AUTOFS4_FS is not set
1014# CONFIG_FUSE_FS is not set
1015
1016#
1017# CD-ROM/DVD Filesystems
1018#
1019# CONFIG_ISO9660_FS is not set
1020# CONFIG_UDF_FS is not set
1021
1022#
1023# DOS/FAT/NT Filesystems
1024#
1025CONFIG_FAT_FS=m
1026CONFIG_MSDOS_FS=m
1027CONFIG_VFAT_FS=m
1028CONFIG_FAT_DEFAULT_CODEPAGE=437
1029CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1030# CONFIG_NTFS_FS is not set
1031
1032#
1033# Pseudo filesystems
1034#
1035CONFIG_PROC_FS=y
1036CONFIG_PROC_KCORE=y
1037CONFIG_SYSFS=y
1038CONFIG_TMPFS=y
1039# CONFIG_HUGETLB_PAGE is not set
1040CONFIG_RAMFS=y
1041# CONFIG_RELAYFS_FS is not set
1042# CONFIG_CONFIGFS_FS is not set
1043
1044#
1045# Miscellaneous filesystems
1046#
1047# CONFIG_ADFS_FS is not set
1048# CONFIG_AFFS_FS is not set
1049# CONFIG_HFS_FS is not set
1050# CONFIG_HFSPLUS_FS is not set
1051# CONFIG_BEFS_FS is not set
1052# CONFIG_BFS_FS is not set
1053# CONFIG_EFS_FS is not set
1054# CONFIG_JFFS_FS is not set
1055CONFIG_JFFS2_FS=y
1056CONFIG_JFFS2_FS_DEBUG=0
1057CONFIG_JFFS2_FS_WRITEBUFFER=y
1058# CONFIG_JFFS2_SUMMARY is not set
1059# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1060CONFIG_JFFS2_ZLIB=y
1061CONFIG_JFFS2_RTIME=y
1062# CONFIG_JFFS2_RUBIN is not set
1063# CONFIG_CRAMFS is not set
1064# CONFIG_VXFS_FS is not set
1065# CONFIG_HPFS_FS is not set
1066# CONFIG_QNX4FS_FS is not set
1067# CONFIG_SYSV_FS is not set
1068# CONFIG_UFS_FS is not set
1069
1070#
1071# Network File Systems
1072#
1073CONFIG_NFS_FS=y
1074CONFIG_NFS_V3=y
1075# CONFIG_NFS_V3_ACL is not set
1076# CONFIG_NFS_V4 is not set
1077# CONFIG_NFS_DIRECTIO is not set
1078# CONFIG_NFSD is not set
1079CONFIG_ROOT_NFS=y
1080CONFIG_LOCKD=y
1081CONFIG_LOCKD_V4=y
1082CONFIG_NFS_COMMON=y
1083CONFIG_SUNRPC=y
1084# CONFIG_RPCSEC_GSS_KRB5 is not set
1085# CONFIG_RPCSEC_GSS_SPKM3 is not set
1086# CONFIG_SMB_FS is not set
1087# CONFIG_CIFS is not set
1088# CONFIG_NCP_FS is not set
1089# CONFIG_CODA_FS is not set
1090# CONFIG_AFS_FS is not set
1091# CONFIG_9P_FS is not set
1092
1093#
1094# Partition Types
1095#
1096CONFIG_PARTITION_ADVANCED=y
1097# CONFIG_ACORN_PARTITION is not set
1098# CONFIG_OSF_PARTITION is not set
1099# CONFIG_AMIGA_PARTITION is not set
1100# CONFIG_ATARI_PARTITION is not set
1101# CONFIG_MAC_PARTITION is not set
1102CONFIG_MSDOS_PARTITION=y
1103# CONFIG_BSD_DISKLABEL is not set
1104# CONFIG_MINIX_SUBPARTITION is not set
1105# CONFIG_SOLARIS_X86_PARTITION is not set
1106# CONFIG_UNIXWARE_DISKLABEL is not set
1107# CONFIG_LDM_PARTITION is not set
1108# CONFIG_SGI_PARTITION is not set
1109# CONFIG_ULTRIX_PARTITION is not set
1110# CONFIG_SUN_PARTITION is not set
1111# CONFIG_KARMA_PARTITION is not set
1112# CONFIG_EFI_PARTITION is not set
1113
1114#
1115# Native Language Support
1116#
1117CONFIG_NLS=y
1118CONFIG_NLS_DEFAULT="iso8859-1"
1119CONFIG_NLS_CODEPAGE_437=m
1120# CONFIG_NLS_CODEPAGE_737 is not set
1121# CONFIG_NLS_CODEPAGE_775 is not set
1122CONFIG_NLS_CODEPAGE_850=m
1123# CONFIG_NLS_CODEPAGE_852 is not set
1124# CONFIG_NLS_CODEPAGE_855 is not set
1125# CONFIG_NLS_CODEPAGE_857 is not set
1126# CONFIG_NLS_CODEPAGE_860 is not set
1127# CONFIG_NLS_CODEPAGE_861 is not set
1128# CONFIG_NLS_CODEPAGE_862 is not set
1129# CONFIG_NLS_CODEPAGE_863 is not set
1130# CONFIG_NLS_CODEPAGE_864 is not set
1131# CONFIG_NLS_CODEPAGE_865 is not set
1132# CONFIG_NLS_CODEPAGE_866 is not set
1133# CONFIG_NLS_CODEPAGE_869 is not set
1134# CONFIG_NLS_CODEPAGE_936 is not set
1135# CONFIG_NLS_CODEPAGE_950 is not set
1136# CONFIG_NLS_CODEPAGE_932 is not set
1137# CONFIG_NLS_CODEPAGE_949 is not set
1138# CONFIG_NLS_CODEPAGE_874 is not set
1139# CONFIG_NLS_ISO8859_8 is not set
1140# CONFIG_NLS_CODEPAGE_1250 is not set
1141# CONFIG_NLS_CODEPAGE_1251 is not set
1142# CONFIG_NLS_ASCII is not set
1143CONFIG_NLS_ISO8859_1=m
1144# CONFIG_NLS_ISO8859_2 is not set
1145# CONFIG_NLS_ISO8859_3 is not set
1146# CONFIG_NLS_ISO8859_4 is not set
1147# CONFIG_NLS_ISO8859_5 is not set
1148# CONFIG_NLS_ISO8859_6 is not set
1149# CONFIG_NLS_ISO8859_7 is not set
1150# CONFIG_NLS_ISO8859_9 is not set
1151# CONFIG_NLS_ISO8859_13 is not set
1152# CONFIG_NLS_ISO8859_14 is not set
1153# CONFIG_NLS_ISO8859_15 is not set
1154# CONFIG_NLS_KOI8_R is not set
1155# CONFIG_NLS_KOI8_U is not set
1156# CONFIG_NLS_UTF8 is not set
1157
1158#
1159# Profiling support
1160#
1161# CONFIG_PROFILING is not set
1162
1163#
1164# Kernel hacking
1165#
1166# CONFIG_PRINTK_TIME is not set
1167# CONFIG_MAGIC_SYSRQ is not set
1168# CONFIG_DEBUG_KERNEL is not set
1169CONFIG_LOG_BUF_SHIFT=14
1170CONFIG_CROSSCOMPILE=y
1171CONFIG_CMDLINE=""
1172
1173#
1174# Security options
1175#
1176# CONFIG_KEYS is not set
1177# CONFIG_SECURITY is not set
1178
1179#
1180# Cryptographic options
1181#
1182CONFIG_CRYPTO=y
1183# CONFIG_CRYPTO_HMAC is not set
1184# CONFIG_CRYPTO_NULL is not set
1185# CONFIG_CRYPTO_MD4 is not set
1186# CONFIG_CRYPTO_MD5 is not set
1187# CONFIG_CRYPTO_SHA1 is not set
1188# CONFIG_CRYPTO_SHA256 is not set
1189# CONFIG_CRYPTO_SHA512 is not set
1190# CONFIG_CRYPTO_WP512 is not set
1191# CONFIG_CRYPTO_TGR192 is not set
1192# CONFIG_CRYPTO_DES is not set
1193# CONFIG_CRYPTO_BLOWFISH is not set
1194# CONFIG_CRYPTO_TWOFISH is not set
1195# CONFIG_CRYPTO_SERPENT is not set
1196# CONFIG_CRYPTO_AES is not set
1197# CONFIG_CRYPTO_CAST5 is not set
1198# CONFIG_CRYPTO_CAST6 is not set
1199# CONFIG_CRYPTO_TEA is not set
1200# CONFIG_CRYPTO_ARC4 is not set
1201# CONFIG_CRYPTO_KHAZAD is not set
1202# CONFIG_CRYPTO_ANUBIS is not set
1203# CONFIG_CRYPTO_DEFLATE is not set
1204# CONFIG_CRYPTO_MICHAEL_MIC is not set
1205# CONFIG_CRYPTO_CRC32C is not set
1206# CONFIG_CRYPTO_TEST is not set
1207
1208#
1209# Hardware crypto devices
1210#
1211
1212#
1213# Library routines
1214#
1215# CONFIG_CRC_CCITT is not set
1216# CONFIG_CRC16 is not set
1217CONFIG_CRC32=y
1218# CONFIG_LIBCRC32C is not set
1219CONFIG_ZLIB_INFLATE=y
1220CONFIG_ZLIB_DEFLATE=y
diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig
index 607e2985ffe3..879ba1ad99ca 100644
--- a/arch/mips/configs/ip22_defconfig
+++ b/arch/mips/configs/ip22_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -136,6 +134,15 @@ CONFIG_FLATMEM=y
136CONFIG_FLAT_NODE_MEM_MAP=y 134CONFIG_FLAT_NODE_MEM_MAP=y
137# CONFIG_SPARSEMEM_STATIC is not set 135# CONFIG_SPARSEMEM_STATIC is not set
138CONFIG_SPLIT_PTLOCK_CPUS=4 136CONFIG_SPLIT_PTLOCK_CPUS=4
137# CONFIG_HZ_48 is not set
138# CONFIG_HZ_100 is not set
139# CONFIG_HZ_128 is not set
140# CONFIG_HZ_250 is not set
141# CONFIG_HZ_256 is not set
142CONFIG_HZ_1000=y
143# CONFIG_HZ_1024 is not set
144CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
145CONFIG_HZ=1000
139# CONFIG_PREEMPT_NONE is not set 146# CONFIG_PREEMPT_NONE is not set
140CONFIG_PREEMPT_VOLUNTARY=y 147CONFIG_PREEMPT_VOLUNTARY=y
141# CONFIG_PREEMPT is not set 148# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig
index f724b4b2ecf2..bb1426806430 100644
--- a/arch/mips/configs/ip27_defconfig
+++ b/arch/mips/configs/ip27_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -63,7 +61,7 @@ CONFIG_SGI_IP27=y
63# CONFIG_TOSHIBA_JMR3927 is not set 61# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 62# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 63# CONFIG_TOSHIBA_RBTX4938 is not set
66# CONFIG_SGI_SN0_N_MODE is not set 64# CONFIG_SGI_SN_N_MODE is not set
67CONFIG_ARCH_DISCONTIGMEM_ENABLE=y 65CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
68CONFIG_NUMA=y 66CONFIG_NUMA=y
69# CONFIG_MAPPED_KERNEL is not set 67# CONFIG_MAPPED_KERNEL is not set
@@ -135,6 +133,15 @@ CONFIG_FLAT_NODE_MEM_MAP=y
135CONFIG_NEED_MULTIPLE_NODES=y 133CONFIG_NEED_MULTIPLE_NODES=y
136# CONFIG_SPARSEMEM_STATIC is not set 134# CONFIG_SPARSEMEM_STATIC is not set
137CONFIG_SPLIT_PTLOCK_CPUS=4 135CONFIG_SPLIT_PTLOCK_CPUS=4
136# CONFIG_HZ_48 is not set
137# CONFIG_HZ_100 is not set
138# CONFIG_HZ_128 is not set
139# CONFIG_HZ_250 is not set
140# CONFIG_HZ_256 is not set
141CONFIG_HZ_1000=y
142# CONFIG_HZ_1024 is not set
143CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
144CONFIG_HZ=1000
138CONFIG_MIGRATION=y 145CONFIG_MIGRATION=y
139CONFIG_SMP=y 146CONFIG_SMP=y
140CONFIG_NR_CPUS=64 147CONFIG_NR_CPUS=64
diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig
index 8f11d3565b2d..31b3c92a3841 100644
--- a/arch/mips/configs/ip32_defconfig
+++ b/arch/mips/configs/ip32_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -136,6 +134,15 @@ CONFIG_FLATMEM=y
136CONFIG_FLAT_NODE_MEM_MAP=y 134CONFIG_FLAT_NODE_MEM_MAP=y
137# CONFIG_SPARSEMEM_STATIC is not set 135# CONFIG_SPARSEMEM_STATIC is not set
138CONFIG_SPLIT_PTLOCK_CPUS=4 136CONFIG_SPLIT_PTLOCK_CPUS=4
137# CONFIG_HZ_48 is not set
138# CONFIG_HZ_100 is not set
139# CONFIG_HZ_128 is not set
140# CONFIG_HZ_250 is not set
141# CONFIG_HZ_256 is not set
142CONFIG_HZ_1000=y
143# CONFIG_HZ_1024 is not set
144CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
145CONFIG_HZ=1000
139# CONFIG_PREEMPT_NONE is not set 146# CONFIG_PREEMPT_NONE is not set
140CONFIG_PREEMPT_VOLUNTARY=y 147CONFIG_PREEMPT_VOLUNTARY=y
141# CONFIG_PREEMPT is not set 148# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/it8172_defconfig b/arch/mips/configs/it8172_defconfig
index 757adf23853d..809bae9013ac 100644
--- a/arch/mips/configs/it8172_defconfig
+++ b/arch/mips/configs/it8172_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS_ITE8172=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -130,6 +128,15 @@ CONFIG_FLATMEM=y
130CONFIG_FLAT_NODE_MEM_MAP=y 128CONFIG_FLAT_NODE_MEM_MAP=y
131# CONFIG_SPARSEMEM_STATIC is not set 129# CONFIG_SPARSEMEM_STATIC is not set
132CONFIG_SPLIT_PTLOCK_CPUS=4 130CONFIG_SPLIT_PTLOCK_CPUS=4
131# CONFIG_HZ_48 is not set
132# CONFIG_HZ_100 is not set
133# CONFIG_HZ_128 is not set
134# CONFIG_HZ_250 is not set
135# CONFIG_HZ_256 is not set
136CONFIG_HZ_1000=y
137# CONFIG_HZ_1024 is not set
138CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
139CONFIG_HZ=1000
133CONFIG_PREEMPT_NONE=y 140CONFIG_PREEMPT_NONE=y
134# CONFIG_PREEMPT_VOLUNTARY is not set 141# CONFIG_PREEMPT_VOLUNTARY is not set
135# CONFIG_PREEMPT is not set 142# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/ivr_defconfig b/arch/mips/configs/ivr_defconfig
index 021761a8a237..55108fd67844 100644
--- a/arch/mips/configs/ivr_defconfig
+++ b/arch/mips/configs/ivr_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS_IVR=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -127,6 +125,15 @@ CONFIG_FLATMEM=y
127CONFIG_FLAT_NODE_MEM_MAP=y 125CONFIG_FLAT_NODE_MEM_MAP=y
128# CONFIG_SPARSEMEM_STATIC is not set 126# CONFIG_SPARSEMEM_STATIC is not set
129CONFIG_SPLIT_PTLOCK_CPUS=4 127CONFIG_SPLIT_PTLOCK_CPUS=4
128# CONFIG_HZ_48 is not set
129# CONFIG_HZ_100 is not set
130# CONFIG_HZ_128 is not set
131# CONFIG_HZ_250 is not set
132# CONFIG_HZ_256 is not set
133CONFIG_HZ_1000=y
134# CONFIG_HZ_1024 is not set
135CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
136CONFIG_HZ=1000
130CONFIG_PREEMPT_NONE=y 137CONFIG_PREEMPT_NONE=y
131# CONFIG_PREEMPT_VOLUNTARY is not set 138# CONFIG_PREEMPT_VOLUNTARY is not set
132# CONFIG_PREEMPT is not set 139# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/jaguar-atx_defconfig b/arch/mips/configs/jaguar-atx_defconfig
index 08f6c30b0abc..ef2843436057 100644
--- a/arch/mips/configs/jaguar-atx_defconfig
+++ b/arch/mips/configs/jaguar-atx_defconfig
@@ -41,8 +41,6 @@ CONFIG_MOMENCO_JAGUAR_ATX=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -136,6 +134,15 @@ CONFIG_FLATMEM=y
136CONFIG_FLAT_NODE_MEM_MAP=y 134CONFIG_FLAT_NODE_MEM_MAP=y
137# CONFIG_SPARSEMEM_STATIC is not set 135# CONFIG_SPARSEMEM_STATIC is not set
138CONFIG_SPLIT_PTLOCK_CPUS=4 136CONFIG_SPLIT_PTLOCK_CPUS=4
137# CONFIG_HZ_48 is not set
138# CONFIG_HZ_100 is not set
139# CONFIG_HZ_128 is not set
140# CONFIG_HZ_250 is not set
141# CONFIG_HZ_256 is not set
142CONFIG_HZ_1000=y
143# CONFIG_HZ_1024 is not set
144CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
145CONFIG_HZ=1000
139# CONFIG_SMP is not set 146# CONFIG_SMP is not set
140CONFIG_PREEMPT_NONE=y 147CONFIG_PREEMPT_NONE=y
141# CONFIG_PREEMPT_VOLUNTARY is not set 148# CONFIG_PREEMPT_VOLUNTARY is not set
diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig
index 38b1e026e10d..5ef5a08289a5 100644
--- a/arch/mips/configs/jmr3927_defconfig
+++ b/arch/mips/configs/jmr3927_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -125,6 +123,15 @@ CONFIG_FLATMEM=y
125CONFIG_FLAT_NODE_MEM_MAP=y 123CONFIG_FLAT_NODE_MEM_MAP=y
126# CONFIG_SPARSEMEM_STATIC is not set 124# CONFIG_SPARSEMEM_STATIC is not set
127CONFIG_SPLIT_PTLOCK_CPUS=4 125CONFIG_SPLIT_PTLOCK_CPUS=4
126# CONFIG_HZ_48 is not set
127# CONFIG_HZ_100 is not set
128# CONFIG_HZ_128 is not set
129# CONFIG_HZ_250 is not set
130# CONFIG_HZ_256 is not set
131CONFIG_HZ_1000=y
132# CONFIG_HZ_1024 is not set
133CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
134CONFIG_HZ=1000
128CONFIG_PREEMPT_NONE=y 135CONFIG_PREEMPT_NONE=y
129# CONFIG_PREEMPT_VOLUNTARY is not set 136# CONFIG_PREEMPT_VOLUNTARY is not set
130# CONFIG_PREEMPT is not set 137# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/lasat200_defconfig b/arch/mips/configs/lasat200_defconfig
index 4d25990a0a05..eabcff26fc0e 100644
--- a/arch/mips/configs/lasat200_defconfig
+++ b/arch/mips/configs/lasat200_defconfig
@@ -41,8 +41,6 @@ CONFIG_LASAT=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -134,6 +132,15 @@ CONFIG_FLATMEM=y
134CONFIG_FLAT_NODE_MEM_MAP=y 132CONFIG_FLAT_NODE_MEM_MAP=y
135# CONFIG_SPARSEMEM_STATIC is not set 133# CONFIG_SPARSEMEM_STATIC is not set
136CONFIG_SPLIT_PTLOCK_CPUS=4 134CONFIG_SPLIT_PTLOCK_CPUS=4
135# CONFIG_HZ_48 is not set
136# CONFIG_HZ_100 is not set
137# CONFIG_HZ_128 is not set
138# CONFIG_HZ_250 is not set
139# CONFIG_HZ_256 is not set
140CONFIG_HZ_1000=y
141# CONFIG_HZ_1024 is not set
142CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
143CONFIG_HZ=1000
137CONFIG_PREEMPT_NONE=y 144CONFIG_PREEMPT_NONE=y
138# CONFIG_PREEMPT_VOLUNTARY is not set 145# CONFIG_PREEMPT_VOLUNTARY is not set
139# CONFIG_PREEMPT is not set 146# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig
index 977f52be51dc..b73cff0d83ca 100644
--- a/arch/mips/configs/malta_defconfig
+++ b/arch/mips/configs/malta_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS_MALTA=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -154,6 +152,15 @@ CONFIG_FLATMEM=y
154CONFIG_FLAT_NODE_MEM_MAP=y 152CONFIG_FLAT_NODE_MEM_MAP=y
155# CONFIG_SPARSEMEM_STATIC is not set 153# CONFIG_SPARSEMEM_STATIC is not set
156CONFIG_SPLIT_PTLOCK_CPUS=4 154CONFIG_SPLIT_PTLOCK_CPUS=4
155# CONFIG_HZ_48 is not set
156CONFIG_HZ_100=y
157# CONFIG_HZ_128 is not set
158# CONFIG_HZ_250 is not set
159# CONFIG_HZ_256 is not set
160# CONFIG_HZ_1000 is not set
161# CONFIG_HZ_1024 is not set
162CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
163CONFIG_HZ=100
157CONFIG_PREEMPT_NONE=y 164CONFIG_PREEMPT_NONE=y
158# CONFIG_PREEMPT_VOLUNTARY is not set 165# CONFIG_PREEMPT_VOLUNTARY is not set
159# CONFIG_PREEMPT is not set 166# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig
index 00560e0143f1..8dd27b55413d 100644
--- a/arch/mips/configs/mipssim_defconfig
+++ b/arch/mips/configs/mipssim_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS_SIM=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -138,6 +136,15 @@ CONFIG_FLATMEM=y
138CONFIG_FLAT_NODE_MEM_MAP=y 136CONFIG_FLAT_NODE_MEM_MAP=y
139# CONFIG_SPARSEMEM_STATIC is not set 137# CONFIG_SPARSEMEM_STATIC is not set
140CONFIG_SPLIT_PTLOCK_CPUS=4 138CONFIG_SPLIT_PTLOCK_CPUS=4
139# CONFIG_HZ_48 is not set
140# CONFIG_HZ_100 is not set
141# CONFIG_HZ_128 is not set
142# CONFIG_HZ_250 is not set
143# CONFIG_HZ_256 is not set
144CONFIG_HZ_1000=y
145# CONFIG_HZ_1024 is not set
146CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
147CONFIG_HZ=1000
141CONFIG_PREEMPT_NONE=y 148CONFIG_PREEMPT_NONE=y
142# CONFIG_PREEMPT_VOLUNTARY is not set 149# CONFIG_PREEMPT_VOLUNTARY is not set
143# CONFIG_PREEMPT is not set 150# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/mpc30x_defconfig b/arch/mips/configs/mpc30x_defconfig
index 286a018375b2..5d6ff3c352c9 100644
--- a/arch/mips/configs/mpc30x_defconfig
+++ b/arch/mips/configs/mpc30x_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47CONFIG_MACH_VR41XX=y 45CONFIG_MACH_VR41XX=y
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -132,6 +130,15 @@ CONFIG_FLATMEM=y
132CONFIG_FLAT_NODE_MEM_MAP=y 130CONFIG_FLAT_NODE_MEM_MAP=y
133# CONFIG_SPARSEMEM_STATIC is not set 131# CONFIG_SPARSEMEM_STATIC is not set
134CONFIG_SPLIT_PTLOCK_CPUS=4 132CONFIG_SPLIT_PTLOCK_CPUS=4
133# CONFIG_HZ_48 is not set
134# CONFIG_HZ_100 is not set
135# CONFIG_HZ_128 is not set
136# CONFIG_HZ_250 is not set
137# CONFIG_HZ_256 is not set
138CONFIG_HZ_1000=y
139# CONFIG_HZ_1024 is not set
140CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
141CONFIG_HZ=1000
135CONFIG_PREEMPT_NONE=y 142CONFIG_PREEMPT_NONE=y
136# CONFIG_PREEMPT_VOLUNTARY is not set 143# CONFIG_PREEMPT_VOLUNTARY is not set
137# CONFIG_PREEMPT is not set 144# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/ocelot_3_defconfig b/arch/mips/configs/ocelot_3_defconfig
index 1ce4310fd92a..fe5e3dd915f5 100644
--- a/arch/mips/configs/ocelot_3_defconfig
+++ b/arch/mips/configs/ocelot_3_defconfig
@@ -41,8 +41,6 @@ CONFIG_MOMENCO_OCELOT_3=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -136,6 +134,15 @@ CONFIG_FLATMEM=y
136CONFIG_FLAT_NODE_MEM_MAP=y 134CONFIG_FLAT_NODE_MEM_MAP=y
137# CONFIG_SPARSEMEM_STATIC is not set 135# CONFIG_SPARSEMEM_STATIC is not set
138CONFIG_SPLIT_PTLOCK_CPUS=4 136CONFIG_SPLIT_PTLOCK_CPUS=4
137# CONFIG_HZ_48 is not set
138# CONFIG_HZ_100 is not set
139# CONFIG_HZ_128 is not set
140# CONFIG_HZ_250 is not set
141# CONFIG_HZ_256 is not set
142CONFIG_HZ_1000=y
143# CONFIG_HZ_1024 is not set
144CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
145CONFIG_HZ=1000
139# CONFIG_SMP is not set 146# CONFIG_SMP is not set
140CONFIG_PREEMPT_NONE=y 147CONFIG_PREEMPT_NONE=y
141# CONFIG_PREEMPT_VOLUNTARY is not set 148# CONFIG_PREEMPT_VOLUNTARY is not set
diff --git a/arch/mips/configs/ocelot_c_defconfig b/arch/mips/configs/ocelot_c_defconfig
index 8a6aa5012f89..f4a33ce47e50 100644
--- a/arch/mips/configs/ocelot_c_defconfig
+++ b/arch/mips/configs/ocelot_c_defconfig
@@ -41,8 +41,6 @@ CONFIG_MOMENCO_OCELOT_C=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -133,6 +131,15 @@ CONFIG_FLATMEM=y
133CONFIG_FLAT_NODE_MEM_MAP=y 131CONFIG_FLAT_NODE_MEM_MAP=y
134# CONFIG_SPARSEMEM_STATIC is not set 132# CONFIG_SPARSEMEM_STATIC is not set
135CONFIG_SPLIT_PTLOCK_CPUS=4 133CONFIG_SPLIT_PTLOCK_CPUS=4
134# CONFIG_HZ_48 is not set
135# CONFIG_HZ_100 is not set
136# CONFIG_HZ_128 is not set
137# CONFIG_HZ_250 is not set
138# CONFIG_HZ_256 is not set
139CONFIG_HZ_1000=y
140# CONFIG_HZ_1024 is not set
141CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
142CONFIG_HZ=1000
136CONFIG_PREEMPT_NONE=y 143CONFIG_PREEMPT_NONE=y
137# CONFIG_PREEMPT_VOLUNTARY is not set 144# CONFIG_PREEMPT_VOLUNTARY is not set
138# CONFIG_PREEMPT is not set 145# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/ocelot_defconfig b/arch/mips/configs/ocelot_defconfig
index f9ee35eeb762..21dea9549feb 100644
--- a/arch/mips/configs/ocelot_defconfig
+++ b/arch/mips/configs/ocelot_defconfig
@@ -41,8 +41,6 @@ CONFIG_MOMENCO_OCELOT=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -137,6 +135,15 @@ CONFIG_FLATMEM=y
137CONFIG_FLAT_NODE_MEM_MAP=y 135CONFIG_FLAT_NODE_MEM_MAP=y
138# CONFIG_SPARSEMEM_STATIC is not set 136# CONFIG_SPARSEMEM_STATIC is not set
139CONFIG_SPLIT_PTLOCK_CPUS=4 137CONFIG_SPLIT_PTLOCK_CPUS=4
138# CONFIG_HZ_48 is not set
139# CONFIG_HZ_100 is not set
140# CONFIG_HZ_128 is not set
141# CONFIG_HZ_250 is not set
142# CONFIG_HZ_256 is not set
143CONFIG_HZ_1000=y
144# CONFIG_HZ_1024 is not set
145CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
146CONFIG_HZ=1000
140CONFIG_PREEMPT_NONE=y 147CONFIG_PREEMPT_NONE=y
141# CONFIG_PREEMPT_VOLUNTARY is not set 148# CONFIG_PREEMPT_VOLUNTARY is not set
142# CONFIG_PREEMPT is not set 149# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/ocelot_g_defconfig b/arch/mips/configs/ocelot_g_defconfig
index b48bdee2411f..c63b1ca8c8b3 100644
--- a/arch/mips/configs/ocelot_g_defconfig
+++ b/arch/mips/configs/ocelot_g_defconfig
@@ -41,8 +41,6 @@ CONFIG_MOMENCO_OCELOT_G=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -136,6 +134,15 @@ CONFIG_FLATMEM=y
136CONFIG_FLAT_NODE_MEM_MAP=y 134CONFIG_FLAT_NODE_MEM_MAP=y
137# CONFIG_SPARSEMEM_STATIC is not set 135# CONFIG_SPARSEMEM_STATIC is not set
138CONFIG_SPLIT_PTLOCK_CPUS=4 136CONFIG_SPLIT_PTLOCK_CPUS=4
137# CONFIG_HZ_48 is not set
138# CONFIG_HZ_100 is not set
139# CONFIG_HZ_128 is not set
140# CONFIG_HZ_250 is not set
141# CONFIG_HZ_256 is not set
142CONFIG_HZ_1000=y
143# CONFIG_HZ_1024 is not set
144CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
145CONFIG_HZ=1000
139CONFIG_PREEMPT_NONE=y 146CONFIG_PREEMPT_NONE=y
140# CONFIG_PREEMPT_VOLUNTARY is not set 147# CONFIG_PREEMPT_VOLUNTARY is not set
141# CONFIG_PREEMPT is not set 148# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig
index 01aac40634b4..6f5c7261e9de 100644
--- a/arch/mips/configs/pb1100_defconfig
+++ b/arch/mips/configs/pb1100_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS_PB1100=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -132,6 +130,15 @@ CONFIG_FLATMEM=y
132CONFIG_FLAT_NODE_MEM_MAP=y 130CONFIG_FLAT_NODE_MEM_MAP=y
133# CONFIG_SPARSEMEM_STATIC is not set 131# CONFIG_SPARSEMEM_STATIC is not set
134CONFIG_SPLIT_PTLOCK_CPUS=4 132CONFIG_SPLIT_PTLOCK_CPUS=4
133# CONFIG_HZ_48 is not set
134# CONFIG_HZ_100 is not set
135# CONFIG_HZ_128 is not set
136# CONFIG_HZ_250 is not set
137# CONFIG_HZ_256 is not set
138CONFIG_HZ_1000=y
139# CONFIG_HZ_1024 is not set
140CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
141CONFIG_HZ=1000
135CONFIG_PREEMPT_NONE=y 142CONFIG_PREEMPT_NONE=y
136# CONFIG_PREEMPT_VOLUNTARY is not set 143# CONFIG_PREEMPT_VOLUNTARY is not set
137# CONFIG_PREEMPT is not set 144# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig
index 398c3c265b9f..5676f3747fd5 100644
--- a/arch/mips/configs/pb1500_defconfig
+++ b/arch/mips/configs/pb1500_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS_PB1500=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -131,6 +129,15 @@ CONFIG_FLATMEM=y
131CONFIG_FLAT_NODE_MEM_MAP=y 129CONFIG_FLAT_NODE_MEM_MAP=y
132# CONFIG_SPARSEMEM_STATIC is not set 130# CONFIG_SPARSEMEM_STATIC is not set
133CONFIG_SPLIT_PTLOCK_CPUS=4 131CONFIG_SPLIT_PTLOCK_CPUS=4
132# CONFIG_HZ_48 is not set
133# CONFIG_HZ_100 is not set
134# CONFIG_HZ_128 is not set
135# CONFIG_HZ_250 is not set
136# CONFIG_HZ_256 is not set
137CONFIG_HZ_1000=y
138# CONFIG_HZ_1024 is not set
139CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
140CONFIG_HZ=1000
134CONFIG_PREEMPT_NONE=y 141CONFIG_PREEMPT_NONE=y
135# CONFIG_PREEMPT_VOLUNTARY is not set 142# CONFIG_PREEMPT_VOLUNTARY is not set
136# CONFIG_PREEMPT is not set 143# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig
index ea282a53bb66..a1c479fa613b 100644
--- a/arch/mips/configs/pb1550_defconfig
+++ b/arch/mips/configs/pb1550_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS_PB1550=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -131,6 +129,15 @@ CONFIG_FLATMEM=y
131CONFIG_FLAT_NODE_MEM_MAP=y 129CONFIG_FLAT_NODE_MEM_MAP=y
132# CONFIG_SPARSEMEM_STATIC is not set 130# CONFIG_SPARSEMEM_STATIC is not set
133CONFIG_SPLIT_PTLOCK_CPUS=4 131CONFIG_SPLIT_PTLOCK_CPUS=4
132# CONFIG_HZ_48 is not set
133# CONFIG_HZ_100 is not set
134# CONFIG_HZ_128 is not set
135# CONFIG_HZ_250 is not set
136# CONFIG_HZ_256 is not set
137CONFIG_HZ_1000=y
138# CONFIG_HZ_1024 is not set
139CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
140CONFIG_HZ=1000
134CONFIG_PREEMPT_NONE=y 141CONFIG_PREEMPT_NONE=y
135# CONFIG_PREEMPT_VOLUNTARY is not set 142# CONFIG_PREEMPT_VOLUNTARY is not set
136# CONFIG_PREEMPT is not set 143# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig
index 4c57e564db0b..b2d991b80309 100644
--- a/arch/mips/configs/pnx8550-jbs_defconfig
+++ b/arch/mips/configs/pnx8550-jbs_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43CONFIG_PNX8550_JBS=y 43CONFIG_PNX8550_JBS=y
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -130,6 +128,15 @@ CONFIG_FLATMEM=y
130CONFIG_FLAT_NODE_MEM_MAP=y 128CONFIG_FLAT_NODE_MEM_MAP=y
131# CONFIG_SPARSEMEM_STATIC is not set 129# CONFIG_SPARSEMEM_STATIC is not set
132CONFIG_SPLIT_PTLOCK_CPUS=4 130CONFIG_SPLIT_PTLOCK_CPUS=4
131# CONFIG_HZ_48 is not set
132# CONFIG_HZ_100 is not set
133# CONFIG_HZ_128 is not set
134# CONFIG_HZ_250 is not set
135# CONFIG_HZ_256 is not set
136CONFIG_HZ_1000=y
137# CONFIG_HZ_1024 is not set
138CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
139CONFIG_HZ=1000
133CONFIG_PREEMPT_NONE=y 140CONFIG_PREEMPT_NONE=y
134# CONFIG_PREEMPT_VOLUNTARY is not set 141# CONFIG_PREEMPT_VOLUNTARY is not set
135# CONFIG_PREEMPT is not set 142# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/pnx8550-v2pci_defconfig b/arch/mips/configs/pnx8550-v2pci_defconfig
index 3c8f35162fec..fe092ac92e89 100644
--- a/arch/mips/configs/pnx8550-v2pci_defconfig
+++ b/arch/mips/configs/pnx8550-v2pci_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42CONFIG_PNX8550_V2PCI=y 42CONFIG_PNX8550_V2PCI=y
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -130,6 +128,15 @@ CONFIG_FLATMEM=y
130CONFIG_FLAT_NODE_MEM_MAP=y 128CONFIG_FLAT_NODE_MEM_MAP=y
131# CONFIG_SPARSEMEM_STATIC is not set 129# CONFIG_SPARSEMEM_STATIC is not set
132CONFIG_SPLIT_PTLOCK_CPUS=4 130CONFIG_SPLIT_PTLOCK_CPUS=4
131# CONFIG_HZ_48 is not set
132# CONFIG_HZ_100 is not set
133# CONFIG_HZ_128 is not set
134# CONFIG_HZ_250 is not set
135# CONFIG_HZ_256 is not set
136CONFIG_HZ_1000=y
137# CONFIG_HZ_1024 is not set
138CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
139CONFIG_HZ=1000
133CONFIG_PREEMPT_NONE=y 140CONFIG_PREEMPT_NONE=y
134# CONFIG_PREEMPT_VOLUNTARY is not set 141# CONFIG_PREEMPT_VOLUNTARY is not set
135# CONFIG_PREEMPT is not set 142# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/qemu_defconfig b/arch/mips/configs/qemu_defconfig
index 4bcc01dea041..db8701344cee 100644
--- a/arch/mips/configs/qemu_defconfig
+++ b/arch/mips/configs/qemu_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -128,6 +126,15 @@ CONFIG_FLAT_NODE_MEM_MAP=y
128# CONFIG_SPARSEMEM_STATIC is not set 126# CONFIG_SPARSEMEM_STATIC is not set
129CONFIG_SPLIT_PTLOCK_CPUS=4 127CONFIG_SPLIT_PTLOCK_CPUS=4
130# CONFIG_SMP is not set 128# CONFIG_SMP is not set
129# CONFIG_HZ_48 is not set
130CONFIG_HZ_100=y
131# CONFIG_HZ_128 is not set
132# CONFIG_HZ_250 is not set
133# CONFIG_HZ_256 is not set
134# CONFIG_HZ_1000 is not set
135# CONFIG_HZ_1024 is not set
136CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
137CONFIG_HZ=100
131CONFIG_PREEMPT_NONE=y 138CONFIG_PREEMPT_NONE=y
132# CONFIG_PREEMPT_VOLUNTARY is not set 139# CONFIG_PREEMPT_VOLUNTARY is not set
133# CONFIG_PREEMPT is not set 140# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/rbhma4500_defconfig b/arch/mips/configs/rbhma4500_defconfig
index 3d441932e43a..b16731f3684b 100644
--- a/arch/mips/configs/rbhma4500_defconfig
+++ b/arch/mips/configs/rbhma4500_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -138,6 +136,15 @@ CONFIG_FLATMEM=y
138CONFIG_FLAT_NODE_MEM_MAP=y 136CONFIG_FLAT_NODE_MEM_MAP=y
139# CONFIG_SPARSEMEM_STATIC is not set 137# CONFIG_SPARSEMEM_STATIC is not set
140CONFIG_SPLIT_PTLOCK_CPUS=4 138CONFIG_SPLIT_PTLOCK_CPUS=4
139# CONFIG_HZ_48 is not set
140# CONFIG_HZ_100 is not set
141# CONFIG_HZ_128 is not set
142# CONFIG_HZ_250 is not set
143# CONFIG_HZ_256 is not set
144CONFIG_HZ_1000=y
145# CONFIG_HZ_1024 is not set
146CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
147CONFIG_HZ=1000
141CONFIG_PREEMPT_NONE=y 148CONFIG_PREEMPT_NONE=y
142# CONFIG_PREEMPT_VOLUNTARY is not set 149# CONFIG_PREEMPT_VOLUNTARY is not set
143# CONFIG_PREEMPT is not set 150# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig
index edfb9679a25a..8b0dd8651264 100644
--- a/arch/mips/configs/rm200_defconfig
+++ b/arch/mips/configs/rm200_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -138,6 +136,15 @@ CONFIG_FLATMEM=y
138CONFIG_FLAT_NODE_MEM_MAP=y 136CONFIG_FLAT_NODE_MEM_MAP=y
139# CONFIG_SPARSEMEM_STATIC is not set 137# CONFIG_SPARSEMEM_STATIC is not set
140CONFIG_SPLIT_PTLOCK_CPUS=4 138CONFIG_SPLIT_PTLOCK_CPUS=4
139# CONFIG_HZ_48 is not set
140# CONFIG_HZ_100 is not set
141# CONFIG_HZ_128 is not set
142# CONFIG_HZ_250 is not set
143# CONFIG_HZ_256 is not set
144CONFIG_HZ_1000=y
145# CONFIG_HZ_1024 is not set
146CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
147CONFIG_HZ=1000
141# CONFIG_PREEMPT_NONE is not set 148# CONFIG_PREEMPT_NONE is not set
142CONFIG_PREEMPT_VOLUNTARY=y 149CONFIG_PREEMPT_VOLUNTARY=y
143# CONFIG_PREEMPT is not set 150# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig
index e388a3dae0a9..ff34ed66fe65 100644
--- a/arch/mips/configs/sb1250-swarm_defconfig
+++ b/arch/mips/configs/sb1250-swarm_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -149,6 +147,15 @@ CONFIG_FLATMEM=y
149CONFIG_FLAT_NODE_MEM_MAP=y 147CONFIG_FLAT_NODE_MEM_MAP=y
150# CONFIG_SPARSEMEM_STATIC is not set 148# CONFIG_SPARSEMEM_STATIC is not set
151CONFIG_SPLIT_PTLOCK_CPUS=4 149CONFIG_SPLIT_PTLOCK_CPUS=4
150# CONFIG_HZ_48 is not set
151# CONFIG_HZ_100 is not set
152# CONFIG_HZ_128 is not set
153# CONFIG_HZ_250 is not set
154# CONFIG_HZ_256 is not set
155CONFIG_HZ_1000=y
156# CONFIG_HZ_1024 is not set
157CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
158CONFIG_HZ=1000
152CONFIG_SMP=y 159CONFIG_SMP=y
153CONFIG_NR_CPUS=2 160CONFIG_NR_CPUS=2
154CONFIG_PREEMPT_NONE=y 161CONFIG_PREEMPT_NONE=y
diff --git a/arch/mips/configs/sead_defconfig b/arch/mips/configs/sead_defconfig
index 6b8a6a416a25..77edeae7f018 100644
--- a/arch/mips/configs/sead_defconfig
+++ b/arch/mips/configs/sead_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS_SEAD=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -134,6 +132,15 @@ CONFIG_FLATMEM=y
134CONFIG_FLAT_NODE_MEM_MAP=y 132CONFIG_FLAT_NODE_MEM_MAP=y
135# CONFIG_SPARSEMEM_STATIC is not set 133# CONFIG_SPARSEMEM_STATIC is not set
136CONFIG_SPLIT_PTLOCK_CPUS=4 134CONFIG_SPLIT_PTLOCK_CPUS=4
135# CONFIG_HZ_48 is not set
136# CONFIG_HZ_100 is not set
137# CONFIG_HZ_128 is not set
138# CONFIG_HZ_250 is not set
139# CONFIG_HZ_256 is not set
140CONFIG_HZ_1000=y
141# CONFIG_HZ_1024 is not set
142CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
143CONFIG_HZ=1000
137CONFIG_PREEMPT_NONE=y 144CONFIG_PREEMPT_NONE=y
138# CONFIG_PREEMPT_VOLUNTARY is not set 145# CONFIG_PREEMPT_VOLUNTARY is not set
139# CONFIG_PREEMPT is not set 146# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig
index dba0bdcdcf29..6aa229d54851 100644
--- a/arch/mips/configs/tb0226_defconfig
+++ b/arch/mips/configs/tb0226_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47CONFIG_MACH_VR41XX=y 45CONFIG_MACH_VR41XX=y
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -134,6 +132,15 @@ CONFIG_FLATMEM=y
134CONFIG_FLAT_NODE_MEM_MAP=y 132CONFIG_FLAT_NODE_MEM_MAP=y
135# CONFIG_SPARSEMEM_STATIC is not set 133# CONFIG_SPARSEMEM_STATIC is not set
136CONFIG_SPLIT_PTLOCK_CPUS=4 134CONFIG_SPLIT_PTLOCK_CPUS=4
135# CONFIG_HZ_48 is not set
136# CONFIG_HZ_100 is not set
137# CONFIG_HZ_128 is not set
138# CONFIG_HZ_250 is not set
139# CONFIG_HZ_256 is not set
140CONFIG_HZ_1000=y
141# CONFIG_HZ_1024 is not set
142CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
143CONFIG_HZ=1000
137CONFIG_PREEMPT_NONE=y 144CONFIG_PREEMPT_NONE=y
138# CONFIG_PREEMPT_VOLUNTARY is not set 145# CONFIG_PREEMPT_VOLUNTARY is not set
139# CONFIG_PREEMPT is not set 146# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/tb0229_defconfig b/arch/mips/configs/tb0229_defconfig
index 5a924c1a5803..a187b1f0004c 100644
--- a/arch/mips/configs/tb0229_defconfig
+++ b/arch/mips/configs/tb0229_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47CONFIG_MACH_VR41XX=y 45CONFIG_MACH_VR41XX=y
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -134,6 +132,15 @@ CONFIG_FLATMEM=y
134CONFIG_FLAT_NODE_MEM_MAP=y 132CONFIG_FLAT_NODE_MEM_MAP=y
135# CONFIG_SPARSEMEM_STATIC is not set 133# CONFIG_SPARSEMEM_STATIC is not set
136CONFIG_SPLIT_PTLOCK_CPUS=4 134CONFIG_SPLIT_PTLOCK_CPUS=4
135# CONFIG_HZ_48 is not set
136# CONFIG_HZ_100 is not set
137# CONFIG_HZ_128 is not set
138# CONFIG_HZ_250 is not set
139# CONFIG_HZ_256 is not set
140CONFIG_HZ_1000=y
141# CONFIG_HZ_1024 is not set
142CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
143CONFIG_HZ=1000
137CONFIG_PREEMPT_NONE=y 144CONFIG_PREEMPT_NONE=y
138# CONFIG_PREEMPT_VOLUNTARY is not set 145# CONFIG_PREEMPT_VOLUNTARY is not set
139# CONFIG_PREEMPT is not set 146# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/tb0287_defconfig b/arch/mips/configs/tb0287_defconfig
index 9f215ea350dc..258457fcbe11 100644
--- a/arch/mips/configs/tb0287_defconfig
+++ b/arch/mips/configs/tb0287_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47CONFIG_MACH_VR41XX=y 45CONFIG_MACH_VR41XX=y
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -135,6 +133,15 @@ CONFIG_FLATMEM=y
135CONFIG_FLAT_NODE_MEM_MAP=y 133CONFIG_FLAT_NODE_MEM_MAP=y
136# CONFIG_SPARSEMEM_STATIC is not set 134# CONFIG_SPARSEMEM_STATIC is not set
137CONFIG_SPLIT_PTLOCK_CPUS=4 135CONFIG_SPLIT_PTLOCK_CPUS=4
136# CONFIG_HZ_48 is not set
137# CONFIG_HZ_100 is not set
138# CONFIG_HZ_128 is not set
139# CONFIG_HZ_250 is not set
140# CONFIG_HZ_256 is not set
141CONFIG_HZ_1000=y
142# CONFIG_HZ_1024 is not set
143CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
144CONFIG_HZ=1000
138CONFIG_PREEMPT_NONE=y 145CONFIG_PREEMPT_NONE=y
139# CONFIG_PREEMPT_VOLUNTARY is not set 146# CONFIG_PREEMPT_VOLUNTARY is not set
140# CONFIG_PREEMPT is not set 147# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/workpad_defconfig b/arch/mips/configs/workpad_defconfig
index ac7765eb8da7..68af54f746e1 100644
--- a/arch/mips/configs/workpad_defconfig
+++ b/arch/mips/configs/workpad_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47CONFIG_MACH_VR41XX=y 45CONFIG_MACH_VR41XX=y
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -130,6 +128,15 @@ CONFIG_FLATMEM=y
130CONFIG_FLAT_NODE_MEM_MAP=y 128CONFIG_FLAT_NODE_MEM_MAP=y
131# CONFIG_SPARSEMEM_STATIC is not set 129# CONFIG_SPARSEMEM_STATIC is not set
132CONFIG_SPLIT_PTLOCK_CPUS=4 130CONFIG_SPLIT_PTLOCK_CPUS=4
131# CONFIG_HZ_48 is not set
132# CONFIG_HZ_100 is not set
133# CONFIG_HZ_128 is not set
134# CONFIG_HZ_250 is not set
135# CONFIG_HZ_256 is not set
136CONFIG_HZ_1000=y
137# CONFIG_HZ_1024 is not set
138CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
139CONFIG_HZ=1000
133CONFIG_PREEMPT_NONE=y 140CONFIG_PREEMPT_NONE=y
134# CONFIG_PREEMPT_VOLUNTARY is not set 141# CONFIG_PREEMPT_VOLUNTARY is not set
135# CONFIG_PREEMPT is not set 142# CONFIG_PREEMPT is not set
diff --git a/arch/mips/configs/ddb5476_defconfig b/arch/mips/configs/wrppmc_defconfig
index 8d88ac1bbfeb..40572a3c8cac 100644
--- a/arch/mips/configs/ddb5476_defconfig
+++ b/arch/mips/configs/wrppmc_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.17-rc2 3# Linux kernel version: 2.6.16.11
4# Mon Apr 24 14:51:00 2006 4# Fri May 5 17:11:22 2006
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7 7
@@ -32,6 +32,7 @@ CONFIG_MIPS=y
32# CONFIG_MIPS_ATLAS is not set 32# CONFIG_MIPS_ATLAS is not set
33# CONFIG_MIPS_MALTA is not set 33# CONFIG_MIPS_MALTA is not set
34# CONFIG_MIPS_SEAD is not set 34# CONFIG_MIPS_SEAD is not set
35CONFIG_WR_PPMC=y
35# CONFIG_MIPS_SIM is not set 36# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set 37# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 38# CONFIG_MOMENCO_OCELOT is not set
@@ -41,8 +42,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 42# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 43# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 44# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45CONFIG_DDB5476=y
46# CONFIG_DDB5477 is not set 45# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 46# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 47# CONFIG_PMC_YOSEMITE is not set
@@ -64,24 +63,23 @@ CONFIG_DDB5476=y
64# CONFIG_TOSHIBA_RBTX4927 is not set 63# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 64# CONFIG_TOSHIBA_RBTX4938 is not set
66CONFIG_RWSEM_GENERIC_SPINLOCK=y 65CONFIG_RWSEM_GENERIC_SPINLOCK=y
67CONFIG_GENERIC_FIND_NEXT_BIT=y
68CONFIG_GENERIC_HWEIGHT=y
69CONFIG_GENERIC_CALIBRATE_DELAY=y 66CONFIG_GENERIC_CALIBRATE_DELAY=y
70CONFIG_DMA_NONCOHERENT=y 67CONFIG_DMA_NONCOHERENT=y
71CONFIG_DMA_NEED_PCI_MAP_STATE=y 68CONFIG_DMA_NEED_PCI_MAP_STATE=y
72CONFIG_I8259=y 69CONFIG_CPU_BIG_ENDIAN=y
73# CONFIG_CPU_BIG_ENDIAN is not set 70# CONFIG_CPU_LITTLE_ENDIAN is not set
74CONFIG_CPU_LITTLE_ENDIAN=y 71CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
75CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y 72CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
76CONFIG_IRQ_CPU=y 73CONFIG_IRQ_CPU=y
77CONFIG_DDB5XXX_COMMON=y 74CONFIG_MIPS_GT64120=y
75CONFIG_SWAP_IO_SPACE=y
76CONFIG_BOOT_ELF32=y
78CONFIG_MIPS_L1_CACHE_SHIFT=5 77CONFIG_MIPS_L1_CACHE_SHIFT=5
79CONFIG_HAVE_STD_PC_SERIAL_PORT=y
80 78
81# 79#
82# CPU selection 80# CPU selection
83# 81#
84# CONFIG_CPU_MIPS32_R1 is not set 82CONFIG_CPU_MIPS32_R1=y
85# CONFIG_CPU_MIPS32_R2 is not set 83# CONFIG_CPU_MIPS32_R2 is not set
86# CONFIG_CPU_MIPS64_R1 is not set 84# CONFIG_CPU_MIPS64_R1 is not set
87# CONFIG_CPU_MIPS64_R2 is not set 85# CONFIG_CPU_MIPS64_R2 is not set
@@ -92,7 +90,7 @@ CONFIG_HAVE_STD_PC_SERIAL_PORT=y
92# CONFIG_CPU_R4X00 is not set 90# CONFIG_CPU_R4X00 is not set
93# CONFIG_CPU_TX49XX is not set 91# CONFIG_CPU_TX49XX is not set
94# CONFIG_CPU_R5000 is not set 92# CONFIG_CPU_R5000 is not set
95CONFIG_CPU_R5432=y 93# CONFIG_CPU_R5432 is not set
96# CONFIG_CPU_R6000 is not set 94# CONFIG_CPU_R6000 is not set
97# CONFIG_CPU_NEVADA is not set 95# CONFIG_CPU_NEVADA is not set
98# CONFIG_CPU_R8000 is not set 96# CONFIG_CPU_R8000 is not set
@@ -100,11 +98,16 @@ CONFIG_CPU_R5432=y
100# CONFIG_CPU_RM7000 is not set 98# CONFIG_CPU_RM7000 is not set
101# CONFIG_CPU_RM9000 is not set 99# CONFIG_CPU_RM9000 is not set
102# CONFIG_CPU_SB1 is not set 100# CONFIG_CPU_SB1 is not set
103CONFIG_SYS_HAS_CPU_R5432=y 101CONFIG_SYS_HAS_CPU_MIPS32_R1=y
102CONFIG_SYS_HAS_CPU_MIPS32_R2=y
103CONFIG_SYS_HAS_CPU_MIPS64_R1=y
104CONFIG_SYS_HAS_CPU_NEVADA=y
105CONFIG_SYS_HAS_CPU_RM7000=y
106CONFIG_CPU_MIPS32=y
107CONFIG_CPU_MIPSR1=y
104CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y 108CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
105CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y 109CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
106CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y 110CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
107CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
108 111
109# 112#
110# Kernel type 113# Kernel type
@@ -115,11 +118,15 @@ CONFIG_PAGE_SIZE_4KB=y
115# CONFIG_PAGE_SIZE_8KB is not set 118# CONFIG_PAGE_SIZE_8KB is not set
116# CONFIG_PAGE_SIZE_16KB is not set 119# CONFIG_PAGE_SIZE_16KB is not set
117# CONFIG_PAGE_SIZE_64KB is not set 120# CONFIG_PAGE_SIZE_64KB is not set
121CONFIG_CPU_HAS_PREFETCH=y
118# CONFIG_MIPS_MT is not set 122# CONFIG_MIPS_MT is not set
123# CONFIG_64BIT_PHYS_ADDR is not set
124# CONFIG_CPU_ADVANCED is not set
119CONFIG_CPU_HAS_LLSC=y 125CONFIG_CPU_HAS_LLSC=y
120CONFIG_CPU_HAS_SYNC=y 126CONFIG_CPU_HAS_SYNC=y
121CONFIG_GENERIC_HARDIRQS=y 127CONFIG_GENERIC_HARDIRQS=y
122CONFIG_GENERIC_IRQ_PROBE=y 128CONFIG_GENERIC_IRQ_PROBE=y
129CONFIG_CPU_SUPPORTS_HIGHMEM=y
123CONFIG_ARCH_FLATMEM_ENABLE=y 130CONFIG_ARCH_FLATMEM_ENABLE=y
124CONFIG_SELECT_MEMORY_MODEL=y 131CONFIG_SELECT_MEMORY_MODEL=y
125CONFIG_FLATMEM_MANUAL=y 132CONFIG_FLATMEM_MANUAL=y
@@ -129,6 +136,15 @@ CONFIG_FLATMEM=y
129CONFIG_FLAT_NODE_MEM_MAP=y 136CONFIG_FLAT_NODE_MEM_MAP=y
130# CONFIG_SPARSEMEM_STATIC is not set 137# CONFIG_SPARSEMEM_STATIC is not set
131CONFIG_SPLIT_PTLOCK_CPUS=4 138CONFIG_SPLIT_PTLOCK_CPUS=4
139# CONFIG_HZ_48 is not set
140# CONFIG_HZ_100 is not set
141# CONFIG_HZ_128 is not set
142# CONFIG_HZ_250 is not set
143# CONFIG_HZ_256 is not set
144CONFIG_HZ_1000=y
145# CONFIG_HZ_1024 is not set
146CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
147CONFIG_HZ=1000
132CONFIG_PREEMPT_NONE=y 148CONFIG_PREEMPT_NONE=y
133# CONFIG_PREEMPT_VOLUNTARY is not set 149# CONFIG_PREEMPT_VOLUNTARY is not set
134# CONFIG_PREEMPT is not set 150# CONFIG_PREEMPT is not set
@@ -145,27 +161,31 @@ CONFIG_INIT_ENV_ARG_LIMIT=32
145# 161#
146CONFIG_LOCALVERSION="" 162CONFIG_LOCALVERSION=""
147CONFIG_LOCALVERSION_AUTO=y 163CONFIG_LOCALVERSION_AUTO=y
148CONFIG_SWAP=y 164# CONFIG_SWAP is not set
149CONFIG_SYSVIPC=y 165CONFIG_SYSVIPC=y
150# CONFIG_POSIX_MQUEUE is not set 166# CONFIG_POSIX_MQUEUE is not set
151# CONFIG_BSD_PROCESS_ACCT is not set 167CONFIG_BSD_PROCESS_ACCT=y
168# CONFIG_BSD_PROCESS_ACCT_V3 is not set
152CONFIG_SYSCTL=y 169CONFIG_SYSCTL=y
153# CONFIG_AUDIT is not set 170# CONFIG_AUDIT is not set
154# CONFIG_IKCONFIG is not set 171# CONFIG_IKCONFIG is not set
155CONFIG_RELAY=y
156CONFIG_INITRAMFS_SOURCE="" 172CONFIG_INITRAMFS_SOURCE=""
157# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 173# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
158CONFIG_EMBEDDED=y 174CONFIG_EMBEDDED=y
159CONFIG_KALLSYMS=y 175CONFIG_KALLSYMS=y
160# CONFIG_KALLSYMS_EXTRA_PASS is not set 176CONFIG_KALLSYMS_EXTRA_PASS=y
161CONFIG_HOTPLUG=y 177CONFIG_HOTPLUG=y
162CONFIG_PRINTK=y 178CONFIG_PRINTK=y
163CONFIG_BUG=y 179CONFIG_BUG=y
164CONFIG_ELF_CORE=y 180CONFIG_ELF_CORE=y
165CONFIG_BASE_FULL=y 181CONFIG_BASE_FULL=y
166CONFIG_FUTEX=y 182CONFIG_FUTEX=y
167CONFIG_EPOLL=y 183# CONFIG_EPOLL is not set
168CONFIG_SHMEM=y 184CONFIG_SHMEM=y
185CONFIG_CC_ALIGN_FUNCTIONS=0
186CONFIG_CC_ALIGN_LABELS=0
187CONFIG_CC_ALIGN_LOOPS=0
188CONFIG_CC_ALIGN_JUMPS=0
169CONFIG_SLAB=y 189CONFIG_SLAB=y
170# CONFIG_TINY_SHMEM is not set 190# CONFIG_TINY_SHMEM is not set
171CONFIG_BASE_SMALL=0 191CONFIG_BASE_SMALL=0
@@ -174,14 +194,18 @@ CONFIG_BASE_SMALL=0
174# 194#
175# Loadable module support 195# Loadable module support
176# 196#
177# CONFIG_MODULES is not set 197CONFIG_MODULES=y
198CONFIG_MODULE_UNLOAD=y
199# CONFIG_MODULE_FORCE_UNLOAD is not set
200CONFIG_OBSOLETE_MODPARM=y
201CONFIG_MODVERSIONS=y
202CONFIG_MODULE_SRCVERSION_ALL=y
203# CONFIG_KMOD is not set
178 204
179# 205#
180# Block layer 206# Block layer
181# 207#
182# CONFIG_LBD is not set 208# CONFIG_LBD is not set
183# CONFIG_BLK_DEV_IO_TRACE is not set
184# CONFIG_LSF is not set
185 209
186# 210#
187# IO Schedulers 211# IO Schedulers
@@ -201,7 +225,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
201# 225#
202CONFIG_HW_HAS_PCI=y 226CONFIG_HW_HAS_PCI=y
203CONFIG_PCI=y 227CONFIG_PCI=y
204CONFIG_ISA=y 228CONFIG_PCI_LEGACY_PROC=y
205CONFIG_MMU=y 229CONFIG_MMU=y
206 230
207# 231#
@@ -212,13 +236,16 @@ CONFIG_MMU=y
212# 236#
213# PCI Hotplug Support 237# PCI Hotplug Support
214# 238#
215# CONFIG_HOTPLUG_PCI is not set 239CONFIG_HOTPLUG_PCI=y
240# CONFIG_HOTPLUG_PCI_FAKE is not set
241# CONFIG_HOTPLUG_PCI_CPCI is not set
242# CONFIG_HOTPLUG_PCI_SHPC is not set
216 243
217# 244#
218# Executable file formats 245# Executable file formats
219# 246#
220CONFIG_BINFMT_ELF=y 247CONFIG_BINFMT_ELF=y
221# CONFIG_BINFMT_MISC is not set 248CONFIG_BINFMT_MISC=y
222CONFIG_TRAD_SIGNALS=y 249CONFIG_TRAD_SIGNALS=y
223 250
224# 251#
@@ -231,35 +258,33 @@ CONFIG_NET=y
231# 258#
232# CONFIG_NETDEBUG is not set 259# CONFIG_NETDEBUG is not set
233CONFIG_PACKET=y 260CONFIG_PACKET=y
234# CONFIG_PACKET_MMAP is not set 261CONFIG_PACKET_MMAP=y
235CONFIG_UNIX=y 262CONFIG_UNIX=y
236CONFIG_XFRM=y 263# CONFIG_NET_KEY is not set
237CONFIG_XFRM_USER=y
238CONFIG_NET_KEY=y
239CONFIG_INET=y 264CONFIG_INET=y
240# CONFIG_IP_MULTICAST is not set 265CONFIG_IP_MULTICAST=y
241# CONFIG_IP_ADVANCED_ROUTER is not set 266# CONFIG_IP_ADVANCED_ROUTER is not set
242CONFIG_IP_FIB_HASH=y 267CONFIG_IP_FIB_HASH=y
243CONFIG_IP_PNP=y 268CONFIG_IP_PNP=y
244# CONFIG_IP_PNP_DHCP is not set 269CONFIG_IP_PNP_DHCP=y
245CONFIG_IP_PNP_BOOTP=y 270CONFIG_IP_PNP_BOOTP=y
246# CONFIG_IP_PNP_RARP is not set 271CONFIG_IP_PNP_RARP=y
247# CONFIG_NET_IPIP is not set 272# CONFIG_NET_IPIP is not set
248# CONFIG_NET_IPGRE is not set 273# CONFIG_NET_IPGRE is not set
249# CONFIG_ARPD is not set 274CONFIG_IP_MROUTE=y
275# CONFIG_IP_PIMSM_V1 is not set
276# CONFIG_IP_PIMSM_V2 is not set
277CONFIG_ARPD=y
250# CONFIG_SYN_COOKIES is not set 278# CONFIG_SYN_COOKIES is not set
251# CONFIG_INET_AH is not set 279# CONFIG_INET_AH is not set
252# CONFIG_INET_ESP is not set 280# CONFIG_INET_ESP is not set
253# CONFIG_INET_IPCOMP is not set 281# CONFIG_INET_IPCOMP is not set
254# CONFIG_INET_XFRM_TUNNEL is not set
255# CONFIG_INET_TUNNEL is not set 282# CONFIG_INET_TUNNEL is not set
256CONFIG_INET_DIAG=y 283CONFIG_INET_DIAG=y
257CONFIG_INET_TCP_DIAG=y 284CONFIG_INET_TCP_DIAG=y
258# CONFIG_TCP_CONG_ADVANCED is not set 285# CONFIG_TCP_CONG_ADVANCED is not set
259CONFIG_TCP_CONG_BIC=y 286CONFIG_TCP_CONG_BIC=y
260# CONFIG_IPV6 is not set 287# CONFIG_IPV6 is not set
261# CONFIG_INET6_XFRM_TUNNEL is not set
262# CONFIG_INET6_TUNNEL is not set
263# CONFIG_NETFILTER is not set 288# CONFIG_NETFILTER is not set
264 289
265# 290#
@@ -301,13 +326,7 @@ CONFIG_TCP_CONG_BIC=y
301# CONFIG_HAMRADIO is not set 326# CONFIG_HAMRADIO is not set
302# CONFIG_IRDA is not set 327# CONFIG_IRDA is not set
303# CONFIG_BT is not set 328# CONFIG_BT is not set
304CONFIG_IEEE80211=y 329# CONFIG_IEEE80211 is not set
305# CONFIG_IEEE80211_DEBUG is not set
306CONFIG_IEEE80211_CRYPT_WEP=y
307CONFIG_IEEE80211_CRYPT_CCMP=y
308CONFIG_IEEE80211_SOFTMAC=y
309# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
310CONFIG_WIRELESS_EXT=y
311 330
312# 331#
313# Device Drivers 332# Device Drivers
@@ -318,13 +337,12 @@ CONFIG_WIRELESS_EXT=y
318# 337#
319CONFIG_STANDALONE=y 338CONFIG_STANDALONE=y
320CONFIG_PREVENT_FIRMWARE_BUILD=y 339CONFIG_PREVENT_FIRMWARE_BUILD=y
321CONFIG_FW_LOADER=y 340# CONFIG_FW_LOADER is not set
322 341
323# 342#
324# Connector - unified userspace <-> kernelspace linker 343# Connector - unified userspace <-> kernelspace linker
325# 344#
326CONFIG_CONNECTOR=y 345# CONFIG_CONNECTOR is not set
327CONFIG_PROC_EVENTS=y
328 346
329# 347#
330# Memory Technology Devices (MTD) 348# Memory Technology Devices (MTD)
@@ -339,7 +357,6 @@ CONFIG_PROC_EVENTS=y
339# 357#
340# Plug and Play support 358# Plug and Play support
341# 359#
342# CONFIG_PNP is not set
343 360
344# 361#
345# Block devices 362# Block devices
@@ -352,53 +369,25 @@ CONFIG_PROC_EVENTS=y
352# CONFIG_BLK_DEV_LOOP is not set 369# CONFIG_BLK_DEV_LOOP is not set
353# CONFIG_BLK_DEV_NBD is not set 370# CONFIG_BLK_DEV_NBD is not set
354# CONFIG_BLK_DEV_SX8 is not set 371# CONFIG_BLK_DEV_SX8 is not set
355# CONFIG_BLK_DEV_RAM is not set 372CONFIG_BLK_DEV_RAM=y
356# CONFIG_BLK_DEV_INITRD is not set 373CONFIG_BLK_DEV_RAM_COUNT=16
357CONFIG_CDROM_PKTCDVD=y 374CONFIG_BLK_DEV_RAM_SIZE=4096
358CONFIG_CDROM_PKTCDVD_BUFFERS=8 375CONFIG_BLK_DEV_INITRD=y
359# CONFIG_CDROM_PKTCDVD_WCACHE is not set 376# CONFIG_CDROM_PKTCDVD is not set
360CONFIG_ATA_OVER_ETH=y 377# CONFIG_ATA_OVER_ETH is not set
361 378
362# 379#
363# ATA/ATAPI/MFM/RLL support 380# ATA/ATAPI/MFM/RLL support
364# 381#
365CONFIG_IDE=y 382# CONFIG_IDE is not set
366CONFIG_BLK_DEV_IDE=y
367
368#
369# Please see Documentation/ide.txt for help/info on IDE drives
370#
371# CONFIG_BLK_DEV_IDE_SATA is not set
372CONFIG_BLK_DEV_IDEDISK=y
373# CONFIG_IDEDISK_MULTI_MODE is not set
374# CONFIG_BLK_DEV_IDECD is not set
375# CONFIG_BLK_DEV_IDETAPE is not set
376# CONFIG_BLK_DEV_IDEFLOPPY is not set
377# CONFIG_IDE_TASK_IOCTL is not set
378
379#
380# IDE chipset support/bugfixes
381#
382CONFIG_IDE_GENERIC=y
383# CONFIG_BLK_DEV_IDEPCI is not set
384# CONFIG_IDE_ARM is not set
385# CONFIG_IDE_CHIPSETS is not set
386# CONFIG_BLK_DEV_IDEDMA is not set
387# CONFIG_IDEDMA_AUTO is not set
388# CONFIG_BLK_DEV_HD is not set
389 383
390# 384#
391# SCSI device support 385# SCSI device support
392# 386#
393CONFIG_RAID_ATTRS=y 387# CONFIG_RAID_ATTRS is not set
394# CONFIG_SCSI is not set 388# CONFIG_SCSI is not set
395 389
396# 390#
397# Old CD-ROM drivers (not SCSI, not IDE)
398#
399# CONFIG_CD_NO_IDESCSI is not set
400
401#
402# Multi-device support (RAID and LVM) 391# Multi-device support (RAID and LVM)
403# 392#
404# CONFIG_MD is not set 393# CONFIG_MD is not set
@@ -440,34 +429,48 @@ CONFIG_PHYLIB=y
440# 429#
441# MII PHY device drivers 430# MII PHY device drivers
442# 431#
443CONFIG_MARVELL_PHY=y 432# CONFIG_MARVELL_PHY is not set
444CONFIG_DAVICOM_PHY=y 433# CONFIG_DAVICOM_PHY is not set
445CONFIG_QSEMI_PHY=y 434# CONFIG_QSEMI_PHY is not set
446CONFIG_LXT_PHY=y 435# CONFIG_LXT_PHY is not set
447CONFIG_CICADA_PHY=y 436# CONFIG_CICADA_PHY is not set
448 437
449# 438#
450# Ethernet (10 or 100Mbit) 439# Ethernet (10 or 100Mbit)
451# 440#
452CONFIG_NET_ETHERNET=y 441CONFIG_NET_ETHERNET=y
453# CONFIG_MII is not set 442CONFIG_MII=y
454# CONFIG_HAPPYMEAL is not set 443# CONFIG_HAPPYMEAL is not set
455# CONFIG_SUNGEM is not set 444# CONFIG_SUNGEM is not set
456# CONFIG_CASSINI is not set 445# CONFIG_CASSINI is not set
457# CONFIG_NET_VENDOR_3COM is not set 446# CONFIG_NET_VENDOR_3COM is not set
458# CONFIG_NET_VENDOR_SMC is not set
459# CONFIG_DM9000 is not set 447# CONFIG_DM9000 is not set
460# CONFIG_NET_VENDOR_RACAL is not set
461 448
462# 449#
463# Tulip family network device support 450# Tulip family network device support
464# 451#
465# CONFIG_NET_TULIP is not set 452# CONFIG_NET_TULIP is not set
466# CONFIG_AT1700 is not set
467# CONFIG_DEPCA is not set
468# CONFIG_HP100 is not set 453# CONFIG_HP100 is not set
469# CONFIG_NET_ISA is not set 454CONFIG_NET_PCI=y
470# CONFIG_NET_PCI is not set 455# CONFIG_PCNET32 is not set
456# CONFIG_AMD8111_ETH is not set
457# CONFIG_ADAPTEC_STARFIRE is not set
458# CONFIG_B44 is not set
459# CONFIG_FORCEDETH is not set
460# CONFIG_DGRS is not set
461# CONFIG_EEPRO100 is not set
462CONFIG_E100=y
463# CONFIG_FEALNX is not set
464# CONFIG_NATSEMI is not set
465# CONFIG_NE2K_PCI is not set
466# CONFIG_8139CP is not set
467# CONFIG_8139TOO is not set
468# CONFIG_SIS900 is not set
469# CONFIG_EPIC100 is not set
470# CONFIG_SUNDANCE is not set
471# CONFIG_TLAN is not set
472# CONFIG_VIA_RHINE is not set
473# CONFIG_LAN_SAA9730 is not set
471 474
472# 475#
473# Ethernet (1000 Mbit) 476# Ethernet (1000 Mbit)
@@ -483,6 +486,7 @@ CONFIG_NET_ETHERNET=y
483# CONFIG_SKGE is not set 486# CONFIG_SKGE is not set
484# CONFIG_SKY2 is not set 487# CONFIG_SKY2 is not set
485# CONFIG_SK98LIN is not set 488# CONFIG_SK98LIN is not set
489# CONFIG_VIA_VELOCITY is not set
486# CONFIG_TIGON3 is not set 490# CONFIG_TIGON3 is not set
487# CONFIG_BNX2 is not set 491# CONFIG_BNX2 is not set
488 492
@@ -529,46 +533,18 @@ CONFIG_NET_ETHERNET=y
529# 533#
530# Input device support 534# Input device support
531# 535#
532CONFIG_INPUT=y 536# CONFIG_INPUT is not set
533
534#
535# Userland interfaces
536#
537CONFIG_INPUT_MOUSEDEV=y
538CONFIG_INPUT_MOUSEDEV_PSAUX=y
539CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
540CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
541# CONFIG_INPUT_JOYDEV is not set
542# CONFIG_INPUT_TSDEV is not set
543# CONFIG_INPUT_EVDEV is not set
544# CONFIG_INPUT_EVBUG is not set
545
546#
547# Input Device Drivers
548#
549# CONFIG_INPUT_KEYBOARD is not set
550# CONFIG_INPUT_MOUSE is not set
551# CONFIG_INPUT_JOYSTICK is not set
552# CONFIG_INPUT_TOUCHSCREEN is not set
553# CONFIG_INPUT_MISC is not set
554 537
555# 538#
556# Hardware I/O ports 539# Hardware I/O ports
557# 540#
558CONFIG_SERIO=y 541# CONFIG_SERIO is not set
559# CONFIG_SERIO_I8042 is not set
560CONFIG_SERIO_SERPORT=y
561# CONFIG_SERIO_PCIPS2 is not set
562# CONFIG_SERIO_LIBPS2 is not set
563CONFIG_SERIO_RAW=y
564# CONFIG_GAMEPORT is not set 542# CONFIG_GAMEPORT is not set
565 543
566# 544#
567# Character devices 545# Character devices
568# 546#
569CONFIG_VT=y 547# CONFIG_VT is not set
570CONFIG_VT_CONSOLE=y
571CONFIG_HW_CONSOLE=y
572# CONFIG_SERIAL_NONSTANDARD is not set 548# CONFIG_SERIAL_NONSTANDARD is not set
573 549
574# 550#
@@ -576,9 +552,8 @@ CONFIG_HW_CONSOLE=y
576# 552#
577CONFIG_SERIAL_8250=y 553CONFIG_SERIAL_8250=y
578CONFIG_SERIAL_8250_CONSOLE=y 554CONFIG_SERIAL_8250_CONSOLE=y
579CONFIG_SERIAL_8250_PCI=y 555CONFIG_SERIAL_8250_NR_UARTS=1
580CONFIG_SERIAL_8250_NR_UARTS=4 556CONFIG_SERIAL_8250_RUNTIME_UARTS=1
581CONFIG_SERIAL_8250_RUNTIME_UARTS=4
582# CONFIG_SERIAL_8250_EXTENDED is not set 557# CONFIG_SERIAL_8250_EXTENDED is not set
583 558
584# 559#
@@ -600,8 +575,7 @@ CONFIG_LEGACY_PTY_COUNT=256
600# Watchdog Cards 575# Watchdog Cards
601# 576#
602# CONFIG_WATCHDOG is not set 577# CONFIG_WATCHDOG is not set
603# CONFIG_RTC is not set 578CONFIG_RTC=y
604# CONFIG_GEN_RTC is not set
605# CONFIG_DTLK is not set 579# CONFIG_DTLK is not set
606# CONFIG_R3964 is not set 580# CONFIG_R3964 is not set
607# CONFIG_APPLICOM is not set 581# CONFIG_APPLICOM is not set
@@ -637,14 +611,20 @@ CONFIG_LEGACY_PTY_COUNT=256
637# 611#
638# Hardware Monitoring support 612# Hardware Monitoring support
639# 613#
640# CONFIG_HWMON is not set 614CONFIG_HWMON=y
641# CONFIG_HWMON_VID is not set 615# CONFIG_HWMON_VID is not set
616# CONFIG_SENSORS_F71805F is not set
617# CONFIG_HWMON_DEBUG_CHIP is not set
642 618
643# 619#
644# Misc devices 620# Misc devices
645# 621#
646 622
647# 623#
624# Multimedia Capabilities Port drivers
625#
626
627#
648# Multimedia devices 628# Multimedia devices
649# 629#
650# CONFIG_VIDEO_DEV is not set 630# CONFIG_VIDEO_DEV is not set
@@ -657,49 +637,7 @@ CONFIG_LEGACY_PTY_COUNT=256
657# 637#
658# Graphics support 638# Graphics support
659# 639#
660CONFIG_FB=y 640# CONFIG_FB is not set
661# CONFIG_FB_CFB_FILLRECT is not set
662# CONFIG_FB_CFB_COPYAREA is not set
663# CONFIG_FB_CFB_IMAGEBLIT is not set
664# CONFIG_FB_MACMODES is not set
665CONFIG_FB_FIRMWARE_EDID=y
666# CONFIG_FB_MODE_HELPERS is not set
667# CONFIG_FB_TILEBLITTING is not set
668# CONFIG_FB_CIRRUS is not set
669# CONFIG_FB_PM2 is not set
670# CONFIG_FB_CYBER2000 is not set
671# CONFIG_FB_ASILIANT is not set
672# CONFIG_FB_IMSTT is not set
673# CONFIG_FB_S1D13XXX is not set
674# CONFIG_FB_NVIDIA is not set
675# CONFIG_FB_RIVA is not set
676# CONFIG_FB_MATROX is not set
677# CONFIG_FB_RADEON is not set
678# CONFIG_FB_ATY128 is not set
679# CONFIG_FB_ATY is not set
680# CONFIG_FB_SAVAGE is not set
681# CONFIG_FB_SIS is not set
682# CONFIG_FB_NEOMAGIC is not set
683# CONFIG_FB_KYRO is not set
684# CONFIG_FB_3DFX is not set
685# CONFIG_FB_VOODOO1 is not set
686# CONFIG_FB_SMIVGX is not set
687# CONFIG_FB_TRIDENT is not set
688# CONFIG_FB_VIRTUAL is not set
689
690#
691# Console display driver support
692#
693# CONFIG_VGA_CONSOLE is not set
694# CONFIG_MDA_CONSOLE is not set
695CONFIG_DUMMY_CONSOLE=y
696# CONFIG_FRAMEBUFFER_CONSOLE is not set
697
698#
699# Logo configuration
700#
701# CONFIG_LOGO is not set
702# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
703 641
704# 642#
705# Sound 643# Sound
@@ -711,7 +649,6 @@ CONFIG_DUMMY_CONSOLE=y
711# 649#
712CONFIG_USB_ARCH_HAS_HCD=y 650CONFIG_USB_ARCH_HAS_HCD=y
713CONFIG_USB_ARCH_HAS_OHCI=y 651CONFIG_USB_ARCH_HAS_OHCI=y
714CONFIG_USB_ARCH_HAS_EHCI=y
715# CONFIG_USB is not set 652# CONFIG_USB is not set
716 653
717# 654#
@@ -729,19 +666,6 @@ CONFIG_USB_ARCH_HAS_EHCI=y
729# CONFIG_MMC is not set 666# CONFIG_MMC is not set
730 667
731# 668#
732# LED devices
733#
734# CONFIG_NEW_LEDS is not set
735
736#
737# LED drivers
738#
739
740#
741# LED Triggers
742#
743
744#
745# InfiniBand support 669# InfiniBand support
746# 670#
747# CONFIG_INFINIBAND is not set 671# CONFIG_INFINIBAND is not set
@@ -751,16 +675,9 @@ CONFIG_USB_ARCH_HAS_EHCI=y
751# 675#
752 676
753# 677#
754# Real Time Clock
755#
756# CONFIG_RTC_CLASS is not set
757
758#
759# File systems 678# File systems
760# 679#
761CONFIG_EXT2_FS=y 680# CONFIG_EXT2_FS is not set
762# CONFIG_EXT2_FS_XATTR is not set
763# CONFIG_EXT2_FS_XIP is not set
764# CONFIG_EXT3_FS is not set 681# CONFIG_EXT3_FS is not set
765# CONFIG_REISERFS_FS is not set 682# CONFIG_REISERFS_FS is not set
766# CONFIG_JFS_FS is not set 683# CONFIG_JFS_FS is not set
@@ -774,7 +691,7 @@ CONFIG_INOTIFY=y
774CONFIG_DNOTIFY=y 691CONFIG_DNOTIFY=y
775# CONFIG_AUTOFS_FS is not set 692# CONFIG_AUTOFS_FS is not set
776# CONFIG_AUTOFS4_FS is not set 693# CONFIG_AUTOFS4_FS is not set
777CONFIG_FUSE_FS=y 694# CONFIG_FUSE_FS is not set
778 695
779# 696#
780# CD-ROM/DVD Filesystems 697# CD-ROM/DVD Filesystems
@@ -795,9 +712,10 @@ CONFIG_FUSE_FS=y
795CONFIG_PROC_FS=y 712CONFIG_PROC_FS=y
796CONFIG_PROC_KCORE=y 713CONFIG_PROC_KCORE=y
797CONFIG_SYSFS=y 714CONFIG_SYSFS=y
798# CONFIG_TMPFS is not set 715CONFIG_TMPFS=y
799# CONFIG_HUGETLB_PAGE is not set 716# CONFIG_HUGETLB_PAGE is not set
800CONFIG_RAMFS=y 717CONFIG_RAMFS=y
718# CONFIG_RELAYFS_FS is not set
801# CONFIG_CONFIGFS_FS is not set 719# CONFIG_CONFIGFS_FS is not set
802 720
803# 721#
@@ -821,12 +739,14 @@ CONFIG_RAMFS=y
821# Network File Systems 739# Network File Systems
822# 740#
823CONFIG_NFS_FS=y 741CONFIG_NFS_FS=y
824# CONFIG_NFS_V3 is not set 742CONFIG_NFS_V3=y
743# CONFIG_NFS_V3_ACL is not set
825# CONFIG_NFS_V4 is not set 744# CONFIG_NFS_V4 is not set
826# CONFIG_NFS_DIRECTIO is not set 745# CONFIG_NFS_DIRECTIO is not set
827# CONFIG_NFSD is not set 746# CONFIG_NFSD is not set
828CONFIG_ROOT_NFS=y 747CONFIG_ROOT_NFS=y
829CONFIG_LOCKD=y 748CONFIG_LOCKD=y
749CONFIG_LOCKD_V4=y
830CONFIG_NFS_COMMON=y 750CONFIG_NFS_COMMON=y
831CONFIG_SUNRPC=y 751CONFIG_SUNRPC=y
832# CONFIG_RPCSEC_GSS_KRB5 is not set 752# CONFIG_RPCSEC_GSS_KRB5 is not set
@@ -861,46 +781,19 @@ CONFIG_MSDOS_PARTITION=y
861# CONFIG_MAGIC_SYSRQ is not set 781# CONFIG_MAGIC_SYSRQ is not set
862# CONFIG_DEBUG_KERNEL is not set 782# CONFIG_DEBUG_KERNEL is not set
863CONFIG_LOG_BUF_SHIFT=14 783CONFIG_LOG_BUF_SHIFT=14
864# CONFIG_DEBUG_FS is not set
865# CONFIG_UNWIND_INFO is not set
866CONFIG_CROSSCOMPILE=y 784CONFIG_CROSSCOMPILE=y
867CONFIG_CMDLINE="ip=any" 785CONFIG_CMDLINE="console=ttyS0,115200n8"
868 786
869# 787#
870# Security options 788# Security options
871# 789#
872CONFIG_KEYS=y 790# CONFIG_KEYS is not set
873CONFIG_KEYS_DEBUG_PROC_KEYS=y
874# CONFIG_SECURITY is not set 791# CONFIG_SECURITY is not set
875 792
876# 793#
877# Cryptographic options 794# Cryptographic options
878# 795#
879CONFIG_CRYPTO=y 796# CONFIG_CRYPTO is not set
880CONFIG_CRYPTO_HMAC=y
881CONFIG_CRYPTO_NULL=y
882CONFIG_CRYPTO_MD4=y
883CONFIG_CRYPTO_MD5=y
884CONFIG_CRYPTO_SHA1=y
885CONFIG_CRYPTO_SHA256=y
886CONFIG_CRYPTO_SHA512=y
887CONFIG_CRYPTO_WP512=y
888CONFIG_CRYPTO_TGR192=y
889CONFIG_CRYPTO_DES=y
890CONFIG_CRYPTO_BLOWFISH=y
891CONFIG_CRYPTO_TWOFISH=y
892CONFIG_CRYPTO_SERPENT=y
893CONFIG_CRYPTO_AES=y
894CONFIG_CRYPTO_CAST5=y
895CONFIG_CRYPTO_CAST6=y
896CONFIG_CRYPTO_TEA=y
897CONFIG_CRYPTO_ARC4=y
898CONFIG_CRYPTO_KHAZAD=y
899CONFIG_CRYPTO_ANUBIS=y
900CONFIG_CRYPTO_DEFLATE=y
901CONFIG_CRYPTO_MICHAEL_MIC=y
902CONFIG_CRYPTO_CRC32C=y
903# CONFIG_CRYPTO_TEST is not set
904 797
905# 798#
906# Hardware crypto devices 799# Hardware crypto devices
@@ -909,9 +802,7 @@ CONFIG_CRYPTO_CRC32C=y
909# 802#
910# Library routines 803# Library routines
911# 804#
912# CONFIG_CRC_CCITT is not set 805CONFIG_CRC_CCITT=y
913CONFIG_CRC16=y 806CONFIG_CRC16=y
914CONFIG_CRC32=y 807CONFIG_CRC32=y
915CONFIG_LIBCRC32C=y 808CONFIG_LIBCRC32C=y
916CONFIG_ZLIB_INFLATE=y
917CONFIG_ZLIB_DEFLATE=y
diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig
index b52d709de962..7ece2c008e9b 100644
--- a/arch/mips/configs/yosemite_defconfig
+++ b/arch/mips/configs/yosemite_defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48CONFIG_PMC_YOSEMITE=y 46CONFIG_PMC_YOSEMITE=y
@@ -130,6 +128,15 @@ CONFIG_FLATMEM=y
130CONFIG_FLAT_NODE_MEM_MAP=y 128CONFIG_FLAT_NODE_MEM_MAP=y
131# CONFIG_SPARSEMEM_STATIC is not set 129# CONFIG_SPARSEMEM_STATIC is not set
132CONFIG_SPLIT_PTLOCK_CPUS=4 130CONFIG_SPLIT_PTLOCK_CPUS=4
131# CONFIG_HZ_48 is not set
132# CONFIG_HZ_100 is not set
133# CONFIG_HZ_128 is not set
134# CONFIG_HZ_250 is not set
135# CONFIG_HZ_256 is not set
136CONFIG_HZ_1000=y
137# CONFIG_HZ_1024 is not set
138CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
139CONFIG_HZ=1000
133CONFIG_SMP=y 140CONFIG_SMP=y
134CONFIG_NR_CPUS=2 141CONFIG_NR_CPUS=2
135CONFIG_PREEMPT_NONE=y 142CONFIG_PREEMPT_NONE=y
diff --git a/arch/mips/ddb5xxx/common/prom.c b/arch/mips/ddb5xxx/common/prom.c
index b8d1f7489f3b..00c62c1c28a3 100644
--- a/arch/mips/ddb5xxx/common/prom.c
+++ b/arch/mips/ddb5xxx/common/prom.c
@@ -56,13 +56,7 @@ void __init prom_init(void)
56 56
57 mips_machgroup = MACH_GROUP_NEC_DDB; 57 mips_machgroup = MACH_GROUP_NEC_DDB;
58 58
59#if defined(CONFIG_DDB5074) 59#if defined(CONFIG_DDB5477)
60 mips_machtype = MACH_NEC_DDB5074;
61 add_memory_region(0, DDB_SDRAM_SIZE, BOOT_MEM_RAM);
62#elif defined(CONFIG_DDB5476)
63 mips_machtype = MACH_NEC_DDB5476;
64 add_memory_region(0, DDB_SDRAM_SIZE, BOOT_MEM_RAM);
65#elif defined(CONFIG_DDB5477)
66 ddb5477_runtime_detection(); 60 ddb5477_runtime_detection();
67 add_memory_region(0, board_ram_size, BOOT_MEM_RAM); 61 add_memory_region(0, board_ram_size, BOOT_MEM_RAM);
68#endif 62#endif
diff --git a/arch/mips/ddb5xxx/ddb5074/Makefile b/arch/mips/ddb5xxx/ddb5074/Makefile
deleted file mode 100644
index 304c02107b46..000000000000
--- a/arch/mips/ddb5xxx/ddb5074/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1#
2# Makefile for the NEC DDB Vrc-5074 specific kernel interface routines
3# under Linux.
4#
5
6obj-y += setup.o irq.o nile4_pic.o
7
8EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/ddb5xxx/ddb5074/irq.c b/arch/mips/ddb5xxx/ddb5074/irq.c
deleted file mode 100644
index 60c087b7738c..000000000000
--- a/arch/mips/ddb5xxx/ddb5074/irq.c
+++ /dev/null
@@ -1,169 +0,0 @@
1/*
2 * arch/mips/ddb5074/irq.c -- NEC DDB Vrc-5074 interrupt routines
3 *
4 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
5 * Sony Software Development Center Europe (SDCE), Brussels
6 */
7#include <linux/init.h>
8#include <linux/irq.h>
9#include <linux/signal.h>
10#include <linux/sched.h>
11#include <linux/types.h>
12#include <linux/interrupt.h>
13#include <linux/ioport.h>
14
15#include <asm/i8259.h>
16#include <asm/io.h>
17#include <asm/irq_cpu.h>
18#include <asm/ptrace.h>
19#include <asm/nile4.h>
20#include <asm/ddb5xxx/ddb5xxx.h>
21#include <asm/ddb5xxx/ddb5074.h>
22
23
24static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
25
26#define M1543_PNP_CONFIG 0x03f0 /* PnP Config Port */
27#define M1543_PNP_INDEX 0x03f0 /* PnP Index Port */
28#define M1543_PNP_DATA 0x03f1 /* PnP Data Port */
29
30#define M1543_PNP_ALT_CONFIG 0x0370 /* Alternative PnP Config Port */
31#define M1543_PNP_ALT_INDEX 0x0370 /* Alternative PnP Index Port */
32#define M1543_PNP_ALT_DATA 0x0371 /* Alternative PnP Data Port */
33
34#define M1543_INT1_MASTER_CTRL 0x0020 /* INT_1 (master) Control Register */
35#define M1543_INT1_MASTER_MASK 0x0021 /* INT_1 (master) Mask Register */
36
37#define M1543_INT1_SLAVE_CTRL 0x00a0 /* INT_1 (slave) Control Register */
38#define M1543_INT1_SLAVE_MASK 0x00a1 /* INT_1 (slave) Mask Register */
39
40#define M1543_INT1_MASTER_ELCR 0x04d0 /* INT_1 (master) Edge/Level Control */
41#define M1543_INT1_SLAVE_ELCR 0x04d1 /* INT_1 (slave) Edge/Level Control */
42
43
44static void m1543_irq_setup(void)
45{
46 /*
47 * The ALI M1543 has 13 interrupt inputs, IRQ1..IRQ13. Not all
48 * the possible IO sources in the M1543 are in use by us. We will
49 * use the following mapping:
50 *
51 * IRQ1 - keyboard (default set by M1543)
52 * IRQ3 - reserved for UART B (default set by M1543) (note that
53 * the schematics for the DDB Vrc-5074 board seem to
54 * indicate that IRQ3 is connected to the DS1386
55 * watchdog timer interrupt output so we might have
56 * a conflict)
57 * IRQ4 - reserved for UART A (default set by M1543)
58 * IRQ5 - parallel (default set by M1543)
59 * IRQ8 - DS1386 time of day (RTC) interrupt
60 * IRQ12 - mouse
61 */
62
63 /*
64 * Assing mouse interrupt to IRQ12
65 */
66
67 /* Enter configuration mode */
68 outb(0x51, M1543_PNP_CONFIG);
69 outb(0x23, M1543_PNP_CONFIG);
70
71 /* Select logical device 7 (Keyboard) */
72 outb(0x07, M1543_PNP_INDEX);
73 outb(0x07, M1543_PNP_DATA);
74
75 /* Select IRQ12 */
76 outb(0x72, M1543_PNP_INDEX);
77 outb(0x0c, M1543_PNP_DATA);
78
79 outb(0x30, M1543_PNP_INDEX);
80 printk("device 7, 0x30: %02x\n",inb(M1543_PNP_DATA));
81
82 outb(0x70, M1543_PNP_INDEX);
83 printk("device 7, 0x70: %02x\n",inb(M1543_PNP_DATA));
84
85 /* Leave configration mode */
86 outb(0xbb, M1543_PNP_CONFIG);
87
88
89}
90
91static void ddb_local0_irqdispatch(struct pt_regs *regs)
92{
93 u32 mask;
94 int nile4_irq;
95
96 mask = nile4_get_irq_stat(0);
97
98 /* Handle the timer interrupt first */
99#if 0
100 if (mask & (1 << NILE4_INT_GPT)) {
101 do_IRQ(nile4_to_irq(NILE4_INT_GPT), regs);
102 mask &= ~(1 << NILE4_INT_GPT);
103 }
104#endif
105 for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1)
106 if (mask & 1) {
107 if (nile4_irq == NILE4_INT_INTE) {
108 int i8259_irq;
109
110 nile4_clear_irq(NILE4_INT_INTE);
111 i8259_irq = nile4_i8259_iack();
112 do_IRQ(i8259_irq, regs);
113 } else
114 do_IRQ(nile4_to_irq(nile4_irq), regs);
115
116 }
117}
118
119static void ddb_local1_irqdispatch(void)
120{
121 printk("ddb_local1_irqdispatch called\n");
122}
123
124static void ddb_buserror_irq(void)
125{
126 printk("ddb_buserror_irq called\n");
127}
128
129static void ddb_8254timer_irq(void)
130{
131 printk("ddb_8254timer_irq called\n");
132}
133
134asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
135{
136 unsigned int pending = read_c0_cause() & read_c0_status();
137
138 if (pending & CAUSEF_IP2)
139 ddb_local0_irqdispatch(regs);
140 else if (pending & CAUSEF_IP3)
141 ddb_local1_irqdispatch();
142 else if (pending & CAUSEF_IP6)
143 ddb_buserror_irq();
144 else if (pending & (CAUSEF_IP4 | CAUSEF_IP5))
145 ddb_8254timer_irq();
146}
147
148void __init arch_init_irq(void)
149{
150 /* setup cascade interrupts */
151 setup_irq(NILE4_IRQ_BASE + NILE4_INT_INTE, &irq_cascade);
152 setup_irq(CPU_IRQ_BASE + CPU_NILE4_CASCADE, &irq_cascade);
153
154 nile4_irq_setup(NILE4_IRQ_BASE);
155 m1543_irq_setup();
156 init_i8259_irqs();
157
158
159 printk("CPU_IRQ_BASE: %d\n",CPU_IRQ_BASE);
160
161 mips_cpu_irq_init(CPU_IRQ_BASE);
162
163 printk("enabling 8259 cascade\n");
164
165 ddb5074_led_hex(0);
166
167 /* Enable the interrupt cascade */
168 nile4_enable_irq(NILE4_IRQ_BASE+IRQ_I8259_CASCADE);
169}
diff --git a/arch/mips/ddb5xxx/ddb5074/nile4_pic.c b/arch/mips/ddb5xxx/ddb5074/nile4_pic.c
deleted file mode 100644
index 8743ffce8653..000000000000
--- a/arch/mips/ddb5xxx/ddb5074/nile4_pic.c
+++ /dev/null
@@ -1,286 +0,0 @@
1/*
2 * arch/mips/ddb5476/nile4.c --
3 * low-level PIC code for NEC Vrc-5476 (Nile 4)
4 *
5 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
6 * Sony Software Development Center Europe (SDCE), Brussels
7 *
8 * Copyright 2001 MontaVista Software Inc.
9 * Author: jsun@mvista.com or jsun@junsun.net
10 *
11 */
12#include <linux/config.h>
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/ioport.h>
17
18#include <asm/addrspace.h>
19
20#include <asm/ddb5xxx/ddb5xxx.h>
21
22static int irq_base;
23
24/*
25 * Interrupt Programming
26 */
27void nile4_map_irq(int nile4_irq, int cpu_irq)
28{
29 u32 offset, t;
30
31 offset = DDB_INTCTRL;
32 if (nile4_irq >= 8) {
33 offset += 4;
34 nile4_irq -= 8;
35 }
36 t = ddb_in32(offset);
37 t &= ~(7 << (nile4_irq * 4));
38 t |= cpu_irq << (nile4_irq * 4);
39 ddb_out32(offset, t);
40}
41
42void nile4_map_irq_all(int cpu_irq)
43{
44 u32 all, t;
45
46 all = cpu_irq;
47 all |= all << 4;
48 all |= all << 8;
49 all |= all << 16;
50 t = ddb_in32(DDB_INTCTRL);
51 t &= 0x88888888;
52 t |= all;
53 ddb_out32(DDB_INTCTRL, t);
54 t = ddb_in32(DDB_INTCTRL + 4);
55 t &= 0x88888888;
56 t |= all;
57 ddb_out32(DDB_INTCTRL + 4, t);
58}
59
60void nile4_enable_irq(unsigned int nile4_irq)
61{
62 u32 offset, t;
63
64 nile4_irq-=irq_base;
65
66 ddb5074_led_hex(8);
67
68 offset = DDB_INTCTRL;
69 if (nile4_irq >= 8) {
70 offset += 4;
71 nile4_irq -= 8;
72 }
73 ddb5074_led_hex(9);
74 t = ddb_in32(offset);
75 ddb5074_led_hex(0xa);
76 t |= 8 << (nile4_irq * 4);
77 ddb_out32(offset, t);
78 ddb5074_led_hex(0xb);
79}
80
81void nile4_disable_irq(unsigned int nile4_irq)
82{
83 u32 offset, t;
84
85 nile4_irq-=irq_base;
86
87 offset = DDB_INTCTRL;
88 if (nile4_irq >= 8) {
89 offset += 4;
90 nile4_irq -= 8;
91 }
92 t = ddb_in32(offset);
93 t &= ~(8 << (nile4_irq * 4));
94 ddb_out32(offset, t);
95}
96
97void nile4_disable_irq_all(void)
98{
99 ddb_out32(DDB_INTCTRL, 0);
100 ddb_out32(DDB_INTCTRL + 4, 0);
101}
102
103u16 nile4_get_irq_stat(int cpu_irq)
104{
105 return ddb_in16(DDB_INTSTAT0 + cpu_irq * 2);
106}
107
108void nile4_enable_irq_output(int cpu_irq)
109{
110 u32 t;
111
112 t = ddb_in32(DDB_INTSTAT1 + 4);
113 t |= 1 << (16 + cpu_irq);
114 ddb_out32(DDB_INTSTAT1, t);
115}
116
117void nile4_disable_irq_output(int cpu_irq)
118{
119 u32 t;
120
121 t = ddb_in32(DDB_INTSTAT1 + 4);
122 t &= ~(1 << (16 + cpu_irq));
123 ddb_out32(DDB_INTSTAT1, t);
124}
125
126void nile4_set_pci_irq_polarity(int pci_irq, int high)
127{
128 u32 t;
129
130 t = ddb_in32(DDB_INTPPES);
131 if (high)
132 t &= ~(1 << (pci_irq * 2));
133 else
134 t |= 1 << (pci_irq * 2);
135 ddb_out32(DDB_INTPPES, t);
136}
137
138void nile4_set_pci_irq_level_or_edge(int pci_irq, int level)
139{
140 u32 t;
141
142 t = ddb_in32(DDB_INTPPES);
143 if (level)
144 t |= 2 << (pci_irq * 2);
145 else
146 t &= ~(2 << (pci_irq * 2));
147 ddb_out32(DDB_INTPPES, t);
148}
149
150void nile4_clear_irq(int nile4_irq)
151{
152 nile4_irq-=irq_base;
153 ddb_out32(DDB_INTCLR, 1 << nile4_irq);
154}
155
156void nile4_clear_irq_mask(u32 mask)
157{
158 ddb_out32(DDB_INTCLR, mask);
159}
160
161u8 nile4_i8259_iack(void)
162{
163 u8 irq;
164 u32 reg;
165
166 /* Set window 0 for interrupt acknowledge */
167 reg = ddb_in32(DDB_PCIINIT0);
168
169 ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
170 irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
171 /* restore window 0 for PCI I/O space */
172 // ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
173 ddb_out32(DDB_PCIINIT0, reg);
174
175 /* i8269.c set the base vector to be 0x0 */
176 return irq ;
177}
178
179static unsigned int nile4_irq_startup(unsigned int irq) {
180
181 nile4_enable_irq(irq);
182 return 0;
183
184}
185
186static void nile4_ack_irq(unsigned int irq) {
187
188 ddb5074_led_hex(4);
189
190 nile4_clear_irq(irq);
191 ddb5074_led_hex(2);
192 nile4_disable_irq(irq);
193
194 ddb5074_led_hex(0);
195}
196
197static void nile4_irq_end(unsigned int irq) {
198
199 ddb5074_led_hex(3);
200 if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
201 ddb5074_led_hex(5);
202 nile4_enable_irq(irq);
203 ddb5074_led_hex(7);
204 }
205
206 ddb5074_led_hex(1);
207}
208
209#define nile4_irq_shutdown nile4_disable_irq
210
211static hw_irq_controller nile4_irq_controller = {
212 .typename = "nile4",
213 .startup = nile4_irq_startup,
214 .shutdown = nile4_irq_shutdown,
215 .enable = nile4_enable_irq,
216 .disable = nile4_disable_irq,
217 .ack = nile4_ack_irq,
218 .end = nile4_irq_end,
219};
220
221void nile4_irq_setup(u32 base) {
222
223 int i;
224
225 irq_base=base;
226
227 /* Map all interrupts to CPU int #0 */
228 nile4_map_irq_all(0);
229
230 /* PCI INTA#-E# must be level triggered */
231 nile4_set_pci_irq_level_or_edge(0, 1);
232 nile4_set_pci_irq_level_or_edge(1, 1);
233 nile4_set_pci_irq_level_or_edge(2, 1);
234 nile4_set_pci_irq_level_or_edge(3, 1);
235 nile4_set_pci_irq_level_or_edge(4, 1);
236
237 /* PCI INTA#-D# must be active low, INTE# must be active high */
238 nile4_set_pci_irq_polarity(0, 0);
239 nile4_set_pci_irq_polarity(1, 0);
240 nile4_set_pci_irq_polarity(2, 0);
241 nile4_set_pci_irq_polarity(3, 0);
242 nile4_set_pci_irq_polarity(4, 1);
243
244
245 for (i = 0; i < 16; i++) {
246 nile4_clear_irq(i);
247 nile4_disable_irq(i);
248 }
249
250 /* Enable CPU int #0 */
251 nile4_enable_irq_output(0);
252
253 for (i= base; i< base + NUM_NILE4_INTERRUPTS; i++) {
254 irq_desc[i].status = IRQ_DISABLED;
255 irq_desc[i].action = NULL;
256 irq_desc[i].depth = 1;
257 irq_desc[i].handler = &nile4_irq_controller;
258 }
259}
260
261#if defined(CONFIG_RUNTIME_DEBUG)
262void nile4_dump_irq_status(void)
263{
264 printk(KERN_DEBUG "
265 CPUSTAT = %p:%p\n", (void *) ddb_in32(DDB_CPUSTAT + 4),
266 (void *) ddb_in32(DDB_CPUSTAT));
267 printk(KERN_DEBUG "
268 INTCTRL = %p:%p\n", (void *) ddb_in32(DDB_INTCTRL + 4),
269 (void *) ddb_in32(DDB_INTCTRL));
270 printk(KERN_DEBUG
271 "INTSTAT0 = %p:%p\n",
272 (void *) ddb_in32(DDB_INTSTAT0 + 4),
273 (void *) ddb_in32(DDB_INTSTAT0));
274 printk(KERN_DEBUG
275 "INTSTAT1 = %p:%p\n",
276 (void *) ddb_in32(DDB_INTSTAT1 + 4),
277 (void *) ddb_in32(DDB_INTSTAT1));
278 printk(KERN_DEBUG
279 "INTCLR = %p:%p\n", (void *) ddb_in32(DDB_INTCLR + 4),
280 (void *) ddb_in32(DDB_INTCLR));
281 printk(KERN_DEBUG
282 "INTPPES = %p:%p\n", (void *) ddb_in32(DDB_INTPPES + 4),
283 (void *) ddb_in32(DDB_INTPPES));
284}
285
286#endif
diff --git a/arch/mips/ddb5xxx/ddb5074/setup.c b/arch/mips/ddb5xxx/ddb5074/setup.c
deleted file mode 100644
index 91456b068c2e..000000000000
--- a/arch/mips/ddb5xxx/ddb5074/setup.c
+++ /dev/null
@@ -1,234 +0,0 @@
1/*
2 * arch/mips/ddb5074/setup.c -- NEC DDB Vrc-5074 setup routines
3 *
4 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
5 * Sony Software Development Center Europe (SDCE), Brussels
6 */
7#include <linux/init.h>
8#include <linux/kbd_ll.h>
9#include <linux/kernel.h>
10#include <linux/kdev_t.h>
11#include <linux/types.h>
12#include <linux/sched.h>
13#include <linux/pci.h>
14#include <linux/ide.h>
15#include <linux/ioport.h>
16#include <linux/irq.h>
17#include <linux/pm.h>
18
19#include <asm/addrspace.h>
20#include <asm/bcache.h>
21#include <asm/irq.h>
22#include <asm/reboot.h>
23#include <asm/gdb-stub.h>
24#include <asm/time.h>
25#include <asm/nile4.h>
26#include <asm/ddb5xxx/ddb5074.h>
27#include <asm/ddb5xxx/ddb5xxx.h>
28
29static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
30
31static void ddb_machine_restart(char *command)
32{
33 u32 t;
34
35 /* PCI cold reset */
36 t = nile4_in32(NILE4_PCICTRL + 4);
37 t |= 0x40000000;
38 nile4_out32(NILE4_PCICTRL + 4, t);
39 /* CPU cold reset */
40 t = nile4_in32(NILE4_CPUSTAT);
41 t |= 1;
42 nile4_out32(NILE4_CPUSTAT, t);
43 /* Call the PROM */
44 back_to_prom();
45}
46
47static void ddb_machine_halt(void)
48{
49 printk("DDB Vrc-5074 halted.\n");
50 do {
51 } while (1);
52}
53
54static void ddb_machine_power_off(void)
55{
56 printk("DDB Vrc-5074 halted. Please turn off the power.\n");
57 do {
58 } while (1);
59}
60
61extern void rtc_ds1386_init(unsigned long base);
62
63extern void (*board_timer_setup) (struct irqaction * irq);
64
65static void __init ddb_timer_init(struct irqaction *irq)
66{
67 /* set the clock to 1 Hz */
68 nile4_out32(NILE4_T2CTRL, 1000000);
69 /* enable the General-Purpose Timer */
70 nile4_out32(NILE4_T2CTRL + 4, 0x00000001);
71 /* reset timer */
72 nile4_out32(NILE4_T2CNTR, 0);
73 /* enable interrupt */
74 setup_irq(nile4_to_irq(NILE4_INT_GPT), irq);
75 nile4_enable_irq(nile4_to_irq(NILE4_INT_GPT));
76 change_c0_status(ST0_IM,
77 IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4);
78
79}
80
81static void __init ddb_time_init(void)
82{
83 /* we have ds1396 RTC chip */
84 rtc_ds1386_init(KSEG1ADDR(DDB_PCI_MEM_BASE));
85}
86
87
88
89void __init plat_setup(void)
90{
91 set_io_port_base(NILE4_PCI_IO_BASE);
92 isa_slot_offset = NILE4_PCI_MEM_BASE;
93 board_timer_setup = ddb_timer_init;
94 board_time_init = ddb_time_init;
95
96
97 _machine_restart = ddb_machine_restart;
98 _machine_halt = ddb_machine_halt;
99 pm_power_off = ddb_machine_power_off;
100
101 ddb_out32(DDB_BAR0, 0);
102
103 ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, 0x10);
104 ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE , 0x10);
105
106 /* Reboot on panic */
107 panic_timeout = 180;
108}
109
110#define USE_NILE4_SERIAL 0
111
112#if USE_NILE4_SERIAL
113#define ns16550_in(reg) nile4_in8((reg)*8)
114#define ns16550_out(reg, val) nile4_out8((reg)*8, (val))
115#else
116#define NS16550_BASE (NILE4_PCI_IO_BASE+0x03f8)
117static inline u8 ns16550_in(u32 reg)
118{
119 return *(volatile u8 *) (NS16550_BASE + reg);
120}
121
122static inline void ns16550_out(u32 reg, u8 val)
123{
124 *(volatile u8 *) (NS16550_BASE + reg) = val;
125}
126#endif
127
128#define NS16550_RBR 0
129#define NS16550_THR 0
130#define NS16550_DLL 0
131#define NS16550_IER 1
132#define NS16550_DLM 1
133#define NS16550_FCR 2
134#define NS16550_IIR 2
135#define NS16550_LCR 3
136#define NS16550_MCR 4
137#define NS16550_LSR 5
138#define NS16550_MSR 6
139#define NS16550_SCR 7
140
141#define NS16550_LSR_DR 0x01 /* Data ready */
142#define NS16550_LSR_OE 0x02 /* Overrun */
143#define NS16550_LSR_PE 0x04 /* Parity error */
144#define NS16550_LSR_FE 0x08 /* Framing error */
145#define NS16550_LSR_BI 0x10 /* Break */
146#define NS16550_LSR_THRE 0x20 /* Xmit holding register empty */
147#define NS16550_LSR_TEMT 0x40 /* Xmitter empty */
148#define NS16550_LSR_ERR 0x80 /* Error */
149
150
151void _serinit(void)
152{
153#if USE_NILE4_SERIAL
154 ns16550_out(NS16550_LCR, 0x80);
155 ns16550_out(NS16550_DLM, 0x00);
156 ns16550_out(NS16550_DLL, 0x36); /* 9600 baud */
157 ns16550_out(NS16550_LCR, 0x00);
158 ns16550_out(NS16550_LCR, 0x03);
159 ns16550_out(NS16550_FCR, 0x47);
160#else
161 /* done by PMON */
162#endif
163}
164
165void _putc(char c)
166{
167 while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE));
168 ns16550_out(NS16550_THR, c);
169 if (c == '\n') {
170 while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE));
171 ns16550_out(NS16550_THR, '\r');
172 }
173}
174
175void _puts(const char *s)
176{
177 char c;
178 while ((c = *s++))
179 _putc(c);
180}
181
182char _getc(void)
183{
184 while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_DR));
185 return ns16550_in(NS16550_RBR);
186}
187
188int _testc(void)
189{
190 return (ns16550_in(NS16550_LSR) & NS16550_LSR_DR) != 0;
191}
192
193
194/*
195 * Hexadecimal 7-segment LED
196 */
197void ddb5074_led_hex(int hex)
198{
199 outb(hex, 0x80);
200}
201
202
203/*
204 * LEDs D2 and D3, connected to the GPIO pins of the PMU in the ALi M1543
205 */
206struct pci_dev *pci_pmu = NULL;
207
208void ddb5074_led_d2(int on)
209{
210 u8 t;
211
212 if (pci_pmu) {
213 pci_read_config_byte(pci_pmu, 0x7e, &t);
214 if (on)
215 t &= 0x7f;
216 else
217 t |= 0x80;
218 pci_write_config_byte(pci_pmu, 0x7e, t);
219 }
220}
221
222void ddb5074_led_d3(int on)
223{
224 u8 t;
225
226 if (pci_pmu) {
227 pci_read_config_byte(pci_pmu, 0x7e, &t);
228 if (on)
229 t &= 0xbf;
230 else
231 t |= 0x40;
232 pci_write_config_byte(pci_pmu, 0x7e, t);
233 }
234}
diff --git a/arch/mips/ddb5xxx/ddb5476/Makefile b/arch/mips/ddb5xxx/ddb5476/Makefile
deleted file mode 100644
index ab0312cb47b4..000000000000
--- a/arch/mips/ddb5xxx/ddb5476/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
1#
2# Makefile for the NEC DDB Vrc-5476 specific kernel interface routines
3# under Linux.
4#
5
6obj-y += setup.o irq.o nile4_pic.o vrc5476_irq.o
7obj-$(CONFIG_KGDB) += dbg_io.o
8
9EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/ddb5xxx/ddb5476/dbg_io.c b/arch/mips/ddb5xxx/ddb5476/dbg_io.c
deleted file mode 100644
index f2296a999953..000000000000
--- a/arch/mips/ddb5xxx/ddb5476/dbg_io.c
+++ /dev/null
@@ -1,136 +0,0 @@
1/*
2 * kgdb io functions for DDB5476. We use the second serial port.
3 *
4 * Copyright (C) 2001 MontaVista Software Inc.
5 * Author: jsun@mvista.com or jsun@junsun.net
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14/* ======================= CONFIG ======================== */
15
16/* [jsun] we use the second serial port for kdb */
17#define BASE 0xa60002f8
18#define MAX_BAUD 115200
19
20/* distance in bytes between two serial registers */
21#define REG_OFFSET 1
22
23/*
24 * 0 - kgdb does serial init
25 * 1 - kgdb skip serial init
26 */
27static int remoteDebugInitialized = 0;
28
29/*
30 * the default baud rate *if* kgdb does serial init
31 */
32#define BAUD_DEFAULT UART16550_BAUD_38400
33
34/* ======================= END OF CONFIG ======================== */
35
36typedef unsigned char uint8;
37typedef unsigned int uint32;
38
39#define UART16550_BAUD_2400 2400
40#define UART16550_BAUD_4800 4800
41#define UART16550_BAUD_9600 9600
42#define UART16550_BAUD_19200 19200
43#define UART16550_BAUD_38400 38400
44#define UART16550_BAUD_57600 57600
45#define UART16550_BAUD_115200 115200
46
47#define UART16550_PARITY_NONE 0
48#define UART16550_PARITY_ODD 0x08
49#define UART16550_PARITY_EVEN 0x18
50#define UART16550_PARITY_MARK 0x28
51#define UART16550_PARITY_SPACE 0x38
52
53#define UART16550_DATA_5BIT 0x0
54#define UART16550_DATA_6BIT 0x1
55#define UART16550_DATA_7BIT 0x2
56#define UART16550_DATA_8BIT 0x3
57
58#define UART16550_STOP_1BIT 0x0
59#define UART16550_STOP_2BIT 0x4
60
61/* register offset */
62#define OFS_RCV_BUFFER 0
63#define OFS_TRANS_HOLD 0
64#define OFS_SEND_BUFFER 0
65#define OFS_INTR_ENABLE (1*REG_OFFSET)
66#define OFS_INTR_ID (2*REG_OFFSET)
67#define OFS_DATA_FORMAT (3*REG_OFFSET)
68#define OFS_LINE_CONTROL (3*REG_OFFSET)
69#define OFS_MODEM_CONTROL (4*REG_OFFSET)
70#define OFS_RS232_OUTPUT (4*REG_OFFSET)
71#define OFS_LINE_STATUS (5*REG_OFFSET)
72#define OFS_MODEM_STATUS (6*REG_OFFSET)
73#define OFS_RS232_INPUT (6*REG_OFFSET)
74#define OFS_SCRATCH_PAD (7*REG_OFFSET)
75
76#define OFS_DIVISOR_LSB (0*REG_OFFSET)
77#define OFS_DIVISOR_MSB (1*REG_OFFSET)
78
79
80/* memory-mapped read/write of the port */
81#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
82#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
83
84void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
85{
86 /* disable interrupts */
87 UART16550_WRITE(OFS_INTR_ENABLE, 0);
88
89 /* set up baud rate */
90 {
91 uint32 divisor;
92
93 /* set DIAB bit */
94 UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
95
96 /* set divisor */
97 divisor = MAX_BAUD / baud;
98 UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
99 UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
100
101 /* clear DIAB bit */
102 UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
103 }
104
105 /* set data format */
106 UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
107}
108
109
110uint8 getDebugChar(void)
111{
112 if (!remoteDebugInitialized) {
113 remoteDebugInitialized = 1;
114 debugInit(BAUD_DEFAULT,
115 UART16550_DATA_8BIT,
116 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
117 }
118
119 while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
120 return UART16550_READ(OFS_RCV_BUFFER);
121}
122
123
124int putDebugChar(uint8 byte)
125{
126 if (!remoteDebugInitialized) {
127 remoteDebugInitialized = 1;
128 debugInit(BAUD_DEFAULT,
129 UART16550_DATA_8BIT,
130 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
131 }
132
133 while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
134 UART16550_WRITE(OFS_SEND_BUFFER, byte);
135 return 1;
136}
diff --git a/arch/mips/ddb5xxx/ddb5476/irq.c b/arch/mips/ddb5xxx/ddb5476/irq.c
deleted file mode 100644
index 7583a1f30711..000000000000
--- a/arch/mips/ddb5xxx/ddb5476/irq.c
+++ /dev/null
@@ -1,165 +0,0 @@
1/*
2 * arch/mips/ddb5476/irq.c -- NEC DDB Vrc-5476 interrupt routines
3 *
4 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
5 * Sony Software Development Center Europe (SDCE), Brussels
6 *
7 * Re-write the whole thing to use new irq.c file.
8 * Copyright (C) 2001 MontaVista Software Inc.
9 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
10 *
11 */
12#include <linux/init.h>
13#include <linux/sched.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16
17#include <asm/i8259.h>
18#include <asm/io.h>
19#include <asm/ptrace.h>
20
21#include <asm/ddb5xxx/ddb5xxx.h>
22
23#define M1543_PNP_CONFIG 0x03f0 /* PnP Config Port */
24#define M1543_PNP_INDEX 0x03f0 /* PnP Index Port */
25#define M1543_PNP_DATA 0x03f1 /* PnP Data Port */
26
27#define M1543_PNP_ALT_CONFIG 0x0370 /* Alternative PnP Config Port */
28#define M1543_PNP_ALT_INDEX 0x0370 /* Alternative PnP Index Port */
29#define M1543_PNP_ALT_DATA 0x0371 /* Alternative PnP Data Port */
30
31#define M1543_INT1_MASTER_CTRL 0x0020 /* INT_1 (master) Control Register */
32#define M1543_INT1_MASTER_MASK 0x0021 /* INT_1 (master) Mask Register */
33
34#define M1543_INT1_SLAVE_CTRL 0x00a0 /* INT_1 (slave) Control Register */
35#define M1543_INT1_SLAVE_MASK 0x00a1 /* INT_1 (slave) Mask Register */
36
37#define M1543_INT1_MASTER_ELCR 0x04d0 /* INT_1 (master) Edge/Level Control */
38#define M1543_INT1_SLAVE_ELCR 0x04d1 /* INT_1 (slave) Edge/Level Control */
39
40static void m1543_irq_setup(void)
41{
42 /*
43 * The ALI M1543 has 13 interrupt inputs, IRQ1..IRQ13. Not all
44 * the possible IO sources in the M1543 are in use by us. We will
45 * use the following mapping:
46 *
47 * IRQ1 - keyboard (default set by M1543)
48 * IRQ3 - reserved for UART B (default set by M1543) (note that
49 * the schematics for the DDB Vrc-5476 board seem to
50 * indicate that IRQ3 is connected to the DS1386
51 * watchdog timer interrupt output so we might have
52 * a conflict)
53 * IRQ4 - reserved for UART A (default set by M1543)
54 * IRQ5 - parallel (default set by M1543)
55 * IRQ8 - DS1386 time of day (RTC) interrupt
56 * IRQ9 - USB (hardwired in ddb_setup)
57 * IRQ10 - PMU (hardwired in ddb_setup)
58 * IRQ12 - mouse
59 * IRQ14,15 - IDE controller (need to be confirmed, jsun)
60 */
61
62 /*
63 * Assing mouse interrupt to IRQ12
64 */
65
66 /* Enter configuration mode */
67 outb(0x51, M1543_PNP_CONFIG);
68 outb(0x23, M1543_PNP_CONFIG);
69
70 /* Select logical device 7 (Keyboard) */
71 outb(0x07, M1543_PNP_INDEX);
72 outb(0x07, M1543_PNP_DATA);
73
74 /* Select IRQ12 */
75 outb(0x72, M1543_PNP_INDEX);
76 outb(0x0c, M1543_PNP_DATA);
77
78 /* Leave configration mode */
79 outb(0xbb, M1543_PNP_CONFIG);
80}
81
82static void nile4_irq_setup(void)
83{
84 int i;
85
86 /* Map all interrupts to CPU int #0 (IP2) */
87 nile4_map_irq_all(0);
88
89 /* PCI INTA#-E# must be level triggered */
90 nile4_set_pci_irq_level_or_edge(0, 1);
91 nile4_set_pci_irq_level_or_edge(1, 1);
92 nile4_set_pci_irq_level_or_edge(2, 1);
93 nile4_set_pci_irq_level_or_edge(3, 1);
94
95 /* PCI INTA#, B#, D# must be active low, INTC# must be active high */
96 nile4_set_pci_irq_polarity(0, 0);
97 nile4_set_pci_irq_polarity(1, 0);
98 nile4_set_pci_irq_polarity(2, 1);
99 nile4_set_pci_irq_polarity(3, 0);
100
101 for (i = 0; i < 16; i++)
102 nile4_clear_irq(i);
103
104 /* Enable CPU int #0 */
105 nile4_enable_irq_output(0);
106
107 /* memory resource acquire in ddb_setup */
108}
109
110static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
111static struct irqaction irq_error = { no_action, 0, CPU_MASK_NONE, "error", NULL, NULL };
112
113extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
114extern void mips_cpu_irq_init(u32 irq_base);
115extern void vrc5476_irq_init(u32 irq_base);
116
117extern void vrc5476_irq_dispatch(struct pt_regs *regs);
118
119asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
120{
121 unsigned int pending = read_c0_cause() & read_c0_status();
122
123 if (pending & STATUSF_IP7)
124 do_IRQ(CPU_IRQ_BASE + 7, regs);
125 else if (pending & STATUSF_IP2)
126 vrc5476_irq_dispatch(regs);
127 else if (pending & STATUSF_IP3)
128 do_IRQ(CPU_IRQ_BASE + 3, regs);
129 else if (pending & STATUSF_IP4)
130 do_IRQ(CPU_IRQ_BASE + 4, regs);
131 else if (pending & STATUSF_IP5)
132 do_IRQ(CPU_IRQ_BASE + 5, regs);
133 else if (pending & STATUSF_IP6)
134 do_IRQ(CPU_IRQ_BASE + 6, regs);
135 else if (pending & STATUSF_IP0)
136 do_IRQ(CPU_IRQ_BASE, regs);
137 else if (pending & STATUSF_IP1)
138 do_IRQ(CPU_IRQ_BASE + 1, regs);
139
140 vrc5476_irq_dispatch(regs);
141}
142
143void __init arch_init_irq(void)
144{
145 /* hardware initialization */
146 nile4_irq_setup();
147 m1543_irq_setup();
148
149 /* controller setup */
150 init_i8259_irqs();
151 vrc5476_irq_init(VRC5476_IRQ_BASE);
152 mips_cpu_irq_init(CPU_IRQ_BASE);
153
154 /* setup cascade interrupts */
155 setup_irq(VRC5476_IRQ_BASE + VRC5476_I8259_CASCADE, &irq_cascade);
156 setup_irq(CPU_IRQ_BASE + CPU_VRC5476_CASCADE, &irq_cascade);
157
158 /* setup error interrupts for debugging */
159 setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CPCE, &irq_error);
160 setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CNTD, &irq_error);
161 setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_MCE, &irq_error);
162 setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_LBRT, &irq_error);
163 setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCIS, &irq_error);
164 setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCI, &irq_error);
165}
diff --git a/arch/mips/ddb5xxx/ddb5476/nile4_pic.c b/arch/mips/ddb5xxx/ddb5476/nile4_pic.c
deleted file mode 100644
index e930cee7944f..000000000000
--- a/arch/mips/ddb5xxx/ddb5476/nile4_pic.c
+++ /dev/null
@@ -1,190 +0,0 @@
1/*
2 * arch/mips/ddb5476/nile4.c --
3 * low-level PIC code for NEC Vrc-5476 (Nile 4)
4 *
5 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
6 * Sony Software Development Center Europe (SDCE), Brussels
7 *
8 * Copyright 2001 MontaVista Software Inc.
9 * Author: jsun@mvista.com or jsun@junsun.net
10 *
11 */
12#include <linux/config.h>
13#include <linux/kernel.h>
14#include <linux/types.h>
15
16#include <asm/addrspace.h>
17
18#include <asm/ddb5xxx/ddb5xxx.h>
19
20
21/*
22 * Interrupt Programming
23 */
24void nile4_map_irq(int nile4_irq, int cpu_irq)
25{
26 u32 offset, t;
27
28 offset = DDB_INTCTRL;
29 if (nile4_irq >= 8) {
30 offset += 4;
31 nile4_irq -= 8;
32 }
33 t = ddb_in32(offset);
34 t &= ~(7 << (nile4_irq * 4));
35 t |= cpu_irq << (nile4_irq * 4);
36 ddb_out32(offset, t);
37}
38
39void nile4_map_irq_all(int cpu_irq)
40{
41 u32 all, t;
42
43 all = cpu_irq;
44 all |= all << 4;
45 all |= all << 8;
46 all |= all << 16;
47 t = ddb_in32(DDB_INTCTRL);
48 t &= 0x88888888;
49 t |= all;
50 ddb_out32(DDB_INTCTRL, t);
51 t = ddb_in32(DDB_INTCTRL + 4);
52 t &= 0x88888888;
53 t |= all;
54 ddb_out32(DDB_INTCTRL + 4, t);
55}
56
57void nile4_enable_irq(int nile4_irq)
58{
59 u32 offset, t;
60
61 offset = DDB_INTCTRL;
62 if (nile4_irq >= 8) {
63 offset += 4;
64 nile4_irq -= 8;
65 }
66 t = ddb_in32(offset);
67 t |= 8 << (nile4_irq * 4);
68 ddb_out32(offset, t);
69}
70
71void nile4_disable_irq(int nile4_irq)
72{
73 u32 offset, t;
74
75 offset = DDB_INTCTRL;
76 if (nile4_irq >= 8) {
77 offset += 4;
78 nile4_irq -= 8;
79 }
80 t = ddb_in32(offset);
81 t &= ~(8 << (nile4_irq * 4));
82 ddb_out32(offset, t);
83}
84
85void nile4_disable_irq_all(void)
86{
87 ddb_out32(DDB_INTCTRL, 0);
88 ddb_out32(DDB_INTCTRL + 4, 0);
89}
90
91u16 nile4_get_irq_stat(int cpu_irq)
92{
93 return ddb_in16(DDB_INTSTAT0 + cpu_irq * 2);
94}
95
96void nile4_enable_irq_output(int cpu_irq)
97{
98 u32 t;
99
100 t = ddb_in32(DDB_INTSTAT1 + 4);
101 t |= 1 << (16 + cpu_irq);
102 ddb_out32(DDB_INTSTAT1, t);
103}
104
105void nile4_disable_irq_output(int cpu_irq)
106{
107 u32 t;
108
109 t = ddb_in32(DDB_INTSTAT1 + 4);
110 t &= ~(1 << (16 + cpu_irq));
111 ddb_out32(DDB_INTSTAT1, t);
112}
113
114void nile4_set_pci_irq_polarity(int pci_irq, int high)
115{
116 u32 t;
117
118 t = ddb_in32(DDB_INTPPES);
119 if (high)
120 t &= ~(1 << (pci_irq * 2));
121 else
122 t |= 1 << (pci_irq * 2);
123 ddb_out32(DDB_INTPPES, t);
124}
125
126void nile4_set_pci_irq_level_or_edge(int pci_irq, int level)
127{
128 u32 t;
129
130 t = ddb_in32(DDB_INTPPES);
131 if (level)
132 t |= 2 << (pci_irq * 2);
133 else
134 t &= ~(2 << (pci_irq * 2));
135 ddb_out32(DDB_INTPPES, t);
136}
137
138void nile4_clear_irq(int nile4_irq)
139{
140 ddb_out32(DDB_INTCLR, 1 << nile4_irq);
141}
142
143void nile4_clear_irq_mask(u32 mask)
144{
145 ddb_out32(DDB_INTCLR, mask);
146}
147
148u8 nile4_i8259_iack(void)
149{
150 u8 irq;
151 u32 reg;
152
153 /* Set window 0 for interrupt acknowledge */
154 reg = ddb_in32(DDB_PCIINIT0);
155
156 ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
157 irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
158 /* restore window 0 for PCI I/O space */
159 // ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
160 ddb_out32(DDB_PCIINIT0, reg);
161
162 /* i8269.c set the base vector to be 0x0 */
163 return irq + I8259_IRQ_BASE;
164}
165
166#if defined(CONFIG_RUNTIME_DEBUG)
167void nile4_dump_irq_status(void)
168{
169 printk(KERN_DEBUG "
170 CPUSTAT = %p:%p\n", (void *) ddb_in32(DDB_CPUSTAT + 4),
171 (void *) ddb_in32(DDB_CPUSTAT));
172 printk(KERN_DEBUG "
173 INTCTRL = %p:%p\n", (void *) ddb_in32(DDB_INTCTRL + 4),
174 (void *) ddb_in32(DDB_INTCTRL));
175 printk(KERN_DEBUG
176 "INTSTAT0 = %p:%p\n",
177 (void *) ddb_in32(DDB_INTSTAT0 + 4),
178 (void *) ddb_in32(DDB_INTSTAT0));
179 printk(KERN_DEBUG
180 "INTSTAT1 = %p:%p\n",
181 (void *) ddb_in32(DDB_INTSTAT1 + 4),
182 (void *) ddb_in32(DDB_INTSTAT1));
183 printk(KERN_DEBUG
184 "INTCLR = %p:%p\n", (void *) ddb_in32(DDB_INTCLR + 4),
185 (void *) ddb_in32(DDB_INTCLR));
186 printk(KERN_DEBUG
187 "INTPPES = %p:%p\n", (void *) ddb_in32(DDB_INTPPES + 4),
188 (void *) ddb_in32(DDB_INTPPES));
189}
190#endif
diff --git a/arch/mips/ddb5xxx/ddb5476/setup.c b/arch/mips/ddb5xxx/ddb5476/setup.c
deleted file mode 100644
index c902adef5942..000000000000
--- a/arch/mips/ddb5xxx/ddb5476/setup.c
+++ /dev/null
@@ -1,296 +0,0 @@
1/*
2 * arch/mips/ddb5476/setup.c -- NEC DDB Vrc-5476 setup routines
3 *
4 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
5 * Sony Software Development Center Europe (SDCE), Brussels
6 */
7#include <linux/init.h>
8#include <linux/kbd_ll.h>
9#include <linux/kernel.h>
10#include <linux/kdev_t.h>
11#include <linux/types.h>
12#include <linux/sched.h>
13#include <linux/pci.h>
14#include <linux/pm.h>
15
16#include <asm/addrspace.h>
17#include <asm/bcache.h>
18#include <asm/irq.h>
19#include <asm/reboot.h>
20#include <asm/gdb-stub.h>
21#include <asm/time.h>
22#include <asm/debug.h>
23#include <asm/traps.h>
24
25#include <asm/ddb5xxx/ddb5xxx.h>
26
27// #define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */
28
29#ifdef USE_CPU_COUNTER_TIMER
30
31#define CPU_COUNTER_FREQUENCY 83000000
32#else
33/* otherwise we use general purpose timer */
34#define TIMER_FREQUENCY 83000000
35#define TIMER_BASE DDB_T2CTRL
36#define TIMER_IRQ (VRC5476_IRQ_BASE + VRC5476_IRQ_GPT)
37#endif
38
39static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
40
41static void ddb_machine_restart(char *command)
42{
43 u32 t;
44
45 /* PCI cold reset */
46 t = ddb_in32(DDB_PCICTRL + 4);
47 t |= 0x40000000;
48 ddb_out32(DDB_PCICTRL + 4, t);
49 /* CPU cold reset */
50 t = ddb_in32(DDB_CPUSTAT);
51 t |= 1;
52 ddb_out32(DDB_CPUSTAT, t);
53 /* Call the PROM */
54 back_to_prom();
55}
56
57static void ddb_machine_halt(void)
58{
59 printk(KERN_NOTICE "DDB Vrc-5476 halted.\n");
60 while (1);
61}
62
63static void ddb_machine_power_off(void)
64{
65 printk(KERN_NOTICE "DDB Vrc-5476 halted. Please turn off the power.\n");
66 while (1);
67}
68
69extern void rtc_ds1386_init(unsigned long base);
70
71static void __init ddb_time_init(void)
72{
73#if defined(USE_CPU_COUNTER_TIMER)
74 mips_hpt_frequency = CPU_COUNTER_FREQUENCY;
75#endif
76
77 /* we have ds1396 RTC chip */
78 rtc_ds1386_init(KSEG1ADDR(DDB_PCI_MEM_BASE));
79}
80
81
82extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
83static void __init ddb_timer_setup(struct irqaction *irq)
84{
85#if defined(USE_CPU_COUNTER_TIMER)
86
87 unsigned int count;
88
89 /* we are using the cpu counter for timer interrupts */
90 setup_irq(CPU_IRQ_BASE + 7, irq);
91
92 /* to generate the first timer interrupt */
93 count = read_c0_count();
94 write_c0_compare(count + 1000);
95
96#else
97
98 ddb_out32(TIMER_BASE, TIMER_FREQUENCY/HZ);
99 ddb_out32(TIMER_BASE+4, 0x1); /* enable timer */
100 setup_irq(TIMER_IRQ, irq);
101#endif
102}
103
104static struct {
105 struct resource dma1;
106 struct resource timer;
107 struct resource rtc;
108 struct resource dma_page_reg;
109 struct resource dma2;
110} ddb5476_ioport = {
111 {
112 "dma1", 0x00, 0x1f, IORESOURCE_BUSY}, {
113 "timer", 0x40, 0x5f, IORESOURCE_BUSY}, {
114 "rtc", 0x70, 0x7f, IORESOURCE_BUSY}, {
115 "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY}, {
116 "dma2", 0xc0, 0xdf, IORESOURCE_BUSY}
117};
118
119static struct {
120 struct resource nile4;
121} ddb5476_iomem = {
122 { "Nile 4", DDB_BASE, DDB_BASE + DDB_SIZE - 1, IORESOURCE_BUSY}
123};
124
125
126static void ddb5476_board_init(void);
127
128void __init plat_setup(void)
129{
130 set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE));
131
132 board_time_init = ddb_time_init;
133 board_timer_setup = ddb_timer_setup;
134
135 _machine_restart = ddb_machine_restart;
136 _machine_halt = ddb_machine_halt;
137 pm_power_off = ddb_machine_power_off;
138
139 /* request io port/mem resources */
140 if (request_resource(&ioport_resource, &ddb5476_ioport.dma1) ||
141 request_resource(&ioport_resource, &ddb5476_ioport.timer) ||
142 request_resource(&ioport_resource, &ddb5476_ioport.rtc) ||
143 request_resource(&ioport_resource,
144 &ddb5476_ioport.dma_page_reg)
145 || request_resource(&ioport_resource, &ddb5476_ioport.dma2)
146 || request_resource(&iomem_resource, &ddb5476_iomem.nile4)) {
147 printk
148 ("ddb_setup - requesting oo port resources failed.\n");
149 for (;;);
150 }
151
152 /* Reboot on panic */
153 panic_timeout = 180;
154
155 /* [jsun] we need to set BAR0 so that SDRAM 0 appears at 0x0 in PCI */
156 /* *(long*)0xbfa00218 = 0x8; */
157
158 /* board initialization stuff */
159 ddb5476_board_init();
160}
161
162/*
163 * We don't trust bios. We essentially does hardware re-initialization
164 * as complete as possible, as far as we know we can safely do.
165 */
166static void ddb5476_board_init(void)
167{
168 /* ----------- setup PDARs ------------ */
169 /* check SDRAM0, whether we are on MEM bus does not matter */
170 db_assert((ddb_in32(DDB_SDRAM0) & 0xffffffef) ==
171 ddb_calc_pdar(DDB_SDRAM_BASE, DDB_SDRAM_SIZE, 32, 0, 1));
172
173 /* SDRAM1 should be turned off. What is this for anyway ? */
174 db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);
175
176 /* flash 1&2, DDB status, DDB control */
177 ddb_set_pdar(DDB_DCS2, DDB_DCS2_BASE, DDB_DCS2_SIZE, 16, 0, 0);
178 ddb_set_pdar(DDB_DCS3, DDB_DCS3_BASE, DDB_DCS3_SIZE, 16, 0, 0);
179 ddb_set_pdar(DDB_DCS4, DDB_DCS4_BASE, DDB_DCS4_SIZE, 8, 0, 0);
180 ddb_set_pdar(DDB_DCS5, DDB_DCS5_BASE, DDB_DCS5_SIZE, 8, 0, 0);
181
182 /* shut off other pdar so they don't accidentally get into the way */
183 ddb_set_pdar(DDB_DCS6, 0xffffffff, 0, 32, 0, 0);
184 ddb_set_pdar(DDB_DCS7, 0xffffffff, 0, 32, 0, 0);
185 ddb_set_pdar(DDB_DCS8, 0xffffffff, 0, 32, 0, 0);
186
187 /* verify VRC5477 base addr */
188 /* don't care about some details */
189 db_assert((ddb_in32(DDB_INTCS) & 0xffffff0f) ==
190 ddb_calc_pdar(DDB_INTCS_BASE, DDB_INTCS_SIZE, 8, 0, 0));
191
192 /* verify BOOT ROM addr */
193 /* don't care about some details */
194 db_assert((ddb_in32(DDB_BOOTCS) & 0xffffff0f) ==
195 ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));
196
197 /* setup PCI windows - window1 for MEM/config, window0 for IO */
198 ddb_set_pdar(DDB_PCIW0, DDB_PCI_IO_BASE, DDB_PCI_IO_SIZE, 32, 0, 1);
199 ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
200
201 ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1);
202 ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32);
203
204 /* ----------- setup PDARs ------------ */
205 /* this is problematic - it will reset Aladin which cause we loose
206 * serial port, and we don't know how to set up Aladin chip again.
207 */
208 // ddb_pci_reset_bus();
209
210 ddb_out32(DDB_BAR0, 0x00000008);
211
212 ddb_out32(DDB_BARC, 0xffffffff);
213 ddb_out32(DDB_BARB, 0xffffffff);
214 ddb_out32(DDB_BAR1, 0xffffffff);
215 ddb_out32(DDB_BAR2, 0xffffffff);
216 ddb_out32(DDB_BAR3, 0xffffffff);
217 ddb_out32(DDB_BAR4, 0xffffffff);
218 ddb_out32(DDB_BAR5, 0xffffffff);
219 ddb_out32(DDB_BAR6, 0xffffffff);
220 ddb_out32(DDB_BAR7, 0xffffffff);
221 ddb_out32(DDB_BAR8, 0xffffffff);
222
223 /* ----------- switch PCI1 to PCI CONFIG space ------------ */
224 ddb_set_pdar(DDB_PCIW1, DDB_PCI_CONFIG_BASE, DDB_PCI_CONFIG_SIZE, 32, 0, 1);
225 ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_CFG, 0x0, DDB_PCI_ACCESS_32);
226
227 /* ----- M1543 PCI setup ------ */
228
229 /* we know M1543 PCI-ISA controller is at addr:18 */
230 /* xxxx1010 makes USB at addr:13 and PMU at addr:14 */
231 *(volatile unsigned char *) 0xa8040072 &= 0xf0;
232 *(volatile unsigned char *) 0xa8040072 |= 0xa;
233
234 /* setup USB interrupt to IRQ 9, (bit 0:3 - 0001)
235 * no IOCHRDY signal, (bit 7 - 1)
236 * M1543C & M7101 VID and Subsys Device ID are read-only (bit 6 - 1)
237 * Make USB Master INTAJ level to edge conversion (bit 4 - 1)
238 */
239 *(unsigned char *) 0xa8040074 = 0xd1;
240
241 /* setup PMU(SCI to IRQ 10 (bit 0:3 - 0011)
242 * SCI routing to IRQ 13 disabled (bit 7 - 1)
243 * SCI interrupt level to edge conversion bypassed (bit 4 - 0)
244 */
245 *(unsigned char *) 0xa8040076 = 0x83;
246
247 /* setup IDE controller
248 * enable IDE controller (bit 6 - 1)
249 * IDE IDSEL to be addr:24 (bit 4:5 - 11)
250 * no IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0)
251 * no IDE ATA Primary Bus Signal Pad Control (bit 2 - 0)
252 * primary IRQ is 14, secondary is 15 (bit 1:0 - 01
253 */
254 // *(unsigned char*)0xa8040058 = 0x71;
255 // *(unsigned char*)0xa8040058 = 0x79;
256 // *(unsigned char*)0xa8040058 = 0x74; // use SIRQ, primary tri-state
257 *(unsigned char *) 0xa8040058 = 0x75; // primary tri-state
258
259#if 0
260 /* this is not necessary if M5229 does not use SIRQ */
261 *(unsigned char *) 0xa8040044 = 0x0d; // primary to IRQ 14
262 *(unsigned char *) 0xa8040075 = 0x0d; // secondary to IRQ 14
263#endif
264
265 /* enable IDE in the M5229 config register 0x50 (bit 0 - 1) */
266 /* M5229 IDSEL is addr:24; see above setting */
267 *(unsigned char *) 0xa9000050 |= 0x1;
268
269 /* enable bus master (bit 2) and IO decoding (bit 0) */
270 *(unsigned char *) 0xa9000004 |= 0x5;
271
272 /* enable native, copied from arch/ppc/k2boot/head.S */
273 /* TODO - need volatile, need to be portable */
274 *(unsigned char *) 0xa9000009 = 0xff;
275
276 /* ----- end of M1543 PCI setup ------ */
277
278 /* ----- reset on-board ether chip ------ */
279 *((volatile u32 *) 0xa8020004) |= 1; /* decode I/O */
280 *((volatile u32 *) 0xa8020010) = 0; /* set BAR address */
281
282 /* send reset command */
283 *((volatile u32 *) 0xa6000000) = 1; /* do a soft reset */
284
285 /* disable ether chip */
286 *((volatile u32 *) 0xa8020004) = 0; /* disable any decoding */
287
288 /* put it into sleep */
289 *((volatile u32 *) 0xa8020040) = 0x80000000;
290
291 /* ----- end of reset on-board ether chip ------ */
292
293 /* ----------- switch PCI1 back to PCI MEM space ------------ */
294 ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1);
295 ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32);
296}
diff --git a/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c b/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c
deleted file mode 100644
index a3c5e7b18018..000000000000
--- a/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c
+++ /dev/null
@@ -1,109 +0,0 @@
1/*
2 * The irq controller for vrc5476.
3 *
4 * Copyright (C) 2001 MontaVista Software Inc.
5 * Author: jsun@mvista.com or jsun@junsun.net
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/types.h>
17#include <linux/ptrace.h>
18
19#include <asm/system.h>
20
21#include <asm/ddb5xxx/ddb5xxx.h>
22
23static int irq_base;
24
25static void vrc5476_irq_enable(uint irq)
26{
27 nile4_enable_irq(irq - irq_base);
28}
29
30static void vrc5476_irq_disable(uint irq)
31{
32 nile4_disable_irq(irq - irq_base);
33}
34
35static unsigned int vrc5476_irq_startup(uint irq)
36{
37 nile4_enable_irq(irq - irq_base);
38 return 0;
39}
40
41#define vrc5476_irq_shutdown vrc5476_irq_disable
42
43static void vrc5476_irq_ack(uint irq)
44{
45 nile4_clear_irq(irq - irq_base);
46 nile4_disable_irq(irq - irq_base);
47}
48
49static void vrc5476_irq_end(uint irq)
50{
51 if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
52 vrc5476_irq_enable(irq);
53}
54
55static hw_irq_controller vrc5476_irq_controller = {
56 .typename = "vrc5476",
57 .startup = vrc5476_irq_startup,
58 .shutdown = vrc5476_irq_shutdown,
59 .enable = vrc5476_irq_enable,
60 .disable = vrc5476_irq_disable,
61 .ack = vrc5476_irq_ack,
62 .end = vrc5476_irq_end
63};
64
65void __init
66vrc5476_irq_init(u32 base)
67{
68 u32 i;
69
70 irq_base = base;
71 for (i= base; i< base + NUM_VRC5476_IRQ; i++) {
72 irq_desc[i].status = IRQ_DISABLED;
73 irq_desc[i].action = NULL;
74 irq_desc[i].depth = 1;
75 irq_desc[i].handler = &vrc5476_irq_controller;
76 }
77}
78
79
80void
81vrc5476_irq_dispatch(struct pt_regs *regs)
82{
83 u32 mask;
84 int nile4_irq;
85
86 mask = nile4_get_irq_stat(0);
87
88 /* quick check for possible time interrupt */
89 if (mask & (1 << VRC5476_IRQ_GPT)) {
90 do_IRQ(VRC5476_IRQ_BASE + VRC5476_IRQ_GPT, regs);
91 return;
92 }
93
94 /* check for i8259 interrupts */
95 if (mask & (1 << VRC5476_I8259_CASCADE)) {
96 int i8259_irq = nile4_i8259_iack();
97 do_IRQ(I8259_IRQ_BASE + i8259_irq, regs);
98 return;
99 }
100
101 /* regular nile4 interrupts (we should not really have any */
102 for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1) {
103 if (mask & 1) {
104 do_IRQ(VRC5476_IRQ_BASE + nile4_irq, regs);
105 return;
106 }
107 }
108 spurious_interrupt(regs);
109}
diff --git a/arch/mips/ddb5xxx/ddb5477/setup.c b/arch/mips/ddb5xxx/ddb5477/setup.c
index 2f566034cc44..93167ecdb424 100644
--- a/arch/mips/ddb5xxx/ddb5477/setup.c
+++ b/arch/mips/ddb5xxx/ddb5477/setup.c
@@ -171,7 +171,7 @@ static void ddb5477_board_init(void);
171extern struct pci_controller ddb5477_ext_controller; 171extern struct pci_controller ddb5477_ext_controller;
172extern struct pci_controller ddb5477_io_controller; 172extern struct pci_controller ddb5477_io_controller;
173 173
174void __init plat_setup(void) 174void __init plat_mem_setup(void)
175{ 175{
176 /* initialize board - we don't trust the loader */ 176 /* initialize board - we don't trust the loader */
177 ddb5477_board_init(); 177 ddb5477_board_init();
diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c
index ad5d436d80c1..9c707b9ceb65 100644
--- a/arch/mips/dec/setup.c
+++ b/arch/mips/dec/setup.c
@@ -147,7 +147,7 @@ static void __init dec_be_init(void)
147extern void dec_time_init(void); 147extern void dec_time_init(void);
148extern void dec_timer_setup(struct irqaction *); 148extern void dec_timer_setup(struct irqaction *);
149 149
150void __init plat_setup(void) 150void __init plat_mem_setup(void)
151{ 151{
152 board_be_init = dec_be_init; 152 board_be_init = dec_be_init;
153 board_time_init = dec_time_init; 153 board_time_init = dec_time_init;
diff --git a/arch/mips/dec/time.c b/arch/mips/dec/time.c
index 74cb055d4bf6..76e4d09ff4d2 100644
--- a/arch/mips/dec/time.c
+++ b/arch/mips/dec/time.c
@@ -181,7 +181,7 @@ void __init dec_time_init(void)
181 } 181 }
182 182
183 /* Set up the rate of periodic DS1287 interrupts. */ 183 /* Set up the rate of periodic DS1287 interrupts. */
184 CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - LOG_2_HZ), RTC_REG_A); 184 CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - __ffs(HZ)), RTC_REG_A);
185} 185}
186 186
187EXPORT_SYMBOL(do_settimeofday); 187EXPORT_SYMBOL(do_settimeofday);
diff --git a/arch/mips/defconfig b/arch/mips/defconfig
index 607e2985ffe3..879ba1ad99ca 100644
--- a/arch/mips/defconfig
+++ b/arch/mips/defconfig
@@ -41,8 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5074 is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
@@ -136,6 +134,15 @@ CONFIG_FLATMEM=y
136CONFIG_FLAT_NODE_MEM_MAP=y 134CONFIG_FLAT_NODE_MEM_MAP=y
137# CONFIG_SPARSEMEM_STATIC is not set 135# CONFIG_SPARSEMEM_STATIC is not set
138CONFIG_SPLIT_PTLOCK_CPUS=4 136CONFIG_SPLIT_PTLOCK_CPUS=4
137# CONFIG_HZ_48 is not set
138# CONFIG_HZ_100 is not set
139# CONFIG_HZ_128 is not set
140# CONFIG_HZ_250 is not set
141# CONFIG_HZ_256 is not set
142CONFIG_HZ_1000=y
143# CONFIG_HZ_1024 is not set
144CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
145CONFIG_HZ=1000
139# CONFIG_PREEMPT_NONE is not set 146# CONFIG_PREEMPT_NONE is not set
140CONFIG_PREEMPT_VOLUNTARY=y 147CONFIG_PREEMPT_VOLUNTARY=y
141# CONFIG_PREEMPT is not set 148# CONFIG_PREEMPT is not set
diff --git a/arch/mips/emma2rh/common/Makefile b/arch/mips/emma2rh/common/Makefile
new file mode 100644
index 000000000000..859121b3867d
--- /dev/null
+++ b/arch/mips/emma2rh/common/Makefile
@@ -0,0 +1,13 @@
1#
2# arch/mips/emma2rh/common/Makefile
3# Makefile for the common code of NEC EMMA2RH based board.
4#
5# Copyright (C) NEC Electronics Corporation 2005-2006
6#
7# This program is free software; you can redistribute it and/or modify
8# it under the terms of the GNU General Public License as published by
9# the Free Software Foundation; either version 2 of the License, or
10# (at your option) any later version.
11#
12
13obj-$(CONFIG_MARKEINS) += irq.o irq_emma2rh.o prom.o
diff --git a/arch/mips/emma2rh/common/irq.c b/arch/mips/emma2rh/common/irq.c
new file mode 100644
index 000000000000..b075281e50e9
--- /dev/null
+++ b/arch/mips/emma2rh/common/irq.c
@@ -0,0 +1,108 @@
1/*
2 * arch/mips/emma2rh/common/irq.c
3 * This file is common irq dispatcher.
4 *
5 * Copyright (C) NEC Electronics Corporation 2005-2006
6 *
7 * This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c
8 *
9 * Copyright 2001 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25#include <linux/config.h>
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/irq.h>
29#include <linux/types.h>
30
31#include <asm/i8259.h>
32#include <asm/system.h>
33#include <asm/mipsregs.h>
34#include <asm/debug.h>
35#include <asm/addrspace.h>
36#include <asm/bootinfo.h>
37
38#include <asm/emma2rh/emma2rh.h>
39
40/*
41 * the first level int-handler will jump here if it is a emma2rh irq
42 */
43asmlinkage void emma2rh_irq_dispatch(struct pt_regs *regs)
44{
45 u32 intStatus;
46 u32 bitmask;
47 u32 i;
48
49 intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_0)
50 & emma2rh_in32(EMMA2RH_BHIF_INT_EN_0);
51
52#ifdef EMMA2RH_SW_CASCADE
53 if (intStatus &
54 (1 << ((EMMA2RH_SW_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
55 u32 swIntStatus;
56 swIntStatus = emma2rh_in32(EMMA2RH_BHIF_SW_INT)
57 & emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
58 for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
59 if (swIntStatus & bitmask) {
60 do_IRQ(EMMA2RH_SW_IRQ_BASE + i, regs);
61 return;
62 }
63 }
64 }
65#endif
66
67 for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
68 if (intStatus & bitmask) {
69 do_IRQ(EMMA2RH_IRQ_BASE + i, regs);
70 return;
71 }
72 }
73
74 intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_1)
75 & emma2rh_in32(EMMA2RH_BHIF_INT_EN_1);
76
77#ifdef EMMA2RH_GPIO_CASCADE
78 if (intStatus &
79 (1 << ((EMMA2RH_GPIO_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
80 u32 gpioIntStatus;
81 gpioIntStatus = emma2rh_in32(EMMA2RH_GPIO_INT_ST)
82 & emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
83 for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
84 if (gpioIntStatus & bitmask) {
85 do_IRQ(EMMA2RH_GPIO_IRQ_BASE + i, regs);
86 return;
87 }
88 }
89 }
90#endif
91
92 for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) {
93 if (intStatus & bitmask) {
94 do_IRQ(EMMA2RH_IRQ_BASE + i, regs);
95 return;
96 }
97 }
98
99 intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_2)
100 & emma2rh_in32(EMMA2RH_BHIF_INT_EN_2);
101
102 for (i = 64, bitmask = 1; i < 96; i++, bitmask <<= 1) {
103 if (intStatus & bitmask) {
104 do_IRQ(EMMA2RH_IRQ_BASE + i, regs);
105 return;
106 }
107 }
108}
diff --git a/arch/mips/emma2rh/common/irq_emma2rh.c b/arch/mips/emma2rh/common/irq_emma2rh.c
new file mode 100644
index 000000000000..b886aa94ca90
--- /dev/null
+++ b/arch/mips/emma2rh/common/irq_emma2rh.c
@@ -0,0 +1,134 @@
1/*
2 * arch/mips/emma2rh/common/irq_emma2rh.c
3 * This file defines the irq handler for EMMA2RH.
4 *
5 * Copyright (C) NEC Electronics Corporation 2005-2006
6 *
7 * This file is based on the arch/mips/ddb5xxx/ddb5477/irq_5477.c
8 *
9 * Copyright 2001 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25
26/*
27 * EMMA2RH defines 64 IRQs.
28 *
29 * This file exports one function:
30 * emma2rh_irq_init(u32 irq_base);
31 */
32
33#include <linux/interrupt.h>
34#include <linux/types.h>
35#include <linux/ptrace.h>
36
37#include <asm/debug.h>
38
39#include <asm/emma2rh/emma2rh.h>
40
41/* number of total irqs supported by EMMA2RH */
42#define NUM_EMMA2RH_IRQ 96
43
44static int emma2rh_irq_base = -1;
45
46void ll_emma2rh_irq_enable(int);
47void ll_emma2rh_irq_disable(int);
48
49static void emma2rh_irq_enable(unsigned int irq)
50{
51 ll_emma2rh_irq_enable(irq - emma2rh_irq_base);
52}
53
54static void emma2rh_irq_disable(unsigned int irq)
55{
56 ll_emma2rh_irq_disable(irq - emma2rh_irq_base);
57}
58
59static unsigned int emma2rh_irq_startup(unsigned int irq)
60{
61 emma2rh_irq_enable(irq);
62 return 0;
63}
64
65#define emma2rh_irq_shutdown emma2rh_irq_disable
66
67static void emma2rh_irq_ack(unsigned int irq)
68{
69 /* disable interrupt - some handler will re-enable the irq
70 * and if the interrupt is leveled, we will have infinite loop
71 */
72 ll_emma2rh_irq_disable(irq - emma2rh_irq_base);
73}
74
75static void emma2rh_irq_end(unsigned int irq)
76{
77 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
78 ll_emma2rh_irq_enable(irq - emma2rh_irq_base);
79}
80
81hw_irq_controller emma2rh_irq_controller = {
82 .typename = "emma2rh_irq",
83 .startup = emma2rh_irq_startup,
84 .shutdown = emma2rh_irq_shutdown,
85 .enable = emma2rh_irq_enable,
86 .disable = emma2rh_irq_disable,
87 .ack = emma2rh_irq_ack,
88 .end = emma2rh_irq_end,
89 .set_affinity = NULL /* no affinity stuff for UP */
90};
91
92void emma2rh_irq_init(u32 irq_base)
93{
94 u32 i;
95
96 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ; i++) {
97 irq_desc[i].status = IRQ_DISABLED;
98 irq_desc[i].action = NULL;
99 irq_desc[i].depth = 1;
100 irq_desc[i].handler = &emma2rh_irq_controller;
101 }
102
103 emma2rh_irq_base = irq_base;
104}
105
106void ll_emma2rh_irq_enable(int emma2rh_irq)
107{
108 u32 reg_value;
109 u32 reg_bitmask;
110 u32 reg_index;
111
112 reg_index = EMMA2RH_BHIF_INT_EN_0
113 + (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0)
114 * (emma2rh_irq / 32);
115 reg_value = emma2rh_in32(reg_index);
116 reg_bitmask = 0x1 << (emma2rh_irq % 32);
117 db_assert((reg_value & reg_bitmask) == 0);
118 emma2rh_out32(reg_index, reg_value | reg_bitmask);
119}
120
121void ll_emma2rh_irq_disable(int emma2rh_irq)
122{
123 u32 reg_value;
124 u32 reg_bitmask;
125 u32 reg_index;
126
127 reg_index = EMMA2RH_BHIF_INT_EN_0
128 + (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0)
129 * (emma2rh_irq / 32);
130 reg_value = emma2rh_in32(reg_index);
131 reg_bitmask = 0x1 << (emma2rh_irq % 32);
132 db_assert((reg_value & reg_bitmask) != 0);
133 emma2rh_out32(reg_index, reg_value & ~reg_bitmask);
134}
diff --git a/arch/mips/emma2rh/common/prom.c b/arch/mips/emma2rh/common/prom.c
new file mode 100644
index 000000000000..8bba0b02a204
--- /dev/null
+++ b/arch/mips/emma2rh/common/prom.c
@@ -0,0 +1,77 @@
1/*
2 * arch/mips/emma2rh/common/prom.c
3 * This file is prom file.
4 *
5 * Copyright (C) NEC Electronics Corporation 2004-2006
6 *
7 * This file is based on the arch/mips/ddb5xxx/common/prom.c
8 *
9 * Copyright 2001 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25#include <linux/config.h>
26#include <linux/init.h>
27#include <linux/mm.h>
28#include <linux/sched.h>
29#include <linux/bootmem.h>
30
31#include <asm/addrspace.h>
32#include <asm/bootinfo.h>
33#include <asm/emma2rh/emma2rh.h>
34#include <asm/debug.h>
35
36const char *get_system_type(void)
37{
38 switch (mips_machtype) {
39 case MACH_NEC_MARKEINS:
40 return "NEC EMMA2RH Mark-eins";
41 default:
42 return "Unknown NEC board";
43 }
44}
45
46/* [jsun@junsun.net] PMON passes arguments in C main() style */
47void __init prom_init(void)
48{
49 int argc = fw_arg0;
50 char **arg = (char **)fw_arg1;
51 int i;
52
53 /* if user passes kernel args, ignore the default one */
54 if (argc > 1)
55 arcs_cmdline[0] = '\0';
56
57 /* arg[0] is "g", the rest is boot parameters */
58 for (i = 1; i < argc; i++) {
59 if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
60 >= sizeof(arcs_cmdline))
61 break;
62 strcat(arcs_cmdline, arg[i]);
63 strcat(arcs_cmdline, " ");
64 }
65
66 mips_machgroup = MACH_GROUP_NEC_EMMA2RH;
67
68#if defined(CONFIG_MARKEINS)
69 mips_machtype = MACH_NEC_MARKEINS;
70 add_memory_region(0, EMMA2RH_RAM_SIZE, BOOT_MEM_RAM);
71#endif
72
73}
74
75void __init prom_free_prom_memory(void)
76{
77}
diff --git a/arch/mips/emma2rh/markeins/Makefile b/arch/mips/emma2rh/markeins/Makefile
new file mode 100644
index 000000000000..14fc268b175c
--- /dev/null
+++ b/arch/mips/emma2rh/markeins/Makefile
@@ -0,0 +1,13 @@
1#
2# arch/mips/emma2rh/markeins/Makefile
3# Makefile for the common code of NEC EMMA2RH based board.
4#
5# Copyright (C) NEC Electronics Corporation 2005-2006
6#
7# This program is free software; you can redistribute it and/or modify
8# it under the terms of the GNU General Public License as published by
9# the Free Software Foundation; either version 2 of the License, or
10# (at your option) any later version.
11#
12
13obj-$(CONFIG_MARKEINS) += irq.o irq_markeins.o setup.o led.o platform.o
diff --git a/arch/mips/emma2rh/markeins/irq.c b/arch/mips/emma2rh/markeins/irq.c
new file mode 100644
index 000000000000..76dc3faeaf4e
--- /dev/null
+++ b/arch/mips/emma2rh/markeins/irq.c
@@ -0,0 +1,134 @@
1/*
2 * arch/mips/emma2rh/markeins/irq.c
3 * This file defines the irq handler for EMMA2RH.
4 *
5 * Copyright (C) NEC Electronics Corporation 2004-2006
6 *
7 * This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c
8 *
9 * Copyright 2001 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25#include <linux/config.h>
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/irq.h>
29#include <linux/types.h>
30#include <linux/ptrace.h>
31#include <linux/delay.h>
32
33#include <asm/i8259.h>
34#include <asm/irq_cpu.h>
35#include <asm/system.h>
36#include <asm/mipsregs.h>
37#include <asm/debug.h>
38#include <asm/addrspace.h>
39#include <asm/bootinfo.h>
40
41#include <asm/emma2rh/emma2rh.h>
42
43/*
44 * IRQ mapping
45 *
46 * 0-7: 8 CPU interrupts
47 * 0 - software interrupt 0
48 * 1 - software interrupt 1
49 * 2 - most Vrc5477 interrupts are routed to this pin
50 * 3 - (optional) some other interrupts routed to this pin for debugg
51 * 4 - not used
52 * 5 - not used
53 * 6 - not used
54 * 7 - cpu timer (used by default)
55 *
56 */
57
58extern void emma2rh_sw_irq_init(u32 base);
59extern void emma2rh_gpio_irq_init(u32 base);
60extern void emma2rh_irq_init(u32 base);
61extern asmlinkage void emma2rh_irq_dispatch(struct pt_regs *regs);
62
63static struct irqaction irq_cascade = {
64 .handler = no_action,
65 .flags = 0,
66 .mask = CPU_MASK_NONE,
67 .name = "cascade",
68 .dev_id = NULL,
69 .next = NULL,
70};
71
72void __init arch_init_irq(void)
73{
74 u32 reg;
75
76 db_run(printk("markeins_irq_setup invoked.\n"));
77
78 /* by default, interrupts are disabled. */
79 emma2rh_out32(EMMA2RH_BHIF_INT_EN_0, 0);
80 emma2rh_out32(EMMA2RH_BHIF_INT_EN_1, 0);
81 emma2rh_out32(EMMA2RH_BHIF_INT_EN_2, 0);
82 emma2rh_out32(EMMA2RH_BHIF_INT1_EN_0, 0);
83 emma2rh_out32(EMMA2RH_BHIF_INT1_EN_1, 0);
84 emma2rh_out32(EMMA2RH_BHIF_INT1_EN_2, 0);
85 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, 0);
86
87 clear_c0_status(0xff00);
88 set_c0_status(0x0400);
89
90#define GPIO_PCI (0xf<<15)
91 /* setup GPIO interrupt for PCI interface */
92 /* direction input */
93 reg = emma2rh_in32(EMMA2RH_GPIO_DIR);
94 emma2rh_out32(EMMA2RH_GPIO_DIR, reg & ~GPIO_PCI);
95 /* disable interrupt */
96 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
97 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg & ~GPIO_PCI);
98 /* level triggerd */
99 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MODE);
100 emma2rh_out32(EMMA2RH_GPIO_INT_MODE, reg | GPIO_PCI);
101 reg = emma2rh_in32(EMMA2RH_GPIO_INT_CND_A);
102 emma2rh_out32(EMMA2RH_GPIO_INT_CND_A, reg & (~GPIO_PCI));
103 /* interrupt clear */
104 emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~GPIO_PCI);
105
106 /* init all controllers */
107 emma2rh_irq_init(EMMA2RH_IRQ_BASE);
108 emma2rh_sw_irq_init(EMMA2RH_SW_IRQ_BASE);
109 emma2rh_gpio_irq_init(EMMA2RH_GPIO_IRQ_BASE);
110 mips_cpu_irq_init(CPU_IRQ_BASE);
111
112 /* setup cascade interrupts */
113 setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);
114 setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade);
115 setup_irq(CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade);
116}
117
118asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
119{
120 unsigned int pending = read_c0_status() & read_c0_cause();
121
122 if (pending & STATUSF_IP7)
123 do_IRQ(CPU_IRQ_BASE + 7, regs);
124 else if (pending & STATUSF_IP2)
125 emma2rh_irq_dispatch(regs);
126 else if (pending & STATUSF_IP1)
127 do_IRQ(CPU_IRQ_BASE + 1, regs);
128 else if (pending & STATUSF_IP0)
129 do_IRQ(CPU_IRQ_BASE + 0, regs);
130 else
131 spurious_interrupt(regs);
132}
133
134
diff --git a/arch/mips/emma2rh/markeins/irq_markeins.c b/arch/mips/emma2rh/markeins/irq_markeins.c
new file mode 100644
index 000000000000..1783fdab6459
--- /dev/null
+++ b/arch/mips/emma2rh/markeins/irq_markeins.c
@@ -0,0 +1,197 @@
1/*
2 * arch/mips/emma2rh/markeins/irq_markeins.c
3 * This file defines the irq handler for Mark-eins.
4 *
5 * Copyright (C) NEC Electronics Corporation 2004-2006
6 *
7 * This file is based on the arch/mips/ddb5xxx/ddb5477/irq_5477.c
8 *
9 * Copyright 2001 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/types.h>
28#include <linux/ptrace.h>
29
30#include <asm/debug.h>
31#include <asm/emma2rh/emma2rh.h>
32
33static int emma2rh_sw_irq_base = -1;
34static int emma2rh_gpio_irq_base = -1;
35
36void ll_emma2rh_sw_irq_enable(int reg);
37void ll_emma2rh_sw_irq_disable(int reg);
38void ll_emma2rh_gpio_irq_enable(int reg);
39void ll_emma2rh_gpio_irq_disable(int reg);
40
41static void emma2rh_sw_irq_enable(unsigned int irq)
42{
43 ll_emma2rh_sw_irq_enable(irq - emma2rh_sw_irq_base);
44}
45
46static void emma2rh_sw_irq_disable(unsigned int irq)
47{
48 ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base);
49}
50
51static unsigned int emma2rh_sw_irq_startup(unsigned int irq)
52{
53 emma2rh_sw_irq_enable(irq);
54 return 0;
55}
56
57#define emma2rh_sw_irq_shutdown emma2rh_sw_irq_disable
58
59static void emma2rh_sw_irq_ack(unsigned int irq)
60{
61 ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base);
62}
63
64static void emma2rh_sw_irq_end(unsigned int irq)
65{
66 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
67 ll_emma2rh_sw_irq_enable(irq - emma2rh_sw_irq_base);
68}
69
70hw_irq_controller emma2rh_sw_irq_controller = {
71 .typename = "emma2rh_sw_irq",
72 .startup = emma2rh_sw_irq_startup,
73 .shutdown = emma2rh_sw_irq_shutdown,
74 .enable = emma2rh_sw_irq_enable,
75 .disable = emma2rh_sw_irq_disable,
76 .ack = emma2rh_sw_irq_ack,
77 .end = emma2rh_sw_irq_end,
78 .set_affinity = NULL,
79};
80
81void emma2rh_sw_irq_init(u32 irq_base)
82{
83 u32 i;
84
85 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_SW; i++) {
86 irq_desc[i].status = IRQ_DISABLED;
87 irq_desc[i].action = NULL;
88 irq_desc[i].depth = 2;
89 irq_desc[i].handler = &emma2rh_sw_irq_controller;
90 }
91
92 emma2rh_sw_irq_base = irq_base;
93}
94
95void ll_emma2rh_sw_irq_enable(int irq)
96{
97 u32 reg;
98
99 db_assert(irq >= 0);
100 db_assert(irq < NUM_EMMA2RH_IRQ_SW);
101
102 reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
103 reg |= 1 << irq;
104 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
105}
106
107void ll_emma2rh_sw_irq_disable(int irq)
108{
109 u32 reg;
110
111 db_assert(irq >= 0);
112 db_assert(irq < 32);
113
114 reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
115 reg &= ~(1 << irq);
116 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
117}
118
119static void emma2rh_gpio_irq_enable(unsigned int irq)
120{
121 ll_emma2rh_gpio_irq_enable(irq - emma2rh_gpio_irq_base);
122}
123
124static void emma2rh_gpio_irq_disable(unsigned int irq)
125{
126 ll_emma2rh_gpio_irq_disable(irq - emma2rh_gpio_irq_base);
127}
128
129static unsigned int emma2rh_gpio_irq_startup(unsigned int irq)
130{
131 emma2rh_gpio_irq_enable(irq);
132 return 0;
133}
134
135#define emma2rh_gpio_irq_shutdown emma2rh_gpio_irq_disable
136
137static void emma2rh_gpio_irq_ack(unsigned int irq)
138{
139 irq -= emma2rh_gpio_irq_base;
140 emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
141 ll_emma2rh_gpio_irq_disable(irq);
142}
143
144static void emma2rh_gpio_irq_end(unsigned int irq)
145{
146 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
147 ll_emma2rh_gpio_irq_enable(irq - emma2rh_gpio_irq_base);
148}
149
150hw_irq_controller emma2rh_gpio_irq_controller = {
151 .typename = "emma2rh_gpio_irq",
152 .startup = emma2rh_gpio_irq_startup,
153 .shutdown = emma2rh_gpio_irq_shutdown,
154 .enable = emma2rh_gpio_irq_enable,
155 .disable = emma2rh_gpio_irq_disable,
156 .ack = emma2rh_gpio_irq_ack,
157 .end = emma2rh_gpio_irq_end,
158 .set_affinity = NULL,
159};
160
161void emma2rh_gpio_irq_init(u32 irq_base)
162{
163 u32 i;
164
165 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_GPIO; i++) {
166 irq_desc[i].status = IRQ_DISABLED;
167 irq_desc[i].action = NULL;
168 irq_desc[i].depth = 2;
169 irq_desc[i].handler = &emma2rh_gpio_irq_controller;
170 }
171
172 emma2rh_gpio_irq_base = irq_base;
173}
174
175void ll_emma2rh_gpio_irq_enable(int irq)
176{
177 u32 reg;
178
179 db_assert(irq >= 0);
180 db_assert(irq < NUM_EMMA2RH_IRQ_GPIO);
181
182 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
183 reg |= 1 << irq;
184 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
185}
186
187void ll_emma2rh_gpio_irq_disable(int irq)
188{
189 u32 reg;
190
191 db_assert(irq >= 0);
192 db_assert(irq < NUM_EMMA2RH_IRQ_GPIO);
193
194 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
195 reg &= ~(1 << irq);
196 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
197}
diff --git a/arch/mips/emma2rh/markeins/led.c b/arch/mips/emma2rh/markeins/led.c
new file mode 100644
index 000000000000..b65254c1bfe9
--- /dev/null
+++ b/arch/mips/emma2rh/markeins/led.c
@@ -0,0 +1,60 @@
1/*
2 * arch/mips/emma2rh/markeins/led.c
3 * This file defines the led display for Mark-eins.
4 *
5 * Copyright (C) NEC Electronics Corporation 2004-2006
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/string.h>
24#include <asm/emma2rh/emma2rh.h>
25
26const unsigned long clear = 0x20202020;
27
28#define LED_BASE 0xb1400038
29
30void markeins_led_clear(void)
31{
32 emma2rh_out32(LED_BASE, clear);
33 emma2rh_out32(LED_BASE + 4, clear);
34}
35
36void markeins_led(const char *str)
37{
38 int i;
39 int len = strlen(str);
40
41 markeins_led_clear();
42 if (len > 8)
43 len = 8;
44
45 if (emma2rh_in32(0xb0000800) & (0x1 << 18))
46 for (i = 0; i < len; i++)
47 emma2rh_out8(LED_BASE + i, str[i]);
48 else
49 for (i = 0; i < len; i++)
50 emma2rh_out8(LED_BASE + (i & 4) + (3 - (i & 3)),
51 str[i]);
52}
53
54void markeins_led_hex(u32 val)
55{
56 char str[10];
57
58 sprintf(str, "%08x", val);
59 markeins_led(str);
60}
diff --git a/arch/mips/emma2rh/markeins/platform.c b/arch/mips/emma2rh/markeins/platform.c
new file mode 100644
index 000000000000..6c1eeae1a898
--- /dev/null
+++ b/arch/mips/emma2rh/markeins/platform.c
@@ -0,0 +1,170 @@
1/*
2 * arch/mips/emma2rh/markeins/platofrm.c
3 * This file sets up platform devices for EMMA2RH Mark-eins.
4 *
5 * Copyright(C) MontaVista Software Inc, 2006
6 *
7 * Author: dmitry pervushin <dpervushin@ru.mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23#include <linux/config.h>
24#include <linux/init.h>
25#include <linux/kernel.h>
26#include <linux/types.h>
27#include <linux/ioport.h>
28#include <linux/serial_8250.h>
29#include <linux/mtd/physmap.h>
30
31#include <asm/cpu.h>
32#include <asm/bootinfo.h>
33#include <asm/addrspace.h>
34#include <asm/time.h>
35#include <asm/bcache.h>
36#include <asm/irq.h>
37#include <asm/reboot.h>
38#include <asm/gdb-stub.h>
39#include <asm/traps.h>
40#include <asm/debug.h>
41
42#include <asm/emma2rh/emma2rh.h>
43
44
45#define I2C_EMMA2RH "emma2rh-iic" /* must be in sync with IIC driver */
46
47static struct resource i2c_emma_resources_0[] = {
48 { NULL, EMMA2RH_IRQ_PIIC0, EMMA2RH_IRQ_PIIC0, IORESOURCE_IRQ },
49 { NULL, KSEG1ADDR(EMMA2RH_PIIC0_BASE), KSEG1ADDR(EMMA2RH_PIIC0_BASE + 0x1000), 0 },
50};
51
52struct resource i2c_emma_resources_1[] = {
53 { NULL, EMMA2RH_IRQ_PIIC1, EMMA2RH_IRQ_PIIC1, IORESOURCE_IRQ },
54 { NULL, KSEG1ADDR(EMMA2RH_PIIC1_BASE), KSEG1ADDR(EMMA2RH_PIIC1_BASE + 0x1000), 0 },
55};
56
57struct resource i2c_emma_resources_2[] = {
58 { NULL, EMMA2RH_IRQ_PIIC2, EMMA2RH_IRQ_PIIC2, IORESOURCE_IRQ },
59 { NULL, KSEG1ADDR(EMMA2RH_PIIC2_BASE), KSEG1ADDR(EMMA2RH_PIIC2_BASE + 0x1000), 0 },
60};
61
62struct platform_device i2c_emma_devices[] = {
63 [0] = {
64 .name = I2C_EMMA2RH,
65 .id = 0,
66 .resource = i2c_emma_resources_0,
67 .num_resources = ARRAY_SIZE(i2c_emma_resources_0),
68 },
69 [1] = {
70 .name = I2C_EMMA2RH,
71 .id = 1,
72 .resource = i2c_emma_resources_1,
73 .num_resources = ARRAY_SIZE(i2c_emma_resources_1),
74 },
75 [2] = {
76 .name = I2C_EMMA2RH,
77 .id = 2,
78 .resource = i2c_emma_resources_2,
79 .num_resources = ARRAY_SIZE(i2c_emma_resources_2),
80 },
81};
82
83#define EMMA2RH_SERIAL_CLOCK 18544000
84#define EMMA2RH_SERIAL_FLAGS UPF_BOOT_AUTOCONF | UPF_SKIP_TEST
85
86static struct plat_serial8250_port platform_serial_ports[] = {
87 [0] = {
88 .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR0_BASE + 3),
89 .irq = EMMA2RH_IRQ_PFUR0,
90 .uartclk = EMMA2RH_SERIAL_CLOCK,
91 .regshift = 4,
92 .iotype = UPIO_MEM,
93 .flags = EMMA2RH_SERIAL_FLAGS,
94 },
95 [1] = {
96 .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR1_BASE + 3),
97 .irq = EMMA2RH_IRQ_PFUR1,
98 .uartclk = EMMA2RH_SERIAL_CLOCK,
99 .regshift = 4,
100 .iotype = UPIO_MEM,
101 .flags = EMMA2RH_SERIAL_FLAGS,
102 },
103 [2] = {
104 .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR2_BASE + 3),
105 .irq = EMMA2RH_IRQ_PFUR2,
106 .uartclk = EMMA2RH_SERIAL_CLOCK,
107 .regshift = 4,
108 .iotype = UPIO_MEM,
109 .flags = EMMA2RH_SERIAL_FLAGS,
110 },
111 [3] = {
112 .flags = 0,
113 },
114};
115
116static struct platform_device serial_emma = {
117 .name = "serial8250",
118 .dev = {
119 .platform_data = &platform_serial_ports,
120 },
121};
122
123static struct platform_device *devices[] = {
124 &i2c_emma_devices[0],
125 &i2c_emma_devices[1],
126 &i2c_emma_devices[2],
127 &serial_emma,
128};
129
130static struct mtd_partition markeins_parts[] = {
131 [0] = {
132 .name = "RootFS",
133 .offset = 0x00000000,
134 .size = 0x00c00000,
135 },
136 [1] = {
137 .name = "boot code area",
138 .offset = MTDPART_OFS_APPEND,
139 .size = 0x00100000,
140 },
141 [2] = {
142 .name = "kernel image",
143 .offset = MTDPART_OFS_APPEND,
144 .size = 0x00300000,
145 },
146 [3] = {
147 .name = "RootFS2",
148 .offset = MTDPART_OFS_APPEND,
149 .size = 0x00c00000,
150 },
151 [4] = {
152 .name = "boot code area2",
153 .offset = MTDPART_OFS_APPEND,
154 .size = 0x00100000,
155 },
156 [5] = {
157 .name = "kernel image2",
158 .offset = MTDPART_OFS_APPEND,
159 .size = MTDPART_SIZ_FULL,
160 },
161};
162
163static int __init platform_devices_setup(void)
164{
165 physmap_set_partitions(markeins_parts, ARRAY_SIZE(markeins_parts));
166 return platform_add_devices(devices, ARRAY_SIZE(devices));
167}
168
169arch_initcall(platform_devices_setup);
170
diff --git a/arch/mips/emma2rh/markeins/setup.c b/arch/mips/emma2rh/markeins/setup.c
new file mode 100644
index 000000000000..7d98fdbf8390
--- /dev/null
+++ b/arch/mips/emma2rh/markeins/setup.c
@@ -0,0 +1,182 @@
1/*
2 * arch/mips/emma2rh/markeins/setup.c
3 * This file is setup for EMMA2RH Mark-eins.
4 *
5 * Copyright (C) NEC Electronics Corporation 2004-2006
6 *
7 * This file is based on the arch/mips/ddb5xxx/ddb5477/setup.c.
8 *
9 * Copyright 2001 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25#include <linux/config.h>
26#include <linux/init.h>
27#include <linux/kernel.h>
28#include <linux/types.h>
29#include <linux/initrd.h>
30#include <linux/irq.h>
31#include <linux/ide.h>
32#include <linux/ioport.h>
33#include <linux/param.h> /* for HZ */
34#include <linux/root_dev.h>
35#include <linux/serial.h>
36#include <linux/serial_core.h>
37
38#include <asm/cpu.h>
39#include <asm/bootinfo.h>
40#include <asm/addrspace.h>
41#include <asm/time.h>
42#include <asm/bcache.h>
43#include <asm/irq.h>
44#include <asm/reboot.h>
45#include <asm/gdb-stub.h>
46#include <asm/traps.h>
47#include <asm/debug.h>
48
49#include <asm/emma2rh/emma2rh.h>
50
51#define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */
52
53extern void markeins_led(const char *);
54
55static int bus_frequency = 0;
56
57static void markeins_machine_restart(char *command)
58{
59 static void (*back_to_prom) (void) = (void (*)(void))0xbfc00000;
60
61 printk("cannot EMMA2RH Mark-eins restart.\n");
62 markeins_led("restart.");
63 back_to_prom();
64}
65
66static void markeins_machine_halt(void)
67{
68 printk("EMMA2RH Mark-eins halted.\n");
69 markeins_led("halted.");
70 while (1) ;
71}
72
73static void markeins_machine_power_off(void)
74{
75 printk("EMMA2RH Mark-eins halted. Please turn off the power.\n");
76 markeins_led("poweroff.");
77 while (1) ;
78}
79
80static unsigned long clock[4] = { 166500000, 187312500, 199800000, 210600000 };
81
82static unsigned int __init detect_bus_frequency(unsigned long rtc_base)
83{
84 u32 reg;
85
86 /* detect from boot strap */
87 reg = emma2rh_in32(EMMA2RH_BHIF_STRAP_0);
88 reg = (reg >> 4) & 0x3;
89 return clock[reg];
90}
91
92static void __init emma2rh_time_init(void)
93{
94 u32 reg;
95 if (bus_frequency == 0)
96 bus_frequency = detect_bus_frequency(0);
97
98 reg = emma2rh_in32(EMMA2RH_BHIF_STRAP_0);
99 if ((reg & 0x3) == 0)
100 reg = (reg >> 6) & 0x3;
101 else {
102 reg = emma2rh_in32(EMMA2RH_BHIF_MAIN_CTRL);
103 reg = (reg >> 4) & 0x3;
104 }
105 mips_hpt_frequency = (bus_frequency * (4 + reg)) / 4 / 2;
106}
107
108static void __init emma2rh_timer_setup(struct irqaction *irq)
109{
110 /* we are using the cpu counter for timer interrupts */
111 setup_irq(CPU_IRQ_BASE + 7, irq);
112}
113
114static void markeins_board_init(void);
115extern void markeins_irq_setup(void);
116
117static void inline __init markeins_sio_setup(void)
118{
119#ifdef CONFIG_KGDB_8250
120 struct uart_port emma_port;
121
122 memset(&emma_port, 0, sizeof(emma_port));
123
124 emma_port.flags =
125 UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
126 emma_port.iotype = UPIO_MEM;
127 emma_port.regshift = 4; /* I/O addresses are every 8 bytes */
128 emma_port.uartclk = 18544000; /* Clock rate of the chip */
129
130 emma_port.line = 0;
131 emma_port.mapbase = KSEG1ADDR(EMMA2RH_PFUR0_BASE + 3);
132 emma_port.membase = (u8*)emma_port.mapbase;
133 early_serial_setup(&emma_port);
134
135 emma_port.line = 1;
136 emma_port.mapbase = KSEG1ADDR(EMMA2RH_PFUR1_BASE + 3);
137 emma_port.membase = (u8*)emma_port.mapbase;
138 early_serial_setup(&emma_port);
139
140 emma_port.irq = EMMA2RH_IRQ_PFUR1;
141 kgdb8250_add_port(1, &emma_port);
142#endif
143}
144
145void __init plat_mem_setup(void)
146{
147 /* initialize board - we don't trust the loader */
148 markeins_board_init();
149
150 set_io_port_base(KSEG1ADDR(EMMA2RH_PCI_IO_BASE));
151
152 board_time_init = emma2rh_time_init;
153 board_timer_setup = emma2rh_timer_setup;
154
155 _machine_restart = markeins_machine_restart;
156 _machine_halt = markeins_machine_halt;
157 pm_power_off = markeins_machine_power_off;
158
159 /* setup resource limits */
160 ioport_resource.start = EMMA2RH_PCI_IO_BASE;
161 ioport_resource.end = EMMA2RH_PCI_IO_BASE + EMMA2RH_PCI_IO_SIZE - 1;
162 iomem_resource.start = EMMA2RH_IO_BASE;
163 iomem_resource.end = EMMA2RH_ROM_BASE - 1;
164
165 /* Reboot on panic */
166 panic_timeout = 180;
167
168 markeins_sio_setup();
169}
170
171static void __init markeins_board_init(void)
172{
173 u32 val;
174
175 val = emma2rh_in32(EMMA2RH_PBRD_INT_EN); /* open serial interrupts. */
176 emma2rh_out32(EMMA2RH_PBRD_INT_EN, val | 0xaa);
177 val = emma2rh_in32(EMMA2RH_PBRD_CLKSEL); /* set serial clocks. */
178 emma2rh_out32(EMMA2RH_PBRD_CLKSEL, val | 0x5); /* 18MHz */
179 emma2rh_out32(EMMA2RH_PCI_CONTROL, 0);
180
181 markeins_led("MVL E2RH");
182}
diff --git a/arch/mips/galileo-boards/ev96100/setup.c b/arch/mips/galileo-boards/ev96100/setup.c
index 78dbb18edeb8..a04aea6123da 100644
--- a/arch/mips/galileo-boards/ev96100/setup.c
+++ b/arch/mips/galileo-boards/ev96100/setup.c
@@ -55,7 +55,7 @@ extern void mips_reboot_setup(void);
55 55
56unsigned char mac_0_1[12]; 56unsigned char mac_0_1[12];
57 57
58void __init plat_setup(void) 58void __init plat_mem_setup(void)
59{ 59{
60 unsigned int config = read_c0_config(); 60 unsigned int config = read_c0_config();
61 unsigned int status = read_c0_status(); 61 unsigned int status = read_c0_status();
diff --git a/arch/mips/gt64120/ev64120/setup.c b/arch/mips/gt64120/ev64120/setup.c
index 6d859d1e7a2d..4236da31ecc6 100644
--- a/arch/mips/gt64120/ev64120/setup.c
+++ b/arch/mips/gt64120/ev64120/setup.c
@@ -71,7 +71,7 @@ unsigned long __init prom_free_prom_memory(void)
71 */ 71 */
72extern void gt64120_time_init(void); 72extern void gt64120_time_init(void);
73 73
74void __init plat_setup(void) 74void __init plat_mem_setup(void)
75{ 75{
76 _machine_restart = galileo_machine_restart; 76 _machine_restart = galileo_machine_restart;
77 _machine_halt = galileo_machine_halt; 77 _machine_halt = galileo_machine_halt;
diff --git a/arch/mips/gt64120/momenco_ocelot/setup.c b/arch/mips/gt64120/momenco_ocelot/setup.c
index 20b65d3d2151..1193a22c4693 100644
--- a/arch/mips/gt64120/momenco_ocelot/setup.c
+++ b/arch/mips/gt64120/momenco_ocelot/setup.c
@@ -152,7 +152,7 @@ void PMON_v2_setup()
152 gt64120_base = 0xe0000000; 152 gt64120_base = 0xe0000000;
153} 153}
154 154
155void __init plat_setup(void) 155void __init plat_mem_setup(void)
156{ 156{
157 void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache); 157 void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache);
158 unsigned int tmpword; 158 unsigned int tmpword;
diff --git a/arch/mips/gt64120/wrppmc/Makefile b/arch/mips/gt64120/wrppmc/Makefile
new file mode 100644
index 000000000000..72606b9af12a
--- /dev/null
+++ b/arch/mips/gt64120/wrppmc/Makefile
@@ -0,0 +1,14 @@
1#
2# This file is subject to the terms and conditions of the GNU General Public
3# License. See the file "COPYING" in the main directory of this archive
4# for more details.
5#
6# Copyright 2006 Wind River System, Inc.
7# Author: Rongkai.Zhan <rongkai.zhan@windriver.com>
8#
9# Makefile for the Wind River MIPS 4KC PPMC Eval Board
10#
11
12obj-y += int-handler.o irq.o reset.o setup.o time.o pci.o
13
14EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/gt64120/wrppmc/int-handler.S b/arch/mips/gt64120/wrppmc/int-handler.S
new file mode 100644
index 000000000000..edee7b394175
--- /dev/null
+++ b/arch/mips/gt64120/wrppmc/int-handler.S
@@ -0,0 +1,59 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1995, 1996, 1997, 2003 by Ralf Baechle
7 * Copyright (C) Wind River System Inc. Rongkai.Zhan <rongkai.zhan@windriver.com>
8 */
9#include <asm/asm.h>
10#include <asm/mipsregs.h>
11#include <asm/addrspace.h>
12#include <asm/regdef.h>
13#include <asm/stackframe.h>
14#include <asm/mach-wrppmc/mach-gt64120.h>
15
16 .align 5
17 .set noat
18NESTED(handle_IRQ, PT_SIZE, sp)
19 SAVE_ALL
20 CLI # Important: mark KERNEL mode !
21 .set at
22
23 mfc0 t0, CP0_CAUSE # get pending interrupts
24 mfc0 t1, CP0_STATUS # get enabled interrupts
25 and t0, t0, t1 # get allowed interrupts
26 andi t0, t0, 0xFF00
27 beqz t0, 1f
28 move a1, sp # Prepare 'struct pt_regs *regs' pointer
29
30 andi t1, t0, CAUSEF_IP7 # CPU Compare/Count internal timer
31 bnez t1, handle_cputimer_irq
32 andi t1, t0, CAUSEF_IP6 # UART 16550 port
33 bnez t1, handle_uart_irq
34 andi t1, t0, CAUSEF_IP3 # PCI INT_A
35 bnez t1, handle_pci_intA_irq
36
37 /* wrong alarm or masked ... */
381: j spurious_interrupt
39 nop
40END(handle_IRQ)
41
42 .align 5
43handle_cputimer_irq:
44 li a0, WRPPMC_MIPS_TIMER_IRQ
45 jal do_IRQ
46 j ret_from_irq
47
48 .align 5
49handle_uart_irq:
50 li a0, WRPPMC_UART16550_IRQ
51 jal do_IRQ
52 j ret_from_irq
53
54 .align 5
55handle_pci_intA_irq:
56 li a0, WRPPMC_PCI_INTA_IRQ
57 jal do_IRQ
58 j ret_from_irq
59
diff --git a/arch/mips/gt64120/wrppmc/irq.c b/arch/mips/gt64120/wrppmc/irq.c
new file mode 100644
index 000000000000..8605687e24ed
--- /dev/null
+++ b/arch/mips/gt64120/wrppmc/irq.c
@@ -0,0 +1,63 @@
1/*
2 * irq.c: GT64120 Interrupt Controller
3 *
4 * Copyright (C) 2006, Wind River System Inc.
5 * Author: Rongkai.Zhan, <rongkai.zhan@windriver.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12#include <linux/errno.h>
13#include <linux/init.h>
14#include <linux/kernel_stat.h>
15#include <linux/module.h>
16#include <linux/signal.h>
17#include <linux/sched.h>
18#include <linux/types.h>
19#include <linux/interrupt.h>
20#include <linux/ioport.h>
21#include <linux/timex.h>
22#include <linux/slab.h>
23#include <linux/random.h>
24#include <linux/bitops.h>
25#include <asm/bootinfo.h>
26#include <asm/io.h>
27#include <asm/bitops.h>
28#include <asm/mipsregs.h>
29#include <asm/system.h>
30#include <asm/irq_cpu.h>
31#include <asm/gt64120.h>
32
33extern asmlinkage void handle_IRQ(void);
34
35/**
36 * Initialize GT64120 Interrupt Controller
37 */
38void gt64120_init_pic(void)
39{
40 /* clear CPU Interrupt Cause Registers */
41 GT_WRITE(GT_INTRCAUSE_OFS, (0x1F << 21));
42 GT_WRITE(GT_HINTRCAUSE_OFS, 0x00);
43
44 /* Disable all interrupts from GT64120 bridge chip */
45 GT_WRITE(GT_INTRMASK_OFS, 0x00);
46 GT_WRITE(GT_HINTRMASK_OFS, 0x00);
47 GT_WRITE(GT_PCI0_ICMASK_OFS, 0x00);
48 GT_WRITE(GT_PCI0_HICMASK_OFS, 0x00);
49}
50
51void __init arch_init_irq(void)
52{
53 /* enable all CPU interrupt bits. */
54 set_c0_status(ST0_IM); /* IE bit is still 0 */
55
56 /* Install MIPS Interrupt Trap Vector */
57 set_except_vector(0, handle_IRQ);
58
59 /* IRQ 0 - 7 are for MIPS common irq_cpu controller */
60 mips_cpu_irq_init(0);
61
62 gt64120_init_pic();
63}
diff --git a/arch/mips/gt64120/wrppmc/pci.c b/arch/mips/gt64120/wrppmc/pci.c
new file mode 100644
index 000000000000..2fbe93467f78
--- /dev/null
+++ b/arch/mips/gt64120/wrppmc/pci.c
@@ -0,0 +1,53 @@
1/*
2 * pci.c: GT64120 PCI support.
3 *
4 * Copyright (C) 2006, Wind River System Inc. Rongkai.Zhan <rongkai.zhan@windriver.com>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/init.h>
11#include <linux/types.h>
12#include <linux/pci.h>
13#include <linux/kernel.h>
14#include <asm/gt64120.h>
15
16extern struct pci_ops gt64120_pci_ops;
17
18static struct resource pci0_io_resource = {
19 .name = "pci_0 io",
20 .start = GT_PCI_IO_BASE,
21 .end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1,
22 .flags = IORESOURCE_IO,
23};
24
25static struct resource pci0_mem_resource = {
26 .name = "pci_0 memory",
27 .start = GT_PCI_MEM_BASE,
28 .end = GT_PCI_MEM_BASE + GT_PCI_MEM_SIZE - 1,
29 .flags = IORESOURCE_MEM,
30};
31
32static struct pci_controller hose_0 = {
33 .pci_ops = &gt64120_pci_ops,
34 .io_resource = &pci0_io_resource,
35 .mem_resource = &pci0_mem_resource,
36};
37
38static int __init gt64120_pci_init(void)
39{
40 u32 tmp;
41
42 tmp = GT_READ(GT_PCI0_CMD_OFS); /* Huh??? -- Ralf */
43 tmp = GT_READ(GT_PCI0_BARE_OFS);
44
45 /* reset the whole PCI I/O space range */
46 ioport_resource.start = GT_PCI_IO_BASE;
47 ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1;
48
49 register_pci_controller(&hose_0);
50 return 0;
51}
52
53arch_initcall(gt64120_pci_init);
diff --git a/arch/mips/gt64120/wrppmc/reset.c b/arch/mips/gt64120/wrppmc/reset.c
new file mode 100644
index 000000000000..b97039c6d3db
--- /dev/null
+++ b/arch/mips/gt64120/wrppmc/reset.c
@@ -0,0 +1,50 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1997 Ralf Baechle
7 */
8#include <linux/sched.h>
9#include <linux/mm.h>
10#include <asm/io.h>
11#include <asm/pgtable.h>
12#include <asm/processor.h>
13#include <asm/reboot.h>
14#include <asm/system.h>
15#include <asm/cacheflush.h>
16
17void wrppmc_machine_restart(char *command)
18{
19 /*
20 * Ouch, we're still alive ... This time we take the silver bullet ...
21 * ... and find that we leave the hardware in a state in which the
22 * kernel in the flush locks up somewhen during of after the PCI
23 * detection stuff.
24 */
25 local_irq_disable();
26 set_c0_status(ST0_BEV | ST0_ERL);
27 change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
28 flush_cache_all();
29 write_c0_wired(0);
30 __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
31}
32
33void wrppmc_machine_halt(void)
34{
35 local_irq_disable();
36
37 printk(KERN_NOTICE "You can safely turn off the power\n");
38 while (1) {
39 __asm__(
40 ".set\tmips3\n\t"
41 "wait\n\t"
42 ".set\tmips0"
43 );
44 }
45}
46
47void wrppmc_machine_power_off(void)
48{
49 wrppmc_machine_halt();
50}
diff --git a/arch/mips/gt64120/wrppmc/setup.c b/arch/mips/gt64120/wrppmc/setup.c
new file mode 100644
index 000000000000..20c591e49dae
--- /dev/null
+++ b/arch/mips/gt64120/wrppmc/setup.c
@@ -0,0 +1,173 @@
1/*
2 * setup.c: Setup pointers to hardware dependent routines.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1996, 1997, 2004 by Ralf Baechle (ralf@linux-mips.org)
9 * Copyright (C) 2006, Wind River System Inc. Rongkai.zhan <rongkai.zhan@windriver.com>
10 */
11#include <linux/config.h>
12#include <linux/init.h>
13#include <linux/string.h>
14#include <linux/kernel.h>
15#include <linux/tty.h>
16#include <linux/serial.h>
17#include <linux/serial_core.h>
18#include <linux/pm.h>
19
20#include <asm/io.h>
21#include <asm/bootinfo.h>
22#include <asm/reboot.h>
23#include <asm/time.h>
24#include <asm/gt64120.h>
25
26unsigned long gt64120_base = KSEG1ADDR(0x14000000);
27
28#ifdef WRPPMC_EARLY_DEBUG
29
30static volatile unsigned char * wrppmc_led = \
31 (volatile unsigned char *)KSEG1ADDR(WRPPMC_LED_BASE);
32
33/*
34 * PPMC LED control register:
35 * -) bit[0] controls DS1 LED (1 - OFF, 0 - ON)
36 * -) bit[1] controls DS2 LED (1 - OFF, 0 - ON)
37 * -) bit[2] controls DS4 LED (1 - OFF, 0 - ON)
38 */
39void wrppmc_led_on(int mask)
40{
41 unsigned char value = *wrppmc_led;
42
43 value &= (0xF8 | mask);
44 *wrppmc_led = value;
45}
46
47/* If mask = 0, turn off all LEDs */
48void wrppmc_led_off(int mask)
49{
50 unsigned char value = *wrppmc_led;
51
52 value |= (0x7 & mask);
53 *wrppmc_led = value;
54}
55
56/*
57 * We assume that bootloader has initialized UART16550 correctly
58 */
59void __init wrppmc_early_putc(char ch)
60{
61 static volatile unsigned char *wrppmc_uart = \
62 (volatile unsigned char *)KSEG1ADDR(WRPPMC_UART16550_BASE);
63 unsigned char value;
64
65 /* Wait until Transmit-Holding-Register is empty */
66 while (1) {
67 value = *(wrppmc_uart + 5);
68 if (value & 0x20)
69 break;
70 }
71
72 *wrppmc_uart = ch;
73}
74
75void __init wrppmc_early_printk(const char *fmt, ...)
76{
77 static char pbuf[256] = {'\0', };
78 char *ch = pbuf;
79 va_list args;
80 unsigned int i;
81
82 memset(pbuf, 0, 256);
83 va_start(args, fmt);
84 i = vsprintf(pbuf, fmt, args);
85 va_end(args);
86
87 /* Print the string */
88 while (*ch != '\0') {
89 wrppmc_early_putc(*ch);
90 /* if print '\n', also print '\r' */
91 if (*ch++ == '\n')
92 wrppmc_early_putc('\r');
93 }
94}
95#endif /* WRPPMC_EARLY_DEBUG */
96
97unsigned long __init prom_free_prom_memory(void)
98{
99 return 0;
100}
101
102#ifdef CONFIG_SERIAL_8250
103static void wrppmc_setup_serial(void)
104{
105 struct uart_port up;
106
107 memset(&up, 0x00, sizeof(struct uart_port));
108
109 /*
110 * A note about mapbase/membase
111 * -) mapbase is the physical address of the IO port.
112 * -) membase is an 'ioremapped' cookie.
113 */
114 up.line = 0;
115 up.type = PORT_16550;
116 up.iotype = UPIO_MEM;
117 up.mapbase = WRPPMC_UART16550_BASE;
118 up.membase = ioremap(up.mapbase, 8);
119 up.irq = WRPPMC_UART16550_IRQ;
120 up.uartclk = WRPPMC_UART16550_CLOCK;
121 up.flags = UPF_SKIP_TEST/* | UPF_BOOT_AUTOCONF */;
122 up.regshift = 0;
123
124 early_serial_setup(&up);
125}
126#endif
127
128void __init plat_setup(void)
129{
130 extern void wrppmc_time_init(void);
131 extern void wrppmc_timer_setup(struct irqaction *);
132 extern void wrppmc_machine_restart(char *command);
133 extern void wrppmc_machine_halt(void);
134 extern void wrppmc_machine_power_off(void);
135
136 _machine_restart = wrppmc_machine_restart;
137 _machine_halt = wrppmc_machine_halt;
138 pm_power_off = wrppmc_machine_power_off;
139
140 /* Use MIPS Count/Compare Timer */
141 board_time_init = wrppmc_time_init;
142 board_timer_setup = wrppmc_timer_setup;
143
144 /* This makes the operations of 'in/out[bwl]' to the
145 * physical address ( < KSEG0) can work via KSEG1
146 */
147 set_io_port_base(KSEG1);
148
149#ifdef CONFIG_SERIAL_8250
150 wrppmc_setup_serial();
151#endif
152}
153
154const char *get_system_type(void)
155{
156 return "Wind River PPMC (GT64120)";
157}
158
159/*
160 * Initializes basic routines and structures pointers, memory size (as
161 * given by the bios and saves the command line.
162 */
163void __init prom_init(void)
164{
165 mips_machgroup = MACH_GROUP_GALILEO;
166 mips_machtype = MACH_EV64120A;
167
168 add_memory_region(WRPPMC_SDRAM_SCS0_BASE, WRPPMC_SDRAM_SCS0_SIZE, BOOT_MEM_RAM);
169 add_memory_region(WRPPMC_BOOTROM_BASE, WRPPMC_BOOTROM_SIZE, BOOT_MEM_ROM_DATA);
170
171 wrppmc_early_printk("prom_init: GT64120 SDRAM Bank 0: 0x%x - 0x%08lx\n",
172 WRPPMC_SDRAM_SCS0_BASE, (WRPPMC_SDRAM_SCS0_BASE + WRPPMC_SDRAM_SCS0_SIZE));
173}
diff --git a/arch/mips/gt64120/wrppmc/time.c b/arch/mips/gt64120/wrppmc/time.c
new file mode 100644
index 000000000000..175d22adb450
--- /dev/null
+++ b/arch/mips/gt64120/wrppmc/time.c
@@ -0,0 +1,57 @@
1/*
2 * time.c: MIPS CPU Count/Compare timer hookup
3 *
4 * Author: Mark.Zhan, <rongkai.zhan@windriver.com>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 1996, 1997, 2004 by Ralf Baechle (ralf@linux-mips.org)
11 * Copyright (C) 2006, Wind River System Inc.
12 */
13#include <linux/config.h>
14#include <linux/init.h>
15#include <linux/string.h>
16#include <linux/kernel.h>
17#include <linux/param.h> /* for HZ */
18#include <linux/irq.h>
19#include <linux/timex.h>
20#include <linux/interrupt.h>
21
22#include <asm/reboot.h>
23#include <asm/time.h>
24#include <asm/io.h>
25#include <asm/bootinfo.h>
26#include <asm/gt64120.h>
27
28#define WRPPMC_CPU_CLK_FREQ 40000000 /* 40MHZ */
29
30void __init wrppmc_timer_setup(struct irqaction *irq)
31{
32 /* Install ISR for timer interrupt */
33 setup_irq(WRPPMC_MIPS_TIMER_IRQ, irq);
34
35 /* to generate the first timer interrupt */
36 write_c0_compare(mips_hpt_frequency/HZ);
37 write_c0_count(0);
38}
39
40/*
41 * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
42 *
43 * NOTE: We disable all GT64120 timers, and use MIPS processor internal
44 * timer as the source of kernel clock tick.
45 */
46void __init wrppmc_time_init(void)
47{
48 /* Disable GT64120 timers */
49 GT_WRITE(GT_TC_CONTROL_OFS, 0x00);
50 GT_WRITE(GT_TC0_OFS, 0x00);
51 GT_WRITE(GT_TC1_OFS, 0x00);
52 GT_WRITE(GT_TC2_OFS, 0x00);
53 GT_WRITE(GT_TC3_OFS, 0x00);
54
55 /* Use MIPS compare/count internal timer */
56 mips_hpt_frequency = WRPPMC_CPU_CLK_FREQ;
57}
diff --git a/arch/mips/ite-boards/generic/it8172_setup.c b/arch/mips/ite-boards/generic/it8172_setup.c
index fc73c8d69df7..da6ae0991199 100644
--- a/arch/mips/ite-boards/generic/it8172_setup.c
+++ b/arch/mips/ite-boards/generic/it8172_setup.c
@@ -72,11 +72,29 @@ struct {
72 struct resource flash; 72 struct resource flash;
73 struct resource boot; 73 struct resource boot;
74} it8172_resources = { 74} it8172_resources = {
75 { "RAM", 0, 0, IORESOURCE_MEM }, /* to be initted */ 75 {
76 { "PCI Mem", 0x10000000, 0x13FFFFFF, IORESOURCE_MEM }, 76 .start = 0, /* to be initted */
77 { "PCI I/O", 0x14000000, 0x17FFFFFF }, 77 .end = 0,
78 { "Flash", 0x08000000, 0x0CFFFFFF }, 78 .name = "RAM",
79 { "Boot ROM", 0x1FC00000, 0x1FFFFFFF } 79 .flags = IORESOURCE_MEM
80 }, {
81 .start = 0x10000000,
82 .end = 0x13FFFFFF,
83 .name = "PCI Mem",
84 .flags = IORESOURCE_MEM
85 }, {
86 .start = 0x14000000,
87 .end = 0x17FFFFFF
88 .name = "PCI I/O",
89 }, {
90 .start = 0x08000000,
91 .end = 0x0CFFFFFF
92 .name = "Flash",
93 }, {
94 .start = 0x1FC00000,
95 .end = 0x1FFFFFFF
96 .name = "Boot ROM",
97 }
80}; 98};
81#else 99#else
82struct { 100struct {
@@ -89,14 +107,44 @@ struct {
89 struct resource flash; 107 struct resource flash;
90 struct resource boot; 108 struct resource boot;
91} it8172_resources = { 109} it8172_resources = {
92 { "RAM", 0, 0, IORESOURCE_MEM }, /* to be initted */ 110 {
93 { "PCI Mem0", 0x0C000000, 0x0FFFFFFF, IORESOURCE_MEM }, 111 .start = 0, /* to be initted */
94 { "PCI Mem1", 0x10000000, 0x13FFFFFF, IORESOURCE_MEM }, 112 .end = 0,
95 { "PCI I/O", 0x14000000, 0x17FFFFFF }, 113 .name = "RAM",
96 { "PCI Mem2", 0x1A000000, 0x1BFFFFFF, IORESOURCE_MEM }, 114 .flags = IORESOURCE_MEM
97 { "PCI Mem3", 0x1C000000, 0x1FBFFFFF, IORESOURCE_MEM }, 115 }, {
98 { "Flash", 0x08000000, 0x0CFFFFFF }, 116 .start = 0x0C000000,
99 { "Boot ROM", 0x1FC00000, 0x1FFFFFFF } 117 .end = 0x0FFFFFFF,
118 .name = "PCI Mem0",
119 .flags = IORESOURCE_MEM
120 }, {
121 .start = 0x10000000,
122 .end = 0x13FFFFFF,
123 .name = "PCI Mem1",
124 .flags = IORESOURCE_MEM
125 }, {
126 .start = 0x14000000,
127 .end = 0x17FFFFFF
128 .name = "PCI I/O",
129 }, {
130 .start = 0x1A000000,
131 .end = 0x1BFFFFFF,
132 .name = "PCI Mem2",
133 .flags = IORESOURCE_MEM
134 }, {
135 .start = 0x1C000000,
136 .end = 0x1FBFFFFF,
137 .name = "PCI Mem3",
138 .flags = IORESOURCE_MEM
139 }, {
140 .start = 0x08000000,
141 .end = 0x0CFFFFFF
142 .name = "Flash",
143 }, {
144 .start = 0x1FC00000,
145 .end = 0x1FFFFFFF
146 .name = "Boot ROM",
147 }
100}; 148};
101#endif 149#endif
102 150
@@ -106,7 +154,7 @@ void __init it8172_init_ram_resource(unsigned long memsize)
106 it8172_resources.ram.end = memsize; 154 it8172_resources.ram.end = memsize;
107} 155}
108 156
109void __init plat_setup(void) 157void __init plat_mem_setup(void)
110{ 158{
111 unsigned short dsr; 159 unsigned short dsr;
112 char *argptr; 160 char *argptr;
diff --git a/arch/mips/jazz/setup.c b/arch/mips/jazz/setup.c
index 4036dc434551..c8d0df7d0c36 100644
--- a/arch/mips/jazz/setup.c
+++ b/arch/mips/jazz/setup.c
@@ -52,7 +52,7 @@ static struct resource jazz_io_resources[] = {
52 { "dma2", 0xc0, 0xdf, IORESOURCE_BUSY }, 52 { "dma2", 0xc0, 0xdf, IORESOURCE_BUSY },
53}; 53};
54 54
55void __init plat_setup(void) 55void __init plat_mem_setup(void)
56{ 56{
57 int i; 57 int i;
58 58
diff --git a/arch/mips/jmr3927/rbhma3100/setup.c b/arch/mips/jmr3927/rbhma3100/setup.c
index 9359cc413494..308e6cdcd245 100644
--- a/arch/mips/jmr3927/rbhma3100/setup.c
+++ b/arch/mips/jmr3927/rbhma3100/setup.c
@@ -82,17 +82,54 @@ struct {
82 struct resource sio0; 82 struct resource sio0;
83 struct resource sio1; 83 struct resource sio1;
84} jmr3927_resources = { 84} jmr3927_resources = {
85 { "RAM0", 0, 0x01FFFFFF, IORESOURCE_MEM }, 85 {
86 { "RAM1", 0x02000000, 0x03FFFFFF, IORESOURCE_MEM }, 86 .start = 0,
87 { "PCIMEM", 0x08000000, 0x07FFFFFF, IORESOURCE_MEM }, 87 .end = 0x01FFFFFF,
88 { "IOB", 0x10000000, 0x13FFFFFF }, 88 .name = "RAM0",
89 { "IOC", 0x14000000, 0x14FFFFFF }, 89 .flags = IORESOURCE_MEM
90 { "PCIIO", 0x15000000, 0x15FFFFFF }, 90 }, {
91 { "JMY1394", 0x1D000000, 0x1D3FFFFF }, 91 .start = 0x02000000,
92 { "ROM1", 0x1E000000, 0x1E3FFFFF }, 92 .end = 0x03FFFFFF,
93 { "ROM0", 0x1FC00000, 0x1FFFFFFF }, 93 .name = "RAM1",
94 { "SIO0", 0xFFFEF300, 0xFFFEF3FF }, 94 .flags = IORESOURCE_MEM
95 { "SIO1", 0xFFFEF400, 0xFFFEF4FF }, 95 }, {
96 .start = 0x08000000,
97 .end = 0x07FFFFFF,
98 .name = "PCIMEM",
99 .flags = IORESOURCE_MEM
100 }, {
101 .start = 0x10000000,
102 .end = 0x13FFFFFF,
103 .name = "IOB"
104 }, {
105 .start = 0x14000000,
106 .end = 0x14FFFFFF,
107 .name = "IOC"
108 }, {
109 .start = 0x15000000,
110 .end = 0x15FFFFFF,
111 .name = "PCIIO"
112 }, {
113 .start = 0x1D000000,
114 .end = 0x1D3FFFFF,
115 .name = "JMY1394"
116 }, {
117 .start = 0x1E000000,
118 .end = 0x1E3FFFFF,
119 .name = "ROM1"
120 }, {
121 .start = 0x1FC00000,
122 .end = 0x1FFFFFFF,
123 .name = "ROM0"
124 }, {
125 .start = 0xFFFEF300,
126 .end = 0xFFFEF3FF,
127 .name = "SIO0"
128 }, {
129 .start = 0xFFFEF400,
130 .end = 0xFFFEF4FF,
131 .name = "SIO1"
132 },
96}; 133};
97 134
98/* don't enable - see errata */ 135/* don't enable - see errata */
@@ -201,7 +238,7 @@ static void jmr3927_board_init(void);
201extern struct resource pci_io_resource; 238extern struct resource pci_io_resource;
202extern struct resource pci_mem_resource; 239extern struct resource pci_mem_resource;
203 240
204void __init plat_setup(void) 241void __init plat_mem_setup(void)
205{ 242{
206 char *argptr; 243 char *argptr;
207 244
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 34e8a256765c..881c467c6982 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -13,6 +13,8 @@ binfmt_irix-objs := irixelf.o irixinv.o irixioctl.o irixsig.o \
13 13
14obj-$(CONFIG_MODULES) += mips_ksyms.o module.o 14obj-$(CONFIG_MODULES) += mips_ksyms.o module.o
15 15
16obj-$(CONFIG_APM) += apm.o
17
16obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o 18obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o
17obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o 19obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o
18obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o 20obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o
diff --git a/arch/mips/kernel/apm.c b/arch/mips/kernel/apm.c
new file mode 100644
index 000000000000..15f46b4471fd
--- /dev/null
+++ b/arch/mips/kernel/apm.c
@@ -0,0 +1,605 @@
1/*
2 * bios-less APM driver for MIPS Linux
3 * Jamey Hicks <jamey@crl.dec.com>
4 * adapted from the APM BIOS driver for Linux by Stephen Rothwell (sfr@linuxcare.com)
5 *
6 * APM 1.2 Reference:
7 * Intel Corporation, Microsoft Corporation. Advanced Power Management
8 * (APM) BIOS Interface Specification, Revision 1.2, February 1996.
9 *
10 * [This document is available from Microsoft at:
11 * http://www.microsoft.com/hwdev/busbios/amp_12.htm]
12 */
13#include <linux/config.h>
14#include <linux/module.h>
15#include <linux/poll.h>
16#include <linux/timer.h>
17#include <linux/slab.h>
18#include <linux/proc_fs.h>
19#include <linux/miscdevice.h>
20#include <linux/apm_bios.h>
21#include <linux/capability.h>
22#include <linux/sched.h>
23#include <linux/pm.h>
24#include <linux/device.h>
25#include <linux/kernel.h>
26#include <linux/list.h>
27#include <linux/init.h>
28#include <linux/completion.h>
29
30#include <asm/apm.h> /* apm_power_info */
31#include <asm/system.h>
32
33/*
34 * The apm_bios device is one of the misc char devices.
35 * This is its minor number.
36 */
37#define APM_MINOR_DEV 134
38
39/*
40 * See Documentation/Config.help for the configuration options.
41 *
42 * Various options can be changed at boot time as follows:
43 * (We allow underscores for compatibility with the modules code)
44 * apm=on/off enable/disable APM
45 */
46
47/*
48 * Maximum number of events stored
49 */
50#define APM_MAX_EVENTS 16
51
52struct apm_queue {
53 unsigned int event_head;
54 unsigned int event_tail;
55 apm_event_t events[APM_MAX_EVENTS];
56};
57
58/*
59 * The per-file APM data
60 */
61struct apm_user {
62 struct list_head list;
63
64 unsigned int suser: 1;
65 unsigned int writer: 1;
66 unsigned int reader: 1;
67
68 int suspend_result;
69 unsigned int suspend_state;
70#define SUSPEND_NONE 0 /* no suspend pending */
71#define SUSPEND_PENDING 1 /* suspend pending read */
72#define SUSPEND_READ 2 /* suspend read, pending ack */
73#define SUSPEND_ACKED 3 /* suspend acked */
74#define SUSPEND_DONE 4 /* suspend completed */
75
76 struct apm_queue queue;
77};
78
79/*
80 * Local variables
81 */
82static int suspends_pending;
83static int apm_disabled;
84static int mips_apm_active;
85
86static DECLARE_WAIT_QUEUE_HEAD(apm_waitqueue);
87static DECLARE_WAIT_QUEUE_HEAD(apm_suspend_waitqueue);
88
89/*
90 * This is a list of everyone who has opened /dev/apm_bios
91 */
92static DECLARE_RWSEM(user_list_lock);
93static LIST_HEAD(apm_user_list);
94
95/*
96 * kapmd info. kapmd provides us a process context to handle
97 * "APM" events within - specifically necessary if we're going
98 * to be suspending the system.
99 */
100static DECLARE_WAIT_QUEUE_HEAD(kapmd_wait);
101static DECLARE_COMPLETION(kapmd_exit);
102static DEFINE_SPINLOCK(kapmd_queue_lock);
103static struct apm_queue kapmd_queue;
104
105
106static const char driver_version[] = "1.13"; /* no spaces */
107
108
109
110/*
111 * Compatibility cruft until the IPAQ people move over to the new
112 * interface.
113 */
114static void __apm_get_power_status(struct apm_power_info *info)
115{
116}
117
118/*
119 * This allows machines to provide their own "apm get power status" function.
120 */
121void (*apm_get_power_status)(struct apm_power_info *) = __apm_get_power_status;
122EXPORT_SYMBOL(apm_get_power_status);
123
124
125/*
126 * APM event queue management.
127 */
128static inline int queue_empty(struct apm_queue *q)
129{
130 return q->event_head == q->event_tail;
131}
132
133static inline apm_event_t queue_get_event(struct apm_queue *q)
134{
135 q->event_tail = (q->event_tail + 1) % APM_MAX_EVENTS;
136 return q->events[q->event_tail];
137}
138
139static void queue_add_event(struct apm_queue *q, apm_event_t event)
140{
141 q->event_head = (q->event_head + 1) % APM_MAX_EVENTS;
142 if (q->event_head == q->event_tail) {
143 static int notified;
144
145 if (notified++ == 0)
146 printk(KERN_ERR "apm: an event queue overflowed\n");
147 q->event_tail = (q->event_tail + 1) % APM_MAX_EVENTS;
148 }
149 q->events[q->event_head] = event;
150}
151
152static void queue_event_one_user(struct apm_user *as, apm_event_t event)
153{
154 if (as->suser && as->writer) {
155 switch (event) {
156 case APM_SYS_SUSPEND:
157 case APM_USER_SUSPEND:
158 /*
159 * If this user already has a suspend pending,
160 * don't queue another one.
161 */
162 if (as->suspend_state != SUSPEND_NONE)
163 return;
164
165 as->suspend_state = SUSPEND_PENDING;
166 suspends_pending++;
167 break;
168 }
169 }
170 queue_add_event(&as->queue, event);
171}
172
173static void queue_event(apm_event_t event, struct apm_user *sender)
174{
175 struct apm_user *as;
176
177 down_read(&user_list_lock);
178 list_for_each_entry(as, &apm_user_list, list) {
179 if (as != sender && as->reader)
180 queue_event_one_user(as, event);
181 }
182 up_read(&user_list_lock);
183 wake_up_interruptible(&apm_waitqueue);
184}
185
186static void apm_suspend(void)
187{
188 struct apm_user *as;
189 int err = pm_suspend(PM_SUSPEND_MEM);
190
191 /*
192 * Anyone on the APM queues will think we're still suspended.
193 * Send a message so everyone knows we're now awake again.
194 */
195 queue_event(APM_NORMAL_RESUME, NULL);
196
197 /*
198 * Finally, wake up anyone who is sleeping on the suspend.
199 */
200 down_read(&user_list_lock);
201 list_for_each_entry(as, &apm_user_list, list) {
202 as->suspend_result = err;
203 as->suspend_state = SUSPEND_DONE;
204 }
205 up_read(&user_list_lock);
206
207 wake_up(&apm_suspend_waitqueue);
208}
209
210static ssize_t apm_read(struct file *fp, char __user *buf, size_t count, loff_t *ppos)
211{
212 struct apm_user *as = fp->private_data;
213 apm_event_t event;
214 int i = count, ret = 0;
215
216 if (count < sizeof(apm_event_t))
217 return -EINVAL;
218
219 if (queue_empty(&as->queue) && fp->f_flags & O_NONBLOCK)
220 return -EAGAIN;
221
222 wait_event_interruptible(apm_waitqueue, !queue_empty(&as->queue));
223
224 while ((i >= sizeof(event)) && !queue_empty(&as->queue)) {
225 event = queue_get_event(&as->queue);
226
227 ret = -EFAULT;
228 if (copy_to_user(buf, &event, sizeof(event)))
229 break;
230
231 if (event == APM_SYS_SUSPEND || event == APM_USER_SUSPEND)
232 as->suspend_state = SUSPEND_READ;
233
234 buf += sizeof(event);
235 i -= sizeof(event);
236 }
237
238 if (i < count)
239 ret = count - i;
240
241 return ret;
242}
243
244static unsigned int apm_poll(struct file *fp, poll_table * wait)
245{
246 struct apm_user *as = fp->private_data;
247
248 poll_wait(fp, &apm_waitqueue, wait);
249 return queue_empty(&as->queue) ? 0 : POLLIN | POLLRDNORM;
250}
251
252/*
253 * apm_ioctl - handle APM ioctl
254 *
255 * APM_IOC_SUSPEND
256 * This IOCTL is overloaded, and performs two functions. It is used to:
257 * - initiate a suspend
258 * - acknowledge a suspend read from /dev/apm_bios.
259 * Only when everyone who has opened /dev/apm_bios with write permission
260 * has acknowledge does the actual suspend happen.
261 */
262static int
263apm_ioctl(struct inode * inode, struct file *filp, u_int cmd, u_long arg)
264{
265 struct apm_user *as = filp->private_data;
266 unsigned long flags;
267 int err = -EINVAL;
268
269 if (!as->suser || !as->writer)
270 return -EPERM;
271
272 switch (cmd) {
273 case APM_IOC_SUSPEND:
274 as->suspend_result = -EINTR;
275
276 if (as->suspend_state == SUSPEND_READ) {
277 /*
278 * If we read a suspend command from /dev/apm_bios,
279 * then the corresponding APM_IOC_SUSPEND ioctl is
280 * interpreted as an acknowledge.
281 */
282 as->suspend_state = SUSPEND_ACKED;
283 suspends_pending--;
284 } else {
285 /*
286 * Otherwise it is a request to suspend the system.
287 * Queue an event for all readers, and expect an
288 * acknowledge from all writers who haven't already
289 * acknowledged.
290 */
291 queue_event(APM_USER_SUSPEND, as);
292 }
293
294 /*
295 * If there are no further acknowledges required, suspend
296 * the system.
297 */
298 if (suspends_pending == 0)
299 apm_suspend();
300
301 /*
302 * Wait for the suspend/resume to complete. If there are
303 * pending acknowledges, we wait here for them.
304 *
305 * Note that we need to ensure that the PM subsystem does
306 * not kick us out of the wait when it suspends the threads.
307 */
308 flags = current->flags;
309 current->flags |= PF_NOFREEZE;
310
311 /*
312 * Note: do not allow a thread which is acking the suspend
313 * to escape until the resume is complete.
314 */
315 if (as->suspend_state == SUSPEND_ACKED)
316 wait_event(apm_suspend_waitqueue,
317 as->suspend_state == SUSPEND_DONE);
318 else
319 wait_event_interruptible(apm_suspend_waitqueue,
320 as->suspend_state == SUSPEND_DONE);
321
322 current->flags = flags;
323 err = as->suspend_result;
324 as->suspend_state = SUSPEND_NONE;
325 break;
326 }
327
328 return err;
329}
330
331static int apm_release(struct inode * inode, struct file * filp)
332{
333 struct apm_user *as = filp->private_data;
334 filp->private_data = NULL;
335
336 down_write(&user_list_lock);
337 list_del(&as->list);
338 up_write(&user_list_lock);
339
340 /*
341 * We are now unhooked from the chain. As far as new
342 * events are concerned, we no longer exist. However, we
343 * need to balance suspends_pending, which means the
344 * possibility of sleeping.
345 */
346 if (as->suspend_state != SUSPEND_NONE) {
347 suspends_pending -= 1;
348 if (suspends_pending == 0)
349 apm_suspend();
350 }
351
352 kfree(as);
353 return 0;
354}
355
356static int apm_open(struct inode * inode, struct file * filp)
357{
358 struct apm_user *as;
359
360 as = (struct apm_user *)kzalloc(sizeof(*as), GFP_KERNEL);
361 if (as) {
362 /*
363 * XXX - this is a tiny bit broken, when we consider BSD
364 * process accounting. If the device is opened by root, we
365 * instantly flag that we used superuser privs. Who knows,
366 * we might close the device immediately without doing a
367 * privileged operation -- cevans
368 */
369 as->suser = capable(CAP_SYS_ADMIN);
370 as->writer = (filp->f_mode & FMODE_WRITE) == FMODE_WRITE;
371 as->reader = (filp->f_mode & FMODE_READ) == FMODE_READ;
372
373 down_write(&user_list_lock);
374 list_add(&as->list, &apm_user_list);
375 up_write(&user_list_lock);
376
377 filp->private_data = as;
378 }
379
380 return as ? 0 : -ENOMEM;
381}
382
383static struct file_operations apm_bios_fops = {
384 .owner = THIS_MODULE,
385 .read = apm_read,
386 .poll = apm_poll,
387 .ioctl = apm_ioctl,
388 .open = apm_open,
389 .release = apm_release,
390};
391
392static struct miscdevice apm_device = {
393 .minor = APM_MINOR_DEV,
394 .name = "apm_bios",
395 .fops = &apm_bios_fops
396};
397
398
399#ifdef CONFIG_PROC_FS
400/*
401 * Arguments, with symbols from linux/apm_bios.h.
402 *
403 * 0) Linux driver version (this will change if format changes)
404 * 1) APM BIOS Version. Usually 1.0, 1.1 or 1.2.
405 * 2) APM flags from APM Installation Check (0x00):
406 * bit 0: APM_16_BIT_SUPPORT
407 * bit 1: APM_32_BIT_SUPPORT
408 * bit 2: APM_IDLE_SLOWS_CLOCK
409 * bit 3: APM_BIOS_DISABLED
410 * bit 4: APM_BIOS_DISENGAGED
411 * 3) AC line status
412 * 0x00: Off-line
413 * 0x01: On-line
414 * 0x02: On backup power (BIOS >= 1.1 only)
415 * 0xff: Unknown
416 * 4) Battery status
417 * 0x00: High
418 * 0x01: Low
419 * 0x02: Critical
420 * 0x03: Charging
421 * 0x04: Selected battery not present (BIOS >= 1.2 only)
422 * 0xff: Unknown
423 * 5) Battery flag
424 * bit 0: High
425 * bit 1: Low
426 * bit 2: Critical
427 * bit 3: Charging
428 * bit 7: No system battery
429 * 0xff: Unknown
430 * 6) Remaining battery life (percentage of charge):
431 * 0-100: valid
432 * -1: Unknown
433 * 7) Remaining battery life (time units):
434 * Number of remaining minutes or seconds
435 * -1: Unknown
436 * 8) min = minutes; sec = seconds
437 */
438static int apm_get_info(char *buf, char **start, off_t fpos, int length)
439{
440 struct apm_power_info info;
441 char *units;
442 int ret;
443
444 info.ac_line_status = 0xff;
445 info.battery_status = 0xff;
446 info.battery_flag = 0xff;
447 info.battery_life = -1;
448 info.time = -1;
449 info.units = -1;
450
451 if (apm_get_power_status)
452 apm_get_power_status(&info);
453
454 switch (info.units) {
455 default: units = "?"; break;
456 case 0: units = "min"; break;
457 case 1: units = "sec"; break;
458 }
459
460 ret = sprintf(buf, "%s 1.2 0x%02x 0x%02x 0x%02x 0x%02x %d%% %d %s\n",
461 driver_version, APM_32_BIT_SUPPORT,
462 info.ac_line_status, info.battery_status,
463 info.battery_flag, info.battery_life,
464 info.time, units);
465
466 return ret;
467}
468#endif
469
470static int kapmd(void *arg)
471{
472 daemonize("kapmd");
473 current->flags |= PF_NOFREEZE;
474
475 do {
476 apm_event_t event;
477
478 wait_event_interruptible(kapmd_wait,
479 !queue_empty(&kapmd_queue) || !mips_apm_active);
480
481 if (!mips_apm_active)
482 break;
483
484 spin_lock_irq(&kapmd_queue_lock);
485 event = 0;
486 if (!queue_empty(&kapmd_queue))
487 event = queue_get_event(&kapmd_queue);
488 spin_unlock_irq(&kapmd_queue_lock);
489
490 switch (event) {
491 case 0:
492 break;
493
494 case APM_LOW_BATTERY:
495 case APM_POWER_STATUS_CHANGE:
496 queue_event(event, NULL);
497 break;
498
499 case APM_USER_SUSPEND:
500 case APM_SYS_SUSPEND:
501 queue_event(event, NULL);
502 if (suspends_pending == 0)
503 apm_suspend();
504 break;
505
506 case APM_CRITICAL_SUSPEND:
507 apm_suspend();
508 break;
509 }
510 } while (1);
511
512 complete_and_exit(&kapmd_exit, 0);
513}
514
515static int __init apm_init(void)
516{
517 int ret;
518
519 if (apm_disabled) {
520 printk(KERN_NOTICE "apm: disabled on user request.\n");
521 return -ENODEV;
522 }
523
524 mips_apm_active = 1;
525
526 ret = kernel_thread(kapmd, NULL, CLONE_KERNEL);
527 if (ret < 0) {
528 mips_apm_active = 0;
529 return ret;
530 }
531
532#ifdef CONFIG_PROC_FS
533 create_proc_info_entry("apm", 0, NULL, apm_get_info);
534#endif
535
536 ret = misc_register(&apm_device);
537 if (ret != 0) {
538 remove_proc_entry("apm", NULL);
539
540 mips_apm_active = 0;
541 wake_up(&kapmd_wait);
542 wait_for_completion(&kapmd_exit);
543 }
544
545 return ret;
546}
547
548static void __exit apm_exit(void)
549{
550 misc_deregister(&apm_device);
551 remove_proc_entry("apm", NULL);
552
553 mips_apm_active = 0;
554 wake_up(&kapmd_wait);
555 wait_for_completion(&kapmd_exit);
556}
557
558module_init(apm_init);
559module_exit(apm_exit);
560
561MODULE_AUTHOR("Stephen Rothwell");
562MODULE_DESCRIPTION("Advanced Power Management");
563MODULE_LICENSE("GPL");
564
565#ifndef MODULE
566static int __init apm_setup(char *str)
567{
568 while ((str != NULL) && (*str != '\0')) {
569 if (strncmp(str, "off", 3) == 0)
570 apm_disabled = 1;
571 if (strncmp(str, "on", 2) == 0)
572 apm_disabled = 0;
573 str = strchr(str, ',');
574 if (str != NULL)
575 str += strspn(str, ", \t");
576 }
577 return 1;
578}
579
580__setup("apm=", apm_setup);
581#endif
582
583/**
584 * apm_queue_event - queue an APM event for kapmd
585 * @event: APM event
586 *
587 * Queue an APM event for kapmd to process and ultimately take the
588 * appropriate action. Only a subset of events are handled:
589 * %APM_LOW_BATTERY
590 * %APM_POWER_STATUS_CHANGE
591 * %APM_USER_SUSPEND
592 * %APM_SYS_SUSPEND
593 * %APM_CRITICAL_SUSPEND
594 */
595void apm_queue_event(apm_event_t event)
596{
597 unsigned long flags;
598
599 spin_lock_irqsave(&kapmd_queue_lock, flags);
600 queue_add_event(&kapmd_queue, event);
601 spin_unlock_irqrestore(&kapmd_queue_lock, flags);
602
603 wake_up_interruptible(&kapmd_wait);
604}
605EXPORT_SYMBOL(apm_queue_event);
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index 0facfaf4e950..f1bb6a2dc5fc 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -141,72 +141,72 @@ void output_thread_defines(void)
141void output_thread_fpu_defines(void) 141void output_thread_fpu_defines(void)
142{ 142{
143 offset("#define THREAD_FPR0 ", 143 offset("#define THREAD_FPR0 ",
144 struct task_struct, thread.fpu.hard.fpr[0]); 144 struct task_struct, thread.fpu.fpr[0]);
145 offset("#define THREAD_FPR1 ", 145 offset("#define THREAD_FPR1 ",
146 struct task_struct, thread.fpu.hard.fpr[1]); 146 struct task_struct, thread.fpu.fpr[1]);
147 offset("#define THREAD_FPR2 ", 147 offset("#define THREAD_FPR2 ",
148 struct task_struct, thread.fpu.hard.fpr[2]); 148 struct task_struct, thread.fpu.fpr[2]);
149 offset("#define THREAD_FPR3 ", 149 offset("#define THREAD_FPR3 ",
150 struct task_struct, thread.fpu.hard.fpr[3]); 150 struct task_struct, thread.fpu.fpr[3]);
151 offset("#define THREAD_FPR4 ", 151 offset("#define THREAD_FPR4 ",
152 struct task_struct, thread.fpu.hard.fpr[4]); 152 struct task_struct, thread.fpu.fpr[4]);
153 offset("#define THREAD_FPR5 ", 153 offset("#define THREAD_FPR5 ",
154 struct task_struct, thread.fpu.hard.fpr[5]); 154 struct task_struct, thread.fpu.fpr[5]);
155 offset("#define THREAD_FPR6 ", 155 offset("#define THREAD_FPR6 ",
156 struct task_struct, thread.fpu.hard.fpr[6]); 156 struct task_struct, thread.fpu.fpr[6]);
157 offset("#define THREAD_FPR7 ", 157 offset("#define THREAD_FPR7 ",
158 struct task_struct, thread.fpu.hard.fpr[7]); 158 struct task_struct, thread.fpu.fpr[7]);
159 offset("#define THREAD_FPR8 ", 159 offset("#define THREAD_FPR8 ",
160 struct task_struct, thread.fpu.hard.fpr[8]); 160 struct task_struct, thread.fpu.fpr[8]);
161 offset("#define THREAD_FPR9 ", 161 offset("#define THREAD_FPR9 ",
162 struct task_struct, thread.fpu.hard.fpr[9]); 162 struct task_struct, thread.fpu.fpr[9]);
163 offset("#define THREAD_FPR10 ", 163 offset("#define THREAD_FPR10 ",
164 struct task_struct, thread.fpu.hard.fpr[10]); 164 struct task_struct, thread.fpu.fpr[10]);
165 offset("#define THREAD_FPR11 ", 165 offset("#define THREAD_FPR11 ",
166 struct task_struct, thread.fpu.hard.fpr[11]); 166 struct task_struct, thread.fpu.fpr[11]);
167 offset("#define THREAD_FPR12 ", 167 offset("#define THREAD_FPR12 ",
168 struct task_struct, thread.fpu.hard.fpr[12]); 168 struct task_struct, thread.fpu.fpr[12]);
169 offset("#define THREAD_FPR13 ", 169 offset("#define THREAD_FPR13 ",
170 struct task_struct, thread.fpu.hard.fpr[13]); 170 struct task_struct, thread.fpu.fpr[13]);
171 offset("#define THREAD_FPR14 ", 171 offset("#define THREAD_FPR14 ",
172 struct task_struct, thread.fpu.hard.fpr[14]); 172 struct task_struct, thread.fpu.fpr[14]);
173 offset("#define THREAD_FPR15 ", 173 offset("#define THREAD_FPR15 ",
174 struct task_struct, thread.fpu.hard.fpr[15]); 174 struct task_struct, thread.fpu.fpr[15]);
175 offset("#define THREAD_FPR16 ", 175 offset("#define THREAD_FPR16 ",
176 struct task_struct, thread.fpu.hard.fpr[16]); 176 struct task_struct, thread.fpu.fpr[16]);
177 offset("#define THREAD_FPR17 ", 177 offset("#define THREAD_FPR17 ",
178 struct task_struct, thread.fpu.hard.fpr[17]); 178 struct task_struct, thread.fpu.fpr[17]);
179 offset("#define THREAD_FPR18 ", 179 offset("#define THREAD_FPR18 ",
180 struct task_struct, thread.fpu.hard.fpr[18]); 180 struct task_struct, thread.fpu.fpr[18]);
181 offset("#define THREAD_FPR19 ", 181 offset("#define THREAD_FPR19 ",
182 struct task_struct, thread.fpu.hard.fpr[19]); 182 struct task_struct, thread.fpu.fpr[19]);
183 offset("#define THREAD_FPR20 ", 183 offset("#define THREAD_FPR20 ",
184 struct task_struct, thread.fpu.hard.fpr[20]); 184 struct task_struct, thread.fpu.fpr[20]);
185 offset("#define THREAD_FPR21 ", 185 offset("#define THREAD_FPR21 ",
186 struct task_struct, thread.fpu.hard.fpr[21]); 186 struct task_struct, thread.fpu.fpr[21]);
187 offset("#define THREAD_FPR22 ", 187 offset("#define THREAD_FPR22 ",
188 struct task_struct, thread.fpu.hard.fpr[22]); 188 struct task_struct, thread.fpu.fpr[22]);
189 offset("#define THREAD_FPR23 ", 189 offset("#define THREAD_FPR23 ",
190 struct task_struct, thread.fpu.hard.fpr[23]); 190 struct task_struct, thread.fpu.fpr[23]);
191 offset("#define THREAD_FPR24 ", 191 offset("#define THREAD_FPR24 ",
192 struct task_struct, thread.fpu.hard.fpr[24]); 192 struct task_struct, thread.fpu.fpr[24]);
193 offset("#define THREAD_FPR25 ", 193 offset("#define THREAD_FPR25 ",
194 struct task_struct, thread.fpu.hard.fpr[25]); 194 struct task_struct, thread.fpu.fpr[25]);
195 offset("#define THREAD_FPR26 ", 195 offset("#define THREAD_FPR26 ",
196 struct task_struct, thread.fpu.hard.fpr[26]); 196 struct task_struct, thread.fpu.fpr[26]);
197 offset("#define THREAD_FPR27 ", 197 offset("#define THREAD_FPR27 ",
198 struct task_struct, thread.fpu.hard.fpr[27]); 198 struct task_struct, thread.fpu.fpr[27]);
199 offset("#define THREAD_FPR28 ", 199 offset("#define THREAD_FPR28 ",
200 struct task_struct, thread.fpu.hard.fpr[28]); 200 struct task_struct, thread.fpu.fpr[28]);
201 offset("#define THREAD_FPR29 ", 201 offset("#define THREAD_FPR29 ",
202 struct task_struct, thread.fpu.hard.fpr[29]); 202 struct task_struct, thread.fpu.fpr[29]);
203 offset("#define THREAD_FPR30 ", 203 offset("#define THREAD_FPR30 ",
204 struct task_struct, thread.fpu.hard.fpr[30]); 204 struct task_struct, thread.fpu.fpr[30]);
205 offset("#define THREAD_FPR31 ", 205 offset("#define THREAD_FPR31 ",
206 struct task_struct, thread.fpu.hard.fpr[31]); 206 struct task_struct, thread.fpu.fpr[31]);
207 207
208 offset("#define THREAD_FCR31 ", 208 offset("#define THREAD_FCR31 ",
209 struct task_struct, thread.fpu.hard.fcr31); 209 struct task_struct, thread.fpu.fcr31);
210 linefeed; 210 linefeed;
211} 211}
212 212
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index b6232d9033cb..76fd3f22c766 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -178,7 +178,7 @@ int __compute_return_epc(struct pt_regs *regs)
178 if (is_fpu_owner()) 178 if (is_fpu_owner())
179 asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); 179 asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
180 else 180 else
181 fcr31 = current->thread.fpu.hard.fcr31; 181 fcr31 = current->thread.fpu.fcr31;
182 preempt_enable(); 182 preempt_enable();
183 183
184 bit = (insn.i_format.rt >> 2); 184 bit = (insn.i_format.rt >> 2);
diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c
index 2125ba5f1d9b..0cb8ed5662f3 100644
--- a/arch/mips/kernel/i8259.c
+++ b/arch/mips/kernel/i8259.c
@@ -302,11 +302,11 @@ static struct irqaction irq2 = {
302}; 302};
303 303
304static struct resource pic1_io_resource = { 304static struct resource pic1_io_resource = {
305 "pic1", 0x20, 0x3f, IORESOURCE_BUSY 305 .name = "pic1", .start = 0x20, .end = 0x3f, .flags = IORESOURCE_BUSY
306}; 306};
307 307
308static struct resource pic2_io_resource = { 308static struct resource pic2_io_resource = {
309 "pic2", 0xa0, 0xbf, IORESOURCE_BUSY 309 .name = "pic2", .start = 0xa0, .end = 0xbf, .flags = IORESOURCE_BUSY
310}; 310};
311 311
312/* 312/*
diff --git a/arch/mips/kernel/irixsig.c b/arch/mips/kernel/irixsig.c
index 8150f071f80a..a9bf6cc3abd1 100644
--- a/arch/mips/kernel/irixsig.c
+++ b/arch/mips/kernel/irixsig.c
@@ -260,7 +260,7 @@ irix_sigreturn(struct pt_regs *regs)
260 260
261 for(i = 0; i < 32; i++) 261 for(i = 0; i < 32; i++)
262 error |= __get_user(fregs[i], &context->fpregs[i]); 262 error |= __get_user(fregs[i], &context->fpregs[i]);
263 error |= __get_user(current->thread.fpu.hard.fcr31, &context->fpcsr); 263 error |= __get_user(current->thread.fpu.fcr31, &context->fpcsr);
264 } 264 }
265 265
266 /* XXX do sigstack crapola here... XXX */ 266 /* XXX do sigstack crapola here... XXX */
diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
index 9b4733c12395..1d44025188d8 100644
--- a/arch/mips/kernel/ptrace.c
+++ b/arch/mips/kernel/ptrace.c
@@ -120,11 +120,11 @@ int ptrace_getfpregs (struct task_struct *child, __u32 __user *data)
120 __put_user ((__u64) -1, i + (__u64 __user *) data); 120 __put_user ((__u64) -1, i + (__u64 __user *) data);
121 } 121 }
122 122
123 __put_user (child->thread.fpu.fcr31, data + 64);
124
123 if (cpu_has_fpu) { 125 if (cpu_has_fpu) {
124 unsigned int flags, tmp; 126 unsigned int flags, tmp;
125 127
126 __put_user (child->thread.fpu.hard.fcr31, data + 64);
127
128 preempt_disable(); 128 preempt_disable();
129 if (cpu_has_mipsmt) { 129 if (cpu_has_mipsmt) {
130 unsigned int vpflags = dvpe(); 130 unsigned int vpflags = dvpe();
@@ -142,7 +142,6 @@ int ptrace_getfpregs (struct task_struct *child, __u32 __user *data)
142 preempt_enable(); 142 preempt_enable();
143 __put_user (tmp, data + 65); 143 __put_user (tmp, data + 65);
144 } else { 144 } else {
145 __put_user (child->thread.fpu.soft.fcr31, data + 64);
146 __put_user ((__u32) 0, data + 65); 145 __put_user ((__u32) 0, data + 65);
147 } 146 }
148 147
@@ -162,10 +161,7 @@ int ptrace_setfpregs (struct task_struct *child, __u32 __user *data)
162 for (i = 0; i < 32; i++) 161 for (i = 0; i < 32; i++)
163 __get_user (fregs[i], i + (__u64 __user *) data); 162 __get_user (fregs[i], i + (__u64 __user *) data);
164 163
165 if (cpu_has_fpu) 164 __get_user (child->thread.fpu.fcr31, data + 64);
166 __get_user (child->thread.fpu.hard.fcr31, data + 64);
167 else
168 __get_user (child->thread.fpu.soft.fcr31, data + 64);
169 165
170 /* FIR may not be written. */ 166 /* FIR may not be written. */
171 167
@@ -241,10 +237,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
241 tmp = regs->lo; 237 tmp = regs->lo;
242 break; 238 break;
243 case FPC_CSR: 239 case FPC_CSR:
244 if (cpu_has_fpu) 240 tmp = child->thread.fpu.fcr31;
245 tmp = child->thread.fpu.hard.fcr31;
246 else
247 tmp = child->thread.fpu.soft.fcr31;
248 break; 241 break;
249 case FPC_EIR: { /* implementation / version register */ 242 case FPC_EIR: { /* implementation / version register */
250 unsigned int flags; 243 unsigned int flags;
@@ -336,9 +329,9 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
336 329
337 if (!tsk_used_math(child)) { 330 if (!tsk_used_math(child)) {
338 /* FP not yet used */ 331 /* FP not yet used */
339 memset(&child->thread.fpu.hard, ~0, 332 memset(&child->thread.fpu, ~0,
340 sizeof(child->thread.fpu.hard)); 333 sizeof(child->thread.fpu));
341 child->thread.fpu.hard.fcr31 = 0; 334 child->thread.fpu.fcr31 = 0;
342 } 335 }
343#ifdef CONFIG_32BIT 336#ifdef CONFIG_32BIT
344 /* 337 /*
@@ -369,10 +362,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
369 regs->lo = data; 362 regs->lo = data;
370 break; 363 break;
371 case FPC_CSR: 364 case FPC_CSR:
372 if (cpu_has_fpu) 365 child->thread.fpu.fcr31 = data;
373 child->thread.fpu.hard.fcr31 = data;
374 else
375 child->thread.fpu.soft.fcr31 = data;
376 break; 366 break;
377 case DSP_BASE ... DSP_BASE + 5: { 367 case DSP_BASE ... DSP_BASE + 5: {
378 dspreg_t *dregs; 368 dspreg_t *dregs;
diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c
index 8704dc0496ea..f40ecd8be05f 100644
--- a/arch/mips/kernel/ptrace32.c
+++ b/arch/mips/kernel/ptrace32.c
@@ -166,10 +166,7 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
166 tmp = regs->lo; 166 tmp = regs->lo;
167 break; 167 break;
168 case FPC_CSR: 168 case FPC_CSR:
169 if (cpu_has_fpu) 169 tmp = child->thread.fpu.fcr31;
170 tmp = child->thread.fpu.hard.fcr31;
171 else
172 tmp = child->thread.fpu.soft.fcr31;
173 break; 170 break;
174 case FPC_EIR: { /* implementation / version register */ 171 case FPC_EIR: { /* implementation / version register */
175 unsigned int flags; 172 unsigned int flags;
@@ -288,9 +285,9 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
288 285
289 if (!tsk_used_math(child)) { 286 if (!tsk_used_math(child)) {
290 /* FP not yet used */ 287 /* FP not yet used */
291 memset(&child->thread.fpu.hard, ~0, 288 memset(&child->thread.fpu, ~0,
292 sizeof(child->thread.fpu.hard)); 289 sizeof(child->thread.fpu));
293 child->thread.fpu.hard.fcr31 = 0; 290 child->thread.fpu.fcr31 = 0;
294 } 291 }
295 /* 292 /*
296 * The odd registers are actually the high order bits 293 * The odd registers are actually the high order bits
@@ -318,10 +315,7 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
318 regs->lo = data; 315 regs->lo = data;
319 break; 316 break;
320 case FPC_CSR: 317 case FPC_CSR:
321 if (cpu_has_fpu) 318 child->thread.fpu.fcr31 = data;
322 child->thread.fpu.hard.fcr31 = data;
323 else
324 child->thread.fpu.soft.fcr31 = data;
325 break; 319 break;
326 case DSP_BASE ... DSP_BASE + 5: { 320 case DSP_BASE ... DSP_BASE + 5: {
327 dspreg_t *dregs; 321 dspreg_t *dregs;
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index 0b1b54acee9f..db94e556fc97 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -75,8 +75,8 @@
75 and t0, t0, t1 75 and t0, t0, t1
76 LONG_S t0, ST_OFF(t3) 76 LONG_S t0, ST_OFF(t3)
77 77
78 fpu_save_double a0 t1 t0 t2 # c0_status passed in t1 78 fpu_save_double a0 t0 t1 # c0_status passed in t0
79 # clobbers t0 and t2 79 # clobbers t1
801: 801:
81 81
82 /* 82 /*
@@ -129,9 +129,9 @@
129 */ 129 */
130LEAF(_save_fp) 130LEAF(_save_fp)
131#ifdef CONFIG_64BIT 131#ifdef CONFIG_64BIT
132 mfc0 t1, CP0_STATUS 132 mfc0 t0, CP0_STATUS
133#endif 133#endif
134 fpu_save_double a0 t1 t0 t2 # clobbers t1 134 fpu_save_double a0 t0 t1 # clobbers t1
135 jr ra 135 jr ra
136 END(_save_fp) 136 END(_save_fp)
137 137
@@ -139,7 +139,10 @@ LEAF(_save_fp)
139 * Restore a thread's fp context. 139 * Restore a thread's fp context.
140 */ 140 */
141LEAF(_restore_fp) 141LEAF(_restore_fp)
142 fpu_restore_double a0, t1 # clobbers t1 142#ifdef CONFIG_64BIT
143 mfc0 t0, CP0_STATUS
144#endif
145 fpu_restore_double a0 t0 t1 # clobbers t1
143 jr ra 146 jr ra
144 END(_restore_fp) 147 END(_restore_fp)
145 148
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 397a70e651b5..bfcec8d9bfe4 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -442,6 +442,48 @@ static inline void bootmem_init(void)
442#endif /* CONFIG_BLK_DEV_INITRD */ 442#endif /* CONFIG_BLK_DEV_INITRD */
443} 443}
444 444
445/*
446 * arch_mem_init - initialize memory managment subsystem
447 *
448 * o plat_mem_setup() detects the memory configuration and will record detected
449 * memory areas using add_memory_region.
450 * o parse_cmdline_early() parses the command line for mem= options which,
451 * iff detected, will override the results of the automatic detection.
452 *
453 * At this stage the memory configuration of the system is known to the
454 * kernel but generic memory managment system is still entirely uninitialized.
455 *
456 * o bootmem_init()
457 * o sparse_init()
458 * o paging_init()
459 *
460 * At this stage the bootmem allocator is ready to use.
461 *
462 * NOTE: historically plat_mem_setup did the entire platform initialization.
463 * This was rather impractical because it meant plat_mem_setup had to
464 * get away without any kind of memory allocator. To keep old code from
465 * breaking plat_setup was just renamed to plat_setup and a second platform
466 * initialization hook for anything else was introduced.
467 */
468
469extern void plat_mem_setup(void);
470
471static void __init arch_mem_init(char **cmdline_p)
472{
473 /* call board setup routine */
474 plat_mem_setup();
475
476 strlcpy(command_line, arcs_cmdline, sizeof(command_line));
477 strlcpy(saved_command_line, command_line, COMMAND_LINE_SIZE);
478
479 *cmdline_p = command_line;
480
481 parse_cmdline_early();
482 bootmem_init();
483 sparse_init();
484 paging_init();
485}
486
445static inline void resource_init(void) 487static inline void resource_init(void)
446{ 488{
447 int i; 489 int i;
@@ -495,8 +537,6 @@ static inline void resource_init(void)
495#undef MAXMEM 537#undef MAXMEM
496#undef MAXMEM_PFN 538#undef MAXMEM_PFN
497 539
498extern void plat_setup(void);
499
500void __init setup_arch(char **cmdline_p) 540void __init setup_arch(char **cmdline_p)
501{ 541{
502 cpu_probe(); 542 cpu_probe();
@@ -511,18 +551,8 @@ void __init setup_arch(char **cmdline_p)
511#endif 551#endif
512#endif 552#endif
513 553
514 /* call board setup routine */ 554 arch_mem_init(cmdline_p);
515 plat_setup();
516 555
517 strlcpy(command_line, arcs_cmdline, sizeof(command_line));
518 strlcpy(saved_command_line, command_line, COMMAND_LINE_SIZE);
519
520 *cmdline_p = command_line;
521
522 parse_cmdline_early();
523 bootmem_init();
524 sparse_init();
525 paging_init();
526 resource_init(); 556 resource_init();
527#ifdef CONFIG_SMP 557#ifdef CONFIG_SMP
528 plat_smp_setup(); 558 plat_smp_setup();
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index a7564b08eb4d..ad16eceb24dd 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -65,7 +65,7 @@ extern asmlinkage void handle_mcheck(void);
65extern asmlinkage void handle_reserved(void); 65extern asmlinkage void handle_reserved(void);
66 66
67extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, 67extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
68 struct mips_fpu_soft_struct *ctx); 68 struct mips_fpu_struct *ctx);
69 69
70void (*board_be_init)(void); 70void (*board_be_init)(void);
71int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 71int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
@@ -600,8 +600,7 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
600 preempt_enable(); 600 preempt_enable();
601 601
602 /* Run the emulator */ 602 /* Run the emulator */
603 sig = fpu_emulator_cop1Handler (regs, 603 sig = fpu_emulator_cop1Handler (regs, &current->thread.fpu);
604 &current->thread.fpu.soft);
605 604
606 preempt_disable(); 605 preempt_disable();
607 606
@@ -610,7 +609,7 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
610 * We can't allow the emulated instruction to leave any of 609 * We can't allow the emulated instruction to leave any of
611 * the cause bit set in $fcr31. 610 * the cause bit set in $fcr31.
612 */ 611 */
613 current->thread.fpu.soft.fcr31 &= ~FPU_CSR_ALL_X; 612 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
614 613
615 /* Restore the hardware register state */ 614 /* Restore the hardware register state */
616 restore_fp(current); 615 restore_fp(current);
@@ -755,7 +754,7 @@ asmlinkage void do_cpu(struct pt_regs *regs)
755 754
756 if (!cpu_has_fpu) { 755 if (!cpu_has_fpu) {
757 int sig = fpu_emulator_cop1Handler(regs, 756 int sig = fpu_emulator_cop1Handler(regs,
758 &current->thread.fpu.soft); 757 &current->thread.fpu);
759 if (sig) 758 if (sig)
760 force_sig(sig, current); 759 force_sig(sig, current);
761#ifdef CONFIG_MIPS_MT_FPAFF 760#ifdef CONFIG_MIPS_MT_FPAFF
diff --git a/arch/mips/lasat/setup.c b/arch/mips/lasat/setup.c
index bb70a8240e61..3f64277429e4 100644
--- a/arch/mips/lasat/setup.c
+++ b/arch/mips/lasat/setup.c
@@ -155,7 +155,7 @@ void __init serial_init(void)
155} 155}
156#endif 156#endif
157 157
158void __init plat_setup(void) 158void __init plat_mem_setup(void)
159{ 159{
160 int i; 160 int i;
161 lasat_misc = &lasat_misc_info[mips_machtype]; 161 lasat_misc = &lasat_misc_info[mips_machtype];
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index cf12caf80774..b225543f5302 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -7,4 +7,7 @@ lib-y += csum_partial_copy.o memcpy.o promlib.o strlen_user.o strncpy_user.o \
7 7
8obj-y += iomap.o 8obj-y += iomap.o
9 9
10# libgcc-style stuff needed in the kernel
11lib-y += ashldi3.o ashrdi3.o lshrdi3.o
12
10EXTRA_AFLAGS := $(CFLAGS) 13EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/lib/ashldi3.c b/arch/mips/lib/ashldi3.c
new file mode 100644
index 000000000000..beb80f316095
--- /dev/null
+++ b/arch/mips/lib/ashldi3.c
@@ -0,0 +1,29 @@
1#include <linux/module.h>
2
3#include "libgcc.h"
4
5long long __ashldi3(long long u, word_type b)
6{
7 DWunion uu, w;
8 word_type bm;
9
10 if (b == 0)
11 return u;
12
13 uu.ll = u;
14 bm = 32 - b;
15
16 if (bm <= 0) {
17 w.s.low = 0;
18 w.s.high = (unsigned int) uu.s.low << -bm;
19 } else {
20 const unsigned int carries = (unsigned int) uu.s.low >> bm;
21
22 w.s.low = (unsigned int) uu.s.low << b;
23 w.s.high = ((unsigned int) uu.s.high << b) | carries;
24 }
25
26 return w.ll;
27}
28
29EXPORT_SYMBOL(__ashldi3);
diff --git a/arch/mips/lib/ashrdi3.c b/arch/mips/lib/ashrdi3.c
new file mode 100644
index 000000000000..c884a912b660
--- /dev/null
+++ b/arch/mips/lib/ashrdi3.c
@@ -0,0 +1,31 @@
1#include <linux/module.h>
2
3#include "libgcc.h"
4
5long long __ashrdi3(long long u, word_type b)
6{
7 DWunion uu, w;
8 word_type bm;
9
10 if (b == 0)
11 return u;
12
13 uu.ll = u;
14 bm = 32 - b;
15
16 if (bm <= 0) {
17 /* w.s.high = 1..1 or 0..0 */
18 w.s.high =
19 uu.s.high >> 31;
20 w.s.low = uu.s.high >> -bm;
21 } else {
22 const unsigned int carries = (unsigned int) uu.s.high << bm;
23
24 w.s.high = uu.s.high >> b;
25 w.s.low = ((unsigned int) uu.s.low >> b) | carries;
26 }
27
28 return w.ll;
29}
30
31EXPORT_SYMBOL(__ashrdi3);
diff --git a/arch/mips/lib/libgcc.h b/arch/mips/lib/libgcc.h
new file mode 100644
index 000000000000..3f19d1c5d942
--- /dev/null
+++ b/arch/mips/lib/libgcc.h
@@ -0,0 +1,26 @@
1#ifndef __ASM_LIBGCC_H
2#define __ASM_LIBGCC_H
3
4#include <asm/byteorder.h>
5
6typedef int word_type __attribute__ ((mode (__word__)));
7
8#ifdef __BIG_ENDIAN
9struct DWstruct {
10 int high, low;
11};
12#elif defined(__LITTLE_ENDIAN)
13struct DWstruct {
14 int low, high;
15};
16#else
17#error I feel sick.
18#endif
19
20typedef union
21{
22 struct DWstruct s;
23 long long ll;
24} DWunion;
25
26#endif /* __ASM_LIBGCC_H */
diff --git a/arch/mips/lib/lshrdi3.c b/arch/mips/lib/lshrdi3.c
new file mode 100644
index 000000000000..dcf8d6810b7c
--- /dev/null
+++ b/arch/mips/lib/lshrdi3.c
@@ -0,0 +1,29 @@
1#include <linux/module.h>
2
3#include "libgcc.h"
4
5long long __lshrdi3(long long u, word_type b)
6{
7 DWunion uu, w;
8 word_type bm;
9
10 if (b == 0)
11 return u;
12
13 uu.ll = u;
14 bm = 32 - b;
15
16 if (bm <= 0) {
17 w.s.high = 0;
18 w.s.low = (unsigned int) uu.s.high >> -bm;
19 } else {
20 const unsigned int carries = (unsigned int) uu.s.high << bm;
21
22 w.s.high = (unsigned int) uu.s.high >> b;
23 w.s.low = ((unsigned int) uu.s.low >> b) | carries;
24 }
25
26 return w.ll;
27}
28
29EXPORT_SYMBOL(__lshrdi3);
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index aa5818a0d884..3f0d5d26d506 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -60,15 +60,15 @@
60 60
61/* Function which emulates a floating point instruction. */ 61/* Function which emulates a floating point instruction. */
62 62
63static int fpu_emu(struct pt_regs *, struct mips_fpu_soft_struct *, 63static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
64 mips_instruction); 64 mips_instruction);
65 65
66#if __mips >= 4 && __mips != 32 66#if __mips >= 4 && __mips != 32
67static int fpux_emu(struct pt_regs *, 67static int fpux_emu(struct pt_regs *,
68 struct mips_fpu_soft_struct *, mips_instruction); 68 struct mips_fpu_struct *, mips_instruction);
69#endif 69#endif
70 70
71/* Further private data for which no space exists in mips_fpu_soft_struct */ 71/* Further private data for which no space exists in mips_fpu_struct */
72 72
73struct mips_fpu_emulator_stats fpuemustats; 73struct mips_fpu_emulator_stats fpuemustats;
74 74
@@ -203,7 +203,7 @@ static int isBranchInstr(mips_instruction * i)
203 * Two instructions if the instruction is in a branch delay slot. 203 * Two instructions if the instruction is in a branch delay slot.
204 */ 204 */
205 205
206static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) 206static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
207{ 207{
208 mips_instruction ir; 208 mips_instruction ir;
209 void * emulpc, *contpc; 209 void * emulpc, *contpc;
@@ -595,7 +595,7 @@ DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub,);
595DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); 595DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
596DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); 596DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
597 597
598static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, 598static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
599 mips_instruction ir) 599 mips_instruction ir)
600{ 600{
601 unsigned rcsr = 0; /* resulting csr */ 601 unsigned rcsr = 0; /* resulting csr */
@@ -759,7 +759,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
759/* 759/*
760 * Emulate a single COP1 arithmetic instruction. 760 * Emulate a single COP1 arithmetic instruction.
761 */ 761 */
762static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, 762static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
763 mips_instruction ir) 763 mips_instruction ir)
764{ 764{
765 int rfmt; /* resulting format */ 765 int rfmt; /* resulting format */
@@ -1233,8 +1233,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
1233 return 0; 1233 return 0;
1234} 1234}
1235 1235
1236int fpu_emulator_cop1Handler(struct pt_regs *xcp, 1236int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
1237 struct mips_fpu_soft_struct *ctx)
1238{ 1237{
1239 unsigned long oldepc, prevepc; 1238 unsigned long oldepc, prevepc;
1240 mips_instruction insn; 1239 mips_instruction insn;
diff --git a/arch/mips/math-emu/ieee754.h b/arch/mips/math-emu/ieee754.h
index 171f177c0f88..dd917332792c 100644
--- a/arch/mips/math-emu/ieee754.h
+++ b/arch/mips/math-emu/ieee754.h
@@ -329,7 +329,7 @@ struct _ieee754_csr {
329 unsigned pad0:7; 329 unsigned pad0:7;
330#endif 330#endif
331}; 331};
332#define ieee754_csr (*(struct _ieee754_csr *)(&current->thread.fpu.soft.fcr31)) 332#define ieee754_csr (*(struct _ieee754_csr *)(&current->thread.fpu.fcr31))
333 333
334static inline unsigned ieee754_getrm(void) 334static inline unsigned ieee754_getrm(void)
335{ 335{
diff --git a/arch/mips/math-emu/kernel_linkage.c b/arch/mips/math-emu/kernel_linkage.c
index d187ab71c2ff..56ca0c6a7178 100644
--- a/arch/mips/math-emu/kernel_linkage.c
+++ b/arch/mips/math-emu/kernel_linkage.c
@@ -39,9 +39,9 @@ void fpu_emulator_init_fpu(void)
39 printk("Algorithmics/MIPS FPU Emulator v1.5\n"); 39 printk("Algorithmics/MIPS FPU Emulator v1.5\n");
40 } 40 }
41 41
42 current->thread.fpu.soft.fcr31 = 0; 42 current->thread.fpu.fcr31 = 0;
43 for (i = 0; i < 32; i++) { 43 for (i = 0; i < 32; i++) {
44 current->thread.fpu.soft.fpr[i] = SIGNALLING_NAN; 44 current->thread.fpu.fpr[i] = SIGNALLING_NAN;
45 } 45 }
46} 46}
47 47
@@ -59,10 +59,9 @@ int fpu_emulator_save_context(struct sigcontext *sc)
59 59
60 for (i = 0; i < 32; i++) { 60 for (i = 0; i < 32; i++) {
61 err |= 61 err |=
62 __put_user(current->thread.fpu.soft.fpr[i], 62 __put_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]);
63 &sc->sc_fpregs[i]);
64 } 63 }
65 err |= __put_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr); 64 err |= __put_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr);
66 65
67 return err; 66 return err;
68} 67}
@@ -74,10 +73,9 @@ int fpu_emulator_restore_context(struct sigcontext *sc)
74 73
75 for (i = 0; i < 32; i++) { 74 for (i = 0; i < 32; i++) {
76 err |= 75 err |=
77 __get_user(current->thread.fpu.soft.fpr[i], 76 __get_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]);
78 &sc->sc_fpregs[i]);
79 } 77 }
80 err |= __get_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr); 78 err |= __get_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr);
81 79
82 return err; 80 return err;
83} 81}
@@ -94,10 +92,9 @@ int fpu_emulator_save_context32(struct sigcontext32 *sc)
94 92
95 for (i = 0; i < 32; i+=2) { 93 for (i = 0; i < 32; i+=2) {
96 err |= 94 err |=
97 __put_user(current->thread.fpu.soft.fpr[i], 95 __put_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]);
98 &sc->sc_fpregs[i]);
99 } 96 }
100 err |= __put_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr); 97 err |= __put_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr);
101 98
102 return err; 99 return err;
103} 100}
@@ -109,10 +106,9 @@ int fpu_emulator_restore_context32(struct sigcontext32 *sc)
109 106
110 for (i = 0; i < 32; i+=2) { 107 for (i = 0; i < 32; i+=2) {
111 err |= 108 err |=
112 __get_user(current->thread.fpu.soft.fpr[i], 109 __get_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]);
113 &sc->sc_fpregs[i]);
114 } 110 }
115 err |= __get_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr); 111 err |= __get_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr);
116 112
117 return err; 113 return err;
118} 114}
diff --git a/arch/mips/mips-boards/atlas/atlas_setup.c b/arch/mips/mips-boards/atlas/atlas_setup.c
index c20d401ecf80..8cc9effcb832 100644
--- a/arch/mips/mips-boards/atlas/atlas_setup.c
+++ b/arch/mips/mips-boards/atlas/atlas_setup.c
@@ -50,7 +50,7 @@ const char *get_system_type(void)
50 return "MIPS Atlas"; 50 return "MIPS Atlas";
51} 51}
52 52
53void __init plat_setup(void) 53void __init plat_mem_setup(void)
54{ 54{
55 mips_pcibios_init(); 55 mips_pcibios_init();
56 56
diff --git a/arch/mips/mips-boards/generic/memory.c b/arch/mips/mips-boards/generic/memory.c
index bc4d093685bb..fd492562584a 100644
--- a/arch/mips/mips-boards/generic/memory.c
+++ b/arch/mips/mips-boards/generic/memory.c
@@ -76,6 +76,15 @@ struct prom_pmemblock * __init prom_getmdesc(void)
76 memsize = simple_strtol(memsize_str, NULL, 0); 76 memsize = simple_strtol(memsize_str, NULL, 0);
77 } 77 }
78 } 78 }
79
80#ifdef CONFIG_CPU_BIG_ENDIAN
81 /*
82 * SOC-it swaps, or perhaps doesn't swap, when DMA'ing the last
83 * word of physical memory
84 */
85 memsize -= PAGE_SIZE;
86#endif
87
79 memset(mdesc, 0, sizeof(mdesc)); 88 memset(mdesc, 0, sizeof(mdesc));
80 89
81 mdesc[0].type = yamon_dontuse; 90 mdesc[0].type = yamon_dontuse;
diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c
index b8488aab6df1..0766e434b6bd 100644
--- a/arch/mips/mips-boards/malta/malta_setup.c
+++ b/arch/mips/mips-boards/malta/malta_setup.c
@@ -53,11 +53,11 @@ extern void kgdb_config(void);
53#endif 53#endif
54 54
55struct resource standard_io_resources[] = { 55struct resource standard_io_resources[] = {
56 { "dma1", 0x00, 0x1f, IORESOURCE_BUSY }, 56 { .name = "dma1", .start = 0x00, .end = 0x1f, .flags = IORESOURCE_BUSY },
57 { "timer", 0x40, 0x5f, IORESOURCE_BUSY }, 57 { .name = "timer", .start = 0x40, .end = 0x5f, .flags = IORESOURCE_BUSY },
58 { "keyboard", 0x60, 0x6f, IORESOURCE_BUSY }, 58 { .name = "keyboard", .start = 0x60, .end = 0x6f, .flags = IORESOURCE_BUSY },
59 { "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY }, 59 { .name = "dma page reg", .start = 0x80, .end = 0x8f, .flags = IORESOURCE_BUSY },
60 { "dma2", 0xc0, 0xdf, IORESOURCE_BUSY }, 60 { .name = "dma2", .start = 0xc0, .end = 0xdf, .flags = IORESOURCE_BUSY },
61}; 61};
62 62
63#ifdef CONFIG_MTD 63#ifdef CONFIG_MTD
@@ -111,7 +111,7 @@ void __init fd_activate(void)
111} 111}
112#endif 112#endif
113 113
114void __init plat_setup(void) 114void __init plat_mem_setup(void)
115{ 115{
116 unsigned int i; 116 unsigned int i;
117 117
diff --git a/arch/mips/mips-boards/malta/malta_smp.c b/arch/mips/mips-boards/malta/malta_smp.c
index 6c6c8eeedbce..cf967170fe29 100644
--- a/arch/mips/mips-boards/malta/malta_smp.c
+++ b/arch/mips/mips-boards/malta/malta_smp.c
@@ -34,25 +34,6 @@ void core_send_ipi(int cpu, unsigned int action)
34} 34}
35 35
36/* 36/*
37 * Detect available CPUs/VPEs/TCs and populate phys_cpu_present_map
38 */
39
40void __init prom_build_cpu_map(void)
41{
42 int nextslot;
43
44 /*
45 * As of November, 2004, MIPSsim only simulates one core
46 * at a time. However, that core may be a MIPS MT core
47 * with multiple virtual processors and thread contexts.
48 */
49
50 if (read_c0_config3() & (1<<2)) {
51 nextslot = mipsmt_build_cpu_map(1);
52 }
53}
54
55/*
56 * Platform "CPU" startup hook 37 * Platform "CPU" startup hook
57 */ 38 */
58 39
diff --git a/arch/mips/mips-boards/sead/sead_setup.c b/arch/mips/mips-boards/sead/sead_setup.c
index 4266ce445174..6430f11f3a95 100644
--- a/arch/mips/mips-boards/sead/sead_setup.c
+++ b/arch/mips/mips-boards/sead/sead_setup.c
@@ -45,7 +45,7 @@ const char *get_system_type(void)
45 return "MIPS SEAD"; 45 return "MIPS SEAD";
46} 46}
47 47
48void __init plat_setup(void) 48void __init plat_mem_setup(void)
49{ 49{
50 ioport_resource.end = 0x7fffffff; 50 ioport_resource.end = 0x7fffffff;
51 51
diff --git a/arch/mips/mips-boards/sim/sim_setup.c b/arch/mips/mips-boards/sim/sim_setup.c
index a2fd62997ca3..15a5dac4ae19 100644
--- a/arch/mips/mips-boards/sim/sim_setup.c
+++ b/arch/mips/mips-boards/sim/sim_setup.c
@@ -50,7 +50,7 @@ const char *get_system_type(void)
50 return "MIPSsim"; 50 return "MIPSsim";
51} 51}
52 52
53void __init plat_setup(void) 53void __init plat_mem_setup(void)
54{ 54{
55 set_io_port_base(0xbfd00000); 55 set_io_port_base(0xbfd00000);
56 56
diff --git a/arch/mips/mips-boards/sim/sim_smp.c b/arch/mips/mips-boards/sim/sim_smp.c
index b7084e7c4bf9..004070956cca 100644
--- a/arch/mips/mips-boards/sim/sim_smp.c
+++ b/arch/mips/mips-boards/sim/sim_smp.c
@@ -51,27 +51,6 @@ void core_send_ipi(int cpu, unsigned int action)
51} 51}
52 52
53/* 53/*
54 * Detect available CPUs/VPEs/TCs and populate phys_cpu_present_map
55 */
56
57void __init prom_build_cpu_map(void)
58{
59#ifdef CONFIG_MIPS_MT_SMTC
60 int nextslot;
61
62 /*
63 * As of November, 2004, MIPSsim only simulates one core
64 * at a time. However, that core may be a MIPS MT core
65 * with multiple virtual processors and thread contexts.
66 */
67
68 if (read_c0_config3() & (1<<2)) {
69 nextslot = mipsmt_build_cpu_map(1);
70 }
71#endif /* CONFIG_MIPS_MT_SMTC */
72}
73
74/*
75 * Platform "CPU" startup hook 54 * Platform "CPU" startup hook
76 */ 55 */
77 56
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index 9dca099ba16b..965cb4c4359d 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -413,7 +413,6 @@ out:
413 return ret; 413 return ret;
414} 414}
415 415
416extern void __init sanitize_tlb_entries(void);
417static void __init probe_tlb(unsigned long config) 416static void __init probe_tlb(unsigned long config)
418{ 417{
419 struct cpuinfo_mips *c = &current_cpu_data; 418 struct cpuinfo_mips *c = &current_cpu_data;
diff --git a/arch/mips/momentum/jaguar_atx/setup.c b/arch/mips/momentum/jaguar_atx/setup.c
index 1379c76845dc..df1485501ce6 100644
--- a/arch/mips/momentum/jaguar_atx/setup.c
+++ b/arch/mips/momentum/jaguar_atx/setup.c
@@ -359,7 +359,7 @@ static __init int __init ja_pci_init(void)
359 359
360arch_initcall(ja_pci_init); 360arch_initcall(ja_pci_init);
361 361
362void __init plat_setup(void) 362void __init plat_mem_setup(void)
363{ 363{
364 unsigned int tmpword; 364 unsigned int tmpword;
365 365
diff --git a/arch/mips/momentum/ocelot_3/setup.c b/arch/mips/momentum/ocelot_3/setup.c
index c69195234309..8c53490ba6f1 100644
--- a/arch/mips/momentum/ocelot_3/setup.c
+++ b/arch/mips/momentum/ocelot_3/setup.c
@@ -313,7 +313,7 @@ static __init int __init ja_pci_init(void)
313 313
314arch_initcall(ja_pci_init); 314arch_initcall(ja_pci_init);
315 315
316void __init plat_setup(void) 316void __init plat_mem_setup(void)
317{ 317{
318 unsigned int tmpword; 318 unsigned int tmpword;
319 319
diff --git a/arch/mips/momentum/ocelot_c/setup.c b/arch/mips/momentum/ocelot_c/setup.c
index a3e6f5575592..257e1d1b72dd 100644
--- a/arch/mips/momentum/ocelot_c/setup.c
+++ b/arch/mips/momentum/ocelot_c/setup.c
@@ -231,7 +231,7 @@ void momenco_time_init(void)
231 rtc_mips_set_time = m48t37y_set_time; 231 rtc_mips_set_time = m48t37y_set_time;
232} 232}
233 233
234void __init plat_setup(void) 234void __init plat_mem_setup(void)
235{ 235{
236 unsigned int tmpword; 236 unsigned int tmpword;
237 237
diff --git a/arch/mips/momentum/ocelot_g/setup.c b/arch/mips/momentum/ocelot_g/setup.c
index fed4e8eee116..72143ab1e900 100644
--- a/arch/mips/momentum/ocelot_g/setup.c
+++ b/arch/mips/momentum/ocelot_g/setup.c
@@ -162,7 +162,7 @@ static void __init setup_l3cache(unsigned long size)
162 printk("Done\n"); 162 printk("Done\n");
163} 163}
164 164
165void __init plat_setup(void) 165void __init plat_mem_setup(void)
166{ 166{
167 void (*l3func)(unsigned long) = (void *) KSEG1ADDR(setup_l3cache); 167 void (*l3func)(unsigned long) = (void *) KSEG1ADDR(setup_l3cache);
168 unsigned int tmpword; 168 unsigned int tmpword;
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 16205b587338..465778c5d816 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -18,12 +18,12 @@ obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
18obj-$(CONFIG_MIPS_TX3927) += ops-tx3927.o 18obj-$(CONFIG_MIPS_TX3927) += ops-tx3927.o
19obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o 19obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o
20obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o 20obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o
21obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
21 22
22# 23#
23# These are still pretty much in the old state, watch, go blind. 24# These are still pretty much in the old state, watch, go blind.
24# 25#
25obj-$(CONFIG_DDB5074) += fixup-ddb5074.o pci-ddb5074.o ops-ddb5074.o 26obj-$(CONFIG_BASLER_EXCITE) = ops-titan.o pci-excite.o fixup-excite.o
26obj-$(CONFIG_DDB5476) += ops-ddb5476.o pci-ddb5476.o
27obj-$(CONFIG_DDB5477) += fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o 27obj-$(CONFIG_DDB5477) += fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o
28obj-$(CONFIG_LASAT) += pci-lasat.o 28obj-$(CONFIG_LASAT) += pci-lasat.o
29obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o 29obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o
@@ -43,7 +43,7 @@ obj-$(CONFIG_MOMENCO_OCELOT_C) += fixup-ocelot-c.o pci-ocelot-c.o
43obj-$(CONFIG_MOMENCO_OCELOT_G) += fixup-ocelot-g.o pci-ocelot-g.o 43obj-$(CONFIG_MOMENCO_OCELOT_G) += fixup-ocelot-g.o pci-ocelot-g.o
44obj-$(CONFIG_PMC_YOSEMITE) += fixup-yosemite.o ops-titan.o ops-titan-ht.o \ 44obj-$(CONFIG_PMC_YOSEMITE) += fixup-yosemite.o ops-titan.o ops-titan-ht.o \
45 pci-yosemite.o 45 pci-yosemite.o
46obj-$(CONFIG_SGI_IP27) += pci-ip27.o 46obj-$(CONFIG_SGI_IP27) += ops-bridge.o pci-ip27.o
47obj-$(CONFIG_SGI_IP32) += fixup-ip32.o ops-mace.o pci-ip32.o 47obj-$(CONFIG_SGI_IP32) += fixup-ip32.o ops-mace.o pci-ip32.o
48obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o 48obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o
49obj-$(CONFIG_SIBYTE_BCM112X) += fixup-sb1250.o pci-sb1250.o 49obj-$(CONFIG_SIBYTE_BCM112X) += fixup-sb1250.o pci-sb1250.o
@@ -57,3 +57,4 @@ obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o ops-tx4927.o
57obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-tx4938.o ops-tx4938.o 57obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-tx4938.o ops-tx4938.o
58obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o 58obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
59obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o 59obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
60obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
diff --git a/arch/mips/pci/fixup-ddb5074.c b/arch/mips/pci/fixup-ddb5074.c
deleted file mode 100644
index 5a4a7c239c42..000000000000
--- a/arch/mips/pci/fixup-ddb5074.c
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * It's nice to have the LEDs on the GPIO pins available for debugging
3 */
4static void ddb5074_fixup(struct pci_dev *dev)
5{
6 extern struct pci_dev *pci_pmu;
7 u8 t8;
8
9 pci_pmu = dev; /* for LEDs D2 and D3 */
10 /* Program the lines for LEDs D2 and D3 to output */
11 pci_read_config_byte(dev, 0x7d, &t8);
12 t8 |= 0xc0;
13 pci_write_config_byte(dev, 0x7d, t8);
14 /* Turn LEDs D2 and D3 off */
15 pci_read_config_byte(dev, 0x7e, &t8);
16 t8 |= 0xc0;
17 pci_write_config_byte(dev, 0x7e, t8);
18}
19
20DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101,
21 ddb5074_fixup);
diff --git a/arch/mips/pci/fixup-emma2rh.c b/arch/mips/pci/fixup-emma2rh.c
new file mode 100644
index 000000000000..3a34cd0efd6b
--- /dev/null
+++ b/arch/mips/pci/fixup-emma2rh.c
@@ -0,0 +1,102 @@
1/*
2 * arch/mips/pci/fixup-emma2rh.c
3 * This file defines the PCI configration.
4 *
5 * Copyright (C) NEC Electronics Corporation 2004-2006
6 *
7 * This file is based on the arch/mips/ddb5xxx/ddb5477/pci.c
8 *
9 * Copyright 2001 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25
26#include <linux/config.h>
27#include <linux/kernel.h>
28#include <linux/init.h>
29#include <linux/types.h>
30#include <linux/pci.h>
31
32#include <asm/bootinfo.h>
33#include <asm/debug.h>
34
35#include <asm/emma2rh/emma2rh.h>
36
37#define EMMA2RH_PCI_HOST_SLOT 0x09
38#define EMMA2RH_USB_SLOT 0x03
39#define PCI_DEVICE_ID_NEC_EMMA2RH 0x014b /* EMMA2RH PCI Host */
40
41/*
42 * we fix up irqs based on the slot number.
43 * The first entry is at AD:11.
44 * Fortunately this works because, although we have two pci buses,
45 * they all have different slot numbers (except for rockhopper slot 20
46 * which is handled below).
47 *
48 */
49
50#define MAX_SLOT_NUM 10
51static unsigned char irq_map[][5] __initdata = {
52 [3] = {0, MARKEINS_PCI_IRQ_INTB, MARKEINS_PCI_IRQ_INTC,
53 MARKEINS_PCI_IRQ_INTD, 0,},
54 [4] = {0, MARKEINS_PCI_IRQ_INTA, 0, 0, 0,},
55 [5] = {0, 0, 0, 0, 0,},
56 [6] = {0, MARKEINS_PCI_IRQ_INTC, MARKEINS_PCI_IRQ_INTD,
57 MARKEINS_PCI_IRQ_INTA, MARKEINS_PCI_IRQ_INTB,},
58};
59
60static void __devinit nec_usb_controller_fixup(struct pci_dev *dev)
61{
62 if (PCI_SLOT(dev->devfn) == EMMA2RH_USB_SLOT)
63 /* on board USB controller configuration */
64 pci_write_config_dword(dev, 0xe4, 1 << 5);
65}
66
67DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
68 nec_usb_controller_fixup);
69
70/*
71 * Prevent the PCI layer from seeing the resources allocated to this device
72 * if it is the host bridge by marking it as such. These resources are of
73 * no consequence to the PCI layer (they are handled elsewhere).
74 */
75static void __devinit emma2rh_pci_host_fixup(struct pci_dev *dev)
76{
77 int i;
78
79 if (PCI_SLOT(dev->devfn) == EMMA2RH_PCI_HOST_SLOT) {
80 dev->class &= 0xff;
81 dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
82 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
83 dev->resource[i].start = 0;
84 dev->resource[i].end = 0;
85 dev->resource[i].flags = 0;
86 }
87 }
88}
89
90DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_EMMA2RH,
91 emma2rh_pci_host_fixup);
92
93int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
94{
95 return irq_map[slot][pin];
96}
97
98/* Do platform specific device initialization at pci_enable_device() time */
99int pcibios_plat_dev_init(struct pci_dev *dev)
100{
101 return 0;
102}
diff --git a/arch/mips/pci/fixup-excite.c b/arch/mips/pci/fixup-excite.c
new file mode 100644
index 000000000000..1da696d43f00
--- /dev/null
+++ b/arch/mips/pci/fixup-excite.c
@@ -0,0 +1,36 @@
1/*
2 * Copyright (C) 2004 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/pci.h>
22#include <excite.h>
23
24int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
25{
26 if (pin == 0)
27 return -1;
28
29 return USB_IRQ; /* USB controller is the only PCI device */
30}
31
32/* Do platform specific device initialization at pci_enable_device() time */
33int pcibios_plat_dev_init(struct pci_dev *dev)
34{
35 return 0;
36}
diff --git a/arch/mips/pci/fixup-wrppmc.c b/arch/mips/pci/fixup-wrppmc.c
new file mode 100644
index 000000000000..3357c1300bb1
--- /dev/null
+++ b/arch/mips/pci/fixup-wrppmc.c
@@ -0,0 +1,37 @@
1/*
2 * fixup-wrppmc.c: PPMC board specific PCI fixup
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2006, Wind River Inc. Rongkai.zhan (rongkai.zhan@windriver.com)
9 */
10#include <linux/init.h>
11#include <linux/pci.h>
12#include <asm/gt64120.h>
13
14/* PCI interrupt pins */
15#define PCI_INTA 1
16#define PCI_INTB 2
17#define PCI_INTC 3
18#define PCI_INTD 4
19
20#define PCI_SLOT_MAXNR 32 /* Each PCI bus has 32 physical slots */
21
22static char pci_irq_tab[PCI_SLOT_MAXNR][5] __initdata = {
23 /* 0 INTA INTB INTC INTD */
24 [0] = {0, 0, 0, 0, 0}, /* Slot 0: GT64120 PCI bridge */
25 [6] = {0, WRPPMC_PCI_INTA_IRQ, 0, 0, 0},
26};
27
28int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
29{
30 return pci_irq_tab[slot][pin];
31}
32
33/* Do platform specific device initialization at pci_enable_device() time */
34int pcibios_plat_dev_init(struct pci_dev *dev)
35{
36 return 0;
37}
diff --git a/arch/mips/pci/ops-bridge.c b/arch/mips/pci/ops-bridge.c
new file mode 100644
index 000000000000..1fa09929cd7a
--- /dev/null
+++ b/arch/mips/pci/ops-bridge.c
@@ -0,0 +1,306 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1999, 2000, 04, 06 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 */
9#include <linux/pci.h>
10#include <asm/paccess.h>
11#include <asm/pci/bridge.h>
12#include <asm/sn/arch.h>
13#include <asm/sn/intr.h>
14#include <asm/sn/sn0/hub.h>
15
16/*
17 * The Bridge ASIC supports both type 0 and type 1 access. Type 1 is
18 * not really documented, so right now I can't write code which uses it.
19 * Therefore we use type 0 accesses for now even though they won't work
20 * correcly for PCI-to-PCI bridges.
21 *
22 * The function is complicated by the ultimate brokeness of the IOC3 chip
23 * which is used in SGI systems. The IOC3 can only handle 32-bit PCI
24 * accesses and does only decode parts of it's address space.
25 */
26
27static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn,
28 int where, int size, u32 * value)
29{
30 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
31 bridge_t *bridge = bc->base;
32 int slot = PCI_SLOT(devfn);
33 int fn = PCI_FUNC(devfn);
34 volatile void *addr;
35 u32 cf, shift, mask;
36 int res;
37
38 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
39 if (get_dbe(cf, (u32 *) addr))
40 return PCIBIOS_DEVICE_NOT_FOUND;
41
42 /*
43 * IOC3 is fucked fucked beyond believe ... Don't even give the
44 * generic PCI code a chance to look at it for real ...
45 */
46 if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
47 goto oh_my_gawd;
48
49 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
50
51 if (size == 1)
52 res = get_dbe(*value, (u8 *) addr);
53 else if (size == 2)
54 res = get_dbe(*value, (u16 *) addr);
55 else
56 res = get_dbe(*value, (u32 *) addr);
57
58 return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
59
60oh_my_gawd:
61
62 /*
63 * IOC3 is fucked fucked beyond believe ... Don't even give the
64 * generic PCI code a chance to look at the wrong register.
65 */
66 if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
67 *value = 0;
68 return PCIBIOS_SUCCESSFUL;
69 }
70
71 /*
72 * IOC3 is fucked fucked beyond believe ... Don't try to access
73 * anything but 32-bit words ...
74 */
75 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
76
77 if (get_dbe(cf, (u32 *) addr))
78 return PCIBIOS_DEVICE_NOT_FOUND;
79
80 shift = ((where & 3) << 3);
81 mask = (0xffffffffU >> ((4 - size) << 3));
82 *value = (cf >> shift) & mask;
83
84 return PCIBIOS_SUCCESSFUL;
85}
86
87static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn,
88 int where, int size, u32 * value)
89{
90 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
91 bridge_t *bridge = bc->base;
92 int busno = bus->number;
93 int slot = PCI_SLOT(devfn);
94 int fn = PCI_FUNC(devfn);
95 volatile void *addr;
96 u32 cf, shift, mask;
97 int res;
98
99 bridge->b_pci_cfg = (busno << 16) | (slot << 11);
100 addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
101 if (get_dbe(cf, (u32 *) addr))
102 return PCIBIOS_DEVICE_NOT_FOUND;
103
104 /*
105 * IOC3 is fucked fucked beyond believe ... Don't even give the
106 * generic PCI code a chance to look at it for real ...
107 */
108 if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
109 goto oh_my_gawd;
110
111 bridge->b_pci_cfg = (busno << 16) | (slot << 11);
112 addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
113
114 if (size == 1)
115 res = get_dbe(*value, (u8 *) addr);
116 else if (size == 2)
117 res = get_dbe(*value, (u16 *) addr);
118 else
119 res = get_dbe(*value, (u32 *) addr);
120
121 return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
122
123oh_my_gawd:
124
125 /*
126 * IOC3 is fucked fucked beyond believe ... Don't even give the
127 * generic PCI code a chance to look at the wrong register.
128 */
129 if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
130 *value = 0;
131 return PCIBIOS_SUCCESSFUL;
132 }
133
134 /*
135 * IOC3 is fucked fucked beyond believe ... Don't try to access
136 * anything but 32-bit words ...
137 */
138 bridge->b_pci_cfg = (busno << 16) | (slot << 11);
139 addr = &bridge->b_type1_cfg.c[(fn << 8) | where];
140
141 if (get_dbe(cf, (u32 *) addr))
142 return PCIBIOS_DEVICE_NOT_FOUND;
143
144 shift = ((where & 3) << 3);
145 mask = (0xffffffffU >> ((4 - size) << 3));
146 *value = (cf >> shift) & mask;
147
148 return PCIBIOS_SUCCESSFUL;
149}
150
151static int pci_read_config(struct pci_bus *bus, unsigned int devfn,
152 int where, int size, u32 * value)
153{
154 if (bus->number > 0)
155 return pci_conf1_read_config(bus, devfn, where, size, value);
156
157 return pci_conf0_read_config(bus, devfn, where, size, value);
158}
159
160static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn,
161 int where, int size, u32 value)
162{
163 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
164 bridge_t *bridge = bc->base;
165 int slot = PCI_SLOT(devfn);
166 int fn = PCI_FUNC(devfn);
167 volatile void *addr;
168 u32 cf, shift, mask, smask;
169 int res;
170
171 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
172 if (get_dbe(cf, (u32 *) addr))
173 return PCIBIOS_DEVICE_NOT_FOUND;
174
175 /*
176 * IOC3 is fucked fucked beyond believe ... Don't even give the
177 * generic PCI code a chance to look at it for real ...
178 */
179 if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
180 goto oh_my_gawd;
181
182 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
183
184 if (size == 1) {
185 res = put_dbe(value, (u8 *) addr);
186 } else if (size == 2) {
187 res = put_dbe(value, (u16 *) addr);
188 } else {
189 res = put_dbe(value, (u32 *) addr);
190 }
191
192 if (res)
193 return PCIBIOS_DEVICE_NOT_FOUND;
194
195 return PCIBIOS_SUCCESSFUL;
196
197oh_my_gawd:
198
199 /*
200 * IOC3 is fucked fucked beyond believe ... Don't even give the
201 * generic PCI code a chance to touch the wrong register.
202 */
203 if ((where >= 0x14 && where < 0x40) || (where >= 0x48))
204 return PCIBIOS_SUCCESSFUL;
205
206 /*
207 * IOC3 is fucked fucked beyond believe ... Don't try to access
208 * anything but 32-bit words ...
209 */
210 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
211
212 if (get_dbe(cf, (u32 *) addr))
213 return PCIBIOS_DEVICE_NOT_FOUND;
214
215 shift = ((where & 3) << 3);
216 mask = (0xffffffffU >> ((4 - size) << 3));
217 smask = mask << shift;
218
219 cf = (cf & ~smask) | ((value & mask) << shift);
220 if (put_dbe(cf, (u32 *) addr))
221 return PCIBIOS_DEVICE_NOT_FOUND;
222
223 return PCIBIOS_SUCCESSFUL;
224}
225
226static int pci_conf1_write_config(struct pci_bus *bus, unsigned int devfn,
227 int where, int size, u32 value)
228{
229 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
230 bridge_t *bridge = bc->base;
231 int slot = PCI_SLOT(devfn);
232 int fn = PCI_FUNC(devfn);
233 int busno = bus->number;
234 volatile void *addr;
235 u32 cf, shift, mask, smask;
236 int res;
237
238 bridge->b_pci_cfg = (busno << 16) | (slot << 11);
239 addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
240 if (get_dbe(cf, (u32 *) addr))
241 return PCIBIOS_DEVICE_NOT_FOUND;
242
243 /*
244 * IOC3 is fucked fucked beyond believe ... Don't even give the
245 * generic PCI code a chance to look at it for real ...
246 */
247 if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
248 goto oh_my_gawd;
249
250 addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
251
252 if (size == 1) {
253 res = put_dbe(value, (u8 *) addr);
254 } else if (size == 2) {
255 res = put_dbe(value, (u16 *) addr);
256 } else {
257 res = put_dbe(value, (u32 *) addr);
258 }
259
260 if (res)
261 return PCIBIOS_DEVICE_NOT_FOUND;
262
263 return PCIBIOS_SUCCESSFUL;
264
265oh_my_gawd:
266
267 /*
268 * IOC3 is fucked fucked beyond believe ... Don't even give the
269 * generic PCI code a chance to touch the wrong register.
270 */
271 if ((where >= 0x14 && where < 0x40) || (where >= 0x48))
272 return PCIBIOS_SUCCESSFUL;
273
274 /*
275 * IOC3 is fucked fucked beyond believe ... Don't try to access
276 * anything but 32-bit words ...
277 */
278 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
279
280 if (get_dbe(cf, (u32 *) addr))
281 return PCIBIOS_DEVICE_NOT_FOUND;
282
283 shift = ((where & 3) << 3);
284 mask = (0xffffffffU >> ((4 - size) << 3));
285 smask = mask << shift;
286
287 cf = (cf & ~smask) | ((value & mask) << shift);
288 if (put_dbe(cf, (u32 *) addr))
289 return PCIBIOS_DEVICE_NOT_FOUND;
290
291 return PCIBIOS_SUCCESSFUL;
292}
293
294static int pci_write_config(struct pci_bus *bus, unsigned int devfn,
295 int where, int size, u32 value)
296{
297 if (bus->number > 0)
298 return pci_conf1_write_config(bus, devfn, where, size, value);
299
300 return pci_conf0_write_config(bus, devfn, where, size, value);
301}
302
303struct pci_ops bridge_pci_ops = {
304 .read = pci_read_config,
305 .write = pci_write_config,
306};
diff --git a/arch/mips/pci/ops-ddb5074.c b/arch/mips/pci/ops-ddb5074.c
deleted file mode 100644
index 89f97bef4fc4..000000000000
--- a/arch/mips/pci/ops-ddb5074.c
+++ /dev/null
@@ -1,271 +0,0 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * arch/mips/ddb5xxx/ddb5476/pci_ops.c
6 * Define the pci_ops for DB5477.
7 *
8 * Much of the code is derived from the original DDB5074 port by
9 * Geert Uytterhoeven <geert@sonycom.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17#include <linux/pci.h>
18#include <linux/kernel.h>
19#include <linux/types.h>
20
21#include <asm/addrspace.h>
22#include <asm/debug.h>
23
24#include <asm/ddb5xxx/ddb5xxx.h>
25
26/*
27 * config_swap structure records what set of pdar/pmr are used
28 * to access pci config space. It also provides a place hold the
29 * original values for future restoring.
30 */
31struct pci_config_swap {
32 u32 pdar;
33 u32 pmr;
34 u32 config_base;
35 u32 config_size;
36 u32 pdar_backup;
37 u32 pmr_backup;
38};
39
40/*
41 * On DDB5476, we have one set of swap registers
42 */
43struct pci_config_swap ext_pci_swap = {
44 DDB_PCIW0,
45 DDB_PCIINIT0,
46 DDB_PCI_CONFIG_BASE,
47 DDB_PCI_CONFIG_SIZE
48};
49
50static int pci_config_workaround = 1;
51
52/*
53 * access config space
54 */
55static inline u32 ddb_access_config_base(struct pci_config_swap *swap, u32 bus, /* 0 means top level bus */
56 u32 slot_num)
57{
58 u32 pci_addr = 0;
59 u32 pciinit_offset = 0;
60 u32 virt_addr = swap->config_base;
61 u32 option;
62
63 if (pci_config_workaround) {
64 if (slot_num == 5)
65 slot_num = 14;
66 } else {
67 if (slot_num == 5)
68 return DDB_BASE + DDB_PCI_BASE;
69 }
70
71 /* minimum pdar (window) size is 2MB */
72 db_assert(swap->config_size >= (2 << 20));
73
74 db_assert(slot_num < (1 << 5));
75 db_assert(bus < (1 << 8));
76
77 /* backup registers */
78 swap->pdar_backup = ddb_in32(swap->pdar);
79 swap->pmr_backup = ddb_in32(swap->pmr);
80
81 /* set the pdar (pci window) register */
82 ddb_set_pdar(swap->pdar, swap->config_base, swap->config_size, 32, /* 32 bit wide */
83 0, /* not on local memory bus */
84 0); /* not visible from PCI bus (N/A) */
85
86 /*
87 * calcuate the absolute pci config addr;
88 * according to the spec, we start scanning from adr:11 (0x800)
89 */
90 if (bus == 0) {
91 /* type 0 config */
92 pci_addr = 0x00040000 << slot_num;
93 } else {
94 /* type 1 config */
95 pci_addr = 0x00040000 << slot_num;
96 panic
97 ("ddb_access_config_base: we don't support type 1 config Yet");
98 }
99
100 /*
101 * if pci_addr is less than pci config window size, we set
102 * pciinit_offset to 0 and adjust the virt_address.
103 * Otherwise we will try to adjust pciinit_offset.
104 */
105 if (pci_addr < swap->config_size) {
106 virt_addr = KSEG1ADDR(swap->config_base + pci_addr);
107 pciinit_offset = 0;
108 } else {
109 db_assert((pci_addr & (swap->config_size - 1)) == 0);
110 virt_addr = KSEG1ADDR(swap->config_base);
111 pciinit_offset = pci_addr;
112 }
113
114 /* set the pmr register */
115 option = DDB_PCI_ACCESS_32;
116 if (bus != 0)
117 option |= DDB_PCI_CFGTYPE1;
118 ddb_set_pmr(swap->pmr, DDB_PCICMD_CFG, pciinit_offset, option);
119
120 return virt_addr;
121}
122
123static inline void ddb_close_config_base(struct pci_config_swap *swap)
124{
125 ddb_out32(swap->pdar, swap->pdar_backup);
126 ddb_out32(swap->pmr, swap->pmr_backup);
127}
128
129static int read_config_dword(struct pci_config_swap *swap,
130 struct pci_dev *dev, u32 where, u32 * val)
131{
132 u32 bus, slot_num, func_num;
133 u32 base;
134
135 db_assert((where & 3) == 0);
136 db_assert(where < (1 << 8));
137
138 /* check if the bus is top-level */
139 if (dev->bus->parent != NULL) {
140 bus = dev->bus->number;
141 db_assert(bus != 0);
142 } else {
143 bus = 0;
144 }
145
146 slot_num = PCI_SLOT(dev->devfn);
147 func_num = PCI_FUNC(dev->devfn);
148 base = ddb_access_config_base(swap, bus, slot_num);
149 *val = *(volatile u32 *) (base + (func_num << 8) + where);
150 ddb_close_config_base(swap);
151 return PCIBIOS_SUCCESSFUL;
152}
153
154static int read_config_word(struct pci_config_swap *swap,
155 struct pci_dev *dev, u32 where, u16 * val)
156{
157 int status;
158 u32 result;
159
160 db_assert((where & 1) == 0);
161
162 status = read_config_dword(swap, dev, where & ~3, &result);
163 if (where & 2)
164 result >>= 16;
165 *val = result & 0xffff;
166 return status;
167}
168
169static int read_config_byte(struct pci_config_swap *swap,
170 struct pci_dev *dev, u32 where, u8 * val)
171{
172 int status;
173 u32 result;
174
175 status = read_config_dword(swap, dev, where & ~3, &result);
176 if (where & 1)
177 result >>= 8;
178 if (where & 2)
179 result >>= 16;
180 *val = result & 0xff;
181 return status;
182}
183
184static int write_config_dword(struct pci_config_swap *swap,
185 struct pci_dev *dev, u32 where, u32 val)
186{
187 u32 bus, slot_num, func_num;
188 u32 base;
189
190 db_assert((where & 3) == 0);
191 db_assert(where < (1 << 8));
192
193 /* check if the bus is top-level */
194 if (dev->bus->parent != NULL) {
195 bus = dev->bus->number;
196 db_assert(bus != 0);
197 } else {
198 bus = 0;
199 }
200
201 slot_num = PCI_SLOT(dev->devfn);
202 func_num = PCI_FUNC(dev->devfn);
203 base = ddb_access_config_base(swap, bus, slot_num);
204 *(volatile u32 *) (base + (func_num << 8) + where) = val;
205 ddb_close_config_base(swap);
206 return PCIBIOS_SUCCESSFUL;
207}
208
209static int write_config_word(struct pci_config_swap *swap,
210 struct pci_dev *dev, u32 where, u16 val)
211{
212 int status, shift = 0;
213 u32 result;
214
215 db_assert((where & 1) == 0);
216
217 status = read_config_dword(swap, dev, where & ~3, &result);
218 if (status != PCIBIOS_SUCCESSFUL)
219 return status;
220
221 if (where & 2)
222 shift += 16;
223 result &= ~(0xffff << shift);
224 result |= val << shift;
225 return write_config_dword(swap, dev, where & ~3, result);
226}
227
228static int write_config_byte(struct pci_config_swap *swap,
229 struct pci_dev *dev, u32 where, u8 val)
230{
231 int status, shift = 0;
232 u32 result;
233
234 status = read_config_dword(swap, dev, where & ~3, &result);
235 if (status != PCIBIOS_SUCCESSFUL)
236 return status;
237
238 if (where & 2)
239 shift += 16;
240 if (where & 1)
241 shift += 8;
242 result &= ~(0xff << shift);
243 result |= val << shift;
244 return write_config_dword(swap, dev, where & ~3, result);
245}
246
247#define MAKE_PCI_OPS(prefix, rw, unitname, unittype, pciswap) \
248static int prefix##_##rw##_config_##unitname(struct pci_dev *dev, int where, unittype val) \
249{ \
250 return rw##_config_##unitname(pciswap, \
251 dev, \
252 where, \
253 val); \
254}
255
256MAKE_PCI_OPS(extpci, read, byte, u8 *, &ext_pci_swap)
257 MAKE_PCI_OPS(extpci, read, word, u16 *, &ext_pci_swap)
258 MAKE_PCI_OPS(extpci, read, dword, u32 *, &ext_pci_swap)
259
260 MAKE_PCI_OPS(extpci, write, byte, u8, &ext_pci_swap)
261 MAKE_PCI_OPS(extpci, write, word, u16, &ext_pci_swap)
262 MAKE_PCI_OPS(extpci, write, dword, u32, &ext_pci_swap)
263
264struct pci_ops ddb5476_ext_pci_ops = {
265 extpci_read_config_byte,
266 extpci_read_config_word,
267 extpci_read_config_dword,
268 extpci_write_config_byte,
269 extpci_write_config_word,
270 extpci_write_config_dword
271};
diff --git a/arch/mips/pci/ops-ddb5476.c b/arch/mips/pci/ops-ddb5476.c
deleted file mode 100644
index 12da58e75ec7..000000000000
--- a/arch/mips/pci/ops-ddb5476.c
+++ /dev/null
@@ -1,286 +0,0 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * arch/mips/ddb5xxx/ddb5476/pci_ops.c
6 * Define the pci_ops for DB5477.
7 *
8 * Much of the code is derived from the original DDB5074 port by
9 * Geert Uytterhoeven <geert@sonycom.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17#include <linux/pci.h>
18#include <linux/kernel.h>
19#include <linux/types.h>
20
21#include <asm/addrspace.h>
22#include <asm/debug.h>
23
24#include <asm/ddb5xxx/ddb5xxx.h>
25
26/*
27 * config_swap structure records what set of pdar/pmr are used
28 * to access pci config space. It also provides a place hold the
29 * original values for future restoring.
30 */
31struct pci_config_swap {
32 u32 pdar;
33 u32 pmr;
34 u32 config_base;
35 u32 config_size;
36 u32 pdar_backup;
37 u32 pmr_backup;
38};
39
40/*
41 * On DDB5476, we have one set of swap registers
42 */
43struct pci_config_swap ext_pci_swap = {
44 DDB_PCIW0,
45 DDB_PCIINIT0,
46 DDB_PCI_CONFIG_BASE,
47 DDB_PCI_CONFIG_SIZE
48};
49
50static int pci_config_workaround = 1;
51
52/*
53 * access config space
54 */
55static inline u32 ddb_access_config_base(struct pci_config_swap *swap, u32 bus, /* 0 means top level bus */
56 u32 slot_num)
57{
58 u32 pci_addr = 0;
59 u32 pciinit_offset = 0;
60 u32 virt_addr = swap->config_base;
61 u32 option;
62
63 if (pci_config_workaround) {
64 /* [jsun] work around Vrc5476 controller itself, returnning
65 * slot 0 essentially makes vrc5476 invisible
66 */
67 if (slot_num == 12)
68 slot_num = 0;
69
70#if 0
71 /* BUG : skip P2P bridge for now */
72 if (slot_num == 5)
73 slot_num = 0;
74#endif
75
76 } else {
77 /* now we have to be hornest, returning the true
78 * PCI config headers for vrc5476
79 */
80 if (slot_num == 12) {
81 swap->pdar_backup = ddb_in32(swap->pdar);
82 swap->pmr_backup = ddb_in32(swap->pmr);
83 return DDB_BASE + DDB_PCI_BASE;
84 }
85 }
86
87 /* minimum pdar (window) size is 2MB */
88 db_assert(swap->config_size >= (2 << 20));
89
90 db_assert(slot_num < (1 << 5));
91 db_assert(bus < (1 << 8));
92
93 /* backup registers */
94 swap->pdar_backup = ddb_in32(swap->pdar);
95 swap->pmr_backup = ddb_in32(swap->pmr);
96
97 /* set the pdar (pci window) register */
98 ddb_set_pdar(swap->pdar, swap->config_base, swap->config_size, 32, /* 32 bit wide */
99 0, /* not on local memory bus */
100 0); /* not visible from PCI bus (N/A) */
101
102 /*
103 * calcuate the absolute pci config addr;
104 * according to the spec, we start scanning from adr:11 (0x800)
105 */
106 if (bus == 0) {
107 /* type 0 config */
108 pci_addr = 0x800 << slot_num;
109 } else {
110 /* type 1 config */
111 pci_addr = (bus << 16) | (slot_num << 11);
112 /* panic("ddb_access_config_base: we don't support type 1 config Yet"); */
113 }
114
115 /*
116 * if pci_addr is less than pci config window size, we set
117 * pciinit_offset to 0 and adjust the virt_address.
118 * Otherwise we will try to adjust pciinit_offset.
119 */
120 if (pci_addr < swap->config_size) {
121 virt_addr = KSEG1ADDR(swap->config_base + pci_addr);
122 pciinit_offset = 0;
123 } else {
124 db_assert((pci_addr & (swap->config_size - 1)) == 0);
125 virt_addr = KSEG1ADDR(swap->config_base);
126 pciinit_offset = pci_addr;
127 }
128
129 /* set the pmr register */
130 option = DDB_PCI_ACCESS_32;
131 if (bus != 0)
132 option |= DDB_PCI_CFGTYPE1;
133 ddb_set_pmr(swap->pmr, DDB_PCICMD_CFG, pciinit_offset, option);
134
135 return virt_addr;
136}
137
138static inline void ddb_close_config_base(struct pci_config_swap *swap)
139{
140 ddb_out32(swap->pdar, swap->pdar_backup);
141 ddb_out32(swap->pmr, swap->pmr_backup);
142}
143
144static int read_config_dword(struct pci_config_swap *swap,
145 struct pci_dev *dev, u32 where, u32 * val)
146{
147 u32 bus, slot_num, func_num;
148 u32 base;
149
150 db_assert((where & 3) == 0);
151 db_assert(where < (1 << 8));
152
153 /* check if the bus is top-level */
154 if (dev->bus->parent != NULL) {
155 bus = dev->bus->number;
156 db_assert(bus != 0);
157 } else {
158 bus = 0;
159 }
160
161 slot_num = PCI_SLOT(dev->devfn);
162 func_num = PCI_FUNC(dev->devfn);
163 base = ddb_access_config_base(swap, bus, slot_num);
164 *val = *(volatile u32 *) (base + (func_num << 8) + where);
165 ddb_close_config_base(swap);
166 return PCIBIOS_SUCCESSFUL;
167}
168
169static int read_config_word(struct pci_config_swap *swap,
170 struct pci_dev *dev, u32 where, u16 * val)
171{
172 int status;
173 u32 result;
174
175 db_assert((where & 1) == 0);
176
177 status = read_config_dword(swap, dev, where & ~3, &result);
178 if (where & 2)
179 result >>= 16;
180 *val = result & 0xffff;
181 return status;
182}
183
184static int read_config_byte(struct pci_config_swap *swap,
185 struct pci_dev *dev, u32 where, u8 * val)
186{
187 int status;
188 u32 result;
189
190 status = read_config_dword(swap, dev, where & ~3, &result);
191 if (where & 1)
192 result >>= 8;
193 if (where & 2)
194 result >>= 16;
195 *val = result & 0xff;
196 return status;
197}
198
199static int write_config_dword(struct pci_config_swap *swap,
200 struct pci_dev *dev, u32 where, u32 val)
201{
202 u32 bus, slot_num, func_num;
203 u32 base;
204
205 db_assert((where & 3) == 0);
206 db_assert(where < (1 << 8));
207
208 /* check if the bus is top-level */
209 if (dev->bus->parent != NULL) {
210 bus = dev->bus->number;
211 db_assert(bus != 0);
212 } else {
213 bus = 0;
214 }
215
216 slot_num = PCI_SLOT(dev->devfn);
217 func_num = PCI_FUNC(dev->devfn);
218 base = ddb_access_config_base(swap, bus, slot_num);
219 *(volatile u32 *) (base + (func_num << 8) + where) = val;
220 ddb_close_config_base(swap);
221 return PCIBIOS_SUCCESSFUL;
222}
223
224static int write_config_word(struct pci_config_swap *swap,
225 struct pci_dev *dev, u32 where, u16 val)
226{
227 int status, shift = 0;
228 u32 result;
229
230 db_assert((where & 1) == 0);
231
232 status = read_config_dword(swap, dev, where & ~3, &result);
233 if (status != PCIBIOS_SUCCESSFUL)
234 return status;
235
236 if (where & 2)
237 shift += 16;
238 result &= ~(0xffff << shift);
239 result |= val << shift;
240 return write_config_dword(swap, dev, where & ~3, result);
241}
242
243static int write_config_byte(struct pci_config_swap *swap,
244 struct pci_dev *dev, u32 where, u8 val)
245{
246 int status, shift = 0;
247 u32 result;
248
249 status = read_config_dword(swap, dev, where & ~3, &result);
250 if (status != PCIBIOS_SUCCESSFUL)
251 return status;
252
253 if (where & 2)
254 shift += 16;
255 if (where & 1)
256 shift += 8;
257 result &= ~(0xff << shift);
258 result |= val << shift;
259 return write_config_dword(swap, dev, where & ~3, result);
260}
261
262#define MAKE_PCI_OPS(prefix, rw, unitname, unittype, pciswap) \
263static int prefix##_##rw##_config_##unitname(struct pci_dev *dev, int where, unittype val) \
264{ \
265 return rw##_config_##unitname(pciswap, \
266 dev, \
267 where, \
268 val); \
269}
270
271MAKE_PCI_OPS(extpci, read, byte, u8 *, &ext_pci_swap)
272 MAKE_PCI_OPS(extpci, read, word, u16 *, &ext_pci_swap)
273 MAKE_PCI_OPS(extpci, read, dword, u32 *, &ext_pci_swap)
274
275 MAKE_PCI_OPS(extpci, write, byte, u8, &ext_pci_swap)
276 MAKE_PCI_OPS(extpci, write, word, u16, &ext_pci_swap)
277 MAKE_PCI_OPS(extpci, write, dword, u32, &ext_pci_swap)
278
279struct pci_ops ddb5476_ext_pci_ops = {
280 extpci_read_config_byte,
281 extpci_read_config_word,
282 extpci_read_config_dword,
283 extpci_write_config_byte,
284 extpci_write_config_word,
285 extpci_write_config_dword
286};
diff --git a/arch/mips/pci/ops-emma2rh.c b/arch/mips/pci/ops-emma2rh.c
new file mode 100644
index 000000000000..e21b11bf66bc
--- /dev/null
+++ b/arch/mips/pci/ops-emma2rh.c
@@ -0,0 +1,186 @@
1/*
2 * arch/mips/pci/ops-emma2rh.c
3 * This file defines the PCI operation for EMMA2RH.
4 *
5 * Copyright (C) NEC Electronics Corporation 2004-2006
6 *
7 * This file is based on the arch/mips/pci/ops-vr41xx.c
8 *
9 * Copyright 2001 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25
26#include <linux/config.h>
27#include <linux/pci.h>
28#include <linux/kernel.h>
29#include <linux/types.h>
30
31#include <asm/addrspace.h>
32#include <asm/debug.h>
33
34#include <asm/emma2rh/emma2rh.h>
35
36#define RTABORT (0x1<<9)
37#define RMABORT (0x1<<10)
38#define EMMA2RH_PCI_SLOT_NUM 9 /* 0000:09.0 is final PCI device */
39
40/*
41 * access config space
42 */
43
44static int check_args(struct pci_bus *bus, u32 devfn, u32 * bus_num)
45{
46 /* check if the bus is top-level */
47 if (bus->parent != NULL) {
48 *bus_num = bus->number;
49 db_assert(bus_num != 0);
50 } else
51 *bus_num = 0;
52
53 if (*bus_num == 0) {
54 /* Type 0 */
55 if (PCI_SLOT(devfn) >= 10)
56 return PCIBIOS_DEVICE_NOT_FOUND;
57 } else {
58 /* Type 1 */
59 if ((*bus_num >= 64) || (PCI_SLOT(devfn) >= 16))
60 return PCIBIOS_DEVICE_NOT_FOUND;
61 }
62 return 0;
63}
64
65static inline int set_pci_configuration_address(unsigned char bus_num,
66 unsigned int devfn, int where)
67{
68 u32 config_win0;
69
70 emma2rh_out32(EMMA2RH_PCI_INT, ~RMABORT);
71 if (bus_num == 0)
72 /*
73 * Type 0 configuration
74 */
75 config_win0 = (1 << (22 + PCI_SLOT(devfn))) | (5 << 9);
76 else
77 /*
78 * Type 1 configuration
79 */
80 config_win0 = (bus_num << 26) | (PCI_SLOT(devfn) << 22) |
81 (1 << 15) | (5 << 9);
82
83 emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, config_win0);
84
85 return 0;
86}
87
88static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
89 int size, uint32_t * val)
90{
91 u32 bus_num;
92 u32 base = KSEG1ADDR(EMMA2RH_PCI_CONFIG_BASE);
93 u32 backup_win0;
94 u32 data;
95
96 *val = 0xffffffffU;
97
98 if (check_args(bus, devfn, &bus_num) == PCIBIOS_DEVICE_NOT_FOUND)
99 return PCIBIOS_DEVICE_NOT_FOUND;
100
101 backup_win0 = emma2rh_in32(EMMA2RH_PCI_IWIN0_CTR);
102
103 if (set_pci_configuration_address(bus_num, devfn, where) < 0)
104 return PCIBIOS_DEVICE_NOT_FOUND;
105
106 data =
107 *(volatile u32 *)(base + (PCI_FUNC(devfn) << 8) +
108 (where & 0xfffffffc));
109
110 switch (size) {
111 case 1:
112 *val = (data >> ((where & 3) << 3)) & 0xffU;
113 break;
114 case 2:
115 *val = (data >> ((where & 2) << 3)) & 0xffffU;
116 break;
117 case 4:
118 *val = data;
119 break;
120 default:
121 emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, backup_win0);
122 return PCIBIOS_FUNC_NOT_SUPPORTED;
123 }
124
125 emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, backup_win0);
126
127 if (emma2rh_in32(EMMA2RH_PCI_INT) & RMABORT)
128 return PCIBIOS_DEVICE_NOT_FOUND;
129
130 return PCIBIOS_SUCCESSFUL;
131}
132
133static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
134 int size, u32 val)
135{
136 u32 bus_num;
137 u32 base = KSEG1ADDR(EMMA2RH_PCI_CONFIG_BASE);
138 u32 backup_win0;
139 u32 data;
140 int shift;
141
142 if (check_args(bus, devfn, &bus_num) == PCIBIOS_DEVICE_NOT_FOUND)
143 return PCIBIOS_DEVICE_NOT_FOUND;
144
145 backup_win0 = emma2rh_in32(EMMA2RH_PCI_IWIN0_CTR);
146
147 if (set_pci_configuration_address(bus_num, devfn, where) < 0)
148 return PCIBIOS_DEVICE_NOT_FOUND;
149
150 /* read modify write */
151 data =
152 *(volatile u32 *)(base + (PCI_FUNC(devfn) << 8) +
153 (where & 0xfffffffc));
154
155 switch (size) {
156 case 1:
157 shift = (where & 3) << 3;
158 data &= ~(0xffU << shift);
159 data |= ((val & 0xffU) << shift);
160 break;
161 case 2:
162 shift = (where & 2) << 3;
163 data &= ~(0xffffU << shift);
164 data |= ((val & 0xffffU) << shift);
165 break;
166 case 4:
167 data = val;
168 break;
169 default:
170 emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, backup_win0);
171 return PCIBIOS_FUNC_NOT_SUPPORTED;
172 }
173 *(volatile u32 *)(base + (PCI_FUNC(devfn) << 8) +
174 (where & 0xfffffffc)) = data;
175
176 emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, backup_win0);
177 if (emma2rh_in32(EMMA2RH_PCI_INT) & RMABORT)
178 return PCIBIOS_DEVICE_NOT_FOUND;
179
180 return PCIBIOS_SUCCESSFUL;
181}
182
183struct pci_ops emma2rh_pci_ops = {
184 .read = pci_config_read,
185 .write = pci_config_write,
186};
diff --git a/arch/mips/pci/ops-it8172.c b/arch/mips/pci/ops-it8172.c
index b7a8b9a6f9db..ba8328505a0a 100644
--- a/arch/mips/pci/ops-it8172.c
+++ b/arch/mips/pci/ops-it8172.c
@@ -50,30 +50,28 @@
50static struct resource pci_mem_resource_1; 50static struct resource pci_mem_resource_1;
51 51
52static struct resource pci_io_resource = { 52static struct resource pci_io_resource = {
53 "io pci IO space", 53 .start = 0x14018000,
54 0x14018000, 54 .end = 0x17FFFFFF,
55 0x17FFFFFF, 55 .name = "io pci IO space",
56 IORESOURCE_IO 56 .flags = IORESOURCE_IO
57}; 57};
58 58
59static struct resource pci_mem_resource_0 = { 59static struct resource pci_mem_resource_0 = {
60 "ext pci memory space 0/1", 60 .start = 0x10101000,
61 0x10101000, 61 .end = 0x13FFFFFF,
62 0x13FFFFFF, 62 .name = "ext pci memory space 0/1",
63 IORESOURCE_MEM, 63 .flags = IORESOURCE_MEM,
64 &pci_mem_resource_0, 64 .parent = &pci_mem_resource_0,
65 NULL, 65 .sibling = NULL,
66 &pci_mem_resource_1 66 .child = &pci_mem_resource_1
67}; 67};
68 68
69static struct resource pci_mem_resource_1 = { 69static struct resource pci_mem_resource_1 = {
70 "ext pci memory space 2/3", 70 .start = 0x1A000000,
71 0x1A000000, 71 .end = 0x1FBFFFFF,
72 0x1FBFFFFF, 72 .name = "ext pci memory space 2/3",
73 IORESOURCE_MEM, 73 .flags = IORESOURCE_MEM,
74 &pci_mem_resource_0, 74 .parent = &pci_mem_resource_0
75 NULL,
76 NULL
77}; 75};
78 76
79extern struct pci_ops it8172_pci_ops; 77extern struct pci_ops it8172_pci_ops;
diff --git a/arch/mips/pci/ops-sni.c b/arch/mips/pci/ops-sni.c
index 62bdd19c7f8e..2b0ccd6d9dcd 100644
--- a/arch/mips/pci/ops-sni.c
+++ b/arch/mips/pci/ops-sni.c
@@ -47,13 +47,13 @@ static int pcimt_read(struct pci_bus *bus, unsigned int devfn, int reg,
47 47
48 switch (size) { 48 switch (size) {
49 case 1: 49 case 1:
50 *val = *(volatile u8 *) (PCIMT_CONFIG_DATA + (reg & 3)); 50 *val = inb(PCIMT_CONFIG_DATA + (reg & 3));
51 break; 51 break;
52 case 2: 52 case 2:
53 *val = *(volatile u16 *) (PCIMT_CONFIG_DATA + (reg & 2)); 53 *val = inw(PCIMT_CONFIG_DATA + (reg & 2));
54 break; 54 break;
55 case 4: 55 case 4:
56 *val = *(volatile u32 *) PCIMT_CONFIG_DATA; 56 *val = inl(PCIMT_CONFIG_DATA);
57 break; 57 break;
58 } 58 }
59 59
@@ -70,13 +70,13 @@ static int pcimt_write(struct pci_bus *bus, unsigned int devfn, int reg,
70 70
71 switch (size) { 71 switch (size) {
72 case 1: 72 case 1:
73 *(volatile u8 *) (PCIMT_CONFIG_DATA + (reg & 3)) = val; 73 outb (val, PCIMT_CONFIG_DATA + (reg & 3));
74 break; 74 break;
75 case 2: 75 case 2:
76 *(volatile u16 *) (PCIMT_CONFIG_DATA + (reg & 2)) = val; 76 outw (val, PCIMT_CONFIG_DATA + (reg & 2));
77 break; 77 break;
78 case 4: 78 case 4:
79 *(volatile u32 *) PCIMT_CONFIG_DATA = val; 79 outl (val, PCIMT_CONFIG_DATA);
80 break; 80 break;
81 } 81 }
82 82
diff --git a/arch/mips/pci/ops-titan.c b/arch/mips/pci/ops-titan.c
index 233ec6f2054d..ebf8fc40e9b2 100644
--- a/arch/mips/pci/ops-titan.c
+++ b/arch/mips/pci/ops-titan.c
@@ -26,8 +26,19 @@
26#include <linux/pci.h> 26#include <linux/pci.h>
27#include <linux/kernel.h> 27#include <linux/kernel.h>
28 28
29#include <asm/titan_dep.h> 29#include <asm/pci.h>
30#include <asm/io.h>
31#include <asm/rm9k-ocd.h>
30 32
33/*
34 * PCI specific defines
35 */
36#define TITAN_PCI_0_CONFIG_ADDRESS 0x780
37#define TITAN_PCI_0_CONFIG_DATA 0x784
38
39/*
40 * Titan PCI Config Read Byte
41 */
31static int titan_read_config(struct pci_bus *bus, unsigned int devfn, int reg, 42static int titan_read_config(struct pci_bus *bus, unsigned int devfn, int reg,
32 int size, u32 * val) 43 int size, u32 * val)
33{ 44{
@@ -43,8 +54,8 @@ static int titan_read_config(struct pci_bus *bus, unsigned int devfn, int reg,
43 54
44 55
45 /* start the configuration cycle */ 56 /* start the configuration cycle */
46 TITAN_WRITE(TITAN_PCI_0_CONFIG_ADDRESS, address); 57 ocd_writel(address, TITAN_PCI_0_CONFIG_ADDRESS);
47 tmp = TITAN_READ(TITAN_PCI_0_CONFIG_DATA) >> ((reg & 3) << 3); 58 tmp = ocd_readl(TITAN_PCI_0_CONFIG_DATA) >> ((reg & 3) << 3);
48 59
49 switch (size) { 60 switch (size) {
50 case 1: 61 case 1:
@@ -71,20 +82,20 @@ static int titan_write_config(struct pci_bus *bus, unsigned int devfn, int reg,
71 (reg & 0xfc) | 0x80000000; 82 (reg & 0xfc) | 0x80000000;
72 83
73 /* start the configuration cycle */ 84 /* start the configuration cycle */
74 TITAN_WRITE(TITAN_PCI_0_CONFIG_ADDRESS, address); 85 ocd_writel(address, TITAN_PCI_0_CONFIG_ADDRESS);
75 86
76 /* write the data */ 87 /* write the data */
77 switch (size) { 88 switch (size) {
78 case 1: 89 case 1:
79 TITAN_WRITE_8(TITAN_PCI_0_CONFIG_DATA + (~reg & 0x3), val); 90 ocd_writeb(val, TITAN_PCI_0_CONFIG_DATA + (~reg & 0x3));
80 break; 91 break;
81 92
82 case 2: 93 case 2:
83 TITAN_WRITE_16(TITAN_PCI_0_CONFIG_DATA + (~reg & 0x2), val); 94 ocd_writew(val, TITAN_PCI_0_CONFIG_DATA + (~reg & 0x2));
84 break; 95 break;
85 96
86 case 4: 97 case 4:
87 TITAN_WRITE(TITAN_PCI_0_CONFIG_DATA, val); 98 ocd_writel(val, TITAN_PCI_0_CONFIG_DATA);
88 break; 99 break;
89 } 100 }
90 101
diff --git a/arch/mips/pci/pci-ddb5074.c b/arch/mips/pci/pci-ddb5074.c
deleted file mode 100644
index 73f9ceeb2f55..000000000000
--- a/arch/mips/pci/pci-ddb5074.c
+++ /dev/null
@@ -1,79 +0,0 @@
1#include <linux/kernel.h>
2#include <linux/init.h>
3#include <linux/types.h>
4#include <linux/pci.h>
5
6#include <asm/debug.h>
7
8#include <asm/ddb5xxx/ddb5xxx.h>
9
10static struct resource extpci_io_resource = {
11 "pci IO space",
12 0x1000, /* leave some room for ISA bus */
13 DDB_PCI_IO_SIZE - 1,
14 IORESOURCE_IO
15};
16
17static struct resource extpci_mem_resource = {
18 "pci memory space",
19 DDB_PCI_MEM_BASE + 0x00100000, /* leave 1 MB for RTC */
20 DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE - 1,
21 IORESOURCE_MEM
22};
23
24extern struct pci_ops ddb5476_ext_pci_ops;
25
26struct pci_controller ddb5476_controller = {
27 .pci_ops = &ddb5476_ext_pci_ops,
28 .io_resource = &extpci_io_resource,
29 .mem_resource = &extpci_mem_resource,
30};
31
32#define PCI_EXT_INTA 8
33#define PCI_EXT_INTB 9
34#define PCI_EXT_INTC 10
35#define PCI_EXT_INTD 11
36#define PCI_EXT_INTE 12
37
38#define MAX_SLOT_NUM 14
39
40static unsigned char irq_map[MAX_SLOT_NUM] = {
41 [ 0] = nile4_to_irq(PCI_EXT_INTE),
42 [ 1] = nile4_to_irq(PCI_EXT_INTA),
43 [ 2] = nile4_to_irq(PCI_EXT_INTA),
44 [ 3] = nile4_to_irq(PCI_EXT_INTB),
45 [ 4] = nile4_to_irq(PCI_EXT_INTC),
46 [ 5] = nile4_to_irq(NILE4_INT_UART),
47 [10] = nile4_to_irq(PCI_EXT_INTE),
48 [13] = nile4_to_irq(PCI_EXT_INTE),
49};
50
51int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
52{
53 return irq_map[slot];
54}
55
56/* Do platform specific device initialization at pci_enable_device() time */
57int pcibios_plat_dev_init(struct pci_dev *dev)
58{
59 return 0;
60}
61
62void __init ddb_pci_reset_bus(void)
63{
64 u32 temp;
65
66 /*
67 * I am not sure about the "official" procedure, the following
68 * steps work as far as I know:
69 * We first set PCI cold reset bit (bit 31) in PCICTRL-H.
70 * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H.
71 * The same is true for both PCI channels.
72 */
73 temp = ddb_in32(DDB_PCICTRL + 4);
74 temp |= 0x80000000;
75 ddb_out32(DDB_PCICTRL + 4, temp);
76 temp &= ~0xc0000000;
77 ddb_out32(DDB_PCICTRL + 4, temp);
78
79}
diff --git a/arch/mips/pci/pci-ddb5476.c b/arch/mips/pci/pci-ddb5476.c
deleted file mode 100644
index 90dd49509800..000000000000
--- a/arch/mips/pci/pci-ddb5476.c
+++ /dev/null
@@ -1,93 +0,0 @@
1#include <linux/kernel.h>
2#include <linux/init.h>
3#include <linux/types.h>
4#include <linux/pci.h>
5
6#include <asm/debug.h>
7
8#include <asm/ddb5xxx/ddb5xxx.h>
9
10static struct resource extpci_io_resource = {
11 "pci IO space",
12 0x1000, /* leave some room for ISA bus */
13 DDB_PCI_IO_SIZE - 1,
14 IORESOURCE_IO
15};
16
17static struct resource extpci_mem_resource = {
18 "pci memory space",
19 DDB_PCI_MEM_BASE + 0x00100000, /* leave 1 MB for RTC */
20 DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE - 1,
21 IORESOURCE_MEM
22};
23
24extern struct pci_ops ddb5476_ext_pci_ops;
25
26struct pci_controller ddb5476_controller = {
27 .pci_ops = &ddb5476_ext_pci_ops,
28 .io_resource = &extpci_io_resource,
29 .mem_resource = &extpci_mem_resource
30};
31
32
33/*
34 * we fix up irqs based on the slot number.
35 * The first entry is at AD:11.
36 *
37 * This does not work for devices on sub-buses yet.
38 */
39
40/*
41 * temporary
42 */
43
44#define PCI_EXT_INTA 8
45#define PCI_EXT_INTB 9
46#define PCI_EXT_INTC 10
47#define PCI_EXT_INTD 11
48#define PCI_EXT_INTE 12
49
50/*
51 * based on ddb5477 manual page 11
52 */
53#define MAX_SLOT_NUM 21
54static unsigned char irq_map[MAX_SLOT_NUM] = {
55 [ 2] = 9, /* AD:13 USB */
56 [ 3] = 10, /* AD:14 PMU */
57 [ 5] = 0, /* AD:16 P2P bridge */
58 [ 6] = nile4_to_irq(PCI_EXT_INTB), /* AD:17 */
59 [ 7] = nile4_to_irq(PCI_EXT_INTC), /* AD:18 */
60 [ 8] = nile4_to_irq(PCI_EXT_INTD), /* AD:19 */
61 [ 9] = nile4_to_irq(PCI_EXT_INTA), /* AD:20 */
62 [13] = 14, /* AD:24 HD controller, M5229 */
63};
64
65int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
66{
67 return irq_map[slot];
68}
69
70/* Do platform specific device initialization at pci_enable_device() time */
71int pcibios_plat_dev_init(struct pci_dev *dev)
72{
73 return 0;
74}
75
76void __init ddb_pci_reset_bus(void)
77{
78 u32 temp;
79
80 /*
81 * I am not sure about the "official" procedure, the following
82 * steps work as far as I know:
83 * We first set PCI cold reset bit (bit 31) in PCICTRL-H.
84 * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H.
85 * The same is true for both PCI channels.
86 */
87 temp = ddb_in32(DDB_PCICTRL + 4);
88 temp |= 0x80000000;
89 ddb_out32(DDB_PCICTRL + 4, temp);
90 temp &= ~0xc0000000;
91 ddb_out32(DDB_PCICTRL + 4, temp);
92
93}
diff --git a/arch/mips/pci/pci-ddb5477.c b/arch/mips/pci/pci-ddb5477.c
index 826d653184e5..d071bc375b11 100644
--- a/arch/mips/pci/pci-ddb5477.c
+++ b/arch/mips/pci/pci-ddb5477.c
@@ -22,31 +22,31 @@
22#include <asm/ddb5xxx/ddb5xxx.h> 22#include <asm/ddb5xxx/ddb5xxx.h>
23 23
24static struct resource extpci_io_resource = { 24static struct resource extpci_io_resource = {
25 "ext pci IO space", 25 .start = DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + 0x4000,
26 DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + 0x4000, 26 .end = DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI0_IO_SIZE - 1,
27 DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI0_IO_SIZE - 1, 27 .name = "ext pci IO space",
28 IORESOURCE_IO 28 .flags = IORESOURCE_IO
29}; 29};
30 30
31static struct resource extpci_mem_resource = { 31static struct resource extpci_mem_resource = {
32 "ext pci memory space", 32 .start = DDB_PCI0_MEM_BASE + 0x100000,
33 DDB_PCI0_MEM_BASE + 0x100000, 33 .end = DDB_PCI0_MEM_BASE + DDB_PCI0_MEM_SIZE - 1,
34 DDB_PCI0_MEM_BASE + DDB_PCI0_MEM_SIZE - 1, 34 .name = "ext pci memory space",
35 IORESOURCE_MEM 35 .flags = IORESOURCE_MEM
36}; 36};
37 37
38static struct resource iopci_io_resource = { 38static struct resource iopci_io_resource = {
39 "io pci IO space", 39 .start = DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE,
40 DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE, 40 .end = DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI1_IO_SIZE - 1,
41 DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI1_IO_SIZE - 1, 41 .name = "io pci IO space",
42 IORESOURCE_IO 42 .flags = IORESOURCE_IO
43}; 43};
44 44
45static struct resource iopci_mem_resource = { 45static struct resource iopci_mem_resource = {
46 "ext pci memory space", 46 .start = DDB_PCI1_MEM_BASE,
47 DDB_PCI1_MEM_BASE, 47 .end = DDB_PCI1_MEM_BASE + DDB_PCI1_MEM_SIZE - 1,
48 DDB_PCI1_MEM_BASE + DDB_PCI1_MEM_SIZE - 1, 48 .name = "ext pci memory space",
49 IORESOURCE_MEM 49 .flags = IORESOURCE_MEM
50}; 50};
51 51
52extern struct pci_ops ddb5477_ext_pci_ops; 52extern struct pci_ops ddb5477_ext_pci_ops;
diff --git a/arch/mips/pci/pci-emma2rh.c b/arch/mips/pci/pci-emma2rh.c
new file mode 100644
index 000000000000..0f8b230057d3
--- /dev/null
+++ b/arch/mips/pci/pci-emma2rh.c
@@ -0,0 +1,90 @@
1/*
2 * arch/mips/pci/pci-emma2rh.c
3 * This file defines the PCI configration.
4 *
5 * Copyright (C) NEC Electronics Corporation 2004-2006
6 *
7 * This file is based on the arch/mips/ddb5xxx/ddb5477/pci.c
8 *
9 * Copyright 2001 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25
26#include <linux/config.h>
27#include <linux/kernel.h>
28#include <linux/init.h>
29#include <linux/types.h>
30#include <linux/pci.h>
31
32#include <asm/bootinfo.h>
33#include <asm/debug.h>
34
35#include <asm/emma2rh/emma2rh.h>
36
37static struct resource pci_io_resource = {
38 .name = "pci IO space",
39 .start = EMMA2RH_PCI_IO_BASE,
40 .end = EMMA2RH_PCI_IO_BASE + EMMA2RH_PCI_IO_SIZE - 1,
41 .flags = IORESOURCE_IO,
42};
43
44static struct resource pci_mem_resource = {
45 .name = "pci memory space",
46 .start = EMMA2RH_PCI_MEM_BASE,
47 .end = EMMA2RH_PCI_MEM_BASE + EMMA2RH_PCI_MEM_SIZE - 1,
48 .flags = IORESOURCE_MEM,
49};
50
51extern struct pci_ops emma2rh_pci_ops;
52
53static struct pci_controller emma2rh_pci_controller = {
54 .pci_ops = &emma2rh_pci_ops,
55 .mem_resource = &pci_mem_resource,
56 .io_resource = &pci_io_resource,
57 .mem_offset = -0x04000000,
58 .io_offset = 0,
59};
60
61static void __init emma2rh_pci_init(void)
62{
63 /* setup PCI interface */
64 emma2rh_out32(EMMA2RH_PCI_ARBIT_CTR, 0x70f);
65
66 emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, 0x80000a18);
67 emma2rh_out32(EMMA2RH_PCI_CONFIG_BASE + PCI_COMMAND,
68 PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_CAP_LIST |
69 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
70 emma2rh_out32(EMMA2RH_PCI_CONFIG_BASE + PCI_BASE_ADDRESS_0, 0x10000000);
71 emma2rh_out32(EMMA2RH_PCI_CONFIG_BASE + PCI_BASE_ADDRESS_1, 0x00000000);
72
73 emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, 0x12000000 | 0x218);
74 emma2rh_out32(EMMA2RH_PCI_IWIN1_CTR, 0x18000000 | 0x600);
75 emma2rh_out32(EMMA2RH_PCI_INIT_ESWP, 0x00000200);
76
77 emma2rh_out32(EMMA2RH_PCI_TWIN_CTR, 0x00009200);
78 emma2rh_out32(EMMA2RH_PCI_TWIN_BADR, 0x00000000);
79 emma2rh_out32(EMMA2RH_PCI_TWIN0_DADR, 0x00000000);
80 emma2rh_out32(EMMA2RH_PCI_TWIN1_DADR, 0x00000000);
81}
82
83static int __init emma2rh_pci_setup(void)
84{
85 emma2rh_pci_init();
86 register_pci_controller(&emma2rh_pci_controller);
87 return 0;
88}
89
90arch_initcall(emma2rh_pci_setup);
diff --git a/arch/mips/pci/pci-excite.c b/arch/mips/pci/pci-excite.c
new file mode 100644
index 000000000000..3c86c77cb74f
--- /dev/null
+++ b/arch/mips/pci/pci-excite.c
@@ -0,0 +1,149 @@
1/*
2 * Copyright (C) 2004 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 * Based on the PMC-Sierra Yosemite board support by Ralf Baechle.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/pci.h>
24#include <linux/bitops.h>
25#include <asm/rm9k-ocd.h>
26#include <excite.h>
27
28
29extern struct pci_ops titan_pci_ops;
30
31
32static struct resource
33 mem_resource = {
34 .name = "PCI memory",
35 .start = EXCITE_PHYS_PCI_MEM,
36 .end = EXCITE_PHYS_PCI_MEM + EXCITE_SIZE_PCI_MEM - 1,
37 .flags = IORESOURCE_MEM
38 },
39 io_resource = {
40 .name = "PCI I/O",
41 .start = EXCITE_PHYS_PCI_IO,
42 .end = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1,
43 .flags = IORESOURCE_IO
44 };
45
46
47static struct pci_controller bx_controller = {
48 .pci_ops = &titan_pci_ops,
49 .mem_resource = &mem_resource,
50 .mem_offset = 0x00000000UL,
51 .io_resource = &io_resource,
52 .io_offset = 0x00000000UL
53};
54
55
56static char
57 iopage_failed[] __initdata = "Cannot allocate PCI I/O page",
58 modebits_no_pci[] __initdata = "PCI is not configured in mode bits";
59
60#define RM9000x2_OCD_HTSC 0x0604
61#define RM9000x2_OCD_HTBHL 0x060c
62#define RM9000x2_OCD_PCIHRST 0x078c
63
64#define RM9K_OCD_MODEBIT1 0x00d4 /* (MODEBIT1) Mode Bit 1 */
65#define RM9K_OCD_CPHDCR 0x00f4 /* CPU-PCI/HT Data Control. */
66
67#define PCISC_FB2B 0x00000200
68#define PCISC_MWICG 0x00000010
69#define PCISC_EMC 0x00000004
70#define PCISC_ERMA 0x00000002
71
72
73
74static int __init basler_excite_pci_setup(void)
75{
76 const unsigned int fullbars = memsize / (256 << 20);
77 unsigned int i;
78
79 /* Check modebits to see if PCI is really enabled. */
80 if (!((ocd_readl(RM9K_OCD_MODEBIT1) >> (47-32)) & 0x1))
81 panic(modebits_no_pci);
82
83 if (NULL == request_mem_region(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO,
84 "Memory-mapped PCI I/O page"))
85 panic(iopage_failed);
86
87 /* Enable PCI 0 as master for config cycles */
88 ocd_writel(PCISC_EMC | PCISC_ERMA, RM9000x2_OCD_HTSC);
89
90
91 /* Set up latency timer */
92 ocd_writel(0x8008, RM9000x2_OCD_HTBHL);
93
94 /* Setup host IO and Memory space */
95 ocd_writel((EXCITE_PHYS_PCI_IO >> 4) | 1, LKB7);
96 ocd_writel(((EXCITE_SIZE_PCI_IO >> 4) & 0x7fffff00) - 0x100, LKM7);
97 ocd_writel((EXCITE_PHYS_PCI_MEM >> 4) | 1, LKB8);
98 ocd_writel(((EXCITE_SIZE_PCI_MEM >> 4) & 0x7fffff00) - 0x100, LKM8);
99
100 /* Set up PCI BARs to map all installed memory */
101 for (i = 0; i < 6; i++) {
102 const unsigned int bar = 0x610 + i * 4;
103
104 if (i < fullbars) {
105 ocd_writel(0x10000000 * i, bar);
106 ocd_writel(0x01000000 * i, bar + 0x140);
107 ocd_writel(0x0ffff029, bar + 0x100);
108 continue;
109 }
110
111 if (i == fullbars) {
112 int o;
113 u32 mask;
114
115 const unsigned long rem = memsize - i * 0x10000000;
116 if (!rem) {
117 ocd_writel(0x00000000, bar + 0x100);
118 continue;
119 }
120
121 o = ffs(rem) - 1;
122 if (rem & ~(0x1 << o))
123 o++;
124 mask = ((0x1 << o) & 0x0ffff000) - 0x1000;
125 ocd_writel(0x10000000 * i, bar);
126 ocd_writel(0x01000000 * i, bar + 0x140);
127 ocd_writel(0x00000029 | mask, bar + 0x100);
128 continue;
129 }
130
131 ocd_writel(0x00000000, bar + 0x100);
132 }
133
134 /* Finally, enable the PCI interupt */
135#if USB_IRQ > 7
136 set_c0_intcontrol(1 << USB_IRQ);
137#else
138 set_c0_status(1 << (USB_IRQ + 8));
139#endif
140
141 ioport_resource.start = EXCITE_PHYS_PCI_IO;
142 ioport_resource.end = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1;
143 set_io_port_base((unsigned long) ioremap_nocache(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO));
144 register_pci_controller(&bx_controller);
145 return 0;
146}
147
148
149arch_initcall(basler_excite_pci_setup);
diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c
index 6002d2a6a262..80eb9af9ecdf 100644
--- a/arch/mips/pci/pci-ip27.c
+++ b/arch/mips/pci/pci-ip27.c
@@ -40,297 +40,7 @@ static struct bridge_controller bridges[MAX_PCI_BUSSES];
40struct bridge_controller *irq_to_bridge[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS]; 40struct bridge_controller *irq_to_bridge[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS];
41int irq_to_slot[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS]; 41int irq_to_slot[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS];
42 42
43/* 43extern struct pci_ops bridge_pci_ops;
44 * The Bridge ASIC supports both type 0 and type 1 access. Type 1 is
45 * not really documented, so right now I can't write code which uses it.
46 * Therefore we use type 0 accesses for now even though they won't work
47 * correcly for PCI-to-PCI bridges.
48 *
49 * The function is complicated by the ultimate brokeness of the IOC3 chip
50 * which is used in SGI systems. The IOC3 can only handle 32-bit PCI
51 * accesses and does only decode parts of it's address space.
52 */
53
54static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn,
55 int where, int size, u32 * value)
56{
57 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
58 bridge_t *bridge = bc->base;
59 int slot = PCI_SLOT(devfn);
60 int fn = PCI_FUNC(devfn);
61 volatile void *addr;
62 u32 cf, shift, mask;
63 int res;
64
65 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
66 if (get_dbe(cf, (u32 *) addr))
67 return PCIBIOS_DEVICE_NOT_FOUND;
68
69 /*
70 * IOC3 is fucked fucked beyond believe ... Don't even give the
71 * generic PCI code a chance to look at it for real ...
72 */
73 if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
74 goto oh_my_gawd;
75
76 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
77
78 if (size == 1)
79 res = get_dbe(*value, (u8 *) addr);
80 else if (size == 2)
81 res = get_dbe(*value, (u16 *) addr);
82 else
83 res = get_dbe(*value, (u32 *) addr);
84
85 return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
86
87oh_my_gawd:
88
89 /*
90 * IOC3 is fucked fucked beyond believe ... Don't even give the
91 * generic PCI code a chance to look at the wrong register.
92 */
93 if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
94 *value = 0;
95 return PCIBIOS_SUCCESSFUL;
96 }
97
98 /*
99 * IOC3 is fucked fucked beyond believe ... Don't try to access
100 * anything but 32-bit words ...
101 */
102 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
103
104 if (get_dbe(cf, (u32 *) addr))
105 return PCIBIOS_DEVICE_NOT_FOUND;
106
107 shift = ((where & 3) << 3);
108 mask = (0xffffffffU >> ((4 - size) << 3));
109 *value = (cf >> shift) & mask;
110
111 return PCIBIOS_SUCCESSFUL;
112}
113
114static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn,
115 int where, int size, u32 * value)
116{
117 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
118 bridge_t *bridge = bc->base;
119 int busno = bus->number;
120 int slot = PCI_SLOT(devfn);
121 int fn = PCI_FUNC(devfn);
122 volatile void *addr;
123 u32 cf, shift, mask;
124 int res;
125
126 bridge->b_pci_cfg = (busno << 16) | (slot << 11);
127 addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
128 if (get_dbe(cf, (u32 *) addr))
129 return PCIBIOS_DEVICE_NOT_FOUND;
130
131 /*
132 * IOC3 is fucked fucked beyond believe ... Don't even give the
133 * generic PCI code a chance to look at it for real ...
134 */
135 if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
136 goto oh_my_gawd;
137
138 bridge->b_pci_cfg = (busno << 16) | (slot << 11);
139 addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
140
141 if (size == 1)
142 res = get_dbe(*value, (u8 *) addr);
143 else if (size == 2)
144 res = get_dbe(*value, (u16 *) addr);
145 else
146 res = get_dbe(*value, (u32 *) addr);
147
148 return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
149
150oh_my_gawd:
151
152 /*
153 * IOC3 is fucked fucked beyond believe ... Don't even give the
154 * generic PCI code a chance to look at the wrong register.
155 */
156 if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
157 *value = 0;
158 return PCIBIOS_SUCCESSFUL;
159 }
160
161 /*
162 * IOC3 is fucked fucked beyond believe ... Don't try to access
163 * anything but 32-bit words ...
164 */
165 bridge->b_pci_cfg = (busno << 16) | (slot << 11);
166 addr = &bridge->b_type1_cfg.c[(fn << 8) | where];
167
168 if (get_dbe(cf, (u32 *) addr))
169 return PCIBIOS_DEVICE_NOT_FOUND;
170
171 shift = ((where & 3) << 3);
172 mask = (0xffffffffU >> ((4 - size) << 3));
173 *value = (cf >> shift) & mask;
174
175 return PCIBIOS_SUCCESSFUL;
176}
177
178static int pci_read_config(struct pci_bus *bus, unsigned int devfn,
179 int where, int size, u32 * value)
180{
181 if (bus->number > 0)
182 return pci_conf1_read_config(bus, devfn, where, size, value);
183
184 return pci_conf0_read_config(bus, devfn, where, size, value);
185}
186
187static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn,
188 int where, int size, u32 value)
189{
190 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
191 bridge_t *bridge = bc->base;
192 int slot = PCI_SLOT(devfn);
193 int fn = PCI_FUNC(devfn);
194 volatile void *addr;
195 u32 cf, shift, mask, smask;
196 int res;
197
198 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
199 if (get_dbe(cf, (u32 *) addr))
200 return PCIBIOS_DEVICE_NOT_FOUND;
201
202 /*
203 * IOC3 is fucked fucked beyond believe ... Don't even give the
204 * generic PCI code a chance to look at it for real ...
205 */
206 if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
207 goto oh_my_gawd;
208
209 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
210
211 if (size == 1) {
212 res = put_dbe(value, (u8 *) addr);
213 } else if (size == 2) {
214 res = put_dbe(value, (u16 *) addr);
215 } else {
216 res = put_dbe(value, (u32 *) addr);
217 }
218
219 if (res)
220 return PCIBIOS_DEVICE_NOT_FOUND;
221
222 return PCIBIOS_SUCCESSFUL;
223
224oh_my_gawd:
225
226 /*
227 * IOC3 is fucked fucked beyond believe ... Don't even give the
228 * generic PCI code a chance to touch the wrong register.
229 */
230 if ((where >= 0x14 && where < 0x40) || (where >= 0x48))
231 return PCIBIOS_SUCCESSFUL;
232
233 /*
234 * IOC3 is fucked fucked beyond believe ... Don't try to access
235 * anything but 32-bit words ...
236 */
237 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
238
239 if (get_dbe(cf, (u32 *) addr))
240 return PCIBIOS_DEVICE_NOT_FOUND;
241
242 shift = ((where & 3) << 3);
243 mask = (0xffffffffU >> ((4 - size) << 3));
244 smask = mask << shift;
245
246 cf = (cf & ~smask) | ((value & mask) << shift);
247 if (put_dbe(cf, (u32 *) addr))
248 return PCIBIOS_DEVICE_NOT_FOUND;
249
250 return PCIBIOS_SUCCESSFUL;
251}
252
253static int pci_conf1_write_config(struct pci_bus *bus, unsigned int devfn,
254 int where, int size, u32 value)
255{
256 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
257 bridge_t *bridge = bc->base;
258 int slot = PCI_SLOT(devfn);
259 int fn = PCI_FUNC(devfn);
260 int busno = bus->number;
261 volatile void *addr;
262 u32 cf, shift, mask, smask;
263 int res;
264
265 bridge->b_pci_cfg = (busno << 16) | (slot << 11);
266 addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
267 if (get_dbe(cf, (u32 *) addr))
268 return PCIBIOS_DEVICE_NOT_FOUND;
269
270 /*
271 * IOC3 is fucked fucked beyond believe ... Don't even give the
272 * generic PCI code a chance to look at it for real ...
273 */
274 if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
275 goto oh_my_gawd;
276
277 addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
278
279 if (size == 1) {
280 res = put_dbe(value, (u8 *) addr);
281 } else if (size == 2) {
282 res = put_dbe(value, (u16 *) addr);
283 } else {
284 res = put_dbe(value, (u32 *) addr);
285 }
286
287 if (res)
288 return PCIBIOS_DEVICE_NOT_FOUND;
289
290 return PCIBIOS_SUCCESSFUL;
291
292oh_my_gawd:
293
294 /*
295 * IOC3 is fucked fucked beyond believe ... Don't even give the
296 * generic PCI code a chance to touch the wrong register.
297 */
298 if ((where >= 0x14 && where < 0x40) || (where >= 0x48))
299 return PCIBIOS_SUCCESSFUL;
300
301 /*
302 * IOC3 is fucked fucked beyond believe ... Don't try to access
303 * anything but 32-bit words ...
304 */
305 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
306
307 if (get_dbe(cf, (u32 *) addr))
308 return PCIBIOS_DEVICE_NOT_FOUND;
309
310 shift = ((where & 3) << 3);
311 mask = (0xffffffffU >> ((4 - size) << 3));
312 smask = mask << shift;
313
314 cf = (cf & ~smask) | ((value & mask) << shift);
315 if (put_dbe(cf, (u32 *) addr))
316 return PCIBIOS_DEVICE_NOT_FOUND;
317
318 return PCIBIOS_SUCCESSFUL;
319}
320
321static int pci_write_config(struct pci_bus *bus, unsigned int devfn,
322 int where, int size, u32 value)
323{
324 if (bus->number > 0)
325 return pci_conf1_write_config(bus, devfn, where, size, value);
326
327 return pci_conf0_write_config(bus, devfn, where, size, value);
328}
329
330static struct pci_ops bridge_pci_ops = {
331 .read = pci_read_config,
332 .write = pci_write_config,
333};
334 44
335int __init bridge_probe(nasid_t nasid, int widget_id, int masterwid) 45int __init bridge_probe(nasid_t nasid, int widget_id, int masterwid)
336{ 46{
@@ -370,8 +80,7 @@ int __init bridge_probe(nasid_t nasid, int widget_id, int masterwid)
370 bc->widget_id = widget_id; 80 bc->widget_id = widget_id;
371 bc->nasid = nasid; 81 bc->nasid = nasid;
372 82
373 bc->baddr = (u64)masterwid << 60; 83 bc->baddr = (u64)masterwid << 60 | PCI64_ATTR_BAR;
374 bc->baddr |= (1UL << 56); /* Barrier set */
375 84
376 /* 85 /*
377 * point to this bridge 86 * point to this bridge
diff --git a/arch/mips/pci/pci-jmr3927.c b/arch/mips/pci/pci-jmr3927.c
index f02ef6e36b02..cb84f4e8ccae 100644
--- a/arch/mips/pci/pci-jmr3927.c
+++ b/arch/mips/pci/pci-jmr3927.c
@@ -35,17 +35,17 @@
35#include <asm/debug.h> 35#include <asm/debug.h>
36 36
37struct resource pci_io_resource = { 37struct resource pci_io_resource = {
38 "IO MEM", 38 .name = "IO MEM",
39 0x1000, /* reserve regacy I/O space */ 39 .start = 0x1000, /* reserve regacy I/O space */
40 0x1000 + JMR3927_PCIIO_SIZE - 1, 40 .end = 0x1000 + JMR3927_PCIIO_SIZE - 1,
41 IORESOURCE_IO 41 .flags = IORESOURCE_IO
42}; 42};
43 43
44struct resource pci_mem_resource = { 44struct resource pci_mem_resource = {
45 "PCI MEM", 45 .name = "PCI MEM",
46 JMR3927_PCIMEM, 46 .start = JMR3927_PCIMEM,
47 JMR3927_PCIMEM + JMR3927_PCIMEM_SIZE - 1, 47 .end = JMR3927_PCIMEM + JMR3927_PCIMEM_SIZE - 1,
48 IORESOURCE_MEM 48 .flags = IORESOURCE_MEM
49}; 49};
50 50
51extern struct pci_ops jmr3927_pci_ops; 51extern struct pci_ops jmr3927_pci_ops;
diff --git a/arch/mips/pci/pci-ocelot.c b/arch/mips/pci/pci-ocelot.c
index 3da8a4ee6baa..2b9495dce6ba 100644
--- a/arch/mips/pci/pci-ocelot.c
+++ b/arch/mips/pci/pci-ocelot.c
@@ -71,13 +71,13 @@ static inline void pci0WriteConfigReg(unsigned int offset, unsigned int data)
71} 71}
72 72
73static struct resource ocelot_mem_resource = { 73static struct resource ocelot_mem_resource = {
74 iomem_resource.start = GT_PCI_MEM_BASE; 74 start = GT_PCI_MEM_BASE;
75 iomem_resource.end = GT_PCI_MEM_BASE + GT_PCI_MEM_BASE - 1; 75 end = GT_PCI_MEM_BASE + GT_PCI_MEM_BASE - 1;
76}; 76};
77 77
78static struct resource ocelot_io_resource = { 78static struct resource ocelot_io_resource = {
79 ioport_resource.start = GT_PCI_IO_BASE; 79 start = GT_PCI_IO_BASE;
80 ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1; 80 end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1;
81}; 81};
82 82
83static struct pci_controller ocelot_pci_controller = { 83static struct pci_controller ocelot_pci_controller = {
diff --git a/arch/mips/pci/pci-yosemite.c b/arch/mips/pci/pci-yosemite.c
index dac9ed4b0ccf..0357946f30e6 100644
--- a/arch/mips/pci/pci-yosemite.c
+++ b/arch/mips/pci/pci-yosemite.c
@@ -14,7 +14,10 @@
14extern struct pci_ops titan_pci_ops; 14extern struct pci_ops titan_pci_ops;
15 15
16static struct resource py_mem_resource = { 16static struct resource py_mem_resource = {
17 "Titan PCI MEM", 0xe0000000UL, 0xe3ffffffUL, IORESOURCE_MEM 17 .start = 0xe0000000UL,
18 .end = 0xe3ffffffUL,
19 .name = "Titan PCI MEM",
20 .flags = IORESOURCE_MEM
18}; 21};
19 22
20/* 23/*
@@ -26,7 +29,10 @@ static struct resource py_mem_resource = {
26#define TITAN_IO_BASE 0xe8000000UL 29#define TITAN_IO_BASE 0xe8000000UL
27 30
28static struct resource py_io_resource = { 31static struct resource py_io_resource = {
29 "Titan IO MEM", 0x00001000UL, TITAN_IO_SIZE - 1, IORESOURCE_IO, 32 .start = 0x00001000UL,
33 .end = TITAN_IO_SIZE - 1,
34 .name = "Titan IO MEM",
35 .flags = IORESOURCE_IO,
30}; 36};
31 37
32static struct pci_controller py_controller = { 38static struct pci_controller py_controller = {
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 21402ffd7c98..4dfce154d4af 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -76,11 +76,6 @@ pcibios_align_resource(void *data, struct resource *res,
76 res->start = start; 76 res->start = start;
77} 77}
78 78
79struct pci_controller * __init alloc_pci_controller(void)
80{
81 return alloc_bootmem(sizeof(struct pci_controller));
82}
83
84void __init register_pci_controller(struct pci_controller *hose) 79void __init register_pci_controller(struct pci_controller *hose)
85{ 80{
86 *hose_tail = hose; 81 *hose_tail = hose;
diff --git a/arch/mips/philips/pnx8550/common/pci.c b/arch/mips/philips/pnx8550/common/pci.c
index baa6905f649f..eee4f3dfc410 100644
--- a/arch/mips/philips/pnx8550/common/pci.c
+++ b/arch/mips/philips/pnx8550/common/pci.c
@@ -27,17 +27,17 @@
27#include <nand.h> 27#include <nand.h>
28 28
29static struct resource pci_io_resource = { 29static struct resource pci_io_resource = {
30 "pci IO space", 30 .start = PNX8550_PCIIO + 0x1000, /* reserve regacy I/O space */
31 (u32)(PNX8550_PCIIO + 0x1000), /* reserve regacy I/O space */ 31 .end = PNX8550_PCIIO + PNX8550_PCIIO_SIZE,
32 (u32)(PNX8550_PCIIO + PNX8550_PCIIO_SIZE), 32 .name = "pci IO space",
33 IORESOURCE_IO 33 .flags = IORESOURCE_IO
34}; 34};
35 35
36static struct resource pci_mem_resource = { 36static struct resource pci_mem_resource = {
37 "pci memory space", 37 .start = PNX8550_PCIMEM,
38 (u32)(PNX8550_PCIMEM), 38 .end = PNX8550_PCIMEM + PNX8550_PCIMEM_SIZE - 1,
39 (u32)(PNX8550_PCIMEM + PNX8550_PCIMEM_SIZE - 1), 39 .name = "pci memory space",
40 IORESOURCE_MEM 40 .flags = IORESOURCE_MEM
41}; 41};
42 42
43extern struct pci_ops pnx8550_pci_ops; 43extern struct pci_ops pnx8550_pci_ops;
diff --git a/arch/mips/philips/pnx8550/common/setup.c b/arch/mips/philips/pnx8550/common/setup.c
index 0d8a77619391..0e791f4f6ea3 100644
--- a/arch/mips/philips/pnx8550/common/setup.c
+++ b/arch/mips/philips/pnx8550/common/setup.c
@@ -58,10 +58,27 @@ extern void prom_printf(char *fmt, ...);
58extern char *prom_getcmdline(void); 58extern char *prom_getcmdline(void);
59 59
60struct resource standard_io_resources[] = { 60struct resource standard_io_resources[] = {
61 {"dma1", 0x00, 0x1f, IORESOURCE_BUSY}, 61 {
62 {"timer", 0x40, 0x5f, IORESOURCE_BUSY}, 62 .start = .0x00,
63 {"dma page reg", 0x80, 0x8f, IORESOURCE_BUSY}, 63 .end = 0x1f,
64 {"dma2", 0xc0, 0xdf, IORESOURCE_BUSY}, 64 .name = "dma1",
65 .flags = IORESOURCE_BUSY
66 }, {
67 .start = 0x40,
68 .end = 0x5f,
69 .name = "timer",
70 .flags = IORESOURCE_BUSY
71 }, {
72 .start = 0x80,
73 .end = 0x8f,
74 .name = "dma page reg",
75 .flags = IORESOURCE_BUSY
76 }, {
77 .start = 0xc0,
78 .end = 0xdf,
79 .name = "dma2",
80 .flags = IORESOURCE_BUSY
81 },
65}; 82};
66 83
67#define STANDARD_IO_RESOURCES (sizeof(standard_io_resources)/sizeof(struct resource)) 84#define STANDARD_IO_RESOURCES (sizeof(standard_io_resources)/sizeof(struct resource))
@@ -82,7 +99,7 @@ unsigned long get_system_mem_size(void)
82 99
83int pnx8550_console_port = -1; 100int pnx8550_console_port = -1;
84 101
85void __init plat_setup(void) 102void __init plat_mem_setup(void)
86{ 103{
87 int i; 104 int i;
88 char* argptr; 105 char* argptr;
diff --git a/arch/mips/pmc-sierra/yosemite/setup.c b/arch/mips/pmc-sierra/yosemite/setup.c
index 3f724d661bdb..aa0d6ff3c6ec 100644
--- a/arch/mips/pmc-sierra/yosemite/setup.c
+++ b/arch/mips/pmc-sierra/yosemite/setup.c
@@ -218,7 +218,7 @@ static void __init py_late_time_init(void)
218 py_rtc_setup(); 218 py_rtc_setup();
219} 219}
220 220
221void __init plat_setup(void) 221void __init plat_mem_setup(void)
222{ 222{
223 board_time_init = yosemite_time_init; 223 board_time_init = yosemite_time_init;
224 late_time_init = py_late_time_init; 224 late_time_init = py_late_time_init;
diff --git a/arch/mips/qemu/Makefile b/arch/mips/qemu/Makefile
index 730f459f3e99..078cd3029c9f 100644
--- a/arch/mips/qemu/Makefile
+++ b/arch/mips/qemu/Makefile
@@ -2,6 +2,6 @@
2# Makefile for Qemu specific kernel interface routines under Linux. 2# Makefile for Qemu specific kernel interface routines under Linux.
3# 3#
4 4
5obj-y = q-firmware.o q-irq.o q-mem.o q-setup.o 5obj-y = q-firmware.o q-irq.o q-mem.o q-setup.o q-reset.o
6 6
7obj-$(CONFIG_SMP) += q-smp.o 7obj-$(CONFIG_SMP) += q-smp.o
diff --git a/arch/mips/qemu/q-reset.c b/arch/mips/qemu/q-reset.c
new file mode 100644
index 000000000000..c04ebcfc7843
--- /dev/null
+++ b/arch/mips/qemu/q-reset.c
@@ -0,0 +1,34 @@
1#include <linux/config.h>
2
3#include <asm/io.h>
4#include <asm/reboot.h>
5#include <asm/cacheflush.h>
6#include <asm/qemu.h>
7
8static void qemu_machine_restart(char *command)
9{
10 volatile unsigned int *reg = (unsigned int *)QEMU_RESTART_REG;
11
12 set_c0_status(ST0_BEV | ST0_ERL);
13 change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
14 flush_cache_all();
15 write_c0_wired(0);
16 *reg = 42;
17 while (1)
18 cpu_wait();
19}
20
21static void qemu_machine_halt(void)
22{
23 volatile unsigned int *reg = (unsigned int *)QEMU_HALT_REG;
24
25 *reg = 42;
26 while (1)
27 cpu_wait();
28}
29
30void qemu_reboot_setup(void)
31{
32 _machine_restart = qemu_machine_restart;
33 _machine_halt = qemu_machine_halt;
34}
diff --git a/arch/mips/qemu/q-setup.c b/arch/mips/qemu/q-setup.c
index 022eb1af6db1..e100d6072e31 100644
--- a/arch/mips/qemu/q-setup.c
+++ b/arch/mips/qemu/q-setup.c
@@ -2,6 +2,8 @@
2#include <asm/io.h> 2#include <asm/io.h>
3#include <asm/time.h> 3#include <asm/time.h>
4 4
5extern void qemu_reboot_setup(void);
6
5#define QEMU_PORT_BASE 0xb4000000 7#define QEMU_PORT_BASE 0xb4000000
6 8
7const char *get_system_type(void) 9const char *get_system_type(void)
@@ -18,8 +20,10 @@ static void __init qemu_timer_setup(struct irqaction *irq)
18 setup_irq(0, irq); 20 setup_irq(0, irq);
19} 21}
20 22
21void __init plat_setup(void) 23void __init plat_mem_setup(void)
22{ 24{
23 set_io_port_base(QEMU_PORT_BASE); 25 set_io_port_base(QEMU_PORT_BASE);
24 board_timer_setup = qemu_timer_setup; 26 board_timer_setup = qemu_timer_setup;
27
28 qemu_reboot_setup();
25} 29}
diff --git a/arch/mips/sgi-ip22/ip22-setup.c b/arch/mips/sgi-ip22/ip22-setup.c
index 7018e1833e85..d7138906eb10 100644
--- a/arch/mips/sgi-ip22/ip22-setup.c
+++ b/arch/mips/sgi-ip22/ip22-setup.c
@@ -53,7 +53,7 @@ EXPORT_SYMBOL(ip22_do_break);
53extern void ip22_be_init(void) __init; 53extern void ip22_be_init(void) __init;
54extern void ip22_time_init(void) __init; 54extern void ip22_time_init(void) __init;
55 55
56void __init plat_setup(void) 56void __init plat_mem_setup(void)
57{ 57{
58 char *ctype; 58 char *ctype;
59 char *cserial; 59 char *cserial;
diff --git a/arch/mips/sgi-ip27/Kconfig b/arch/mips/sgi-ip27/Kconfig
index 7b0bc4437243..f14ef38646d0 100644
--- a/arch/mips/sgi-ip27/Kconfig
+++ b/arch/mips/sgi-ip27/Kconfig
@@ -4,31 +4,29 @@
4# This options adds support for userspace processes upto 16TB size. 4# This options adds support for userspace processes upto 16TB size.
5# Normally the limit is just .5TB. 5# Normally the limit is just .5TB.
6 6
7config SGI_SN0_N_MODE 7choice
8 bool "IP27 N-Mode" 8 prompt "Node addressing mode"
9 depends on SGI_IP27 9 depends on SGI_IP27
10 help 10 default SGI_SN_M_MODE
11 The nodes of Origin 200, Origin 2000 and Onyx 2 systems can be
12 configured in either N-Modes which allows for more nodes or M-Mode
13 which allows for more memory. Your system is most probably
14 running in M-Mode, so you should say N here.
15 11
16config ARCH_DISCONTIGMEM_ENABLE 12config SGI_SN_M_MODE
17 bool 13 bool "IP27 M-Mode"
18 default y if SGI_IP27
19 help 14 help
20 Say Y to upport efficient handling of discontiguous physical memory, 15 The nodes of Origin, Onyx, Fuel and Tezro systems can be configured
21 for architectures which are either NUMA (Non-Uniform Memory Access) 16 in either N-Modes which allows for more nodes or M-Mode which allows
22 or have huge holes in the physical address space for other reasons. 17 for more memory. Your hardware is almost certainly running in
23 See <file:Documentation/vm/numa> for more. 18 M-Mode, so choose M-mode here.
24 19
25config NUMA 20config SGI_SN_N_MODE
26 bool "NUMA Support" 21 bool "IP27 N-Mode"
27 depends on SGI_IP27 22 depends on EXPERIMENTAL
28 help 23 help
29 Say Y to compile the kernel to support NUMA (Non-Uniform Memory 24 The nodes of Origin, Onyx, Fuel and Tezro systems can be configured
30 Access). This option is for configuring high-end multiprocessor 25 in either N-Modes which allows for more nodes or M-Mode which allows
31 server machines. If in doubt, say N. 26 for more memory. Your hardware is almost certainly running in
27 M-Mode, so choose M-mode here.
28
29endchoice
32 30
33config MAPPED_KERNEL 31config MAPPED_KERNEL
34 bool "Mapped kernel support" 32 bool "Mapped kernel support"
diff --git a/arch/mips/sgi-ip27/ip27-init.c b/arch/mips/sgi-ip27/ip27-init.c
index 8651a0e75404..a6b490e99709 100644
--- a/arch/mips/sgi-ip27/ip27-init.c
+++ b/arch/mips/sgi-ip27/ip27-init.c
@@ -196,7 +196,7 @@ extern void ip27_setup_console(void);
196extern void ip27_time_init(void); 196extern void ip27_time_init(void);
197extern void ip27_reboot_setup(void); 197extern void ip27_reboot_setup(void);
198 198
199void __init plat_setup(void) 199void __init plat_mem_setup(void)
200{ 200{
201 hubreg_t p, e, n_mode; 201 hubreg_t p, e, n_mode;
202 nasid_t nid; 202 nasid_t nid;
@@ -228,7 +228,7 @@ void __init plat_setup(void)
228 */ 228 */
229 n_mode = LOCAL_HUB_L(NI_STATUS_REV_ID) & NSRI_MORENODES_MASK; 229 n_mode = LOCAL_HUB_L(NI_STATUS_REV_ID) & NSRI_MORENODES_MASK;
230 printk("Machine is in %c mode.\n", n_mode ? 'N' : 'M'); 230 printk("Machine is in %c mode.\n", n_mode ? 'N' : 'M');
231#ifdef CONFIG_SGI_SN0_N_MODE 231#ifdef CONFIG_SGI_SN_N_MODE
232 if (!n_mode) 232 if (!n_mode)
233 panic("Kernel compiled for M mode."); 233 panic("Kernel compiled for M mode.");
234#else 234#else
diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c
index 2e643d2f51cb..0b61a39ce2bb 100644
--- a/arch/mips/sgi-ip27/ip27-irq.c
+++ b/arch/mips/sgi-ip27/ip27-irq.c
@@ -360,7 +360,7 @@ static struct hw_interrupt_type bridge_irq_type = {
360 360
361static unsigned long irq_map[NR_IRQS / BITS_PER_LONG]; 361static unsigned long irq_map[NR_IRQS / BITS_PER_LONG];
362 362
363static int allocate_irqno(void) 363int allocate_irqno(void)
364{ 364{
365 int irq; 365 int irq;
366 366
diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c
index 36b662e27b6e..1fb860c7ac6d 100644
--- a/arch/mips/sgi-ip27/ip27-timer.c
+++ b/arch/mips/sgi-ip27/ip27-timer.c
@@ -89,11 +89,13 @@ static int set_rtc_mmss(unsigned long nowtime)
89} 89}
90#endif 90#endif
91 91
92static unsigned int rt_timer_irq;
93
92void ip27_rt_timer_interrupt(struct pt_regs *regs) 94void ip27_rt_timer_interrupt(struct pt_regs *regs)
93{ 95{
94 int cpu = smp_processor_id(); 96 int cpu = smp_processor_id();
95 int cpuA = cputoslice(cpu) == 0; 97 int cpuA = cputoslice(cpu) == 0;
96 int irq = 9; /* XXX Assign number */ 98 unsigned int irq = rt_timer_irq;
97 99
98 irq_enter(); 100 irq_enter();
99 write_seqlock(&xtime_lock); 101 write_seqlock(&xtime_lock);
@@ -179,13 +181,68 @@ static __init unsigned long get_m48t35_time(void)
179 return mktime(year, month, date, hour, min, sec); 181 return mktime(year, month, date, hour, min, sec);
180} 182}
181 183
184static void startup_rt_irq(unsigned int irq)
185{
186}
187
188static void shutdown_rt_irq(unsigned int irq)
189{
190}
191
192static void enable_rt_irq(unsigned int irq)
193{
194}
195
196static void disable_rt_irq(unsigned int irq)
197{
198}
199
200static void mask_and_ack_rt(unsigned int irq)
201{
202}
203
204static void end_rt_irq(unsigned int irq)
205{
206}
207
208static struct hw_interrupt_type rt_irq_type = {
209 .typename = "SN HUB RT timer",
210 .startup = startup_rt_irq,
211 .shutdown = shutdown_rt_irq,
212 .enable = enable_rt_irq,
213 .disable = disable_rt_irq,
214 .ack = mask_and_ack_rt,
215 .end = end_rt_irq,
216};
217
218static struct irqaction rt_irqaction = {
219 .handler = ip27_rt_timer_interrupt,
220 .flags = SA_INTERRUPT,
221 .mask = CPU_MASK_NONE,
222 .name = "timer"
223};
224
225extern int allocate_irqno(void);
226
182static void ip27_timer_setup(struct irqaction *irq) 227static void ip27_timer_setup(struct irqaction *irq)
183{ 228{
229 int irqno = allocate_irqno();
230
231 if (irqno < 0)
232 panic("Can't allocate interrupt number for timer interrupt");
233
234 irq_desc[irqno].status = IRQ_DISABLED;
235 irq_desc[irqno].action = NULL;
236 irq_desc[irqno].depth = 1;
237 irq_desc[irqno].handler = &rt_irq_type;
238
184 /* over-write the handler, we use our own way */ 239 /* over-write the handler, we use our own way */
185 irq->handler = no_action; 240 irq->handler = no_action;
186 241
187 /* setup irqaction */ 242 /* setup irqaction */
188// setup_irq(IP27_TIMER_IRQ, irq); /* XXX Can't do this yet. */ 243 irq_desc[irqno].status |= IRQ_PER_CPU;
244
245 rt_timer_irq = irqno;
189} 246}
190 247
191void __init ip27_time_init(void) 248void __init ip27_time_init(void)
diff --git a/arch/mips/sgi-ip32/ip32-setup.c b/arch/mips/sgi-ip32/ip32-setup.c
index a2dd8ae1ea8f..acbdad06fac1 100644
--- a/arch/mips/sgi-ip32/ip32-setup.c
+++ b/arch/mips/sgi-ip32/ip32-setup.c
@@ -87,7 +87,7 @@ void __init ip32_timer_setup(struct irqaction *irq)
87 setup_irq(IP32_R4K_TIMER_IRQ, irq); 87 setup_irq(IP32_R4K_TIMER_IRQ, irq);
88} 88}
89 89
90void __init plat_setup(void) 90void __init plat_mem_setup(void)
91{ 91{
92 board_be_init = ip32_be_init; 92 board_be_init = ip32_be_init;
93 93
diff --git a/arch/mips/sibyte/bcm1480/time.c b/arch/mips/sibyte/bcm1480/time.c
index e545752695a1..efaf83efd2e4 100644
--- a/arch/mips/sibyte/bcm1480/time.c
+++ b/arch/mips/sibyte/bcm1480/time.c
@@ -110,17 +110,18 @@ void bcm1480_timer_interrupt(struct pt_regs *regs)
110 __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS, 110 __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS,
111 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); 111 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
112 112
113 /*
114 * CPU 0 handles the global timer interrupt job
115 */
116 if (cpu == 0) { 113 if (cpu == 0) {
114 /*
115 * CPU 0 handles the global timer interrupt job
116 */
117 ll_timer_interrupt(irq, regs); 117 ll_timer_interrupt(irq, regs);
118 } 118 }
119 119 else {
120 /* 120 /*
121 * every CPU should do profiling and process accouting 121 * other CPUs should just do profiling and process accounting
122 */ 122 */
123 ll_local_timer_interrupt(irq, regs); 123 ll_local_timer_interrupt(irq, regs);
124 }
124} 125}
125 126
126/* 127/*
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index 0f6e54db4888..f853c32f60a0 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -435,13 +435,17 @@ static inline int dclz(unsigned long long x)
435 return lz; 435 return lz;
436} 436}
437 437
438extern void sb1250_timer_interrupt(struct pt_regs *regs);
439extern void sb1250_mailbox_interrupt(struct pt_regs *regs);
440extern void sb1250_kgdb_interrupt(struct pt_regs *regs);
441
438asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 442asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
439{ 443{
440 unsigned int pending; 444 unsigned int pending;
441 445
442#ifdef CONFIG_SIBYTE_SB1250_PROF 446#ifdef CONFIG_SIBYTE_SB1250_PROF
443 /* Set compare to count to silence count/compare timer interrupts */ 447 /* Set compare to count to silence count/compare timer interrupts */
444 write_c0_count(read_c0_count()); 448 write_c0_compare(read_c0_count());
445#endif 449#endif
446 450
447 /* 451 /*
@@ -482,7 +486,7 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
482 * Default...we've hit an IP[2] interrupt, which means we've 486 * Default...we've hit an IP[2] interrupt, which means we've
483 * got to check the 1250 interrupt registers to figure out what 487 * got to check the 1250 interrupt registers to figure out what
484 * to do. Need to detect which CPU we're on, now that 488 * to do. Need to detect which CPU we're on, now that
485 ~ smp_affinity is supported. 489 * smp_affinity is supported.
486 */ 490 */
487 mask = __raw_readq(IOADDR(A_IMR_REGISTER(smp_processor_id(), 491 mask = __raw_readq(IOADDR(A_IMR_REGISTER(smp_processor_id(),
488 R_IMR_INTERRUPT_STATUS_BASE))); 492 R_IMR_INTERRUPT_STATUS_BASE)));
diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c
index 4b5f74ff3edd..f9e694988cdf 100644
--- a/arch/mips/sibyte/swarm/setup.c
+++ b/arch/mips/sibyte/swarm/setup.c
@@ -72,8 +72,10 @@ const char *get_system_type(void)
72 72
73void __init swarm_time_init(void) 73void __init swarm_time_init(void)
74{ 74{
75#if defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
75 /* Setup HPT */ 76 /* Setup HPT */
76 sb1250_hpt_setup(); 77 sb1250_hpt_setup();
78#endif
77} 79}
78 80
79void __init swarm_timer_setup(struct irqaction *irq) 81void __init swarm_timer_setup(struct irqaction *irq)
@@ -103,7 +105,7 @@ int swarm_be_handler(struct pt_regs *regs, int is_fixup)
103 return (is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL); 105 return (is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL);
104} 106}
105 107
106void __init plat_setup(void) 108void __init plat_mem_setup(void)
107{ 109{
108#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) 110#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
109 bcm1480_setup(); 111 bcm1480_setup();
diff --git a/arch/mips/sni/Makefile b/arch/mips/sni/Makefile
index 9c7eaa5fb210..a5eb0adb87c7 100644
--- a/arch/mips/sni/Makefile
+++ b/arch/mips/sni/Makefile
@@ -3,5 +3,6 @@
3# 3#
4 4
5obj-y += irq.o pcimt_scache.o reset.o setup.o 5obj-y += irq.o pcimt_scache.o reset.o setup.o
6obj-$(CONFIG_CPU_BIG_ENDIAN) += sniprom.o
6 7
7EXTRA_AFLAGS := $(CFLAGS) 8EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c
index 01ba6c581e3d..a050bb6ae704 100644
--- a/arch/mips/sni/setup.c
+++ b/arch/mips/sni/setup.c
@@ -21,8 +21,11 @@
21#include <linux/fb.h> 21#include <linux/fb.h>
22#include <linux/tty.h> 22#include <linux/tty.h>
23 23
24#ifdef CONFIG_ARC
24#include <asm/arc/types.h> 25#include <asm/arc/types.h>
25#include <asm/sgialib.h> 26#include <asm/sgialib.h>
27#endif
28
26#include <asm/bcache.h> 29#include <asm/bcache.h>
27#include <asm/bootinfo.h> 30#include <asm/bootinfo.h>
28#include <asm/io.h> 31#include <asm/io.h>
@@ -72,8 +75,7 @@ static inline void sni_pcimt_detect(void)
72 75
73static void __init sni_display_setup(void) 76static void __init sni_display_setup(void)
74{ 77{
75#ifdef CONFIG_VT 78#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) && defined(CONFIG_ARC)
76#if defined(CONFIG_VGA_CONSOLE)
77 struct screen_info *si = &screen_info; 79 struct screen_info *si = &screen_info;
78 DISPLAY_STATUS *di; 80 DISPLAY_STATUS *di;
79 81
@@ -88,24 +90,54 @@ static void __init sni_display_setup(void)
88 si->orig_video_points = 16; 90 si->orig_video_points = 16;
89 } 91 }
90#endif 92#endif
91#endif
92} 93}
93 94
94static struct resource sni_io_resource = { 95static struct resource sni_io_resource = {
95 "PCIMT IO MEM", 0x00001000UL, 0x03bfffffUL, IORESOURCE_IO, 96 .start = 0x00001000UL,
97 .end = 0x03bfffffUL,
98 .name = "PCIMT IO MEM",
99 .flags = IORESOURCE_IO,
96}; 100};
97 101
98static struct resource pcimt_io_resources[] = { 102static struct resource pcimt_io_resources[] = {
99 { "dma1", 0x00, 0x1f, IORESOURCE_BUSY }, 103 {
100 { "timer", 0x40, 0x5f, IORESOURCE_BUSY }, 104 .start = 0x00,
101 { "keyboard", 0x60, 0x6f, IORESOURCE_BUSY }, 105 .end = 0x1f,
102 { "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY }, 106 .name = "dma1",
103 { "dma2", 0xc0, 0xdf, IORESOURCE_BUSY }, 107 .flags = IORESOURCE_BUSY
104 { "PCI config data", 0xcfc, 0xcff, IORESOURCE_BUSY } 108 }, {
109 .start = 0x40,
110 .end = 0x5f,
111 .name = "timer",
112 .flags = IORESOURCE_BUSY
113 }, {
114 .start = 0x60,
115 .end = 0x6f,
116 .name = "keyboard",
117 .flags = IORESOURCE_BUSY
118 }, {
119 .start = 0x80,
120 .end = 0x8f,
121 .name = "dma page reg",
122 .flags = IORESOURCE_BUSY
123 }, {
124 .start = 0xc0,
125 .end = 0xdf,
126 .name = "dma2",
127 .flags = IORESOURCE_BUSY
128 }, {
129 .start = 0xcfc,
130 .end = 0xcff,
131 .name = "PCI config data",
132 .flags = IORESOURCE_BUSY
133 }
105}; 134};
106 135
107static struct resource sni_mem_resource = { 136static struct resource sni_mem_resource = {
108 "PCIMT PCI MEM", 0x10000000UL, 0xffffffffUL, IORESOURCE_MEM 137 .start = 0x10000000UL,
138 .end = 0xffffffffUL,
139 .name = "PCIMT PCI MEM",
140 .flags = IORESOURCE_MEM
109}; 141};
110 142
111/* 143/*
@@ -122,19 +154,72 @@ static struct resource sni_mem_resource = {
122 * 0xa0000000 - 0xffffffff (1.5GB) PCI/EISA Bus Memory 154 * 0xa0000000 - 0xffffffff (1.5GB) PCI/EISA Bus Memory
123 */ 155 */
124static struct resource pcimt_mem_resources[] = { 156static struct resource pcimt_mem_resources[] = {
125 { "Video RAM area", 0x100a0000, 0x100bffff, IORESOURCE_BUSY }, 157 {
126 { "ISA Reserved", 0x100c0000, 0x100fffff, IORESOURCE_BUSY }, 158 .start = 0x100a0000,
127 { "PCI IO", 0x14000000, 0x17bfffff, IORESOURCE_BUSY }, 159 .end = 0x100bffff,
128 { "Cache Replacement Area", 0x17c00000, 0x17ffffff, IORESOURCE_BUSY}, 160 .name = "Video RAM area",
129 { "PCI INT Acknowledge", 0x1a000000, 0x1a000003, IORESOURCE_BUSY }, 161 .flags = IORESOURCE_BUSY
130 { "Boot PROM", 0x1fc00000, 0x1fc7ffff, IORESOURCE_BUSY}, 162 }, {
131 { "Diag PROM", 0x1fc80000, 0x1fcfffff, IORESOURCE_BUSY}, 163 .start = 0x100c0000,
132 { "X-Bus", 0x1fd00000, 0x1fdfffff, IORESOURCE_BUSY}, 164 .end = 0x100fffff,
133 { "BIOS map", 0x1fe00000, 0x1fefffff, IORESOURCE_BUSY}, 165 .name = "ISA Reserved",
134 { "NVRAM / EEPROM", 0x1ff00000, 0x1ff7ffff, IORESOURCE_BUSY}, 166 .flags = IORESOURCE_BUSY
135 { "ASIC PCI", 0x1fff0000, 0x1fffefff, IORESOURCE_BUSY}, 167 }, {
136 { "MP Agent", 0x1ffff000, 0x1fffffff, IORESOURCE_BUSY}, 168 .start = 0x14000000,
137 { "Main Memory", 0x20000000, 0x9fffffff, IORESOURCE_BUSY} 169 .end = 0x17bfffff,
170 .name = "PCI IO",
171 .flags = IORESOURCE_BUSY
172 }, {
173 .start = 0x17c00000,
174 .end = 0x17ffffff,
175 .name = "Cache Replacement Area",
176 .flags = IORESOURCE_BUSY
177 }, {
178 .start = 0x1a000000,
179 .end = 0x1a000003,
180 .name = "PCI INT Acknowledge",
181 .flags = IORESOURCE_BUSY
182 }, {
183 .start = 0x1fc00000,
184 .end = 0x1fc7ffff,
185 .name = "Boot PROM",
186 .flags = IORESOURCE_BUSY
187 }, {
188 .start = 0x1fc80000,
189 .end = 0x1fcfffff,
190 .name = "Diag PROM",
191 .flags = IORESOURCE_BUSY
192 }, {
193 .start = 0x1fd00000,
194 .end = 0x1fdfffff,
195 .name = "X-Bus",
196 .flags = IORESOURCE_BUSY
197 }, {
198 .start = 0x1fe00000,
199 .end = 0x1fefffff,
200 .name = "BIOS map",
201 .flags = IORESOURCE_BUSY
202 }, {
203 .start = 0x1ff00000,
204 .end = 0x1ff7ffff,
205 .name = "NVRAM / EEPROM",
206 .flags = IORESOURCE_BUSY
207 }, {
208 .start = 0x1fff0000,
209 .end = 0x1fffefff,
210 .name = "ASIC PCI",
211 .flags = IORESOURCE_BUSY
212 }, {
213 .start = 0x1ffff000,
214 .end = 0x1fffffff,
215 .name = "MP Agent",
216 .flags = IORESOURCE_BUSY
217 }, {
218 .start = 0x20000000,
219 .end = 0x9fffffff,
220 .name = "Main Memory",
221 .flags = IORESOURCE_BUSY
222 }
138}; 223};
139 224
140static void __init sni_resource_init(void) 225static void __init sni_resource_init(void)
@@ -168,7 +253,7 @@ static inline void sni_pcimt_time_init(void)
168 rtc_mips_set_time = mc146818_set_rtc_mmss; 253 rtc_mips_set_time = mc146818_set_rtc_mmss;
169} 254}
170 255
171void __init plat_setup(void) 256void __init plat_mem_setup(void)
172{ 257{
173 sni_pcimt_detect(); 258 sni_pcimt_detect();
174 sni_pcimt_sc_init(); 259 sni_pcimt_sc_init();
diff --git a/arch/mips/sni/sniprom.c b/arch/mips/sni/sniprom.c
new file mode 100644
index 000000000000..d1d0f1f493b4
--- /dev/null
+++ b/arch/mips/sni/sniprom.c
@@ -0,0 +1,158 @@
1/*
2 * Big Endian PROM code for SNI RM machines
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2005-2006 Florian Lohoff (flo@rfc822.org)
9 * Copyright (C) 2005-2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
10 */
11
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/string.h>
15
16#include <asm/addrspace.h>
17#include <asm/sni.h>
18#include <asm/mipsprom.h>
19#include <asm/bootinfo.h>
20
21/* special SNI prom calls */
22/*
23 * This does not exist in all proms - SINIX compares
24 * the prom env variable "version" against "2.0008"
25 * or greater. If lesser it tries to probe interesting
26 * registers
27 */
28#define PROM_GET_MEMCONF 58
29
30#define PROM_VEC (u64 *)CKSEG1ADDR(0x1fc00000)
31#define PROM_ENTRY(x) (PROM_VEC + (x))
32
33
34#undef DEBUG
35#ifdef DEBUG
36#define DBG_PRINTF(x...) prom_printf(x)
37#else
38#define DBG_PRINTF(x...)
39#endif
40
41static int *(*__prom_putchar)(int) = (int *(*)(int))PROM_ENTRY(PROM_PUTCHAR);
42static char *(*__prom_getenv)(char *) = (char *(*)(char *))PROM_ENTRY(PROM_GETENV);
43static void (*__prom_get_memconf)(void *) = (void (*)(void *))PROM_ENTRY(PROM_GET_MEMCONF);
44
45char *prom_getenv (char *s)
46{
47 return __prom_getenv(s);
48}
49
50void prom_printf(char *fmt, ...)
51{
52 va_list args;
53 char ppbuf[1024];
54 char *bptr;
55
56 va_start(args, fmt);
57 vsprintf(ppbuf, fmt, args);
58
59 bptr = ppbuf;
60
61 while (*bptr != 0) {
62 if (*bptr == '\n')
63 __prom_putchar('\r');
64
65 __prom_putchar(*bptr++);
66 }
67 va_end(args);
68}
69
70unsigned long prom_free_prom_memory(void)
71{
72 return 0;
73}
74
75/*
76 * /proc/cpuinfo system type
77 *
78 */
79static const char *systype = "Unknown";
80const char *get_system_type(void)
81{
82 return systype;
83}
84
85#define SNI_IDPROM_BASE 0xbff00000
86#define SNI_IDPROM_MEMSIZE (SNI_IDPROM_BASE+0x28) /* Memsize in 16MB quantities */
87#define SNI_IDPROM_BRDTYPE (SNI_IDPROM_BASE+0x29) /* Board Type */
88#define SNI_IDPROM_CPUTYPE (SNI_IDPROM_BASE+0x30) /* CPU Type */
89
90#define SNI_IDPROM_SIZE 0x1000
91
92#ifdef DEBUG
93static void sni_idprom_dump(void)
94{
95 int i;
96
97 prom_printf("SNI IDProm dump (first 128byte):\n");
98 for(i=0;i<128;i++) {
99 if (i%16 == 0)
100 prom_printf("%04x ", i);
101
102 prom_printf("%02x ", *(unsigned char *) (SNI_IDPROM_BASE+i));
103
104 if (i%16 == 15)
105 prom_printf("\n");
106 }
107}
108#endif
109
110static void sni_mem_init(void )
111{
112 int i, memsize;
113 struct membank {
114 u32 size;
115 u32 base;
116 u32 size2;
117 u32 pad1;
118 u32 pad2;
119 } memconf[8];
120
121 /* MemSIZE from prom in 16MByte chunks */
122 memsize=*((unsigned char *) SNI_IDPROM_MEMSIZE) * 16;
123
124 DBG_PRINTF("IDProm memsize: %lu MByte\n", memsize);
125
126 /* get memory bank layout from prom */
127 __prom_get_memconf(&memconf);
128
129 DBG_PRINTF("prom_get_mem_conf memory configuration:\n");
130 for(i=0;i<8 && memconf[i].size;i++) {
131 prom_printf("Bank%d: %08x @ %08x\n", i,
132 memconf[i].size, memconf[i].base);
133 add_memory_region(memconf[i].base, memconf[i].size, BOOT_MEM_RAM);
134 }
135}
136
137void __init prom_init(void)
138{
139 int argc = fw_arg0;
140 char **argv = (void *)fw_arg1;
141 unsigned int sni_brd_type = *(unsigned char *) SNI_IDPROM_BRDTYPE;
142 int i;
143
144 DBG_PRINTF("Found SNI brdtype %02x\n", sni_brd_type);
145
146#ifdef DEBUG
147 sni_idprom_dump();
148#endif
149 sni_mem_init();
150
151 /* copy prom cmdline parameters to kernel cmdline */
152 for (i = 1; i < argc; i++) {
153 strcat(arcs_cmdline, argv[i]);
154 if (i < (argc - 1))
155 strcat(arcs_cmdline, " ");
156 }
157}
158
diff --git a/arch/mips/tx4927/common/tx4927_setup.c b/arch/mips/tx4927/common/tx4927_setup.c
index 77c3b66fb959..81a5acfe8c42 100644
--- a/arch/mips/tx4927/common/tx4927_setup.c
+++ b/arch/mips/tx4927/common/tx4927_setup.c
@@ -64,7 +64,7 @@ static void tx4927_write_buffer_flush(void)
64} 64}
65 65
66 66
67void __init plat_setup(void) 67void __init plat_mem_setup(void)
68{ 68{
69 board_time_init = tx4927_time_init; 69 board_time_init = tx4927_time_init;
70 board_timer_setup = tx4927_timer_setup; 70 board_timer_setup = tx4927_timer_setup;
diff --git a/arch/mips/tx4938/common/setup.c b/arch/mips/tx4938/common/setup.c
index fc992953bf95..ef59a5cffc69 100644
--- a/arch/mips/tx4938/common/setup.c
+++ b/arch/mips/tx4938/common/setup.c
@@ -61,7 +61,7 @@ tx4938_write_buffer_flush(void)
61} 61}
62 62
63void __init 63void __init
64plat_setup(void) 64plat_mem_setup(void)
65{ 65{
66 board_time_init = tx4938_time_init; 66 board_time_init = tx4938_time_init;
67 board_timer_setup = tx4938_timer_setup; 67 board_timer_setup = tx4938_timer_setup;
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/setup.c b/arch/mips/tx4938/toshiba_rbtx4938/setup.c
index 9166cd4557eb..96e833cd4c14 100644
--- a/arch/mips/tx4938/toshiba_rbtx4938/setup.c
+++ b/arch/mips/tx4938/toshiba_rbtx4938/setup.c
@@ -664,7 +664,10 @@ static struct resource rbtx4938_fpga_resource;
664 664
665static char pcode_str[8]; 665static char pcode_str[8];
666static struct resource tx4938_reg_resource = { 666static struct resource tx4938_reg_resource = {
667 pcode_str, TX4938_REG_BASE, TX4938_REG_BASE+TX4938_REG_SIZE, IORESOURCE_MEM 667 .start = TX4938_REG_BASE,
668 .end = TX4938_REG_BASE + TX4938_REG_SIZE,
669 .name = pcode_str,
670 .flags = IORESOURCE_MEM
668}; 671};
669 672
670void __init tx4938_board_setup(void) 673void __init tx4938_board_setup(void)
diff --git a/arch/mips/vr41xx/Kconfig b/arch/mips/vr41xx/Kconfig
index 055a2cdfc841..6046ef23b2bf 100644
--- a/arch/mips/vr41xx/Kconfig
+++ b/arch/mips/vr41xx/Kconfig
@@ -4,7 +4,6 @@ config CASIO_E55
4 select DMA_NONCOHERENT 4 select DMA_NONCOHERENT
5 select IRQ_CPU 5 select IRQ_CPU
6 select ISA 6 select ISA
7 select SYS_HAS_CPU_VR41XX
8 select SYS_SUPPORTS_32BIT_KERNEL 7 select SYS_SUPPORTS_32BIT_KERNEL
9 select SYS_SUPPORTS_LITTLE_ENDIAN 8 select SYS_SUPPORTS_LITTLE_ENDIAN
10 9
@@ -14,18 +13,15 @@ config IBM_WORKPAD
14 select DMA_NONCOHERENT 13 select DMA_NONCOHERENT
15 select IRQ_CPU 14 select IRQ_CPU
16 select ISA 15 select ISA
17 select SYS_HAS_CPU_VR41XX
18 select SYS_SUPPORTS_32BIT_KERNEL 16 select SYS_SUPPORTS_32BIT_KERNEL
19 select SYS_SUPPORTS_LITTLE_ENDIAN 17 select SYS_SUPPORTS_LITTLE_ENDIAN
20 18
21config NEC_CMBVR4133 19config NEC_CMBVR4133
22 bool "Support for NEC CMB-VR4133" 20 bool "Support for NEC CMB-VR4133"
23 depends on MACH_VR41XX 21 depends on MACH_VR41XX
24 select CPU_VR41XX
25 select DMA_NONCOHERENT 22 select DMA_NONCOHERENT
26 select IRQ_CPU 23 select IRQ_CPU
27 select HW_HAS_PCI 24 select HW_HAS_PCI
28 select SYS_HAS_CPU_VR41XX
29 select SYS_SUPPORTS_32BIT_KERNEL 25 select SYS_SUPPORTS_32BIT_KERNEL
30 select SYS_SUPPORTS_LITTLE_ENDIAN 26 select SYS_SUPPORTS_LITTLE_ENDIAN
31 27
@@ -41,7 +37,6 @@ config TANBAC_TB022X
41 select DMA_NONCOHERENT 37 select DMA_NONCOHERENT
42 select HW_HAS_PCI 38 select HW_HAS_PCI
43 select IRQ_CPU 39 select IRQ_CPU
44 select SYS_HAS_CPU_VR41XX
45 select SYS_SUPPORTS_32BIT_KERNEL 40 select SYS_SUPPORTS_32BIT_KERNEL
46 select SYS_SUPPORTS_LITTLE_ENDIAN 41 select SYS_SUPPORTS_LITTLE_ENDIAN
47 help 42 help
@@ -74,7 +69,6 @@ config VICTOR_MPC30X
74 select DMA_NONCOHERENT 69 select DMA_NONCOHERENT
75 select HW_HAS_PCI 70 select HW_HAS_PCI
76 select IRQ_CPU 71 select IRQ_CPU
77 select SYS_HAS_CPU_VR41XX
78 select SYS_SUPPORTS_32BIT_KERNEL 72 select SYS_SUPPORTS_32BIT_KERNEL
79 select SYS_SUPPORTS_LITTLE_ENDIAN 73 select SYS_SUPPORTS_LITTLE_ENDIAN
80 74
@@ -84,7 +78,6 @@ config ZAO_CAPCELLA
84 select DMA_NONCOHERENT 78 select DMA_NONCOHERENT
85 select HW_HAS_PCI 79 select HW_HAS_PCI
86 select IRQ_CPU 80 select IRQ_CPU
87 select SYS_HAS_CPU_VR41XX
88 select SYS_SUPPORTS_32BIT_KERNEL 81 select SYS_SUPPORTS_32BIT_KERNEL
89 select SYS_SUPPORTS_LITTLE_ENDIAN 82 select SYS_SUPPORTS_LITTLE_ENDIAN
90 83
diff --git a/arch/mips/vr41xx/common/init.c b/arch/mips/vr41xx/common/init.c
index 707bd0933eed..915bfa5c0719 100644
--- a/arch/mips/vr41xx/common/init.c
+++ b/arch/mips/vr41xx/common/init.c
@@ -58,7 +58,7 @@ static void __init timer_init(void)
58 board_timer_setup = setup_timer_irq; 58 board_timer_setup = setup_timer_irq;
59} 59}
60 60
61void __init plat_setup(void) 61void __init plat_mem_setup(void)
62{ 62{
63 vr41xx_calculate_clock_frequency(); 63 vr41xx_calculate_clock_frequency();
64 64
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index 41e9ab40cd54..f70bd090dacd 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -822,6 +822,7 @@ static void __init prom_send_capabilities(void)
822 /* try calling the ibm,client-architecture-support method */ 822 /* try calling the ibm,client-architecture-support method */
823 if (call_prom_ret("call-method", 3, 2, &ret, 823 if (call_prom_ret("call-method", 3, 2, &ret,
824 ADDR("ibm,client-architecture-support"), 824 ADDR("ibm,client-architecture-support"),
825 root,
825 ADDR(ibm_architecture_vec)) == 0) { 826 ADDR(ibm_architecture_vec)) == 0) {
826 /* the call exists... */ 827 /* the call exists... */
827 if (ret) 828 if (ret)
@@ -1622,6 +1623,15 @@ static int __init prom_find_machine_type(void)
1622 if (strstr(p, RELOC("Power Macintosh")) || 1623 if (strstr(p, RELOC("Power Macintosh")) ||
1623 strstr(p, RELOC("MacRISC"))) 1624 strstr(p, RELOC("MacRISC")))
1624 return PLATFORM_POWERMAC; 1625 return PLATFORM_POWERMAC;
1626#ifdef CONFIG_PPC64
1627 /* We must make sure we don't detect the IBM Cell
1628 * blades as pSeries due to some firmware issues,
1629 * so we do it here.
1630 */
1631 if (strstr(p, RELOC("IBM,CBEA")) ||
1632 strstr(p, RELOC("IBM,CPBW-1.0")))
1633 return PLATFORM_GENERIC;
1634#endif /* CONFIG_PPC64 */
1625 i += sl + 1; 1635 i += sl + 1;
1626 } 1636 }
1627 } 1637 }
diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c
index 01e3c08cb550..8fdeca2d4597 100644
--- a/arch/powerpc/kernel/signal_32.c
+++ b/arch/powerpc/kernel/signal_32.c
@@ -803,10 +803,13 @@ static int do_setcontext(struct ucontext __user *ucp, struct pt_regs *regs, int
803 if (__get_user(cmcp, &ucp->uc_regs)) 803 if (__get_user(cmcp, &ucp->uc_regs))
804 return -EFAULT; 804 return -EFAULT;
805 mcp = (struct mcontext __user *)(u64)cmcp; 805 mcp = (struct mcontext __user *)(u64)cmcp;
806 /* no need to check access_ok(mcp), since mcp < 4GB */
806 } 807 }
807#else 808#else
808 if (__get_user(mcp, &ucp->uc_regs)) 809 if (__get_user(mcp, &ucp->uc_regs))
809 return -EFAULT; 810 return -EFAULT;
811 if (!access_ok(VERIFY_READ, mcp, sizeof(*mcp)))
812 return -EFAULT;
810#endif 813#endif
811 restore_sigmask(&set); 814 restore_sigmask(&set);
812 if (restore_user_regs(regs, mcp, sig)) 815 if (restore_user_regs(regs, mcp, sig))
@@ -908,13 +911,14 @@ int sys_debug_setcontext(struct ucontext __user *ctx,
908{ 911{
909 struct sig_dbg_op op; 912 struct sig_dbg_op op;
910 int i; 913 int i;
914 unsigned char tmp;
911 unsigned long new_msr = regs->msr; 915 unsigned long new_msr = regs->msr;
912#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) 916#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
913 unsigned long new_dbcr0 = current->thread.dbcr0; 917 unsigned long new_dbcr0 = current->thread.dbcr0;
914#endif 918#endif
915 919
916 for (i=0; i<ndbg; i++) { 920 for (i=0; i<ndbg; i++) {
917 if (__copy_from_user(&op, dbg, sizeof(op))) 921 if (copy_from_user(&op, dbg + i, sizeof(op)))
918 return -EFAULT; 922 return -EFAULT;
919 switch (op.dbg_type) { 923 switch (op.dbg_type) {
920 case SIG_DBG_SINGLE_STEPPING: 924 case SIG_DBG_SINGLE_STEPPING:
@@ -959,6 +963,11 @@ int sys_debug_setcontext(struct ucontext __user *ctx,
959 current->thread.dbcr0 = new_dbcr0; 963 current->thread.dbcr0 = new_dbcr0;
960#endif 964#endif
961 965
966 if (!access_ok(VERIFY_READ, ctx, sizeof(*ctx))
967 || __get_user(tmp, (u8 __user *) ctx)
968 || __get_user(tmp, (u8 __user *) (ctx + 1) - 1))
969 return -EFAULT;
970
962 /* 971 /*
963 * If we get a fault copying the context into the kernel's 972 * If we get a fault copying the context into the kernel's
964 * image of the user's registers, we can't just return -EFAULT 973 * image of the user's registers, we can't just return -EFAULT
diff --git a/arch/powerpc/kernel/signal_64.c b/arch/powerpc/kernel/signal_64.c
index 27f65b95184d..c2db642f4cdd 100644
--- a/arch/powerpc/kernel/signal_64.c
+++ b/arch/powerpc/kernel/signal_64.c
@@ -182,6 +182,8 @@ static long restore_sigcontext(struct pt_regs *regs, sigset_t *set, int sig,
182 err |= __get_user(msr, &sc->gp_regs[PT_MSR]); 182 err |= __get_user(msr, &sc->gp_regs[PT_MSR]);
183 if (err) 183 if (err)
184 return err; 184 return err;
185 if (v_regs && !access_ok(VERIFY_READ, v_regs, 34 * sizeof(vector128)))
186 return -EFAULT;
185 /* Copy 33 vec registers (vr0..31 and vscr) from the stack */ 187 /* Copy 33 vec registers (vr0..31 and vscr) from the stack */
186 if (v_regs != 0 && (msr & MSR_VEC) != 0) 188 if (v_regs != 0 && (msr & MSR_VEC) != 0)
187 err |= __copy_from_user(current->thread.vr, v_regs, 189 err |= __copy_from_user(current->thread.vr, v_regs,
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index 33654d1b1b43..994856e55b7c 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -52,7 +52,7 @@ static inline void __tlbie(unsigned long va, unsigned int psize)
52 default: 52 default:
53 penc = mmu_psize_defs[psize].penc; 53 penc = mmu_psize_defs[psize].penc;
54 va &= ~((1ul << mmu_psize_defs[psize].shift) - 1); 54 va &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
55 va |= (0x7f >> (8 - penc)) << 12; 55 va |= penc << 12;
56 asm volatile("tlbie %0,1" : : "r" (va) : "memory"); 56 asm volatile("tlbie %0,1" : : "r" (va) : "memory");
57 break; 57 break;
58 } 58 }
@@ -74,7 +74,7 @@ static inline void __tlbiel(unsigned long va, unsigned int psize)
74 default: 74 default:
75 penc = mmu_psize_defs[psize].penc; 75 penc = mmu_psize_defs[psize].penc;
76 va &= ~((1ul << mmu_psize_defs[psize].shift) - 1); 76 va &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
77 va |= (0x7f >> (8 - penc)) << 12; 77 va |= penc << 12;
78 asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)" 78 asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)"
79 : : "r"(va) : "memory"); 79 : : "r"(va) : "memory");
80 break; 80 break;
diff --git a/arch/powerpc/platforms/cell/setup.c b/arch/powerpc/platforms/cell/setup.c
index 6574b22b3cf3..fd3e5609e3e0 100644
--- a/arch/powerpc/platforms/cell/setup.c
+++ b/arch/powerpc/platforms/cell/setup.c
@@ -125,14 +125,13 @@ static void __init cell_init_early(void)
125 125
126static int __init cell_probe(void) 126static int __init cell_probe(void)
127{ 127{
128 /* XXX This is temporary, the Cell maintainer will come up with
129 * more appropriate detection logic
130 */
131 unsigned long root = of_get_flat_dt_root(); 128 unsigned long root = of_get_flat_dt_root();
132 if (!of_flat_dt_is_compatible(root, "IBM,CPBW-1.0"))
133 return 0;
134 129
135 return 1; 130 if (of_flat_dt_is_compatible(root, "IBM,CBEA") ||
131 of_flat_dt_is_compatible(root, "IBM,CPBW-1.0"))
132 return 1;
133
134 return 0;
136} 135}
137 136
138/* 137/*
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c
index 5f79f01c44f2..3ba87835757e 100644
--- a/arch/powerpc/platforms/pseries/setup.c
+++ b/arch/powerpc/platforms/pseries/setup.c
@@ -389,6 +389,7 @@ static int __init pSeries_probe_hypertas(unsigned long node,
389 389
390static int __init pSeries_probe(void) 390static int __init pSeries_probe(void)
391{ 391{
392 unsigned long root = of_get_flat_dt_root();
392 char *dtype = of_get_flat_dt_prop(of_get_flat_dt_root(), 393 char *dtype = of_get_flat_dt_prop(of_get_flat_dt_root(),
393 "device_type", NULL); 394 "device_type", NULL);
394 if (dtype == NULL) 395 if (dtype == NULL)
@@ -396,6 +397,13 @@ static int __init pSeries_probe(void)
396 if (strcmp(dtype, "chrp")) 397 if (strcmp(dtype, "chrp"))
397 return 0; 398 return 0;
398 399
400 /* Cell blades firmware claims to be chrp while it's not. Until this
401 * is fixed, we need to avoid those here.
402 */
403 if (of_flat_dt_is_compatible(root, "IBM,CPBW-1.0") ||
404 of_flat_dt_is_compatible(root, "IBM,CBEA"))
405 return 0;
406
399 DBG("pSeries detected, looking for LPAR capability...\n"); 407 DBG("pSeries detected, looking for LPAR capability...\n");
400 408
401 /* Now try to figure out if we are running on LPAR */ 409 /* Now try to figure out if we are running on LPAR */
diff --git a/arch/sparc/kernel/smp.c b/arch/sparc/kernel/smp.c
index a93f5da6855d..40b42c88e6a7 100644
--- a/arch/sparc/kernel/smp.c
+++ b/arch/sparc/kernel/smp.c
@@ -69,6 +69,17 @@ void __init smp_store_cpu_info(int id)
69 "clock-frequency", 0); 69 "clock-frequency", 0);
70 cpu_data(id).prom_node = cpu_node; 70 cpu_data(id).prom_node = cpu_node;
71 cpu_data(id).mid = cpu_get_hwmid(cpu_node); 71 cpu_data(id).mid = cpu_get_hwmid(cpu_node);
72
73 /* this is required to tune the scheduler correctly */
74 /* is it possible to have CPUs with different cache sizes? */
75 if (id == boot_cpu_id) {
76 int cache_line,cache_nlines;
77 cache_line = 0x20;
78 cache_line = prom_getintdefault(cpu_node, "ecache-line-size", cache_line);
79 cache_nlines = 0x8000;
80 cache_nlines = prom_getintdefault(cpu_node, "ecache-nlines", cache_nlines);
81 max_cache_size = cache_line * cache_nlines;
82 }
72 if (cpu_data(id).mid < 0) 83 if (cpu_data(id).mid < 0)
73 panic("No MID found for CPU%d at node 0x%08d", id, cpu_node); 84 panic("No MID found for CPU%d at node 0x%08d", id, cpu_node);
74} 85}
diff --git a/arch/sparc64/kernel/pci_sun4v.c b/arch/sparc64/kernel/pci_sun4v.c
index 2b7a1f316a93..0c0895202970 100644
--- a/arch/sparc64/kernel/pci_sun4v.c
+++ b/arch/sparc64/kernel/pci_sun4v.c
@@ -599,18 +599,128 @@ struct pci_iommu_ops pci_sun4v_iommu_ops = {
599 599
600/* SUN4V PCI configuration space accessors. */ 600/* SUN4V PCI configuration space accessors. */
601 601
602static inline int pci_sun4v_out_of_range(struct pci_pbm_info *pbm, unsigned int bus, unsigned int device, unsigned int func) 602struct pdev_entry {
603 struct pdev_entry *next;
604 u32 devhandle;
605 unsigned int bus;
606 unsigned int device;
607 unsigned int func;
608};
609
610#define PDEV_HTAB_SIZE 16
611#define PDEV_HTAB_MASK (PDEV_HTAB_SIZE - 1)
612static struct pdev_entry *pdev_htab[PDEV_HTAB_SIZE];
613
614static inline unsigned int pdev_hashfn(u32 devhandle, unsigned int bus, unsigned int device, unsigned int func)
603{ 615{
604 if (bus == pbm->pci_first_busno) { 616 unsigned int val;
605 if (device == 0 && func == 0) 617
606 return 0; 618 val = (devhandle ^ (devhandle >> 4));
607 return 1; 619 val ^= bus;
620 val ^= device;
621 val ^= func;
622
623 return val & PDEV_HTAB_MASK;
624}
625
626static int pdev_htab_add(u32 devhandle, unsigned int bus, unsigned int device, unsigned int func)
627{
628 struct pdev_entry *p = kmalloc(sizeof(*p), GFP_KERNEL);
629 struct pdev_entry **slot;
630
631 if (!p)
632 return -ENOMEM;
633
634 slot = &pdev_htab[pdev_hashfn(devhandle, bus, device, func)];
635 p->next = *slot;
636 *slot = p;
637
638 p->devhandle = devhandle;
639 p->bus = bus;
640 p->device = device;
641 p->func = func;
642
643 return 0;
644}
645
646/* Recursively descend into the OBP device tree, rooted at toplevel_node,
647 * looking for a PCI device matching bus and devfn.
648 */
649static int obp_find(struct linux_prom_pci_registers *pregs, int toplevel_node, unsigned int bus, unsigned int devfn)
650{
651 toplevel_node = prom_getchild(toplevel_node);
652
653 while (toplevel_node != 0) {
654 int ret = obp_find(pregs, toplevel_node, bus, devfn);
655
656 if (ret != 0)
657 return ret;
658
659 ret = prom_getproperty(toplevel_node, "reg", (char *) pregs,
660 sizeof(*pregs) * PROMREG_MAX);
661 if (ret == 0 || ret == -1)
662 goto next_sibling;
663
664 if (((pregs[0].phys_hi >> 16) & 0xff) == bus &&
665 ((pregs[0].phys_hi >> 8) & 0xff) == devfn)
666 break;
667
668 next_sibling:
669 toplevel_node = prom_getsibling(toplevel_node);
670 }
671
672 return toplevel_node;
673}
674
675static int pdev_htab_populate(struct pci_pbm_info *pbm)
676{
677 struct linux_prom_pci_registers pr[PROMREG_MAX];
678 u32 devhandle = pbm->devhandle;
679 unsigned int bus;
680
681 for (bus = pbm->pci_first_busno; bus <= pbm->pci_last_busno; bus++) {
682 unsigned int devfn;
683
684 for (devfn = 0; devfn < 256; devfn++) {
685 unsigned int device = PCI_SLOT(devfn);
686 unsigned int func = PCI_FUNC(devfn);
687
688 if (obp_find(pr, pbm->prom_node, bus, devfn)) {
689 int err = pdev_htab_add(devhandle, bus,
690 device, func);
691 if (err)
692 return err;
693 }
694 }
695 }
696
697 return 0;
698}
699
700static struct pdev_entry *pdev_find(u32 devhandle, unsigned int bus, unsigned int device, unsigned int func)
701{
702 struct pdev_entry *p;
703
704 p = pdev_htab[pdev_hashfn(devhandle, bus, device, func)];
705 while (p) {
706 if (p->devhandle == devhandle &&
707 p->bus == bus &&
708 p->device == device &&
709 p->func == func)
710 break;
711
712 p = p->next;
608 } 713 }
609 714
715 return p;
716}
717
718static inline int pci_sun4v_out_of_range(struct pci_pbm_info *pbm, unsigned int bus, unsigned int device, unsigned int func)
719{
610 if (bus < pbm->pci_first_busno || 720 if (bus < pbm->pci_first_busno ||
611 bus > pbm->pci_last_busno) 721 bus > pbm->pci_last_busno)
612 return 1; 722 return 1;
613 return 0; 723 return pdev_find(pbm->devhandle, bus, device, func) == NULL;
614} 724}
615 725
616static int pci_sun4v_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn, 726static int pci_sun4v_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
@@ -1063,6 +1173,8 @@ static void pci_sun4v_pbm_init(struct pci_controller_info *p, int prom_node, u32
1063 1173
1064 pci_sun4v_get_bus_range(pbm); 1174 pci_sun4v_get_bus_range(pbm);
1065 pci_sun4v_iommu_init(pbm); 1175 pci_sun4v_iommu_init(pbm);
1176
1177 pdev_htab_populate(pbm);
1066} 1178}
1067 1179
1068void sun4v_pci_init(int node, char *model_name) 1180void sun4v_pci_init(int node, char *model_name)
diff --git a/arch/sparc64/kernel/smp.c b/arch/sparc64/kernel/smp.c
index 4e8cd79156e0..f03d52d0b88d 100644
--- a/arch/sparc64/kernel/smp.c
+++ b/arch/sparc64/kernel/smp.c
@@ -1287,6 +1287,40 @@ int setup_profiling_timer(unsigned int multiplier)
1287 return 0; 1287 return 0;
1288} 1288}
1289 1289
1290static void __init smp_tune_scheduling(void)
1291{
1292 int instance, node;
1293 unsigned int def, smallest = ~0U;
1294
1295 def = ((tlb_type == hypervisor) ?
1296 (3 * 1024 * 1024) :
1297 (4 * 1024 * 1024));
1298
1299 instance = 0;
1300 while (!cpu_find_by_instance(instance, &node, NULL)) {
1301 unsigned int val;
1302
1303 val = prom_getintdefault(node, "ecache-size", def);
1304 if (val < smallest)
1305 smallest = val;
1306
1307 instance++;
1308 }
1309
1310 /* Any value less than 256K is nonsense. */
1311 if (smallest < (256U * 1024U))
1312 smallest = 256 * 1024;
1313
1314 max_cache_size = smallest;
1315
1316 if (smallest < 1U * 1024U * 1024U)
1317 printk(KERN_INFO "Using max_cache_size of %uKB\n",
1318 smallest / 1024U);
1319 else
1320 printk(KERN_INFO "Using max_cache_size of %uMB\n",
1321 smallest / 1024U / 1024U);
1322}
1323
1290/* Constrain the number of cpus to max_cpus. */ 1324/* Constrain the number of cpus to max_cpus. */
1291void __init smp_prepare_cpus(unsigned int max_cpus) 1325void __init smp_prepare_cpus(unsigned int max_cpus)
1292{ 1326{
@@ -1322,6 +1356,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
1322 } 1356 }
1323 1357
1324 smp_store_cpu_info(boot_cpu_id); 1358 smp_store_cpu_info(boot_cpu_id);
1359 smp_tune_scheduling();
1325} 1360}
1326 1361
1327/* Set this up early so that things like the scheduler can init 1362/* Set this up early so that things like the scheduler can init
diff --git a/arch/sparc64/kernel/sparc64_ksyms.c b/arch/sparc64/kernel/sparc64_ksyms.c
index 62d8a99271ea..38e569f786dd 100644
--- a/arch/sparc64/kernel/sparc64_ksyms.c
+++ b/arch/sparc64/kernel/sparc64_ksyms.c
@@ -297,7 +297,6 @@ EXPORT_SYMBOL(svr4_getcontext);
297EXPORT_SYMBOL(svr4_setcontext); 297EXPORT_SYMBOL(svr4_setcontext);
298EXPORT_SYMBOL(compat_sys_ioctl); 298EXPORT_SYMBOL(compat_sys_ioctl);
299EXPORT_SYMBOL(sparc32_open); 299EXPORT_SYMBOL(sparc32_open);
300EXPORT_SYMBOL(sys_close);
301#endif 300#endif
302 301
303/* Special internal versions of library functions. */ 302/* Special internal versions of library functions. */
diff --git a/arch/sparc64/kernel/traps.c b/arch/sparc64/kernel/traps.c
index 2793a5d82380..563db528e031 100644
--- a/arch/sparc64/kernel/traps.c
+++ b/arch/sparc64/kernel/traps.c
@@ -1797,7 +1797,9 @@ static const char *sun4v_err_type_to_str(u32 type)
1797 }; 1797 };
1798} 1798}
1799 1799
1800static void sun4v_log_error(struct sun4v_error_entry *ent, int cpu, const char *pfx, atomic_t *ocnt) 1800extern void __show_regs(struct pt_regs * regs);
1801
1802static void sun4v_log_error(struct pt_regs *regs, struct sun4v_error_entry *ent, int cpu, const char *pfx, atomic_t *ocnt)
1801{ 1803{
1802 int cnt; 1804 int cnt;
1803 1805
@@ -1830,6 +1832,8 @@ static void sun4v_log_error(struct sun4v_error_entry *ent, int cpu, const char *
1830 pfx, 1832 pfx,
1831 ent->err_raddr, ent->err_size, ent->err_cpu); 1833 ent->err_raddr, ent->err_size, ent->err_cpu);
1832 1834
1835 __show_regs(regs);
1836
1833 if ((cnt = atomic_read(ocnt)) != 0) { 1837 if ((cnt = atomic_read(ocnt)) != 0) {
1834 atomic_set(ocnt, 0); 1838 atomic_set(ocnt, 0);
1835 wmb(); 1839 wmb();
@@ -1862,7 +1866,7 @@ void sun4v_resum_error(struct pt_regs *regs, unsigned long offset)
1862 1866
1863 put_cpu(); 1867 put_cpu();
1864 1868
1865 sun4v_log_error(&local_copy, cpu, 1869 sun4v_log_error(regs, &local_copy, cpu,
1866 KERN_ERR "RESUMABLE ERROR", 1870 KERN_ERR "RESUMABLE ERROR",
1867 &sun4v_resum_oflow_cnt); 1871 &sun4v_resum_oflow_cnt);
1868} 1872}
@@ -1910,7 +1914,7 @@ void sun4v_nonresum_error(struct pt_regs *regs, unsigned long offset)
1910 } 1914 }
1911#endif 1915#endif
1912 1916
1913 sun4v_log_error(&local_copy, cpu, 1917 sun4v_log_error(regs, &local_copy, cpu,
1914 KERN_EMERG "NON-RESUMABLE ERROR", 1918 KERN_EMERG "NON-RESUMABLE ERROR",
1915 &sun4v_nonresum_oflow_cnt); 1919 &sun4v_nonresum_oflow_cnt);
1916 1920
@@ -2200,7 +2204,6 @@ static inline struct reg_window *kernel_stack_up(struct reg_window *rw)
2200void die_if_kernel(char *str, struct pt_regs *regs) 2204void die_if_kernel(char *str, struct pt_regs *regs)
2201{ 2205{
2202 static int die_counter; 2206 static int die_counter;
2203 extern void __show_regs(struct pt_regs * regs);
2204 extern void smp_report_regs(void); 2207 extern void smp_report_regs(void);
2205 int count = 0; 2208 int count = 0;
2206 2209
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 23:14:49 -0500