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authorRalf Baechle <ralf@linux-mips.org>2005-11-15 08:55:06 -0500
committerRalf Baechle <ralf@linux-mips.org>2005-11-17 11:23:56 -0500
commit09b696efd93560609f25821208dae18027187425 (patch)
tree54618abf054e5a94e530f9bfe8ea53e6cf929334 /arch
parent561a0792405bea8ead78990d755dd1f95b8e95b8 (diff)
[MIPS] TX3927: Try to glue the PCI code.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/pci/ops-tx3927.c114
1 files changed, 43 insertions, 71 deletions
diff --git a/arch/mips/pci/ops-tx3927.c b/arch/mips/pci/ops-tx3927.c
index 0e0daadc303d..42530a0b84b3 100644
--- a/arch/mips/pci/ops-tx3927.c
+++ b/arch/mips/pci/ops-tx3927.c
@@ -72,13 +72,9 @@ static inline int check_abort(void)
72static int jmr3927_pci_read_config(struct pci_bus *bus, unsigned int devfn, 72static int jmr3927_pci_read_config(struct pci_bus *bus, unsigned int devfn,
73 int where, int size, u32 * val) 73 int where, int size, u32 * val)
74{ 74{
75 int ret, busno; 75 int ret;
76 76
77 /* check if the bus is top-level */ 77 ret = mkaddr(bus->number, devfn, where);
78 if (bus->parent != NULL)
79 busno = bus->number;
80
81 ret = mkaddr(busno, devfn, where);
82 if (ret) 78 if (ret)
83 return ret; 79 return ret;
84 80
@@ -102,15 +98,9 @@ static int jmr3927_pci_read_config(struct pci_bus *bus, unsigned int devfn,
102static int jmr3927_pci_write_config(struct pci_bus *bus, unsigned int devfn, 98static int jmr3927_pci_write_config(struct pci_bus *bus, unsigned int devfn,
103 int where, int size, u32 val) 99 int where, int size, u32 val)
104{ 100{
105 int ret, busno; 101 int ret;
106
107 /* check if the bus is top-level */
108 if (bus->parent != NULL)
109 bus = bus->number;
110 else
111 bus = 0;
112 102
113 ret = mkaddr(busno, devfn, where); 103 ret = mkaddr(bus->number, devfn, where);
114 if (ret) 104 if (ret)
115 return ret; 105 return ret;
116 106
@@ -120,7 +110,7 @@ static int jmr3927_pci_write_config(struct pci_bus *bus, unsigned int devfn,
120 break; 110 break;
121 111
122 case 2: 112 case 2:
123 *(volatile u16 *) (unsigned longulong) & tx3927_pcicptr->icd | (where & 2)) = 113 *(volatile u16 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 2)) =
124 cpu_to_le16(val); 114 cpu_to_le16(val);
125 break; 115 break;
126 116
@@ -137,8 +127,8 @@ static int jmr3927_pci_write_config(struct pci_bus *bus, unsigned int devfn,
137} 127}
138 128
139struct pci_ops jmr3927_pci_ops = { 129struct pci_ops jmr3927_pci_ops = {
140 jmr3927_pcibios_read_config, 130 jmr3927_pci_read_config,
141 jmr3927_pcibios_write_config, 131 jmr3927_pci_write_config,
142}; 132};
143 133
144 134
@@ -159,15 +149,14 @@ unsigned long tc_readl(volatile __u32 * addr)
159{ 149{
160 unsigned long val; 150 unsigned long val;
161 151
162 addr = PHYSADDR(addr); 152 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
163 *(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr = 153 (unsigned long) CPHYSADDR(addr);
164 (unsigned long) addr; 154 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
165 *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe =
166 (PCI_IPCIBE_ICMD_MEMREAD << PCI_IPCIBE_ICMD_SHIFT) | 155 (PCI_IPCIBE_ICMD_MEMREAD << PCI_IPCIBE_ICMD_SHIFT) |
167 PCI_IPCIBE_IBE_LONG; 156 PCI_IPCIBE_IBE_LONG;
168 while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)); 157 while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
169 val = 158 val =
170 le32_to_cpu(*(volatile u32 *) (ulong) & tx3927_pcicptr-> 159 le32_to_cpu(*(volatile u32 *) (unsigned long) & tx3927_pcicptr->
171 ipcidata); 160 ipcidata);
172 /* clear by setting */ 161 /* clear by setting */
173 tx3927_pcicptr->istat |= PCI_ISTAT_IDICC; 162 tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
@@ -176,12 +165,11 @@ unsigned long tc_readl(volatile __u32 * addr)
176 165
177void tc_writel(unsigned long data, volatile __u32 * addr) 166void tc_writel(unsigned long data, volatile __u32 * addr)
178{ 167{
179 addr = PHYSADDR(addr); 168 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcidata =
180 *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcidata =
181 cpu_to_le32(data); 169 cpu_to_le32(data);
182 *(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr = 170 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
183 (unsigned long) addr; 171 (unsigned long) CPHYSADDR(addr);
184 *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe = 172 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
185 (PCI_IPCIBE_ICMD_MEMWRITE << PCI_IPCIBE_ICMD_SHIFT) | 173 (PCI_IPCIBE_ICMD_MEMWRITE << PCI_IPCIBE_ICMD_SHIFT) |
186 PCI_IPCIBE_IBE_LONG; 174 PCI_IPCIBE_IBE_LONG;
187 while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)); 175 while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
@@ -198,21 +186,15 @@ unsigned char tx_ioinb(unsigned char *addr)
198 186
199 ioaddr = (unsigned long) addr; 187 ioaddr = (unsigned long) addr;
200 offset = ioaddr & 0x3; 188 offset = ioaddr & 0x3;
201 if (offset == 0) 189 byte = 0xf & ~(8 >> offset);
202 byte = 0x7; 190
203 else if (offset == 1) 191 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
204 byte = 0xb;
205 else if (offset == 2)
206 byte = 0xd;
207 else if (offset == 3)
208 byte = 0xe;
209 *(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr =
210 (unsigned long) ioaddr; 192 (unsigned long) ioaddr;
211 *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe = 193 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
212 (PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | byte; 194 (PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | byte;
213 while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)); 195 while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
214 val = 196 val =
215 le32_to_cpu(*(volatile u32 *) (ulong) & tx3927_pcicptr-> 197 le32_to_cpu(*(volatile u32 *) (unsigned long) & tx3927_pcicptr->
216 ipcidata); 198 ipcidata);
217 val = val & 0xff; 199 val = val & 0xff;
218 /* clear by setting */ 200 /* clear by setting */
@@ -229,18 +211,12 @@ void tx_iooutb(unsigned long data, unsigned char *addr)
229 data = data | (data << 8) | (data << 16) | (data << 24); 211 data = data | (data << 8) | (data << 16) | (data << 24);
230 ioaddr = (unsigned long) addr; 212 ioaddr = (unsigned long) addr;
231 offset = ioaddr & 0x3; 213 offset = ioaddr & 0x3;
232 if (offset == 0) 214 byte = 0xf & ~(8 >> offset);
233 byte = 0x7; 215
234 else if (offset == 1) 216 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcidata = data;
235 byte = 0xb; 217 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
236 else if (offset == 2)
237 byte = 0xd;
238 else if (offset == 3)
239 byte = 0xe;
240 *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcidata = data;
241 *(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr =
242 (unsigned long) ioaddr; 218 (unsigned long) ioaddr;
243 *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe = 219 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
244 (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) | byte; 220 (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) | byte;
245 while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)); 221 while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
246 /* clear by setting */ 222 /* clear by setting */
@@ -255,18 +231,16 @@ unsigned short tx_ioinw(unsigned short *addr)
255 int byte; 231 int byte;
256 232
257 ioaddr = (unsigned long) addr; 233 ioaddr = (unsigned long) addr;
258 offset = ioaddr & 0x3; 234 offset = ioaddr & 0x2;
259 if (offset == 0) 235 byte = 3 << offset;
260 byte = 0x3; 236
261 else if (offset == 2) 237 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
262 byte = 0xc;
263 *(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr =
264 (unsigned long) ioaddr; 238 (unsigned long) ioaddr;
265 *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe = 239 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
266 (PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | byte; 240 (PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | byte;
267 while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)); 241 while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
268 val = 242 val =
269 le32_to_cpu(*(volatile u32 *) (ulong) & tx3927_pcicptr-> 243 le32_to_cpu(*(volatile u32 *) (unsigned long) & tx3927_pcicptr->
270 ipcidata); 244 ipcidata);
271 val = val & 0xffff; 245 val = val & 0xffff;
272 /* clear by setting */ 246 /* clear by setting */
@@ -283,15 +257,13 @@ void tx_iooutw(unsigned long data, unsigned short *addr)
283 257
284 data = data | (data << 16); 258 data = data | (data << 16);
285 ioaddr = (unsigned long) addr; 259 ioaddr = (unsigned long) addr;
286 offset = ioaddr & 0x3; 260 offset = ioaddr & 0x2;
287 if (offset == 0) 261 byte = 3 << offset;
288 byte = 0x3; 262
289 else if (offset == 2) 263 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcidata = data;
290 byte = 0xc; 264 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
291 *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcidata = data;
292 *(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr =
293 (unsigned long) ioaddr; 265 (unsigned long) ioaddr;
294 *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe = 266 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
295 (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) | byte; 267 (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) | byte;
296 while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)); 268 while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
297 /* clear by setting */ 269 /* clear by setting */
@@ -304,14 +276,14 @@ unsigned long tx_ioinl(unsigned int *addr)
304 __u32 ioaddr; 276 __u32 ioaddr;
305 277
306 ioaddr = (unsigned long) addr; 278 ioaddr = (unsigned long) addr;
307 *(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr = 279 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
308 (unsigned long) ioaddr; 280 (unsigned long) ioaddr;
309 *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe = 281 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
310 (PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | 282 (PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) |
311 PCI_IPCIBE_IBE_LONG; 283 PCI_IPCIBE_IBE_LONG;
312 while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)); 284 while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
313 val = 285 val =
314 le32_to_cpu(*(volatile u32 *) (ulong) & tx3927_pcicptr-> 286 le32_to_cpu(*(volatile u32 *) (unsigned long) & tx3927_pcicptr->
315 ipcidata); 287 ipcidata);
316 /* clear by setting */ 288 /* clear by setting */
317 tx3927_pcicptr->istat |= PCI_ISTAT_IDICC; 289 tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
@@ -323,11 +295,11 @@ void tx_iooutl(unsigned long data, unsigned int *addr)
323 __u32 ioaddr; 295 __u32 ioaddr;
324 296
325 ioaddr = (unsigned long) addr; 297 ioaddr = (unsigned long) addr;
326 *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcidata = 298 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcidata =
327 cpu_to_le32(data); 299 cpu_to_le32(data);
328 *(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr = 300 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
329 (unsigned long) ioaddr; 301 (unsigned long) ioaddr;
330 *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe = 302 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
331 (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) | 303 (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) |
332 PCI_IPCIBE_IBE_LONG; 304 PCI_IPCIBE_IBE_LONG;
333 while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)); 305 while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));