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authorStuart Brady <sdb@parisc-linux.org>2005-10-21 22:44:14 -0400
committerKyle McMartin <kyle@parisc-linux.org>2005-10-21 22:44:14 -0400
commit2464212f68136527f6364d63c23a529e1fd7d168 (patch)
tree5a7a9b56570be465c87047a28d38aadf1357e698 /arch
parentf053725b8985d10c2cc4b837a80a381104c936a4 (diff)
[PARISC] Fix parisc_setup_cache_timing to choose a better flush threshold
update comment about CAFL_STRIDE Signed-off-by: Kyle McMartin <kyle@parisc-linux.org> Fixed a bug in parisc_setup_cache_timing() which caused it to calculate a poor value for parisc_cache_flush_threshold. Thanks to Joel Soete for spotting the bug. Thanks to James Bottomley for pointing out the clean way to fix this. Signed-off-by: Stuart Brady <sdb@parisc-linux.org> Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/parisc/kernel/cache.c10
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/parisc/kernel/cache.c b/arch/parisc/kernel/cache.c
index f46a07a79218..e15f09eaed12 100644
--- a/arch/parisc/kernel/cache.c
+++ b/arch/parisc/kernel/cache.c
@@ -27,6 +27,7 @@
27#include <asm/page.h> 27#include <asm/page.h>
28#include <asm/pgalloc.h> 28#include <asm/pgalloc.h>
29#include <asm/processor.h> 29#include <asm/processor.h>
30#include <asm/sections.h>
30 31
31int split_tlb; 32int split_tlb;
32int dcache_stride; 33int dcache_stride;
@@ -207,6 +208,9 @@ parisc_cache_init(void)
207 208
208 /* "New and Improved" version from Jim Hull 209 /* "New and Improved" version from Jim Hull
209 * (1 << (cc_block-1)) * (cc_line << (4 + cnf.cc_shift)) 210 * (1 << (cc_block-1)) * (cc_line << (4 + cnf.cc_shift))
211 * The following CAFL_STRIDE is an optimized version, see
212 * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023625.html
213 * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023671.html
210 */ 214 */
211#define CAFL_STRIDE(cnf) (cnf.cc_line << (3 + cnf.cc_block + cnf.cc_shift)) 215#define CAFL_STRIDE(cnf) (cnf.cc_line << (3 + cnf.cc_block + cnf.cc_shift))
212 dcache_stride = CAFL_STRIDE(cache_info.dc_conf); 216 dcache_stride = CAFL_STRIDE(cache_info.dc_conf);
@@ -339,17 +343,15 @@ int parisc_cache_flush_threshold = FLUSH_THRESHOLD;
339void parisc_setup_cache_timing(void) 343void parisc_setup_cache_timing(void)
340{ 344{
341 unsigned long rangetime, alltime; 345 unsigned long rangetime, alltime;
342 extern char _text; /* start of kernel code, defined by linker */
343 extern char _end; /* end of BSS, defined by linker */
344 unsigned long size; 346 unsigned long size;
345 347
346 alltime = mfctl(16); 348 alltime = mfctl(16);
347 flush_data_cache(); 349 flush_data_cache();
348 alltime = mfctl(16) - alltime; 350 alltime = mfctl(16) - alltime;
349 351
350 size = (unsigned long)(&_end - _text); 352 size = (unsigned long)(_end - _text);
351 rangetime = mfctl(16); 353 rangetime = mfctl(16);
352 flush_kernel_dcache_range((unsigned long)&_text, size); 354 flush_kernel_dcache_range((unsigned long)_text, size);
353 rangetime = mfctl(16) - rangetime; 355 rangetime = mfctl(16) - rangetime;
354 356
355 printk(KERN_DEBUG "Whole cache flush %lu cycles, flushing %lu bytes %lu cycles\n", 357 printk(KERN_DEBUG "Whole cache flush %lu cycles, flushing %lu bytes %lu cycles\n",