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authorHirokazu Takata <takata@linux-m32r.org>2007-08-17 05:11:37 -0400
committerHirokazu Takata <takata@linux-m32r.org>2007-09-02 22:30:18 -0400
commit5171b100511513bc52875055f7d900fc3f7c922b (patch)
treeba8eace198bd5b4fb695c145b21c2da4999a445b /arch
parente070fb743d9d13d9757e633d1bdd1f9c20b2d792 (diff)
m32r: Simplify ei_handler code
Simplify and clean up messy ei_handler code in arch/m32r/kernel/entry.S. - Remove ifdef's for CONFIG_CHIP_* configulations. - Rearrange the M32700 workaround code. - Remove the messy platform-dependent interrupt check routines and consolidate them to common INT0/INT1/INT2 check routines for all platforms with cascaded interrupt controllers. Signed-off-by: Hitoshi Yamamoto <hitoshiy@linux-m32r.org> Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/m32r/kernel/entry.S241
1 files changed, 39 insertions, 202 deletions
diff --git a/arch/m32r/kernel/entry.S b/arch/m32r/kernel/entry.S
index a2c472c0549f..07d95a4f51a2 100644
--- a/arch/m32r/kernel/entry.S
+++ b/arch/m32r/kernel/entry.S
@@ -290,16 +290,12 @@ syscall_badsys:
290 */ 290 */
291ENTRY(ei_handler) 291ENTRY(ei_handler)
292#if defined(CONFIG_CHIP_M32700) 292#if defined(CONFIG_CHIP_M32700)
293 SWITCH_TO_KERNEL_STACK
294 ; WORKAROUND: force to clear SM bit and use the kernel stack (SPI). 293 ; WORKAROUND: force to clear SM bit and use the kernel stack (SPI).
294 SWITCH_TO_KERNEL_STACK
295#endif 295#endif
296 SAVE_ALL 296 SAVE_ALL
297 mv r1, sp ; arg1(regs) 297 mv r1, sp ; arg1(regs)
298#if defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_XNUX2) \ 298 ; GET_ICU_STATUS;
299 || defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \
300 || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104)
301
302; GET_ICU_STATUS;
303 seth r0, #shigh(M32R_ICU_ISTS_ADDR) 299 seth r0, #shigh(M32R_ICU_ISTS_ADDR)
304 ld r0, @(low(M32R_ICU_ISTS_ADDR),r0) 300 ld r0, @(low(M32R_ICU_ISTS_ADDR),r0)
305 push r0 301 push r0
@@ -314,10 +310,15 @@ ENTRY(ei_handler)
314 ;; IRQ exist check 310 ;; IRQ exist check
315#if defined(CONFIG_CHIP_M32700) 311#if defined(CONFIG_CHIP_M32700)
316 /* WORKAROUND: IMASK bug M32700-TS1, TS2 chip. */ 312 /* WORKAROUND: IMASK bug M32700-TS1, TS2 chip. */
317 beqz r0, 3f ; if (!irq_num) goto exit 313 bnez r0, 0f
318#else 314 ld24 r14, #0x00070000
315 seth r0, #shigh(M32R_ICU_IMASK_ADDR)
316 st r14, @(low(M32R_ICU_IMASK_ADDR),r0)
317 bra 1f
318 .fillinsn
3190:
320#endif /* CONFIG_CHIP_M32700 */
319 beqz r0, 1f ; if (!irq_num) goto exit 321 beqz r0, 1f ; if (!irq_num) goto exit
320#endif /* WORKAROUND */
321 ;; IPI check 322 ;; IPI check
322 cmpi r0, #(M32R_IRQ_IPI0<<2) ; ISN < IPI0 check 323 cmpi r0, #(M32R_IRQ_IPI0<<2) ; ISN < IPI0 check
323 bc 2f 324 bc 2f
@@ -333,218 +334,54 @@ ENTRY(ei_handler)
3331: 3341:
334 addi sp, #4 335 addi sp, #4
335 bra ret_to_intr 336 bra ret_to_intr
336#if defined(CONFIG_CHIP_M32700)
337 /* WORKAROUND: IMASK bug M32700-TS1, TS2 chip. */
338 .fillinsn
3393:
340 ld24 r14, #0x00070000
341 seth r0, #shigh(M32R_ICU_IMASK_ADDR)
342 st r14, @(low(M32R_ICU_IMASK_ADDR), r0)
343 addi sp, #4
344 bra ret_to_intr
345#endif /* WORKAROUND */
346 ;; do_IRQ
347 .fillinsn 337 .fillinsn
3482: 3382:
349 srli r0, #2 339 srli r0, #2
350#if defined(CONFIG_PLAT_USRV) 340#else /* not CONFIG_SMP */
351 add3 r2, r0, #-(M32R_IRQ_INT1) ; INT1# interrupt
352 bnez r2, 9f
353 ; read ICU status register of PLD
354 seth r0, #high(PLD_ICUISTS)
355 or3 r0, r0, #low(PLD_ICUISTS)
356 lduh r0, @r0
357 slli r0, #21
358 srli r0, #27 ; ISN
359 addi r0, #(M32700UT_PLD_IRQ_BASE)
360 .fillinsn
3619:
362#elif defined(CONFIG_PLAT_M32700UT)
363 add3 r2, r0, #-(M32R_IRQ_INT1) ; INT1# interrupt
364 bnez r2, check_int0
365 ; read ICU status register of PLD
366 seth r0, #high(PLD_ICUISTS)
367 or3 r0, r0, #low(PLD_ICUISTS)
368 lduh r0, @r0
369 slli r0, #21
370 srli r0, #27 ; ISN
371 addi r0, #(M32700UT_PLD_IRQ_BASE)
372 bra check_end
373 .fillinsn
374check_int0:
375 add3 r2, r0, #-(M32R_IRQ_INT0) ; INT0# interrupt
376 bnez r2, check_int2
377 ; read ICU status of LAN-board
378 seth r0, #high(M32700UT_LAN_ICUISTS)
379 or3 r0, r0, #low(M32700UT_LAN_ICUISTS)
380 lduh r0, @r0
381 slli r0, #21
382 srli r0, #27 ; ISN
383 add3 r0, r0, #(M32700UT_LAN_PLD_IRQ_BASE)
384 bra check_end
385 .fillinsn
386check_int2:
387 add3 r2, r0, #-(M32R_IRQ_INT2) ; INT2# interrupt
388 bnez r2, check_end
389 ; read ICU status of LCD-board
390 seth r0, #high(M32700UT_LCD_ICUISTS)
391 or3 r0, r0, #low(M32700UT_LCD_ICUISTS)
392 lduh r0, @r0
393 slli r0, #21
394 srli r0, #27 ; ISN
395 add3 r0, r0, #(M32700UT_LCD_PLD_IRQ_BASE)
396 bra check_end
397 .fillinsn
398check_end:
399#elif defined(CONFIG_PLAT_OPSPUT)
400 add3 r2, r0, #-(M32R_IRQ_INT1) ; INT1# interrupt
401 bnez r2, check_int0
402 ; read ICU status register of PLD
403 seth r0, #high(PLD_ICUISTS)
404 or3 r0, r0, #low(PLD_ICUISTS)
405 lduh r0, @r0
406 slli r0, #21
407 srli r0, #27 ; ISN
408 addi r0, #(OPSPUT_PLD_IRQ_BASE)
409 bra check_end
410 .fillinsn
411check_int0:
412 add3 r2, r0, #-(M32R_IRQ_INT0) ; INT0# interrupt
413 bnez r2, check_int2
414 ; read ICU status of LAN-board
415 seth r0, #high(OPSPUT_LAN_ICUISTS)
416 or3 r0, r0, #low(OPSPUT_LAN_ICUISTS)
417 lduh r0, @r0
418 slli r0, #21
419 srli r0, #27 ; ISN
420 add3 r0, r0, #(OPSPUT_LAN_PLD_IRQ_BASE)
421 bra check_end
422 .fillinsn
423check_int2:
424 add3 r2, r0, #-(M32R_IRQ_INT2) ; INT2# interrupt
425 bnez r2, check_end
426 ; read ICU status of LCD-board
427 seth r0, #high(OPSPUT_LCD_ICUISTS)
428 or3 r0, r0, #low(OPSPUT_LCD_ICUISTS)
429 lduh r0, @r0
430 slli r0, #21
431 srli r0, #27 ; ISN
432 add3 r0, r0, #(OPSPUT_LCD_PLD_IRQ_BASE)
433 bra check_end
434 .fillinsn
435check_end:
436#endif /* CONFIG_PLAT_OPSPUT */
437 bl do_IRQ ; r0(irq), r1(regs)
438#else /* not CONFIG_SMP */
439 srli r0, #22 ; r0(irq) 341 srli r0, #22 ; r0(irq)
440#if defined(CONFIG_PLAT_USRV) 342#endif /* not CONFIG_SMP */
343
344#if defined(CONFIG_PLAT_HAS_INT1ICU)
441 add3 r2, r0, #-(M32R_IRQ_INT1) ; INT1# interrupt 345 add3 r2, r0, #-(M32R_IRQ_INT1) ; INT1# interrupt
442 bnez r2, 1f 346 bnez r2, 3f
443 ; read ICU status register of PLD 347 seth r0, #shigh(M32R_INT1ICU_ISTS)
444 seth r0, #high(PLD_ICUISTS) 348 lduh r0, @(low(M32R_INT1ICU_ISTS),r0) ; bit10-6 : ISN
445 or3 r0, r0, #low(PLD_ICUISTS)
446 lduh r0, @r0
447 slli r0, #21 349 slli r0, #21
448 srli r0, #27 ; ISN 350 srli r0, #27 ; ISN
449 addi r0, #(M32700UT_PLD_IRQ_BASE) 351 addi r0, #(M32R_INT1ICU_IRQ_BASE)
450 .fillinsn
4511:
452#elif defined(CONFIG_PLAT_M32700UT)
453 add3 r2, r0, #-(M32R_IRQ_INT1) ; INT1# interrupt
454 bnez r2, check_int0
455 ; read ICU status register of PLD
456 seth r0, #high(PLD_ICUISTS)
457 or3 r0, r0, #low(PLD_ICUISTS)
458 lduh r0, @r0
459 slli r0, #21
460 srli r0, #27 ; ISN
461 addi r0, #(M32700UT_PLD_IRQ_BASE)
462 bra check_end 352 bra check_end
463 .fillinsn 353 .fillinsn
464check_int0: 3543:
465 add3 r2, r0, #-(M32R_IRQ_INT0) ; INT0# interrupt 355#endif /* CONFIG_PLAT_HAS_INT1ICU */
466 bnez r2, check_int2 356#if defined(CONFIG_PLAT_HAS_INT0ICU)
467 ; read ICU status of LAN-board 357 add3 r2, r0, #-(M32R_IRQ_INT0) ; INT0# interrupt
468 seth r0, #high(M32700UT_LAN_ICUISTS) 358 bnez r2, 4f
469 or3 r0, r0, #low(M32700UT_LAN_ICUISTS) 359 seth r0, #shigh(M32R_INT0ICU_ISTS)
470 lduh r0, @r0 360 lduh r0, @(low(M32R_INT0ICU_ISTS),r0) ; bit10-6 : ISN
471 slli r0, #21
472 srli r0, #27 ; ISN
473 add3 r0, r0, #(M32700UT_LAN_PLD_IRQ_BASE)
474 bra check_end
475 .fillinsn
476check_int2:
477 add3 r2, r0, #-(M32R_IRQ_INT2) ; INT2# interrupt
478 bnez r2, check_end
479 ; read ICU status of LCD-board
480 seth r0, #high(M32700UT_LCD_ICUISTS)
481 or3 r0, r0, #low(M32700UT_LCD_ICUISTS)
482 lduh r0, @r0
483 slli r0, #21
484 srli r0, #27 ; ISN
485 add3 r0, r0, #(M32700UT_LCD_PLD_IRQ_BASE)
486 bra check_end
487 .fillinsn
488check_end:
489#elif defined(CONFIG_PLAT_OPSPUT)
490 add3 r2, r0, #-(M32R_IRQ_INT1) ; INT1# interrupt
491 bnez r2, check_int0
492 ; read ICU status register of PLD
493 seth r0, #high(PLD_ICUISTS)
494 or3 r0, r0, #low(PLD_ICUISTS)
495 lduh r0, @r0
496 slli r0, #21
497 srli r0, #27 ; ISN
498 addi r0, #(OPSPUT_PLD_IRQ_BASE)
499 bra check_end
500 .fillinsn
501check_int0:
502 add3 r2, r0, #-(M32R_IRQ_INT0) ; INT0# interrupt
503 bnez r2, check_int2
504 ; read ICU status of LAN-board
505 seth r0, #high(OPSPUT_LAN_ICUISTS)
506 or3 r0, r0, #low(OPSPUT_LAN_ICUISTS)
507 lduh r0, @r0
508 slli r0, #21
509 srli r0, #27 ; ISN
510 add3 r0, r0, #(OPSPUT_LAN_PLD_IRQ_BASE)
511 bra check_end
512 .fillinsn
513check_int2:
514 add3 r2, r0, #-(M32R_IRQ_INT2) ; INT2# interrupt
515 bnez r2, check_end
516 ; read ICU status of LCD-board
517 seth r0, #high(OPSPUT_LCD_ICUISTS)
518 or3 r0, r0, #low(OPSPUT_LCD_ICUISTS)
519 lduh r0, @r0
520 slli r0, #21 361 slli r0, #21
521 srli r0, #27 ; ISN 362 srli r0, #27 ; ISN
522 add3 r0, r0, #(OPSPUT_LCD_PLD_IRQ_BASE) 363 addi r0, #(M32R_INT0ICU_IRQ_BASE)
523 bra check_end 364 bra check_end
524 .fillinsn 365 .fillinsn
525check_end: 3664:
526#elif defined(CONFIG_PLAT_M32104UT) 367#endif /* CONFIG_PLAT_HAS_INT0ICU */
527 add3 r2, r0, #-(M32R_IRQ_INT1) ; INT1# interrupt 368#if defined(CONFIG_PLAT_HAS_INT2ICU)
528 bnez r2, check_end 369 add3 r2, r0, #-(M32R_IRQ_INT2) ; INT2# interrupt
529 ; read ICU status register of PLD 370 bnez r2, 5f
530 seth r0, #high(PLD_ICUISTS) 371 seth r0, #shigh(M32R_INT2ICU_ISTS)
531 or3 r0, r0, #low(PLD_ICUISTS) 372 lduh r0, @(low(M32R_INT2ICU_ISTS),r0) ; bit10-6 : ISN
532 lduh r0, @r0
533 slli r0, #21 373 slli r0, #21
534 srli r0, #27 ; ISN 374 srli r0, #27 ; ISN
535 addi r0, #(M32104UT_PLD_IRQ_BASE) 375 addi r0, #(M32R_INT2ICU_IRQ_BASE)
536 bra check_end 376 ; bra check_end
537 .fillinsn 377 .fillinsn
3785:
379#endif /* CONFIG_PLAT_HAS_INT2ICU */
538check_end: 380check_end:
539#endif /* CONFIG_PLAT_M32104UT */
540 bl do_IRQ 381 bl do_IRQ
541#endif /* CONFIG_SMP */
542 pop r14 382 pop r14
543 seth r0, #shigh(M32R_ICU_IMASK_ADDR) 383 seth r0, #shigh(M32R_ICU_IMASK_ADDR)
544 st r14, @(low(M32R_ICU_IMASK_ADDR),r0) 384 st r14, @(low(M32R_ICU_IMASK_ADDR),r0)
545#else
546#error no chip configuration
547#endif
548ret_to_intr: 385ret_to_intr:
549 bra ret_from_intr 386 bra ret_from_intr
550 387
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