diff options
author | Chris Dearman <chris@mips.com> | 2007-02-01 14:54:13 -0500 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2007-02-06 11:53:23 -0500 |
commit | 6d6671066a311703bca1b91645bb1e04cc983387 (patch) | |
tree | e28189728ddb9c5364c259a09bee6966a060b21c /arch | |
parent | b86b30f81c7601d9a410d2ce0c64d9ba50d673ae (diff) |
[MIPS] Check FCSR for pending interrupts before restoring from a context.
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/mips/kernel/r4k_fpu.S | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S index 880fa6e841ee..8b5ccfa99dd1 100644 --- a/arch/mips/kernel/r4k_fpu.S +++ b/arch/mips/kernel/r4k_fpu.S | |||
@@ -114,6 +114,14 @@ LEAF(_save_fp_context32) | |||
114 | */ | 114 | */ |
115 | LEAF(_restore_fp_context) | 115 | LEAF(_restore_fp_context) |
116 | EX lw t0, SC_FPC_CSR(a0) | 116 | EX lw t0, SC_FPC_CSR(a0) |
117 | |||
118 | /* Fail if the CSR has exceptions pending */ | ||
119 | srl t1, t0, 5 | ||
120 | and t1, t0 | ||
121 | andi t1, 0x1f << 7 | ||
122 | bnez t1, fault | ||
123 | nop | ||
124 | |||
117 | #ifdef CONFIG_64BIT | 125 | #ifdef CONFIG_64BIT |
118 | EX ldc1 $f1, SC_FPREGS+8(a0) | 126 | EX ldc1 $f1, SC_FPREGS+8(a0) |
119 | EX ldc1 $f3, SC_FPREGS+24(a0) | 127 | EX ldc1 $f3, SC_FPREGS+24(a0) |
@@ -157,6 +165,14 @@ LEAF(_restore_fp_context) | |||
157 | LEAF(_restore_fp_context32) | 165 | LEAF(_restore_fp_context32) |
158 | /* Restore an o32 sigcontext. */ | 166 | /* Restore an o32 sigcontext. */ |
159 | EX lw t0, SC32_FPC_CSR(a0) | 167 | EX lw t0, SC32_FPC_CSR(a0) |
168 | |||
169 | /* Fail if the CSR has exceptions pending */ | ||
170 | srl t1, t0, 5 | ||
171 | and t1, t0 | ||
172 | andi t1, 0x1f << 7 | ||
173 | bnez t1, fault | ||
174 | nop | ||
175 | |||
160 | EX ldc1 $f0, SC32_FPREGS+0(a0) | 176 | EX ldc1 $f0, SC32_FPREGS+0(a0) |
161 | EX ldc1 $f2, SC32_FPREGS+16(a0) | 177 | EX ldc1 $f2, SC32_FPREGS+16(a0) |
162 | EX ldc1 $f4, SC32_FPREGS+32(a0) | 178 | EX ldc1 $f4, SC32_FPREGS+32(a0) |