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authorTony Lindgren <tony@atomide.com>2010-12-21 19:53:00 -0500
committerTony Lindgren <tony@atomide.com>2010-12-21 19:53:00 -0500
commitbb3613aa34a81a5e2f1227ccdb801fde04a7da10 (patch)
treebb79c15d5da41113bd7b83d9e74fbfc4a1bf8569 /arch
parent6971071cdda79cad5f53ba390e466d696e7e9006 (diff)
parentbb1c9034b3ce7f29d3d178a87b42b767611d6574 (diff)
Merge branch 'pm-next' of ssh://master.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm into omap-for-linus
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-at91/Makefile2
-rw-r--r--arch/arm/mach-at91/board-pcontrol-g20.c98
-rw-r--r--arch/arm/mach-at91/board-stamp9g20.c82
-rw-r--r--arch/arm/mach-at91/clock.c2
-rw-r--r--arch/arm/mach-at91/include/mach/stamp9g20.h7
-rw-r--r--arch/arm/mach-omap2/control.c22
-rw-r--r--arch/arm/mach-omap2/control.h9
-rw-r--r--arch/arm/mach-omap2/cpuidle34xx.c36
-rw-r--r--arch/arm/mach-omap2/pm.c2
-rw-r--r--arch/arm/mach-omap2/pm.h15
-rw-r--r--arch/arm/mach-omap2/pm24xx.c16
-rw-r--r--arch/arm/mach-omap2/pm34xx.c66
-rw-r--r--arch/arm/mach-omap2/pm44xx.c16
-rw-r--r--arch/arm/mach-omap2/sdrc.h1
-rw-r--r--arch/arm/mach-omap2/sleep34xx.S832
-rw-r--r--arch/arm/mach-s3c2412/Kconfig7
-rw-r--r--arch/arm/mach-s3c2412/Makefile3
-rw-r--r--arch/arm/mach-s3c2416/Kconfig1
-rw-r--r--arch/arm/mach-s5pv210/mach-aquila.c6
-rw-r--r--arch/arm/mach-s5pv210/mach-goni.c6
-rw-r--r--arch/arm/mach-shmobile/include/mach/entry-macro.S30
-rw-r--r--arch/arm/mach-shmobile/include/mach/vmalloc.h2
-rw-r--r--arch/arm/plat-omap/include/plat/sram.h11
-rw-r--r--arch/arm/plat-omap/sram.c7
-rw-r--r--arch/arm/plat-s3c24xx/Kconfig2
-rw-r--r--arch/mips/Kconfig38
-rw-r--r--arch/mips/alchemy/common/platform.c2
-rw-r--r--arch/mips/alchemy/devboards/prom.c5
-rw-r--r--arch/mips/ar7/clock.c9
-rw-r--r--arch/mips/ar7/time.c3
-rw-r--r--arch/mips/bcm47xx/setup.c153
-rw-r--r--arch/mips/include/asm/cpu.h4
-rw-r--r--arch/mips/include/asm/elf.h8
-rw-r--r--arch/mips/include/asm/io.h12
-rw-r--r--arch/mips/include/asm/mach-ar7/ar7.h3
-rw-r--r--arch/mips/include/asm/mach-bcm47xx/nvram.h7
-rw-r--r--arch/mips/jz4740/board-qi_lb60.c4
-rw-r--r--arch/mips/jz4740/platform.c2
-rw-r--r--arch/mips/jz4740/prom.c2
-rw-r--r--arch/mips/kernel/cevt-r4k.c2
-rw-r--r--arch/mips/kernel/cpu-probe.c7
-rw-r--r--arch/mips/kernel/linux32.c13
-rw-r--r--arch/mips/kernel/process.c1
-rw-r--r--arch/mips/kernel/prom.c2
-rw-r--r--arch/mips/kernel/smp-mt.c2
-rw-r--r--arch/mips/kernel/traps.c44
-rw-r--r--arch/mips/kernel/vpe.c14
-rw-r--r--arch/mips/lib/memset.S4
-rw-r--r--arch/mips/loongson/common/env.c4
-rw-r--r--arch/mips/math-emu/cp1emu.c116
-rw-r--r--arch/mips/mm/dma-default.c4
-rw-r--r--arch/mips/mm/sc-mips.c4
-rw-r--r--arch/mips/pmc-sierra/yosemite/py-console.c12
-rw-r--r--arch/mips/sibyte/swarm/setup.c8
-rw-r--r--arch/mn10300/kernel/time.c10
-rw-r--r--arch/tile/include/asm/signal.h2
-rw-r--r--arch/tile/kernel/compat_signal.c6
-rw-r--r--arch/tile/kernel/intvec_32.S24
-rw-r--r--arch/tile/kernel/process.c8
-rw-r--r--arch/tile/kernel/signal.c10
-rw-r--r--arch/x86/boot/compressed/misc.c2
-rw-r--r--arch/x86/include/asm/e820.h3
-rw-r--r--arch/x86/include/asm/kvm_host.h2
-rw-r--r--arch/x86/kernel/Makefile1
-rw-r--r--arch/x86/kernel/apic/apic.c8
-rw-r--r--arch/x86/kernel/apic/io_apic.c4
-rw-r--r--arch/x86/kernel/apic/probe_64.c7
-rw-r--r--arch/x86/kernel/head_32.S16
-rw-r--r--arch/x86/kernel/hpet.c26
-rw-r--r--arch/x86/kernel/resource.c48
-rw-r--r--arch/x86/kernel/setup.c1
-rw-r--r--arch/x86/kernel/xsave.c3
-rw-r--r--arch/x86/kvm/svm.c4
-rw-r--r--arch/x86/kvm/vmx.c5
-rw-r--r--arch/x86/kvm/x86.c11
-rw-r--r--arch/x86/kvm/x86.h5
-rw-r--r--arch/x86/lguest/boot.c16
-rw-r--r--arch/x86/lguest/i386_head.S105
-rw-r--r--arch/x86/pci/i386.c18
-rw-r--r--arch/x86/vdso/Makefile4
80 files changed, 1310 insertions, 809 deletions
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 62d686f0b426..d13add71f72a 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -65,7 +65,7 @@ obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o
65obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o 65obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o
66obj-$(CONFIG_MACH_STAMP9G20) += board-stamp9g20.o 66obj-$(CONFIG_MACH_STAMP9G20) += board-stamp9g20.o
67obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o 67obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o
68obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o 68obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o board-stamp9g20.o
69 69
70# AT91SAM9260/AT91SAM9G20 board-specific support 70# AT91SAM9260/AT91SAM9G20 board-specific support
71obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o 71obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
index bba5a560e02b..feb65787c30b 100644
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ b/arch/arm/mach-at91/board-pcontrol-g20.c
@@ -31,6 +31,7 @@
31 31
32#include <mach/board.h> 32#include <mach/board.h>
33#include <mach/at91sam9_smc.h> 33#include <mach/at91sam9_smc.h>
34#include <mach/stamp9g20.h>
34 35
35#include "sam9_smc.h" 36#include "sam9_smc.h"
36#include "generic.h" 37#include "generic.h"
@@ -38,11 +39,7 @@
38 39
39static void __init pcontrol_g20_map_io(void) 40static void __init pcontrol_g20_map_io(void)
40{ 41{
41 /* Initialize processor: 18.432 MHz crystal */ 42 stamp9g20_map_io();
42 at91sam9260_initialize(18432000);
43
44 /* DGBU on ttyS0. (Rx, Tx) only TTL -> JTAG connector X7 17,19 ) */
45 at91_register_uart(0, 0, 0);
46 43
47 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) piggyback A2 */ 44 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) piggyback A2 */
48 at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS 45 at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS
@@ -54,9 +51,6 @@ static void __init pcontrol_g20_map_io(void)
54 51
55 /* USART2 on ttyS3. (Rx, Tx) 9bit-Bus Multidrop-mode X4 */ 52 /* USART2 on ttyS3. (Rx, Tx) 9bit-Bus Multidrop-mode X4 */
56 at91_register_uart(AT91SAM9260_ID_US4, 3, 0); 53 at91_register_uart(AT91SAM9260_ID_US4, 3, 0);
57
58 /* set serial console to ttyS0 (ie, DBGU) */
59 at91_set_serial_console(0);
60} 54}
61 55
62 56
@@ -66,38 +60,6 @@ static void __init init_irq(void)
66} 60}
67 61
68 62
69/*
70 * NAND flash 512MiB 1,8V 8-bit, sector size 128 KiB
71 */
72static struct atmel_nand_data __initdata nand_data = {
73 .ale = 21,
74 .cle = 22,
75 .rdy_pin = AT91_PIN_PC13,
76 .enable_pin = AT91_PIN_PC14,
77};
78
79/*
80 * Bus timings; unit = 7.57ns
81 */
82static struct sam9_smc_config __initdata nand_smc_config = {
83 .ncs_read_setup = 0,
84 .nrd_setup = 2,
85 .ncs_write_setup = 0,
86 .nwe_setup = 2,
87
88 .ncs_read_pulse = 4,
89 .nrd_pulse = 4,
90 .ncs_write_pulse = 4,
91 .nwe_pulse = 4,
92
93 .read_cycle = 7,
94 .write_cycle = 7,
95
96 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE
97 | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
98 .tdf_cycles = 3,
99};
100
101static struct sam9_smc_config __initdata pcontrol_smc_config[2] = { { 63static struct sam9_smc_config __initdata pcontrol_smc_config[2] = { {
102 .ncs_read_setup = 16, 64 .ncs_read_setup = 16,
103 .nrd_setup = 18, 65 .nrd_setup = 18,
@@ -138,14 +100,6 @@ static struct sam9_smc_config __initdata pcontrol_smc_config[2] = { {
138 .tdf_cycles = 1, 100 .tdf_cycles = 1,
139} }; 101} };
140 102
141static void __init add_device_nand(void)
142{
143 /* configure chip-select 3 (NAND) */
144 sam9_smc_configure(3, &nand_smc_config);
145 at91_add_device_nand(&nand_data);
146}
147
148
149static void __init add_device_pcontrol(void) 103static void __init add_device_pcontrol(void)
150{ 104{
151 /* configure chip-select 4 (IO compatible to 8051 X4 ) */ 105 /* configure chip-select 4 (IO compatible to 8051 X4 ) */
@@ -156,23 +110,6 @@ static void __init add_device_pcontrol(void)
156 110
157 111
158/* 112/*
159 * MCI (SD/MMC)
160 * det_pin, wp_pin and vcc_pin are not connected
161 */
162#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
163static struct mci_platform_data __initdata mmc_data = {
164 .slot[0] = {
165 .bus_width = 4,
166 },
167};
168#else
169static struct at91_mmc_data __initdata mmc_data = {
170 .wire4 = 1,
171};
172#endif
173
174
175/*
176 * USB Host port 113 * USB Host port
177 */ 114 */
178static struct at91_usbh_data __initdata usbh_data = { 115static struct at91_usbh_data __initdata usbh_data = {
@@ -265,42 +202,13 @@ static struct spi_board_info pcontrol_g20_spi_devices[] = {
265}; 202};
266 203
267 204
268/*
269 * Dallas 1-Wire DS2431
270 */
271static struct w1_gpio_platform_data w1_gpio_pdata = {
272 .pin = AT91_PIN_PA29,
273 .is_open_drain = 1,
274};
275
276static struct platform_device w1_device = {
277 .name = "w1-gpio",
278 .id = -1,
279 .dev.platform_data = &w1_gpio_pdata,
280};
281
282static void add_wire1(void)
283{
284 at91_set_GPIO_periph(w1_gpio_pdata.pin, 1);
285 at91_set_multi_drive(w1_gpio_pdata.pin, 1);
286 platform_device_register(&w1_device);
287}
288
289
290static void __init pcontrol_g20_board_init(void) 205static void __init pcontrol_g20_board_init(void)
291{ 206{
292 at91_add_device_serial(); 207 stamp9g20_board_init();
293 add_device_nand();
294#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
295 at91_add_device_mci(0, &mmc_data);
296#else
297 at91_add_device_mmc(0, &mmc_data);
298#endif
299 at91_add_device_usbh(&usbh_data); 208 at91_add_device_usbh(&usbh_data);
300 at91_add_device_eth(&macb_data); 209 at91_add_device_eth(&macb_data);
301 at91_add_device_i2c(pcontrol_g20_i2c_devices, 210 at91_add_device_i2c(pcontrol_g20_i2c_devices,
302 ARRAY_SIZE(pcontrol_g20_i2c_devices)); 211 ARRAY_SIZE(pcontrol_g20_i2c_devices));
303 add_wire1();
304 add_device_pcontrol(); 212 add_device_pcontrol();
305 at91_add_device_spi(pcontrol_g20_spi_devices, 213 at91_add_device_spi(pcontrol_g20_spi_devices,
306 ARRAY_SIZE(pcontrol_g20_spi_devices)); 214 ARRAY_SIZE(pcontrol_g20_spi_devices));
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index 5206eef4a67e..f8902b118960 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -32,7 +32,7 @@
32#include "generic.h" 32#include "generic.h"
33 33
34 34
35static void __init portuxg20_map_io(void) 35void __init stamp9g20_map_io(void)
36{ 36{
37 /* Initialize processor: 18.432 MHz crystal */ 37 /* Initialize processor: 18.432 MHz crystal */
38 at91sam9260_initialize(18432000); 38 at91sam9260_initialize(18432000);
@@ -40,6 +40,24 @@ static void __init portuxg20_map_io(void)
40 /* DGBU on ttyS0. (Rx & Tx only) */ 40 /* DGBU on ttyS0. (Rx & Tx only) */
41 at91_register_uart(0, 0, 0); 41 at91_register_uart(0, 0, 0);
42 42
43 /* set serial console to ttyS0 (ie, DBGU) */
44 at91_set_serial_console(0);
45}
46
47static void __init stamp9g20evb_map_io(void)
48{
49 stamp9g20_map_io();
50
51 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
52 at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
53 | ATMEL_UART_DTR | ATMEL_UART_DSR
54 | ATMEL_UART_DCD | ATMEL_UART_RI);
55}
56
57static void __init portuxg20_map_io(void)
58{
59 stamp9g20_map_io();
60
43 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ 61 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
44 at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS 62 at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
45 | ATMEL_UART_DTR | ATMEL_UART_DSR 63 | ATMEL_UART_DTR | ATMEL_UART_DSR
@@ -56,26 +74,6 @@ static void __init portuxg20_map_io(void)
56 74
57 /* USART5 on ttyS6. (Rx, Tx only) */ 75 /* USART5 on ttyS6. (Rx, Tx only) */
58 at91_register_uart(AT91SAM9260_ID_US5, 6, 0); 76 at91_register_uart(AT91SAM9260_ID_US5, 6, 0);
59
60 /* set serial console to ttyS0 (ie, DBGU) */
61 at91_set_serial_console(0);
62}
63
64static void __init stamp9g20_map_io(void)
65{
66 /* Initialize processor: 18.432 MHz crystal */
67 at91sam9260_initialize(18432000);
68
69 /* DGBU on ttyS0. (Rx & Tx only) */
70 at91_register_uart(0, 0, 0);
71
72 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
73 at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
74 | ATMEL_UART_DTR | ATMEL_UART_DSR
75 | ATMEL_UART_DCD | ATMEL_UART_RI);
76
77 /* set serial console to ttyS0 (ie, DBGU) */
78 at91_set_serial_console(0);
79} 77}
80 78
81static void __init init_irq(void) 79static void __init init_irq(void)
@@ -156,7 +154,7 @@ static struct at91_udc_data __initdata portuxg20_udc_data = {
156 .pullup_pin = 0, /* pull-up driven by UDC */ 154 .pullup_pin = 0, /* pull-up driven by UDC */
157}; 155};
158 156
159static struct at91_udc_data __initdata stamp9g20_udc_data = { 157static struct at91_udc_data __initdata stamp9g20evb_udc_data = {
160 .vbus_pin = AT91_PIN_PA22, 158 .vbus_pin = AT91_PIN_PA22,
161 .pullup_pin = 0, /* pull-up driven by UDC */ 159 .pullup_pin = 0, /* pull-up driven by UDC */
162}; 160};
@@ -190,7 +188,7 @@ static struct gpio_led portuxg20_leds[] = {
190 } 188 }
191}; 189};
192 190
193static struct gpio_led stamp9g20_leds[] = { 191static struct gpio_led stamp9g20evb_leds[] = {
194 { 192 {
195 .name = "D8", 193 .name = "D8",
196 .gpio = AT91_PIN_PB18, 194 .gpio = AT91_PIN_PB18,
@@ -250,7 +248,7 @@ void add_w1(void)
250} 248}
251 249
252 250
253static void __init generic_board_init(void) 251void __init stamp9g20_board_init(void)
254{ 252{
255 /* Serial */ 253 /* Serial */
256 at91_add_device_serial(); 254 at91_add_device_serial();
@@ -262,34 +260,40 @@ static void __init generic_board_init(void)
262#else 260#else
263 at91_add_device_mmc(0, &mmc_data); 261 at91_add_device_mmc(0, &mmc_data);
264#endif 262#endif
265 /* USB Host */
266 at91_add_device_usbh(&usbh_data);
267 /* Ethernet */
268 at91_add_device_eth(&macb_data);
269 /* I2C */
270 at91_add_device_i2c(NULL, 0);
271 /* W1 */ 263 /* W1 */
272 add_w1(); 264 add_w1();
273} 265}
274 266
275static void __init portuxg20_board_init(void) 267static void __init portuxg20_board_init(void)
276{ 268{
277 generic_board_init(); 269 stamp9g20_board_init();
278 /* SPI */ 270 /* USB Host */
279 at91_add_device_spi(portuxg20_spi_devices, ARRAY_SIZE(portuxg20_spi_devices)); 271 at91_add_device_usbh(&usbh_data);
280 /* USB Device */ 272 /* USB Device */
281 at91_add_device_udc(&portuxg20_udc_data); 273 at91_add_device_udc(&portuxg20_udc_data);
274 /* Ethernet */
275 at91_add_device_eth(&macb_data);
276 /* I2C */
277 at91_add_device_i2c(NULL, 0);
278 /* SPI */
279 at91_add_device_spi(portuxg20_spi_devices, ARRAY_SIZE(portuxg20_spi_devices));
282 /* LEDs */ 280 /* LEDs */
283 at91_gpio_leds(portuxg20_leds, ARRAY_SIZE(portuxg20_leds)); 281 at91_gpio_leds(portuxg20_leds, ARRAY_SIZE(portuxg20_leds));
284} 282}
285 283
286static void __init stamp9g20_board_init(void) 284static void __init stamp9g20evb_board_init(void)
287{ 285{
288 generic_board_init(); 286 stamp9g20_board_init();
287 /* USB Host */
288 at91_add_device_usbh(&usbh_data);
289 /* USB Device */ 289 /* USB Device */
290 at91_add_device_udc(&stamp9g20_udc_data); 290 at91_add_device_udc(&stamp9g20evb_udc_data);
291 /* Ethernet */
292 at91_add_device_eth(&macb_data);
293 /* I2C */
294 at91_add_device_i2c(NULL, 0);
291 /* LEDs */ 295 /* LEDs */
292 at91_gpio_leds(stamp9g20_leds, ARRAY_SIZE(stamp9g20_leds)); 296 at91_gpio_leds(stamp9g20evb_leds, ARRAY_SIZE(stamp9g20evb_leds));
293} 297}
294 298
295MACHINE_START(PORTUXG20, "taskit PortuxG20") 299MACHINE_START(PORTUXG20, "taskit PortuxG20")
@@ -305,7 +309,7 @@ MACHINE_START(STAMP9G20, "taskit Stamp9G20")
305 /* Maintainer: taskit GmbH */ 309 /* Maintainer: taskit GmbH */
306 .boot_params = AT91_SDRAM_BASE + 0x100, 310 .boot_params = AT91_SDRAM_BASE + 0x100,
307 .timer = &at91sam926x_timer, 311 .timer = &at91sam926x_timer,
308 .map_io = stamp9g20_map_io, 312 .map_io = stamp9g20evb_map_io,
309 .init_irq = init_irq, 313 .init_irq = init_irq,
310 .init_machine = stamp9g20_board_init, 314 .init_machine = stamp9g20evb_board_init,
311MACHINE_END 315MACHINE_END
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 7525cee3983f..9113da6845f1 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -658,7 +658,7 @@ static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
658 /* Now set uhpck values */ 658 /* Now set uhpck values */
659 uhpck.parent = &utmi_clk; 659 uhpck.parent = &utmi_clk;
660 uhpck.pmc_mask = AT91SAM926x_PMC_UHP; 660 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
661 uhpck.rate_hz = utmi_clk.parent->rate_hz; 661 uhpck.rate_hz = utmi_clk.rate_hz;
662 uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8); 662 uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
663} 663}
664 664
diff --git a/arch/arm/mach-at91/include/mach/stamp9g20.h b/arch/arm/mach-at91/include/mach/stamp9g20.h
new file mode 100644
index 000000000000..6120f9c46d59
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/stamp9g20.h
@@ -0,0 +1,7 @@
1#ifndef __MACH_STAMP9G20_H
2#define __MACH_STAMP9G20_H
3
4void stamp9g20_map_io(void);
5void stamp9g20_board_init(void);
6
7#endif
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 1fa3294b6048..0269bb055b69 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -239,9 +239,19 @@ void omap3_save_scratchpad_contents(void)
239 struct omap3_scratchpad_prcm_block prcm_block_contents; 239 struct omap3_scratchpad_prcm_block prcm_block_contents;
240 struct omap3_scratchpad_sdrc_block sdrc_block_contents; 240 struct omap3_scratchpad_sdrc_block sdrc_block_contents;
241 241
242 /* Populate the Scratchpad contents */ 242 /*
243 * Populate the Scratchpad contents
244 *
245 * The "get_*restore_pointer" functions are used to provide a
246 * physical restore address where the ROM code jumps while waking
247 * up from MPU OFF/OSWR state.
248 * The restore pointer is stored into the scratchpad.
249 */
243 scratchpad_contents.boot_config_ptr = 0x0; 250 scratchpad_contents.boot_config_ptr = 0x0;
244 if (omap_rev() != OMAP3430_REV_ES3_0 && 251 if (cpu_is_omap3630())
252 scratchpad_contents.public_restore_ptr =
253 virt_to_phys(get_omap3630_restore_pointer());
254 else if (omap_rev() != OMAP3430_REV_ES3_0 &&
245 omap_rev() != OMAP3430_REV_ES3_1) 255 omap_rev() != OMAP3430_REV_ES3_1)
246 scratchpad_contents.public_restore_ptr = 256 scratchpad_contents.public_restore_ptr =
247 virt_to_phys(get_restore_pointer()); 257 virt_to_phys(get_restore_pointer());
@@ -474,4 +484,12 @@ void omap3_control_restore_context(void)
474 omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI); 484 omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
475 return; 485 return;
476} 486}
487
488void omap3630_ctrl_disable_rta(void)
489{
490 if (!cpu_is_omap3630())
491 return;
492 omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL);
493}
494
477#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ 495#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index b6c6b7c450b3..6e5f7e512ff7 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -204,6 +204,10 @@
204#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014) 204#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
205#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018) 205#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
206 206
207/* 36xx-only RTA - Retention till Accesss control registers and bits */
208#define OMAP36XX_CONTROL_MEM_RTA_CTRL 0x40C
209#define OMAP36XX_RTA_DISABLE 0x0
210
207/* 34xx D2D idle-related pins, handled by PM core */ 211/* 34xx D2D idle-related pins, handled by PM core */
208#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 212#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
209#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 213#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
@@ -270,6 +274,8 @@
270#define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860) 274#define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860)
271#define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910) 275#define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910)
272#define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C 276#define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C
277#define OMAP343X_SCRATCHPAD_REGADDR(reg) OMAP2_L4_IO_ADDRESS(\
278 OMAP343X_SCRATCHPAD + reg)
273 279
274/* AM35XX_CONTROL_IPSS_CLK_CTRL bits */ 280/* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
275#define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0 281#define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0
@@ -347,10 +353,11 @@ extern void omap3_save_scratchpad_contents(void);
347extern void omap3_clear_scratchpad_contents(void); 353extern void omap3_clear_scratchpad_contents(void);
348extern u32 *get_restore_pointer(void); 354extern u32 *get_restore_pointer(void);
349extern u32 *get_es3_restore_pointer(void); 355extern u32 *get_es3_restore_pointer(void);
356extern u32 *get_omap3630_restore_pointer(void);
350extern u32 omap3_arm_context[128]; 357extern u32 omap3_arm_context[128];
351extern void omap3_control_save_context(void); 358extern void omap3_control_save_context(void);
352extern void omap3_control_restore_context(void); 359extern void omap3_control_restore_context(void);
353 360extern void omap3630_ctrl_disable_rta(void);
354#else 361#else
355#define omap_ctrl_base_get() 0 362#define omap_ctrl_base_get() 0
356#define omap_ctrl_readb(x) 0 363#define omap_ctrl_readb(x) 0
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 0d50b45d041c..0fb619c52588 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -293,25 +293,26 @@ select_state:
293DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); 293DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
294 294
295/** 295/**
296 * omap3_cpuidle_update_states - Update the cpuidle states. 296 * omap3_cpuidle_update_states() - Update the cpuidle states
297 * @mpu_deepest_state: Enable states upto and including this for mpu domain
298 * @core_deepest_state: Enable states upto and including this for core domain
297 * 299 *
298 * Currently, this function toggles the validity of idle states based upon 300 * This goes through the list of states available and enables and disables the
299 * the flag 'enable_off_mode'. When the flag is set all states are valid. 301 * validity of C states based on deepest state that can be achieved for the
300 * Else, states leading to OFF state set to be invalid. 302 * variable domain
301 */ 303 */
302void omap3_cpuidle_update_states(void) 304void omap3_cpuidle_update_states(u32 mpu_deepest_state, u32 core_deepest_state)
303{ 305{
304 int i; 306 int i;
305 307
306 for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) { 308 for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
307 struct omap3_processor_cx *cx = &omap3_power_states[i]; 309 struct omap3_processor_cx *cx = &omap3_power_states[i];
308 310
309 if (enable_off_mode) { 311 if ((cx->mpu_state >= mpu_deepest_state) &&
312 (cx->core_state >= core_deepest_state)) {
310 cx->valid = 1; 313 cx->valid = 1;
311 } else { 314 } else {
312 if ((cx->mpu_state == PWRDM_POWER_OFF) || 315 cx->valid = 0;
313 (cx->core_state == PWRDM_POWER_OFF))
314 cx->valid = 0;
315 } 316 }
316 } 317 }
317} 318}
@@ -452,6 +453,18 @@ void omap_init_power_states(void)
452 omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF; 453 omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
453 omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID | 454 omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID |
454 CPUIDLE_FLAG_CHECK_BM; 455 CPUIDLE_FLAG_CHECK_BM;
456
457 /*
458 * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
459 * enable OFF mode in a stable form for previous revisions.
460 * we disable C7 state as a result.
461 */
462 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
463 omap3_power_states[OMAP3_STATE_C7].valid = 0;
464 cpuidle_params_table[OMAP3_STATE_C7].valid = 0;
465 WARN_ONCE(1, "%s: core off state C7 disabled due to i583\n",
466 __func__);
467 }
455} 468}
456 469
457struct cpuidle_driver omap3_idle_driver = { 470struct cpuidle_driver omap3_idle_driver = {
@@ -504,7 +517,10 @@ int __init omap3_idle_init(void)
504 return -EINVAL; 517 return -EINVAL;
505 dev->state_count = count; 518 dev->state_count = count;
506 519
507 omap3_cpuidle_update_states(); 520 if (enable_off_mode)
521 omap3_cpuidle_update_states(PWRDM_POWER_OFF, PWRDM_POWER_OFF);
522 else
523 omap3_cpuidle_update_states(PWRDM_POWER_RET, PWRDM_POWER_RET);
508 524
509 if (cpuidle_register_device(dev)) { 525 if (cpuidle_register_device(dev)) {
510 printk(KERN_ERR "%s: CPUidle register device failed\n", 526 printk(KERN_ERR "%s: CPUidle register device failed\n",
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 59ca03b0e691..6ec2ee12272a 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -143,5 +143,5 @@ static int __init omap2_common_pm_init(void)
143 143
144 return 0; 144 return 0;
145} 145}
146device_initcall(omap2_common_pm_init); 146postcore_initcall(omap2_common_pm_init);
147 147
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 0d75bfd1fdbe..c04f7b50e26f 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -58,7 +58,7 @@ extern u32 sleep_while_idle;
58#endif 58#endif
59 59
60#if defined(CONFIG_CPU_IDLE) 60#if defined(CONFIG_CPU_IDLE)
61extern void omap3_cpuidle_update_states(void); 61extern void omap3_cpuidle_update_states(u32, u32);
62#endif 62#endif
63 63
64#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) 64#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
@@ -80,9 +80,20 @@ extern void save_secure_ram_context(u32 *addr);
80extern void omap3_save_scratchpad_contents(void); 80extern void omap3_save_scratchpad_contents(void);
81 81
82extern unsigned int omap24xx_idle_loop_suspend_sz; 82extern unsigned int omap24xx_idle_loop_suspend_sz;
83extern unsigned int omap34xx_suspend_sz;
84extern unsigned int save_secure_ram_context_sz; 83extern unsigned int save_secure_ram_context_sz;
85extern unsigned int omap24xx_cpu_suspend_sz; 84extern unsigned int omap24xx_cpu_suspend_sz;
86extern unsigned int omap34xx_cpu_suspend_sz; 85extern unsigned int omap34xx_cpu_suspend_sz;
87 86
87#define PM_RTA_ERRATUM_i608 (1 << 0)
88#define PM_SDRC_WAKEUP_ERRATUM_i583 (1 << 1)
89
90#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
91extern u16 pm34xx_errata;
92#define IS_PM34XX_ERRATUM(id) (pm34xx_errata & (id))
93extern void enable_omap3630_toggle_l2_on_restore(void);
94#else
95#define IS_PM34XX_ERRATUM(id) 0
96static inline void enable_omap3630_toggle_l2_on_restore(void) { }
97#endif /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */
98
88#endif 99#endif
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index aaeea49b9bdd..aea7ced9a2ff 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -301,14 +301,8 @@ out:
301 301
302static int omap2_pm_begin(suspend_state_t state) 302static int omap2_pm_begin(suspend_state_t state)
303{ 303{
304 suspend_state = state;
305 return 0;
306}
307
308static int omap2_pm_prepare(void)
309{
310 /* We cannot sleep in idle until we have resumed */
311 disable_hlt(); 304 disable_hlt();
305 suspend_state = state;
312 return 0; 306 return 0;
313} 307}
314 308
@@ -349,21 +343,15 @@ static int omap2_pm_enter(suspend_state_t state)
349 return ret; 343 return ret;
350} 344}
351 345
352static void omap2_pm_finish(void)
353{
354 enable_hlt();
355}
356
357static void omap2_pm_end(void) 346static void omap2_pm_end(void)
358{ 347{
359 suspend_state = PM_SUSPEND_ON; 348 suspend_state = PM_SUSPEND_ON;
349 enable_hlt();
360} 350}
361 351
362static struct platform_suspend_ops omap_pm_ops = { 352static struct platform_suspend_ops omap_pm_ops = {
363 .begin = omap2_pm_begin, 353 .begin = omap2_pm_begin,
364 .prepare = omap2_pm_prepare,
365 .enter = omap2_pm_enter, 354 .enter = omap2_pm_enter,
366 .finish = omap2_pm_finish,
367 .end = omap2_pm_end, 355 .end = omap2_pm_end,
368 .valid = suspend_valid_only_mem, 356 .valid = suspend_valid_only_mem,
369}; 357};
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 648b8c50d024..c45b4fa1deeb 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -68,6 +68,9 @@ static inline bool is_suspending(void)
68#define OMAP343X_TABLE_VALUE_OFFSET 0xc0 68#define OMAP343X_TABLE_VALUE_OFFSET 0xc0
69#define OMAP343X_CONTROL_REG_VALUE_OFFSET 0xc8 69#define OMAP343X_CONTROL_REG_VALUE_OFFSET 0xc8
70 70
71/* pm34xx errata defined in pm.h */
72u16 pm34xx_errata;
73
71struct power_state { 74struct power_state {
72 struct powerdomain *pwrdm; 75 struct powerdomain *pwrdm;
73 u32 next_state; 76 u32 next_state;
@@ -143,7 +146,7 @@ static void omap3_core_save_context(void)
143 146
144 /* 147 /*
145 * Force write last pad into memory, as this can fail in some 148 * Force write last pad into memory, as this can fail in some
146 * cases according to erratas 1.157, 1.185 149 * cases according to errata 1.157, 1.185
147 */ 150 */
148 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), 151 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
149 OMAP343X_CONTROL_MEM_WKUP + 0x2a0); 152 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
@@ -430,7 +433,7 @@ void omap_sram_idle(void)
430 /* 433 /*
431 * On EMU/HS devices ROM code restores a SRDC value 434 * On EMU/HS devices ROM code restores a SRDC value
432 * from scratchpad which has automatic self refresh on timeout 435 * from scratchpad which has automatic self refresh on timeout
433 * of AUTO_CNT = 1 enabled. This takes care of errata 1.142. 436 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
434 * Hence store/restore the SDRC_POWER register here. 437 * Hence store/restore the SDRC_POWER register here.
435 */ 438 */
436 if (omap_rev() >= OMAP3430_REV_ES3_0 && 439 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
@@ -529,12 +532,6 @@ out:
529} 532}
530 533
531#ifdef CONFIG_SUSPEND 534#ifdef CONFIG_SUSPEND
532static int omap3_pm_prepare(void)
533{
534 disable_hlt();
535 return 0;
536}
537
538static int omap3_pm_suspend(void) 535static int omap3_pm_suspend(void)
539{ 536{
540 struct power_state *pwrst; 537 struct power_state *pwrst;
@@ -597,14 +594,10 @@ static int omap3_pm_enter(suspend_state_t unused)
597 return ret; 594 return ret;
598} 595}
599 596
600static void omap3_pm_finish(void)
601{
602 enable_hlt();
603}
604
605/* Hooks to enable / disable UART interrupts during suspend */ 597/* Hooks to enable / disable UART interrupts during suspend */
606static int omap3_pm_begin(suspend_state_t state) 598static int omap3_pm_begin(suspend_state_t state)
607{ 599{
600 disable_hlt();
608 suspend_state = state; 601 suspend_state = state;
609 omap_uart_enable_irqs(0); 602 omap_uart_enable_irqs(0);
610 return 0; 603 return 0;
@@ -614,15 +607,14 @@ static void omap3_pm_end(void)
614{ 607{
615 suspend_state = PM_SUSPEND_ON; 608 suspend_state = PM_SUSPEND_ON;
616 omap_uart_enable_irqs(1); 609 omap_uart_enable_irqs(1);
610 enable_hlt();
617 return; 611 return;
618} 612}
619 613
620static struct platform_suspend_ops omap_pm_ops = { 614static struct platform_suspend_ops omap_pm_ops = {
621 .begin = omap3_pm_begin, 615 .begin = omap3_pm_begin,
622 .end = omap3_pm_end, 616 .end = omap3_pm_end,
623 .prepare = omap3_pm_prepare,
624 .enter = omap3_pm_enter, 617 .enter = omap3_pm_enter,
625 .finish = omap3_pm_finish,
626 .valid = suspend_valid_only_mem, 618 .valid = suspend_valid_only_mem,
627}; 619};
628#endif /* CONFIG_SUSPEND */ 620#endif /* CONFIG_SUSPEND */
@@ -925,12 +917,29 @@ void omap3_pm_off_mode_enable(int enable)
925 state = PWRDM_POWER_RET; 917 state = PWRDM_POWER_RET;
926 918
927#ifdef CONFIG_CPU_IDLE 919#ifdef CONFIG_CPU_IDLE
928 omap3_cpuidle_update_states(); 920 /*
921 * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
922 * enable OFF mode in a stable form for previous revisions, restrict
923 * instead to RET
924 */
925 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
926 omap3_cpuidle_update_states(state, PWRDM_POWER_RET);
927 else
928 omap3_cpuidle_update_states(state, state);
929#endif 929#endif
930 930
931 list_for_each_entry(pwrst, &pwrst_list, node) { 931 list_for_each_entry(pwrst, &pwrst_list, node) {
932 pwrst->next_state = state; 932 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
933 omap_set_pwrdm_state(pwrst->pwrdm, state); 933 pwrst->pwrdm == core_pwrdm &&
934 state == PWRDM_POWER_OFF) {
935 pwrst->next_state = PWRDM_POWER_RET;
936 WARN_ONCE(1,
937 "%s: Core OFF disabled due to errata i583\n",
938 __func__);
939 } else {
940 pwrst->next_state = state;
941 }
942 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
934 } 943 }
935} 944}
936 945
@@ -1002,6 +1011,17 @@ void omap_push_sram_idle(void)
1002 save_secure_ram_context_sz); 1011 save_secure_ram_context_sz);
1003} 1012}
1004 1013
1014static void __init pm_errata_configure(void)
1015{
1016 if (cpu_is_omap3630()) {
1017 pm34xx_errata |= PM_RTA_ERRATUM_i608;
1018 /* Enable the l2 cache toggling in sleep logic */
1019 enable_omap3630_toggle_l2_on_restore();
1020 if (omap_rev() < OMAP3630_REV_ES1_2)
1021 pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
1022 }
1023}
1024
1005static int __init omap3_pm_init(void) 1025static int __init omap3_pm_init(void)
1006{ 1026{
1007 struct power_state *pwrst, *tmp; 1027 struct power_state *pwrst, *tmp;
@@ -1011,6 +1031,8 @@ static int __init omap3_pm_init(void)
1011 if (!cpu_is_omap34xx()) 1031 if (!cpu_is_omap34xx())
1012 return -ENODEV; 1032 return -ENODEV;
1013 1033
1034 pm_errata_configure();
1035
1014 printk(KERN_ERR "Power Management for TI OMAP3.\n"); 1036 printk(KERN_ERR "Power Management for TI OMAP3.\n");
1015 1037
1016 /* XXX prcm_setup_regs needs to be before enabling hw 1038 /* XXX prcm_setup_regs needs to be before enabling hw
@@ -1058,6 +1080,14 @@ static int __init omap3_pm_init(void)
1058 pm_idle = omap3_pm_idle; 1080 pm_idle = omap3_pm_idle;
1059 omap3_idle_init(); 1081 omap3_idle_init();
1060 1082
1083 /*
1084 * RTA is disabled during initialization as per erratum i608
1085 * it is safer to disable RTA by the bootloader, but we would like
1086 * to be doubly sure here and prevent any mishaps.
1087 */
1088 if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
1089 omap3630_ctrl_disable_rta();
1090
1061 clkdm_add_wkdep(neon_clkdm, mpu_clkdm); 1091 clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
1062 if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 1092 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
1063 omap3_secure_ram_storage = 1093 omap3_secure_ram_storage =
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 54544b4fc76b..6aff9961e35d 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -31,12 +31,6 @@ struct power_state {
31static LIST_HEAD(pwrst_list); 31static LIST_HEAD(pwrst_list);
32 32
33#ifdef CONFIG_SUSPEND 33#ifdef CONFIG_SUSPEND
34static int omap4_pm_prepare(void)
35{
36 disable_hlt();
37 return 0;
38}
39
40static int omap4_pm_suspend(void) 34static int omap4_pm_suspend(void)
41{ 35{
42 do_wfi(); 36 do_wfi();
@@ -59,28 +53,22 @@ static int omap4_pm_enter(suspend_state_t suspend_state)
59 return ret; 53 return ret;
60} 54}
61 55
62static void omap4_pm_finish(void)
63{
64 enable_hlt();
65 return;
66}
67
68static int omap4_pm_begin(suspend_state_t state) 56static int omap4_pm_begin(suspend_state_t state)
69{ 57{
58 disable_hlt();
70 return 0; 59 return 0;
71} 60}
72 61
73static void omap4_pm_end(void) 62static void omap4_pm_end(void)
74{ 63{
64 enable_hlt();
75 return; 65 return;
76} 66}
77 67
78static struct platform_suspend_ops omap_pm_ops = { 68static struct platform_suspend_ops omap_pm_ops = {
79 .begin = omap4_pm_begin, 69 .begin = omap4_pm_begin,
80 .end = omap4_pm_end, 70 .end = omap4_pm_end,
81 .prepare = omap4_pm_prepare,
82 .enter = omap4_pm_enter, 71 .enter = omap4_pm_enter,
83 .finish = omap4_pm_finish,
84 .valid = suspend_valid_only_mem, 72 .valid = suspend_valid_only_mem,
85}; 73};
86#endif /* CONFIG_SUSPEND */ 74#endif /* CONFIG_SUSPEND */
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h
index 68f57bb67fc5..b3f83799e6cf 100644
--- a/arch/arm/mach-omap2/sdrc.h
+++ b/arch/arm/mach-omap2/sdrc.h
@@ -74,5 +74,4 @@ static inline u32 sms_read_reg(u16 reg)
74 */ 74 */
75#define SDRC_MPURATE_LOOPS 96 75#define SDRC_MPURATE_LOOPS 96
76 76
77
78#endif 77#endif
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 2fb205a7f285..e3b5cd76c54c 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -1,6 +1,4 @@
1/* 1/*
2 * linux/arch/arm/mach-omap2/sleep.S
3 *
4 * (C) Copyright 2007 2 * (C) Copyright 2007
5 * Texas Instruments 3 * Texas Instruments
6 * Karthik Dasu <karthik-dp@ti.com> 4 * Karthik Dasu <karthik-dp@ti.com>
@@ -26,6 +24,7 @@
26 */ 24 */
27#include <linux/linkage.h> 25#include <linux/linkage.h>
28#include <asm/assembler.h> 26#include <asm/assembler.h>
27#include <plat/sram.h>
29#include <mach/io.h> 28#include <mach/io.h>
30 29
31#include "cm.h" 30#include "cm.h"
@@ -33,21 +32,27 @@
33#include "sdrc.h" 32#include "sdrc.h"
34#include "control.h" 33#include "control.h"
35 34
36#define SDRC_SCRATCHPAD_SEM_V 0xfa00291c 35/*
37 36 * Registers access definitions
38#define PM_PREPWSTST_CORE_V OMAP34XX_PRM_REGADDR(CORE_MOD, \ 37 */
39 OMAP3430_PM_PREPWSTST) 38#define SDRC_SCRATCHPAD_SEM_OFFS 0xc
40#define PM_PREPWSTST_CORE_P 0x48306AE8 39#define SDRC_SCRATCHPAD_SEM_V OMAP343X_SCRATCHPAD_REGADDR\
41#define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \ 40 (SDRC_SCRATCHPAD_SEM_OFFS)
42 OMAP3430_PM_PREPWSTST) 41#define PM_PREPWSTST_CORE_P OMAP3430_PRM_BASE + CORE_MOD +\
42 OMAP3430_PM_PREPWSTST
43#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL 43#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL
44#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1) 44#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
45#define SRAM_BASE_P 0x40200000 45#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
46#define CONTROL_STAT 0x480022F0 46#define SRAM_BASE_P OMAP3_SRAM_PA
47#define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is 47#define CONTROL_STAT OMAP343X_CTRL_BASE + OMAP343X_CONTROL_STATUS
48 * available */ 48#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE +\
49#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE + OMAP343X_CONTROL_MEM_WKUP\ 49 OMAP36XX_CONTROL_MEM_RTA_CTRL)
50 + SCRATCHPAD_MEM_OFFS) 50
51/* Move this as correct place is available */
52#define SCRATCHPAD_MEM_OFFS 0x310
53#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE +\
54 OMAP343X_CONTROL_MEM_WKUP +\
55 SCRATCHPAD_MEM_OFFS)
51#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER) 56#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER)
52#define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG) 57#define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG)
53#define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0) 58#define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0)
@@ -59,48 +64,38 @@
59#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) 64#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
60#define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL) 65#define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
61 66
62 .text 67
63/* Function to acquire the semaphore in scratchpad */ 68/*
64ENTRY(lock_scratchpad_sem) 69 * API functions
65 stmfd sp!, {lr} @ save registers on stack 70 */
66wait_sem: 71
67 mov r0,#1 72/*
68 ldr r1, sdrc_scratchpad_sem 73 * The "get_*restore_pointer" functions are used to provide a
69wait_loop: 74 * physical restore address where the ROM code jumps while waking
70 ldr r2, [r1] @ load the lock value 75 * up from MPU OFF/OSWR state.
71 cmp r2, r0 @ is the lock free ? 76 * The restore pointer is stored into the scratchpad.
72 beq wait_loop @ not free... 77 */
73 swp r2, r0, [r1] @ semaphore free so lock it and proceed
74 cmp r2, r0 @ did we succeed ?
75 beq wait_sem @ no - try again
76 ldmfd sp!, {pc} @ restore regs and return
77sdrc_scratchpad_sem:
78 .word SDRC_SCRATCHPAD_SEM_V
79ENTRY(lock_scratchpad_sem_sz)
80 .word . - lock_scratchpad_sem
81
82 .text
83/* Function to release the scratchpad semaphore */
84ENTRY(unlock_scratchpad_sem)
85 stmfd sp!, {lr} @ save registers on stack
86 ldr r3, sdrc_scratchpad_sem
87 mov r2,#0
88 str r2,[r3]
89 ldmfd sp!, {pc} @ restore regs and return
90ENTRY(unlock_scratchpad_sem_sz)
91 .word . - unlock_scratchpad_sem
92 78
93 .text 79 .text
94/* Function call to get the restore pointer for resume from OFF */ 80/* Function call to get the restore pointer for resume from OFF */
95ENTRY(get_restore_pointer) 81ENTRY(get_restore_pointer)
96 stmfd sp!, {lr} @ save registers on stack 82 stmfd sp!, {lr} @ save registers on stack
97 adr r0, restore 83 adr r0, restore
98 ldmfd sp!, {pc} @ restore regs and return 84 ldmfd sp!, {pc} @ restore regs and return
99ENTRY(get_restore_pointer_sz) 85ENTRY(get_restore_pointer_sz)
100 .word . - get_restore_pointer 86 .word . - get_restore_pointer
101 87
102 .text 88 .text
103/* Function call to get the restore pointer for for ES3 to resume from OFF */ 89/* Function call to get the restore pointer for 3630 resume from OFF */
90ENTRY(get_omap3630_restore_pointer)
91 stmfd sp!, {lr} @ save registers on stack
92 adr r0, restore_3630
93 ldmfd sp!, {pc} @ restore regs and return
94ENTRY(get_omap3630_restore_pointer_sz)
95 .word . - get_omap3630_restore_pointer
96
97 .text
98/* Function call to get the restore pointer for ES3 to resume from OFF */
104ENTRY(get_es3_restore_pointer) 99ENTRY(get_es3_restore_pointer)
105 stmfd sp!, {lr} @ save registers on stack 100 stmfd sp!, {lr} @ save registers on stack
106 adr r0, restore_es3 101 adr r0, restore_es3
@@ -108,54 +103,23 @@ ENTRY(get_es3_restore_pointer)
108ENTRY(get_es3_restore_pointer_sz) 103ENTRY(get_es3_restore_pointer_sz)
109 .word . - get_es3_restore_pointer 104 .word . - get_es3_restore_pointer
110 105
111ENTRY(es3_sdrc_fix) 106 .text
112 ldr r4, sdrc_syscfg @ get config addr 107/*
113 ldr r5, [r4] @ get value 108 * L2 cache needs to be toggled for stable OFF mode functionality on 3630.
114 tst r5, #0x100 @ is part access blocked 109 * This function sets up a flag that will allow for this toggling to take
115 it eq 110 * place on 3630. Hopefully some version in the future may not need this.
116 biceq r5, r5, #0x100 @ clear bit if set 111 */
117 str r5, [r4] @ write back change 112ENTRY(enable_omap3630_toggle_l2_on_restore)
118 ldr r4, sdrc_mr_0 @ get config addr 113 stmfd sp!, {lr} @ save registers on stack
119 ldr r5, [r4] @ get value 114 /* Setup so that we will disable and enable l2 */
120 str r5, [r4] @ write back change 115 mov r1, #0x1
121 ldr r4, sdrc_emr2_0 @ get config addr 116 str r1, l2dis_3630
122 ldr r5, [r4] @ get value 117 ldmfd sp!, {pc} @ restore regs and return
123 str r5, [r4] @ write back change
124 ldr r4, sdrc_manual_0 @ get config addr
125 mov r5, #0x2 @ autorefresh command
126 str r5, [r4] @ kick off refreshes
127 ldr r4, sdrc_mr_1 @ get config addr
128 ldr r5, [r4] @ get value
129 str r5, [r4] @ write back change
130 ldr r4, sdrc_emr2_1 @ get config addr
131 ldr r5, [r4] @ get value
132 str r5, [r4] @ write back change
133 ldr r4, sdrc_manual_1 @ get config addr
134 mov r5, #0x2 @ autorefresh command
135 str r5, [r4] @ kick off refreshes
136 bx lr
137sdrc_syscfg:
138 .word SDRC_SYSCONFIG_P
139sdrc_mr_0:
140 .word SDRC_MR_0_P
141sdrc_emr2_0:
142 .word SDRC_EMR2_0_P
143sdrc_manual_0:
144 .word SDRC_MANUAL_0_P
145sdrc_mr_1:
146 .word SDRC_MR_1_P
147sdrc_emr2_1:
148 .word SDRC_EMR2_1_P
149sdrc_manual_1:
150 .word SDRC_MANUAL_1_P
151ENTRY(es3_sdrc_fix_sz)
152 .word . - es3_sdrc_fix
153 118
119 .text
154/* Function to call rom code to save secure ram context */ 120/* Function to call rom code to save secure ram context */
155ENTRY(save_secure_ram_context) 121ENTRY(save_secure_ram_context)
156 stmfd sp!, {r1-r12, lr} @ save registers on stack 122 stmfd sp!, {r1-r12, lr} @ save registers on stack
157save_secure_ram_debug:
158 /* b save_secure_ram_debug */ @ enable to debug save code
159 adr r3, api_params @ r3 points to parameters 123 adr r3, api_params @ r3 points to parameters
160 str r0, [r3,#0x4] @ r0 has sdram address 124 str r0, [r3,#0x4] @ r0 has sdram address
161 ldr r12, high_mask 125 ldr r12, high_mask
@@ -185,35 +149,162 @@ ENTRY(save_secure_ram_context_sz)
185 .word . - save_secure_ram_context 149 .word . - save_secure_ram_context
186 150
187/* 151/*
152 * ======================
153 * == Idle entry point ==
154 * ======================
155 */
156
157/*
188 * Forces OMAP into idle state 158 * Forces OMAP into idle state
189 * 159 *
190 * omap34xx_suspend() - This bit of code just executes the WFI 160 * omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed
191 * for normal idles. 161 * and executes the WFI instruction. Calling WFI effectively changes the
162 * power domains states to the desired target power states.
163 *
192 * 164 *
193 * Note: This code get's copied to internal SRAM at boot. When the OMAP 165 * Notes:
194 * wakes up it continues execution at the point it went to sleep. 166 * - this code gets copied to internal SRAM at boot and after wake-up
167 * from OFF mode. The execution pointer in SRAM is _omap_sram_idle.
168 * - when the OMAP wakes up it continues at different execution points
169 * depending on the low power mode (non-OFF vs OFF modes),
170 * cf. 'Resume path for xxx mode' comments.
195 */ 171 */
196ENTRY(omap34xx_cpu_suspend) 172ENTRY(omap34xx_cpu_suspend)
197 stmfd sp!, {r0-r12, lr} @ save registers on stack 173 stmfd sp!, {r0-r12, lr} @ save registers on stack
198loop:
199 /*b loop*/ @Enable to debug by stepping through code
200 /* r0 contains restore pointer in sdram */
201 /* r1 contains information about saving context */
202 ldr r4, sdrc_power @ read the SDRC_POWER register
203 ldr r5, [r4] @ read the contents of SDRC_POWER
204 orr r5, r5, #0x40 @ enable self refresh on idle req
205 str r5, [r4] @ write back to SDRC_POWER register
206 174
175 /*
176 * r0 contains restore pointer in sdram
177 * r1 contains information about saving context:
178 * 0 - No context lost
179 * 1 - Only L1 and logic lost
180 * 2 - Only L2 lost
181 * 3 - Both L1 and L2 lost
182 */
183
184 /* Directly jump to WFI is the context save is not required */
207 cmp r1, #0x0 185 cmp r1, #0x0
208 /* If context save is required, do that and execute wfi */ 186 beq omap3_do_wfi
209 bne save_context_wfi 187
188 /* Otherwise fall through to the save context code */
189save_context_wfi:
190 mov r8, r0 @ Store SDRAM address in r8
191 mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register
192 mov r4, #0x1 @ Number of parameters for restore call
193 stmia r8!, {r4-r5} @ Push parameters for restore call
194 mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register
195 stmia r8!, {r4-r5} @ Push parameters for restore call
196
197 /* Check what that target sleep state is from r1 */
198 cmp r1, #0x2 @ Only L2 lost, no need to save context
199 beq clean_caches
200
201l1_logic_lost:
202 /* Store sp and spsr to SDRAM */
203 mov r4, sp
204 mrs r5, spsr
205 mov r6, lr
206 stmia r8!, {r4-r6}
207 /* Save all ARM registers */
208 /* Coprocessor access control register */
209 mrc p15, 0, r6, c1, c0, 2
210 stmia r8!, {r6}
211 /* TTBR0, TTBR1 and Translation table base control */
212 mrc p15, 0, r4, c2, c0, 0
213 mrc p15, 0, r5, c2, c0, 1
214 mrc p15, 0, r6, c2, c0, 2
215 stmia r8!, {r4-r6}
216 /*
217 * Domain access control register, data fault status register,
218 * and instruction fault status register
219 */
220 mrc p15, 0, r4, c3, c0, 0
221 mrc p15, 0, r5, c5, c0, 0
222 mrc p15, 0, r6, c5, c0, 1
223 stmia r8!, {r4-r6}
224 /*
225 * Data aux fault status register, instruction aux fault status,
226 * data fault address register and instruction fault address register
227 */
228 mrc p15, 0, r4, c5, c1, 0
229 mrc p15, 0, r5, c5, c1, 1
230 mrc p15, 0, r6, c6, c0, 0
231 mrc p15, 0, r7, c6, c0, 2
232 stmia r8!, {r4-r7}
233 /*
234 * user r/w thread and process ID, user r/o thread and process ID,
235 * priv only thread and process ID, cache size selection
236 */
237 mrc p15, 0, r4, c13, c0, 2
238 mrc p15, 0, r5, c13, c0, 3
239 mrc p15, 0, r6, c13, c0, 4
240 mrc p15, 2, r7, c0, c0, 0
241 stmia r8!, {r4-r7}
242 /* Data TLB lockdown, instruction TLB lockdown registers */
243 mrc p15, 0, r5, c10, c0, 0
244 mrc p15, 0, r6, c10, c0, 1
245 stmia r8!, {r5-r6}
246 /* Secure or non secure vector base address, FCSE PID, Context PID*/
247 mrc p15, 0, r4, c12, c0, 0
248 mrc p15, 0, r5, c13, c0, 0
249 mrc p15, 0, r6, c13, c0, 1
250 stmia r8!, {r4-r6}
251 /* Primary remap, normal remap registers */
252 mrc p15, 0, r4, c10, c2, 0
253 mrc p15, 0, r5, c10, c2, 1
254 stmia r8!,{r4-r5}
255
256 /* Store current cpsr*/
257 mrs r2, cpsr
258 stmia r8!, {r2}
259
260 mrc p15, 0, r4, c1, c0, 0
261 /* save control register */
262 stmia r8!, {r4}
263
264clean_caches:
265 /*
266 * Clean Data or unified cache to POU
267 * How to invalidate only L1 cache???? - #FIX_ME#
268 * mcr p15, 0, r11, c7, c11, 1
269 */
270 cmp r1, #0x1 @ Check whether L2 inval is required
271 beq omap3_do_wfi
272
273clean_l2:
274 /*
275 * jump out to kernel flush routine
276 * - reuse that code is better
277 * - it executes in a cached space so is faster than refetch per-block
278 * - should be faster and will change with kernel
279 * - 'might' have to copy address, load and jump to it
280 */
281 ldr r1, kernel_flush
282 mov lr, pc
283 bx r1
284
285omap3_do_wfi:
286 ldr r4, sdrc_power @ read the SDRC_POWER register
287 ldr r5, [r4] @ read the contents of SDRC_POWER
288 orr r5, r5, #0x40 @ enable self refresh on idle req
289 str r5, [r4] @ write back to SDRC_POWER register
290
210 /* Data memory barrier and Data sync barrier */ 291 /* Data memory barrier and Data sync barrier */
211 mov r1, #0 292 mov r1, #0
212 mcr p15, 0, r1, c7, c10, 4 293 mcr p15, 0, r1, c7, c10, 4
213 mcr p15, 0, r1, c7, c10, 5 294 mcr p15, 0, r1, c7, c10, 5
214 295
296/*
297 * ===================================
298 * == WFI instruction => Enter idle ==
299 * ===================================
300 */
215 wfi @ wait for interrupt 301 wfi @ wait for interrupt
216 302
303/*
304 * ===================================
305 * == Resume path for non-OFF modes ==
306 * ===================================
307 */
217 nop 308 nop
218 nop 309 nop
219 nop 310 nop
@@ -226,9 +317,30 @@ loop:
226 nop 317 nop
227 bl wait_sdrc_ok 318 bl wait_sdrc_ok
228 319
229 ldmfd sp!, {r0-r12, pc} @ restore regs and return 320/*
321 * ===================================
322 * == Exit point from non-OFF modes ==
323 * ===================================
324 */
325 ldmfd sp!, {r0-r12, pc} @ restore regs and return
326
327
328/*
329 * ==============================
330 * == Resume path for OFF mode ==
331 * ==============================
332 */
333
334/*
335 * The restore_* functions are called by the ROM code
336 * when back from WFI in OFF mode.
337 * Cf. the get_*restore_pointer functions.
338 *
339 * restore_es3: applies to 34xx >= ES3.0
340 * restore_3630: applies to 36xx
341 * restore: common code for 3xxx
342 */
230restore_es3: 343restore_es3:
231 /*b restore_es3*/ @ Enable to debug restore code
232 ldr r5, pm_prepwstst_core_p 344 ldr r5, pm_prepwstst_core_p
233 ldr r4, [r5] 345 ldr r4, [r5]
234 and r4, r4, #0x3 346 and r4, r4, #0x3
@@ -245,82 +357,117 @@ copy_to_sram:
245 bne copy_to_sram 357 bne copy_to_sram
246 ldr r1, sram_base 358 ldr r1, sram_base
247 blx r1 359 blx r1
360 b restore
361
362restore_3630:
363 ldr r1, pm_prepwstst_core_p
364 ldr r2, [r1]
365 and r2, r2, #0x3
366 cmp r2, #0x0 @ Check if previous power state of CORE is OFF
367 bne restore
368 /* Disable RTA before giving control */
369 ldr r1, control_mem_rta
370 mov r2, #OMAP36XX_RTA_DISABLE
371 str r2, [r1]
372
373 /* Fall through to common code for the remaining logic */
374
248restore: 375restore:
249 /* b restore*/ @ Enable to debug restore code 376 /*
250 /* Check what was the reason for mpu reset and store the reason in r9*/ 377 * Check what was the reason for mpu reset and store the reason in r9:
251 /* 1 - Only L1 and logic lost */ 378 * 0 - No context lost
252 /* 2 - Only L2 lost - In this case, we wont be here */ 379 * 1 - Only L1 and logic lost
253 /* 3 - Both L1 and L2 lost */ 380 * 2 - Only L2 lost - In this case, we wont be here
254 ldr r1, pm_pwstctrl_mpu 381 * 3 - Both L1 and L2 lost
382 */
383 ldr r1, pm_pwstctrl_mpu
255 ldr r2, [r1] 384 ldr r2, [r1]
256 and r2, r2, #0x3 385 and r2, r2, #0x3
257 cmp r2, #0x0 @ Check if target power state was OFF or RET 386 cmp r2, #0x0 @ Check if target power state was OFF or RET
258 moveq r9, #0x3 @ MPU OFF => L1 and L2 lost 387 moveq r9, #0x3 @ MPU OFF => L1 and L2 lost
259 movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation 388 movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation
260 bne logic_l1_restore 389 bne logic_l1_restore
390
391 ldr r0, l2dis_3630
392 cmp r0, #0x1 @ should we disable L2 on 3630?
393 bne skipl2dis
394 mrc p15, 0, r0, c1, c0, 1
395 bic r0, r0, #2 @ disable L2 cache
396 mcr p15, 0, r0, c1, c0, 1
397skipl2dis:
261 ldr r0, control_stat 398 ldr r0, control_stat
262 ldr r1, [r0] 399 ldr r1, [r0]
263 and r1, #0x700 400 and r1, #0x700
264 cmp r1, #0x300 401 cmp r1, #0x300
265 beq l2_inv_gp 402 beq l2_inv_gp
266 mov r0, #40 @ set service ID for PPA 403 mov r0, #40 @ set service ID for PPA
267 mov r12, r0 @ copy secure Service ID in r12 404 mov r12, r0 @ copy secure Service ID in r12
268 mov r1, #0 @ set task id for ROM code in r1 405 mov r1, #0 @ set task id for ROM code in r1
269 mov r2, #4 @ set some flags in r2, r6 406 mov r2, #4 @ set some flags in r2, r6
270 mov r6, #0xff 407 mov r6, #0xff
271 adr r3, l2_inv_api_params @ r3 points to dummy parameters 408 adr r3, l2_inv_api_params @ r3 points to dummy parameters
272 mcr p15, 0, r0, c7, c10, 4 @ data write barrier 409 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
273 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 410 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
274 .word 0xE1600071 @ call SMI monitor (smi #1) 411 .word 0xE1600071 @ call SMI monitor (smi #1)
275 /* Write to Aux control register to set some bits */ 412 /* Write to Aux control register to set some bits */
276 mov r0, #42 @ set service ID for PPA 413 mov r0, #42 @ set service ID for PPA
277 mov r12, r0 @ copy secure Service ID in r12 414 mov r12, r0 @ copy secure Service ID in r12
278 mov r1, #0 @ set task id for ROM code in r1 415 mov r1, #0 @ set task id for ROM code in r1
279 mov r2, #4 @ set some flags in r2, r6 416 mov r2, #4 @ set some flags in r2, r6
280 mov r6, #0xff 417 mov r6, #0xff
281 ldr r4, scratchpad_base 418 ldr r4, scratchpad_base
282 ldr r3, [r4, #0xBC] @ r3 points to parameters 419 ldr r3, [r4, #0xBC] @ r3 points to parameters
283 mcr p15, 0, r0, c7, c10, 4 @ data write barrier 420 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
284 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 421 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
285 .word 0xE1600071 @ call SMI monitor (smi #1) 422 .word 0xE1600071 @ call SMI monitor (smi #1)
286 423
287#ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE 424#ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE
288 /* Restore L2 aux control register */ 425 /* Restore L2 aux control register */
289 @ set service ID for PPA 426 @ set service ID for PPA
290 mov r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID 427 mov r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID
291 mov r12, r0 @ copy service ID in r12 428 mov r12, r0 @ copy service ID in r12
292 mov r1, #0 @ set task ID for ROM code in r1 429 mov r1, #0 @ set task ID for ROM code in r1
293 mov r2, #4 @ set some flags in r2, r6 430 mov r2, #4 @ set some flags in r2, r6
294 mov r6, #0xff 431 mov r6, #0xff
295 ldr r4, scratchpad_base 432 ldr r4, scratchpad_base
296 ldr r3, [r4, #0xBC] 433 ldr r3, [r4, #0xBC]
297 adds r3, r3, #8 @ r3 points to parameters 434 adds r3, r3, #8 @ r3 points to parameters
298 mcr p15, 0, r0, c7, c10, 4 @ data write barrier 435 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
299 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 436 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
300 .word 0xE1600071 @ call SMI monitor (smi #1) 437 .word 0xE1600071 @ call SMI monitor (smi #1)
301#endif 438#endif
302 b logic_l1_restore 439 b logic_l1_restore
440
303l2_inv_api_params: 441l2_inv_api_params:
304 .word 0x1, 0x00 442 .word 0x1, 0x00
305l2_inv_gp: 443l2_inv_gp:
306 /* Execute smi to invalidate L2 cache */ 444 /* Execute smi to invalidate L2 cache */
307 mov r12, #0x1 @ set up to invalide L2 445 mov r12, #0x1 @ set up to invalidate L2
308smi: .word 0xE1600070 @ Call SMI monitor (smieq) 446 .word 0xE1600070 @ Call SMI monitor (smieq)
309 /* Write to Aux control register to set some bits */ 447 /* Write to Aux control register to set some bits */
310 ldr r4, scratchpad_base 448 ldr r4, scratchpad_base
311 ldr r3, [r4,#0xBC] 449 ldr r3, [r4,#0xBC]
312 ldr r0, [r3,#4] 450 ldr r0, [r3,#4]
313 mov r12, #0x3 451 mov r12, #0x3
314 .word 0xE1600070 @ Call SMI monitor (smieq) 452 .word 0xE1600070 @ Call SMI monitor (smieq)
315 ldr r4, scratchpad_base 453 ldr r4, scratchpad_base
316 ldr r3, [r4,#0xBC] 454 ldr r3, [r4,#0xBC]
317 ldr r0, [r3,#12] 455 ldr r0, [r3,#12]
318 mov r12, #0x2 456 mov r12, #0x2
319 .word 0xE1600070 @ Call SMI monitor (smieq) 457 .word 0xE1600070 @ Call SMI monitor (smieq)
320logic_l1_restore: 458logic_l1_restore:
459 ldr r1, l2dis_3630
460 cmp r1, #0x1 @ Test if L2 re-enable needed on 3630
461 bne skipl2reen
462 mrc p15, 0, r1, c1, c0, 1
463 orr r1, r1, #2 @ re-enable L2 cache
464 mcr p15, 0, r1, c1, c0, 1
465skipl2reen:
321 mov r1, #0 466 mov r1, #0
322 /* Invalidate all instruction caches to PoU 467 /*
323 * and flush branch target cache */ 468 * Invalidate all instruction caches to PoU
469 * and flush branch target cache
470 */
324 mcr p15, 0, r1, c7, c5, 0 471 mcr p15, 0, r1, c7, c5, 0
325 472
326 ldr r4, scratchpad_base 473 ldr r4, scratchpad_base
@@ -341,33 +488,33 @@ logic_l1_restore:
341 MCR p15, 0, r6, c2, c0, 1 488 MCR p15, 0, r6, c2, c0, 1
342 /* Translation table base control register */ 489 /* Translation table base control register */
343 MCR p15, 0, r7, c2, c0, 2 490 MCR p15, 0, r7, c2, c0, 2
344 /*domain access Control Register */ 491 /* Domain access Control Register */
345 MCR p15, 0, r8, c3, c0, 0 492 MCR p15, 0, r8, c3, c0, 0
346 /* data fault status Register */ 493 /* Data fault status Register */
347 MCR p15, 0, r9, c5, c0, 0 494 MCR p15, 0, r9, c5, c0, 0
348 495
349 ldmia r3!,{r4-r8} 496 ldmia r3!,{r4-r8}
350 /* instruction fault status Register */ 497 /* Instruction fault status Register */
351 MCR p15, 0, r4, c5, c0, 1 498 MCR p15, 0, r4, c5, c0, 1
352 /*Data Auxiliary Fault Status Register */ 499 /* Data Auxiliary Fault Status Register */
353 MCR p15, 0, r5, c5, c1, 0 500 MCR p15, 0, r5, c5, c1, 0
354 /*Instruction Auxiliary Fault Status Register*/ 501 /* Instruction Auxiliary Fault Status Register*/
355 MCR p15, 0, r6, c5, c1, 1 502 MCR p15, 0, r6, c5, c1, 1
356 /*Data Fault Address Register */ 503 /* Data Fault Address Register */
357 MCR p15, 0, r7, c6, c0, 0 504 MCR p15, 0, r7, c6, c0, 0
358 /*Instruction Fault Address Register*/ 505 /* Instruction Fault Address Register*/
359 MCR p15, 0, r8, c6, c0, 2 506 MCR p15, 0, r8, c6, c0, 2
360 ldmia r3!,{r4-r7} 507 ldmia r3!,{r4-r7}
361 508
362 /* user r/w thread and process ID */ 509 /* User r/w thread and process ID */
363 MCR p15, 0, r4, c13, c0, 2 510 MCR p15, 0, r4, c13, c0, 2
364 /* user ro thread and process ID */ 511 /* User ro thread and process ID */
365 MCR p15, 0, r5, c13, c0, 3 512 MCR p15, 0, r5, c13, c0, 3
366 /*Privileged only thread and process ID */ 513 /* Privileged only thread and process ID */
367 MCR p15, 0, r6, c13, c0, 4 514 MCR p15, 0, r6, c13, c0, 4
368 /* cache size selection */ 515 /* Cache size selection */
369 MCR p15, 2, r7, c0, c0, 0 516 MCR p15, 2, r7, c0, c0, 0
370 ldmia r3!,{r4-r8} 517 ldmia r3!,{r4-r8}
371 /* Data TLB lockdown registers */ 518 /* Data TLB lockdown registers */
372 MCR p15, 0, r4, c10, c0, 0 519 MCR p15, 0, r4, c10, c0, 0
373 /* Instruction TLB lockdown registers */ 520 /* Instruction TLB lockdown registers */
@@ -379,26 +526,27 @@ logic_l1_restore:
379 /* Context PID */ 526 /* Context PID */
380 MCR p15, 0, r8, c13, c0, 1 527 MCR p15, 0, r8, c13, c0, 1
381 528
382 ldmia r3!,{r4-r5} 529 ldmia r3!,{r4-r5}
383 /* primary memory remap register */ 530 /* Primary memory remap register */
384 MCR p15, 0, r4, c10, c2, 0 531 MCR p15, 0, r4, c10, c2, 0
385 /*normal memory remap register */ 532 /* Normal memory remap register */
386 MCR p15, 0, r5, c10, c2, 1 533 MCR p15, 0, r5, c10, c2, 1
387 534
388 /* Restore cpsr */ 535 /* Restore cpsr */
389 ldmia r3!,{r4} /*load CPSR from SDRAM*/ 536 ldmia r3!,{r4} @ load CPSR from SDRAM
390 msr cpsr, r4 /*store cpsr */ 537 msr cpsr, r4 @ store cpsr
391 538
392 /* Enabling MMU here */ 539 /* Enabling MMU here */
393 mrc p15, 0, r7, c2, c0, 2 /* Read TTBRControl */ 540 mrc p15, 0, r7, c2, c0, 2 @ Read TTBRControl
394 /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1*/ 541 /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1 */
395 and r7, #0x7 542 and r7, #0x7
396 cmp r7, #0x0 543 cmp r7, #0x0
397 beq usettbr0 544 beq usettbr0
398ttbr_error: 545ttbr_error:
399 /* More work needs to be done to support N[0:2] value other than 0 546 /*
400 * So looping here so that the error can be detected 547 * More work needs to be done to support N[0:2] value other than 0
401 */ 548 * So looping here so that the error can be detected
549 */
402 b ttbr_error 550 b ttbr_error
403usettbr0: 551usettbr0:
404 mrc p15, 0, r2, c2, c0, 0 552 mrc p15, 0, r2, c2, c0, 0
@@ -406,21 +554,25 @@ usettbr0:
406 and r2, r5 554 and r2, r5
407 mov r4, pc 555 mov r4, pc
408 ldr r5, table_index_mask 556 ldr r5, table_index_mask
409 and r4, r5 /* r4 = 31 to 20 bits of pc */ 557 and r4, r5 @ r4 = 31 to 20 bits of pc
410 /* Extract the value to be written to table entry */ 558 /* Extract the value to be written to table entry */
411 ldr r1, table_entry 559 ldr r1, table_entry
412 add r1, r1, r4 /* r1 has value to be written to table entry*/ 560 /* r1 has the value to be written to table entry*/
561 add r1, r1, r4
413 /* Getting the address of table entry to modify */ 562 /* Getting the address of table entry to modify */
414 lsr r4, #18 563 lsr r4, #18
415 add r2, r4 /* r2 has the location which needs to be modified */ 564 /* r2 has the location which needs to be modified */
565 add r2, r4
416 /* Storing previous entry of location being modified */ 566 /* Storing previous entry of location being modified */
417 ldr r5, scratchpad_base 567 ldr r5, scratchpad_base
418 ldr r4, [r2] 568 ldr r4, [r2]
419 str r4, [r5, #0xC0] 569 str r4, [r5, #0xC0]
420 /* Modify the table entry */ 570 /* Modify the table entry */
421 str r1, [r2] 571 str r1, [r2]
422 /* Storing address of entry being modified 572 /*
423 * - will be restored after enabling MMU */ 573 * Storing address of entry being modified
574 * - will be restored after enabling MMU
575 */
424 ldr r5, scratchpad_base 576 ldr r5, scratchpad_base
425 str r2, [r5, #0xC4] 577 str r2, [r5, #0xC4]
426 578
@@ -429,8 +581,11 @@ usettbr0:
429 mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array 581 mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array
430 mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB 582 mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB
431 mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB 583 mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB
432 /* Restore control register but dont enable caches here*/ 584 /*
433 /* Caches will be enabled after restoring MMU table entry */ 585 * Restore control register. This enables the MMU.
586 * The caches and prediction are not enabled here, they
587 * will be enabled after restoring the MMU table entry.
588 */
434 ldmia r3!, {r4} 589 ldmia r3!, {r4}
435 /* Store previous value of control register in scratchpad */ 590 /* Store previous value of control register in scratchpad */
436 str r4, [r5, #0xC8] 591 str r4, [r5, #0xC8]
@@ -438,212 +593,144 @@ usettbr0:
438 and r4, r2 593 and r4, r2
439 mcr p15, 0, r4, c1, c0, 0 594 mcr p15, 0, r4, c1, c0, 0
440 595
441 ldmfd sp!, {r0-r12, pc} @ restore regs and return 596/*
442save_context_wfi: 597 * ==============================
443 /*b save_context_wfi*/ @ enable to debug save code 598 * == Exit point from OFF mode ==
444 mov r8, r0 /* Store SDRAM address in r8 */ 599 * ==============================
445 mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register 600 */
446 mov r4, #0x1 @ Number of parameters for restore call 601 ldmfd sp!, {r0-r12, pc} @ restore regs and return
447 stmia r8!, {r4-r5} @ Push parameters for restore call
448 mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register
449 stmia r8!, {r4-r5} @ Push parameters for restore call
450 /* Check what that target sleep state is:stored in r1*/
451 /* 1 - Only L1 and logic lost */
452 /* 2 - Only L2 lost */
453 /* 3 - Both L1 and L2 lost */
454 cmp r1, #0x2 /* Only L2 lost */
455 beq clean_l2
456 cmp r1, #0x1 /* L2 retained */
457 /* r9 stores whether to clean L2 or not*/
458 moveq r9, #0x0 /* Dont Clean L2 */
459 movne r9, #0x1 /* Clean L2 */
460l1_logic_lost:
461 /* Store sp and spsr to SDRAM */
462 mov r4, sp
463 mrs r5, spsr
464 mov r6, lr
465 stmia r8!, {r4-r6}
466 /* Save all ARM registers */
467 /* Coprocessor access control register */
468 mrc p15, 0, r6, c1, c0, 2
469 stmia r8!, {r6}
470 /* TTBR0, TTBR1 and Translation table base control */
471 mrc p15, 0, r4, c2, c0, 0
472 mrc p15, 0, r5, c2, c0, 1
473 mrc p15, 0, r6, c2, c0, 2
474 stmia r8!, {r4-r6}
475 /* Domain access control register, data fault status register,
476 and instruction fault status register */
477 mrc p15, 0, r4, c3, c0, 0
478 mrc p15, 0, r5, c5, c0, 0
479 mrc p15, 0, r6, c5, c0, 1
480 stmia r8!, {r4-r6}
481 /* Data aux fault status register, instruction aux fault status,
482 datat fault address register and instruction fault address register*/
483 mrc p15, 0, r4, c5, c1, 0
484 mrc p15, 0, r5, c5, c1, 1
485 mrc p15, 0, r6, c6, c0, 0
486 mrc p15, 0, r7, c6, c0, 2
487 stmia r8!, {r4-r7}
488 /* user r/w thread and process ID, user r/o thread and process ID,
489 priv only thread and process ID, cache size selection */
490 mrc p15, 0, r4, c13, c0, 2
491 mrc p15, 0, r5, c13, c0, 3
492 mrc p15, 0, r6, c13, c0, 4
493 mrc p15, 2, r7, c0, c0, 0
494 stmia r8!, {r4-r7}
495 /* Data TLB lockdown, instruction TLB lockdown registers */
496 mrc p15, 0, r5, c10, c0, 0
497 mrc p15, 0, r6, c10, c0, 1
498 stmia r8!, {r5-r6}
499 /* Secure or non secure vector base address, FCSE PID, Context PID*/
500 mrc p15, 0, r4, c12, c0, 0
501 mrc p15, 0, r5, c13, c0, 0
502 mrc p15, 0, r6, c13, c0, 1
503 stmia r8!, {r4-r6}
504 /* Primary remap, normal remap registers */
505 mrc p15, 0, r4, c10, c2, 0
506 mrc p15, 0, r5, c10, c2, 1
507 stmia r8!,{r4-r5}
508 602
509 /* Store current cpsr*/
510 mrs r2, cpsr
511 stmia r8!, {r2}
512 603
513 mrc p15, 0, r4, c1, c0, 0 604/*
514 /* save control register */ 605 * Internal functions
515 stmia r8!, {r4} 606 */
516clean_caches:
517 /* Clean Data or unified cache to POU*/
518 /* How to invalidate only L1 cache???? - #FIX_ME# */
519 /* mcr p15, 0, r11, c7, c11, 1 */
520 cmp r9, #1 /* Check whether L2 inval is required or not*/
521 bne skip_l2_inval
522clean_l2:
523 /* read clidr */
524 mrc p15, 1, r0, c0, c0, 1
525 /* extract loc from clidr */
526 ands r3, r0, #0x7000000
527 /* left align loc bit field */
528 mov r3, r3, lsr #23
529 /* if loc is 0, then no need to clean */
530 beq finished
531 /* start clean at cache level 0 */
532 mov r10, #0
533loop1:
534 /* work out 3x current cache level */
535 add r2, r10, r10, lsr #1
536 /* extract cache type bits from clidr*/
537 mov r1, r0, lsr r2
538 /* mask of the bits for current cache only */
539 and r1, r1, #7
540 /* see what cache we have at this level */
541 cmp r1, #2
542 /* skip if no cache, or just i-cache */
543 blt skip
544 /* select current cache level in cssr */
545 mcr p15, 2, r10, c0, c0, 0
546 /* isb to sych the new cssr&csidr */
547 isb
548 /* read the new csidr */
549 mrc p15, 1, r1, c0, c0, 0
550 /* extract the length of the cache lines */
551 and r2, r1, #7
552 /* add 4 (line length offset) */
553 add r2, r2, #4
554 ldr r4, assoc_mask
555 /* find maximum number on the way size */
556 ands r4, r4, r1, lsr #3
557 /* find bit position of way size increment */
558 clz r5, r4
559 ldr r7, numset_mask
560 /* extract max number of the index size*/
561 ands r7, r7, r1, lsr #13
562loop2:
563 mov r9, r4
564 /* create working copy of max way size*/
565loop3:
566 /* factor way and cache number into r11 */
567 orr r11, r10, r9, lsl r5
568 /* factor index number into r11 */
569 orr r11, r11, r7, lsl r2
570 /*clean & invalidate by set/way */
571 mcr p15, 0, r11, c7, c10, 2
572 /* decrement the way*/
573 subs r9, r9, #1
574 bge loop3
575 /*decrement the index */
576 subs r7, r7, #1
577 bge loop2
578skip:
579 add r10, r10, #2
580 /* increment cache number */
581 cmp r3, r10
582 bgt loop1
583finished:
584 /*swith back to cache level 0 */
585 mov r10, #0
586 /* select current cache level in cssr */
587 mcr p15, 2, r10, c0, c0, 0
588 isb
589skip_l2_inval:
590 /* Data memory barrier and Data sync barrier */
591 mov r1, #0
592 mcr p15, 0, r1, c7, c10, 4
593 mcr p15, 0, r1, c7, c10, 5
594 607
595 wfi @ wait for interrupt 608/* This function implements the erratum ID i443 WA, applies to 34xx >= ES3.0 */
596 nop 609 .text
597 nop 610ENTRY(es3_sdrc_fix)
598 nop 611 ldr r4, sdrc_syscfg @ get config addr
599 nop 612 ldr r5, [r4] @ get value
600 nop 613 tst r5, #0x100 @ is part access blocked
601 nop 614 it eq
602 nop 615 biceq r5, r5, #0x100 @ clear bit if set
603 nop 616 str r5, [r4] @ write back change
604 nop 617 ldr r4, sdrc_mr_0 @ get config addr
605 nop 618 ldr r5, [r4] @ get value
606 bl wait_sdrc_ok 619 str r5, [r4] @ write back change
607 /* restore regs and return */ 620 ldr r4, sdrc_emr2_0 @ get config addr
608 ldmfd sp!, {r0-r12, pc} 621 ldr r5, [r4] @ get value
622 str r5, [r4] @ write back change
623 ldr r4, sdrc_manual_0 @ get config addr
624 mov r5, #0x2 @ autorefresh command
625 str r5, [r4] @ kick off refreshes
626 ldr r4, sdrc_mr_1 @ get config addr
627 ldr r5, [r4] @ get value
628 str r5, [r4] @ write back change
629 ldr r4, sdrc_emr2_1 @ get config addr
630 ldr r5, [r4] @ get value
631 str r5, [r4] @ write back change
632 ldr r4, sdrc_manual_1 @ get config addr
633 mov r5, #0x2 @ autorefresh command
634 str r5, [r4] @ kick off refreshes
635 bx lr
636
637sdrc_syscfg:
638 .word SDRC_SYSCONFIG_P
639sdrc_mr_0:
640 .word SDRC_MR_0_P
641sdrc_emr2_0:
642 .word SDRC_EMR2_0_P
643sdrc_manual_0:
644 .word SDRC_MANUAL_0_P
645sdrc_mr_1:
646 .word SDRC_MR_1_P
647sdrc_emr2_1:
648 .word SDRC_EMR2_1_P
649sdrc_manual_1:
650 .word SDRC_MANUAL_1_P
651ENTRY(es3_sdrc_fix_sz)
652 .word . - es3_sdrc_fix
653
654/*
655 * This function implements the erratum ID i581 WA:
656 * SDRC state restore before accessing the SDRAM
657 *
658 * Only used at return from non-OFF mode. For OFF
659 * mode the ROM code configures the SDRC and
660 * the DPLL before calling the restore code directly
661 * from DDR.
662 */
609 663
610/* Make sure SDRC accesses are ok */ 664/* Make sure SDRC accesses are ok */
611wait_sdrc_ok: 665wait_sdrc_ok:
612 ldr r4, cm_idlest1_core 666
613 ldr r5, [r4] 667/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this */
614 and r5, r5, #0x2 668 ldr r4, cm_idlest_ckgen
615 cmp r5, #0 669wait_dpll3_lock:
616 bne wait_sdrc_ok 670 ldr r5, [r4]
617 ldr r4, sdrc_power 671 tst r5, #1
618 ldr r5, [r4] 672 beq wait_dpll3_lock
619 bic r5, r5, #0x40 673
620 str r5, [r4] 674 ldr r4, cm_idlest1_core
675wait_sdrc_ready:
676 ldr r5, [r4]
677 tst r5, #0x2
678 bne wait_sdrc_ready
679 /* allow DLL powerdown upon hw idle req */
680 ldr r4, sdrc_power
681 ldr r5, [r4]
682 bic r5, r5, #0x40
683 str r5, [r4]
684
685is_dll_in_lock_mode:
686 /* Is dll in lock mode? */
687 ldr r4, sdrc_dlla_ctrl
688 ldr r5, [r4]
689 tst r5, #0x4
690 bxne lr @ Return if locked
691 /* wait till dll locks */
692wait_dll_lock_timed:
693 ldr r4, wait_dll_lock_counter
694 add r4, r4, #1
695 str r4, wait_dll_lock_counter
696 ldr r4, sdrc_dlla_status
697 /* Wait 20uS for lock */
698 mov r6, #8
621wait_dll_lock: 699wait_dll_lock:
622 /* Is dll in lock mode? */ 700 subs r6, r6, #0x1
623 ldr r4, sdrc_dlla_ctrl 701 beq kick_dll
624 ldr r5, [r4] 702 ldr r5, [r4]
625 tst r5, #0x4 703 and r5, r5, #0x4
626 bxne lr 704 cmp r5, #0x4
627 /* wait till dll locks */ 705 bne wait_dll_lock
628 ldr r4, sdrc_dlla_status 706 bx lr @ Return when locked
629 ldr r5, [r4] 707
630 and r5, r5, #0x4 708 /* disable/reenable DLL if not locked */
631 cmp r5, #0x4 709kick_dll:
632 bne wait_dll_lock 710 ldr r4, sdrc_dlla_ctrl
633 bx lr 711 ldr r5, [r4]
712 mov r6, r5
713 bic r6, #(1<<3) @ disable dll
714 str r6, [r4]
715 dsb
716 orr r6, r6, #(1<<3) @ enable dll
717 str r6, [r4]
718 dsb
719 ldr r4, kick_counter
720 add r4, r4, #1
721 str r4, kick_counter
722 b wait_dll_lock_timed
634 723
635cm_idlest1_core: 724cm_idlest1_core:
636 .word CM_IDLEST1_CORE_V 725 .word CM_IDLEST1_CORE_V
726cm_idlest_ckgen:
727 .word CM_IDLEST_CKGEN_V
637sdrc_dlla_status: 728sdrc_dlla_status:
638 .word SDRC_DLLA_STATUS_V 729 .word SDRC_DLLA_STATUS_V
639sdrc_dlla_ctrl: 730sdrc_dlla_ctrl:
640 .word SDRC_DLLA_CTRL_V 731 .word SDRC_DLLA_CTRL_V
641pm_prepwstst_core:
642 .word PM_PREPWSTST_CORE_V
643pm_prepwstst_core_p: 732pm_prepwstst_core_p:
644 .word PM_PREPWSTST_CORE_P 733 .word PM_PREPWSTST_CORE_P
645pm_prepwstst_mpu:
646 .word PM_PREPWSTST_MPU_V
647pm_pwstctrl_mpu: 734pm_pwstctrl_mpu:
648 .word PM_PWSTCTRL_MPU_P 735 .word PM_PWSTCTRL_MPU_P
649scratchpad_base: 736scratchpad_base:
@@ -651,13 +738,7 @@ scratchpad_base:
651sram_base: 738sram_base:
652 .word SRAM_BASE_P + 0x8000 739 .word SRAM_BASE_P + 0x8000
653sdrc_power: 740sdrc_power:
654 .word SDRC_POWER_V 741 .word SDRC_POWER_V
655clk_stabilize_delay:
656 .word 0x000001FF
657assoc_mask:
658 .word 0x3ff
659numset_mask:
660 .word 0x7fff
661ttbrbit_mask: 742ttbrbit_mask:
662 .word 0xFFFFC000 743 .word 0xFFFFC000
663table_index_mask: 744table_index_mask:
@@ -668,5 +749,20 @@ cache_pred_disable_mask:
668 .word 0xFFFFE7FB 749 .word 0xFFFFE7FB
669control_stat: 750control_stat:
670 .word CONTROL_STAT 751 .word CONTROL_STAT
752control_mem_rta:
753 .word CONTROL_MEM_RTA_CTRL
754kernel_flush:
755 .word v7_flush_dcache_all
756l2dis_3630:
757 .word 0
758 /*
759 * When exporting to userspace while the counters are in SRAM,
760 * these 2 words need to be at the end to facilitate retrival!
761 */
762kick_counter:
763 .word 0
764wait_dll_lock_counter:
765 .word 0
766
671ENTRY(omap34xx_cpu_suspend_sz) 767ENTRY(omap34xx_cpu_suspend_sz)
672 .word . - omap34xx_cpu_suspend 768 .word . - omap34xx_cpu_suspend
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
index fa2e5bffbb8e..6983cb4d4cae 100644
--- a/arch/arm/mach-s3c2412/Kconfig
+++ b/arch/arm/mach-s3c2412/Kconfig
@@ -28,9 +28,16 @@ config S3C2412_DMA
28 28
29config S3C2412_PM 29config S3C2412_PM
30 bool 30 bool
31 select S3C2412_PM_SLEEP
31 help 32 help
32 Internal config node to apply S3C2412 power management 33 Internal config node to apply S3C2412 power management
33 34
35config S3C2412_PM_SLEEP
36 bool
37 help
38 Internal config node to apply sleep for S3C2412 power management.
39 Can be selected by another SoCs with similar sleep procedure.
40
34# Note, the S3C2412 IOtiming support is in plat-s3c24xx 41# Note, the S3C2412 IOtiming support is in plat-s3c24xx
35 42
36config S3C2412_CPUFREQ 43config S3C2412_CPUFREQ
diff --git a/arch/arm/mach-s3c2412/Makefile b/arch/arm/mach-s3c2412/Makefile
index 530ec46cbaea..6c48a91ea39e 100644
--- a/arch/arm/mach-s3c2412/Makefile
+++ b/arch/arm/mach-s3c2412/Makefile
@@ -14,7 +14,8 @@ obj-$(CONFIG_CPU_S3C2412) += irq.o
14obj-$(CONFIG_CPU_S3C2412) += clock.o 14obj-$(CONFIG_CPU_S3C2412) += clock.o
15obj-$(CONFIG_CPU_S3C2412) += gpio.o 15obj-$(CONFIG_CPU_S3C2412) += gpio.o
16obj-$(CONFIG_S3C2412_DMA) += dma.o 16obj-$(CONFIG_S3C2412_DMA) += dma.o
17obj-$(CONFIG_S3C2412_PM) += pm.o sleep.o 17obj-$(CONFIG_S3C2412_PM) += pm.o
18obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep.o
18obj-$(CONFIG_S3C2412_CPUFREQ) += cpu-freq.o 19obj-$(CONFIG_S3C2412_CPUFREQ) += cpu-freq.o
19 20
20# Machine support 21# Machine support
diff --git a/arch/arm/mach-s3c2416/Kconfig b/arch/arm/mach-s3c2416/Kconfig
index 27b3e7c9d613..df8d14974c90 100644
--- a/arch/arm/mach-s3c2416/Kconfig
+++ b/arch/arm/mach-s3c2416/Kconfig
@@ -27,6 +27,7 @@ config S3C2416_DMA
27 27
28config S3C2416_PM 28config S3C2416_PM
29 bool 29 bool
30 select S3C2412_PM_SLEEP
30 help 31 help
31 Internal config node to apply S3C2416 power management 32 Internal config node to apply S3C2416 power management
32 33
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 28677caf3613..461aa035afc0 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -378,6 +378,12 @@ static struct max8998_regulator_data aquila_regulators[] = {
378static struct max8998_platform_data aquila_max8998_pdata = { 378static struct max8998_platform_data aquila_max8998_pdata = {
379 .num_regulators = ARRAY_SIZE(aquila_regulators), 379 .num_regulators = ARRAY_SIZE(aquila_regulators),
380 .regulators = aquila_regulators, 380 .regulators = aquila_regulators,
381 .buck1_set1 = S5PV210_GPH0(3),
382 .buck1_set2 = S5PV210_GPH0(4),
383 .buck2_set3 = S5PV210_GPH0(5),
384 .buck1_max_voltage1 = 1200000,
385 .buck1_max_voltage2 = 1200000,
386 .buck2_max_voltage = 1200000,
381}; 387};
382#endif 388#endif
383 389
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index b1dcf964a768..e22d5112fd44 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -518,6 +518,12 @@ static struct max8998_regulator_data goni_regulators[] = {
518static struct max8998_platform_data goni_max8998_pdata = { 518static struct max8998_platform_data goni_max8998_pdata = {
519 .num_regulators = ARRAY_SIZE(goni_regulators), 519 .num_regulators = ARRAY_SIZE(goni_regulators),
520 .regulators = goni_regulators, 520 .regulators = goni_regulators,
521 .buck1_set1 = S5PV210_GPH0(3),
522 .buck1_set2 = S5PV210_GPH0(4),
523 .buck2_set3 = S5PV210_GPH0(5),
524 .buck1_max_voltage1 = 1200000,
525 .buck1_max_voltage2 = 1200000,
526 .buck2_max_voltage = 1200000,
521}; 527};
522#endif 528#endif
523 529
diff --git a/arch/arm/mach-shmobile/include/mach/entry-macro.S b/arch/arm/mach-shmobile/include/mach/entry-macro.S
index a285d13c7416..f428c4db2b60 100644
--- a/arch/arm/mach-shmobile/include/mach/entry-macro.S
+++ b/arch/arm/mach-shmobile/include/mach/entry-macro.S
@@ -1,4 +1,5 @@
1/* 1/*
2 * Copyright (C) 2010 Magnus Damm
2 * Copyright (C) 2008 Renesas Solutions Corp. 3 * Copyright (C) 2008 Renesas Solutions Corp.
3 * 4 *
4 * This program is free software; you can redistribute it and/or modify 5 * This program is free software; you can redistribute it and/or modify
@@ -14,24 +15,45 @@
14 * along with this program; if not, write to the Free Software 15 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
16 */ 17 */
17#include <mach/hardware.h>
18#include <mach/irqs.h> 18#include <mach/irqs.h>
19 19
20#define INTCA_BASE 0xe6980000
21#define INTFLGA_OFFS 0x00000018 /* accept pending interrupt */
22#define INTEVTA_OFFS 0x00000020 /* vector number of accepted interrupt */
23#define INTLVLA_OFFS 0x00000030 /* priority level of accepted interrupt */
24#define INTLVLB_OFFS 0x00000034 /* previous priority level */
25
20 .macro disable_fiq 26 .macro disable_fiq
21 .endm 27 .endm
22 28
23 .macro get_irqnr_preamble, base, tmp 29 .macro get_irqnr_preamble, base, tmp
24 ldr \base, =INTFLGA 30 ldr \base, =INTCA_BASE
25 .endm 31 .endm
26 32
27 .macro arch_ret_to_user, tmp1, tmp2 33 .macro arch_ret_to_user, tmp1, tmp2
28 .endm 34 .endm
29 35
30 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 36 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
31 ldr \irqnr, [\base] 37 /* The single INTFLGA read access below results in the following:
38 *
39 * 1. INTLVLB is updated with old priority value from INTLVLA
40 * 2. Highest priority interrupt is accepted
41 * 3. INTLVLA is updated to contain priority of accepted interrupt
42 * 4. Accepted interrupt vector is stored in INTFLGA and INTEVTA
43 */
44 ldr \irqnr, [\base, #INTFLGA_OFFS]
45
46 /* Restore INTLVLA with the value saved in INTLVLB.
47 * This is required to support interrupt priorities properly.
48 */
49 ldrb \tmp, [\base, #INTLVLB_OFFS]
50 strb \tmp, [\base, #INTLVLA_OFFS]
51
52 /* Handle invalid vector number case */
32 cmp \irqnr, #0 53 cmp \irqnr, #0
33 beq 1000f 54 beq 1000f
34 /* intevt to irq number */ 55
56 /* Convert vector to irq number, same as the evt2irq() macro */
35 lsr \irqnr, \irqnr, #0x5 57 lsr \irqnr, \irqnr, #0x5
36 subs \irqnr, \irqnr, #16 58 subs \irqnr, \irqnr, #16
37 59
diff --git a/arch/arm/mach-shmobile/include/mach/vmalloc.h b/arch/arm/mach-shmobile/include/mach/vmalloc.h
index 4aecf6e3a859..2b8fd8b942fe 100644
--- a/arch/arm/mach-shmobile/include/mach/vmalloc.h
+++ b/arch/arm/mach-shmobile/include/mach/vmalloc.h
@@ -2,6 +2,6 @@
2#define __ASM_MACH_VMALLOC_H 2#define __ASM_MACH_VMALLOC_H
3 3
4/* Vmalloc at ... - 0xe5ffffff */ 4/* Vmalloc at ... - 0xe5ffffff */
5#define VMALLOC_END 0xe6000000 5#define VMALLOC_END 0xe6000000UL
6 6
7#endif /* __ASM_MACH_VMALLOC_H */ 7#endif /* __ASM_MACH_VMALLOC_H */
diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h
index 5905100b29a1..9967d5e855c7 100644
--- a/arch/arm/plat-omap/include/plat/sram.h
+++ b/arch/arm/plat-omap/include/plat/sram.h
@@ -11,6 +11,7 @@
11#ifndef __ARCH_ARM_OMAP_SRAM_H 11#ifndef __ARCH_ARM_OMAP_SRAM_H
12#define __ARCH_ARM_OMAP_SRAM_H 12#define __ARCH_ARM_OMAP_SRAM_H
13 13
14#ifndef __ASSEMBLY__
14extern void * omap_sram_push(void * start, unsigned long size); 15extern void * omap_sram_push(void * start, unsigned long size);
15extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl); 16extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
16 17
@@ -74,4 +75,14 @@ extern void omap_push_sram_idle(void);
74static inline void omap_push_sram_idle(void) {} 75static inline void omap_push_sram_idle(void) {}
75#endif /* CONFIG_PM */ 76#endif /* CONFIG_PM */
76 77
78#endif /* __ASSEMBLY__ */
79
80/*
81 * OMAP2+: define the SRAM PA addresses.
82 * Used by the SRAM management code and the idle sleep code.
83 */
84#define OMAP2_SRAM_PA 0x40200000
85#define OMAP3_SRAM_PA 0x40200000
86#define OMAP4_SRAM_PA 0x40300000
87
77#endif 88#endif
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 819ea0cfb81a..1a686c89d8dd 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -41,15 +41,12 @@
41 41
42#define OMAP1_SRAM_PA 0x20000000 42#define OMAP1_SRAM_PA 0x20000000
43#define OMAP1_SRAM_VA VMALLOC_END 43#define OMAP1_SRAM_VA VMALLOC_END
44#define OMAP2_SRAM_PA 0x40200000 44#define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800)
45#define OMAP2_SRAM_PUB_PA 0x4020f800
46#define OMAP2_SRAM_VA 0xfe400000 45#define OMAP2_SRAM_VA 0xfe400000
47#define OMAP2_SRAM_PUB_VA (OMAP2_SRAM_VA + 0x800) 46#define OMAP2_SRAM_PUB_VA (OMAP2_SRAM_VA + 0x800)
48#define OMAP3_SRAM_PA 0x40200000
49#define OMAP3_SRAM_VA 0xfe400000 47#define OMAP3_SRAM_VA 0xfe400000
50#define OMAP3_SRAM_PUB_PA 0x40208000 48#define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000)
51#define OMAP3_SRAM_PUB_VA (OMAP3_SRAM_VA + 0x8000) 49#define OMAP3_SRAM_PUB_VA (OMAP3_SRAM_VA + 0x8000)
52#define OMAP4_SRAM_PA 0x40300000
53#define OMAP4_SRAM_VA 0xfe400000 50#define OMAP4_SRAM_VA 0xfe400000
54#define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000) 51#define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000)
55#define OMAP4_SRAM_PUB_VA (OMAP4_SRAM_VA + 0x4000) 52#define OMAP4_SRAM_PUB_VA (OMAP4_SRAM_VA + 0x4000)
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index 5a27b1b538f2..eb105e61c746 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -8,7 +8,7 @@ config PLAT_S3C24XX
8 default y 8 default y
9 select NO_IOPORT 9 select NO_IOPORT
10 select ARCH_REQUIRE_GPIOLIB 10 select ARCH_REQUIRE_GPIOLIB
11 select S3C_DEVICE_NAND 11 select S3C_DEV_NAND
12 select S3C_GPIO_CFG_S3C24XX 12 select S3C_GPIO_CFG_S3C24XX
13 help 13 help
14 Base platform code for any Samsung S3C24XX device 14 Base platform code for any Samsung S3C24XX device
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 67a2fa2caa49..0a9b5b8b2a19 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -19,6 +19,8 @@ config MIPS
19 select GENERIC_ATOMIC64 if !64BIT 19 select GENERIC_ATOMIC64 if !64BIT
20 select HAVE_DMA_ATTRS 20 select HAVE_DMA_ATTRS
21 select HAVE_DMA_API_DEBUG 21 select HAVE_DMA_API_DEBUG
22 select HAVE_GENERIC_HARDIRQS
23 select GENERIC_IRQ_PROBE
22 24
23menu "Machine selection" 25menu "Machine selection"
24 26
@@ -1664,6 +1666,28 @@ config PAGE_SIZE_64KB
1664 1666
1665endchoice 1667endchoice
1666 1668
1669config FORCE_MAX_ZONEORDER
1670 int "Maximum zone order"
1671 range 13 64 if SYS_SUPPORTS_HUGETLBFS && PAGE_SIZE_32KB
1672 default "13" if SYS_SUPPORTS_HUGETLBFS && PAGE_SIZE_32KB
1673 range 12 64 if SYS_SUPPORTS_HUGETLBFS && PAGE_SIZE_16KB
1674 default "12" if SYS_SUPPORTS_HUGETLBFS && PAGE_SIZE_16KB
1675 range 11 64
1676 default "11"
1677 help
1678 The kernel memory allocator divides physically contiguous memory
1679 blocks into "zones", where each zone is a power of two number of
1680 pages. This option selects the largest power of two that the kernel
1681 keeps in the memory allocator. If you need to allocate very large
1682 blocks of physically contiguous memory, then you may need to
1683 increase this value.
1684
1685 This config option is actually maximum order plus one. For example,
1686 a value of 11 means that the largest free memory block is 2^10 pages.
1687
1688 The page size is not necessarily 4KB. Keep this in mind
1689 when choosing a value for this option.
1690
1667config BOARD_SCACHE 1691config BOARD_SCACHE
1668 bool 1692 bool
1669 1693
@@ -1922,20 +1946,6 @@ config CPU_R4400_WORKAROUNDS
1922 bool 1946 bool
1923 1947
1924# 1948#
1925# Use the generic interrupt handling code in kernel/irq/:
1926#
1927config GENERIC_HARDIRQS
1928 bool
1929 default y
1930
1931config GENERIC_IRQ_PROBE
1932 bool
1933 default y
1934
1935config IRQ_PER_CPU
1936 bool
1937
1938#
1939# - Highmem only makes sense for the 32-bit kernel. 1949# - Highmem only makes sense for the 32-bit kernel.
1940# - The current highmem code will only work properly on physically indexed 1950# - The current highmem code will only work properly on physically indexed
1941# caches such as R3000, SB1, R7000 or those that look like they're virtually 1951# caches such as R3000, SB1, R7000 or those that look like they're virtually
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index 3691630931d6..9e7814db3d03 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -27,6 +27,7 @@
27static void alchemy_8250_pm(struct uart_port *port, unsigned int state, 27static void alchemy_8250_pm(struct uart_port *port, unsigned int state,
28 unsigned int old_state) 28 unsigned int old_state)
29{ 29{
30#ifdef CONFIG_SERIAL_8250
30 switch (state) { 31 switch (state) {
31 case 0: 32 case 0:
32 if ((__raw_readl(port->membase + UART_MOD_CNTRL) & 3) != 3) { 33 if ((__raw_readl(port->membase + UART_MOD_CNTRL) & 3) != 3) {
@@ -49,6 +50,7 @@ static void alchemy_8250_pm(struct uart_port *port, unsigned int state,
49 serial8250_do_pm(port, state, old_state); 50 serial8250_do_pm(port, state, old_state);
50 break; 51 break;
51 } 52 }
53#endif
52} 54}
53 55
54#define PORT(_base, _irq) \ 56#define PORT(_base, _irq) \
diff --git a/arch/mips/alchemy/devboards/prom.c b/arch/mips/alchemy/devboards/prom.c
index b30df5c97ad3..baeb21385058 100644
--- a/arch/mips/alchemy/devboards/prom.c
+++ b/arch/mips/alchemy/devboards/prom.c
@@ -54,10 +54,9 @@ void __init prom_init(void)
54 54
55 prom_init_cmdline(); 55 prom_init_cmdline();
56 memsize_str = prom_getenv("memsize"); 56 memsize_str = prom_getenv("memsize");
57 if (!memsize_str) 57 if (!memsize_str || strict_strtoul(memsize_str, 0, &memsize))
58 memsize = ALCHEMY_BOARD_DEFAULT_MEMSIZE; 58 memsize = ALCHEMY_BOARD_DEFAULT_MEMSIZE;
59 else 59
60 strict_strtoul(memsize_str, 0, &memsize);
61 add_memory_region(0, memsize, BOOT_MEM_RAM); 60 add_memory_region(0, memsize, BOOT_MEM_RAM);
62} 61}
63 62
diff --git a/arch/mips/ar7/clock.c b/arch/mips/ar7/clock.c
index fc0e7154e8d6..2ca4ada1c291 100644
--- a/arch/mips/ar7/clock.c
+++ b/arch/mips/ar7/clock.c
@@ -239,12 +239,12 @@ static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
239 calculate(base_clock, frequency, &prediv, &postdiv, &mul); 239 calculate(base_clock, frequency, &prediv, &postdiv, &mul);
240 240
241 writel(((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1), &clock->ctrl); 241 writel(((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1), &clock->ctrl);
242 msleep(1); 242 mdelay(1);
243 writel(4, &clock->pll); 243 writel(4, &clock->pll);
244 while (readl(&clock->pll) & PLL_STATUS) 244 while (readl(&clock->pll) & PLL_STATUS)
245 ; 245 ;
246 writel(((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e, &clock->pll); 246 writel(((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e, &clock->pll);
247 msleep(75); 247 mdelay(75);
248} 248}
249 249
250static void __init tnetd7300_init_clocks(void) 250static void __init tnetd7300_init_clocks(void)
@@ -456,7 +456,7 @@ void clk_put(struct clk *clk)
456} 456}
457EXPORT_SYMBOL(clk_put); 457EXPORT_SYMBOL(clk_put);
458 458
459int __init ar7_init_clocks(void) 459void __init ar7_init_clocks(void)
460{ 460{
461 switch (ar7_chip_id()) { 461 switch (ar7_chip_id()) {
462 case AR7_CHIP_7100: 462 case AR7_CHIP_7100:
@@ -472,7 +472,4 @@ int __init ar7_init_clocks(void)
472 } 472 }
473 /* adjust vbus clock rate */ 473 /* adjust vbus clock rate */
474 vbus_clk.rate = bus_clk.rate / 2; 474 vbus_clk.rate = bus_clk.rate / 2;
475
476 return 0;
477} 475}
478arch_initcall(ar7_init_clocks);
diff --git a/arch/mips/ar7/time.c b/arch/mips/ar7/time.c
index 5fb8a0134085..22c93213b233 100644
--- a/arch/mips/ar7/time.c
+++ b/arch/mips/ar7/time.c
@@ -30,6 +30,9 @@ void __init plat_time_init(void)
30{ 30{
31 struct clk *cpu_clk; 31 struct clk *cpu_clk;
32 32
33 /* Initialize ar7 clocks so the CPU clock frequency is correct */
34 ar7_init_clocks();
35
33 cpu_clk = clk_get(NULL, "cpu"); 36 cpu_clk = clk_get(NULL, "cpu");
34 if (IS_ERR(cpu_clk)) { 37 if (IS_ERR(cpu_clk)) {
35 printk(KERN_ERR "unable to get cpu clock\n"); 38 printk(KERN_ERR "unable to get cpu clock\n");
diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c
index b1aee33efd11..c95f90bf734c 100644
--- a/arch/mips/bcm47xx/setup.c
+++ b/arch/mips/bcm47xx/setup.c
@@ -32,7 +32,6 @@
32#include <asm/reboot.h> 32#include <asm/reboot.h>
33#include <asm/time.h> 33#include <asm/time.h>
34#include <bcm47xx.h> 34#include <bcm47xx.h>
35#include <asm/fw/cfe/cfe_api.h>
36#include <asm/mach-bcm47xx/nvram.h> 35#include <asm/mach-bcm47xx/nvram.h>
37 36
38struct ssb_bus ssb_bcm47xx; 37struct ssb_bus ssb_bcm47xx;
@@ -57,68 +56,112 @@ static void bcm47xx_machine_halt(void)
57 cpu_relax(); 56 cpu_relax();
58} 57}
59 58
60static void str2eaddr(char *str, char *dest) 59#define READ_FROM_NVRAM(_outvar, name, buf) \
61{ 60 if (nvram_getenv(name, buf, sizeof(buf)) >= 0)\
62 int i = 0; 61 sprom->_outvar = simple_strtoul(buf, NULL, 0);
63 62
64 if (str == NULL) { 63static void bcm47xx_fill_sprom(struct ssb_sprom *sprom)
65 memset(dest, 0, 6); 64{
66 return; 65 char buf[100];
66 u32 boardflags;
67
68 memset(sprom, 0, sizeof(struct ssb_sprom));
69
70 sprom->revision = 1; /* Fallback: Old hardware does not define this. */
71 READ_FROM_NVRAM(revision, "sromrev", buf);
72 if (nvram_getenv("il0macaddr", buf, sizeof(buf)) >= 0)
73 nvram_parse_macaddr(buf, sprom->il0mac);
74 if (nvram_getenv("et0macaddr", buf, sizeof(buf)) >= 0)
75 nvram_parse_macaddr(buf, sprom->et0mac);
76 if (nvram_getenv("et1macaddr", buf, sizeof(buf)) >= 0)
77 nvram_parse_macaddr(buf, sprom->et1mac);
78 READ_FROM_NVRAM(et0phyaddr, "et0phyaddr", buf);
79 READ_FROM_NVRAM(et1phyaddr, "et1phyaddr", buf);
80 READ_FROM_NVRAM(et0mdcport, "et0mdcport", buf);
81 READ_FROM_NVRAM(et1mdcport, "et1mdcport", buf);
82 READ_FROM_NVRAM(board_rev, "boardrev", buf);
83 READ_FROM_NVRAM(country_code, "ccode", buf);
84 READ_FROM_NVRAM(ant_available_a, "aa5g", buf);
85 READ_FROM_NVRAM(ant_available_bg, "aa2g", buf);
86 READ_FROM_NVRAM(pa0b0, "pa0b0", buf);
87 READ_FROM_NVRAM(pa0b1, "pa0b1", buf);
88 READ_FROM_NVRAM(pa0b2, "pa0b2", buf);
89 READ_FROM_NVRAM(pa1b0, "pa1b0", buf);
90 READ_FROM_NVRAM(pa1b1, "pa1b1", buf);
91 READ_FROM_NVRAM(pa1b2, "pa1b2", buf);
92 READ_FROM_NVRAM(pa1lob0, "pa1lob0", buf);
93 READ_FROM_NVRAM(pa1lob2, "pa1lob1", buf);
94 READ_FROM_NVRAM(pa1lob1, "pa1lob2", buf);
95 READ_FROM_NVRAM(pa1hib0, "pa1hib0", buf);
96 READ_FROM_NVRAM(pa1hib2, "pa1hib1", buf);
97 READ_FROM_NVRAM(pa1hib1, "pa1hib2", buf);
98 READ_FROM_NVRAM(gpio0, "wl0gpio0", buf);
99 READ_FROM_NVRAM(gpio1, "wl0gpio1", buf);
100 READ_FROM_NVRAM(gpio2, "wl0gpio2", buf);
101 READ_FROM_NVRAM(gpio3, "wl0gpio3", buf);
102 READ_FROM_NVRAM(maxpwr_bg, "pa0maxpwr", buf);
103 READ_FROM_NVRAM(maxpwr_al, "pa1lomaxpwr", buf);
104 READ_FROM_NVRAM(maxpwr_a, "pa1maxpwr", buf);
105 READ_FROM_NVRAM(maxpwr_ah, "pa1himaxpwr", buf);
106 READ_FROM_NVRAM(itssi_a, "pa1itssit", buf);
107 READ_FROM_NVRAM(itssi_bg, "pa0itssit", buf);
108 READ_FROM_NVRAM(tri2g, "tri2g", buf);
109 READ_FROM_NVRAM(tri5gl, "tri5gl", buf);
110 READ_FROM_NVRAM(tri5g, "tri5g", buf);
111 READ_FROM_NVRAM(tri5gh, "tri5gh", buf);
112 READ_FROM_NVRAM(rxpo2g, "rxpo2g", buf);
113 READ_FROM_NVRAM(rxpo5g, "rxpo5g", buf);
114 READ_FROM_NVRAM(rssisav2g, "rssisav2g", buf);
115 READ_FROM_NVRAM(rssismc2g, "rssismc2g", buf);
116 READ_FROM_NVRAM(rssismf2g, "rssismf2g", buf);
117 READ_FROM_NVRAM(bxa2g, "bxa2g", buf);
118 READ_FROM_NVRAM(rssisav5g, "rssisav5g", buf);
119 READ_FROM_NVRAM(rssismc5g, "rssismc5g", buf);
120 READ_FROM_NVRAM(rssismf5g, "rssismf5g", buf);
121 READ_FROM_NVRAM(bxa5g, "bxa5g", buf);
122 READ_FROM_NVRAM(cck2gpo, "cck2gpo", buf);
123 READ_FROM_NVRAM(ofdm2gpo, "ofdm2gpo", buf);
124 READ_FROM_NVRAM(ofdm5glpo, "ofdm5glpo", buf);
125 READ_FROM_NVRAM(ofdm5gpo, "ofdm5gpo", buf);
126 READ_FROM_NVRAM(ofdm5ghpo, "ofdm5ghpo", buf);
127
128 if (nvram_getenv("boardflags", buf, sizeof(buf)) >= 0) {
129 boardflags = simple_strtoul(buf, NULL, 0);
130 if (boardflags) {
131 sprom->boardflags_lo = (boardflags & 0x0000FFFFU);
132 sprom->boardflags_hi = (boardflags & 0xFFFF0000U) >> 16;
133 }
67 } 134 }
68 135 if (nvram_getenv("boardflags2", buf, sizeof(buf)) >= 0) {
69 for (;;) { 136 boardflags = simple_strtoul(buf, NULL, 0);
70 dest[i++] = (char) simple_strtoul(str, NULL, 16); 137 if (boardflags) {
71 str += 2; 138 sprom->boardflags2_lo = (boardflags & 0x0000FFFFU);
72 if (!*str++ || i == 6) 139 sprom->boardflags2_hi = (boardflags & 0xFFFF0000U) >> 16;
73 break; 140 }
74 } 141 }
75} 142}
76 143
77static int bcm47xx_get_invariants(struct ssb_bus *bus, 144static int bcm47xx_get_invariants(struct ssb_bus *bus,
78 struct ssb_init_invariants *iv) 145 struct ssb_init_invariants *iv)
79{ 146{
80 char buf[100]; 147 char buf[20];
81 148
82 /* Fill boardinfo structure */ 149 /* Fill boardinfo structure */
83 memset(&(iv->boardinfo), 0 , sizeof(struct ssb_boardinfo)); 150 memset(&(iv->boardinfo), 0 , sizeof(struct ssb_boardinfo));
84 151
85 if (cfe_getenv("boardvendor", buf, sizeof(buf)) >= 0 || 152 if (nvram_getenv("boardvendor", buf, sizeof(buf)) >= 0)
86 nvram_getenv("boardvendor", buf, sizeof(buf)) >= 0) 153 iv->boardinfo.vendor = (u16)simple_strtoul(buf, NULL, 0);
87 iv->boardinfo.type = (u16)simple_strtoul(buf, NULL, 0); 154 else
88 if (cfe_getenv("boardtype", buf, sizeof(buf)) >= 0 || 155 iv->boardinfo.vendor = SSB_BOARDVENDOR_BCM;
89 nvram_getenv("boardtype", buf, sizeof(buf)) >= 0) 156 if (nvram_getenv("boardtype", buf, sizeof(buf)) >= 0)
90 iv->boardinfo.type = (u16)simple_strtoul(buf, NULL, 0); 157 iv->boardinfo.type = (u16)simple_strtoul(buf, NULL, 0);
91 if (cfe_getenv("boardrev", buf, sizeof(buf)) >= 0 || 158 if (nvram_getenv("boardrev", buf, sizeof(buf)) >= 0)
92 nvram_getenv("boardrev", buf, sizeof(buf)) >= 0)
93 iv->boardinfo.rev = (u16)simple_strtoul(buf, NULL, 0); 159 iv->boardinfo.rev = (u16)simple_strtoul(buf, NULL, 0);
94 160
95 /* Fill sprom structure */ 161 bcm47xx_fill_sprom(&iv->sprom);
96 memset(&(iv->sprom), 0, sizeof(struct ssb_sprom));
97 iv->sprom.revision = 3;
98
99 if (cfe_getenv("et0macaddr", buf, sizeof(buf)) >= 0 ||
100 nvram_getenv("et0macaddr", buf, sizeof(buf)) >= 0)
101 str2eaddr(buf, iv->sprom.et0mac);
102 162
103 if (cfe_getenv("et1macaddr", buf, sizeof(buf)) >= 0 || 163 if (nvram_getenv("cardbus", buf, sizeof(buf)) >= 0)
104 nvram_getenv("et1macaddr", buf, sizeof(buf)) >= 0) 164 iv->has_cardbus_slot = !!simple_strtoul(buf, NULL, 10);
105 str2eaddr(buf, iv->sprom.et1mac);
106
107 if (cfe_getenv("et0phyaddr", buf, sizeof(buf)) >= 0 ||
108 nvram_getenv("et0phyaddr", buf, sizeof(buf)) >= 0)
109 iv->sprom.et0phyaddr = simple_strtoul(buf, NULL, 0);
110
111 if (cfe_getenv("et1phyaddr", buf, sizeof(buf)) >= 0 ||
112 nvram_getenv("et1phyaddr", buf, sizeof(buf)) >= 0)
113 iv->sprom.et1phyaddr = simple_strtoul(buf, NULL, 0);
114
115 if (cfe_getenv("et0mdcport", buf, sizeof(buf)) >= 0 ||
116 nvram_getenv("et0mdcport", buf, sizeof(buf)) >= 0)
117 iv->sprom.et0mdcport = simple_strtoul(buf, NULL, 10);
118
119 if (cfe_getenv("et1mdcport", buf, sizeof(buf)) >= 0 ||
120 nvram_getenv("et1mdcport", buf, sizeof(buf)) >= 0)
121 iv->sprom.et1mdcport = simple_strtoul(buf, NULL, 10);
122 165
123 return 0; 166 return 0;
124} 167}
@@ -126,12 +169,28 @@ static int bcm47xx_get_invariants(struct ssb_bus *bus,
126void __init plat_mem_setup(void) 169void __init plat_mem_setup(void)
127{ 170{
128 int err; 171 int err;
172 char buf[100];
173 struct ssb_mipscore *mcore;
129 174
130 err = ssb_bus_ssbbus_register(&ssb_bcm47xx, SSB_ENUM_BASE, 175 err = ssb_bus_ssbbus_register(&ssb_bcm47xx, SSB_ENUM_BASE,
131 bcm47xx_get_invariants); 176 bcm47xx_get_invariants);
132 if (err) 177 if (err)
133 panic("Failed to initialize SSB bus (err %d)\n", err); 178 panic("Failed to initialize SSB bus (err %d)\n", err);
134 179
180 mcore = &ssb_bcm47xx.mipscore;
181 if (nvram_getenv("kernel_args", buf, sizeof(buf)) >= 0) {
182 if (strstr(buf, "console=ttyS1")) {
183 struct ssb_serial_port port;
184
185 printk(KERN_DEBUG "Swapping serial ports!\n");
186 /* swap serial ports */
187 memcpy(&port, &mcore->serial_ports[0], sizeof(port));
188 memcpy(&mcore->serial_ports[0], &mcore->serial_ports[1],
189 sizeof(port));
190 memcpy(&mcore->serial_ports[1], &port, sizeof(port));
191 }
192 }
193
135 _machine_restart = bcm47xx_machine_restart; 194 _machine_restart = bcm47xx_machine_restart;
136 _machine_halt = bcm47xx_machine_halt; 195 _machine_halt = bcm47xx_machine_halt;
137 pm_power_off = bcm47xx_machine_halt; 196 pm_power_off = bcm47xx_machine_halt;
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 06d59dcbe243..86877539c6e8 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -111,8 +111,8 @@
111 * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM 111 * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
112 */ 112 */
113 113
114#define PRID_IMP_BMIPS4KC 0x4000 114#define PRID_IMP_BMIPS32_REV4 0x4000
115#define PRID_IMP_BMIPS32 0x8000 115#define PRID_IMP_BMIPS32_REV8 0x8000
116#define PRID_IMP_BMIPS3300 0x9000 116#define PRID_IMP_BMIPS3300 0x9000
117#define PRID_IMP_BMIPS3300_ALT 0x9100 117#define PRID_IMP_BMIPS3300_ALT 0x9100
118#define PRID_IMP_BMIPS3300_BUG 0x0000 118#define PRID_IMP_BMIPS3300_BUG 0x0000
diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h
index fd1d39eb7431..455c0ac7d4ea 100644
--- a/arch/mips/include/asm/elf.h
+++ b/arch/mips/include/asm/elf.h
@@ -249,7 +249,8 @@ extern struct mips_abi mips_abi_n32;
249 249
250#define SET_PERSONALITY(ex) \ 250#define SET_PERSONALITY(ex) \
251do { \ 251do { \
252 set_personality(PER_LINUX); \ 252 if (personality(current->personality) != PER_LINUX) \
253 set_personality(PER_LINUX); \
253 \ 254 \
254 current->thread.abi = &mips_abi; \ 255 current->thread.abi = &mips_abi; \
255} while (0) 256} while (0)
@@ -296,6 +297,8 @@ do { \
296 297
297#define SET_PERSONALITY(ex) \ 298#define SET_PERSONALITY(ex) \
298do { \ 299do { \
300 unsigned int p; \
301 \
299 clear_thread_flag(TIF_32BIT_REGS); \ 302 clear_thread_flag(TIF_32BIT_REGS); \
300 clear_thread_flag(TIF_32BIT_ADDR); \ 303 clear_thread_flag(TIF_32BIT_ADDR); \
301 \ 304 \
@@ -304,7 +307,8 @@ do { \
304 else \ 307 else \
305 current->thread.abi = &mips_abi; \ 308 current->thread.abi = &mips_abi; \
306 \ 309 \
307 if (current->personality != PER_LINUX32) \ 310 p = personality(current->personality); \
311 if (p != PER_LINUX32 && p != PER_LINUX) \
308 set_personality(PER_LINUX); \ 312 set_personality(PER_LINUX); \
309} while (0) 313} while (0)
310 314
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index c98bf514ec7d..5b017f23e243 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -329,10 +329,14 @@ static inline void pfx##write##bwlq(type val, \
329 "dsrl32 %L0, %L0, 0" "\n\t" \ 329 "dsrl32 %L0, %L0, 0" "\n\t" \
330 "dsll32 %M0, %M0, 0" "\n\t" \ 330 "dsll32 %M0, %M0, 0" "\n\t" \
331 "or %L0, %L0, %M0" "\n\t" \ 331 "or %L0, %L0, %M0" "\n\t" \
332 ".set push" "\n\t" \
333 ".set noreorder" "\n\t" \
334 ".set nomacro" "\n\t" \
332 "sd %L0, %2" "\n\t" \ 335 "sd %L0, %2" "\n\t" \
336 ".set pop" "\n\t" \
333 ".set mips0" "\n" \ 337 ".set mips0" "\n" \
334 : "=r" (__tmp) \ 338 : "=r" (__tmp) \
335 : "0" (__val), "m" (*__mem)); \ 339 : "0" (__val), "R" (*__mem)); \
336 if (irq) \ 340 if (irq) \
337 local_irq_restore(__flags); \ 341 local_irq_restore(__flags); \
338 } else \ 342 } else \
@@ -355,12 +359,16 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
355 local_irq_save(__flags); \ 359 local_irq_save(__flags); \
356 __asm__ __volatile__( \ 360 __asm__ __volatile__( \
357 ".set mips3" "\t\t# __readq" "\n\t" \ 361 ".set mips3" "\t\t# __readq" "\n\t" \
362 ".set push" "\n\t" \
363 ".set noreorder" "\n\t" \
364 ".set nomacro" "\n\t" \
358 "ld %L0, %1" "\n\t" \ 365 "ld %L0, %1" "\n\t" \
366 ".set pop" "\n\t" \
359 "dsra32 %M0, %L0, 0" "\n\t" \ 367 "dsra32 %M0, %L0, 0" "\n\t" \
360 "sll %L0, %L0, 0" "\n\t" \ 368 "sll %L0, %L0, 0" "\n\t" \
361 ".set mips0" "\n" \ 369 ".set mips0" "\n" \
362 : "=r" (__val) \ 370 : "=r" (__val) \
363 : "m" (*__mem)); \ 371 : "R" (*__mem)); \
364 if (irq) \ 372 if (irq) \
365 local_irq_restore(__flags); \ 373 local_irq_restore(__flags); \
366 } else { \ 374 } else { \
diff --git a/arch/mips/include/asm/mach-ar7/ar7.h b/arch/mips/include/asm/mach-ar7/ar7.h
index 7919d76186bf..07d3fadb2443 100644
--- a/arch/mips/include/asm/mach-ar7/ar7.h
+++ b/arch/mips/include/asm/mach-ar7/ar7.h
@@ -201,7 +201,6 @@ static inline void ar7_device_off(u32 bit)
201} 201}
202 202
203int __init ar7_gpio_init(void); 203int __init ar7_gpio_init(void);
204 204void __init ar7_init_clocks(void);
205int __init ar7_gpio_init(void);
206 205
207#endif /* __AR7_H__ */ 206#endif /* __AR7_H__ */
diff --git a/arch/mips/include/asm/mach-bcm47xx/nvram.h b/arch/mips/include/asm/mach-bcm47xx/nvram.h
index c58ebd8bc155..9759588ba3cf 100644
--- a/arch/mips/include/asm/mach-bcm47xx/nvram.h
+++ b/arch/mips/include/asm/mach-bcm47xx/nvram.h
@@ -12,6 +12,7 @@
12#define __NVRAM_H 12#define __NVRAM_H
13 13
14#include <linux/types.h> 14#include <linux/types.h>
15#include <linux/kernel.h>
15 16
16struct nvram_header { 17struct nvram_header {
17 u32 magic; 18 u32 magic;
@@ -36,4 +37,10 @@ struct nvram_header {
36 37
37extern int nvram_getenv(char *name, char *val, size_t val_len); 38extern int nvram_getenv(char *name, char *val, size_t val_len);
38 39
40static inline void nvram_parse_macaddr(char *buf, u8 *macaddr)
41{
42 sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0], &macaddr[1],
43 &macaddr[2], &macaddr[3], &macaddr[4], &macaddr[5]);
44}
45
39#endif 46#endif
diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c
index 5742bb4d78f4..5c0a3575877c 100644
--- a/arch/mips/jz4740/board-qi_lb60.c
+++ b/arch/mips/jz4740/board-qi_lb60.c
@@ -5,7 +5,7 @@
5 * 5 *
6 * Copyright (c) 2009 Qi Hardware inc., 6 * Copyright (c) 2009 Qi Hardware inc.,
7 * Author: Xiangfu Liu <xiangfu@qi-hardware.com> 7 * Author: Xiangfu Liu <xiangfu@qi-hardware.com>
8 * Copyright 2010, Lars-Petrer Clausen <lars@metafoo.de> 8 * Copyright 2010, Lars-Peter Clausen <lars@metafoo.de>
9 * 9 *
10 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 or later 11 * it under the terms of the GNU General Public License version 2 or later
@@ -235,7 +235,7 @@ static const unsigned int qi_lb60_keypad_rows[] = {
235 QI_LB60_GPIO_KEYIN(3), 235 QI_LB60_GPIO_KEYIN(3),
236 QI_LB60_GPIO_KEYIN(4), 236 QI_LB60_GPIO_KEYIN(4),
237 QI_LB60_GPIO_KEYIN(5), 237 QI_LB60_GPIO_KEYIN(5),
238 QI_LB60_GPIO_KEYIN(7), 238 QI_LB60_GPIO_KEYIN(6),
239 QI_LB60_GPIO_KEYIN8, 239 QI_LB60_GPIO_KEYIN8,
240}; 240};
241 241
diff --git a/arch/mips/jz4740/platform.c b/arch/mips/jz4740/platform.c
index 95bc2b5b14f1..1cc9e544d16b 100644
--- a/arch/mips/jz4740/platform.c
+++ b/arch/mips/jz4740/platform.c
@@ -208,7 +208,7 @@ struct platform_device jz4740_i2s_device = {
208 208
209/* PCM */ 209/* PCM */
210struct platform_device jz4740_pcm_device = { 210struct platform_device jz4740_pcm_device = {
211 .name = "jz4740-pcm", 211 .name = "jz4740-pcm-audio",
212 .id = -1, 212 .id = -1,
213}; 213};
214 214
diff --git a/arch/mips/jz4740/prom.c b/arch/mips/jz4740/prom.c
index cfeac15eb2e4..4a70407f55bb 100644
--- a/arch/mips/jz4740/prom.c
+++ b/arch/mips/jz4740/prom.c
@@ -23,7 +23,7 @@
23#include <asm/bootinfo.h> 23#include <asm/bootinfo.h>
24#include <asm/mach-jz4740/base.h> 24#include <asm/mach-jz4740/base.h>
25 25
26void jz4740_init_cmdline(int argc, char *argv[]) 26static __init void jz4740_init_cmdline(int argc, char *argv[])
27{ 27{
28 unsigned int count = COMMAND_LINE_SIZE - 1; 28 unsigned int count = COMMAND_LINE_SIZE - 1;
29 int i; 29 int i;
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 2f4d7a99bcc2..98c5a9737c14 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -32,7 +32,7 @@ static int mips_next_event(unsigned long delta,
32 cnt = read_c0_count(); 32 cnt = read_c0_count();
33 cnt += delta; 33 cnt += delta;
34 write_c0_compare(cnt); 34 write_c0_compare(cnt);
35 res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0; 35 res = ((int)(read_c0_count() - cnt) >= 0) ? -ETIME : 0;
36 return res; 36 return res;
37} 37}
38 38
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 71620e19827a..68dae7b6b5db 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -905,7 +905,8 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
905{ 905{
906 decode_configs(c); 906 decode_configs(c);
907 switch (c->processor_id & 0xff00) { 907 switch (c->processor_id & 0xff00) {
908 case PRID_IMP_BMIPS32: 908 case PRID_IMP_BMIPS32_REV4:
909 case PRID_IMP_BMIPS32_REV8:
909 c->cputype = CPU_BMIPS32; 910 c->cputype = CPU_BMIPS32;
910 __cpu_name[cpu] = "Broadcom BMIPS32"; 911 __cpu_name[cpu] = "Broadcom BMIPS32";
911 break; 912 break;
@@ -933,10 +934,6 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
933 __cpu_name[cpu] = "Broadcom BMIPS5000"; 934 __cpu_name[cpu] = "Broadcom BMIPS5000";
934 c->options |= MIPS_CPU_ULRI; 935 c->options |= MIPS_CPU_ULRI;
935 break; 936 break;
936 case PRID_IMP_BMIPS4KC:
937 c->cputype = CPU_4KC;
938 __cpu_name[cpu] = "MIPS 4Kc";
939 break;
940 } 937 }
941} 938}
942 939
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index 6343b4a5b835..876a75cc376f 100644
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -251,14 +251,15 @@ SYSCALL_DEFINE5(n32_msgrcv, int, msqid, u32, msgp, size_t, msgsz,
251 251
252SYSCALL_DEFINE1(32_personality, unsigned long, personality) 252SYSCALL_DEFINE1(32_personality, unsigned long, personality)
253{ 253{
254 unsigned int p = personality & 0xffffffff;
254 int ret; 255 int ret;
255 personality &= 0xffffffff; 256
256 if (personality(current->personality) == PER_LINUX32 && 257 if (personality(current->personality) == PER_LINUX32 &&
257 personality == PER_LINUX) 258 personality(p) == PER_LINUX)
258 personality = PER_LINUX32; 259 p = (p & ~PER_MASK) | PER_LINUX32;
259 ret = sys_personality(personality); 260 ret = sys_personality(p);
260 if (ret == PER_LINUX32) 261 if (ret != -1 && personality(ret) == PER_LINUX32)
261 ret = PER_LINUX; 262 ret = (ret & ~PER_MASK) | PER_LINUX;
262 return ret; 263 return ret;
263} 264}
264 265
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index 99960940d4a4..ae167df73ddd 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -142,7 +142,6 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
142 childregs->regs[7] = 0; /* Clear error flag */ 142 childregs->regs[7] = 0; /* Clear error flag */
143 143
144 childregs->regs[2] = 0; /* Child gets zero as return value */ 144 childregs->regs[2] = 0; /* Child gets zero as return value */
145 regs->regs[2] = p->pid;
146 145
147 if (childregs->cp0_status & ST0_CU0) { 146 if (childregs->cp0_status & ST0_CU0) {
148 childregs->regs[28] = (unsigned long) ti; 147 childregs->regs[28] = (unsigned long) ti;
diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c
index e000b278f024..9dbe58368953 100644
--- a/arch/mips/kernel/prom.c
+++ b/arch/mips/kernel/prom.c
@@ -100,7 +100,7 @@ void __init device_tree_init(void)
100 return; 100 return;
101 101
102 base = virt_to_phys((void *)initial_boot_params); 102 base = virt_to_phys((void *)initial_boot_params);
103 size = initial_boot_params->totalsize; 103 size = be32_to_cpu(initial_boot_params->totalsize);
104 104
105 /* Before we do anything, lets reserve the dt blob */ 105 /* Before we do anything, lets reserve the dt blob */
106 reserve_mem_mach(base, size); 106 reserve_mem_mach(base, size);
diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index 43e7cdc5ded2..c0e81418ba21 100644
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -153,7 +153,7 @@ static void __cpuinit vsmp_init_secondary(void)
153{ 153{
154 extern int gic_present; 154 extern int gic_present;
155 155
156 /* This is Malta specific: IPI,performance and timer inetrrupts */ 156 /* This is Malta specific: IPI,performance and timer interrupts */
157 if (gic_present) 157 if (gic_present)
158 change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | 158 change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 |
159 STATUSF_IP6 | STATUSF_IP7); 159 STATUSF_IP6 | STATUSF_IP7);
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 8e9fbe75894e..e97104302541 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -83,7 +83,8 @@ extern asmlinkage void handle_mcheck(void);
83extern asmlinkage void handle_reserved(void); 83extern asmlinkage void handle_reserved(void);
84 84
85extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, 85extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
86 struct mips_fpu_struct *ctx, int has_fpu); 86 struct mips_fpu_struct *ctx, int has_fpu,
87 void *__user *fault_addr);
87 88
88void (*board_be_init)(void); 89void (*board_be_init)(void);
89int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 90int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
@@ -661,12 +662,36 @@ asmlinkage void do_ov(struct pt_regs *regs)
661 force_sig_info(SIGFPE, &info, current); 662 force_sig_info(SIGFPE, &info, current);
662} 663}
663 664
665static int process_fpemu_return(int sig, void __user *fault_addr)
666{
667 if (sig == SIGSEGV || sig == SIGBUS) {
668 struct siginfo si = {0};
669 si.si_addr = fault_addr;
670 si.si_signo = sig;
671 if (sig == SIGSEGV) {
672 if (find_vma(current->mm, (unsigned long)fault_addr))
673 si.si_code = SEGV_ACCERR;
674 else
675 si.si_code = SEGV_MAPERR;
676 } else {
677 si.si_code = BUS_ADRERR;
678 }
679 force_sig_info(sig, &si, current);
680 return 1;
681 } else if (sig) {
682 force_sig(sig, current);
683 return 1;
684 } else {
685 return 0;
686 }
687}
688
664/* 689/*
665 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX 690 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
666 */ 691 */
667asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) 692asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
668{ 693{
669 siginfo_t info; 694 siginfo_t info = {0};
670 695
671 if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE) 696 if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE)
672 == NOTIFY_STOP) 697 == NOTIFY_STOP)
@@ -675,6 +700,7 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
675 700
676 if (fcr31 & FPU_CSR_UNI_X) { 701 if (fcr31 & FPU_CSR_UNI_X) {
677 int sig; 702 int sig;
703 void __user *fault_addr = NULL;
678 704
679 /* 705 /*
680 * Unimplemented operation exception. If we've got the full 706 * Unimplemented operation exception. If we've got the full
@@ -690,7 +716,8 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
690 lose_fpu(1); 716 lose_fpu(1);
691 717
692 /* Run the emulator */ 718 /* Run the emulator */
693 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1); 719 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
720 &fault_addr);
694 721
695 /* 722 /*
696 * We can't allow the emulated instruction to leave any of 723 * We can't allow the emulated instruction to leave any of
@@ -702,8 +729,7 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
702 own_fpu(1); /* Using the FPU again. */ 729 own_fpu(1); /* Using the FPU again. */
703 730
704 /* If something went wrong, signal */ 731 /* If something went wrong, signal */
705 if (sig) 732 process_fpemu_return(sig, fault_addr);
706 force_sig(sig, current);
707 733
708 return; 734 return;
709 } else if (fcr31 & FPU_CSR_INV_X) 735 } else if (fcr31 & FPU_CSR_INV_X)
@@ -996,11 +1022,11 @@ asmlinkage void do_cpu(struct pt_regs *regs)
996 1022
997 if (!raw_cpu_has_fpu) { 1023 if (!raw_cpu_has_fpu) {
998 int sig; 1024 int sig;
1025 void __user *fault_addr = NULL;
999 sig = fpu_emulator_cop1Handler(regs, 1026 sig = fpu_emulator_cop1Handler(regs,
1000 &current->thread.fpu, 0); 1027 &current->thread.fpu,
1001 if (sig) 1028 0, &fault_addr);
1002 force_sig(sig, current); 1029 if (!process_fpemu_return(sig, fault_addr))
1003 else
1004 mt_ase_fp_affinity(); 1030 mt_ase_fp_affinity();
1005 } 1031 }
1006 1032
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index 3eb3cde2f661..6a1fdfef8fde 100644
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -1092,6 +1092,10 @@ static int vpe_open(struct inode *inode, struct file *filp)
1092 1092
1093 /* this of-course trashes what was there before... */ 1093 /* this of-course trashes what was there before... */
1094 v->pbuffer = vmalloc(P_SIZE); 1094 v->pbuffer = vmalloc(P_SIZE);
1095 if (!v->pbuffer) {
1096 pr_warning("VPE loader: unable to allocate memory\n");
1097 return -ENOMEM;
1098 }
1095 v->plen = P_SIZE; 1099 v->plen = P_SIZE;
1096 v->load_addr = NULL; 1100 v->load_addr = NULL;
1097 v->len = 0; 1101 v->len = 0;
@@ -1149,10 +1153,9 @@ static int vpe_release(struct inode *inode, struct file *filp)
1149 if (ret < 0) 1153 if (ret < 0)
1150 v->shared_ptr = NULL; 1154 v->shared_ptr = NULL;
1151 1155
1152 // cleanup any temp buffers 1156 vfree(v->pbuffer);
1153 if (v->pbuffer)
1154 vfree(v->pbuffer);
1155 v->plen = 0; 1157 v->plen = 0;
1158
1156 return ret; 1159 return ret;
1157} 1160}
1158 1161
@@ -1169,11 +1172,6 @@ static ssize_t vpe_write(struct file *file, const char __user * buffer,
1169 if (v == NULL) 1172 if (v == NULL)
1170 return -ENODEV; 1173 return -ENODEV;
1171 1174
1172 if (v->pbuffer == NULL) {
1173 printk(KERN_ERR "VPE loader: no buffer for program\n");
1174 return -ENOMEM;
1175 }
1176
1177 if ((count + v->len) > v->plen) { 1175 if ((count + v->len) > v->plen) {
1178 printk(KERN_WARNING 1176 printk(KERN_WARNING
1179 "VPE loader: elf size too big. Perhaps strip uneeded symbols\n"); 1177 "VPE loader: elf size too big. Perhaps strip uneeded symbols\n");
diff --git a/arch/mips/lib/memset.S b/arch/mips/lib/memset.S
index 77dc3b20110a..606c8a9efe3b 100644
--- a/arch/mips/lib/memset.S
+++ b/arch/mips/lib/memset.S
@@ -161,16 +161,16 @@ FEXPORT(__bzero)
161 161
162.Lfwd_fixup: 162.Lfwd_fixup:
163 PTR_L t0, TI_TASK($28) 163 PTR_L t0, TI_TASK($28)
164 LONG_L t0, THREAD_BUADDR(t0)
165 andi a2, 0x3f 164 andi a2, 0x3f
165 LONG_L t0, THREAD_BUADDR(t0)
166 LONG_ADDU a2, t1 166 LONG_ADDU a2, t1
167 jr ra 167 jr ra
168 LONG_SUBU a2, t0 168 LONG_SUBU a2, t0
169 169
170.Lpartial_fixup: 170.Lpartial_fixup:
171 PTR_L t0, TI_TASK($28) 171 PTR_L t0, TI_TASK($28)
172 LONG_L t0, THREAD_BUADDR(t0)
173 andi a2, LONGMASK 172 andi a2, LONGMASK
173 LONG_L t0, THREAD_BUADDR(t0)
174 LONG_ADDU a2, t1 174 LONG_ADDU a2, t1
175 jr ra 175 jr ra
176 LONG_SUBU a2, t0 176 LONG_SUBU a2, t0
diff --git a/arch/mips/loongson/common/env.c b/arch/mips/loongson/common/env.c
index ae4cff97a56c..11b193f848f8 100644
--- a/arch/mips/loongson/common/env.c
+++ b/arch/mips/loongson/common/env.c
@@ -29,9 +29,9 @@ unsigned long memsize, highmemsize;
29 29
30#define parse_even_earlier(res, option, p) \ 30#define parse_even_earlier(res, option, p) \
31do { \ 31do { \
32 int ret; \
32 if (strncmp(option, (char *)p, strlen(option)) == 0) \ 33 if (strncmp(option, (char *)p, strlen(option)) == 0) \
33 strict_strtol((char *)p + strlen(option"="), \ 34 ret = strict_strtol((char *)p + strlen(option"="), 10, &res); \
34 10, &res); \
35} while (0) 35} while (0)
36 36
37void __init prom_init_env(void) 37void __init prom_init_env(void)
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index b2ad1b0910ff..d32cb0503110 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -64,7 +64,7 @@ static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
64 64
65#if __mips >= 4 && __mips != 32 65#if __mips >= 4 && __mips != 32
66static int fpux_emu(struct pt_regs *, 66static int fpux_emu(struct pt_regs *,
67 struct mips_fpu_struct *, mips_instruction); 67 struct mips_fpu_struct *, mips_instruction, void *__user *);
68#endif 68#endif
69 69
70/* Further private data for which no space exists in mips_fpu_struct */ 70/* Further private data for which no space exists in mips_fpu_struct */
@@ -208,16 +208,23 @@ static inline int cop1_64bit(struct pt_regs *xcp)
208 * Two instructions if the instruction is in a branch delay slot. 208 * Two instructions if the instruction is in a branch delay slot.
209 */ 209 */
210 210
211static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) 211static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
212 void *__user *fault_addr)
212{ 213{
213 mips_instruction ir; 214 mips_instruction ir;
214 unsigned long emulpc, contpc; 215 unsigned long emulpc, contpc;
215 unsigned int cond; 216 unsigned int cond;
216 217
217 if (get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) { 218 if (!access_ok(VERIFY_READ, xcp->cp0_epc, sizeof(mips_instruction))) {
218 MIPS_FPU_EMU_INC_STATS(errors); 219 MIPS_FPU_EMU_INC_STATS(errors);
220 *fault_addr = (mips_instruction __user *)xcp->cp0_epc;
219 return SIGBUS; 221 return SIGBUS;
220 } 222 }
223 if (__get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) {
224 MIPS_FPU_EMU_INC_STATS(errors);
225 *fault_addr = (mips_instruction __user *)xcp->cp0_epc;
226 return SIGSEGV;
227 }
221 228
222 /* XXX NEC Vr54xx bug workaround */ 229 /* XXX NEC Vr54xx bug workaround */
223 if ((xcp->cp0_cause & CAUSEF_BD) && !isBranchInstr(&ir)) 230 if ((xcp->cp0_cause & CAUSEF_BD) && !isBranchInstr(&ir))
@@ -245,10 +252,16 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
245#endif 252#endif
246 return SIGILL; 253 return SIGILL;
247 } 254 }
248 if (get_user(ir, (mips_instruction __user *) emulpc)) { 255 if (!access_ok(VERIFY_READ, emulpc, sizeof(mips_instruction))) {
249 MIPS_FPU_EMU_INC_STATS(errors); 256 MIPS_FPU_EMU_INC_STATS(errors);
257 *fault_addr = (mips_instruction __user *)emulpc;
250 return SIGBUS; 258 return SIGBUS;
251 } 259 }
260 if (__get_user(ir, (mips_instruction __user *) emulpc)) {
261 MIPS_FPU_EMU_INC_STATS(errors);
262 *fault_addr = (mips_instruction __user *)emulpc;
263 return SIGSEGV;
264 }
252 /* __compute_return_epc() will have updated cp0_epc */ 265 /* __compute_return_epc() will have updated cp0_epc */
253 contpc = xcp->cp0_epc; 266 contpc = xcp->cp0_epc;
254 /* In order not to confuse ptrace() et al, tweak context */ 267 /* In order not to confuse ptrace() et al, tweak context */
@@ -269,10 +282,17 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
269 u64 val; 282 u64 val;
270 283
271 MIPS_FPU_EMU_INC_STATS(loads); 284 MIPS_FPU_EMU_INC_STATS(loads);
272 if (get_user(val, va)) { 285
286 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
273 MIPS_FPU_EMU_INC_STATS(errors); 287 MIPS_FPU_EMU_INC_STATS(errors);
288 *fault_addr = va;
274 return SIGBUS; 289 return SIGBUS;
275 } 290 }
291 if (__get_user(val, va)) {
292 MIPS_FPU_EMU_INC_STATS(errors);
293 *fault_addr = va;
294 return SIGSEGV;
295 }
276 DITOREG(val, MIPSInst_RT(ir)); 296 DITOREG(val, MIPSInst_RT(ir));
277 break; 297 break;
278 } 298 }
@@ -284,10 +304,16 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
284 304
285 MIPS_FPU_EMU_INC_STATS(stores); 305 MIPS_FPU_EMU_INC_STATS(stores);
286 DIFROMREG(val, MIPSInst_RT(ir)); 306 DIFROMREG(val, MIPSInst_RT(ir));
287 if (put_user(val, va)) { 307 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
288 MIPS_FPU_EMU_INC_STATS(errors); 308 MIPS_FPU_EMU_INC_STATS(errors);
309 *fault_addr = va;
289 return SIGBUS; 310 return SIGBUS;
290 } 311 }
312 if (__put_user(val, va)) {
313 MIPS_FPU_EMU_INC_STATS(errors);
314 *fault_addr = va;
315 return SIGSEGV;
316 }
291 break; 317 break;
292 } 318 }
293 319
@@ -297,10 +323,16 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
297 u32 val; 323 u32 val;
298 324
299 MIPS_FPU_EMU_INC_STATS(loads); 325 MIPS_FPU_EMU_INC_STATS(loads);
300 if (get_user(val, va)) { 326 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
301 MIPS_FPU_EMU_INC_STATS(errors); 327 MIPS_FPU_EMU_INC_STATS(errors);
328 *fault_addr = va;
302 return SIGBUS; 329 return SIGBUS;
303 } 330 }
331 if (__get_user(val, va)) {
332 MIPS_FPU_EMU_INC_STATS(errors);
333 *fault_addr = va;
334 return SIGSEGV;
335 }
304 SITOREG(val, MIPSInst_RT(ir)); 336 SITOREG(val, MIPSInst_RT(ir));
305 break; 337 break;
306 } 338 }
@@ -312,10 +344,16 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
312 344
313 MIPS_FPU_EMU_INC_STATS(stores); 345 MIPS_FPU_EMU_INC_STATS(stores);
314 SIFROMREG(val, MIPSInst_RT(ir)); 346 SIFROMREG(val, MIPSInst_RT(ir));
315 if (put_user(val, va)) { 347 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
316 MIPS_FPU_EMU_INC_STATS(errors); 348 MIPS_FPU_EMU_INC_STATS(errors);
349 *fault_addr = va;
317 return SIGBUS; 350 return SIGBUS;
318 } 351 }
352 if (__put_user(val, va)) {
353 MIPS_FPU_EMU_INC_STATS(errors);
354 *fault_addr = va;
355 return SIGSEGV;
356 }
319 break; 357 break;
320 } 358 }
321 359
@@ -440,11 +478,18 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
440 contpc = (xcp->cp0_epc + 478 contpc = (xcp->cp0_epc +
441 (MIPSInst_SIMM(ir) << 2)); 479 (MIPSInst_SIMM(ir) << 2));
442 480
443 if (get_user(ir, 481 if (!access_ok(VERIFY_READ, xcp->cp0_epc,
444 (mips_instruction __user *) xcp->cp0_epc)) { 482 sizeof(mips_instruction))) {
445 MIPS_FPU_EMU_INC_STATS(errors); 483 MIPS_FPU_EMU_INC_STATS(errors);
484 *fault_addr = (mips_instruction __user *)xcp->cp0_epc;
446 return SIGBUS; 485 return SIGBUS;
447 } 486 }
487 if (__get_user(ir,
488 (mips_instruction __user *) xcp->cp0_epc)) {
489 MIPS_FPU_EMU_INC_STATS(errors);
490 *fault_addr = (mips_instruction __user *)xcp->cp0_epc;
491 return SIGSEGV;
492 }
448 493
449 switch (MIPSInst_OPCODE(ir)) { 494 switch (MIPSInst_OPCODE(ir)) {
450 case lwc1_op: 495 case lwc1_op:
@@ -506,9 +551,8 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
506 551
507#if __mips >= 4 && __mips != 32 552#if __mips >= 4 && __mips != 32
508 case cop1x_op:{ 553 case cop1x_op:{
509 int sig; 554 int sig = fpux_emu(xcp, ctx, ir, fault_addr);
510 555 if (sig)
511 if ((sig = fpux_emu(xcp, ctx, ir)))
512 return sig; 556 return sig;
513 break; 557 break;
514 } 558 }
@@ -604,7 +648,7 @@ DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
604DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); 648DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
605 649
606static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 650static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
607 mips_instruction ir) 651 mips_instruction ir, void *__user *fault_addr)
608{ 652{
609 unsigned rcsr = 0; /* resulting csr */ 653 unsigned rcsr = 0; /* resulting csr */
610 654
@@ -624,10 +668,16 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
624 xcp->regs[MIPSInst_FT(ir)]); 668 xcp->regs[MIPSInst_FT(ir)]);
625 669
626 MIPS_FPU_EMU_INC_STATS(loads); 670 MIPS_FPU_EMU_INC_STATS(loads);
627 if (get_user(val, va)) { 671 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
628 MIPS_FPU_EMU_INC_STATS(errors); 672 MIPS_FPU_EMU_INC_STATS(errors);
673 *fault_addr = va;
629 return SIGBUS; 674 return SIGBUS;
630 } 675 }
676 if (__get_user(val, va)) {
677 MIPS_FPU_EMU_INC_STATS(errors);
678 *fault_addr = va;
679 return SIGSEGV;
680 }
631 SITOREG(val, MIPSInst_FD(ir)); 681 SITOREG(val, MIPSInst_FD(ir));
632 break; 682 break;
633 683
@@ -638,10 +688,16 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
638 MIPS_FPU_EMU_INC_STATS(stores); 688 MIPS_FPU_EMU_INC_STATS(stores);
639 689
640 SIFROMREG(val, MIPSInst_FS(ir)); 690 SIFROMREG(val, MIPSInst_FS(ir));
641 if (put_user(val, va)) { 691 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
642 MIPS_FPU_EMU_INC_STATS(errors); 692 MIPS_FPU_EMU_INC_STATS(errors);
693 *fault_addr = va;
643 return SIGBUS; 694 return SIGBUS;
644 } 695 }
696 if (put_user(val, va)) {
697 MIPS_FPU_EMU_INC_STATS(errors);
698 *fault_addr = va;
699 return SIGSEGV;
700 }
645 break; 701 break;
646 702
647 case madd_s_op: 703 case madd_s_op:
@@ -701,10 +757,16 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
701 xcp->regs[MIPSInst_FT(ir)]); 757 xcp->regs[MIPSInst_FT(ir)]);
702 758
703 MIPS_FPU_EMU_INC_STATS(loads); 759 MIPS_FPU_EMU_INC_STATS(loads);
704 if (get_user(val, va)) { 760 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
705 MIPS_FPU_EMU_INC_STATS(errors); 761 MIPS_FPU_EMU_INC_STATS(errors);
762 *fault_addr = va;
706 return SIGBUS; 763 return SIGBUS;
707 } 764 }
765 if (__get_user(val, va)) {
766 MIPS_FPU_EMU_INC_STATS(errors);
767 *fault_addr = va;
768 return SIGSEGV;
769 }
708 DITOREG(val, MIPSInst_FD(ir)); 770 DITOREG(val, MIPSInst_FD(ir));
709 break; 771 break;
710 772
@@ -714,10 +776,16 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
714 776
715 MIPS_FPU_EMU_INC_STATS(stores); 777 MIPS_FPU_EMU_INC_STATS(stores);
716 DIFROMREG(val, MIPSInst_FS(ir)); 778 DIFROMREG(val, MIPSInst_FS(ir));
717 if (put_user(val, va)) { 779 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
718 MIPS_FPU_EMU_INC_STATS(errors); 780 MIPS_FPU_EMU_INC_STATS(errors);
781 *fault_addr = va;
719 return SIGBUS; 782 return SIGBUS;
720 } 783 }
784 if (__put_user(val, va)) {
785 MIPS_FPU_EMU_INC_STATS(errors);
786 *fault_addr = va;
787 return SIGSEGV;
788 }
721 break; 789 break;
722 790
723 case madd_d_op: 791 case madd_d_op:
@@ -1242,7 +1310,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1242} 1310}
1243 1311
1244int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 1312int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1245 int has_fpu) 1313 int has_fpu, void *__user *fault_addr)
1246{ 1314{
1247 unsigned long oldepc, prevepc; 1315 unsigned long oldepc, prevepc;
1248 mips_instruction insn; 1316 mips_instruction insn;
@@ -1252,10 +1320,16 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1252 do { 1320 do {
1253 prevepc = xcp->cp0_epc; 1321 prevepc = xcp->cp0_epc;
1254 1322
1255 if (get_user(insn, (mips_instruction __user *) xcp->cp0_epc)) { 1323 if (!access_ok(VERIFY_READ, xcp->cp0_epc, sizeof(mips_instruction))) {
1256 MIPS_FPU_EMU_INC_STATS(errors); 1324 MIPS_FPU_EMU_INC_STATS(errors);
1325 *fault_addr = (mips_instruction __user *)xcp->cp0_epc;
1257 return SIGBUS; 1326 return SIGBUS;
1258 } 1327 }
1328 if (__get_user(insn, (mips_instruction __user *) xcp->cp0_epc)) {
1329 MIPS_FPU_EMU_INC_STATS(errors);
1330 *fault_addr = (mips_instruction __user *)xcp->cp0_epc;
1331 return SIGSEGV;
1332 }
1259 if (insn == 0) 1333 if (insn == 0)
1260 xcp->cp0_epc += 4; /* skip nops */ 1334 xcp->cp0_epc += 4; /* skip nops */
1261 else { 1335 else {
@@ -1267,7 +1341,7 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1267 */ 1341 */
1268 /* convert to ieee library modes */ 1342 /* convert to ieee library modes */
1269 ieee754_csr.rm = ieee_rm[ieee754_csr.rm]; 1343 ieee754_csr.rm = ieee_rm[ieee754_csr.rm];
1270 sig = cop1Emulate(xcp, ctx); 1344 sig = cop1Emulate(xcp, ctx, fault_addr);
1271 /* revert to mips rounding mode */ 1345 /* revert to mips rounding mode */
1272 ieee754_csr.rm = mips_rm[ieee754_csr.rm]; 1346 ieee754_csr.rm = mips_rm[ieee754_csr.rm];
1273 } 1347 }
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 4fc1a0fbe007..21ea14efb837 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -288,7 +288,7 @@ int mips_dma_supported(struct device *dev, u64 mask)
288 return plat_dma_supported(dev, mask); 288 return plat_dma_supported(dev, mask);
289} 289}
290 290
291void mips_dma_cache_sync(struct device *dev, void *vaddr, size_t size, 291void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
292 enum dma_data_direction direction) 292 enum dma_data_direction direction)
293{ 293{
294 BUG_ON(direction == DMA_NONE); 294 BUG_ON(direction == DMA_NONE);
@@ -298,6 +298,8 @@ void mips_dma_cache_sync(struct device *dev, void *vaddr, size_t size,
298 __dma_sync((unsigned long)vaddr, size, direction); 298 __dma_sync((unsigned long)vaddr, size, direction);
299} 299}
300 300
301EXPORT_SYMBOL(dma_cache_sync);
302
301static struct dma_map_ops mips_default_dma_map_ops = { 303static struct dma_map_ops mips_default_dma_map_ops = {
302 .alloc_coherent = mips_dma_alloc_coherent, 304 .alloc_coherent = mips_dma_alloc_coherent,
303 .free_coherent = mips_dma_free_coherent, 305 .free_coherent = mips_dma_free_coherent,
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 505fecad4684..9cca8de00545 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -68,6 +68,9 @@ static struct bcache_ops mips_sc_ops = {
68 */ 68 */
69static inline int mips_sc_is_activated(struct cpuinfo_mips *c) 69static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
70{ 70{
71 unsigned int config2 = read_c0_config2();
72 unsigned int tmp;
73
71 /* Check the bypass bit (L2B) */ 74 /* Check the bypass bit (L2B) */
72 switch (c->cputype) { 75 switch (c->cputype) {
73 case CPU_34K: 76 case CPU_34K:
@@ -83,6 +86,7 @@ static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
83 c->scache.linesz = 2 << tmp; 86 c->scache.linesz = 2 << tmp;
84 else 87 else
85 return 0; 88 return 0;
89 return 1;
86} 90}
87 91
88static inline int __init mips_sc_probe(void) 92static inline int __init mips_sc_probe(void)
diff --git a/arch/mips/pmc-sierra/yosemite/py-console.c b/arch/mips/pmc-sierra/yosemite/py-console.c
index b7f1d9c4a8a3..434d7b1a8c6a 100644
--- a/arch/mips/pmc-sierra/yosemite/py-console.c
+++ b/arch/mips/pmc-sierra/yosemite/py-console.c
@@ -65,11 +65,15 @@ static unsigned char readb_outer_space(unsigned long long phys)
65 65
66 __asm__ __volatile__ ( 66 __asm__ __volatile__ (
67 " .set mips3 \n" 67 " .set mips3 \n"
68 " .set push \n"
69 " .set noreorder \n"
70 " .set nomacro \n"
68 " ld %0, %1 \n" 71 " ld %0, %1 \n"
72 " .set pop \n"
69 " lbu %0, (%0) \n" 73 " lbu %0, (%0) \n"
70 " .set mips0 \n" 74 " .set mips0 \n"
71 : "=r" (res) 75 : "=r" (res)
72 : "m" (vaddr)); 76 : "R" (vaddr));
73 77
74 write_c0_status(sr); 78 write_c0_status(sr);
75 ssnop_4(); 79 ssnop_4();
@@ -89,11 +93,15 @@ static void writeb_outer_space(unsigned long long phys, unsigned char c)
89 93
90 __asm__ __volatile__ ( 94 __asm__ __volatile__ (
91 " .set mips3 \n" 95 " .set mips3 \n"
96 " .set push \n"
97 " .set noreorder \n"
98 " .set nomacro \n"
92 " ld %0, %1 \n" 99 " ld %0, %1 \n"
100 " .set pop \n"
93 " sb %2, (%0) \n" 101 " sb %2, (%0) \n"
94 " .set mips0 \n" 102 " .set mips0 \n"
95 : "=&r" (tmp) 103 : "=&r" (tmp)
96 : "m" (vaddr), "r" (c)); 104 : "R" (vaddr), "r" (c));
97 105
98 write_c0_status(sr); 106 write_c0_status(sr);
99 ssnop_4(); 107 ssnop_4();
diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c
index c308989fc464..41707a245dea 100644
--- a/arch/mips/sibyte/swarm/setup.c
+++ b/arch/mips/sibyte/swarm/setup.c
@@ -82,7 +82,7 @@ int swarm_be_handler(struct pt_regs *regs, int is_fixup)
82enum swarm_rtc_type { 82enum swarm_rtc_type {
83 RTC_NONE, 83 RTC_NONE,
84 RTC_XICOR, 84 RTC_XICOR,
85 RTC_M4LT81 85 RTC_M41T81,
86}; 86};
87 87
88enum swarm_rtc_type swarm_rtc_type; 88enum swarm_rtc_type swarm_rtc_type;
@@ -96,7 +96,7 @@ void read_persistent_clock(struct timespec *ts)
96 sec = xicor_get_time(); 96 sec = xicor_get_time();
97 break; 97 break;
98 98
99 case RTC_M4LT81: 99 case RTC_M41T81:
100 sec = m41t81_get_time(); 100 sec = m41t81_get_time();
101 break; 101 break;
102 102
@@ -115,7 +115,7 @@ int rtc_mips_set_time(unsigned long sec)
115 case RTC_XICOR: 115 case RTC_XICOR:
116 return xicor_set_time(sec); 116 return xicor_set_time(sec);
117 117
118 case RTC_M4LT81: 118 case RTC_M41T81:
119 return m41t81_set_time(sec); 119 return m41t81_set_time(sec);
120 120
121 case RTC_NONE: 121 case RTC_NONE:
@@ -141,7 +141,7 @@ void __init plat_mem_setup(void)
141 if (xicor_probe()) 141 if (xicor_probe())
142 swarm_rtc_type = RTC_XICOR; 142 swarm_rtc_type = RTC_XICOR;
143 if (m41t81_probe()) 143 if (m41t81_probe())
144 swarm_rtc_type = RTC_M4LT81; 144 swarm_rtc_type = RTC_M41T81;
145 145
146#ifdef CONFIG_VT 146#ifdef CONFIG_VT
147 screen_info = (struct screen_info) { 147 screen_info = (struct screen_info) {
diff --git a/arch/mn10300/kernel/time.c b/arch/mn10300/kernel/time.c
index f860a340acc9..75da468090b9 100644
--- a/arch/mn10300/kernel/time.c
+++ b/arch/mn10300/kernel/time.c
@@ -40,21 +40,17 @@ unsigned long long sched_clock(void)
40 unsigned long long ll; 40 unsigned long long ll;
41 unsigned l[2]; 41 unsigned l[2];
42 } tsc64, result; 42 } tsc64, result;
43 unsigned long tsc, tmp; 43 unsigned long tmp;
44 unsigned product[3]; /* 96-bit intermediate value */ 44 unsigned product[3]; /* 96-bit intermediate value */
45 45
46 /* cnt32_to_63() is not safe with preemption */ 46 /* cnt32_to_63() is not safe with preemption */
47 preempt_disable(); 47 preempt_disable();
48 48
49 /* read the TSC value 49 /* expand the tsc to 64-bits.
50 */
51 tsc = get_cycles();
52
53 /* expand to 64-bits.
54 * - sched_clock() must be called once a minute or better or the 50 * - sched_clock() must be called once a minute or better or the
55 * following will go horribly wrong - see cnt32_to_63() 51 * following will go horribly wrong - see cnt32_to_63()
56 */ 52 */
57 tsc64.ll = cnt32_to_63(tsc) & 0x7fffffffffffffffULL; 53 tsc64.ll = cnt32_to_63(get_cycles()) & 0x7fffffffffffffffULL;
58 54
59 preempt_enable(); 55 preempt_enable();
60 56
diff --git a/arch/tile/include/asm/signal.h b/arch/tile/include/asm/signal.h
index c1ee1d61d44c..81d92a45cd4b 100644
--- a/arch/tile/include/asm/signal.h
+++ b/arch/tile/include/asm/signal.h
@@ -25,7 +25,7 @@
25 25
26#if defined(__KERNEL__) && !defined(__ASSEMBLY__) 26#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
27struct pt_regs; 27struct pt_regs;
28int restore_sigcontext(struct pt_regs *, struct sigcontext __user *, long *); 28int restore_sigcontext(struct pt_regs *, struct sigcontext __user *);
29int setup_sigcontext(struct sigcontext __user *, struct pt_regs *); 29int setup_sigcontext(struct sigcontext __user *, struct pt_regs *);
30void do_signal(struct pt_regs *regs); 30void do_signal(struct pt_regs *regs);
31#endif 31#endif
diff --git a/arch/tile/kernel/compat_signal.c b/arch/tile/kernel/compat_signal.c
index 543d6a33aa26..dbb0dfc7bece 100644
--- a/arch/tile/kernel/compat_signal.c
+++ b/arch/tile/kernel/compat_signal.c
@@ -290,12 +290,12 @@ long compat_sys_sigaltstack(const struct compat_sigaltstack __user *uss_ptr,
290 return ret; 290 return ret;
291} 291}
292 292
293/* The assembly shim for this function arranges to ignore the return value. */
293long compat_sys_rt_sigreturn(struct pt_regs *regs) 294long compat_sys_rt_sigreturn(struct pt_regs *regs)
294{ 295{
295 struct compat_rt_sigframe __user *frame = 296 struct compat_rt_sigframe __user *frame =
296 (struct compat_rt_sigframe __user *) compat_ptr(regs->sp); 297 (struct compat_rt_sigframe __user *) compat_ptr(regs->sp);
297 sigset_t set; 298 sigset_t set;
298 long r0;
299 299
300 if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) 300 if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
301 goto badframe; 301 goto badframe;
@@ -308,13 +308,13 @@ long compat_sys_rt_sigreturn(struct pt_regs *regs)
308 recalc_sigpending(); 308 recalc_sigpending();
309 spin_unlock_irq(&current->sighand->siglock); 309 spin_unlock_irq(&current->sighand->siglock);
310 310
311 if (restore_sigcontext(regs, &frame->uc.uc_mcontext, &r0)) 311 if (restore_sigcontext(regs, &frame->uc.uc_mcontext))
312 goto badframe; 312 goto badframe;
313 313
314 if (compat_sys_sigaltstack(&frame->uc.uc_stack, NULL, regs) != 0) 314 if (compat_sys_sigaltstack(&frame->uc.uc_stack, NULL, regs) != 0)
315 goto badframe; 315 goto badframe;
316 316
317 return r0; 317 return 0;
318 318
319badframe: 319badframe:
320 force_sig(SIGSEGV, current); 320 force_sig(SIGSEGV, current);
diff --git a/arch/tile/kernel/intvec_32.S b/arch/tile/kernel/intvec_32.S
index f5821626247f..5eed4a02bf62 100644
--- a/arch/tile/kernel/intvec_32.S
+++ b/arch/tile/kernel/intvec_32.S
@@ -1342,8 +1342,8 @@ handle_syscall:
1342 lw r20, r20 1342 lw r20, r20
1343 1343
1344 /* Jump to syscall handler. */ 1344 /* Jump to syscall handler. */
1345 jalr r20; .Lhandle_syscall_link: 1345 jalr r20
1346 FEEDBACK_REENTER(handle_syscall) 1346.Lhandle_syscall_link: /* value of "lr" after "jalr r20" above */
1347 1347
1348 /* 1348 /*
1349 * Write our r0 onto the stack so it gets restored instead 1349 * Write our r0 onto the stack so it gets restored instead
@@ -1352,6 +1352,9 @@ handle_syscall:
1352 PTREGS_PTR(r29, PTREGS_OFFSET_REG(0)) 1352 PTREGS_PTR(r29, PTREGS_OFFSET_REG(0))
1353 sw r29, r0 1353 sw r29, r0
1354 1354
1355.Lsyscall_sigreturn_skip:
1356 FEEDBACK_REENTER(handle_syscall)
1357
1355 /* Do syscall trace again, if requested. */ 1358 /* Do syscall trace again, if requested. */
1356 lw r30, r31 1359 lw r30, r31
1357 andi r30, r30, _TIF_SYSCALL_TRACE 1360 andi r30, r30, _TIF_SYSCALL_TRACE
@@ -1536,9 +1539,24 @@ STD_ENTRY_LOCAL(bad_intr)
1536 }; \ 1539 }; \
1537 STD_ENDPROC(_##x) 1540 STD_ENDPROC(_##x)
1538 1541
1542/*
1543 * Special-case sigreturn to not write r0 to the stack on return.
1544 * This is technically more efficient, but it also avoids difficulties
1545 * in the 64-bit OS when handling 32-bit compat code, since we must not
1546 * sign-extend r0 for the sigreturn return-value case.
1547 */
1548#define PTREGS_SYSCALL_SIGRETURN(x, reg) \
1549 STD_ENTRY(_##x); \
1550 addli lr, lr, .Lsyscall_sigreturn_skip - .Lhandle_syscall_link; \
1551 { \
1552 PTREGS_PTR(reg, PTREGS_OFFSET_BASE); \
1553 j x \
1554 }; \
1555 STD_ENDPROC(_##x)
1556
1539PTREGS_SYSCALL(sys_execve, r3) 1557PTREGS_SYSCALL(sys_execve, r3)
1540PTREGS_SYSCALL(sys_sigaltstack, r2) 1558PTREGS_SYSCALL(sys_sigaltstack, r2)
1541PTREGS_SYSCALL(sys_rt_sigreturn, r0) 1559PTREGS_SYSCALL_SIGRETURN(sys_rt_sigreturn, r0)
1542PTREGS_SYSCALL(sys_cmpxchg_badaddr, r1) 1560PTREGS_SYSCALL(sys_cmpxchg_badaddr, r1)
1543 1561
1544/* Save additional callee-saves to pt_regs, put address in r4 and jump. */ 1562/* Save additional callee-saves to pt_regs, put address in r4 and jump. */
diff --git a/arch/tile/kernel/process.c b/arch/tile/kernel/process.c
index 8430f45daea6..e90eb53173b0 100644
--- a/arch/tile/kernel/process.c
+++ b/arch/tile/kernel/process.c
@@ -212,6 +212,13 @@ int copy_thread(unsigned long clone_flags, unsigned long sp,
212 childregs->sp = sp; /* override with new user stack pointer */ 212 childregs->sp = sp; /* override with new user stack pointer */
213 213
214 /* 214 /*
215 * If CLONE_SETTLS is set, set "tp" in the new task to "r4",
216 * which is passed in as arg #5 to sys_clone().
217 */
218 if (clone_flags & CLONE_SETTLS)
219 childregs->tp = regs->regs[4];
220
221 /*
215 * Copy the callee-saved registers from the passed pt_regs struct 222 * Copy the callee-saved registers from the passed pt_regs struct
216 * into the context-switch callee-saved registers area. 223 * into the context-switch callee-saved registers area.
217 * This way when we start the interrupt-return sequence, the 224 * This way when we start the interrupt-return sequence, the
@@ -539,6 +546,7 @@ struct task_struct *__sched _switch_to(struct task_struct *prev,
539 return __switch_to(prev, next, next_current_ksp0(next)); 546 return __switch_to(prev, next, next_current_ksp0(next));
540} 547}
541 548
549/* Note there is an implicit fifth argument if (clone_flags & CLONE_SETTLS). */
542SYSCALL_DEFINE5(clone, unsigned long, clone_flags, unsigned long, newsp, 550SYSCALL_DEFINE5(clone, unsigned long, clone_flags, unsigned long, newsp,
543 void __user *, parent_tidptr, void __user *, child_tidptr, 551 void __user *, parent_tidptr, void __user *, child_tidptr,
544 struct pt_regs *, regs) 552 struct pt_regs *, regs)
diff --git a/arch/tile/kernel/signal.c b/arch/tile/kernel/signal.c
index 757407e36696..1260321155f1 100644
--- a/arch/tile/kernel/signal.c
+++ b/arch/tile/kernel/signal.c
@@ -52,7 +52,7 @@ SYSCALL_DEFINE3(sigaltstack, const stack_t __user *, uss,
52 */ 52 */
53 53
54int restore_sigcontext(struct pt_regs *regs, 54int restore_sigcontext(struct pt_regs *regs,
55 struct sigcontext __user *sc, long *pr0) 55 struct sigcontext __user *sc)
56{ 56{
57 int err = 0; 57 int err = 0;
58 int i; 58 int i;
@@ -75,17 +75,15 @@ int restore_sigcontext(struct pt_regs *regs,
75 75
76 regs->faultnum = INT_SWINT_1_SIGRETURN; 76 regs->faultnum = INT_SWINT_1_SIGRETURN;
77 77
78 err |= __get_user(*pr0, &sc->gregs[0]);
79 return err; 78 return err;
80} 79}
81 80
82/* sigreturn() returns long since it restores r0 in the interrupted code. */ 81/* The assembly shim for this function arranges to ignore the return value. */
83SYSCALL_DEFINE1(rt_sigreturn, struct pt_regs *, regs) 82SYSCALL_DEFINE1(rt_sigreturn, struct pt_regs *, regs)
84{ 83{
85 struct rt_sigframe __user *frame = 84 struct rt_sigframe __user *frame =
86 (struct rt_sigframe __user *)(regs->sp); 85 (struct rt_sigframe __user *)(regs->sp);
87 sigset_t set; 86 sigset_t set;
88 long r0;
89 87
90 if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) 88 if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
91 goto badframe; 89 goto badframe;
@@ -98,13 +96,13 @@ SYSCALL_DEFINE1(rt_sigreturn, struct pt_regs *, regs)
98 recalc_sigpending(); 96 recalc_sigpending();
99 spin_unlock_irq(&current->sighand->siglock); 97 spin_unlock_irq(&current->sighand->siglock);
100 98
101 if (restore_sigcontext(regs, &frame->uc.uc_mcontext, &r0)) 99 if (restore_sigcontext(regs, &frame->uc.uc_mcontext))
102 goto badframe; 100 goto badframe;
103 101
104 if (do_sigaltstack(&frame->uc.uc_stack, NULL, regs->sp) == -EFAULT) 102 if (do_sigaltstack(&frame->uc.uc_stack, NULL, regs->sp) == -EFAULT)
105 goto badframe; 103 goto badframe;
106 104
107 return r0; 105 return 0;
108 106
109badframe: 107badframe:
110 force_sig(SIGSEGV, current); 108 force_sig(SIGSEGV, current);
diff --git a/arch/x86/boot/compressed/misc.c b/arch/x86/boot/compressed/misc.c
index 23f315c9f215..325c05294fc4 100644
--- a/arch/x86/boot/compressed/misc.c
+++ b/arch/x86/boot/compressed/misc.c
@@ -355,7 +355,7 @@ asmlinkage void decompress_kernel(void *rmode, memptr heap,
355 if (heap > 0x3fffffffffffUL) 355 if (heap > 0x3fffffffffffUL)
356 error("Destination address too large"); 356 error("Destination address too large");
357#else 357#else
358 if (heap > ((-__PAGE_OFFSET-(512<<20)-1) & 0x7fffffff)) 358 if (heap > ((-__PAGE_OFFSET-(128<<20)-1) & 0x7fffffff))
359 error("Destination address too large"); 359 error("Destination address too large");
360#endif 360#endif
361#ifndef CONFIG_RELOCATABLE 361#ifndef CONFIG_RELOCATABLE
diff --git a/arch/x86/include/asm/e820.h b/arch/x86/include/asm/e820.h
index 5be1542fbfaf..e99d55d74df5 100644
--- a/arch/x86/include/asm/e820.h
+++ b/arch/x86/include/asm/e820.h
@@ -72,6 +72,9 @@ struct e820map {
72#define BIOS_BEGIN 0x000a0000 72#define BIOS_BEGIN 0x000a0000
73#define BIOS_END 0x00100000 73#define BIOS_END 0x00100000
74 74
75#define BIOS_ROM_BASE 0xffe00000
76#define BIOS_ROM_END 0xffffffff
77
75#ifdef __KERNEL__ 78#ifdef __KERNEL__
76/* see comment in arch/x86/kernel/e820.c */ 79/* see comment in arch/x86/kernel/e820.c */
77extern struct e820map e820; 80extern struct e820map e820;
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index 9e6fe391094e..f702f82aa1eb 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -79,7 +79,7 @@
79#define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT) 79#define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT)
80#define KVM_MIN_FREE_MMU_PAGES 5 80#define KVM_MIN_FREE_MMU_PAGES 5
81#define KVM_REFILL_PAGES 25 81#define KVM_REFILL_PAGES 25
82#define KVM_MAX_CPUID_ENTRIES 40 82#define KVM_MAX_CPUID_ENTRIES 80
83#define KVM_NR_FIXED_MTRR_REGION 88 83#define KVM_NR_FIXED_MTRR_REGION 88
84#define KVM_NR_VAR_MTRR 8 84#define KVM_NR_VAR_MTRR 8
85 85
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 9e13763b6092..1e994754d323 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -45,6 +45,7 @@ obj-y += pci-dma.o quirks.o i8237.o topology.o kdebugfs.o
45obj-y += alternative.o i8253.o pci-nommu.o hw_breakpoint.o 45obj-y += alternative.o i8253.o pci-nommu.o hw_breakpoint.o
46obj-y += tsc.o io_delay.o rtc.o 46obj-y += tsc.o io_delay.o rtc.o
47obj-y += pci-iommu_table.o 47obj-y += pci-iommu_table.o
48obj-y += resource.o
48 49
49obj-$(CONFIG_X86_TRAMPOLINE) += trampoline.o 50obj-$(CONFIG_X86_TRAMPOLINE) += trampoline.o
50obj-y += process.o 51obj-y += process.o
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 3f838d537392..78218135b48e 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1389,6 +1389,14 @@ void __cpuinit end_local_APIC_setup(void)
1389 1389
1390 setup_apic_nmi_watchdog(NULL); 1390 setup_apic_nmi_watchdog(NULL);
1391 apic_pm_activate(); 1391 apic_pm_activate();
1392
1393 /*
1394 * Now that local APIC setup is completed for BP, configure the fault
1395 * handling for interrupt remapping.
1396 */
1397 if (!smp_processor_id() && intr_remapping_enabled)
1398 enable_drhd_fault_handling();
1399
1392} 1400}
1393 1401
1394#ifdef CONFIG_X86_X2APIC 1402#ifdef CONFIG_X86_X2APIC
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 7cc0a721f628..fadcd743a74f 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -2430,13 +2430,12 @@ static void ack_apic_level(struct irq_data *data)
2430{ 2430{
2431 struct irq_cfg *cfg = data->chip_data; 2431 struct irq_cfg *cfg = data->chip_data;
2432 int i, do_unmask_irq = 0, irq = data->irq; 2432 int i, do_unmask_irq = 0, irq = data->irq;
2433 struct irq_desc *desc = irq_to_desc(irq);
2434 unsigned long v; 2433 unsigned long v;
2435 2434
2436 irq_complete_move(cfg); 2435 irq_complete_move(cfg);
2437#ifdef CONFIG_GENERIC_PENDING_IRQ 2436#ifdef CONFIG_GENERIC_PENDING_IRQ
2438 /* If we are moving the irq we need to mask it */ 2437 /* If we are moving the irq we need to mask it */
2439 if (unlikely(desc->status & IRQ_MOVE_PENDING)) { 2438 if (unlikely(irq_to_desc(irq)->status & IRQ_MOVE_PENDING)) {
2440 do_unmask_irq = 1; 2439 do_unmask_irq = 1;
2441 mask_ioapic(cfg); 2440 mask_ioapic(cfg);
2442 } 2441 }
@@ -3413,6 +3412,7 @@ dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
3413 msg.data |= MSI_DATA_VECTOR(cfg->vector); 3412 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3414 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; 3413 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3415 msg.address_lo |= MSI_ADDR_DEST_ID(dest); 3414 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3415 msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest);
3416 3416
3417 dmar_msi_write(irq, &msg); 3417 dmar_msi_write(irq, &msg);
3418 3418
diff --git a/arch/x86/kernel/apic/probe_64.c b/arch/x86/kernel/apic/probe_64.c
index f9e4e6a54073..d8c4a6feb286 100644
--- a/arch/x86/kernel/apic/probe_64.c
+++ b/arch/x86/kernel/apic/probe_64.c
@@ -79,13 +79,6 @@ void __init default_setup_apic_routing(void)
79 /* need to update phys_pkg_id */ 79 /* need to update phys_pkg_id */
80 apic->phys_pkg_id = apicid_phys_pkg_id; 80 apic->phys_pkg_id = apicid_phys_pkg_id;
81 } 81 }
82
83 /*
84 * Now that apic routing model is selected, configure the
85 * fault handling for intr remapping.
86 */
87 if (intr_remapping_enabled)
88 enable_drhd_fault_handling();
89} 82}
90 83
91/* Same for both flat and physical. */ 84/* Same for both flat and physical. */
diff --git a/arch/x86/kernel/head_32.S b/arch/x86/kernel/head_32.S
index bcece91dd311..c0dbd9ac24f0 100644
--- a/arch/x86/kernel/head_32.S
+++ b/arch/x86/kernel/head_32.S
@@ -60,16 +60,18 @@
60#define PAGE_TABLE_SIZE(pages) ((pages) / PTRS_PER_PGD) 60#define PAGE_TABLE_SIZE(pages) ((pages) / PTRS_PER_PGD)
61#endif 61#endif
62 62
63/* Number of possible pages in the lowmem region */
64LOWMEM_PAGES = (((1<<32) - __PAGE_OFFSET) >> PAGE_SHIFT)
65
63/* Enough space to fit pagetables for the low memory linear map */ 66/* Enough space to fit pagetables for the low memory linear map */
64MAPPING_BEYOND_END = \ 67MAPPING_BEYOND_END = PAGE_TABLE_SIZE(LOWMEM_PAGES) << PAGE_SHIFT
65 PAGE_TABLE_SIZE(((1<<32) - __PAGE_OFFSET) >> PAGE_SHIFT) << PAGE_SHIFT
66 68
67/* 69/*
68 * Worst-case size of the kernel mapping we need to make: 70 * Worst-case size of the kernel mapping we need to make:
69 * the worst-case size of the kernel itself, plus the extra we need 71 * a relocatable kernel can live anywhere in lowmem, so we need to be able
70 * to map for the linear map. 72 * to map all of lowmem.
71 */ 73 */
72KERNEL_PAGES = (KERNEL_IMAGE_SIZE + MAPPING_BEYOND_END)>>PAGE_SHIFT 74KERNEL_PAGES = LOWMEM_PAGES
73 75
74INIT_MAP_SIZE = PAGE_TABLE_SIZE(KERNEL_PAGES) * PAGE_SIZE_asm 76INIT_MAP_SIZE = PAGE_TABLE_SIZE(KERNEL_PAGES) * PAGE_SIZE_asm
75RESERVE_BRK(pagetables, INIT_MAP_SIZE) 77RESERVE_BRK(pagetables, INIT_MAP_SIZE)
@@ -620,13 +622,13 @@ ENTRY(initial_code)
620__PAGE_ALIGNED_BSS 622__PAGE_ALIGNED_BSS
621 .align PAGE_SIZE_asm 623 .align PAGE_SIZE_asm
622#ifdef CONFIG_X86_PAE 624#ifdef CONFIG_X86_PAE
623initial_pg_pmd: 625ENTRY(initial_pg_pmd)
624 .fill 1024*KPMDS,4,0 626 .fill 1024*KPMDS,4,0
625#else 627#else
626ENTRY(initial_page_table) 628ENTRY(initial_page_table)
627 .fill 1024,4,0 629 .fill 1024,4,0
628#endif 630#endif
629initial_pg_fixmap: 631ENTRY(initial_pg_fixmap)
630 .fill 1024,4,0 632 .fill 1024,4,0
631ENTRY(empty_zero_page) 633ENTRY(empty_zero_page)
632 .fill 4096,1,0 634 .fill 4096,1,0
diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c
index ae03cab4352e..4ff5968f12d2 100644
--- a/arch/x86/kernel/hpet.c
+++ b/arch/x86/kernel/hpet.c
@@ -27,6 +27,9 @@
27#define HPET_DEV_FSB_CAP 0x1000 27#define HPET_DEV_FSB_CAP 0x1000
28#define HPET_DEV_PERI_CAP 0x2000 28#define HPET_DEV_PERI_CAP 0x2000
29 29
30#define HPET_MIN_CYCLES 128
31#define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
32
30#define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt) 33#define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt)
31 34
32/* 35/*
@@ -299,8 +302,9 @@ static void hpet_legacy_clockevent_register(void)
299 /* Calculate the min / max delta */ 302 /* Calculate the min / max delta */
300 hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, 303 hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
301 &hpet_clockevent); 304 &hpet_clockevent);
302 /* 5 usec minimum reprogramming delta. */ 305 /* Setup minimum reprogramming delta. */
303 hpet_clockevent.min_delta_ns = 5000; 306 hpet_clockevent.min_delta_ns = clockevent_delta2ns(HPET_MIN_PROG_DELTA,
307 &hpet_clockevent);
304 308
305 /* 309 /*
306 * Start hpet with the boot cpu mask and make it 310 * Start hpet with the boot cpu mask and make it
@@ -393,22 +397,24 @@ static int hpet_next_event(unsigned long delta,
393 * the wraparound into account) nor a simple count down event 397 * the wraparound into account) nor a simple count down event
394 * mode. Further the write to the comparator register is 398 * mode. Further the write to the comparator register is
395 * delayed internally up to two HPET clock cycles in certain 399 * delayed internally up to two HPET clock cycles in certain
396 * chipsets (ATI, ICH9,10). We worked around that by reading 400 * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
397 * back the compare register, but that required another 401 * longer delays. We worked around that by reading back the
398 * workaround for ICH9,10 chips where the first readout after 402 * compare register, but that required another workaround for
399 * write can return the old stale value. We already have a 403 * ICH9,10 chips where the first readout after write can
400 * minimum delta of 5us enforced, but a NMI or SMI hitting 404 * return the old stale value. We already had a minimum
405 * programming delta of 5us enforced, but a NMI or SMI hitting
401 * between the counter readout and the comparator write can 406 * between the counter readout and the comparator write can
402 * move us behind that point easily. Now instead of reading 407 * move us behind that point easily. Now instead of reading
403 * the compare register back several times, we make the ETIME 408 * the compare register back several times, we make the ETIME
404 * decision based on the following: Return ETIME if the 409 * decision based on the following: Return ETIME if the
405 * counter value after the write is less than 8 HPET cycles 410 * counter value after the write is less than HPET_MIN_CYCLES
406 * away from the event or if the counter is already ahead of 411 * away from the event or if the counter is already ahead of
407 * the event. 412 * the event. The minimum programming delta for the generic
413 * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
408 */ 414 */
409 res = (s32)(cnt - hpet_readl(HPET_COUNTER)); 415 res = (s32)(cnt - hpet_readl(HPET_COUNTER));
410 416
411 return res < 8 ? -ETIME : 0; 417 return res < HPET_MIN_CYCLES ? -ETIME : 0;
412} 418}
413 419
414static void hpet_legacy_set_mode(enum clock_event_mode mode, 420static void hpet_legacy_set_mode(enum clock_event_mode mode,
diff --git a/arch/x86/kernel/resource.c b/arch/x86/kernel/resource.c
new file mode 100644
index 000000000000..2a26819bb6a8
--- /dev/null
+++ b/arch/x86/kernel/resource.c
@@ -0,0 +1,48 @@
1#include <linux/ioport.h>
2#include <asm/e820.h>
3
4static void resource_clip(struct resource *res, resource_size_t start,
5 resource_size_t end)
6{
7 resource_size_t low = 0, high = 0;
8
9 if (res->end < start || res->start > end)
10 return; /* no conflict */
11
12 if (res->start < start)
13 low = start - res->start;
14
15 if (res->end > end)
16 high = res->end - end;
17
18 /* Keep the area above or below the conflict, whichever is larger */
19 if (low > high)
20 res->end = start - 1;
21 else
22 res->start = end + 1;
23}
24
25static void remove_e820_regions(struct resource *avail)
26{
27 int i;
28 struct e820entry *entry;
29
30 for (i = 0; i < e820.nr_map; i++) {
31 entry = &e820.map[i];
32
33 resource_clip(avail, entry->addr,
34 entry->addr + entry->size - 1);
35 }
36}
37
38void arch_remove_reservations(struct resource *avail)
39{
40 /* Trim out BIOS areas (low 1MB and high 2MB) and E820 regions */
41 if (avail->flags & IORESOURCE_MEM) {
42 if (avail->start < BIOS_END)
43 avail->start = BIOS_END;
44 resource_clip(avail, BIOS_ROM_BASE, BIOS_ROM_END);
45
46 remove_e820_regions(avail);
47 }
48}
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index 21c6746338af..85268f8eadf6 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -769,7 +769,6 @@ void __init setup_arch(char **cmdline_p)
769 769
770 x86_init.oem.arch_setup(); 770 x86_init.oem.arch_setup();
771 771
772 resource_alloc_from_bottom = 0;
773 iomem_resource.end = (1ULL << boot_cpu_data.x86_phys_bits) - 1; 772 iomem_resource.end = (1ULL << boot_cpu_data.x86_phys_bits) - 1;
774 setup_memory_map(); 773 setup_memory_map();
775 parse_setup_data(); 774 parse_setup_data();
diff --git a/arch/x86/kernel/xsave.c b/arch/x86/kernel/xsave.c
index 9c253bd65e24..547128546cc3 100644
--- a/arch/x86/kernel/xsave.c
+++ b/arch/x86/kernel/xsave.c
@@ -394,7 +394,8 @@ static void __init setup_xstate_init(void)
394 * Setup init_xstate_buf to represent the init state of 394 * Setup init_xstate_buf to represent the init state of
395 * all the features managed by the xsave 395 * all the features managed by the xsave
396 */ 396 */
397 init_xstate_buf = alloc_bootmem(xstate_size); 397 init_xstate_buf = alloc_bootmem_align(xstate_size,
398 __alignof__(struct xsave_struct));
398 init_xstate_buf->i387.mxcsr = MXCSR_DEFAULT; 399 init_xstate_buf->i387.mxcsr = MXCSR_DEFAULT;
399 400
400 clts(); 401 clts();
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 1ca12298ffc7..b81a9b7c2ca4 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -3494,6 +3494,10 @@ static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3494static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) 3494static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3495{ 3495{
3496 switch (func) { 3496 switch (func) {
3497 case 0x00000001:
3498 /* Mask out xsave bit as long as it is not supported by SVM */
3499 entry->ecx &= ~(bit(X86_FEATURE_XSAVE));
3500 break;
3497 case 0x80000001: 3501 case 0x80000001:
3498 if (nested) 3502 if (nested)
3499 entry->ecx |= (1 << 2); /* Set SVM bit */ 3503 entry->ecx |= (1 << 2); /* Set SVM bit */
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index ff21fdda0c53..81fcbe9515c5 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -4227,11 +4227,6 @@ static int vmx_get_lpage_level(void)
4227 return PT_PDPE_LEVEL; 4227 return PT_PDPE_LEVEL;
4228} 4228}
4229 4229
4230static inline u32 bit(int bitno)
4231{
4232 return 1 << (bitno & 31);
4233}
4234
4235static void vmx_cpuid_update(struct kvm_vcpu *vcpu) 4230static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4236{ 4231{
4237 struct kvm_cpuid_entry2 *best; 4232 struct kvm_cpuid_entry2 *best;
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index cdac9e592aa5..b989e1f1e5d3 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -155,11 +155,6 @@ struct kvm_stats_debugfs_item debugfs_entries[] = {
155 155
156u64 __read_mostly host_xcr0; 156u64 __read_mostly host_xcr0;
157 157
158static inline u32 bit(int bitno)
159{
160 return 1 << (bitno & 31);
161}
162
163static void kvm_on_user_return(struct user_return_notifier *urn) 158static void kvm_on_user_return(struct user_return_notifier *urn)
164{ 159{
165 unsigned slot; 160 unsigned slot;
@@ -4569,9 +4564,11 @@ static void kvm_timer_init(void)
4569#ifdef CONFIG_CPU_FREQ 4564#ifdef CONFIG_CPU_FREQ
4570 struct cpufreq_policy policy; 4565 struct cpufreq_policy policy;
4571 memset(&policy, 0, sizeof(policy)); 4566 memset(&policy, 0, sizeof(policy));
4572 cpufreq_get_policy(&policy, get_cpu()); 4567 cpu = get_cpu();
4568 cpufreq_get_policy(&policy, cpu);
4573 if (policy.cpuinfo.max_freq) 4569 if (policy.cpuinfo.max_freq)
4574 max_tsc_khz = policy.cpuinfo.max_freq; 4570 max_tsc_khz = policy.cpuinfo.max_freq;
4571 put_cpu();
4575#endif 4572#endif
4576 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 4573 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4577 CPUFREQ_TRANSITION_NOTIFIER); 4574 CPUFREQ_TRANSITION_NOTIFIER);
@@ -5522,6 +5519,8 @@ int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5522 5519
5523 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 5520 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
5524 kvm_x86_ops->set_cr4(vcpu, sregs->cr4); 5521 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
5522 if (sregs->cr4 & X86_CR4_OSXSAVE)
5523 update_cpuid(vcpu);
5525 if (!is_long_mode(vcpu) && is_pae(vcpu)) { 5524 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
5526 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3); 5525 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
5527 mmu_reset_needed = 1; 5526 mmu_reset_needed = 1;
diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h
index 2cea414489f3..c600da830ce0 100644
--- a/arch/x86/kvm/x86.h
+++ b/arch/x86/kvm/x86.h
@@ -70,6 +70,11 @@ static inline int is_paging(struct kvm_vcpu *vcpu)
70 return kvm_read_cr0_bits(vcpu, X86_CR0_PG); 70 return kvm_read_cr0_bits(vcpu, X86_CR0_PG);
71} 71}
72 72
73static inline u32 bit(int bitno)
74{
75 return 1 << (bitno & 31);
76}
77
73void kvm_before_handle_nmi(struct kvm_vcpu *vcpu); 78void kvm_before_handle_nmi(struct kvm_vcpu *vcpu);
74void kvm_after_handle_nmi(struct kvm_vcpu *vcpu); 79void kvm_after_handle_nmi(struct kvm_vcpu *vcpu);
75int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq); 80int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq);
diff --git a/arch/x86/lguest/boot.c b/arch/x86/lguest/boot.c
index 73b1e1a1f489..4996cf5f73a0 100644
--- a/arch/x86/lguest/boot.c
+++ b/arch/x86/lguest/boot.c
@@ -531,7 +531,10 @@ static void lguest_write_cr3(unsigned long cr3)
531{ 531{
532 lguest_data.pgdir = cr3; 532 lguest_data.pgdir = cr3;
533 lazy_hcall1(LHCALL_NEW_PGTABLE, cr3); 533 lazy_hcall1(LHCALL_NEW_PGTABLE, cr3);
534 cr3_changed = true; 534
535 /* These two page tables are simple, linear, and used during boot */
536 if (cr3 != __pa(swapper_pg_dir) && cr3 != __pa(initial_page_table))
537 cr3_changed = true;
535} 538}
536 539
537static unsigned long lguest_read_cr3(void) 540static unsigned long lguest_read_cr3(void)
@@ -703,9 +706,9 @@ static void lguest_set_pmd(pmd_t *pmdp, pmd_t pmdval)
703 * to forget all of them. Fortunately, this is very rare. 706 * to forget all of them. Fortunately, this is very rare.
704 * 707 *
705 * ... except in early boot when the kernel sets up the initial pagetables, 708 * ... except in early boot when the kernel sets up the initial pagetables,
706 * which makes booting astonishingly slow: 1.83 seconds! So we don't even tell 709 * which makes booting astonishingly slow: 48 seconds! So we don't even tell
707 * the Host anything changed until we've done the first page table switch, 710 * the Host anything changed until we've done the first real page table switch,
708 * which brings boot back to 0.25 seconds. 711 * which brings boot back to 4.3 seconds.
709 */ 712 */
710static void lguest_set_pte(pte_t *ptep, pte_t pteval) 713static void lguest_set_pte(pte_t *ptep, pte_t pteval)
711{ 714{
@@ -1002,7 +1005,7 @@ static void lguest_time_init(void)
1002 clockevents_register_device(&lguest_clockevent); 1005 clockevents_register_device(&lguest_clockevent);
1003 1006
1004 /* Finally, we unblock the timer interrupt. */ 1007 /* Finally, we unblock the timer interrupt. */
1005 enable_lguest_irq(0); 1008 clear_bit(0, lguest_data.blocked_interrupts);
1006} 1009}
1007 1010
1008/* 1011/*
@@ -1349,9 +1352,6 @@ __init void lguest_init(void)
1349 */ 1352 */
1350 switch_to_new_gdt(0); 1353 switch_to_new_gdt(0);
1351 1354
1352 /* We actually boot with all memory mapped, but let's say 128MB. */
1353 max_pfn_mapped = (128*1024*1024) >> PAGE_SHIFT;
1354
1355 /* 1355 /*
1356 * The Host<->Guest Switcher lives at the top of our address space, and 1356 * The Host<->Guest Switcher lives at the top of our address space, and
1357 * the Host told us how big it is when we made LGUEST_INIT hypercall: 1357 * the Host told us how big it is when we made LGUEST_INIT hypercall:
diff --git a/arch/x86/lguest/i386_head.S b/arch/x86/lguest/i386_head.S
index 4f420c2f2d55..e7d5382ef263 100644
--- a/arch/x86/lguest/i386_head.S
+++ b/arch/x86/lguest/i386_head.S
@@ -4,6 +4,7 @@
4#include <asm/asm-offsets.h> 4#include <asm/asm-offsets.h>
5#include <asm/thread_info.h> 5#include <asm/thread_info.h>
6#include <asm/processor-flags.h> 6#include <asm/processor-flags.h>
7#include <asm/pgtable.h>
7 8
8/*G:020 9/*G:020
9 * Our story starts with the kernel booting into startup_32 in 10 * Our story starts with the kernel booting into startup_32 in
@@ -37,9 +38,113 @@ ENTRY(lguest_entry)
37 /* Set up the initial stack so we can run C code. */ 38 /* Set up the initial stack so we can run C code. */
38 movl $(init_thread_union+THREAD_SIZE),%esp 39 movl $(init_thread_union+THREAD_SIZE),%esp
39 40
41 call init_pagetables
42
40 /* Jumps are relative: we're running __PAGE_OFFSET too low. */ 43 /* Jumps are relative: we're running __PAGE_OFFSET too low. */
41 jmp lguest_init+__PAGE_OFFSET 44 jmp lguest_init+__PAGE_OFFSET
42 45
46/*
47 * Initialize page tables. This creates a PDE and a set of page
48 * tables, which are located immediately beyond __brk_base. The variable
49 * _brk_end is set up to point to the first "safe" location.
50 * Mappings are created both at virtual address 0 (identity mapping)
51 * and PAGE_OFFSET for up to _end.
52 *
53 * FIXME: This code is taken verbatim from arch/x86/kernel/head_32.S: they
54 * don't have a stack at this point, so we can't just use call and ret.
55 */
56init_pagetables:
57#if PTRS_PER_PMD > 1
58#define PAGE_TABLE_SIZE(pages) (((pages) / PTRS_PER_PMD) + PTRS_PER_PGD)
59#else
60#define PAGE_TABLE_SIZE(pages) ((pages) / PTRS_PER_PGD)
61#endif
62#define pa(X) ((X) - __PAGE_OFFSET)
63
64/* Enough space to fit pagetables for the low memory linear map */
65MAPPING_BEYOND_END = \
66 PAGE_TABLE_SIZE(((1<<32) - __PAGE_OFFSET) >> PAGE_SHIFT) << PAGE_SHIFT
67#ifdef CONFIG_X86_PAE
68
69 /*
70 * In PAE mode initial_page_table is statically defined to contain
71 * enough entries to cover the VMSPLIT option (that is the top 1, 2 or 3
72 * entries). The identity mapping is handled by pointing two PGD entries
73 * to the first kernel PMD.
74 *
75 * Note the upper half of each PMD or PTE are always zero at this stage.
76 */
77
78#define KPMDS (((-__PAGE_OFFSET) >> 30) & 3) /* Number of kernel PMDs */
79
80 xorl %ebx,%ebx /* %ebx is kept at zero */
81
82 movl $pa(__brk_base), %edi
83 movl $pa(initial_pg_pmd), %edx
84 movl $PTE_IDENT_ATTR, %eax
8510:
86 leal PDE_IDENT_ATTR(%edi),%ecx /* Create PMD entry */
87 movl %ecx,(%edx) /* Store PMD entry */
88 /* Upper half already zero */
89 addl $8,%edx
90 movl $512,%ecx
9111:
92 stosl
93 xchgl %eax,%ebx
94 stosl
95 xchgl %eax,%ebx
96 addl $0x1000,%eax
97 loop 11b
98
99 /*
100 * End condition: we must map up to the end + MAPPING_BEYOND_END.
101 */
102 movl $pa(_end) + MAPPING_BEYOND_END + PTE_IDENT_ATTR, %ebp
103 cmpl %ebp,%eax
104 jb 10b
1051:
106 addl $__PAGE_OFFSET, %edi
107 movl %edi, pa(_brk_end)
108 shrl $12, %eax
109 movl %eax, pa(max_pfn_mapped)
110
111 /* Do early initialization of the fixmap area */
112 movl $pa(initial_pg_fixmap)+PDE_IDENT_ATTR,%eax
113 movl %eax,pa(initial_pg_pmd+0x1000*KPMDS-8)
114#else /* Not PAE */
115
116page_pde_offset = (__PAGE_OFFSET >> 20);
117
118 movl $pa(__brk_base), %edi
119 movl $pa(initial_page_table), %edx
120 movl $PTE_IDENT_ATTR, %eax
12110:
122 leal PDE_IDENT_ATTR(%edi),%ecx /* Create PDE entry */
123 movl %ecx,(%edx) /* Store identity PDE entry */
124 movl %ecx,page_pde_offset(%edx) /* Store kernel PDE entry */
125 addl $4,%edx
126 movl $1024, %ecx
12711:
128 stosl
129 addl $0x1000,%eax
130 loop 11b
131 /*
132 * End condition: we must map up to the end + MAPPING_BEYOND_END.
133 */
134 movl $pa(_end) + MAPPING_BEYOND_END + PTE_IDENT_ATTR, %ebp
135 cmpl %ebp,%eax
136 jb 10b
137 addl $__PAGE_OFFSET, %edi
138 movl %edi, pa(_brk_end)
139 shrl $12, %eax
140 movl %eax, pa(max_pfn_mapped)
141
142 /* Do early initialization of the fixmap area */
143 movl $pa(initial_pg_fixmap)+PDE_IDENT_ATTR,%eax
144 movl %eax,pa(initial_page_table+0xffc)
145#endif
146 ret
147
43/*G:055 148/*G:055
44 * We create a macro which puts the assembler code between lgstart_ and lgend_ 149 * We create a macro which puts the assembler code between lgstart_ and lgend_
45 * markers. These templates are put in the .text section: they can't be 150 * markers. These templates are put in the .text section: they can't be
diff --git a/arch/x86/pci/i386.c b/arch/x86/pci/i386.c
index c4bb261c106e..b1805b78842f 100644
--- a/arch/x86/pci/i386.c
+++ b/arch/x86/pci/i386.c
@@ -65,21 +65,13 @@ pcibios_align_resource(void *data, const struct resource *res,
65 resource_size_t size, resource_size_t align) 65 resource_size_t size, resource_size_t align)
66{ 66{
67 struct pci_dev *dev = data; 67 struct pci_dev *dev = data;
68 resource_size_t start = round_down(res->end - size + 1, align); 68 resource_size_t start = res->start;
69 69
70 if (res->flags & IORESOURCE_IO) { 70 if (res->flags & IORESOURCE_IO) {
71 71 if (skip_isa_ioresource_align(dev))
72 /* 72 return start;
73 * If we're avoiding ISA aliases, the largest contiguous I/O 73 if (start & 0x300)
74 * port space is 256 bytes. Clearing bits 9 and 10 preserves 74 start = (start + 0x3ff) & ~0x3ff;
75 * all 256-byte and smaller alignments, so the result will
76 * still be correctly aligned.
77 */
78 if (!skip_isa_ioresource_align(dev))
79 start &= ~0x300;
80 } else if (res->flags & IORESOURCE_MEM) {
81 if (start < BIOS_END)
82 start = res->end; /* fail; no space */
83 } 75 }
84 return start; 76 return start;
85} 77}
diff --git a/arch/x86/vdso/Makefile b/arch/x86/vdso/Makefile
index 4a2afa1bac51..b6552b189bcd 100644
--- a/arch/x86/vdso/Makefile
+++ b/arch/x86/vdso/Makefile
@@ -25,7 +25,7 @@ targets += vdso.so vdso.so.dbg vdso.lds $(vobjs-y)
25 25
26export CPPFLAGS_vdso.lds += -P -C 26export CPPFLAGS_vdso.lds += -P -C
27 27
28VDSO_LDFLAGS_vdso.lds = -m elf_x86_64 -Wl,-soname=linux-vdso.so.1 \ 28VDSO_LDFLAGS_vdso.lds = -m64 -Wl,-soname=linux-vdso.so.1 \
29 -Wl,-z,max-page-size=4096 -Wl,-z,common-page-size=4096 29 -Wl,-z,max-page-size=4096 -Wl,-z,common-page-size=4096
30 30
31$(obj)/vdso.o: $(src)/vdso.S $(obj)/vdso.so 31$(obj)/vdso.o: $(src)/vdso.S $(obj)/vdso.so
@@ -69,7 +69,7 @@ vdso32.so-$(VDSO32-y) += sysenter
69vdso32-images = $(vdso32.so-y:%=vdso32-%.so) 69vdso32-images = $(vdso32.so-y:%=vdso32-%.so)
70 70
71CPPFLAGS_vdso32.lds = $(CPPFLAGS_vdso.lds) 71CPPFLAGS_vdso32.lds = $(CPPFLAGS_vdso.lds)
72VDSO_LDFLAGS_vdso32.lds = -m elf_i386 -Wl,-soname=linux-gate.so.1 72VDSO_LDFLAGS_vdso32.lds = -m32 -Wl,-soname=linux-gate.so.1
73 73
74# This makes sure the $(obj) subdirectory exists even though vdso32/ 74# This makes sure the $(obj) subdirectory exists even though vdso32/
75# is not a kbuild sub-make subdirectory. 75# is not a kbuild sub-make subdirectory.
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-06 14:20:46 -0400