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authorManuel Lauss <manuel.lauss@googlemail.com>2009-11-02 15:21:43 -0500
committerRalf Baechle <ralf@linux-mips.org>2010-02-27 06:53:00 -0500
commit63323ec54a7e922a232c82070727e44eb1a5b43c (patch)
tree4f78c66c8db7fdaded28a3eaf76f196bd1c59753 /arch
parent206aa6cdadad8bbedee5649f1346fe47e922a039 (diff)
MIPS: Alchemy: Extended DB1200 board support.
Create own directory for DB1200 code and update it with new features. - SPI support: - tmp121 temperature sensor - SPI flash on DB1200 - I2C support - NE1619 sensor - AT24 eeprom - I2C/SPI can be selected at boot time via switch S6.8 - Carddetect IRQs for SD cards. - gen_nand based NAND support. - hexleds count sleep/wake transitions. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/alchemy/common/reset.c3
-rw-r--r--arch/mips/alchemy/devboards/Makefile2
-rw-r--r--arch/mips/alchemy/devboards/db1200/Makefile1
-rw-r--r--arch/mips/alchemy/devboards/db1200/platform.c510
-rw-r--r--arch/mips/alchemy/devboards/db1200/setup.c137
-rw-r--r--arch/mips/alchemy/devboards/pb1200/board_setup.c9
-rw-r--r--arch/mips/alchemy/devboards/pb1200/platform.c34
-rw-r--r--arch/mips/include/asm/mach-db1x00/db1200.h33
8 files changed, 654 insertions, 75 deletions
diff --git a/arch/mips/alchemy/common/reset.c b/arch/mips/alchemy/common/reset.c
index 4791011e8f92..266afd48c194 100644
--- a/arch/mips/alchemy/common/reset.c
+++ b/arch/mips/alchemy/common/reset.c
@@ -164,9 +164,6 @@ void au1000_halt(void)
164#ifdef CONFIG_MIPS_MIRAGE 164#ifdef CONFIG_MIPS_MIRAGE
165 gpio_direction_output(210, 1); 165 gpio_direction_output(210, 1);
166#endif 166#endif
167#ifdef CONFIG_MIPS_DB1200
168 au_writew(au_readw(0xB980001C) | (1 << 14), 0xB980001C);
169#endif
170#ifdef CONFIG_PM 167#ifdef CONFIG_PM
171 au_sleep(); 168 au_sleep();
172 169
diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile
index c74ef80b92fc..ecbd37f9ee87 100644
--- a/arch/mips/alchemy/devboards/Makefile
+++ b/arch/mips/alchemy/devboards/Makefile
@@ -11,7 +11,7 @@ obj-$(CONFIG_MIPS_PB1500) += pb1500/
11obj-$(CONFIG_MIPS_PB1550) += pb1550/ 11obj-$(CONFIG_MIPS_PB1550) += pb1550/
12obj-$(CONFIG_MIPS_DB1000) += db1x00/ 12obj-$(CONFIG_MIPS_DB1000) += db1x00/
13obj-$(CONFIG_MIPS_DB1100) += db1x00/ 13obj-$(CONFIG_MIPS_DB1100) += db1x00/
14obj-$(CONFIG_MIPS_DB1200) += pb1200/ 14obj-$(CONFIG_MIPS_DB1200) += db1200/
15obj-$(CONFIG_MIPS_DB1500) += db1x00/ 15obj-$(CONFIG_MIPS_DB1500) += db1x00/
16obj-$(CONFIG_MIPS_DB1550) += db1x00/ 16obj-$(CONFIG_MIPS_DB1550) += db1x00/
17obj-$(CONFIG_MIPS_BOSPORUS) += db1x00/ 17obj-$(CONFIG_MIPS_BOSPORUS) += db1x00/
diff --git a/arch/mips/alchemy/devboards/db1200/Makefile b/arch/mips/alchemy/devboards/db1200/Makefile
new file mode 100644
index 000000000000..17840a5e2738
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1200/Makefile
@@ -0,0 +1 @@
obj-y += setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c
new file mode 100644
index 000000000000..5a6ef8deda10
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1200/platform.c
@@ -0,0 +1,510 @@
1/*
2 * DBAu1200 board platform device registration
3 *
4 * Copyright (C) 2008-2009 Manuel Lauss
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/dma-mapping.h>
22#include <linux/gpio.h>
23#include <linux/i2c.h>
24#include <linux/init.h>
25#include <linux/io.h>
26#include <linux/leds.h>
27#include <linux/mmc/host.h>
28#include <linux/mtd/mtd.h>
29#include <linux/mtd/nand.h>
30#include <linux/mtd/partitions.h>
31#include <linux/platform_device.h>
32#include <linux/serial_8250.h>
33#include <linux/spi/spi.h>
34#include <linux/spi/flash.h>
35#include <linux/smc91x.h>
36
37#include <asm/mach-au1x00/au1100_mmc.h>
38#include <asm/mach-au1x00/au1xxx_dbdma.h>
39#include <asm/mach-au1x00/au1550_spi.h>
40#include <asm/mach-db1x00/bcsr.h>
41#include <asm/mach-db1x00/db1200.h>
42
43#include "../platform.h"
44
45static struct mtd_partition db1200_spiflash_parts[] = {
46 {
47 .name = "DB1200 SPI flash",
48 .offset = 0,
49 .size = MTDPART_SIZ_FULL,
50 },
51};
52
53static struct flash_platform_data db1200_spiflash_data = {
54 .name = "s25fl001",
55 .parts = db1200_spiflash_parts,
56 .nr_parts = ARRAY_SIZE(db1200_spiflash_parts),
57 .type = "m25p10",
58};
59
60static struct spi_board_info db1200_spi_devs[] __initdata = {
61 {
62 /* TI TMP121AIDBVR temp sensor */
63 .modalias = "tmp121",
64 .max_speed_hz = 2000000,
65 .bus_num = 0,
66 .chip_select = 0,
67 .mode = 0,
68 },
69 {
70 /* Spansion S25FL001D0FMA SPI flash */
71 .modalias = "m25p80",
72 .max_speed_hz = 50000000,
73 .bus_num = 0,
74 .chip_select = 1,
75 .mode = 0,
76 .platform_data = &db1200_spiflash_data,
77 },
78};
79
80static struct i2c_board_info db1200_i2c_devs[] __initdata = {
81 {
82 /* AT24C04-10 I2C eeprom */
83 I2C_BOARD_INFO("24c04", 0x52),
84 },
85 {
86 /* Philips NE1619 temp/voltage sensor (adm1025 drv) */
87 I2C_BOARD_INFO("ne1619", 0x2d),
88 },
89 {
90 /* I2S audio codec WM8731 */
91 I2C_BOARD_INFO("wm8731", 0x1b),
92 },
93};
94
95/**********************************************************************/
96
97static void au1200_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
98 unsigned int ctrl)
99{
100 struct nand_chip *this = mtd->priv;
101 unsigned long ioaddr = (unsigned long)this->IO_ADDR_W;
102
103 ioaddr &= 0xffffff00;
104
105 if (ctrl & NAND_CLE) {
106 ioaddr += MEM_STNAND_CMD;
107 } else if (ctrl & NAND_ALE) {
108 ioaddr += MEM_STNAND_ADDR;
109 } else {
110 /* assume we want to r/w real data by default */
111 ioaddr += MEM_STNAND_DATA;
112 }
113 this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr;
114 if (cmd != NAND_CMD_NONE) {
115 __raw_writeb(cmd, this->IO_ADDR_W);
116 wmb();
117 }
118}
119
120static int au1200_nand_device_ready(struct mtd_info *mtd)
121{
122 return __raw_readl((void __iomem *)MEM_STSTAT) & 1;
123}
124
125static const char *db1200_part_probes[] = { "cmdlinepart", NULL };
126
127static struct mtd_partition db1200_nand_parts[] = {
128 {
129 .name = "NAND FS 0",
130 .offset = 0,
131 .size = 8 * 1024 * 1024,
132 },
133 {
134 .name = "NAND FS 1",
135 .offset = MTDPART_OFS_APPEND,
136 .size = MTDPART_SIZ_FULL
137 },
138};
139
140struct platform_nand_data db1200_nand_platdata = {
141 .chip = {
142 .nr_chips = 1,
143 .chip_offset = 0,
144 .nr_partitions = ARRAY_SIZE(db1200_nand_parts),
145 .partitions = db1200_nand_parts,
146 .chip_delay = 20,
147 .part_probe_types = db1200_part_probes,
148 },
149 .ctrl = {
150 .dev_ready = au1200_nand_device_ready,
151 .cmd_ctrl = au1200_nand_cmd_ctrl,
152 },
153};
154
155static struct resource db1200_nand_res[] = {
156 [0] = {
157 .start = DB1200_NAND_PHYS_ADDR,
158 .end = DB1200_NAND_PHYS_ADDR + 0xff,
159 .flags = IORESOURCE_MEM,
160 },
161};
162
163static struct platform_device db1200_nand_dev = {
164 .name = "gen_nand",
165 .num_resources = ARRAY_SIZE(db1200_nand_res),
166 .resource = db1200_nand_res,
167 .id = -1,
168 .dev = {
169 .platform_data = &db1200_nand_platdata,
170 }
171};
172
173/**********************************************************************/
174
175static struct smc91x_platdata db1200_eth_data = {
176 .flags = SMC91X_NOWAIT | SMC91X_USE_16BIT,
177 .leda = RPC_LED_100_10,
178 .ledb = RPC_LED_TX_RX,
179};
180
181static struct resource db1200_eth_res[] = {
182 [0] = {
183 .start = DB1200_ETH_PHYS_ADDR,
184 .end = DB1200_ETH_PHYS_ADDR + 0xf,
185 .flags = IORESOURCE_MEM,
186 },
187 [1] = {
188 .start = DB1200_ETH_INT,
189 .end = DB1200_ETH_INT,
190 .flags = IORESOURCE_IRQ,
191 },
192};
193
194static struct platform_device db1200_eth_dev = {
195 .dev = {
196 .platform_data = &db1200_eth_data,
197 },
198 .name = "smc91x",
199 .id = -1,
200 .num_resources = ARRAY_SIZE(db1200_eth_res),
201 .resource = db1200_eth_res,
202};
203
204/**********************************************************************/
205
206static struct resource db1200_ide_res[] = {
207 [0] = {
208 .start = DB1200_IDE_PHYS_ADDR,
209 .end = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1,
210 .flags = IORESOURCE_MEM,
211 },
212 [1] = {
213 .start = DB1200_IDE_INT,
214 .end = DB1200_IDE_INT,
215 .flags = IORESOURCE_IRQ,
216 }
217};
218
219static u64 ide_dmamask = DMA_32BIT_MASK;
220
221static struct platform_device db1200_ide_dev = {
222 .name = "au1200-ide",
223 .id = 0,
224 .dev = {
225 .dma_mask = &ide_dmamask,
226 .coherent_dma_mask = DMA_32BIT_MASK,
227 },
228 .num_resources = ARRAY_SIZE(db1200_ide_res),
229 .resource = db1200_ide_res,
230};
231
232/**********************************************************************/
233
234static struct platform_device db1200_rtc_dev = {
235 .name = "rtc-au1xxx",
236 .id = -1,
237};
238
239/**********************************************************************/
240
241/* SD carddetects: they're supposed to be edge-triggered, but ack
242 * doesn't seem to work (CPLD Rev 2). Instead, the screaming one
243 * is disabled and its counterpart enabled. The 500ms timeout is
244 * because the carddetect isn't debounced in hardware.
245 */
246static irqreturn_t db1200_mmc_cd(int irq, void *ptr)
247{
248 void(*mmc_cd)(struct mmc_host *, unsigned long);
249
250 if (irq == DB1200_SD0_INSERT_INT) {
251 disable_irq_nosync(DB1200_SD0_INSERT_INT);
252 enable_irq(DB1200_SD0_EJECT_INT);
253 } else {
254 disable_irq_nosync(DB1200_SD0_EJECT_INT);
255 enable_irq(DB1200_SD0_INSERT_INT);
256 }
257
258 /* link against CONFIG_MMC=m */
259 mmc_cd = symbol_get(mmc_detect_change);
260 if (mmc_cd) {
261 mmc_cd(ptr, msecs_to_jiffies(500));
262 symbol_put(mmc_detect_change);
263 }
264
265 return IRQ_HANDLED;
266}
267
268static int db1200_mmc_cd_setup(void *mmc_host, int en)
269{
270 int ret;
271
272 if (en) {
273 ret = request_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd,
274 IRQF_DISABLED, "sd_insert", mmc_host);
275 if (ret)
276 goto out;
277
278 ret = request_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd,
279 IRQF_DISABLED, "sd_eject", mmc_host);
280 if (ret) {
281 free_irq(DB1200_SD0_INSERT_INT, mmc_host);
282 goto out;
283 }
284
285 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT)
286 enable_irq(DB1200_SD0_EJECT_INT);
287 else
288 enable_irq(DB1200_SD0_INSERT_INT);
289
290 } else {
291 free_irq(DB1200_SD0_INSERT_INT, mmc_host);
292 free_irq(DB1200_SD0_EJECT_INT, mmc_host);
293 }
294 ret = 0;
295out:
296 return ret;
297}
298
299static void db1200_mmc_set_power(void *mmc_host, int state)
300{
301 if (state) {
302 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR);
303 msleep(400); /* stabilization time */
304 } else
305 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0);
306}
307
308static int db1200_mmc_card_readonly(void *mmc_host)
309{
310 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0;
311}
312
313static int db1200_mmc_card_inserted(void *mmc_host)
314{
315 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0;
316}
317
318static void db1200_mmcled_set(struct led_classdev *led,
319 enum led_brightness brightness)
320{
321 if (brightness != LED_OFF)
322 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
323 else
324 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
325}
326
327static struct led_classdev db1200_mmc_led = {
328 .brightness_set = db1200_mmcled_set,
329};
330
331/* needed by arch/mips/alchemy/common/platform.c */
332struct au1xmmc_platform_data au1xmmc_platdata[] = {
333 [0] = {
334 .cd_setup = db1200_mmc_cd_setup,
335 .set_power = db1200_mmc_set_power,
336 .card_inserted = db1200_mmc_card_inserted,
337 .card_readonly = db1200_mmc_card_readonly,
338 .led = &db1200_mmc_led,
339 },
340};
341
342/**********************************************************************/
343
344static struct resource au1200_psc0_res[] = {
345 [0] = {
346 .start = PSC0_PHYS_ADDR,
347 .end = PSC0_PHYS_ADDR + 0x000fffff,
348 .flags = IORESOURCE_MEM,
349 },
350 [1] = {
351 .start = AU1200_PSC0_INT,
352 .end = AU1200_PSC0_INT,
353 .flags = IORESOURCE_IRQ,
354 },
355 [2] = {
356 .start = DSCR_CMD0_PSC0_TX,
357 .end = DSCR_CMD0_PSC0_TX,
358 .flags = IORESOURCE_DMA,
359 },
360 [3] = {
361 .start = DSCR_CMD0_PSC0_RX,
362 .end = DSCR_CMD0_PSC0_RX,
363 .flags = IORESOURCE_DMA,
364 },
365};
366
367static struct platform_device db1200_i2c_dev = {
368 .name = "au1xpsc_smbus",
369 .id = 0, /* bus number */
370 .num_resources = ARRAY_SIZE(au1200_psc0_res),
371 .resource = au1200_psc0_res,
372};
373
374static void db1200_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol)
375{
376 if (cs)
377 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_SPISEL);
378 else
379 bcsr_mod(BCSR_RESETS, BCSR_RESETS_SPISEL, 0);
380}
381
382static struct au1550_spi_info db1200_spi_platdata = {
383 .mainclk_hz = 50000000, /* PSC0 clock */
384 .num_chipselect = 2,
385 .activate_cs = db1200_spi_cs_en,
386};
387
388static u64 spi_dmamask = DMA_32BIT_MASK;
389
390static struct platform_device db1200_spi_dev = {
391 .dev = {
392 .dma_mask = &spi_dmamask,
393 .coherent_dma_mask = DMA_32BIT_MASK,
394 .platform_data = &db1200_spi_platdata,
395 },
396 .name = "au1550-spi",
397 .id = 0, /* bus number */
398 .num_resources = ARRAY_SIZE(au1200_psc0_res),
399 .resource = au1200_psc0_res,
400};
401
402static struct platform_device *db1200_devs[] __initdata = {
403 NULL, /* PSC0, selected by S6.8 */
404 &db1200_ide_dev,
405 &db1200_eth_dev,
406 &db1200_rtc_dev,
407 &db1200_nand_dev,
408};
409
410static int __init db1200_dev_init(void)
411{
412 unsigned long pfc;
413 unsigned short sw;
414 int swapped;
415
416 i2c_register_board_info(0, db1200_i2c_devs,
417 ARRAY_SIZE(db1200_i2c_devs));
418 spi_register_board_info(db1200_spi_devs,
419 ARRAY_SIZE(db1200_i2c_devs));
420
421 /* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI)
422 */
423
424 /* NOTE: GPIO215 controls OTG VBUS supply. In SPI mode however
425 * this pin is claimed by PSC0 (unused though, but pinmux doesn't
426 * allow to free it without crippling the SPI interface).
427 * As a result, in SPI mode, OTG simply won't work (PSC0 uses
428 * it as an input pin which is pulled high on the boards).
429 */
430 pfc = __raw_readl((void __iomem *)SYS_PINFUNC) & ~SYS_PINFUNC_P0A;
431
432 /* switch off OTG VBUS supply */
433 gpio_request(215, "otg-vbus");
434 gpio_direction_output(215, 1);
435
436 printk(KERN_INFO "DB1200 device configuration:\n");
437
438 sw = bcsr_read(BCSR_SWITCHES);
439 if (sw & BCSR_SWITCHES_DIP_8) {
440 db1200_devs[0] = &db1200_i2c_dev;
441 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
442
443 pfc |= (2 << 17); /* GPIO2 block owns GPIO215 */
444
445 printk(KERN_INFO " S6.8 OFF: PSC0 mode I2C\n");
446 printk(KERN_INFO " OTG port VBUS supply available!\n");
447 } else {
448 db1200_devs[0] = &db1200_spi_dev;
449 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC0MUX);
450
451 pfc |= (1 << 17); /* PSC0 owns GPIO215 */
452
453 printk(KERN_INFO " S6.8 ON : PSC0 mode SPI\n");
454 printk(KERN_INFO " OTG port VBUS supply disabled\n");
455 }
456 __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
457 wmb();
458
459 db1x_register_pcmcia_socket(PCMCIA_ATTR_PSEUDO_PHYS,
460 PCMCIA_ATTR_PSEUDO_PHYS + 0x00040000 - 1,
461 PCMCIA_MEM_PSEUDO_PHYS,
462 PCMCIA_MEM_PSEUDO_PHYS + 0x00040000 - 1,
463 PCMCIA_IO_PSEUDO_PHYS,
464 PCMCIA_IO_PSEUDO_PHYS + 0x00001000 - 1,
465 DB1200_PC0_INT,
466 DB1200_PC0_INSERT_INT,
467 /*DB1200_PC0_STSCHG_INT*/0,
468 DB1200_PC0_EJECT_INT,
469 0);
470
471 db1x_register_pcmcia_socket(PCMCIA_ATTR_PSEUDO_PHYS + 0x00400000,
472 PCMCIA_ATTR_PSEUDO_PHYS + 0x00440000 - 1,
473 PCMCIA_MEM_PSEUDO_PHYS + 0x00400000,
474 PCMCIA_MEM_PSEUDO_PHYS + 0x00440000 - 1,
475 PCMCIA_IO_PSEUDO_PHYS + 0x00400000,
476 PCMCIA_IO_PSEUDO_PHYS + 0x00401000 - 1,
477 DB1200_PC1_INT,
478 DB1200_PC1_INSERT_INT,
479 /*DB1200_PC1_STSCHG_INT*/0,
480 DB1200_PC1_EJECT_INT,
481 1);
482
483 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
484 db1x_register_norflash(64 << 20, 2, swapped);
485
486 return platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs));
487}
488device_initcall(db1200_dev_init);
489
490/* au1200fb calls these: STERBT EINEN TRAGISCHEN TOD!!! */
491int board_au1200fb_panel(void)
492{
493 return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
494}
495
496int board_au1200fb_panel_init(void)
497{
498 /* Apply power */
499 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
500 BCSR_BOARD_LCDBL);
501 return 0;
502}
503
504int board_au1200fb_panel_shutdown(void)
505{
506 /* Remove power */
507 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
508 BCSR_BOARD_LCDBL, 0);
509 return 0;
510}
diff --git a/arch/mips/alchemy/devboards/db1200/setup.c b/arch/mips/alchemy/devboards/db1200/setup.c
new file mode 100644
index 000000000000..a3458c0e4051
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1200/setup.c
@@ -0,0 +1,137 @@
1/*
2 * Alchemy/AMD/RMI DB1200 board setup.
3 *
4 * Licensed under the terms outlined in the file COPYING in the root of
5 * this source archive.
6 */
7
8#include <linux/init.h>
9#include <linux/interrupt.h>
10#include <linux/io.h>
11#include <linux/kernel.h>
12#include <linux/pm.h>
13#include <asm/mach-au1x00/au1000.h>
14#include <asm/mach-db1x00/bcsr.h>
15#include <asm/mach-db1x00/db1200.h>
16#include <asm/processor.h>
17#include <asm/reboot.h>
18
19const char *get_system_type(void)
20{
21 return "Alchemy Db1200";
22}
23
24static void board_power_off(void)
25{
26 bcsr_write(BCSR_RESETS, 0);
27 bcsr_write(BCSR_SYSTEM, BCSR_SYSTEM_PWROFF | BCSR_SYSTEM_RESET);
28}
29
30void board_reset(void)
31{
32 bcsr_write(BCSR_RESETS, 0);
33 bcsr_write(BCSR_SYSTEM, 0);
34}
35
36void __init board_setup(void)
37{
38 unsigned long freq0, clksrc, div, pfc;
39 unsigned short whoami;
40
41 bcsr_init(DB1200_BCSR_PHYS_ADDR,
42 DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
43
44 whoami = bcsr_read(BCSR_WHOAMI);
45 printk(KERN_INFO "Alchemy/AMD/RMI DB1200 Board, CPLD Rev %d"
46 " Board-ID %d Daughtercard ID %d\n",
47 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
48
49 /* SMBus/SPI on PSC0, Audio on PSC1 */
50 pfc = __raw_readl((void __iomem *)SYS_PINFUNC);
51 pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
52 pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);
53 pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */
54 __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
55 wmb();
56
57 /* Clock configurations: PSC0: ~50MHz via Clkgen0, derived from
58 * CPU clock; all other clock generators off/unused.
59 */
60 div = (get_au1x00_speed() + 25000000) / 50000000;
61 if (div & 1)
62 div++;
63 div = ((div >> 1) - 1) & 0xff;
64
65 freq0 = div << SYS_FC_FRDIV0_BIT;
66 __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
67 wmb();
68 freq0 |= SYS_FC_FE0; /* enable F0 */
69 __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
70 wmb();
71
72 /* psc0_intclk comes 1:1 from F0 */
73 clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT;
74 __raw_writel(clksrc, (void __iomem *)SYS_CLKSRC);
75 wmb();
76
77 pm_power_off = board_power_off;
78 _machine_halt = board_power_off;
79 _machine_restart = (void(*)(char *))board_reset;
80}
81
82/* use the hexleds to count the number of times the cpu has entered
83 * wait, the dots to indicate whether the CPU is currently idle or
84 * active (dots off = sleeping, dots on = working) for cases where
85 * the number doesn't change for a long(er) period of time.
86 */
87static void db1200_wait(void)
88{
89 __asm__(" .set push \n"
90 " .set mips3 \n"
91 " .set noreorder \n"
92 " cache 0x14, 0(%0) \n"
93 " cache 0x14, 32(%0) \n"
94 " cache 0x14, 64(%0) \n"
95 /* dots off: we're about to call wait */
96 " lui $26, 0xb980 \n"
97 " ori $27, $0, 3 \n"
98 " sb $27, 0x18($26) \n"
99 " sync \n"
100 " nop \n"
101 " wait \n"
102 " nop \n"
103 " nop \n"
104 " nop \n"
105 " nop \n"
106 " nop \n"
107 /* dots on: there's work to do, increment cntr */
108 " lui $26, 0xb980 \n"
109 " sb $0, 0x18($26) \n"
110 " lui $26, 0xb9c0 \n"
111 " lb $27, 0($26) \n"
112 " addiu $27, $27, 1 \n"
113 " sb $27, 0($26) \n"
114 " sync \n"
115 " .set pop \n"
116 : : "r" (db1200_wait));
117}
118
119static int __init db1200_arch_init(void)
120{
121 /* GPIO7 is low-level triggered CPLD cascade */
122 set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
123 bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
124
125 /* do not autoenable these: CPLD has broken edge int handling,
126 * and the CD handler setup requires manual enabling to work
127 * around that.
128 */
129 irq_to_desc(DB1200_SD0_INSERT_INT)->status |= IRQ_NOAUTOEN;
130 irq_to_desc(DB1200_SD0_EJECT_INT)->status |= IRQ_NOAUTOEN;
131
132 if (cpu_wait)
133 cpu_wait = db1200_wait;
134
135 return 0;
136}
137arch_initcall(db1200_arch_init);
diff --git a/arch/mips/alchemy/devboards/pb1200/board_setup.c b/arch/mips/alchemy/devboards/pb1200/board_setup.c
index 352acf68fc8d..2cf59e728247 100644
--- a/arch/mips/alchemy/devboards/pb1200/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1200/board_setup.c
@@ -58,16 +58,9 @@ void __init board_setup(void)
58{ 58{
59 char *argptr; 59 char *argptr;
60 60
61#ifdef CONFIG_MIPS_PB1200
62 printk(KERN_INFO "AMD Alchemy Pb1200 Board\n"); 61 printk(KERN_INFO "AMD Alchemy Pb1200 Board\n");
63 bcsr_init(PB1200_BCSR_PHYS_ADDR, 62 bcsr_init(PB1200_BCSR_PHYS_ADDR,
64 PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS); 63 PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS);
65#endif
66#ifdef CONFIG_MIPS_DB1200
67 printk(KERN_INFO "AMD Alchemy Db1200 Board\n");
68 bcsr_init(DB1200_BCSR_PHYS_ADDR,
69 DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
70#endif
71 64
72 argptr = prom_getcmdline(); 65 argptr = prom_getcmdline();
73#ifdef CONFIG_SERIAL_8250_CONSOLE 66#ifdef CONFIG_SERIAL_8250_CONSOLE
@@ -149,7 +142,6 @@ void __init board_setup(void)
149 142
150static int __init pb1200_init_irq(void) 143static int __init pb1200_init_irq(void)
151{ 144{
152#ifdef CONFIG_MIPS_PB1200
153 /* We have a problem with CPLD rev 3. */ 145 /* We have a problem with CPLD rev 3. */
154 if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) { 146 if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) {
155 printk(KERN_ERR "WARNING!!!\n"); 147 printk(KERN_ERR "WARNING!!!\n");
@@ -169,7 +161,6 @@ static int __init pb1200_init_irq(void)
169 printk(KERN_ERR "WARNING!!!\n"); 161 printk(KERN_ERR "WARNING!!!\n");
170 panic("Game over. Your score is 0."); 162 panic("Game over. Your score is 0.");
171 } 163 }
172#endif
173 164
174 set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW); 165 set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
175 bcsr_init_irq(PB1200_INT_BEGIN, PB1200_INT_END, AU1200_GPIO7_INT); 166 bcsr_init_irq(PB1200_INT_BEGIN, PB1200_INT_END, AU1200_GPIO7_INT);
diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c
index 736d647ebe0c..14e889fffcc5 100644
--- a/arch/mips/alchemy/devboards/pb1200/platform.c
+++ b/arch/mips/alchemy/devboards/pb1200/platform.c
@@ -68,7 +68,6 @@ static struct led_classdev pb1200mmc_led = {
68 .brightness_set = pb1200_mmcled_set, 68 .brightness_set = pb1200_mmcled_set,
69}; 69};
70 70
71#ifndef CONFIG_MIPS_DB1200
72static void pb1200mmc1_set_power(void *mmc_host, int state) 71static void pb1200mmc1_set_power(void *mmc_host, int state)
73{ 72{
74 if (state) 73 if (state)
@@ -88,7 +87,6 @@ static int pb1200mmc1_card_inserted(void *mmc_host)
88{ 87{
89 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0; 88 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;
90} 89}
91#endif
92 90
93const struct au1xmmc_platform_data au1xmmc_platdata[2] = { 91const struct au1xmmc_platform_data au1xmmc_platdata[2] = {
94 [0] = { 92 [0] = {
@@ -98,7 +96,6 @@ const struct au1xmmc_platform_data au1xmmc_platdata[2] = {
98 .cd_setup = NULL, /* use poll-timer in driver */ 96 .cd_setup = NULL, /* use poll-timer in driver */
99 .led = &pb1200mmc_led, 97 .led = &pb1200mmc_led,
100 }, 98 },
101#ifndef CONFIG_MIPS_DB1200
102 [1] = { 99 [1] = {
103 .set_power = pb1200mmc1_set_power, 100 .set_power = pb1200mmc1_set_power,
104 .card_inserted = pb1200mmc1_card_inserted, 101 .card_inserted = pb1200mmc1_card_inserted,
@@ -106,7 +103,6 @@ const struct au1xmmc_platform_data au1xmmc_platdata[2] = {
106 .cd_setup = NULL, /* use poll-timer in driver */ 103 .cd_setup = NULL, /* use poll-timer in driver */
107 .led = &pb1200mmc_led, 104 .led = &pb1200mmc_led,
108 }, 105 },
109#endif
110}; 106};
111 107
112static struct resource ide_resources[] = { 108static struct resource ide_resources[] = {
@@ -174,7 +170,6 @@ static int __init board_register_devices(void)
174{ 170{
175 int swapped; 171 int swapped;
176 172
177#ifdef CONFIG_MIPS_PB1200
178 db1x_register_pcmcia_socket(PCMCIA_ATTR_PSEUDO_PHYS, 173 db1x_register_pcmcia_socket(PCMCIA_ATTR_PSEUDO_PHYS,
179 PCMCIA_ATTR_PSEUDO_PHYS + 0x00040000 - 1, 174 PCMCIA_ATTR_PSEUDO_PHYS + 0x00040000 - 1,
180 PCMCIA_MEM_PSEUDO_PHYS, 175 PCMCIA_MEM_PSEUDO_PHYS,
@@ -198,38 +193,9 @@ static int __init board_register_devices(void)
198 /*PB1200_PC1_STSCHG_INT*/0, 193 /*PB1200_PC1_STSCHG_INT*/0,
199 PB1200_PC1_EJECT_INT, 194 PB1200_PC1_EJECT_INT,
200 1); 195 1);
201#else
202 db1x_register_pcmcia_socket(PCMCIA_ATTR_PSEUDO_PHYS,
203 PCMCIA_ATTR_PSEUDO_PHYS + 0x00040000 - 1,
204 PCMCIA_MEM_PSEUDO_PHYS,
205 PCMCIA_MEM_PSEUDO_PHYS + 0x00040000 - 1,
206 PCMCIA_IO_PSEUDO_PHYS,
207 PCMCIA_IO_PSEUDO_PHYS + 0x00001000 - 1,
208 DB1200_PC0_INT,
209 DB1200_PC0_INSERT_INT,
210 /*DB1200_PC0_STSCHG_INT*/0,
211 DB1200_PC0_EJECT_INT,
212 0);
213
214 db1x_register_pcmcia_socket(PCMCIA_ATTR_PSEUDO_PHYS + 0x00400000,
215 PCMCIA_ATTR_PSEUDO_PHYS + 0x00440000 - 1,
216 PCMCIA_MEM_PSEUDO_PHYS + 0x00400000,
217 PCMCIA_MEM_PSEUDO_PHYS + 0x00440000 - 1,
218 PCMCIA_IO_PSEUDO_PHYS + 0x00400000,
219 PCMCIA_IO_PSEUDO_PHYS + 0x00401000 - 1,
220 DB1200_PC1_INT,
221 DB1200_PC1_INSERT_INT,
222 /*DB1200_PC1_STSCHG_INT*/0,
223 DB1200_PC1_EJECT_INT,
224 1);
225#endif
226 196
227 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; 197 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
228#ifdef CONFIG_MIPS_PB1200
229 db1x_register_norflash(128 * 1024 * 1024, 2, swapped); 198 db1x_register_norflash(128 * 1024 * 1024, 2, swapped);
230#else
231 db1x_register_norflash(64 * 1024 * 1024, 2, swapped);
232#endif
233 199
234 return platform_add_devices(board_platform_devices, 200 return platform_add_devices(board_platform_devices,
235 ARRAY_SIZE(board_platform_devices)); 201 ARRAY_SIZE(board_platform_devices));
diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h
index 52b1d84a92c7..3404248f5094 100644
--- a/arch/mips/include/asm/mach-db1x00/db1200.h
+++ b/arch/mips/include/asm/mach-db1x00/db1200.h
@@ -28,24 +28,6 @@
28#include <asm/mach-au1x00/au1000.h> 28#include <asm/mach-au1x00/au1000.h>
29#include <asm/mach-au1x00/au1xxx_psc.h> 29#include <asm/mach-au1x00/au1xxx_psc.h>
30 30
31#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
32#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
33#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
34#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
35
36/*
37 * SPI and SMB are muxed on the DBAu1200 board.
38 * Refer to board documentation.
39 */
40#define SPI_PSC_BASE PSC0_BASE_ADDR
41#define SMBUS_PSC_BASE PSC0_BASE_ADDR
42/*
43 * AC'97 and I2S are muxed on the DBAu1200 board.
44 * Refer to board documentation.
45 */
46#define AC97_PSC_BASE PSC1_BASE_ADDR
47#define I2S_PSC_BASE PSC1_BASE_ADDR
48
49/* Bit positions for the different interrupt sources */ 31/* Bit positions for the different interrupt sources */
50#define BCSR_INT_IDE 0x0001 32#define BCSR_INT_IDE 0x0001
51#define BCSR_INT_ETH 0x0002 33#define BCSR_INT_ETH 0x0002
@@ -62,17 +44,15 @@
62#define BCSR_INT_SD0INSERT 0x1000 44#define BCSR_INT_SD0INSERT 0x1000
63#define BCSR_INT_SD0EJECT 0x2000 45#define BCSR_INT_SD0EJECT 0x2000
64 46
65#define SMC91C111_PHYS_ADDR 0x19000300
66#define SMC91C111_INT DB1200_ETH_INT
67
68#define IDE_PHYS_ADDR 0x18800000 47#define IDE_PHYS_ADDR 0x18800000
69#define IDE_REG_SHIFT 5 48#define IDE_REG_SHIFT 5
70#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
71#define IDE_INT DB1200_IDE_INT
72#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 49#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
73#define IDE_RQSIZE 128 50#define IDE_RQSIZE 128
74 51
75#define NAND_PHYS_ADDR 0x20000000 52#define DB1200_IDE_PHYS_ADDR IDE_PHYS_ADDR
53#define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
54#define DB1200_ETH_PHYS_ADDR 0x19000300
55#define DB1200_NAND_PHYS_ADDR 0x20000000
76 56
77/* 57/*
78 * External Interrupts for DBAu1200 as of 8/6/2004. 58 * External Interrupts for DBAu1200 as of 8/6/2004.
@@ -82,7 +62,7 @@
82 * Example: IDE bis pos is = 64 - 64 62 * Example: IDE bis pos is = 64 - 64
83 * ETH bit pos is = 65 - 64 63 * ETH bit pos is = 65 - 64
84 */ 64 */
85enum external_pb1200_ints { 65enum external_db1200_ints {
86 DB1200_INT_BEGIN = AU1000_MAX_INTR + 1, 66 DB1200_INT_BEGIN = AU1000_MAX_INTR + 1,
87 67
88 DB1200_IDE_INT = DB1200_INT_BEGIN, 68 DB1200_IDE_INT = DB1200_INT_BEGIN,
@@ -103,7 +83,4 @@ enum external_pb1200_ints {
103 DB1200_INT_END = DB1200_INT_BEGIN + 15, 83 DB1200_INT_END = DB1200_INT_BEGIN + 15,
104}; 84};
105 85
106/* NAND chip select */
107#define NAND_CS 1
108
109#endif /* __ASM_DB1200_H */ 86#endif /* __ASM_DB1200_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 00:18:02 -0500