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authorPaul Mundt <lethal@linux-sh.org>2011-01-12 00:47:21 -0500
committerPaul Mundt <lethal@linux-sh.org>2011-01-12 00:47:21 -0500
commit53582c4c508a95ece9f7c907edef9911c7eb79eb (patch)
treec099e9880f7bf7d60e87dfa6a19cb4e8780ec860 /arch
parent6ae1e19dbb43ff0d429a9f45087c513212686836 (diff)
parentda97da73d418533187a8390cf6541f48bed653e8 (diff)
Merge branch 'rmobile/sdio' into rmobile-latest
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-dove/common.c4
-rw-r--r--arch/arm/mach-shmobile/board-ap4evb.c3
-rw-r--r--arch/arm/mach-shmobile/board-g4evm.c15
-rw-r--r--arch/arm/mach-shmobile/board-mackerel.c6
-rw-r--r--arch/arm/mach-shmobile/intc-sh7367.c6
-rw-r--r--arch/arm/mach-shmobile/intc-sh7372.c4
-rw-r--r--arch/arm/mach-shmobile/intc-sh7377.c4
-rw-r--r--arch/arm/mach-tegra/include/mach/sdhci.h29
-rw-r--r--arch/blackfin/Makefile9
-rw-r--r--arch/blackfin/boot/Makefile2
-rw-r--r--arch/blackfin/configs/BF561-EZKIT-SMP_defconfig113
-rw-r--r--arch/blackfin/configs/DNP5370_defconfig121
-rw-r--r--arch/blackfin/include/asm/bfin_dma.h91
-rw-r--r--arch/blackfin/include/asm/bfin_serial.h275
-rw-r--r--arch/blackfin/include/asm/bitops.h2
-rw-r--r--arch/blackfin/include/asm/cache.h2
-rw-r--r--arch/blackfin/include/asm/cacheflush.h3
-rw-r--r--arch/blackfin/include/asm/dma.h37
-rw-r--r--arch/blackfin/include/asm/dpmc.h2
-rw-r--r--arch/blackfin/include/asm/io.h268
-rw-r--r--arch/blackfin/include/asm/irqflags.h3
-rw-r--r--arch/blackfin/include/asm/processor.h4
-rw-r--r--arch/blackfin/include/asm/spinlock.h28
-rw-r--r--arch/blackfin/include/mach-common/pll.h86
-rw-r--r--arch/blackfin/include/mach-common/ports-a.h25
-rw-r--r--arch/blackfin/include/mach-common/ports-b.h25
-rw-r--r--arch/blackfin/include/mach-common/ports-c.h25
-rw-r--r--arch/blackfin/include/mach-common/ports-d.h25
-rw-r--r--arch/blackfin/include/mach-common/ports-e.h25
-rw-r--r--arch/blackfin/include/mach-common/ports-f.h25
-rw-r--r--arch/blackfin/include/mach-common/ports-g.h25
-rw-r--r--arch/blackfin/include/mach-common/ports-h.h25
-rw-r--r--arch/blackfin/include/mach-common/ports-i.h25
-rw-r--r--arch/blackfin/include/mach-common/ports-j.h25
-rw-r--r--arch/blackfin/kernel/cplb-nompu/cplbinit.c2
-rw-r--r--arch/blackfin/kernel/kgdb.c26
-rw-r--r--arch/blackfin/kernel/kgdb_test.c4
-rw-r--r--arch/blackfin/mach-bf518/boards/ezbrd.c29
-rw-r--r--arch/blackfin/mach-bf518/boards/tcm-bf518.c12
-rw-r--r--arch/blackfin/mach-bf518/dma.c2
-rw-r--r--arch/blackfin/mach-bf518/include/mach/bfin_serial.h14
-rw-r--r--arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h73
-rw-r--r--arch/blackfin/mach-bf518/include/mach/blackfin.h68
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF512.h1038
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF514.h5
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF516.h5
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF518.h5
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h1061
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF512.h1388
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF51x_base.h1495
-rw-r--r--arch/blackfin/mach-bf518/include/mach/gpio.h4
-rw-r--r--arch/blackfin/mach-bf518/include/mach/pll.h64
-rw-r--r--arch/blackfin/mach-bf527/boards/ad7160eval.c13
-rw-r--r--arch/blackfin/mach-bf527/boards/cm_bf527.c13
-rw-r--r--arch/blackfin/mach-bf527/boards/ezbrd.c13
-rw-r--r--arch/blackfin/mach-bf527/boards/ezkit.c18
-rw-r--r--arch/blackfin/mach-bf527/boards/tll6527m.c14
-rw-r--r--arch/blackfin/mach-bf527/dma.c2
-rw-r--r--arch/blackfin/mach-bf527/include/mach/bfin_serial.h14
-rw-r--r--arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h73
-rw-r--r--arch/blackfin/mach-bf527/include/mach/blackfin.h48
-rw-r--r--arch/blackfin/mach-bf527/include/mach/cdefBF522.h1092
-rw-r--r--arch/blackfin/mach-bf527/include/mach/cdefBF525.h7
-rw-r--r--arch/blackfin/mach-bf527/include/mach/cdefBF527.h7
-rw-r--r--arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h1113
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF522.h1393
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF525.h2
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF527.h2
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF52x_base.h1506
-rw-r--r--arch/blackfin/mach-bf527/include/mach/gpio.h4
-rw-r--r--arch/blackfin/mach-bf527/include/mach/pll.h64
-rw-r--r--arch/blackfin/mach-bf533/boards/H8606.c2
-rw-r--r--arch/blackfin/mach-bf533/boards/blackstamp.c25
-rw-r--r--arch/blackfin/mach-bf533/boards/cm_bf533.c10
-rw-r--r--arch/blackfin/mach-bf533/boards/ezkit.c2
-rw-r--r--arch/blackfin/mach-bf533/boards/ip0x.c11
-rw-r--r--arch/blackfin/mach-bf533/boards/stamp.c30
-rw-r--r--arch/blackfin/mach-bf533/dma.c2
-rw-r--r--arch/blackfin/mach-bf533/include/mach/bfin_serial.h14
-rw-r--r--arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h74
-rw-r--r--arch/blackfin/mach-bf533/include/mach/blackfin.h30
-rw-r--r--arch/blackfin/mach-bf533/include/mach/cdefBF532.h63
-rw-r--r--arch/blackfin/mach-bf533/include/mach/defBF532.h128
-rw-r--r--arch/blackfin/mach-bf533/include/mach/fio_flag.h55
-rw-r--r--arch/blackfin/mach-bf533/include/mach/gpio.h2
-rw-r--r--arch/blackfin/mach-bf533/include/mach/pll.h58
-rw-r--r--arch/blackfin/mach-bf537/boards/Kconfig6
-rw-r--r--arch/blackfin/mach-bf537/boards/Makefile1
-rw-r--r--arch/blackfin/mach-bf537/boards/cm_bf537e.c12
-rw-r--r--arch/blackfin/mach-bf537/boards/cm_bf537u.c12
-rw-r--r--arch/blackfin/mach-bf537/boards/dnp5370.c418
-rw-r--r--arch/blackfin/mach-bf537/boards/minotaur.c12
-rw-r--r--arch/blackfin/mach-bf537/boards/pnav10.c4
-rw-r--r--arch/blackfin/mach-bf537/boards/stamp.c18
-rw-r--r--arch/blackfin/mach-bf537/boards/tcm_bf537.c12
-rw-r--r--arch/blackfin/mach-bf537/dma.c2
-rw-r--r--arch/blackfin/mach-bf537/include/mach/bfin_serial.h14
-rw-r--r--arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h72
-rw-r--r--arch/blackfin/mach-bf537/include/mach/blackfin.h38
-rw-r--r--arch/blackfin/mach-bf537/include/mach/cdefBF534.h27
-rw-r--r--arch/blackfin/mach-bf537/include/mach/cdefBF537.h5
-rw-r--r--arch/blackfin/mach-bf537/include/mach/defBF534.h111
-rw-r--r--arch/blackfin/mach-bf537/include/mach/defBF537.h5
-rw-r--r--arch/blackfin/mach-bf537/include/mach/gpio.h4
-rw-r--r--arch/blackfin/mach-bf537/include/mach/pll.h58
-rw-r--r--arch/blackfin/mach-bf538/boards/ezkit.c20
-rw-r--r--arch/blackfin/mach-bf538/dma.c18
-rw-r--r--arch/blackfin/mach-bf538/include/mach/bfin_serial.h14
-rw-r--r--arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h73
-rw-r--r--arch/blackfin/mach-bf538/include/mach/blackfin.h37
-rw-r--r--arch/blackfin/mach-bf538/include/mach/cdefBF538.h504
-rw-r--r--arch/blackfin/mach-bf538/include/mach/cdefBF539.h8
-rw-r--r--arch/blackfin/mach-bf538/include/mach/defBF538.h1825
-rw-r--r--arch/blackfin/mach-bf538/include/mach/defBF539.h2095
-rw-r--r--arch/blackfin/mach-bf538/include/mach/gpio.h5
-rw-r--r--arch/blackfin/mach-bf538/include/mach/pll.h64
-rw-r--r--arch/blackfin/mach-bf548/boards/cm_bf548.c23
-rw-r--r--arch/blackfin/mach-bf548/boards/ezkit.c23
-rw-r--r--arch/blackfin/mach-bf548/dma.c2
-rw-r--r--arch/blackfin/mach-bf548/include/mach/bfin_serial.h16
-rw-r--r--arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h60
-rw-r--r--arch/blackfin/mach-bf548/include/mach/blackfin.h70
-rw-r--r--arch/blackfin/mach-bf548/include/mach/cdefBF542.h10
-rw-r--r--arch/blackfin/mach-bf548/include/mach/cdefBF544.h10
-rw-r--r--arch/blackfin/mach-bf548/include/mach/cdefBF547.h10
-rw-r--r--arch/blackfin/mach-bf548/include/mach/cdefBF548.h10
-rw-r--r--arch/blackfin/mach-bf548/include/mach/cdefBF549.h10
-rw-r--r--arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h23
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF542.h7
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF544.h7
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF547.h7
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF548.h7
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF549.h7
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF54x_base.h321
-rw-r--r--arch/blackfin/mach-bf548/include/mach/gpio.h11
-rw-r--r--arch/blackfin/mach-bf548/include/mach/irq.h22
-rw-r--r--arch/blackfin/mach-bf548/include/mach/pll.h70
-rw-r--r--arch/blackfin/mach-bf561/atomic.S5
-rw-r--r--arch/blackfin/mach-bf561/boards/acvilon.c2
-rw-r--r--arch/blackfin/mach-bf561/boards/cm_bf561.c2
-rw-r--r--arch/blackfin/mach-bf561/boards/ezkit.c2
-rw-r--r--arch/blackfin/mach-bf561/boards/tepla.c2
-rw-r--r--arch/blackfin/mach-bf561/dma.c18
-rw-r--r--arch/blackfin/mach-bf561/hotplug.c2
-rw-r--r--arch/blackfin/mach-bf561/include/mach/anomaly.h6
-rw-r--r--arch/blackfin/mach-bf561/include/mach/bfin_serial.h14
-rw-r--r--arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h74
-rw-r--r--arch/blackfin/mach-bf561/include/mach/blackfin.h26
-rw-r--r--arch/blackfin/mach-bf561/include/mach/cdefBF561.h503
-rw-r--r--arch/blackfin/mach-bf561/include/mach/defBF561.h408
-rw-r--r--arch/blackfin/mach-bf561/include/mach/gpio.h2
-rw-r--r--arch/blackfin/mach-bf561/include/mach/mem_map.h16
-rw-r--r--arch/blackfin/mach-bf561/include/mach/pll.h83
-rw-r--r--arch/blackfin/mach-bf561/include/mach/smp.h10
-rw-r--r--arch/blackfin/mach-bf561/smp.c29
-rw-r--r--arch/blackfin/mach-common/entry.S4
-rw-r--r--arch/blackfin/mach-common/ints-priority.c1
-rw-r--r--arch/blackfin/mach-common/pm.c10
-rw-r--r--arch/blackfin/mach-common/smp.c204
-rw-r--r--arch/blackfin/mm/sram-alloc.c18
-rw-r--r--arch/microblaze/Kconfig.debug4
-rw-r--r--arch/microblaze/Makefile2
-rw-r--r--arch/microblaze/configs/mmu_defconfig1
-rw-r--r--arch/microblaze/include/asm/pvr.h185
-rw-r--r--arch/microblaze/kernel/cpu/cpuinfo.c1
-rw-r--r--arch/microblaze/kernel/entry.S46
-rw-r--r--arch/microblaze/kernel/exceptions.c3
-rw-r--r--arch/microblaze/kernel/hw_exception_handler.S9
-rw-r--r--arch/microblaze/kernel/prom.c4
-rw-r--r--arch/microblaze/kernel/vmlinux.lds.S16
-rw-r--r--arch/microblaze/lib/memmove.c2
-rw-r--r--arch/microblaze/lib/muldi3.S121
-rw-r--r--arch/microblaze/lib/muldi3.c60
-rw-r--r--arch/powerpc/Kconfig16
-rw-r--r--arch/powerpc/boot/dts/canyonlands.dts31
-rw-r--r--arch/powerpc/boot/dts/kilauea.dts9
-rw-r--r--arch/powerpc/boot/dts/mpc8308_p1m.dts8
-rw-r--r--arch/powerpc/boot/dts/mpc8308rdb.dts8
-rw-r--r--arch/powerpc/configs/40x/kilauea_defconfig5
-rw-r--r--arch/powerpc/configs/44x/canyonlands_defconfig3
-rw-r--r--arch/powerpc/include/asm/bitops.h9
-rw-r--r--arch/powerpc/include/asm/cputable.h9
-rw-r--r--arch/powerpc/include/asm/cputhreads.h15
-rw-r--r--arch/powerpc/include/asm/device.h6
-rw-r--r--arch/powerpc/include/asm/firmware.h3
-rw-r--r--arch/powerpc/include/asm/hvcall.h4
-rw-r--r--arch/powerpc/include/asm/lppaca.h5
-rw-r--r--arch/powerpc/include/asm/machdep.h6
-rw-r--r--arch/powerpc/include/asm/mmzone.h5
-rw-r--r--arch/powerpc/include/asm/nvram.h52
-rw-r--r--arch/powerpc/include/asm/ppc-opcode.h8
-rw-r--r--arch/powerpc/include/asm/processor.h2
-rw-r--r--arch/powerpc/include/asm/topology.h15
-rw-r--r--arch/powerpc/include/asm/vdso_datapage.h2
-rw-r--r--arch/powerpc/kernel/Makefile9
-rw-r--r--arch/powerpc/kernel/asm-offsets.c1
-rw-r--r--arch/powerpc/kernel/cputable.c22
-rw-r--r--arch/powerpc/kernel/crash_dump.c33
-rw-r--r--arch/powerpc/kernel/dma-iommu.c2
-rw-r--r--arch/powerpc/kernel/entry_32.S1
-rw-r--r--arch/powerpc/kernel/exceptions-64s.S1
-rw-r--r--arch/powerpc/kernel/fpu.S1
-rw-r--r--arch/powerpc/kernel/head_40x.S1
-rw-r--r--arch/powerpc/kernel/head_44x.S1
-rw-r--r--arch/powerpc/kernel/head_64.S7
-rw-r--r--arch/powerpc/kernel/head_8xx.S1
-rw-r--r--arch/powerpc/kernel/head_fsl_booke.S1
-rw-r--r--arch/powerpc/kernel/iommu.c14
-rw-r--r--arch/powerpc/kernel/misc.S5
-rw-r--r--arch/powerpc/kernel/misc_32.S1
-rw-r--r--arch/powerpc/kernel/misc_64.S1
-rw-r--r--arch/powerpc/kernel/nvram_64.c481
-rw-r--r--arch/powerpc/kernel/pci_64.c3
-rw-r--r--arch/powerpc/kernel/ppc_ksyms.c7
-rw-r--r--arch/powerpc/kernel/ppc_save_regs.S1
-rw-r--r--arch/powerpc/kernel/ptrace.c22
-rw-r--r--arch/powerpc/kernel/ptrace32.c7
-rw-r--r--arch/powerpc/kernel/rtas.c3
-rw-r--r--arch/powerpc/kernel/setup_64.c4
-rw-r--r--arch/powerpc/kernel/smp.c19
-rw-r--r--arch/powerpc/kernel/time.c2
-rw-r--r--arch/powerpc/kernel/vector.S1
-rw-r--r--arch/powerpc/kernel/vio.c15
-rw-r--r--arch/powerpc/lib/Makefile2
-rw-r--r--arch/powerpc/lib/hweight_64.S110
-rw-r--r--arch/powerpc/mm/hash_utils_64.c2
-rw-r--r--arch/powerpc/mm/mmu_context_nohash.c12
-rw-r--r--arch/powerpc/mm/numa.c311
-rw-r--r--arch/powerpc/mm/pgtable_32.c3
-rw-r--r--arch/powerpc/mm/pgtable_64.c2
-rw-r--r--arch/powerpc/platforms/44x/Makefile5
-rw-r--r--arch/powerpc/platforms/Kconfig7
-rw-r--r--arch/powerpc/platforms/cell/beat_iommu.c3
-rw-r--r--arch/powerpc/platforms/cell/spufs/lscsa_alloc.c3
-rw-r--r--arch/powerpc/platforms/chrp/time.c4
-rw-r--r--arch/powerpc/platforms/iseries/mf.c62
-rw-r--r--arch/powerpc/platforms/pasemi/iommu.c19
-rw-r--r--arch/powerpc/platforms/powermac/setup.c9
-rw-r--r--arch/powerpc/platforms/pseries/Kconfig10
-rw-r--r--arch/powerpc/platforms/pseries/Makefile1
-rw-r--r--arch/powerpc/platforms/pseries/firmware.c1
-rw-r--r--arch/powerpc/platforms/pseries/hvCall.S1
-rw-r--r--arch/powerpc/platforms/pseries/iommu.c49
-rw-r--r--arch/powerpc/platforms/pseries/lpar.c12
-rw-r--r--arch/powerpc/platforms/pseries/nvram.c205
-rw-r--r--arch/powerpc/platforms/pseries/pseries_energy.c326
-rw-r--r--arch/powerpc/sysdev/Makefile1
-rw-r--r--arch/powerpc/sysdev/dart_iommu.c9
-rw-r--r--arch/powerpc/sysdev/mpc8xxx_gpio.c75
-rw-r--r--arch/powerpc/sysdev/ppc4xx_cpm.c346
-rw-r--r--arch/powerpc/sysdev/tsi108_dev.c8
-rw-r--r--arch/sparc/kernel/cpu.c2
-rw-r--r--arch/sparc/kernel/pcr.c2
-rw-r--r--arch/x86/include/asm/acpi.h11
-rw-r--r--arch/x86/include/asm/amd_nb.h13
-rw-r--r--arch/x86/include/asm/fixmap.h4
-rw-r--r--arch/x86/include/asm/gpio.h5
-rw-r--r--arch/x86/include/asm/kdebug.h1
-rw-r--r--arch/x86/include/asm/mach_traps.h12
-rw-r--r--arch/x86/include/asm/nmi.h20
-rw-r--r--arch/x86/include/asm/numa_64.h2
-rw-r--r--arch/x86/include/asm/perf_event_p4.h3
-rw-r--r--arch/x86/kernel/amd_nb.c7
-rw-r--r--arch/x86/kernel/aperture_64.c44
-rw-r--r--arch/x86/kernel/apic/apic.c2
-rw-r--r--arch/x86/kernel/apic/hw_nmi.c3
-rw-r--r--arch/x86/kernel/apic/x2apic_uv_x.c4
-rw-r--r--arch/x86/kernel/cpu/mcheck/mce-inject.c5
-rw-r--r--arch/x86/kernel/cpu/perf_event.c3
-rw-r--r--arch/x86/kernel/cpu/perf_event_p4.c28
-rw-r--r--arch/x86/kernel/dumpstack.c6
-rw-r--r--arch/x86/kernel/entry_64.S36
-rw-r--r--arch/x86/kernel/kgdb.c7
-rw-r--r--arch/x86/kernel/reboot.c5
-rw-r--r--arch/x86/kernel/smpboot.c4
-rw-r--r--arch/x86/kernel/traps.c102
-rw-r--r--arch/x86/kernel/tsc.c2
-rw-r--r--arch/x86/mm/amdtopology_64.c86
-rw-r--r--arch/x86/mm/numa_64.c157
-rw-r--r--arch/x86/mm/srat_64.c26
-rw-r--r--arch/x86/oprofile/nmi_int.c3
-rw-r--r--arch/x86/oprofile/nmi_timer_int.c2
-rw-r--r--arch/x86/pci/amd_bus.c33
283 files changed, 12046 insertions, 11761 deletions
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index f7a12586a1f5..fe627aba6da7 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -770,7 +770,7 @@ static struct resource dove_sdio0_resources[] = {
770}; 770};
771 771
772static struct platform_device dove_sdio0 = { 772static struct platform_device dove_sdio0 = {
773 .name = "sdhci-mv", 773 .name = "sdhci-dove",
774 .id = 0, 774 .id = 0,
775 .dev = { 775 .dev = {
776 .dma_mask = &sdio_dmamask, 776 .dma_mask = &sdio_dmamask,
@@ -798,7 +798,7 @@ static struct resource dove_sdio1_resources[] = {
798}; 798};
799 799
800static struct platform_device dove_sdio1 = { 800static struct platform_device dove_sdio1 = {
801 .name = "sdhci-mv", 801 .name = "sdhci-dove",
802 .id = 1, 802 .id = 1,
803 .dev = { 803 .dev = {
804 .dma_mask = &sdio_dmamask, 804 .dma_mask = &sdio_dmamask,
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index cd79d7c1ba0d..f888d9d1d010 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -308,6 +308,7 @@ static struct platform_device sh_mmcif_device = {
308static struct sh_mobile_sdhi_info sdhi0_info = { 308static struct sh_mobile_sdhi_info sdhi0_info = {
309 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, 309 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
310 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, 310 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
311 .tmio_caps = MMC_CAP_SDIO_IRQ,
311}; 312};
312 313
313static struct resource sdhi0_resources[] = { 314static struct resource sdhi0_resources[] = {
@@ -339,7 +340,7 @@ static struct sh_mobile_sdhi_info sdhi1_info = {
339 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX, 340 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
340 .tmio_ocr_mask = MMC_VDD_165_195, 341 .tmio_ocr_mask = MMC_VDD_165_195,
341 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE, 342 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE,
342 .tmio_caps = MMC_CAP_NEEDS_POLL, 343 .tmio_caps = MMC_CAP_NEEDS_POLL | MMC_CAP_SDIO_IRQ,
343 .get_cd = slot_cn7_get_cd, 344 .get_cd = slot_cn7_get_cd,
344}; 345};
345 346
diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c
index c13f01280b7e..dee3e9231fb9 100644
--- a/arch/arm/mach-shmobile/board-g4evm.c
+++ b/arch/arm/mach-shmobile/board-g4evm.c
@@ -30,6 +30,7 @@
30#include <linux/io.h> 30#include <linux/io.h>
31#include <linux/input.h> 31#include <linux/input.h>
32#include <linux/input/sh_keysc.h> 32#include <linux/input/sh_keysc.h>
33#include <linux/mmc/host.h>
33#include <linux/mfd/sh_mobile_sdhi.h> 34#include <linux/mfd/sh_mobile_sdhi.h>
34#include <linux/gpio.h> 35#include <linux/gpio.h>
35#include <mach/sh7377.h> 36#include <mach/sh7377.h>
@@ -196,6 +197,10 @@ static struct platform_device keysc_device = {
196}; 197};
197 198
198/* SDHI */ 199/* SDHI */
200static struct sh_mobile_sdhi_info sdhi0_info = {
201 .tmio_caps = MMC_CAP_SDIO_IRQ,
202};
203
199static struct resource sdhi0_resources[] = { 204static struct resource sdhi0_resources[] = {
200 [0] = { 205 [0] = {
201 .name = "SDHI0", 206 .name = "SDHI0",
@@ -214,6 +219,13 @@ static struct platform_device sdhi0_device = {
214 .num_resources = ARRAY_SIZE(sdhi0_resources), 219 .num_resources = ARRAY_SIZE(sdhi0_resources),
215 .resource = sdhi0_resources, 220 .resource = sdhi0_resources,
216 .id = 0, 221 .id = 0,
222 .dev = {
223 .platform_data = &sdhi0_info,
224 },
225};
226
227static struct sh_mobile_sdhi_info sdhi1_info = {
228 .tmio_caps = MMC_CAP_NONREMOVABLE | MMC_CAP_SDIO_IRQ,
217}; 229};
218 230
219static struct resource sdhi1_resources[] = { 231static struct resource sdhi1_resources[] = {
@@ -234,6 +246,9 @@ static struct platform_device sdhi1_device = {
234 .num_resources = ARRAY_SIZE(sdhi1_resources), 246 .num_resources = ARRAY_SIZE(sdhi1_resources),
235 .resource = sdhi1_resources, 247 .resource = sdhi1_resources,
236 .id = 1, 248 .id = 1,
249 .dev = {
250 .platform_data = &sdhi1_info,
251 },
237}; 252};
238 253
239static struct platform_device *g4evm_devices[] __initdata = { 254static struct platform_device *g4evm_devices[] __initdata = {
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 6601c595b1e0..ad7e14aba164 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -667,7 +667,7 @@ static int slot_cn7_get_cd(struct platform_device *pdev)
667static struct sh_mobile_sdhi_info sdhi0_info = { 667static struct sh_mobile_sdhi_info sdhi0_info = {
668 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, 668 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
669 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, 669 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
670 .tmio_caps = MMC_CAP_SD_HIGHSPEED, 670 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
671}; 671};
672 672
673static struct resource sdhi0_resources[] = { 673static struct resource sdhi0_resources[] = {
@@ -700,7 +700,7 @@ static struct sh_mobile_sdhi_info sdhi1_info = {
700 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX, 700 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
701 .tmio_ocr_mask = MMC_VDD_165_195, 701 .tmio_ocr_mask = MMC_VDD_165_195,
702 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE, 702 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE,
703 .tmio_caps = MMC_CAP_SD_HIGHSPEED | 703 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
704 MMC_CAP_NEEDS_POLL, 704 MMC_CAP_NEEDS_POLL,
705 .get_cd = slot_cn7_get_cd, 705 .get_cd = slot_cn7_get_cd,
706}; 706};
@@ -743,7 +743,7 @@ static struct sh_mobile_sdhi_info sdhi2_info = {
743 .dma_slave_tx = SHDMA_SLAVE_SDHI2_TX, 743 .dma_slave_tx = SHDMA_SLAVE_SDHI2_TX,
744 .dma_slave_rx = SHDMA_SLAVE_SDHI2_RX, 744 .dma_slave_rx = SHDMA_SLAVE_SDHI2_RX,
745 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE, 745 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE,
746 .tmio_caps = MMC_CAP_SD_HIGHSPEED | 746 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
747 MMC_CAP_NEEDS_POLL, 747 MMC_CAP_NEEDS_POLL,
748 .get_cd = slot_cn23_get_cd, 748 .get_cd = slot_cn23_get_cd,
749}; 749};
diff --git a/arch/arm/mach-shmobile/intc-sh7367.c b/arch/arm/mach-shmobile/intc-sh7367.c
index 1a20c489b20d..2fe9704d5ea1 100644
--- a/arch/arm/mach-shmobile/intc-sh7367.c
+++ b/arch/arm/mach-shmobile/intc-sh7367.c
@@ -189,10 +189,10 @@ static struct intc_mask_reg intca_mask_registers[] __initdata = {
189 { SCIFB, SCIFA5, SCIFA4, MSIOF1, 189 { SCIFB, SCIFA5, SCIFA4, MSIOF1,
190 0, 0, MSIOF2, 0 } }, 190 0, 0, MSIOF2, 0 } },
191 { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */ 191 { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
192 { DISABLED, DISABLED, ENABLED, ENABLED, 192 { DISABLED, ENABLED, ENABLED, ENABLED,
193 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, 193 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
194 { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */ 194 { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
195 { DISABLED, DISABLED, ENABLED, ENABLED, 195 { DISABLED, ENABLED, ENABLED, ENABLED,
196 TTI20, USBDMAC_USHDMI, SPU, SIU } }, 196 TTI20, USBDMAC_USHDMI, SPU, SIU } },
197 { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ 197 { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
198 { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10, 198 { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
@@ -207,7 +207,7 @@ static struct intc_mask_reg intca_mask_registers[] __initdata = {
207 { 0, 0, TPU0, TPU1, 207 { 0, 0, TPU0, TPU1,
208 TPU2, TPU3, TPU4, 0 } }, 208 TPU2, TPU3, TPU4, 0 } },
209 { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */ 209 { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
210 { DISABLED, DISABLED, ENABLED, ENABLED, 210 { DISABLED, ENABLED, ENABLED, ENABLED,
211 MISTY, CMT3, RWDT1, RWDT0 } }, 211 MISTY, CMT3, RWDT1, RWDT0 } },
212}; 212};
213 213
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
index 30b2f400666a..f78a1ead71a5 100644
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -230,10 +230,10 @@ static struct intc_mask_reg intca_mask_registers[] __initdata = {
230 { SCIFB, SCIFA5, SCIFA4, MSIOF1, 230 { SCIFB, SCIFA5, SCIFA4, MSIOF1,
231 0, 0, MSIOF2, 0 } }, 231 0, 0, MSIOF2, 0 } },
232 { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */ 232 { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
233 { DISABLED, DISABLED, ENABLED, ENABLED, 233 { DISABLED, ENABLED, ENABLED, ENABLED,
234 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, 234 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
235 { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */ 235 { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
236 { 0, DISABLED, ENABLED, ENABLED, 236 { 0, ENABLED, ENABLED, ENABLED,
237 TTI20, USBHSDMAC0_USHDMI, 0, 0 } }, 237 TTI20, USBHSDMAC0_USHDMI, 0, 0 } },
238 { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ 238 { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
239 { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10, 239 { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
diff --git a/arch/arm/mach-shmobile/intc-sh7377.c b/arch/arm/mach-shmobile/intc-sh7377.c
index 2cdeb8ccd821..dd568382cc9f 100644
--- a/arch/arm/mach-shmobile/intc-sh7377.c
+++ b/arch/arm/mach-shmobile/intc-sh7377.c
@@ -234,10 +234,10 @@ static struct intc_mask_reg intca_mask_registers[] __initdata = {
234 { SCIFB, SCIFA5, SCIFA4, MSIOF1, 234 { SCIFB, SCIFA5, SCIFA4, MSIOF1,
235 0, 0, MSIOF2, 0 } }, 235 0, 0, MSIOF2, 0 } },
236 { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */ 236 { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
237 { DISABLED, DISABLED, ENABLED, ENABLED, 237 { DISABLED, ENABLED, ENABLED, ENABLED,
238 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, 238 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
239 { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */ 239 { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
240 { DISABLED, DISABLED, ENABLED, ENABLED, 240 { DISABLED, ENABLED, ENABLED, ENABLED,
241 TTI20, USBDMAC_USHDMI, 0, MSUG } }, 241 TTI20, USBDMAC_USHDMI, 0, MSUG } },
242 { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ 242 { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
243 { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10, 243 { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
diff --git a/arch/arm/mach-tegra/include/mach/sdhci.h b/arch/arm/mach-tegra/include/mach/sdhci.h
new file mode 100644
index 000000000000..3ad086e859c3
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/sdhci.h
@@ -0,0 +1,29 @@
1/*
2 * include/asm-arm/arch-tegra/include/mach/sdhci.h
3 *
4 * Copyright (C) 2009 Palm, Inc.
5 * Author: Yvonne Yip <y@palm.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17#ifndef __ASM_ARM_ARCH_TEGRA_SDHCI_H
18#define __ASM_ARM_ARCH_TEGRA_SDHCI_H
19
20#include <linux/mmc/host.h>
21
22struct tegra_sdhci_platform_data {
23 int cd_gpio;
24 int wp_gpio;
25 int power_gpio;
26 int is_8bit;
27};
28
29#endif
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile
index 46738d49b7c8..46f42b2066e5 100644
--- a/arch/blackfin/Makefile
+++ b/arch/blackfin/Makefile
@@ -19,7 +19,7 @@ KBUILD_CFLAGS += -mlong-calls
19endif 19endif
20KBUILD_AFLAGS += $(call cc-option,-mno-fdpic) 20KBUILD_AFLAGS += $(call cc-option,-mno-fdpic)
21KBUILD_CFLAGS_MODULE += -mlong-calls 21KBUILD_CFLAGS_MODULE += -mlong-calls
22KBUILD_LDFLAGS_MODULE += -m elf32bfin 22LDFLAGS += -m elf32bfin
23KALLSYMS += --symbol-prefix=_ 23KALLSYMS += --symbol-prefix=_
24 24
25KBUILD_DEFCONFIG := BF537-STAMP_defconfig 25KBUILD_DEFCONFIG := BF537-STAMP_defconfig
@@ -97,8 +97,11 @@ rev-$(CONFIG_BF_REV_0_6) := 0.6
97rev-$(CONFIG_BF_REV_NONE) := none 97rev-$(CONFIG_BF_REV_NONE) := none
98rev-$(CONFIG_BF_REV_ANY) := any 98rev-$(CONFIG_BF_REV_ANY) := any
99 99
100KBUILD_CFLAGS += -mcpu=$(cpu-y)-$(rev-y) 100CPU_REV := $(cpu-y)-$(rev-y)
101KBUILD_AFLAGS += -mcpu=$(cpu-y)-$(rev-y) 101export CPU_REV
102
103KBUILD_CFLAGS += -mcpu=$(CPU_REV)
104KBUILD_AFLAGS += -mcpu=$(CPU_REV)
102 105
103# - we utilize the silicon rev from the toolchain, so move it over to the checkflags 106# - we utilize the silicon rev from the toolchain, so move it over to the checkflags
104CHECKFLAGS_SILICON = $(shell echo "" | $(CPP) $(KBUILD_CFLAGS) -dD - 2>/dev/null | awk '$$2 == "__SILICON_REVISION__" { print $$3 }') 107CHECKFLAGS_SILICON = $(shell echo "" | $(CPP) $(KBUILD_CFLAGS) -dD - 2>/dev/null | awk '$$2 == "__SILICON_REVISION__" { print $$3 }')
diff --git a/arch/blackfin/boot/Makefile b/arch/blackfin/boot/Makefile
index 13d2dbd658e3..0a49279e3428 100644
--- a/arch/blackfin/boot/Makefile
+++ b/arch/blackfin/boot/Makefile
@@ -17,7 +17,7 @@ UIMAGE_OPTS-$(CONFIG_ROMKERNEL) += -a $(CONFIG_ROM_BASE) -x
17 17
18quiet_cmd_uimage = UIMAGE $@ 18quiet_cmd_uimage = UIMAGE $@
19 cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(ARCH) -O linux -T kernel \ 19 cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(ARCH) -O linux -T kernel \
20 -C $(2) -n '$(MACHINE)-$(KERNELRELEASE)' \ 20 -C $(2) -n '$(CPU_REV)-$(KERNELRELEASE)' \
21 -e $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}') \ 21 -e $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}') \
22 $(UIMAGE_OPTS-y) -d $< $@ 22 $(UIMAGE_OPTS-y) -d $< $@
23 23
diff --git a/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig b/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig
new file mode 100644
index 000000000000..4cf451024fd8
--- /dev/null
+++ b/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig
@@ -0,0 +1,113 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y
3CONFIG_IKCONFIG=y
4CONFIG_IKCONFIG_PROC=y
5CONFIG_LOG_BUF_SHIFT=14
6CONFIG_BLK_DEV_INITRD=y
7# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
8CONFIG_EMBEDDED=y
9# CONFIG_SYSCTL_SYSCALL is not set
10# CONFIG_ELF_CORE is not set
11# CONFIG_FUTEX is not set
12# CONFIG_SIGNALFD is not set
13# CONFIG_TIMERFD is not set
14# CONFIG_EVENTFD is not set
15# CONFIG_AIO is not set
16CONFIG_SLAB=y
17CONFIG_MMAP_ALLOW_UNINITIALIZED=y
18CONFIG_MODULES=y
19CONFIG_MODULE_UNLOAD=y
20# CONFIG_LBDAF is not set
21# CONFIG_BLK_DEV_BSG is not set
22# CONFIG_IOSCHED_DEADLINE is not set
23# CONFIG_IOSCHED_CFQ is not set
24CONFIG_PREEMPT_VOLUNTARY=y
25CONFIG_BF561=y
26CONFIG_SMP=y
27CONFIG_IRQ_TIMER0=10
28CONFIG_CLKIN_HZ=30000000
29CONFIG_HIGH_RES_TIMERS=y
30CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
31CONFIG_BFIN_GPTIMERS=m
32CONFIG_C_CDPRIO=y
33CONFIG_BANK_3=0xAAC2
34CONFIG_BINFMT_FLAT=y
35CONFIG_BINFMT_ZFLAT=y
36CONFIG_PM=y
37CONFIG_NET=y
38CONFIG_PACKET=y
39CONFIG_UNIX=y
40CONFIG_INET=y
41CONFIG_IP_PNP=y
42# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
43# CONFIG_INET_XFRM_MODE_TUNNEL is not set
44# CONFIG_INET_XFRM_MODE_BEET is not set
45# CONFIG_INET_LRO is not set
46# CONFIG_INET_DIAG is not set
47# CONFIG_IPV6 is not set
48CONFIG_IRDA=m
49CONFIG_IRLAN=m
50CONFIG_IRCOMM=m
51CONFIG_IRDA_CACHE_LAST_LSAP=y
52CONFIG_IRTTY_SIR=m
53# CONFIG_WIRELESS is not set
54CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
55# CONFIG_FW_LOADER is not set
56CONFIG_MTD=y
57CONFIG_MTD_PARTITIONS=y
58CONFIG_MTD_CMDLINE_PARTS=y
59CONFIG_MTD_CHAR=m
60CONFIG_MTD_BLOCK=y
61CONFIG_MTD_CFI=m
62CONFIG_MTD_CFI_AMDSTD=m
63CONFIG_MTD_RAM=y
64CONFIG_MTD_ROM=m
65CONFIG_MTD_PHYSMAP=m
66CONFIG_BLK_DEV_RAM=y
67CONFIG_NETDEVICES=y
68CONFIG_NET_ETHERNET=y
69CONFIG_SMC91X=y
70# CONFIG_NETDEV_1000 is not set
71# CONFIG_NETDEV_10000 is not set
72# CONFIG_WLAN is not set
73CONFIG_INPUT=m
74# CONFIG_INPUT_MOUSEDEV is not set
75CONFIG_INPUT_EVDEV=m
76# CONFIG_INPUT_KEYBOARD is not set
77# CONFIG_INPUT_MOUSE is not set
78# CONFIG_SERIO is not set
79# CONFIG_VT is not set
80# CONFIG_DEVKMEM is not set
81CONFIG_BFIN_JTAG_COMM=m
82CONFIG_SERIAL_BFIN=y
83CONFIG_SERIAL_BFIN_CONSOLE=y
84# CONFIG_LEGACY_PTYS is not set
85# CONFIG_HW_RANDOM is not set
86CONFIG_SPI=y
87CONFIG_SPI_BFIN=y
88CONFIG_GPIOLIB=y
89CONFIG_GPIO_SYSFS=y
90# CONFIG_HWMON is not set
91CONFIG_WATCHDOG=y
92CONFIG_BFIN_WDT=y
93# CONFIG_USB_SUPPORT is not set
94# CONFIG_DNOTIFY is not set
95CONFIG_JFFS2_FS=m
96CONFIG_NFS_FS=m
97CONFIG_NFS_V3=y
98CONFIG_SMB_FS=m
99CONFIG_DEBUG_KERNEL=y
100CONFIG_DEBUG_SHIRQ=y
101CONFIG_DETECT_HUNG_TASK=y
102CONFIG_DEBUG_INFO=y
103# CONFIG_RCU_CPU_STALL_DETECTOR is not set
104# CONFIG_FTRACE is not set
105CONFIG_DEBUG_MMRS=y
106CONFIG_DEBUG_HWERR=y
107CONFIG_EXACT_HWERR=y
108CONFIG_DEBUG_DOUBLEFAULT=y
109CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
110CONFIG_EARLY_PRINTK=y
111CONFIG_CPLB_INFO=y
112CONFIG_CRYPTO=y
113# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/DNP5370_defconfig b/arch/blackfin/configs/DNP5370_defconfig
new file mode 100644
index 000000000000..0ebc7d9aa426
--- /dev/null
+++ b/arch/blackfin/configs/DNP5370_defconfig
@@ -0,0 +1,121 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_LOCALVERSION="DNP5370"
3CONFIG_SYSVIPC=y
4CONFIG_IKCONFIG=y
5CONFIG_IKCONFIG_PROC=y
6CONFIG_LOG_BUF_SHIFT=14
7CONFIG_BLK_DEV_INITRD=y
8CONFIG_EMBEDDED=y
9CONFIG_SLOB=y
10# CONFIG_BLK_DEV_BSG is not set
11# CONFIG_IOSCHED_CFQ is not set
12CONFIG_BF537=y
13CONFIG_BF_REV_0_3=y
14CONFIG_DNP5370=y
15CONFIG_IRQ_ERROR=7
16# CONFIG_CYCLES_CLOCKSOURCE is not set
17CONFIG_C_CDPRIO=y
18CONFIG_C_AMBEN_B0_B1_B2=y
19CONFIG_PM=y
20# CONFIG_SUSPEND is not set
21CONFIG_NET=y
22CONFIG_PACKET=y
23CONFIG_UNIX=y
24CONFIG_INET=y
25CONFIG_IP_PNP=y
26CONFIG_IP_PNP_RARP=y
27CONFIG_SYN_COOKIES=y
28# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
29# CONFIG_INET_XFRM_MODE_TUNNEL is not set
30# CONFIG_INET_XFRM_MODE_BEET is not set
31# CONFIG_INET_LRO is not set
32# CONFIG_INET_DIAG is not set
33# CONFIG_IPV6 is not set
34CONFIG_LLC2=y
35CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
36CONFIG_MTD=y
37CONFIG_MTD_DEBUG=y
38CONFIG_MTD_DEBUG_VERBOSE=1
39CONFIG_MTD_PARTITIONS=y
40CONFIG_MTD_CHAR=y
41CONFIG_MTD_BLOCK=y
42CONFIG_NFTL=y
43CONFIG_NFTL_RW=y
44CONFIG_MTD_CFI=y
45CONFIG_MTD_CFI_AMDSTD=y
46CONFIG_MTD_ROM=y
47CONFIG_MTD_ABSENT=y
48CONFIG_MTD_COMPLEX_MAPPINGS=y
49CONFIG_MTD_PHYSMAP=y
50CONFIG_MTD_UCLINUX=y
51CONFIG_MTD_PLATRAM=y
52CONFIG_MTD_DATAFLASH=y
53CONFIG_MTD_BLOCK2MTD=y
54CONFIG_MTD_NAND=y
55CONFIG_MTD_NAND_PLATFORM=y
56CONFIG_BLK_DEV_LOOP=y
57CONFIG_BLK_DEV_RAM=y
58# CONFIG_MISC_DEVICES is not set
59CONFIG_NETDEVICES=y
60CONFIG_DAVICOM_PHY=y
61CONFIG_NET_ETHERNET=y
62CONFIG_BFIN_MAC=y
63# CONFIG_NETDEV_1000 is not set
64# CONFIG_NETDEV_10000 is not set
65# CONFIG_WLAN is not set
66# CONFIG_INPUT is not set
67# CONFIG_SERIO is not set
68# CONFIG_BFIN_DMA_INTERFACE is not set
69# CONFIG_VT is not set
70# CONFIG_DEVKMEM is not set
71CONFIG_BFIN_JTAG_COMM=y
72CONFIG_BFIN_JTAG_COMM_CONSOLE=y
73CONFIG_SERIAL_BFIN=y
74CONFIG_SERIAL_BFIN_CONSOLE=y
75CONFIG_SERIAL_BFIN_UART0=y
76CONFIG_LEGACY_PTY_COUNT=64
77# CONFIG_HW_RANDOM is not set
78CONFIG_I2C=y
79CONFIG_I2C_CHARDEV=y
80CONFIG_I2C_BLACKFIN_TWI=y
81CONFIG_SPI=y
82CONFIG_SPI_BFIN=y
83CONFIG_SPI_SPIDEV=y
84CONFIG_GPIOLIB=y
85CONFIG_GPIO_SYSFS=y
86CONFIG_SENSORS_LM75=y
87# CONFIG_USB_SUPPORT is not set
88CONFIG_MMC=y
89CONFIG_MMC_SPI=y
90CONFIG_DMADEVICES=y
91CONFIG_EXT2_FS=y
92CONFIG_EXT2_FS_XATTR=y
93# CONFIG_DNOTIFY is not set
94CONFIG_MSDOS_FS=y
95CONFIG_VFAT_FS=y
96CONFIG_FAT_DEFAULT_CODEPAGE=850
97CONFIG_JFFS2_FS=y
98CONFIG_CRAMFS=y
99CONFIG_ROMFS_FS=y
100CONFIG_ROMFS_BACKED_BY_BOTH=y
101# CONFIG_NETWORK_FILESYSTEMS is not set
102CONFIG_NLS_CODEPAGE_437=y
103CONFIG_NLS_CODEPAGE_850=y
104CONFIG_NLS_ISO8859_1=y
105CONFIG_DEBUG_KERNEL=y
106CONFIG_DEBUG_SHIRQ=y
107CONFIG_DETECT_HUNG_TASK=y
108CONFIG_DEBUG_OBJECTS=y
109CONFIG_DEBUG_LOCK_ALLOC=y
110CONFIG_DEBUG_KOBJECT=y
111CONFIG_DEBUG_INFO=y
112CONFIG_DEBUG_VM=y
113CONFIG_DEBUG_MEMORY_INIT=y
114CONFIG_DEBUG_LIST=y
115# CONFIG_RCU_CPU_STALL_DETECTOR is not set
116CONFIG_SYSCTL_SYSCALL_CHECK=y
117CONFIG_PAGE_POISONING=y
118# CONFIG_FTRACE is not set
119CONFIG_DEBUG_DOUBLEFAULT=y
120CONFIG_CPLB_INFO=y
121CONFIG_CRC_CCITT=y
diff --git a/arch/blackfin/include/asm/bfin_dma.h b/arch/blackfin/include/asm/bfin_dma.h
new file mode 100644
index 000000000000..d51120744148
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_dma.h
@@ -0,0 +1,91 @@
1/*
2 * bfin_dma.h - Blackfin DMA defines/structures/etc...
3 *
4 * Copyright 2004-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __ASM_BFIN_DMA_H__
10#define __ASM_BFIN_DMA_H__
11
12#include <linux/types.h>
13
14/* DMA_CONFIG Masks */
15#define DMAEN 0x0001 /* DMA Channel Enable */
16#define WNR 0x0002 /* Channel Direction (W/R*) */
17#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
18#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
19#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
20#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
21#define RESTART 0x0020 /* DMA Buffer Clear */
22#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
23#define DI_EN 0x0080 /* Data Interrupt Enable */
24#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
25#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
26#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
27#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
28#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
29#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
30#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
31#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
32#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
33#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
34#define NDSIZE 0x0f00 /* Next Descriptor Size */
35#define DMAFLOW 0x7000 /* Flow Control */
36#define DMAFLOW_STOP 0x0000 /* Stop Mode */
37#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
38#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
39#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
40#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
41
42/* DMA_IRQ_STATUS Masks */
43#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
44#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
45#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
46#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
47
48/*
49 * All Blackfin system MMRs are padded to 32bits even if the register
50 * itself is only 16bits. So use a helper macro to streamline this.
51 */
52#define __BFP(m) u16 m; u16 __pad_##m
53
54/*
55 * bfin dma registers layout
56 */
57struct bfin_dma_regs {
58 u32 next_desc_ptr;
59 u32 start_addr;
60 __BFP(config);
61 u32 __pad0;
62 __BFP(x_count);
63 __BFP(x_modify);
64 __BFP(y_count);
65 __BFP(y_modify);
66 u32 curr_desc_ptr;
67 u32 curr_addr;
68 __BFP(irq_status);
69 __BFP(peripheral_map);
70 __BFP(curr_x_count);
71 u32 __pad1;
72 __BFP(curr_y_count);
73 u32 __pad2;
74};
75
76/*
77 * bfin handshake mdma registers layout
78 */
79struct bfin_hmdma_regs {
80 __BFP(control);
81 __BFP(ecinit);
82 __BFP(bcinit);
83 __BFP(ecurgent);
84 __BFP(ecoverflow);
85 __BFP(ecount);
86 __BFP(bcount);
87};
88
89#undef __BFP
90
91#endif
diff --git a/arch/blackfin/include/asm/bfin_serial.h b/arch/blackfin/include/asm/bfin_serial.h
new file mode 100644
index 000000000000..1ff9f1468c02
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_serial.h
@@ -0,0 +1,275 @@
1/*
2 * bfin_serial.h - Blackfin UART/Serial definitions
3 *
4 * Copyright 2006-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_ASM_SERIAL_H__
10#define __BFIN_ASM_SERIAL_H__
11
12#include <linux/serial_core.h>
13#include <mach/anomaly.h>
14#include <mach/bfin_serial.h>
15
16#if defined(CONFIG_BFIN_UART0_CTSRTS) || \
17 defined(CONFIG_BFIN_UART1_CTSRTS) || \
18 defined(CONFIG_BFIN_UART2_CTSRTS) || \
19 defined(CONFIG_BFIN_UART3_CTSRTS)
20# ifdef BFIN_UART_BF54X_STYLE
21# define CONFIG_SERIAL_BFIN_HARD_CTSRTS
22# else
23# define CONFIG_SERIAL_BFIN_CTSRTS
24# endif
25#endif
26
27struct circ_buf;
28struct timer_list;
29struct work_struct;
30
31struct bfin_serial_port {
32 struct uart_port port;
33 unsigned int old_status;
34 int status_irq;
35#ifndef BFIN_UART_BF54X_STYLE
36 unsigned int lsr;
37#endif
38#ifdef CONFIG_SERIAL_BFIN_DMA
39 int tx_done;
40 int tx_count;
41 struct circ_buf rx_dma_buf;
42 struct timer_list rx_dma_timer;
43 int rx_dma_nrows;
44 unsigned int tx_dma_channel;
45 unsigned int rx_dma_channel;
46 struct work_struct tx_dma_workqueue;
47#elif ANOMALY_05000363
48 unsigned int anomaly_threshold;
49#endif
50#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
51 int scts;
52#endif
53#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
54 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
55 int cts_pin;
56 int rts_pin;
57#endif
58};
59
60/* UART_LCR Masks */
61#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
62#define STB 0x04 /* Stop Bits */
63#define PEN 0x08 /* Parity Enable */
64#define EPS 0x10 /* Even Parity Select */
65#define STP 0x20 /* Stick Parity */
66#define SB 0x40 /* Set Break */
67#define DLAB 0x80 /* Divisor Latch Access */
68
69/* UART_LSR Masks */
70#define DR 0x01 /* Data Ready */
71#define OE 0x02 /* Overrun Error */
72#define PE 0x04 /* Parity Error */
73#define FE 0x08 /* Framing Error */
74#define BI 0x10 /* Break Interrupt */
75#define THRE 0x20 /* THR Empty */
76#define TEMT 0x40 /* TSR and UART_THR Empty */
77#define TFI 0x80 /* Transmission Finished Indicator */
78
79/* UART_IER Masks */
80#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
81#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
82#define ELSI 0x04 /* Enable RX Status Interrupt */
83#define EDSSI 0x08 /* Enable Modem Status Interrupt */
84#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */
85#define ETFI 0x20 /* Enable Transmission Finished Interrupt */
86#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */
87
88/* UART_MCR Masks */
89#define XOFF 0x01 /* Transmitter Off */
90#define MRTS 0x02 /* Manual Request To Send */
91#define RFIT 0x04 /* Receive FIFO IRQ Threshold */
92#define RFRT 0x08 /* Receive FIFO RTS Threshold */
93#define LOOP_ENA 0x10 /* Loopback Mode Enable */
94#define FCPOL 0x20 /* Flow Control Pin Polarity */
95#define ARTS 0x40 /* Automatic Request To Send */
96#define ACTS 0x80 /* Automatic Clear To Send */
97
98/* UART_MSR Masks */
99#define SCTS 0x01 /* Sticky CTS */
100#define CTS 0x10 /* Clear To Send */
101#define RFCS 0x20 /* Receive FIFO Count Status */
102
103/* UART_GCTL Masks */
104#define UCEN 0x01 /* Enable UARTx Clocks */
105#define IREN 0x02 /* Enable IrDA Mode */
106#define TPOLC 0x04 /* IrDA TX Polarity Change */
107#define RPOLC 0x08 /* IrDA RX Polarity Change */
108#define FPE 0x10 /* Force Parity Error On Transmit */
109#define FFE 0x20 /* Force Framing Error On Transmit */
110
111#ifdef BFIN_UART_BF54X_STYLE
112# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
113# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
114# define OFFSET_GCTL 0x08 /* Global Control Register */
115# define OFFSET_LCR 0x0C /* Line Control Register */
116# define OFFSET_MCR 0x10 /* Modem Control Register */
117# define OFFSET_LSR 0x14 /* Line Status Register */
118# define OFFSET_MSR 0x18 /* Modem Status Register */
119# define OFFSET_SCR 0x1C /* SCR Scratch Register */
120# define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
121# define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
122# define OFFSET_THR 0x28 /* Transmit Holding register */
123# define OFFSET_RBR 0x2C /* Receive Buffer register */
124#else /* BF533 style */
125# define OFFSET_THR 0x00 /* Transmit Holding register */
126# define OFFSET_RBR 0x00 /* Receive Buffer register */
127# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
128# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
129# define OFFSET_IER 0x04 /* Interrupt Enable Register */
130# define OFFSET_IIR 0x08 /* Interrupt Identification Register */
131# define OFFSET_LCR 0x0C /* Line Control Register */
132# define OFFSET_MCR 0x10 /* Modem Control Register */
133# define OFFSET_LSR 0x14 /* Line Status Register */
134# define OFFSET_MSR 0x18 /* Modem Status Register */
135# define OFFSET_SCR 0x1C /* SCR Scratch Register */
136# define OFFSET_GCTL 0x24 /* Global Control Register */
137/* code should not need IIR, so force build error if they use it */
138# undef OFFSET_IIR
139#endif
140
141/*
142 * All Blackfin system MMRs are padded to 32bits even if the register
143 * itself is only 16bits. So use a helper macro to streamline this.
144 */
145#define __BFP(m) u16 m; u16 __pad_##m
146struct bfin_uart_regs {
147#ifdef BFIN_UART_BF54X_STYLE
148 __BFP(dll);
149 __BFP(dlh);
150 __BFP(gctl);
151 __BFP(lcr);
152 __BFP(mcr);
153 __BFP(lsr);
154 __BFP(msr);
155 __BFP(scr);
156 __BFP(ier_set);
157 __BFP(ier_clear);
158 __BFP(thr);
159 __BFP(rbr);
160#else
161 union {
162 u16 dll;
163 u16 thr;
164 const u16 rbr;
165 };
166 const u16 __pad0;
167 union {
168 u16 dlh;
169 u16 ier;
170 };
171 const u16 __pad1;
172 const __BFP(iir);
173 __BFP(lcr);
174 __BFP(mcr);
175 __BFP(lsr);
176 __BFP(msr);
177 __BFP(scr);
178 const u32 __pad2;
179 __BFP(gctl);
180#endif
181};
182#undef __BFP
183
184#ifndef port_membase
185# define port_membase(p) (((struct bfin_serial_port *)(p))->port.membase)
186#endif
187
188#define UART_GET_CHAR(p) bfin_read16(port_membase(p) + OFFSET_RBR)
189#define UART_GET_DLL(p) bfin_read16(port_membase(p) + OFFSET_DLL)
190#define UART_GET_DLH(p) bfin_read16(port_membase(p) + OFFSET_DLH)
191#define UART_GET_GCTL(p) bfin_read16(port_membase(p) + OFFSET_GCTL)
192#define UART_GET_LCR(p) bfin_read16(port_membase(p) + OFFSET_LCR)
193#define UART_GET_MCR(p) bfin_read16(port_membase(p) + OFFSET_MCR)
194#define UART_GET_MSR(p) bfin_read16(port_membase(p) + OFFSET_MSR)
195
196#define UART_PUT_CHAR(p, v) bfin_write16(port_membase(p) + OFFSET_THR, v)
197#define UART_PUT_DLL(p, v) bfin_write16(port_membase(p) + OFFSET_DLL, v)
198#define UART_PUT_DLH(p, v) bfin_write16(port_membase(p) + OFFSET_DLH, v)
199#define UART_PUT_GCTL(p, v) bfin_write16(port_membase(p) + OFFSET_GCTL, v)
200#define UART_PUT_LCR(p, v) bfin_write16(port_membase(p) + OFFSET_LCR, v)
201#define UART_PUT_MCR(p, v) bfin_write16(port_membase(p) + OFFSET_MCR, v)
202
203#ifdef BFIN_UART_BF54X_STYLE
204
205#define UART_CLEAR_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_CLEAR, v)
206#define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER_SET)
207#define UART_SET_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_SET, v)
208
209#define UART_CLEAR_DLAB(p) /* MMRs not muxed on BF54x */
210#define UART_SET_DLAB(p) /* MMRs not muxed on BF54x */
211
212#define UART_CLEAR_LSR(p) bfin_write16(port_membase(p) + OFFSET_LSR, -1)
213#define UART_GET_LSR(p) bfin_read16(port_membase(p) + OFFSET_LSR)
214#define UART_PUT_LSR(p, v) bfin_write16(port_membase(p) + OFFSET_LSR, v)
215
216/* This handles hard CTS/RTS */
217#define BFIN_UART_CTSRTS_HARD
218#define UART_CLEAR_SCTS(p) bfin_write16((port_membase(p) + OFFSET_MSR), SCTS)
219#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
220#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS))
221#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
222#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
223#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
224
225#else /* BF533 style */
226
227#define UART_CLEAR_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) & ~(v))
228#define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER)
229#define UART_PUT_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER, v)
230#define UART_SET_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) | (v))
231
232#define UART_CLEAR_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0)
233#define UART_SET_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0)
234
235#ifndef put_lsr_cache
236# define put_lsr_cache(p, v) (((struct bfin_serial_port *)(p))->lsr = (v))
237#endif
238#ifndef get_lsr_cache
239# define get_lsr_cache(p) (((struct bfin_serial_port *)(p))->lsr)
240#endif
241
242/* The hardware clears the LSR bits upon read, so we need to cache
243 * some of the more fun bits in software so they don't get lost
244 * when checking the LSR in other code paths (TX).
245 */
246static inline void UART_CLEAR_LSR(void *p)
247{
248 put_lsr_cache(p, 0);
249 bfin_write16(port_membase(p) + OFFSET_LSR, -1);
250}
251static inline unsigned int UART_GET_LSR(void *p)
252{
253 unsigned int lsr = bfin_read16(port_membase(p) + OFFSET_LSR);
254 put_lsr_cache(p, get_lsr_cache(p) | (lsr & (BI|FE|PE|OE)));
255 return lsr | get_lsr_cache(p);
256}
257static inline void UART_PUT_LSR(void *p, uint16_t val)
258{
259 put_lsr_cache(p, get_lsr_cache(p) & ~val);
260}
261
262/* This handles soft CTS/RTS */
263#define UART_GET_CTS(x) gpio_get_value((x)->cts_pin)
264#define UART_DISABLE_RTS(x) gpio_set_value((x)->rts_pin, 1)
265#define UART_ENABLE_RTS(x) gpio_set_value((x)->rts_pin, 0)
266#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
267#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
268
269#endif
270
271#ifndef BFIN_UART_TX_FIFO_SIZE
272# define BFIN_UART_TX_FIFO_SIZE 2
273#endif
274
275#endif /* __BFIN_ASM_SERIAL_H__ */
diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h
index 3f7ef4d97791..29f4fd886174 100644
--- a/arch/blackfin/include/asm/bitops.h
+++ b/arch/blackfin/include/asm/bitops.h
@@ -108,7 +108,9 @@ static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
108#define smp_mb__before_clear_bit() barrier() 108#define smp_mb__before_clear_bit() barrier()
109#define smp_mb__after_clear_bit() barrier() 109#define smp_mb__after_clear_bit() barrier()
110 110
111#define test_bit __skip_test_bit
111#include <asm-generic/bitops/non-atomic.h> 112#include <asm-generic/bitops/non-atomic.h>
113#undef test_bit
112 114
113#endif /* CONFIG_SMP */ 115#endif /* CONFIG_SMP */
114 116
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h
index bd0641a267f1..568885a2c286 100644
--- a/arch/blackfin/include/asm/cache.h
+++ b/arch/blackfin/include/asm/cache.h
@@ -7,6 +7,8 @@
7#ifndef __ARCH_BLACKFIN_CACHE_H 7#ifndef __ARCH_BLACKFIN_CACHE_H
8#define __ARCH_BLACKFIN_CACHE_H 8#define __ARCH_BLACKFIN_CACHE_H
9 9
10#include <linux/linkage.h> /* for asmlinkage */
11
10/* 12/*
11 * Bytes per L1 cache line 13 * Bytes per L1 cache line
12 * Blackfin loads 32 bytes for cache 14 * Blackfin loads 32 bytes for cache
diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h
index 2666ff8ea952..77135b62818e 100644
--- a/arch/blackfin/include/asm/cacheflush.h
+++ b/arch/blackfin/include/asm/cacheflush.h
@@ -11,6 +11,9 @@
11 11
12#include <asm/blackfin.h> /* for SSYNC() */ 12#include <asm/blackfin.h> /* for SSYNC() */
13#include <asm/sections.h> /* for _ramend */ 13#include <asm/sections.h> /* for _ramend */
14#ifdef CONFIG_SMP
15#include <asm/smp.h>
16#endif
14 17
15extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address); 18extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address);
16extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address); 19extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address);
diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h
index eedf3ca65ba2..d9dbc1a53534 100644
--- a/arch/blackfin/include/asm/dma.h
+++ b/arch/blackfin/include/asm/dma.h
@@ -14,40 +14,7 @@
14#include <asm/blackfin.h> 14#include <asm/blackfin.h>
15#include <asm/page.h> 15#include <asm/page.h>
16#include <asm-generic/dma.h> 16#include <asm-generic/dma.h>
17 17#include <asm/bfin_dma.h>
18/* DMA_CONFIG Masks */
19#define DMAEN 0x0001 /* DMA Channel Enable */
20#define WNR 0x0002 /* Channel Direction (W/R*) */
21#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
22#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
23#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
24#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
25#define RESTART 0x0020 /* DMA Buffer Clear */
26#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
27#define DI_EN 0x0080 /* Data Interrupt Enable */
28#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
29#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
30#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
31#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
32#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
33#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
34#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
35#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
36#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
37#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
38#define NDSIZE 0x0f00 /* Next Descriptor Size */
39#define DMAFLOW 0x7000 /* Flow Control */
40#define DMAFLOW_STOP 0x0000 /* Stop Mode */
41#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
42#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
43#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
44#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
45
46/* DMA_IRQ_STATUS Masks */
47#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
48#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
49#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
50#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
51 18
52/*------------------------- 19/*-------------------------
53 * config reg bits value 20 * config reg bits value
@@ -149,7 +116,7 @@ void blackfin_dma_resume(void);
149* DMA API's 116* DMA API's
150*******************************************************************************/ 117*******************************************************************************/
151extern struct dma_channel dma_ch[MAX_DMA_CHANNELS]; 118extern struct dma_channel dma_ch[MAX_DMA_CHANNELS];
152extern struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS]; 119extern struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS];
153extern int channel2irq(unsigned int channel); 120extern int channel2irq(unsigned int channel);
154 121
155static inline void set_dma_start_addr(unsigned int channel, unsigned long addr) 122static inline void set_dma_start_addr(unsigned int channel, unsigned long addr)
diff --git a/arch/blackfin/include/asm/dpmc.h b/arch/blackfin/include/asm/dpmc.h
index efcc3aebeae4..3047120cfcff 100644
--- a/arch/blackfin/include/asm/dpmc.h
+++ b/arch/blackfin/include/asm/dpmc.h
@@ -9,6 +9,8 @@
9#ifndef _BLACKFIN_DPMC_H_ 9#ifndef _BLACKFIN_DPMC_H_
10#define _BLACKFIN_DPMC_H_ 10#define _BLACKFIN_DPMC_H_
11 11
12#include <mach/pll.h>
13
12/* PLL_CTL Masks */ 14/* PLL_CTL Masks */
13#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ 15#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
14#define PLL_OFF 0x0002 /* PLL Not Powered */ 16#define PLL_OFF 0x0002 /* PLL Not Powered */
diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h
index 234fbac17ec1..dccae26805b0 100644
--- a/arch/blackfin/include/asm/io.h
+++ b/arch/blackfin/include/asm/io.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2004-2009 Analog Devices Inc. 2 * Copyright 2004-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
@@ -7,148 +7,48 @@
7#ifndef _BFIN_IO_H 7#ifndef _BFIN_IO_H
8#define _BFIN_IO_H 8#define _BFIN_IO_H
9 9
10#ifdef __KERNEL__
11
12#ifndef __ASSEMBLY__
13#include <linux/types.h>
14#endif
15#include <linux/compiler.h> 10#include <linux/compiler.h>
16 11#include <linux/types.h>
17/* 12#include <asm/byteorder.h>
18 * These are for ISA/PCI shared memory _only_ and should never be used 13
19 * on any other type of memory, including Zorro memory. They are meant to 14#define DECLARE_BFIN_RAW_READX(size, type, asm, asm_sign) \
20 * access the bus in the bus byte order which is little-endian!. 15static inline type __raw_read##size(const volatile void __iomem *addr) \
21 * 16{ \
22 * readX/writeX() are used to access memory mapped devices. On some 17 unsigned int val; \
23 * architectures the memory mapped IO stuff needs to be accessed 18 int tmp; \
24 * differently. On the bfin architecture, we just read/write the 19 __asm__ __volatile__ ( \
25 * memory location directly. 20 "cli %1;" \
26 */ 21 "NOP; NOP; SSYNC;" \
27#ifndef __ASSEMBLY__ 22 "%0 = "#asm" [%2] "#asm_sign";" \
28 23 "sti %1;" \
29static inline unsigned char readb(const volatile void __iomem *addr) 24 : "=d"(val), "=d"(tmp) \
30{ 25 : "a"(addr) \
31 unsigned int val; 26 ); \
32 int tmp; 27 return (type) val; \
33
34 __asm__ __volatile__ (
35 "cli %1;"
36 "NOP; NOP; SSYNC;"
37 "%0 = b [%2] (z);"
38 "sti %1;"
39 : "=d"(val), "=d"(tmp)
40 : "a"(addr)
41 );
42
43 return (unsigned char) val;
44}
45
46static inline unsigned short readw(const volatile void __iomem *addr)
47{
48 unsigned int val;
49 int tmp;
50
51 __asm__ __volatile__ (
52 "cli %1;"
53 "NOP; NOP; SSYNC;"
54 "%0 = w [%2] (z);"
55 "sti %1;"
56 : "=d"(val), "=d"(tmp)
57 : "a"(addr)
58 );
59
60 return (unsigned short) val;
61}
62
63static inline unsigned int readl(const volatile void __iomem *addr)
64{
65 unsigned int val;
66 int tmp;
67
68 __asm__ __volatile__ (
69 "cli %1;"
70 "NOP; NOP; SSYNC;"
71 "%0 = [%2];"
72 "sti %1;"
73 : "=d"(val), "=d"(tmp)
74 : "a"(addr)
75 );
76
77 return val;
78} 28}
79 29DECLARE_BFIN_RAW_READX(b, u8, b, (z))
80#endif /* __ASSEMBLY__ */ 30#define __raw_readb __raw_readb
81 31DECLARE_BFIN_RAW_READX(w, u16, w, (z))
82#define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b)) 32#define __raw_readw __raw_readw
83#define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b)) 33DECLARE_BFIN_RAW_READX(l, u32, , )
84#define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b)) 34#define __raw_readl __raw_readl
85
86#define __raw_readb readb
87#define __raw_readw readw
88#define __raw_readl readl
89#define __raw_writeb writeb
90#define __raw_writew writew
91#define __raw_writel writel
92#define memset_io(a, b, c) memset((void *)(a), (b), (c))
93#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c))
94#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c))
95
96/* Convert "I/O port addresses" to actual addresses. i.e. ugly casts. */
97#define __io(port) ((void *)(unsigned long)(port))
98
99#define inb(port) readb(__io(port))
100#define inw(port) readw(__io(port))
101#define inl(port) readl(__io(port))
102#define outb(x, port) writeb(x, __io(port))
103#define outw(x, port) writew(x, __io(port))
104#define outl(x, port) writel(x, __io(port))
105
106#define inb_p(port) inb(__io(port))
107#define inw_p(port) inw(__io(port))
108#define inl_p(port) inl(__io(port))
109#define outb_p(x, port) outb(x, __io(port))
110#define outw_p(x, port) outw(x, __io(port))
111#define outl_p(x, port) outl(x, __io(port))
112
113#define ioread8_rep(a, d, c) readsb(a, d, c)
114#define ioread16_rep(a, d, c) readsw(a, d, c)
115#define ioread32_rep(a, d, c) readsl(a, d, c)
116#define iowrite8_rep(a, s, c) writesb(a, s, c)
117#define iowrite16_rep(a, s, c) writesw(a, s, c)
118#define iowrite32_rep(a, s, c) writesl(a, s, c)
119
120#define ioread8(x) readb(x)
121#define ioread16(x) readw(x)
122#define ioread32(x) readl(x)
123#define iowrite8(val, x) writeb(val, x)
124#define iowrite16(val, x) writew(val, x)
125#define iowrite32(val, x) writel(val, x)
126
127/**
128 * I/O write barrier
129 *
130 * Ensure ordering of I/O space writes. This will make sure that writes
131 * following the barrier will arrive after all previous writes.
132 */
133#define mmiowb() do { SSYNC(); wmb(); } while (0)
134
135#define IO_SPACE_LIMIT 0xffffffff
136
137/* Values for nocacheflag and cmode */
138#define IOMAP_NOCACHE_SER 1
139
140#ifndef __ASSEMBLY__
141 35
142extern void outsb(unsigned long port, const void *addr, unsigned long count); 36extern void outsb(unsigned long port, const void *addr, unsigned long count);
143extern void outsw(unsigned long port, const void *addr, unsigned long count); 37extern void outsw(unsigned long port, const void *addr, unsigned long count);
144extern void outsw_8(unsigned long port, const void *addr, unsigned long count); 38extern void outsw_8(unsigned long port, const void *addr, unsigned long count);
145extern void outsl(unsigned long port, const void *addr, unsigned long count); 39extern void outsl(unsigned long port, const void *addr, unsigned long count);
40#define outsb outsb
41#define outsw outsw
42#define outsl outsl
146 43
147extern void insb(unsigned long port, void *addr, unsigned long count); 44extern void insb(unsigned long port, void *addr, unsigned long count);
148extern void insw(unsigned long port, void *addr, unsigned long count); 45extern void insw(unsigned long port, void *addr, unsigned long count);
149extern void insw_8(unsigned long port, void *addr, unsigned long count); 46extern void insw_8(unsigned long port, void *addr, unsigned long count);
150extern void insl(unsigned long port, void *addr, unsigned long count); 47extern void insl(unsigned long port, void *addr, unsigned long count);
151extern void insl_16(unsigned long port, void *addr, unsigned long count); 48extern void insl_16(unsigned long port, void *addr, unsigned long count);
49#define insb insb
50#define insw insw
51#define insl insl
152 52
153extern void dma_outsb(unsigned long port, const void *addr, unsigned short count); 53extern void dma_outsb(unsigned long port, const void *addr, unsigned short count);
154extern void dma_outsw(unsigned long port, const void *addr, unsigned short count); 54extern void dma_outsw(unsigned long port, const void *addr, unsigned short count);
@@ -158,108 +58,14 @@ extern void dma_insb(unsigned long port, void *addr, unsigned short count);
158extern void dma_insw(unsigned long port, void *addr, unsigned short count); 58extern void dma_insw(unsigned long port, void *addr, unsigned short count);
159extern void dma_insl(unsigned long port, void *addr, unsigned short count); 59extern void dma_insl(unsigned long port, void *addr, unsigned short count);
160 60
161static inline void readsl(const void __iomem *addr, void *buf, int len) 61/**
162{ 62 * I/O write barrier
163 insl((unsigned long)addr, buf, len); 63 *
164} 64 * Ensure ordering of I/O space writes. This will make sure that writes
165 65 * following the barrier will arrive after all previous writes.
166static inline void readsw(const void __iomem *addr, void *buf, int len)
167{
168 insw((unsigned long)addr, buf, len);
169}
170
171static inline void readsb(const void __iomem *addr, void *buf, int len)
172{
173 insb((unsigned long)addr, buf, len);
174}
175
176static inline void writesl(const void __iomem *addr, const void *buf, int len)
177{
178 outsl((unsigned long)addr, buf, len);
179}
180
181static inline void writesw(const void __iomem *addr, const void *buf, int len)
182{
183 outsw((unsigned long)addr, buf, len);
184}
185
186static inline void writesb(const void __iomem *addr, const void *buf, int len)
187{
188 outsb((unsigned long)addr, buf, len);
189}
190
191/*
192 * Map some physical address range into the kernel address space.
193 */
194static inline void __iomem *__ioremap(unsigned long physaddr, unsigned long size,
195 int cacheflag)
196{
197 return (void __iomem *)physaddr;
198}
199
200/*
201 * Unmap a ioremap()ed region again
202 */
203static inline void iounmap(void *addr)
204{
205}
206
207/*
208 * __iounmap unmaps nearly everything, so be careful
209 * it doesn't free currently pointer/page tables anymore but it
210 * wans't used anyway and might be added later.
211 */
212static inline void __iounmap(void *addr, unsigned long size)
213{
214}
215
216/*
217 * Set new cache mode for some kernel address space.
218 * The caller must push data for that range itself, if such data may already
219 * be in the cache.
220 */ 66 */
221static inline void kernel_set_cachemode(void *addr, unsigned long size, 67#define mmiowb() do { SSYNC(); wmb(); } while (0)
222 int cmode)
223{
224}
225
226static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size)
227{
228 return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
229}
230static inline void __iomem *ioremap_nocache(unsigned long physaddr,
231 unsigned long size)
232{
233 return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
234}
235 68
236extern void blkfin_inv_cache_all(void); 69#include <asm-generic/io.h>
237 70
238#endif 71#endif
239
240#define ioport_map(port, nr) ((void __iomem*)(port))
241#define ioport_unmap(addr)
242
243/* Pages to physical address... */
244#define page_to_bus(page) ((page - mem_map) << PAGE_SHIFT)
245
246#define phys_to_virt(vaddr) ((void *) (vaddr))
247#define virt_to_phys(vaddr) ((unsigned long) (vaddr))
248
249#define virt_to_bus virt_to_phys
250#define bus_to_virt phys_to_virt
251
252/*
253 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
254 * access
255 */
256#define xlate_dev_mem_ptr(p) __va(p)
257
258/*
259 * Convert a virtual cached pointer to an uncached pointer
260 */
261#define xlate_dev_kmem_ptr(p) p
262
263#endif /* __KERNEL__ */
264
265#endif /* _BFIN_IO_H */
diff --git a/arch/blackfin/include/asm/irqflags.h b/arch/blackfin/include/asm/irqflags.h
index 41c4d70544ef..3365cb97f539 100644
--- a/arch/blackfin/include/asm/irqflags.h
+++ b/arch/blackfin/include/asm/irqflags.h
@@ -13,9 +13,6 @@
13#ifdef CONFIG_SMP 13#ifdef CONFIG_SMP
14# include <asm/pda.h> 14# include <asm/pda.h>
15# include <asm/processor.h> 15# include <asm/processor.h>
16/* Forward decl needed due to cdef inter dependencies */
17static inline uint32_t __pure bfin_dspid(void);
18# define blackfin_core_id() (bfin_dspid() & 0xff)
19# define bfin_irq_flags cpu_pda[blackfin_core_id()].imask 16# define bfin_irq_flags cpu_pda[blackfin_core_id()].imask
20#else 17#else
21extern unsigned long bfin_irq_flags; 18extern unsigned long bfin_irq_flags;
diff --git a/arch/blackfin/include/asm/processor.h b/arch/blackfin/include/asm/processor.h
index aea880274de7..8af7772e84cc 100644
--- a/arch/blackfin/include/asm/processor.h
+++ b/arch/blackfin/include/asm/processor.h
@@ -14,7 +14,7 @@
14#define current_text_addr() ({ __label__ _l; _l: &&_l;}) 14#define current_text_addr() ({ __label__ _l; _l: &&_l;})
15 15
16#include <asm/ptrace.h> 16#include <asm/ptrace.h>
17#include <asm/blackfin.h> 17#include <mach/blackfin.h>
18 18
19static inline unsigned long rdusp(void) 19static inline unsigned long rdusp(void)
20{ 20{
@@ -134,6 +134,8 @@ static inline uint32_t __pure bfin_dspid(void)
134 return bfin_read_DSPID(); 134 return bfin_read_DSPID();
135} 135}
136 136
137#define blackfin_core_id() (bfin_dspid() & 0xff)
138
137static inline uint32_t __pure bfin_compiled_revid(void) 139static inline uint32_t __pure bfin_compiled_revid(void)
138{ 140{
139#if defined(CONFIG_BF_REV_0_0) 141#if defined(CONFIG_BF_REV_0_0)
diff --git a/arch/blackfin/include/asm/spinlock.h b/arch/blackfin/include/asm/spinlock.h
index 1942ccfedbe0..1f286e71c21f 100644
--- a/arch/blackfin/include/asm/spinlock.h
+++ b/arch/blackfin/include/asm/spinlock.h
@@ -17,12 +17,12 @@ asmlinkage int __raw_spin_is_locked_asm(volatile int *ptr);
17asmlinkage void __raw_spin_lock_asm(volatile int *ptr); 17asmlinkage void __raw_spin_lock_asm(volatile int *ptr);
18asmlinkage int __raw_spin_trylock_asm(volatile int *ptr); 18asmlinkage int __raw_spin_trylock_asm(volatile int *ptr);
19asmlinkage void __raw_spin_unlock_asm(volatile int *ptr); 19asmlinkage void __raw_spin_unlock_asm(volatile int *ptr);
20asmlinkage void arch_read_lock_asm(volatile int *ptr); 20asmlinkage void __raw_read_lock_asm(volatile int *ptr);
21asmlinkage int arch_read_trylock_asm(volatile int *ptr); 21asmlinkage int __raw_read_trylock_asm(volatile int *ptr);
22asmlinkage void arch_read_unlock_asm(volatile int *ptr); 22asmlinkage void __raw_read_unlock_asm(volatile int *ptr);
23asmlinkage void arch_write_lock_asm(volatile int *ptr); 23asmlinkage void __raw_write_lock_asm(volatile int *ptr);
24asmlinkage int arch_write_trylock_asm(volatile int *ptr); 24asmlinkage int __raw_write_trylock_asm(volatile int *ptr);
25asmlinkage void arch_write_unlock_asm(volatile int *ptr); 25asmlinkage void __raw_write_unlock_asm(volatile int *ptr);
26 26
27static inline int arch_spin_is_locked(arch_spinlock_t *lock) 27static inline int arch_spin_is_locked(arch_spinlock_t *lock)
28{ 28{
@@ -64,32 +64,36 @@ static inline int arch_write_can_lock(arch_rwlock_t *rw)
64 64
65static inline void arch_read_lock(arch_rwlock_t *rw) 65static inline void arch_read_lock(arch_rwlock_t *rw)
66{ 66{
67 arch_read_lock_asm(&rw->lock); 67 __raw_read_lock_asm(&rw->lock);
68} 68}
69 69
70#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
71
70static inline int arch_read_trylock(arch_rwlock_t *rw) 72static inline int arch_read_trylock(arch_rwlock_t *rw)
71{ 73{
72 return arch_read_trylock_asm(&rw->lock); 74 return __raw_read_trylock_asm(&rw->lock);
73} 75}
74 76
75static inline void arch_read_unlock(arch_rwlock_t *rw) 77static inline void arch_read_unlock(arch_rwlock_t *rw)
76{ 78{
77 arch_read_unlock_asm(&rw->lock); 79 __raw_read_unlock_asm(&rw->lock);
78} 80}
79 81
80static inline void arch_write_lock(arch_rwlock_t *rw) 82static inline void arch_write_lock(arch_rwlock_t *rw)
81{ 83{
82 arch_write_lock_asm(&rw->lock); 84 __raw_write_lock_asm(&rw->lock);
83} 85}
84 86
87#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
88
85static inline int arch_write_trylock(arch_rwlock_t *rw) 89static inline int arch_write_trylock(arch_rwlock_t *rw)
86{ 90{
87 return arch_write_trylock_asm(&rw->lock); 91 return __raw_write_trylock_asm(&rw->lock);
88} 92}
89 93
90static inline void arch_write_unlock(arch_rwlock_t *rw) 94static inline void arch_write_unlock(arch_rwlock_t *rw)
91{ 95{
92 arch_write_unlock_asm(&rw->lock); 96 __raw_write_unlock_asm(&rw->lock);
93} 97}
94 98
95#define arch_spin_relax(lock) cpu_relax() 99#define arch_spin_relax(lock) cpu_relax()
diff --git a/arch/blackfin/include/mach-common/pll.h b/arch/blackfin/include/mach-common/pll.h
new file mode 100644
index 000000000000..382178b361af
--- /dev/null
+++ b/arch/blackfin/include/mach-common/pll.h
@@ -0,0 +1,86 @@
1/*
2 * Copyright 2005-2010 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 */
6
7#ifndef _MACH_COMMON_PLL_H
8#define _MACH_COMMON_PLL_H
9
10#ifndef __ASSEMBLY__
11
12#include <asm/blackfin.h>
13#include <asm/irqflags.h>
14
15#ifndef bfin_iwr_restore
16static inline void
17bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2)
18{
19#ifdef SIC_IWR
20 bfin_write_SIC_IWR(iwr0);
21#else
22 bfin_write_SIC_IWR0(iwr0);
23# ifdef SIC_IWR1
24 bfin_write_SIC_IWR1(iwr1);
25# endif
26# ifdef SIC_IWR2
27 bfin_write_SIC_IWR2(iwr2);
28# endif
29#endif
30}
31#endif
32
33#ifndef bfin_iwr_save
34static inline void
35bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2,
36 unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
37{
38#ifdef SIC_IWR
39 *iwr0 = bfin_read_SIC_IWR();
40#else
41 *iwr0 = bfin_read_SIC_IWR0();
42# ifdef SIC_IWR1
43 *iwr1 = bfin_read_SIC_IWR1();
44# endif
45# ifdef SIC_IWR2
46 *iwr2 = bfin_read_SIC_IWR2();
47# endif
48#endif
49 bfin_iwr_restore(niwr0, niwr1, niwr2);
50}
51#endif
52
53static inline void _bfin_write_pll_relock(u32 addr, unsigned int val)
54{
55 unsigned long flags, iwr0, iwr1, iwr2;
56
57 if (val == bfin_read_PLL_CTL())
58 return;
59
60 flags = hard_local_irq_save();
61 /* Enable the PLL Wakeup bit in SIC IWR */
62 bfin_iwr_save(IWR_ENABLE(0), 0, 0, &iwr0, &iwr1, &iwr2);
63
64 bfin_write16(addr, val);
65 SSYNC();
66 asm("IDLE;");
67
68 bfin_iwr_restore(iwr0, iwr1, iwr2);
69 hard_local_irq_restore(flags);
70}
71
72/* Writing to PLL_CTL initiates a PLL relock sequence */
73static inline void bfin_write_PLL_CTL(unsigned int val)
74{
75 _bfin_write_pll_relock(PLL_CTL, val);
76}
77
78/* Writing to VR_CTL initiates a PLL relock sequence */
79static inline void bfin_write_VR_CTL(unsigned int val)
80{
81 _bfin_write_pll_relock(VR_CTL, val);
82}
83
84#endif
85
86#endif
diff --git a/arch/blackfin/include/mach-common/ports-a.h b/arch/blackfin/include/mach-common/ports-a.h
new file mode 100644
index 000000000000..9f78a761c40a
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-a.h
@@ -0,0 +1,25 @@
1/*
2 * Port A Masks
3 */
4
5#ifndef __BFIN_PERIPHERAL_PORT_A__
6#define __BFIN_PERIPHERAL_PORT_A__
7
8#define PA0 (1 << 0)
9#define PA1 (1 << 1)
10#define PA2 (1 << 2)
11#define PA3 (1 << 3)
12#define PA4 (1 << 4)
13#define PA5 (1 << 5)
14#define PA6 (1 << 6)
15#define PA7 (1 << 7)
16#define PA8 (1 << 8)
17#define PA9 (1 << 9)
18#define PA10 (1 << 10)
19#define PA11 (1 << 11)
20#define PA12 (1 << 12)
21#define PA13 (1 << 13)
22#define PA14 (1 << 14)
23#define PA15 (1 << 15)
24
25#endif
diff --git a/arch/blackfin/include/mach-common/ports-b.h b/arch/blackfin/include/mach-common/ports-b.h
new file mode 100644
index 000000000000..b81702f09ec6
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-b.h
@@ -0,0 +1,25 @@
1/*
2 * Port B Masks
3 */
4
5#ifndef __BFIN_PERIPHERAL_PORT_B__
6#define __BFIN_PERIPHERAL_PORT_B__
7
8#define PB0 (1 << 0)
9#define PB1 (1 << 1)
10#define PB2 (1 << 2)
11#define PB3 (1 << 3)
12#define PB4 (1 << 4)
13#define PB5 (1 << 5)
14#define PB6 (1 << 6)
15#define PB7 (1 << 7)
16#define PB8 (1 << 8)
17#define PB9 (1 << 9)
18#define PB10 (1 << 10)
19#define PB11 (1 << 11)
20#define PB12 (1 << 12)
21#define PB13 (1 << 13)
22#define PB14 (1 << 14)
23#define PB15 (1 << 15)
24
25#endif
diff --git a/arch/blackfin/include/mach-common/ports-c.h b/arch/blackfin/include/mach-common/ports-c.h
new file mode 100644
index 000000000000..3cc665e0ba08
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-c.h
@@ -0,0 +1,25 @@
1/*
2 * Port C Masks
3 */
4
5#ifndef __BFIN_PERIPHERAL_PORT_C__
6#define __BFIN_PERIPHERAL_PORT_C__
7
8#define PC0 (1 << 0)
9#define PC1 (1 << 1)
10#define PC2 (1 << 2)
11#define PC3 (1 << 3)
12#define PC4 (1 << 4)
13#define PC5 (1 << 5)
14#define PC6 (1 << 6)
15#define PC7 (1 << 7)
16#define PC8 (1 << 8)
17#define PC9 (1 << 9)
18#define PC10 (1 << 10)
19#define PC11 (1 << 11)
20#define PC12 (1 << 12)
21#define PC13 (1 << 13)
22#define PC14 (1 << 14)
23#define PC15 (1 << 15)
24
25#endif
diff --git a/arch/blackfin/include/mach-common/ports-d.h b/arch/blackfin/include/mach-common/ports-d.h
new file mode 100644
index 000000000000..868c6a01f1b2
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-d.h
@@ -0,0 +1,25 @@
1/*
2 * Port D Masks
3 */
4
5#ifndef __BFIN_PERIPHERAL_PORT_D__
6#define __BFIN_PERIPHERAL_PORT_D__
7
8#define PD0 (1 << 0)
9#define PD1 (1 << 1)
10#define PD2 (1 << 2)
11#define PD3 (1 << 3)
12#define PD4 (1 << 4)
13#define PD5 (1 << 5)
14#define PD6 (1 << 6)
15#define PD7 (1 << 7)
16#define PD8 (1 << 8)
17#define PD9 (1 << 9)
18#define PD10 (1 << 10)
19#define PD11 (1 << 11)
20#define PD12 (1 << 12)
21#define PD13 (1 << 13)
22#define PD14 (1 << 14)
23#define PD15 (1 << 15)
24
25#endif
diff --git a/arch/blackfin/include/mach-common/ports-e.h b/arch/blackfin/include/mach-common/ports-e.h
new file mode 100644
index 000000000000..c88b0d0dd443
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-e.h
@@ -0,0 +1,25 @@
1/*
2 * Port E Masks
3 */
4
5#ifndef __BFIN_PERIPHERAL_PORT_E__
6#define __BFIN_PERIPHERAL_PORT_E__
7
8#define PE0 (1 << 0)
9#define PE1 (1 << 1)
10#define PE2 (1 << 2)
11#define PE3 (1 << 3)
12#define PE4 (1 << 4)
13#define PE5 (1 << 5)
14#define PE6 (1 << 6)
15#define PE7 (1 << 7)
16#define PE8 (1 << 8)
17#define PE9 (1 << 9)
18#define PE10 (1 << 10)
19#define PE11 (1 << 11)
20#define PE12 (1 << 12)
21#define PE13 (1 << 13)
22#define PE14 (1 << 14)
23#define PE15 (1 << 15)
24
25#endif
diff --git a/arch/blackfin/include/mach-common/ports-f.h b/arch/blackfin/include/mach-common/ports-f.h
new file mode 100644
index 000000000000..d6af20633278
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-f.h
@@ -0,0 +1,25 @@
1/*
2 * Port F Masks
3 */
4
5#ifndef __BFIN_PERIPHERAL_PORT_F__
6#define __BFIN_PERIPHERAL_PORT_F__
7
8#define PF0 (1 << 0)
9#define PF1 (1 << 1)
10#define PF2 (1 << 2)
11#define PF3 (1 << 3)
12#define PF4 (1 << 4)
13#define PF5 (1 << 5)
14#define PF6 (1 << 6)
15#define PF7 (1 << 7)
16#define PF8 (1 << 8)
17#define PF9 (1 << 9)
18#define PF10 (1 << 10)
19#define PF11 (1 << 11)
20#define PF12 (1 << 12)
21#define PF13 (1 << 13)
22#define PF14 (1 << 14)
23#define PF15 (1 << 15)
24
25#endif
diff --git a/arch/blackfin/include/mach-common/ports-g.h b/arch/blackfin/include/mach-common/ports-g.h
new file mode 100644
index 000000000000..09355d333c0e
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-g.h
@@ -0,0 +1,25 @@
1/*
2 * Port G Masks
3 */
4
5#ifndef __BFIN_PERIPHERAL_PORT_G__
6#define __BFIN_PERIPHERAL_PORT_G__
7
8#define PG0 (1 << 0)
9#define PG1 (1 << 1)
10#define PG2 (1 << 2)
11#define PG3 (1 << 3)
12#define PG4 (1 << 4)
13#define PG5 (1 << 5)
14#define PG6 (1 << 6)
15#define PG7 (1 << 7)
16#define PG8 (1 << 8)
17#define PG9 (1 << 9)
18#define PG10 (1 << 10)
19#define PG11 (1 << 11)
20#define PG12 (1 << 12)
21#define PG13 (1 << 13)
22#define PG14 (1 << 14)
23#define PG15 (1 << 15)
24
25#endif
diff --git a/arch/blackfin/include/mach-common/ports-h.h b/arch/blackfin/include/mach-common/ports-h.h
new file mode 100644
index 000000000000..fa3910c6fbd4
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-h.h
@@ -0,0 +1,25 @@
1/*
2 * Port H Masks
3 */
4
5#ifndef __BFIN_PERIPHERAL_PORT_H__
6#define __BFIN_PERIPHERAL_PORT_H__
7
8#define PH0 (1 << 0)
9#define PH1 (1 << 1)
10#define PH2 (1 << 2)
11#define PH3 (1 << 3)
12#define PH4 (1 << 4)
13#define PH5 (1 << 5)
14#define PH6 (1 << 6)
15#define PH7 (1 << 7)
16#define PH8 (1 << 8)
17#define PH9 (1 << 9)
18#define PH10 (1 << 10)
19#define PH11 (1 << 11)
20#define PH12 (1 << 12)
21#define PH13 (1 << 13)
22#define PH14 (1 << 14)
23#define PH15 (1 << 15)
24
25#endif
diff --git a/arch/blackfin/include/mach-common/ports-i.h b/arch/blackfin/include/mach-common/ports-i.h
new file mode 100644
index 000000000000..f176f08af624
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-i.h
@@ -0,0 +1,25 @@
1/*
2 * Port I Masks
3 */
4
5#ifndef __BFIN_PERIPHERAL_PORT_I__
6#define __BFIN_PERIPHERAL_PORT_I__
7
8#define PI0 (1 << 0)
9#define PI1 (1 << 1)
10#define PI2 (1 << 2)
11#define PI3 (1 << 3)
12#define PI4 (1 << 4)
13#define PI5 (1 << 5)
14#define PI6 (1 << 6)
15#define PI7 (1 << 7)
16#define PI8 (1 << 8)
17#define PI9 (1 << 9)
18#define PI10 (1 << 10)
19#define PI11 (1 << 11)
20#define PI12 (1 << 12)
21#define PI13 (1 << 13)
22#define PI14 (1 << 14)
23#define PI15 (1 << 15)
24
25#endif
diff --git a/arch/blackfin/include/mach-common/ports-j.h b/arch/blackfin/include/mach-common/ports-j.h
new file mode 100644
index 000000000000..924123ecec5a
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-j.h
@@ -0,0 +1,25 @@
1/*
2 * Port J Masks
3 */
4
5#ifndef __BFIN_PERIPHERAL_PORT_J__
6#define __BFIN_PERIPHERAL_PORT_J__
7
8#define PJ0 (1 << 0)
9#define PJ1 (1 << 1)
10#define PJ2 (1 << 2)
11#define PJ3 (1 << 3)
12#define PJ4 (1 << 4)
13#define PJ5 (1 << 5)
14#define PJ6 (1 << 6)
15#define PJ7 (1 << 7)
16#define PJ8 (1 << 8)
17#define PJ9 (1 << 9)
18#define PJ10 (1 << 10)
19#define PJ11 (1 << 11)
20#define PJ12 (1 << 12)
21#define PJ13 (1 << 13)
22#define PJ14 (1 << 14)
23#define PJ15 (1 << 15)
24
25#endif
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
index bfe75af4e8bd..886e00014d75 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
@@ -116,7 +116,7 @@ void __init generate_cplb_tables_all(void)
116 ((_ramend - uncached_end) >= 1 * 1024 * 1024)) 116 ((_ramend - uncached_end) >= 1 * 1024 * 1024))
117 dcplb_bounds[i_d].eaddr = uncached_end; 117 dcplb_bounds[i_d].eaddr = uncached_end;
118 else 118 else
119 dcplb_bounds[i_d].eaddr = uncached_end & ~(1 * 1024 * 1024); 119 dcplb_bounds[i_d].eaddr = uncached_end & ~(1 * 1024 * 1024 - 1);
120 dcplb_bounds[i_d++].data = SDRAM_DGENERIC; 120 dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
121 /* DMA uncached region. */ 121 /* DMA uncached region. */
122 if (DMA_UNCACHED_REGION) { 122 if (DMA_UNCACHED_REGION) {
diff --git a/arch/blackfin/kernel/kgdb.c b/arch/blackfin/kernel/kgdb.c
index edae461b1c54..eb92592fd80c 100644
--- a/arch/blackfin/kernel/kgdb.c
+++ b/arch/blackfin/kernel/kgdb.c
@@ -345,6 +345,23 @@ void kgdb_roundup_cpu(int cpu, unsigned long flags)
345} 345}
346#endif 346#endif
347 347
348#ifdef CONFIG_IPIPE
349static unsigned long kgdb_arch_imask;
350#endif
351
352void kgdb_post_primary_code(struct pt_regs *regs, int e_vector, int err_code)
353{
354 if (kgdb_single_step)
355 preempt_enable();
356
357#ifdef CONFIG_IPIPE
358 if (kgdb_arch_imask) {
359 cpu_pda[raw_smp_processor_id()].ex_imask = kgdb_arch_imask;
360 kgdb_arch_imask = 0;
361 }
362#endif
363}
364
348int kgdb_arch_handle_exception(int vector, int signo, 365int kgdb_arch_handle_exception(int vector, int signo,
349 int err_code, char *remcom_in_buffer, 366 int err_code, char *remcom_in_buffer,
350 char *remcom_out_buffer, 367 char *remcom_out_buffer,
@@ -388,6 +405,12 @@ int kgdb_arch_handle_exception(int vector, int signo,
388 * kgdb_single_step > 0 means in single step mode 405 * kgdb_single_step > 0 means in single step mode
389 */ 406 */
390 kgdb_single_step = i + 1; 407 kgdb_single_step = i + 1;
408
409 preempt_disable();
410#ifdef CONFIG_IPIPE
411 kgdb_arch_imask = cpu_pda[raw_smp_processor_id()].ex_imask;
412 cpu_pda[raw_smp_processor_id()].ex_imask = 0;
413#endif
391 } 414 }
392 415
393 bfin_correct_hw_break(); 416 bfin_correct_hw_break();
@@ -448,6 +471,9 @@ void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long ip)
448int kgdb_arch_init(void) 471int kgdb_arch_init(void)
449{ 472{
450 kgdb_single_step = 0; 473 kgdb_single_step = 0;
474#ifdef CONFIG_IPIPE
475 kgdb_arch_imask = 0;
476#endif
451 477
452 bfin_remove_all_hw_break(); 478 bfin_remove_all_hw_break();
453 return 0; 479 return 0;
diff --git a/arch/blackfin/kernel/kgdb_test.c b/arch/blackfin/kernel/kgdb_test.c
index 08c0236acf3c..2a6e9dbb62a5 100644
--- a/arch/blackfin/kernel/kgdb_test.c
+++ b/arch/blackfin/kernel/kgdb_test.c
@@ -95,6 +95,10 @@ static int __init kgdbtest_init(void)
95{ 95{
96 struct proc_dir_entry *entry; 96 struct proc_dir_entry *entry;
97 97
98#if L2_LENGTH
99 num2 = 0;
100#endif
101
98 entry = proc_create("kgdbtest", 0, NULL, &kgdb_test_proc_fops); 102 entry = proc_create("kgdbtest", 0, NULL, &kgdb_test_proc_fops);
99 if (entry == NULL) 103 if (entry == NULL)
100 return -ENOMEM; 104 return -ENOMEM;
diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c
index b894c8abe7ec..c0ccadcfa44e 100644
--- a/arch/blackfin/mach-bf518/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf518/boards/ezbrd.c
@@ -104,24 +104,23 @@ static const unsigned short bfin_mac_peripherals[] = {
104 104
105static struct bfin_phydev_platform_data bfin_phydev_data[] = { 105static struct bfin_phydev_platform_data bfin_phydev_data[] = {
106 { 106 {
107 .addr = 1, 107#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
108 .irq = IRQ_MAC_PHYINT,
109 },
110 {
111 .addr = 2,
112 .irq = IRQ_MAC_PHYINT,
113 },
114 {
115 .addr = 3, 108 .addr = 3,
109#else
110 .addr = 1,
111#endif
116 .irq = IRQ_MAC_PHYINT, 112 .irq = IRQ_MAC_PHYINT,
117 }, 113 },
118}; 114};
119 115
120static struct bfin_mii_bus_platform_data bfin_mii_bus_data = { 116static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
121 .phydev_number = 3, 117 .phydev_number = 1,
122 .phydev_data = bfin_phydev_data, 118 .phydev_data = bfin_phydev_data,
123 .phy_mode = PHY_INTERFACE_MODE_MII, 119 .phy_mode = PHY_INTERFACE_MODE_MII,
124 .mac_peripherals = bfin_mac_peripherals, 120 .mac_peripherals = bfin_mac_peripherals,
121#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
122 .phy_mask = 0xfff7, /* Only probe the port phy connect to the on chip MAC */
123#endif
125}; 124};
126 125
127static struct platform_device bfin_mii_bus = { 126static struct platform_device bfin_mii_bus = {
@@ -453,7 +452,7 @@ static struct resource bfin_uart0_resources[] = {
453 }, 452 },
454}; 453};
455 454
456unsigned short bfin_uart0_peripherals[] = { 455static unsigned short bfin_uart0_peripherals[] = {
457 P_UART0_TX, P_UART0_RX, 0 456 P_UART0_TX, P_UART0_RX, 0
458}; 457};
459 458
@@ -496,7 +495,7 @@ static struct resource bfin_uart1_resources[] = {
496 }, 495 },
497}; 496};
498 497
499unsigned short bfin_uart1_peripherals[] = { 498static unsigned short bfin_uart1_peripherals[] = {
500 P_UART1_TX, P_UART1_RX, 0 499 P_UART1_TX, P_UART1_RX, 0
501}; 500};
502 501
@@ -636,9 +635,9 @@ static struct resource bfin_sport0_uart_resources[] = {
636 }, 635 },
637}; 636};
638 637
639unsigned short bfin_sport0_peripherals[] = { 638static unsigned short bfin_sport0_peripherals[] = {
640 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 639 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
641 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 640 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
642}; 641};
643 642
644static struct platform_device bfin_sport0_uart_device = { 643static struct platform_device bfin_sport0_uart_device = {
@@ -670,9 +669,9 @@ static struct resource bfin_sport1_uart_resources[] = {
670 }, 669 },
671}; 670};
672 671
673unsigned short bfin_sport1_peripherals[] = { 672static unsigned short bfin_sport1_peripherals[] = {
674 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 673 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
675 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 674 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
676}; 675};
677 676
678static struct platform_device bfin_sport1_uart_device = { 677static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf518/boards/tcm-bf518.c b/arch/blackfin/mach-bf518/boards/tcm-bf518.c
index e6ce1d7c523a..50fc5c89e379 100644
--- a/arch/blackfin/mach-bf518/boards/tcm-bf518.c
+++ b/arch/blackfin/mach-bf518/boards/tcm-bf518.c
@@ -377,7 +377,7 @@ static struct resource bfin_uart0_resources[] = {
377 }, 377 },
378}; 378};
379 379
380unsigned short bfin_uart0_peripherals[] = { 380static unsigned short bfin_uart0_peripherals[] = {
381 P_UART0_TX, P_UART0_RX, 0 381 P_UART0_TX, P_UART0_RX, 0
382}; 382};
383 383
@@ -420,7 +420,7 @@ static struct resource bfin_uart1_resources[] = {
420 }, 420 },
421}; 421};
422 422
423unsigned short bfin_uart1_peripherals[] = { 423static unsigned short bfin_uart1_peripherals[] = {
424 P_UART1_TX, P_UART1_RX, 0 424 P_UART1_TX, P_UART1_RX, 0
425}; 425};
426 426
@@ -547,9 +547,9 @@ static struct resource bfin_sport0_uart_resources[] = {
547 }, 547 },
548}; 548};
549 549
550unsigned short bfin_sport0_peripherals[] = { 550static unsigned short bfin_sport0_peripherals[] = {
551 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 551 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
552 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 552 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
553}; 553};
554 554
555static struct platform_device bfin_sport0_uart_device = { 555static struct platform_device bfin_sport0_uart_device = {
@@ -581,9 +581,9 @@ static struct resource bfin_sport1_uart_resources[] = {
581 }, 581 },
582}; 582};
583 583
584unsigned short bfin_sport1_peripherals[] = { 584static unsigned short bfin_sport1_peripherals[] = {
585 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 585 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
586 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 586 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
587}; 587};
588 588
589static struct platform_device bfin_sport1_uart_device = { 589static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf518/dma.c b/arch/blackfin/mach-bf518/dma.c
index 78b43605a0b5..bcd1fbc8c543 100644
--- a/arch/blackfin/mach-bf518/dma.c
+++ b/arch/blackfin/mach-bf518/dma.c
@@ -11,7 +11,7 @@
11#include <asm/blackfin.h> 11#include <asm/blackfin.h>
12#include <asm/dma.h> 12#include <asm/dma.h>
13 13
14struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { 14struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
15 (struct dma_register *) DMA0_NEXT_DESC_PTR, 15 (struct dma_register *) DMA0_NEXT_DESC_PTR,
16 (struct dma_register *) DMA1_NEXT_DESC_PTR, 16 (struct dma_register *) DMA1_NEXT_DESC_PTR,
17 (struct dma_register *) DMA2_NEXT_DESC_PTR, 17 (struct dma_register *) DMA2_NEXT_DESC_PTR,
diff --git a/arch/blackfin/mach-bf518/include/mach/bfin_serial.h b/arch/blackfin/mach-bf518/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..00c603fe8218
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/bfin_serial.h
@@ -0,0 +1,14 @@
1/*
2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
3 *
4 * Copyright 2006-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_MACH_SERIAL_H__
10#define __BFIN_MACH_SERIAL_H__
11
12#define BFIN_UART_NR_PORTS 2
13
14#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
index 970d310021e7..f6d924ac0c44 100644
--- a/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
@@ -4,36 +4,9 @@
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later
5 */ 5 */
6 6
7#include <linux/serial.h>
8#include <asm/dma.h> 7#include <asm/dma.h>
9#include <asm/portmux.h> 8#include <asm/portmux.h>
10 9
11#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
12#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
13#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
14#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
15#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
16#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
17#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
18
19#define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v)
20#define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
21#define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v)
22#define UART_SET_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
23#define UART_CLEAR_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
24#define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
25#define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
26#define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
27
28#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
29#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
30
31#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
32#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
33#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
34#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
35#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
36
37#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) 10#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
38# define CONFIG_SERIAL_BFIN_CTSRTS 11# define CONFIG_SERIAL_BFIN_CTSRTS
39 12
@@ -54,50 +27,6 @@
54# endif 27# endif
55#endif 28#endif
56 29
57#define BFIN_UART_TX_FIFO_SIZE 2
58
59/*
60 * The pin configuration is different from schematic
61 */
62struct bfin_serial_port {
63 struct uart_port port;
64 unsigned int old_status;
65 int status_irq;
66 unsigned int lsr;
67#ifdef CONFIG_SERIAL_BFIN_DMA
68 int tx_done;
69 int tx_count;
70 struct circ_buf rx_dma_buf;
71 struct timer_list rx_dma_timer;
72 int rx_dma_nrows;
73 unsigned int tx_dma_channel;
74 unsigned int rx_dma_channel;
75 struct work_struct tx_dma_workqueue;
76#endif
77#ifdef CONFIG_SERIAL_BFIN_CTSRTS
78 struct timer_list cts_timer;
79 int cts_pin;
80 int rts_pin;
81#endif
82};
83
84/* The hardware clears the LSR bits upon read, so we need to cache
85 * some of the more fun bits in software so they don't get lost
86 * when checking the LSR in other code paths (TX).
87 */
88static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
89{
90 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
91 uart->lsr |= (lsr & (BI|FE|PE|OE));
92 return lsr | uart->lsr;
93}
94
95static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
96{
97 uart->lsr = 0;
98 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
99}
100
101struct bfin_serial_res { 30struct bfin_serial_res {
102 unsigned long uart_base_addr; 31 unsigned long uart_base_addr;
103 int uart_irq; 32 int uart_irq;
@@ -146,3 +75,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
146}; 75};
147 76
148#define DRIVER_NAME "bfin-uart" 77#define DRIVER_NAME "bfin-uart"
78
79#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf518/include/mach/blackfin.h b/arch/blackfin/mach-bf518/include/mach/blackfin.h
index 9053462be4b1..a8828863226e 100644
--- a/arch/blackfin/mach-bf518/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf518/include/mach/blackfin.h
@@ -1,61 +1,43 @@
1/* 1/*
2 * Copyright 2008-2009 Analog Devices Inc. 2 * Copyright 2008-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later.
5 */ 5 */
6 6
7#ifndef _MACH_BLACKFIN_H_ 7#ifndef _MACH_BLACKFIN_H_
8#define _MACH_BLACKFIN_H_ 8#define _MACH_BLACKFIN_H_
9 9
10#include "bf518.h" 10#include "bf518.h"
11#include "defBF512.h"
12#include "anomaly.h" 11#include "anomaly.h"
13 12
14#if defined(CONFIG_BF518) 13#include <asm/def_LPBlackfin.h>
15#include "defBF518.h" 14#ifdef CONFIG_BF512
15# include "defBF512.h"
16#endif 16#endif
17 17#ifdef CONFIG_BF514
18#if defined(CONFIG_BF516) 18# include "defBF514.h"
19#include "defBF516.h"
20#endif
21
22#if defined(CONFIG_BF514)
23#include "defBF514.h"
24#endif 19#endif
25 20#ifdef CONFIG_BF516
26#if defined(CONFIG_BF512) 21# include "defBF516.h"
27#include "defBF512.h"
28#endif 22#endif
29 23#ifdef CONFIG_BF518
30#if !defined(__ASSEMBLY__) 24# include "defBF518.h"
31#include "cdefBF512.h"
32
33#if defined(CONFIG_BF518)
34#include "cdefBF518.h"
35#endif 25#endif
36 26
37#if defined(CONFIG_BF516) 27#ifndef __ASSEMBLY__
38#include "cdefBF516.h" 28# include <asm/cdef_LPBlackfin.h>
29# ifdef CONFIG_BF512
30# include "cdefBF512.h"
31# endif
32# ifdef CONFIG_BF514
33# include "cdefBF514.h"
34# endif
35# ifdef CONFIG_BF516
36# include "cdefBF516.h"
37# endif
38# ifdef CONFIG_BF518
39# include "cdefBF518.h"
40# endif
39#endif 41#endif
40 42
41#if defined(CONFIG_BF514)
42#include "cdefBF514.h"
43#endif
44#endif
45
46#define BFIN_UART_NR_PORTS 2
47
48#define OFFSET_THR 0x00 /* Transmit Holding register */
49#define OFFSET_RBR 0x00 /* Receive Buffer register */
50#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
51#define OFFSET_IER 0x04 /* Interrupt Enable Register */
52#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
53#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
54#define OFFSET_LCR 0x0C /* Line Control Register */
55#define OFFSET_MCR 0x10 /* Modem Control Register */
56#define OFFSET_LSR 0x14 /* Line Status Register */
57#define OFFSET_MSR 0x18 /* Modem Status Register */
58#define OFFSET_SCR 0x1C /* SCR Scratch Register */
59#define OFFSET_GCTL 0x24 /* Global Control Register */
60
61#endif 43#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h b/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
index 493020d0a65a..b657d37a3402 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2008-2009 Analog Devices Inc. 2 * Copyright 2008-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
@@ -7,15 +7,1037 @@
7#ifndef _CDEF_BF512_H 7#ifndef _CDEF_BF512_H
8#define _CDEF_BF512_H 8#define _CDEF_BF512_H
9 9
10/* include all Core registers and bit definitions */ 10/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
11#include "defBF512.h" 11#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
12#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
13#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
14#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
15#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
16#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
17#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
18#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
19#define bfin_read_CHIPID() bfin_read32(CHIPID)
20#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
12 21
13/* include core specific register pointer definitions */
14#include <asm/cdef_LPBlackfin.h>
15 22
16/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF512 */ 23/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
24#define bfin_read_SWRST() bfin_read16(SWRST)
25#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
26#define bfin_read_SYSCR() bfin_read16(SYSCR)
27#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
17 28
18/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ 29#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
19#include "cdefBF51x_base.h" 30#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
31#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
32#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
33#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6))
34#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)
35
36#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
37#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
38#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
39#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
40#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
41#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
42#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
43#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
44
45#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
46#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
47#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6))
48#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
49
50#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
51#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
52#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6))
53#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)
54
55/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */
56
57#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
58#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
59#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
60#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
61#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
62#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
63#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
64#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
65#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
66#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
67#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
68#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
69#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
70#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
71
72/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
73#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
74#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
75#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
76#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
77#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
78#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
79
80
81/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
82#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
83#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
84#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
85#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
86#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
87#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
88#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
89#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
90#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
91#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
92#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
93#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val)
94#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
95#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
96
97
98/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
99#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
100#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
101#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
102#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
103#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
104#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
105#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
106#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
107#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
108#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
109#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
110#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
111#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
112#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
113#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
114#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
115#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
116#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
117#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
118#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
119#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
120#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
121#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
122#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
123
124
125/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
126#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
127#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
128#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
129#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
130#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
131#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
132#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
133#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
134
135#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
136#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
137#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
138#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
139#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
140#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
141#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
142#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
143
144#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
145#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
146#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
147#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
148#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
149#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
150#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
151#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
152
153#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
154#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
155#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
156#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
157#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
158#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
159#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
160#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
161
162#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
163#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
164#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
165#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
166#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
167#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
168#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
169#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
170
171#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
172#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
173#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
174#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
175#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
176#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
177#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
178#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
179
180#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
181#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
182#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
183#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
184#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
185#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
186#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
187#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
188
189#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
190#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
191#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
192#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
193#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
194#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
195#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
196#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
197
198#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
199#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
200#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
201#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
202#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
203#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val)
204
205
206/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
207#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
208#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
209#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
210#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
211#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
212#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
213#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
214#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
215#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
216#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
217#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
218#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
219#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
220#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
221#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
222#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
223#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
224#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
225#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
226#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
227#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
228#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
229#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
230#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
231#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
232#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
233#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
234#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
235#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
236#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
237#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
238#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
239#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
240#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
241
242
243/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
244#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
245#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
246#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
247#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
248#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
249#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
250#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
251#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
252#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
253#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
254#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
255#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
256#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
257#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX, val)
258#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
259#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX, val)
260#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
261#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX, val)
262#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
263#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX, val)
264#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
265#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
266#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
267#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
268#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
269#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
270#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
271#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
272#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
273#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
274#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
275#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
276#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
277#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
278#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
279#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
280#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
281#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
282#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
283#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
284#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
285#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
286#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
287#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
288#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
289#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
290#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
291#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
292#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
293#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
294#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
295#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
296
297
298/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
299#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
300#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
301#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
302#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
303#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
304#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
305#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
306#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
307#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
308#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
309#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
310#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
311#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
312#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX, val)
313#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
314#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX, val)
315#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
316#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX, val)
317#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
318#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX, val)
319#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
320#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
321#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
322#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
323#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
324#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
325#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
326#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
327#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
328#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
329#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
330#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
331#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
332#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
333#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
334#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
335#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
336#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
337#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
338#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
339#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
340#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
341#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
342#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
343#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
344#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
345#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
346#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
347#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
348#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
349#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
350#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
351
352
353/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
354#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
355#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
356#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
357#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
358#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
359#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
360#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
361#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
362#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
363#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
364#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
365#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
366#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
367#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
368
369
370/* DMA Traffic Control Registers */
371#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
372#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER, val)
373#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
374#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT, val)
375
376/* DMA Controller */
377#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
378#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
379#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
380#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
381#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
382#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
383#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
384#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
385#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
386#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
387#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
388#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
389#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
390#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
391#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
392#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
393#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
394#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
395#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
396#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
397#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
398#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
399#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
400#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
401#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
402#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
403
404#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
405#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
406#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
407#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
408#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
409#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
410#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
411#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
412#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
413#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
414#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
415#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
416#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
417#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
418#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
419#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
420#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
421#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
422#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
423#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
424#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
425#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
426#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
427#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
428#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
429#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
430
431#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
432#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
433#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
434#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
435#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
436#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
437#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
438#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
439#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
440#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
441#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
442#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
443#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
444#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
445#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
446#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
447#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
448#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
449#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
450#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
451#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
452#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
453#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
454#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
455#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
456#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
457
458#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
459#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
460#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
461#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
462#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
463#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
464#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
465#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
466#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
467#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
468#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
469#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
470#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
471#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
472#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
473#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
474#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
475#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
476#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
477#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
478#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
479#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
480#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
481#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
482#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
483#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
484
485#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
486#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
487#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
488#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
489#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
490#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
491#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
492#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
493#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
494#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
495#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
496#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
497#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
498#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
499#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
500#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
501#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
502#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
503#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
504#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
505#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
506#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
507#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
508#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
509#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
510#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
511
512#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
513#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
514#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
515#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
516#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
517#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
518#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
519#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
520#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
521#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
522#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
523#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
524#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
525#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
526#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
527#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
528#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
529#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
530#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
531#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
532#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
533#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
534#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
535#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
536#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
537#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
538
539#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
540#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
541#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
542#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
543#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
544#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
545#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
546#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
547#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
548#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
549#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
550#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
551#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
552#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
553#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
554#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
555#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
556#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
557#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
558#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
559#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
560#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
561#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
562#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
563#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
564#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
565
566#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
567#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
568#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
569#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
570#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
571#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
572#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
573#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
574#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
575#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
576#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
577#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
578#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
579#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
580#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
581#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
582#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
583#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
584#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
585#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
586#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
587#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
588#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
589#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
590#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
591#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
592
593#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
594#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
595#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
596#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
597#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
598#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
599#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
600#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
601#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
602#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
603#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
604#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
605#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
606#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
607#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
608#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
609#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
610#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
611#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
612#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
613#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
614#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
615#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
616#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
617#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
618#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
619
620#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
621#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
622#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
623#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
624#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
625#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
626#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
627#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
628#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
629#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
630#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
631#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
632#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
633#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
634#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
635#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
636#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
637#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
638#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
639#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
640#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
641#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
642#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
643#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
644#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
645#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
646
647#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
648#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
649#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
650#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
651#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
652#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
653#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
654#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
655#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
656#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
657#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
658#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
659#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
660#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
661#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
662#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
663#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
664#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
665#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
666#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
667#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
668#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
669#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
670#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
671#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
672#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
673
674#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
675#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
676#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
677#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
678#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
679#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
680#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
681#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
682#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
683#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
684#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
685#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
686#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
687#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
688#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
689#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
690#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
691#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
692#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
693#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
694#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
695#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
696#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
697#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
698#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
699#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
700
701#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
702#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
703#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
704#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
705#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
706#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
707#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
708#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
709#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
710#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
711#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
712#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
713#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
714#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
715#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
716#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
717#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
718#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
719#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
720#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
721#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
722#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
723#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
724#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
725#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
726#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
727
728#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
729#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
730#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
731#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
732#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
733#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
734#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
735#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
736#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
737#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
738#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
739#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
740#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
741#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
742#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
743#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
744#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
745#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
746#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
747#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
748#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
749#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
750#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
751#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
752#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
753#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
754
755#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
756#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
757#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
758#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
759#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
760#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
761#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
762#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
763#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
764#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
765#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
766#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
767#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
768#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
769#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
770#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
771#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
772#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
773#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
774#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
775#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
776#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
777#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
778#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
779#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
780#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
781
782#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
783#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
784#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
785#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
786#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
787#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
788#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
789#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
790#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
791#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
792#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
793#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
794#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
795#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
796#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
797#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
798#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
799#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
800#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
801#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
802#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
803#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
804#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
805#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
806#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
807#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
808
809
810/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
811#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
812#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
813#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
814#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
815#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF)
816#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
817#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
818#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
819#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
820#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
821#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
822
823
824/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
825
826/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
827#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
828#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val)
829#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
830#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val)
831#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
832#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val)
833#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
834#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
835#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
836#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val)
837#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
838#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
839#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
840#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
841#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
842#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
843#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
844#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val)
845#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
846#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
847#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
848#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
849#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
850#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
851#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
852#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val)
853#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
854#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val)
855#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
856#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val)
857#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
858#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val)
859#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
860#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val)
861
862
863/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
864#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
865#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val)
866#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
867#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val)
868#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
869#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val)
870#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
871#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
872#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
873#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val)
874#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
875#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
876#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
877#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
878#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
879#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
880#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
881#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val)
882#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
883#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
884#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
885#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
886#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
887#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
888#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
889#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val)
890#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
891#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val)
892#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
893#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val)
894#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
895#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val)
896#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
897#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val)
898
899
900/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
901#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
902#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
903#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
904#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
905#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
906#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
907#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
908#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
909#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
910#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
911#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
912#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
913#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
914#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
915#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
916#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
917#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
918#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
919#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
920#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
921#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
922#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
923#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
924#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
925
926/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF51x processor) */
927
928/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
929#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
930#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
931#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
932#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
933#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
934#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
935#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX)
936#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val)
937
938
939/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
940#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
941#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
942#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
943#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
944#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
945#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
946#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
947#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
948#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
949#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
950#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
951#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
952#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
953#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
954
955#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
956#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
957#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
958#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
959#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
960#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
961#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
962#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
963#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
964#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
965#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
966#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
967#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
968#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
969
970/* ==== end from cdefBF534.h ==== */
971
972/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
973
974#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX)
975#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val)
976#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX)
977#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val)
978#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX)
979#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val)
980
981#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE)
982#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val)
983#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE)
984#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val)
985#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE)
986#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val)
987#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW)
988#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val)
989#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW)
990#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val)
991#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW)
992#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val)
993#define bfin_read_PORTF_HYSTERISIS() bfin_read16(PORTF_HYSTERISIS)
994#define bfin_write_PORTF_HYSTERISIS(val) bfin_write16(PORTF_HYSTERISIS, val)
995#define bfin_read_PORTG_HYSTERISIS() bfin_read16(PORTG_HYSTERISIS)
996#define bfin_write_PORTG_HYSTERISIS(val) bfin_write16(PORTG_HYSTERISIS, val)
997#define bfin_read_PORTH_HYSTERISIS() bfin_read16(PORTH_HYSTERISIS)
998#define bfin_write_PORTH_HYSTERISIS(val) bfin_write16(PORTH_HYSTERISIS, val)
999#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE)
1000#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val)
1001#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW)
1002#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val)
1003#define bfin_read_MISCPORT_HYSTERISIS() bfin_read16(MISCPORT_HYSTERISIS)
1004#define bfin_write_MISCPORT_HYSTERISIS(val) bfin_write16(MISCPORT_HYSTERISIS, val)
1005
1006/* HOST Port Registers */
1007
1008#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
1009#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
1010#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
1011#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
1012#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
1013#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
1014
1015/* Counter Registers */
1016
1017#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
1018#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
1019#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
1020#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
1021#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
1022#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
1023#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
1024#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
1025#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
1026#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
1027#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
1028#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
1029#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
1030#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
1031#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
1032#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
1033
1034/* Security Registers */
1035
1036#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
1037#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
1038#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
1039#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
1040#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
1041#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
20 1042
21#endif /* _CDEF_BF512_H */ 1043#endif /* _CDEF_BF512_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
index 108fa4bde277..dc988668203e 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2008-2009 Analog Devices Inc. 2 * Copyright 2008-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
@@ -7,9 +7,6 @@
7#ifndef _CDEF_BF514_H 7#ifndef _CDEF_BF514_H
8#define _CDEF_BF514_H 8#define _CDEF_BF514_H
9 9
10/* include all Core registers and bit definitions */
11#include "defBF514.h"
12
13/* BF514 is BF512 + RSI */ 10/* BF514 is BF512 + RSI */
14#include "cdefBF512.h" 11#include "cdefBF512.h"
15 12
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
index 2751592ef1c1..142e45cbc253 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2008-2009 Analog Devices Inc. 2 * Copyright 2008-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
@@ -7,9 +7,6 @@
7#ifndef _CDEF_BF516_H 7#ifndef _CDEF_BF516_H
8#define _CDEF_BF516_H 8#define _CDEF_BF516_H
9 9
10/* include all Core registers and bit definitions */
11#include "defBF516.h"
12
13/* BF516 is BF514 + EMAC */ 10/* BF516 is BF514 + EMAC */
14#include "cdefBF514.h" 11#include "cdefBF514.h"
15 12
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
index 7fb7f0eab990..e638197bf8b1 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2008-2009 Analog Devices Inc. 2 * Copyright 2008-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
@@ -7,9 +7,6 @@
7#ifndef _CDEF_BF518_H 7#ifndef _CDEF_BF518_H
8#define _CDEF_BF518_H 8#define _CDEF_BF518_H
9 9
10/* include all Core registers and bit definitions */
11#include "defBF518.h"
12
13/* BF518 is BF516 + IEEE-1588 */ 10/* BF518 is BF516 + IEEE-1588 */
14#include "cdefBF516.h" 11#include "cdefBF516.h"
15 12
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
deleted file mode 100644
index e16969f24ffd..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
+++ /dev/null
@@ -1,1061 +0,0 @@
1/*
2 * Copyright 2008 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later
5 */
6
7#ifndef _CDEF_BF52X_H
8#define _CDEF_BF52X_H
9
10#include <asm/blackfin.h>
11
12#include "defBF51x_base.h"
13
14/* Include core specific register pointer definitions */
15#include <asm/cdef_LPBlackfin.h>
16
17/* ==== begin from cdefBF534.h ==== */
18
19/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
20#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
21#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
22#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
23#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
24#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
25#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
26#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
27#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
28#define bfin_read_CHIPID() bfin_read32(CHIPID)
29#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
30
31
32/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
33#define bfin_read_SWRST() bfin_read16(SWRST)
34#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
35#define bfin_read_SYSCR() bfin_read16(SYSCR)
36#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
37
38#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
39#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
40#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
41#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
42#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6))
43#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)
44
45#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
46#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
47#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
48#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
49#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
50#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
51#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
52#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
53
54#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
55#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
56#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6))
57#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
58
59#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
60#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
61#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6))
62#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)
63
64/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */
65
66#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
67#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
68#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
69#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
70#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
71#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
72#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
73#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
74#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
75#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
76#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
77#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
78#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
79#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
80
81/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
82#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
83#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
84#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
85#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
86#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
87#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
88
89
90/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
91#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
92#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
93#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
94#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
95#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
96#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
97#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
98#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
99#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
100#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
101#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
102#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val)
103#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
104#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
105
106
107/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
108#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
109#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
110#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
111#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
112#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
113#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
114#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
115#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
116#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
117#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
118#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
119#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
120#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
121#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
122#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
123#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
124#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
125#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
126#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
127#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
128#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
129#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
130#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
131#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
132
133
134/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
135#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
136#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
137#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
138#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
139#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
140#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
141#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
142#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
143
144#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
145#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
146#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
147#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
148#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
149#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
150#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
151#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
152
153#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
154#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
155#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
156#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
157#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
158#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
159#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
160#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
161
162#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
163#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
164#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
165#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
166#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
167#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
168#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
169#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
170
171#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
172#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
173#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
174#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
175#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
176#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
177#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
178#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
179
180#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
181#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
182#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
183#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
184#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
185#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
186#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
187#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
188
189#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
190#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
191#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
192#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
193#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
194#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
195#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
196#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
197
198#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
199#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
200#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
201#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
202#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
203#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
204#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
205#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
206
207#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
208#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
209#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
210#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
211#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
212#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val)
213
214
215/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
216#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
217#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
218#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
219#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
220#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
221#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
222#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
223#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
224#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
225#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
226#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
227#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
228#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
229#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
230#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
231#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
232#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
233#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
234#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
235#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
236#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
237#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
238#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
239#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
240#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
241#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
242#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
243#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
244#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
245#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
246#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
247#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
248#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
249#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
250
251
252/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
253#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
254#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
255#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
256#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
257#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
258#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
259#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
260#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
261#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
262#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
263#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
264#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
265#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
266#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX, val)
267#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
268#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX, val)
269#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
270#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX, val)
271#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
272#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX, val)
273#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
274#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
275#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
276#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
277#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
278#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
279#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
280#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
281#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
282#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
283#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
284#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
285#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
286#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
287#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
288#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
289#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
290#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
291#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
292#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
293#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
294#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
295#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
296#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
297#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
298#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
299#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
300#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
301#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
302#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
303#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
304#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
305
306
307/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
308#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
309#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
310#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
311#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
312#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
313#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
314#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
315#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
316#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
317#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
318#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
319#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
320#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
321#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX, val)
322#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
323#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX, val)
324#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
325#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX, val)
326#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
327#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX, val)
328#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
329#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
330#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
331#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
332#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
333#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
334#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
335#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
336#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
337#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
338#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
339#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
340#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
341#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
342#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
343#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
344#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
345#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
346#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
347#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
348#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
349#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
350#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
351#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
352#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
353#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
354#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
355#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
356#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
357#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
358#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
359#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
360
361
362/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
363#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
364#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
365#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
366#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
367#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
368#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
369#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
370#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
371#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
372#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
373#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
374#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
375#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
376#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
377
378
379/* DMA Traffic Control Registers */
380#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
381#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val)
382#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
383#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val)
384
385/* Alternate deprecated register names (below) provided for backwards code compatibility */
386#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
387#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER, val)
388#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
389#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT, val)
390
391/* DMA Controller */
392#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
393#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
394#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
395#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
396#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
397#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
398#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
399#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
400#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
401#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
402#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
403#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
404#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
405#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
406#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
407#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
408#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
409#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
410#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
411#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
412#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
413#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
414#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
415#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
416#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
417#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
418
419#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
420#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
421#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
422#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
423#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
424#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
425#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
426#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
427#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
428#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
429#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
430#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
431#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
432#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
433#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
434#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
435#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
436#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
437#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
438#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
439#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
440#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
441#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
442#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
443#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
444#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
445
446#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
447#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
448#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
449#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
450#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
451#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
452#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
453#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
454#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
455#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
456#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
457#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
458#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
459#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
460#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
461#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
462#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
463#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
464#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
465#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
466#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
467#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
468#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
469#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
470#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
471#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
472
473#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
474#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
475#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
476#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
477#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
478#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
479#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
480#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
481#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
482#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
483#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
484#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
485#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
486#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
487#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
488#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
489#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
490#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
491#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
492#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
493#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
494#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
495#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
496#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
497#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
498#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
499
500#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
501#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
502#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
503#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
504#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
505#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
506#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
507#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
508#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
509#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
510#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
511#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
512#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
513#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
514#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
515#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
516#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
517#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
518#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
519#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
520#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
521#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
522#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
523#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
524#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
525#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
526
527#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
528#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
529#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
530#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
531#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
532#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
533#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
534#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
535#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
536#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
537#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
538#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
539#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
540#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
541#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
542#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
543#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
544#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
545#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
546#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
547#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
548#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
549#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
550#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
551#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
552#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
553
554#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
555#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
556#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
557#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
558#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
559#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
560#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
561#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
562#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
563#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
564#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
565#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
566#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
567#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
568#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
569#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
570#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
571#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
572#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
573#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
574#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
575#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
576#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
577#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
578#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
579#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
580
581#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
582#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
583#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
584#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
585#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
586#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
587#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
588#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
589#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
590#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
591#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
592#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
593#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
594#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
595#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
596#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
597#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
598#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
599#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
600#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
601#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
602#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
603#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
604#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
605#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
606#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
607
608#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
609#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
610#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
611#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
612#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
613#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
614#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
615#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
616#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
617#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
618#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
619#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
620#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
621#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
622#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
623#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
624#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
625#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
626#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
627#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
628#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
629#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
630#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
631#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
632#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
633#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
634
635#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
636#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
637#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
638#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
639#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
640#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
641#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
642#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
643#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
644#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
645#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
646#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
647#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
648#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
649#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
650#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
651#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
652#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
653#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
654#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
655#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
656#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
657#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
658#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
659#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
660#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
661
662#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
663#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
664#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
665#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
666#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
667#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
668#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
669#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
670#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
671#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
672#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
673#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
674#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
675#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
676#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
677#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
678#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
679#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
680#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
681#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
682#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
683#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
684#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
685#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
686#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
687#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
688
689#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
690#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
691#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
692#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
693#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
694#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
695#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
696#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
697#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
698#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
699#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
700#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
701#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
702#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
703#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
704#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
705#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
706#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
707#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
708#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
709#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
710#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
711#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
712#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
713#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
714#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
715
716#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
717#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
718#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
719#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
720#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
721#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
722#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
723#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
724#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
725#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
726#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
727#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
728#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
729#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
730#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
731#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
732#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
733#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
734#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
735#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
736#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
737#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
738#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
739#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
740#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
741#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
742
743#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
744#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
745#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
746#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
747#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
748#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
749#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
750#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
751#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
752#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
753#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
754#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
755#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
756#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
757#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
758#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
759#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
760#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
761#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
762#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
763#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
764#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
765#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
766#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
767#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
768#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
769
770#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
771#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
772#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
773#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
774#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
775#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
776#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
777#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
778#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
779#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
780#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
781#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
782#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
783#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
784#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
785#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
786#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
787#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
788#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
789#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
790#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
791#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
792#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
793#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
794#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
795#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
796
797#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
798#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
799#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
800#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
801#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
802#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
803#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
804#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
805#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
806#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
807#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
808#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
809#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
810#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
811#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
812#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
813#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
814#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
815#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
816#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
817#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
818#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
819#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
820#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
821#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
822#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
823
824
825/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
826#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
827#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
828#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
829#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
830#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF)
831#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
832#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
833#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
834#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
835#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
836#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
837
838
839/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
840
841/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
842#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
843#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val)
844#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
845#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val)
846#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
847#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val)
848#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
849#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
850#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
851#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val)
852#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
853#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
854#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
855#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
856#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
857#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
858#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
859#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val)
860#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
861#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
862#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
863#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
864#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
865#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
866#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
867#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val)
868#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
869#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val)
870#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
871#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val)
872#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
873#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val)
874#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
875#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val)
876
877
878/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
879#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
880#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val)
881#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
882#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val)
883#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
884#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val)
885#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
886#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
887#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
888#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val)
889#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
890#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
891#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
892#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
893#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
894#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
895#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
896#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val)
897#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
898#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
899#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
900#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
901#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
902#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
903#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
904#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val)
905#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
906#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val)
907#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
908#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val)
909#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
910#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val)
911#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
912#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val)
913
914
915/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
916#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
917#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
918#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
919#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
920#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
921#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
922#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
923#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
924#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
925#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
926#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
927#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
928#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
929#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
930#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
931#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
932#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
933#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
934#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
935#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
936#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
937#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
938#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
939#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
940
941/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF51x processor) */
942
943/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
944#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
945#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
946#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
947#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
948#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
949#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
950#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX)
951#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val)
952
953
954/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
955#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
956#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
957#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
958#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
959#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
960#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
961#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
962#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
963#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
964#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
965#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
966#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
967#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
968#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
969
970#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
971#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
972#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
973#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
974#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
975#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
976#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
977#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
978#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
979#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
980#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
981#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
982#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
983#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
984
985/* ==== end from cdefBF534.h ==== */
986
987/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
988
989#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX)
990#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val)
991#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX)
992#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val)
993#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX)
994#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val)
995
996#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE)
997#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val)
998#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE)
999#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val)
1000#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE)
1001#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val)
1002#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW)
1003#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val)
1004#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW)
1005#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val)
1006#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW)
1007#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val)
1008#define bfin_read_PORTF_HYSTERISIS() bfin_read16(PORTF_HYSTERISIS)
1009#define bfin_write_PORTF_HYSTERISIS(val) bfin_write16(PORTF_HYSTERISIS, val)
1010#define bfin_read_PORTG_HYSTERISIS() bfin_read16(PORTG_HYSTERISIS)
1011#define bfin_write_PORTG_HYSTERISIS(val) bfin_write16(PORTG_HYSTERISIS, val)
1012#define bfin_read_PORTH_HYSTERISIS() bfin_read16(PORTH_HYSTERISIS)
1013#define bfin_write_PORTH_HYSTERISIS(val) bfin_write16(PORTH_HYSTERISIS, val)
1014#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE)
1015#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val)
1016#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW)
1017#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val)
1018#define bfin_read_MISCPORT_HYSTERISIS() bfin_read16(MISCPORT_HYSTERISIS)
1019#define bfin_write_MISCPORT_HYSTERISIS(val) bfin_write16(MISCPORT_HYSTERISIS, val)
1020
1021/* HOST Port Registers */
1022
1023#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
1024#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
1025#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
1026#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
1027#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
1028#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
1029
1030/* Counter Registers */
1031
1032#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
1033#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
1034#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
1035#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
1036#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
1037#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
1038#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
1039#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
1040#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
1041#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
1042#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
1043#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
1044#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
1045#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
1046#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
1047#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
1048
1049/* Security Registers */
1050
1051#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
1052#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
1053#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
1054#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
1055#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
1056#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
1057
1058/* These need to be last due to the cdef/linux inter-dependencies */
1059#include <asm/irq.h>
1060
1061#endif /* _CDEF_BF52X_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF512.h b/arch/blackfin/mach-bf518/include/mach/defBF512.h
index 9b505bb0cb2d..27285823fb25 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF512.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF512.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2008 Analog Devices Inc. 2 * Copyright 2008-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
@@ -7,12 +7,1388 @@
7#ifndef _DEF_BF512_H 7#ifndef _DEF_BF512_H
8#define _DEF_BF512_H 8#define _DEF_BF512_H
9 9
10/* Include all Core registers and bit definitions */ 10/* ************************************************************** */
11#include <asm/def_LPBlackfin.h> 11/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF51x */
12/* ************************************************************** */
12 13
13/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF512 */ 14/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
15#define PLL_CTL 0xFFC00000 /* PLL Control Register */
16#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
17#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
18#define PLL_STAT 0xFFC0000C /* PLL Status Register */
19#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
20#define CHIPID 0xFFC00014 /* Device ID Register */
14 21
15/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ 22/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
16#include "defBF51x_base.h" 23#define SWRST 0xFFC00100 /* Software Reset Register */
24#define SYSCR 0xFFC00104 /* System Configuration Register */
25#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
26
27#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
28#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
29#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
30#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
31#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
32#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
33#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
34
35/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */
36#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */
37#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */
38#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */
39#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */
40#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */
41#define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */
42#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */
43
44
45/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
46#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
47#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
48#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
49
50
51/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
52#define RTC_STAT 0xFFC00300 /* RTC Status Register */
53#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
54#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
55#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
56#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
57#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
58#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
59
60
61/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
62#define UART0_THR 0xFFC00400 /* Transmit Holding register */
63#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
64#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
65#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
66#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
67#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
68#define UART0_LCR 0xFFC0040C /* Line Control Register */
69#define UART0_MCR 0xFFC00410 /* Modem Control Register */
70#define UART0_LSR 0xFFC00414 /* Line Status Register */
71#define UART0_MSR 0xFFC00418 /* Modem Status Register */
72#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
73#define UART0_GCTL 0xFFC00424 /* Global Control Register */
74
75/* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */
76#define SPI0_REGBASE 0xFFC00500
77#define SPI0_CTL 0xFFC00500 /* SPI Control Register */
78#define SPI0_FLG 0xFFC00504 /* SPI Flag register */
79#define SPI0_STAT 0xFFC00508 /* SPI Status register */
80#define SPI0_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
81#define SPI0_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
82#define SPI0_BAUD 0xFFC00514 /* SPI Baud rate Register */
83#define SPI0_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
84
85/* SPI1 Controller (0xFFC03400 - 0xFFC034FF) */
86#define SPI1_REGBASE 0xFFC03400
87#define SPI1_CTL 0xFFC03400 /* SPI Control Register */
88#define SPI1_FLG 0xFFC03404 /* SPI Flag register */
89#define SPI1_STAT 0xFFC03408 /* SPI Status register */
90#define SPI1_TDBR 0xFFC0340C /* SPI Transmit Data Buffer Register */
91#define SPI1_RDBR 0xFFC03410 /* SPI Receive Data Buffer Register */
92#define SPI1_BAUD 0xFFC03414 /* SPI Baud rate Register */
93#define SPI1_SHADOW 0xFFC03418 /* SPI_RDBR Shadow Register */
94
95/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
96#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
97#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
98#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
99#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
100
101#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
102#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
103#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
104#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
105
106#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
107#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
108#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
109#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
110
111#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
112#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
113#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
114#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
115
116#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
117#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
118#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
119#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
120
121#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
122#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
123#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
124#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
125
126#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
127#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
128#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
129#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
130
131#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
132#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
133#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
134#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
135
136#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
137#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
138#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
139
140/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
141#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
142#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
143#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
144#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
145#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
146#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
147#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
148#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
149#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
150#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
151#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
152#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
153#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
154#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
155#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
156#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
157#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
158
159/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
160#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
161#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
162#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
163#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
164#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
165#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
166#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
167#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
168#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
169#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
170#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
171#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
172#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
173#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
174#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
175#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
176#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
177#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
178#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
179#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
180#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
181#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
182
183/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
184#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
185#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
186#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
187#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
188#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
189#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
190#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
191#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
192#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
193#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
194#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
195#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
196#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
197#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
198#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
199#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
200#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
201#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
202#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
203#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
204#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
205#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
206
207/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
208#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
209#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
210#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
211#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
212#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
213#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
214#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
215
216/* DMA Traffic Control Registers */
217#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
218#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
219
220/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
221#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
222#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
223#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
224#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
225#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
226#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
227#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
228#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
229#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
230#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
231#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
232#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
233#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
234
235#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
236#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
237#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
238#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
239#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
240#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
241#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
242#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
243#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
244#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
245#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
246#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
247#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
248
249#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
250#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
251#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
252#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
253#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
254#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
255#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
256#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
257#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
258#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
259#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
260#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
261#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
262
263#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
264#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
265#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
266#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
267#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
268#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
269#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
270#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
271#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
272#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
273#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
274#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
275#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
276
277#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
278#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
279#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
280#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
281#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
282#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
283#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
284#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
285#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
286#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
287#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
288#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
289#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
290
291#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
292#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
293#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
294#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
295#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
296#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
297#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
298#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
299#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
300#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
301#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
302#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
303#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
304
305#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
306#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
307#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
308#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
309#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
310#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
311#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
312#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
313#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
314#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
315#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
316#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
317#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
318
319#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
320#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
321#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
322#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
323#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
324#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
325#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
326#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
327#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
328#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
329#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
330#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
331#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
332
333#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
334#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
335#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
336#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
337#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
338#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
339#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
340#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
341#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
342#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
343#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
344#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
345#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
346
347#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
348#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
349#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
350#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
351#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
352#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
353#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
354#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
355#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
356#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
357#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
358#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
359#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
360
361#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
362#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
363#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
364#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
365#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
366#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
367#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
368#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
369#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
370#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
371#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
372#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
373#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
374
375#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
376#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
377#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
378#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
379#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
380#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
381#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
382#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
383#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
384#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
385#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
386#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
387#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
388
389#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
390#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
391#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
392#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
393#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
394#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
395#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
396#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
397#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
398#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
399#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
400#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
401#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
402
403#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
404#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
405#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
406#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
407#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
408#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
409#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
410#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
411#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
412#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
413#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
414#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
415#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
416
417#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
418#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
419#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
420#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
421#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
422#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
423#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
424#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
425#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
426#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
427#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
428#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
429#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
430
431#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
432#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
433#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
434#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
435#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
436#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
437#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
438#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
439#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
440#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
441#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
442#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
443#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
444
445
446/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
447#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
448#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
449#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
450#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
451#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
452
453
454/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
455#define TWI0_REGBASE 0xFFC01400
456#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
457#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */
458#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
459#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
460#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
461#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
462#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
463#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
464#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
465#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
466#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
467#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
468#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
469#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
470#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
471#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
472
473
474/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
475#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
476#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
477#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
478#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
479#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
480#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
481#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
482#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
483#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
484#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
485#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
486#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
487#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
488#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
489#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
490#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
491#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
492
493
494/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
495#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
496#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
497#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
498#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
499#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
500#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
501#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
502#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
503#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
504#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
505#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
506#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
507#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
508#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
509#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
510#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
511#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
512
513
514/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
515#define UART1_THR 0xFFC02000 /* Transmit Holding register */
516#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
517#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
518#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
519#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
520#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
521#define UART1_LCR 0xFFC0200C /* Line Control Register */
522#define UART1_MCR 0xFFC02010 /* Modem Control Register */
523#define UART1_LSR 0xFFC02014 /* Line Status Register */
524#define UART1_MSR 0xFFC02018 /* Modem Status Register */
525#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
526#define UART1_GCTL 0xFFC02024 /* Global Control Register */
527
528
529/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
530#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
531#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
532#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
533#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
534
535
536/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
537#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
538#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
539#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
540#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */
541#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
542#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
543#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
544
545#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
546#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
547#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
548#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */
549#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
550#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
551#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
552
553
554/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
555#define PORTF_MUX 0xFFC03210 /* Port F mux control */
556#define PORTG_MUX 0xFFC03214 /* Port G mux control */
557#define PORTH_MUX 0xFFC03218 /* Port H mux control */
558#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */
559#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */
560#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */
561#define PORTF_SLEW 0xFFC03230 /* Port F slew control */
562#define PORTG_SLEW 0xFFC03234 /* Port G slew control */
563#define PORTH_SLEW 0xFFC03238 /* Port H slew control */
564#define PORTF_HYSTERISIS 0xFFC03240 /* Port F Schmitt trigger control */
565#define PORTG_HYSTERISIS 0xFFC03244 /* Port G Schmitt trigger control */
566#define PORTH_HYSTERISIS 0xFFC03248 /* Port H Schmitt trigger control */
567#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */
568#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */
569#define MISCPORT_HYSTERISIS 0xFFC03288 /* Misc Port Schmitt trigger control */
570
571
572/***********************************************************************************
573** System MMR Register Bits And Macros
574**
575** Disclaimer: All macros are intended to make C and Assembly code more readable.
576** Use these macros carefully, as any that do left shifts for field
577** depositing will result in the lower order bits being destroyed. Any
578** macro that shifts left to properly position the bit-field should be
579** used as part of an OR to initialize a register and NOT as a dynamic
580** modifier UNLESS the lower order bits are saved and ORed back in when
581** the macro is used.
582*************************************************************************************/
583
584/* CHIPID Masks */
585#define CHIPID_VERSION 0xF0000000
586#define CHIPID_FAMILY 0x0FFFF000
587#define CHIPID_MANUFACTURE 0x00000FFE
588
589/* SWRST Masks */
590#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
591#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
592#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
593#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
594#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
595
596/* SYSCR Masks */
597#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
598#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
599
600
601/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
602/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
603
604#if 0
605#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */
606
607#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
608#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
609#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */
610#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */
611#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */
612#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */
613#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */
614
615#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */
616#define IRQ_TWI 0x00000200 /* TWI Interrupt */
617#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */
618#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */
619#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */
620#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */
621#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */
622#define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */
623
624#define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */
625#define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */
626#define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */
627#define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */
628#define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */
629#define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */
630#define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */
631#define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */
632#define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */
633#define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */
634
635#define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */
636#define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */
637#define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */
638#define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */
639#define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */
640#define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */
641#define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
642#define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */
643#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
644#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */
645#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */
646#endif
647
648/* SIC_IAR0 Macros */
649#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
650#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
651#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
652#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
653#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
654#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
655#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
656#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
657
658/* SIC_IAR1 Macros */
659#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
660#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
661#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
662#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
663#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
664#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
665#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
666#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
667
668/* SIC_IAR2 Macros */
669#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
670#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
671#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
672#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
673#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
674#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
675#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
676#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
677
678/* SIC_IAR3 Macros */
679#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
680#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
681#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
682#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
683#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
684#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
685#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
686#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
687
688
689/* SIC_IMASK Masks */
690#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
691#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
692#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
693#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
694
695/* SIC_IWR Masks */
696#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
697#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
698#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
699#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
700
701/* **************** GENERAL PURPOSE TIMER MASKS **********************/
702/* TIMER_ENABLE Masks */
703#define TIMEN0 0x0001 /* Enable Timer 0 */
704#define TIMEN1 0x0002 /* Enable Timer 1 */
705#define TIMEN2 0x0004 /* Enable Timer 2 */
706#define TIMEN3 0x0008 /* Enable Timer 3 */
707#define TIMEN4 0x0010 /* Enable Timer 4 */
708#define TIMEN5 0x0020 /* Enable Timer 5 */
709#define TIMEN6 0x0040 /* Enable Timer 6 */
710#define TIMEN7 0x0080 /* Enable Timer 7 */
711
712/* TIMER_DISABLE Masks */
713#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
714#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
715#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
716#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
717#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
718#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
719#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
720#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
721
722/* TIMER_STATUS Masks */
723#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
724#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
725#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
726#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
727#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
728#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
729#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
730#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
731#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
732#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
733#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
734#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
735#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
736#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
737#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
738#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
739#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
740#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
741#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
742#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
743#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
744#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
745#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
746#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
747
748/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
749#define TOVL_ERR0 TOVF_ERR0
750#define TOVL_ERR1 TOVF_ERR1
751#define TOVL_ERR2 TOVF_ERR2
752#define TOVL_ERR3 TOVF_ERR3
753#define TOVL_ERR4 TOVF_ERR4
754#define TOVL_ERR5 TOVF_ERR5
755#define TOVL_ERR6 TOVF_ERR6
756#define TOVL_ERR7 TOVF_ERR7
757
758/* TIMERx_CONFIG Masks */
759#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
760#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
761#define EXT_CLK 0x0003 /* External Clock Mode */
762#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
763#define PERIOD_CNT 0x0008 /* Period Count */
764#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
765#define TIN_SEL 0x0020 /* Timer Input Select */
766#define OUT_DIS 0x0040 /* Output Pad Disable */
767#define CLK_SEL 0x0080 /* Timer Clock Select */
768#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
769#define EMU_RUN 0x0200 /* Emulation Behavior Select */
770#define ERR_TYP 0xC000 /* Error Type */
771
772/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
773/* EBIU_AMGCTL Masks */
774#define AMCKEN 0x0001 /* Enable CLKOUT */
775#define AMBEN_NONE 0x0000 /* All Banks Disabled */
776#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
777#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
778#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
779#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
780
781/* EBIU_AMBCTL0 Masks */
782#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
783#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
784#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
785#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
786#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
787#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
788#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
789#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
790#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
791#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
792#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
793#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
794#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
795#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
796#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
797#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
798#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
799#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
800#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
801#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
802#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
803#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
804#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
805#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
806#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
807#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
808#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
809#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
810#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
811#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
812#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
813#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
814#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
815#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
816#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
817#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
818#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
819#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
820#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
821#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
822#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
823#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
824#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
825#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
826
827#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
828#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
829#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
830#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
831#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
832#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
833#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
834#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
835#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
836#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
837#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
838#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
839#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
840#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
841#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
842#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
843#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
844#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
845#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
846#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
847#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
848#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
849#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
850#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
851#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
852#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
853#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
854#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
855#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
856#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
857#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
858#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
859#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
860#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
861#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
862#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
863#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
864#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
865#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
866#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
867#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
868#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
869#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
870#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
871
872/* EBIU_AMBCTL1 Masks */
873#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
874#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
875#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
876#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
877#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
878#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
879#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
880#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
881#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
882#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
883#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
884#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
885#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
886#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
887#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
888#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
889#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
890#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
891#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
892#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
893#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
894#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
895#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
896#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
897#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
898#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
899#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
900#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
901#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
902#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
903#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
904#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
905#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
906#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
907#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
908#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
909#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
910#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
911#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
912#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
913#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
914#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
915#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
916#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
917
918#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
919#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
920#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
921#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
922#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
923#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
924#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
925#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
926#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
927#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
928#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
929#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
930#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
931#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
932#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
933#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
934#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
935#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
936#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
937#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
938#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
939#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
940#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
941#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
942#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
943#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
944#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
945#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
946#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
947#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
948#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
949#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
950#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
951#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
952#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
953#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
954#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
955#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
956#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
957#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
958#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
959#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
960#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
961#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
962
963
964/* ********************** SDRAM CONTROLLER MASKS **********************************************/
965/* EBIU_SDGCTL Masks */
966#define SCTLE 0x00000001 /* Enable SDRAM Signals */
967#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
968#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
969#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
970#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
971#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
972#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
973#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
974#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
975#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
976#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
977#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
978#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
979#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
980#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
981#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
982#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
983#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
984#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
985#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
986#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
987#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
988#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
989#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
990#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
991#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
992#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
993#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
994#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
995#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
996#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
997#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
998#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
999#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
1000#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
1001#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
1002#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
1003#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
1004#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
1005#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
1006#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
1007#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
1008#define EBUFE 0x02000000 /* Enable External Buffering Timing */
1009#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
1010#define EMREN 0x10000000 /* Extended Mode Register Enable */
1011#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
1012#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
1013
1014/* EBIU_SDBCTL Masks */
1015#define EBE 0x0001 /* Enable SDRAM External Bank */
1016#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
1017#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
1018#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
1019#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
1020#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
1021#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
1022#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
1023#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
1024#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
1025#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
1026
1027/* EBIU_SDSTAT Masks */
1028#define SDCI 0x0001 /* SDRAM Controller Idle */
1029#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
1030#define SDPUA 0x0004 /* SDRAM Power-Up Active */
1031#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
1032#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
1033#define BGSTAT 0x0020 /* Bus Grant Status */
1034
1035
1036/* ************************** DMA CONTROLLER MASKS ********************************/
1037
1038/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
1039#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
1040#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
1041#define PMAP_PPI 0x0000 /* PPI Port DMA */
1042#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
1043#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
1044#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
1045#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
1046#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
1047#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
1048#define PMAP_SPI 0x7000 /* SPI Port DMA */
1049#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
1050#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
1051#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
1052#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
1053
1054/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
1055/* PPI_CONTROL Masks */
1056#define PORT_EN 0x0001 /* PPI Port Enable */
1057#define PORT_DIR 0x0002 /* PPI Port Direction */
1058#define XFR_TYPE 0x000C /* PPI Transfer Type */
1059#define PORT_CFG 0x0030 /* PPI Port Configuration */
1060#define FLD_SEL 0x0040 /* PPI Active Field Select */
1061#define PACK_EN 0x0080 /* PPI Packing Mode */
1062#define DMA32 0x0100 /* PPI 32-bit DMA Enable */
1063#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
1064#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
1065#define DLEN_8 0x0000 /* Data Length = 8 Bits */
1066#define DLEN_10 0x0800 /* Data Length = 10 Bits */
1067#define DLEN_11 0x1000 /* Data Length = 11 Bits */
1068#define DLEN_12 0x1800 /* Data Length = 12 Bits */
1069#define DLEN_13 0x2000 /* Data Length = 13 Bits */
1070#define DLEN_14 0x2800 /* Data Length = 14 Bits */
1071#define DLEN_15 0x3000 /* Data Length = 15 Bits */
1072#define DLEN_16 0x3800 /* Data Length = 16 Bits */
1073#define DLENGTH 0x3800 /* PPI Data Length */
1074#define POLC 0x4000 /* PPI Clock Polarity */
1075#define POLS 0x8000 /* PPI Frame Sync Polarity */
1076
1077/* PPI_STATUS Masks */
1078#define FLD 0x0400 /* Field Indicator */
1079#define FT_ERR 0x0800 /* Frame Track Error */
1080#define OVR 0x1000 /* FIFO Overflow Error */
1081#define UNDR 0x2000 /* FIFO Underrun Error */
1082#define ERR_DET 0x4000 /* Error Detected Indicator */
1083#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
1084
1085
1086/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
1087/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
1088#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
1089#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
1090
1091/* TWI_PRESCALE Masks */
1092#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
1093#define TWI_ENA 0x0080 /* TWI Enable */
1094#define SCCB 0x0200 /* SCCB Compatibility Enable */
1095
1096/* TWI_SLAVE_CTL Masks */
1097#define SEN 0x0001 /* Slave Enable */
1098#define SADD_LEN 0x0002 /* Slave Address Length */
1099#define STDVAL 0x0004 /* Slave Transmit Data Valid */
1100#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
1101#define GEN 0x0010 /* General Call Adrress Matching Enabled */
1102
1103/* TWI_SLAVE_STAT Masks */
1104#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
1105#define GCALL 0x0002 /* General Call Indicator */
1106
1107/* TWI_MASTER_CTL Masks */
1108#define MEN 0x0001 /* Master Mode Enable */
1109#define MADD_LEN 0x0002 /* Master Address Length */
1110#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
1111#define FAST 0x0008 /* Use Fast Mode Timing Specs */
1112#define STOP 0x0010 /* Issue Stop Condition */
1113#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
1114#define DCNT 0x3FC0 /* Data Bytes To Transfer */
1115#define SDAOVR 0x4000 /* Serial Data Override */
1116#define SCLOVR 0x8000 /* Serial Clock Override */
1117
1118/* TWI_MASTER_STAT Masks */
1119#define MPROG 0x0001 /* Master Transfer In Progress */
1120#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
1121#define ANAK 0x0004 /* Address Not Acknowledged */
1122#define DNAK 0x0008 /* Data Not Acknowledged */
1123#define BUFRDERR 0x0010 /* Buffer Read Error */
1124#define BUFWRERR 0x0020 /* Buffer Write Error */
1125#define SDASEN 0x0040 /* Serial Data Sense */
1126#define SCLSEN 0x0080 /* Serial Clock Sense */
1127#define BUSBUSY 0x0100 /* Bus Busy Indicator */
1128
1129/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
1130#define SINIT 0x0001 /* Slave Transfer Initiated */
1131#define SCOMP 0x0002 /* Slave Transfer Complete */
1132#define SERR 0x0004 /* Slave Transfer Error */
1133#define SOVF 0x0008 /* Slave Overflow */
1134#define MCOMP 0x0010 /* Master Transfer Complete */
1135#define MERR 0x0020 /* Master Transfer Error */
1136#define XMTSERV 0x0040 /* Transmit FIFO Service */
1137#define RCVSERV 0x0080 /* Receive FIFO Service */
1138
1139/* TWI_FIFO_CTRL Masks */
1140#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
1141#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
1142#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
1143#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
1144
1145/* TWI_FIFO_STAT Masks */
1146#define XMTSTAT 0x0003 /* Transmit FIFO Status */
1147#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
1148#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
1149#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
1150
1151#define RCVSTAT 0x000C /* Receive FIFO Status */
1152#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
1153#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
1154#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
1155
1156
1157/* ******************* PIN CONTROL REGISTER MASKS ************************/
1158/* PORT_MUX Masks */
1159#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
1160#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
1161#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
1162
1163#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
1164#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
1165#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
1166#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
1167
1168#define PFDE 0x0008 /* Port F DMA Request Enable */
1169#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
1170#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
1171
1172#define PFTE 0x0010 /* Port F Timer Enable */
1173#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
1174#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
1175
1176#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
1177#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
1178#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
1179
1180#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
1181#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
1182#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
1183
1184#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
1185#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
1186#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
1187
1188#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
1189#define PFFE_TIMER 0x0000 /* Enable TMR2 */
1190#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
1191
1192#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
1193#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
1194#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
1195
1196#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
1197#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
1198#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
1199
1200#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
1201#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
1202#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
1203
1204
1205/* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/
1206/* HDMAx_CTL Masks */
1207#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */
1208#define REP 0x0002 /* HDMA Request Polarity */
1209#define UTE 0x0004 /* Urgency Threshold Enable */
1210#define OIE 0x0010 /* Overflow Interrupt Enable */
1211#define BDIE 0x0020 /* Block Done Interrupt Enable */
1212#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */
1213#define DRQ 0x0300 /* HDMA Request Type */
1214#define DRQ_NONE 0x0000 /* No Request */
1215#define DRQ_SINGLE 0x0100 /* Channels Request Single */
1216#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */
1217#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */
1218#define RBC 0x1000 /* Reload BCNT With IBCNT */
1219#define PS 0x2000 /* HDMA Pin Status */
1220#define OI 0x4000 /* Overflow Interrupt Generated */
1221#define BDI 0x8000 /* Block Done Interrupt Generated */
1222
1223/* entry addresses of the user-callable Boot ROM functions */
1224
1225#define _BOOTROM_RESET 0xEF000000
1226#define _BOOTROM_FINAL_INIT 0xEF000002
1227#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
1228#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
1229#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
1230#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
1231#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
1232#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
1233#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
1234
1235/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
1236#define PGDE_UART PFDE_UART
1237#define PGDE_DMA PFDE_DMA
1238#define CKELOW SCKELOW
1239
1240/* HOST Port Registers */
1241
1242#define HOST_CONTROL 0xffc03400 /* HOST Control Register */
1243#define HOST_STATUS 0xffc03404 /* HOST Status Register */
1244#define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */
1245
1246/* Counter Registers */
1247
1248#define CNT_CONFIG 0xffc03500 /* Configuration Register */
1249#define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */
1250#define CNT_STATUS 0xffc03508 /* Status Register */
1251#define CNT_COMMAND 0xffc0350c /* Command Register */
1252#define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */
1253#define CNT_COUNTER 0xffc03514 /* Counter Register */
1254#define CNT_MAX 0xffc03518 /* Maximal Count Register */
1255#define CNT_MIN 0xffc0351c /* Minimal Count Register */
1256
1257/* OTP/FUSE Registers */
1258
1259#define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */
1260#define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */
1261#define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */
1262#define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */
1263
1264/* Security Registers */
1265
1266#define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */
1267#define SECURE_CONTROL 0xffc03624 /* Secure Control */
1268#define SECURE_STATUS 0xffc03628 /* Secure Status */
1269
1270/* OTP Read/Write Data Buffer Registers */
1271
1272#define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1273#define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1274#define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1275#define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1276
1277/* Motor Control PWM Registers */
1278
1279#define PWM_CTRL 0xffc03700 /* PWM Control Register */
1280#define PWM_STAT 0xffc03704 /* PWM Status Register */
1281#define PWM_TM 0xffc03708 /* PWM Period Register */
1282#define PWM_DT 0xffc0370c /* PWM Dead Time Register */
1283#define PWM_GATE 0xffc03710 /* PWM Chopping Control */
1284#define PWM_CHA 0xffc03714 /* PWM Channel A Duty Control */
1285#define PWM_CHB 0xffc03718 /* PWM Channel B Duty Control */
1286#define PWM_CHC 0xffc0371c /* PWM Channel C Duty Control */
1287#define PWM_SEG 0xffc03720 /* PWM Crossover and Output Enable */
1288#define PWM_SYNCWT 0xffc03724 /* PWM Sync Pluse Width Control */
1289#define PWM_CHAL 0xffc03728 /* PWM Channel AL Duty Control (SR mode only) */
1290#define PWM_CHBL 0xffc0372c /* PWM Channel BL Duty Control (SR mode only) */
1291#define PWM_CHCL 0xffc03730 /* PWM Channel CL Duty Control (SR mode only) */
1292#define PWM_LSI 0xffc03734 /* PWM Low Side Invert (SR mode only) */
1293#define PWM_STAT2 0xffc03738 /* PWM Status Register 2 */
1294
1295
1296/* ********************************************************** */
1297/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
1298/* and MULTI BIT READ MACROS */
1299/* ********************************************************** */
1300
1301/* Bit masks for HOST_CONTROL */
1302
1303#define HOST_CNTR_HOST_EN 0x1 /* Host Enable */
1304#define HOST_CNTR_nHOST_EN 0x0
1305#define HOST_CNTR_HOST_END 0x2 /* Host Endianess */
1306#define HOST_CNTR_nHOST_END 0x0
1307#define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */
1308#define HOST_CNTR_nDATA_SIZE 0x0
1309#define HOST_CNTR_HOST_RST 0x8 /* Host Reset */
1310#define HOST_CNTR_nHOST_RST 0x0
1311#define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */
1312#define HOST_CNTR_nHRDY_OVR 0x0
1313#define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */
1314#define HOST_CNTR_nINT_MODE 0x0
1315#define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */
1316#define HOST_CNTR_ nBT_EN 0x0
1317#define HOST_CNTR_EHW 0x100 /* Enable Host Write */
1318#define HOST_CNTR_nEHW 0x0
1319#define HOST_CNTR_EHR 0x200 /* Enable Host Read */
1320#define HOST_CNTR_nEHR 0x0
1321#define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */
1322#define HOST_CNTR_nBDR 0x0
1323
1324/* Bit masks for HOST_STATUS */
1325
1326#define HOST_STAT_READY 0x1 /* DMA Ready */
1327#define HOST_STAT_nREADY 0x0
1328#define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */
1329#define HOST_STAT_nFIFOFULL 0x0
1330#define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */
1331#define HOST_STAT_nFIFOEMPTY 0x0
1332#define HOST_STAT_COMPLETE 0x8 /* DMA Complete */
1333#define HOST_STAT_nCOMPLETE 0x0
1334#define HOST_STAT_HSHK 0x10 /* Host Handshake */
1335#define HOST_STAT_nHSHK 0x0
1336#define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */
1337#define HOST_STAT_nTIMEOUT 0x0
1338#define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */
1339#define HOST_STAT_nHIRQ 0x0
1340#define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */
1341#define HOST_STAT_nALLOW_CNFG 0x0
1342#define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */
1343#define HOST_STAT_nDMA_DIR 0x0
1344#define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */
1345#define HOST_STAT_nBTE 0x0
1346#define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */
1347#define HOST_STAT_nHOSTRD_DONE 0x0
1348
1349/* Bit masks for HOST_TIMEOUT */
1350
1351#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */
1352
1353/* Bit masks for SECURE_SYSSWT */
1354
1355#define EMUDABL 0x1 /* Emulation Disable. */
1356#define nEMUDABL 0x0
1357#define RSTDABL 0x2 /* Reset Disable */
1358#define nRSTDABL 0x0
1359#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
1360#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
1361#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
1362#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
1363#define nDMA0OVR 0x0
1364#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
1365#define nDMA1OVR 0x0
1366#define EMUOVR 0x4000 /* Emulation Override */
1367#define nEMUOVR 0x0
1368#define OTPSEN 0x8000 /* OTP Secrets Enable. */
1369#define nOTPSEN 0x0
1370#define L2DABL 0x70000 /* L2 Memory Disable. */
1371
1372/* Bit masks for SECURE_CONTROL */
1373
1374#define SECURE0 0x1 /* SECURE 0 */
1375#define nSECURE0 0x0
1376#define SECURE1 0x2 /* SECURE 1 */
1377#define nSECURE1 0x0
1378#define SECURE2 0x4 /* SECURE 2 */
1379#define nSECURE2 0x0
1380#define SECURE3 0x8 /* SECURE 3 */
1381#define nSECURE3 0x0
1382
1383/* Bit masks for SECURE_STATUS */
1384
1385#define SECMODE 0x3 /* Secured Mode Control State */
1386#define NMI 0x4 /* Non Maskable Interrupt */
1387#define nNMI 0x0
1388#define AFVALID 0x8 /* Authentication Firmware Valid */
1389#define nAFVALID 0x0
1390#define AFEXIT 0x10 /* Authentication Firmware Exit */
1391#define nAFEXIT 0x0
1392#define SECSTAT 0xe0 /* Secure Status */
17 1393
18#endif /* _DEF_BF512_H */ 1394#endif /* _DEF_BF512_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
deleted file mode 100644
index 5f84913dcd91..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
+++ /dev/null
@@ -1,1495 +0,0 @@
1/*
2 * Copyright 2008 Analog Devices Inc.
3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */
6
7#ifndef _DEF_BF51X_H
8#define _DEF_BF51X_H
9
10
11/* ************************************************************** */
12/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF51x */
13/* ************************************************************** */
14
15/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
16#define PLL_CTL 0xFFC00000 /* PLL Control Register */
17#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
18#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
19#define PLL_STAT 0xFFC0000C /* PLL Status Register */
20#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
21#define CHIPID 0xFFC00014 /* Device ID Register */
22
23/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
24#define SWRST 0xFFC00100 /* Software Reset Register */
25#define SYSCR 0xFFC00104 /* System Configuration Register */
26#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
27
28#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
29#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
30#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
31#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
32#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
33#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
34#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
35
36/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */
37#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */
38#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */
39#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */
40#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */
41#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */
42#define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */
43#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */
44
45
46/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
47#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
48#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
49#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
50
51
52/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
53#define RTC_STAT 0xFFC00300 /* RTC Status Register */
54#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
55#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
56#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
57#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
58#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
59#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
60
61
62/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
63#define UART0_THR 0xFFC00400 /* Transmit Holding register */
64#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
65#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
66#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
67#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
68#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
69#define UART0_LCR 0xFFC0040C /* Line Control Register */
70#define UART0_MCR 0xFFC00410 /* Modem Control Register */
71#define UART0_LSR 0xFFC00414 /* Line Status Register */
72#define UART0_MSR 0xFFC00418 /* Modem Status Register */
73#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
74#define UART0_GCTL 0xFFC00424 /* Global Control Register */
75
76/* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */
77#define SPI0_REGBASE 0xFFC00500
78#define SPI0_CTL 0xFFC00500 /* SPI Control Register */
79#define SPI0_FLG 0xFFC00504 /* SPI Flag register */
80#define SPI0_STAT 0xFFC00508 /* SPI Status register */
81#define SPI0_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
82#define SPI0_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
83#define SPI0_BAUD 0xFFC00514 /* SPI Baud rate Register */
84#define SPI0_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
85
86/* SPI1 Controller (0xFFC03400 - 0xFFC034FF) */
87#define SPI1_REGBASE 0xFFC03400
88#define SPI1_CTL 0xFFC03400 /* SPI Control Register */
89#define SPI1_FLG 0xFFC03404 /* SPI Flag register */
90#define SPI1_STAT 0xFFC03408 /* SPI Status register */
91#define SPI1_TDBR 0xFFC0340C /* SPI Transmit Data Buffer Register */
92#define SPI1_RDBR 0xFFC03410 /* SPI Receive Data Buffer Register */
93#define SPI1_BAUD 0xFFC03414 /* SPI Baud rate Register */
94#define SPI1_SHADOW 0xFFC03418 /* SPI_RDBR Shadow Register */
95
96/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
97#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
98#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
99#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
100#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
101
102#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
103#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
104#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
105#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
106
107#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
108#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
109#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
110#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
111
112#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
113#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
114#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
115#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
116
117#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
118#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
119#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
120#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
121
122#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
123#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
124#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
125#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
126
127#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
128#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
129#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
130#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
131
132#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
133#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
134#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
135#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
136
137#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
138#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
139#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
140
141/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
142#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
143#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
144#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
145#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
146#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
147#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
148#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
149#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
150#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
151#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
152#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
153#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
154#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
155#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
156#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
157#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
158#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
159
160/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
161#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
162#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
163#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
164#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
165#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
166#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
167#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
168#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
169#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
170#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
171#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
172#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
173#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
174#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
175#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
176#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
177#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
178#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
179#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
180#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
181#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
182#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
183
184/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
185#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
186#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
187#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
188#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
189#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
190#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
191#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
192#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
193#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
194#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
195#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
196#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
197#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
198#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
199#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
200#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
201#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
202#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
203#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
204#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
205#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
206#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
207
208/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
209#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
210#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
211#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
212#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
213#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
214#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
215#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
216
217/* DMA Traffic Control Registers */
218#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
219#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
220
221/* Alternate deprecated register names (below) provided for backwards code compatibility */
222#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
223#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
224
225/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
226#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
227#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
228#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
229#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
230#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
231#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
232#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
233#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
234#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
235#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
236#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
237#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
238#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
239
240#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
241#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
242#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
243#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
244#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
245#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
246#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
247#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
248#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
249#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
250#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
251#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
252#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
253
254#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
255#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
256#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
257#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
258#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
259#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
260#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
261#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
262#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
263#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
264#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
265#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
266#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
267
268#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
269#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
270#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
271#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
272#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
273#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
274#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
275#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
276#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
277#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
278#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
279#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
280#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
281
282#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
283#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
284#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
285#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
286#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
287#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
288#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
289#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
290#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
291#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
292#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
293#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
294#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
295
296#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
297#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
298#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
299#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
300#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
301#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
302#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
303#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
304#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
305#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
306#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
307#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
308#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
309
310#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
311#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
312#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
313#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
314#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
315#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
316#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
317#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
318#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
319#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
320#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
321#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
322#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
323
324#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
325#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
326#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
327#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
328#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
329#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
330#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
331#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
332#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
333#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
334#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
335#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
336#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
337
338#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
339#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
340#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
341#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
342#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
343#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
344#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
345#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
346#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
347#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
348#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
349#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
350#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
351
352#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
353#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
354#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
355#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
356#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
357#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
358#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
359#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
360#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
361#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
362#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
363#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
364#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
365
366#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
367#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
368#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
369#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
370#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
371#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
372#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
373#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
374#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
375#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
376#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
377#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
378#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
379
380#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
381#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
382#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
383#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
384#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
385#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
386#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
387#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
388#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
389#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
390#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
391#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
392#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
393
394#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
395#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
396#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
397#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
398#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
399#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
400#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
401#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
402#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
403#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
404#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
405#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
406#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
407
408#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
409#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
410#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
411#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
412#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
413#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
414#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
415#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
416#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
417#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
418#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
419#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
420#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
421
422#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
423#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
424#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
425#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
426#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
427#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
428#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
429#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
430#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
431#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
432#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
433#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
434#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
435
436#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
437#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
438#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
439#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
440#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
441#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
442#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
443#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
444#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
445#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
446#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
447#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
448#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
449
450
451/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
452#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
453#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
454#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
455#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
456#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
457
458
459/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
460#define TWI0_REGBASE 0xFFC01400
461#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
462#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */
463#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
464#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
465#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
466#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
467#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
468#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
469#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
470#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
471#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
472#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
473#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
474#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
475#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
476#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
477
478
479/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
480#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
481#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
482#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
483#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
484#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
485#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
486#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
487#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
488#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
489#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
490#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
491#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
492#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
493#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
494#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
495#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
496#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
497
498
499/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
500#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
501#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
502#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
503#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
504#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
505#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
506#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
507#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
508#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
509#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
510#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
511#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
512#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
513#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
514#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
515#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
516#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
517
518
519/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
520#define UART1_THR 0xFFC02000 /* Transmit Holding register */
521#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
522#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
523#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
524#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
525#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
526#define UART1_LCR 0xFFC0200C /* Line Control Register */
527#define UART1_MCR 0xFFC02010 /* Modem Control Register */
528#define UART1_LSR 0xFFC02014 /* Line Status Register */
529#define UART1_MSR 0xFFC02018 /* Modem Status Register */
530#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
531#define UART1_GCTL 0xFFC02024 /* Global Control Register */
532
533
534/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
535#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
536#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
537#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
538#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
539
540
541/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
542#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
543#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
544#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
545#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */
546#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
547#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
548#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
549
550#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
551#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
552#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
553#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */
554#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
555#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
556#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
557
558
559/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
560#define PORTF_MUX 0xFFC03210 /* Port F mux control */
561#define PORTG_MUX 0xFFC03214 /* Port G mux control */
562#define PORTH_MUX 0xFFC03218 /* Port H mux control */
563#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */
564#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */
565#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */
566#define PORTF_SLEW 0xFFC03230 /* Port F slew control */
567#define PORTG_SLEW 0xFFC03234 /* Port G slew control */
568#define PORTH_SLEW 0xFFC03238 /* Port H slew control */
569#define PORTF_HYSTERISIS 0xFFC03240 /* Port F Schmitt trigger control */
570#define PORTG_HYSTERISIS 0xFFC03244 /* Port G Schmitt trigger control */
571#define PORTH_HYSTERISIS 0xFFC03248 /* Port H Schmitt trigger control */
572#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */
573#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */
574#define MISCPORT_HYSTERISIS 0xFFC03288 /* Misc Port Schmitt trigger control */
575
576
577/***********************************************************************************
578** System MMR Register Bits And Macros
579**
580** Disclaimer: All macros are intended to make C and Assembly code more readable.
581** Use these macros carefully, as any that do left shifts for field
582** depositing will result in the lower order bits being destroyed. Any
583** macro that shifts left to properly position the bit-field should be
584** used as part of an OR to initialize a register and NOT as a dynamic
585** modifier UNLESS the lower order bits are saved and ORed back in when
586** the macro is used.
587*************************************************************************************/
588
589/* CHIPID Masks */
590#define CHIPID_VERSION 0xF0000000
591#define CHIPID_FAMILY 0x0FFFF000
592#define CHIPID_MANUFACTURE 0x00000FFE
593
594/* SWRST Masks */
595#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
596#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
597#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
598#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
599#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
600
601/* SYSCR Masks */
602#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
603#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
604
605
606/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
607/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
608
609#if 0
610#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */
611
612#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
613#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
614#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */
615#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */
616#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */
617#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */
618#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */
619
620#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */
621#define IRQ_TWI 0x00000200 /* TWI Interrupt */
622#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */
623#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */
624#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */
625#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */
626#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */
627#define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */
628
629#define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */
630#define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */
631#define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */
632#define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */
633#define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */
634#define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */
635#define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */
636#define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */
637#define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */
638#define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */
639
640#define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */
641#define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */
642#define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */
643#define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */
644#define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */
645#define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */
646#define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
647#define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */
648#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
649#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */
650#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */
651#endif
652
653/* SIC_IAR0 Macros */
654#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
655#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
656#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
657#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
658#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
659#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
660#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
661#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
662
663/* SIC_IAR1 Macros */
664#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
665#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
666#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
667#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
668#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
669#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
670#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
671#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
672
673/* SIC_IAR2 Macros */
674#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
675#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
676#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
677#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
678#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
679#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
680#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
681#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
682
683/* SIC_IAR3 Macros */
684#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
685#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
686#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
687#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
688#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
689#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
690#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
691#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
692
693
694/* SIC_IMASK Masks */
695#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
696#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
697#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
698#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
699
700/* SIC_IWR Masks */
701#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
702#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
703#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
704#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
705
706
707/* ************** UART CONTROLLER MASKS *************************/
708/* UARTx_LCR Masks */
709#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
710#define STB 0x04 /* Stop Bits */
711#define PEN 0x08 /* Parity Enable */
712#define EPS 0x10 /* Even Parity Select */
713#define STP 0x20 /* Stick Parity */
714#define SB 0x40 /* Set Break */
715#define DLAB 0x80 /* Divisor Latch Access */
716
717/* UARTx_MCR Mask */
718#define LOOP_ENA 0x10 /* Loopback Mode Enable */
719#define LOOP_ENA_P 0x04
720
721/* UARTx_LSR Masks */
722#define DR 0x01 /* Data Ready */
723#define OE 0x02 /* Overrun Error */
724#define PE 0x04 /* Parity Error */
725#define FE 0x08 /* Framing Error */
726#define BI 0x10 /* Break Interrupt */
727#define THRE 0x20 /* THR Empty */
728#define TEMT 0x40 /* TSR and UART_THR Empty */
729
730/* UARTx_IER Masks */
731#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
732#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
733#define ELSI 0x04 /* Enable RX Status Interrupt */
734
735/* UARTx_IIR Masks */
736#define NINT 0x01 /* Pending Interrupt */
737#define IIR_TX_READY 0x02 /* UART_THR empty */
738#define IIR_RX_READY 0x04 /* Receive data ready */
739#define IIR_LINE_CHANGE 0x06 /* Receive line status */
740#define IIR_STATUS 0x06 /* Highest Priority Pending Interrupt */
741
742/* UARTx_GCTL Masks */
743#define UCEN 0x01 /* Enable UARTx Clocks */
744#define IREN 0x02 /* Enable IrDA Mode */
745#define TPOLC 0x04 /* IrDA TX Polarity Change */
746#define RPOLC 0x08 /* IrDA RX Polarity Change */
747#define FPE 0x10 /* Force Parity Error On Transmit */
748#define FFE 0x20 /* Force Framing Error On Transmit */
749
750
751/* **************** GENERAL PURPOSE TIMER MASKS **********************/
752/* TIMER_ENABLE Masks */
753#define TIMEN0 0x0001 /* Enable Timer 0 */
754#define TIMEN1 0x0002 /* Enable Timer 1 */
755#define TIMEN2 0x0004 /* Enable Timer 2 */
756#define TIMEN3 0x0008 /* Enable Timer 3 */
757#define TIMEN4 0x0010 /* Enable Timer 4 */
758#define TIMEN5 0x0020 /* Enable Timer 5 */
759#define TIMEN6 0x0040 /* Enable Timer 6 */
760#define TIMEN7 0x0080 /* Enable Timer 7 */
761
762/* TIMER_DISABLE Masks */
763#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
764#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
765#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
766#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
767#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
768#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
769#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
770#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
771
772/* TIMER_STATUS Masks */
773#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
774#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
775#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
776#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
777#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
778#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
779#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
780#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
781#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
782#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
783#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
784#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
785#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
786#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
787#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
788#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
789#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
790#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
791#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
792#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
793#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
794#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
795#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
796#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
797
798/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
799#define TOVL_ERR0 TOVF_ERR0
800#define TOVL_ERR1 TOVF_ERR1
801#define TOVL_ERR2 TOVF_ERR2
802#define TOVL_ERR3 TOVF_ERR3
803#define TOVL_ERR4 TOVF_ERR4
804#define TOVL_ERR5 TOVF_ERR5
805#define TOVL_ERR6 TOVF_ERR6
806#define TOVL_ERR7 TOVF_ERR7
807
808/* TIMERx_CONFIG Masks */
809#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
810#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
811#define EXT_CLK 0x0003 /* External Clock Mode */
812#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
813#define PERIOD_CNT 0x0008 /* Period Count */
814#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
815#define TIN_SEL 0x0020 /* Timer Input Select */
816#define OUT_DIS 0x0040 /* Output Pad Disable */
817#define CLK_SEL 0x0080 /* Timer Clock Select */
818#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
819#define EMU_RUN 0x0200 /* Emulation Behavior Select */
820#define ERR_TYP 0xC000 /* Error Type */
821
822
823/* ****************** GPIO PORTS F, G, H MASKS ***********************/
824/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
825/* Port F Masks */
826#define PF0 0x0001
827#define PF1 0x0002
828#define PF2 0x0004
829#define PF3 0x0008
830#define PF4 0x0010
831#define PF5 0x0020
832#define PF6 0x0040
833#define PF7 0x0080
834#define PF8 0x0100
835#define PF9 0x0200
836#define PF10 0x0400
837#define PF11 0x0800
838#define PF12 0x1000
839#define PF13 0x2000
840#define PF14 0x4000
841#define PF15 0x8000
842
843/* Port G Masks */
844#define PG0 0x0001
845#define PG1 0x0002
846#define PG2 0x0004
847#define PG3 0x0008
848#define PG4 0x0010
849#define PG5 0x0020
850#define PG6 0x0040
851#define PG7 0x0080
852#define PG8 0x0100
853#define PG9 0x0200
854#define PG10 0x0400
855#define PG11 0x0800
856#define PG12 0x1000
857#define PG13 0x2000
858#define PG14 0x4000
859#define PG15 0x8000
860
861/* Port H Masks */
862#define PH0 0x0001
863#define PH1 0x0002
864#define PH2 0x0004
865#define PH3 0x0008
866#define PH4 0x0010
867#define PH5 0x0020
868#define PH6 0x0040
869#define PH7 0x0080
870
871/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
872/* EBIU_AMGCTL Masks */
873#define AMCKEN 0x0001 /* Enable CLKOUT */
874#define AMBEN_NONE 0x0000 /* All Banks Disabled */
875#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
876#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
877#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
878#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
879
880/* EBIU_AMBCTL0 Masks */
881#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
882#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
883#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
884#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
885#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
886#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
887#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
888#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
889#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
890#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
891#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
892#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
893#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
894#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
895#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
896#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
897#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
898#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
899#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
900#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
901#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
902#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
903#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
904#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
905#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
906#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
907#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
908#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
909#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
910#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
911#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
912#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
913#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
914#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
915#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
916#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
917#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
918#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
919#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
920#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
921#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
922#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
923#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
924#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
925
926#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
927#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
928#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
929#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
930#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
931#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
932#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
933#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
934#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
935#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
936#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
937#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
938#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
939#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
940#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
941#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
942#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
943#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
944#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
945#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
946#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
947#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
948#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
949#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
950#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
951#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
952#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
953#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
954#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
955#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
956#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
957#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
958#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
959#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
960#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
961#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
962#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
963#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
964#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
965#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
966#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
967#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
968#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
969#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
970
971/* EBIU_AMBCTL1 Masks */
972#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
973#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
974#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
975#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
976#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
977#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
978#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
979#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
980#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
981#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
982#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
983#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
984#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
985#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
986#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
987#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
988#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
989#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
990#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
991#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
992#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
993#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
994#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
995#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
996#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
997#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
998#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
999#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
1000#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
1001#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
1002#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
1003#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
1004#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
1005#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
1006#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
1007#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
1008#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
1009#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
1010#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
1011#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
1012#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
1013#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
1014#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
1015#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
1016
1017#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
1018#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
1019#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
1020#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
1021#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
1022#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
1023#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
1024#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
1025#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
1026#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
1027#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1028#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1029#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1030#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1031#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
1032#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
1033#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
1034#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
1035#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
1036#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
1037#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
1038#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
1039#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
1040#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
1041#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
1042#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
1043#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
1044#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
1045#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
1046#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
1047#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
1048#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
1049#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
1050#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
1051#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
1052#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
1053#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
1054#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
1055#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
1056#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
1057#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
1058#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
1059#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
1060#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
1061
1062
1063/* ********************** SDRAM CONTROLLER MASKS **********************************************/
1064/* EBIU_SDGCTL Masks */
1065#define SCTLE 0x00000001 /* Enable SDRAM Signals */
1066#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
1067#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
1068#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
1069#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
1070#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
1071#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
1072#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
1073#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
1074#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
1075#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
1076#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
1077#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
1078#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
1079#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
1080#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
1081#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
1082#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
1083#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
1084#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
1085#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
1086#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
1087#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
1088#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
1089#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
1090#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
1091#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
1092#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
1093#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
1094#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
1095#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
1096#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
1097#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
1098#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
1099#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
1100#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
1101#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
1102#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
1103#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
1104#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
1105#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
1106#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
1107#define EBUFE 0x02000000 /* Enable External Buffering Timing */
1108#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
1109#define EMREN 0x10000000 /* Extended Mode Register Enable */
1110#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
1111#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
1112
1113/* EBIU_SDBCTL Masks */
1114#define EBE 0x0001 /* Enable SDRAM External Bank */
1115#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
1116#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
1117#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
1118#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
1119#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
1120#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
1121#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
1122#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
1123#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
1124#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
1125
1126/* EBIU_SDSTAT Masks */
1127#define SDCI 0x0001 /* SDRAM Controller Idle */
1128#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
1129#define SDPUA 0x0004 /* SDRAM Power-Up Active */
1130#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
1131#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
1132#define BGSTAT 0x0020 /* Bus Grant Status */
1133
1134
1135/* ************************** DMA CONTROLLER MASKS ********************************/
1136
1137/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
1138#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
1139#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
1140#define PMAP_PPI 0x0000 /* PPI Port DMA */
1141#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
1142#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
1143#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
1144#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
1145#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
1146#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
1147#define PMAP_SPI 0x7000 /* SPI Port DMA */
1148#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
1149#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
1150#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
1151#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
1152
1153/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
1154/* PPI_CONTROL Masks */
1155#define PORT_EN 0x0001 /* PPI Port Enable */
1156#define PORT_DIR 0x0002 /* PPI Port Direction */
1157#define XFR_TYPE 0x000C /* PPI Transfer Type */
1158#define PORT_CFG 0x0030 /* PPI Port Configuration */
1159#define FLD_SEL 0x0040 /* PPI Active Field Select */
1160#define PACK_EN 0x0080 /* PPI Packing Mode */
1161#define DMA32 0x0100 /* PPI 32-bit DMA Enable */
1162#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
1163#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
1164#define DLEN_8 0x0000 /* Data Length = 8 Bits */
1165#define DLEN_10 0x0800 /* Data Length = 10 Bits */
1166#define DLEN_11 0x1000 /* Data Length = 11 Bits */
1167#define DLEN_12 0x1800 /* Data Length = 12 Bits */
1168#define DLEN_13 0x2000 /* Data Length = 13 Bits */
1169#define DLEN_14 0x2800 /* Data Length = 14 Bits */
1170#define DLEN_15 0x3000 /* Data Length = 15 Bits */
1171#define DLEN_16 0x3800 /* Data Length = 16 Bits */
1172#define DLENGTH 0x3800 /* PPI Data Length */
1173#define POLC 0x4000 /* PPI Clock Polarity */
1174#define POLS 0x8000 /* PPI Frame Sync Polarity */
1175
1176/* PPI_STATUS Masks */
1177#define FLD 0x0400 /* Field Indicator */
1178#define FT_ERR 0x0800 /* Frame Track Error */
1179#define OVR 0x1000 /* FIFO Overflow Error */
1180#define UNDR 0x2000 /* FIFO Underrun Error */
1181#define ERR_DET 0x4000 /* Error Detected Indicator */
1182#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
1183
1184
1185/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
1186/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
1187#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
1188#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
1189
1190/* TWI_PRESCALE Masks */
1191#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
1192#define TWI_ENA 0x0080 /* TWI Enable */
1193#define SCCB 0x0200 /* SCCB Compatibility Enable */
1194
1195/* TWI_SLAVE_CTL Masks */
1196#define SEN 0x0001 /* Slave Enable */
1197#define SADD_LEN 0x0002 /* Slave Address Length */
1198#define STDVAL 0x0004 /* Slave Transmit Data Valid */
1199#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
1200#define GEN 0x0010 /* General Call Adrress Matching Enabled */
1201
1202/* TWI_SLAVE_STAT Masks */
1203#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
1204#define GCALL 0x0002 /* General Call Indicator */
1205
1206/* TWI_MASTER_CTL Masks */
1207#define MEN 0x0001 /* Master Mode Enable */
1208#define MADD_LEN 0x0002 /* Master Address Length */
1209#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
1210#define FAST 0x0008 /* Use Fast Mode Timing Specs */
1211#define STOP 0x0010 /* Issue Stop Condition */
1212#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
1213#define DCNT 0x3FC0 /* Data Bytes To Transfer */
1214#define SDAOVR 0x4000 /* Serial Data Override */
1215#define SCLOVR 0x8000 /* Serial Clock Override */
1216
1217/* TWI_MASTER_STAT Masks */
1218#define MPROG 0x0001 /* Master Transfer In Progress */
1219#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
1220#define ANAK 0x0004 /* Address Not Acknowledged */
1221#define DNAK 0x0008 /* Data Not Acknowledged */
1222#define BUFRDERR 0x0010 /* Buffer Read Error */
1223#define BUFWRERR 0x0020 /* Buffer Write Error */
1224#define SDASEN 0x0040 /* Serial Data Sense */
1225#define SCLSEN 0x0080 /* Serial Clock Sense */
1226#define BUSBUSY 0x0100 /* Bus Busy Indicator */
1227
1228/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
1229#define SINIT 0x0001 /* Slave Transfer Initiated */
1230#define SCOMP 0x0002 /* Slave Transfer Complete */
1231#define SERR 0x0004 /* Slave Transfer Error */
1232#define SOVF 0x0008 /* Slave Overflow */
1233#define MCOMP 0x0010 /* Master Transfer Complete */
1234#define MERR 0x0020 /* Master Transfer Error */
1235#define XMTSERV 0x0040 /* Transmit FIFO Service */
1236#define RCVSERV 0x0080 /* Receive FIFO Service */
1237
1238/* TWI_FIFO_CTRL Masks */
1239#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
1240#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
1241#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
1242#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
1243
1244/* TWI_FIFO_STAT Masks */
1245#define XMTSTAT 0x0003 /* Transmit FIFO Status */
1246#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
1247#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
1248#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
1249
1250#define RCVSTAT 0x000C /* Receive FIFO Status */
1251#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
1252#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
1253#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
1254
1255
1256/* ******************* PIN CONTROL REGISTER MASKS ************************/
1257/* PORT_MUX Masks */
1258#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
1259#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
1260#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
1261
1262#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
1263#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
1264#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
1265#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
1266
1267#define PFDE 0x0008 /* Port F DMA Request Enable */
1268#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
1269#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
1270
1271#define PFTE 0x0010 /* Port F Timer Enable */
1272#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
1273#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
1274
1275#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
1276#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
1277#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
1278
1279#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
1280#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
1281#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
1282
1283#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
1284#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
1285#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
1286
1287#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
1288#define PFFE_TIMER 0x0000 /* Enable TMR2 */
1289#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
1290
1291#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
1292#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
1293#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
1294
1295#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
1296#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
1297#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
1298
1299#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
1300#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
1301#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
1302
1303
1304/* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/
1305/* HDMAx_CTL Masks */
1306#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */
1307#define REP 0x0002 /* HDMA Request Polarity */
1308#define UTE 0x0004 /* Urgency Threshold Enable */
1309#define OIE 0x0010 /* Overflow Interrupt Enable */
1310#define BDIE 0x0020 /* Block Done Interrupt Enable */
1311#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */
1312#define DRQ 0x0300 /* HDMA Request Type */
1313#define DRQ_NONE 0x0000 /* No Request */
1314#define DRQ_SINGLE 0x0100 /* Channels Request Single */
1315#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */
1316#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */
1317#define RBC 0x1000 /* Reload BCNT With IBCNT */
1318#define PS 0x2000 /* HDMA Pin Status */
1319#define OI 0x4000 /* Overflow Interrupt Generated */
1320#define BDI 0x8000 /* Block Done Interrupt Generated */
1321
1322/* entry addresses of the user-callable Boot ROM functions */
1323
1324#define _BOOTROM_RESET 0xEF000000
1325#define _BOOTROM_FINAL_INIT 0xEF000002
1326#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
1327#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
1328#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
1329#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
1330#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
1331#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
1332#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
1333
1334/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
1335#define PGDE_UART PFDE_UART
1336#define PGDE_DMA PFDE_DMA
1337#define CKELOW SCKELOW
1338
1339/* HOST Port Registers */
1340
1341#define HOST_CONTROL 0xffc03400 /* HOST Control Register */
1342#define HOST_STATUS 0xffc03404 /* HOST Status Register */
1343#define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */
1344
1345/* Counter Registers */
1346
1347#define CNT_CONFIG 0xffc03500 /* Configuration Register */
1348#define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */
1349#define CNT_STATUS 0xffc03508 /* Status Register */
1350#define CNT_COMMAND 0xffc0350c /* Command Register */
1351#define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */
1352#define CNT_COUNTER 0xffc03514 /* Counter Register */
1353#define CNT_MAX 0xffc03518 /* Maximal Count Register */
1354#define CNT_MIN 0xffc0351c /* Minimal Count Register */
1355
1356/* OTP/FUSE Registers */
1357
1358#define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */
1359#define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */
1360#define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */
1361#define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */
1362
1363/* Security Registers */
1364
1365#define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */
1366#define SECURE_CONTROL 0xffc03624 /* Secure Control */
1367#define SECURE_STATUS 0xffc03628 /* Secure Status */
1368
1369/* OTP Read/Write Data Buffer Registers */
1370
1371#define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1372#define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1373#define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1374#define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1375
1376/* Motor Control PWM Registers */
1377
1378#define PWM_CTRL 0xffc03700 /* PWM Control Register */
1379#define PWM_STAT 0xffc03704 /* PWM Status Register */
1380#define PWM_TM 0xffc03708 /* PWM Period Register */
1381#define PWM_DT 0xffc0370c /* PWM Dead Time Register */
1382#define PWM_GATE 0xffc03710 /* PWM Chopping Control */
1383#define PWM_CHA 0xffc03714 /* PWM Channel A Duty Control */
1384#define PWM_CHB 0xffc03718 /* PWM Channel B Duty Control */
1385#define PWM_CHC 0xffc0371c /* PWM Channel C Duty Control */
1386#define PWM_SEG 0xffc03720 /* PWM Crossover and Output Enable */
1387#define PWM_SYNCWT 0xffc03724 /* PWM Sync Pluse Width Control */
1388#define PWM_CHAL 0xffc03728 /* PWM Channel AL Duty Control (SR mode only) */
1389#define PWM_CHBL 0xffc0372c /* PWM Channel BL Duty Control (SR mode only) */
1390#define PWM_CHCL 0xffc03730 /* PWM Channel CL Duty Control (SR mode only) */
1391#define PWM_LSI 0xffc03734 /* PWM Low Side Invert (SR mode only) */
1392#define PWM_STAT2 0xffc03738 /* PWM Status Register 2 */
1393
1394
1395/* ********************************************************** */
1396/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
1397/* and MULTI BIT READ MACROS */
1398/* ********************************************************** */
1399
1400/* Bit masks for HOST_CONTROL */
1401
1402#define HOST_CNTR_HOST_EN 0x1 /* Host Enable */
1403#define HOST_CNTR_nHOST_EN 0x0
1404#define HOST_CNTR_HOST_END 0x2 /* Host Endianess */
1405#define HOST_CNTR_nHOST_END 0x0
1406#define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */
1407#define HOST_CNTR_nDATA_SIZE 0x0
1408#define HOST_CNTR_HOST_RST 0x8 /* Host Reset */
1409#define HOST_CNTR_nHOST_RST 0x0
1410#define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */
1411#define HOST_CNTR_nHRDY_OVR 0x0
1412#define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */
1413#define HOST_CNTR_nINT_MODE 0x0
1414#define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */
1415#define HOST_CNTR_ nBT_EN 0x0
1416#define HOST_CNTR_EHW 0x100 /* Enable Host Write */
1417#define HOST_CNTR_nEHW 0x0
1418#define HOST_CNTR_EHR 0x200 /* Enable Host Read */
1419#define HOST_CNTR_nEHR 0x0
1420#define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */
1421#define HOST_CNTR_nBDR 0x0
1422
1423/* Bit masks for HOST_STATUS */
1424
1425#define HOST_STAT_READY 0x1 /* DMA Ready */
1426#define HOST_STAT_nREADY 0x0
1427#define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */
1428#define HOST_STAT_nFIFOFULL 0x0
1429#define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */
1430#define HOST_STAT_nFIFOEMPTY 0x0
1431#define HOST_STAT_COMPLETE 0x8 /* DMA Complete */
1432#define HOST_STAT_nCOMPLETE 0x0
1433#define HOST_STAT_HSHK 0x10 /* Host Handshake */
1434#define HOST_STAT_nHSHK 0x0
1435#define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */
1436#define HOST_STAT_nTIMEOUT 0x0
1437#define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */
1438#define HOST_STAT_nHIRQ 0x0
1439#define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */
1440#define HOST_STAT_nALLOW_CNFG 0x0
1441#define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */
1442#define HOST_STAT_nDMA_DIR 0x0
1443#define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */
1444#define HOST_STAT_nBTE 0x0
1445#define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */
1446#define HOST_STAT_nHOSTRD_DONE 0x0
1447
1448/* Bit masks for HOST_TIMEOUT */
1449
1450#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */
1451
1452/* Bit masks for SECURE_SYSSWT */
1453
1454#define EMUDABL 0x1 /* Emulation Disable. */
1455#define nEMUDABL 0x0
1456#define RSTDABL 0x2 /* Reset Disable */
1457#define nRSTDABL 0x0
1458#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
1459#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
1460#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
1461#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
1462#define nDMA0OVR 0x0
1463#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
1464#define nDMA1OVR 0x0
1465#define EMUOVR 0x4000 /* Emulation Override */
1466#define nEMUOVR 0x0
1467#define OTPSEN 0x8000 /* OTP Secrets Enable. */
1468#define nOTPSEN 0x0
1469#define L2DABL 0x70000 /* L2 Memory Disable. */
1470
1471/* Bit masks for SECURE_CONTROL */
1472
1473#define SECURE0 0x1 /* SECURE 0 */
1474#define nSECURE0 0x0
1475#define SECURE1 0x2 /* SECURE 1 */
1476#define nSECURE1 0x0
1477#define SECURE2 0x4 /* SECURE 2 */
1478#define nSECURE2 0x0
1479#define SECURE3 0x8 /* SECURE 3 */
1480#define nSECURE3 0x0
1481
1482/* Bit masks for SECURE_STATUS */
1483
1484#define SECMODE 0x3 /* Secured Mode Control State */
1485#define NMI 0x4 /* Non Maskable Interrupt */
1486#define nNMI 0x0
1487#define AFVALID 0x8 /* Authentication Firmware Valid */
1488#define nAFVALID 0x0
1489#define AFEXIT 0x10 /* Authentication Firmware Exit */
1490#define nAFEXIT 0x0
1491#define SECSTAT 0xe0 /* Secure Status */
1492
1493
1494
1495#endif /* _DEF_BF51X_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/gpio.h b/arch/blackfin/mach-bf518/include/mach/gpio.h
index 9af6ce0f6321..b480705bfc2e 100644
--- a/arch/blackfin/mach-bf518/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf518/include/mach/gpio.h
@@ -55,4 +55,8 @@
55#define PORT_G GPIO_PG0 55#define PORT_G GPIO_PG0
56#define PORT_H GPIO_PH0 56#define PORT_H GPIO_PH0
57 57
58#include <mach-common/ports-f.h>
59#include <mach-common/ports-g.h>
60#include <mach-common/ports-h.h>
61
58#endif /* _MACH_GPIO_H_ */ 62#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf518/include/mach/pll.h b/arch/blackfin/mach-bf518/include/mach/pll.h
index d5502988896b..94cca674d835 100644
--- a/arch/blackfin/mach-bf518/include/mach/pll.h
+++ b/arch/blackfin/mach-bf518/include/mach/pll.h
@@ -1,63 +1 @@
1/* #include <mach-common/pll.h>
2 * Copyright 2008 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr0, iwr1;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 flags = hard_local_irq_save();
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr0 = bfin_read32(SIC_IWR0);
24 iwr1 = bfin_read32(SIC_IWR1);
25 /* Only allow PPL Wakeup) */
26 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
27 bfin_write32(SIC_IWR1, 0);
28
29 bfin_write16(PLL_CTL, val);
30 SSYNC();
31 asm("IDLE;");
32
33 bfin_write32(SIC_IWR0, iwr0);
34 bfin_write32(SIC_IWR1, iwr1);
35 hard_local_irq_restore(flags);
36}
37
38/* Writing to VR_CTL initiates a PLL relock sequence. */
39static __inline__ void bfin_write_VR_CTL(unsigned int val)
40{
41 unsigned long flags, iwr0, iwr1;
42
43 if (val == bfin_read_VR_CTL())
44 return;
45
46 flags = hard_local_irq_save();
47 /* Enable the PLL Wakeup bit in SIC IWR */
48 iwr0 = bfin_read32(SIC_IWR0);
49 iwr1 = bfin_read32(SIC_IWR1);
50 /* Only allow PPL Wakeup) */
51 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
52 bfin_write32(SIC_IWR1, 0);
53
54 bfin_write16(VR_CTL, val);
55 SSYNC();
56 asm("IDLE;");
57
58 bfin_write32(SIC_IWR0, iwr0);
59 bfin_write32(SIC_IWR1, iwr1);
60 hard_local_irq_restore(flags);
61}
62
63#endif /* _MACH_PLL_H */
diff --git a/arch/blackfin/mach-bf527/boards/ad7160eval.c b/arch/blackfin/mach-bf527/boards/ad7160eval.c
index 52295fff5577..ccab4c689dc3 100644
--- a/arch/blackfin/mach-bf527/boards/ad7160eval.c
+++ b/arch/blackfin/mach-bf527/boards/ad7160eval.c
@@ -67,6 +67,7 @@ static struct musb_hdrc_config musb_config = {
67 * if it is the case. 67 * if it is the case.
68 */ 68 */
69 .gpio_vrsel_active = 1, 69 .gpio_vrsel_active = 1,
70 .clkin = 24, /* musb CLKIN in MHZ */
70}; 71};
71 72
72static struct musb_hdrc_platform_data musb_plat = { 73static struct musb_hdrc_platform_data musb_plat = {
@@ -419,7 +420,7 @@ static struct resource bfin_uart0_resources[] = {
419 }, 420 },
420}; 421};
421 422
422unsigned short bfin_uart0_peripherals[] = { 423static unsigned short bfin_uart0_peripherals[] = {
423 P_UART0_TX, P_UART0_RX, 0 424 P_UART0_TX, P_UART0_RX, 0
424}; 425};
425 426
@@ -474,7 +475,7 @@ static struct resource bfin_uart1_resources[] = {
474#endif 475#endif
475}; 476};
476 477
477unsigned short bfin_uart1_peripherals[] = { 478static unsigned short bfin_uart1_peripherals[] = {
478 P_UART1_TX, P_UART1_RX, 0 479 P_UART1_TX, P_UART1_RX, 0
479}; 480};
480 481
@@ -627,9 +628,9 @@ static struct resource bfin_sport0_uart_resources[] = {
627 }, 628 },
628}; 629};
629 630
630unsigned short bfin_sport0_peripherals[] = { 631static unsigned short bfin_sport0_peripherals[] = {
631 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 632 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
632 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 633 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
633}; 634};
634 635
635static struct platform_device bfin_sport0_uart_device = { 636static struct platform_device bfin_sport0_uart_device = {
@@ -661,9 +662,9 @@ static struct resource bfin_sport1_uart_resources[] = {
661 }, 662 },
662}; 663};
663 664
664unsigned short bfin_sport1_peripherals[] = { 665static unsigned short bfin_sport1_peripherals[] = {
665 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 666 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
666 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 667 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
667}; 668};
668 669
669static struct platform_device bfin_sport1_uart_device = { 670static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c
index 50533edc3994..c9d6dc88f0e6 100644
--- a/arch/blackfin/mach-bf527/boards/cm_bf527.c
+++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c
@@ -104,6 +104,7 @@ static struct musb_hdrc_config musb_config = {
104 * if it is the case. 104 * if it is the case.
105 */ 105 */
106 .gpio_vrsel_active = 1, 106 .gpio_vrsel_active = 1,
107 .clkin = 24, /* musb CLKIN in MHZ */
107}; 108};
108 109
109static struct musb_hdrc_platform_data musb_plat = { 110static struct musb_hdrc_platform_data musb_plat = {
@@ -614,7 +615,7 @@ static struct resource bfin_uart0_resources[] = {
614 }, 615 },
615}; 616};
616 617
617unsigned short bfin_uart0_peripherals[] = { 618static unsigned short bfin_uart0_peripherals[] = {
618 P_UART0_TX, P_UART0_RX, 0 619 P_UART0_TX, P_UART0_RX, 0
619}; 620};
620 621
@@ -669,7 +670,7 @@ static struct resource bfin_uart1_resources[] = {
669#endif 670#endif
670}; 671};
671 672
672unsigned short bfin_uart1_peripherals[] = { 673static unsigned short bfin_uart1_peripherals[] = {
673 P_UART1_TX, P_UART1_RX, 0 674 P_UART1_TX, P_UART1_RX, 0
674}; 675};
675 676
@@ -801,9 +802,9 @@ static struct resource bfin_sport0_uart_resources[] = {
801 }, 802 },
802}; 803};
803 804
804unsigned short bfin_sport0_peripherals[] = { 805static unsigned short bfin_sport0_peripherals[] = {
805 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 806 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
806 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 807 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
807}; 808};
808 809
809static struct platform_device bfin_sport0_uart_device = { 810static struct platform_device bfin_sport0_uart_device = {
@@ -835,9 +836,9 @@ static struct resource bfin_sport1_uart_resources[] = {
835 }, 836 },
836}; 837};
837 838
838unsigned short bfin_sport1_peripherals[] = { 839static unsigned short bfin_sport1_peripherals[] = {
839 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 840 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
840 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 841 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
841}; 842};
842 843
843static struct platform_device bfin_sport1_uart_device = { 844static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c
index d06177b5fe22..b7101aa6e3aa 100644
--- a/arch/blackfin/mach-bf527/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf527/boards/ezbrd.c
@@ -68,6 +68,7 @@ static struct musb_hdrc_config musb_config = {
68 * if it is the case. 68 * if it is the case.
69 */ 69 */
70 .gpio_vrsel_active = 1, 70 .gpio_vrsel_active = 1,
71 .clkin = 24, /* musb CLKIN in MHZ */
71}; 72};
72 73
73static struct musb_hdrc_platform_data musb_plat = { 74static struct musb_hdrc_platform_data musb_plat = {
@@ -499,7 +500,7 @@ static struct resource bfin_uart0_resources[] = {
499 }, 500 },
500}; 501};
501 502
502unsigned short bfin_uart0_peripherals[] = { 503static unsigned short bfin_uart0_peripherals[] = {
503 P_UART0_TX, P_UART0_RX, 0 504 P_UART0_TX, P_UART0_RX, 0
504}; 505};
505 506
@@ -554,7 +555,7 @@ static struct resource bfin_uart1_resources[] = {
554#endif 555#endif
555}; 556};
556 557
557unsigned short bfin_uart1_peripherals[] = { 558static unsigned short bfin_uart1_peripherals[] = {
558 P_UART1_TX, P_UART1_RX, 0 559 P_UART1_TX, P_UART1_RX, 0
559}; 560};
560 561
@@ -681,9 +682,9 @@ static struct resource bfin_sport0_uart_resources[] = {
681 }, 682 },
682}; 683};
683 684
684unsigned short bfin_sport0_peripherals[] = { 685static unsigned short bfin_sport0_peripherals[] = {
685 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 686 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
686 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 687 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
687}; 688};
688 689
689static struct platform_device bfin_sport0_uart_device = { 690static struct platform_device bfin_sport0_uart_device = {
@@ -715,9 +716,9 @@ static struct resource bfin_sport1_uart_resources[] = {
715 }, 716 },
716}; 717};
717 718
718unsigned short bfin_sport1_peripherals[] = { 719static unsigned short bfin_sport1_peripherals[] = {
719 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 720 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
720 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 721 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
721}; 722};
722 723
723static struct platform_device bfin_sport1_uart_device = { 724static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index 35a88a5a5013..2cd2ff6f3043 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -108,6 +108,7 @@ static struct musb_hdrc_config musb_config = {
108 * if it is the case. 108 * if it is the case.
109 */ 109 */
110 .gpio_vrsel_active = 1, 110 .gpio_vrsel_active = 1,
111 .clkin = 24, /* musb CLKIN in MHZ */
111}; 112};
112 113
113static struct musb_hdrc_platform_data musb_plat = { 114static struct musb_hdrc_platform_data musb_plat = {
@@ -708,7 +709,7 @@ static struct resource bfin_uart0_resources[] = {
708 }, 709 },
709}; 710};
710 711
711unsigned short bfin_uart0_peripherals[] = { 712static unsigned short bfin_uart0_peripherals[] = {
712 P_UART0_TX, P_UART0_RX, 0 713 P_UART0_TX, P_UART0_RX, 0
713}; 714};
714 715
@@ -763,7 +764,7 @@ static struct resource bfin_uart1_resources[] = {
763#endif 764#endif
764}; 765};
765 766
766unsigned short bfin_uart1_peripherals[] = { 767static unsigned short bfin_uart1_peripherals[] = {
767 P_UART1_TX, P_UART1_RX, 0 768 P_UART1_TX, P_UART1_RX, 0
768}; 769};
769 770
@@ -962,6 +963,11 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
962 I2C_BOARD_INFO("ad5252", 0x2f), 963 I2C_BOARD_INFO("ad5252", 0x2f),
963 }, 964 },
964#endif 965#endif
966#if defined(CONFIG_SND_SOC_ADAU1373) || defined(CONFIG_SND_SOC_ADAU1373_MODULE)
967 {
968 I2C_BOARD_INFO("adau1373", 0x1A),
969 },
970#endif
965}; 971};
966 972
967#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) 973#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
@@ -984,9 +990,9 @@ static struct resource bfin_sport0_uart_resources[] = {
984 }, 990 },
985}; 991};
986 992
987unsigned short bfin_sport0_peripherals[] = { 993static unsigned short bfin_sport0_peripherals[] = {
988 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 994 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
989 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 995 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
990}; 996};
991 997
992static struct platform_device bfin_sport0_uart_device = { 998static struct platform_device bfin_sport0_uart_device = {
@@ -1018,9 +1024,9 @@ static struct resource bfin_sport1_uart_resources[] = {
1018 }, 1024 },
1019}; 1025};
1020 1026
1021unsigned short bfin_sport1_peripherals[] = { 1027static unsigned short bfin_sport1_peripherals[] = {
1022 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 1028 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
1023 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 1029 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
1024}; 1030};
1025 1031
1026static struct platform_device bfin_sport1_uart_device = { 1032static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf527/boards/tll6527m.c b/arch/blackfin/mach-bf527/boards/tll6527m.c
index 130861bd2589..18d303dd5627 100644
--- a/arch/blackfin/mach-bf527/boards/tll6527m.c
+++ b/arch/blackfin/mach-bf527/boards/tll6527m.c
@@ -193,7 +193,7 @@ static unsigned gpio_addr_inputs[] = {
193 GPIO_PG1, GPIO_PH9, GPIO_PH10 193 GPIO_PG1, GPIO_PH9, GPIO_PH10
194}; 194};
195 195
196static struct gpio_decoder_platfrom_data spi_decoded_cs = { 196static struct gpio_decoder_platform_data spi_decoded_cs = {
197 .base = EXP_GPIO_SPISEL_BASE, 197 .base = EXP_GPIO_SPISEL_BASE,
198 .input_addrs = gpio_addr_inputs, 198 .input_addrs = gpio_addr_inputs,
199 .nr_input_addrs = ARRAY_SIZE(gpio_addr_inputs), 199 .nr_input_addrs = ARRAY_SIZE(gpio_addr_inputs),
@@ -586,7 +586,7 @@ static struct resource bfin_uart0_resources[] = {
586 }, 586 },
587}; 587};
588 588
589unsigned short bfin_uart0_peripherals[] = { 589static unsigned short bfin_uart0_peripherals[] = {
590 P_UART0_TX, P_UART0_RX, 0 590 P_UART0_TX, P_UART0_RX, 0
591}; 591};
592 592
@@ -642,7 +642,7 @@ static struct resource bfin_uart1_resources[] = {
642#endif 642#endif
643}; 643};
644 644
645unsigned short bfin_uart1_peripherals[] = { 645static unsigned short bfin_uart1_peripherals[] = {
646 P_UART1_TX, P_UART1_RX, 0 646 P_UART1_TX, P_UART1_RX, 0
647}; 647};
648 648
@@ -799,9 +799,9 @@ static struct resource bfin_sport0_uart_resources[] = {
799 }, 799 },
800}; 800};
801 801
802unsigned short bfin_sport0_peripherals[] = { 802static unsigned short bfin_sport0_peripherals[] = {
803 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 803 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
804 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 804 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
805}; 805};
806 806
807static struct platform_device bfin_sport0_uart_device = { 807static struct platform_device bfin_sport0_uart_device = {
@@ -834,9 +834,9 @@ static struct resource bfin_sport1_uart_resources[] = {
834 }, 834 },
835}; 835};
836 836
837unsigned short bfin_sport1_peripherals[] = { 837static unsigned short bfin_sport1_peripherals[] = {
838 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 838 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
839 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 839 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
840}; 840};
841 841
842static struct platform_device bfin_sport1_uart_device = { 842static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf527/dma.c b/arch/blackfin/mach-bf527/dma.c
index 7bc7577d6c4f..1fabdefea73a 100644
--- a/arch/blackfin/mach-bf527/dma.c
+++ b/arch/blackfin/mach-bf527/dma.c
@@ -11,7 +11,7 @@
11#include <asm/blackfin.h> 11#include <asm/blackfin.h>
12#include <asm/dma.h> 12#include <asm/dma.h>
13 13
14struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { 14struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
15 (struct dma_register *) DMA0_NEXT_DESC_PTR, 15 (struct dma_register *) DMA0_NEXT_DESC_PTR,
16 (struct dma_register *) DMA1_NEXT_DESC_PTR, 16 (struct dma_register *) DMA1_NEXT_DESC_PTR,
17 (struct dma_register *) DMA2_NEXT_DESC_PTR, 17 (struct dma_register *) DMA2_NEXT_DESC_PTR,
diff --git a/arch/blackfin/mach-bf527/include/mach/bfin_serial.h b/arch/blackfin/mach-bf527/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..00c603fe8218
--- /dev/null
+++ b/arch/blackfin/mach-bf527/include/mach/bfin_serial.h
@@ -0,0 +1,14 @@
1/*
2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
3 *
4 * Copyright 2006-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_MACH_SERIAL_H__
10#define __BFIN_MACH_SERIAL_H__
11
12#define BFIN_UART_NR_PORTS 2
13
14#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
index c1d55b878b45..960e08919def 100644
--- a/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
@@ -4,36 +4,9 @@
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later
5 */ 5 */
6 6
7#include <linux/serial.h>
8#include <asm/dma.h> 7#include <asm/dma.h>
9#include <asm/portmux.h> 8#include <asm/portmux.h>
10 9
11#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
12#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
13#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
14#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
15#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
16#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
17#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
18
19#define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v)
20#define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
21#define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v)
22#define UART_SET_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
23#define UART_CLEAR_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
24#define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
25#define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
26#define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
27
28#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
29#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
30
31#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
32#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
33#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
34#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
35#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
36
37#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) 10#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
38# define CONFIG_SERIAL_BFIN_CTSRTS 11# define CONFIG_SERIAL_BFIN_CTSRTS
39 12
@@ -54,50 +27,6 @@
54# endif 27# endif
55#endif 28#endif
56 29
57#define BFIN_UART_TX_FIFO_SIZE 2
58
59/*
60 * The pin configuration is different from schematic
61 */
62struct bfin_serial_port {
63 struct uart_port port;
64 unsigned int old_status;
65 int status_irq;
66 unsigned int lsr;
67#ifdef CONFIG_SERIAL_BFIN_DMA
68 int tx_done;
69 int tx_count;
70 struct circ_buf rx_dma_buf;
71 struct timer_list rx_dma_timer;
72 int rx_dma_nrows;
73 unsigned int tx_dma_channel;
74 unsigned int rx_dma_channel;
75 struct work_struct tx_dma_workqueue;
76#endif
77#ifdef CONFIG_SERIAL_BFIN_CTSRTS
78 struct timer_list cts_timer;
79 int cts_pin;
80 int rts_pin;
81#endif
82};
83
84/* The hardware clears the LSR bits upon read, so we need to cache
85 * some of the more fun bits in software so they don't get lost
86 * when checking the LSR in other code paths (TX).
87 */
88static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
89{
90 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
91 uart->lsr |= (lsr & (BI|FE|PE|OE));
92 return lsr | uart->lsr;
93}
94
95static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
96{
97 uart->lsr = 0;
98 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
99}
100
101struct bfin_serial_res { 30struct bfin_serial_res {
102 unsigned long uart_base_addr; 31 unsigned long uart_base_addr;
103 int uart_irq; 32 int uart_irq;
@@ -146,3 +75,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
146}; 75};
147 76
148#define DRIVER_NAME "bfin-uart" 77#define DRIVER_NAME "bfin-uart"
78
79#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf527/include/mach/blackfin.h b/arch/blackfin/mach-bf527/include/mach/blackfin.h
index f714c5de3073..e1d279274487 100644
--- a/arch/blackfin/mach-bf527/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf527/include/mach/blackfin.h
@@ -1,49 +1,37 @@
1/* 1/*
2 * Copyright 2007-2009 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later.
5 */ 5 */
6 6
7#ifndef _MACH_BLACKFIN_H_ 7#ifndef _MACH_BLACKFIN_H_
8#define _MACH_BLACKFIN_H_ 8#define _MACH_BLACKFIN_H_
9 9
10#include "bf527.h" 10#include "bf527.h"
11#include "defBF522.h"
12#include "anomaly.h" 11#include "anomaly.h"
13 12
14#if defined(CONFIG_BF527) || defined(CONFIG_BF526) 13#include <asm/def_LPBlackfin.h>
15#include "defBF527.h" 14#if defined(CONFIG_BF523) || defined(CONFIG_BF522)
15# include "defBF522.h"
16#endif 16#endif
17
18#if defined(CONFIG_BF525) || defined(CONFIG_BF524) 17#if defined(CONFIG_BF525) || defined(CONFIG_BF524)
19#include "defBF525.h" 18# include "defBF525.h"
20#endif 19#endif
21
22#if !defined(__ASSEMBLY__)
23#include "cdefBF522.h"
24
25#if defined(CONFIG_BF527) || defined(CONFIG_BF526) 20#if defined(CONFIG_BF527) || defined(CONFIG_BF526)
26#include "cdefBF527.h" 21# include "defBF527.h"
27#endif 22#endif
28 23
29#if defined(CONFIG_BF525) || defined(CONFIG_BF524) 24#if !defined(__ASSEMBLY__)
30#include "cdefBF525.h" 25# include <asm/cdef_LPBlackfin.h>
31#endif 26# if defined(CONFIG_BF523) || defined(CONFIG_BF522)
27# include "cdefBF522.h"
28# endif
29# if defined(CONFIG_BF525) || defined(CONFIG_BF524)
30# include "cdefBF525.h"
31# endif
32# if defined(CONFIG_BF527) || defined(CONFIG_BF526)
33# include "cdefBF527.h"
34# endif
32#endif 35#endif
33 36
34#define BFIN_UART_NR_PORTS 2
35
36#define OFFSET_THR 0x00 /* Transmit Holding register */
37#define OFFSET_RBR 0x00 /* Receive Buffer register */
38#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
39#define OFFSET_IER 0x04 /* Interrupt Enable Register */
40#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
41#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
42#define OFFSET_LCR 0x0C /* Line Control Register */
43#define OFFSET_MCR 0x10 /* Modem Control Register */
44#define OFFSET_LSR 0x14 /* Line Status Register */
45#define OFFSET_MSR 0x18 /* Modem Status Register */
46#define OFFSET_SCR 0x1C /* SCR Scratch Register */
47#define OFFSET_GCTL 0x24 /* Global Control Register */
48
49#endif 37#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF522.h b/arch/blackfin/mach-bf527/include/mach/cdefBF522.h
index 1079af8c7aef..618dfcdfa91a 100644
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF522.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF522.h
@@ -1,21 +1,1095 @@
1/* 1/*
2 * Copyright 2007-2008 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later.
5 */ 5 */
6 6
7#ifndef _CDEF_BF522_H 7#ifndef _CDEF_BF522_H
8#define _CDEF_BF522_H 8#define _CDEF_BF522_H
9 9
10/* include all Core registers and bit definitions */ 10/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
11#include "defBF522.h" 11#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
12#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
13#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
14#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
15#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
16#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
17#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
18#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
19#define bfin_read_CHIPID() bfin_read32(CHIPID)
20#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
12 21
13/* include core specific register pointer definitions */
14#include <asm/cdef_LPBlackfin.h>
15 22
16/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */ 23/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
24#define bfin_read_SWRST() bfin_read16(SWRST)
25#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
26#define bfin_read_SYSCR() bfin_read16(SYSCR)
27#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
17 28
18/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */ 29#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
19#include "cdefBF52x_base.h" 30#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
31#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
32#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
33#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6))
34#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)
35
36#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
37#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
38#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
39#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
40#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
41#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
42#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
43#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
44
45#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
46#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
47#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6))
48#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
49
50#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
51#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
52#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6))
53#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)
54
55/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
56
57#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
58#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
59#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
60#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
61#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
62#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
63#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
64#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
65#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
66#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
67#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
68#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
69#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
70#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
71
72/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
73#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
74#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
75#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
76#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
77#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
78#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
79
80
81/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
82#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
83#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
84#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
85#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
86#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
87#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
88#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
89#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
90#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
91#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
92#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
93#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val)
94#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
95#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
96
97
98/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
99#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
100#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
101#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
102#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
103#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
104#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
105#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
106#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
107#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
108#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
109#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
110#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
111#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
112#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
113#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
114#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
115#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
116#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
117#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
118#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
119#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
120#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
121#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
122#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
123
124
125/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
126#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
127#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val)
128#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
129#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val)
130#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
131#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val)
132#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
133#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val)
134#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
135#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val)
136#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
137#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val)
138#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
139#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val)
140
141
142/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
143#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
144#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
145#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
146#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
147#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
148#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
149#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
150#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
151
152#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
153#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
154#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
155#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
156#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
157#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
158#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
159#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
160
161#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
162#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
163#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
164#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
165#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
166#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
167#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
168#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
169
170#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
171#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
172#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
173#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
174#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
175#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
176#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
177#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
178
179#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
180#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
181#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
182#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
183#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
184#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
185#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
186#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
187
188#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
189#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
190#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
191#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
192#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
193#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
194#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
195#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
196
197#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
198#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
199#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
200#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
201#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
202#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
203#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
204#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
205
206#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
207#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
208#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
209#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
210#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
211#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
212#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
213#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
214
215#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
216#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
217#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
218#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
219#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
220#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val)
221
222
223/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
224#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
225#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
226#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
227#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
228#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
229#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
230#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
231#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
232#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
233#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
234#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
235#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
236#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
237#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
238#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
239#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
240#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
241#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
242#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
243#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
244#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
245#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
246#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
247#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
248#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
249#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
250#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
251#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
252#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
253#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
254#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
255#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
256#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
257#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
258
259
260/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
261#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
262#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
263#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
264#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
265#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
266#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
267#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
268#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
269#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
270#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
271#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
272#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
273#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
274#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX, val)
275#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
276#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX, val)
277#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
278#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX, val)
279#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
280#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX, val)
281#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
282#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
283#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
284#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
285#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
286#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
287#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
288#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
289#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
290#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
291#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
292#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
293#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
294#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
295#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
296#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
297#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
298#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
299#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
300#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
301#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
302#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
303#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
304#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
305#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
306#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
307#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
308#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
309#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
310#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
311#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
312#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
313
314
315/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
316#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
317#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
318#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
319#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
320#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
321#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
322#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
323#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
324#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
325#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
326#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
327#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
328#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
329#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX, val)
330#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
331#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX, val)
332#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
333#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX, val)
334#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
335#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX, val)
336#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
337#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
338#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
339#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
340#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
341#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
342#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
343#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
344#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
345#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
346#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
347#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
348#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
349#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
350#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
351#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
352#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
353#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
354#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
355#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
356#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
357#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
358#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
359#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
360#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
361#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
362#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
363#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
364#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
365#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
366#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
367#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
368
369
370/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
371#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
372#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
373#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
374#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
375#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
376#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
377#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
378#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
379#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
380#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
381#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
382#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
383#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
384#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
385
386
387/* DMA Traffic Control Registers */
388#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
389#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER, val)
390#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
391#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT, val)
392
393/* DMA Controller */
394#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
395#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
396#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
397#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
398#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
399#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
400#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
401#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
402#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
403#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
404#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
405#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
406#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
407#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
408#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
409#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
410#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
411#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
412#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
413#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
414#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
415#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
416#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
417#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
418#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
419#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
420
421#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
422#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
423#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
424#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
425#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
426#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
427#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
428#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
429#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
430#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
431#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
432#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
433#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
434#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
435#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
436#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
437#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
438#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
439#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
440#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
441#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
442#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
443#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
444#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
445#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
446#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
447
448#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
449#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
450#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
451#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
452#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
453#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
454#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
455#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
456#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
457#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
458#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
459#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
460#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
461#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
462#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
463#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
464#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
465#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
466#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
467#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
468#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
469#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
470#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
471#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
472#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
473#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
474
475#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
476#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
477#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
478#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
479#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
480#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
481#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
482#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
483#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
484#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
485#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
486#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
487#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
488#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
489#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
490#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
491#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
492#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
493#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
494#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
495#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
496#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
497#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
498#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
499#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
500#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
501
502#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
503#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
504#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
505#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
506#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
507#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
508#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
509#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
510#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
511#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
512#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
513#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
514#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
515#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
516#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
517#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
518#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
519#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
520#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
521#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
522#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
523#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
524#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
525#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
526#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
527#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
528
529#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
530#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
531#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
532#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
533#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
534#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
535#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
536#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
537#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
538#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
539#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
540#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
541#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
542#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
543#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
544#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
545#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
546#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
547#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
548#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
549#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
550#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
551#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
552#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
553#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
554#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
555
556#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
557#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
558#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
559#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
560#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
561#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
562#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
563#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
564#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
565#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
566#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
567#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
568#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
569#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
570#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
571#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
572#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
573#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
574#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
575#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
576#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
577#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
578#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
579#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
580#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
581#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
582
583#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
584#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
585#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
586#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
587#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
588#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
589#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
590#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
591#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
592#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
593#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
594#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
595#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
596#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
597#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
598#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
599#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
600#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
601#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
602#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
603#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
604#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
605#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
606#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
607#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
608#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
609
610#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
611#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
612#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
613#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
614#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
615#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
616#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
617#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
618#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
619#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
620#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
621#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
622#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
623#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
624#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
625#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
626#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
627#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
628#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
629#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
630#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
631#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
632#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
633#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
634#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
635#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
636
637#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
638#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
639#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
640#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
641#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
642#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
643#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
644#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
645#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
646#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
647#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
648#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
649#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
650#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
651#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
652#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
653#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
654#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
655#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
656#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
657#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
658#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
659#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
660#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
661#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
662#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
663
664#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
665#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
666#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
667#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
668#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
669#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
670#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
671#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
672#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
673#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
674#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
675#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
676#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
677#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
678#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
679#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
680#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
681#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
682#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
683#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
684#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
685#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
686#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
687#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
688#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
689#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
690
691#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
692#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
693#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
694#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
695#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
696#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
697#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
698#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
699#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
700#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
701#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
702#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
703#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
704#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
705#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
706#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
707#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
708#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
709#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
710#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
711#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
712#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
713#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
714#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
715#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
716#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
717
718#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
719#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
720#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
721#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
722#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
723#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
724#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
725#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
726#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
727#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
728#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
729#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
730#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
731#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
732#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
733#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
734#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
735#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
736#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
737#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
738#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
739#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
740#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
741#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
742#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
743#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
744
745#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
746#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
747#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
748#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
749#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
750#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
751#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
752#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
753#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
754#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
755#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
756#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
757#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
758#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
759#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
760#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
761#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
762#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
763#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
764#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
765#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
766#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
767#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
768#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
769#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
770#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
771
772#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
773#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
774#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
775#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
776#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
777#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
778#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
779#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
780#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
781#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
782#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
783#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
784#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
785#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
786#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
787#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
788#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
789#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
790#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
791#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
792#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
793#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
794#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
795#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
796#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
797#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
798
799#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
800#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
801#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
802#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
803#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
804#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
805#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
806#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
807#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
808#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
809#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
810#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
811#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
812#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
813#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
814#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
815#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
816#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
817#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
818#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
819#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
820#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
821#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
822#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
823#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
824#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
825
826
827/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
828#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
829#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
830#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
831#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
832#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF)
833#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
834#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
835#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
836#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
837#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
838#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
839
840
841/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
842
843/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
844#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
845#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val)
846#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
847#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val)
848#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
849#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val)
850#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
851#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
852#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
853#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val)
854#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
855#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
856#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
857#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
858#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
859#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
860#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
861#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val)
862#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
863#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
864#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
865#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
866#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
867#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
868#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
869#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val)
870#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
871#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val)
872#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
873#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val)
874#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
875#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val)
876#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
877#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val)
878
879
880/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
881#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
882#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val)
883#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
884#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val)
885#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
886#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val)
887#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
888#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
889#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
890#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val)
891#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
892#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
893#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
894#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
895#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
896#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
897#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
898#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val)
899#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
900#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
901#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
902#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
903#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
904#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
905#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
906#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val)
907#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
908#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val)
909#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
910#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val)
911#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
912#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val)
913#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
914#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val)
915
916
917/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
918#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
919#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
920#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
921#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
922#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
923#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
924#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
925#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
926#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
927#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
928#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
929#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
930#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
931#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
932#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
933#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
934#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
935#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
936#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
937#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
938#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
939#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
940#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
941#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
942
943/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF52x processor) */
944
945/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
946#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
947#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
948#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
949#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
950#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
951#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
952#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX)
953#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val)
954
955
956/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
957#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
958#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
959#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
960#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
961#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
962#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
963#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
964#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
965#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
966#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
967#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
968#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
969#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
970#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
971
972#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
973#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
974#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
975#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
976#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
977#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
978#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
979#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
980#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
981#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
982#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
983#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
984#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
985#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
986
987/* ==== end from cdefBF534.h ==== */
988
989/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
990
991#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX)
992#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val)
993#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX)
994#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val)
995#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX)
996#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val)
997
998#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE)
999#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val)
1000#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE)
1001#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val)
1002#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE)
1003#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val)
1004#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW)
1005#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val)
1006#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW)
1007#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val)
1008#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW)
1009#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val)
1010#define bfin_read_PORTF_HYSTERISIS() bfin_read16(PORTF_HYSTERISIS)
1011#define bfin_write_PORTF_HYSTERISIS(val) bfin_write16(PORTF_HYSTERISIS, val)
1012#define bfin_read_PORTG_HYSTERISIS() bfin_read16(PORTG_HYSTERISIS)
1013#define bfin_write_PORTG_HYSTERISIS(val) bfin_write16(PORTG_HYSTERISIS, val)
1014#define bfin_read_PORTH_HYSTERISIS() bfin_read16(PORTH_HYSTERISIS)
1015#define bfin_write_PORTH_HYSTERISIS(val) bfin_write16(PORTH_HYSTERISIS, val)
1016#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE)
1017#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val)
1018#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW)
1019#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val)
1020#define bfin_read_MISCPORT_HYSTERISIS() bfin_read16(MISCPORT_HYSTERISIS)
1021#define bfin_write_MISCPORT_HYSTERISIS(val) bfin_write16(MISCPORT_HYSTERISIS, val)
1022
1023/* HOST Port Registers */
1024
1025#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
1026#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
1027#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
1028#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
1029#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
1030#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
1031
1032/* Counter Registers */
1033
1034#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
1035#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
1036#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
1037#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
1038#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
1039#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
1040#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
1041#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
1042#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
1043#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
1044#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
1045#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
1046#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
1047#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
1048#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
1049#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
1050
1051/* Security Registers */
1052
1053#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
1054#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
1055#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
1056#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
1057#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
1058#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
1059
1060/* NFC Registers */
1061
1062#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
1063#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
1064#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
1065#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
1066#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
1067#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
1068#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
1069#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
1070#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
1071#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
1072#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
1073#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
1074#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
1075#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
1076#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
1077#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
1078#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
1079#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
1080#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
1081#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
1082#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
1083#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
1084#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
1085#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
1086#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
1087#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
1088#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
1089#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
1090#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
1091#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
1092#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
1093#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
20 1094
21#endif /* _CDEF_BF522_H */ 1095#endif /* _CDEF_BF522_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF525.h b/arch/blackfin/mach-bf527/include/mach/cdefBF525.h
index d7e2751c6bcc..d90a85b6b6b9 100644
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF525.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF525.h
@@ -1,15 +1,12 @@
1/* 1/*
2 * Copyright 2007-2008 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later.
5 */ 5 */
6 6
7#ifndef _CDEF_BF525_H 7#ifndef _CDEF_BF525_H
8#define _CDEF_BF525_H 8#define _CDEF_BF525_H
9 9
10/* include all Core registers and bit definitions */
11#include "defBF525.h"
12
13/* BF525 is BF522 + USB */ 10/* BF525 is BF522 + USB */
14#include "cdefBF522.h" 11#include "cdefBF522.h"
15 12
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF527.h b/arch/blackfin/mach-bf527/include/mach/cdefBF527.h
index c7ba544d50b6..eb22f5866105 100644
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF527.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF527.h
@@ -1,15 +1,12 @@
1/* 1/*
2 * Copyright 2007-2008 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later.
5 */ 5 */
6 6
7#ifndef _CDEF_BF527_H 7#ifndef _CDEF_BF527_H
8#define _CDEF_BF527_H 8#define _CDEF_BF527_H
9 9
10/* include all Core registers and bit definitions */
11#include "defBF527.h"
12
13/* BF527 is BF525 + EMAC */ 10/* BF527 is BF525 + EMAC */
14#include "cdefBF525.h" 11#include "cdefBF525.h"
15 12
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
deleted file mode 100644
index 3048b52bf46a..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
+++ /dev/null
@@ -1,1113 +0,0 @@
1/*
2 * Copyright 2007-2008 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later
5 */
6
7#ifndef _CDEF_BF52X_H
8#define _CDEF_BF52X_H
9
10#include <asm/blackfin.h>
11
12#include "defBF52x_base.h"
13
14/* Include core specific register pointer definitions */
15#include <asm/cdef_LPBlackfin.h>
16
17/* ==== begin from cdefBF534.h ==== */
18
19/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
20#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
21#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
22#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
23#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
24#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
25#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
26#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
27#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
28#define bfin_read_CHIPID() bfin_read32(CHIPID)
29#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
30
31
32/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
33#define bfin_read_SWRST() bfin_read16(SWRST)
34#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
35#define bfin_read_SYSCR() bfin_read16(SYSCR)
36#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
37
38#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
39#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
40#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
41#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
42#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6))
43#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)
44
45#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
46#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
47#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
48#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
49#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
50#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
51#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
52#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
53
54#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
55#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
56#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6))
57#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
58
59#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
60#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
61#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6))
62#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)
63
64/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
65
66#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
67#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
68#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
69#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
70#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
71#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
72#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
73#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
74#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
75#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
76#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
77#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
78#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
79#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
80
81/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
82#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
83#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
84#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
85#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
86#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
87#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
88
89
90/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
91#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
92#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
93#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
94#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
95#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
96#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
97#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
98#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
99#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
100#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
101#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
102#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val)
103#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
104#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
105
106
107/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
108#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
109#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
110#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
111#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
112#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
113#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
114#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
115#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
116#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
117#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
118#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
119#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
120#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
121#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
122#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
123#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
124#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
125#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
126#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
127#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
128#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
129#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
130#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
131#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
132
133
134/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
135#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
136#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val)
137#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
138#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val)
139#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
140#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val)
141#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
142#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val)
143#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
144#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val)
145#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
146#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val)
147#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
148#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val)
149
150
151/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
152#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
153#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
154#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
155#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
156#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
157#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
158#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
159#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
160
161#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
162#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
163#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
164#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
165#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
166#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
167#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
168#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
169
170#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
171#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
172#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
173#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
174#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
175#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
176#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
177#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
178
179#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
180#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
181#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
182#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
183#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
184#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
185#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
186#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
187
188#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
189#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
190#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
191#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
192#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
193#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
194#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
195#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
196
197#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
198#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
199#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
200#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
201#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
202#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
203#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
204#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
205
206#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
207#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
208#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
209#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
210#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
211#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
212#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
213#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
214
215#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
216#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
217#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
218#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
219#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
220#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
221#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
222#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
223
224#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
225#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
226#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
227#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
228#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
229#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val)
230
231
232/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
233#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
234#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
235#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
236#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
237#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
238#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
239#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
240#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
241#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
242#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
243#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
244#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
245#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
246#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
247#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
248#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
249#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
250#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
251#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
252#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
253#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
254#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
255#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
256#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
257#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
258#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
259#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
260#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
261#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
262#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
263#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
264#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
265#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
266#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
267
268
269/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
270#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
271#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
272#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
273#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
274#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
275#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
276#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
277#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
278#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
279#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
280#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
281#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
282#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
283#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX, val)
284#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
285#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX, val)
286#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
287#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX, val)
288#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
289#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX, val)
290#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
291#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
292#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
293#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
294#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
295#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
296#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
297#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
298#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
299#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
300#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
301#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
302#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
303#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
304#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
305#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
306#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
307#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
308#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
309#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
310#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
311#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
312#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
313#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
314#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
315#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
316#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
317#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
318#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
319#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
320#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
321#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
322
323
324/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
325#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
326#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
327#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
328#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
329#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
330#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
331#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
332#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
333#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
334#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
335#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
336#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
337#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
338#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX, val)
339#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
340#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX, val)
341#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
342#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX, val)
343#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
344#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX, val)
345#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
346#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
347#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
348#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
349#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
350#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
351#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
352#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
353#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
354#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
355#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
356#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
357#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
358#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
359#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
360#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
361#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
362#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
363#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
364#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
365#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
366#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
367#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
368#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
369#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
370#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
371#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
372#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
373#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
374#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
375#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
376#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
377
378
379/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
380#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
381#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
382#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
383#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
384#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
385#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
386#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
387#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
388#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
389#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
390#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
391#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
392#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
393#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
394
395
396/* DMA Traffic Control Registers */
397#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
398#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val)
399#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
400#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val)
401
402/* Alternate deprecated register names (below) provided for backwards code compatibility */
403#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
404#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER, val)
405#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
406#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT, val)
407
408/* DMA Controller */
409#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
410#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
411#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
412#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
413#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
414#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
415#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
416#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
417#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
418#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
419#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
420#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
421#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
422#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
423#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
424#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
425#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
426#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
427#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
428#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
429#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
430#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
431#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
432#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
433#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
434#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
435
436#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
437#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
438#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
439#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
440#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
441#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
442#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
443#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
444#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
445#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
446#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
447#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
448#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
449#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
450#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
451#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
452#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
453#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
454#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
455#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
456#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
457#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
458#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
459#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
460#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
461#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
462
463#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
464#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
465#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
466#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
467#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
468#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
469#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
470#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
471#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
472#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
473#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
474#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
475#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
476#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
477#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
478#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
479#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
480#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
481#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
482#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
483#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
484#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
485#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
486#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
487#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
488#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
489
490#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
491#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
492#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
493#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
494#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
495#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
496#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
497#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
498#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
499#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
500#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
501#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
502#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
503#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
504#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
505#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
506#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
507#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
508#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
509#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
510#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
511#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
512#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
513#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
514#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
515#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
516
517#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
518#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
519#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
520#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
521#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
522#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
523#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
524#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
525#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
526#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
527#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
528#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
529#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
530#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
531#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
532#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
533#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
534#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
535#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
536#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
537#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
538#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
539#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
540#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
541#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
542#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
543
544#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
545#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
546#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
547#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
548#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
549#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
550#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
551#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
552#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
553#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
554#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
555#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
556#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
557#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
558#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
559#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
560#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
561#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
562#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
563#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
564#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
565#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
566#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
567#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
568#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
569#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
570
571#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
572#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
573#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
574#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
575#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
576#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
577#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
578#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
579#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
580#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
581#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
582#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
583#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
584#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
585#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
586#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
587#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
588#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
589#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
590#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
591#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
592#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
593#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
594#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
595#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
596#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
597
598#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
599#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
600#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
601#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
602#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
603#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
604#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
605#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
606#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
607#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
608#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
609#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
610#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
611#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
612#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
613#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
614#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
615#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
616#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
617#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
618#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
619#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
620#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
621#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
622#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
623#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
624
625#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
626#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
627#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
628#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
629#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
630#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
631#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
632#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
633#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
634#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
635#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
636#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
637#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
638#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
639#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
640#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
641#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
642#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
643#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
644#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
645#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
646#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
647#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
648#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
649#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
650#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
651
652#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
653#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
654#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
655#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
656#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
657#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
658#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
659#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
660#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
661#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
662#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
663#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
664#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
665#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
666#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
667#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
668#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
669#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
670#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
671#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
672#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
673#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
674#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
675#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
676#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
677#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
678
679#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
680#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
681#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
682#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
683#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
684#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
685#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
686#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
687#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
688#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
689#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
690#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
691#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
692#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
693#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
694#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
695#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
696#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
697#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
698#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
699#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
700#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
701#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
702#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
703#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
704#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
705
706#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
707#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
708#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
709#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
710#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
711#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
712#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
713#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
714#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
715#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
716#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
717#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
718#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
719#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
720#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
721#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
722#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
723#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
724#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
725#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
726#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
727#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
728#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
729#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
730#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
731#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
732
733#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
734#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
735#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
736#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
737#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
738#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
739#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
740#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
741#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
742#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
743#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
744#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
745#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
746#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
747#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
748#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
749#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
750#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
751#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
752#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
753#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
754#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
755#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
756#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
757#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
758#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
759
760#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
761#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
762#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
763#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
764#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
765#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
766#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
767#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
768#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
769#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
770#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
771#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
772#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
773#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
774#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
775#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
776#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
777#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
778#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
779#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
780#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
781#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
782#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
783#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
784#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
785#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
786
787#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
788#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
789#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
790#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
791#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
792#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
793#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
794#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
795#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
796#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
797#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
798#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
799#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
800#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
801#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
802#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
803#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
804#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
805#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
806#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
807#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
808#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
809#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
810#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
811#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
812#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
813
814#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
815#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
816#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
817#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
818#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
819#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
820#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
821#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
822#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
823#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
824#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
825#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
826#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
827#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
828#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
829#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
830#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
831#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
832#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
833#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
834#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
835#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
836#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
837#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
838#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
839#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
840
841
842/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
843#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
844#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
845#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
846#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
847#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF)
848#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
849#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
850#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
851#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
852#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
853#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
854
855
856/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
857
858/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
859#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
860#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val)
861#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
862#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val)
863#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
864#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val)
865#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
866#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
867#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
868#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val)
869#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
870#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
871#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
872#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
873#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
874#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
875#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
876#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val)
877#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
878#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
879#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
880#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
881#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
882#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
883#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
884#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val)
885#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
886#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val)
887#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
888#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val)
889#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
890#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val)
891#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
892#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val)
893
894
895/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
896#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
897#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val)
898#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
899#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val)
900#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
901#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val)
902#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
903#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
904#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
905#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val)
906#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
907#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
908#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
909#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
910#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
911#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
912#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
913#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val)
914#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
915#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
916#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
917#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
918#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
919#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
920#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
921#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val)
922#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
923#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val)
924#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
925#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val)
926#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
927#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val)
928#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
929#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val)
930
931
932/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
933#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
934#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
935#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
936#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
937#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
938#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
939#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
940#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
941#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
942#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
943#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
944#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
945#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
946#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
947#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
948#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
949#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
950#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
951#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
952#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
953#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
954#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
955#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
956#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
957
958/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF52x processor) */
959
960/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
961#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
962#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
963#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
964#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
965#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
966#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
967#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX)
968#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val)
969
970
971/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
972#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
973#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
974#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
975#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
976#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
977#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
978#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
979#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
980#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
981#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
982#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
983#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
984#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
985#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
986
987#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
988#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
989#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
990#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
991#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
992#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
993#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
994#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
995#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
996#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
997#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
998#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
999#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
1000#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
1001
1002/* ==== end from cdefBF534.h ==== */
1003
1004/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
1005
1006#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX)
1007#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val)
1008#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX)
1009#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val)
1010#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX)
1011#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val)
1012
1013#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE)
1014#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val)
1015#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE)
1016#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val)
1017#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE)
1018#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val)
1019#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW)
1020#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val)
1021#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW)
1022#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val)
1023#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW)
1024#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val)
1025#define bfin_read_PORTF_HYSTERISIS() bfin_read16(PORTF_HYSTERISIS)
1026#define bfin_write_PORTF_HYSTERISIS(val) bfin_write16(PORTF_HYSTERISIS, val)
1027#define bfin_read_PORTG_HYSTERISIS() bfin_read16(PORTG_HYSTERISIS)
1028#define bfin_write_PORTG_HYSTERISIS(val) bfin_write16(PORTG_HYSTERISIS, val)
1029#define bfin_read_PORTH_HYSTERISIS() bfin_read16(PORTH_HYSTERISIS)
1030#define bfin_write_PORTH_HYSTERISIS(val) bfin_write16(PORTH_HYSTERISIS, val)
1031#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE)
1032#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val)
1033#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW)
1034#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val)
1035#define bfin_read_MISCPORT_HYSTERISIS() bfin_read16(MISCPORT_HYSTERISIS)
1036#define bfin_write_MISCPORT_HYSTERISIS(val) bfin_write16(MISCPORT_HYSTERISIS, val)
1037
1038/* HOST Port Registers */
1039
1040#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
1041#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
1042#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
1043#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
1044#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
1045#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
1046
1047/* Counter Registers */
1048
1049#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
1050#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
1051#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
1052#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
1053#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
1054#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
1055#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
1056#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
1057#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
1058#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
1059#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
1060#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
1061#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
1062#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
1063#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
1064#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
1065
1066/* Security Registers */
1067
1068#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
1069#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
1070#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
1071#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
1072#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
1073#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
1074
1075/* NFC Registers */
1076
1077#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
1078#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
1079#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
1080#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
1081#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
1082#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
1083#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
1084#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
1085#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
1086#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
1087#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
1088#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
1089#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
1090#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
1091#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
1092#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
1093#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
1094#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
1095#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
1096#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
1097#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
1098#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
1099#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
1100#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
1101#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
1102#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
1103#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
1104#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
1105#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
1106#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
1107#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
1108#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
1109
1110/* These need to be last due to the cdef/linux inter-dependencies */
1111#include <asm/irq.h>
1112
1113#endif /* _CDEF_BF52X_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF522.h b/arch/blackfin/mach-bf527/include/mach/defBF522.h
index cb139a254810..89f5420ee6cd 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF522.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF522.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2007-2008 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
@@ -7,12 +7,1393 @@
7#ifndef _DEF_BF522_H 7#ifndef _DEF_BF522_H
8#define _DEF_BF522_H 8#define _DEF_BF522_H
9 9
10/* Include all Core registers and bit definitions */ 10/* ************************************************************** */
11#include <asm/def_LPBlackfin.h> 11/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x */
12/* ************************************************************** */
12 13
13/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */ 14/* ==== begin from defBF534.h ==== */
14 15
15/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */ 16/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
16#include "defBF52x_base.h" 17#define PLL_CTL 0xFFC00000 /* PLL Control Register */
18#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
19#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
20#define PLL_STAT 0xFFC0000C /* PLL Status Register */
21#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
22#define CHIPID 0xFFC00014 /* Device ID Register */
23
24
25/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
26#define SWRST 0xFFC00100 /* Software Reset Register */
27#define SYSCR 0xFFC00104 /* System Configuration Register */
28#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
29
30#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
31#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
32#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
33#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
34#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
35#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
36#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
37
38/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
39#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */
40#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */
41#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */
42#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */
43#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */
44#define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */
45#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */
46
47
48/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
49#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
50#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
51#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
52
53
54/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
55#define RTC_STAT 0xFFC00300 /* RTC Status Register */
56#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
57#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
58#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
59#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
60#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
61#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
62
63
64/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
65#define UART0_THR 0xFFC00400 /* Transmit Holding register */
66#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
67#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
68#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
69#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
70#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
71#define UART0_LCR 0xFFC0040C /* Line Control Register */
72#define UART0_MCR 0xFFC00410 /* Modem Control Register */
73#define UART0_LSR 0xFFC00414 /* Line Status Register */
74#define UART0_MSR 0xFFC00418 /* Modem Status Register */
75#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
76#define UART0_GCTL 0xFFC00424 /* Global Control Register */
77
78
79/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
80#define SPI0_REGBASE 0xFFC00500
81#define SPI_CTL 0xFFC00500 /* SPI Control Register */
82#define SPI_FLG 0xFFC00504 /* SPI Flag register */
83#define SPI_STAT 0xFFC00508 /* SPI Status register */
84#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
85#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
86#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
87#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
88
89
90/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
91#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
92#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
93#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
94#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
95
96#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
97#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
98#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
99#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
100
101#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
102#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
103#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
104#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
105
106#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
107#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
108#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
109#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
110
111#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
112#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
113#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
114#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
115
116#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
117#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
118#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
119#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
120
121#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
122#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
123#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
124#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
125
126#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
127#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
128#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
129#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
130
131#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
132#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
133#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
134
135
136/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
137#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
138#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
139#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
140#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
141#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
142#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
143#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
144#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
145#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
146#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
147#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
148#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
149#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
150#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
151#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
152#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
153#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
154
155
156/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
157#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
158#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
159#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
160#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
161#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
162#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
163#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
164#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
165#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
166#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
167#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
168#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
169#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
170#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
171#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
172#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
173#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
174#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
175#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
176#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
177#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
178#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
179
180
181/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
182#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
183#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
184#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
185#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
186#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
187#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
188#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
189#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
190#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
191#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
192#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
193#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
194#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
195#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
196#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
197#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
198#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
199#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
200#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
201#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
202#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
203#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
204
205
206/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
207#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
208#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
209#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
210#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
211#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
212#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
213#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
214
215
216/* DMA Traffic Control Registers */
217#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
218#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
219
220/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
221#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
222#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
223#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
224#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
225#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
226#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
227#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
228#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
229#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
230#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
231#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
232#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
233#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
234
235#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
236#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
237#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
238#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
239#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
240#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
241#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
242#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
243#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
244#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
245#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
246#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
247#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
248
249#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
250#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
251#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
252#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
253#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
254#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
255#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
256#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
257#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
258#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
259#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
260#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
261#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
262
263#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
264#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
265#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
266#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
267#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
268#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
269#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
270#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
271#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
272#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
273#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
274#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
275#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
276
277#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
278#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
279#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
280#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
281#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
282#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
283#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
284#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
285#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
286#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
287#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
288#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
289#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
290
291#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
292#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
293#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
294#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
295#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
296#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
297#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
298#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
299#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
300#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
301#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
302#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
303#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
304
305#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
306#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
307#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
308#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
309#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
310#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
311#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
312#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
313#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
314#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
315#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
316#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
317#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
318
319#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
320#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
321#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
322#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
323#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
324#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
325#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
326#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
327#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
328#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
329#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
330#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
331#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
332
333#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
334#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
335#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
336#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
337#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
338#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
339#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
340#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
341#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
342#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
343#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
344#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
345#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
346
347#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
348#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
349#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
350#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
351#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
352#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
353#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
354#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
355#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
356#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
357#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
358#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
359#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
360
361#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
362#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
363#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
364#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
365#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
366#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
367#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
368#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
369#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
370#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
371#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
372#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
373#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
374
375#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
376#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
377#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
378#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
379#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
380#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
381#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
382#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
383#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
384#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
385#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
386#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
387#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
388
389#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
390#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
391#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
392#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
393#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
394#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
395#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
396#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
397#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
398#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
399#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
400#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
401#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
402
403#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
404#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
405#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
406#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
407#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
408#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
409#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
410#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
411#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
412#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
413#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
414#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
415#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
416
417#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
418#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
419#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
420#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
421#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
422#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
423#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
424#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
425#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
426#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
427#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
428#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
429#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
430
431#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
432#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
433#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
434#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
435#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
436#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
437#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
438#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
439#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
440#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
441#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
442#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
443#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
444
445
446/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
447#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
448#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
449#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
450#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
451#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
452
453
454/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
455#define TWI0_REGBASE 0xFFC01400
456#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
457#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */
458#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
459#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
460#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
461#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
462#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
463#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
464#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
465#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
466#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
467#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
468#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
469#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
470#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
471#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
472
473
474/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
475#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
476#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
477#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
478#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
479#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
480#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
481#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
482#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
483#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
484#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
485#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
486#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
487#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
488#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
489#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
490#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
491#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
492
493
494/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
495#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
496#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
497#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
498#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
499#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
500#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
501#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
502#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
503#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
504#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
505#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
506#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
507#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
508#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
509#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
510#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
511#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
512
513
514/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
515#define UART1_THR 0xFFC02000 /* Transmit Holding register */
516#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
517#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
518#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
519#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
520#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
521#define UART1_LCR 0xFFC0200C /* Line Control Register */
522#define UART1_MCR 0xFFC02010 /* Modem Control Register */
523#define UART1_LSR 0xFFC02014 /* Line Status Register */
524#define UART1_MSR 0xFFC02018 /* Modem Status Register */
525#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
526#define UART1_GCTL 0xFFC02024 /* Global Control Register */
527
528
529/* Omit CAN register sets from the defBF534.h (CAN is not in the ADSP-BF52x processor) */
530
531/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
532#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
533#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
534#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
535#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
536
537
538/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
539#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
540#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
541#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
542#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */
543#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
544#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
545#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
546
547#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
548#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
549#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
550#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */
551#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
552#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
553#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
554
555/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
556#define PORTF_MUX 0xFFC03210 /* Port F mux control */
557#define PORTG_MUX 0xFFC03214 /* Port G mux control */
558#define PORTH_MUX 0xFFC03218 /* Port H mux control */
559#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */
560#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */
561#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */
562#define PORTF_SLEW 0xFFC03230 /* Port F slew control */
563#define PORTG_SLEW 0xFFC03234 /* Port G slew control */
564#define PORTH_SLEW 0xFFC03238 /* Port H slew control */
565#define PORTF_HYSTERISIS 0xFFC03240 /* Port F Schmitt trigger control */
566#define PORTG_HYSTERISIS 0xFFC03244 /* Port G Schmitt trigger control */
567#define PORTH_HYSTERISIS 0xFFC03248 /* Port H Schmitt trigger control */
568#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */
569#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */
570#define MISCPORT_HYSTERISIS 0xFFC03288 /* Misc Port Schmitt trigger control */
571
572
573/***********************************************************************************
574** System MMR Register Bits And Macros
575**
576** Disclaimer: All macros are intended to make C and Assembly code more readable.
577** Use these macros carefully, as any that do left shifts for field
578** depositing will result in the lower order bits being destroyed. Any
579** macro that shifts left to properly position the bit-field should be
580** used as part of an OR to initialize a register and NOT as a dynamic
581** modifier UNLESS the lower order bits are saved and ORed back in when
582** the macro is used.
583*************************************************************************************/
584
585/* CHIPID Masks */
586#define CHIPID_VERSION 0xF0000000
587#define CHIPID_FAMILY 0x0FFFF000
588#define CHIPID_MANUFACTURE 0x00000FFE
589
590/* SWRST Masks */
591#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
592#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
593#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
594#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
595#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
596
597/* SYSCR Masks */
598#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
599#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
600
601
602/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
603/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
604
605#if 0
606#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */
607
608#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
609#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
610#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */
611#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */
612#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */
613#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */
614#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */
615
616#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */
617#define IRQ_TWI 0x00000200 /* TWI Interrupt */
618#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */
619#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */
620#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */
621#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */
622#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */
623#define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */
624
625#define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */
626#define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */
627#define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */
628#define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */
629#define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */
630#define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */
631#define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */
632#define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */
633#define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */
634#define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */
635
636#define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */
637#define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */
638#define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */
639#define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */
640#define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */
641#define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */
642#define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
643#define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */
644#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
645#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */
646#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */
647#endif
648
649/* SIC_IAR0 Macros */
650#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
651#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
652#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
653#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
654#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
655#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
656#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
657#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
658
659/* SIC_IAR1 Macros */
660#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
661#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
662#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
663#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
664#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
665#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
666#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
667#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
668
669/* SIC_IAR2 Macros */
670#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
671#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
672#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
673#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
674#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
675#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
676#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
677#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
678
679/* SIC_IAR3 Macros */
680#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
681#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
682#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
683#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
684#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
685#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
686#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
687#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
688
689
690/* SIC_IMASK Masks */
691#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
692#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
693#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
694#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
695
696/* SIC_IWR Masks */
697#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
698#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
699#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
700#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
701
702/* **************** GENERAL PURPOSE TIMER MASKS **********************/
703/* TIMER_ENABLE Masks */
704#define TIMEN0 0x0001 /* Enable Timer 0 */
705#define TIMEN1 0x0002 /* Enable Timer 1 */
706#define TIMEN2 0x0004 /* Enable Timer 2 */
707#define TIMEN3 0x0008 /* Enable Timer 3 */
708#define TIMEN4 0x0010 /* Enable Timer 4 */
709#define TIMEN5 0x0020 /* Enable Timer 5 */
710#define TIMEN6 0x0040 /* Enable Timer 6 */
711#define TIMEN7 0x0080 /* Enable Timer 7 */
712
713/* TIMER_DISABLE Masks */
714#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
715#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
716#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
717#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
718#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
719#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
720#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
721#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
722
723/* TIMER_STATUS Masks */
724#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
725#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
726#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
727#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
728#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
729#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
730#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
731#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
732#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
733#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
734#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
735#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
736#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
737#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
738#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
739#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
740#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
741#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
742#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
743#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
744#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
745#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
746#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
747#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
748
749/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
750#define TOVL_ERR0 TOVF_ERR0
751#define TOVL_ERR1 TOVF_ERR1
752#define TOVL_ERR2 TOVF_ERR2
753#define TOVL_ERR3 TOVF_ERR3
754#define TOVL_ERR4 TOVF_ERR4
755#define TOVL_ERR5 TOVF_ERR5
756#define TOVL_ERR6 TOVF_ERR6
757#define TOVL_ERR7 TOVF_ERR7
758
759/* TIMERx_CONFIG Masks */
760#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
761#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
762#define EXT_CLK 0x0003 /* External Clock Mode */
763#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
764#define PERIOD_CNT 0x0008 /* Period Count */
765#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
766#define TIN_SEL 0x0020 /* Timer Input Select */
767#define OUT_DIS 0x0040 /* Output Pad Disable */
768#define CLK_SEL 0x0080 /* Timer Clock Select */
769#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
770#define EMU_RUN 0x0200 /* Emulation Behavior Select */
771#define ERR_TYP 0xC000 /* Error Type */
772
773/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
774/* EBIU_AMGCTL Masks */
775#define AMCKEN 0x0001 /* Enable CLKOUT */
776#define AMBEN_NONE 0x0000 /* All Banks Disabled */
777#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
778#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
779#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
780#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
781
782/* EBIU_AMBCTL0 Masks */
783#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
784#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
785#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
786#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
787#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
788#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
789#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
790#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
791#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
792#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
793#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
794#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
795#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
796#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
797#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
798#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
799#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
800#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
801#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
802#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
803#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
804#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
805#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
806#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
807#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
808#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
809#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
810#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
811#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
812#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
813#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
814#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
815#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
816#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
817#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
818#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
819#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
820#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
821#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
822#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
823#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
824#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
825#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
826#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
827
828#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
829#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
830#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
831#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
832#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
833#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
834#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
835#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
836#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
837#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
838#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
839#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
840#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
841#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
842#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
843#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
844#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
845#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
846#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
847#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
848#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
849#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
850#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
851#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
852#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
853#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
854#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
855#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
856#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
857#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
858#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
859#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
860#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
861#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
862#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
863#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
864#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
865#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
866#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
867#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
868#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
869#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
870#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
871#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
872
873/* EBIU_AMBCTL1 Masks */
874#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
875#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
876#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
877#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
878#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
879#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
880#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
881#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
882#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
883#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
884#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
885#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
886#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
887#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
888#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
889#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
890#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
891#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
892#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
893#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
894#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
895#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
896#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
897#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
898#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
899#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
900#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
901#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
902#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
903#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
904#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
905#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
906#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
907#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
908#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
909#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
910#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
911#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
912#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
913#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
914#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
915#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
916#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
917#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
918
919#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
920#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
921#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
922#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
923#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
924#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
925#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
926#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
927#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
928#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
929#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
930#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
931#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
932#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
933#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
934#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
935#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
936#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
937#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
938#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
939#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
940#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
941#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
942#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
943#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
944#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
945#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
946#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
947#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
948#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
949#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
950#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
951#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
952#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
953#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
954#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
955#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
956#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
957#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
958#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
959#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
960#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
961#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
962#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
963
964
965/* ********************** SDRAM CONTROLLER MASKS **********************************************/
966/* EBIU_SDGCTL Masks */
967#define SCTLE 0x00000001 /* Enable SDRAM Signals */
968#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
969#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
970#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
971#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
972#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
973#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
974#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
975#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
976#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
977#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
978#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
979#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
980#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
981#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
982#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
983#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
984#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
985#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
986#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
987#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
988#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
989#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
990#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
991#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
992#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
993#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
994#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
995#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
996#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
997#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
998#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
999#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
1000#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
1001#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
1002#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
1003#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
1004#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
1005#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
1006#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
1007#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
1008#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
1009#define EBUFE 0x02000000 /* Enable External Buffering Timing */
1010#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
1011#define EMREN 0x10000000 /* Extended Mode Register Enable */
1012#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
1013#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
1014
1015/* EBIU_SDBCTL Masks */
1016#define EBE 0x0001 /* Enable SDRAM External Bank */
1017#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
1018#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
1019#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
1020#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
1021#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
1022#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
1023#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
1024#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
1025#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
1026#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
1027
1028/* EBIU_SDSTAT Masks */
1029#define SDCI 0x0001 /* SDRAM Controller Idle */
1030#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
1031#define SDPUA 0x0004 /* SDRAM Power-Up Active */
1032#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
1033#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
1034#define BGSTAT 0x0020 /* Bus Grant Status */
1035
1036
1037/* ************************** DMA CONTROLLER MASKS ********************************/
1038
1039/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
1040#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
1041#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
1042#define PMAP_PPI 0x0000 /* PPI Port DMA */
1043#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
1044#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
1045#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
1046#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
1047#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
1048#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
1049#define PMAP_SPI 0x7000 /* SPI Port DMA */
1050#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
1051#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
1052#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
1053#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
1054
1055/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
1056/* PPI_CONTROL Masks */
1057#define PORT_EN 0x0001 /* PPI Port Enable */
1058#define PORT_DIR 0x0002 /* PPI Port Direction */
1059#define XFR_TYPE 0x000C /* PPI Transfer Type */
1060#define PORT_CFG 0x0030 /* PPI Port Configuration */
1061#define FLD_SEL 0x0040 /* PPI Active Field Select */
1062#define PACK_EN 0x0080 /* PPI Packing Mode */
1063#define DMA32 0x0100 /* PPI 32-bit DMA Enable */
1064#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
1065#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
1066#define DLEN_8 0x0000 /* Data Length = 8 Bits */
1067#define DLEN_10 0x0800 /* Data Length = 10 Bits */
1068#define DLEN_11 0x1000 /* Data Length = 11 Bits */
1069#define DLEN_12 0x1800 /* Data Length = 12 Bits */
1070#define DLEN_13 0x2000 /* Data Length = 13 Bits */
1071#define DLEN_14 0x2800 /* Data Length = 14 Bits */
1072#define DLEN_15 0x3000 /* Data Length = 15 Bits */
1073#define DLEN_16 0x3800 /* Data Length = 16 Bits */
1074#define DLENGTH 0x3800 /* PPI Data Length */
1075#define POLC 0x4000 /* PPI Clock Polarity */
1076#define POLS 0x8000 /* PPI Frame Sync Polarity */
1077
1078/* PPI_STATUS Masks */
1079#define FLD 0x0400 /* Field Indicator */
1080#define FT_ERR 0x0800 /* Frame Track Error */
1081#define OVR 0x1000 /* FIFO Overflow Error */
1082#define UNDR 0x2000 /* FIFO Underrun Error */
1083#define ERR_DET 0x4000 /* Error Detected Indicator */
1084#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
1085
1086
1087/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
1088/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
1089#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
1090#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
1091
1092/* TWI_PRESCALE Masks */
1093#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
1094#define TWI_ENA 0x0080 /* TWI Enable */
1095#define SCCB 0x0200 /* SCCB Compatibility Enable */
1096
1097/* TWI_SLAVE_CTL Masks */
1098#define SEN 0x0001 /* Slave Enable */
1099#define SADD_LEN 0x0002 /* Slave Address Length */
1100#define STDVAL 0x0004 /* Slave Transmit Data Valid */
1101#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
1102#define GEN 0x0010 /* General Call Adrress Matching Enabled */
1103
1104/* TWI_SLAVE_STAT Masks */
1105#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
1106#define GCALL 0x0002 /* General Call Indicator */
1107
1108/* TWI_MASTER_CTL Masks */
1109#define MEN 0x0001 /* Master Mode Enable */
1110#define MADD_LEN 0x0002 /* Master Address Length */
1111#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
1112#define FAST 0x0008 /* Use Fast Mode Timing Specs */
1113#define STOP 0x0010 /* Issue Stop Condition */
1114#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
1115#define DCNT 0x3FC0 /* Data Bytes To Transfer */
1116#define SDAOVR 0x4000 /* Serial Data Override */
1117#define SCLOVR 0x8000 /* Serial Clock Override */
1118
1119/* TWI_MASTER_STAT Masks */
1120#define MPROG 0x0001 /* Master Transfer In Progress */
1121#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
1122#define ANAK 0x0004 /* Address Not Acknowledged */
1123#define DNAK 0x0008 /* Data Not Acknowledged */
1124#define BUFRDERR 0x0010 /* Buffer Read Error */
1125#define BUFWRERR 0x0020 /* Buffer Write Error */
1126#define SDASEN 0x0040 /* Serial Data Sense */
1127#define SCLSEN 0x0080 /* Serial Clock Sense */
1128#define BUSBUSY 0x0100 /* Bus Busy Indicator */
1129
1130/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
1131#define SINIT 0x0001 /* Slave Transfer Initiated */
1132#define SCOMP 0x0002 /* Slave Transfer Complete */
1133#define SERR 0x0004 /* Slave Transfer Error */
1134#define SOVF 0x0008 /* Slave Overflow */
1135#define MCOMP 0x0010 /* Master Transfer Complete */
1136#define MERR 0x0020 /* Master Transfer Error */
1137#define XMTSERV 0x0040 /* Transmit FIFO Service */
1138#define RCVSERV 0x0080 /* Receive FIFO Service */
1139
1140/* TWI_FIFO_CTRL Masks */
1141#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
1142#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
1143#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
1144#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
1145
1146/* TWI_FIFO_STAT Masks */
1147#define XMTSTAT 0x0003 /* Transmit FIFO Status */
1148#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
1149#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
1150#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
1151
1152#define RCVSTAT 0x000C /* Receive FIFO Status */
1153#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
1154#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
1155#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
1156
1157
1158/* Omit CAN masks from defBF534.h */
1159
1160/* ******************* PIN CONTROL REGISTER MASKS ************************/
1161/* PORT_MUX Masks */
1162#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
1163#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
1164#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
1165
1166#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
1167#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
1168#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
1169#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
1170
1171#define PFDE 0x0008 /* Port F DMA Request Enable */
1172#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
1173#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
1174
1175#define PFTE 0x0010 /* Port F Timer Enable */
1176#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
1177#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
1178
1179#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
1180#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
1181#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
1182
1183#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
1184#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
1185#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
1186
1187#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
1188#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
1189#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
1190
1191#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
1192#define PFFE_TIMER 0x0000 /* Enable TMR2 */
1193#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
1194
1195#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
1196#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
1197#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
1198
1199#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
1200#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
1201#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
1202
1203#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
1204#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
1205#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
1206
1207
1208/* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/
1209/* HDMAx_CTL Masks */
1210#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */
1211#define REP 0x0002 /* HDMA Request Polarity */
1212#define UTE 0x0004 /* Urgency Threshold Enable */
1213#define OIE 0x0010 /* Overflow Interrupt Enable */
1214#define BDIE 0x0020 /* Block Done Interrupt Enable */
1215#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */
1216#define DRQ 0x0300 /* HDMA Request Type */
1217#define DRQ_NONE 0x0000 /* No Request */
1218#define DRQ_SINGLE 0x0100 /* Channels Request Single */
1219#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */
1220#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */
1221#define RBC 0x1000 /* Reload BCNT With IBCNT */
1222#define PS 0x2000 /* HDMA Pin Status */
1223#define OI 0x4000 /* Overflow Interrupt Generated */
1224#define BDI 0x8000 /* Block Done Interrupt Generated */
1225
1226/* entry addresses of the user-callable Boot ROM functions */
1227
1228#define _BOOTROM_RESET 0xEF000000
1229#define _BOOTROM_FINAL_INIT 0xEF000002
1230#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
1231#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
1232#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
1233#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
1234#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
1235#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
1236#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
1237
1238/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
1239#define PGDE_UART PFDE_UART
1240#define PGDE_DMA PFDE_DMA
1241#define CKELOW SCKELOW
1242
1243/* ==== end from defBF534.h ==== */
1244
1245/* HOST Port Registers */
1246
1247#define HOST_CONTROL 0xffc03400 /* HOST Control Register */
1248#define HOST_STATUS 0xffc03404 /* HOST Status Register */
1249#define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */
1250
1251/* Counter Registers */
1252
1253#define CNT_CONFIG 0xffc03500 /* Configuration Register */
1254#define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */
1255#define CNT_STATUS 0xffc03508 /* Status Register */
1256#define CNT_COMMAND 0xffc0350c /* Command Register */
1257#define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */
1258#define CNT_COUNTER 0xffc03514 /* Counter Register */
1259#define CNT_MAX 0xffc03518 /* Maximal Count Register */
1260#define CNT_MIN 0xffc0351c /* Minimal Count Register */
1261
1262/* OTP/FUSE Registers */
1263
1264#define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */
1265#define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */
1266#define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */
1267#define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */
1268
1269/* Security Registers */
1270
1271#define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */
1272#define SECURE_CONTROL 0xffc03624 /* Secure Control */
1273#define SECURE_STATUS 0xffc03628 /* Secure Status */
1274
1275/* OTP Read/Write Data Buffer Registers */
1276
1277#define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1278#define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1279#define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1280#define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1281
1282/* NFC Registers */
1283
1284#define NFC_CTL 0xffc03700 /* NAND Control Register */
1285#define NFC_STAT 0xffc03704 /* NAND Status Register */
1286#define NFC_IRQSTAT 0xffc03708 /* NAND Interrupt Status Register */
1287#define NFC_IRQMASK 0xffc0370c /* NAND Interrupt Mask Register */
1288#define NFC_ECC0 0xffc03710 /* NAND ECC Register 0 */
1289#define NFC_ECC1 0xffc03714 /* NAND ECC Register 1 */
1290#define NFC_ECC2 0xffc03718 /* NAND ECC Register 2 */
1291#define NFC_ECC3 0xffc0371c /* NAND ECC Register 3 */
1292#define NFC_COUNT 0xffc03720 /* NAND ECC Count Register */
1293#define NFC_RST 0xffc03724 /* NAND ECC Reset Register */
1294#define NFC_PGCTL 0xffc03728 /* NAND Page Control Register */
1295#define NFC_READ 0xffc0372c /* NAND Read Data Register */
1296#define NFC_ADDR 0xffc03740 /* NAND Address Register */
1297#define NFC_CMD 0xffc03744 /* NAND Command Register */
1298#define NFC_DATA_WR 0xffc03748 /* NAND Data Write Register */
1299#define NFC_DATA_RD 0xffc0374c /* NAND Data Read Register */
1300
1301/* ********************************************************** */
1302/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
1303/* and MULTI BIT READ MACROS */
1304/* ********************************************************** */
1305
1306/* Bit masks for HOST_CONTROL */
1307
1308#define HOST_CNTR_HOST_EN 0x1 /* Host Enable */
1309#define HOST_CNTR_nHOST_EN 0x0
1310#define HOST_CNTR_HOST_END 0x2 /* Host Endianess */
1311#define HOST_CNTR_nHOST_END 0x0
1312#define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */
1313#define HOST_CNTR_nDATA_SIZE 0x0
1314#define HOST_CNTR_HOST_RST 0x8 /* Host Reset */
1315#define HOST_CNTR_nHOST_RST 0x0
1316#define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */
1317#define HOST_CNTR_nHRDY_OVR 0x0
1318#define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */
1319#define HOST_CNTR_nINT_MODE 0x0
1320#define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */
1321#define HOST_CNTR_ nBT_EN 0x0
1322#define HOST_CNTR_EHW 0x100 /* Enable Host Write */
1323#define HOST_CNTR_nEHW 0x0
1324#define HOST_CNTR_EHR 0x200 /* Enable Host Read */
1325#define HOST_CNTR_nEHR 0x0
1326#define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */
1327#define HOST_CNTR_nBDR 0x0
1328
1329/* Bit masks for HOST_STATUS */
1330
1331#define HOST_STAT_READY 0x1 /* DMA Ready */
1332#define HOST_STAT_nREADY 0x0
1333#define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */
1334#define HOST_STAT_nFIFOFULL 0x0
1335#define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */
1336#define HOST_STAT_nFIFOEMPTY 0x0
1337#define HOST_STAT_COMPLETE 0x8 /* DMA Complete */
1338#define HOST_STAT_nCOMPLETE 0x0
1339#define HOST_STAT_HSHK 0x10 /* Host Handshake */
1340#define HOST_STAT_nHSHK 0x0
1341#define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */
1342#define HOST_STAT_nTIMEOUT 0x0
1343#define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */
1344#define HOST_STAT_nHIRQ 0x0
1345#define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */
1346#define HOST_STAT_nALLOW_CNFG 0x0
1347#define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */
1348#define HOST_STAT_nDMA_DIR 0x0
1349#define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */
1350#define HOST_STAT_nBTE 0x0
1351#define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */
1352#define HOST_STAT_nHOSTRD_DONE 0x0
1353
1354/* Bit masks for HOST_TIMEOUT */
1355
1356#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */
1357
1358/* Bit masks for SECURE_SYSSWT */
1359
1360#define EMUDABL 0x1 /* Emulation Disable. */
1361#define nEMUDABL 0x0
1362#define RSTDABL 0x2 /* Reset Disable */
1363#define nRSTDABL 0x0
1364#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
1365#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
1366#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
1367#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
1368#define nDMA0OVR 0x0
1369#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
1370#define nDMA1OVR 0x0
1371#define EMUOVR 0x4000 /* Emulation Override */
1372#define nEMUOVR 0x0
1373#define OTPSEN 0x8000 /* OTP Secrets Enable. */
1374#define nOTPSEN 0x0
1375#define L2DABL 0x70000 /* L2 Memory Disable. */
1376
1377/* Bit masks for SECURE_CONTROL */
1378
1379#define SECURE0 0x1 /* SECURE 0 */
1380#define nSECURE0 0x0
1381#define SECURE1 0x2 /* SECURE 1 */
1382#define nSECURE1 0x0
1383#define SECURE2 0x4 /* SECURE 2 */
1384#define nSECURE2 0x0
1385#define SECURE3 0x8 /* SECURE 3 */
1386#define nSECURE3 0x0
1387
1388/* Bit masks for SECURE_STATUS */
1389
1390#define SECMODE 0x3 /* Secured Mode Control State */
1391#define NMI 0x4 /* Non Maskable Interrupt */
1392#define nNMI 0x0
1393#define AFVALID 0x8 /* Authentication Firmware Valid */
1394#define nAFVALID 0x0
1395#define AFEXIT 0x10 /* Authentication Firmware Exit */
1396#define nAFEXIT 0x0
1397#define SECSTAT 0xe0 /* Secure Status */
17 1398
18#endif /* _DEF_BF522_H */ 1399#endif /* _DEF_BF522_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF525.h b/arch/blackfin/mach-bf527/include/mach/defBF525.h
index c136f7032962..cc383adfdffa 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF525.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF525.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2007-2008 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF527.h b/arch/blackfin/mach-bf527/include/mach/defBF527.h
index 4dd58fb33156..05369a92fbc8 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF527.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF527.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2007-2008 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
deleted file mode 100644
index 09475034c6a1..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
+++ /dev/null
@@ -1,1506 +0,0 @@
1/*
2 * Copyright 2007-2008 Analog Devices Inc.
3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */
6
7#ifndef _DEF_BF52X_H
8#define _DEF_BF52X_H
9
10
11/* ************************************************************** */
12/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x */
13/* ************************************************************** */
14
15/* ==== begin from defBF534.h ==== */
16
17/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
18#define PLL_CTL 0xFFC00000 /* PLL Control Register */
19#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
20#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
21#define PLL_STAT 0xFFC0000C /* PLL Status Register */
22#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
23#define CHIPID 0xFFC00014 /* Device ID Register */
24
25
26/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
27#define SWRST 0xFFC00100 /* Software Reset Register */
28#define SYSCR 0xFFC00104 /* System Configuration Register */
29#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
30
31#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
32#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
33#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
34#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
35#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
36#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
37#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
38
39/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
40#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */
41#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */
42#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */
43#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */
44#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */
45#define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */
46#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */
47
48
49/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
50#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
51#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
52#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
53
54
55/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
56#define RTC_STAT 0xFFC00300 /* RTC Status Register */
57#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
58#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
59#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
60#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
61#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
62#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
63
64
65/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
66#define UART0_THR 0xFFC00400 /* Transmit Holding register */
67#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
68#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
69#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
70#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
71#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
72#define UART0_LCR 0xFFC0040C /* Line Control Register */
73#define UART0_MCR 0xFFC00410 /* Modem Control Register */
74#define UART0_LSR 0xFFC00414 /* Line Status Register */
75#define UART0_MSR 0xFFC00418 /* Modem Status Register */
76#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
77#define UART0_GCTL 0xFFC00424 /* Global Control Register */
78
79
80/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
81#define SPI0_REGBASE 0xFFC00500
82#define SPI_CTL 0xFFC00500 /* SPI Control Register */
83#define SPI_FLG 0xFFC00504 /* SPI Flag register */
84#define SPI_STAT 0xFFC00508 /* SPI Status register */
85#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
86#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
87#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
88#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
89
90
91/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
92#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
93#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
94#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
95#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
96
97#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
98#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
99#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
100#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
101
102#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
103#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
104#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
105#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
106
107#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
108#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
109#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
110#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
111
112#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
113#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
114#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
115#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
116
117#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
118#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
119#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
120#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
121
122#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
123#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
124#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
125#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
126
127#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
128#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
129#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
130#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
131
132#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
133#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
134#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
135
136
137/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
138#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
139#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
140#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
141#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
142#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
143#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
144#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
145#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
146#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
147#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
148#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
149#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
150#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
151#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
152#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
153#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
154#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
155
156
157/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
158#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
159#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
160#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
161#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
162#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
163#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
164#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
165#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
166#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
167#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
168#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
169#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
170#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
171#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
172#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
173#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
174#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
175#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
176#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
177#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
178#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
179#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
180
181
182/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
183#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
184#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
185#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
186#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
187#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
188#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
189#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
190#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
191#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
192#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
193#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
194#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
195#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
196#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
197#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
198#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
199#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
200#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
201#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
202#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
203#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
204#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
205
206
207/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
208#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
209#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
210#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
211#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
212#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
213#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
214#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
215
216
217/* DMA Traffic Control Registers */
218#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
219#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
220
221/* Alternate deprecated register names (below) provided for backwards code compatibility */
222#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
223#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
224
225/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
226#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
227#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
228#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
229#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
230#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
231#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
232#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
233#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
234#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
235#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
236#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
237#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
238#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
239
240#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
241#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
242#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
243#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
244#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
245#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
246#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
247#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
248#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
249#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
250#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
251#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
252#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
253
254#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
255#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
256#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
257#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
258#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
259#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
260#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
261#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
262#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
263#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
264#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
265#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
266#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
267
268#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
269#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
270#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
271#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
272#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
273#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
274#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
275#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
276#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
277#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
278#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
279#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
280#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
281
282#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
283#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
284#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
285#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
286#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
287#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
288#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
289#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
290#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
291#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
292#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
293#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
294#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
295
296#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
297#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
298#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
299#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
300#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
301#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
302#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
303#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
304#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
305#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
306#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
307#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
308#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
309
310#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
311#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
312#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
313#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
314#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
315#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
316#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
317#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
318#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
319#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
320#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
321#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
322#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
323
324#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
325#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
326#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
327#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
328#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
329#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
330#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
331#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
332#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
333#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
334#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
335#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
336#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
337
338#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
339#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
340#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
341#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
342#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
343#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
344#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
345#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
346#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
347#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
348#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
349#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
350#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
351
352#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
353#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
354#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
355#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
356#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
357#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
358#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
359#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
360#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
361#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
362#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
363#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
364#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
365
366#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
367#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
368#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
369#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
370#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
371#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
372#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
373#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
374#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
375#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
376#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
377#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
378#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
379
380#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
381#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
382#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
383#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
384#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
385#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
386#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
387#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
388#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
389#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
390#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
391#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
392#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
393
394#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
395#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
396#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
397#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
398#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
399#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
400#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
401#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
402#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
403#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
404#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
405#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
406#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
407
408#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
409#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
410#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
411#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
412#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
413#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
414#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
415#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
416#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
417#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
418#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
419#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
420#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
421
422#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
423#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
424#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
425#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
426#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
427#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
428#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
429#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
430#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
431#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
432#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
433#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
434#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
435
436#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
437#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
438#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
439#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
440#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
441#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
442#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
443#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
444#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
445#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
446#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
447#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
448#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
449
450
451/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
452#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
453#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
454#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
455#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
456#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
457
458
459/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
460#define TWI0_REGBASE 0xFFC01400
461#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
462#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */
463#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
464#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
465#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
466#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
467#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
468#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
469#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
470#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
471#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
472#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
473#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
474#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
475#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
476#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
477
478
479/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
480#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
481#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
482#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
483#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
484#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
485#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
486#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
487#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
488#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
489#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
490#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
491#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
492#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
493#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
494#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
495#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
496#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
497
498
499/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
500#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
501#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
502#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
503#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
504#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
505#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
506#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
507#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
508#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
509#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
510#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
511#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
512#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
513#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
514#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
515#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
516#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
517
518
519/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
520#define UART1_THR 0xFFC02000 /* Transmit Holding register */
521#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
522#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
523#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
524#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
525#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
526#define UART1_LCR 0xFFC0200C /* Line Control Register */
527#define UART1_MCR 0xFFC02010 /* Modem Control Register */
528#define UART1_LSR 0xFFC02014 /* Line Status Register */
529#define UART1_MSR 0xFFC02018 /* Modem Status Register */
530#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
531#define UART1_GCTL 0xFFC02024 /* Global Control Register */
532
533
534/* Omit CAN register sets from the defBF534.h (CAN is not in the ADSP-BF52x processor) */
535
536/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
537#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
538#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
539#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
540#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
541
542
543/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
544#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
545#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
546#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
547#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */
548#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
549#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
550#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
551
552#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
553#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
554#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
555#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */
556#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
557#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
558#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
559
560/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
561#define PORTF_MUX 0xFFC03210 /* Port F mux control */
562#define PORTG_MUX 0xFFC03214 /* Port G mux control */
563#define PORTH_MUX 0xFFC03218 /* Port H mux control */
564#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */
565#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */
566#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */
567#define PORTF_SLEW 0xFFC03230 /* Port F slew control */
568#define PORTG_SLEW 0xFFC03234 /* Port G slew control */
569#define PORTH_SLEW 0xFFC03238 /* Port H slew control */
570#define PORTF_HYSTERISIS 0xFFC03240 /* Port F Schmitt trigger control */
571#define PORTG_HYSTERISIS 0xFFC03244 /* Port G Schmitt trigger control */
572#define PORTH_HYSTERISIS 0xFFC03248 /* Port H Schmitt trigger control */
573#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */
574#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */
575#define MISCPORT_HYSTERISIS 0xFFC03288 /* Misc Port Schmitt trigger control */
576
577
578/***********************************************************************************
579** System MMR Register Bits And Macros
580**
581** Disclaimer: All macros are intended to make C and Assembly code more readable.
582** Use these macros carefully, as any that do left shifts for field
583** depositing will result in the lower order bits being destroyed. Any
584** macro that shifts left to properly position the bit-field should be
585** used as part of an OR to initialize a register and NOT as a dynamic
586** modifier UNLESS the lower order bits are saved and ORed back in when
587** the macro is used.
588*************************************************************************************/
589
590/* CHIPID Masks */
591#define CHIPID_VERSION 0xF0000000
592#define CHIPID_FAMILY 0x0FFFF000
593#define CHIPID_MANUFACTURE 0x00000FFE
594
595/* SWRST Masks */
596#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
597#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
598#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
599#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
600#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
601
602/* SYSCR Masks */
603#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
604#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
605
606
607/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
608/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
609
610#if 0
611#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */
612
613#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
614#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
615#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */
616#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */
617#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */
618#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */
619#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */
620
621#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */
622#define IRQ_TWI 0x00000200 /* TWI Interrupt */
623#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */
624#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */
625#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */
626#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */
627#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */
628#define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */
629
630#define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */
631#define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */
632#define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */
633#define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */
634#define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */
635#define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */
636#define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */
637#define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */
638#define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */
639#define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */
640
641#define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */
642#define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */
643#define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */
644#define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */
645#define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */
646#define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */
647#define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
648#define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */
649#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
650#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */
651#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */
652#endif
653
654/* SIC_IAR0 Macros */
655#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
656#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
657#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
658#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
659#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
660#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
661#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
662#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
663
664/* SIC_IAR1 Macros */
665#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
666#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
667#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
668#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
669#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
670#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
671#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
672#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
673
674/* SIC_IAR2 Macros */
675#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
676#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
677#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
678#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
679#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
680#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
681#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
682#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
683
684/* SIC_IAR3 Macros */
685#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
686#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
687#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
688#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
689#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
690#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
691#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
692#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
693
694
695/* SIC_IMASK Masks */
696#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
697#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
698#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
699#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
700
701/* SIC_IWR Masks */
702#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
703#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
704#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
705#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
706
707
708/* ************** UART CONTROLLER MASKS *************************/
709/* UARTx_LCR Masks */
710#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
711#define STB 0x04 /* Stop Bits */
712#define PEN 0x08 /* Parity Enable */
713#define EPS 0x10 /* Even Parity Select */
714#define STP 0x20 /* Stick Parity */
715#define SB 0x40 /* Set Break */
716#define DLAB 0x80 /* Divisor Latch Access */
717
718/* UARTx_MCR Mask */
719#define LOOP_ENA 0x10 /* Loopback Mode Enable */
720#define LOOP_ENA_P 0x04
721
722/* UARTx_LSR Masks */
723#define DR 0x01 /* Data Ready */
724#define OE 0x02 /* Overrun Error */
725#define PE 0x04 /* Parity Error */
726#define FE 0x08 /* Framing Error */
727#define BI 0x10 /* Break Interrupt */
728#define THRE 0x20 /* THR Empty */
729#define TEMT 0x40 /* TSR and UART_THR Empty */
730
731/* UARTx_IER Masks */
732#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
733#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
734#define ELSI 0x04 /* Enable RX Status Interrupt */
735
736/* UARTx_IIR Masks */
737#define NINT 0x01 /* Pending Interrupt */
738#define IIR_TX_READY 0x02 /* UART_THR empty */
739#define IIR_RX_READY 0x04 /* Receive data ready */
740#define IIR_LINE_CHANGE 0x06 /* Receive line status */
741#define IIR_STATUS 0x06 /* Highest Priority Pending Interrupt */
742
743/* UARTx_GCTL Masks */
744#define UCEN 0x01 /* Enable UARTx Clocks */
745#define IREN 0x02 /* Enable IrDA Mode */
746#define TPOLC 0x04 /* IrDA TX Polarity Change */
747#define RPOLC 0x08 /* IrDA RX Polarity Change */
748#define FPE 0x10 /* Force Parity Error On Transmit */
749#define FFE 0x20 /* Force Framing Error On Transmit */
750
751
752/* **************** GENERAL PURPOSE TIMER MASKS **********************/
753/* TIMER_ENABLE Masks */
754#define TIMEN0 0x0001 /* Enable Timer 0 */
755#define TIMEN1 0x0002 /* Enable Timer 1 */
756#define TIMEN2 0x0004 /* Enable Timer 2 */
757#define TIMEN3 0x0008 /* Enable Timer 3 */
758#define TIMEN4 0x0010 /* Enable Timer 4 */
759#define TIMEN5 0x0020 /* Enable Timer 5 */
760#define TIMEN6 0x0040 /* Enable Timer 6 */
761#define TIMEN7 0x0080 /* Enable Timer 7 */
762
763/* TIMER_DISABLE Masks */
764#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
765#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
766#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
767#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
768#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
769#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
770#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
771#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
772
773/* TIMER_STATUS Masks */
774#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
775#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
776#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
777#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
778#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
779#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
780#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
781#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
782#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
783#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
784#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
785#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
786#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
787#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
788#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
789#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
790#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
791#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
792#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
793#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
794#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
795#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
796#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
797#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
798
799/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
800#define TOVL_ERR0 TOVF_ERR0
801#define TOVL_ERR1 TOVF_ERR1
802#define TOVL_ERR2 TOVF_ERR2
803#define TOVL_ERR3 TOVF_ERR3
804#define TOVL_ERR4 TOVF_ERR4
805#define TOVL_ERR5 TOVF_ERR5
806#define TOVL_ERR6 TOVF_ERR6
807#define TOVL_ERR7 TOVF_ERR7
808
809/* TIMERx_CONFIG Masks */
810#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
811#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
812#define EXT_CLK 0x0003 /* External Clock Mode */
813#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
814#define PERIOD_CNT 0x0008 /* Period Count */
815#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
816#define TIN_SEL 0x0020 /* Timer Input Select */
817#define OUT_DIS 0x0040 /* Output Pad Disable */
818#define CLK_SEL 0x0080 /* Timer Clock Select */
819#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
820#define EMU_RUN 0x0200 /* Emulation Behavior Select */
821#define ERR_TYP 0xC000 /* Error Type */
822
823
824/* ****************** GPIO PORTS F, G, H MASKS ***********************/
825/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
826/* Port F Masks */
827#define PF0 0x0001
828#define PF1 0x0002
829#define PF2 0x0004
830#define PF3 0x0008
831#define PF4 0x0010
832#define PF5 0x0020
833#define PF6 0x0040
834#define PF7 0x0080
835#define PF8 0x0100
836#define PF9 0x0200
837#define PF10 0x0400
838#define PF11 0x0800
839#define PF12 0x1000
840#define PF13 0x2000
841#define PF14 0x4000
842#define PF15 0x8000
843
844/* Port G Masks */
845#define PG0 0x0001
846#define PG1 0x0002
847#define PG2 0x0004
848#define PG3 0x0008
849#define PG4 0x0010
850#define PG5 0x0020
851#define PG6 0x0040
852#define PG7 0x0080
853#define PG8 0x0100
854#define PG9 0x0200
855#define PG10 0x0400
856#define PG11 0x0800
857#define PG12 0x1000
858#define PG13 0x2000
859#define PG14 0x4000
860#define PG15 0x8000
861
862/* Port H Masks */
863#define PH0 0x0001
864#define PH1 0x0002
865#define PH2 0x0004
866#define PH3 0x0008
867#define PH4 0x0010
868#define PH5 0x0020
869#define PH6 0x0040
870#define PH7 0x0080
871#define PH8 0x0100
872#define PH9 0x0200
873#define PH10 0x0400
874#define PH11 0x0800
875#define PH12 0x1000
876#define PH13 0x2000
877#define PH14 0x4000
878#define PH15 0x8000
879
880/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
881/* EBIU_AMGCTL Masks */
882#define AMCKEN 0x0001 /* Enable CLKOUT */
883#define AMBEN_NONE 0x0000 /* All Banks Disabled */
884#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
885#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
886#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
887#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
888
889/* EBIU_AMBCTL0 Masks */
890#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
891#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
892#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
893#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
894#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
895#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
896#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
897#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
898#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
899#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
900#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
901#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
902#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
903#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
904#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
905#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
906#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
907#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
908#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
909#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
910#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
911#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
912#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
913#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
914#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
915#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
916#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
917#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
918#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
919#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
920#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
921#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
922#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
923#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
924#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
925#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
926#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
927#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
928#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
929#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
930#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
931#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
932#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
933#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
934
935#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
936#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
937#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
938#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
939#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
940#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
941#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
942#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
943#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
944#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
945#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
946#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
947#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
948#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
949#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
950#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
951#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
952#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
953#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
954#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
955#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
956#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
957#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
958#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
959#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
960#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
961#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
962#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
963#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
964#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
965#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
966#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
967#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
968#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
969#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
970#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
971#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
972#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
973#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
974#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
975#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
976#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
977#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
978#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
979
980/* EBIU_AMBCTL1 Masks */
981#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
982#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
983#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
984#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
985#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
986#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
987#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
988#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
989#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
990#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
991#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
992#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
993#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
994#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
995#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
996#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
997#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
998#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
999#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
1000#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
1001#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
1002#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
1003#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
1004#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
1005#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
1006#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
1007#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
1008#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
1009#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
1010#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
1011#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
1012#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
1013#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
1014#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
1015#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
1016#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
1017#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
1018#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
1019#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
1020#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
1021#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
1022#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
1023#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
1024#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
1025
1026#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
1027#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
1028#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
1029#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
1030#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
1031#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
1032#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
1033#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
1034#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
1035#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
1036#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1037#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1038#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1039#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1040#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
1041#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
1042#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
1043#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
1044#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
1045#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
1046#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
1047#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
1048#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
1049#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
1050#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
1051#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
1052#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
1053#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
1054#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
1055#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
1056#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
1057#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
1058#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
1059#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
1060#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
1061#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
1062#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
1063#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
1064#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
1065#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
1066#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
1067#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
1068#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
1069#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
1070
1071
1072/* ********************** SDRAM CONTROLLER MASKS **********************************************/
1073/* EBIU_SDGCTL Masks */
1074#define SCTLE 0x00000001 /* Enable SDRAM Signals */
1075#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
1076#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
1077#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
1078#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
1079#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
1080#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
1081#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
1082#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
1083#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
1084#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
1085#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
1086#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
1087#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
1088#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
1089#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
1090#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
1091#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
1092#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
1093#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
1094#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
1095#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
1096#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
1097#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
1098#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
1099#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
1100#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
1101#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
1102#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
1103#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
1104#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
1105#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
1106#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
1107#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
1108#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
1109#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
1110#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
1111#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
1112#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
1113#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
1114#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
1115#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
1116#define EBUFE 0x02000000 /* Enable External Buffering Timing */
1117#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
1118#define EMREN 0x10000000 /* Extended Mode Register Enable */
1119#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
1120#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
1121
1122/* EBIU_SDBCTL Masks */
1123#define EBE 0x0001 /* Enable SDRAM External Bank */
1124#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
1125#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
1126#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
1127#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
1128#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
1129#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
1130#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
1131#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
1132#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
1133#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
1134
1135/* EBIU_SDSTAT Masks */
1136#define SDCI 0x0001 /* SDRAM Controller Idle */
1137#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
1138#define SDPUA 0x0004 /* SDRAM Power-Up Active */
1139#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
1140#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
1141#define BGSTAT 0x0020 /* Bus Grant Status */
1142
1143
1144/* ************************** DMA CONTROLLER MASKS ********************************/
1145
1146/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
1147#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
1148#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
1149#define PMAP_PPI 0x0000 /* PPI Port DMA */
1150#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
1151#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
1152#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
1153#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
1154#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
1155#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
1156#define PMAP_SPI 0x7000 /* SPI Port DMA */
1157#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
1158#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
1159#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
1160#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
1161
1162/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
1163/* PPI_CONTROL Masks */
1164#define PORT_EN 0x0001 /* PPI Port Enable */
1165#define PORT_DIR 0x0002 /* PPI Port Direction */
1166#define XFR_TYPE 0x000C /* PPI Transfer Type */
1167#define PORT_CFG 0x0030 /* PPI Port Configuration */
1168#define FLD_SEL 0x0040 /* PPI Active Field Select */
1169#define PACK_EN 0x0080 /* PPI Packing Mode */
1170#define DMA32 0x0100 /* PPI 32-bit DMA Enable */
1171#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
1172#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
1173#define DLEN_8 0x0000 /* Data Length = 8 Bits */
1174#define DLEN_10 0x0800 /* Data Length = 10 Bits */
1175#define DLEN_11 0x1000 /* Data Length = 11 Bits */
1176#define DLEN_12 0x1800 /* Data Length = 12 Bits */
1177#define DLEN_13 0x2000 /* Data Length = 13 Bits */
1178#define DLEN_14 0x2800 /* Data Length = 14 Bits */
1179#define DLEN_15 0x3000 /* Data Length = 15 Bits */
1180#define DLEN_16 0x3800 /* Data Length = 16 Bits */
1181#define DLENGTH 0x3800 /* PPI Data Length */
1182#define POLC 0x4000 /* PPI Clock Polarity */
1183#define POLS 0x8000 /* PPI Frame Sync Polarity */
1184
1185/* PPI_STATUS Masks */
1186#define FLD 0x0400 /* Field Indicator */
1187#define FT_ERR 0x0800 /* Frame Track Error */
1188#define OVR 0x1000 /* FIFO Overflow Error */
1189#define UNDR 0x2000 /* FIFO Underrun Error */
1190#define ERR_DET 0x4000 /* Error Detected Indicator */
1191#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
1192
1193
1194/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
1195/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
1196#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
1197#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
1198
1199/* TWI_PRESCALE Masks */
1200#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
1201#define TWI_ENA 0x0080 /* TWI Enable */
1202#define SCCB 0x0200 /* SCCB Compatibility Enable */
1203
1204/* TWI_SLAVE_CTL Masks */
1205#define SEN 0x0001 /* Slave Enable */
1206#define SADD_LEN 0x0002 /* Slave Address Length */
1207#define STDVAL 0x0004 /* Slave Transmit Data Valid */
1208#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
1209#define GEN 0x0010 /* General Call Adrress Matching Enabled */
1210
1211/* TWI_SLAVE_STAT Masks */
1212#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
1213#define GCALL 0x0002 /* General Call Indicator */
1214
1215/* TWI_MASTER_CTL Masks */
1216#define MEN 0x0001 /* Master Mode Enable */
1217#define MADD_LEN 0x0002 /* Master Address Length */
1218#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
1219#define FAST 0x0008 /* Use Fast Mode Timing Specs */
1220#define STOP 0x0010 /* Issue Stop Condition */
1221#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
1222#define DCNT 0x3FC0 /* Data Bytes To Transfer */
1223#define SDAOVR 0x4000 /* Serial Data Override */
1224#define SCLOVR 0x8000 /* Serial Clock Override */
1225
1226/* TWI_MASTER_STAT Masks */
1227#define MPROG 0x0001 /* Master Transfer In Progress */
1228#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
1229#define ANAK 0x0004 /* Address Not Acknowledged */
1230#define DNAK 0x0008 /* Data Not Acknowledged */
1231#define BUFRDERR 0x0010 /* Buffer Read Error */
1232#define BUFWRERR 0x0020 /* Buffer Write Error */
1233#define SDASEN 0x0040 /* Serial Data Sense */
1234#define SCLSEN 0x0080 /* Serial Clock Sense */
1235#define BUSBUSY 0x0100 /* Bus Busy Indicator */
1236
1237/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
1238#define SINIT 0x0001 /* Slave Transfer Initiated */
1239#define SCOMP 0x0002 /* Slave Transfer Complete */
1240#define SERR 0x0004 /* Slave Transfer Error */
1241#define SOVF 0x0008 /* Slave Overflow */
1242#define MCOMP 0x0010 /* Master Transfer Complete */
1243#define MERR 0x0020 /* Master Transfer Error */
1244#define XMTSERV 0x0040 /* Transmit FIFO Service */
1245#define RCVSERV 0x0080 /* Receive FIFO Service */
1246
1247/* TWI_FIFO_CTRL Masks */
1248#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
1249#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
1250#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
1251#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
1252
1253/* TWI_FIFO_STAT Masks */
1254#define XMTSTAT 0x0003 /* Transmit FIFO Status */
1255#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
1256#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
1257#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
1258
1259#define RCVSTAT 0x000C /* Receive FIFO Status */
1260#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
1261#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
1262#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
1263
1264
1265/* Omit CAN masks from defBF534.h */
1266
1267/* ******************* PIN CONTROL REGISTER MASKS ************************/
1268/* PORT_MUX Masks */
1269#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
1270#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
1271#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
1272
1273#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
1274#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
1275#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
1276#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
1277
1278#define PFDE 0x0008 /* Port F DMA Request Enable */
1279#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
1280#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
1281
1282#define PFTE 0x0010 /* Port F Timer Enable */
1283#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
1284#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
1285
1286#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
1287#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
1288#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
1289
1290#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
1291#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
1292#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
1293
1294#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
1295#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
1296#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
1297
1298#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
1299#define PFFE_TIMER 0x0000 /* Enable TMR2 */
1300#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
1301
1302#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
1303#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
1304#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
1305
1306#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
1307#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
1308#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
1309
1310#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
1311#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
1312#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
1313
1314
1315/* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/
1316/* HDMAx_CTL Masks */
1317#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */
1318#define REP 0x0002 /* HDMA Request Polarity */
1319#define UTE 0x0004 /* Urgency Threshold Enable */
1320#define OIE 0x0010 /* Overflow Interrupt Enable */
1321#define BDIE 0x0020 /* Block Done Interrupt Enable */
1322#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */
1323#define DRQ 0x0300 /* HDMA Request Type */
1324#define DRQ_NONE 0x0000 /* No Request */
1325#define DRQ_SINGLE 0x0100 /* Channels Request Single */
1326#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */
1327#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */
1328#define RBC 0x1000 /* Reload BCNT With IBCNT */
1329#define PS 0x2000 /* HDMA Pin Status */
1330#define OI 0x4000 /* Overflow Interrupt Generated */
1331#define BDI 0x8000 /* Block Done Interrupt Generated */
1332
1333/* entry addresses of the user-callable Boot ROM functions */
1334
1335#define _BOOTROM_RESET 0xEF000000
1336#define _BOOTROM_FINAL_INIT 0xEF000002
1337#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
1338#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
1339#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
1340#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
1341#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
1342#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
1343#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
1344
1345/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
1346#define PGDE_UART PFDE_UART
1347#define PGDE_DMA PFDE_DMA
1348#define CKELOW SCKELOW
1349
1350/* ==== end from defBF534.h ==== */
1351
1352/* HOST Port Registers */
1353
1354#define HOST_CONTROL 0xffc03400 /* HOST Control Register */
1355#define HOST_STATUS 0xffc03404 /* HOST Status Register */
1356#define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */
1357
1358/* Counter Registers */
1359
1360#define CNT_CONFIG 0xffc03500 /* Configuration Register */
1361#define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */
1362#define CNT_STATUS 0xffc03508 /* Status Register */
1363#define CNT_COMMAND 0xffc0350c /* Command Register */
1364#define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */
1365#define CNT_COUNTER 0xffc03514 /* Counter Register */
1366#define CNT_MAX 0xffc03518 /* Maximal Count Register */
1367#define CNT_MIN 0xffc0351c /* Minimal Count Register */
1368
1369/* OTP/FUSE Registers */
1370
1371#define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */
1372#define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */
1373#define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */
1374#define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */
1375
1376/* Security Registers */
1377
1378#define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */
1379#define SECURE_CONTROL 0xffc03624 /* Secure Control */
1380#define SECURE_STATUS 0xffc03628 /* Secure Status */
1381
1382/* OTP Read/Write Data Buffer Registers */
1383
1384#define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1385#define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1386#define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1387#define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1388
1389/* NFC Registers */
1390
1391#define NFC_CTL 0xffc03700 /* NAND Control Register */
1392#define NFC_STAT 0xffc03704 /* NAND Status Register */
1393#define NFC_IRQSTAT 0xffc03708 /* NAND Interrupt Status Register */
1394#define NFC_IRQMASK 0xffc0370c /* NAND Interrupt Mask Register */
1395#define NFC_ECC0 0xffc03710 /* NAND ECC Register 0 */
1396#define NFC_ECC1 0xffc03714 /* NAND ECC Register 1 */
1397#define NFC_ECC2 0xffc03718 /* NAND ECC Register 2 */
1398#define NFC_ECC3 0xffc0371c /* NAND ECC Register 3 */
1399#define NFC_COUNT 0xffc03720 /* NAND ECC Count Register */
1400#define NFC_RST 0xffc03724 /* NAND ECC Reset Register */
1401#define NFC_PGCTL 0xffc03728 /* NAND Page Control Register */
1402#define NFC_READ 0xffc0372c /* NAND Read Data Register */
1403#define NFC_ADDR 0xffc03740 /* NAND Address Register */
1404#define NFC_CMD 0xffc03744 /* NAND Command Register */
1405#define NFC_DATA_WR 0xffc03748 /* NAND Data Write Register */
1406#define NFC_DATA_RD 0xffc0374c /* NAND Data Read Register */
1407
1408/* ********************************************************** */
1409/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
1410/* and MULTI BIT READ MACROS */
1411/* ********************************************************** */
1412
1413/* Bit masks for HOST_CONTROL */
1414
1415#define HOST_CNTR_HOST_EN 0x1 /* Host Enable */
1416#define HOST_CNTR_nHOST_EN 0x0
1417#define HOST_CNTR_HOST_END 0x2 /* Host Endianess */
1418#define HOST_CNTR_nHOST_END 0x0
1419#define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */
1420#define HOST_CNTR_nDATA_SIZE 0x0
1421#define HOST_CNTR_HOST_RST 0x8 /* Host Reset */
1422#define HOST_CNTR_nHOST_RST 0x0
1423#define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */
1424#define HOST_CNTR_nHRDY_OVR 0x0
1425#define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */
1426#define HOST_CNTR_nINT_MODE 0x0
1427#define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */
1428#define HOST_CNTR_ nBT_EN 0x0
1429#define HOST_CNTR_EHW 0x100 /* Enable Host Write */
1430#define HOST_CNTR_nEHW 0x0
1431#define HOST_CNTR_EHR 0x200 /* Enable Host Read */
1432#define HOST_CNTR_nEHR 0x0
1433#define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */
1434#define HOST_CNTR_nBDR 0x0
1435
1436/* Bit masks for HOST_STATUS */
1437
1438#define HOST_STAT_READY 0x1 /* DMA Ready */
1439#define HOST_STAT_nREADY 0x0
1440#define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */
1441#define HOST_STAT_nFIFOFULL 0x0
1442#define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */
1443#define HOST_STAT_nFIFOEMPTY 0x0
1444#define HOST_STAT_COMPLETE 0x8 /* DMA Complete */
1445#define HOST_STAT_nCOMPLETE 0x0
1446#define HOST_STAT_HSHK 0x10 /* Host Handshake */
1447#define HOST_STAT_nHSHK 0x0
1448#define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */
1449#define HOST_STAT_nTIMEOUT 0x0
1450#define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */
1451#define HOST_STAT_nHIRQ 0x0
1452#define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */
1453#define HOST_STAT_nALLOW_CNFG 0x0
1454#define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */
1455#define HOST_STAT_nDMA_DIR 0x0
1456#define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */
1457#define HOST_STAT_nBTE 0x0
1458#define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */
1459#define HOST_STAT_nHOSTRD_DONE 0x0
1460
1461/* Bit masks for HOST_TIMEOUT */
1462
1463#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */
1464
1465/* Bit masks for SECURE_SYSSWT */
1466
1467#define EMUDABL 0x1 /* Emulation Disable. */
1468#define nEMUDABL 0x0
1469#define RSTDABL 0x2 /* Reset Disable */
1470#define nRSTDABL 0x0
1471#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
1472#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
1473#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
1474#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
1475#define nDMA0OVR 0x0
1476#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
1477#define nDMA1OVR 0x0
1478#define EMUOVR 0x4000 /* Emulation Override */
1479#define nEMUOVR 0x0
1480#define OTPSEN 0x8000 /* OTP Secrets Enable. */
1481#define nOTPSEN 0x0
1482#define L2DABL 0x70000 /* L2 Memory Disable. */
1483
1484/* Bit masks for SECURE_CONTROL */
1485
1486#define SECURE0 0x1 /* SECURE 0 */
1487#define nSECURE0 0x0
1488#define SECURE1 0x2 /* SECURE 1 */
1489#define nSECURE1 0x0
1490#define SECURE2 0x4 /* SECURE 2 */
1491#define nSECURE2 0x0
1492#define SECURE3 0x8 /* SECURE 3 */
1493#define nSECURE3 0x0
1494
1495/* Bit masks for SECURE_STATUS */
1496
1497#define SECMODE 0x3 /* Secured Mode Control State */
1498#define NMI 0x4 /* Non Maskable Interrupt */
1499#define nNMI 0x0
1500#define AFVALID 0x8 /* Authentication Firmware Valid */
1501#define nAFVALID 0x0
1502#define AFEXIT 0x10 /* Authentication Firmware Exit */
1503#define nAFEXIT 0x0
1504#define SECSTAT 0xe0 /* Secure Status */
1505
1506#endif /* _DEF_BF52X_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/gpio.h b/arch/blackfin/mach-bf527/include/mach/gpio.h
index f80c2995efdb..fba606b699c3 100644
--- a/arch/blackfin/mach-bf527/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf527/include/mach/gpio.h
@@ -62,4 +62,8 @@
62#define PORT_G GPIO_PG0 62#define PORT_G GPIO_PG0
63#define PORT_H GPIO_PH0 63#define PORT_H GPIO_PH0
64 64
65#include <mach-common/ports-f.h>
66#include <mach-common/ports-g.h>
67#include <mach-common/ports-h.h>
68
65#endif /* _MACH_GPIO_H_ */ 69#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf527/include/mach/pll.h b/arch/blackfin/mach-bf527/include/mach/pll.h
index 24f1d7c02325..94cca674d835 100644
--- a/arch/blackfin/mach-bf527/include/mach/pll.h
+++ b/arch/blackfin/mach-bf527/include/mach/pll.h
@@ -1,63 +1 @@
1/* #include <mach-common/pll.h>
2 * Copyright 2007-2008 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr0, iwr1;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 flags = hard_local_irq_save();
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr0 = bfin_read32(SIC_IWR0);
24 iwr1 = bfin_read32(SIC_IWR1);
25 /* Only allow PPL Wakeup) */
26 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
27 bfin_write32(SIC_IWR1, 0);
28
29 bfin_write16(PLL_CTL, val);
30 SSYNC();
31 asm("IDLE;");
32
33 bfin_write32(SIC_IWR0, iwr0);
34 bfin_write32(SIC_IWR1, iwr1);
35 hard_local_irq_restore(flags);
36}
37
38/* Writing to VR_CTL initiates a PLL relock sequence. */
39static __inline__ void bfin_write_VR_CTL(unsigned int val)
40{
41 unsigned long flags, iwr0, iwr1;
42
43 if (val == bfin_read_VR_CTL())
44 return;
45
46 flags = hard_local_irq_save();
47 /* Enable the PLL Wakeup bit in SIC IWR */
48 iwr0 = bfin_read32(SIC_IWR0);
49 iwr1 = bfin_read32(SIC_IWR1);
50 /* Only allow PPL Wakeup) */
51 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
52 bfin_write32(SIC_IWR1, 0);
53
54 bfin_write16(VR_CTL, val);
55 SSYNC();
56 asm("IDLE;");
57
58 bfin_write32(SIC_IWR0, iwr0);
59 bfin_write32(SIC_IWR1, iwr1);
60 hard_local_irq_restore(flags);
61}
62
63#endif /* _MACH_PLL_H */
diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c
index 2ce7b16faee1..d4bfcea56828 100644
--- a/arch/blackfin/mach-bf533/boards/H8606.c
+++ b/arch/blackfin/mach-bf533/boards/H8606.c
@@ -286,7 +286,7 @@ static struct resource bfin_uart0_resources[] = {
286 }, 286 },
287}; 287};
288 288
289unsigned short bfin_uart0_peripherals[] = { 289static unsigned short bfin_uart0_peripherals[] = {
290 P_UART0_TX, P_UART0_RX, 0 290 P_UART0_TX, P_UART0_RX, 0
291}; 291};
292 292
diff --git a/arch/blackfin/mach-bf533/boards/blackstamp.c b/arch/blackfin/mach-bf533/boards/blackstamp.c
index 20c102285bef..87b5af3693c1 100644
--- a/arch/blackfin/mach-bf533/boards/blackstamp.c
+++ b/arch/blackfin/mach-bf533/boards/blackstamp.c
@@ -25,7 +25,6 @@
25#include <asm/bfin5xx_spi.h> 25#include <asm/bfin5xx_spi.h>
26#include <asm/portmux.h> 26#include <asm/portmux.h>
27#include <asm/dpmc.h> 27#include <asm/dpmc.h>
28#include <mach/fio_flag.h>
29 28
30/* 29/*
31 * Name the Board for the /proc/cpuinfo 30 * Name the Board for the /proc/cpuinfo
@@ -225,7 +224,7 @@ static struct resource bfin_uart0_resources[] = {
225 }, 224 },
226}; 225};
227 226
228unsigned short bfin_uart0_peripherals[] = { 227static unsigned short bfin_uart0_peripherals[] = {
229 P_UART0_TX, P_UART0_RX, 0 228 P_UART0_TX, P_UART0_RX, 0
230}; 229};
231 230
@@ -290,9 +289,9 @@ static struct resource bfin_sport0_uart_resources[] = {
290 }, 289 },
291}; 290};
292 291
293unsigned short bfin_sport0_peripherals[] = { 292static unsigned short bfin_sport0_peripherals[] = {
294 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 293 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
295 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 294 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
296}; 295};
297 296
298static struct platform_device bfin_sport0_uart_device = { 297static struct platform_device bfin_sport0_uart_device = {
@@ -324,9 +323,9 @@ static struct resource bfin_sport1_uart_resources[] = {
324 }, 323 },
325}; 324};
326 325
327unsigned short bfin_sport1_peripherals[] = { 326static unsigned short bfin_sport1_peripherals[] = {
328 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 327 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
329 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 328 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
330}; 329};
331 330
332static struct platform_device bfin_sport1_uart_device = { 331static struct platform_device bfin_sport1_uart_device = {
@@ -476,10 +475,16 @@ static int __init blackstamp_init(void)
476 return ret; 475 return ret;
477 476
478#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) 477#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
479 /* setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC */ 478 /*
480 bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF0); 479 * setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC.
481 bfin_write_FIO_FLAG_S(PF0); 480 * the bfin-async-map driver takes care of flipping between
482 SSYNC(); 481 * flash and ethernet when necessary.
482 */
483 ret = gpio_request(GPIO_PF0, "enet_cpld");
484 if (!ret) {
485 gpio_direction_output(GPIO_PF0, 1);
486 gpio_free(GPIO_PF0);
487 }
483#endif 488#endif
484 489
485 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); 490 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c
index adbe62a81e25..4d5604eaa7c2 100644
--- a/arch/blackfin/mach-bf533/boards/cm_bf533.c
+++ b/arch/blackfin/mach-bf533/boards/cm_bf533.c
@@ -271,7 +271,7 @@ static struct resource bfin_uart0_resources[] = {
271 }, 271 },
272}; 272};
273 273
274unsigned short bfin_uart0_peripherals[] = { 274static unsigned short bfin_uart0_peripherals[] = {
275 P_UART0_TX, P_UART0_RX, 0 275 P_UART0_TX, P_UART0_RX, 0
276}; 276};
277 277
@@ -336,9 +336,9 @@ static struct resource bfin_sport0_uart_resources[] = {
336 }, 336 },
337}; 337};
338 338
339unsigned short bfin_sport0_peripherals[] = { 339static unsigned short bfin_sport0_peripherals[] = {
340 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 340 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
341 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 341 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
342}; 342};
343 343
344static struct platform_device bfin_sport0_uart_device = { 344static struct platform_device bfin_sport0_uart_device = {
@@ -370,9 +370,9 @@ static struct resource bfin_sport1_uart_resources[] = {
370 }, 370 },
371}; 371};
372 372
373unsigned short bfin_sport1_peripherals[] = { 373static unsigned short bfin_sport1_peripherals[] = {
374 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 374 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
375 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 375 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
376}; 376};
377 377
378static struct platform_device bfin_sport1_uart_device = { 378static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c
index a1cb8e7c1010..b67b91d82242 100644
--- a/arch/blackfin/mach-bf533/boards/ezkit.c
+++ b/arch/blackfin/mach-bf533/boards/ezkit.c
@@ -349,7 +349,7 @@ static struct resource bfin_uart0_resources[] = {
349 }, 349 },
350}; 350};
351 351
352unsigned short bfin_uart0_peripherals[] = { 352static unsigned short bfin_uart0_peripherals[] = {
353 P_UART0_TX, P_UART0_RX, 0 353 P_UART0_TX, P_UART0_RX, 0
354}; 354};
355 355
diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c
index 5ba4b02a12eb..f869a3711480 100644
--- a/arch/blackfin/mach-bf533/boards/ip0x.c
+++ b/arch/blackfin/mach-bf533/boards/ip0x.c
@@ -22,7 +22,6 @@
22#include <asm/dma.h> 22#include <asm/dma.h>
23#include <asm/bfin5xx_spi.h> 23#include <asm/bfin5xx_spi.h>
24#include <asm/portmux.h> 24#include <asm/portmux.h>
25#include <mach/fio_flag.h>
26 25
27/* 26/*
28 * Name the Board for the /proc/cpuinfo 27 * Name the Board for the /proc/cpuinfo
@@ -174,7 +173,7 @@ static struct resource bfin_uart0_resources[] = {
174 }, 173 },
175}; 174};
176 175
177unsigned short bfin_uart0_peripherals[] = { 176static unsigned short bfin_uart0_peripherals[] = {
178 P_UART0_TX, P_UART0_RX, 0 177 P_UART0_TX, P_UART0_RX, 0
179}; 178};
180 179
@@ -295,15 +294,7 @@ static int __init ip0x_init(void)
295 printk(KERN_INFO "%s(): registering device resources\n", __func__); 294 printk(KERN_INFO "%s(): registering device resources\n", __func__);
296 platform_add_devices(ip0x_devices, ARRAY_SIZE(ip0x_devices)); 295 platform_add_devices(ip0x_devices, ARRAY_SIZE(ip0x_devices));
297 296
298#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
299 for (i = 0; i < ARRAY_SIZE(bfin_spi_board_info); ++i) {
300 int j = 1 << bfin_spi_board_info[i].chip_select;
301 /* set spi cs to 1 */
302 bfin_write_FIO_DIR(bfin_read_FIO_DIR() | j);
303 bfin_write_FIO_FLAG_S(j);
304 }
305 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); 297 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
306#endif
307 298
308 return 0; 299 return 0;
309} 300}
diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c
index b3b1cdea2703..43224ef00b8c 100644
--- a/arch/blackfin/mach-bf533/boards/stamp.c
+++ b/arch/blackfin/mach-bf533/boards/stamp.c
@@ -24,7 +24,6 @@
24#include <asm/reboot.h> 24#include <asm/reboot.h>
25#include <asm/portmux.h> 25#include <asm/portmux.h>
26#include <asm/dpmc.h> 26#include <asm/dpmc.h>
27#include <mach/fio_flag.h>
28 27
29/* 28/*
30 * Name the Board for the /proc/cpuinfo 29 * Name the Board for the /proc/cpuinfo
@@ -354,7 +353,7 @@ static struct resource bfin_uart0_resources[] = {
354 }, 353 },
355}; 354};
356 355
357unsigned short bfin_uart0_peripherals[] = { 356static unsigned short bfin_uart0_peripherals[] = {
358 P_UART0_TX, P_UART0_RX, 0 357 P_UART0_TX, P_UART0_RX, 0
359}; 358};
360 359
@@ -419,9 +418,9 @@ static struct resource bfin_sport0_uart_resources[] = {
419 }, 418 },
420}; 419};
421 420
422unsigned short bfin_sport0_peripherals[] = { 421static unsigned short bfin_sport0_peripherals[] = {
423 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 422 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
424 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 423 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
425}; 424};
426 425
427static struct platform_device bfin_sport0_uart_device = { 426static struct platform_device bfin_sport0_uart_device = {
@@ -453,9 +452,9 @@ static struct resource bfin_sport1_uart_resources[] = {
453 }, 452 },
454}; 453};
455 454
456unsigned short bfin_sport1_peripherals[] = { 455static unsigned short bfin_sport1_peripherals[] = {
457 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 456 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
458 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 457 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
459}; 458};
460 459
461static struct platform_device bfin_sport1_uart_device = { 460static struct platform_device bfin_sport1_uart_device = {
@@ -674,10 +673,16 @@ static int __init stamp_init(void)
674 return ret; 673 return ret;
675 674
676#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) 675#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
677 /* setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC */ 676 /*
678 bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF0); 677 * setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC.
679 bfin_write_FIO_FLAG_S(PF0); 678 * the bfin-async-map driver takes care of flipping between
680 SSYNC(); 679 * flash and ethernet when necessary.
680 */
681 ret = gpio_request(GPIO_PF0, "enet_cpld");
682 if (!ret) {
683 gpio_direction_output(GPIO_PF0, 1);
684 gpio_free(GPIO_PF0);
685 }
681#endif 686#endif
682 687
683 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); 688 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
@@ -713,7 +718,6 @@ void __init native_machine_early_platform_add_devices(void)
713void native_machine_restart(char *cmd) 718void native_machine_restart(char *cmd)
714{ 719{
715 /* workaround pull up on cpld / flash pin not being strong enough */ 720 /* workaround pull up on cpld / flash pin not being strong enough */
716 bfin_write_FIO_INEN(~PF0); 721 gpio_request(GPIO_PF0, "flash_cpld");
717 bfin_write_FIO_DIR(PF0); 722 gpio_direction_output(GPIO_PF0, 0);
718 bfin_write_FIO_FLAG_C(PF0);
719} 723}
diff --git a/arch/blackfin/mach-bf533/dma.c b/arch/blackfin/mach-bf533/dma.c
index 4a14a46a9a68..1f5988d43139 100644
--- a/arch/blackfin/mach-bf533/dma.c
+++ b/arch/blackfin/mach-bf533/dma.c
@@ -11,7 +11,7 @@
11#include <asm/blackfin.h> 11#include <asm/blackfin.h>
12#include <asm/dma.h> 12#include <asm/dma.h>
13 13
14struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { 14struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
15 (struct dma_register *) DMA0_NEXT_DESC_PTR, 15 (struct dma_register *) DMA0_NEXT_DESC_PTR,
16 (struct dma_register *) DMA1_NEXT_DESC_PTR, 16 (struct dma_register *) DMA1_NEXT_DESC_PTR,
17 (struct dma_register *) DMA2_NEXT_DESC_PTR, 17 (struct dma_register *) DMA2_NEXT_DESC_PTR,
diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_serial.h b/arch/blackfin/mach-bf533/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..08072c86d5dc
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/bfin_serial.h
@@ -0,0 +1,14 @@
1/*
2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
3 *
4 * Copyright 2006-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_MACH_SERIAL_H__
10#define __BFIN_MACH_SERIAL_H__
11
12#define BFIN_UART_NR_PORTS 1
13
14#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
index 9e1f3defb6bc..45dcaa4f3e41 100644
--- a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
@@ -4,36 +4,9 @@
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later
5 */ 5 */
6 6
7#include <linux/serial.h>
8#include <asm/dma.h> 7#include <asm/dma.h>
9#include <asm/portmux.h> 8#include <asm/portmux.h>
10 9
11#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
12#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
13#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
14#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
15#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
16#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
17#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
18
19#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
20#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
21#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
22#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
23#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
24#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
25#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
26#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
27
28#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
29#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
30
31#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
32#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
33#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
34#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
35#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
36
37#ifdef CONFIG_BFIN_UART0_CTSRTS 10#ifdef CONFIG_BFIN_UART0_CTSRTS
38# define CONFIG_SERIAL_BFIN_CTSRTS 11# define CONFIG_SERIAL_BFIN_CTSRTS
39# ifndef CONFIG_UART0_CTS_PIN 12# ifndef CONFIG_UART0_CTS_PIN
@@ -44,51 +17,6 @@
44# endif 17# endif
45#endif 18#endif
46 19
47#define BFIN_UART_TX_FIFO_SIZE 2
48
49struct bfin_serial_port {
50 struct uart_port port;
51 unsigned int old_status;
52 int status_irq;
53 unsigned int lsr;
54#ifdef CONFIG_SERIAL_BFIN_DMA
55 int tx_done;
56 int tx_count;
57 struct circ_buf rx_dma_buf;
58 struct timer_list rx_dma_timer;
59 int rx_dma_nrows;
60 unsigned int tx_dma_channel;
61 unsigned int rx_dma_channel;
62 struct work_struct tx_dma_workqueue;
63#else
64# if ANOMALY_05000363
65 unsigned int anomaly_threshold;
66# endif
67#endif
68#ifdef CONFIG_SERIAL_BFIN_CTSRTS
69 struct timer_list cts_timer;
70 int cts_pin;
71 int rts_pin;
72#endif
73};
74
75/* The hardware clears the LSR bits upon read, so we need to cache
76 * some of the more fun bits in software so they don't get lost
77 * when checking the LSR in other code paths (TX).
78 */
79static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
80{
81 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
82 uart->lsr |= (lsr & (BI|FE|PE|OE));
83 return lsr | uart->lsr;
84}
85
86static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
87{
88 uart->lsr = 0;
89 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
90}
91
92struct bfin_serial_res { 20struct bfin_serial_res {
93 unsigned long uart_base_addr; 21 unsigned long uart_base_addr;
94 int uart_irq; 22 int uart_irq;
@@ -120,3 +48,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
120}; 48};
121 49
122#define DRIVER_NAME "bfin-uart" 50#define DRIVER_NAME "bfin-uart"
51
52#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf533/include/mach/blackfin.h b/arch/blackfin/mach-bf533/include/mach/blackfin.h
index f4bd6df5d968..e366207fbf12 100644
--- a/arch/blackfin/mach-bf533/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf533/include/mach/blackfin.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2005-2009 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later.
5 */ 5 */
6 6
7#ifndef _MACH_BLACKFIN_H_ 7#ifndef _MACH_BLACKFIN_H_
@@ -10,26 +10,14 @@
10#define BF533_FAMILY 10#define BF533_FAMILY
11 11
12#include "bf533.h" 12#include "bf533.h"
13#include "defBF532.h"
14#include "anomaly.h" 13#include "anomaly.h"
15 14
16#if !defined(__ASSEMBLY__) 15#include <asm/def_LPBlackfin.h>
17#include "cdefBF532.h" 16#include "defBF532.h"
18#endif
19
20#define BFIN_UART_NR_PORTS 1
21 17
22#define OFFSET_THR 0x00 /* Transmit Holding register */ 18#ifndef __ASSEMBLY__
23#define OFFSET_RBR 0x00 /* Receive Buffer register */ 19# include <asm/cdef_LPBlackfin.h>
24#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ 20# include "cdefBF532.h"
25#define OFFSET_IER 0x04 /* Interrupt Enable Register */ 21#endif
26#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
27#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
28#define OFFSET_LCR 0x0C /* Line Control Register */
29#define OFFSET_MCR 0x10 /* Modem Control Register */
30#define OFFSET_LSR 0x14 /* Line Status Register */
31#define OFFSET_MSR 0x18 /* Modem Status Register */
32#define OFFSET_SCR 0x1C /* SCR Scratch Register */
33#define OFFSET_GCTL 0x24 /* Global Control Register */
34 22
35#endif /* _MACH_BLACKFIN_H_ */ 23#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
index 401e524f5321..fd0cbe4df21a 100644
--- a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
+++ b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2005-2008 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later
5 */ 5 */
@@ -7,9 +7,6 @@
7#ifndef _CDEF_BF532_H 7#ifndef _CDEF_BF532_H
8#define _CDEF_BF532_H 8#define _CDEF_BF532_H
9 9
10/*include core specific register pointer definitions*/
11#include <asm/cdef_LPBlackfin.h>
12
13/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */ 10/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
14#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 11#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
15#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 12#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
@@ -66,16 +63,10 @@
66#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val) 63#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val)
67 64
68/* DMA Traffic controls */ 65/* DMA Traffic controls */
69#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER) 66#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
70#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val) 67#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val)
71#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT) 68#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
72#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val) 69#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val)
73
74/* Alternate deprecated register names (below) provided for backwards code compatibility */
75#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
76#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val)
77#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
78#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val)
79 70
80/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */ 71/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
81#define bfin_read_FIO_DIR() bfin_read16(FIO_DIR) 72#define bfin_read_FIO_DIR() bfin_read16(FIO_DIR)
@@ -105,6 +96,47 @@
105#define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T) 96#define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T)
106#define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val) 97#define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val)
107 98
99#if ANOMALY_05000311
100/* Keep at the CPP expansion to avoid circular header dependency loops */
101#define BFIN_WRITE_FIO_FLAG(name, val) \
102 do { \
103 unsigned long __flags; \
104 __flags = hard_local_irq_save(); \
105 bfin_write16(FIO_FLAG_##name, val); \
106 bfin_read_CHIPID(); \
107 hard_local_irq_restore(__flags); \
108 } while (0)
109#define bfin_write_FIO_FLAG_D(val) BFIN_WRITE_FIO_FLAG(D, val)
110#define bfin_write_FIO_FLAG_C(val) BFIN_WRITE_FIO_FLAG(C, val)
111#define bfin_write_FIO_FLAG_S(val) BFIN_WRITE_FIO_FLAG(S, val)
112#define bfin_write_FIO_FLAG_T(val) BFIN_WRITE_FIO_FLAG(T, val)
113
114#define BFIN_READ_FIO_FLAG(name) \
115 ({ \
116 unsigned long __flags; \
117 u16 __ret; \
118 __flags = hard_local_irq_save(); \
119 __ret = bfin_read16(FIO_FLAG_##name); \
120 bfin_read_CHIPID(); \
121 hard_local_irq_restore(__flags); \
122 __ret; \
123 })
124#define bfin_read_FIO_FLAG_D() BFIN_READ_FIO_FLAG(D)
125#define bfin_read_FIO_FLAG_C() BFIN_READ_FIO_FLAG(C)
126#define bfin_read_FIO_FLAG_S() BFIN_READ_FIO_FLAG(S)
127#define bfin_read_FIO_FLAG_T() BFIN_READ_FIO_FLAG(T)
128
129#else
130#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val)
131#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val)
132#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val)
133#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val)
134#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D)
135#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C)
136#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S)
137#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T)
138#endif
139
108/* DMA Controller */ 140/* DMA Controller */
109#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) 141#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
110#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val) 142#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val)
@@ -647,7 +679,4 @@
647#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) 679#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
648#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val) 680#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val)
649 681
650/* These need to be last due to the cdef/linux inter-dependencies */
651#include <asm/irq.h>
652
653#endif /* _CDEF_BF532_H */ 682#endif /* _CDEF_BF532_H */
diff --git a/arch/blackfin/mach-bf533/include/mach/defBF532.h b/arch/blackfin/mach-bf533/include/mach/defBF532.h
index 3adb0b44e597..2376d5393511 100644
--- a/arch/blackfin/mach-bf533/include/mach/defBF532.h
+++ b/arch/blackfin/mach-bf533/include/mach/defBF532.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * System & MMR bit and Address definitions for ADSP-BF532 2 * System & MMR bit and Address definitions for ADSP-BF532
3 * 3 *
4 * Copyright 2005-2008 Analog Devices Inc. 4 * Copyright 2005-2010 Analog Devices Inc.
5 * 5 *
6 * Licensed under the ADI BSD license or the GPL-2 (or later) 6 * Licensed under the ADI BSD license or the GPL-2 (or later)
7 */ 7 */
@@ -9,9 +9,6 @@
9#ifndef _DEF_BF532_H 9#ifndef _DEF_BF532_H
10#define _DEF_BF532_H 10#define _DEF_BF532_H
11 11
12/* include all Core registers and bit definitions */
13#include <asm/def_LPBlackfin.h>
14
15/*********************************************************************************** */ 12/*********************************************************************************** */
16/* System MMR Register Map */ 13/* System MMR Register Map */
17/*********************************************************************************** */ 14/*********************************************************************************** */
@@ -182,12 +179,8 @@
182#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ 179#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
183 180
184/* DMA Traffic controls */ 181/* DMA Traffic controls */
185#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ 182#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
186#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ 183#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
187
188/* Alternate deprecated register names (below) provided for backwards code compatibility */
189#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
190#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
191 184
192/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ 185/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
193#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ 186#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
@@ -432,83 +425,6 @@
432#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ 425#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
433#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ 426#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
434 427
435/* ***************************** UART CONTROLLER MASKS ********************** */
436
437/* UART_LCR Register */
438
439#define DLAB 0x80
440#define SB 0x40
441#define STP 0x20
442#define EPS 0x10
443#define PEN 0x08
444#define STB 0x04
445#define WLS(x) ((x-5) & 0x03)
446
447#define DLAB_P 0x07
448#define SB_P 0x06
449#define STP_P 0x05
450#define EPS_P 0x04
451#define PEN_P 0x03
452#define STB_P 0x02
453#define WLS_P1 0x01
454#define WLS_P0 0x00
455
456/* UART_MCR Register */
457#define LOOP_ENA 0x10
458#define LOOP_ENA_P 0x04
459
460/* UART_LSR Register */
461#define TEMT 0x40
462#define THRE 0x20
463#define BI 0x10
464#define FE 0x08
465#define PE 0x04
466#define OE 0x02
467#define DR 0x01
468
469#define TEMP_P 0x06
470#define THRE_P 0x05
471#define BI_P 0x04
472#define FE_P 0x03
473#define PE_P 0x02
474#define OE_P 0x01
475#define DR_P 0x00
476
477/* UART_IER Register */
478#define ELSI 0x04
479#define ETBEI 0x02
480#define ERBFI 0x01
481
482#define ELSI_P 0x02
483#define ETBEI_P 0x01
484#define ERBFI_P 0x00
485
486/* UART_IIR Register */
487#define STATUS(x) ((x << 1) & 0x06)
488#define NINT 0x01
489#define STATUS_P1 0x02
490#define STATUS_P0 0x01
491#define NINT_P 0x00
492#define IIR_TX_READY 0x02 /* UART_THR empty */
493#define IIR_RX_READY 0x04 /* Receive data ready */
494#define IIR_LINE_CHANGE 0x06 /* Receive line status */
495#define IIR_STATUS 0x06
496
497/* UART_GCTL Register */
498#define FFE 0x20
499#define FPE 0x10
500#define RPOLC 0x08
501#define TPOLC 0x04
502#define IREN 0x02
503#define UCEN 0x01
504
505#define FFE_P 0x05
506#define FPE_P 0x04
507#define RPOLC_P 0x03
508#define TPOLC_P 0x02
509#define IREN_P 0x01
510#define UCEN_P 0x00
511
512/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ 428/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
513 429
514/* PPI_CONTROL Masks */ 430/* PPI_CONTROL Masks */
@@ -643,44 +559,6 @@
643#define ERR_TYP_P0 0x0E 559#define ERR_TYP_P0 0x0E
644#define ERR_TYP_P1 0x0F 560#define ERR_TYP_P1 0x0F
645 561
646/*/ ****************** PROGRAMMABLE FLAG MASKS ********************* */
647
648/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
649#define PF0 0x0001
650#define PF1 0x0002
651#define PF2 0x0004
652#define PF3 0x0008
653#define PF4 0x0010
654#define PF5 0x0020
655#define PF6 0x0040
656#define PF7 0x0080
657#define PF8 0x0100
658#define PF9 0x0200
659#define PF10 0x0400
660#define PF11 0x0800
661#define PF12 0x1000
662#define PF13 0x2000
663#define PF14 0x4000
664#define PF15 0x8000
665
666/* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */
667#define PF0_P 0
668#define PF1_P 1
669#define PF2_P 2
670#define PF3_P 3
671#define PF4_P 4
672#define PF5_P 5
673#define PF6_P 6
674#define PF7_P 7
675#define PF8_P 8
676#define PF9_P 9
677#define PF10_P 10
678#define PF11_P 11
679#define PF12_P 12
680#define PF13_P 13
681#define PF14_P 14
682#define PF15_P 15
683
684/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ 562/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
685 563
686/* AMGCTL Masks */ 564/* AMGCTL Masks */
diff --git a/arch/blackfin/mach-bf533/include/mach/fio_flag.h b/arch/blackfin/mach-bf533/include/mach/fio_flag.h
deleted file mode 100644
index d0bfba0b083b..000000000000
--- a/arch/blackfin/mach-bf533/include/mach/fio_flag.h
+++ /dev/null
@@ -1,55 +0,0 @@
1/*
2 * Copyright 2005-2008 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later
5 */
6
7#ifndef _MACH_FIO_FLAG_H
8#define _MACH_FIO_FLAG_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13#if ANOMALY_05000311
14#define BFIN_WRITE_FIO_FLAG(name) \
15static inline void bfin_write_FIO_FLAG_##name(unsigned short val) \
16{ \
17 unsigned long flags; \
18 flags = hard_local_irq_save(); \
19 bfin_write16(FIO_FLAG_##name, val); \
20 bfin_read_CHIPID(); \
21 hard_local_irq_restore(flags); \
22}
23BFIN_WRITE_FIO_FLAG(D)
24BFIN_WRITE_FIO_FLAG(C)
25BFIN_WRITE_FIO_FLAG(S)
26BFIN_WRITE_FIO_FLAG(T)
27
28#define BFIN_READ_FIO_FLAG(name) \
29static inline u16 bfin_read_FIO_FLAG_##name(void) \
30{ \
31 unsigned long flags; \
32 u16 ret; \
33 flags = hard_local_irq_save(); \
34 ret = bfin_read16(FIO_FLAG_##name); \
35 bfin_read_CHIPID(); \
36 hard_local_irq_restore(flags); \
37 return ret; \
38}
39BFIN_READ_FIO_FLAG(D)
40BFIN_READ_FIO_FLAG(C)
41BFIN_READ_FIO_FLAG(S)
42BFIN_READ_FIO_FLAG(T)
43
44#else
45#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val)
46#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val)
47#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val)
48#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val)
49#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T)
50#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C)
51#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S)
52#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D)
53#endif
54
55#endif /* _MACH_FIO_FLAG_H */
diff --git a/arch/blackfin/mach-bf533/include/mach/gpio.h b/arch/blackfin/mach-bf533/include/mach/gpio.h
index e02416db4b00..cce4f8fb3785 100644
--- a/arch/blackfin/mach-bf533/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf533/include/mach/gpio.h
@@ -28,4 +28,6 @@
28 28
29#define PORT_F GPIO_PF0 29#define PORT_F GPIO_PF0
30 30
31#include <mach-common/ports-f.h>
32
31#endif /* _MACH_GPIO_H_ */ 33#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf533/include/mach/pll.h b/arch/blackfin/mach-bf533/include/mach/pll.h
index 169c106d0edb..94cca674d835 100644
--- a/arch/blackfin/mach-bf533/include/mach/pll.h
+++ b/arch/blackfin/mach-bf533/include/mach/pll.h
@@ -1,57 +1 @@
1/* #include <mach-common/pll.h>
2 * Copyright 2005-2008 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 flags = hard_local_irq_save();
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr = bfin_read32(SIC_IWR);
24 /* Only allow PPL Wakeup) */
25 bfin_write32(SIC_IWR, IWR_ENABLE(0));
26
27 bfin_write16(PLL_CTL, val);
28 SSYNC();
29 asm("IDLE;");
30
31 bfin_write32(SIC_IWR, iwr);
32 hard_local_irq_restore(flags);
33}
34
35/* Writing to VR_CTL initiates a PLL relock sequence. */
36static __inline__ void bfin_write_VR_CTL(unsigned int val)
37{
38 unsigned long flags, iwr;
39
40 if (val == bfin_read_VR_CTL())
41 return;
42
43 flags = hard_local_irq_save();
44 /* Enable the PLL Wakeup bit in SIC IWR */
45 iwr = bfin_read32(SIC_IWR);
46 /* Only allow PPL Wakeup) */
47 bfin_write32(SIC_IWR, IWR_ENABLE(0));
48
49 bfin_write16(VR_CTL, val);
50 SSYNC();
51 asm("IDLE;");
52
53 bfin_write32(SIC_IWR, iwr);
54 hard_local_irq_restore(flags);
55}
56
57#endif /* _MACH_PLL_H */
diff --git a/arch/blackfin/mach-bf537/boards/Kconfig b/arch/blackfin/mach-bf537/boards/Kconfig
index 44132fda63be..a44bf3a1816e 100644
--- a/arch/blackfin/mach-bf537/boards/Kconfig
+++ b/arch/blackfin/mach-bf537/boards/Kconfig
@@ -39,4 +39,10 @@ config CAMSIG_MINOTAUR
39 help 39 help
40 Board supply package for CSP Minotaur 40 Board supply package for CSP Minotaur
41 41
42config DNP5370
43 bool "SSV Dil/NetPC DNP/5370"
44 depends on (BF537)
45 help
46 Board supply package for DNP/5370 DIL64 module
47
42endchoice 48endchoice
diff --git a/arch/blackfin/mach-bf537/boards/Makefile b/arch/blackfin/mach-bf537/boards/Makefile
index 7e6aa4e5b205..fe42258fe1f4 100644
--- a/arch/blackfin/mach-bf537/boards/Makefile
+++ b/arch/blackfin/mach-bf537/boards/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_BFIN537_BLUETECHNIX_CM_U) += cm_bf537u.o
8obj-$(CONFIG_BFIN537_BLUETECHNIX_TCM) += tcm_bf537.o 8obj-$(CONFIG_BFIN537_BLUETECHNIX_TCM) += tcm_bf537.o
9obj-$(CONFIG_PNAV10) += pnav10.o 9obj-$(CONFIG_PNAV10) += pnav10.o
10obj-$(CONFIG_CAMSIG_MINOTAUR) += minotaur.o 10obj-$(CONFIG_CAMSIG_MINOTAUR) += minotaur.o
11obj-$(CONFIG_DNP5370) += dnp5370.o
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537e.c b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
index 836698c4ee54..2c776e188a94 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537e.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
@@ -373,7 +373,7 @@ static struct resource bfin_uart0_resources[] = {
373#endif 373#endif
374}; 374};
375 375
376unsigned short bfin_uart0_peripherals[] = { 376static unsigned short bfin_uart0_peripherals[] = {
377 P_UART0_TX, P_UART0_RX, 0 377 P_UART0_TX, P_UART0_RX, 0
378}; 378};
379 379
@@ -434,7 +434,7 @@ static struct resource bfin_uart1_resources[] = {
434#endif 434#endif
435}; 435};
436 436
437unsigned short bfin_uart1_peripherals[] = { 437static unsigned short bfin_uart1_peripherals[] = {
438 P_UART1_TX, P_UART1_RX, 0 438 P_UART1_TX, P_UART1_RX, 0
439}; 439};
440 440
@@ -545,9 +545,9 @@ static struct resource bfin_sport0_uart_resources[] = {
545 }, 545 },
546}; 546};
547 547
548unsigned short bfin_sport0_peripherals[] = { 548static unsigned short bfin_sport0_peripherals[] = {
549 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 549 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
550 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 550 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
551}; 551};
552 552
553static struct platform_device bfin_sport0_uart_device = { 553static struct platform_device bfin_sport0_uart_device = {
@@ -579,9 +579,9 @@ static struct resource bfin_sport1_uart_resources[] = {
579 }, 579 },
580}; 580};
581 581
582unsigned short bfin_sport1_peripherals[] = { 582static unsigned short bfin_sport1_peripherals[] = {
583 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 583 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
584 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 584 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
585}; 585};
586 586
587static struct platform_device bfin_sport1_uart_device = { 587static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537u.c b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
index 2a85670273cb..085661175ec7 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537u.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
@@ -356,7 +356,7 @@ static struct resource bfin_uart0_resources[] = {
356 }, 356 },
357}; 357};
358 358
359unsigned short bfin_uart0_peripherals[] = { 359static unsigned short bfin_uart0_peripherals[] = {
360 P_UART0_TX, P_UART0_RX, 0 360 P_UART0_TX, P_UART0_RX, 0
361}; 361};
362 362
@@ -399,7 +399,7 @@ static struct resource bfin_uart1_resources[] = {
399 }, 399 },
400}; 400};
401 401
402unsigned short bfin_uart1_peripherals[] = { 402static unsigned short bfin_uart1_peripherals[] = {
403 P_UART1_TX, P_UART1_RX, 0 403 P_UART1_TX, P_UART1_RX, 0
404}; 404};
405 405
@@ -510,9 +510,9 @@ static struct resource bfin_sport0_uart_resources[] = {
510 }, 510 },
511}; 511};
512 512
513unsigned short bfin_sport0_peripherals[] = { 513static unsigned short bfin_sport0_peripherals[] = {
514 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 514 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
515 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 515 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
516}; 516};
517 517
518static struct platform_device bfin_sport0_uart_device = { 518static struct platform_device bfin_sport0_uart_device = {
@@ -544,9 +544,9 @@ static struct resource bfin_sport1_uart_resources[] = {
544 }, 544 },
545}; 545};
546 546
547unsigned short bfin_sport1_peripherals[] = { 547static unsigned short bfin_sport1_peripherals[] = {
548 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 548 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
549 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 549 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
550}; 550};
551 551
552static struct platform_device bfin_sport1_uart_device = { 552static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf537/boards/dnp5370.c b/arch/blackfin/mach-bf537/boards/dnp5370.c
new file mode 100644
index 000000000000..e1e9ea02ad89
--- /dev/null
+++ b/arch/blackfin/mach-bf537/boards/dnp5370.c
@@ -0,0 +1,418 @@
1/*
2 * This is the configuration for SSV Dil/NetPC DNP/5370 board.
3 *
4 * DIL module: http://www.dilnetpc.com/dnp0086.htm
5 * SK28 (starter kit): http://www.dilnetpc.com/dnp0088.htm
6 *
7 * Copyright 2010 3ality Digital Systems
8 * Copyright 2005 National ICT Australia (NICTA)
9 * Copyright 2004-2006 Analog Devices Inc.
10 *
11 * Licensed under the GPL-2 or later.
12 */
13
14#include <linux/device.h>
15#include <linux/kernel.h>
16#include <linux/platform_device.h>
17#include <linux/io.h>
18#include <linux/mtd/mtd.h>
19#include <linux/mtd/nand.h>
20#include <linux/mtd/partitions.h>
21#include <linux/mtd/plat-ram.h>
22#include <linux/mtd/physmap.h>
23#include <linux/spi/spi.h>
24#include <linux/spi/flash.h>
25#include <linux/irq.h>
26#include <linux/interrupt.h>
27#include <linux/i2c.h>
28#include <linux/spi/mmc_spi.h>
29#include <linux/phy.h>
30#include <asm/dma.h>
31#include <asm/bfin5xx_spi.h>
32#include <asm/reboot.h>
33#include <asm/portmux.h>
34#include <asm/dpmc.h>
35
36/*
37 * Name the Board for the /proc/cpuinfo
38 */
39const char bfin_board_name[] = "DNP/5370";
40#define FLASH_MAC 0x202f0000
41#define CONFIG_MTD_PHYSMAP_LEN 0x300000
42
43#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
44static struct platform_device rtc_device = {
45 .name = "rtc-bfin",
46 .id = -1,
47};
48#endif
49
50#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
51#include <linux/bfin_mac.h>
52static const unsigned short bfin_mac_peripherals[] = P_RMII0;
53
54static struct bfin_phydev_platform_data bfin_phydev_data[] = {
55 {
56 .addr = 1,
57 .irq = PHY_POLL, /* IRQ_MAC_PHYINT */
58 },
59};
60
61static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
62 .phydev_number = 1,
63 .phydev_data = bfin_phydev_data,
64 .phy_mode = PHY_INTERFACE_MODE_RMII,
65 .mac_peripherals = bfin_mac_peripherals,
66};
67
68static struct platform_device bfin_mii_bus = {
69 .name = "bfin_mii_bus",
70 .dev = {
71 .platform_data = &bfin_mii_bus_data,
72 }
73};
74
75static struct platform_device bfin_mac_device = {
76 .name = "bfin_mac",
77 .dev = {
78 .platform_data = &bfin_mii_bus,
79 }
80};
81#endif
82
83#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
84static struct mtd_partition asmb_flash_partitions[] = {
85 {
86 .name = "bootloader(nor)",
87 .size = 0x30000,
88 .offset = 0,
89 }, {
90 .name = "linux kernel and rootfs(nor)",
91 .size = 0x300000 - 0x30000 - 0x10000,
92 .offset = MTDPART_OFS_APPEND,
93 }, {
94 .name = "MAC address(nor)",
95 .size = 0x10000,
96 .offset = MTDPART_OFS_APPEND,
97 .mask_flags = MTD_WRITEABLE,
98 }
99};
100
101static struct physmap_flash_data asmb_flash_data = {
102 .width = 1,
103 .parts = asmb_flash_partitions,
104 .nr_parts = ARRAY_SIZE(asmb_flash_partitions),
105};
106
107static struct resource asmb_flash_resource = {
108 .start = 0x20000000,
109 .end = 0x202fffff,
110 .flags = IORESOURCE_MEM,
111};
112
113/* 4 MB NOR flash attached to async memory banks 0-2,
114 * therefore only 3 MB visible.
115 */
116static struct platform_device asmb_flash_device = {
117 .name = "physmap-flash",
118 .id = 0,
119 .dev = {
120 .platform_data = &asmb_flash_data,
121 },
122 .num_resources = 1,
123 .resource = &asmb_flash_resource,
124};
125#endif
126
127#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
128
129#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
130
131#define MMC_SPI_CARD_DETECT_INT IRQ_PF5
132
133static int bfin_mmc_spi_init(struct device *dev,
134 irqreturn_t (*detect_int)(int, void *), void *data)
135{
136 return request_irq(MMC_SPI_CARD_DETECT_INT, detect_int,
137 IRQF_TRIGGER_FALLING, "mmc-spi-detect", data);
138}
139
140static void bfin_mmc_spi_exit(struct device *dev, void *data)
141{
142 free_irq(MMC_SPI_CARD_DETECT_INT, data);
143}
144
145static struct bfin5xx_spi_chip mmc_spi_chip_info = {
146 .enable_dma = 0, /* use no dma transfer with this chip*/
147 .bits_per_word = 8,
148};
149
150static struct mmc_spi_platform_data bfin_mmc_spi_pdata = {
151 .init = bfin_mmc_spi_init,
152 .exit = bfin_mmc_spi_exit,
153 .detect_delay = 100, /* msecs */
154};
155#endif
156
157#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
158/* This mapping is for at45db642 it has 1056 page size,
159 * partition size and offset should be page aligned
160 */
161static struct mtd_partition bfin_spi_dataflash_partitions[] = {
162 {
163 .name = "JFFS2 dataflash(nor)",
164#ifdef CONFIG_MTD_PAGESIZE_1024
165 .offset = 0x40000,
166 .size = 0x7C0000,
167#else
168 .offset = 0x0,
169 .size = 0x840000,
170#endif
171 }
172};
173
174static struct flash_platform_data bfin_spi_dataflash_data = {
175 .name = "mtd_dataflash",
176 .parts = bfin_spi_dataflash_partitions,
177 .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
178 .type = "mtd_dataflash",
179};
180
181static struct bfin5xx_spi_chip spi_dataflash_chip_info = {
182 .enable_dma = 0, /* use no dma transfer with this chip*/
183 .bits_per_word = 8,
184};
185#endif
186
187static struct spi_board_info bfin_spi_board_info[] __initdata = {
188/* SD/MMC card reader at SPI bus */
189#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
190 {
191 .modalias = "mmc_spi",
192 .max_speed_hz = 20000000,
193 .bus_num = 0,
194 .chip_select = 1,
195 .platform_data = &bfin_mmc_spi_pdata,
196 .controller_data = &mmc_spi_chip_info,
197 .mode = SPI_MODE_3,
198 },
199#endif
200
201/* 8 Megabyte Atmel NOR flash chip at SPI bus */
202#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
203 {
204 .modalias = "mtd_dataflash",
205 .max_speed_hz = 16700000,
206 .bus_num = 0,
207 .chip_select = 2,
208 .platform_data = &bfin_spi_dataflash_data,
209 .controller_data = &spi_dataflash_chip_info,
210 .mode = SPI_MODE_3, /* SPI_CPHA and SPI_CPOL */
211 },
212#endif
213};
214
215/* SPI controller data */
216/* SPI (0) */
217static struct resource bfin_spi0_resource[] = {
218 [0] = {
219 .start = SPI0_REGBASE,
220 .end = SPI0_REGBASE + 0xFF,
221 .flags = IORESOURCE_MEM,
222 },
223 [1] = {
224 .start = CH_SPI,
225 .end = CH_SPI,
226 .flags = IORESOURCE_DMA,
227 },
228 [2] = {
229 .start = IRQ_SPI,
230 .end = IRQ_SPI,
231 .flags = IORESOURCE_IRQ,
232 },
233};
234
235static struct bfin5xx_spi_master spi_bfin_master_info = {
236 .num_chipselect = 8,
237 .enable_dma = 1, /* master has the ability to do dma transfer */
238 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
239};
240
241static struct platform_device spi_bfin_master_device = {
242 .name = "bfin-spi",
243 .id = 0, /* Bus number */
244 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
245 .resource = bfin_spi0_resource,
246 .dev = {
247 .platform_data = &spi_bfin_master_info, /* Passed to driver */
248 },
249};
250#endif
251
252#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
253#ifdef CONFIG_SERIAL_BFIN_UART0
254static struct resource bfin_uart0_resources[] = {
255 {
256 .start = UART0_THR,
257 .end = UART0_GCTL+2,
258 .flags = IORESOURCE_MEM,
259 },
260 {
261 .start = IRQ_UART0_RX,
262 .end = IRQ_UART0_RX+1,
263 .flags = IORESOURCE_IRQ,
264 },
265 {
266 .start = IRQ_UART0_ERROR,
267 .end = IRQ_UART0_ERROR,
268 .flags = IORESOURCE_IRQ,
269 },
270 {
271 .start = CH_UART0_TX,
272 .end = CH_UART0_TX,
273 .flags = IORESOURCE_DMA,
274 },
275 {
276 .start = CH_UART0_RX,
277 .end = CH_UART0_RX,
278 .flags = IORESOURCE_DMA,
279 },
280};
281
282static unsigned short bfin_uart0_peripherals[] = {
283 P_UART0_TX, P_UART0_RX, 0
284};
285
286static struct platform_device bfin_uart0_device = {
287 .name = "bfin-uart",
288 .id = 0,
289 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
290 .resource = bfin_uart0_resources,
291 .dev = {
292 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
293 },
294};
295#endif
296
297#ifdef CONFIG_SERIAL_BFIN_UART1
298static struct resource bfin_uart1_resources[] = {
299 {
300 .start = UART1_THR,
301 .end = UART1_GCTL+2,
302 .flags = IORESOURCE_MEM,
303 },
304 {
305 .start = IRQ_UART1_RX,
306 .end = IRQ_UART1_RX+1,
307 .flags = IORESOURCE_IRQ,
308 },
309 {
310 .start = IRQ_UART1_ERROR,
311 .end = IRQ_UART1_ERROR,
312 .flags = IORESOURCE_IRQ,
313 },
314 {
315 .start = CH_UART1_TX,
316 .end = CH_UART1_TX,
317 .flags = IORESOURCE_DMA,
318 },
319 {
320 .start = CH_UART1_RX,
321 .end = CH_UART1_RX,
322 .flags = IORESOURCE_DMA,
323 },
324};
325
326static unsigned short bfin_uart1_peripherals[] = {
327 P_UART1_TX, P_UART1_RX, 0
328};
329
330static struct platform_device bfin_uart1_device = {
331 .name = "bfin-uart",
332 .id = 1,
333 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
334 .resource = bfin_uart1_resources,
335 .dev = {
336 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
337 },
338};
339#endif
340#endif
341
342#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
343static struct resource bfin_twi0_resource[] = {
344 [0] = {
345 .start = TWI0_REGBASE,
346 .end = TWI0_REGBASE + 0xff,
347 .flags = IORESOURCE_MEM,
348 },
349 [1] = {
350 .start = IRQ_TWI,
351 .end = IRQ_TWI,
352 .flags = IORESOURCE_IRQ,
353 },
354};
355
356static struct platform_device i2c_bfin_twi_device = {
357 .name = "i2c-bfin-twi",
358 .id = 0,
359 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
360 .resource = bfin_twi0_resource,
361};
362#endif
363
364static struct platform_device *dnp5370_devices[] __initdata = {
365
366#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
367#ifdef CONFIG_SERIAL_BFIN_UART0
368 &bfin_uart0_device,
369#endif
370#ifdef CONFIG_SERIAL_BFIN_UART1
371 &bfin_uart1_device,
372#endif
373#endif
374
375#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
376 &asmb_flash_device,
377#endif
378
379#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
380 &bfin_mii_bus,
381 &bfin_mac_device,
382#endif
383
384#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
385 &spi_bfin_master_device,
386#endif
387
388#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
389 &i2c_bfin_twi_device,
390#endif
391
392#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
393 &rtc_device,
394#endif
395
396};
397
398static int __init dnp5370_init(void)
399{
400 printk(KERN_INFO "DNP/5370: registering device resources\n");
401 platform_add_devices(dnp5370_devices, ARRAY_SIZE(dnp5370_devices));
402 printk(KERN_INFO "DNP/5370: registering %zu SPI slave devices\n",
403 ARRAY_SIZE(bfin_spi_board_info));
404 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
405 printk(KERN_INFO "DNP/5370: MAC %pM\n", (void *)FLASH_MAC);
406 return 0;
407}
408arch_initcall(dnp5370_init);
409
410/*
411 * Currently the MAC address is saved in Flash by U-Boot
412 */
413void bfin_get_ether_addr(char *addr)
414{
415 *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC);
416 *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4);
417}
418EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c
index 49800518412c..bfb3671a78da 100644
--- a/arch/blackfin/mach-bf537/boards/minotaur.c
+++ b/arch/blackfin/mach-bf537/boards/minotaur.c
@@ -263,7 +263,7 @@ static struct resource bfin_uart0_resources[] = {
263 }, 263 },
264}; 264};
265 265
266unsigned short bfin_uart0_peripherals[] = { 266static unsigned short bfin_uart0_peripherals[] = {
267 P_UART0_TX, P_UART0_RX, 0 267 P_UART0_TX, P_UART0_RX, 0
268}; 268};
269 269
@@ -306,7 +306,7 @@ static struct resource bfin_uart1_resources[] = {
306 }, 306 },
307}; 307};
308 308
309unsigned short bfin_uart1_peripherals[] = { 309static unsigned short bfin_uart1_peripherals[] = {
310 P_UART1_TX, P_UART1_RX, 0 310 P_UART1_TX, P_UART1_RX, 0
311}; 311};
312 312
@@ -419,9 +419,9 @@ static struct resource bfin_sport0_uart_resources[] = {
419 }, 419 },
420}; 420};
421 421
422unsigned short bfin_sport0_peripherals[] = { 422static unsigned short bfin_sport0_peripherals[] = {
423 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 423 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
424 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 424 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
425}; 425};
426 426
427static struct platform_device bfin_sport0_uart_device = { 427static struct platform_device bfin_sport0_uart_device = {
@@ -453,9 +453,9 @@ static struct resource bfin_sport1_uart_resources[] = {
453 }, 453 },
454}; 454};
455 455
456unsigned short bfin_sport1_peripherals[] = { 456static unsigned short bfin_sport1_peripherals[] = {
457 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 457 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
458 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 458 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
459}; 459};
460 460
461static struct platform_device bfin_sport1_uart_device = { 461static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c
index b95807894e25..9389f03e3b0a 100644
--- a/arch/blackfin/mach-bf537/boards/pnav10.c
+++ b/arch/blackfin/mach-bf537/boards/pnav10.c
@@ -367,7 +367,7 @@ static struct resource bfin_uart0_resources[] = {
367 }, 367 },
368}; 368};
369 369
370unsigned short bfin_uart0_peripherals[] = { 370static unsigned short bfin_uart0_peripherals[] = {
371 P_UART0_TX, P_UART0_RX, 0 371 P_UART0_TX, P_UART0_RX, 0
372}; 372};
373 373
@@ -410,7 +410,7 @@ static struct resource bfin_uart1_resources[] = {
410 }, 410 },
411}; 411};
412 412
413unsigned short bfin_uart1_peripherals[] = { 413static unsigned short bfin_uart1_peripherals[] = {
414 P_UART1_TX, P_UART1_RX, 0 414 P_UART1_TX, P_UART1_RX, 0
415}; 415};
416 416
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index 3aa344ce8e52..2c69785a7bbe 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -289,7 +289,7 @@ static struct platform_device isp1362_hcd_device = {
289#endif 289#endif
290 290
291#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) 291#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
292unsigned short bfin_can_peripherals[] = { 292static unsigned short bfin_can_peripherals[] = {
293 P_CAN0_RX, P_CAN0_TX, 0 293 P_CAN0_RX, P_CAN0_TX, 0
294}; 294};
295 295
@@ -693,7 +693,7 @@ static struct bfin5xx_spi_chip ad2s90_spi_chip_info = {
693#endif 693#endif
694 694
695#if defined(CONFIG_AD2S120X) || defined(CONFIG_AD2S120X_MODULE) 695#if defined(CONFIG_AD2S120X) || defined(CONFIG_AD2S120X_MODULE)
696unsigned short ad2s120x_platform_data[] = { 696static unsigned short ad2s120x_platform_data[] = {
697 /* used as SAMPLE and RDVEL */ 697 /* used as SAMPLE and RDVEL */
698 GPIO_PF5, GPIO_PF6, 0 698 GPIO_PF5, GPIO_PF6, 0
699}; 699};
@@ -705,7 +705,7 @@ static struct bfin5xx_spi_chip ad2s120x_spi_chip_info = {
705#endif 705#endif
706 706
707#if defined(CONFIG_AD2S1210) || defined(CONFIG_AD2S1210_MODULE) 707#if defined(CONFIG_AD2S1210) || defined(CONFIG_AD2S1210_MODULE)
708unsigned short ad2s1210_platform_data[] = { 708static unsigned short ad2s1210_platform_data[] = {
709 /* use as SAMPLE, A0, A1 */ 709 /* use as SAMPLE, A0, A1 */
710 GPIO_PF7, GPIO_PF8, GPIO_PF9, 710 GPIO_PF7, GPIO_PF8, GPIO_PF9,
711# if defined(CONFIG_AD2S1210_GPIO_INPUT) || defined(CONFIG_AD2S1210_GPIO_OUTPUT) 711# if defined(CONFIG_AD2S1210_GPIO_INPUT) || defined(CONFIG_AD2S1210_GPIO_OUTPUT)
@@ -1717,7 +1717,7 @@ static struct resource bfin_uart0_resources[] = {
1717#endif 1717#endif
1718}; 1718};
1719 1719
1720unsigned short bfin_uart0_peripherals[] = { 1720static unsigned short bfin_uart0_peripherals[] = {
1721 P_UART0_TX, P_UART0_RX, 0 1721 P_UART0_TX, P_UART0_RX, 0
1722}; 1722};
1723 1723
@@ -1760,7 +1760,7 @@ static struct resource bfin_uart1_resources[] = {
1760 }, 1760 },
1761}; 1761};
1762 1762
1763unsigned short bfin_uart1_peripherals[] = { 1763static unsigned short bfin_uart1_peripherals[] = {
1764 P_UART1_TX, P_UART1_RX, 0 1764 P_UART1_TX, P_UART1_RX, 0
1765}; 1765};
1766 1766
@@ -2447,9 +2447,9 @@ static struct resource bfin_sport0_uart_resources[] = {
2447 }, 2447 },
2448}; 2448};
2449 2449
2450unsigned short bfin_sport0_peripherals[] = { 2450static unsigned short bfin_sport0_peripherals[] = {
2451 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 2451 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
2452 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 2452 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
2453}; 2453};
2454 2454
2455static struct platform_device bfin_sport0_uart_device = { 2455static struct platform_device bfin_sport0_uart_device = {
@@ -2481,9 +2481,9 @@ static struct resource bfin_sport1_uart_resources[] = {
2481 }, 2481 },
2482}; 2482};
2483 2483
2484unsigned short bfin_sport1_peripherals[] = { 2484static unsigned short bfin_sport1_peripherals[] = {
2485 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 2485 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
2486 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 2486 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
2487}; 2487};
2488 2488
2489static struct platform_device bfin_sport1_uart_device = { 2489static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
index 31498add1a42..0761b201abca 100644
--- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c
+++ b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
@@ -356,7 +356,7 @@ static struct resource bfin_uart0_resources[] = {
356 }, 356 },
357}; 357};
358 358
359unsigned short bfin_uart0_peripherals[] = { 359static unsigned short bfin_uart0_peripherals[] = {
360 P_UART0_TX, P_UART0_RX, 0 360 P_UART0_TX, P_UART0_RX, 0
361}; 361};
362 362
@@ -399,7 +399,7 @@ static struct resource bfin_uart1_resources[] = {
399 }, 399 },
400}; 400};
401 401
402unsigned short bfin_uart1_peripherals[] = { 402static unsigned short bfin_uart1_peripherals[] = {
403 P_UART1_TX, P_UART1_RX, 0 403 P_UART1_TX, P_UART1_RX, 0
404}; 404};
405 405
@@ -512,9 +512,9 @@ static struct resource bfin_sport0_uart_resources[] = {
512 }, 512 },
513}; 513};
514 514
515unsigned short bfin_sport0_peripherals[] = { 515static unsigned short bfin_sport0_peripherals[] = {
516 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 516 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
517 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 517 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
518}; 518};
519 519
520static struct platform_device bfin_sport0_uart_device = { 520static struct platform_device bfin_sport0_uart_device = {
@@ -546,9 +546,9 @@ static struct resource bfin_sport1_uart_resources[] = {
546 }, 546 },
547}; 547};
548 548
549unsigned short bfin_sport1_peripherals[] = { 549static unsigned short bfin_sport1_peripherals[] = {
550 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 550 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
551 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 551 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
552}; 552};
553 553
554static struct platform_device bfin_sport1_uart_device = { 554static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf537/dma.c b/arch/blackfin/mach-bf537/dma.c
index 5c8c4ed517bb..5c62e99c9fac 100644
--- a/arch/blackfin/mach-bf537/dma.c
+++ b/arch/blackfin/mach-bf537/dma.c
@@ -11,7 +11,7 @@
11#include <asm/blackfin.h> 11#include <asm/blackfin.h>
12#include <asm/dma.h> 12#include <asm/dma.h>
13 13
14struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { 14struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
15 (struct dma_register *) DMA0_NEXT_DESC_PTR, 15 (struct dma_register *) DMA0_NEXT_DESC_PTR,
16 (struct dma_register *) DMA1_NEXT_DESC_PTR, 16 (struct dma_register *) DMA1_NEXT_DESC_PTR,
17 (struct dma_register *) DMA2_NEXT_DESC_PTR, 17 (struct dma_register *) DMA2_NEXT_DESC_PTR,
diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_serial.h b/arch/blackfin/mach-bf537/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..00c603fe8218
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/bfin_serial.h
@@ -0,0 +1,14 @@
1/*
2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
3 *
4 * Copyright 2006-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_MACH_SERIAL_H__
10#define __BFIN_MACH_SERIAL_H__
11
12#define BFIN_UART_NR_PORTS 2
13
14#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
index 635c91c526a3..3e955dba8951 100644
--- a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
@@ -4,36 +4,9 @@
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later
5 */ 5 */
6 6
7#include <linux/serial.h>
8#include <asm/dma.h> 7#include <asm/dma.h>
9#include <asm/portmux.h> 8#include <asm/portmux.h>
10 9
11#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
12#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
13#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
14#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
15#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
16#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
17#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
18
19#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
20#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
21#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
22#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
23#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
24#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
25#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
26#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
27
28#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
29#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
30
31#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
32#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
33#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
34#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
35#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
36
37#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) 10#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
38# define CONFIG_SERIAL_BFIN_CTSRTS 11# define CONFIG_SERIAL_BFIN_CTSRTS
39 12
@@ -54,49 +27,6 @@
54# endif 27# endif
55#endif 28#endif
56 29
57#define BFIN_UART_TX_FIFO_SIZE 2
58
59/*
60 * The pin configuration is different from schematic
61 */
62struct bfin_serial_port {
63 struct uart_port port;
64 unsigned int old_status;
65 int status_irq;
66 unsigned int lsr;
67#ifdef CONFIG_SERIAL_BFIN_DMA
68 int tx_done;
69 int tx_count;
70 struct circ_buf rx_dma_buf;
71 struct timer_list rx_dma_timer;
72 int rx_dma_nrows;
73 unsigned int tx_dma_channel;
74 unsigned int rx_dma_channel;
75 struct work_struct tx_dma_workqueue;
76#endif
77#ifdef CONFIG_SERIAL_BFIN_CTSRTS
78 int cts_pin;
79 int rts_pin;
80#endif
81};
82
83/* The hardware clears the LSR bits upon read, so we need to cache
84 * some of the more fun bits in software so they don't get lost
85 * when checking the LSR in other code paths (TX).
86 */
87static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
88{
89 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
90 uart->lsr |= (lsr & (BI|FE|PE|OE));
91 return lsr | uart->lsr;
92}
93
94static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
95{
96 uart->lsr = 0;
97 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
98}
99
100struct bfin_serial_res { 30struct bfin_serial_res {
101 unsigned long uart_base_addr; 31 unsigned long uart_base_addr;
102 int uart_irq; 32 int uart_irq;
@@ -145,3 +75,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
145}; 75};
146 76
147#define DRIVER_NAME "bfin-uart" 77#define DRIVER_NAME "bfin-uart"
78
79#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf537/include/mach/blackfin.h b/arch/blackfin/mach-bf537/include/mach/blackfin.h
index a12d4b6a221d..baa096fc724a 100644
--- a/arch/blackfin/mach-bf537/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf537/include/mach/blackfin.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2005-2009 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later.
5 */ 5 */
6 6
7#ifndef _MACH_BLACKFIN_H_ 7#ifndef _MACH_BLACKFIN_H_
@@ -10,34 +10,24 @@
10#define BF537_FAMILY 10#define BF537_FAMILY
11 11
12#include "bf537.h" 12#include "bf537.h"
13#include "defBF534.h"
14#include "anomaly.h" 13#include "anomaly.h"
15 14
15#include <asm/def_LPBlackfin.h>
16#ifdef CONFIG_BF534
17# include "defBF534.h"
18#endif
16#if defined(CONFIG_BF537) || defined(CONFIG_BF536) 19#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
17#include "defBF537.h" 20# include "defBF537.h"
18#endif 21#endif
19 22
20#if !defined(__ASSEMBLY__) 23#if !defined(__ASSEMBLY__)
21#include "cdefBF534.h" 24# include <asm/cdef_LPBlackfin.h>
22 25# ifdef CONFIG_BF534
23#if defined(CONFIG_BF537) || defined(CONFIG_BF536) 26# include "cdefBF534.h"
24#include "cdefBF537.h" 27# endif
28# if defined(CONFIG_BF537) || defined(CONFIG_BF536)
29# include "cdefBF537.h"
30# endif
25#endif 31#endif
26#endif
27
28#define BFIN_UART_NR_PORTS 2
29
30#define OFFSET_THR 0x00 /* Transmit Holding register */
31#define OFFSET_RBR 0x00 /* Receive Buffer register */
32#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
33#define OFFSET_IER 0x04 /* Interrupt Enable Register */
34#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
35#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
36#define OFFSET_LCR 0x0C /* Line Control Register */
37#define OFFSET_MCR 0x10 /* Modem Control Register */
38#define OFFSET_LSR 0x14 /* Line Status Register */
39#define OFFSET_MSR 0x18 /* Modem Status Register */
40#define OFFSET_SCR 0x1C /* SCR Scratch Register */
41#define OFFSET_GCTL 0x24 /* Global Control Register */
42 32
43#endif 33#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
index fbeb35e14135..563ede907336 100644
--- a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2005-2008 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later
5 */ 5 */
@@ -7,14 +7,6 @@
7#ifndef _CDEF_BF534_H 7#ifndef _CDEF_BF534_H
8#define _CDEF_BF534_H 8#define _CDEF_BF534_H
9 9
10#include <asm/blackfin.h>
11
12/* Include all Core registers and bit definitions */
13#include "defBF534.h"
14
15/* Include core specific register pointer definitions */
16#include <asm/cdef_LPBlackfin.h>
17
18/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ 10/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
19#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 11#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
20#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 12#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
@@ -355,16 +347,10 @@
355#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val) 347#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
356 348
357/* DMA Traffic Control Registers */ 349/* DMA Traffic Control Registers */
358#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) 350#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
359#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val) 351#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val)
360#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) 352#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
361#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val) 353#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val)
362
363/* Alternate deprecated register names (below) provided for backwards code compatibility */
364#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
365#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val)
366#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
367#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val)
368 354
369/* DMA Controller */ 355/* DMA Controller */
370#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) 356#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
@@ -1747,7 +1733,4 @@
1747#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) 1733#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
1748#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT,val) 1734#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT,val)
1749 1735
1750/* These need to be last due to the cdef/linux inter-dependencies */
1751#include <asm/irq.h>
1752
1753#endif /* _CDEF_BF534_H */ 1736#endif /* _CDEF_BF534_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF537.h b/arch/blackfin/mach-bf537/include/mach/cdefBF537.h
index 9363c3990421..19ec21ea150a 100644
--- a/arch/blackfin/mach-bf537/include/mach/cdefBF537.h
+++ b/arch/blackfin/mach-bf537/include/mach/cdefBF537.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2005-2008 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later
5 */ 5 */
@@ -10,9 +10,6 @@
10/* Include MMRs Common to BF534 */ 10/* Include MMRs Common to BF534 */
11#include "cdefBF534.h" 11#include "cdefBF534.h"
12 12
13/* Include all Core registers and bit definitions */
14#include "defBF537.h"
15
16/* Include Macro "Defines" For EMAC (Unique to BF536/BF537 */ 13/* Include Macro "Defines" For EMAC (Unique to BF536/BF537 */
17/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ 14/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
18#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE) 15#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h
index 0323e6bacdae..32529a03b266 100644
--- a/arch/blackfin/mach-bf537/include/mach/defBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2005-2008 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
@@ -7,9 +7,6 @@
7#ifndef _DEF_BF534_H 7#ifndef _DEF_BF534_H
8#define _DEF_BF534_H 8#define _DEF_BF534_H
9 9
10/* Include all Core registers and bit definitions */
11#include <asm/def_LPBlackfin.h>
12
13/************************************************************************************ 10/************************************************************************************
14** System MMR Register Map 11** System MMR Register Map
15*************************************************************************************/ 12*************************************************************************************/
@@ -193,12 +190,8 @@
193#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ 190#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
194 191
195/* DMA Traffic Control Registers */ 192/* DMA Traffic Control Registers */
196#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ 193#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
197#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ 194#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
198
199/* Alternate deprecated register names (below) provided for backwards code compatibility */
200#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
201#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
202 195
203/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ 196/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
204#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ 197#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
@@ -1029,48 +1022,6 @@
1029#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ 1022#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
1030#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ 1023#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
1031 1024
1032/* ************** UART CONTROLLER MASKS *************************/
1033/* UARTx_LCR Masks */
1034#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
1035#define STB 0x04 /* Stop Bits */
1036#define PEN 0x08 /* Parity Enable */
1037#define EPS 0x10 /* Even Parity Select */
1038#define STP 0x20 /* Stick Parity */
1039#define SB 0x40 /* Set Break */
1040#define DLAB 0x80 /* Divisor Latch Access */
1041
1042/* UARTx_MCR Mask */
1043#define LOOP_ENA 0x10 /* Loopback Mode Enable */
1044#define LOOP_ENA_P 0x04
1045/* UARTx_LSR Masks */
1046#define DR 0x01 /* Data Ready */
1047#define OE 0x02 /* Overrun Error */
1048#define PE 0x04 /* Parity Error */
1049#define FE 0x08 /* Framing Error */
1050#define BI 0x10 /* Break Interrupt */
1051#define THRE 0x20 /* THR Empty */
1052#define TEMT 0x40 /* TSR and UART_THR Empty */
1053
1054/* UARTx_IER Masks */
1055#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
1056#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
1057#define ELSI 0x04 /* Enable RX Status Interrupt */
1058
1059/* UARTx_IIR Masks */
1060#define NINT 0x01 /* Pending Interrupt */
1061#define IIR_TX_READY 0x02 /* UART_THR empty */
1062#define IIR_RX_READY 0x04 /* Receive data ready */
1063#define IIR_LINE_CHANGE 0x06 /* Receive line status */
1064#define IIR_STATUS 0x06
1065
1066/* UARTx_GCTL Masks */
1067#define UCEN 0x01 /* Enable UARTx Clocks */
1068#define IREN 0x02 /* Enable IrDA Mode */
1069#define TPOLC 0x04 /* IrDA TX Polarity Change */
1070#define RPOLC 0x08 /* IrDA RX Polarity Change */
1071#define FPE 0x10 /* Force Parity Error On Transmit */
1072#define FFE 0x20 /* Force Framing Error On Transmit */
1073
1074/* **************** GENERAL PURPOSE TIMER MASKS **********************/ 1025/* **************** GENERAL PURPOSE TIMER MASKS **********************/
1075/* TIMER_ENABLE Masks */ 1026/* TIMER_ENABLE Masks */
1076#define TIMEN0 0x0001 /* Enable Timer 0 */ 1027#define TIMEN0 0x0001 /* Enable Timer 0 */
@@ -1141,62 +1092,6 @@
1141#define EMU_RUN 0x0200 /* Emulation Behavior Select */ 1092#define EMU_RUN 0x0200 /* Emulation Behavior Select */
1142#define ERR_TYP 0xC000 /* Error Type */ 1093#define ERR_TYP 0xC000 /* Error Type */
1143 1094
1144/* ****************** GPIO PORTS F, G, H MASKS ***********************/
1145/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
1146/* Port F Masks */
1147#define PF0 0x0001
1148#define PF1 0x0002
1149#define PF2 0x0004
1150#define PF3 0x0008
1151#define PF4 0x0010
1152#define PF5 0x0020
1153#define PF6 0x0040
1154#define PF7 0x0080
1155#define PF8 0x0100
1156#define PF9 0x0200
1157#define PF10 0x0400
1158#define PF11 0x0800
1159#define PF12 0x1000
1160#define PF13 0x2000
1161#define PF14 0x4000
1162#define PF15 0x8000
1163
1164/* Port G Masks */
1165#define PG0 0x0001
1166#define PG1 0x0002
1167#define PG2 0x0004
1168#define PG3 0x0008
1169#define PG4 0x0010
1170#define PG5 0x0020
1171#define PG6 0x0040
1172#define PG7 0x0080
1173#define PG8 0x0100
1174#define PG9 0x0200
1175#define PG10 0x0400
1176#define PG11 0x0800
1177#define PG12 0x1000
1178#define PG13 0x2000
1179#define PG14 0x4000
1180#define PG15 0x8000
1181
1182/* Port H Masks */
1183#define PH0 0x0001
1184#define PH1 0x0002
1185#define PH2 0x0004
1186#define PH3 0x0008
1187#define PH4 0x0010
1188#define PH5 0x0020
1189#define PH6 0x0040
1190#define PH7 0x0080
1191#define PH8 0x0100
1192#define PH9 0x0200
1193#define PH10 0x0400
1194#define PH11 0x0800
1195#define PH12 0x1000
1196#define PH13 0x2000
1197#define PH14 0x4000
1198#define PH15 0x8000
1199
1200/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/ 1095/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
1201/* EBIU_AMGCTL Masks */ 1096/* EBIU_AMGCTL Masks */
1202#define AMCKEN 0x0001 /* Enable CLKOUT */ 1097#define AMCKEN 0x0001 /* Enable CLKOUT */
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF537.h b/arch/blackfin/mach-bf537/include/mach/defBF537.h
index 8cb5d5cf0c94..3d471d752684 100644
--- a/arch/blackfin/mach-bf537/include/mach/defBF537.h
+++ b/arch/blackfin/mach-bf537/include/mach/defBF537.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2005-2008 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
@@ -7,9 +7,6 @@
7#ifndef _DEF_BF537_H 7#ifndef _DEF_BF537_H
8#define _DEF_BF537_H 8#define _DEF_BF537_H
9 9
10/* Include all Core registers and bit definitions*/
11#include <asm/cdef_LPBlackfin.h>
12
13/* Include all MMR and bit defines common to BF534 */ 10/* Include all MMR and bit defines common to BF534 */
14#include "defBF534.h" 11#include "defBF534.h"
15 12
diff --git a/arch/blackfin/mach-bf537/include/mach/gpio.h b/arch/blackfin/mach-bf537/include/mach/gpio.h
index f80c2995efdb..fba606b699c3 100644
--- a/arch/blackfin/mach-bf537/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf537/include/mach/gpio.h
@@ -62,4 +62,8 @@
62#define PORT_G GPIO_PG0 62#define PORT_G GPIO_PG0
63#define PORT_H GPIO_PH0 63#define PORT_H GPIO_PH0
64 64
65#include <mach-common/ports-f.h>
66#include <mach-common/ports-g.h>
67#include <mach-common/ports-h.h>
68
65#endif /* _MACH_GPIO_H_ */ 69#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf537/include/mach/pll.h b/arch/blackfin/mach-bf537/include/mach/pll.h
index 169c106d0edb..94cca674d835 100644
--- a/arch/blackfin/mach-bf537/include/mach/pll.h
+++ b/arch/blackfin/mach-bf537/include/mach/pll.h
@@ -1,57 +1 @@
1/* #include <mach-common/pll.h>
2 * Copyright 2005-2008 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 flags = hard_local_irq_save();
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr = bfin_read32(SIC_IWR);
24 /* Only allow PPL Wakeup) */
25 bfin_write32(SIC_IWR, IWR_ENABLE(0));
26
27 bfin_write16(PLL_CTL, val);
28 SSYNC();
29 asm("IDLE;");
30
31 bfin_write32(SIC_IWR, iwr);
32 hard_local_irq_restore(flags);
33}
34
35/* Writing to VR_CTL initiates a PLL relock sequence. */
36static __inline__ void bfin_write_VR_CTL(unsigned int val)
37{
38 unsigned long flags, iwr;
39
40 if (val == bfin_read_VR_CTL())
41 return;
42
43 flags = hard_local_irq_save();
44 /* Enable the PLL Wakeup bit in SIC IWR */
45 iwr = bfin_read32(SIC_IWR);
46 /* Only allow PPL Wakeup) */
47 bfin_write32(SIC_IWR, IWR_ENABLE(0));
48
49 bfin_write16(VR_CTL, val);
50 SSYNC();
51 asm("IDLE;");
52
53 bfin_write32(SIC_IWR, iwr);
54 hard_local_irq_restore(flags);
55}
56
57#endif /* _MACH_PLL_H */
diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c
index c6fb0a52f849..e61424ef35eb 100644
--- a/arch/blackfin/mach-bf538/boards/ezkit.c
+++ b/arch/blackfin/mach-bf538/boards/ezkit.c
@@ -82,7 +82,7 @@ static struct resource bfin_uart0_resources[] = {
82#endif 82#endif
83}; 83};
84 84
85unsigned short bfin_uart0_peripherals[] = { 85static unsigned short bfin_uart0_peripherals[] = {
86 P_UART0_TX, P_UART0_RX, 0 86 P_UART0_TX, P_UART0_RX, 0
87}; 87};
88 88
@@ -125,7 +125,7 @@ static struct resource bfin_uart1_resources[] = {
125 }, 125 },
126}; 126};
127 127
128unsigned short bfin_uart1_peripherals[] = { 128static unsigned short bfin_uart1_peripherals[] = {
129 P_UART1_TX, P_UART1_RX, 0 129 P_UART1_TX, P_UART1_RX, 0
130}; 130};
131 131
@@ -168,7 +168,7 @@ static struct resource bfin_uart2_resources[] = {
168 }, 168 },
169}; 169};
170 170
171unsigned short bfin_uart2_peripherals[] = { 171static unsigned short bfin_uart2_peripherals[] = {
172 P_UART2_TX, P_UART2_RX, 0 172 P_UART2_TX, P_UART2_RX, 0
173}; 173};
174 174
@@ -282,9 +282,9 @@ static struct resource bfin_sport0_uart_resources[] = {
282 }, 282 },
283}; 283};
284 284
285unsigned short bfin_sport0_peripherals[] = { 285static unsigned short bfin_sport0_peripherals[] = {
286 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 286 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
287 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 287 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
288}; 288};
289 289
290static struct platform_device bfin_sport0_uart_device = { 290static struct platform_device bfin_sport0_uart_device = {
@@ -316,9 +316,9 @@ static struct resource bfin_sport1_uart_resources[] = {
316 }, 316 },
317}; 317};
318 318
319unsigned short bfin_sport1_peripherals[] = { 319static unsigned short bfin_sport1_peripherals[] = {
320 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 320 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
321 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 321 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
322}; 322};
323 323
324static struct platform_device bfin_sport1_uart_device = { 324static struct platform_device bfin_sport1_uart_device = {
@@ -350,7 +350,7 @@ static struct resource bfin_sport2_uart_resources[] = {
350 }, 350 },
351}; 351};
352 352
353unsigned short bfin_sport2_peripherals[] = { 353static unsigned short bfin_sport2_peripherals[] = {
354 P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS, 354 P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
355 P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0 355 P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
356}; 356};
@@ -384,7 +384,7 @@ static struct resource bfin_sport3_uart_resources[] = {
384 }, 384 },
385}; 385};
386 386
387unsigned short bfin_sport3_peripherals[] = { 387static unsigned short bfin_sport3_peripherals[] = {
388 P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS, 388 P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
389 P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0 389 P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
390}; 390};
@@ -402,7 +402,7 @@ static struct platform_device bfin_sport3_uart_device = {
402#endif 402#endif
403 403
404#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) 404#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
405unsigned short bfin_can_peripherals[] = { 405static unsigned short bfin_can_peripherals[] = {
406 P_CAN0_RX, P_CAN0_TX, 0 406 P_CAN0_RX, P_CAN0_TX, 0
407}; 407};
408 408
diff --git a/arch/blackfin/mach-bf538/dma.c b/arch/blackfin/mach-bf538/dma.c
index 5dc022589214..cce8ef5a5cec 100644
--- a/arch/blackfin/mach-bf538/dma.c
+++ b/arch/blackfin/mach-bf538/dma.c
@@ -11,7 +11,7 @@
11#include <asm/blackfin.h> 11#include <asm/blackfin.h>
12#include <asm/dma.h> 12#include <asm/dma.h>
13 13
14struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { 14struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
15 (struct dma_register *) DMA0_NEXT_DESC_PTR, 15 (struct dma_register *) DMA0_NEXT_DESC_PTR,
16 (struct dma_register *) DMA1_NEXT_DESC_PTR, 16 (struct dma_register *) DMA1_NEXT_DESC_PTR,
17 (struct dma_register *) DMA2_NEXT_DESC_PTR, 17 (struct dma_register *) DMA2_NEXT_DESC_PTR,
@@ -32,14 +32,14 @@ struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
32 (struct dma_register *) DMA17_NEXT_DESC_PTR, 32 (struct dma_register *) DMA17_NEXT_DESC_PTR,
33 (struct dma_register *) DMA18_NEXT_DESC_PTR, 33 (struct dma_register *) DMA18_NEXT_DESC_PTR,
34 (struct dma_register *) DMA19_NEXT_DESC_PTR, 34 (struct dma_register *) DMA19_NEXT_DESC_PTR,
35 (struct dma_register *) MDMA0_D0_NEXT_DESC_PTR, 35 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
36 (struct dma_register *) MDMA0_S0_NEXT_DESC_PTR, 36 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
37 (struct dma_register *) MDMA0_D1_NEXT_DESC_PTR, 37 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
38 (struct dma_register *) MDMA0_S1_NEXT_DESC_PTR, 38 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
39 (struct dma_register *) MDMA1_D0_NEXT_DESC_PTR, 39 (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
40 (struct dma_register *) MDMA1_S0_NEXT_DESC_PTR, 40 (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
41 (struct dma_register *) MDMA1_D1_NEXT_DESC_PTR, 41 (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
42 (struct dma_register *) MDMA1_S1_NEXT_DESC_PTR, 42 (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
43}; 43};
44EXPORT_SYMBOL(dma_io_base_addr); 44EXPORT_SYMBOL(dma_io_base_addr);
45 45
diff --git a/arch/blackfin/mach-bf538/include/mach/bfin_serial.h b/arch/blackfin/mach-bf538/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..c66e2760aad3
--- /dev/null
+++ b/arch/blackfin/mach-bf538/include/mach/bfin_serial.h
@@ -0,0 +1,14 @@
1/*
2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
3 *
4 * Copyright 2006-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_MACH_SERIAL_H__
10#define __BFIN_MACH_SERIAL_H__
11
12#define BFIN_UART_NR_PORTS 3
13
14#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
index 5c148142f041..beb502e9cb33 100644
--- a/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
@@ -4,36 +4,9 @@
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
6 6
7#include <linux/serial.h>
8#include <asm/dma.h> 7#include <asm/dma.h>
9#include <asm/portmux.h> 8#include <asm/portmux.h>
10 9
11#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
12#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
13#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
14#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
15#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
16#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
17#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
18
19#define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v)
20#define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
21#define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v)
22#define UART_SET_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
23#define UART_CLEAR_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
24#define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
25#define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
26#define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
27
28#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
29#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
30
31#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
32#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
33#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
34#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
35#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
36
37#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) 10#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
38# define CONFIG_SERIAL_BFIN_CTSRTS 11# define CONFIG_SERIAL_BFIN_CTSRTS
39 12
@@ -54,50 +27,6 @@
54# endif 27# endif
55#endif 28#endif
56 29
57#define BFIN_UART_TX_FIFO_SIZE 2
58
59/*
60 * The pin configuration is different from schematic
61 */
62struct bfin_serial_port {
63 struct uart_port port;
64 unsigned int old_status;
65 int status_irq;
66 unsigned int lsr;
67#ifdef CONFIG_SERIAL_BFIN_DMA
68 int tx_done;
69 int tx_count;
70 struct circ_buf rx_dma_buf;
71 struct timer_list rx_dma_timer;
72 int rx_dma_nrows;
73 unsigned int tx_dma_channel;
74 unsigned int rx_dma_channel;
75 struct work_struct tx_dma_workqueue;
76#endif
77#ifdef CONFIG_SERIAL_BFIN_CTSRTS
78 struct timer_list cts_timer;
79 int cts_pin;
80 int rts_pin;
81#endif
82};
83
84/* The hardware clears the LSR bits upon read, so we need to cache
85 * some of the more fun bits in software so they don't get lost
86 * when checking the LSR in other code paths (TX).
87 */
88static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
89{
90 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
91 uart->lsr |= (lsr & (BI|FE|PE|OE));
92 return lsr | uart->lsr;
93}
94
95static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
96{
97 uart->lsr = 0;
98 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
99}
100
101struct bfin_serial_res { 30struct bfin_serial_res {
102 unsigned long uart_base_addr; 31 unsigned long uart_base_addr;
103 int uart_irq; 32 int uart_irq;
@@ -160,3 +89,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
160}; 89};
161 90
162#define DRIVER_NAME "bfin-uart" 91#define DRIVER_NAME "bfin-uart"
92
93#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf538/include/mach/blackfin.h b/arch/blackfin/mach-bf538/include/mach/blackfin.h
index 08b5eabb1ed5..791d08400cf0 100644
--- a/arch/blackfin/mach-bf538/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf538/include/mach/blackfin.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2008-2009 Analog Devices Inc. 2 * Copyright 2008-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
@@ -10,31 +10,24 @@
10#define BF538_FAMILY 10#define BF538_FAMILY
11 11
12#include "bf538.h" 12#include "bf538.h"
13#include "defBF539.h"
14#include "anomaly.h" 13#include "anomaly.h"
15 14
16 15#include <asm/def_LPBlackfin.h>
17#if !defined(__ASSEMBLY__) 16#ifdef CONFIG_BF538
18#include "cdefBF538.h" 17# include "defBF538.h"
19
20#if defined(CONFIG_BF539)
21#include "cdefBF539.h"
22#endif 18#endif
19#ifdef CONFIG_BF539
20# include "defBF539.h"
23#endif 21#endif
24 22
25#define BFIN_UART_NR_PORTS 3 23#ifndef __ASSEMBLY__
26 24# include <asm/cdef_LPBlackfin.h>
27#define OFFSET_THR 0x00 /* Transmit Holding register */ 25# ifdef CONFIG_BF538
28#define OFFSET_RBR 0x00 /* Receive Buffer register */ 26# include "cdefBF538.h"
29#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ 27# endif
30#define OFFSET_IER 0x04 /* Interrupt Enable Register */ 28# ifdef CONFIG_BF539
31#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ 29# include "cdefBF539.h"
32#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ 30# endif
33#define OFFSET_LCR 0x0C /* Line Control Register */ 31#endif
34#define OFFSET_MCR 0x10 /* Modem Control Register */
35#define OFFSET_LSR 0x14 /* Line Status Register */
36#define OFFSET_MSR 0x18 /* Modem Status Register */
37#define OFFSET_SCR 0x1C /* SCR Scratch Register */
38#define OFFSET_GCTL 0x24 /* Global Control Register */
39 32
40#endif 33#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
index 085b06b8c0a5..f6a56792180b 100644
--- a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
+++ b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2008-2009 Analog Devices Inc. 2 * Copyright 2008-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
@@ -7,14 +7,6 @@
7#ifndef _CDEF_BF538_H 7#ifndef _CDEF_BF538_H
8#define _CDEF_BF538_H 8#define _CDEF_BF538_H
9 9
10#include <asm/blackfin.h>
11
12/*include all Core registers and bit definitions*/
13#include "defBF539.h"
14
15/*include core specific register pointer definitions*/
16#include <asm/cdef_LPBlackfin.h>
17
18#define bfin_writePTR(addr, val) bfin_write32(addr, val) 10#define bfin_writePTR(addr, val) bfin_write32(addr, val)
19 11
20#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 12#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
@@ -487,10 +479,10 @@
487#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) 479#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
488#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) 480#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
489#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) 481#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
490#define bfin_read_DMA0_TC_PER() bfin_read16(DMA0_TC_PER) 482#define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER)
491#define bfin_write_DMA0_TC_PER(val) bfin_write16(DMA0_TC_PER, val) 483#define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER, val)
492#define bfin_read_DMA0_TC_CNT() bfin_read16(DMA0_TC_CNT) 484#define bfin_read_DMAC0_TC_CNT() bfin_read16(DMAC0_TC_CNT)
493#define bfin_write_DMA0_TC_CNT(val) bfin_write16(DMA0_TC_CNT, val) 485#define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT, val)
494#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR) 486#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
495#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val) 487#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
496#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR) 488#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
@@ -699,10 +691,10 @@
699#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) 691#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
700#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) 692#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
701#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) 693#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
702#define bfin_read_DMA1_TC_PER() bfin_read16(DMA1_TC_PER) 694#define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER)
703#define bfin_write_DMA1_TC_PER(val) bfin_write16(DMA1_TC_PER, val) 695#define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER, val)
704#define bfin_read_DMA1_TC_CNT() bfin_read16(DMA1_TC_CNT) 696#define bfin_read_DMAC1_TC_CNT() bfin_read16(DMAC1_TC_CNT)
705#define bfin_write_DMA1_TC_CNT(val) bfin_write16(DMA1_TC_CNT, val) 697#define bfin_write_DMAC1_TC_CNT(val) bfin_write16(DMAC1_TC_CNT, val)
706#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR) 698#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
707#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val) 699#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
708#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR) 700#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
@@ -1015,273 +1007,214 @@
1015#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val) 1007#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
1016#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT) 1008#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
1017#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val) 1009#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
1018#define bfin_read_MDMA0_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA0_D0_NEXT_DESC_PTR) 1010#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
1019#define bfin_write_MDMA0_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_D0_NEXT_DESC_PTR, val) 1011#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
1020#define bfin_read_MDMA0_D0_START_ADDR() bfin_readPTR(MDMA0_D0_START_ADDR) 1012#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
1021#define bfin_write_MDMA0_D0_START_ADDR(val) bfin_writePTR(MDMA0_D0_START_ADDR, val) 1013#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
1022#define bfin_read_MDMA0_D0_CONFIG() bfin_read16(MDMA0_D0_CONFIG) 1014#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
1023#define bfin_write_MDMA0_D0_CONFIG(val) bfin_write16(MDMA0_D0_CONFIG, val) 1015#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
1024#define bfin_read_MDMA0_D0_X_COUNT() bfin_read16(MDMA0_D0_X_COUNT) 1016#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
1025#define bfin_write_MDMA0_D0_X_COUNT(val) bfin_write16(MDMA0_D0_X_COUNT, val) 1017#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
1026#define bfin_read_MDMA0_D0_X_MODIFY() bfin_read16(MDMA0_D0_X_MODIFY) 1018#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
1027#define bfin_write_MDMA0_D0_X_MODIFY(val) bfin_write16(MDMA0_D0_X_MODIFY, val) 1019#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
1028#define bfin_read_MDMA0_D0_Y_COUNT() bfin_read16(MDMA0_D0_Y_COUNT) 1020#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
1029#define bfin_write_MDMA0_D0_Y_COUNT(val) bfin_write16(MDMA0_D0_Y_COUNT, val) 1021#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
1030#define bfin_read_MDMA0_D0_Y_MODIFY() bfin_read16(MDMA0_D0_Y_MODIFY) 1022#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
1031#define bfin_write_MDMA0_D0_Y_MODIFY(val) bfin_write16(MDMA0_D0_Y_MODIFY, val) 1023#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
1032#define bfin_read_MDMA0_D0_CURR_DESC_PTR() bfin_readPTR(MDMA0_D0_CURR_DESC_PTR) 1024#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
1033#define bfin_write_MDMA0_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_D0_CURR_DESC_PTR, val) 1025#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
1034#define bfin_read_MDMA0_D0_CURR_ADDR() bfin_readPTR(MDMA0_D0_CURR_ADDR) 1026#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
1035#define bfin_write_MDMA0_D0_CURR_ADDR(val) bfin_writePTR(MDMA0_D0_CURR_ADDR, val) 1027#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
1036#define bfin_read_MDMA0_D0_IRQ_STATUS() bfin_read16(MDMA0_D0_IRQ_STATUS) 1028#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
1037#define bfin_write_MDMA0_D0_IRQ_STATUS(val) bfin_write16(MDMA0_D0_IRQ_STATUS, val) 1029#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
1038#define bfin_read_MDMA0_D0_PERIPHERAL_MAP() bfin_read16(MDMA0_D0_PERIPHERAL_MAP) 1030#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
1039#define bfin_write_MDMA0_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA0_D0_PERIPHERAL_MAP, val) 1031#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
1040#define bfin_read_MDMA0_D0_CURR_X_COUNT() bfin_read16(MDMA0_D0_CURR_X_COUNT) 1032#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
1041#define bfin_write_MDMA0_D0_CURR_X_COUNT(val) bfin_write16(MDMA0_D0_CURR_X_COUNT, val) 1033#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
1042#define bfin_read_MDMA0_D0_CURR_Y_COUNT() bfin_read16(MDMA0_D0_CURR_Y_COUNT) 1034#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
1043#define bfin_write_MDMA0_D0_CURR_Y_COUNT(val) bfin_write16(MDMA0_D0_CURR_Y_COUNT, val) 1035#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
1044#define bfin_read_MDMA0_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA0_S0_NEXT_DESC_PTR) 1036#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
1045#define bfin_write_MDMA0_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_S0_NEXT_DESC_PTR, val) 1037#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
1046#define bfin_read_MDMA0_S0_START_ADDR() bfin_readPTR(MDMA0_S0_START_ADDR) 1038#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
1047#define bfin_write_MDMA0_S0_START_ADDR(val) bfin_writePTR(MDMA0_S0_START_ADDR, val) 1039#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
1048#define bfin_read_MDMA0_S0_CONFIG() bfin_read16(MDMA0_S0_CONFIG) 1040#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
1049#define bfin_write_MDMA0_S0_CONFIG(val) bfin_write16(MDMA0_S0_CONFIG, val) 1041#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
1050#define bfin_read_MDMA0_S0_X_COUNT() bfin_read16(MDMA0_S0_X_COUNT) 1042#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
1051#define bfin_write_MDMA0_S0_X_COUNT(val) bfin_write16(MDMA0_S0_X_COUNT, val) 1043#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
1052#define bfin_read_MDMA0_S0_X_MODIFY() bfin_read16(MDMA0_S0_X_MODIFY) 1044#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
1053#define bfin_write_MDMA0_S0_X_MODIFY(val) bfin_write16(MDMA0_S0_X_MODIFY, val) 1045#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
1054#define bfin_read_MDMA0_S0_Y_COUNT() bfin_read16(MDMA0_S0_Y_COUNT) 1046#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
1055#define bfin_write_MDMA0_S0_Y_COUNT(val) bfin_write16(MDMA0_S0_Y_COUNT, val) 1047#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
1056#define bfin_read_MDMA0_S0_Y_MODIFY() bfin_read16(MDMA0_S0_Y_MODIFY) 1048#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
1057#define bfin_write_MDMA0_S0_Y_MODIFY(val) bfin_write16(MDMA0_S0_Y_MODIFY, val) 1049#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
1058#define bfin_read_MDMA0_S0_CURR_DESC_PTR() bfin_readPTR(MDMA0_S0_CURR_DESC_PTR) 1050#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
1059#define bfin_write_MDMA0_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_S0_CURR_DESC_PTR, val) 1051#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
1060#define bfin_read_MDMA0_S0_CURR_ADDR() bfin_readPTR(MDMA0_S0_CURR_ADDR) 1052#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
1061#define bfin_write_MDMA0_S0_CURR_ADDR(val) bfin_writePTR(MDMA0_S0_CURR_ADDR, val) 1053#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
1062#define bfin_read_MDMA0_S0_IRQ_STATUS() bfin_read16(MDMA0_S0_IRQ_STATUS) 1054#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
1063#define bfin_write_MDMA0_S0_IRQ_STATUS(val) bfin_write16(MDMA0_S0_IRQ_STATUS, val) 1055#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
1064#define bfin_read_MDMA0_S0_PERIPHERAL_MAP() bfin_read16(MDMA0_S0_PERIPHERAL_MAP) 1056#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
1065#define bfin_write_MDMA0_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA0_S0_PERIPHERAL_MAP, val) 1057#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
1066#define bfin_read_MDMA0_S0_CURR_X_COUNT() bfin_read16(MDMA0_S0_CURR_X_COUNT) 1058#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
1067#define bfin_write_MDMA0_S0_CURR_X_COUNT(val) bfin_write16(MDMA0_S0_CURR_X_COUNT, val) 1059#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
1068#define bfin_read_MDMA0_S0_CURR_Y_COUNT() bfin_read16(MDMA0_S0_CURR_Y_COUNT) 1060#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
1069#define bfin_write_MDMA0_S0_CURR_Y_COUNT(val) bfin_write16(MDMA0_S0_CURR_Y_COUNT, val) 1061#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
1070#define bfin_read_MDMA0_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA0_D1_NEXT_DESC_PTR) 1062#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
1071#define bfin_write_MDMA0_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_D1_NEXT_DESC_PTR, val) 1063#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
1072#define bfin_read_MDMA0_D1_START_ADDR() bfin_readPTR(MDMA0_D1_START_ADDR) 1064#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
1073#define bfin_write_MDMA0_D1_START_ADDR(val) bfin_writePTR(MDMA0_D1_START_ADDR, val) 1065#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
1074#define bfin_read_MDMA0_D1_CONFIG() bfin_read16(MDMA0_D1_CONFIG) 1066#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
1075#define bfin_write_MDMA0_D1_CONFIG(val) bfin_write16(MDMA0_D1_CONFIG, val) 1067#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
1076#define bfin_read_MDMA0_D1_X_COUNT() bfin_read16(MDMA0_D1_X_COUNT) 1068#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
1077#define bfin_write_MDMA0_D1_X_COUNT(val) bfin_write16(MDMA0_D1_X_COUNT, val) 1069#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
1078#define bfin_read_MDMA0_D1_X_MODIFY() bfin_read16(MDMA0_D1_X_MODIFY) 1070#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
1079#define bfin_write_MDMA0_D1_X_MODIFY(val) bfin_write16(MDMA0_D1_X_MODIFY, val) 1071#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
1080#define bfin_read_MDMA0_D1_Y_COUNT() bfin_read16(MDMA0_D1_Y_COUNT) 1072#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
1081#define bfin_write_MDMA0_D1_Y_COUNT(val) bfin_write16(MDMA0_D1_Y_COUNT, val) 1073#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
1082#define bfin_read_MDMA0_D1_Y_MODIFY() bfin_read16(MDMA0_D1_Y_MODIFY) 1074#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
1083#define bfin_write_MDMA0_D1_Y_MODIFY(val) bfin_write16(MDMA0_D1_Y_MODIFY, val) 1075#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
1084#define bfin_read_MDMA0_D1_CURR_DESC_PTR() bfin_readPTR(MDMA0_D1_CURR_DESC_PTR) 1076#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
1085#define bfin_write_MDMA0_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_D1_CURR_DESC_PTR, val) 1077#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
1086#define bfin_read_MDMA0_D1_CURR_ADDR() bfin_readPTR(MDMA0_D1_CURR_ADDR) 1078#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
1087#define bfin_write_MDMA0_D1_CURR_ADDR(val) bfin_writePTR(MDMA0_D1_CURR_ADDR, val) 1079#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
1088#define bfin_read_MDMA0_D1_IRQ_STATUS() bfin_read16(MDMA0_D1_IRQ_STATUS) 1080#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
1089#define bfin_write_MDMA0_D1_IRQ_STATUS(val) bfin_write16(MDMA0_D1_IRQ_STATUS, val) 1081#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
1090#define bfin_read_MDMA0_D1_PERIPHERAL_MAP() bfin_read16(MDMA0_D1_PERIPHERAL_MAP) 1082#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
1091#define bfin_write_MDMA0_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA0_D1_PERIPHERAL_MAP, val) 1083#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
1092#define bfin_read_MDMA0_D1_CURR_X_COUNT() bfin_read16(MDMA0_D1_CURR_X_COUNT) 1084#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
1093#define bfin_write_MDMA0_D1_CURR_X_COUNT(val) bfin_write16(MDMA0_D1_CURR_X_COUNT, val) 1085#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
1094#define bfin_read_MDMA0_D1_CURR_Y_COUNT() bfin_read16(MDMA0_D1_CURR_Y_COUNT) 1086#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
1095#define bfin_write_MDMA0_D1_CURR_Y_COUNT(val) bfin_write16(MDMA0_D1_CURR_Y_COUNT, val) 1087#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
1096#define bfin_read_MDMA0_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA0_S1_NEXT_DESC_PTR) 1088#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
1097#define bfin_write_MDMA0_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_S1_NEXT_DESC_PTR, val) 1089#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
1098#define bfin_read_MDMA0_S1_START_ADDR() bfin_readPTR(MDMA0_S1_START_ADDR) 1090#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
1099#define bfin_write_MDMA0_S1_START_ADDR(val) bfin_writePTR(MDMA0_S1_START_ADDR, val) 1091#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
1100#define bfin_read_MDMA0_S1_CONFIG() bfin_read16(MDMA0_S1_CONFIG) 1092#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
1101#define bfin_write_MDMA0_S1_CONFIG(val) bfin_write16(MDMA0_S1_CONFIG, val) 1093#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
1102#define bfin_read_MDMA0_S1_X_COUNT() bfin_read16(MDMA0_S1_X_COUNT) 1094#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
1103#define bfin_write_MDMA0_S1_X_COUNT(val) bfin_write16(MDMA0_S1_X_COUNT, val) 1095#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
1104#define bfin_read_MDMA0_S1_X_MODIFY() bfin_read16(MDMA0_S1_X_MODIFY) 1096#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
1105#define bfin_write_MDMA0_S1_X_MODIFY(val) bfin_write16(MDMA0_S1_X_MODIFY, val) 1097#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
1106#define bfin_read_MDMA0_S1_Y_COUNT() bfin_read16(MDMA0_S1_Y_COUNT) 1098#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
1107#define bfin_write_MDMA0_S1_Y_COUNT(val) bfin_write16(MDMA0_S1_Y_COUNT, val) 1099#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
1108#define bfin_read_MDMA0_S1_Y_MODIFY() bfin_read16(MDMA0_S1_Y_MODIFY) 1100#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
1109#define bfin_write_MDMA0_S1_Y_MODIFY(val) bfin_write16(MDMA0_S1_Y_MODIFY, val) 1101#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
1110#define bfin_read_MDMA0_S1_CURR_DESC_PTR() bfin_readPTR(MDMA0_S1_CURR_DESC_PTR) 1102#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
1111#define bfin_write_MDMA0_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_S1_CURR_DESC_PTR, val) 1103#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
1112#define bfin_read_MDMA0_S1_CURR_ADDR() bfin_readPTR(MDMA0_S1_CURR_ADDR) 1104#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
1113#define bfin_write_MDMA0_S1_CURR_ADDR(val) bfin_writePTR(MDMA0_S1_CURR_ADDR, val) 1105#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
1114#define bfin_read_MDMA0_S1_IRQ_STATUS() bfin_read16(MDMA0_S1_IRQ_STATUS) 1106#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
1115#define bfin_write_MDMA0_S1_IRQ_STATUS(val) bfin_write16(MDMA0_S1_IRQ_STATUS, val) 1107#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
1116#define bfin_read_MDMA0_S1_PERIPHERAL_MAP() bfin_read16(MDMA0_S1_PERIPHERAL_MAP) 1108#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
1117#define bfin_write_MDMA0_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA0_S1_PERIPHERAL_MAP, val) 1109#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
1118#define bfin_read_MDMA0_S1_CURR_X_COUNT() bfin_read16(MDMA0_S1_CURR_X_COUNT) 1110#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
1119#define bfin_write_MDMA0_S1_CURR_X_COUNT(val) bfin_write16(MDMA0_S1_CURR_X_COUNT, val) 1111#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
1120#define bfin_read_MDMA0_S1_CURR_Y_COUNT() bfin_read16(MDMA0_S1_CURR_Y_COUNT) 1112#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
1121#define bfin_write_MDMA0_S1_CURR_Y_COUNT(val) bfin_write16(MDMA0_S1_CURR_Y_COUNT, val) 1113#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
1122#define bfin_read_MDMA1_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D0_NEXT_DESC_PTR) 1114#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
1123#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D0_NEXT_DESC_PTR, val) 1115#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
1124#define bfin_read_MDMA1_D0_START_ADDR() bfin_readPTR(MDMA1_D0_START_ADDR) 1116#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
1125#define bfin_write_MDMA1_D0_START_ADDR(val) bfin_writePTR(MDMA1_D0_START_ADDR, val) 1117#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
1126#define bfin_read_MDMA1_D0_CONFIG() bfin_read16(MDMA1_D0_CONFIG) 1118#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
1127#define bfin_write_MDMA1_D0_CONFIG(val) bfin_write16(MDMA1_D0_CONFIG, val) 1119#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
1128#define bfin_read_MDMA1_D0_X_COUNT() bfin_read16(MDMA1_D0_X_COUNT) 1120#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
1129#define bfin_write_MDMA1_D0_X_COUNT(val) bfin_write16(MDMA1_D0_X_COUNT, val) 1121#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
1130#define bfin_read_MDMA1_D0_X_MODIFY() bfin_read16(MDMA1_D0_X_MODIFY) 1122#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
1131#define bfin_write_MDMA1_D0_X_MODIFY(val) bfin_write16(MDMA1_D0_X_MODIFY, val) 1123#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
1132#define bfin_read_MDMA1_D0_Y_COUNT() bfin_read16(MDMA1_D0_Y_COUNT) 1124#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
1133#define bfin_write_MDMA1_D0_Y_COUNT(val) bfin_write16(MDMA1_D0_Y_COUNT, val) 1125#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
1134#define bfin_read_MDMA1_D0_Y_MODIFY() bfin_read16(MDMA1_D0_Y_MODIFY) 1126#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
1135#define bfin_write_MDMA1_D0_Y_MODIFY(val) bfin_write16(MDMA1_D0_Y_MODIFY, val) 1127#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
1136#define bfin_read_MDMA1_D0_CURR_DESC_PTR() bfin_readPTR(MDMA1_D0_CURR_DESC_PTR) 1128#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
1137#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D0_CURR_DESC_PTR, val) 1129#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
1138#define bfin_read_MDMA1_D0_CURR_ADDR() bfin_readPTR(MDMA1_D0_CURR_ADDR) 1130#define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR)
1139#define bfin_write_MDMA1_D0_CURR_ADDR(val) bfin_writePTR(MDMA1_D0_CURR_ADDR, val) 1131#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
1140#define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS) 1132#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
1141#define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS, val) 1133#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
1142#define bfin_read_MDMA1_D0_PERIPHERAL_MAP() bfin_read16(MDMA1_D0_PERIPHERAL_MAP) 1134#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
1143#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP, val) 1135#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
1144#define bfin_read_MDMA1_D0_CURR_X_COUNT() bfin_read16(MDMA1_D0_CURR_X_COUNT) 1136#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
1145#define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT, val) 1137#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
1146#define bfin_read_MDMA1_D0_CURR_Y_COUNT() bfin_read16(MDMA1_D0_CURR_Y_COUNT) 1138#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
1147#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT, val) 1139#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
1148#define bfin_read_MDMA1_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S0_NEXT_DESC_PTR) 1140#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
1149#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S0_NEXT_DESC_PTR, val) 1141#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
1150#define bfin_read_MDMA1_S0_START_ADDR() bfin_readPTR(MDMA1_S0_START_ADDR) 1142#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
1151#define bfin_write_MDMA1_S0_START_ADDR(val) bfin_writePTR(MDMA1_S0_START_ADDR, val) 1143#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
1152#define bfin_read_MDMA1_S0_CONFIG() bfin_read16(MDMA1_S0_CONFIG) 1144#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
1153#define bfin_write_MDMA1_S0_CONFIG(val) bfin_write16(MDMA1_S0_CONFIG, val) 1145#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
1154#define bfin_read_MDMA1_S0_X_COUNT() bfin_read16(MDMA1_S0_X_COUNT) 1146#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
1155#define bfin_write_MDMA1_S0_X_COUNT(val) bfin_write16(MDMA1_S0_X_COUNT, val) 1147#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
1156#define bfin_read_MDMA1_S0_X_MODIFY() bfin_read16(MDMA1_S0_X_MODIFY) 1148#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
1157#define bfin_write_MDMA1_S0_X_MODIFY(val) bfin_write16(MDMA1_S0_X_MODIFY, val) 1149#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
1158#define bfin_read_MDMA1_S0_Y_COUNT() bfin_read16(MDMA1_S0_Y_COUNT) 1150#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
1159#define bfin_write_MDMA1_S0_Y_COUNT(val) bfin_write16(MDMA1_S0_Y_COUNT, val) 1151#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
1160#define bfin_read_MDMA1_S0_Y_MODIFY() bfin_read16(MDMA1_S0_Y_MODIFY) 1152#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
1161#define bfin_write_MDMA1_S0_Y_MODIFY(val) bfin_write16(MDMA1_S0_Y_MODIFY, val) 1153#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
1162#define bfin_read_MDMA1_S0_CURR_DESC_PTR() bfin_readPTR(MDMA1_S0_CURR_DESC_PTR) 1154#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
1163#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S0_CURR_DESC_PTR, val) 1155#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
1164#define bfin_read_MDMA1_S0_CURR_ADDR() bfin_readPTR(MDMA1_S0_CURR_ADDR) 1156#define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR)
1165#define bfin_write_MDMA1_S0_CURR_ADDR(val) bfin_writePTR(MDMA1_S0_CURR_ADDR, val) 1157#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
1166#define bfin_read_MDMA1_S0_IRQ_STATUS() bfin_read16(MDMA1_S0_IRQ_STATUS) 1158#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
1167#define bfin_write_MDMA1_S0_IRQ_STATUS(val) bfin_write16(MDMA1_S0_IRQ_STATUS, val) 1159#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
1168#define bfin_read_MDMA1_S0_PERIPHERAL_MAP() bfin_read16(MDMA1_S0_PERIPHERAL_MAP) 1160#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
1169#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP, val) 1161#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
1170#define bfin_read_MDMA1_S0_CURR_X_COUNT() bfin_read16(MDMA1_S0_CURR_X_COUNT) 1162#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
1171#define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT, val) 1163#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
1172#define bfin_read_MDMA1_S0_CURR_Y_COUNT() bfin_read16(MDMA1_S0_CURR_Y_COUNT) 1164#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
1173#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT, val) 1165#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
1174#define bfin_read_MDMA1_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D1_NEXT_DESC_PTR) 1166#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
1175#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D1_NEXT_DESC_PTR, val) 1167#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
1176#define bfin_read_MDMA1_D1_START_ADDR() bfin_readPTR(MDMA1_D1_START_ADDR) 1168#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
1177#define bfin_write_MDMA1_D1_START_ADDR(val) bfin_writePTR(MDMA1_D1_START_ADDR, val) 1169#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
1178#define bfin_read_MDMA1_D1_CONFIG() bfin_read16(MDMA1_D1_CONFIG) 1170#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
1179#define bfin_write_MDMA1_D1_CONFIG(val) bfin_write16(MDMA1_D1_CONFIG, val) 1171#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
1180#define bfin_read_MDMA1_D1_X_COUNT() bfin_read16(MDMA1_D1_X_COUNT) 1172#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
1181#define bfin_write_MDMA1_D1_X_COUNT(val) bfin_write16(MDMA1_D1_X_COUNT, val) 1173#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
1182#define bfin_read_MDMA1_D1_X_MODIFY() bfin_read16(MDMA1_D1_X_MODIFY) 1174#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
1183#define bfin_write_MDMA1_D1_X_MODIFY(val) bfin_write16(MDMA1_D1_X_MODIFY, val) 1175#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
1184#define bfin_read_MDMA1_D1_Y_COUNT() bfin_read16(MDMA1_D1_Y_COUNT) 1176#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
1185#define bfin_write_MDMA1_D1_Y_COUNT(val) bfin_write16(MDMA1_D1_Y_COUNT, val) 1177#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
1186#define bfin_read_MDMA1_D1_Y_MODIFY() bfin_read16(MDMA1_D1_Y_MODIFY) 1178#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
1187#define bfin_write_MDMA1_D1_Y_MODIFY(val) bfin_write16(MDMA1_D1_Y_MODIFY, val) 1179#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
1188#define bfin_read_MDMA1_D1_CURR_DESC_PTR() bfin_readPTR(MDMA1_D1_CURR_DESC_PTR) 1180#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
1189#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D1_CURR_DESC_PTR, val) 1181#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
1190#define bfin_read_MDMA1_D1_CURR_ADDR() bfin_readPTR(MDMA1_D1_CURR_ADDR) 1182#define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR)
1191#define bfin_write_MDMA1_D1_CURR_ADDR(val) bfin_writePTR(MDMA1_D1_CURR_ADDR, val) 1183#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
1192#define bfin_read_MDMA1_D1_IRQ_STATUS() bfin_read16(MDMA1_D1_IRQ_STATUS) 1184#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
1193#define bfin_write_MDMA1_D1_IRQ_STATUS(val) bfin_write16(MDMA1_D1_IRQ_STATUS, val) 1185#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
1194#define bfin_read_MDMA1_D1_PERIPHERAL_MAP() bfin_read16(MDMA1_D1_PERIPHERAL_MAP) 1186#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
1195#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP, val) 1187#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
1196#define bfin_read_MDMA1_D1_CURR_X_COUNT() bfin_read16(MDMA1_D1_CURR_X_COUNT) 1188#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
1197#define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT, val) 1189#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
1198#define bfin_read_MDMA1_D1_CURR_Y_COUNT() bfin_read16(MDMA1_D1_CURR_Y_COUNT) 1190#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
1199#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT, val) 1191#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
1200#define bfin_read_MDMA1_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S1_NEXT_DESC_PTR) 1192#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
1201#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S1_NEXT_DESC_PTR, val) 1193#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
1202#define bfin_read_MDMA1_S1_START_ADDR() bfin_readPTR(MDMA1_S1_START_ADDR) 1194#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
1203#define bfin_write_MDMA1_S1_START_ADDR(val) bfin_writePTR(MDMA1_S1_START_ADDR, val) 1195#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
1204#define bfin_read_MDMA1_S1_CONFIG() bfin_read16(MDMA1_S1_CONFIG) 1196#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
1205#define bfin_write_MDMA1_S1_CONFIG(val) bfin_write16(MDMA1_S1_CONFIG, val) 1197#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
1206#define bfin_read_MDMA1_S1_X_COUNT() bfin_read16(MDMA1_S1_X_COUNT) 1198#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
1207#define bfin_write_MDMA1_S1_X_COUNT(val) bfin_write16(MDMA1_S1_X_COUNT, val) 1199#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
1208#define bfin_read_MDMA1_S1_X_MODIFY() bfin_read16(MDMA1_S1_X_MODIFY) 1200#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
1209#define bfin_write_MDMA1_S1_X_MODIFY(val) bfin_write16(MDMA1_S1_X_MODIFY, val) 1201#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
1210#define bfin_read_MDMA1_S1_Y_COUNT() bfin_read16(MDMA1_S1_Y_COUNT) 1202#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
1211#define bfin_write_MDMA1_S1_Y_COUNT(val) bfin_write16(MDMA1_S1_Y_COUNT, val) 1203#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
1212#define bfin_read_MDMA1_S1_Y_MODIFY() bfin_read16(MDMA1_S1_Y_MODIFY) 1204#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
1213#define bfin_write_MDMA1_S1_Y_MODIFY(val) bfin_write16(MDMA1_S1_Y_MODIFY, val) 1205#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
1214#define bfin_read_MDMA1_S1_CURR_DESC_PTR() bfin_readPTR(MDMA1_S1_CURR_DESC_PTR) 1206#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
1215#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S1_CURR_DESC_PTR, val) 1207#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
1216#define bfin_read_MDMA1_S1_CURR_ADDR() bfin_readPTR(MDMA1_S1_CURR_ADDR) 1208#define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR)
1217#define bfin_write_MDMA1_S1_CURR_ADDR(val) bfin_writePTR(MDMA1_S1_CURR_ADDR, val) 1209#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
1218#define bfin_read_MDMA1_S1_IRQ_STATUS() bfin_read16(MDMA1_S1_IRQ_STATUS) 1210#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
1219#define bfin_write_MDMA1_S1_IRQ_STATUS(val) bfin_write16(MDMA1_S1_IRQ_STATUS, val) 1211#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
1220#define bfin_read_MDMA1_S1_PERIPHERAL_MAP() bfin_read16(MDMA1_S1_PERIPHERAL_MAP) 1212#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
1221#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP, val) 1213#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
1222#define bfin_read_MDMA1_S1_CURR_X_COUNT() bfin_read16(MDMA1_S1_CURR_X_COUNT) 1214#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
1223#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT, val) 1215#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
1224#define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT) 1216#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
1225#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT, val) 1217#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
1226
1227#define bfin_read_MDMA_S0_CONFIG() bfin_read_MDMA0_S0_CONFIG()
1228#define bfin_write_MDMA_S0_CONFIG(val) bfin_write_MDMA0_S0_CONFIG(val)
1229#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read_MDMA0_S0_IRQ_STATUS()
1230#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write_MDMA0_S0_IRQ_STATUS(val)
1231#define bfin_read_MDMA_S0_X_MODIFY() bfin_read_MDMA0_S0_X_MODIFY()
1232#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write_MDMA0_S0_X_MODIFY(val)
1233#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read_MDMA0_S0_Y_MODIFY()
1234#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write_MDMA0_S0_Y_MODIFY(val)
1235#define bfin_read_MDMA_S0_X_COUNT() bfin_read_MDMA0_S0_X_COUNT()
1236#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write_MDMA0_S0_X_COUNT(val)
1237#define bfin_read_MDMA_S0_Y_COUNT() bfin_read_MDMA0_S0_Y_COUNT()
1238#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write_MDMA0_S0_Y_COUNT(val)
1239#define bfin_read_MDMA_S0_START_ADDR() bfin_read_MDMA0_S0_START_ADDR()
1240#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write_MDMA0_S0_START_ADDR(val)
1241#define bfin_read_MDMA_D0_CONFIG() bfin_read_MDMA0_D0_CONFIG()
1242#define bfin_write_MDMA_D0_CONFIG(val) bfin_write_MDMA0_D0_CONFIG(val)
1243#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read_MDMA0_D0_IRQ_STATUS()
1244#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write_MDMA0_D0_IRQ_STATUS(val)
1245#define bfin_read_MDMA_D0_X_MODIFY() bfin_read_MDMA0_D0_X_MODIFY()
1246#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write_MDMA0_D0_X_MODIFY(val)
1247#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read_MDMA0_D0_Y_MODIFY()
1248#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write_MDMA0_D0_Y_MODIFY(val)
1249#define bfin_read_MDMA_D0_X_COUNT() bfin_read_MDMA0_D0_X_COUNT()
1250#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write_MDMA0_D0_X_COUNT(val)
1251#define bfin_read_MDMA_D0_Y_COUNT() bfin_read_MDMA0_D0_Y_COUNT()
1252#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write_MDMA0_D0_Y_COUNT(val)
1253#define bfin_read_MDMA_D0_START_ADDR() bfin_read_MDMA0_D0_START_ADDR()
1254#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA0_D0_START_ADDR(val)
1255
1256#define bfin_read_MDMA_S1_CONFIG() bfin_read_MDMA0_S1_CONFIG()
1257#define bfin_write_MDMA_S1_CONFIG(val) bfin_write_MDMA0_S1_CONFIG(val)
1258#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read_MDMA0_S1_IRQ_STATUS()
1259#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write_MDMA0_S1_IRQ_STATUS(val)
1260#define bfin_read_MDMA_S1_X_MODIFY() bfin_read_MDMA0_S1_X_MODIFY()
1261#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write_MDMA0_S1_X_MODIFY(val)
1262#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read_MDMA0_S1_Y_MODIFY()
1263#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write_MDMA0_S1_Y_MODIFY(val)
1264#define bfin_read_MDMA_S1_X_COUNT() bfin_read_MDMA0_S1_X_COUNT()
1265#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write_MDMA0_S1_X_COUNT(val)
1266#define bfin_read_MDMA_S1_Y_COUNT() bfin_read_MDMA0_S1_Y_COUNT()
1267#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write_MDMA0_S1_Y_COUNT(val)
1268#define bfin_read_MDMA_S1_START_ADDR() bfin_read_MDMA0_S1_START_ADDR()
1269#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write_MDMA0_S1_START_ADDR(val)
1270#define bfin_read_MDMA_D1_CONFIG() bfin_read_MDMA0_D1_CONFIG()
1271#define bfin_write_MDMA_D1_CONFIG(val) bfin_write_MDMA0_D1_CONFIG(val)
1272#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read_MDMA0_D1_IRQ_STATUS()
1273#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write_MDMA0_D1_IRQ_STATUS(val)
1274#define bfin_read_MDMA_D1_X_MODIFY() bfin_read_MDMA0_D1_X_MODIFY()
1275#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write_MDMA0_D1_X_MODIFY(val)
1276#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read_MDMA0_D1_Y_MODIFY()
1277#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write_MDMA0_D1_Y_MODIFY(val)
1278#define bfin_read_MDMA_D1_X_COUNT() bfin_read_MDMA0_D1_X_COUNT()
1279#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write_MDMA0_D1_X_COUNT(val)
1280#define bfin_read_MDMA_D1_Y_COUNT() bfin_read_MDMA0_D1_Y_COUNT()
1281#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write_MDMA0_D1_Y_COUNT(val)
1282#define bfin_read_MDMA_D1_START_ADDR() bfin_read_MDMA0_D1_START_ADDR()
1283#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write_MDMA0_D1_START_ADDR(val)
1284
1285#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) 1218#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
1286#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) 1219#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
1287#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) 1220#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
@@ -2024,7 +1957,4 @@
2024#define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1) 1957#define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1)
2025#define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1, val) 1958#define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1, val)
2026 1959
2027/* These need to be last due to the cdef/linux inter-dependencies */
2028#include <asm/irq.h>
2029
2030#endif 1960#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF539.h b/arch/blackfin/mach-bf538/include/mach/cdefBF539.h
index 198c4bbc8e5d..acc15f3aba38 100644
--- a/arch/blackfin/mach-bf538/include/mach/cdefBF539.h
+++ b/arch/blackfin/mach-bf538/include/mach/cdefBF539.h
@@ -1,6 +1,7 @@
1/* DO NOT EDIT THIS FILE 1/*
2 * Automatically generated by generate-cdef-headers.xsl 2 * Copyright 2008-2010 Analog Devices Inc.
3 * DO NOT EDIT THIS FILE 3 *
4 * Licensed under the GPL-2 or later.
4 */ 5 */
5 6
6#ifndef _CDEF_BF539_H 7#ifndef _CDEF_BF539_H
@@ -9,7 +10,6 @@
9/* Include MMRs Common to BF538 */ 10/* Include MMRs Common to BF538 */
10#include "cdefBF538.h" 11#include "cdefBF538.h"
11 12
12
13#define bfin_read_MXVR_CONFIG() bfin_read16(MXVR_CONFIG) 13#define bfin_read_MXVR_CONFIG() bfin_read16(MXVR_CONFIG)
14#define bfin_write_MXVR_CONFIG(val) bfin_write16(MXVR_CONFIG, val) 14#define bfin_write_MXVR_CONFIG(val) bfin_write16(MXVR_CONFIG, val)
15#define bfin_read_MXVR_PLL_CTL_0() bfin_read32(MXVR_PLL_CTL_0) 15#define bfin_read_MXVR_PLL_CTL_0() bfin_read32(MXVR_PLL_CTL_0)
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF538.h b/arch/blackfin/mach-bf538/include/mach/defBF538.h
new file mode 100644
index 000000000000..d27f81d6c4b1
--- /dev/null
+++ b/arch/blackfin/mach-bf538/include/mach/defBF538.h
@@ -0,0 +1,1825 @@
1/*
2 * Copyright 2008-2010 Analog Devices Inc.
3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */
6
7#ifndef _DEF_BF538_H
8#define _DEF_BF538_H
9
10/* Clock/Regulator Control (0xFFC00000 - 0xFFC000FF) */
11#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
12#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
13#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
14#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
15#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
16#define CHIPID 0xFFC00014 /* Chip ID Register */
17
18/* CHIPID Masks */
19#define CHIPID_VERSION 0xF0000000
20#define CHIPID_FAMILY 0x0FFFF000
21#define CHIPID_MANUFACTURE 0x00000FFE
22
23/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
24#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
25#define SYSCR 0xFFC00104 /* System Configuration registe */
26#define SIC_RVECT 0xFFC00108
27#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
28#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
29#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
30#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
31#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
32#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
33#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
34#define SIC_IMASK1 0xFFC00128 /* Interrupt Mask Register 1 */
35#define SIC_ISR1 0xFFC0012C /* Interrupt Status Register 1 */
36#define SIC_IWR1 0xFFC00130 /* Interrupt Wakeup Register 1 */
37#define SIC_IAR4 0xFFC00134 /* Interrupt Assignment Register 4 */
38#define SIC_IAR5 0xFFC00138 /* Interrupt Assignment Register 5 */
39#define SIC_IAR6 0xFFC0013C /* Interrupt Assignment Register 6 */
40
41
42/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
43#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
44#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
45#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
46
47
48/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
49#define RTC_STAT 0xFFC00300 /* RTC Status Register */
50#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
51#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
52#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
53#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
54#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
55#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */
56
57
58/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
59#define UART0_THR 0xFFC00400 /* Transmit Holding register */
60#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
61#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
62#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
63#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
64#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
65#define UART0_LCR 0xFFC0040C /* Line Control Register */
66#define UART0_MCR 0xFFC00410 /* Modem Control Register */
67#define UART0_LSR 0xFFC00414 /* Line Status Register */
68#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
69#define UART0_GCTL 0xFFC00424 /* Global Control Register */
70
71
72/* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */
73
74#define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */
75#define SPI0_FLG 0xFFC00504 /* SPI0 Flag register */
76#define SPI0_STAT 0xFFC00508 /* SPI0 Status register */
77#define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */
78#define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */
79#define SPI0_BAUD 0xFFC00514 /* SPI0 Baud rate Register */
80#define SPI0_SHADOW 0xFFC00518 /* SPI0_RDBR Shadow Register */
81#define SPI0_REGBASE SPI0_CTL
82
83
84/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
85#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
86#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
87#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
88#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
89
90#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
91#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
92#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
93#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
94
95#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
96#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
97#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
98#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
99
100#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */
101#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */
102#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */
103
104
105/* Programmable Flags (0xFFC00700 - 0xFFC007FF) */
106#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */
107#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */
108#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */
109#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */
110#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */
111#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */
112#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */
113#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */
114#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */
115#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */
116#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */
117#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */
118#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */
119#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */
120#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */
121#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */
122#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */
123
124
125/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
126#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
127#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
128#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
129#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
130#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
131#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
132#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
133#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
134#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
135#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
136#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
137#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
138#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
139#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
140#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
141#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
142#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
143#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
144#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
145#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
146#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
147#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
148
149
150/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
151#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
152#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
153#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
154#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
155#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
156#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
157#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
158#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
159#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
160#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
161#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
162#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
163#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
164#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
165#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
166#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
167#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
168#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
169#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
170#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
171#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
172#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
173
174
175/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
176/* Asynchronous Memory Controller */
177#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
178#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
179#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
180
181/* SDRAM Controller */
182#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
183#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
184#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
185#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
186
187
188
189/* DMA Controller 0 Traffic Control Registers (0xFFC00B00 - 0xFFC00BFF) */
190
191#define DMAC0_TC_PER 0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */
192#define DMAC0_TC_CNT 0xFFC00B10 /* DMA Controller 0 Traffic Control Current Counts Register */
193
194
195
196/* DMA Controller 0 (0xFFC00C00 - 0xFFC00FFF) */
197
198#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
199#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
200#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
201#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
202#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
203#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
204#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
205#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
206#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
207#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
208#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
209#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
210#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
211
212#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
213#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
214#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
215#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
216#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
217#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
218#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
219#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
220#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
221#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
222#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
223#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
224#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
225
226#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
227#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
228#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
229#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
230#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
231#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
232#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
233#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
234#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
235#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
236#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
237#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
238#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
239
240#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
241#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
242#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
243#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
244#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
245#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
246#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
247#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
248#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
249#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
250#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
251#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
252#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
253
254#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
255#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
256#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
257#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
258#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
259#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
260#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
261#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
262#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
263#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
264#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
265#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
266#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
267
268#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
269#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
270#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
271#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
272#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
273#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
274#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
275#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
276#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
277#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
278#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
279#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
280#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
281
282#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
283#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
284#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
285#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
286#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
287#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
288#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
289#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
290#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
291#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
292#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
293#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
294#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
295
296#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
297#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
298#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
299#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
300#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
301#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
302#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
303#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
304#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
305#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
306#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
307#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
308#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
309
310#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA0 Stream 0 Destination Next Descriptor Pointer Register */
311#define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA0 Stream 0 Destination Start Address Register */
312#define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA0 Stream 0 Destination Configuration Register */
313#define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA0 Stream 0 Destination X Count Register */
314#define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA0 Stream 0 Destination X Modify Register */
315#define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA0 Stream 0 Destination Y Count Register */
316#define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA0 Stream 0 Destination Y Modify Register */
317#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA0 Stream 0 Destination Current Descriptor Pointer Register */
318#define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA0 Stream 0 Destination Current Address Register */
319#define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA0 Stream 0 Destination Interrupt/Status Register */
320#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA0 Stream 0 Destination Peripheral Map Register */
321#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA0 Stream 0 Destination Current X Count Register */
322#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA0 Stream 0 Destination Current Y Count Register */
323
324#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA0 Stream 0 Source Next Descriptor Pointer Register */
325#define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA0 Stream 0 Source Start Address Register */
326#define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA0 Stream 0 Source Configuration Register */
327#define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA0 Stream 0 Source X Count Register */
328#define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA0 Stream 0 Source X Modify Register */
329#define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA0 Stream 0 Source Y Count Register */
330#define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA0 Stream 0 Source Y Modify Register */
331#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA0 Stream 0 Source Current Descriptor Pointer Register */
332#define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA0 Stream 0 Source Current Address Register */
333#define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA0 Stream 0 Source Interrupt/Status Register */
334#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA0 Stream 0 Source Peripheral Map Register */
335#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA0 Stream 0 Source Current X Count Register */
336#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA0 Stream 0 Source Current Y Count Register */
337
338#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA0 Stream 1 Destination Next Descriptor Pointer Register */
339#define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA0 Stream 1 Destination Start Address Register */
340#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA0 Stream 1 Destination Configuration Register */
341#define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA0 Stream 1 Destination X Count Register */
342#define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA0 Stream 1 Destination X Modify Register */
343#define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA0 Stream 1 Destination Y Count Register */
344#define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA0 Stream 1 Destination Y Modify Register */
345#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA0 Stream 1 Destination Current Descriptor Pointer Register */
346#define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA0 Stream 1 Destination Current Address Register */
347#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA0 Stream 1 Destination Interrupt/Status Register */
348#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA0 Stream 1 Destination Peripheral Map Register */
349#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA0 Stream 1 Destination Current X Count Register */
350#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA0 Stream 1 Destination Current Y Count Register */
351
352#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA0 Stream 1 Source Next Descriptor Pointer Register */
353#define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA0 Stream 1 Source Start Address Register */
354#define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA0 Stream 1 Source Configuration Register */
355#define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA0 Stream 1 Source X Count Register */
356#define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA0 Stream 1 Source X Modify Register */
357#define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA0 Stream 1 Source Y Count Register */
358#define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA0 Stream 1 Source Y Modify Register */
359#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA0 Stream 1 Source Current Descriptor Pointer Register */
360#define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA0 Stream 1 Source Current Address Register */
361#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA0 Stream 1 Source Interrupt/Status Register */
362#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA0 Stream 1 Source Peripheral Map Register */
363#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA0 Stream 1 Source Current X Count Register */
364#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA0 Stream 1 Source Current Y Count Register */
365
366
367/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
368#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
369#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
370#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
371#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
372#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
373
374
375/* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF) */
376#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
377#define TWI0_CONTROL 0xFFC01404 /* TWI0 Master Internal Time Reference Register */
378#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
379#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
380#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
381#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
382#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
383#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
384#define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */
385#define TWI0_INT_MASK 0xFFC01424 /* TWI0 Master Interrupt Mask Register */
386#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
387#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
388#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
389#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
390#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
391#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
392
393#define TWI0_REGBASE TWI0_CLKDIV
394
395/* the following are for backwards compatibility */
396#define TWI0_PRESCALE TWI0_CONTROL
397#define TWI0_INT_SRC TWI0_INT_STAT
398#define TWI0_INT_ENABLE TWI0_INT_MASK
399
400
401/* General-Purpose Ports (0xFFC01500 - 0xFFC015FF) */
402
403/* GPIO Port C Register Names */
404#define PORTCIO_FER 0xFFC01500 /* GPIO Pin Port C Configuration Register */
405#define PORTCIO 0xFFC01510 /* GPIO Pin Port C Data Register */
406#define PORTCIO_CLEAR 0xFFC01520 /* Clear GPIO Pin Port C Register */
407#define PORTCIO_SET 0xFFC01530 /* Set GPIO Pin Port C Register */
408#define PORTCIO_TOGGLE 0xFFC01540 /* Toggle GPIO Pin Port C Register */
409#define PORTCIO_DIR 0xFFC01550 /* GPIO Pin Port C Direction Register */
410#define PORTCIO_INEN 0xFFC01560 /* GPIO Pin Port C Input Enable Register */
411
412/* GPIO Port D Register Names */
413#define PORTDIO_FER 0xFFC01504 /* GPIO Pin Port D Configuration Register */
414#define PORTDIO 0xFFC01514 /* GPIO Pin Port D Data Register */
415#define PORTDIO_CLEAR 0xFFC01524 /* Clear GPIO Pin Port D Register */
416#define PORTDIO_SET 0xFFC01534 /* Set GPIO Pin Port D Register */
417#define PORTDIO_TOGGLE 0xFFC01544 /* Toggle GPIO Pin Port D Register */
418#define PORTDIO_DIR 0xFFC01554 /* GPIO Pin Port D Direction Register */
419#define PORTDIO_INEN 0xFFC01564 /* GPIO Pin Port D Input Enable Register */
420
421/* GPIO Port E Register Names */
422#define PORTEIO_FER 0xFFC01508 /* GPIO Pin Port E Configuration Register */
423#define PORTEIO 0xFFC01518 /* GPIO Pin Port E Data Register */
424#define PORTEIO_CLEAR 0xFFC01528 /* Clear GPIO Pin Port E Register */
425#define PORTEIO_SET 0xFFC01538 /* Set GPIO Pin Port E Register */
426#define PORTEIO_TOGGLE 0xFFC01548 /* Toggle GPIO Pin Port E Register */
427#define PORTEIO_DIR 0xFFC01558 /* GPIO Pin Port E Direction Register */
428#define PORTEIO_INEN 0xFFC01568 /* GPIO Pin Port E Input Enable Register */
429
430/* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */
431
432#define DMAC1_TC_PER 0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */
433#define DMAC1_TC_CNT 0xFFC01B10 /* DMA Controller 1 Traffic Control Current Counts Register */
434
435
436
437/* DMA Controller 1 (0xFFC01C00 - 0xFFC01FFF) */
438#define DMA8_NEXT_DESC_PTR 0xFFC01C00 /* DMA Channel 8 Next Descriptor Pointer Register */
439#define DMA8_START_ADDR 0xFFC01C04 /* DMA Channel 8 Start Address Register */
440#define DMA8_CONFIG 0xFFC01C08 /* DMA Channel 8 Configuration Register */
441#define DMA8_X_COUNT 0xFFC01C10 /* DMA Channel 8 X Count Register */
442#define DMA8_X_MODIFY 0xFFC01C14 /* DMA Channel 8 X Modify Register */
443#define DMA8_Y_COUNT 0xFFC01C18 /* DMA Channel 8 Y Count Register */
444#define DMA8_Y_MODIFY 0xFFC01C1C /* DMA Channel 8 Y Modify Register */
445#define DMA8_CURR_DESC_PTR 0xFFC01C20 /* DMA Channel 8 Current Descriptor Pointer Register */
446#define DMA8_CURR_ADDR 0xFFC01C24 /* DMA Channel 8 Current Address Register */
447#define DMA8_IRQ_STATUS 0xFFC01C28 /* DMA Channel 8 Interrupt/Status Register */
448#define DMA8_PERIPHERAL_MAP 0xFFC01C2C /* DMA Channel 8 Peripheral Map Register */
449#define DMA8_CURR_X_COUNT 0xFFC01C30 /* DMA Channel 8 Current X Count Register */
450#define DMA8_CURR_Y_COUNT 0xFFC01C38 /* DMA Channel 8 Current Y Count Register */
451
452#define DMA9_NEXT_DESC_PTR 0xFFC01C40 /* DMA Channel 9 Next Descriptor Pointer Register */
453#define DMA9_START_ADDR 0xFFC01C44 /* DMA Channel 9 Start Address Register */
454#define DMA9_CONFIG 0xFFC01C48 /* DMA Channel 9 Configuration Register */
455#define DMA9_X_COUNT 0xFFC01C50 /* DMA Channel 9 X Count Register */
456#define DMA9_X_MODIFY 0xFFC01C54 /* DMA Channel 9 X Modify Register */
457#define DMA9_Y_COUNT 0xFFC01C58 /* DMA Channel 9 Y Count Register */
458#define DMA9_Y_MODIFY 0xFFC01C5C /* DMA Channel 9 Y Modify Register */
459#define DMA9_CURR_DESC_PTR 0xFFC01C60 /* DMA Channel 9 Current Descriptor Pointer Register */
460#define DMA9_CURR_ADDR 0xFFC01C64 /* DMA Channel 9 Current Address Register */
461#define DMA9_IRQ_STATUS 0xFFC01C68 /* DMA Channel 9 Interrupt/Status Register */
462#define DMA9_PERIPHERAL_MAP 0xFFC01C6C /* DMA Channel 9 Peripheral Map Register */
463#define DMA9_CURR_X_COUNT 0xFFC01C70 /* DMA Channel 9 Current X Count Register */
464#define DMA9_CURR_Y_COUNT 0xFFC01C78 /* DMA Channel 9 Current Y Count Register */
465
466#define DMA10_NEXT_DESC_PTR 0xFFC01C80 /* DMA Channel 10 Next Descriptor Pointer Register */
467#define DMA10_START_ADDR 0xFFC01C84 /* DMA Channel 10 Start Address Register */
468#define DMA10_CONFIG 0xFFC01C88 /* DMA Channel 10 Configuration Register */
469#define DMA10_X_COUNT 0xFFC01C90 /* DMA Channel 10 X Count Register */
470#define DMA10_X_MODIFY 0xFFC01C94 /* DMA Channel 10 X Modify Register */
471#define DMA10_Y_COUNT 0xFFC01C98 /* DMA Channel 10 Y Count Register */
472#define DMA10_Y_MODIFY 0xFFC01C9C /* DMA Channel 10 Y Modify Register */
473#define DMA10_CURR_DESC_PTR 0xFFC01CA0 /* DMA Channel 10 Current Descriptor Pointer Register */
474#define DMA10_CURR_ADDR 0xFFC01CA4 /* DMA Channel 10 Current Address Register */
475#define DMA10_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 10 Interrupt/Status Register */
476#define DMA10_PERIPHERAL_MAP 0xFFC01CAC /* DMA Channel 10 Peripheral Map Register */
477#define DMA10_CURR_X_COUNT 0xFFC01CB0 /* DMA Channel 10 Current X Count Register */
478#define DMA10_CURR_Y_COUNT 0xFFC01CB8 /* DMA Channel 10 Current Y Count Register */
479
480#define DMA11_NEXT_DESC_PTR 0xFFC01CC0 /* DMA Channel 11 Next Descriptor Pointer Register */
481#define DMA11_START_ADDR 0xFFC01CC4 /* DMA Channel 11 Start Address Register */
482#define DMA11_CONFIG 0xFFC01CC8 /* DMA Channel 11 Configuration Register */
483#define DMA11_X_COUNT 0xFFC01CD0 /* DMA Channel 11 X Count Register */
484#define DMA11_X_MODIFY 0xFFC01CD4 /* DMA Channel 11 X Modify Register */
485#define DMA11_Y_COUNT 0xFFC01CD8 /* DMA Channel 11 Y Count Register */
486#define DMA11_Y_MODIFY 0xFFC01CDC /* DMA Channel 11 Y Modify Register */
487#define DMA11_CURR_DESC_PTR 0xFFC01CE0 /* DMA Channel 11 Current Descriptor Pointer Register */
488#define DMA11_CURR_ADDR 0xFFC01CE4 /* DMA Channel 11 Current Address Register */
489#define DMA11_IRQ_STATUS 0xFFC01CE8 /* DMA Channel 11 Interrupt/Status Register */
490#define DMA11_PERIPHERAL_MAP 0xFFC01CEC /* DMA Channel 11 Peripheral Map Register */
491#define DMA11_CURR_X_COUNT 0xFFC01CF0 /* DMA Channel 11 Current X Count Register */
492#define DMA11_CURR_Y_COUNT 0xFFC01CF8 /* DMA Channel 11 Current Y Count Register */
493
494#define DMA12_NEXT_DESC_PTR 0xFFC01D00 /* DMA Channel 12 Next Descriptor Pointer Register */
495#define DMA12_START_ADDR 0xFFC01D04 /* DMA Channel 12 Start Address Register */
496#define DMA12_CONFIG 0xFFC01D08 /* DMA Channel 12 Configuration Register */
497#define DMA12_X_COUNT 0xFFC01D10 /* DMA Channel 12 X Count Register */
498#define DMA12_X_MODIFY 0xFFC01D14 /* DMA Channel 12 X Modify Register */
499#define DMA12_Y_COUNT 0xFFC01D18 /* DMA Channel 12 Y Count Register */
500#define DMA12_Y_MODIFY 0xFFC01D1C /* DMA Channel 12 Y Modify Register */
501#define DMA12_CURR_DESC_PTR 0xFFC01D20 /* DMA Channel 12 Current Descriptor Pointer Register */
502#define DMA12_CURR_ADDR 0xFFC01D24 /* DMA Channel 12 Current Address Register */
503#define DMA12_IRQ_STATUS 0xFFC01D28 /* DMA Channel 12 Interrupt/Status Register */
504#define DMA12_PERIPHERAL_MAP 0xFFC01D2C /* DMA Channel 12 Peripheral Map Register */
505#define DMA12_CURR_X_COUNT 0xFFC01D30 /* DMA Channel 12 Current X Count Register */
506#define DMA12_CURR_Y_COUNT 0xFFC01D38 /* DMA Channel 12 Current Y Count Register */
507
508#define DMA13_NEXT_DESC_PTR 0xFFC01D40 /* DMA Channel 13 Next Descriptor Pointer Register */
509#define DMA13_START_ADDR 0xFFC01D44 /* DMA Channel 13 Start Address Register */
510#define DMA13_CONFIG 0xFFC01D48 /* DMA Channel 13 Configuration Register */
511#define DMA13_X_COUNT 0xFFC01D50 /* DMA Channel 13 X Count Register */
512#define DMA13_X_MODIFY 0xFFC01D54 /* DMA Channel 13 X Modify Register */
513#define DMA13_Y_COUNT 0xFFC01D58 /* DMA Channel 13 Y Count Register */
514#define DMA13_Y_MODIFY 0xFFC01D5C /* DMA Channel 13 Y Modify Register */
515#define DMA13_CURR_DESC_PTR 0xFFC01D60 /* DMA Channel 13 Current Descriptor Pointer Register */
516#define DMA13_CURR_ADDR 0xFFC01D64 /* DMA Channel 13 Current Address Register */
517#define DMA13_IRQ_STATUS 0xFFC01D68 /* DMA Channel 13 Interrupt/Status Register */
518#define DMA13_PERIPHERAL_MAP 0xFFC01D6C /* DMA Channel 13 Peripheral Map Register */
519#define DMA13_CURR_X_COUNT 0xFFC01D70 /* DMA Channel 13 Current X Count Register */
520#define DMA13_CURR_Y_COUNT 0xFFC01D78 /* DMA Channel 13 Current Y Count Register */
521
522#define DMA14_NEXT_DESC_PTR 0xFFC01D80 /* DMA Channel 14 Next Descriptor Pointer Register */
523#define DMA14_START_ADDR 0xFFC01D84 /* DMA Channel 14 Start Address Register */
524#define DMA14_CONFIG 0xFFC01D88 /* DMA Channel 14 Configuration Register */
525#define DMA14_X_COUNT 0xFFC01D90 /* DMA Channel 14 X Count Register */
526#define DMA14_X_MODIFY 0xFFC01D94 /* DMA Channel 14 X Modify Register */
527#define DMA14_Y_COUNT 0xFFC01D98 /* DMA Channel 14 Y Count Register */
528#define DMA14_Y_MODIFY 0xFFC01D9C /* DMA Channel 14 Y Modify Register */
529#define DMA14_CURR_DESC_PTR 0xFFC01DA0 /* DMA Channel 14 Current Descriptor Pointer Register */
530#define DMA14_CURR_ADDR 0xFFC01DA4 /* DMA Channel 14 Current Address Register */
531#define DMA14_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 14 Interrupt/Status Register */
532#define DMA14_PERIPHERAL_MAP 0xFFC01DAC /* DMA Channel 14 Peripheral Map Register */
533#define DMA14_CURR_X_COUNT 0xFFC01DB0 /* DMA Channel 14 Current X Count Register */
534#define DMA14_CURR_Y_COUNT 0xFFC01DB8 /* DMA Channel 14 Current Y Count Register */
535
536#define DMA15_NEXT_DESC_PTR 0xFFC01DC0 /* DMA Channel 15 Next Descriptor Pointer Register */
537#define DMA15_START_ADDR 0xFFC01DC4 /* DMA Channel 15 Start Address Register */
538#define DMA15_CONFIG 0xFFC01DC8 /* DMA Channel 15 Configuration Register */
539#define DMA15_X_COUNT 0xFFC01DD0 /* DMA Channel 15 X Count Register */
540#define DMA15_X_MODIFY 0xFFC01DD4 /* DMA Channel 15 X Modify Register */
541#define DMA15_Y_COUNT 0xFFC01DD8 /* DMA Channel 15 Y Count Register */
542#define DMA15_Y_MODIFY 0xFFC01DDC /* DMA Channel 15 Y Modify Register */
543#define DMA15_CURR_DESC_PTR 0xFFC01DE0 /* DMA Channel 15 Current Descriptor Pointer Register */
544#define DMA15_CURR_ADDR 0xFFC01DE4 /* DMA Channel 15 Current Address Register */
545#define DMA15_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 15 Interrupt/Status Register */
546#define DMA15_PERIPHERAL_MAP 0xFFC01DEC /* DMA Channel 15 Peripheral Map Register */
547#define DMA15_CURR_X_COUNT 0xFFC01DF0 /* DMA Channel 15 Current X Count Register */
548#define DMA15_CURR_Y_COUNT 0xFFC01DF8 /* DMA Channel 15 Current Y Count Register */
549
550#define DMA16_NEXT_DESC_PTR 0xFFC01E00 /* DMA Channel 16 Next Descriptor Pointer Register */
551#define DMA16_START_ADDR 0xFFC01E04 /* DMA Channel 16 Start Address Register */
552#define DMA16_CONFIG 0xFFC01E08 /* DMA Channel 16 Configuration Register */
553#define DMA16_X_COUNT 0xFFC01E10 /* DMA Channel 16 X Count Register */
554#define DMA16_X_MODIFY 0xFFC01E14 /* DMA Channel 16 X Modify Register */
555#define DMA16_Y_COUNT 0xFFC01E18 /* DMA Channel 16 Y Count Register */
556#define DMA16_Y_MODIFY 0xFFC01E1C /* DMA Channel 16 Y Modify Register */
557#define DMA16_CURR_DESC_PTR 0xFFC01E20 /* DMA Channel 16 Current Descriptor Pointer Register */
558#define DMA16_CURR_ADDR 0xFFC01E24 /* DMA Channel 16 Current Address Register */
559#define DMA16_IRQ_STATUS 0xFFC01E28 /* DMA Channel 16 Interrupt/Status Register */
560#define DMA16_PERIPHERAL_MAP 0xFFC01E2C /* DMA Channel 16 Peripheral Map Register */
561#define DMA16_CURR_X_COUNT 0xFFC01E30 /* DMA Channel 16 Current X Count Register */
562#define DMA16_CURR_Y_COUNT 0xFFC01E38 /* DMA Channel 16 Current Y Count Register */
563
564#define DMA17_NEXT_DESC_PTR 0xFFC01E40 /* DMA Channel 17 Next Descriptor Pointer Register */
565#define DMA17_START_ADDR 0xFFC01E44 /* DMA Channel 17 Start Address Register */
566#define DMA17_CONFIG 0xFFC01E48 /* DMA Channel 17 Configuration Register */
567#define DMA17_X_COUNT 0xFFC01E50 /* DMA Channel 17 X Count Register */
568#define DMA17_X_MODIFY 0xFFC01E54 /* DMA Channel 17 X Modify Register */
569#define DMA17_Y_COUNT 0xFFC01E58 /* DMA Channel 17 Y Count Register */
570#define DMA17_Y_MODIFY 0xFFC01E5C /* DMA Channel 17 Y Modify Register */
571#define DMA17_CURR_DESC_PTR 0xFFC01E60 /* DMA Channel 17 Current Descriptor Pointer Register */
572#define DMA17_CURR_ADDR 0xFFC01E64 /* DMA Channel 17 Current Address Register */
573#define DMA17_IRQ_STATUS 0xFFC01E68 /* DMA Channel 17 Interrupt/Status Register */
574#define DMA17_PERIPHERAL_MAP 0xFFC01E6C /* DMA Channel 17 Peripheral Map Register */
575#define DMA17_CURR_X_COUNT 0xFFC01E70 /* DMA Channel 17 Current X Count Register */
576#define DMA17_CURR_Y_COUNT 0xFFC01E78 /* DMA Channel 17 Current Y Count Register */
577
578#define DMA18_NEXT_DESC_PTR 0xFFC01E80 /* DMA Channel 18 Next Descriptor Pointer Register */
579#define DMA18_START_ADDR 0xFFC01E84 /* DMA Channel 18 Start Address Register */
580#define DMA18_CONFIG 0xFFC01E88 /* DMA Channel 18 Configuration Register */
581#define DMA18_X_COUNT 0xFFC01E90 /* DMA Channel 18 X Count Register */
582#define DMA18_X_MODIFY 0xFFC01E94 /* DMA Channel 18 X Modify Register */
583#define DMA18_Y_COUNT 0xFFC01E98 /* DMA Channel 18 Y Count Register */
584#define DMA18_Y_MODIFY 0xFFC01E9C /* DMA Channel 18 Y Modify Register */
585#define DMA18_CURR_DESC_PTR 0xFFC01EA0 /* DMA Channel 18 Current Descriptor Pointer Register */
586#define DMA18_CURR_ADDR 0xFFC01EA4 /* DMA Channel 18 Current Address Register */
587#define DMA18_IRQ_STATUS 0xFFC01EA8 /* DMA Channel 18 Interrupt/Status Register */
588#define DMA18_PERIPHERAL_MAP 0xFFC01EAC /* DMA Channel 18 Peripheral Map Register */
589#define DMA18_CURR_X_COUNT 0xFFC01EB0 /* DMA Channel 18 Current X Count Register */
590#define DMA18_CURR_Y_COUNT 0xFFC01EB8 /* DMA Channel 18 Current Y Count Register */
591
592#define DMA19_NEXT_DESC_PTR 0xFFC01EC0 /* DMA Channel 19 Next Descriptor Pointer Register */
593#define DMA19_START_ADDR 0xFFC01EC4 /* DMA Channel 19 Start Address Register */
594#define DMA19_CONFIG 0xFFC01EC8 /* DMA Channel 19 Configuration Register */
595#define DMA19_X_COUNT 0xFFC01ED0 /* DMA Channel 19 X Count Register */
596#define DMA19_X_MODIFY 0xFFC01ED4 /* DMA Channel 19 X Modify Register */
597#define DMA19_Y_COUNT 0xFFC01ED8 /* DMA Channel 19 Y Count Register */
598#define DMA19_Y_MODIFY 0xFFC01EDC /* DMA Channel 19 Y Modify Register */
599#define DMA19_CURR_DESC_PTR 0xFFC01EE0 /* DMA Channel 19 Current Descriptor Pointer Register */
600#define DMA19_CURR_ADDR 0xFFC01EE4 /* DMA Channel 19 Current Address Register */
601#define DMA19_IRQ_STATUS 0xFFC01EE8 /* DMA Channel 19 Interrupt/Status Register */
602#define DMA19_PERIPHERAL_MAP 0xFFC01EEC /* DMA Channel 19 Peripheral Map Register */
603#define DMA19_CURR_X_COUNT 0xFFC01EF0 /* DMA Channel 19 Current X Count Register */
604#define DMA19_CURR_Y_COUNT 0xFFC01EF8 /* DMA Channel 19 Current Y Count Register */
605
606#define MDMA_D2_NEXT_DESC_PTR 0xFFC01F00 /* MemDMA1 Stream 0 Destination Next Descriptor Pointer Register */
607#define MDMA_D2_START_ADDR 0xFFC01F04 /* MemDMA1 Stream 0 Destination Start Address Register */
608#define MDMA_D2_CONFIG 0xFFC01F08 /* MemDMA1 Stream 0 Destination Configuration Register */
609#define MDMA_D2_X_COUNT 0xFFC01F10 /* MemDMA1 Stream 0 Destination X Count Register */
610#define MDMA_D2_X_MODIFY 0xFFC01F14 /* MemDMA1 Stream 0 Destination X Modify Register */
611#define MDMA_D2_Y_COUNT 0xFFC01F18 /* MemDMA1 Stream 0 Destination Y Count Register */
612#define MDMA_D2_Y_MODIFY 0xFFC01F1C /* MemDMA1 Stream 0 Destination Y Modify Register */
613#define MDMA_D2_CURR_DESC_PTR 0xFFC01F20 /* MemDMA1 Stream 0 Destination Current Descriptor Pointer Register */
614#define MDMA_D2_CURR_ADDR 0xFFC01F24 /* MemDMA1 Stream 0 Destination Current Address Register */
615#define MDMA_D2_IRQ_STATUS 0xFFC01F28 /* MemDMA1 Stream 0 Destination Interrupt/Status Register */
616#define MDMA_D2_PERIPHERAL_MAP 0xFFC01F2C /* MemDMA1 Stream 0 Destination Peripheral Map Register */
617#define MDMA_D2_CURR_X_COUNT 0xFFC01F30 /* MemDMA1 Stream 0 Destination Current X Count Register */
618#define MDMA_D2_CURR_Y_COUNT 0xFFC01F38 /* MemDMA1 Stream 0 Destination Current Y Count Register */
619
620#define MDMA_S2_NEXT_DESC_PTR 0xFFC01F40 /* MemDMA1 Stream 0 Source Next Descriptor Pointer Register */
621#define MDMA_S2_START_ADDR 0xFFC01F44 /* MemDMA1 Stream 0 Source Start Address Register */
622#define MDMA_S2_CONFIG 0xFFC01F48 /* MemDMA1 Stream 0 Source Configuration Register */
623#define MDMA_S2_X_COUNT 0xFFC01F50 /* MemDMA1 Stream 0 Source X Count Register */
624#define MDMA_S2_X_MODIFY 0xFFC01F54 /* MemDMA1 Stream 0 Source X Modify Register */
625#define MDMA_S2_Y_COUNT 0xFFC01F58 /* MemDMA1 Stream 0 Source Y Count Register */
626#define MDMA_S2_Y_MODIFY 0xFFC01F5C /* MemDMA1 Stream 0 Source Y Modify Register */
627#define MDMA_S2_CURR_DESC_PTR 0xFFC01F60 /* MemDMA1 Stream 0 Source Current Descriptor Pointer Register */
628#define MDMA_S2_CURR_ADDR 0xFFC01F64 /* MemDMA1 Stream 0 Source Current Address Register */
629#define MDMA_S2_IRQ_STATUS 0xFFC01F68 /* MemDMA1 Stream 0 Source Interrupt/Status Register */
630#define MDMA_S2_PERIPHERAL_MAP 0xFFC01F6C /* MemDMA1 Stream 0 Source Peripheral Map Register */
631#define MDMA_S2_CURR_X_COUNT 0xFFC01F70 /* MemDMA1 Stream 0 Source Current X Count Register */
632#define MDMA_S2_CURR_Y_COUNT 0xFFC01F78 /* MemDMA1 Stream 0 Source Current Y Count Register */
633
634#define MDMA_D3_NEXT_DESC_PTR 0xFFC01F80 /* MemDMA1 Stream 1 Destination Next Descriptor Pointer Register */
635#define MDMA_D3_START_ADDR 0xFFC01F84 /* MemDMA1 Stream 1 Destination Start Address Register */
636#define MDMA_D3_CONFIG 0xFFC01F88 /* MemDMA1 Stream 1 Destination Configuration Register */
637#define MDMA_D3_X_COUNT 0xFFC01F90 /* MemDMA1 Stream 1 Destination X Count Register */
638#define MDMA_D3_X_MODIFY 0xFFC01F94 /* MemDMA1 Stream 1 Destination X Modify Register */
639#define MDMA_D3_Y_COUNT 0xFFC01F98 /* MemDMA1 Stream 1 Destination Y Count Register */
640#define MDMA_D3_Y_MODIFY 0xFFC01F9C /* MemDMA1 Stream 1 Destination Y Modify Register */
641#define MDMA_D3_CURR_DESC_PTR 0xFFC01FA0 /* MemDMA1 Stream 1 Destination Current Descriptor Pointer Register */
642#define MDMA_D3_CURR_ADDR 0xFFC01FA4 /* MemDMA1 Stream 1 Destination Current Address Register */
643#define MDMA_D3_IRQ_STATUS 0xFFC01FA8 /* MemDMA1 Stream 1 Destination Interrupt/Status Register */
644#define MDMA_D3_PERIPHERAL_MAP 0xFFC01FAC /* MemDMA1 Stream 1 Destination Peripheral Map Register */
645#define MDMA_D3_CURR_X_COUNT 0xFFC01FB0 /* MemDMA1 Stream 1 Destination Current X Count Register */
646#define MDMA_D3_CURR_Y_COUNT 0xFFC01FB8 /* MemDMA1 Stream 1 Destination Current Y Count Register */
647
648#define MDMA_S3_NEXT_DESC_PTR 0xFFC01FC0 /* MemDMA1 Stream 1 Source Next Descriptor Pointer Register */
649#define MDMA_S3_START_ADDR 0xFFC01FC4 /* MemDMA1 Stream 1 Source Start Address Register */
650#define MDMA_S3_CONFIG 0xFFC01FC8 /* MemDMA1 Stream 1 Source Configuration Register */
651#define MDMA_S3_X_COUNT 0xFFC01FD0 /* MemDMA1 Stream 1 Source X Count Register */
652#define MDMA_S3_X_MODIFY 0xFFC01FD4 /* MemDMA1 Stream 1 Source X Modify Register */
653#define MDMA_S3_Y_COUNT 0xFFC01FD8 /* MemDMA1 Stream 1 Source Y Count Register */
654#define MDMA_S3_Y_MODIFY 0xFFC01FDC /* MemDMA1 Stream 1 Source Y Modify Register */
655#define MDMA_S3_CURR_DESC_PTR 0xFFC01FE0 /* MemDMA1 Stream 1 Source Current Descriptor Pointer Register */
656#define MDMA_S3_CURR_ADDR 0xFFC01FE4 /* MemDMA1 Stream 1 Source Current Address Register */
657#define MDMA_S3_IRQ_STATUS 0xFFC01FE8 /* MemDMA1 Stream 1 Source Interrupt/Status Register */
658#define MDMA_S3_PERIPHERAL_MAP 0xFFC01FEC /* MemDMA1 Stream 1 Source Peripheral Map Register */
659#define MDMA_S3_CURR_X_COUNT 0xFFC01FF0 /* MemDMA1 Stream 1 Source Current X Count Register */
660#define MDMA_S3_CURR_Y_COUNT 0xFFC01FF8 /* MemDMA1 Stream 1 Source Current Y Count Register */
661
662
663/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
664#define UART1_THR 0xFFC02000 /* Transmit Holding register */
665#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
666#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
667#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
668#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
669#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
670#define UART1_LCR 0xFFC0200C /* Line Control Register */
671#define UART1_MCR 0xFFC02010 /* Modem Control Register */
672#define UART1_LSR 0xFFC02014 /* Line Status Register */
673#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
674#define UART1_GCTL 0xFFC02024 /* Global Control Register */
675
676
677/* UART2 Controller (0xFFC02100 - 0xFFC021FF) */
678#define UART2_THR 0xFFC02100 /* Transmit Holding register */
679#define UART2_RBR 0xFFC02100 /* Receive Buffer register */
680#define UART2_DLL 0xFFC02100 /* Divisor Latch (Low-Byte) */
681#define UART2_IER 0xFFC02104 /* Interrupt Enable Register */
682#define UART2_DLH 0xFFC02104 /* Divisor Latch (High-Byte) */
683#define UART2_IIR 0xFFC02108 /* Interrupt Identification Register */
684#define UART2_LCR 0xFFC0210C /* Line Control Register */
685#define UART2_MCR 0xFFC02110 /* Modem Control Register */
686#define UART2_LSR 0xFFC02114 /* Line Status Register */
687#define UART2_SCR 0xFFC0211C /* SCR Scratch Register */
688#define UART2_GCTL 0xFFC02124 /* Global Control Register */
689
690
691/* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF) */
692#define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */
693#define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */
694#define TWI1_SLAVE_CTL 0xFFC02208 /* Slave Mode Control Register */
695#define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */
696#define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */
697#define TWI1_MASTER_CTL 0xFFC02214 /* Master Mode Control Register */
698#define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */
699#define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */
700#define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */
701#define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */
702#define TWI1_FIFO_CTL 0xFFC02228 /* FIFO Control Register */
703#define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */
704#define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */
705#define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */
706#define TWI1_RCV_DATA8 0xFFC02288 /* FIFO Receive Data Single Byte Register */
707#define TWI1_RCV_DATA16 0xFFC0228C /* FIFO Receive Data Double Byte Register */
708#define TWI1_REGBASE TWI1_CLKDIV
709
710
711/* the following are for backwards compatibility */
712#define TWI1_PRESCALE TWI1_CONTROL
713#define TWI1_INT_SRC TWI1_INT_STAT
714#define TWI1_INT_ENABLE TWI1_INT_MASK
715
716
717/* SPI1 Controller (0xFFC02300 - 0xFFC023FF) */
718#define SPI1_CTL 0xFFC02300 /* SPI1 Control Register */
719#define SPI1_FLG 0xFFC02304 /* SPI1 Flag register */
720#define SPI1_STAT 0xFFC02308 /* SPI1 Status register */
721#define SPI1_TDBR 0xFFC0230C /* SPI1 Transmit Data Buffer Register */
722#define SPI1_RDBR 0xFFC02310 /* SPI1 Receive Data Buffer Register */
723#define SPI1_BAUD 0xFFC02314 /* SPI1 Baud rate Register */
724#define SPI1_SHADOW 0xFFC02318 /* SPI1_RDBR Shadow Register */
725#define SPI1_REGBASE SPI1_CTL
726
727/* SPI2 Controller (0xFFC02400 - 0xFFC024FF) */
728#define SPI2_CTL 0xFFC02400 /* SPI2 Control Register */
729#define SPI2_FLG 0xFFC02404 /* SPI2 Flag register */
730#define SPI2_STAT 0xFFC02408 /* SPI2 Status register */
731#define SPI2_TDBR 0xFFC0240C /* SPI2 Transmit Data Buffer Register */
732#define SPI2_RDBR 0xFFC02410 /* SPI2 Receive Data Buffer Register */
733#define SPI2_BAUD 0xFFC02414 /* SPI2 Baud rate Register */
734#define SPI2_SHADOW 0xFFC02418 /* SPI2_RDBR Shadow Register */
735#define SPI2_REGBASE SPI2_CTL
736
737/* SPORT2 Controller (0xFFC02500 - 0xFFC025FF) */
738#define SPORT2_TCR1 0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */
739#define SPORT2_TCR2 0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */
740#define SPORT2_TCLKDIV 0xFFC02508 /* SPORT2 Transmit Clock Divider */
741#define SPORT2_TFSDIV 0xFFC0250C /* SPORT2 Transmit Frame Sync Divider */
742#define SPORT2_TX 0xFFC02510 /* SPORT2 TX Data Register */
743#define SPORT2_RX 0xFFC02518 /* SPORT2 RX Data Register */
744#define SPORT2_RCR1 0xFFC02520 /* SPORT2 Transmit Configuration 1 Register */
745#define SPORT2_RCR2 0xFFC02524 /* SPORT2 Transmit Configuration 2 Register */
746#define SPORT2_RCLKDIV 0xFFC02528 /* SPORT2 Receive Clock Divider */
747#define SPORT2_RFSDIV 0xFFC0252C /* SPORT2 Receive Frame Sync Divider */
748#define SPORT2_STAT 0xFFC02530 /* SPORT2 Status Register */
749#define SPORT2_CHNL 0xFFC02534 /* SPORT2 Current Channel Register */
750#define SPORT2_MCMC1 0xFFC02538 /* SPORT2 Multi-Channel Configuration Register 1 */
751#define SPORT2_MCMC2 0xFFC0253C /* SPORT2 Multi-Channel Configuration Register 2 */
752#define SPORT2_MTCS0 0xFFC02540 /* SPORT2 Multi-Channel Transmit Select Register 0 */
753#define SPORT2_MTCS1 0xFFC02544 /* SPORT2 Multi-Channel Transmit Select Register 1 */
754#define SPORT2_MTCS2 0xFFC02548 /* SPORT2 Multi-Channel Transmit Select Register 2 */
755#define SPORT2_MTCS3 0xFFC0254C /* SPORT2 Multi-Channel Transmit Select Register 3 */
756#define SPORT2_MRCS0 0xFFC02550 /* SPORT2 Multi-Channel Receive Select Register 0 */
757#define SPORT2_MRCS1 0xFFC02554 /* SPORT2 Multi-Channel Receive Select Register 1 */
758#define SPORT2_MRCS2 0xFFC02558 /* SPORT2 Multi-Channel Receive Select Register 2 */
759#define SPORT2_MRCS3 0xFFC0255C /* SPORT2 Multi-Channel Receive Select Register 3 */
760
761
762/* SPORT3 Controller (0xFFC02600 - 0xFFC026FF) */
763#define SPORT3_TCR1 0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */
764#define SPORT3_TCR2 0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */
765#define SPORT3_TCLKDIV 0xFFC02608 /* SPORT3 Transmit Clock Divider */
766#define SPORT3_TFSDIV 0xFFC0260C /* SPORT3 Transmit Frame Sync Divider */
767#define SPORT3_TX 0xFFC02610 /* SPORT3 TX Data Register */
768#define SPORT3_RX 0xFFC02618 /* SPORT3 RX Data Register */
769#define SPORT3_RCR1 0xFFC02620 /* SPORT3 Transmit Configuration 1 Register */
770#define SPORT3_RCR2 0xFFC02624 /* SPORT3 Transmit Configuration 2 Register */
771#define SPORT3_RCLKDIV 0xFFC02628 /* SPORT3 Receive Clock Divider */
772#define SPORT3_RFSDIV 0xFFC0262C /* SPORT3 Receive Frame Sync Divider */
773#define SPORT3_STAT 0xFFC02630 /* SPORT3 Status Register */
774#define SPORT3_CHNL 0xFFC02634 /* SPORT3 Current Channel Register */
775#define SPORT3_MCMC1 0xFFC02638 /* SPORT3 Multi-Channel Configuration Register 1 */
776#define SPORT3_MCMC2 0xFFC0263C /* SPORT3 Multi-Channel Configuration Register 2 */
777#define SPORT3_MTCS0 0xFFC02640 /* SPORT3 Multi-Channel Transmit Select Register 0 */
778#define SPORT3_MTCS1 0xFFC02644 /* SPORT3 Multi-Channel Transmit Select Register 1 */
779#define SPORT3_MTCS2 0xFFC02648 /* SPORT3 Multi-Channel Transmit Select Register 2 */
780#define SPORT3_MTCS3 0xFFC0264C /* SPORT3 Multi-Channel Transmit Select Register 3 */
781#define SPORT3_MRCS0 0xFFC02650 /* SPORT3 Multi-Channel Receive Select Register 0 */
782#define SPORT3_MRCS1 0xFFC02654 /* SPORT3 Multi-Channel Receive Select Register 1 */
783#define SPORT3_MRCS2 0xFFC02658 /* SPORT3 Multi-Channel Receive Select Register 2 */
784#define SPORT3_MRCS3 0xFFC0265C /* SPORT3 Multi-Channel Receive Select Register 3 */
785
786
787/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
788/* For Mailboxes 0-15 */
789#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */
790#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */
791#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */
792#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */
793#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */
794#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */
795#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */
796#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */
797#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */
798#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */
799#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */
800#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */
801#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmission reg 1 */
802
803/* For Mailboxes 16-31 */
804#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */
805#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */
806#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */
807#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */
808#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */
809#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */
810#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */
811#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */
812#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */
813#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */
814#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */
815#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */
816#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmission reg 2 */
817
818#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */
819#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */
820
821#define CAN_DEBUG 0xFFC02A88 /* Debug Register */
822/* the following is for backwards compatibility */
823#define CAN_CNF CAN_DEBUG
824
825#define CAN_STATUS 0xFFC02A8C /* Global Status Register */
826#define CAN_CEC 0xFFC02A90 /* Error Counter Register */
827#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */
828#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */
829#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */
830#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */
831#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */
832#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
833#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
834#define CAN_ESR 0xFFC02AB4 /* Error Status Register */
835#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */
836#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Reload/Capture Register */
837#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */
838
839/* Mailbox Acceptance Masks */
840#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */
841#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */
842#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */
843#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */
844#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */
845#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */
846#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */
847#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */
848#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */
849#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */
850#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */
851#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */
852#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */
853#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */
854#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */
855#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */
856#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */
857#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */
858#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */
859#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */
860#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */
861#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */
862#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */
863#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */
864#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */
865#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */
866#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */
867#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */
868#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */
869#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */
870#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */
871#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */
872
873#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */
874#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */
875#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */
876#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */
877#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */
878#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */
879#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */
880#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */
881#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */
882#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */
883#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */
884#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */
885#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */
886#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */
887#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */
888#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */
889#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */
890#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */
891#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */
892#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */
893#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */
894#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */
895#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */
896#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */
897#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */
898#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */
899#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */
900#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */
901#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */
902#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */
903#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */
904#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */
905
906/* CAN Acceptance Mask Macros */
907#define CAN_AM_L(x) (CAN_AM00L+((x)*0x8))
908#define CAN_AM_H(x) (CAN_AM00H+((x)*0x8))
909
910/* Mailbox Registers */
911#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */
912#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */
913#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */
914#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */
915#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */
916#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */
917#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */
918#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */
919
920#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */
921#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */
922#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */
923#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */
924#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */
925#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */
926#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */
927#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */
928
929#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */
930#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */
931#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */
932#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */
933#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */
934#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */
935#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */
936#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */
937
938#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */
939#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */
940#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */
941#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */
942#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */
943#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */
944#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */
945#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */
946
947#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */
948#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */
949#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */
950#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */
951#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */
952#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */
953#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */
954#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */
955
956#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */
957#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */
958#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */
959#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */
960#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */
961#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */
962#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */
963#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */
964
965#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */
966#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */
967#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */
968#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */
969#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */
970#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */
971#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */
972#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */
973
974#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */
975#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */
976#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */
977#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */
978#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */
979#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */
980#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */
981#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */
982
983#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */
984#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */
985#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */
986#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */
987#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */
988#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */
989#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */
990#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */
991
992#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */
993#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */
994#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */
995#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */
996#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */
997#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */
998#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */
999#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */
1000
1001#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */
1002#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */
1003#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */
1004#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */
1005#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */
1006#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */
1007#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */
1008#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */
1009
1010#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */
1011#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */
1012#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */
1013#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */
1014#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */
1015#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */
1016#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */
1017#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */
1018
1019#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */
1020#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */
1021#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */
1022#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */
1023#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */
1024#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */
1025#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */
1026#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */
1027
1028#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */
1029#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */
1030#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */
1031#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */
1032#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */
1033#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */
1034#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */
1035#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */
1036
1037#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */
1038#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */
1039#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */
1040#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */
1041#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */
1042#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */
1043#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */
1044#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */
1045
1046#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */
1047#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */
1048#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */
1049#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */
1050#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */
1051#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */
1052#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */
1053#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */
1054
1055#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */
1056#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */
1057#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */
1058#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */
1059#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */
1060#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */
1061#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */
1062#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */
1063
1064#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */
1065#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */
1066#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */
1067#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */
1068#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */
1069#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */
1070#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */
1071#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */
1072
1073#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */
1074#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */
1075#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */
1076#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */
1077#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */
1078#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */
1079#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */
1080#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */
1081
1082#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */
1083#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */
1084#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */
1085#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */
1086#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */
1087#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */
1088#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */
1089#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */
1090
1091#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */
1092#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */
1093#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */
1094#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */
1095#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */
1096#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */
1097#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */
1098#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */
1099
1100#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */
1101#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */
1102#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */
1103#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */
1104#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */
1105#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */
1106#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */
1107#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */
1108
1109#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */
1110#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */
1111#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */
1112#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */
1113#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */
1114#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */
1115#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */
1116#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */
1117
1118#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */
1119#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */
1120#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */
1121#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */
1122#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */
1123#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */
1124#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */
1125#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */
1126
1127#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */
1128#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */
1129#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */
1130#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */
1131#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */
1132#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */
1133#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */
1134#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */
1135
1136#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */
1137#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */
1138#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */
1139#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */
1140#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */
1141#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */
1142#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */
1143#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */
1144
1145#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */
1146#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */
1147#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */
1148#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */
1149#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */
1150#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */
1151#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */
1152#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */
1153
1154#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */
1155#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */
1156#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */
1157#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */
1158#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */
1159#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */
1160#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */
1161#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */
1162
1163#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */
1164#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */
1165#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */
1166#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */
1167#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */
1168#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */
1169#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */
1170#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */
1171
1172#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */
1173#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */
1174#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */
1175#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */
1176#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */
1177#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */
1178#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */
1179#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */
1180
1181#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */
1182#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */
1183#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */
1184#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */
1185#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */
1186#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */
1187#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */
1188#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */
1189
1190#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */
1191#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */
1192#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */
1193#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */
1194#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */
1195#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */
1196#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */
1197#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */
1198
1199/* CAN Mailbox Area Macros */
1200#define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20))
1201#define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20))
1202#define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20))
1203#define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20))
1204#define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20))
1205#define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20))
1206#define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20))
1207#define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20))
1208
1209
1210/*********************************************************************************** */
1211/* System MMR Register Bits and Macros */
1212/******************************************************************************* */
1213
1214/* SWRST Mask */
1215#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
1216#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
1217#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
1218#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
1219#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
1220
1221/* SYSCR Masks */
1222#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
1223#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
1224
1225
1226/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
1227
1228/* Peripheral Masks For SIC0_ISR, SIC0_IWR, SIC0_IMASK */
1229#define PLL_WAKEUP_IRQ 0x00000001 /* PLL Wakeup Interrupt Request */
1230#define DMAC0_ERR_IRQ 0x00000002 /* DMA Controller 0 Error Interrupt Request */
1231#define PPI_ERR_IRQ 0x00000004 /* PPI Error Interrupt Request */
1232#define SPORT0_ERR_IRQ 0x00000008 /* SPORT0 Error Interrupt Request */
1233#define SPORT1_ERR_IRQ 0x00000010 /* SPORT1 Error Interrupt Request */
1234#define SPI0_ERR_IRQ 0x00000020 /* SPI0 Error Interrupt Request */
1235#define UART0_ERR_IRQ 0x00000040 /* UART0 Error Interrupt Request */
1236#define RTC_IRQ 0x00000080 /* Real-Time Clock Interrupt Request */
1237#define DMA0_IRQ 0x00000100 /* DMA Channel 0 (PPI) Interrupt Request */
1238#define DMA1_IRQ 0x00000200 /* DMA Channel 1 (SPORT0 RX) Interrupt Request */
1239#define DMA2_IRQ 0x00000400 /* DMA Channel 2 (SPORT0 TX) Interrupt Request */
1240#define DMA3_IRQ 0x00000800 /* DMA Channel 3 (SPORT1 RX) Interrupt Request */
1241#define DMA4_IRQ 0x00001000 /* DMA Channel 4 (SPORT1 TX) Interrupt Request */
1242#define DMA5_IRQ 0x00002000 /* DMA Channel 5 (SPI) Interrupt Request */
1243#define DMA6_IRQ 0x00004000 /* DMA Channel 6 (UART RX) Interrupt Request */
1244#define DMA7_IRQ 0x00008000 /* DMA Channel 7 (UART TX) Interrupt Request */
1245#define TIMER0_IRQ 0x00010000 /* Timer 0 Interrupt Request */
1246#define TIMER1_IRQ 0x00020000 /* Timer 1 Interrupt Request */
1247#define TIMER2_IRQ 0x00040000 /* Timer 2 Interrupt Request */
1248#define PFA_IRQ 0x00080000 /* Programmable Flag Interrupt Request A */
1249#define PFB_IRQ 0x00100000 /* Programmable Flag Interrupt Request B */
1250#define MDMA0_0_IRQ 0x00200000 /* MemDMA0 Stream 0 Interrupt Request */
1251#define MDMA0_1_IRQ 0x00400000 /* MemDMA0 Stream 1 Interrupt Request */
1252#define WDOG_IRQ 0x00800000 /* Software Watchdog Timer Interrupt Request */
1253#define DMAC1_ERR_IRQ 0x01000000 /* DMA Controller 1 Error Interrupt Request */
1254#define SPORT2_ERR_IRQ 0x02000000 /* SPORT2 Error Interrupt Request */
1255#define SPORT3_ERR_IRQ 0x04000000 /* SPORT3 Error Interrupt Request */
1256#define MXVR_SD_IRQ 0x08000000 /* MXVR Synchronous Data Interrupt Request */
1257#define SPI1_ERR_IRQ 0x10000000 /* SPI1 Error Interrupt Request */
1258#define SPI2_ERR_IRQ 0x20000000 /* SPI2 Error Interrupt Request */
1259#define UART1_ERR_IRQ 0x40000000 /* UART1 Error Interrupt Request */
1260#define UART2_ERR_IRQ 0x80000000 /* UART2 Error Interrupt Request */
1261
1262/* the following are for backwards compatibility */
1263#define DMA0_ERR_IRQ DMAC0_ERR_IRQ
1264#define DMA1_ERR_IRQ DMAC1_ERR_IRQ
1265
1266
1267/* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1 */
1268#define CAN_ERR_IRQ 0x00000001 /* CAN Error Interrupt Request */
1269#define DMA8_IRQ 0x00000002 /* DMA Channel 8 (SPORT2 RX) Interrupt Request */
1270#define DMA9_IRQ 0x00000004 /* DMA Channel 9 (SPORT2 TX) Interrupt Request */
1271#define DMA10_IRQ 0x00000008 /* DMA Channel 10 (SPORT3 RX) Interrupt Request */
1272#define DMA11_IRQ 0x00000010 /* DMA Channel 11 (SPORT3 TX) Interrupt Request */
1273#define DMA12_IRQ 0x00000020 /* DMA Channel 12 Interrupt Request */
1274#define DMA13_IRQ 0x00000040 /* DMA Channel 13 Interrupt Request */
1275#define DMA14_IRQ 0x00000080 /* DMA Channel 14 (SPI1) Interrupt Request */
1276#define DMA15_IRQ 0x00000100 /* DMA Channel 15 (SPI2) Interrupt Request */
1277#define DMA16_IRQ 0x00000200 /* DMA Channel 16 (UART1 RX) Interrupt Request */
1278#define DMA17_IRQ 0x00000400 /* DMA Channel 17 (UART1 TX) Interrupt Request */
1279#define DMA18_IRQ 0x00000800 /* DMA Channel 18 (UART2 RX) Interrupt Request */
1280#define DMA19_IRQ 0x00001000 /* DMA Channel 19 (UART2 TX) Interrupt Request */
1281#define TWI0_IRQ 0x00002000 /* TWI0 Interrupt Request */
1282#define TWI1_IRQ 0x00004000 /* TWI1 Interrupt Request */
1283#define CAN_RX_IRQ 0x00008000 /* CAN Receive Interrupt Request */
1284#define CAN_TX_IRQ 0x00010000 /* CAN Transmit Interrupt Request */
1285#define MDMA1_0_IRQ 0x00020000 /* MemDMA1 Stream 0 Interrupt Request */
1286#define MDMA1_1_IRQ 0x00040000 /* MemDMA1 Stream 1 Interrupt Request */
1287#define MXVR_STAT_IRQ 0x00080000 /* MXVR Status Interrupt Request */
1288#define MXVR_CM_IRQ 0x00100000 /* MXVR Control Message Interrupt Request */
1289#define MXVR_AP_IRQ 0x00200000 /* MXVR Asynchronous Packet Interrupt */
1290
1291/* the following are for backwards compatibility */
1292#define MDMA0_IRQ MDMA1_0_IRQ
1293#define MDMA1_IRQ MDMA1_1_IRQ
1294
1295#ifdef _MISRA_RULES
1296#define _MF15 0xFu
1297#define _MF7 7u
1298#else
1299#define _MF15 0xF
1300#define _MF7 7
1301#endif /* _MISRA_RULES */
1302
1303/* SIC_IMASKx Masks */
1304#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
1305#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
1306#ifdef _MISRA_RULES
1307#define SIC_MASK(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
1308#define SIC_UNMASK(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Unmask Peripheral #x interrupt */
1309#else
1310#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
1311#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
1312#endif /* _MISRA_RULES */
1313
1314/* SIC_IWRx Masks */
1315#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
1316#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
1317#ifdef _MISRA_RULES
1318#define IWR_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
1319#define IWR_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Wakeup Disable Peripheral #x */
1320#else
1321#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
1322#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
1323#endif /* _MISRA_RULES */
1324
1325/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
1326/* PPI_CONTROL Masks */
1327#define PORT_EN 0x0001 /* PPI Port Enable */
1328#define PORT_DIR 0x0002 /* PPI Port Direction */
1329#define XFR_TYPE 0x000C /* PPI Transfer Type */
1330#define PORT_CFG 0x0030 /* PPI Port Configuration */
1331#define FLD_SEL 0x0040 /* PPI Active Field Select */
1332#define PACK_EN 0x0080 /* PPI Packing Mode */
1333/* previous versions of defBF539.h erroneously included DMA32 (PPI 32-bit DMA Enable) */
1334#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
1335#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
1336#define DLENGTH 0x3800 /* PPI Data Length */
1337#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */
1338#define DLEN_10 0x0800 /* Data Length = 10 Bits */
1339#define DLEN_11 0x1000 /* Data Length = 11 Bits */
1340#define DLEN_12 0x1800 /* Data Length = 12 Bits */
1341#define DLEN_13 0x2000 /* Data Length = 13 Bits */
1342#define DLEN_14 0x2800 /* Data Length = 14 Bits */
1343#define DLEN_15 0x3000 /* Data Length = 15 Bits */
1344#define DLEN_16 0x3800 /* Data Length = 16 Bits */
1345#ifdef _MISRA_RULES
1346#define DLEN(x) ((((x)-9u) & 0x07u) << 11) /* PPI Data Length (only works for x=10-->x=16) */
1347#else
1348#define DLEN(x) ((((x)-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
1349#endif /* _MISRA_RULES */
1350#define POL 0xC000 /* PPI Signal Polarities */
1351#define POLC 0x4000 /* PPI Clock Polarity */
1352#define POLS 0x8000 /* PPI Frame Sync Polarity */
1353
1354
1355/* PPI_STATUS Masks */
1356#define FLD 0x0400 /* Field Indicator */
1357#define FT_ERR 0x0800 /* Frame Track Error */
1358#define OVR 0x1000 /* FIFO Overflow Error */
1359#define UNDR 0x2000 /* FIFO Underrun Error */
1360#define ERR_DET 0x4000 /* Error Detected Indicator */
1361#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
1362
1363
1364/* ********** DMA CONTROLLER MASKS ***********************/
1365
1366/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
1367
1368#define CTYPE 0x0040 /* DMA Channel Type Indicator */
1369#define CTYPE_P 0x6 /* DMA Channel Type Indicator BIT POSITION */
1370#define PCAP8 0x0080 /* DMA 8-bit Operation Indicator */
1371#define PCAP16 0x0100 /* DMA 16-bit Operation Indicator */
1372#define PCAP32 0x0200 /* DMA 32-bit Operation Indicator */
1373#define PCAPWR 0x0400 /* DMA Write Operation Indicator */
1374#define PCAPRD 0x0800 /* DMA Read Operation Indicator */
1375#define PMAP 0xF000 /* DMA Peripheral Map Field */
1376
1377/* PMAP Encodings For DMA Controller 0 */
1378#define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */
1379#define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */
1380#define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */
1381#define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */
1382#define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */
1383#define PMAP_SPI0 0x5000 /* PMAP SPI DMA */
1384#define PMAP_UART0RX 0x6000 /* PMAP UART Receive DMA */
1385#define PMAP_UART0TX 0x7000 /* PMAP UART Transmit DMA */
1386
1387/* PMAP Encodings For DMA Controller 1 */
1388#define PMAP_SPORT2RX 0x0000 /* PMAP SPORT2 Receive DMA */
1389#define PMAP_SPORT2TX 0x1000 /* PMAP SPORT2 Transmit DMA */
1390#define PMAP_SPORT3RX 0x2000 /* PMAP SPORT3 Receive DMA */
1391#define PMAP_SPORT3TX 0x3000 /* PMAP SPORT3 Transmit DMA */
1392#define PMAP_SPI1 0x6000 /* PMAP SPI1 DMA */
1393#define PMAP_SPI2 0x7000 /* PMAP SPI2 DMA */
1394#define PMAP_UART1RX 0x8000 /* PMAP UART1 Receive DMA */
1395#define PMAP_UART1TX 0x9000 /* PMAP UART1 Transmit DMA */
1396#define PMAP_UART2RX 0xA000 /* PMAP UART2 Receive DMA */
1397#define PMAP_UART2TX 0xB000 /* PMAP UART2 Transmit DMA */
1398
1399
1400/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
1401/* PWM Timer bit definitions */
1402/* TIMER_ENABLE Register */
1403#define TIMEN0 0x0001 /* Enable Timer 0 */
1404#define TIMEN1 0x0002 /* Enable Timer 1 */
1405#define TIMEN2 0x0004 /* Enable Timer 2 */
1406
1407#define TIMEN0_P 0x00
1408#define TIMEN1_P 0x01
1409#define TIMEN2_P 0x02
1410
1411/* TIMER_DISABLE Register */
1412#define TIMDIS0 0x0001 /* Disable Timer 0 */
1413#define TIMDIS1 0x0002 /* Disable Timer 1 */
1414#define TIMDIS2 0x0004 /* Disable Timer 2 */
1415
1416#define TIMDIS0_P 0x00
1417#define TIMDIS1_P 0x01
1418#define TIMDIS2_P 0x02
1419
1420/* TIMER_STATUS Register */
1421#define TIMIL0 0x0001 /* Timer 0 Interrupt */
1422#define TIMIL1 0x0002 /* Timer 1 Interrupt */
1423#define TIMIL2 0x0004 /* Timer 2 Interrupt */
1424#define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */
1425#define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */
1426#define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */
1427#define TRUN0 0x1000 /* Timer 0 Slave Enable Status */
1428#define TRUN1 0x2000 /* Timer 1 Slave Enable Status */
1429#define TRUN2 0x4000 /* Timer 2 Slave Enable Status */
1430
1431#define TIMIL0_P 0x00
1432#define TIMIL1_P 0x01
1433#define TIMIL2_P 0x02
1434#define TOVF_ERR0_P 0x04
1435#define TOVF_ERR1_P 0x05
1436#define TOVF_ERR2_P 0x06
1437#define TRUN0_P 0x0C
1438#define TRUN1_P 0x0D
1439#define TRUN2_P 0x0E
1440
1441/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
1442#define TOVL_ERR0 TOVF_ERR0
1443#define TOVL_ERR1 TOVF_ERR1
1444#define TOVL_ERR2 TOVF_ERR2
1445#define TOVL_ERR0_P TOVF_ERR0_P
1446#define TOVL_ERR1_P TOVF_ERR1_P
1447#define TOVL_ERR2_P TOVF_ERR2_P
1448
1449/* TIMERx_CONFIG Registers */
1450#define PWM_OUT 0x0001
1451#define WDTH_CAP 0x0002
1452#define EXT_CLK 0x0003
1453#define PULSE_HI 0x0004
1454#define PERIOD_CNT 0x0008
1455#define IRQ_ENA 0x0010
1456#define TIN_SEL 0x0020
1457#define OUT_DIS 0x0040
1458#define CLK_SEL 0x0080
1459#define TOGGLE_HI 0x0100
1460#define EMU_RUN 0x0200
1461#ifdef _MISRA_RULES
1462#define ERR_TYP(x) (((x) & 0x03u) << 14)
1463#else
1464#define ERR_TYP(x) (((x) & 0x03) << 14)
1465#endif /* _MISRA_RULES */
1466
1467#define TMODE_P0 0x00
1468#define TMODE_P1 0x01
1469#define PULSE_HI_P 0x02
1470#define PERIOD_CNT_P 0x03
1471#define IRQ_ENA_P 0x04
1472#define TIN_SEL_P 0x05
1473#define OUT_DIS_P 0x06
1474#define CLK_SEL_P 0x07
1475#define TOGGLE_HI_P 0x08
1476#define EMU_RUN_P 0x09
1477#define ERR_TYP_P0 0x0E
1478#define ERR_TYP_P1 0x0F
1479
1480/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
1481/* EBIU_AMGCTL Masks */
1482#define AMCKEN 0x0001 /* Enable CLKOUT */
1483#define AMBEN_NONE 0x0000 /* All Banks Disabled */
1484#define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */
1485#define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */
1486#define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
1487#define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
1488#define CDPRIO 0x0100 /* DMA has priority over core for external accesses */
1489
1490/* EBIU_AMGCTL Bit Positions */
1491#define AMCKEN_P 0x0000 /* Enable CLKOUT */
1492#define AMBEN_P0 0x0001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
1493#define AMBEN_P1 0x0002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
1494#define AMBEN_P2 0x0003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
1495
1496/* EBIU_AMBCTL0 Masks */
1497#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
1498#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
1499#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
1500#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
1501#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
1502#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
1503#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
1504#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
1505#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
1506#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
1507#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
1508#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
1509#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
1510#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
1511#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
1512#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
1513#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
1514#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
1515#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
1516#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
1517#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
1518#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
1519#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
1520#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
1521#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
1522#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
1523#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
1524#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
1525#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
1526#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
1527#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
1528#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
1529#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
1530#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
1531#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
1532#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
1533#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
1534#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
1535#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
1536#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
1537#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
1538#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
1539#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
1540#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
1541#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
1542#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
1543#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
1544#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
1545#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
1546#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
1547#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1548#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1549#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1550#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1551#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1552#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1553#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1554#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1555#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
1556#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
1557#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
1558#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
1559#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
1560#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
1561#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
1562#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
1563#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
1564#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
1565#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
1566#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
1567#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
1568#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
1569#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
1570#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
1571#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
1572#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
1573#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
1574#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
1575#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
1576#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
1577#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
1578#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
1579#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
1580#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
1581#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
1582#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
1583#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
1584#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
1585
1586/* EBIU_AMBCTL1 Masks */
1587#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
1588#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
1589#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
1590#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
1591#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
1592#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
1593#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1594#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1595#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1596#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1597#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1598#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1599#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1600#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1601#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
1602#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
1603#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
1604#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
1605#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
1606#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
1607#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
1608#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
1609#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
1610#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
1611#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
1612#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
1613#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
1614#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
1615#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
1616#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
1617#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
1618#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
1619#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
1620#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
1621#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
1622#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
1623#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
1624#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
1625#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
1626#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
1627#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
1628#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
1629#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
1630#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
1631#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
1632#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
1633#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
1634#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
1635#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
1636#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
1637#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1638#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1639#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1640#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1641#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1642#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1643#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1644#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1645#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
1646#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
1647#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
1648#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
1649#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
1650#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
1651#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
1652#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
1653#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
1654#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
1655#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
1656#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
1657#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
1658#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
1659#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
1660#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
1661#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
1662#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
1663#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
1664#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
1665#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
1666#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
1667#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
1668#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
1669#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
1670#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
1671#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
1672#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
1673#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
1674#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
1675
1676/* ********************** SDRAM CONTROLLER MASKS *************************** */
1677/* EBIU_SDGCTL Masks */
1678#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
1679#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
1680#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
1681#define PFE 0x00000010 /* Enable SDRAM prefetch */
1682#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
1683#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
1684#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
1685#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
1686#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
1687#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
1688#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
1689#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
1690#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
1691#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
1692#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
1693#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
1694#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
1695#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
1696#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
1697#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
1698#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
1699#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
1700#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
1701#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
1702#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
1703#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
1704#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
1705#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
1706#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
1707#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
1708#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
1709#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
1710#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
1711#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
1712#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
1713#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
1714#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
1715#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
1716#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
1717#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
1718#define PUPSD 0x00200000 /*Power-up start delay */
1719#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
1720#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
1721#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
1722#define EBUFE 0x02000000 /* Enable external buffering timing */
1723#define FBBRW 0x04000000 /* Fast back-to-back read write enable */
1724#define EMREN 0x10000000 /* Extended mode register enable */
1725#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
1726#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
1727
1728/* EBIU_SDBCTL Masks */
1729#define EBE 0x00000001 /* Enable SDRAM external bank */
1730#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */
1731#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */
1732#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */
1733#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */
1734#define EBSZ_256 0x00000008 /* SDRAM External Bank Size = 256MB */
1735#define EBSZ_512 0x0000000A /* SDRAM External Bank Size = 512MB */
1736#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
1737#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
1738#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
1739#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
1740
1741/* EBIU_SDSTAT Masks */
1742#define SDCI 0x00000001 /* SDRAM controller is idle */
1743#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
1744#define SDPUA 0x00000004 /* SDRAM power up active */
1745#define SDRS 0x00000008 /* SDRAM is in reset state */
1746#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
1747#define BGSTAT 0x00000020 /* Bus granted */
1748
1749
1750/* ******************** TWO-WIRE INTERFACE (TWIx) MASKS ***********************/
1751/* TWIx_CLKDIV Macros (Use: *pTWIx_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
1752#ifdef _MISRA_RULES
1753#define CLKLOW(x) ((x) & 0xFFu) /* Periods Clock Is Held Low */
1754#define CLKHI(y) (((y)&0xFFu)<<0x8) /* Periods Before New Clock Low */
1755#else
1756#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
1757#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
1758#endif /* _MISRA_RULES */
1759
1760/* TWIx_PRESCALE Masks */
1761#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
1762#define TWI_ENA 0x0080 /* TWI Enable */
1763#define SCCB 0x0200 /* SCCB Compatibility Enable */
1764
1765/* TWIx_SLAVE_CTRL Masks */
1766#define SEN 0x0001 /* Slave Enable */
1767#define SADD_LEN 0x0002 /* Slave Address Length */
1768#define STDVAL 0x0004 /* Slave Transmit Data Valid */
1769#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
1770#define GEN 0x0010 /* General Call Adrress Matching Enabled */
1771
1772/* TWIx_SLAVE_STAT Masks */
1773#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
1774#define GCALL 0x0002 /* General Call Indicator */
1775
1776/* TWIx_MASTER_CTRL Masks */
1777#define MEN 0x0001 /* Master Mode Enable */
1778#define MADD_LEN 0x0002 /* Master Address Length */
1779#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
1780#define FAST 0x0008 /* Use Fast Mode Timing Specs */
1781#define STOP 0x0010 /* Issue Stop Condition */
1782#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
1783#define DCNT 0x3FC0 /* Data Bytes To Transfer */
1784#define SDAOVR 0x4000 /* Serial Data Override */
1785#define SCLOVR 0x8000 /* Serial Clock Override */
1786
1787/* TWIx_MASTER_STAT Masks */
1788#define MPROG 0x0001 /* Master Transfer In Progress */
1789#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
1790#define ANAK 0x0004 /* Address Not Acknowledged */
1791#define DNAK 0x0008 /* Data Not Acknowledged */
1792#define BUFRDERR 0x0010 /* Buffer Read Error */
1793#define BUFWRERR 0x0020 /* Buffer Write Error */
1794#define SDASEN 0x0040 /* Serial Data Sense */
1795#define SCLSEN 0x0080 /* Serial Clock Sense */
1796#define BUSBUSY 0x0100 /* Bus Busy Indicator */
1797
1798/* TWIx_INT_SRC and TWIx_INT_ENABLE Masks */
1799#define SINIT 0x0001 /* Slave Transfer Initiated */
1800#define SCOMP 0x0002 /* Slave Transfer Complete */
1801#define SERR 0x0004 /* Slave Transfer Error */
1802#define SOVF 0x0008 /* Slave Overflow */
1803#define MCOMP 0x0010 /* Master Transfer Complete */
1804#define MERR 0x0020 /* Master Transfer Error */
1805#define XMTSERV 0x0040 /* Transmit FIFO Service */
1806#define RCVSERV 0x0080 /* Receive FIFO Service */
1807
1808/* TWIx_FIFO_CTL Masks */
1809#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
1810#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
1811#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
1812#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
1813
1814/* TWIx_FIFO_STAT Masks */
1815#define XMTSTAT 0x0003 /* Transmit FIFO Status */
1816#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
1817#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
1818#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
1819
1820#define RCVSTAT 0x000C /* Receive FIFO Status */
1821#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
1822#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
1823#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
1824
1825#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h
index 7a8ac5f44204..8100bcd01a0d 100644
--- a/arch/blackfin/mach-bf538/include/mach/defBF539.h
+++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h
@@ -1,859 +1,13 @@
1/* 1/*
2 * Copyright 2008-2009 Analog Devices Inc. 2 * Copyright 2008-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF538/9 */
8
9#ifndef _DEF_BF539_H 7#ifndef _DEF_BF539_H
10#define _DEF_BF539_H 8#define _DEF_BF539_H
11 9
12/* include all Core registers and bit definitions */ 10#include "defBF538.h"
13#include <asm/def_LPBlackfin.h>
14
15
16/*********************************************************************************** */
17/* System MMR Register Map */
18/*********************************************************************************** */
19/* Clock/Regulator Control (0xFFC00000 - 0xFFC000FF) */
20#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
21#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
22#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
23#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
24#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
25#define CHIPID 0xFFC00014 /* Chip ID Register */
26
27/* CHIPID Masks */
28#define CHIPID_VERSION 0xF0000000
29#define CHIPID_FAMILY 0x0FFFF000
30#define CHIPID_MANUFACTURE 0x00000FFE
31
32/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
33#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
34#define SYSCR 0xFFC00104 /* System Configuration registe */
35#define SIC_RVECT 0xFFC00108
36#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
37#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
38#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
39#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
40#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
41#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
42#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
43#define SIC_IMASK1 0xFFC00128 /* Interrupt Mask Register 1 */
44#define SIC_ISR1 0xFFC0012C /* Interrupt Status Register 1 */
45#define SIC_IWR1 0xFFC00130 /* Interrupt Wakeup Register 1 */
46#define SIC_IAR4 0xFFC00134 /* Interrupt Assignment Register 4 */
47#define SIC_IAR5 0xFFC00138 /* Interrupt Assignment Register 5 */
48#define SIC_IAR6 0xFFC0013C /* Interrupt Assignment Register 6 */
49
50
51/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
52#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
53#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
54#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
55
56
57/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
58#define RTC_STAT 0xFFC00300 /* RTC Status Register */
59#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
60#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
61#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
62#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
63#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
64#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */
65
66
67/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
68#define UART0_THR 0xFFC00400 /* Transmit Holding register */
69#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
70#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
71#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
72#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
73#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
74#define UART0_LCR 0xFFC0040C /* Line Control Register */
75#define UART0_MCR 0xFFC00410 /* Modem Control Register */
76#define UART0_LSR 0xFFC00414 /* Line Status Register */
77#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
78#define UART0_GCTL 0xFFC00424 /* Global Control Register */
79
80
81/* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */
82
83#define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */
84#define SPI0_FLG 0xFFC00504 /* SPI0 Flag register */
85#define SPI0_STAT 0xFFC00508 /* SPI0 Status register */
86#define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */
87#define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */
88#define SPI0_BAUD 0xFFC00514 /* SPI0 Baud rate Register */
89#define SPI0_SHADOW 0xFFC00518 /* SPI0_RDBR Shadow Register */
90#define SPI0_REGBASE SPI0_CTL
91
92
93/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
94#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
95#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
96#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
97#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
98
99#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
100#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
101#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
102#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
103
104#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
105#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
106#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
107#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
108
109#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */
110#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */
111#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */
112
113
114/* Programmable Flags (0xFFC00700 - 0xFFC007FF) */
115#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */
116#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */
117#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */
118#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */
119#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */
120#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */
121#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */
122#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */
123#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */
124#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */
125#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */
126#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */
127#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */
128#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */
129#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */
130#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */
131#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */
132
133
134/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
135#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
136#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
137#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
138#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
139#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
140#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
141#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
142#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
143#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
144#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
145#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
146#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
147#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
148#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
149#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
150#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
151#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
152#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
153#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
154#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
155#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
156#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
157
158
159/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
160#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
161#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
162#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
163#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
164#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
165#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
166#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
167#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
168#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
169#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
170#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
171#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
172#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
173#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
174#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
175#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
176#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
177#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
178#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
179#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
180#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
181#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
182
183
184/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
185/* Asynchronous Memory Controller */
186#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
187#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
188#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
189
190/* SDRAM Controller */
191#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
192#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
193#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
194#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
195
196
197
198/* DMA Controller 0 Traffic Control Registers (0xFFC00B00 - 0xFFC00BFF) */
199
200#define DMAC0_TC_PER 0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */
201#define DMAC0_TC_CNT 0xFFC00B10 /* DMA Controller 0 Traffic Control Current Counts Register */
202
203/* Alternate deprecated register names (below) provided for backwards code compatibility */
204#define DMA0_TCPER DMAC0_TC_PER
205#define DMA0_TCCNT DMAC0_TC_CNT
206
207
208/* DMA Controller 0 (0xFFC00C00 - 0xFFC00FFF) */
209
210#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
211#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
212#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
213#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
214#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
215#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
216#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
217#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
218#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
219#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
220#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
221#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
222#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
223
224#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
225#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
226#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
227#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
228#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
229#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
230#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
231#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
232#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
233#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
234#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
235#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
236#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
237
238#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
239#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
240#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
241#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
242#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
243#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
244#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
245#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
246#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
247#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
248#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
249#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
250#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
251
252#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
253#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
254#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
255#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
256#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
257#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
258#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
259#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
260#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
261#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
262#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
263#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
264#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
265
266#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
267#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
268#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
269#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
270#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
271#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
272#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
273#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
274#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
275#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
276#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
277#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
278#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
279
280#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
281#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
282#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
283#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
284#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
285#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
286#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
287#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
288#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
289#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
290#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
291#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
292#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
293
294#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
295#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
296#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
297#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
298#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
299#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
300#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
301#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
302#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
303#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
304#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
305#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
306#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
307
308#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
309#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
310#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
311#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
312#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
313#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
314#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
315#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
316#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
317#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
318#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
319#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
320#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
321
322#define MDMA0_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA0 Stream 0 Destination Next Descriptor Pointer Register */
323#define MDMA0_D0_START_ADDR 0xFFC00E04 /* MemDMA0 Stream 0 Destination Start Address Register */
324#define MDMA0_D0_CONFIG 0xFFC00E08 /* MemDMA0 Stream 0 Destination Configuration Register */
325#define MDMA0_D0_X_COUNT 0xFFC00E10 /* MemDMA0 Stream 0 Destination X Count Register */
326#define MDMA0_D0_X_MODIFY 0xFFC00E14 /* MemDMA0 Stream 0 Destination X Modify Register */
327#define MDMA0_D0_Y_COUNT 0xFFC00E18 /* MemDMA0 Stream 0 Destination Y Count Register */
328#define MDMA0_D0_Y_MODIFY 0xFFC00E1C /* MemDMA0 Stream 0 Destination Y Modify Register */
329#define MDMA0_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA0 Stream 0 Destination Current Descriptor Pointer Register */
330#define MDMA0_D0_CURR_ADDR 0xFFC00E24 /* MemDMA0 Stream 0 Destination Current Address Register */
331#define MDMA0_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA0 Stream 0 Destination Interrupt/Status Register */
332#define MDMA0_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA0 Stream 0 Destination Peripheral Map Register */
333#define MDMA0_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA0 Stream 0 Destination Current X Count Register */
334#define MDMA0_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA0 Stream 0 Destination Current Y Count Register */
335
336#define MDMA0_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA0 Stream 0 Source Next Descriptor Pointer Register */
337#define MDMA0_S0_START_ADDR 0xFFC00E44 /* MemDMA0 Stream 0 Source Start Address Register */
338#define MDMA0_S0_CONFIG 0xFFC00E48 /* MemDMA0 Stream 0 Source Configuration Register */
339#define MDMA0_S0_X_COUNT 0xFFC00E50 /* MemDMA0 Stream 0 Source X Count Register */
340#define MDMA0_S0_X_MODIFY 0xFFC00E54 /* MemDMA0 Stream 0 Source X Modify Register */
341#define MDMA0_S0_Y_COUNT 0xFFC00E58 /* MemDMA0 Stream 0 Source Y Count Register */
342#define MDMA0_S0_Y_MODIFY 0xFFC00E5C /* MemDMA0 Stream 0 Source Y Modify Register */
343#define MDMA0_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA0 Stream 0 Source Current Descriptor Pointer Register */
344#define MDMA0_S0_CURR_ADDR 0xFFC00E64 /* MemDMA0 Stream 0 Source Current Address Register */
345#define MDMA0_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA0 Stream 0 Source Interrupt/Status Register */
346#define MDMA0_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA0 Stream 0 Source Peripheral Map Register */
347#define MDMA0_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA0 Stream 0 Source Current X Count Register */
348#define MDMA0_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA0 Stream 0 Source Current Y Count Register */
349
350#define MDMA0_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA0 Stream 1 Destination Next Descriptor Pointer Register */
351#define MDMA0_D1_START_ADDR 0xFFC00E84 /* MemDMA0 Stream 1 Destination Start Address Register */
352#define MDMA0_D1_CONFIG 0xFFC00E88 /* MemDMA0 Stream 1 Destination Configuration Register */
353#define MDMA0_D1_X_COUNT 0xFFC00E90 /* MemDMA0 Stream 1 Destination X Count Register */
354#define MDMA0_D1_X_MODIFY 0xFFC00E94 /* MemDMA0 Stream 1 Destination X Modify Register */
355#define MDMA0_D1_Y_COUNT 0xFFC00E98 /* MemDMA0 Stream 1 Destination Y Count Register */
356#define MDMA0_D1_Y_MODIFY 0xFFC00E9C /* MemDMA0 Stream 1 Destination Y Modify Register */
357#define MDMA0_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA0 Stream 1 Destination Current Descriptor Pointer Register */
358#define MDMA0_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA0 Stream 1 Destination Current Address Register */
359#define MDMA0_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA0 Stream 1 Destination Interrupt/Status Register */
360#define MDMA0_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA0 Stream 1 Destination Peripheral Map Register */
361#define MDMA0_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA0 Stream 1 Destination Current X Count Register */
362#define MDMA0_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA0 Stream 1 Destination Current Y Count Register */
363
364#define MDMA0_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA0 Stream 1 Source Next Descriptor Pointer Register */
365#define MDMA0_S1_START_ADDR 0xFFC00EC4 /* MemDMA0 Stream 1 Source Start Address Register */
366#define MDMA0_S1_CONFIG 0xFFC00EC8 /* MemDMA0 Stream 1 Source Configuration Register */
367#define MDMA0_S1_X_COUNT 0xFFC00ED0 /* MemDMA0 Stream 1 Source X Count Register */
368#define MDMA0_S1_X_MODIFY 0xFFC00ED4 /* MemDMA0 Stream 1 Source X Modify Register */
369#define MDMA0_S1_Y_COUNT 0xFFC00ED8 /* MemDMA0 Stream 1 Source Y Count Register */
370#define MDMA0_S1_Y_MODIFY 0xFFC00EDC /* MemDMA0 Stream 1 Source Y Modify Register */
371#define MDMA0_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA0 Stream 1 Source Current Descriptor Pointer Register */
372#define MDMA0_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA0 Stream 1 Source Current Address Register */
373#define MDMA0_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA0 Stream 1 Source Interrupt/Status Register */
374#define MDMA0_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA0 Stream 1 Source Peripheral Map Register */
375#define MDMA0_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA0 Stream 1 Source Current X Count Register */
376#define MDMA0_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA0 Stream 1 Source Current Y Count Register */
377
378#define MDMA_D0_NEXT_DESC_PTR MDMA0_D0_NEXT_DESC_PTR
379#define MDMA_D0_START_ADDR MDMA0_D0_START_ADDR
380#define MDMA_D0_CONFIG MDMA0_D0_CONFIG
381#define MDMA_D0_X_COUNT MDMA0_D0_X_COUNT
382#define MDMA_D0_X_MODIFY MDMA0_D0_X_MODIFY
383#define MDMA_D0_Y_COUNT MDMA0_D0_Y_COUNT
384#define MDMA_D0_Y_MODIFY MDMA0_D0_Y_MODIFY
385#define MDMA_D0_CURR_DESC_PTR MDMA0_D0_CURR_DESC_PTR
386#define MDMA_D0_CURR_ADDR MDMA0_D0_CURR_ADDR
387#define MDMA_D0_IRQ_STATUS MDMA0_D0_IRQ_STATUS
388#define MDMA_D0_PERIPHERAL_MAP MDMA0_D0_PERIPHERAL_MAP
389#define MDMA_D0_CURR_X_COUNT MDMA0_D0_CURR_X_COUNT
390#define MDMA_D0_CURR_Y_COUNT MDMA0_D0_CURR_Y_COUNT
391
392#define MDMA_S0_NEXT_DESC_PTR MDMA0_S0_NEXT_DESC_PTR
393#define MDMA_S0_START_ADDR MDMA0_S0_START_ADDR
394#define MDMA_S0_CONFIG MDMA0_S0_CONFIG
395#define MDMA_S0_X_COUNT MDMA0_S0_X_COUNT
396#define MDMA_S0_X_MODIFY MDMA0_S0_X_MODIFY
397#define MDMA_S0_Y_COUNT MDMA0_S0_Y_COUNT
398#define MDMA_S0_Y_MODIFY MDMA0_S0_Y_MODIFY
399#define MDMA_S0_CURR_DESC_PTR MDMA0_S0_CURR_DESC_PTR
400#define MDMA_S0_CURR_ADDR MDMA0_S0_CURR_ADDR
401#define MDMA_S0_IRQ_STATUS MDMA0_S0_IRQ_STATUS
402#define MDMA_S0_PERIPHERAL_MAP MDMA0_S0_PERIPHERAL_MAP
403#define MDMA_S0_CURR_X_COUNT MDMA0_S0_CURR_X_COUNT
404#define MDMA_S0_CURR_Y_COUNT MDMA0_S0_CURR_Y_COUNT
405
406#define MDMA_D1_NEXT_DESC_PTR MDMA0_D1_NEXT_DESC_PTR
407#define MDMA_D1_START_ADDR MDMA0_D1_START_ADDR
408#define MDMA_D1_CONFIG MDMA0_D1_CONFIG
409#define MDMA_D1_X_COUNT MDMA0_D1_X_COUNT
410#define MDMA_D1_X_MODIFY MDMA0_D1_X_MODIFY
411#define MDMA_D1_Y_COUNT MDMA0_D1_Y_COUNT
412#define MDMA_D1_Y_MODIFY MDMA0_D1_Y_MODIFY
413#define MDMA_D1_CURR_DESC_PTR MDMA0_D1_CURR_DESC_PTR
414#define MDMA_D1_CURR_ADDR MDMA0_D1_CURR_ADDR
415#define MDMA_D1_IRQ_STATUS MDMA0_D1_IRQ_STATUS
416#define MDMA_D1_PERIPHERAL_MAP MDMA0_D1_PERIPHERAL_MAP
417#define MDMA_D1_CURR_X_COUNT MDMA0_D1_CURR_X_COUNT
418#define MDMA_D1_CURR_Y_COUNT MDMA0_D1_CURR_Y_COUNT
419
420#define MDMA_S1_NEXT_DESC_PTR MDMA0_S1_NEXT_DESC_PTR
421#define MDMA_S1_START_ADDR MDMA0_S1_START_ADDR
422#define MDMA_S1_CONFIG MDMA0_S1_CONFIG
423#define MDMA_S1_X_COUNT MDMA0_S1_X_COUNT
424#define MDMA_S1_X_MODIFY MDMA0_S1_X_MODIFY
425#define MDMA_S1_Y_COUNT MDMA0_S1_Y_COUNT
426#define MDMA_S1_Y_MODIFY MDMA0_S1_Y_MODIFY
427#define MDMA_S1_CURR_DESC_PTR MDMA0_S1_CURR_DESC_PTR
428#define MDMA_S1_CURR_ADDR MDMA0_S1_CURR_ADDR
429#define MDMA_S1_IRQ_STATUS MDMA0_S1_IRQ_STATUS
430#define MDMA_S1_PERIPHERAL_MAP MDMA0_S1_PERIPHERAL_MAP
431#define MDMA_S1_CURR_X_COUNT MDMA0_S1_CURR_X_COUNT
432#define MDMA_S1_CURR_Y_COUNT MDMA0_S1_CURR_Y_COUNT
433
434
435/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
436#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
437#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
438#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
439#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
440#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
441
442
443/* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF) */
444#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
445#define TWI0_CONTROL 0xFFC01404 /* TWI0 Master Internal Time Reference Register */
446#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
447#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
448#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
449#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
450#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
451#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
452#define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */
453#define TWI0_INT_MASK 0xFFC01424 /* TWI0 Master Interrupt Mask Register */
454#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
455#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
456#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
457#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
458#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
459#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
460
461#define TWI0_REGBASE TWI0_CLKDIV
462
463/* the following are for backwards compatibility */
464#define TWI0_PRESCALE TWI0_CONTROL
465#define TWI0_INT_SRC TWI0_INT_STAT
466#define TWI0_INT_ENABLE TWI0_INT_MASK
467
468
469/* General-Purpose Ports (0xFFC01500 - 0xFFC015FF) */
470
471/* GPIO Port C Register Names */
472#define PORTCIO_FER 0xFFC01500 /* GPIO Pin Port C Configuration Register */
473#define PORTCIO 0xFFC01510 /* GPIO Pin Port C Data Register */
474#define PORTCIO_CLEAR 0xFFC01520 /* Clear GPIO Pin Port C Register */
475#define PORTCIO_SET 0xFFC01530 /* Set GPIO Pin Port C Register */
476#define PORTCIO_TOGGLE 0xFFC01540 /* Toggle GPIO Pin Port C Register */
477#define PORTCIO_DIR 0xFFC01550 /* GPIO Pin Port C Direction Register */
478#define PORTCIO_INEN 0xFFC01560 /* GPIO Pin Port C Input Enable Register */
479
480/* GPIO Port D Register Names */
481#define PORTDIO_FER 0xFFC01504 /* GPIO Pin Port D Configuration Register */
482#define PORTDIO 0xFFC01514 /* GPIO Pin Port D Data Register */
483#define PORTDIO_CLEAR 0xFFC01524 /* Clear GPIO Pin Port D Register */
484#define PORTDIO_SET 0xFFC01534 /* Set GPIO Pin Port D Register */
485#define PORTDIO_TOGGLE 0xFFC01544 /* Toggle GPIO Pin Port D Register */
486#define PORTDIO_DIR 0xFFC01554 /* GPIO Pin Port D Direction Register */
487#define PORTDIO_INEN 0xFFC01564 /* GPIO Pin Port D Input Enable Register */
488
489/* GPIO Port E Register Names */
490#define PORTEIO_FER 0xFFC01508 /* GPIO Pin Port E Configuration Register */
491#define PORTEIO 0xFFC01518 /* GPIO Pin Port E Data Register */
492#define PORTEIO_CLEAR 0xFFC01528 /* Clear GPIO Pin Port E Register */
493#define PORTEIO_SET 0xFFC01538 /* Set GPIO Pin Port E Register */
494#define PORTEIO_TOGGLE 0xFFC01548 /* Toggle GPIO Pin Port E Register */
495#define PORTEIO_DIR 0xFFC01558 /* GPIO Pin Port E Direction Register */
496#define PORTEIO_INEN 0xFFC01568 /* GPIO Pin Port E Input Enable Register */
497
498/* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */
499
500#define DMAC1_TC_PER 0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */
501#define DMAC1_TC_CNT 0xFFC01B10 /* DMA Controller 1 Traffic Control Current Counts Register */
502
503/* Alternate deprecated register names (below) provided for backwards code compatibility */
504#define DMA1_TCPER DMAC1_TC_PER
505#define DMA1_TCCNT DMAC1_TC_CNT
506
507
508/* DMA Controller 1 (0xFFC01C00 - 0xFFC01FFF) */
509#define DMA8_NEXT_DESC_PTR 0xFFC01C00 /* DMA Channel 8 Next Descriptor Pointer Register */
510#define DMA8_START_ADDR 0xFFC01C04 /* DMA Channel 8 Start Address Register */
511#define DMA8_CONFIG 0xFFC01C08 /* DMA Channel 8 Configuration Register */
512#define DMA8_X_COUNT 0xFFC01C10 /* DMA Channel 8 X Count Register */
513#define DMA8_X_MODIFY 0xFFC01C14 /* DMA Channel 8 X Modify Register */
514#define DMA8_Y_COUNT 0xFFC01C18 /* DMA Channel 8 Y Count Register */
515#define DMA8_Y_MODIFY 0xFFC01C1C /* DMA Channel 8 Y Modify Register */
516#define DMA8_CURR_DESC_PTR 0xFFC01C20 /* DMA Channel 8 Current Descriptor Pointer Register */
517#define DMA8_CURR_ADDR 0xFFC01C24 /* DMA Channel 8 Current Address Register */
518#define DMA8_IRQ_STATUS 0xFFC01C28 /* DMA Channel 8 Interrupt/Status Register */
519#define DMA8_PERIPHERAL_MAP 0xFFC01C2C /* DMA Channel 8 Peripheral Map Register */
520#define DMA8_CURR_X_COUNT 0xFFC01C30 /* DMA Channel 8 Current X Count Register */
521#define DMA8_CURR_Y_COUNT 0xFFC01C38 /* DMA Channel 8 Current Y Count Register */
522
523#define DMA9_NEXT_DESC_PTR 0xFFC01C40 /* DMA Channel 9 Next Descriptor Pointer Register */
524#define DMA9_START_ADDR 0xFFC01C44 /* DMA Channel 9 Start Address Register */
525#define DMA9_CONFIG 0xFFC01C48 /* DMA Channel 9 Configuration Register */
526#define DMA9_X_COUNT 0xFFC01C50 /* DMA Channel 9 X Count Register */
527#define DMA9_X_MODIFY 0xFFC01C54 /* DMA Channel 9 X Modify Register */
528#define DMA9_Y_COUNT 0xFFC01C58 /* DMA Channel 9 Y Count Register */
529#define DMA9_Y_MODIFY 0xFFC01C5C /* DMA Channel 9 Y Modify Register */
530#define DMA9_CURR_DESC_PTR 0xFFC01C60 /* DMA Channel 9 Current Descriptor Pointer Register */
531#define DMA9_CURR_ADDR 0xFFC01C64 /* DMA Channel 9 Current Address Register */
532#define DMA9_IRQ_STATUS 0xFFC01C68 /* DMA Channel 9 Interrupt/Status Register */
533#define DMA9_PERIPHERAL_MAP 0xFFC01C6C /* DMA Channel 9 Peripheral Map Register */
534#define DMA9_CURR_X_COUNT 0xFFC01C70 /* DMA Channel 9 Current X Count Register */
535#define DMA9_CURR_Y_COUNT 0xFFC01C78 /* DMA Channel 9 Current Y Count Register */
536
537#define DMA10_NEXT_DESC_PTR 0xFFC01C80 /* DMA Channel 10 Next Descriptor Pointer Register */
538#define DMA10_START_ADDR 0xFFC01C84 /* DMA Channel 10 Start Address Register */
539#define DMA10_CONFIG 0xFFC01C88 /* DMA Channel 10 Configuration Register */
540#define DMA10_X_COUNT 0xFFC01C90 /* DMA Channel 10 X Count Register */
541#define DMA10_X_MODIFY 0xFFC01C94 /* DMA Channel 10 X Modify Register */
542#define DMA10_Y_COUNT 0xFFC01C98 /* DMA Channel 10 Y Count Register */
543#define DMA10_Y_MODIFY 0xFFC01C9C /* DMA Channel 10 Y Modify Register */
544#define DMA10_CURR_DESC_PTR 0xFFC01CA0 /* DMA Channel 10 Current Descriptor Pointer Register */
545#define DMA10_CURR_ADDR 0xFFC01CA4 /* DMA Channel 10 Current Address Register */
546#define DMA10_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 10 Interrupt/Status Register */
547#define DMA10_PERIPHERAL_MAP 0xFFC01CAC /* DMA Channel 10 Peripheral Map Register */
548#define DMA10_CURR_X_COUNT 0xFFC01CB0 /* DMA Channel 10 Current X Count Register */
549#define DMA10_CURR_Y_COUNT 0xFFC01CB8 /* DMA Channel 10 Current Y Count Register */
550
551#define DMA11_NEXT_DESC_PTR 0xFFC01CC0 /* DMA Channel 11 Next Descriptor Pointer Register */
552#define DMA11_START_ADDR 0xFFC01CC4 /* DMA Channel 11 Start Address Register */
553#define DMA11_CONFIG 0xFFC01CC8 /* DMA Channel 11 Configuration Register */
554#define DMA11_X_COUNT 0xFFC01CD0 /* DMA Channel 11 X Count Register */
555#define DMA11_X_MODIFY 0xFFC01CD4 /* DMA Channel 11 X Modify Register */
556#define DMA11_Y_COUNT 0xFFC01CD8 /* DMA Channel 11 Y Count Register */
557#define DMA11_Y_MODIFY 0xFFC01CDC /* DMA Channel 11 Y Modify Register */
558#define DMA11_CURR_DESC_PTR 0xFFC01CE0 /* DMA Channel 11 Current Descriptor Pointer Register */
559#define DMA11_CURR_ADDR 0xFFC01CE4 /* DMA Channel 11 Current Address Register */
560#define DMA11_IRQ_STATUS 0xFFC01CE8 /* DMA Channel 11 Interrupt/Status Register */
561#define DMA11_PERIPHERAL_MAP 0xFFC01CEC /* DMA Channel 11 Peripheral Map Register */
562#define DMA11_CURR_X_COUNT 0xFFC01CF0 /* DMA Channel 11 Current X Count Register */
563#define DMA11_CURR_Y_COUNT 0xFFC01CF8 /* DMA Channel 11 Current Y Count Register */
564
565#define DMA12_NEXT_DESC_PTR 0xFFC01D00 /* DMA Channel 12 Next Descriptor Pointer Register */
566#define DMA12_START_ADDR 0xFFC01D04 /* DMA Channel 12 Start Address Register */
567#define DMA12_CONFIG 0xFFC01D08 /* DMA Channel 12 Configuration Register */
568#define DMA12_X_COUNT 0xFFC01D10 /* DMA Channel 12 X Count Register */
569#define DMA12_X_MODIFY 0xFFC01D14 /* DMA Channel 12 X Modify Register */
570#define DMA12_Y_COUNT 0xFFC01D18 /* DMA Channel 12 Y Count Register */
571#define DMA12_Y_MODIFY 0xFFC01D1C /* DMA Channel 12 Y Modify Register */
572#define DMA12_CURR_DESC_PTR 0xFFC01D20 /* DMA Channel 12 Current Descriptor Pointer Register */
573#define DMA12_CURR_ADDR 0xFFC01D24 /* DMA Channel 12 Current Address Register */
574#define DMA12_IRQ_STATUS 0xFFC01D28 /* DMA Channel 12 Interrupt/Status Register */
575#define DMA12_PERIPHERAL_MAP 0xFFC01D2C /* DMA Channel 12 Peripheral Map Register */
576#define DMA12_CURR_X_COUNT 0xFFC01D30 /* DMA Channel 12 Current X Count Register */
577#define DMA12_CURR_Y_COUNT 0xFFC01D38 /* DMA Channel 12 Current Y Count Register */
578
579#define DMA13_NEXT_DESC_PTR 0xFFC01D40 /* DMA Channel 13 Next Descriptor Pointer Register */
580#define DMA13_START_ADDR 0xFFC01D44 /* DMA Channel 13 Start Address Register */
581#define DMA13_CONFIG 0xFFC01D48 /* DMA Channel 13 Configuration Register */
582#define DMA13_X_COUNT 0xFFC01D50 /* DMA Channel 13 X Count Register */
583#define DMA13_X_MODIFY 0xFFC01D54 /* DMA Channel 13 X Modify Register */
584#define DMA13_Y_COUNT 0xFFC01D58 /* DMA Channel 13 Y Count Register */
585#define DMA13_Y_MODIFY 0xFFC01D5C /* DMA Channel 13 Y Modify Register */
586#define DMA13_CURR_DESC_PTR 0xFFC01D60 /* DMA Channel 13 Current Descriptor Pointer Register */
587#define DMA13_CURR_ADDR 0xFFC01D64 /* DMA Channel 13 Current Address Register */
588#define DMA13_IRQ_STATUS 0xFFC01D68 /* DMA Channel 13 Interrupt/Status Register */
589#define DMA13_PERIPHERAL_MAP 0xFFC01D6C /* DMA Channel 13 Peripheral Map Register */
590#define DMA13_CURR_X_COUNT 0xFFC01D70 /* DMA Channel 13 Current X Count Register */
591#define DMA13_CURR_Y_COUNT 0xFFC01D78 /* DMA Channel 13 Current Y Count Register */
592
593#define DMA14_NEXT_DESC_PTR 0xFFC01D80 /* DMA Channel 14 Next Descriptor Pointer Register */
594#define DMA14_START_ADDR 0xFFC01D84 /* DMA Channel 14 Start Address Register */
595#define DMA14_CONFIG 0xFFC01D88 /* DMA Channel 14 Configuration Register */
596#define DMA14_X_COUNT 0xFFC01D90 /* DMA Channel 14 X Count Register */
597#define DMA14_X_MODIFY 0xFFC01D94 /* DMA Channel 14 X Modify Register */
598#define DMA14_Y_COUNT 0xFFC01D98 /* DMA Channel 14 Y Count Register */
599#define DMA14_Y_MODIFY 0xFFC01D9C /* DMA Channel 14 Y Modify Register */
600#define DMA14_CURR_DESC_PTR 0xFFC01DA0 /* DMA Channel 14 Current Descriptor Pointer Register */
601#define DMA14_CURR_ADDR 0xFFC01DA4 /* DMA Channel 14 Current Address Register */
602#define DMA14_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 14 Interrupt/Status Register */
603#define DMA14_PERIPHERAL_MAP 0xFFC01DAC /* DMA Channel 14 Peripheral Map Register */
604#define DMA14_CURR_X_COUNT 0xFFC01DB0 /* DMA Channel 14 Current X Count Register */
605#define DMA14_CURR_Y_COUNT 0xFFC01DB8 /* DMA Channel 14 Current Y Count Register */
606
607#define DMA15_NEXT_DESC_PTR 0xFFC01DC0 /* DMA Channel 15 Next Descriptor Pointer Register */
608#define DMA15_START_ADDR 0xFFC01DC4 /* DMA Channel 15 Start Address Register */
609#define DMA15_CONFIG 0xFFC01DC8 /* DMA Channel 15 Configuration Register */
610#define DMA15_X_COUNT 0xFFC01DD0 /* DMA Channel 15 X Count Register */
611#define DMA15_X_MODIFY 0xFFC01DD4 /* DMA Channel 15 X Modify Register */
612#define DMA15_Y_COUNT 0xFFC01DD8 /* DMA Channel 15 Y Count Register */
613#define DMA15_Y_MODIFY 0xFFC01DDC /* DMA Channel 15 Y Modify Register */
614#define DMA15_CURR_DESC_PTR 0xFFC01DE0 /* DMA Channel 15 Current Descriptor Pointer Register */
615#define DMA15_CURR_ADDR 0xFFC01DE4 /* DMA Channel 15 Current Address Register */
616#define DMA15_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 15 Interrupt/Status Register */
617#define DMA15_PERIPHERAL_MAP 0xFFC01DEC /* DMA Channel 15 Peripheral Map Register */
618#define DMA15_CURR_X_COUNT 0xFFC01DF0 /* DMA Channel 15 Current X Count Register */
619#define DMA15_CURR_Y_COUNT 0xFFC01DF8 /* DMA Channel 15 Current Y Count Register */
620
621#define DMA16_NEXT_DESC_PTR 0xFFC01E00 /* DMA Channel 16 Next Descriptor Pointer Register */
622#define DMA16_START_ADDR 0xFFC01E04 /* DMA Channel 16 Start Address Register */
623#define DMA16_CONFIG 0xFFC01E08 /* DMA Channel 16 Configuration Register */
624#define DMA16_X_COUNT 0xFFC01E10 /* DMA Channel 16 X Count Register */
625#define DMA16_X_MODIFY 0xFFC01E14 /* DMA Channel 16 X Modify Register */
626#define DMA16_Y_COUNT 0xFFC01E18 /* DMA Channel 16 Y Count Register */
627#define DMA16_Y_MODIFY 0xFFC01E1C /* DMA Channel 16 Y Modify Register */
628#define DMA16_CURR_DESC_PTR 0xFFC01E20 /* DMA Channel 16 Current Descriptor Pointer Register */
629#define DMA16_CURR_ADDR 0xFFC01E24 /* DMA Channel 16 Current Address Register */
630#define DMA16_IRQ_STATUS 0xFFC01E28 /* DMA Channel 16 Interrupt/Status Register */
631#define DMA16_PERIPHERAL_MAP 0xFFC01E2C /* DMA Channel 16 Peripheral Map Register */
632#define DMA16_CURR_X_COUNT 0xFFC01E30 /* DMA Channel 16 Current X Count Register */
633#define DMA16_CURR_Y_COUNT 0xFFC01E38 /* DMA Channel 16 Current Y Count Register */
634
635#define DMA17_NEXT_DESC_PTR 0xFFC01E40 /* DMA Channel 17 Next Descriptor Pointer Register */
636#define DMA17_START_ADDR 0xFFC01E44 /* DMA Channel 17 Start Address Register */
637#define DMA17_CONFIG 0xFFC01E48 /* DMA Channel 17 Configuration Register */
638#define DMA17_X_COUNT 0xFFC01E50 /* DMA Channel 17 X Count Register */
639#define DMA17_X_MODIFY 0xFFC01E54 /* DMA Channel 17 X Modify Register */
640#define DMA17_Y_COUNT 0xFFC01E58 /* DMA Channel 17 Y Count Register */
641#define DMA17_Y_MODIFY 0xFFC01E5C /* DMA Channel 17 Y Modify Register */
642#define DMA17_CURR_DESC_PTR 0xFFC01E60 /* DMA Channel 17 Current Descriptor Pointer Register */
643#define DMA17_CURR_ADDR 0xFFC01E64 /* DMA Channel 17 Current Address Register */
644#define DMA17_IRQ_STATUS 0xFFC01E68 /* DMA Channel 17 Interrupt/Status Register */
645#define DMA17_PERIPHERAL_MAP 0xFFC01E6C /* DMA Channel 17 Peripheral Map Register */
646#define DMA17_CURR_X_COUNT 0xFFC01E70 /* DMA Channel 17 Current X Count Register */
647#define DMA17_CURR_Y_COUNT 0xFFC01E78 /* DMA Channel 17 Current Y Count Register */
648
649#define DMA18_NEXT_DESC_PTR 0xFFC01E80 /* DMA Channel 18 Next Descriptor Pointer Register */
650#define DMA18_START_ADDR 0xFFC01E84 /* DMA Channel 18 Start Address Register */
651#define DMA18_CONFIG 0xFFC01E88 /* DMA Channel 18 Configuration Register */
652#define DMA18_X_COUNT 0xFFC01E90 /* DMA Channel 18 X Count Register */
653#define DMA18_X_MODIFY 0xFFC01E94 /* DMA Channel 18 X Modify Register */
654#define DMA18_Y_COUNT 0xFFC01E98 /* DMA Channel 18 Y Count Register */
655#define DMA18_Y_MODIFY 0xFFC01E9C /* DMA Channel 18 Y Modify Register */
656#define DMA18_CURR_DESC_PTR 0xFFC01EA0 /* DMA Channel 18 Current Descriptor Pointer Register */
657#define DMA18_CURR_ADDR 0xFFC01EA4 /* DMA Channel 18 Current Address Register */
658#define DMA18_IRQ_STATUS 0xFFC01EA8 /* DMA Channel 18 Interrupt/Status Register */
659#define DMA18_PERIPHERAL_MAP 0xFFC01EAC /* DMA Channel 18 Peripheral Map Register */
660#define DMA18_CURR_X_COUNT 0xFFC01EB0 /* DMA Channel 18 Current X Count Register */
661#define DMA18_CURR_Y_COUNT 0xFFC01EB8 /* DMA Channel 18 Current Y Count Register */
662
663#define DMA19_NEXT_DESC_PTR 0xFFC01EC0 /* DMA Channel 19 Next Descriptor Pointer Register */
664#define DMA19_START_ADDR 0xFFC01EC4 /* DMA Channel 19 Start Address Register */
665#define DMA19_CONFIG 0xFFC01EC8 /* DMA Channel 19 Configuration Register */
666#define DMA19_X_COUNT 0xFFC01ED0 /* DMA Channel 19 X Count Register */
667#define DMA19_X_MODIFY 0xFFC01ED4 /* DMA Channel 19 X Modify Register */
668#define DMA19_Y_COUNT 0xFFC01ED8 /* DMA Channel 19 Y Count Register */
669#define DMA19_Y_MODIFY 0xFFC01EDC /* DMA Channel 19 Y Modify Register */
670#define DMA19_CURR_DESC_PTR 0xFFC01EE0 /* DMA Channel 19 Current Descriptor Pointer Register */
671#define DMA19_CURR_ADDR 0xFFC01EE4 /* DMA Channel 19 Current Address Register */
672#define DMA19_IRQ_STATUS 0xFFC01EE8 /* DMA Channel 19 Interrupt/Status Register */
673#define DMA19_PERIPHERAL_MAP 0xFFC01EEC /* DMA Channel 19 Peripheral Map Register */
674#define DMA19_CURR_X_COUNT 0xFFC01EF0 /* DMA Channel 19 Current X Count Register */
675#define DMA19_CURR_Y_COUNT 0xFFC01EF8 /* DMA Channel 19 Current Y Count Register */
676
677#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00 /* MemDMA1 Stream 0 Destination Next Descriptor Pointer Register */
678#define MDMA1_D0_START_ADDR 0xFFC01F04 /* MemDMA1 Stream 0 Destination Start Address Register */
679#define MDMA1_D0_CONFIG 0xFFC01F08 /* MemDMA1 Stream 0 Destination Configuration Register */
680#define MDMA1_D0_X_COUNT 0xFFC01F10 /* MemDMA1 Stream 0 Destination X Count Register */
681#define MDMA1_D0_X_MODIFY 0xFFC01F14 /* MemDMA1 Stream 0 Destination X Modify Register */
682#define MDMA1_D0_Y_COUNT 0xFFC01F18 /* MemDMA1 Stream 0 Destination Y Count Register */
683#define MDMA1_D0_Y_MODIFY 0xFFC01F1C /* MemDMA1 Stream 0 Destination Y Modify Register */
684#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20 /* MemDMA1 Stream 0 Destination Current Descriptor Pointer Register */
685#define MDMA1_D0_CURR_ADDR 0xFFC01F24 /* MemDMA1 Stream 0 Destination Current Address Register */
686#define MDMA1_D0_IRQ_STATUS 0xFFC01F28 /* MemDMA1 Stream 0 Destination Interrupt/Status Register */
687#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C /* MemDMA1 Stream 0 Destination Peripheral Map Register */
688#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30 /* MemDMA1 Stream 0 Destination Current X Count Register */
689#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38 /* MemDMA1 Stream 0 Destination Current Y Count Register */
690
691#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40 /* MemDMA1 Stream 0 Source Next Descriptor Pointer Register */
692#define MDMA1_S0_START_ADDR 0xFFC01F44 /* MemDMA1 Stream 0 Source Start Address Register */
693#define MDMA1_S0_CONFIG 0xFFC01F48 /* MemDMA1 Stream 0 Source Configuration Register */
694#define MDMA1_S0_X_COUNT 0xFFC01F50 /* MemDMA1 Stream 0 Source X Count Register */
695#define MDMA1_S0_X_MODIFY 0xFFC01F54 /* MemDMA1 Stream 0 Source X Modify Register */
696#define MDMA1_S0_Y_COUNT 0xFFC01F58 /* MemDMA1 Stream 0 Source Y Count Register */
697#define MDMA1_S0_Y_MODIFY 0xFFC01F5C /* MemDMA1 Stream 0 Source Y Modify Register */
698#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60 /* MemDMA1 Stream 0 Source Current Descriptor Pointer Register */
699#define MDMA1_S0_CURR_ADDR 0xFFC01F64 /* MemDMA1 Stream 0 Source Current Address Register */
700#define MDMA1_S0_IRQ_STATUS 0xFFC01F68 /* MemDMA1 Stream 0 Source Interrupt/Status Register */
701#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C /* MemDMA1 Stream 0 Source Peripheral Map Register */
702#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70 /* MemDMA1 Stream 0 Source Current X Count Register */
703#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78 /* MemDMA1 Stream 0 Source Current Y Count Register */
704
705#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80 /* MemDMA1 Stream 1 Destination Next Descriptor Pointer Register */
706#define MDMA1_D1_START_ADDR 0xFFC01F84 /* MemDMA1 Stream 1 Destination Start Address Register */
707#define MDMA1_D1_CONFIG 0xFFC01F88 /* MemDMA1 Stream 1 Destination Configuration Register */
708#define MDMA1_D1_X_COUNT 0xFFC01F90 /* MemDMA1 Stream 1 Destination X Count Register */
709#define MDMA1_D1_X_MODIFY 0xFFC01F94 /* MemDMA1 Stream 1 Destination X Modify Register */
710#define MDMA1_D1_Y_COUNT 0xFFC01F98 /* MemDMA1 Stream 1 Destination Y Count Register */
711#define MDMA1_D1_Y_MODIFY 0xFFC01F9C /* MemDMA1 Stream 1 Destination Y Modify Register */
712#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0 /* MemDMA1 Stream 1 Destination Current Descriptor Pointer Register */
713#define MDMA1_D1_CURR_ADDR 0xFFC01FA4 /* MemDMA1 Stream 1 Destination Current Address Register */
714#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8 /* MemDMA1 Stream 1 Destination Interrupt/Status Register */
715#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC /* MemDMA1 Stream 1 Destination Peripheral Map Register */
716#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0 /* MemDMA1 Stream 1 Destination Current X Count Register */
717#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8 /* MemDMA1 Stream 1 Destination Current Y Count Register */
718
719#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0 /* MemDMA1 Stream 1 Source Next Descriptor Pointer Register */
720#define MDMA1_S1_START_ADDR 0xFFC01FC4 /* MemDMA1 Stream 1 Source Start Address Register */
721#define MDMA1_S1_CONFIG 0xFFC01FC8 /* MemDMA1 Stream 1 Source Configuration Register */
722#define MDMA1_S1_X_COUNT 0xFFC01FD0 /* MemDMA1 Stream 1 Source X Count Register */
723#define MDMA1_S1_X_MODIFY 0xFFC01FD4 /* MemDMA1 Stream 1 Source X Modify Register */
724#define MDMA1_S1_Y_COUNT 0xFFC01FD8 /* MemDMA1 Stream 1 Source Y Count Register */
725#define MDMA1_S1_Y_MODIFY 0xFFC01FDC /* MemDMA1 Stream 1 Source Y Modify Register */
726#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0 /* MemDMA1 Stream 1 Source Current Descriptor Pointer Register */
727#define MDMA1_S1_CURR_ADDR 0xFFC01FE4 /* MemDMA1 Stream 1 Source Current Address Register */
728#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8 /* MemDMA1 Stream 1 Source Interrupt/Status Register */
729#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC /* MemDMA1 Stream 1 Source Peripheral Map Register */
730#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0 /* MemDMA1 Stream 1 Source Current X Count Register */
731#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8 /* MemDMA1 Stream 1 Source Current Y Count Register */
732
733
734/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
735#define UART1_THR 0xFFC02000 /* Transmit Holding register */
736#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
737#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
738#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
739#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
740#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
741#define UART1_LCR 0xFFC0200C /* Line Control Register */
742#define UART1_MCR 0xFFC02010 /* Modem Control Register */
743#define UART1_LSR 0xFFC02014 /* Line Status Register */
744#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
745#define UART1_GCTL 0xFFC02024 /* Global Control Register */
746
747
748/* UART2 Controller (0xFFC02100 - 0xFFC021FF) */
749#define UART2_THR 0xFFC02100 /* Transmit Holding register */
750#define UART2_RBR 0xFFC02100 /* Receive Buffer register */
751#define UART2_DLL 0xFFC02100 /* Divisor Latch (Low-Byte) */
752#define UART2_IER 0xFFC02104 /* Interrupt Enable Register */
753#define UART2_DLH 0xFFC02104 /* Divisor Latch (High-Byte) */
754#define UART2_IIR 0xFFC02108 /* Interrupt Identification Register */
755#define UART2_LCR 0xFFC0210C /* Line Control Register */
756#define UART2_MCR 0xFFC02110 /* Modem Control Register */
757#define UART2_LSR 0xFFC02114 /* Line Status Register */
758#define UART2_SCR 0xFFC0211C /* SCR Scratch Register */
759#define UART2_GCTL 0xFFC02124 /* Global Control Register */
760
761
762/* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF) */
763#define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */
764#define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */
765#define TWI1_SLAVE_CTL 0xFFC02208 /* Slave Mode Control Register */
766#define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */
767#define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */
768#define TWI1_MASTER_CTL 0xFFC02214 /* Master Mode Control Register */
769#define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */
770#define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */
771#define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */
772#define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */
773#define TWI1_FIFO_CTL 0xFFC02228 /* FIFO Control Register */
774#define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */
775#define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */
776#define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */
777#define TWI1_RCV_DATA8 0xFFC02288 /* FIFO Receive Data Single Byte Register */
778#define TWI1_RCV_DATA16 0xFFC0228C /* FIFO Receive Data Double Byte Register */
779#define TWI1_REGBASE TWI1_CLKDIV
780
781
782/* the following are for backwards compatibility */
783#define TWI1_PRESCALE TWI1_CONTROL
784#define TWI1_INT_SRC TWI1_INT_STAT
785#define TWI1_INT_ENABLE TWI1_INT_MASK
786
787
788/* SPI1 Controller (0xFFC02300 - 0xFFC023FF) */
789#define SPI1_CTL 0xFFC02300 /* SPI1 Control Register */
790#define SPI1_FLG 0xFFC02304 /* SPI1 Flag register */
791#define SPI1_STAT 0xFFC02308 /* SPI1 Status register */
792#define SPI1_TDBR 0xFFC0230C /* SPI1 Transmit Data Buffer Register */
793#define SPI1_RDBR 0xFFC02310 /* SPI1 Receive Data Buffer Register */
794#define SPI1_BAUD 0xFFC02314 /* SPI1 Baud rate Register */
795#define SPI1_SHADOW 0xFFC02318 /* SPI1_RDBR Shadow Register */
796#define SPI1_REGBASE SPI1_CTL
797
798/* SPI2 Controller (0xFFC02400 - 0xFFC024FF) */
799#define SPI2_CTL 0xFFC02400 /* SPI2 Control Register */
800#define SPI2_FLG 0xFFC02404 /* SPI2 Flag register */
801#define SPI2_STAT 0xFFC02408 /* SPI2 Status register */
802#define SPI2_TDBR 0xFFC0240C /* SPI2 Transmit Data Buffer Register */
803#define SPI2_RDBR 0xFFC02410 /* SPI2 Receive Data Buffer Register */
804#define SPI2_BAUD 0xFFC02414 /* SPI2 Baud rate Register */
805#define SPI2_SHADOW 0xFFC02418 /* SPI2_RDBR Shadow Register */
806#define SPI2_REGBASE SPI2_CTL
807
808/* SPORT2 Controller (0xFFC02500 - 0xFFC025FF) */
809#define SPORT2_TCR1 0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */
810#define SPORT2_TCR2 0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */
811#define SPORT2_TCLKDIV 0xFFC02508 /* SPORT2 Transmit Clock Divider */
812#define SPORT2_TFSDIV 0xFFC0250C /* SPORT2 Transmit Frame Sync Divider */
813#define SPORT2_TX 0xFFC02510 /* SPORT2 TX Data Register */
814#define SPORT2_RX 0xFFC02518 /* SPORT2 RX Data Register */
815#define SPORT2_RCR1 0xFFC02520 /* SPORT2 Transmit Configuration 1 Register */
816#define SPORT2_RCR2 0xFFC02524 /* SPORT2 Transmit Configuration 2 Register */
817#define SPORT2_RCLKDIV 0xFFC02528 /* SPORT2 Receive Clock Divider */
818#define SPORT2_RFSDIV 0xFFC0252C /* SPORT2 Receive Frame Sync Divider */
819#define SPORT2_STAT 0xFFC02530 /* SPORT2 Status Register */
820#define SPORT2_CHNL 0xFFC02534 /* SPORT2 Current Channel Register */
821#define SPORT2_MCMC1 0xFFC02538 /* SPORT2 Multi-Channel Configuration Register 1 */
822#define SPORT2_MCMC2 0xFFC0253C /* SPORT2 Multi-Channel Configuration Register 2 */
823#define SPORT2_MTCS0 0xFFC02540 /* SPORT2 Multi-Channel Transmit Select Register 0 */
824#define SPORT2_MTCS1 0xFFC02544 /* SPORT2 Multi-Channel Transmit Select Register 1 */
825#define SPORT2_MTCS2 0xFFC02548 /* SPORT2 Multi-Channel Transmit Select Register 2 */
826#define SPORT2_MTCS3 0xFFC0254C /* SPORT2 Multi-Channel Transmit Select Register 3 */
827#define SPORT2_MRCS0 0xFFC02550 /* SPORT2 Multi-Channel Receive Select Register 0 */
828#define SPORT2_MRCS1 0xFFC02554 /* SPORT2 Multi-Channel Receive Select Register 1 */
829#define SPORT2_MRCS2 0xFFC02558 /* SPORT2 Multi-Channel Receive Select Register 2 */
830#define SPORT2_MRCS3 0xFFC0255C /* SPORT2 Multi-Channel Receive Select Register 3 */
831
832
833/* SPORT3 Controller (0xFFC02600 - 0xFFC026FF) */
834#define SPORT3_TCR1 0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */
835#define SPORT3_TCR2 0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */
836#define SPORT3_TCLKDIV 0xFFC02608 /* SPORT3 Transmit Clock Divider */
837#define SPORT3_TFSDIV 0xFFC0260C /* SPORT3 Transmit Frame Sync Divider */
838#define SPORT3_TX 0xFFC02610 /* SPORT3 TX Data Register */
839#define SPORT3_RX 0xFFC02618 /* SPORT3 RX Data Register */
840#define SPORT3_RCR1 0xFFC02620 /* SPORT3 Transmit Configuration 1 Register */
841#define SPORT3_RCR2 0xFFC02624 /* SPORT3 Transmit Configuration 2 Register */
842#define SPORT3_RCLKDIV 0xFFC02628 /* SPORT3 Receive Clock Divider */
843#define SPORT3_RFSDIV 0xFFC0262C /* SPORT3 Receive Frame Sync Divider */
844#define SPORT3_STAT 0xFFC02630 /* SPORT3 Status Register */
845#define SPORT3_CHNL 0xFFC02634 /* SPORT3 Current Channel Register */
846#define SPORT3_MCMC1 0xFFC02638 /* SPORT3 Multi-Channel Configuration Register 1 */
847#define SPORT3_MCMC2 0xFFC0263C /* SPORT3 Multi-Channel Configuration Register 2 */
848#define SPORT3_MTCS0 0xFFC02640 /* SPORT3 Multi-Channel Transmit Select Register 0 */
849#define SPORT3_MTCS1 0xFFC02644 /* SPORT3 Multi-Channel Transmit Select Register 1 */
850#define SPORT3_MTCS2 0xFFC02648 /* SPORT3 Multi-Channel Transmit Select Register 2 */
851#define SPORT3_MTCS3 0xFFC0264C /* SPORT3 Multi-Channel Transmit Select Register 3 */
852#define SPORT3_MRCS0 0xFFC02650 /* SPORT3 Multi-Channel Receive Select Register 0 */
853#define SPORT3_MRCS1 0xFFC02654 /* SPORT3 Multi-Channel Receive Select Register 1 */
854#define SPORT3_MRCS2 0xFFC02658 /* SPORT3 Multi-Channel Receive Select Register 2 */
855#define SPORT3_MRCS3 0xFFC0265C /* SPORT3 Multi-Channel Receive Select Register 3 */
856
857 11
858/* Media Transceiver (MXVR) (0xFFC02700 - 0xFFC028FF) */ 12/* Media Transceiver (MXVR) (0xFFC02700 - 0xFFC028FF) */
859 13
@@ -995,1249 +149,4 @@
995#define MXVR_BLOCK_CNT 0xFFC028C0 /* MXVR Block Counter */ 149#define MXVR_BLOCK_CNT 0xFFC028C0 /* MXVR Block Counter */
996#define MXVR_PLL_CTL_2 0xFFC028C4 /* MXVR Phase Lock Loop Control Register 2 */ 150#define MXVR_PLL_CTL_2 0xFFC028C4 /* MXVR Phase Lock Loop Control Register 2 */
997 151
998
999/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
1000/* For Mailboxes 0-15 */
1001#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */
1002#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */
1003#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */
1004#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */
1005#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */
1006#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */
1007#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */
1008#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */
1009#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */
1010#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */
1011#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */
1012#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */
1013#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmission reg 1 */
1014
1015/* For Mailboxes 16-31 */
1016#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */
1017#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */
1018#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */
1019#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */
1020#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */
1021#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */
1022#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */
1023#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */
1024#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */
1025#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */
1026#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */
1027#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */
1028#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmission reg 2 */
1029
1030#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */
1031#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */
1032
1033#define CAN_DEBUG 0xFFC02A88 /* Debug Register */
1034/* the following is for backwards compatibility */
1035#define CAN_CNF CAN_DEBUG
1036
1037#define CAN_STATUS 0xFFC02A8C /* Global Status Register */
1038#define CAN_CEC 0xFFC02A90 /* Error Counter Register */
1039#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */
1040#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */
1041#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */
1042#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */
1043#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */
1044#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
1045#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
1046#define CAN_ESR 0xFFC02AB4 /* Error Status Register */
1047#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */
1048#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Reload/Capture Register */
1049#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */
1050
1051/* Mailbox Acceptance Masks */
1052#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */
1053#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */
1054#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */
1055#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */
1056#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */
1057#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */
1058#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */
1059#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */
1060#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */
1061#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */
1062#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */
1063#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */
1064#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */
1065#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */
1066#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */
1067#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */
1068#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */
1069#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */
1070#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */
1071#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */
1072#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */
1073#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */
1074#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */
1075#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */
1076#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */
1077#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */
1078#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */
1079#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */
1080#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */
1081#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */
1082#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */
1083#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */
1084
1085#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */
1086#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */
1087#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */
1088#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */
1089#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */
1090#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */
1091#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */
1092#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */
1093#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */
1094#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */
1095#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */
1096#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */
1097#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */
1098#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */
1099#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */
1100#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */
1101#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */
1102#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */
1103#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */
1104#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */
1105#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */
1106#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */
1107#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */
1108#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */
1109#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */
1110#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */
1111#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */
1112#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */
1113#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */
1114#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */
1115#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */
1116#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */
1117
1118/* CAN Acceptance Mask Macros */
1119#define CAN_AM_L(x) (CAN_AM00L+((x)*0x8))
1120#define CAN_AM_H(x) (CAN_AM00H+((x)*0x8))
1121
1122/* Mailbox Registers */
1123#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */
1124#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */
1125#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */
1126#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */
1127#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */
1128#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */
1129#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */
1130#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */
1131
1132#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */
1133#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */
1134#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */
1135#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */
1136#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */
1137#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */
1138#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */
1139#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */
1140
1141#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */
1142#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */
1143#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */
1144#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */
1145#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */
1146#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */
1147#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */
1148#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */
1149
1150#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */
1151#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */
1152#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */
1153#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */
1154#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */
1155#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */
1156#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */
1157#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */
1158
1159#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */
1160#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */
1161#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */
1162#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */
1163#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */
1164#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */
1165#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */
1166#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */
1167
1168#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */
1169#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */
1170#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */
1171#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */
1172#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */
1173#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */
1174#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */
1175#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */
1176
1177#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */
1178#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */
1179#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */
1180#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */
1181#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */
1182#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */
1183#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */
1184#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */
1185
1186#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */
1187#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */
1188#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */
1189#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */
1190#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */
1191#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */
1192#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */
1193#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */
1194
1195#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */
1196#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */
1197#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */
1198#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */
1199#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */
1200#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */
1201#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */
1202#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */
1203
1204#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */
1205#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */
1206#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */
1207#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */
1208#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */
1209#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */
1210#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */
1211#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */
1212
1213#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */
1214#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */
1215#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */
1216#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */
1217#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */
1218#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */
1219#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */
1220#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */
1221
1222#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */
1223#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */
1224#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */
1225#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */
1226#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */
1227#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */
1228#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */
1229#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */
1230
1231#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */
1232#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */
1233#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */
1234#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */
1235#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */
1236#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */
1237#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */
1238#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */
1239
1240#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */
1241#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */
1242#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */
1243#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */
1244#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */
1245#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */
1246#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */
1247#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */
1248
1249#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */
1250#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */
1251#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */
1252#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */
1253#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */
1254#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */
1255#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */
1256#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */
1257
1258#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */
1259#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */
1260#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */
1261#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */
1262#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */
1263#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */
1264#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */
1265#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */
1266
1267#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */
1268#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */
1269#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */
1270#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */
1271#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */
1272#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */
1273#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */
1274#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */
1275
1276#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */
1277#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */
1278#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */
1279#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */
1280#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */
1281#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */
1282#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */
1283#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */
1284
1285#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */
1286#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */
1287#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */
1288#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */
1289#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */
1290#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */
1291#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */
1292#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */
1293
1294#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */
1295#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */
1296#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */
1297#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */
1298#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */
1299#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */
1300#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */
1301#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */
1302
1303#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */
1304#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */
1305#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */
1306#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */
1307#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */
1308#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */
1309#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */
1310#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */
1311
1312#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */
1313#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */
1314#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */
1315#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */
1316#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */
1317#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */
1318#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */
1319#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */
1320
1321#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */
1322#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */
1323#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */
1324#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */
1325#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */
1326#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */
1327#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */
1328#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */
1329
1330#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */
1331#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */
1332#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */
1333#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */
1334#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */
1335#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */
1336#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */
1337#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */
1338
1339#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */
1340#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */
1341#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */
1342#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */
1343#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */
1344#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */
1345#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */
1346#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */
1347
1348#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */
1349#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */
1350#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */
1351#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */
1352#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */
1353#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */
1354#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */
1355#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */
1356
1357#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */
1358#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */
1359#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */
1360#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */
1361#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */
1362#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */
1363#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */
1364#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */
1365
1366#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */
1367#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */
1368#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */
1369#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */
1370#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */
1371#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */
1372#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */
1373#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */
1374
1375#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */
1376#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */
1377#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */
1378#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */
1379#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */
1380#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */
1381#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */
1382#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */
1383
1384#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */
1385#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */
1386#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */
1387#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */
1388#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */
1389#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */
1390#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */
1391#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */
1392
1393#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */
1394#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */
1395#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */
1396#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */
1397#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */
1398#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */
1399#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */
1400#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */
1401
1402#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */
1403#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */
1404#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */
1405#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */
1406#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */
1407#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */
1408#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */
1409#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */
1410
1411/* CAN Mailbox Area Macros */
1412#define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20))
1413#define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20))
1414#define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20))
1415#define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20))
1416#define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20))
1417#define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20))
1418#define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20))
1419#define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20))
1420
1421
1422/*********************************************************************************** */
1423/* System MMR Register Bits and Macros */
1424/******************************************************************************* */
1425
1426/* SWRST Mask */
1427#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
1428#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
1429#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
1430#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
1431#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
1432
1433/* SYSCR Masks */
1434#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
1435#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
1436
1437
1438/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
1439
1440/* Peripheral Masks For SIC0_ISR, SIC0_IWR, SIC0_IMASK */
1441#define PLL_WAKEUP_IRQ 0x00000001 /* PLL Wakeup Interrupt Request */
1442#define DMAC0_ERR_IRQ 0x00000002 /* DMA Controller 0 Error Interrupt Request */
1443#define PPI_ERR_IRQ 0x00000004 /* PPI Error Interrupt Request */
1444#define SPORT0_ERR_IRQ 0x00000008 /* SPORT0 Error Interrupt Request */
1445#define SPORT1_ERR_IRQ 0x00000010 /* SPORT1 Error Interrupt Request */
1446#define SPI0_ERR_IRQ 0x00000020 /* SPI0 Error Interrupt Request */
1447#define UART0_ERR_IRQ 0x00000040 /* UART0 Error Interrupt Request */
1448#define RTC_IRQ 0x00000080 /* Real-Time Clock Interrupt Request */
1449#define DMA0_IRQ 0x00000100 /* DMA Channel 0 (PPI) Interrupt Request */
1450#define DMA1_IRQ 0x00000200 /* DMA Channel 1 (SPORT0 RX) Interrupt Request */
1451#define DMA2_IRQ 0x00000400 /* DMA Channel 2 (SPORT0 TX) Interrupt Request */
1452#define DMA3_IRQ 0x00000800 /* DMA Channel 3 (SPORT1 RX) Interrupt Request */
1453#define DMA4_IRQ 0x00001000 /* DMA Channel 4 (SPORT1 TX) Interrupt Request */
1454#define DMA5_IRQ 0x00002000 /* DMA Channel 5 (SPI) Interrupt Request */
1455#define DMA6_IRQ 0x00004000 /* DMA Channel 6 (UART RX) Interrupt Request */
1456#define DMA7_IRQ 0x00008000 /* DMA Channel 7 (UART TX) Interrupt Request */
1457#define TIMER0_IRQ 0x00010000 /* Timer 0 Interrupt Request */
1458#define TIMER1_IRQ 0x00020000 /* Timer 1 Interrupt Request */
1459#define TIMER2_IRQ 0x00040000 /* Timer 2 Interrupt Request */
1460#define PFA_IRQ 0x00080000 /* Programmable Flag Interrupt Request A */
1461#define PFB_IRQ 0x00100000 /* Programmable Flag Interrupt Request B */
1462#define MDMA0_0_IRQ 0x00200000 /* MemDMA0 Stream 0 Interrupt Request */
1463#define MDMA0_1_IRQ 0x00400000 /* MemDMA0 Stream 1 Interrupt Request */
1464#define WDOG_IRQ 0x00800000 /* Software Watchdog Timer Interrupt Request */
1465#define DMAC1_ERR_IRQ 0x01000000 /* DMA Controller 1 Error Interrupt Request */
1466#define SPORT2_ERR_IRQ 0x02000000 /* SPORT2 Error Interrupt Request */
1467#define SPORT3_ERR_IRQ 0x04000000 /* SPORT3 Error Interrupt Request */
1468#define MXVR_SD_IRQ 0x08000000 /* MXVR Synchronous Data Interrupt Request */
1469#define SPI1_ERR_IRQ 0x10000000 /* SPI1 Error Interrupt Request */
1470#define SPI2_ERR_IRQ 0x20000000 /* SPI2 Error Interrupt Request */
1471#define UART1_ERR_IRQ 0x40000000 /* UART1 Error Interrupt Request */
1472#define UART2_ERR_IRQ 0x80000000 /* UART2 Error Interrupt Request */
1473
1474/* the following are for backwards compatibility */
1475#define DMA0_ERR_IRQ DMAC0_ERR_IRQ
1476#define DMA1_ERR_IRQ DMAC1_ERR_IRQ
1477
1478
1479/* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1 */
1480#define CAN_ERR_IRQ 0x00000001 /* CAN Error Interrupt Request */
1481#define DMA8_IRQ 0x00000002 /* DMA Channel 8 (SPORT2 RX) Interrupt Request */
1482#define DMA9_IRQ 0x00000004 /* DMA Channel 9 (SPORT2 TX) Interrupt Request */
1483#define DMA10_IRQ 0x00000008 /* DMA Channel 10 (SPORT3 RX) Interrupt Request */
1484#define DMA11_IRQ 0x00000010 /* DMA Channel 11 (SPORT3 TX) Interrupt Request */
1485#define DMA12_IRQ 0x00000020 /* DMA Channel 12 Interrupt Request */
1486#define DMA13_IRQ 0x00000040 /* DMA Channel 13 Interrupt Request */
1487#define DMA14_IRQ 0x00000080 /* DMA Channel 14 (SPI1) Interrupt Request */
1488#define DMA15_IRQ 0x00000100 /* DMA Channel 15 (SPI2) Interrupt Request */
1489#define DMA16_IRQ 0x00000200 /* DMA Channel 16 (UART1 RX) Interrupt Request */
1490#define DMA17_IRQ 0x00000400 /* DMA Channel 17 (UART1 TX) Interrupt Request */
1491#define DMA18_IRQ 0x00000800 /* DMA Channel 18 (UART2 RX) Interrupt Request */
1492#define DMA19_IRQ 0x00001000 /* DMA Channel 19 (UART2 TX) Interrupt Request */
1493#define TWI0_IRQ 0x00002000 /* TWI0 Interrupt Request */
1494#define TWI1_IRQ 0x00004000 /* TWI1 Interrupt Request */
1495#define CAN_RX_IRQ 0x00008000 /* CAN Receive Interrupt Request */
1496#define CAN_TX_IRQ 0x00010000 /* CAN Transmit Interrupt Request */
1497#define MDMA1_0_IRQ 0x00020000 /* MemDMA1 Stream 0 Interrupt Request */
1498#define MDMA1_1_IRQ 0x00040000 /* MemDMA1 Stream 1 Interrupt Request */
1499#define MXVR_STAT_IRQ 0x00080000 /* MXVR Status Interrupt Request */
1500#define MXVR_CM_IRQ 0x00100000 /* MXVR Control Message Interrupt Request */
1501#define MXVR_AP_IRQ 0x00200000 /* MXVR Asynchronous Packet Interrupt */
1502
1503/* the following are for backwards compatibility */
1504#define MDMA0_IRQ MDMA1_0_IRQ
1505#define MDMA1_IRQ MDMA1_1_IRQ
1506
1507#ifdef _MISRA_RULES
1508#define _MF15 0xFu
1509#define _MF7 7u
1510#else
1511#define _MF15 0xF
1512#define _MF7 7
1513#endif /* _MISRA_RULES */
1514
1515/* SIC_IMASKx Masks */
1516#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
1517#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
1518#ifdef _MISRA_RULES
1519#define SIC_MASK(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
1520#define SIC_UNMASK(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Unmask Peripheral #x interrupt */
1521#else
1522#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
1523#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
1524#endif /* _MISRA_RULES */
1525
1526/* SIC_IWRx Masks */
1527#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
1528#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
1529#ifdef _MISRA_RULES
1530#define IWR_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
1531#define IWR_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Wakeup Disable Peripheral #x */
1532#else
1533#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
1534#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
1535#endif /* _MISRA_RULES */
1536
1537
1538/* ***************************** UART CONTROLLER MASKS ********************** */
1539/* UARTx_LCR Register */
1540#ifdef _MISRA_RULES
1541#define WLS(x) (((x)-5u) & 0x03u) /* Word Length Select */
1542#else
1543#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
1544#endif /* _MISRA_RULES */
1545#define STB 0x04 /* Stop Bits */
1546#define PEN 0x08 /* Parity Enable */
1547#define EPS 0x10 /* Even Parity Select */
1548#define STP 0x20 /* Stick Parity */
1549#define SB 0x40 /* Set Break */
1550#define DLAB 0x80 /* Divisor Latch Access */
1551
1552#define DLAB_P 0x07
1553#define SB_P 0x06
1554#define STP_P 0x05
1555#define EPS_P 0x04
1556#define PEN_P 0x03
1557#define STB_P 0x02
1558#define WLS_P1 0x01
1559#define WLS_P0 0x00
1560
1561/* UARTx_MCR Register */
1562#define LOOP_ENA 0x10 /* Loopback Mode Enable */
1563#define LOOP_ENA_P 0x04
1564/* Deprecated UARTx_MCR Mask */
1565
1566/* UARTx_LSR Register */
1567#define DR 0x01 /* Data Ready */
1568#define OE 0x02 /* Overrun Error */
1569#define PE 0x04 /* Parity Error */
1570#define FE 0x08 /* Framing Error */
1571#define BI 0x10 /* Break Interrupt */
1572#define THRE 0x20 /* THR Empty */
1573#define TEMT 0x40 /* TSR and UART_THR Empty */
1574
1575#define TEMP_P 0x06
1576#define THRE_P 0x05
1577#define BI_P 0x04
1578#define FE_P 0x03
1579#define PE_P 0x02
1580#define OE_P 0x01
1581#define DR_P 0x00
1582
1583/* UARTx_IER Register */
1584#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
1585#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
1586#define ELSI 0x04 /* Enable RX Status Interrupt */
1587
1588#define ELSI_P 0x02
1589#define ETBEI_P 0x01
1590#define ERBFI_P 0x00
1591
1592/* UARTx_IIR Register */
1593#define NINT 0x01
1594#define STATUS_P1 0x02
1595#define STATUS_P0 0x01
1596#define NINT_P 0x00
1597
1598/* UARTx_GCTL Register */
1599#define UCEN 0x01 /* Enable UARTx Clocks */
1600#define IREN 0x02 /* Enable IrDA Mode */
1601#define TPOLC 0x04 /* IrDA TX Polarity Change */
1602#define RPOLC 0x08 /* IrDA RX Polarity Change */
1603#define FPE 0x10 /* Force Parity Error On Transmit */
1604#define FFE 0x20 /* Force Framing Error On Transmit */
1605
1606#define FFE_P 0x05
1607#define FPE_P 0x04
1608#define RPOLC_P 0x03
1609#define TPOLC_P 0x02
1610#define IREN_P 0x01
1611#define UCEN_P 0x00
1612
1613
1614/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
1615/* PPI_CONTROL Masks */
1616#define PORT_EN 0x0001 /* PPI Port Enable */
1617#define PORT_DIR 0x0002 /* PPI Port Direction */
1618#define XFR_TYPE 0x000C /* PPI Transfer Type */
1619#define PORT_CFG 0x0030 /* PPI Port Configuration */
1620#define FLD_SEL 0x0040 /* PPI Active Field Select */
1621#define PACK_EN 0x0080 /* PPI Packing Mode */
1622/* previous versions of defBF539.h erroneously included DMA32 (PPI 32-bit DMA Enable) */
1623#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
1624#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
1625#define DLENGTH 0x3800 /* PPI Data Length */
1626#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */
1627#define DLEN_10 0x0800 /* Data Length = 10 Bits */
1628#define DLEN_11 0x1000 /* Data Length = 11 Bits */
1629#define DLEN_12 0x1800 /* Data Length = 12 Bits */
1630#define DLEN_13 0x2000 /* Data Length = 13 Bits */
1631#define DLEN_14 0x2800 /* Data Length = 14 Bits */
1632#define DLEN_15 0x3000 /* Data Length = 15 Bits */
1633#define DLEN_16 0x3800 /* Data Length = 16 Bits */
1634#ifdef _MISRA_RULES
1635#define DLEN(x) ((((x)-9u) & 0x07u) << 11) /* PPI Data Length (only works for x=10-->x=16) */
1636#else
1637#define DLEN(x) ((((x)-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
1638#endif /* _MISRA_RULES */
1639#define POL 0xC000 /* PPI Signal Polarities */
1640#define POLC 0x4000 /* PPI Clock Polarity */
1641#define POLS 0x8000 /* PPI Frame Sync Polarity */
1642
1643
1644/* PPI_STATUS Masks */
1645#define FLD 0x0400 /* Field Indicator */
1646#define FT_ERR 0x0800 /* Frame Track Error */
1647#define OVR 0x1000 /* FIFO Overflow Error */
1648#define UNDR 0x2000 /* FIFO Underrun Error */
1649#define ERR_DET 0x4000 /* Error Detected Indicator */
1650#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
1651
1652
1653/* ********** DMA CONTROLLER MASKS ***********************/
1654
1655/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
1656
1657#define CTYPE 0x0040 /* DMA Channel Type Indicator */
1658#define CTYPE_P 0x6 /* DMA Channel Type Indicator BIT POSITION */
1659#define PCAP8 0x0080 /* DMA 8-bit Operation Indicator */
1660#define PCAP16 0x0100 /* DMA 16-bit Operation Indicator */
1661#define PCAP32 0x0200 /* DMA 32-bit Operation Indicator */
1662#define PCAPWR 0x0400 /* DMA Write Operation Indicator */
1663#define PCAPRD 0x0800 /* DMA Read Operation Indicator */
1664#define PMAP 0xF000 /* DMA Peripheral Map Field */
1665
1666/* PMAP Encodings For DMA Controller 0 */
1667#define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */
1668#define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */
1669#define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */
1670#define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */
1671#define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */
1672#define PMAP_SPI0 0x5000 /* PMAP SPI DMA */
1673#define PMAP_UART0RX 0x6000 /* PMAP UART Receive DMA */
1674#define PMAP_UART0TX 0x7000 /* PMAP UART Transmit DMA */
1675
1676/* PMAP Encodings For DMA Controller 1 */
1677#define PMAP_SPORT2RX 0x0000 /* PMAP SPORT2 Receive DMA */
1678#define PMAP_SPORT2TX 0x1000 /* PMAP SPORT2 Transmit DMA */
1679#define PMAP_SPORT3RX 0x2000 /* PMAP SPORT3 Receive DMA */
1680#define PMAP_SPORT3TX 0x3000 /* PMAP SPORT3 Transmit DMA */
1681#define PMAP_SPI1 0x6000 /* PMAP SPI1 DMA */
1682#define PMAP_SPI2 0x7000 /* PMAP SPI2 DMA */
1683#define PMAP_UART1RX 0x8000 /* PMAP UART1 Receive DMA */
1684#define PMAP_UART1TX 0x9000 /* PMAP UART1 Transmit DMA */
1685#define PMAP_UART2RX 0xA000 /* PMAP UART2 Receive DMA */
1686#define PMAP_UART2TX 0xB000 /* PMAP UART2 Transmit DMA */
1687
1688
1689/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
1690/* PWM Timer bit definitions */
1691/* TIMER_ENABLE Register */
1692#define TIMEN0 0x0001 /* Enable Timer 0 */
1693#define TIMEN1 0x0002 /* Enable Timer 1 */
1694#define TIMEN2 0x0004 /* Enable Timer 2 */
1695
1696#define TIMEN0_P 0x00
1697#define TIMEN1_P 0x01
1698#define TIMEN2_P 0x02
1699
1700/* TIMER_DISABLE Register */
1701#define TIMDIS0 0x0001 /* Disable Timer 0 */
1702#define TIMDIS1 0x0002 /* Disable Timer 1 */
1703#define TIMDIS2 0x0004 /* Disable Timer 2 */
1704
1705#define TIMDIS0_P 0x00
1706#define TIMDIS1_P 0x01
1707#define TIMDIS2_P 0x02
1708
1709/* TIMER_STATUS Register */
1710#define TIMIL0 0x0001 /* Timer 0 Interrupt */
1711#define TIMIL1 0x0002 /* Timer 1 Interrupt */
1712#define TIMIL2 0x0004 /* Timer 2 Interrupt */
1713#define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */
1714#define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */
1715#define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */
1716#define TRUN0 0x1000 /* Timer 0 Slave Enable Status */
1717#define TRUN1 0x2000 /* Timer 1 Slave Enable Status */
1718#define TRUN2 0x4000 /* Timer 2 Slave Enable Status */
1719
1720#define TIMIL0_P 0x00
1721#define TIMIL1_P 0x01
1722#define TIMIL2_P 0x02
1723#define TOVF_ERR0_P 0x04
1724#define TOVF_ERR1_P 0x05
1725#define TOVF_ERR2_P 0x06
1726#define TRUN0_P 0x0C
1727#define TRUN1_P 0x0D
1728#define TRUN2_P 0x0E
1729
1730/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
1731#define TOVL_ERR0 TOVF_ERR0
1732#define TOVL_ERR1 TOVF_ERR1
1733#define TOVL_ERR2 TOVF_ERR2
1734#define TOVL_ERR0_P TOVF_ERR0_P
1735#define TOVL_ERR1_P TOVF_ERR1_P
1736#define TOVL_ERR2_P TOVF_ERR2_P
1737
1738/* TIMERx_CONFIG Registers */
1739#define PWM_OUT 0x0001
1740#define WDTH_CAP 0x0002
1741#define EXT_CLK 0x0003
1742#define PULSE_HI 0x0004
1743#define PERIOD_CNT 0x0008
1744#define IRQ_ENA 0x0010
1745#define TIN_SEL 0x0020
1746#define OUT_DIS 0x0040
1747#define CLK_SEL 0x0080
1748#define TOGGLE_HI 0x0100
1749#define EMU_RUN 0x0200
1750#ifdef _MISRA_RULES
1751#define ERR_TYP(x) (((x) & 0x03u) << 14)
1752#else
1753#define ERR_TYP(x) (((x) & 0x03) << 14)
1754#endif /* _MISRA_RULES */
1755
1756#define TMODE_P0 0x00
1757#define TMODE_P1 0x01
1758#define PULSE_HI_P 0x02
1759#define PERIOD_CNT_P 0x03
1760#define IRQ_ENA_P 0x04
1761#define TIN_SEL_P 0x05
1762#define OUT_DIS_P 0x06
1763#define CLK_SEL_P 0x07
1764#define TOGGLE_HI_P 0x08
1765#define EMU_RUN_P 0x09
1766#define ERR_TYP_P0 0x0E
1767#define ERR_TYP_P1 0x0F
1768
1769
1770/*/ ****************** GENERAL-PURPOSE I/O ********************* */
1771/* Flag I/O (FIO_) Masks */
1772#define PF0 0x0001
1773#define PF1 0x0002
1774#define PF2 0x0004
1775#define PF3 0x0008
1776#define PF4 0x0010
1777#define PF5 0x0020
1778#define PF6 0x0040
1779#define PF7 0x0080
1780#define PF8 0x0100
1781#define PF9 0x0200
1782#define PF10 0x0400
1783#define PF11 0x0800
1784#define PF12 0x1000
1785#define PF13 0x2000
1786#define PF14 0x4000
1787#define PF15 0x8000
1788
1789/* PORT F BIT POSITIONS */
1790#define PF0_P 0x0
1791#define PF1_P 0x1
1792#define PF2_P 0x2
1793#define PF3_P 0x3
1794#define PF4_P 0x4
1795#define PF5_P 0x5
1796#define PF6_P 0x6
1797#define PF7_P 0x7
1798#define PF8_P 0x8
1799#define PF9_P 0x9
1800#define PF10_P 0xA
1801#define PF11_P 0xB
1802#define PF12_P 0xC
1803#define PF13_P 0xD
1804#define PF14_P 0xE
1805#define PF15_P 0xF
1806
1807
1808/******************* GPIO MASKS *********************/
1809/* Port C Masks */
1810#define PC0 0x0001
1811#define PC1 0x0002
1812#define PC4 0x0010
1813#define PC5 0x0020
1814#define PC6 0x0040
1815#define PC7 0x0080
1816#define PC8 0x0100
1817#define PC9 0x0200
1818/* Port C Bit Positions */
1819#define PC0_P 0x0
1820#define PC1_P 0x1
1821#define PC4_P 0x4
1822#define PC5_P 0x5
1823#define PC6_P 0x6
1824#define PC7_P 0x7
1825#define PC8_P 0x8
1826#define PC9_P 0x9
1827
1828/* Port D */
1829#define PD0 0x0001
1830#define PD1 0x0002
1831#define PD2 0x0004
1832#define PD3 0x0008
1833#define PD4 0x0010
1834#define PD5 0x0020
1835#define PD6 0x0040
1836#define PD7 0x0080
1837#define PD8 0x0100
1838#define PD9 0x0200
1839#define PD10 0x0400
1840#define PD11 0x0800
1841#define PD12 0x1000
1842#define PD13 0x2000
1843#define PD14 0x4000
1844#define PD15 0x8000
1845/* Port D Bit Positions */
1846#define PD0_P 0x0
1847#define PD1_P 0x1
1848#define PD2_P 0x2
1849#define PD3_P 0x3
1850#define PD4_P 0x4
1851#define PD5_P 0x5
1852#define PD6_P 0x6
1853#define PD7_P 0x7
1854#define PD8_P 0x8
1855#define PD9_P 0x9
1856#define PD10_P 0xA
1857#define PD11_P 0xB
1858#define PD12_P 0xC
1859#define PD13_P 0xD
1860#define PD14_P 0xE
1861#define PD15_P 0xF
1862
1863/* Port E */
1864#define PE0 0x0001
1865#define PE1 0x0002
1866#define PE2 0x0004
1867#define PE3 0x0008
1868#define PE4 0x0010
1869#define PE5 0x0020
1870#define PE6 0x0040
1871#define PE7 0x0080
1872#define PE8 0x0100
1873#define PE9 0x0200
1874#define PE10 0x0400
1875#define PE11 0x0800
1876#define PE12 0x1000
1877#define PE13 0x2000
1878#define PE14 0x4000
1879#define PE15 0x8000
1880/* Port E Bit Positions */
1881#define PE0_P 0x0
1882#define PE1_P 0x1
1883#define PE2_P 0x2
1884#define PE3_P 0x3
1885#define PE4_P 0x4
1886#define PE5_P 0x5
1887#define PE6_P 0x6
1888#define PE7_P 0x7
1889#define PE8_P 0x8
1890#define PE9_P 0x9
1891#define PE10_P 0xA
1892#define PE11_P 0xB
1893#define PE12_P 0xC
1894#define PE13_P 0xD
1895#define PE14_P 0xE
1896#define PE15_P 0xF
1897
1898/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
1899/* EBIU_AMGCTL Masks */
1900#define AMCKEN 0x0001 /* Enable CLKOUT */
1901#define AMBEN_NONE 0x0000 /* All Banks Disabled */
1902#define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */
1903#define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */
1904#define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
1905#define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
1906#define CDPRIO 0x0100 /* DMA has priority over core for external accesses */
1907
1908/* EBIU_AMGCTL Bit Positions */
1909#define AMCKEN_P 0x0000 /* Enable CLKOUT */
1910#define AMBEN_P0 0x0001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
1911#define AMBEN_P1 0x0002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
1912#define AMBEN_P2 0x0003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
1913
1914/* EBIU_AMBCTL0 Masks */
1915#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
1916#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
1917#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
1918#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
1919#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
1920#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
1921#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
1922#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
1923#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
1924#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
1925#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
1926#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
1927#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
1928#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
1929#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
1930#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
1931#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
1932#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
1933#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
1934#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
1935#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
1936#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
1937#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
1938#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
1939#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
1940#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
1941#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
1942#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
1943#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
1944#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
1945#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
1946#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
1947#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
1948#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
1949#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
1950#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
1951#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
1952#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
1953#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
1954#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
1955#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
1956#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
1957#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
1958#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
1959#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
1960#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
1961#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
1962#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
1963#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
1964#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
1965#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1966#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1967#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1968#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1969#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1970#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1971#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1972#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1973#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
1974#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
1975#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
1976#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
1977#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
1978#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
1979#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
1980#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
1981#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
1982#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
1983#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
1984#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
1985#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
1986#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
1987#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
1988#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
1989#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
1990#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
1991#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
1992#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
1993#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
1994#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
1995#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
1996#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
1997#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
1998#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
1999#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
2000#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
2001#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
2002#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
2003
2004/* EBIU_AMBCTL1 Masks */
2005#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
2006#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
2007#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
2008#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
2009#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
2010#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
2011#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
2012#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
2013#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
2014#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
2015#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
2016#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
2017#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
2018#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
2019#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
2020#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
2021#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
2022#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
2023#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
2024#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
2025#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
2026#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
2027#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
2028#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
2029#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
2030#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
2031#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
2032#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
2033#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
2034#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
2035#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
2036#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
2037#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
2038#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
2039#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
2040#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
2041#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
2042#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
2043#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
2044#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
2045#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
2046#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
2047#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
2048#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
2049#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
2050#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
2051#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
2052#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
2053#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
2054#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
2055#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
2056#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
2057#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
2058#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
2059#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
2060#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
2061#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
2062#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
2063#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
2064#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
2065#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
2066#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
2067#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
2068#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
2069#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
2070#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
2071#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
2072#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
2073#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
2074#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
2075#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
2076#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
2077#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
2078#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
2079#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
2080#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
2081#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
2082#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
2083#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
2084#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
2085#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
2086#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
2087#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
2088#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
2089#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
2090#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
2091#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
2092#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
2093
2094/* ********************** SDRAM CONTROLLER MASKS *************************** */
2095/* EBIU_SDGCTL Masks */
2096#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
2097#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
2098#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
2099#define PFE 0x00000010 /* Enable SDRAM prefetch */
2100#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
2101#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
2102#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
2103#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
2104#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
2105#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
2106#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
2107#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
2108#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
2109#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
2110#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
2111#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
2112#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
2113#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
2114#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
2115#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
2116#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
2117#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
2118#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
2119#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
2120#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
2121#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
2122#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
2123#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
2124#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
2125#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
2126#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
2127#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
2128#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
2129#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
2130#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
2131#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
2132#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
2133#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
2134#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
2135#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
2136#define PUPSD 0x00200000 /*Power-up start delay */
2137#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
2138#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
2139#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
2140#define EBUFE 0x02000000 /* Enable external buffering timing */
2141#define FBBRW 0x04000000 /* Fast back-to-back read write enable */
2142#define EMREN 0x10000000 /* Extended mode register enable */
2143#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
2144#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
2145
2146/* EBIU_SDBCTL Masks */
2147#define EBE 0x00000001 /* Enable SDRAM external bank */
2148#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */
2149#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */
2150#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */
2151#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */
2152#define EBSZ_256 0x00000008 /* SDRAM External Bank Size = 256MB */
2153#define EBSZ_512 0x0000000A /* SDRAM External Bank Size = 512MB */
2154#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
2155#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
2156#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
2157#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
2158
2159/* EBIU_SDSTAT Masks */
2160#define SDCI 0x00000001 /* SDRAM controller is idle */
2161#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
2162#define SDPUA 0x00000004 /* SDRAM power up active */
2163#define SDRS 0x00000008 /* SDRAM is in reset state */
2164#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
2165#define BGSTAT 0x00000020 /* Bus granted */
2166
2167
2168/* ******************** TWO-WIRE INTERFACE (TWIx) MASKS ***********************/
2169/* TWIx_CLKDIV Macros (Use: *pTWIx_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
2170#ifdef _MISRA_RULES
2171#define CLKLOW(x) ((x) & 0xFFu) /* Periods Clock Is Held Low */
2172#define CLKHI(y) (((y)&0xFFu)<<0x8) /* Periods Before New Clock Low */
2173#else
2174#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
2175#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
2176#endif /* _MISRA_RULES */
2177
2178/* TWIx_PRESCALE Masks */
2179#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
2180#define TWI_ENA 0x0080 /* TWI Enable */
2181#define SCCB 0x0200 /* SCCB Compatibility Enable */
2182
2183/* TWIx_SLAVE_CTRL Masks */
2184#define SEN 0x0001 /* Slave Enable */
2185#define SADD_LEN 0x0002 /* Slave Address Length */
2186#define STDVAL 0x0004 /* Slave Transmit Data Valid */
2187#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
2188#define GEN 0x0010 /* General Call Adrress Matching Enabled */
2189
2190/* TWIx_SLAVE_STAT Masks */
2191#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
2192#define GCALL 0x0002 /* General Call Indicator */
2193
2194/* TWIx_MASTER_CTRL Masks */
2195#define MEN 0x0001 /* Master Mode Enable */
2196#define MADD_LEN 0x0002 /* Master Address Length */
2197#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
2198#define FAST 0x0008 /* Use Fast Mode Timing Specs */
2199#define STOP 0x0010 /* Issue Stop Condition */
2200#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
2201#define DCNT 0x3FC0 /* Data Bytes To Transfer */
2202#define SDAOVR 0x4000 /* Serial Data Override */
2203#define SCLOVR 0x8000 /* Serial Clock Override */
2204
2205/* TWIx_MASTER_STAT Masks */
2206#define MPROG 0x0001 /* Master Transfer In Progress */
2207#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
2208#define ANAK 0x0004 /* Address Not Acknowledged */
2209#define DNAK 0x0008 /* Data Not Acknowledged */
2210#define BUFRDERR 0x0010 /* Buffer Read Error */
2211#define BUFWRERR 0x0020 /* Buffer Write Error */
2212#define SDASEN 0x0040 /* Serial Data Sense */
2213#define SCLSEN 0x0080 /* Serial Clock Sense */
2214#define BUSBUSY 0x0100 /* Bus Busy Indicator */
2215
2216/* TWIx_INT_SRC and TWIx_INT_ENABLE Masks */
2217#define SINIT 0x0001 /* Slave Transfer Initiated */
2218#define SCOMP 0x0002 /* Slave Transfer Complete */
2219#define SERR 0x0004 /* Slave Transfer Error */
2220#define SOVF 0x0008 /* Slave Overflow */
2221#define MCOMP 0x0010 /* Master Transfer Complete */
2222#define MERR 0x0020 /* Master Transfer Error */
2223#define XMTSERV 0x0040 /* Transmit FIFO Service */
2224#define RCVSERV 0x0080 /* Receive FIFO Service */
2225
2226/* TWIx_FIFO_CTL Masks */
2227#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
2228#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
2229#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
2230#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
2231
2232/* TWIx_FIFO_STAT Masks */
2233#define XMTSTAT 0x0003 /* Transmit FIFO Status */
2234#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
2235#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
2236#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
2237
2238#define RCVSTAT 0x000C /* Receive FIFO Status */
2239#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
2240#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
2241#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
2242
2243#endif /* _DEF_BF539_H */ 152#endif /* _DEF_BF539_H */
diff --git a/arch/blackfin/mach-bf538/include/mach/gpio.h b/arch/blackfin/mach-bf538/include/mach/gpio.h
index bd9adb7183da..8a5beeece996 100644
--- a/arch/blackfin/mach-bf538/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf538/include/mach/gpio.h
@@ -70,4 +70,9 @@
70#define PORT_D GPIO_PD0 70#define PORT_D GPIO_PD0
71#define PORT_E GPIO_PE0 71#define PORT_E GPIO_PE0
72 72
73#include <mach-common/ports-c.h>
74#include <mach-common/ports-d.h>
75#include <mach-common/ports-e.h>
76#include <mach-common/ports-f.h>
77
73#endif /* _MACH_GPIO_H_ */ 78#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf538/include/mach/pll.h b/arch/blackfin/mach-bf538/include/mach/pll.h
index b30bbcd412a7..94cca674d835 100644
--- a/arch/blackfin/mach-bf538/include/mach/pll.h
+++ b/arch/blackfin/mach-bf538/include/mach/pll.h
@@ -1,63 +1 @@
1/* #include <mach-common/pll.h>
2 * Copyright 2008-2009 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr0, iwr1;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 flags = hard_local_irq_save();
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr0 = bfin_read32(SIC_IWR0);
24 iwr1 = bfin_read32(SIC_IWR1);
25 /* Only allow PPL Wakeup) */
26 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
27 bfin_write32(SIC_IWR1, 0);
28
29 bfin_write16(PLL_CTL, val);
30 SSYNC();
31 asm("IDLE;");
32
33 bfin_write32(SIC_IWR0, iwr0);
34 bfin_write32(SIC_IWR1, iwr1);
35 hard_local_irq_restore(flags);
36}
37
38/* Writing to VR_CTL initiates a PLL relock sequence. */
39static __inline__ void bfin_write_VR_CTL(unsigned int val)
40{
41 unsigned long flags, iwr0, iwr1;
42
43 if (val == bfin_read_VR_CTL())
44 return;
45
46 flags = hard_local_irq_save();
47 /* Enable the PLL Wakeup bit in SIC IWR */
48 iwr0 = bfin_read32(SIC_IWR0);
49 iwr1 = bfin_read32(SIC_IWR1);
50 /* Only allow PPL Wakeup) */
51 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
52 bfin_write32(SIC_IWR1, 0);
53
54 bfin_write16(VR_CTL, val);
55 SSYNC();
56 asm("IDLE;");
57
58 bfin_write32(SIC_IWR0, iwr0);
59 bfin_write32(SIC_IWR1, iwr1);
60 hard_local_irq_restore(flags);
61}
62
63#endif /* _MACH_PLL_H */
diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c
index 4c2ee6789099..d11502ac5623 100644
--- a/arch/blackfin/mach-bf548/boards/cm_bf548.c
+++ b/arch/blackfin/mach-bf548/boards/cm_bf548.c
@@ -156,7 +156,7 @@ static struct resource bfin_uart0_resources[] = {
156 }, 156 },
157}; 157};
158 158
159unsigned short bfin_uart0_peripherals[] = { 159static unsigned short bfin_uart0_peripherals[] = {
160 P_UART0_TX, P_UART0_RX, 0 160 P_UART0_TX, P_UART0_RX, 0
161}; 161};
162 162
@@ -211,7 +211,7 @@ static struct resource bfin_uart1_resources[] = {
211#endif 211#endif
212}; 212};
213 213
214unsigned short bfin_uart1_peripherals[] = { 214static unsigned short bfin_uart1_peripherals[] = {
215 P_UART1_TX, P_UART1_RX, 215 P_UART1_TX, P_UART1_RX,
216#ifdef CONFIG_BFIN_UART1_CTSRTS 216#ifdef CONFIG_BFIN_UART1_CTSRTS
217 P_UART1_RTS, P_UART1_CTS, 217 P_UART1_RTS, P_UART1_CTS,
@@ -258,7 +258,7 @@ static struct resource bfin_uart2_resources[] = {
258 }, 258 },
259}; 259};
260 260
261unsigned short bfin_uart2_peripherals[] = { 261static unsigned short bfin_uart2_peripherals[] = {
262 P_UART2_TX, P_UART2_RX, 0 262 P_UART2_TX, P_UART2_RX, 0
263}; 263};
264 264
@@ -313,7 +313,7 @@ static struct resource bfin_uart3_resources[] = {
313#endif 313#endif
314}; 314};
315 315
316unsigned short bfin_uart3_peripherals[] = { 316static unsigned short bfin_uart3_peripherals[] = {
317 P_UART3_TX, P_UART3_RX, 317 P_UART3_TX, P_UART3_RX,
318#ifdef CONFIG_BFIN_UART3_CTSRTS 318#ifdef CONFIG_BFIN_UART3_CTSRTS
319 P_UART3_RTS, P_UART3_CTS, 319 P_UART3_RTS, P_UART3_CTS,
@@ -504,6 +504,7 @@ static struct musb_hdrc_config musb_config = {
504 * if it is the case. 504 * if it is the case.
505 */ 505 */
506 .gpio_vrsel_active = 1, 506 .gpio_vrsel_active = 1,
507 .clkin = 24, /* musb CLKIN in MHZ */
507}; 508};
508 509
509static struct musb_hdrc_platform_data musb_plat = { 510static struct musb_hdrc_platform_data musb_plat = {
@@ -552,9 +553,9 @@ static struct resource bfin_sport0_uart_resources[] = {
552 }, 553 },
553}; 554};
554 555
555unsigned short bfin_sport0_peripherals[] = { 556static unsigned short bfin_sport0_peripherals[] = {
556 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 557 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
557 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 558 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
558}; 559};
559 560
560static struct platform_device bfin_sport0_uart_device = { 561static struct platform_device bfin_sport0_uart_device = {
@@ -586,9 +587,9 @@ static struct resource bfin_sport1_uart_resources[] = {
586 }, 587 },
587}; 588};
588 589
589unsigned short bfin_sport1_peripherals[] = { 590static unsigned short bfin_sport1_peripherals[] = {
590 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 591 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
591 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 592 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
592}; 593};
593 594
594static struct platform_device bfin_sport1_uart_device = { 595static struct platform_device bfin_sport1_uart_device = {
@@ -620,7 +621,7 @@ static struct resource bfin_sport2_uart_resources[] = {
620 }, 621 },
621}; 622};
622 623
623unsigned short bfin_sport2_peripherals[] = { 624static unsigned short bfin_sport2_peripherals[] = {
624 P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS, 625 P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
625 P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0 626 P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
626}; 627};
@@ -654,7 +655,7 @@ static struct resource bfin_sport3_uart_resources[] = {
654 }, 655 },
655}; 656};
656 657
657unsigned short bfin_sport3_peripherals[] = { 658static unsigned short bfin_sport3_peripherals[] = {
658 P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS, 659 P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
659 P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0 660 P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
660}; 661};
@@ -756,7 +757,7 @@ static struct platform_device bf54x_sdh_device = {
756#endif 757#endif
757 758
758#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) 759#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
759unsigned short bfin_can_peripherals[] = { 760static unsigned short bfin_can_peripherals[] = {
760 P_CAN0_RX, P_CAN0_TX, 0 761 P_CAN0_RX, P_CAN0_TX, 0
761}; 762};
762 763
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index 4f03fbc4c9be..ce5a2bb147dc 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -261,7 +261,7 @@ static struct resource bfin_uart0_resources[] = {
261 }, 261 },
262}; 262};
263 263
264unsigned short bfin_uart0_peripherals[] = { 264static unsigned short bfin_uart0_peripherals[] = {
265 P_UART0_TX, P_UART0_RX, 0 265 P_UART0_TX, P_UART0_RX, 0
266}; 266};
267 267
@@ -316,7 +316,7 @@ static struct resource bfin_uart1_resources[] = {
316#endif 316#endif
317}; 317};
318 318
319unsigned short bfin_uart1_peripherals[] = { 319static unsigned short bfin_uart1_peripherals[] = {
320 P_UART1_TX, P_UART1_RX, 320 P_UART1_TX, P_UART1_RX,
321#ifdef CONFIG_BFIN_UART1_CTSRTS 321#ifdef CONFIG_BFIN_UART1_CTSRTS
322 P_UART1_RTS, P_UART1_CTS, 322 P_UART1_RTS, P_UART1_CTS,
@@ -363,7 +363,7 @@ static struct resource bfin_uart2_resources[] = {
363 }, 363 },
364}; 364};
365 365
366unsigned short bfin_uart2_peripherals[] = { 366static unsigned short bfin_uart2_peripherals[] = {
367 P_UART2_TX, P_UART2_RX, 0 367 P_UART2_TX, P_UART2_RX, 0
368}; 368};
369 369
@@ -418,7 +418,7 @@ static struct resource bfin_uart3_resources[] = {
418#endif 418#endif
419}; 419};
420 420
421unsigned short bfin_uart3_peripherals[] = { 421static unsigned short bfin_uart3_peripherals[] = {
422 P_UART3_TX, P_UART3_RX, 422 P_UART3_TX, P_UART3_RX,
423#ifdef CONFIG_BFIN_UART3_CTSRTS 423#ifdef CONFIG_BFIN_UART3_CTSRTS
424 P_UART3_RTS, P_UART3_CTS, 424 P_UART3_RTS, P_UART3_CTS,
@@ -609,6 +609,7 @@ static struct musb_hdrc_config musb_config = {
609 * if it is the case. 609 * if it is the case.
610 */ 610 */
611 .gpio_vrsel_active = 1, 611 .gpio_vrsel_active = 1,
612 .clkin = 24, /* musb CLKIN in MHZ */
612}; 613};
613 614
614static struct musb_hdrc_platform_data musb_plat = { 615static struct musb_hdrc_platform_data musb_plat = {
@@ -657,9 +658,9 @@ static struct resource bfin_sport0_uart_resources[] = {
657 }, 658 },
658}; 659};
659 660
660unsigned short bfin_sport0_peripherals[] = { 661static unsigned short bfin_sport0_peripherals[] = {
661 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 662 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
662 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 663 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
663}; 664};
664 665
665static struct platform_device bfin_sport0_uart_device = { 666static struct platform_device bfin_sport0_uart_device = {
@@ -691,9 +692,9 @@ static struct resource bfin_sport1_uart_resources[] = {
691 }, 692 },
692}; 693};
693 694
694unsigned short bfin_sport1_peripherals[] = { 695static unsigned short bfin_sport1_peripherals[] = {
695 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 696 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
696 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 697 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
697}; 698};
698 699
699static struct platform_device bfin_sport1_uart_device = { 700static struct platform_device bfin_sport1_uart_device = {
@@ -725,7 +726,7 @@ static struct resource bfin_sport2_uart_resources[] = {
725 }, 726 },
726}; 727};
727 728
728unsigned short bfin_sport2_peripherals[] = { 729static unsigned short bfin_sport2_peripherals[] = {
729 P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS, 730 P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
730 P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0 731 P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
731}; 732};
@@ -759,7 +760,7 @@ static struct resource bfin_sport3_uart_resources[] = {
759 }, 760 },
760}; 761};
761 762
762unsigned short bfin_sport3_peripherals[] = { 763static unsigned short bfin_sport3_peripherals[] = {
763 P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS, 764 P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
764 P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0 765 P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
765}; 766};
@@ -777,7 +778,7 @@ static struct platform_device bfin_sport3_uart_device = {
777#endif 778#endif
778 779
779#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) 780#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
780unsigned short bfin_can_peripherals[] = { 781static unsigned short bfin_can_peripherals[] = {
781 P_CAN0_RX, P_CAN0_TX, 0 782 P_CAN0_RX, P_CAN0_TX, 0
782}; 783};
783 784
diff --git a/arch/blackfin/mach-bf548/dma.c b/arch/blackfin/mach-bf548/dma.c
index 888b9cc0b822..69ead33cbf91 100644
--- a/arch/blackfin/mach-bf548/dma.c
+++ b/arch/blackfin/mach-bf548/dma.c
@@ -11,7 +11,7 @@
11#include <asm/blackfin.h> 11#include <asm/blackfin.h>
12#include <asm/dma.h> 12#include <asm/dma.h>
13 13
14struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { 14struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
15 (struct dma_register *) DMA0_NEXT_DESC_PTR, 15 (struct dma_register *) DMA0_NEXT_DESC_PTR,
16 (struct dma_register *) DMA1_NEXT_DESC_PTR, 16 (struct dma_register *) DMA1_NEXT_DESC_PTR,
17 (struct dma_register *) DMA2_NEXT_DESC_PTR, 17 (struct dma_register *) DMA2_NEXT_DESC_PTR,
diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_serial.h b/arch/blackfin/mach-bf548/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..a77109f99720
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/bfin_serial.h
@@ -0,0 +1,16 @@
1/*
2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
3 *
4 * Copyright 2006-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_MACH_SERIAL_H__
10#define __BFIN_MACH_SERIAL_H__
11
12#define BFIN_UART_NR_PORTS 4
13
14#define BFIN_UART_BF54X_STYLE
15
16#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
index dd44aa75fe72..0d94edaaaa2e 100644
--- a/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
@@ -4,72 +4,14 @@
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
6 6
7#include <linux/serial.h>
8#include <asm/dma.h> 7#include <asm/dma.h>
9#include <asm/portmux.h> 8#include <asm/portmux.h>
10 9
11#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
12#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
13#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
14#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER_SET))
15#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
16#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
17#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
18#define UART_GET_MSR(uart) bfin_read16(((uart)->port.membase + OFFSET_MSR))
19#define UART_GET_MCR(uart) bfin_read16(((uart)->port.membase + OFFSET_MCR))
20
21#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
22#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
23#define UART_SET_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v)
24#define UART_CLEAR_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v)
25#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
26#define UART_PUT_LSR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LSR),v)
27#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
28#define UART_CLEAR_LSR(uart) bfin_write16(((uart)->port.membase + OFFSET_LSR), -1)
29#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
30#define UART_PUT_MCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_MCR),v)
31#define UART_CLEAR_SCTS(uart) bfin_write16(((uart)->port.membase + OFFSET_MSR),SCTS)
32
33#define UART_SET_DLAB(uart) /* MMRs not muxed on BF54x */
34#define UART_CLEAR_DLAB(uart) /* MMRs not muxed on BF54x */
35
36#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
37#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS|MRTS))
38#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
39#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
40#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
41
42#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) || \ 10#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) || \
43 defined(CONFIG_BFIN_UART2_CTSRTS) || defined(CONFIG_BFIN_UART3_CTSRTS) 11 defined(CONFIG_BFIN_UART2_CTSRTS) || defined(CONFIG_BFIN_UART3_CTSRTS)
44# define CONFIG_SERIAL_BFIN_HARD_CTSRTS 12# define CONFIG_SERIAL_BFIN_HARD_CTSRTS
45#endif 13#endif
46 14
47#define BFIN_UART_TX_FIFO_SIZE 2
48
49/*
50 * The pin configuration is different from schematic
51 */
52struct bfin_serial_port {
53 struct uart_port port;
54 unsigned int old_status;
55 int status_irq;
56#ifdef CONFIG_SERIAL_BFIN_DMA
57 int tx_done;
58 int tx_count;
59 struct circ_buf rx_dma_buf;
60 struct timer_list rx_dma_timer;
61 int rx_dma_nrows;
62 unsigned int tx_dma_channel;
63 unsigned int rx_dma_channel;
64 struct work_struct tx_dma_workqueue;
65#endif
66#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
67 int scts;
68 int cts_pin;
69 int rts_pin;
70#endif
71};
72
73struct bfin_serial_res { 15struct bfin_serial_res {
74 unsigned long uart_base_addr; 16 unsigned long uart_base_addr;
75 int uart_irq; 17 int uart_irq;
@@ -148,3 +90,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
148}; 90};
149 91
150#define DRIVER_NAME "bfin-uart" 92#define DRIVER_NAME "bfin-uart"
93
94#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf548/include/mach/blackfin.h b/arch/blackfin/mach-bf548/include/mach/blackfin.h
index 5684030ccc21..72da721a77f5 100644
--- a/arch/blackfin/mach-bf548/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf548/include/mach/blackfin.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2007-2009 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
@@ -10,58 +10,40 @@
10#include "bf548.h" 10#include "bf548.h"
11#include "anomaly.h" 11#include "anomaly.h"
12 12
13#include <asm/def_LPBlackfin.h>
13#ifdef CONFIG_BF542 14#ifdef CONFIG_BF542
14#include "defBF542.h" 15# include "defBF542.h"
15#endif 16#endif
16
17#ifdef CONFIG_BF544 17#ifdef CONFIG_BF544
18#include "defBF544.h" 18# include "defBF544.h"
19#endif 19#endif
20
21#ifdef CONFIG_BF547 20#ifdef CONFIG_BF547
22#include "defBF547.h" 21# include "defBF547.h"
23#endif 22#endif
24
25#ifdef CONFIG_BF548 23#ifdef CONFIG_BF548
26#include "defBF548.h" 24# include "defBF548.h"
27#endif 25#endif
28
29#ifdef CONFIG_BF549 26#ifdef CONFIG_BF549
30#include "defBF549.h" 27# include "defBF549.h"
31#endif 28#endif
32 29
33#if !defined(__ASSEMBLY__) 30#ifndef __ASSEMBLY__
34#ifdef CONFIG_BF542 31# include <asm/cdef_LPBlackfin.h>
35#include "cdefBF542.h" 32# ifdef CONFIG_BF542
33# include "cdefBF542.h"
34# endif
35# ifdef CONFIG_BF544
36# include "cdefBF544.h"
37# endif
38# ifdef CONFIG_BF547
39# include "cdefBF547.h"
40# endif
41# ifdef CONFIG_BF548
42# include "cdefBF548.h"
43# endif
44# ifdef CONFIG_BF549
45# include "cdefBF549.h"
46# endif
36#endif 47#endif
37#ifdef CONFIG_BF544
38#include "cdefBF544.h"
39#endif
40#ifdef CONFIG_BF547
41#include "cdefBF547.h"
42#endif
43#ifdef CONFIG_BF548
44#include "cdefBF548.h"
45#endif
46#ifdef CONFIG_BF549
47#include "cdefBF549.h"
48#endif
49
50#endif
51
52#define BFIN_UART_NR_PORTS 4
53
54#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
55#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
56#define OFFSET_GCTL 0x08 /* Global Control Register */
57#define OFFSET_LCR 0x0C /* Line Control Register */
58#define OFFSET_MCR 0x10 /* Modem Control Register */
59#define OFFSET_LSR 0x14 /* Line Status Register */
60#define OFFSET_MSR 0x18 /* Modem Status Register */
61#define OFFSET_SCR 0x1C /* SCR Scratch Register */
62#define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
63#define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
64#define OFFSET_THR 0x28 /* Transmit Holding register */
65#define OFFSET_RBR 0x2C /* Receive Buffer register */
66 48
67#endif 49#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF542.h b/arch/blackfin/mach-bf548/include/mach/cdefBF542.h
index 42f4a9469549..d09c19cd1b7b 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF542.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF542.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2007-2008 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
@@ -7,14 +7,6 @@
7#ifndef _CDEF_BF542_H 7#ifndef _CDEF_BF542_H
8#define _CDEF_BF542_H 8#define _CDEF_BF542_H
9 9
10/* include all Core registers and bit definitions */
11#include "defBF542.h"
12
13/* include core sbfin_read_()ecific register pointer definitions */
14#include <asm/cdef_LPBlackfin.h>
15
16/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
17
18/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ 10/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
19#include "cdefBF54x_base.h" 11#include "cdefBF54x_base.h"
20 12
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF544.h b/arch/blackfin/mach-bf548/include/mach/cdefBF544.h
index 2207799575ff..33ec8102ceda 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF544.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF544.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2007-2008 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
@@ -7,14 +7,6 @@
7#ifndef _CDEF_BF544_H 7#ifndef _CDEF_BF544_H
8#define _CDEF_BF544_H 8#define _CDEF_BF544_H
9 9
10/* include all Core registers and bit definitions */
11#include "defBF544.h"
12
13/* include core sbfin_read_()ecific register pointer definitions */
14#include <asm/cdef_LPBlackfin.h>
15
16/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */
17
18/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ 10/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
19#include "cdefBF54x_base.h" 11#include "cdefBF54x_base.h"
20 12
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF547.h b/arch/blackfin/mach-bf548/include/mach/cdefBF547.h
index bc650e6ea482..bcb9726dea54 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF547.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF547.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2008 Analog Devices Inc. 2 * Copyright 2008-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
@@ -7,14 +7,6 @@
7#ifndef _CDEF_BF547_H 7#ifndef _CDEF_BF547_H
8#define _CDEF_BF547_H 8#define _CDEF_BF547_H
9 9
10/* include all Core registers and bit definitions */
11#include "defBF547.h"
12
13/* include core sbfin_read_()ecific register pointer definitions */
14#include <asm/cdef_LPBlackfin.h>
15
16/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF547 */
17
18/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ 10/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
19#include "cdefBF54x_base.h" 11#include "cdefBF54x_base.h"
20 12
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF548.h b/arch/blackfin/mach-bf548/include/mach/cdefBF548.h
index 3523e08f7968..bae67a65633e 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF548.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF548.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2007-2008 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
@@ -7,14 +7,6 @@
7#ifndef _CDEF_BF548_H 7#ifndef _CDEF_BF548_H
8#define _CDEF_BF548_H 8#define _CDEF_BF548_H
9 9
10/* include all Core registers and bit definitions */
11#include "defBF548.h"
12
13/* include core sbfin_read_()ecific register pointer definitions */
14#include <asm/cdef_LPBlackfin.h>
15
16/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
17
18/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ 10/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
19#include "cdefBF54x_base.h" 11#include "cdefBF54x_base.h"
20 12
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF549.h b/arch/blackfin/mach-bf548/include/mach/cdefBF549.h
index 80201ed41f80..002136ad5a44 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF549.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF549.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2007-2008 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
@@ -7,14 +7,6 @@
7#ifndef _CDEF_BF549_H 7#ifndef _CDEF_BF549_H
8#define _CDEF_BF549_H 8#define _CDEF_BF549_H
9 9
10/* include all Core registers and bit definitions */
11#include "defBF549.h"
12
13/* include core sbfin_read_()ecific register pointer definitions */
14#include <asm/cdef_LPBlackfin.h>
15
16/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */
17
18/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ 10/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
19#include "cdefBF54x_base.h" 11#include "cdefBF54x_base.h"
20 12
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
index deaf5d6542d5..50c89c8052f3 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2007-2008 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
@@ -7,10 +7,6 @@
7#ifndef _CDEF_BF54X_H 7#ifndef _CDEF_BF54X_H
8#define _CDEF_BF54X_H 8#define _CDEF_BF54X_H
9 9
10#include <asm/blackfin.h>
11
12#include "defBF54x_base.h"
13
14/* ************************************************************** */ 10/* ************************************************************** */
15/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */ 11/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
16/* ************************************************************** */ 12/* ************************************************************** */
@@ -2633,22 +2629,5 @@
2633 2629
2634/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 bfin_read_()rocessor */ 2630/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 bfin_read_()rocessor */
2635 2631
2636/* legacy definitions */
2637#define bfin_read_EBIU_AMCBCTL0 bfin_read_EBIU_AMBCTL0
2638#define bfin_write_EBIU_AMCBCTL0 bfin_write_EBIU_AMBCTL0
2639#define bfin_read_EBIU_AMCBCTL1 bfin_read_EBIU_AMBCTL1
2640#define bfin_write_EBIU_AMCBCTL1 bfin_write_EBIU_AMBCTL1
2641#define bfin_read_PINT0_IRQ bfin_read_PINT0_REQUEST
2642#define bfin_write_PINT0_IRQ bfin_write_PINT0_REQUEST
2643#define bfin_read_PINT1_IRQ bfin_read_PINT1_REQUEST
2644#define bfin_write_PINT1_IRQ bfin_write_PINT1_REQUEST
2645#define bfin_read_PINT2_IRQ bfin_read_PINT2_REQUEST
2646#define bfin_write_PINT2_IRQ bfin_write_PINT2_REQUEST
2647#define bfin_read_PINT3_IRQ bfin_read_PINT3_REQUEST
2648#define bfin_write_PINT3_IRQ bfin_write_PINT3_REQUEST
2649
2650/* These need to be last due to the cdef/linux inter-dependencies */
2651#include <asm/irq.h>
2652
2653#endif /* _CDEF_BF54X_H */ 2632#endif /* _CDEF_BF54X_H */
2654 2633
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF542.h b/arch/blackfin/mach-bf548/include/mach/defBF542.h
index abf5f750dd8b..629bf216e2b5 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF542.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF542.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2007-2008 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
@@ -7,11 +7,6 @@
7#ifndef _DEF_BF542_H 7#ifndef _DEF_BF542_H
8#define _DEF_BF542_H 8#define _DEF_BF542_H
9 9
10/* Include all Core registers and bit definitions */
11#include <asm/def_LPBlackfin.h>
12
13/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
14
15/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ 10/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
16#include "defBF54x_base.h" 11#include "defBF54x_base.h"
17 12
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF544.h b/arch/blackfin/mach-bf548/include/mach/defBF544.h
index e2771094de02..642468c1bcb1 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF544.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF544.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2007-2008 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
@@ -7,11 +7,6 @@
7#ifndef _DEF_BF544_H 7#ifndef _DEF_BF544_H
8#define _DEF_BF544_H 8#define _DEF_BF544_H
9 9
10/* Include all Core registers and bit definitions */
11#include <asm/def_LPBlackfin.h>
12
13/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */
14
15/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ 10/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
16#include "defBF54x_base.h" 11#include "defBF54x_base.h"
17 12
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h
index be21ba5b3aa8..2f3337cd311e 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF547.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF547.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2008 Analog Devices Inc. 2 * Copyright 2008-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
@@ -7,11 +7,6 @@
7#ifndef _DEF_BF547_H 7#ifndef _DEF_BF547_H
8#define _DEF_BF547_H 8#define _DEF_BF547_H
9 9
10/* Include all Core registers and bit definitions */
11#include <asm/def_LPBlackfin.h>
12
13/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF547 */
14
15/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ 10/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
16#include "defBF54x_base.h" 11#include "defBF54x_base.h"
17 12
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF548.h b/arch/blackfin/mach-bf548/include/mach/defBF548.h
index 3fb33b040ab7..3c7f1b69349e 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF548.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF548.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2007-2008 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
@@ -7,11 +7,6 @@
7#ifndef _DEF_BF548_H 7#ifndef _DEF_BF548_H
8#define _DEF_BF548_H 8#define _DEF_BF548_H
9 9
10/* Include all Core registers and bit definitions */
11#include <asm/def_LPBlackfin.h>
12
13/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
14
15/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ 10/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
16#include "defBF54x_base.h" 11#include "defBF54x_base.h"
17 12
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF549.h b/arch/blackfin/mach-bf548/include/mach/defBF549.h
index 5a04e6d4017e..9a45cb6b30da 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF549.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF549.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2007-2008 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
@@ -7,11 +7,6 @@
7#ifndef _DEF_BF549_H 7#ifndef _DEF_BF549_H
8#define _DEF_BF549_H 8#define _DEF_BF549_H
9 9
10/* Include all Core registers and bit definitions */
11#include <asm/def_LPBlackfin.h>
12
13/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */
14
15/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ 10/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
16#include "defBF54x_base.h" 11#include "defBF54x_base.h"
17 12
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
index 78f91103f175..0867c2bedb43 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2007-2008 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
@@ -1615,14 +1615,14 @@
1615#define CTYPE 0x40 /* DMA Channel Type */ 1615#define CTYPE 0x40 /* DMA Channel Type */
1616#define PMAP 0xf000 /* Peripheral Mapped To This Channel */ 1616#define PMAP 0xf000 /* Peripheral Mapped To This Channel */
1617 1617
1618/* Bit masks for DMACx_TCPER */ 1618/* Bit masks for DMACx_TC_PER */
1619 1619
1620#define DCB_TRAFFIC_PERIOD 0xf /* DCB Traffic Control Period */ 1620#define DCB_TRAFFIC_PERIOD 0xf /* DCB Traffic Control Period */
1621#define DEB_TRAFFIC_PERIOD 0xf0 /* DEB Traffic Control Period */ 1621#define DEB_TRAFFIC_PERIOD 0xf0 /* DEB Traffic Control Period */
1622#define DAB_TRAFFIC_PERIOD 0x700 /* DAB Traffic Control Period */ 1622#define DAB_TRAFFIC_PERIOD 0x700 /* DAB Traffic Control Period */
1623#define MDMA_ROUND_ROBIN_PERIOD 0xf800 /* MDMA Round Robin Period */ 1623#define MDMA_ROUND_ROBIN_PERIOD 0xf800 /* MDMA Round Robin Period */
1624 1624
1625/* Bit masks for DMACx_TCCNT */ 1625/* Bit masks for DMACx_TC_CNT */
1626 1626
1627#define DCB_TRAFFIC_COUNT 0xf /* DCB Traffic Control Count */ 1627#define DCB_TRAFFIC_COUNT 0xf /* DCB Traffic Control Count */
1628#define DEB_TRAFFIC_COUNT 0xf0 /* DEB Traffic Control Count */ 1628#define DEB_TRAFFIC_COUNT 0xf0 /* DEB Traffic Control Count */
@@ -2172,68 +2172,6 @@
2172 2172
2173#define RCVDATA16 0xffff /* Receive FIFO 16-Bit Data */ 2173#define RCVDATA16 0xffff /* Receive FIFO 16-Bit Data */
2174 2174
2175/* Bit masks for UARTx_LCR */
2176
2177#if 0
2178/* conflicts with legacy one in last section */
2179#define WLS 0x3 /* Word Length Select */
2180#endif
2181#define STB 0x4 /* Stop Bits */
2182#define PEN 0x8 /* Parity Enable */
2183#define EPS 0x10 /* Even Parity Select */
2184#define STP 0x20 /* Sticky Parity */
2185#define SB 0x40 /* Set Break */
2186
2187/* Bit masks for UARTx_MCR */
2188
2189#define XOFF 0x1 /* Transmitter Off */
2190#define MRTS 0x2 /* Manual Request To Send */
2191#define RFIT 0x4 /* Receive FIFO IRQ Threshold */
2192#define RFRT 0x8 /* Receive FIFO RTS Threshold */
2193#define LOOP_ENA 0x10 /* Loopback Mode Enable */
2194#define FCPOL 0x20 /* Flow Control Pin Polarity */
2195#define ARTS 0x40 /* Automatic Request To Send */
2196#define ACTS 0x80 /* Automatic Clear To Send */
2197
2198/* Bit masks for UARTx_LSR */
2199
2200#define DR 0x1 /* Data Ready */
2201#define OE 0x2 /* Overrun Error */
2202#define PE 0x4 /* Parity Error */
2203#define FE 0x8 /* Framing Error */
2204#define BI 0x10 /* Break Interrupt */
2205#define THRE 0x20 /* THR Empty */
2206#define TEMT 0x40 /* Transmitter Empty */
2207#define TFI 0x80 /* Transmission Finished Indicator */
2208
2209/* Bit masks for UARTx_MSR */
2210
2211#define SCTS 0x1 /* Sticky CTS */
2212#define CTS 0x10 /* Clear To Send */
2213#define RFCS 0x20 /* Receive FIFO Count Status */
2214
2215/* Bit masks for UARTx_IER_SET & UARTx_IER_CLEAR */
2216
2217#define ERBFI 0x1 /* Enable Receive Buffer Full Interrupt */
2218#define ETBEI 0x2 /* Enable Transmit Buffer Empty Interrupt */
2219#define ELSI 0x4 /* Enable Receive Status Interrupt */
2220#define EDSSI 0x8 /* Enable Modem Status Interrupt */
2221#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */
2222#define ETFI 0x20 /* Enable Transmission Finished Interrupt */
2223#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */
2224
2225/* Bit masks for UARTx_GCTL */
2226
2227#define UCEN 0x1 /* UART Enable */
2228#define IREN 0x2 /* IrDA Mode Enable */
2229#define TPOLC 0x4 /* IrDA TX Polarity Change */
2230#define RPOLC 0x8 /* IrDA RX Polarity Change */
2231#define FPE 0x10 /* Force Parity Error */
2232#define FFE 0x20 /* Force Framing Error */
2233#define EDBO 0x40 /* Enable Divide-by-One */
2234#define EGLSI 0x80 /* Enable Global LS Interrupt */
2235
2236
2237/* ******************************************* */ 2175/* ******************************************* */
2238/* MULTI BIT MACRO ENUMERATIONS */ 2176/* MULTI BIT MACRO ENUMERATIONS */
2239/* ******************************************* */ 2177/* ******************************************* */
@@ -2251,13 +2189,6 @@
2251#define WDTH_CAP 0x0002 2189#define WDTH_CAP 0x0002
2252#define EXT_CLK 0x0003 2190#define EXT_CLK 0x0003
2253 2191
2254/* UARTx_LCR bit field options */
2255
2256#define WLS_5 0x0000 /* 5 data bits */
2257#define WLS_6 0x0001 /* 6 data bits */
2258#define WLS_7 0x0002 /* 7 data bits */
2259#define WLS_8 0x0003 /* 8 data bits */
2260
2261/* PINTx Register Bit Definitions */ 2192/* PINTx Register Bit Definitions */
2262 2193
2263#define PIQ0 0x00000001 2194#define PIQ0 0x00000001
@@ -2300,240 +2231,6 @@
2300#define PIQ30 0x40000000 2231#define PIQ30 0x40000000
2301#define PIQ31 0x80000000 2232#define PIQ31 0x80000000
2302 2233
2303/* PORT A Bit Definitions for the registers
2304PORTA, PORTA_SET, PORTA_CLEAR,
2305PORTA_DIR_SET, PORTA_DIR_CLEAR, PORTA_INEN,
2306PORTA_FER registers
2307*/
2308
2309#define PA0 0x0001
2310#define PA1 0x0002
2311#define PA2 0x0004
2312#define PA3 0x0008
2313#define PA4 0x0010
2314#define PA5 0x0020
2315#define PA6 0x0040
2316#define PA7 0x0080
2317#define PA8 0x0100
2318#define PA9 0x0200
2319#define PA10 0x0400
2320#define PA11 0x0800
2321#define PA12 0x1000
2322#define PA13 0x2000
2323#define PA14 0x4000
2324#define PA15 0x8000
2325
2326/* PORT B Bit Definitions for the registers
2327PORTB, PORTB_SET, PORTB_CLEAR,
2328PORTB_DIR_SET, PORTB_DIR_CLEAR, PORTB_INEN,
2329PORTB_FER registers
2330*/
2331
2332#define PB0 0x0001
2333#define PB1 0x0002
2334#define PB2 0x0004
2335#define PB3 0x0008
2336#define PB4 0x0010
2337#define PB5 0x0020
2338#define PB6 0x0040
2339#define PB7 0x0080
2340#define PB8 0x0100
2341#define PB9 0x0200
2342#define PB10 0x0400
2343#define PB11 0x0800
2344#define PB12 0x1000
2345#define PB13 0x2000
2346#define PB14 0x4000
2347
2348
2349/* PORT C Bit Definitions for the registers
2350PORTC, PORTC_SET, PORTC_CLEAR,
2351PORTC_DIR_SET, PORTC_DIR_CLEAR, PORTC_INEN,
2352PORTC_FER registers
2353*/
2354
2355
2356#define PC0 0x0001
2357#define PC1 0x0002
2358#define PC2 0x0004
2359#define PC3 0x0008
2360#define PC4 0x0010
2361#define PC5 0x0020
2362#define PC6 0x0040
2363#define PC7 0x0080
2364#define PC8 0x0100
2365#define PC9 0x0200
2366#define PC10 0x0400
2367#define PC11 0x0800
2368#define PC12 0x1000
2369#define PC13 0x2000
2370
2371
2372/* PORT D Bit Definitions for the registers
2373PORTD, PORTD_SET, PORTD_CLEAR,
2374PORTD_DIR_SET, PORTD_DIR_CLEAR, PORTD_INEN,
2375PORTD_FER registers
2376*/
2377
2378#define PD0 0x0001
2379#define PD1 0x0002
2380#define PD2 0x0004
2381#define PD3 0x0008
2382#define PD4 0x0010
2383#define PD5 0x0020
2384#define PD6 0x0040
2385#define PD7 0x0080
2386#define PD8 0x0100
2387#define PD9 0x0200
2388#define PD10 0x0400
2389#define PD11 0x0800
2390#define PD12 0x1000
2391#define PD13 0x2000
2392#define PD14 0x4000
2393#define PD15 0x8000
2394
2395/* PORT E Bit Definitions for the registers
2396PORTE, PORTE_SET, PORTE_CLEAR,
2397PORTE_DIR_SET, PORTE_DIR_CLEAR, PORTE_INEN,
2398PORTE_FER registers
2399*/
2400
2401
2402#define PE0 0x0001
2403#define PE1 0x0002
2404#define PE2 0x0004
2405#define PE3 0x0008
2406#define PE4 0x0010
2407#define PE5 0x0020
2408#define PE6 0x0040
2409#define PE7 0x0080
2410#define PE8 0x0100
2411#define PE9 0x0200
2412#define PE10 0x0400
2413#define PE11 0x0800
2414#define PE12 0x1000
2415#define PE13 0x2000
2416#define PE14 0x4000
2417#define PE15 0x8000
2418
2419/* PORT F Bit Definitions for the registers
2420PORTF, PORTF_SET, PORTF_CLEAR,
2421PORTF_DIR_SET, PORTF_DIR_CLEAR, PORTF_INEN,
2422PORTF_FER registers
2423*/
2424
2425
2426#define PF0 0x0001
2427#define PF1 0x0002
2428#define PF2 0x0004
2429#define PF3 0x0008
2430#define PF4 0x0010
2431#define PF5 0x0020
2432#define PF6 0x0040
2433#define PF7 0x0080
2434#define PF8 0x0100
2435#define PF9 0x0200
2436#define PF10 0x0400
2437#define PF11 0x0800
2438#define PF12 0x1000
2439#define PF13 0x2000
2440#define PF14 0x4000
2441#define PF15 0x8000
2442
2443/* PORT G Bit Definitions for the registers
2444PORTG, PORTG_SET, PORTG_CLEAR,
2445PORTG_DIR_SET, PORTG_DIR_CLEAR, PORTG_INEN,
2446PORTG_FER registers
2447*/
2448
2449
2450#define PG0 0x0001
2451#define PG1 0x0002
2452#define PG2 0x0004
2453#define PG3 0x0008
2454#define PG4 0x0010
2455#define PG5 0x0020
2456#define PG6 0x0040
2457#define PG7 0x0080
2458#define PG8 0x0100
2459#define PG9 0x0200
2460#define PG10 0x0400
2461#define PG11 0x0800
2462#define PG12 0x1000
2463#define PG13 0x2000
2464#define PG14 0x4000
2465#define PG15 0x8000
2466
2467/* PORT H Bit Definitions for the registers
2468PORTH, PORTH_SET, PORTH_CLEAR,
2469PORTH_DIR_SET, PORTH_DIR_CLEAR, PORTH_INEN,
2470PORTH_FER registers
2471*/
2472
2473
2474#define PH0 0x0001
2475#define PH1 0x0002
2476#define PH2 0x0004
2477#define PH3 0x0008
2478#define PH4 0x0010
2479#define PH5 0x0020
2480#define PH6 0x0040
2481#define PH7 0x0080
2482#define PH8 0x0100
2483#define PH9 0x0200
2484#define PH10 0x0400
2485#define PH11 0x0800
2486#define PH12 0x1000
2487#define PH13 0x2000
2488
2489
2490/* PORT I Bit Definitions for the registers
2491PORTI, PORTI_SET, PORTI_CLEAR,
2492PORTI_DIR_SET, PORTI_DIR_CLEAR, PORTI_INEN,
2493PORTI_FER registers
2494*/
2495
2496
2497#define PI0 0x0001
2498#define PI1 0x0002
2499#define PI2 0x0004
2500#define PI3 0x0008
2501#define PI4 0x0010
2502#define PI5 0x0020
2503#define PI6 0x0040
2504#define PI7 0x0080
2505#define PI8 0x0100
2506#define PI9 0x0200
2507#define PI10 0x0400
2508#define PI11 0x0800
2509#define PI12 0x1000
2510#define PI13 0x2000
2511#define PI14 0x4000
2512#define PI15 0x8000
2513
2514/* PORT J Bit Definitions for the registers
2515PORTJ, PORTJ_SET, PORTJ_CLEAR,
2516PORTJ_DIR_SET, PORTJ_DIR_CLEAR, PORTJ_INEN,
2517PORTJ_FER registers
2518*/
2519
2520
2521#define PJ0 0x0001
2522#define PJ1 0x0002
2523#define PJ2 0x0004
2524#define PJ3 0x0008
2525#define PJ4 0x0010
2526#define PJ5 0x0020
2527#define PJ6 0x0040
2528#define PJ7 0x0080
2529#define PJ8 0x0100
2530#define PJ9 0x0200
2531#define PJ10 0x0400
2532#define PJ11 0x0800
2533#define PJ12 0x1000
2534#define PJ13 0x2000
2535
2536
2537/* Port Muxing Bit Fields for PORTx_MUX Registers */ 2234/* Port Muxing Bit Fields for PORTx_MUX Registers */
2538 2235
2539#define MUX0 0x00000003 2236#define MUX0 0x00000003
@@ -2703,16 +2400,4 @@ PORTJ_FER registers
2703#define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */ 2400#define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */
2704#define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */ 2401#define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */
2705 2402
2706
2707/* for legacy compatibility */
2708
2709#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
2710#define W1LMAX_MAX W1LMAX_MIN
2711#define EBIU_AMCBCTL0 EBIU_AMBCTL0
2712#define EBIU_AMCBCTL1 EBIU_AMBCTL1
2713#define PINT0_IRQ PINT0_REQUEST
2714#define PINT1_IRQ PINT1_REQUEST
2715#define PINT2_IRQ PINT2_REQUEST
2716#define PINT3_IRQ PINT3_REQUEST
2717
2718#endif /* _DEF_BF54X_H */ 2403#endif /* _DEF_BF54X_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/gpio.h b/arch/blackfin/mach-bf548/include/mach/gpio.h
index 28037e331964..7db433514e3f 100644
--- a/arch/blackfin/mach-bf548/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf548/include/mach/gpio.h
@@ -200,4 +200,15 @@ struct gpio_port_s {
200 200
201#endif 201#endif
202 202
203#include <mach-common/ports-a.h>
204#include <mach-common/ports-b.h>
205#include <mach-common/ports-c.h>
206#include <mach-common/ports-d.h>
207#include <mach-common/ports-e.h>
208#include <mach-common/ports-f.h>
209#include <mach-common/ports-g.h>
210#include <mach-common/ports-h.h>
211#include <mach-common/ports-i.h>
212#include <mach-common/ports-j.h>
213
203#endif /* _MACH_GPIO_H_ */ 214#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h
index 1f99b51a3d56..99fd1b2c53d8 100644
--- a/arch/blackfin/mach-bf548/include/mach/irq.h
+++ b/arch/blackfin/mach-bf548/include/mach/irq.h
@@ -474,4 +474,26 @@ Events (highest priority) EMU 0
474#define IRQ_PINT2_POS 24 474#define IRQ_PINT2_POS 24
475#define IRQ_PINT3_POS 28 475#define IRQ_PINT3_POS 28
476 476
477#ifndef __ASSEMBLY__
478#include <linux/types.h>
479
480/*
481 * bfin pint registers layout
482 */
483struct bfin_pint_regs {
484 u32 mask_set;
485 u32 mask_clear;
486 u32 irq;
487 u32 assign;
488 u32 edge_set;
489 u32 edge_clear;
490 u32 invert_set;
491 u32 invert_clear;
492 u32 pinstate;
493 u32 latch;
494 u32 __pad0[2];
495};
496
497#endif
498
477#endif /* _BF548_IRQ_H_ */ 499#endif /* _BF548_IRQ_H_ */
diff --git a/arch/blackfin/mach-bf548/include/mach/pll.h b/arch/blackfin/mach-bf548/include/mach/pll.h
index 7865a090d333..94cca674d835 100644
--- a/arch/blackfin/mach-bf548/include/mach/pll.h
+++ b/arch/blackfin/mach-bf548/include/mach/pll.h
@@ -1,69 +1 @@
1/* #include <mach-common/pll.h>
2 * Copyright 2007-2008 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr0, iwr1, iwr2;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 flags = hard_local_irq_save();
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr0 = bfin_read32(SIC_IWR0);
24 iwr1 = bfin_read32(SIC_IWR1);
25 iwr2 = bfin_read32(SIC_IWR2);
26 /* Only allow PPL Wakeup) */
27 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
28 bfin_write32(SIC_IWR1, 0);
29 bfin_write32(SIC_IWR2, 0);
30
31 bfin_write16(PLL_CTL, val);
32 SSYNC();
33 asm("IDLE;");
34
35 bfin_write32(SIC_IWR0, iwr0);
36 bfin_write32(SIC_IWR1, iwr1);
37 bfin_write32(SIC_IWR2, iwr2);
38 hard_local_irq_restore(flags);
39}
40
41/* Writing to VR_CTL initiates a PLL relock sequence. */
42static __inline__ void bfin_write_VR_CTL(unsigned int val)
43{
44 unsigned long flags, iwr0, iwr1, iwr2;
45
46 if (val == bfin_read_VR_CTL())
47 return;
48
49 flags = hard_local_irq_save();
50 /* Enable the PLL Wakeup bit in SIC IWR */
51 iwr0 = bfin_read32(SIC_IWR0);
52 iwr1 = bfin_read32(SIC_IWR1);
53 iwr2 = bfin_read32(SIC_IWR2);
54 /* Only allow PPL Wakeup) */
55 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
56 bfin_write32(SIC_IWR1, 0);
57 bfin_write32(SIC_IWR2, 0);
58
59 bfin_write16(VR_CTL, val);
60 SSYNC();
61 asm("IDLE;");
62
63 bfin_write32(SIC_IWR0, iwr0);
64 bfin_write32(SIC_IWR1, iwr1);
65 bfin_write32(SIC_IWR2, iwr2);
66 hard_local_irq_restore(flags);
67}
68
69#endif /* _MACH_PLL_H */
diff --git a/arch/blackfin/mach-bf561/atomic.S b/arch/blackfin/mach-bf561/atomic.S
index f99f174b129f..52d6f73fcced 100644
--- a/arch/blackfin/mach-bf561/atomic.S
+++ b/arch/blackfin/mach-bf561/atomic.S
@@ -49,6 +49,7 @@ ENTRY(_get_core_lock)
49 jump .Lretry_corelock 49 jump .Lretry_corelock
50.Ldone_corelock: 50.Ldone_corelock:
51 p0 = r1; 51 p0 = r1;
52 /* flush core internal write buffer before invalidate dcache */
52 CSYNC(r2); 53 CSYNC(r2);
53 flushinv[p0]; 54 flushinv[p0];
54 SSYNC(r2); 55 SSYNC(r2);
@@ -685,6 +686,8 @@ ENTRY(___raw_atomic_test_asm)
685 r1 = -L1_CACHE_BYTES; 686 r1 = -L1_CACHE_BYTES;
686 r1 = r0 & r1; 687 r1 = r0 & r1;
687 p0 = r1; 688 p0 = r1;
689 /* flush core internal write buffer before invalidate dcache */
690 CSYNC(r2);
688 flushinv[p0]; 691 flushinv[p0];
689 SSYNC(r2); 692 SSYNC(r2);
690 r0 = [p1]; 693 r0 = [p1];
@@ -907,6 +910,8 @@ ENTRY(___raw_uncached_fetch_asm)
907 r1 = -L1_CACHE_BYTES; 910 r1 = -L1_CACHE_BYTES;
908 r1 = r0 & r1; 911 r1 = r0 & r1;
909 p0 = r1; 912 p0 = r1;
913 /* flush core internal write buffer before invalidate dcache */
914 CSYNC(r2);
910 flushinv[p0]; 915 flushinv[p0];
911 SSYNC(r2); 916 SSYNC(r2);
912 r0 = [p1]; 917 r0 = [p1];
diff --git a/arch/blackfin/mach-bf561/boards/acvilon.c b/arch/blackfin/mach-bf561/boards/acvilon.c
index 0b1c20f14fe0..3926cd909b66 100644
--- a/arch/blackfin/mach-bf561/boards/acvilon.c
+++ b/arch/blackfin/mach-bf561/boards/acvilon.c
@@ -224,7 +224,7 @@ static struct resource bfin_uart0_resources[] = {
224 }, 224 },
225}; 225};
226 226
227unsigned short bfin_uart0_peripherals[] = { 227static unsigned short bfin_uart0_peripherals[] = {
228 P_UART0_TX, P_UART0_RX, 0 228 P_UART0_TX, P_UART0_RX, 0
229}; 229};
230 230
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c
index 087b6b05cc73..3b67929d4c0a 100644
--- a/arch/blackfin/mach-bf561/boards/cm_bf561.c
+++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c
@@ -334,7 +334,7 @@ static struct resource bfin_uart0_resources[] = {
334 }, 334 },
335}; 335};
336 336
337unsigned short bfin_uart0_peripherals[] = { 337static unsigned short bfin_uart0_peripherals[] = {
338 P_UART0_TX, P_UART0_RX, 0 338 P_UART0_TX, P_UART0_RX, 0
339}; 339};
340 340
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
index ab7a487975fd..f667e7704197 100644
--- a/arch/blackfin/mach-bf561/boards/ezkit.c
+++ b/arch/blackfin/mach-bf561/boards/ezkit.c
@@ -190,7 +190,7 @@ static struct resource bfin_uart0_resources[] = {
190 }, 190 },
191}; 191};
192 192
193unsigned short bfin_uart0_peripherals[] = { 193static unsigned short bfin_uart0_peripherals[] = {
194 P_UART0_TX, P_UART0_RX, 0 194 P_UART0_TX, P_UART0_RX, 0
195}; 195};
196 196
diff --git a/arch/blackfin/mach-bf561/boards/tepla.c b/arch/blackfin/mach-bf561/boards/tepla.c
index d3017e53686b..bb056e60f6ed 100644
--- a/arch/blackfin/mach-bf561/boards/tepla.c
+++ b/arch/blackfin/mach-bf561/boards/tepla.c
@@ -72,7 +72,7 @@ static struct resource bfin_uart0_resources[] = {
72 }, 72 },
73}; 73};
74 74
75unsigned short bfin_uart0_peripherals[] = { 75static unsigned short bfin_uart0_peripherals[] = {
76 P_UART0_TX, P_UART0_RX, 0 76 P_UART0_TX, P_UART0_RX, 0
77}; 77};
78 78
diff --git a/arch/blackfin/mach-bf561/dma.c b/arch/blackfin/mach-bf561/dma.c
index c938c3c7355d..8ffdd6b4a242 100644
--- a/arch/blackfin/mach-bf561/dma.c
+++ b/arch/blackfin/mach-bf561/dma.c
@@ -11,7 +11,7 @@
11#include <asm/blackfin.h> 11#include <asm/blackfin.h>
12#include <asm/dma.h> 12#include <asm/dma.h>
13 13
14struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { 14struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
15 (struct dma_register *) DMA1_0_NEXT_DESC_PTR, 15 (struct dma_register *) DMA1_0_NEXT_DESC_PTR,
16 (struct dma_register *) DMA1_1_NEXT_DESC_PTR, 16 (struct dma_register *) DMA1_1_NEXT_DESC_PTR,
17 (struct dma_register *) DMA1_2_NEXT_DESC_PTR, 17 (struct dma_register *) DMA1_2_NEXT_DESC_PTR,
@@ -36,14 +36,14 @@ struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
36 (struct dma_register *) DMA2_9_NEXT_DESC_PTR, 36 (struct dma_register *) DMA2_9_NEXT_DESC_PTR,
37 (struct dma_register *) DMA2_10_NEXT_DESC_PTR, 37 (struct dma_register *) DMA2_10_NEXT_DESC_PTR,
38 (struct dma_register *) DMA2_11_NEXT_DESC_PTR, 38 (struct dma_register *) DMA2_11_NEXT_DESC_PTR,
39 (struct dma_register *) MDMA1_D0_NEXT_DESC_PTR, 39 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
40 (struct dma_register *) MDMA1_S0_NEXT_DESC_PTR, 40 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
41 (struct dma_register *) MDMA1_D1_NEXT_DESC_PTR, 41 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
42 (struct dma_register *) MDMA1_S1_NEXT_DESC_PTR, 42 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
43 (struct dma_register *) MDMA2_D0_NEXT_DESC_PTR, 43 (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
44 (struct dma_register *) MDMA2_S0_NEXT_DESC_PTR, 44 (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
45 (struct dma_register *) MDMA2_D1_NEXT_DESC_PTR, 45 (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
46 (struct dma_register *) MDMA2_S1_NEXT_DESC_PTR, 46 (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
47 (struct dma_register *) IMDMA_D0_NEXT_DESC_PTR, 47 (struct dma_register *) IMDMA_D0_NEXT_DESC_PTR,
48 (struct dma_register *) IMDMA_S0_NEXT_DESC_PTR, 48 (struct dma_register *) IMDMA_S0_NEXT_DESC_PTR,
49 (struct dma_register *) IMDMA_D1_NEXT_DESC_PTR, 49 (struct dma_register *) IMDMA_D1_NEXT_DESC_PTR,
diff --git a/arch/blackfin/mach-bf561/hotplug.c b/arch/blackfin/mach-bf561/hotplug.c
index c95169b612dc..4cd3b28cd046 100644
--- a/arch/blackfin/mach-bf561/hotplug.c
+++ b/arch/blackfin/mach-bf561/hotplug.c
@@ -6,7 +6,9 @@
6 */ 6 */
7 7
8#include <asm/blackfin.h> 8#include <asm/blackfin.h>
9#include <asm/irq.h>
9#include <asm/smp.h> 10#include <asm/smp.h>
11
10#define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1)) 12#define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
11 13
12int hotplug_coreb; 14int hotplug_coreb;
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
index 4c108c99cb6e..6a3499b02097 100644
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h
@@ -181,7 +181,11 @@
181/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ 181/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
182#define ANOMALY_05000254 (__SILICON_REVISION__ > 3) 182#define ANOMALY_05000254 (__SILICON_REVISION__ > 3)
183/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ 183/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
184#define ANOMALY_05000257 (__SILICON_REVISION__ < 5) 184/* Tempoary work around for kgdb bug 6333 in SMP kernel. It looks coreb hangs in exception
185 * without handling anomaly 05000257 properly on bf561 v0.5. This work around may change
186 * after the behavior and the root cause are confirmed with hardware team.
187 */
188#define ANOMALY_05000257 (__SILICON_REVISION__ < 5 || (__SILICON_REVISION__ == 5 && CONFIG_SMP))
185/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */ 189/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
186#define ANOMALY_05000258 (__SILICON_REVISION__ < 5) 190#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
187/* ICPLB_STATUS MMR Register May Be Corrupted */ 191/* ICPLB_STATUS MMR Register May Be Corrupted */
diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_serial.h b/arch/blackfin/mach-bf561/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..08072c86d5dc
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/bfin_serial.h
@@ -0,0 +1,14 @@
1/*
2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
3 *
4 * Copyright 2006-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_MACH_SERIAL_H__
10#define __BFIN_MACH_SERIAL_H__
11
12#define BFIN_UART_NR_PORTS 1
13
14#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
index e33e158bc16d..3a6947456cf1 100644
--- a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
@@ -4,36 +4,9 @@
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
6 6
7#include <linux/serial.h>
8#include <asm/dma.h> 7#include <asm/dma.h>
9#include <asm/portmux.h> 8#include <asm/portmux.h>
10 9
11#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
12#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
13#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
14#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
15#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
16#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
17#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
18
19#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
20#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
21#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
22#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
23#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
24#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
25#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
26#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
27
28#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
29#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
30
31#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
32#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
33#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
34#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
35#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
36
37#ifdef CONFIG_BFIN_UART0_CTSRTS 10#ifdef CONFIG_BFIN_UART0_CTSRTS
38# define CONFIG_SERIAL_BFIN_CTSRTS 11# define CONFIG_SERIAL_BFIN_CTSRTS
39# ifndef CONFIG_UART0_CTS_PIN 12# ifndef CONFIG_UART0_CTS_PIN
@@ -44,51 +17,6 @@
44# endif 17# endif
45#endif 18#endif
46 19
47#define BFIN_UART_TX_FIFO_SIZE 2
48
49struct bfin_serial_port {
50 struct uart_port port;
51 unsigned int old_status;
52 int status_irq;
53 unsigned int lsr;
54#ifdef CONFIG_SERIAL_BFIN_DMA
55 int tx_done;
56 int tx_count;
57 struct circ_buf rx_dma_buf;
58 struct timer_list rx_dma_timer;
59 int rx_dma_nrows;
60 unsigned int tx_dma_channel;
61 unsigned int rx_dma_channel;
62 struct work_struct tx_dma_workqueue;
63#else
64# if ANOMALY_05000363
65 unsigned int anomaly_threshold;
66# endif
67#endif
68#ifdef CONFIG_SERIAL_BFIN_CTSRTS
69 struct timer_list cts_timer;
70 int cts_pin;
71 int rts_pin;
72#endif
73};
74
75/* The hardware clears the LSR bits upon read, so we need to cache
76 * some of the more fun bits in software so they don't get lost
77 * when checking the LSR in other code paths (TX).
78 */
79static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
80{
81 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
82 uart->lsr |= (lsr & (BI|FE|PE|OE));
83 return lsr | uart->lsr;
84}
85
86static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
87{
88 uart->lsr = 0;
89 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
90}
91
92struct bfin_serial_res { 20struct bfin_serial_res {
93 unsigned long uart_base_addr; 21 unsigned long uart_base_addr;
94 int uart_irq; 22 int uart_irq;
@@ -120,3 +48,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
120}; 48};
121 49
122#define DRIVER_NAME "bfin-uart" 50#define DRIVER_NAME "bfin-uart"
51
52#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf561/include/mach/blackfin.h b/arch/blackfin/mach-bf561/include/mach/blackfin.h
index 6c7dc58c018c..dc470534c085 100644
--- a/arch/blackfin/mach-bf561/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf561/include/mach/blackfin.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2005-2009 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
@@ -10,11 +10,14 @@
10#define BF561_FAMILY 10#define BF561_FAMILY
11 11
12#include "bf561.h" 12#include "bf561.h"
13#include "defBF561.h"
14#include "anomaly.h" 13#include "anomaly.h"
15 14
16#if !defined(__ASSEMBLY__) 15#include <asm/def_LPBlackfin.h>
17#include "cdefBF561.h" 16#include "defBF561.h"
17
18#ifndef __ASSEMBLY__
19# include <asm/cdef_LPBlackfin.h>
20# include "cdefBF561.h"
18#endif 21#endif
19 22
20#define bfin_read_FIO_FLAG_D() bfin_read_FIO0_FLAG_D() 23#define bfin_read_FIO_FLAG_D() bfin_read_FIO0_FLAG_D()
@@ -35,19 +38,4 @@
35#define bfin_read_SICB_ISR(x) bfin_read32(__SIC_MUX(SICB_ISR0, x)) 38#define bfin_read_SICB_ISR(x) bfin_read32(__SIC_MUX(SICB_ISR0, x))
36#define bfin_write_SICB_ISR(x, val) bfin_write32(__SIC_MUX(SICB_ISR0, x), val) 39#define bfin_write_SICB_ISR(x, val) bfin_write32(__SIC_MUX(SICB_ISR0, x), val)
37 40
38#define BFIN_UART_NR_PORTS 1
39
40#define OFFSET_THR 0x00 /* Transmit Holding register */
41#define OFFSET_RBR 0x00 /* Receive Buffer register */
42#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
43#define OFFSET_IER 0x04 /* Interrupt Enable Register */
44#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
45#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
46#define OFFSET_LCR 0x0C /* Line Control Register */
47#define OFFSET_MCR 0x10 /* Modem Control Register */
48#define OFFSET_LSR 0x14 /* Line Status Register */
49#define OFFSET_MSR 0x18 /* Modem Status Register */
50#define OFFSET_SCR 0x1C /* SCR Scratch Register */
51#define OFFSET_GCTL 0x24 /* Global Control Register */
52
53#endif /* _MACH_BLACKFIN_H_ */ 41#endif /* _MACH_BLACKFIN_H_ */
diff --git a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
index 2bab99152495..753331597207 100644
--- a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2005-2009 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
@@ -7,14 +7,6 @@
7#ifndef _CDEF_BF561_H 7#ifndef _CDEF_BF561_H
8#define _CDEF_BF561_H 8#define _CDEF_BF561_H
9 9
10#include <asm/blackfin.h>
11
12/* include all Core registers and bit definitions */
13#include "defBF561.h"
14
15/*include core specific register pointer definitions*/
16#include <asm/cdef_LPBlackfin.h>
17
18/*********************************************************************************** */ 10/*********************************************************************************** */
19/* System MMR Register Map */ 11/* System MMR Register Map */
20/*********************************************************************************** */ 12/*********************************************************************************** */
@@ -523,14 +515,14 @@
523#define bfin_read_PPI1_FRAME() bfin_read16(PPI1_FRAME) 515#define bfin_read_PPI1_FRAME() bfin_read16(PPI1_FRAME)
524#define bfin_write_PPI1_FRAME(val) bfin_write16(PPI1_FRAME,val) 516#define bfin_write_PPI1_FRAME(val) bfin_write16(PPI1_FRAME,val)
525/*DMA traffic control registers */ 517/*DMA traffic control registers */
526#define bfin_read_DMA1_TC_PER() bfin_read16(DMA1_TC_PER) 518#define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER)
527#define bfin_write_DMA1_TC_PER(val) bfin_write16(DMA1_TC_PER,val) 519#define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER,val)
528#define bfin_read_DMA1_TC_CNT() bfin_read16(DMA1_TC_CNT) 520#define bfin_read_DMAC0_TC_CNT() bfin_read16(DMAC0_TC_CNT)
529#define bfin_write_DMA1_TC_CNT(val) bfin_write16(DMA1_TC_CNT,val) 521#define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT,val)
530#define bfin_read_DMA2_TC_PER() bfin_read16(DMA2_TC_PER) 522#define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER)
531#define bfin_write_DMA2_TC_PER(val) bfin_write16(DMA2_TC_PER,val) 523#define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER,val)
532#define bfin_read_DMA2_TC_CNT() bfin_read16(DMA2_TC_CNT) 524#define bfin_read_DMAC1_TC_CNT() bfin_read16(DMAC1_TC_CNT)
533#define bfin_write_DMA2_TC_CNT(val) bfin_write16(DMA2_TC_CNT,val) 525#define bfin_write_DMAC1_TC_CNT(val) bfin_write16(DMAC1_TC_CNT,val)
534/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */ 526/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
535#define bfin_read_DMA1_0_CONFIG() bfin_read16(DMA1_0_CONFIG) 527#define bfin_read_DMA1_0_CONFIG() bfin_read16(DMA1_0_CONFIG)
536#define bfin_write_DMA1_0_CONFIG(val) bfin_write16(DMA1_0_CONFIG,val) 528#define bfin_write_DMA1_0_CONFIG(val) bfin_write16(DMA1_0_CONFIG,val)
@@ -845,110 +837,110 @@
845#define bfin_read_DMA1_11_PERIPHERAL_MAP() bfin_read16(DMA1_11_PERIPHERAL_MAP) 837#define bfin_read_DMA1_11_PERIPHERAL_MAP() bfin_read16(DMA1_11_PERIPHERAL_MAP)
846#define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP,val) 838#define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP,val)
847/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */ 839/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
848#define bfin_read_MDMA1_D0_CONFIG() bfin_read16(MDMA1_D0_CONFIG) 840#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
849#define bfin_write_MDMA1_D0_CONFIG(val) bfin_write16(MDMA1_D0_CONFIG,val) 841#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG,val)
850#define bfin_read_MDMA1_D0_NEXT_DESC_PTR() bfin_read32(MDMA1_D0_NEXT_DESC_PTR) 842#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_read32(MDMA_D2_NEXT_DESC_PTR)
851#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA1_D0_NEXT_DESC_PTR,val) 843#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR,val)
852#define bfin_read_MDMA1_D0_START_ADDR() bfin_read32(MDMA1_D0_START_ADDR) 844#define bfin_read_MDMA_D2_START_ADDR() bfin_read32(MDMA_D2_START_ADDR)
853#define bfin_write_MDMA1_D0_START_ADDR(val) bfin_write32(MDMA1_D0_START_ADDR,val) 845#define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR,val)
854#define bfin_read_MDMA1_D0_X_COUNT() bfin_read16(MDMA1_D0_X_COUNT) 846#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
855#define bfin_write_MDMA1_D0_X_COUNT(val) bfin_write16(MDMA1_D0_X_COUNT,val) 847#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT,val)
856#define bfin_read_MDMA1_D0_Y_COUNT() bfin_read16(MDMA1_D0_Y_COUNT) 848#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
857#define bfin_write_MDMA1_D0_Y_COUNT(val) bfin_write16(MDMA1_D0_Y_COUNT,val) 849#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT,val)
858#define bfin_read_MDMA1_D0_X_MODIFY() bfin_read16(MDMA1_D0_X_MODIFY) 850#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
859#define bfin_write_MDMA1_D0_X_MODIFY(val) bfin_write16(MDMA1_D0_X_MODIFY,val) 851#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY,val)
860#define bfin_read_MDMA1_D0_Y_MODIFY() bfin_read16(MDMA1_D0_Y_MODIFY) 852#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
861#define bfin_write_MDMA1_D0_Y_MODIFY(val) bfin_write16(MDMA1_D0_Y_MODIFY,val) 853#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY,val)
862#define bfin_read_MDMA1_D0_CURR_DESC_PTR() bfin_read32(MDMA1_D0_CURR_DESC_PTR) 854#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_read32(MDMA_D2_CURR_DESC_PTR)
863#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_write32(MDMA1_D0_CURR_DESC_PTR,val) 855#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR,val)
864#define bfin_read_MDMA1_D0_CURR_ADDR() bfin_read32(MDMA1_D0_CURR_ADDR) 856#define bfin_read_MDMA_D2_CURR_ADDR() bfin_read32(MDMA_D2_CURR_ADDR)
865#define bfin_write_MDMA1_D0_CURR_ADDR(val) bfin_write32(MDMA1_D0_CURR_ADDR,val) 857#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR,val)
866#define bfin_read_MDMA1_D0_CURR_X_COUNT() bfin_read16(MDMA1_D0_CURR_X_COUNT) 858#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
867#define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT,val) 859#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT,val)
868#define bfin_read_MDMA1_D0_CURR_Y_COUNT() bfin_read16(MDMA1_D0_CURR_Y_COUNT) 860#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
869#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT,val) 861#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT,val)
870#define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS) 862#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
871#define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS,val) 863#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS,val)
872#define bfin_read_MDMA1_D0_PERIPHERAL_MAP() bfin_read16(MDMA1_D0_PERIPHERAL_MAP) 864#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
873#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP,val) 865#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP,val)
874#define bfin_read_MDMA1_S0_CONFIG() bfin_read16(MDMA1_S0_CONFIG) 866#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
875#define bfin_write_MDMA1_S0_CONFIG(val) bfin_write16(MDMA1_S0_CONFIG,val) 867#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG,val)
876#define bfin_read_MDMA1_S0_NEXT_DESC_PTR() bfin_read32(MDMA1_S0_NEXT_DESC_PTR) 868#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_read32(MDMA_S2_NEXT_DESC_PTR)
877#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA1_S0_NEXT_DESC_PTR,val) 869#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR,val)
878#define bfin_read_MDMA1_S0_START_ADDR() bfin_read32(MDMA1_S0_START_ADDR) 870#define bfin_read_MDMA_S2_START_ADDR() bfin_read32(MDMA_S2_START_ADDR)
879#define bfin_write_MDMA1_S0_START_ADDR(val) bfin_write32(MDMA1_S0_START_ADDR,val) 871#define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR,val)
880#define bfin_read_MDMA1_S0_X_COUNT() bfin_read16(MDMA1_S0_X_COUNT) 872#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
881#define bfin_write_MDMA1_S0_X_COUNT(val) bfin_write16(MDMA1_S0_X_COUNT,val) 873#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT,val)
882#define bfin_read_MDMA1_S0_Y_COUNT() bfin_read16(MDMA1_S0_Y_COUNT) 874#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
883#define bfin_write_MDMA1_S0_Y_COUNT(val) bfin_write16(MDMA1_S0_Y_COUNT,val) 875#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT,val)
884#define bfin_read_MDMA1_S0_X_MODIFY() bfin_read16(MDMA1_S0_X_MODIFY) 876#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
885#define bfin_write_MDMA1_S0_X_MODIFY(val) bfin_write16(MDMA1_S0_X_MODIFY,val) 877#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY,val)
886#define bfin_read_MDMA1_S0_Y_MODIFY() bfin_read16(MDMA1_S0_Y_MODIFY) 878#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
887#define bfin_write_MDMA1_S0_Y_MODIFY(val) bfin_write16(MDMA1_S0_Y_MODIFY,val) 879#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY,val)
888#define bfin_read_MDMA1_S0_CURR_DESC_PTR() bfin_read32(MDMA1_S0_CURR_DESC_PTR) 880#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_read32(MDMA_S2_CURR_DESC_PTR)
889#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_write32(MDMA1_S0_CURR_DESC_PTR,val) 881#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR,val)
890#define bfin_read_MDMA1_S0_CURR_ADDR() bfin_read32(MDMA1_S0_CURR_ADDR) 882#define bfin_read_MDMA_S2_CURR_ADDR() bfin_read32(MDMA_S2_CURR_ADDR)
891#define bfin_write_MDMA1_S0_CURR_ADDR(val) bfin_write32(MDMA1_S0_CURR_ADDR,val) 883#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR,val)
892#define bfin_read_MDMA1_S0_CURR_X_COUNT() bfin_read16(MDMA1_S0_CURR_X_COUNT) 884#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
893#define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT,val) 885#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT,val)
894#define bfin_read_MDMA1_S0_CURR_Y_COUNT() bfin_read16(MDMA1_S0_CURR_Y_COUNT) 886#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
895#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT,val) 887#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT,val)
896#define bfin_read_MDMA1_S0_IRQ_STATUS() bfin_read16(MDMA1_S0_IRQ_STATUS) 888#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
897#define bfin_write_MDMA1_S0_IRQ_STATUS(val) bfin_write16(MDMA1_S0_IRQ_STATUS,val) 889#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS,val)
898#define bfin_read_MDMA1_S0_PERIPHERAL_MAP() bfin_read16(MDMA1_S0_PERIPHERAL_MAP) 890#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
899#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP,val) 891#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP,val)
900#define bfin_read_MDMA1_D1_CONFIG() bfin_read16(MDMA1_D1_CONFIG) 892#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
901#define bfin_write_MDMA1_D1_CONFIG(val) bfin_write16(MDMA1_D1_CONFIG,val) 893#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG,val)
902#define bfin_read_MDMA1_D1_NEXT_DESC_PTR() bfin_read32(MDMA1_D1_NEXT_DESC_PTR) 894#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_read32(MDMA_D3_NEXT_DESC_PTR)
903#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_D1_NEXT_DESC_PTR,val) 895#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR,val)
904#define bfin_read_MDMA1_D1_START_ADDR() bfin_read32(MDMA1_D1_START_ADDR) 896#define bfin_read_MDMA_D3_START_ADDR() bfin_read32(MDMA_D3_START_ADDR)
905#define bfin_write_MDMA1_D1_START_ADDR(val) bfin_write32(MDMA1_D1_START_ADDR,val) 897#define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR,val)
906#define bfin_read_MDMA1_D1_X_COUNT() bfin_read16(MDMA1_D1_X_COUNT) 898#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
907#define bfin_write_MDMA1_D1_X_COUNT(val) bfin_write16(MDMA1_D1_X_COUNT,val) 899#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT,val)
908#define bfin_read_MDMA1_D1_Y_COUNT() bfin_read16(MDMA1_D1_Y_COUNT) 900#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
909#define bfin_write_MDMA1_D1_Y_COUNT(val) bfin_write16(MDMA1_D1_Y_COUNT,val) 901#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT,val)
910#define bfin_read_MDMA1_D1_X_MODIFY() bfin_read16(MDMA1_D1_X_MODIFY) 902#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
911#define bfin_write_MDMA1_D1_X_MODIFY(val) bfin_write16(MDMA1_D1_X_MODIFY,val) 903#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY,val)
912#define bfin_read_MDMA1_D1_Y_MODIFY() bfin_read16(MDMA1_D1_Y_MODIFY) 904#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
913#define bfin_write_MDMA1_D1_Y_MODIFY(val) bfin_write16(MDMA1_D1_Y_MODIFY,val) 905#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY,val)
914#define bfin_read_MDMA1_D1_CURR_DESC_PTR() bfin_read32(MDMA1_D1_CURR_DESC_PTR) 906#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_read32(MDMA_D3_CURR_DESC_PTR)
915#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_write32(MDMA1_D1_CURR_DESC_PTR,val) 907#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR,val)
916#define bfin_read_MDMA1_D1_CURR_ADDR() bfin_read32(MDMA1_D1_CURR_ADDR) 908#define bfin_read_MDMA_D3_CURR_ADDR() bfin_read32(MDMA_D3_CURR_ADDR)
917#define bfin_write_MDMA1_D1_CURR_ADDR(val) bfin_write32(MDMA1_D1_CURR_ADDR,val) 909#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR,val)
918#define bfin_read_MDMA1_D1_CURR_X_COUNT() bfin_read16(MDMA1_D1_CURR_X_COUNT) 910#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
919#define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT,val) 911#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT,val)
920#define bfin_read_MDMA1_D1_CURR_Y_COUNT() bfin_read16(MDMA1_D1_CURR_Y_COUNT) 912#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
921#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT,val) 913#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT,val)
922#define bfin_read_MDMA1_D1_IRQ_STATUS() bfin_read16(MDMA1_D1_IRQ_STATUS) 914#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
923#define bfin_write_MDMA1_D1_IRQ_STATUS(val) bfin_write16(MDMA1_D1_IRQ_STATUS,val) 915#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS,val)
924#define bfin_read_MDMA1_D1_PERIPHERAL_MAP() bfin_read16(MDMA1_D1_PERIPHERAL_MAP) 916#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
925#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP,val) 917#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP,val)
926#define bfin_read_MDMA1_S1_CONFIG() bfin_read16(MDMA1_S1_CONFIG) 918#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
927#define bfin_write_MDMA1_S1_CONFIG(val) bfin_write16(MDMA1_S1_CONFIG,val) 919#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG,val)
928#define bfin_read_MDMA1_S1_NEXT_DESC_PTR() bfin_read32(MDMA1_S1_NEXT_DESC_PTR) 920#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_read32(MDMA_S3_NEXT_DESC_PTR)
929#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_S1_NEXT_DESC_PTR,val) 921#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR,val)
930#define bfin_read_MDMA1_S1_START_ADDR() bfin_read32(MDMA1_S1_START_ADDR) 922#define bfin_read_MDMA_S3_START_ADDR() bfin_read32(MDMA_S3_START_ADDR)
931#define bfin_write_MDMA1_S1_START_ADDR(val) bfin_write32(MDMA1_S1_START_ADDR,val) 923#define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR,val)
932#define bfin_read_MDMA1_S1_X_COUNT() bfin_read16(MDMA1_S1_X_COUNT) 924#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
933#define bfin_write_MDMA1_S1_X_COUNT(val) bfin_write16(MDMA1_S1_X_COUNT,val) 925#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT,val)
934#define bfin_read_MDMA1_S1_Y_COUNT() bfin_read16(MDMA1_S1_Y_COUNT) 926#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
935#define bfin_write_MDMA1_S1_Y_COUNT(val) bfin_write16(MDMA1_S1_Y_COUNT,val) 927#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT,val)
936#define bfin_read_MDMA1_S1_X_MODIFY() bfin_read16(MDMA1_S1_X_MODIFY) 928#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
937#define bfin_write_MDMA1_S1_X_MODIFY(val) bfin_write16(MDMA1_S1_X_MODIFY,val) 929#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY,val)
938#define bfin_read_MDMA1_S1_Y_MODIFY() bfin_read16(MDMA1_S1_Y_MODIFY) 930#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
939#define bfin_write_MDMA1_S1_Y_MODIFY(val) bfin_write16(MDMA1_S1_Y_MODIFY,val) 931#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY,val)
940#define bfin_read_MDMA1_S1_CURR_DESC_PTR() bfin_read32(MDMA1_S1_CURR_DESC_PTR) 932#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_read32(MDMA_S3_CURR_DESC_PTR)
941#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_write32(MDMA1_S1_CURR_DESC_PTR,val) 933#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR,val)
942#define bfin_read_MDMA1_S1_CURR_ADDR() bfin_read32(MDMA1_S1_CURR_ADDR) 934#define bfin_read_MDMA_S3_CURR_ADDR() bfin_read32(MDMA_S3_CURR_ADDR)
943#define bfin_write_MDMA1_S1_CURR_ADDR(val) bfin_write32(MDMA1_S1_CURR_ADDR,val) 935#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR,val)
944#define bfin_read_MDMA1_S1_CURR_X_COUNT() bfin_read16(MDMA1_S1_CURR_X_COUNT) 936#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
945#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT,val) 937#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT,val)
946#define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT) 938#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
947#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT,val) 939#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT,val)
948#define bfin_read_MDMA1_S1_IRQ_STATUS() bfin_read16(MDMA1_S1_IRQ_STATUS) 940#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
949#define bfin_write_MDMA1_S1_IRQ_STATUS(val) bfin_write16(MDMA1_S1_IRQ_STATUS,val) 941#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS,val)
950#define bfin_read_MDMA1_S1_PERIPHERAL_MAP() bfin_read16(MDMA1_S1_PERIPHERAL_MAP) 942#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
951#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP,val) 943#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP,val)
952/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */ 944/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
953#define bfin_read_DMA2_0_CONFIG() bfin_read16(DMA2_0_CONFIG) 945#define bfin_read_DMA2_0_CONFIG() bfin_read16(DMA2_0_CONFIG)
954#define bfin_write_DMA2_0_CONFIG(val) bfin_write16(DMA2_0_CONFIG,val) 946#define bfin_write_DMA2_0_CONFIG(val) bfin_write16(DMA2_0_CONFIG,val)
@@ -1263,110 +1255,110 @@
1263#define bfin_read_DMA2_11_PERIPHERAL_MAP() bfin_read16(DMA2_11_PERIPHERAL_MAP) 1255#define bfin_read_DMA2_11_PERIPHERAL_MAP() bfin_read16(DMA2_11_PERIPHERAL_MAP)
1264#define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP,val) 1256#define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP,val)
1265/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */ 1257/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
1266#define bfin_read_MDMA2_D0_CONFIG() bfin_read16(MDMA2_D0_CONFIG) 1258#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
1267#define bfin_write_MDMA2_D0_CONFIG(val) bfin_write16(MDMA2_D0_CONFIG,val) 1259#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val)
1268#define bfin_read_MDMA2_D0_NEXT_DESC_PTR() bfin_read32(MDMA2_D0_NEXT_DESC_PTR) 1260#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
1269#define bfin_write_MDMA2_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA2_D0_NEXT_DESC_PTR,val) 1261#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
1270#define bfin_read_MDMA2_D0_START_ADDR() bfin_read32(MDMA2_D0_START_ADDR) 1262#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
1271#define bfin_write_MDMA2_D0_START_ADDR(val) bfin_write32(MDMA2_D0_START_ADDR,val) 1263#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val)
1272#define bfin_read_MDMA2_D0_X_COUNT() bfin_read16(MDMA2_D0_X_COUNT) 1264#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
1273#define bfin_write_MDMA2_D0_X_COUNT(val) bfin_write16(MDMA2_D0_X_COUNT,val) 1265#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val)
1274#define bfin_read_MDMA2_D0_Y_COUNT() bfin_read16(MDMA2_D0_Y_COUNT) 1266#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
1275#define bfin_write_MDMA2_D0_Y_COUNT(val) bfin_write16(MDMA2_D0_Y_COUNT,val) 1267#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val)
1276#define bfin_read_MDMA2_D0_X_MODIFY() bfin_read16(MDMA2_D0_X_MODIFY) 1268#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
1277#define bfin_write_MDMA2_D0_X_MODIFY(val) bfin_write16(MDMA2_D0_X_MODIFY,val) 1269#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val)
1278#define bfin_read_MDMA2_D0_Y_MODIFY() bfin_read16(MDMA2_D0_Y_MODIFY) 1270#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
1279#define bfin_write_MDMA2_D0_Y_MODIFY(val) bfin_write16(MDMA2_D0_Y_MODIFY,val) 1271#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val)
1280#define bfin_read_MDMA2_D0_CURR_DESC_PTR() bfin_read32(MDMA2_D0_CURR_DESC_PTR) 1272#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
1281#define bfin_write_MDMA2_D0_CURR_DESC_PTR(val) bfin_write32(MDMA2_D0_CURR_DESC_PTR,val) 1273#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
1282#define bfin_read_MDMA2_D0_CURR_ADDR() bfin_read32(MDMA2_D0_CURR_ADDR) 1274#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
1283#define bfin_write_MDMA2_D0_CURR_ADDR(val) bfin_write32(MDMA2_D0_CURR_ADDR,val) 1275#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val)
1284#define bfin_read_MDMA2_D0_CURR_X_COUNT() bfin_read16(MDMA2_D0_CURR_X_COUNT) 1276#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
1285#define bfin_write_MDMA2_D0_CURR_X_COUNT(val) bfin_write16(MDMA2_D0_CURR_X_COUNT,val) 1277#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
1286#define bfin_read_MDMA2_D0_CURR_Y_COUNT() bfin_read16(MDMA2_D0_CURR_Y_COUNT) 1278#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
1287#define bfin_write_MDMA2_D0_CURR_Y_COUNT(val) bfin_write16(MDMA2_D0_CURR_Y_COUNT,val) 1279#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
1288#define bfin_read_MDMA2_D0_IRQ_STATUS() bfin_read16(MDMA2_D0_IRQ_STATUS) 1280#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
1289#define bfin_write_MDMA2_D0_IRQ_STATUS(val) bfin_write16(MDMA2_D0_IRQ_STATUS,val) 1281#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val)
1290#define bfin_read_MDMA2_D0_PERIPHERAL_MAP() bfin_read16(MDMA2_D0_PERIPHERAL_MAP) 1282#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
1291#define bfin_write_MDMA2_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D0_PERIPHERAL_MAP,val) 1283#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
1292#define bfin_read_MDMA2_S0_CONFIG() bfin_read16(MDMA2_S0_CONFIG) 1284#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
1293#define bfin_write_MDMA2_S0_CONFIG(val) bfin_write16(MDMA2_S0_CONFIG,val) 1285#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val)
1294#define bfin_read_MDMA2_S0_NEXT_DESC_PTR() bfin_read32(MDMA2_S0_NEXT_DESC_PTR) 1286#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
1295#define bfin_write_MDMA2_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA2_S0_NEXT_DESC_PTR,val) 1287#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
1296#define bfin_read_MDMA2_S0_START_ADDR() bfin_read32(MDMA2_S0_START_ADDR) 1288#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
1297#define bfin_write_MDMA2_S0_START_ADDR(val) bfin_write32(MDMA2_S0_START_ADDR,val) 1289#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val)
1298#define bfin_read_MDMA2_S0_X_COUNT() bfin_read16(MDMA2_S0_X_COUNT) 1290#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
1299#define bfin_write_MDMA2_S0_X_COUNT(val) bfin_write16(MDMA2_S0_X_COUNT,val) 1291#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val)
1300#define bfin_read_MDMA2_S0_Y_COUNT() bfin_read16(MDMA2_S0_Y_COUNT) 1292#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
1301#define bfin_write_MDMA2_S0_Y_COUNT(val) bfin_write16(MDMA2_S0_Y_COUNT,val) 1293#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val)
1302#define bfin_read_MDMA2_S0_X_MODIFY() bfin_read16(MDMA2_S0_X_MODIFY) 1294#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
1303#define bfin_write_MDMA2_S0_X_MODIFY(val) bfin_write16(MDMA2_S0_X_MODIFY,val) 1295#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val)
1304#define bfin_read_MDMA2_S0_Y_MODIFY() bfin_read16(MDMA2_S0_Y_MODIFY) 1296#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
1305#define bfin_write_MDMA2_S0_Y_MODIFY(val) bfin_write16(MDMA2_S0_Y_MODIFY,val) 1297#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val)
1306#define bfin_read_MDMA2_S0_CURR_DESC_PTR() bfin_read32(MDMA2_S0_CURR_DESC_PTR) 1298#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
1307#define bfin_write_MDMA2_S0_CURR_DESC_PTR(val) bfin_write32(MDMA2_S0_CURR_DESC_PTR,val) 1299#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
1308#define bfin_read_MDMA2_S0_CURR_ADDR() bfin_read32(MDMA2_S0_CURR_ADDR) 1300#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
1309#define bfin_write_MDMA2_S0_CURR_ADDR(val) bfin_write32(MDMA2_S0_CURR_ADDR,val) 1301#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val)
1310#define bfin_read_MDMA2_S0_CURR_X_COUNT() bfin_read16(MDMA2_S0_CURR_X_COUNT) 1302#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
1311#define bfin_write_MDMA2_S0_CURR_X_COUNT(val) bfin_write16(MDMA2_S0_CURR_X_COUNT,val) 1303#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
1312#define bfin_read_MDMA2_S0_CURR_Y_COUNT() bfin_read16(MDMA2_S0_CURR_Y_COUNT) 1304#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
1313#define bfin_write_MDMA2_S0_CURR_Y_COUNT(val) bfin_write16(MDMA2_S0_CURR_Y_COUNT,val) 1305#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
1314#define bfin_read_MDMA2_S0_IRQ_STATUS() bfin_read16(MDMA2_S0_IRQ_STATUS) 1306#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
1315#define bfin_write_MDMA2_S0_IRQ_STATUS(val) bfin_write16(MDMA2_S0_IRQ_STATUS,val) 1307#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val)
1316#define bfin_read_MDMA2_S0_PERIPHERAL_MAP() bfin_read16(MDMA2_S0_PERIPHERAL_MAP) 1308#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
1317#define bfin_write_MDMA2_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S0_PERIPHERAL_MAP,val) 1309#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
1318#define bfin_read_MDMA2_D1_CONFIG() bfin_read16(MDMA2_D1_CONFIG) 1310#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
1319#define bfin_write_MDMA2_D1_CONFIG(val) bfin_write16(MDMA2_D1_CONFIG,val) 1311#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val)
1320#define bfin_read_MDMA2_D1_NEXT_DESC_PTR() bfin_read32(MDMA2_D1_NEXT_DESC_PTR) 1312#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
1321#define bfin_write_MDMA2_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA2_D1_NEXT_DESC_PTR,val) 1313#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
1322#define bfin_read_MDMA2_D1_START_ADDR() bfin_read32(MDMA2_D1_START_ADDR) 1314#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
1323#define bfin_write_MDMA2_D1_START_ADDR(val) bfin_write32(MDMA2_D1_START_ADDR,val) 1315#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val)
1324#define bfin_read_MDMA2_D1_X_COUNT() bfin_read16(MDMA2_D1_X_COUNT) 1316#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
1325#define bfin_write_MDMA2_D1_X_COUNT(val) bfin_write16(MDMA2_D1_X_COUNT,val) 1317#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val)
1326#define bfin_read_MDMA2_D1_Y_COUNT() bfin_read16(MDMA2_D1_Y_COUNT) 1318#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
1327#define bfin_write_MDMA2_D1_Y_COUNT(val) bfin_write16(MDMA2_D1_Y_COUNT,val) 1319#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val)
1328#define bfin_read_MDMA2_D1_X_MODIFY() bfin_read16(MDMA2_D1_X_MODIFY) 1320#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
1329#define bfin_write_MDMA2_D1_X_MODIFY(val) bfin_write16(MDMA2_D1_X_MODIFY,val) 1321#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val)
1330#define bfin_read_MDMA2_D1_Y_MODIFY() bfin_read16(MDMA2_D1_Y_MODIFY) 1322#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
1331#define bfin_write_MDMA2_D1_Y_MODIFY(val) bfin_write16(MDMA2_D1_Y_MODIFY,val) 1323#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val)
1332#define bfin_read_MDMA2_D1_CURR_DESC_PTR() bfin_read32(MDMA2_D1_CURR_DESC_PTR) 1324#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
1333#define bfin_write_MDMA2_D1_CURR_DESC_PTR(val) bfin_write32(MDMA2_D1_CURR_DESC_PTR,val) 1325#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
1334#define bfin_read_MDMA2_D1_CURR_ADDR() bfin_read32(MDMA2_D1_CURR_ADDR) 1326#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
1335#define bfin_write_MDMA2_D1_CURR_ADDR(val) bfin_write32(MDMA2_D1_CURR_ADDR,val) 1327#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val)
1336#define bfin_read_MDMA2_D1_CURR_X_COUNT() bfin_read16(MDMA2_D1_CURR_X_COUNT) 1328#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
1337#define bfin_write_MDMA2_D1_CURR_X_COUNT(val) bfin_write16(MDMA2_D1_CURR_X_COUNT,val) 1329#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
1338#define bfin_read_MDMA2_D1_CURR_Y_COUNT() bfin_read16(MDMA2_D1_CURR_Y_COUNT) 1330#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
1339#define bfin_write_MDMA2_D1_CURR_Y_COUNT(val) bfin_write16(MDMA2_D1_CURR_Y_COUNT,val) 1331#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
1340#define bfin_read_MDMA2_D1_IRQ_STATUS() bfin_read16(MDMA2_D1_IRQ_STATUS) 1332#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
1341#define bfin_write_MDMA2_D1_IRQ_STATUS(val) bfin_write16(MDMA2_D1_IRQ_STATUS,val) 1333#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val)
1342#define bfin_read_MDMA2_D1_PERIPHERAL_MAP() bfin_read16(MDMA2_D1_PERIPHERAL_MAP) 1334#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
1343#define bfin_write_MDMA2_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D1_PERIPHERAL_MAP,val) 1335#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
1344#define bfin_read_MDMA2_S1_CONFIG() bfin_read16(MDMA2_S1_CONFIG) 1336#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
1345#define bfin_write_MDMA2_S1_CONFIG(val) bfin_write16(MDMA2_S1_CONFIG,val) 1337#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val)
1346#define bfin_read_MDMA2_S1_NEXT_DESC_PTR() bfin_read32(MDMA2_S1_NEXT_DESC_PTR) 1338#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
1347#define bfin_write_MDMA2_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA2_S1_NEXT_DESC_PTR,val) 1339#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
1348#define bfin_read_MDMA2_S1_START_ADDR() bfin_read32(MDMA2_S1_START_ADDR) 1340#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
1349#define bfin_write_MDMA2_S1_START_ADDR(val) bfin_write32(MDMA2_S1_START_ADDR,val) 1341#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val)
1350#define bfin_read_MDMA2_S1_X_COUNT() bfin_read16(MDMA2_S1_X_COUNT) 1342#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
1351#define bfin_write_MDMA2_S1_X_COUNT(val) bfin_write16(MDMA2_S1_X_COUNT,val) 1343#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val)
1352#define bfin_read_MDMA2_S1_Y_COUNT() bfin_read16(MDMA2_S1_Y_COUNT) 1344#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
1353#define bfin_write_MDMA2_S1_Y_COUNT(val) bfin_write16(MDMA2_S1_Y_COUNT,val) 1345#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val)
1354#define bfin_read_MDMA2_S1_X_MODIFY() bfin_read16(MDMA2_S1_X_MODIFY) 1346#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
1355#define bfin_write_MDMA2_S1_X_MODIFY(val) bfin_write16(MDMA2_S1_X_MODIFY,val) 1347#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val)
1356#define bfin_read_MDMA2_S1_Y_MODIFY() bfin_read16(MDMA2_S1_Y_MODIFY) 1348#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
1357#define bfin_write_MDMA2_S1_Y_MODIFY(val) bfin_write16(MDMA2_S1_Y_MODIFY,val) 1349#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val)
1358#define bfin_read_MDMA2_S1_CURR_DESC_PTR() bfin_read32(MDMA2_S1_CURR_DESC_PTR) 1350#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
1359#define bfin_write_MDMA2_S1_CURR_DESC_PTR(val) bfin_write32(MDMA2_S1_CURR_DESC_PTR,val) 1351#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
1360#define bfin_read_MDMA2_S1_CURR_ADDR() bfin_read32(MDMA2_S1_CURR_ADDR) 1352#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
1361#define bfin_write_MDMA2_S1_CURR_ADDR(val) bfin_write32(MDMA2_S1_CURR_ADDR,val) 1353#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val)
1362#define bfin_read_MDMA2_S1_CURR_X_COUNT() bfin_read16(MDMA2_S1_CURR_X_COUNT) 1354#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
1363#define bfin_write_MDMA2_S1_CURR_X_COUNT(val) bfin_write16(MDMA2_S1_CURR_X_COUNT,val) 1355#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
1364#define bfin_read_MDMA2_S1_CURR_Y_COUNT() bfin_read16(MDMA2_S1_CURR_Y_COUNT) 1356#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
1365#define bfin_write_MDMA2_S1_CURR_Y_COUNT(val) bfin_write16(MDMA2_S1_CURR_Y_COUNT,val) 1357#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
1366#define bfin_read_MDMA2_S1_IRQ_STATUS() bfin_read16(MDMA2_S1_IRQ_STATUS) 1358#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
1367#define bfin_write_MDMA2_S1_IRQ_STATUS(val) bfin_write16(MDMA2_S1_IRQ_STATUS,val) 1359#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val)
1368#define bfin_read_MDMA2_S1_PERIPHERAL_MAP() bfin_read16(MDMA2_S1_PERIPHERAL_MAP) 1360#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
1369#define bfin_write_MDMA2_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S1_PERIPHERAL_MAP,val) 1361#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
1370/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */ 1362/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
1371#define bfin_read_IMDMA_D0_CONFIG() bfin_read16(IMDMA_D0_CONFIG) 1363#define bfin_read_IMDMA_D0_CONFIG() bfin_read16(IMDMA_D0_CONFIG)
1372#define bfin_write_IMDMA_D0_CONFIG(val) bfin_write16(IMDMA_D0_CONFIG,val) 1364#define bfin_write_IMDMA_D0_CONFIG(val) bfin_write16(IMDMA_D0_CONFIG,val)
@@ -1465,65 +1457,4 @@
1465#define bfin_read_IMDMA_S1_IRQ_STATUS() bfin_read16(IMDMA_S1_IRQ_STATUS) 1457#define bfin_read_IMDMA_S1_IRQ_STATUS() bfin_read16(IMDMA_S1_IRQ_STATUS)
1466#define bfin_write_IMDMA_S1_IRQ_STATUS(val) bfin_write16(IMDMA_S1_IRQ_STATUS,val) 1458#define bfin_write_IMDMA_S1_IRQ_STATUS(val) bfin_write16(IMDMA_S1_IRQ_STATUS,val)
1467 1459
1468#define bfin_read_MDMA_S0_CONFIG() bfin_read_MDMA1_S0_CONFIG()
1469#define bfin_write_MDMA_S0_CONFIG(val) bfin_write_MDMA1_S0_CONFIG(val)
1470#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read_MDMA1_S0_IRQ_STATUS()
1471#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write_MDMA1_S0_IRQ_STATUS(val)
1472#define bfin_read_MDMA_S0_X_MODIFY() bfin_read_MDMA1_S0_X_MODIFY()
1473#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write_MDMA1_S0_X_MODIFY(val)
1474#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read_MDMA1_S0_Y_MODIFY()
1475#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write_MDMA1_S0_Y_MODIFY(val)
1476#define bfin_read_MDMA_S0_X_COUNT() bfin_read_MDMA1_S0_X_COUNT()
1477#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write_MDMA1_S0_X_COUNT(val)
1478#define bfin_read_MDMA_S0_Y_COUNT() bfin_read_MDMA1_S0_Y_COUNT()
1479#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write_MDMA1_S0_Y_COUNT(val)
1480#define bfin_read_MDMA_S0_START_ADDR() bfin_read_MDMA1_S0_START_ADDR()
1481#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write_MDMA1_S0_START_ADDR(val)
1482#define bfin_read_MDMA_D0_CONFIG() bfin_read_MDMA1_D0_CONFIG()
1483#define bfin_write_MDMA_D0_CONFIG(val) bfin_write_MDMA1_D0_CONFIG(val)
1484#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read_MDMA1_D0_IRQ_STATUS()
1485#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write_MDMA1_D0_IRQ_STATUS(val)
1486#define bfin_read_MDMA_D0_X_MODIFY() bfin_read_MDMA1_D0_X_MODIFY()
1487#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write_MDMA1_D0_X_MODIFY(val)
1488#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read_MDMA1_D0_Y_MODIFY()
1489#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write_MDMA1_D0_Y_MODIFY(val)
1490#define bfin_read_MDMA_D0_X_COUNT() bfin_read_MDMA1_D0_X_COUNT()
1491#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write_MDMA1_D0_X_COUNT(val)
1492#define bfin_read_MDMA_D0_Y_COUNT() bfin_read_MDMA1_D0_Y_COUNT()
1493#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write_MDMA1_D0_Y_COUNT(val)
1494#define bfin_read_MDMA_D0_START_ADDR() bfin_read_MDMA1_D0_START_ADDR()
1495#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA1_D0_START_ADDR(val)
1496
1497#define bfin_read_MDMA_S1_CONFIG() bfin_read_MDMA1_S1_CONFIG()
1498#define bfin_write_MDMA_S1_CONFIG(val) bfin_write_MDMA1_S1_CONFIG(val)
1499#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read_MDMA1_S1_IRQ_STATUS()
1500#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write_MDMA1_S1_IRQ_STATUS(val)
1501#define bfin_read_MDMA_S1_X_MODIFY() bfin_read_MDMA1_S1_X_MODIFY()
1502#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write_MDMA1_S1_X_MODIFY(val)
1503#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read_MDMA1_S1_Y_MODIFY()
1504#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write_MDMA1_S1_Y_MODIFY(val)
1505#define bfin_read_MDMA_S1_X_COUNT() bfin_read_MDMA1_S1_X_COUNT()
1506#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write_MDMA1_S1_X_COUNT(val)
1507#define bfin_read_MDMA_S1_Y_COUNT() bfin_read_MDMA1_S1_Y_COUNT()
1508#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write_MDMA1_S1_Y_COUNT(val)
1509#define bfin_read_MDMA_S1_START_ADDR() bfin_read_MDMA1_S1_START_ADDR()
1510#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write_MDMA1_S1_START_ADDR(val)
1511#define bfin_read_MDMA_D1_CONFIG() bfin_read_MDMA1_D1_CONFIG()
1512#define bfin_write_MDMA_D1_CONFIG(val) bfin_write_MDMA1_D1_CONFIG(val)
1513#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read_MDMA1_D1_IRQ_STATUS()
1514#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write_MDMA1_D1_IRQ_STATUS(val)
1515#define bfin_read_MDMA_D1_X_MODIFY() bfin_read_MDMA1_D1_X_MODIFY()
1516#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write_MDMA1_D1_X_MODIFY(val)
1517#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read_MDMA1_D1_Y_MODIFY()
1518#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write_MDMA1_D1_Y_MODIFY(val)
1519#define bfin_read_MDMA_D1_X_COUNT() bfin_read_MDMA1_D1_X_COUNT()
1520#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write_MDMA1_D1_X_COUNT(val)
1521#define bfin_read_MDMA_D1_Y_COUNT() bfin_read_MDMA1_D1_Y_COUNT()
1522#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write_MDMA1_D1_Y_COUNT(val)
1523#define bfin_read_MDMA_D1_START_ADDR() bfin_read_MDMA1_D1_START_ADDR()
1524#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write_MDMA1_D1_START_ADDR(val)
1525
1526/* These need to be last due to the cdef/linux inter-dependencies */
1527#include <asm/irq.h>
1528
1529#endif /* _CDEF_BF561_H */ 1460#endif /* _CDEF_BF561_H */
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h
index 79e048d452e0..71e805ea74e5 100644
--- a/arch/blackfin/mach-bf561/include/mach/defBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h
@@ -1,18 +1,11 @@
1/* 1/*
2 * Copyright 2005-2009 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#ifndef _DEF_BF561_H 7#ifndef _DEF_BF561_H
8#define _DEF_BF561_H 8#define _DEF_BF561_H
9/*
10#if !defined(__ADSPBF561__)
11#warning defBF561.h should only be included for BF561 chip.
12#endif
13*/
14/* include all Core registers and bit definitions */
15#include <asm/def_LPBlackfin.h>
16 9
17/*********************************************************************************** */ 10/*********************************************************************************** */
18/* System MMR Register Map */ 11/* System MMR Register Map */
@@ -311,10 +304,10 @@
311#define PPI1_FRAME 0xFFC01310 /* PPI1 Frame Length register */ 304#define PPI1_FRAME 0xFFC01310 /* PPI1 Frame Length register */
312 305
313/*DMA traffic control registers */ 306/*DMA traffic control registers */
314#define DMA1_TC_PER 0xFFC01B0C /* Traffic control periods */ 307#define DMAC0_TC_PER 0xFFC00B0C /* Traffic control periods */
315#define DMA1_TC_CNT 0xFFC01B10 /* Traffic control current counts */ 308#define DMAC0_TC_CNT 0xFFC00B10 /* Traffic control current counts */
316#define DMA2_TC_PER 0xFFC00B0C /* Traffic control periods */ 309#define DMAC1_TC_PER 0xFFC01B0C /* Traffic control periods */
317#define DMA2_TC_CNT 0xFFC00B10 /* Traffic control current counts */ 310#define DMAC1_TC_CNT 0xFFC01B10 /* Traffic control current counts */
318 311
319/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */ 312/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
320#define DMA1_0_CONFIG 0xFFC01C08 /* DMA1 Channel 0 Configuration register */ 313#define DMA1_0_CONFIG 0xFFC01C08 /* DMA1 Channel 0 Configuration register */
@@ -486,61 +479,61 @@
486#define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC /* DMA1 Channel 11 Peripheral Map Register */ 479#define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC /* DMA1 Channel 11 Peripheral Map Register */
487 480
488/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */ 481/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
489#define MDMA1_D0_CONFIG 0xFFC01F08 /*MemDMA1 Stream 0 Destination Configuration */ 482#define MDMA_D2_CONFIG 0xFFC01F08 /*MemDMA1 Stream 0 Destination Configuration */
490#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00 /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */ 483#define MDMA_D2_NEXT_DESC_PTR 0xFFC01F00 /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */
491#define MDMA1_D0_START_ADDR 0xFFC01F04 /*MemDMA1 Stream 0 Destination Start Address */ 484#define MDMA_D2_START_ADDR 0xFFC01F04 /*MemDMA1 Stream 0 Destination Start Address */
492#define MDMA1_D0_X_COUNT 0xFFC01F10 /*MemDMA1 Stream 0 Destination Inner-Loop Count */ 485#define MDMA_D2_X_COUNT 0xFFC01F10 /*MemDMA1 Stream 0 Destination Inner-Loop Count */
493#define MDMA1_D0_Y_COUNT 0xFFC01F18 /*MemDMA1 Stream 0 Destination Outer-Loop Count */ 486#define MDMA_D2_Y_COUNT 0xFFC01F18 /*MemDMA1 Stream 0 Destination Outer-Loop Count */
494#define MDMA1_D0_X_MODIFY 0xFFC01F14 /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */ 487#define MDMA_D2_X_MODIFY 0xFFC01F14 /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */
495#define MDMA1_D0_Y_MODIFY 0xFFC01F1C /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */ 488#define MDMA_D2_Y_MODIFY 0xFFC01F1C /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */
496#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20 /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */ 489#define MDMA_D2_CURR_DESC_PTR 0xFFC01F20 /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */
497#define MDMA1_D0_CURR_ADDR 0xFFC01F24 /*MemDMA1 Stream 0 Destination Current Address */ 490#define MDMA_D2_CURR_ADDR 0xFFC01F24 /*MemDMA1 Stream 0 Destination Current Address */
498#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30 /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */ 491#define MDMA_D2_CURR_X_COUNT 0xFFC01F30 /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */
499#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38 /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */ 492#define MDMA_D2_CURR_Y_COUNT 0xFFC01F38 /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */
500#define MDMA1_D0_IRQ_STATUS 0xFFC01F28 /*MemDMA1 Stream 0 Destination Interrupt/Status */ 493#define MDMA_D2_IRQ_STATUS 0xFFC01F28 /*MemDMA1 Stream 0 Destination Interrupt/Status */
501#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C /*MemDMA1 Stream 0 Destination Peripheral Map */ 494#define MDMA_D2_PERIPHERAL_MAP 0xFFC01F2C /*MemDMA1 Stream 0 Destination Peripheral Map */
502 495
503#define MDMA1_S0_CONFIG 0xFFC01F48 /*MemDMA1 Stream 0 Source Configuration */ 496#define MDMA_S2_CONFIG 0xFFC01F48 /*MemDMA1 Stream 0 Source Configuration */
504#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40 /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */ 497#define MDMA_S2_NEXT_DESC_PTR 0xFFC01F40 /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */
505#define MDMA1_S0_START_ADDR 0xFFC01F44 /*MemDMA1 Stream 0 Source Start Address */ 498#define MDMA_S2_START_ADDR 0xFFC01F44 /*MemDMA1 Stream 0 Source Start Address */
506#define MDMA1_S0_X_COUNT 0xFFC01F50 /*MemDMA1 Stream 0 Source Inner-Loop Count */ 499#define MDMA_S2_X_COUNT 0xFFC01F50 /*MemDMA1 Stream 0 Source Inner-Loop Count */
507#define MDMA1_S0_Y_COUNT 0xFFC01F58 /*MemDMA1 Stream 0 Source Outer-Loop Count */ 500#define MDMA_S2_Y_COUNT 0xFFC01F58 /*MemDMA1 Stream 0 Source Outer-Loop Count */
508#define MDMA1_S0_X_MODIFY 0xFFC01F54 /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */ 501#define MDMA_S2_X_MODIFY 0xFFC01F54 /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */
509#define MDMA1_S0_Y_MODIFY 0xFFC01F5C /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */ 502#define MDMA_S2_Y_MODIFY 0xFFC01F5C /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */
510#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60 /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */ 503#define MDMA_S2_CURR_DESC_PTR 0xFFC01F60 /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */
511#define MDMA1_S0_CURR_ADDR 0xFFC01F64 /*MemDMA1 Stream 0 Source Current Address */ 504#define MDMA_S2_CURR_ADDR 0xFFC01F64 /*MemDMA1 Stream 0 Source Current Address */
512#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70 /*MemDMA1 Stream 0 Source Current Inner-Loop Count */ 505#define MDMA_S2_CURR_X_COUNT 0xFFC01F70 /*MemDMA1 Stream 0 Source Current Inner-Loop Count */
513#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78 /*MemDMA1 Stream 0 Source Current Outer-Loop Count */ 506#define MDMA_S2_CURR_Y_COUNT 0xFFC01F78 /*MemDMA1 Stream 0 Source Current Outer-Loop Count */
514#define MDMA1_S0_IRQ_STATUS 0xFFC01F68 /*MemDMA1 Stream 0 Source Interrupt/Status */ 507#define MDMA_S2_IRQ_STATUS 0xFFC01F68 /*MemDMA1 Stream 0 Source Interrupt/Status */
515#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C /*MemDMA1 Stream 0 Source Peripheral Map */ 508#define MDMA_S2_PERIPHERAL_MAP 0xFFC01F6C /*MemDMA1 Stream 0 Source Peripheral Map */
516 509
517#define MDMA1_D1_CONFIG 0xFFC01F88 /*MemDMA1 Stream 1 Destination Configuration */ 510#define MDMA_D3_CONFIG 0xFFC01F88 /*MemDMA1 Stream 1 Destination Configuration */
518#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80 /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */ 511#define MDMA_D3_NEXT_DESC_PTR 0xFFC01F80 /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */
519#define MDMA1_D1_START_ADDR 0xFFC01F84 /*MemDMA1 Stream 1 Destination Start Address */ 512#define MDMA_D3_START_ADDR 0xFFC01F84 /*MemDMA1 Stream 1 Destination Start Address */
520#define MDMA1_D1_X_COUNT 0xFFC01F90 /*MemDMA1 Stream 1 Destination Inner-Loop Count */ 513#define MDMA_D3_X_COUNT 0xFFC01F90 /*MemDMA1 Stream 1 Destination Inner-Loop Count */
521#define MDMA1_D1_Y_COUNT 0xFFC01F98 /*MemDMA1 Stream 1 Destination Outer-Loop Count */ 514#define MDMA_D3_Y_COUNT 0xFFC01F98 /*MemDMA1 Stream 1 Destination Outer-Loop Count */
522#define MDMA1_D1_X_MODIFY 0xFFC01F94 /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */ 515#define MDMA_D3_X_MODIFY 0xFFC01F94 /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */
523#define MDMA1_D1_Y_MODIFY 0xFFC01F9C /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */ 516#define MDMA_D3_Y_MODIFY 0xFFC01F9C /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */
524#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0 /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */ 517#define MDMA_D3_CURR_DESC_PTR 0xFFC01FA0 /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */
525#define MDMA1_D1_CURR_ADDR 0xFFC01FA4 /*MemDMA1 Stream 1 Dest Current Address */ 518#define MDMA_D3_CURR_ADDR 0xFFC01FA4 /*MemDMA1 Stream 1 Dest Current Address */
526#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0 /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */ 519#define MDMA_D3_CURR_X_COUNT 0xFFC01FB0 /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */
527#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8 /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */ 520#define MDMA_D3_CURR_Y_COUNT 0xFFC01FB8 /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */
528#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8 /*MemDMA1 Stream 1 Dest Interrupt/Status */ 521#define MDMA_D3_IRQ_STATUS 0xFFC01FA8 /*MemDMA1 Stream 1 Dest Interrupt/Status */
529#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC /*MemDMA1 Stream 1 Dest Peripheral Map */ 522#define MDMA_D3_PERIPHERAL_MAP 0xFFC01FAC /*MemDMA1 Stream 1 Dest Peripheral Map */
530 523
531#define MDMA1_S1_CONFIG 0xFFC01FC8 /*MemDMA1 Stream 1 Source Configuration */ 524#define MDMA_S3_CONFIG 0xFFC01FC8 /*MemDMA1 Stream 1 Source Configuration */
532#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0 /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */ 525#define MDMA_S3_NEXT_DESC_PTR 0xFFC01FC0 /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */
533#define MDMA1_S1_START_ADDR 0xFFC01FC4 /*MemDMA1 Stream 1 Source Start Address */ 526#define MDMA_S3_START_ADDR 0xFFC01FC4 /*MemDMA1 Stream 1 Source Start Address */
534#define MDMA1_S1_X_COUNT 0xFFC01FD0 /*MemDMA1 Stream 1 Source Inner-Loop Count */ 527#define MDMA_S3_X_COUNT 0xFFC01FD0 /*MemDMA1 Stream 1 Source Inner-Loop Count */
535#define MDMA1_S1_Y_COUNT 0xFFC01FD8 /*MemDMA1 Stream 1 Source Outer-Loop Count */ 528#define MDMA_S3_Y_COUNT 0xFFC01FD8 /*MemDMA1 Stream 1 Source Outer-Loop Count */
536#define MDMA1_S1_X_MODIFY 0xFFC01FD4 /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */ 529#define MDMA_S3_X_MODIFY 0xFFC01FD4 /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */
537#define MDMA1_S1_Y_MODIFY 0xFFC01FDC /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */ 530#define MDMA_S3_Y_MODIFY 0xFFC01FDC /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */
538#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0 /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */ 531#define MDMA_S3_CURR_DESC_PTR 0xFFC01FE0 /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */
539#define MDMA1_S1_CURR_ADDR 0xFFC01FE4 /*MemDMA1 Stream 1 Source Current Address */ 532#define MDMA_S3_CURR_ADDR 0xFFC01FE4 /*MemDMA1 Stream 1 Source Current Address */
540#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0 /*MemDMA1 Stream 1 Source Current Inner-Loop Count */ 533#define MDMA_S3_CURR_X_COUNT 0xFFC01FF0 /*MemDMA1 Stream 1 Source Current Inner-Loop Count */
541#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8 /*MemDMA1 Stream 1 Source Current Outer-Loop Count */ 534#define MDMA_S3_CURR_Y_COUNT 0xFFC01FF8 /*MemDMA1 Stream 1 Source Current Outer-Loop Count */
542#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8 /*MemDMA1 Stream 1 Source Interrupt/Status */ 535#define MDMA_S3_IRQ_STATUS 0xFFC01FE8 /*MemDMA1 Stream 1 Source Interrupt/Status */
543#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC /*MemDMA1 Stream 1 Source Peripheral Map */ 536#define MDMA_S3_PERIPHERAL_MAP 0xFFC01FEC /*MemDMA1 Stream 1 Source Peripheral Map */
544 537
545/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */ 538/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
546#define DMA2_0_CONFIG 0xFFC00C08 /* DMA2 Channel 0 Configuration register */ 539#define DMA2_0_CONFIG 0xFFC00C08 /* DMA2 Channel 0 Configuration register */
@@ -712,117 +705,61 @@
712#define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC /* DMA2 Channel 11 Peripheral Map Register */ 705#define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC /* DMA2 Channel 11 Peripheral Map Register */
713 706
714/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */ 707/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
715#define MDMA2_D0_CONFIG 0xFFC00F08 /*MemDMA2 Stream 0 Destination Configuration register */ 708#define MDMA_D0_CONFIG 0xFFC00F08 /*MemDMA2 Stream 0 Destination Configuration register */
716#define MDMA2_D0_NEXT_DESC_PTR 0xFFC00F00 /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */ 709#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */
717#define MDMA2_D0_START_ADDR 0xFFC00F04 /*MemDMA2 Stream 0 Destination Start Address */ 710#define MDMA_D0_START_ADDR 0xFFC00F04 /*MemDMA2 Stream 0 Destination Start Address */
718#define MDMA2_D0_X_COUNT 0xFFC00F10 /*MemDMA2 Stream 0 Dest Inner-Loop Count register */ 711#define MDMA_D0_X_COUNT 0xFFC00F10 /*MemDMA2 Stream 0 Dest Inner-Loop Count register */
719#define MDMA2_D0_Y_COUNT 0xFFC00F18 /*MemDMA2 Stream 0 Dest Outer-Loop Count register */ 712#define MDMA_D0_Y_COUNT 0xFFC00F18 /*MemDMA2 Stream 0 Dest Outer-Loop Count register */
720#define MDMA2_D0_X_MODIFY 0xFFC00F14 /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */ 713#define MDMA_D0_X_MODIFY 0xFFC00F14 /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */
721#define MDMA2_D0_Y_MODIFY 0xFFC00F1C /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */ 714#define MDMA_D0_Y_MODIFY 0xFFC00F1C /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */
722#define MDMA2_D0_CURR_DESC_PTR 0xFFC00F20 /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */ 715#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */
723#define MDMA2_D0_CURR_ADDR 0xFFC00F24 /*MemDMA2 Stream 0 Destination Current Address */ 716#define MDMA_D0_CURR_ADDR 0xFFC00F24 /*MemDMA2 Stream 0 Destination Current Address */
724#define MDMA2_D0_CURR_X_COUNT 0xFFC00F30 /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */ 717#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */
725#define MDMA2_D0_CURR_Y_COUNT 0xFFC00F38 /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */ 718#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */
726#define MDMA2_D0_IRQ_STATUS 0xFFC00F28 /*MemDMA2 Stream 0 Dest Interrupt/Status Register */ 719#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /*MemDMA2 Stream 0 Dest Interrupt/Status Register */
727#define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C /*MemDMA2 Stream 0 Destination Peripheral Map register */ 720#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /*MemDMA2 Stream 0 Destination Peripheral Map register */
728 721
729#define MDMA2_S0_CONFIG 0xFFC00F48 /*MemDMA2 Stream 0 Source Configuration register */ 722#define MDMA_S0_CONFIG 0xFFC00F48 /*MemDMA2 Stream 0 Source Configuration register */
730#define MDMA2_S0_NEXT_DESC_PTR 0xFFC00F40 /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */ 723#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */
731#define MDMA2_S0_START_ADDR 0xFFC00F44 /*MemDMA2 Stream 0 Source Start Address */ 724#define MDMA_S0_START_ADDR 0xFFC00F44 /*MemDMA2 Stream 0 Source Start Address */
732#define MDMA2_S0_X_COUNT 0xFFC00F50 /*MemDMA2 Stream 0 Source Inner-Loop Count register */ 725#define MDMA_S0_X_COUNT 0xFFC00F50 /*MemDMA2 Stream 0 Source Inner-Loop Count register */
733#define MDMA2_S0_Y_COUNT 0xFFC00F58 /*MemDMA2 Stream 0 Source Outer-Loop Count register */ 726#define MDMA_S0_Y_COUNT 0xFFC00F58 /*MemDMA2 Stream 0 Source Outer-Loop Count register */
734#define MDMA2_S0_X_MODIFY 0xFFC00F54 /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */ 727#define MDMA_S0_X_MODIFY 0xFFC00F54 /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */
735#define MDMA2_S0_Y_MODIFY 0xFFC00F5C /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */ 728#define MDMA_S0_Y_MODIFY 0xFFC00F5C /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */
736#define MDMA2_S0_CURR_DESC_PTR 0xFFC00F60 /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */ 729#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */
737#define MDMA2_S0_CURR_ADDR 0xFFC00F64 /*MemDMA2 Stream 0 Source Current Address */ 730#define MDMA_S0_CURR_ADDR 0xFFC00F64 /*MemDMA2 Stream 0 Source Current Address */
738#define MDMA2_S0_CURR_X_COUNT 0xFFC00F70 /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */ 731#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */
739#define MDMA2_S0_CURR_Y_COUNT 0xFFC00F78 /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */ 732#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */
740#define MDMA2_S0_IRQ_STATUS 0xFFC00F68 /*MemDMA2 Stream 0 Source Interrupt/Status Register */ 733#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /*MemDMA2 Stream 0 Source Interrupt/Status Register */
741#define MDMA2_S0_PERIPHERAL_MAP 0xFFC00F6C /*MemDMA2 Stream 0 Source Peripheral Map register */ 734#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /*MemDMA2 Stream 0 Source Peripheral Map register */
742 735
743#define MDMA2_D1_CONFIG 0xFFC00F88 /*MemDMA2 Stream 1 Destination Configuration register */ 736#define MDMA_D1_CONFIG 0xFFC00F88 /*MemDMA2 Stream 1 Destination Configuration register */
744#define MDMA2_D1_NEXT_DESC_PTR 0xFFC00F80 /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */ 737#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */
745#define MDMA2_D1_START_ADDR 0xFFC00F84 /*MemDMA2 Stream 1 Destination Start Address */ 738#define MDMA_D1_START_ADDR 0xFFC00F84 /*MemDMA2 Stream 1 Destination Start Address */
746#define MDMA2_D1_X_COUNT 0xFFC00F90 /*MemDMA2 Stream 1 Dest Inner-Loop Count register */ 739#define MDMA_D1_X_COUNT 0xFFC00F90 /*MemDMA2 Stream 1 Dest Inner-Loop Count register */
747#define MDMA2_D1_Y_COUNT 0xFFC00F98 /*MemDMA2 Stream 1 Dest Outer-Loop Count register */ 740#define MDMA_D1_Y_COUNT 0xFFC00F98 /*MemDMA2 Stream 1 Dest Outer-Loop Count register */
748#define MDMA2_D1_X_MODIFY 0xFFC00F94 /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */ 741#define MDMA_D1_X_MODIFY 0xFFC00F94 /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */
749#define MDMA2_D1_Y_MODIFY 0xFFC00F9C /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */ 742#define MDMA_D1_Y_MODIFY 0xFFC00F9C /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */
750#define MDMA2_D1_CURR_DESC_PTR 0xFFC00FA0 /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */ 743#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */
751#define MDMA2_D1_CURR_ADDR 0xFFC00FA4 /*MemDMA2 Stream 1 Destination Current Address reg */ 744#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /*MemDMA2 Stream 1 Destination Current Address reg */
752#define MDMA2_D1_CURR_X_COUNT 0xFFC00FB0 /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */ 745#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */
753#define MDMA2_D1_CURR_Y_COUNT 0xFFC00FB8 /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */ 746#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */
754#define MDMA2_D1_IRQ_STATUS 0xFFC00FA8 /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */ 747#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */
755#define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC /*MemDMA2 Stream 1 Destination Peripheral Map register */ 748#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /*MemDMA2 Stream 1 Destination Peripheral Map register */
756 749
757#define MDMA2_S1_CONFIG 0xFFC00FC8 /*MemDMA2 Stream 1 Source Configuration register */ 750#define MDMA_S1_CONFIG 0xFFC00FC8 /*MemDMA2 Stream 1 Source Configuration register */
758#define MDMA2_S1_NEXT_DESC_PTR 0xFFC00FC0 /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */ 751#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */
759#define MDMA2_S1_START_ADDR 0xFFC00FC4 /*MemDMA2 Stream 1 Source Start Address */ 752#define MDMA_S1_START_ADDR 0xFFC00FC4 /*MemDMA2 Stream 1 Source Start Address */
760#define MDMA2_S1_X_COUNT 0xFFC00FD0 /*MemDMA2 Stream 1 Source Inner-Loop Count register */ 753#define MDMA_S1_X_COUNT 0xFFC00FD0 /*MemDMA2 Stream 1 Source Inner-Loop Count register */
761#define MDMA2_S1_Y_COUNT 0xFFC00FD8 /*MemDMA2 Stream 1 Source Outer-Loop Count register */ 754#define MDMA_S1_Y_COUNT 0xFFC00FD8 /*MemDMA2 Stream 1 Source Outer-Loop Count register */
762#define MDMA2_S1_X_MODIFY 0xFFC00FD4 /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */ 755#define MDMA_S1_X_MODIFY 0xFFC00FD4 /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */
763#define MDMA2_S1_Y_MODIFY 0xFFC00FDC /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */ 756#define MDMA_S1_Y_MODIFY 0xFFC00FDC /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */
764#define MDMA2_S1_CURR_DESC_PTR 0xFFC00FE0 /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */ 757#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */
765#define MDMA2_S1_CURR_ADDR 0xFFC00FE4 /*MemDMA2 Stream 1 Source Current Address */ 758#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /*MemDMA2 Stream 1 Source Current Address */
766#define MDMA2_S1_CURR_X_COUNT 0xFFC00FF0 /*MemDMA2 Stream 1 Source Current Inner-Loop Count */ 759#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /*MemDMA2 Stream 1 Source Current Inner-Loop Count */
767#define MDMA2_S1_CURR_Y_COUNT 0xFFC00FF8 /*MemDMA2 Stream 1 Source Current Outer-Loop Count */ 760#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /*MemDMA2 Stream 1 Source Current Outer-Loop Count */
768#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */ 761#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */
769#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */ 762#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */
770
771#define MDMA_D0_NEXT_DESC_PTR MDMA1_D0_NEXT_DESC_PTR
772#define MDMA_D0_START_ADDR MDMA1_D0_START_ADDR
773#define MDMA_D0_CONFIG MDMA1_D0_CONFIG
774#define MDMA_D0_X_COUNT MDMA1_D0_X_COUNT
775#define MDMA_D0_X_MODIFY MDMA1_D0_X_MODIFY
776#define MDMA_D0_Y_COUNT MDMA1_D0_Y_COUNT
777#define MDMA_D0_Y_MODIFY MDMA1_D0_Y_MODIFY
778#define MDMA_D0_CURR_DESC_PTR MDMA1_D0_CURR_DESC_PTR
779#define MDMA_D0_CURR_ADDR MDMA1_D0_CURR_ADDR
780#define MDMA_D0_IRQ_STATUS MDMA1_D0_IRQ_STATUS
781#define MDMA_D0_PERIPHERAL_MAP MDMA1_D0_PERIPHERAL_MAP
782#define MDMA_D0_CURR_X_COUNT MDMA1_D0_CURR_X_COUNT
783#define MDMA_D0_CURR_Y_COUNT MDMA1_D0_CURR_Y_COUNT
784
785#define MDMA_S0_NEXT_DESC_PTR MDMA1_S0_NEXT_DESC_PTR
786#define MDMA_S0_START_ADDR MDMA1_S0_START_ADDR
787#define MDMA_S0_CONFIG MDMA1_S0_CONFIG
788#define MDMA_S0_X_COUNT MDMA1_S0_X_COUNT
789#define MDMA_S0_X_MODIFY MDMA1_S0_X_MODIFY
790#define MDMA_S0_Y_COUNT MDMA1_S0_Y_COUNT
791#define MDMA_S0_Y_MODIFY MDMA1_S0_Y_MODIFY
792#define MDMA_S0_CURR_DESC_PTR MDMA1_S0_CURR_DESC_PTR
793#define MDMA_S0_CURR_ADDR MDMA1_S0_CURR_ADDR
794#define MDMA_S0_IRQ_STATUS MDMA1_S0_IRQ_STATUS
795#define MDMA_S0_PERIPHERAL_MAP MDMA1_S0_PERIPHERAL_MAP
796#define MDMA_S0_CURR_X_COUNT MDMA1_S0_CURR_X_COUNT
797#define MDMA_S0_CURR_Y_COUNT MDMA1_S0_CURR_Y_COUNT
798
799#define MDMA_D1_NEXT_DESC_PTR MDMA1_D1_NEXT_DESC_PTR
800#define MDMA_D1_START_ADDR MDMA1_D1_START_ADDR
801#define MDMA_D1_CONFIG MDMA1_D1_CONFIG
802#define MDMA_D1_X_COUNT MDMA1_D1_X_COUNT
803#define MDMA_D1_X_MODIFY MDMA1_D1_X_MODIFY
804#define MDMA_D1_Y_COUNT MDMA1_D1_Y_COUNT
805#define MDMA_D1_Y_MODIFY MDMA1_D1_Y_MODIFY
806#define MDMA_D1_CURR_DESC_PTR MDMA1_D1_CURR_DESC_PTR
807#define MDMA_D1_CURR_ADDR MDMA1_D1_CURR_ADDR
808#define MDMA_D1_IRQ_STATUS MDMA1_D1_IRQ_STATUS
809#define MDMA_D1_PERIPHERAL_MAP MDMA1_D1_PERIPHERAL_MAP
810#define MDMA_D1_CURR_X_COUNT MDMA1_D1_CURR_X_COUNT
811#define MDMA_D1_CURR_Y_COUNT MDMA1_D1_CURR_Y_COUNT
812
813#define MDMA_S1_NEXT_DESC_PTR MDMA1_S1_NEXT_DESC_PTR
814#define MDMA_S1_START_ADDR MDMA1_S1_START_ADDR
815#define MDMA_S1_CONFIG MDMA1_S1_CONFIG
816#define MDMA_S1_X_COUNT MDMA1_S1_X_COUNT
817#define MDMA_S1_X_MODIFY MDMA1_S1_X_MODIFY
818#define MDMA_S1_Y_COUNT MDMA1_S1_Y_COUNT
819#define MDMA_S1_Y_MODIFY MDMA1_S1_Y_MODIFY
820#define MDMA_S1_CURR_DESC_PTR MDMA1_S1_CURR_DESC_PTR
821#define MDMA_S1_CURR_ADDR MDMA1_S1_CURR_ADDR
822#define MDMA_S1_IRQ_STATUS MDMA1_S1_IRQ_STATUS
823#define MDMA_S1_PERIPHERAL_MAP MDMA1_S1_PERIPHERAL_MAP
824#define MDMA_S1_CURR_X_COUNT MDMA1_S1_CURR_X_COUNT
825#define MDMA_S1_CURR_Y_COUNT MDMA1_S1_CURR_Y_COUNT
826 763
827/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */ 764/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
828#define IMDMA_D0_CONFIG 0xFFC01808 /*IMDMA Stream 0 Destination Configuration */ 765#define IMDMA_D0_CONFIG 0xFFC01808 /*IMDMA Stream 0 Destination Configuration */
@@ -927,83 +864,6 @@
927#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ 864#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
928#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ 865#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
929 866
930/* ***************************** UART CONTROLLER MASKS ********************** */
931
932/* UART_LCR Register */
933
934#define DLAB 0x80
935#define SB 0x40
936#define STP 0x20
937#define EPS 0x10
938#define PEN 0x08
939#define STB 0x04
940#define WLS(x) ((x-5) & 0x03)
941
942#define DLAB_P 0x07
943#define SB_P 0x06
944#define STP_P 0x05
945#define EPS_P 0x04
946#define PEN_P 0x03
947#define STB_P 0x02
948#define WLS_P1 0x01
949#define WLS_P0 0x00
950
951/* UART_MCR Register */
952#define LOOP_ENA 0x10
953#define LOOP_ENA_P 0x04
954
955/* UART_LSR Register */
956#define TEMT 0x40
957#define THRE 0x20
958#define BI 0x10
959#define FE 0x08
960#define PE 0x04
961#define OE 0x02
962#define DR 0x01
963
964#define TEMP_P 0x06
965#define THRE_P 0x05
966#define BI_P 0x04
967#define FE_P 0x03
968#define PE_P 0x02
969#define OE_P 0x01
970#define DR_P 0x00
971
972/* UART_IER Register */
973#define ELSI 0x04
974#define ETBEI 0x02
975#define ERBFI 0x01
976
977#define ELSI_P 0x02
978#define ETBEI_P 0x01
979#define ERBFI_P 0x00
980
981/* UART_IIR Register */
982#define STATUS(x) ((x << 1) & 0x06)
983#define NINT 0x01
984#define STATUS_P1 0x02
985#define STATUS_P0 0x01
986#define NINT_P 0x00
987#define IIR_TX_READY 0x02 /* UART_THR empty */
988#define IIR_RX_READY 0x04 /* Receive data ready */
989#define IIR_LINE_CHANGE 0x06 /* Receive line status */
990#define IIR_STATUS 0x06
991
992/* UART_GCTL Register */
993#define FFE 0x20
994#define FPE 0x10
995#define RPOLC 0x08
996#define TPOLC 0x04
997#define IREN 0x02
998#define UCEN 0x01
999
1000#define FFE_P 0x05
1001#define FPE_P 0x04
1002#define RPOLC_P 0x03
1003#define TPOLC_P 0x02
1004#define IREN_P 0x01
1005#define UCEN_P 0x00
1006
1007/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ 867/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
1008 868
1009/* PPI_CONTROL Masks */ 869/* PPI_CONTROL Masks */
@@ -1230,44 +1090,6 @@
1230#define ERR_TYP_P0 0x0E 1090#define ERR_TYP_P0 0x0E
1231#define ERR_TYP_P1 0x0F 1091#define ERR_TYP_P1 0x0F
1232 1092
1233/*/ ****************** PROGRAMMABLE FLAG MASKS ********************* */
1234
1235/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
1236#define PF0 0x0001
1237#define PF1 0x0002
1238#define PF2 0x0004
1239#define PF3 0x0008
1240#define PF4 0x0010
1241#define PF5 0x0020
1242#define PF6 0x0040
1243#define PF7 0x0080
1244#define PF8 0x0100
1245#define PF9 0x0200
1246#define PF10 0x0400
1247#define PF11 0x0800
1248#define PF12 0x1000
1249#define PF13 0x2000
1250#define PF14 0x4000
1251#define PF15 0x8000
1252
1253/* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */
1254#define PF0_P 0
1255#define PF1_P 1
1256#define PF2_P 2
1257#define PF3_P 3
1258#define PF4_P 4
1259#define PF5_P 5
1260#define PF6_P 6
1261#define PF7_P 7
1262#define PF8_P 8
1263#define PF9_P 9
1264#define PF10_P 10
1265#define PF11_P 11
1266#define PF12_P 12
1267#define PF13_P 13
1268#define PF14_P 14
1269#define PF15_P 15
1270
1271/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ 1093/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
1272 1094
1273/* AMGCTL Masks */ 1095/* AMGCTL Masks */
diff --git a/arch/blackfin/mach-bf561/include/mach/gpio.h b/arch/blackfin/mach-bf561/include/mach/gpio.h
index 4f8aa5d08802..57d5eab59faf 100644
--- a/arch/blackfin/mach-bf561/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf561/include/mach/gpio.h
@@ -62,4 +62,6 @@
62#define PORT_FIO1 GPIO_16 62#define PORT_FIO1 GPIO_16
63#define PORT_FIO2 GPIO_32 63#define PORT_FIO2 GPIO_32
64 64
65#include <mach-common/ports-f.h>
66
65#endif /* _MACH_GPIO_H_ */ 67#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf561/include/mach/mem_map.h b/arch/blackfin/mach-bf561/include/mach/mem_map.h
index 5b96ea549a04..4cc91995f781 100644
--- a/arch/blackfin/mach-bf561/include/mach/mem_map.h
+++ b/arch/blackfin/mach-bf561/include/mach/mem_map.h
@@ -106,7 +106,7 @@
106#define COREA_L1_SCRATCH_START 0xFFB00000 106#define COREA_L1_SCRATCH_START 0xFFB00000
107#define COREB_L1_SCRATCH_START 0xFF700000 107#define COREB_L1_SCRATCH_START 0xFF700000
108 108
109#ifdef __ASSEMBLY__ 109#ifdef CONFIG_SMP
110 110
111/* 111/*
112 * The following macros both return the address of the PDA for the 112 * The following macros both return the address of the PDA for the
@@ -121,8 +121,7 @@
121 * is allowed to use the specified Dreg for determining the PDA 121 * is allowed to use the specified Dreg for determining the PDA
122 * address to be returned into Preg. 122 * address to be returned into Preg.
123 */ 123 */
124#ifdef CONFIG_SMP 124# define GET_PDA_SAFE(preg) \
125#define GET_PDA_SAFE(preg) \
126 preg.l = lo(DSPID); \ 125 preg.l = lo(DSPID); \
127 preg.h = hi(DSPID); \ 126 preg.h = hi(DSPID); \
128 preg = [preg]; \ 127 preg = [preg]; \
@@ -158,7 +157,7 @@
158 preg = [preg]; \ 157 preg = [preg]; \
1594: 1584:
160 159
161#define GET_PDA(preg, dreg) \ 160# define GET_PDA(preg, dreg) \
162 preg.l = lo(DSPID); \ 161 preg.l = lo(DSPID); \
163 preg.h = hi(DSPID); \ 162 preg.h = hi(DSPID); \
164 dreg = [preg]; \ 163 dreg = [preg]; \
@@ -169,13 +168,17 @@
169 preg = [preg]; \ 168 preg = [preg]; \
1701: \ 1691: \
171 170
172#define GET_CPUID(preg, dreg) \ 171# define GET_CPUID(preg, dreg) \
173 preg.l = lo(DSPID); \ 172 preg.l = lo(DSPID); \
174 preg.h = hi(DSPID); \ 173 preg.h = hi(DSPID); \
175 dreg = [preg]; \ 174 dreg = [preg]; \
176 dreg = ROT dreg BY -1; \ 175 dreg = ROT dreg BY -1; \
177 dreg = CC; 176 dreg = CC;
178 177
178# ifndef __ASSEMBLY__
179
180# include <asm/processor.h>
181
179static inline unsigned long get_l1_scratch_start_cpu(int cpu) 182static inline unsigned long get_l1_scratch_start_cpu(int cpu)
180{ 183{
181 return cpu ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START; 184 return cpu ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START;
@@ -210,8 +213,7 @@ static inline unsigned long get_l1_data_b_start(void)
210 return get_l1_data_b_start_cpu(blackfin_core_id()); 213 return get_l1_data_b_start_cpu(blackfin_core_id());
211} 214}
212 215
216# endif /* __ASSEMBLY__ */
213#endif /* CONFIG_SMP */ 217#endif /* CONFIG_SMP */
214 218
215#endif /* __ASSEMBLY__ */
216
217#endif 219#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/pll.h b/arch/blackfin/mach-bf561/include/mach/pll.h
index f2b1fbdb8e72..7977db2f1c12 100644
--- a/arch/blackfin/mach-bf561/include/mach/pll.h
+++ b/arch/blackfin/mach-bf561/include/mach/pll.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2005-2009 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
@@ -7,57 +7,48 @@
7#ifndef _MACH_PLL_H 7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H 8#define _MACH_PLL_H
9 9
10#ifndef __ASSEMBLY__
11
12#ifdef CONFIG_SMP
13
10#include <asm/blackfin.h> 14#include <asm/blackfin.h>
11#include <asm/irqflags.h> 15#include <asm/irqflags.h>
16#include <mach/irq.h>
17
18#define SUPPLE_0_WAKEUP ((IRQ_SUPPLE_0 - (IRQ_CORETMR + 1)) % 32)
12 19
13/* Writing to PLL_CTL initiates a PLL relock sequence. */ 20static inline void
14static __inline__ void bfin_write_PLL_CTL(unsigned int val) 21bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2)
15{ 22{
16 unsigned long flags, iwr0, iwr1; 23 unsigned long SICA_SICB_OFF = ((bfin_read_DSPID() & 0xff) ? 0x1000 : 0);
17 24
18 if (val == bfin_read_PLL_CTL()) 25 bfin_write32(SIC_IWR0 + SICA_SICB_OFF, iwr0);
19 return; 26 bfin_write32(SIC_IWR1 + SICA_SICB_OFF, iwr1);
20
21 flags = hard_local_irq_save();
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr0 = bfin_read32(SICA_IWR0);
24 iwr1 = bfin_read32(SICA_IWR1);
25 /* Only allow PPL Wakeup) */
26 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
27 bfin_write32(SICA_IWR1, 0);
28
29 bfin_write16(PLL_CTL, val);
30 SSYNC();
31 asm("IDLE;");
32
33 bfin_write32(SICA_IWR0, iwr0);
34 bfin_write32(SICA_IWR1, iwr1);
35 hard_local_irq_restore(flags);
36} 27}
28#define bfin_iwr_restore bfin_iwr_restore
37 29
38/* Writing to VR_CTL initiates a PLL relock sequence. */ 30static inline void
39static __inline__ void bfin_write_VR_CTL(unsigned int val) 31bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2,
32 unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
40{ 33{
41 unsigned long flags, iwr0, iwr1; 34 unsigned long SICA_SICB_OFF = ((bfin_read_DSPID() & 0xff) ? 0x1000 : 0);
42 35
43 if (val == bfin_read_VR_CTL()) 36 *iwr0 = bfin_read32(SIC_IWR0 + SICA_SICB_OFF);
44 return; 37 *iwr1 = bfin_read32(SIC_IWR1 + SICA_SICB_OFF);
45 38 bfin_iwr_restore(niwr0, niwr1, niwr2);
46 flags = hard_local_irq_save();
47 /* Enable the PLL Wakeup bit in SIC IWR */
48 iwr0 = bfin_read32(SICA_IWR0);
49 iwr1 = bfin_read32(SICA_IWR1);
50 /* Only allow PPL Wakeup) */
51 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
52 bfin_write32(SICA_IWR1, 0);
53
54 bfin_write16(VR_CTL, val);
55 SSYNC();
56 asm("IDLE;");
57
58 bfin_write32(SICA_IWR0, iwr0);
59 bfin_write32(SICA_IWR1, iwr1);
60 hard_local_irq_restore(flags);
61} 39}
40#define bfin_iwr_save bfin_iwr_save
41
42static inline void
43bfin_iwr_set_sup0(unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
44{
45 bfin_iwr_save(0, IWR_ENABLE(SUPPLE_0_WAKEUP), 0, iwr0, iwr1, iwr2);
46}
47
48#endif
49
50#endif
51
52#include <mach-common/pll.h>
62 53
63#endif /* _MACH_PLL_H */ 54#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/smp.h b/arch/blackfin/mach-bf561/include/mach/smp.h
index 2c8c514dd386..346c60589be6 100644
--- a/arch/blackfin/mach-bf561/include/mach/smp.h
+++ b/arch/blackfin/mach-bf561/include/mach/smp.h
@@ -7,6 +7,8 @@
7#ifndef _MACH_BF561_SMP 7#ifndef _MACH_BF561_SMP
8#define _MACH_BF561_SMP 8#define _MACH_BF561_SMP
9 9
10/* This header has to stand alone to avoid circular deps */
11
10struct task_struct; 12struct task_struct;
11 13
12void platform_init_cpus(void); 14void platform_init_cpus(void);
@@ -17,13 +19,13 @@ int platform_boot_secondary(unsigned int cpu, struct task_struct *idle);
17 19
18void platform_secondary_init(unsigned int cpu); 20void platform_secondary_init(unsigned int cpu);
19 21
20void platform_request_ipi(int (*handler)(int, void *)); 22void platform_request_ipi(int irq, /*irq_handler_t*/ void *handler);
21 23
22void platform_send_ipi(cpumask_t callmap); 24void platform_send_ipi(cpumask_t callmap, int irq);
23 25
24void platform_send_ipi_cpu(unsigned int cpu); 26void platform_send_ipi_cpu(unsigned int cpu, int irq);
25 27
26void platform_clear_ipi(unsigned int cpu); 28void platform_clear_ipi(unsigned int cpu, int irq);
27 29
28void bfin_local_timer_setup(void); 30void bfin_local_timer_setup(void);
29 31
diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c
index f540ed1257d6..1074a7ef81c7 100644
--- a/arch/blackfin/mach-bf561/smp.c
+++ b/arch/blackfin/mach-bf561/smp.c
@@ -86,12 +86,12 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle
86 86
87 spin_lock(&boot_lock); 87 spin_lock(&boot_lock);
88 88
89 if ((bfin_read_SIC_SYSCR() & COREB_SRAM_INIT) == 0) { 89 if ((bfin_read_SYSCR() & COREB_SRAM_INIT) == 0) {
90 /* CoreB already running, sending ipi to wakeup it */ 90 /* CoreB already running, sending ipi to wakeup it */
91 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0); 91 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
92 } else { 92 } else {
93 /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */ 93 /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
94 bfin_write_SIC_SYSCR(bfin_read_SIC_SYSCR() & ~COREB_SRAM_INIT); 94 bfin_write_SYSCR(bfin_read_SYSCR() & ~COREB_SRAM_INIT);
95 SSYNC(); 95 SSYNC();
96 } 96 }
97 97
@@ -111,41 +111,46 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle
111 panic("CPU%u: processor failed to boot\n", cpu); 111 panic("CPU%u: processor failed to boot\n", cpu);
112} 112}
113 113
114void __init platform_request_ipi(irq_handler_t handler) 114static const char supple0[] = "IRQ_SUPPLE_0";
115static const char supple1[] = "IRQ_SUPPLE_1";
116void __init platform_request_ipi(int irq, void *handler)
115{ 117{
116 int ret; 118 int ret;
119 const char *name = (irq == IRQ_SUPPLE_0) ? supple0 : supple1;
117 120
118 ret = request_irq(IRQ_SUPPLE_0, handler, IRQF_DISABLED, 121 ret = request_irq(irq, handler, IRQF_DISABLED | IRQF_PERCPU, name, handler);
119 "Supplemental Interrupt0", handler);
120 if (ret) 122 if (ret)
121 panic("Cannot request supplemental interrupt 0 for IPI service"); 123 panic("Cannot request %s for IPI service", name);
122} 124}
123 125
124void platform_send_ipi(cpumask_t callmap) 126void platform_send_ipi(cpumask_t callmap, int irq)
125{ 127{
126 unsigned int cpu; 128 unsigned int cpu;
129 int offset = (irq == IRQ_SUPPLE_0) ? 6 : 8;
127 130
128 for_each_cpu_mask(cpu, callmap) { 131 for_each_cpu_mask(cpu, callmap) {
129 BUG_ON(cpu >= 2); 132 BUG_ON(cpu >= 2);
130 SSYNC(); 133 SSYNC();
131 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu))); 134 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
132 SSYNC(); 135 SSYNC();
133 } 136 }
134} 137}
135 138
136void platform_send_ipi_cpu(unsigned int cpu) 139void platform_send_ipi_cpu(unsigned int cpu, int irq)
137{ 140{
141 int offset = (irq == IRQ_SUPPLE_0) ? 6 : 8;
138 BUG_ON(cpu >= 2); 142 BUG_ON(cpu >= 2);
139 SSYNC(); 143 SSYNC();
140 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu))); 144 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
141 SSYNC(); 145 SSYNC();
142} 146}
143 147
144void platform_clear_ipi(unsigned int cpu) 148void platform_clear_ipi(unsigned int cpu, int irq)
145{ 149{
150 int offset = (irq == IRQ_SUPPLE_0) ? 10 : 12;
146 BUG_ON(cpu >= 2); 151 BUG_ON(cpu >= 2);
147 SSYNC(); 152 SSYNC();
148 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + cpu))); 153 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
149 SSYNC(); 154 SSYNC();
150} 155}
151 156
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index 2ca915ee181f..bc08c98d008d 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -615,7 +615,7 @@ ENTRY(_system_call)
615#ifdef CONFIG_IPIPE 615#ifdef CONFIG_IPIPE
616 r0 = sp; 616 r0 = sp;
617 SP += -12; 617 SP += -12;
618 call ___ipipe_syscall_root; 618 pseudo_long_call ___ipipe_syscall_root, p0;
619 SP += 12; 619 SP += 12;
620 cc = r0 == 1; 620 cc = r0 == 1;
621 if cc jump .Lsyscall_really_exit; 621 if cc jump .Lsyscall_really_exit;
@@ -692,7 +692,7 @@ ENTRY(_system_call)
692 [--sp] = reti; 692 [--sp] = reti;
693 SP += 4; /* don't merge with next insn to keep the pattern obvious */ 693 SP += 4; /* don't merge with next insn to keep the pattern obvious */
694 SP += -12; 694 SP += -12;
695 call ___ipipe_sync_root; 695 pseudo_long_call ___ipipe_sync_root, p4;
696 SP += 12; 696 SP += 12;
697 jump .Lresume_userspace_1; 697 jump .Lresume_userspace_1;
698.Lsyscall_no_irqsync: 698.Lsyscall_no_irqsync:
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index da7e3c63746b..a604f19d8dc3 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -866,7 +866,6 @@ static void bfin_gpio_unmask_irq(unsigned int irq)
866 u32 pintbit = PINT_BIT(pint_val); 866 u32 pintbit = PINT_BIT(pint_val);
867 u32 bank = PINT_2_BANK(pint_val); 867 u32 bank = PINT_2_BANK(pint_val);
868 868
869 pint[bank]->request = pintbit;
870 pint[bank]->mask_set = pintbit; 869 pint[bank]->mask_set = pintbit;
871} 870}
872 871
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c
index 80884b136a0c..42fa87e8375c 100644
--- a/arch/blackfin/mach-common/pm.c
+++ b/arch/blackfin/mach-common/pm.c
@@ -23,9 +23,6 @@
23 23
24void bfin_pm_suspend_standby_enter(void) 24void bfin_pm_suspend_standby_enter(void)
25{ 25{
26 unsigned long flags;
27
28 flags = hard_local_irq_save();
29 bfin_pm_standby_setup(); 26 bfin_pm_standby_setup();
30 27
31#ifdef CONFIG_PM_BFIN_SLEEP_DEEPER 28#ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
@@ -55,8 +52,6 @@ void bfin_pm_suspend_standby_enter(void)
55#else 52#else
56 bfin_write_SIC_IWR(IWR_DISABLE_ALL); 53 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
57#endif 54#endif
58
59 hard_local_irq_restore(flags);
60} 55}
61 56
62int bf53x_suspend_l1_mem(unsigned char *memptr) 57int bf53x_suspend_l1_mem(unsigned char *memptr)
@@ -127,7 +122,6 @@ static void flushinv_all_dcache(void)
127 122
128int bfin_pm_suspend_mem_enter(void) 123int bfin_pm_suspend_mem_enter(void)
129{ 124{
130 unsigned long flags;
131 int wakeup, ret; 125 int wakeup, ret;
132 126
133 unsigned char *memptr = kmalloc(L1_CODE_LENGTH + L1_DATA_A_LENGTH 127 unsigned char *memptr = kmalloc(L1_CODE_LENGTH + L1_DATA_A_LENGTH
@@ -149,12 +143,9 @@ int bfin_pm_suspend_mem_enter(void)
149 wakeup |= GPWE; 143 wakeup |= GPWE;
150#endif 144#endif
151 145
152 flags = hard_local_irq_save();
153
154 ret = blackfin_dma_suspend(); 146 ret = blackfin_dma_suspend();
155 147
156 if (ret) { 148 if (ret) {
157 hard_local_irq_restore(flags);
158 kfree(memptr); 149 kfree(memptr);
159 return ret; 150 return ret;
160 } 151 }
@@ -178,7 +169,6 @@ int bfin_pm_suspend_mem_enter(void)
178 bfin_gpio_pm_hibernate_restore(); 169 bfin_gpio_pm_hibernate_restore();
179 blackfin_dma_resume(); 170 blackfin_dma_resume();
180 171
181 hard_local_irq_restore(flags);
182 kfree(memptr); 172 kfree(memptr);
183 173
184 return 0; 174 return 0;
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index a17107a700d5..9f251406a76a 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -19,6 +19,7 @@
19#include <linux/mm.h> 19#include <linux/mm.h>
20#include <linux/cpu.h> 20#include <linux/cpu.h>
21#include <linux/smp.h> 21#include <linux/smp.h>
22#include <linux/cpumask.h>
22#include <linux/seq_file.h> 23#include <linux/seq_file.h>
23#include <linux/irq.h> 24#include <linux/irq.h>
24#include <linux/slab.h> 25#include <linux/slab.h>
@@ -43,12 +44,6 @@ void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb,
43 *init_saved_seqstat_coreb, *init_saved_icplb_fault_addr_coreb, 44 *init_saved_seqstat_coreb, *init_saved_icplb_fault_addr_coreb,
44 *init_saved_dcplb_fault_addr_coreb; 45 *init_saved_dcplb_fault_addr_coreb;
45 46
46cpumask_t cpu_possible_map;
47EXPORT_SYMBOL(cpu_possible_map);
48
49cpumask_t cpu_online_map;
50EXPORT_SYMBOL(cpu_online_map);
51
52#define BFIN_IPI_RESCHEDULE 0 47#define BFIN_IPI_RESCHEDULE 0
53#define BFIN_IPI_CALL_FUNC 1 48#define BFIN_IPI_CALL_FUNC 1
54#define BFIN_IPI_CPU_STOP 2 49#define BFIN_IPI_CPU_STOP 2
@@ -65,8 +60,7 @@ struct smp_call_struct {
65 void (*func)(void *info); 60 void (*func)(void *info);
66 void *info; 61 void *info;
67 int wait; 62 int wait;
68 cpumask_t pending; 63 cpumask_t *waitmask;
69 cpumask_t waitmask;
70}; 64};
71 65
72static struct blackfin_flush_data smp_flush_data; 66static struct blackfin_flush_data smp_flush_data;
@@ -74,15 +68,19 @@ static struct blackfin_flush_data smp_flush_data;
74static DEFINE_SPINLOCK(stop_lock); 68static DEFINE_SPINLOCK(stop_lock);
75 69
76struct ipi_message { 70struct ipi_message {
77 struct list_head list;
78 unsigned long type; 71 unsigned long type;
79 struct smp_call_struct call_struct; 72 struct smp_call_struct call_struct;
80}; 73};
81 74
75/* A magic number - stress test shows this is safe for common cases */
76#define BFIN_IPI_MSGQ_LEN 5
77
78/* Simple FIFO buffer, overflow leads to panic */
82struct ipi_message_queue { 79struct ipi_message_queue {
83 struct list_head head;
84 spinlock_t lock; 80 spinlock_t lock;
85 unsigned long count; 81 unsigned long count;
82 unsigned long head; /* head of the queue */
83 struct ipi_message ipi_message[BFIN_IPI_MSGQ_LEN];
86}; 84};
87 85
88static DEFINE_PER_CPU(struct ipi_message_queue, ipi_msg_queue); 86static DEFINE_PER_CPU(struct ipi_message_queue, ipi_msg_queue);
@@ -121,7 +119,6 @@ static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
121 func = msg->call_struct.func; 119 func = msg->call_struct.func;
122 info = msg->call_struct.info; 120 info = msg->call_struct.info;
123 wait = msg->call_struct.wait; 121 wait = msg->call_struct.wait;
124 cpu_clear(cpu, msg->call_struct.pending);
125 func(info); 122 func(info);
126 if (wait) { 123 if (wait) {
127#ifdef __ARCH_SYNC_CORE_DCACHE 124#ifdef __ARCH_SYNC_CORE_DCACHE
@@ -132,51 +129,57 @@ static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
132 */ 129 */
133 resync_core_dcache(); 130 resync_core_dcache();
134#endif 131#endif
135 cpu_clear(cpu, msg->call_struct.waitmask); 132 cpu_clear(cpu, *msg->call_struct.waitmask);
136 } else 133 }
137 kfree(msg); 134}
135
136/* Use IRQ_SUPPLE_0 to request reschedule.
137 * When returning from interrupt to user space,
138 * there is chance to reschedule */
139static irqreturn_t ipi_handler_int0(int irq, void *dev_instance)
140{
141 unsigned int cpu = smp_processor_id();
142
143 platform_clear_ipi(cpu, IRQ_SUPPLE_0);
144 return IRQ_HANDLED;
138} 145}
139 146
140static irqreturn_t ipi_handler(int irq, void *dev_instance) 147static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
141{ 148{
142 struct ipi_message *msg; 149 struct ipi_message *msg;
143 struct ipi_message_queue *msg_queue; 150 struct ipi_message_queue *msg_queue;
144 unsigned int cpu = smp_processor_id(); 151 unsigned int cpu = smp_processor_id();
152 unsigned long flags;
145 153
146 platform_clear_ipi(cpu); 154 platform_clear_ipi(cpu, IRQ_SUPPLE_1);
147 155
148 msg_queue = &__get_cpu_var(ipi_msg_queue); 156 msg_queue = &__get_cpu_var(ipi_msg_queue);
149 msg_queue->count++;
150 157
151 spin_lock(&msg_queue->lock); 158 spin_lock_irqsave(&msg_queue->lock, flags);
152 while (!list_empty(&msg_queue->head)) { 159
153 msg = list_entry(msg_queue->head.next, typeof(*msg), list); 160 while (msg_queue->count) {
154 list_del(&msg->list); 161 msg = &msg_queue->ipi_message[msg_queue->head];
155 switch (msg->type) { 162 switch (msg->type) {
156 case BFIN_IPI_RESCHEDULE:
157 /* That's the easiest one; leave it to
158 * return_from_int. */
159 kfree(msg);
160 break;
161 case BFIN_IPI_CALL_FUNC: 163 case BFIN_IPI_CALL_FUNC:
162 spin_unlock(&msg_queue->lock); 164 spin_unlock_irqrestore(&msg_queue->lock, flags);
163 ipi_call_function(cpu, msg); 165 ipi_call_function(cpu, msg);
164 spin_lock(&msg_queue->lock); 166 spin_lock_irqsave(&msg_queue->lock, flags);
165 break; 167 break;
166 case BFIN_IPI_CPU_STOP: 168 case BFIN_IPI_CPU_STOP:
167 spin_unlock(&msg_queue->lock); 169 spin_unlock_irqrestore(&msg_queue->lock, flags);
168 ipi_cpu_stop(cpu); 170 ipi_cpu_stop(cpu);
169 spin_lock(&msg_queue->lock); 171 spin_lock_irqsave(&msg_queue->lock, flags);
170 kfree(msg);
171 break; 172 break;
172 default: 173 default:
173 printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%lx\n", 174 printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%lx\n",
174 cpu, msg->type); 175 cpu, msg->type);
175 kfree(msg);
176 break; 176 break;
177 } 177 }
178 msg_queue->head++;
179 msg_queue->head %= BFIN_IPI_MSGQ_LEN;
180 msg_queue->count--;
178 } 181 }
179 spin_unlock(&msg_queue->lock); 182 spin_unlock_irqrestore(&msg_queue->lock, flags);
180 return IRQ_HANDLED; 183 return IRQ_HANDLED;
181} 184}
182 185
@@ -186,48 +189,47 @@ static void ipi_queue_init(void)
186 struct ipi_message_queue *msg_queue; 189 struct ipi_message_queue *msg_queue;
187 for_each_possible_cpu(cpu) { 190 for_each_possible_cpu(cpu) {
188 msg_queue = &per_cpu(ipi_msg_queue, cpu); 191 msg_queue = &per_cpu(ipi_msg_queue, cpu);
189 INIT_LIST_HEAD(&msg_queue->head);
190 spin_lock_init(&msg_queue->lock); 192 spin_lock_init(&msg_queue->lock);
191 msg_queue->count = 0; 193 msg_queue->count = 0;
194 msg_queue->head = 0;
192 } 195 }
193} 196}
194 197
195int smp_call_function(void (*func)(void *info), void *info, int wait) 198static inline void smp_send_message(cpumask_t callmap, unsigned long type,
199 void (*func) (void *info), void *info, int wait)
196{ 200{
197 unsigned int cpu; 201 unsigned int cpu;
198 cpumask_t callmap;
199 unsigned long flags;
200 struct ipi_message_queue *msg_queue; 202 struct ipi_message_queue *msg_queue;
201 struct ipi_message *msg; 203 struct ipi_message *msg;
202 204 unsigned long flags, next_msg;
203 callmap = cpu_online_map; 205 cpumask_t waitmask = callmap; /* waitmask is shared by all cpus */
204 cpu_clear(smp_processor_id(), callmap);
205 if (cpus_empty(callmap))
206 return 0;
207
208 msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
209 if (!msg)
210 return -ENOMEM;
211 INIT_LIST_HEAD(&msg->list);
212 msg->call_struct.func = func;
213 msg->call_struct.info = info;
214 msg->call_struct.wait = wait;
215 msg->call_struct.pending = callmap;
216 msg->call_struct.waitmask = callmap;
217 msg->type = BFIN_IPI_CALL_FUNC;
218 206
219 for_each_cpu_mask(cpu, callmap) { 207 for_each_cpu_mask(cpu, callmap) {
220 msg_queue = &per_cpu(ipi_msg_queue, cpu); 208 msg_queue = &per_cpu(ipi_msg_queue, cpu);
221 spin_lock_irqsave(&msg_queue->lock, flags); 209 spin_lock_irqsave(&msg_queue->lock, flags);
222 list_add_tail(&msg->list, &msg_queue->head); 210 if (msg_queue->count < BFIN_IPI_MSGQ_LEN) {
211 next_msg = (msg_queue->head + msg_queue->count)
212 % BFIN_IPI_MSGQ_LEN;
213 msg = &msg_queue->ipi_message[next_msg];
214 msg->type = type;
215 if (type == BFIN_IPI_CALL_FUNC) {
216 msg->call_struct.func = func;
217 msg->call_struct.info = info;
218 msg->call_struct.wait = wait;
219 msg->call_struct.waitmask = &waitmask;
220 }
221 msg_queue->count++;
222 } else
223 panic("IPI message queue overflow\n");
223 spin_unlock_irqrestore(&msg_queue->lock, flags); 224 spin_unlock_irqrestore(&msg_queue->lock, flags);
224 platform_send_ipi_cpu(cpu); 225 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1);
225 } 226 }
227
226 if (wait) { 228 if (wait) {
227 while (!cpus_empty(msg->call_struct.waitmask)) 229 while (!cpus_empty(waitmask))
228 blackfin_dcache_invalidate_range( 230 blackfin_dcache_invalidate_range(
229 (unsigned long)(&msg->call_struct.waitmask), 231 (unsigned long)(&waitmask),
230 (unsigned long)(&msg->call_struct.waitmask)); 232 (unsigned long)(&waitmask));
231#ifdef __ARCH_SYNC_CORE_DCACHE 233#ifdef __ARCH_SYNC_CORE_DCACHE
232 /* 234 /*
233 * Invalidate D cache in case shared data was changed by 235 * Invalidate D cache in case shared data was changed by
@@ -235,8 +237,20 @@ int smp_call_function(void (*func)(void *info), void *info, int wait)
235 */ 237 */
236 resync_core_dcache(); 238 resync_core_dcache();
237#endif 239#endif
238 kfree(msg);
239 } 240 }
241}
242
243int smp_call_function(void (*func)(void *info), void *info, int wait)
244{
245 cpumask_t callmap;
246
247 callmap = cpu_online_map;
248 cpu_clear(smp_processor_id(), callmap);
249 if (cpus_empty(callmap))
250 return 0;
251
252 smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
253
240 return 0; 254 return 0;
241} 255}
242EXPORT_SYMBOL_GPL(smp_call_function); 256EXPORT_SYMBOL_GPL(smp_call_function);
@@ -246,100 +260,39 @@ int smp_call_function_single(int cpuid, void (*func) (void *info), void *info,
246{ 260{
247 unsigned int cpu = cpuid; 261 unsigned int cpu = cpuid;
248 cpumask_t callmap; 262 cpumask_t callmap;
249 unsigned long flags;
250 struct ipi_message_queue *msg_queue;
251 struct ipi_message *msg;
252 263
253 if (cpu_is_offline(cpu)) 264 if (cpu_is_offline(cpu))
254 return 0; 265 return 0;
255 cpus_clear(callmap); 266 cpus_clear(callmap);
256 cpu_set(cpu, callmap); 267 cpu_set(cpu, callmap);
257 268
258 msg = kmalloc(sizeof(*msg), GFP_ATOMIC); 269 smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
259 if (!msg)
260 return -ENOMEM;
261 INIT_LIST_HEAD(&msg->list);
262 msg->call_struct.func = func;
263 msg->call_struct.info = info;
264 msg->call_struct.wait = wait;
265 msg->call_struct.pending = callmap;
266 msg->call_struct.waitmask = callmap;
267 msg->type = BFIN_IPI_CALL_FUNC;
268
269 msg_queue = &per_cpu(ipi_msg_queue, cpu);
270 spin_lock_irqsave(&msg_queue->lock, flags);
271 list_add_tail(&msg->list, &msg_queue->head);
272 spin_unlock_irqrestore(&msg_queue->lock, flags);
273 platform_send_ipi_cpu(cpu);
274 270
275 if (wait) {
276 while (!cpus_empty(msg->call_struct.waitmask))
277 blackfin_dcache_invalidate_range(
278 (unsigned long)(&msg->call_struct.waitmask),
279 (unsigned long)(&msg->call_struct.waitmask));
280#ifdef __ARCH_SYNC_CORE_DCACHE
281 /*
282 * Invalidate D cache in case shared data was changed by
283 * other processors to ensure cache coherence.
284 */
285 resync_core_dcache();
286#endif
287 kfree(msg);
288 }
289 return 0; 271 return 0;
290} 272}
291EXPORT_SYMBOL_GPL(smp_call_function_single); 273EXPORT_SYMBOL_GPL(smp_call_function_single);
292 274
293void smp_send_reschedule(int cpu) 275void smp_send_reschedule(int cpu)
294{ 276{
295 unsigned long flags; 277 /* simply trigger an ipi */
296 struct ipi_message_queue *msg_queue;
297 struct ipi_message *msg;
298
299 if (cpu_is_offline(cpu)) 278 if (cpu_is_offline(cpu))
300 return; 279 return;
301 280 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
302 msg = kzalloc(sizeof(*msg), GFP_ATOMIC);
303 if (!msg)
304 return;
305 INIT_LIST_HEAD(&msg->list);
306 msg->type = BFIN_IPI_RESCHEDULE;
307
308 msg_queue = &per_cpu(ipi_msg_queue, cpu);
309 spin_lock_irqsave(&msg_queue->lock, flags);
310 list_add_tail(&msg->list, &msg_queue->head);
311 spin_unlock_irqrestore(&msg_queue->lock, flags);
312 platform_send_ipi_cpu(cpu);
313 281
314 return; 282 return;
315} 283}
316 284
317void smp_send_stop(void) 285void smp_send_stop(void)
318{ 286{
319 unsigned int cpu;
320 cpumask_t callmap; 287 cpumask_t callmap;
321 unsigned long flags;
322 struct ipi_message_queue *msg_queue;
323 struct ipi_message *msg;
324 288
325 callmap = cpu_online_map; 289 callmap = cpu_online_map;
326 cpu_clear(smp_processor_id(), callmap); 290 cpu_clear(smp_processor_id(), callmap);
327 if (cpus_empty(callmap)) 291 if (cpus_empty(callmap))
328 return; 292 return;
329 293
330 msg = kzalloc(sizeof(*msg), GFP_ATOMIC); 294 smp_send_message(callmap, BFIN_IPI_CPU_STOP, NULL, NULL, 0);
331 if (!msg)
332 return;
333 INIT_LIST_HEAD(&msg->list);
334 msg->type = BFIN_IPI_CPU_STOP;
335 295
336 for_each_cpu_mask(cpu, callmap) {
337 msg_queue = &per_cpu(ipi_msg_queue, cpu);
338 spin_lock_irqsave(&msg_queue->lock, flags);
339 list_add_tail(&msg->list, &msg_queue->head);
340 spin_unlock_irqrestore(&msg_queue->lock, flags);
341 platform_send_ipi_cpu(cpu);
342 }
343 return; 296 return;
344} 297}
345 298
@@ -446,7 +399,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
446{ 399{
447 platform_prepare_cpus(max_cpus); 400 platform_prepare_cpus(max_cpus);
448 ipi_queue_init(); 401 ipi_queue_init();
449 platform_request_ipi(&ipi_handler); 402 platform_request_ipi(IRQ_SUPPLE_0, ipi_handler_int0);
403 platform_request_ipi(IRQ_SUPPLE_1, ipi_handler_int1);
450} 404}
451 405
452void __init smp_cpus_done(unsigned int max_cpus) 406void __init smp_cpus_done(unsigned int max_cpus)
diff --git a/arch/blackfin/mm/sram-alloc.c b/arch/blackfin/mm/sram-alloc.c
index 627e04b5ba9a..dfd304a4a3ea 100644
--- a/arch/blackfin/mm/sram-alloc.c
+++ b/arch/blackfin/mm/sram-alloc.c
@@ -704,18 +704,18 @@ int sram_free_with_lsl(const void *addr)
704{ 704{
705 struct sram_list_struct *lsl, **tmp; 705 struct sram_list_struct *lsl, **tmp;
706 struct mm_struct *mm = current->mm; 706 struct mm_struct *mm = current->mm;
707 int ret = -1;
707 708
708 for (tmp = &mm->context.sram_list; *tmp; tmp = &(*tmp)->next) 709 for (tmp = &mm->context.sram_list; *tmp; tmp = &(*tmp)->next)
709 if ((*tmp)->addr == addr) 710 if ((*tmp)->addr == addr) {
710 goto found; 711 lsl = *tmp;
711 return -1; 712 ret = sram_free(addr);
712found: 713 *tmp = lsl->next;
713 lsl = *tmp; 714 kfree(lsl);
714 sram_free(addr); 715 break;
715 *tmp = lsl->next; 716 }
716 kfree(lsl);
717 717
718 return 0; 718 return ret;
719} 719}
720EXPORT_SYMBOL(sram_free_with_lsl); 720EXPORT_SYMBOL(sram_free_with_lsl);
721 721
diff --git a/arch/microblaze/Kconfig.debug b/arch/microblaze/Kconfig.debug
index e66e25c4b0b2..012e377330cd 100644
--- a/arch/microblaze/Kconfig.debug
+++ b/arch/microblaze/Kconfig.debug
@@ -23,8 +23,4 @@ config HEART_BEAT
23 This option turns on/off heart beat kernel functionality. 23 This option turns on/off heart beat kernel functionality.
24 First GPIO node is taken. 24 First GPIO node is taken.
25 25
26config DEBUG_BOOTMEM
27 depends on DEBUG_KERNEL
28 bool "Debug BOOTMEM initialization"
29
30endmenu 26endmenu
diff --git a/arch/microblaze/Makefile b/arch/microblaze/Makefile
index 15f1f1d1840d..6f432e6df9af 100644
--- a/arch/microblaze/Makefile
+++ b/arch/microblaze/Makefile
@@ -17,7 +17,7 @@ export CPU_VER CPU_MAJOR CPU_MINOR CPU_REV
17# The various CONFIG_XILINX cpu features options are integers 0/1/2... 17# The various CONFIG_XILINX cpu features options are integers 0/1/2...
18# rather than bools y/n 18# rather than bools y/n
19 19
20# Work out HW multipler support. This is icky. 20# Work out HW multipler support. This is tricky.
21# 1. Spartan2 has no HW multiplers. 21# 1. Spartan2 has no HW multiplers.
22# 2. MicroBlaze v3.x always uses them, except in Spartan 2 22# 2. MicroBlaze v3.x always uses them, except in Spartan 2
23# 3. All other FPGa/CPU ver combos, we can trust the CONFIG_ settings 23# 3. All other FPGa/CPU ver combos, we can trust the CONFIG_ settings
diff --git a/arch/microblaze/configs/mmu_defconfig b/arch/microblaze/configs/mmu_defconfig
index 8b422b12ef78..ab8fbe7ad90b 100644
--- a/arch/microblaze/configs/mmu_defconfig
+++ b/arch/microblaze/configs/mmu_defconfig
@@ -66,5 +66,4 @@ CONFIG_DEBUG_SPINLOCK=y
66CONFIG_DEBUG_INFO=y 66CONFIG_DEBUG_INFO=y
67# CONFIG_RCU_CPU_STALL_DETECTOR is not set 67# CONFIG_RCU_CPU_STALL_DETECTOR is not set
68CONFIG_EARLY_PRINTK=y 68CONFIG_EARLY_PRINTK=y
69CONFIG_DEBUG_BOOTMEM=y
70# CONFIG_CRYPTO_ANSI_CPRNG is not set 69# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/microblaze/include/asm/pvr.h b/arch/microblaze/include/asm/pvr.h
index 37db96a15b45..a10bec62e857 100644
--- a/arch/microblaze/include/asm/pvr.h
+++ b/arch/microblaze/include/asm/pvr.h
@@ -1,9 +1,9 @@
1/* 1/*
2 * Support for the MicroBlaze PVR (Processor Version Register) 2 * Support for the MicroBlaze PVR (Processor Version Register)
3 * 3 *
4 * Copyright (C) 2009 Michal Simek <monstr@monstr.eu> 4 * Copyright (C) 2009 - 2011 Michal Simek <monstr@monstr.eu>
5 * Copyright (C) 2007 John Williams <john.williams@petalogix.com> 5 * Copyright (C) 2007 John Williams <john.williams@petalogix.com>
6 * Copyright (C) 2007 - 2009 PetaLogix 6 * Copyright (C) 2007 - 2011 PetaLogix
7 * 7 *
8 * This file is subject to the terms and conditions of the GNU General 8 * This file is subject to the terms and conditions of the GNU General
9 * Public License. See the file COPYING in the main directory of this 9 * Public License. See the file COPYING in the main directory of this
@@ -46,11 +46,11 @@ struct pvr_s {
46#define PVR2_I_LMB_MASK 0x10000000 46#define PVR2_I_LMB_MASK 0x10000000
47#define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000 47#define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000
48#define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000 48#define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000
49#define PVR2_D_PLB_MASK 0x02000000 /* new */ 49#define PVR2_D_PLB_MASK 0x02000000 /* new */
50#define PVR2_I_PLB_MASK 0x01000000 /* new */ 50#define PVR2_I_PLB_MASK 0x01000000 /* new */
51#define PVR2_INTERCONNECT 0x00800000 /* new */ 51#define PVR2_INTERCONNECT 0x00800000 /* new */
52#define PVR2_USE_EXTEND_FSL 0x00080000 /* new */ 52#define PVR2_USE_EXTEND_FSL 0x00080000 /* new */
53#define PVR2_USE_FSL_EXC 0x00040000 /* new */ 53#define PVR2_USE_FSL_EXC 0x00040000 /* new */
54#define PVR2_USE_MSR_INSTR 0x00020000 54#define PVR2_USE_MSR_INSTR 0x00020000
55#define PVR2_USE_PCMP_INSTR 0x00010000 55#define PVR2_USE_PCMP_INSTR 0x00010000
56#define PVR2_AREA_OPTIMISED 0x00008000 56#define PVR2_AREA_OPTIMISED 0x00008000
@@ -59,7 +59,7 @@ struct pvr_s {
59#define PVR2_USE_HW_MUL_MASK 0x00001000 59#define PVR2_USE_HW_MUL_MASK 0x00001000
60#define PVR2_USE_FPU_MASK 0x00000800 60#define PVR2_USE_FPU_MASK 0x00000800
61#define PVR2_USE_MUL64_MASK 0x00000400 61#define PVR2_USE_MUL64_MASK 0x00000400
62#define PVR2_USE_FPU2_MASK 0x00000200 /* new */ 62#define PVR2_USE_FPU2_MASK 0x00000200 /* new */
63#define PVR2_USE_IPLBEXC 0x00000100 63#define PVR2_USE_IPLBEXC 0x00000100
64#define PVR2_USE_DPLBEXC 0x00000080 64#define PVR2_USE_DPLBEXC 0x00000080
65#define PVR2_OPCODE_0x0_ILL_MASK 0x00000040 65#define PVR2_OPCODE_0x0_ILL_MASK 0x00000040
@@ -122,96 +122,103 @@ struct pvr_s {
122 122
123 123
124/* PVR access macros */ 124/* PVR access macros */
125#define PVR_IS_FULL(pvr) (pvr.pvr[0] & PVR0_PVR_FULL_MASK) 125#define PVR_IS_FULL(_pvr) (_pvr.pvr[0] & PVR0_PVR_FULL_MASK)
126#define PVR_USE_BARREL(pvr) (pvr.pvr[0] & PVR0_USE_BARREL_MASK) 126#define PVR_USE_BARREL(_pvr) (_pvr.pvr[0] & PVR0_USE_BARREL_MASK)
127#define PVR_USE_DIV(pvr) (pvr.pvr[0] & PVR0_USE_DIV_MASK) 127#define PVR_USE_DIV(_pvr) (_pvr.pvr[0] & PVR0_USE_DIV_MASK)
128#define PVR_USE_HW_MUL(pvr) (pvr.pvr[0] & PVR0_USE_HW_MUL_MASK) 128#define PVR_USE_HW_MUL(_pvr) (_pvr.pvr[0] & PVR0_USE_HW_MUL_MASK)
129#define PVR_USE_FPU(pvr) (pvr.pvr[0] & PVR0_USE_FPU_MASK) 129#define PVR_USE_FPU(_pvr) (_pvr.pvr[0] & PVR0_USE_FPU_MASK)
130#define PVR_USE_FPU2(pvr) (pvr.pvr[2] & PVR2_USE_FPU2_MASK) 130#define PVR_USE_FPU2(_pvr) (_pvr.pvr[2] & PVR2_USE_FPU2_MASK)
131#define PVR_USE_ICACHE(pvr) (pvr.pvr[0] & PVR0_USE_ICACHE_MASK) 131#define PVR_USE_ICACHE(_pvr) (_pvr.pvr[0] & PVR0_USE_ICACHE_MASK)
132#define PVR_USE_DCACHE(pvr) (pvr.pvr[0] & PVR0_USE_DCACHE_MASK) 132#define PVR_USE_DCACHE(_pvr) (_pvr.pvr[0] & PVR0_USE_DCACHE_MASK)
133#define PVR_VERSION(pvr) ((pvr.pvr[0] & PVR0_VERSION_MASK) >> 8) 133#define PVR_VERSION(_pvr) ((_pvr.pvr[0] & PVR0_VERSION_MASK) >> 8)
134#define PVR_USER1(pvr) (pvr.pvr[0] & PVR0_USER1_MASK) 134#define PVR_USER1(_pvr) (_pvr.pvr[0] & PVR0_USER1_MASK)
135#define PVR_USER2(pvr) (pvr.pvr[1] & PVR1_USER2_MASK) 135#define PVR_USER2(_pvr) (_pvr.pvr[1] & PVR1_USER2_MASK)
136 136
137#define PVR_D_OPB(pvr) (pvr.pvr[2] & PVR2_D_OPB_MASK) 137#define PVR_D_OPB(_pvr) (_pvr.pvr[2] & PVR2_D_OPB_MASK)
138#define PVR_D_LMB(pvr) (pvr.pvr[2] & PVR2_D_LMB_MASK) 138#define PVR_D_LMB(_pvr) (_pvr.pvr[2] & PVR2_D_LMB_MASK)
139#define PVR_I_OPB(pvr) (pvr.pvr[2] & PVR2_I_OPB_MASK) 139#define PVR_I_OPB(_pvr) (_pvr.pvr[2] & PVR2_I_OPB_MASK)
140#define PVR_I_LMB(pvr) (pvr.pvr[2] & PVR2_I_LMB_MASK) 140#define PVR_I_LMB(_pvr) (_pvr.pvr[2] & PVR2_I_LMB_MASK)
141#define PVR_INTERRUPT_IS_EDGE(pvr) \ 141#define PVR_INTERRUPT_IS_EDGE(_pvr) \
142 (pvr.pvr[2] & PVR2_INTERRUPT_IS_EDGE_MASK) 142 (_pvr.pvr[2] & PVR2_INTERRUPT_IS_EDGE_MASK)
143#define PVR_EDGE_IS_POSITIVE(pvr) \ 143#define PVR_EDGE_IS_POSITIVE(_pvr) \
144 (pvr.pvr[2] & PVR2_EDGE_IS_POSITIVE_MASK) 144 (_pvr.pvr[2] & PVR2_EDGE_IS_POSITIVE_MASK)
145#define PVR_USE_MSR_INSTR(pvr) (pvr.pvr[2] & PVR2_USE_MSR_INSTR) 145#define PVR_USE_MSR_INSTR(_pvr) (_pvr.pvr[2] & PVR2_USE_MSR_INSTR)
146#define PVR_USE_PCMP_INSTR(pvr) (pvr.pvr[2] & PVR2_USE_PCMP_INSTR) 146#define PVR_USE_PCMP_INSTR(_pvr) (_pvr.pvr[2] & PVR2_USE_PCMP_INSTR)
147#define PVR_AREA_OPTIMISED(pvr) (pvr.pvr[2] & PVR2_AREA_OPTIMISED) 147#define PVR_AREA_OPTIMISED(_pvr) (_pvr.pvr[2] & PVR2_AREA_OPTIMISED)
148#define PVR_USE_MUL64(pvr) (pvr.pvr[2] & PVR2_USE_MUL64_MASK) 148#define PVR_USE_MUL64(_pvr) (_pvr.pvr[2] & PVR2_USE_MUL64_MASK)
149#define PVR_OPCODE_0x0_ILLEGAL(pvr) \ 149#define PVR_OPCODE_0x0_ILLEGAL(_pvr) \
150 (pvr.pvr[2] & PVR2_OPCODE_0x0_ILL_MASK) 150 (_pvr.pvr[2] & PVR2_OPCODE_0x0_ILL_MASK)
151#define PVR_UNALIGNED_EXCEPTION(pvr) \ 151#define PVR_UNALIGNED_EXCEPTION(_pvr) \
152 (pvr.pvr[2] & PVR2_UNALIGNED_EXC_MASK) 152 (_pvr.pvr[2] & PVR2_UNALIGNED_EXC_MASK)
153#define PVR_ILL_OPCODE_EXCEPTION(pvr) \ 153#define PVR_ILL_OPCODE_EXCEPTION(_pvr) \
154 (pvr.pvr[2] & PVR2_ILL_OPCODE_EXC_MASK) 154 (_pvr.pvr[2] & PVR2_ILL_OPCODE_EXC_MASK)
155#define PVR_IOPB_BUS_EXCEPTION(pvr) \ 155#define PVR_IOPB_BUS_EXCEPTION(_pvr) \
156 (pvr.pvr[2] & PVR2_IOPB_BUS_EXC_MASK) 156 (_pvr.pvr[2] & PVR2_IOPB_BUS_EXC_MASK)
157#define PVR_DOPB_BUS_EXCEPTION(pvr) \ 157#define PVR_DOPB_BUS_EXCEPTION(_pvr) \
158 (pvr.pvr[2] & PVR2_DOPB_BUS_EXC_MASK) 158 (_pvr.pvr[2] & PVR2_DOPB_BUS_EXC_MASK)
159#define PVR_DIV_ZERO_EXCEPTION(pvr) \ 159#define PVR_DIV_ZERO_EXCEPTION(_pvr) \
160 (pvr.pvr[2] & PVR2_DIV_ZERO_EXC_MASK) 160 (_pvr.pvr[2] & PVR2_DIV_ZERO_EXC_MASK)
161#define PVR_FPU_EXCEPTION(pvr) (pvr.pvr[2] & PVR2_FPU_EXC_MASK) 161#define PVR_FPU_EXCEPTION(_pvr) (_pvr.pvr[2] & PVR2_FPU_EXC_MASK)
162#define PVR_FSL_EXCEPTION(pvr) (pvr.pvr[2] & PVR2_USE_EXTEND_FSL) 162#define PVR_FSL_EXCEPTION(_pvr) (_pvr.pvr[2] & PVR2_USE_EXTEND_FSL)
163 163
164#define PVR_DEBUG_ENABLED(pvr) (pvr.pvr[3] & PVR3_DEBUG_ENABLED_MASK) 164#define PVR_DEBUG_ENABLED(_pvr) (_pvr.pvr[3] & PVR3_DEBUG_ENABLED_MASK)
165#define PVR_NUMBER_OF_PC_BRK(pvr) \ 165#define PVR_NUMBER_OF_PC_BRK(_pvr) \
166 ((pvr.pvr[3] & PVR3_NUMBER_OF_PC_BRK_MASK) >> 25) 166 ((_pvr.pvr[3] & PVR3_NUMBER_OF_PC_BRK_MASK) >> 25)
167#define PVR_NUMBER_OF_RD_ADDR_BRK(pvr) \ 167#define PVR_NUMBER_OF_RD_ADDR_BRK(_pvr) \
168 ((pvr.pvr[3] & PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19) 168 ((_pvr.pvr[3] & PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19)
169#define PVR_NUMBER_OF_WR_ADDR_BRK(pvr) \ 169#define PVR_NUMBER_OF_WR_ADDR_BRK(_pvr) \
170 ((pvr.pvr[3] & PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13) 170 ((_pvr.pvr[3] & PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13)
171#define PVR_FSL_LINKS(pvr) ((pvr.pvr[3] & PVR3_FSL_LINKS_MASK) >> 7) 171#define PVR_FSL_LINKS(_pvr) ((_pvr.pvr[3] & PVR3_FSL_LINKS_MASK) >> 7)
172 172
173#define PVR_ICACHE_ADDR_TAG_BITS(pvr) \ 173#define PVR_ICACHE_ADDR_TAG_BITS(_pvr) \
174 ((pvr.pvr[4] & PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26) 174 ((_pvr.pvr[4] & PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26)
175#define PVR_ICACHE_USE_FSL(pvr) (pvr.pvr[4] & PVR4_ICACHE_USE_FSL_MASK) 175#define PVR_ICACHE_USE_FSL(_pvr) \
176#define PVR_ICACHE_ALLOW_WR(pvr) (pvr.pvr[4] & PVR4_ICACHE_ALLOW_WR_MASK) 176 (_pvr.pvr[4] & PVR4_ICACHE_USE_FSL_MASK)
177#define PVR_ICACHE_LINE_LEN(pvr) \ 177#define PVR_ICACHE_ALLOW_WR(_pvr) \
178 (1 << ((pvr.pvr[4] & PVR4_ICACHE_LINE_LEN_MASK) >> 21)) 178 (_pvr.pvr[4] & PVR4_ICACHE_ALLOW_WR_MASK)
179#define PVR_ICACHE_BYTE_SIZE(pvr) \ 179#define PVR_ICACHE_LINE_LEN(_pvr) \
180 (1 << ((pvr.pvr[4] & PVR4_ICACHE_BYTE_SIZE_MASK) >> 16)) 180 (1 << ((_pvr.pvr[4] & PVR4_ICACHE_LINE_LEN_MASK) >> 21))
181 181#define PVR_ICACHE_BYTE_SIZE(_pvr) \
182#define PVR_DCACHE_ADDR_TAG_BITS(pvr) \ 182 (1 << ((_pvr.pvr[4] & PVR4_ICACHE_BYTE_SIZE_MASK) >> 16))
183 ((pvr.pvr[5] & PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26) 183
184#define PVR_DCACHE_USE_FSL(pvr) (pvr.pvr[5] & PVR5_DCACHE_USE_FSL_MASK) 184#define PVR_DCACHE_ADDR_TAG_BITS(_pvr) \
185#define PVR_DCACHE_ALLOW_WR(pvr) (pvr.pvr[5] & PVR5_DCACHE_ALLOW_WR_MASK) 185 ((_pvr.pvr[5] & PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26)
186#define PVR_DCACHE_USE_FSL(_pvr) (_pvr.pvr[5] & PVR5_DCACHE_USE_FSL_MASK)
187#define PVR_DCACHE_ALLOW_WR(_pvr) \
188 (_pvr.pvr[5] & PVR5_DCACHE_ALLOW_WR_MASK)
186/* FIXME two shifts on one line needs any comment */ 189/* FIXME two shifts on one line needs any comment */
187#define PVR_DCACHE_LINE_LEN(pvr) \ 190#define PVR_DCACHE_LINE_LEN(_pvr) \
188 (1 << ((pvr.pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21)) 191 (1 << ((_pvr.pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21))
189#define PVR_DCACHE_BYTE_SIZE(pvr) \ 192#define PVR_DCACHE_BYTE_SIZE(_pvr) \
190 (1 << ((pvr.pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16)) 193 (1 << ((_pvr.pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16))
191 194
192#define PVR_DCACHE_USE_WRITEBACK(pvr) \ 195#define PVR_DCACHE_USE_WRITEBACK(_pvr) \
193 ((pvr.pvr[5] & PVR5_DCACHE_USE_WRITEBACK) >> 14) 196 ((_pvr.pvr[5] & PVR5_DCACHE_USE_WRITEBACK) >> 14)
194 197
195#define PVR_ICACHE_BASEADDR(pvr) (pvr.pvr[6] & PVR6_ICACHE_BASEADDR_MASK) 198#define PVR_ICACHE_BASEADDR(_pvr) \
196#define PVR_ICACHE_HIGHADDR(pvr) (pvr.pvr[7] & PVR7_ICACHE_HIGHADDR_MASK) 199 (_pvr.pvr[6] & PVR6_ICACHE_BASEADDR_MASK)
200#define PVR_ICACHE_HIGHADDR(_pvr) \
201 (_pvr.pvr[7] & PVR7_ICACHE_HIGHADDR_MASK)
202#define PVR_DCACHE_BASEADDR(_pvr) \
203 (_pvr.pvr[8] & PVR8_DCACHE_BASEADDR_MASK)
204#define PVR_DCACHE_HIGHADDR(_pvr) \
205 (_pvr.pvr[9] & PVR9_DCACHE_HIGHADDR_MASK)
197 206
198#define PVR_DCACHE_BASEADDR(pvr) (pvr.pvr[8] & PVR8_DCACHE_BASEADDR_MASK) 207#define PVR_TARGET_FAMILY(_pvr) \
199#define PVR_DCACHE_HIGHADDR(pvr) (pvr.pvr[9] & PVR9_DCACHE_HIGHADDR_MASK) 208 ((_pvr.pvr[10] & PVR10_TARGET_FAMILY_MASK) >> 24)
200 209
201#define PVR_TARGET_FAMILY(pvr) ((pvr.pvr[10] & PVR10_TARGET_FAMILY_MASK) >> 24) 210#define PVR_MSR_RESET_VALUE(_pvr) \
202 211 (_pvr.pvr[11] & PVR11_MSR_RESET_VALUE_MASK)
203#define PVR_MSR_RESET_VALUE(pvr) \
204 (pvr.pvr[11] & PVR11_MSR_RESET_VALUE_MASK)
205 212
206/* mmu */ 213/* mmu */
207#define PVR_USE_MMU(pvr) ((pvr.pvr[11] & PVR11_USE_MMU) >> 30) 214#define PVR_USE_MMU(_pvr) ((_pvr.pvr[11] & PVR11_USE_MMU) >> 30)
208#define PVR_MMU_ITLB_SIZE(pvr) (pvr.pvr[11] & PVR11_MMU_ITLB_SIZE) 215#define PVR_MMU_ITLB_SIZE(_pvr) (_pvr.pvr[11] & PVR11_MMU_ITLB_SIZE)
209#define PVR_MMU_DTLB_SIZE(pvr) (pvr.pvr[11] & PVR11_MMU_DTLB_SIZE) 216#define PVR_MMU_DTLB_SIZE(_pvr) (_pvr.pvr[11] & PVR11_MMU_DTLB_SIZE)
210#define PVR_MMU_TLB_ACCESS(pvr) (pvr.pvr[11] & PVR11_MMU_TLB_ACCESS) 217#define PVR_MMU_TLB_ACCESS(_pvr) (_pvr.pvr[11] & PVR11_MMU_TLB_ACCESS)
211#define PVR_MMU_ZONES(pvr) (pvr.pvr[11] & PVR11_MMU_ZONES) 218#define PVR_MMU_ZONES(_pvr) (_pvr.pvr[11] & PVR11_MMU_ZONES)
212 219
213/* endian */ 220/* endian */
214#define PVR_ENDIAN(pvr) (pvr.pvr[0] & PVR0_ENDI) 221#define PVR_ENDIAN(_pvr) (_pvr.pvr[0] & PVR0_ENDI)
215 222
216int cpu_has_pvr(void); 223int cpu_has_pvr(void);
217void get_pvr(struct pvr_s *pvr); 224void get_pvr(struct pvr_s *pvr);
diff --git a/arch/microblaze/kernel/cpu/cpuinfo.c b/arch/microblaze/kernel/cpu/cpuinfo.c
index 87c79fa275c3..2c309fccf230 100644
--- a/arch/microblaze/kernel/cpu/cpuinfo.c
+++ b/arch/microblaze/kernel/cpu/cpuinfo.c
@@ -32,6 +32,7 @@ const struct cpu_ver_key cpu_ver_lookup[] = {
32 {"7.30.a", 0x10}, 32 {"7.30.a", 0x10},
33 {"7.30.b", 0x11}, 33 {"7.30.b", 0x11},
34 {"8.00.a", 0x12}, 34 {"8.00.a", 0x12},
35 {"8.00.b", 0x13},
35 {NULL, 0}, 36 {NULL, 0},
36}; 37};
37 38
diff --git a/arch/microblaze/kernel/entry.S b/arch/microblaze/kernel/entry.S
index 819238b8a429..41c30cdb2704 100644
--- a/arch/microblaze/kernel/entry.S
+++ b/arch/microblaze/kernel/entry.S
@@ -287,25 +287,44 @@
287 * are masked. This is nice, means we don't have to CLI before state save 287 * are masked. This is nice, means we don't have to CLI before state save
288 */ 288 */
289C_ENTRY(_user_exception): 289C_ENTRY(_user_exception):
290 addi r14, r14, 4 /* return address is 4 byte after call */
291 swi r1, r0, TOPHYS(PER_CPU(ENTRY_SP)) /* save stack */ 290 swi r1, r0, TOPHYS(PER_CPU(ENTRY_SP)) /* save stack */
291 addi r14, r14, 4 /* return address is 4 byte after call */
292
293 mfs r1, rmsr
294 nop
295 andi r1, r1, MSR_UMS
296 bnei r1, 1f
297
298/* Kernel-mode state save - kernel execve */
299 lwi r1, r0, TOPHYS(PER_CPU(ENTRY_SP)); /* Reload kernel stack-ptr*/
300 tophys(r1,r1);
301
302 addik r1, r1, -STATE_SAVE_SIZE; /* Make room on the stack. */
303 SAVE_REGS
292 304
305 swi r1, r1, PTO + PT_MODE; /* pt_regs -> kernel mode */
306 brid 2f;
307 nop; /* Fill delay slot */
308
309/* User-mode state save. */
3101:
293 lwi r1, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); /* get saved current */ 311 lwi r1, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); /* get saved current */
294 tophys(r1,r1); 312 tophys(r1,r1);
295 lwi r1, r1, TS_THREAD_INFO; /* get stack from task_struct */ 313 lwi r1, r1, TS_THREAD_INFO; /* get stack from task_struct */
296 /* MS these three instructions can be added to one */ 314/* calculate kernel stack pointer from task struct 8k */
297 /* addik r1, r1, THREAD_SIZE; */ 315 addik r1, r1, THREAD_SIZE;
298 /* tophys(r1,r1); */ 316 tophys(r1,r1);
299 /* addik r1, r1, -STATE_SAVE_SIZE; */ 317
300 addik r1, r1, THREAD_SIZE + CONFIG_KERNEL_BASE_ADDR - CONFIG_KERNEL_START - STATE_SAVE_SIZE; 318 addik r1, r1, -STATE_SAVE_SIZE; /* Make room on the stack. */
301 SAVE_REGS 319 SAVE_REGS
302 swi r0, r1, PTO + PT_R3 320 swi r0, r1, PTO + PT_R3
303 swi r0, r1, PTO + PT_R4 321 swi r0, r1, PTO + PT_R4
304 322
323 swi r0, r1, PTO + PT_MODE; /* Was in user-mode. */
305 lwi r11, r0, TOPHYS(PER_CPU(ENTRY_SP)); 324 lwi r11, r0, TOPHYS(PER_CPU(ENTRY_SP));
306 swi r11, r1, PTO+PT_R1; /* Store user SP. */ 325 swi r11, r1, PTO+PT_R1; /* Store user SP. */
307 clear_ums; 326 clear_ums;
308 lwi CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); 3272: lwi CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE));
309 /* Save away the syscall number. */ 328 /* Save away the syscall number. */
310 swi r12, r1, PTO+PT_R0; 329 swi r12, r1, PTO+PT_R0;
311 tovirt(r1,r1) 330 tovirt(r1,r1)
@@ -375,6 +394,9 @@ C_ENTRY(ret_from_trap):
375 swi r3, r1, PTO + PT_R3 394 swi r3, r1, PTO + PT_R3
376 swi r4, r1, PTO + PT_R4 395 swi r4, r1, PTO + PT_R4
377 396
397 lwi r11, r1, PTO + PT_MODE;
398/* See if returning to kernel mode, if so, skip resched &c. */
399 bnei r11, 2f;
378 /* We're returning to user mode, so check for various conditions that 400 /* We're returning to user mode, so check for various conditions that
379 * trigger rescheduling. */ 401 * trigger rescheduling. */
380 /* FIXME: Restructure all these flag checks. */ 402 /* FIXME: Restructure all these flag checks. */
@@ -417,6 +439,16 @@ C_ENTRY(ret_from_trap):
417 RESTORE_REGS; 439 RESTORE_REGS;
418 addik r1, r1, STATE_SAVE_SIZE /* Clean up stack space. */ 440 addik r1, r1, STATE_SAVE_SIZE /* Clean up stack space. */
419 lwi r1, r1, PT_R1 - PT_SIZE;/* Restore user stack pointer. */ 441 lwi r1, r1, PT_R1 - PT_SIZE;/* Restore user stack pointer. */
442 bri 6f;
443
444/* Return to kernel state. */
4452: set_bip; /* Ints masked for state restore */
446 VM_OFF;
447 tophys(r1,r1);
448 RESTORE_REGS;
449 addik r1, r1, STATE_SAVE_SIZE /* Clean up stack space. */
450 tovirt(r1,r1);
4516:
420TRAP_return: /* Make global symbol for debugging */ 452TRAP_return: /* Make global symbol for debugging */
421 rtbd r14, 0; /* Instructions to return from an IRQ */ 453 rtbd r14, 0; /* Instructions to return from an IRQ */
422 nop; 454 nop;
diff --git a/arch/microblaze/kernel/exceptions.c b/arch/microblaze/kernel/exceptions.c
index 478f2943ede7..a7fa6ae76d89 100644
--- a/arch/microblaze/kernel/exceptions.c
+++ b/arch/microblaze/kernel/exceptions.c
@@ -25,6 +25,7 @@
25#include <linux/errno.h> 25#include <linux/errno.h>
26#include <linux/ptrace.h> 26#include <linux/ptrace.h>
27#include <asm/current.h> 27#include <asm/current.h>
28#include <asm/cacheflush.h>
28 29
29#define MICROBLAZE_ILL_OPCODE_EXCEPTION 0x02 30#define MICROBLAZE_ILL_OPCODE_EXCEPTION 0x02
30#define MICROBLAZE_IBUS_EXCEPTION 0x03 31#define MICROBLAZE_IBUS_EXCEPTION 0x03
@@ -52,6 +53,8 @@ void die(const char *str, struct pt_regs *fp, long err)
52void sw_exception(struct pt_regs *regs) 53void sw_exception(struct pt_regs *regs)
53{ 54{
54 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->r16); 55 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->r16);
56 flush_dcache_range(regs->r16, regs->r16 + 0x4);
57 flush_icache_range(regs->r16, regs->r16 + 0x4);
55} 58}
56 59
57void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) 60void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
diff --git a/arch/microblaze/kernel/hw_exception_handler.S b/arch/microblaze/kernel/hw_exception_handler.S
index 781195438ee6..25f6e07d8de8 100644
--- a/arch/microblaze/kernel/hw_exception_handler.S
+++ b/arch/microblaze/kernel/hw_exception_handler.S
@@ -945,11 +945,20 @@ store3: sbi r3, r4, 2;
945store4: sbi r3, r4, 3; /* Delay slot */ 945store4: sbi r3, r4, 3; /* Delay slot */
946ex_shw_vm: 946ex_shw_vm:
947 /* Store the lower half-word, byte-by-byte into destination address */ 947 /* Store the lower half-word, byte-by-byte into destination address */
948#ifdef __MICROBLAZEEL__
949 lbui r3, r5, 0;
950store5: sbi r3, r4, 0;
951 lbui r3, r5, 1;
952 brid ret_from_exc;
953store6: sbi r3, r4, 1; /* Delay slot */
954#else
948 lbui r3, r5, 2; 955 lbui r3, r5, 2;
949store5: sbi r3, r4, 0; 956store5: sbi r3, r4, 0;
950 lbui r3, r5, 3; 957 lbui r3, r5, 3;
951 brid ret_from_exc; 958 brid ret_from_exc;
952store6: sbi r3, r4, 1; /* Delay slot */ 959store6: sbi r3, r4, 1; /* Delay slot */
960#endif
961
953ex_sw_end_vm: /* Exception handling of store word, ends. */ 962ex_sw_end_vm: /* Exception handling of store word, ends. */
954 963
955/* We have to prevent cases that get/put_user macros get unaligned pointer 964/* We have to prevent cases that get/put_user macros get unaligned pointer
diff --git a/arch/microblaze/kernel/prom.c b/arch/microblaze/kernel/prom.c
index a105301e2b7f..c881393f07fd 100644
--- a/arch/microblaze/kernel/prom.c
+++ b/arch/microblaze/kernel/prom.c
@@ -61,14 +61,12 @@ static int __init early_init_dt_scan_serial(unsigned long node,
61 char *p; 61 char *p;
62 int *addr; 62 int *addr;
63 63
64 pr_debug("search \"chosen\", depth: %d, uname: %s\n", depth, uname); 64 pr_debug("search \"serial\", depth: %d, uname: %s\n", depth, uname);
65 65
66/* find all serial nodes */ 66/* find all serial nodes */
67 if (strncmp(uname, "serial", 6) != 0) 67 if (strncmp(uname, "serial", 6) != 0)
68 return 0; 68 return 0;
69 69
70 early_init_dt_check_for_initrd(node);
71
72/* find compatible node with uartlite */ 70/* find compatible node with uartlite */
73 p = of_get_flat_dt_prop(node, "compatible", &l); 71 p = of_get_flat_dt_prop(node, "compatible", &l);
74 if ((strncmp(p, "xlnx,xps-uartlite", 17) != 0) && 72 if ((strncmp(p, "xlnx,xps-uartlite", 17) != 0) &&
diff --git a/arch/microblaze/kernel/vmlinux.lds.S b/arch/microblaze/kernel/vmlinux.lds.S
index 96a88c31fe48..3451bdec9f05 100644
--- a/arch/microblaze/kernel/vmlinux.lds.S
+++ b/arch/microblaze/kernel/vmlinux.lds.S
@@ -123,20 +123,10 @@ SECTIONS {
123 123
124 __init_end_before_initramfs = .; 124 __init_end_before_initramfs = .;
125 125
126 .init.ramfs ALIGN(PAGE_SIZE) : AT(ADDR(.init.ramfs) - LOAD_OFFSET) { 126 .init.ramfs : AT(ADDR(.init.ramfs) - LOAD_OFFSET) {
127 __initramfs_start = .; 127 INIT_RAM_FS
128 *(.init.ramfs)
129 __initramfs_end = .;
130 . = ALIGN(4);
131 LONG(0);
132/*
133 * FIXME this can break initramfs for MMU.
134 * Pad init.ramfs up to page boundary,
135 * so that __init_end == __bss_start. This will make image.elf
136 * consistent with the image.bin
137 */
138 /* . = ALIGN(PAGE_SIZE); */
139 } 128 }
129
140 __init_end = .; 130 __init_end = .;
141 131
142 .bss ALIGN (PAGE_SIZE) : AT(ADDR(.bss) - LOAD_OFFSET) { 132 .bss ALIGN (PAGE_SIZE) : AT(ADDR(.bss) - LOAD_OFFSET) {
diff --git a/arch/microblaze/lib/memmove.c b/arch/microblaze/lib/memmove.c
index 123e3616f2dd..810fd68775e3 100644
--- a/arch/microblaze/lib/memmove.c
+++ b/arch/microblaze/lib/memmove.c
@@ -182,7 +182,7 @@ void *memmove(void *v_dst, const void *v_src, __kernel_size_t c)
182 for (; c >= 4; c -= 4) { 182 for (; c >= 4; c -= 4) {
183 value = *--i_src; 183 value = *--i_src;
184 *--i_dst = buf_hold | ((value & 0xFF000000)>> 24); 184 *--i_dst = buf_hold | ((value & 0xFF000000)>> 24);
185 buf_hold = (value & 0xFFFFFF) << 8;; 185 buf_hold = (value & 0xFFFFFF) << 8;
186 } 186 }
187#endif 187#endif
188 /* Realign the source */ 188 /* Realign the source */
diff --git a/arch/microblaze/lib/muldi3.S b/arch/microblaze/lib/muldi3.S
deleted file mode 100644
index ceeaa8c407f2..000000000000
--- a/arch/microblaze/lib/muldi3.S
+++ /dev/null
@@ -1,121 +0,0 @@
1#include <linux/linkage.h>
2
3/*
4 * Multiply operation for 64 bit integers, for devices with hard multiply
5 * Input : Operand1[H] in Reg r5
6 * Operand1[L] in Reg r6
7 * Operand2[H] in Reg r7
8 * Operand2[L] in Reg r8
9 * Output: Result[H] in Reg r3
10 * Result[L] in Reg r4
11 *
12 * Explaination:
13 *
14 * Both the input numbers are divided into 16 bit number as follows
15 * op1 = A B C D
16 * op2 = E F G H
17 * result = D * H
18 * + (C * H + D * G) << 16
19 * + (B * H + C * G + D * F) << 32
20 * + (A * H + B * G + C * F + D * E) << 48
21 *
22 * Only 64 bits of the output are considered
23 */
24
25 .text
26 .globl __muldi3
27 .type __muldi3, @function
28 .ent __muldi3
29
30__muldi3:
31 addi r1, r1, -40
32
33/* Save the input operands on the caller's stack */
34 swi r5, r1, 44
35 swi r6, r1, 48
36 swi r7, r1, 52
37 swi r8, r1, 56
38
39/* Store all the callee saved registers */
40 sw r20, r1, r0
41 swi r21, r1, 4
42 swi r22, r1, 8
43 swi r23, r1, 12
44 swi r24, r1, 16
45 swi r25, r1, 20
46 swi r26, r1, 24
47 swi r27, r1, 28
48
49/* Load all the 16 bit values for A thru H */
50 lhui r20, r1, 44 /* A */
51 lhui r21, r1, 46 /* B */
52 lhui r22, r1, 48 /* C */
53 lhui r23, r1, 50 /* D */
54 lhui r24, r1, 52 /* E */
55 lhui r25, r1, 54 /* F */
56 lhui r26, r1, 56 /* G */
57 lhui r27, r1, 58 /* H */
58
59/* D * H ==> LSB of the result on stack ==> Store1 */
60 mul r9, r23, r27
61 swi r9, r1, 36 /* Pos2 and Pos3 */
62
63/* Hi (Store1) + C * H + D * G ==> Store2 ==> Pos1 and Pos2 */
64/* Store the carry generated in position 2 for Pos 3 */
65 lhui r11, r1, 36 /* Pos2 */
66 mul r9, r22, r27 /* C * H */
67 mul r10, r23, r26 /* D * G */
68 add r9, r9, r10
69 addc r12, r0, r0
70 add r9, r9, r11
71 addc r12, r12, r0 /* Store the Carry */
72 shi r9, r1, 36 /* Store Pos2 */
73 swi r9, r1, 32
74 lhui r11, r1, 32
75 shi r11, r1, 34 /* Store Pos1 */
76
77/* Hi (Store2) + B * H + C * G + D * F ==> Store3 ==> Pos0 and Pos1 */
78 mul r9, r21, r27 /* B * H */
79 mul r10, r22, r26 /* C * G */
80 mul r7, r23, r25 /* D * F */
81 add r9, r9, r11
82 add r9, r9, r10
83 add r9, r9, r7
84 swi r9, r1, 32 /* Pos0 and Pos1 */
85
86/* Hi (Store3) + A * H + B * G + C * F + D * E ==> Store3 ==> Pos0 */
87 lhui r11, r1, 32 /* Pos0 */
88 mul r9, r20, r27 /* A * H */
89 mul r10, r21, r26 /* B * G */
90 mul r7, r22, r25 /* C * F */
91 mul r8, r23, r24 /* D * E */
92 add r9, r9, r11
93 add r9, r9, r10
94 add r9, r9, r7
95 add r9, r9, r8
96 sext16 r9, r9 /* Sign extend the MSB */
97 shi r9, r1, 32
98
99/* Move results to r3 and r4 */
100 lhui r3, r1, 32
101 add r3, r3, r12
102 shi r3, r1, 32
103 lwi r3, r1, 32 /* Hi Part */
104 lwi r4, r1, 36 /* Lo Part */
105
106/* Restore Callee saved registers */
107 lw r20, r1, r0
108 lwi r21, r1, 4
109 lwi r22, r1, 8
110 lwi r23, r1, 12
111 lwi r24, r1, 16
112 lwi r25, r1, 20
113 lwi r26, r1, 24
114 lwi r27, r1, 28
115
116/* Restore Frame and return */
117 rtsd r15, 8
118 addi r1, r1, 40
119
120.size __muldi3, . - __muldi3
121.end __muldi3
diff --git a/arch/microblaze/lib/muldi3.c b/arch/microblaze/lib/muldi3.c
new file mode 100644
index 000000000000..d4860e154d29
--- /dev/null
+++ b/arch/microblaze/lib/muldi3.c
@@ -0,0 +1,60 @@
1#include <linux/module.h>
2
3#include "libgcc.h"
4
5#define DWtype long long
6#define UWtype unsigned long
7#define UHWtype unsigned short
8
9#define W_TYPE_SIZE 32
10
11#define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
12#define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
13#define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
14
15/* If we still don't have umul_ppmm, define it using plain C. */
16#if !defined(umul_ppmm)
17#define umul_ppmm(w1, w0, u, v) \
18 do { \
19 UWtype __x0, __x1, __x2, __x3; \
20 UHWtype __ul, __vl, __uh, __vh; \
21 \
22 __ul = __ll_lowpart(u); \
23 __uh = __ll_highpart(u); \
24 __vl = __ll_lowpart(v); \
25 __vh = __ll_highpart(v); \
26 \
27 __x0 = (UWtype) __ul * __vl; \
28 __x1 = (UWtype) __ul * __vh; \
29 __x2 = (UWtype) __uh * __vl; \
30 __x3 = (UWtype) __uh * __vh; \
31 \
32 __x1 += __ll_highpart(__x0); /* this can't give carry */\
33 __x1 += __x2; /* but this indeed can */ \
34 if (__x1 < __x2) /* did we get it? */ \
35 __x3 += __ll_B; /* yes, add it in the proper pos */ \
36 \
37 (w1) = __x3 + __ll_highpart(__x1); \
38 (w0) = __ll_lowpart(__x1) * __ll_B + __ll_lowpart(__x0);\
39 } while (0)
40#endif
41
42#if !defined(__umulsidi3)
43#define __umulsidi3(u, v) ({ \
44 DWunion __w; \
45 umul_ppmm(__w.s.high, __w.s.low, u, v); \
46 __w.ll; \
47 })
48#endif
49
50DWtype __muldi3(DWtype u, DWtype v)
51{
52 const DWunion uu = {.ll = u};
53 const DWunion vv = {.ll = v};
54 DWunion w = {.ll = __umulsidi3(uu.s.low, vv.s.low)};
55
56 w.s.high += ((UWtype) uu.s.low * (UWtype) vv.s.high
57 + (UWtype) uu.s.high * (UWtype) vv.s.low);
58
59 return w.ll;
60}
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 48fb4790bfec..959f38ccb9a7 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -20,6 +20,9 @@ config WORD_SIZE
20config ARCH_PHYS_ADDR_T_64BIT 20config ARCH_PHYS_ADDR_T_64BIT
21 def_bool PPC64 || PHYS_64BIT 21 def_bool PPC64 || PHYS_64BIT
22 22
23config ARCH_DMA_ADDR_T_64BIT
24 def_bool ARCH_PHYS_ADDR_T_64BIT
25
23config MMU 26config MMU
24 bool 27 bool
25 default y 28 default y
@@ -209,7 +212,7 @@ config ARCH_HIBERNATION_POSSIBLE
209config ARCH_SUSPEND_POSSIBLE 212config ARCH_SUSPEND_POSSIBLE
210 def_bool y 213 def_bool y
211 depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 || PPC_83xx || \ 214 depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 || PPC_83xx || \
212 PPC_85xx || PPC_86xx || PPC_PSERIES 215 PPC_85xx || PPC_86xx || PPC_PSERIES || 44x || 40x
213 216
214config PPC_DCR_NATIVE 217config PPC_DCR_NATIVE
215 bool 218 bool
@@ -595,13 +598,11 @@ config EXTRA_TARGETS
595 598
596 If unsure, leave blank 599 If unsure, leave blank
597 600
598if !44x || BROKEN
599config ARCH_WANTS_FREEZER_CONTROL 601config ARCH_WANTS_FREEZER_CONTROL
600 def_bool y 602 def_bool y
601 depends on ADB_PMU 603 depends on ADB_PMU
602 604
603source kernel/power/Kconfig 605source kernel/power/Kconfig
604endif
605 606
606config SECCOMP 607config SECCOMP
607 bool "Enable seccomp to safely compute untrusted bytecode" 608 bool "Enable seccomp to safely compute untrusted bytecode"
@@ -682,6 +683,15 @@ config FSL_PMC
682 Freescale MPC85xx/MPC86xx power management controller support 683 Freescale MPC85xx/MPC86xx power management controller support
683 (suspend/resume). For MPC83xx see platforms/83xx/suspend.c 684 (suspend/resume). For MPC83xx see platforms/83xx/suspend.c
684 685
686config PPC4xx_CPM
687 bool
688 default y
689 depends on SUSPEND && (44x || 40x)
690 help
691 PPC4xx Clock Power Management (CPM) support (suspend/resume).
692 It also enables support for two different idle states (idle-wait
693 and idle-doze).
694
685config 4xx_SOC 695config 4xx_SOC
686 bool 696 bool
687 697
diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts
index a30370396250..5b27a4b74b79 100644
--- a/arch/powerpc/boot/dts/canyonlands.dts
+++ b/arch/powerpc/boot/dts/canyonlands.dts
@@ -105,6 +105,15 @@
105 dcr-reg = <0x00c 0x002>; 105 dcr-reg = <0x00c 0x002>;
106 }; 106 };
107 107
108 CPM0: cpm {
109 compatible = "ibm,cpm";
110 dcr-access-method = "native";
111 dcr-reg = <0x160 0x003>;
112 unused-units = <0x00000100>;
113 idle-doze = <0x02000000>;
114 standby = <0xfeff791d>;
115 };
116
108 L2C0: l2c { 117 L2C0: l2c {
109 compatible = "ibm,l2-cache-460ex", "ibm,l2-cache"; 118 compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
110 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */ 119 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
@@ -270,28 +279,6 @@
270 interrupts = <0x1 0x4>; 279 interrupts = <0x1 0x4>;
271 }; 280 };
272 281
273 UART2: serial@ef600500 {
274 device_type = "serial";
275 compatible = "ns16550";
276 reg = <0xef600500 0x00000008>;
277 virtual-reg = <0xef600500>;
278 clock-frequency = <0>; /* Filled in by U-Boot */
279 current-speed = <0>; /* Filled in by U-Boot */
280 interrupt-parent = <&UIC1>;
281 interrupts = <28 0x4>;
282 };
283
284 UART3: serial@ef600600 {
285 device_type = "serial";
286 compatible = "ns16550";
287 reg = <0xef600600 0x00000008>;
288 virtual-reg = <0xef600600>;
289 clock-frequency = <0>; /* Filled in by U-Boot */
290 current-speed = <0>; /* Filled in by U-Boot */
291 interrupt-parent = <&UIC1>;
292 interrupts = <29 0x4>;
293 };
294
295 IIC0: i2c@ef600700 { 282 IIC0: i2c@ef600700 {
296 compatible = "ibm,iic-460ex", "ibm,iic"; 283 compatible = "ibm,iic-460ex", "ibm,iic";
297 reg = <0xef600700 0x00000014>; 284 reg = <0xef600700 0x00000014>;
diff --git a/arch/powerpc/boot/dts/kilauea.dts b/arch/powerpc/boot/dts/kilauea.dts
index 083e68eeaca4..89edb16649c3 100644
--- a/arch/powerpc/boot/dts/kilauea.dts
+++ b/arch/powerpc/boot/dts/kilauea.dts
@@ -82,6 +82,15 @@
82 interrupt-parent = <&UIC0>; 82 interrupt-parent = <&UIC0>;
83 }; 83 };
84 84
85 CPM0: cpm {
86 compatible = "ibm,cpm";
87 dcr-access-method = "native";
88 dcr-reg = <0x0b0 0x003>;
89 unused-units = <0x00000000>;
90 idle-doze = <0x02000000>;
91 standby = <0xe3e74800>;
92 };
93
85 plb { 94 plb {
86 compatible = "ibm,plb-405ex", "ibm,plb4"; 95 compatible = "ibm,plb-405ex", "ibm,plb4";
87 #address-cells = <1>; 96 #address-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc8308_p1m.dts b/arch/powerpc/boot/dts/mpc8308_p1m.dts
index 05a76ccfd499..697b3f6b78bf 100644
--- a/arch/powerpc/boot/dts/mpc8308_p1m.dts
+++ b/arch/powerpc/boot/dts/mpc8308_p1m.dts
@@ -297,6 +297,14 @@
297 interrupt-parent = < &ipic >; 297 interrupt-parent = < &ipic >;
298 }; 298 };
299 299
300 dma@2c000 {
301 compatible = "fsl,mpc8308-dma", "fsl,mpc5121-dma";
302 reg = <0x2c000 0x1800>;
303 interrupts = <3 0x8
304 94 0x8>;
305 interrupt-parent = < &ipic >;
306 };
307
300 }; 308 };
301 309
302 pci0: pcie@e0009000 { 310 pci0: pcie@e0009000 {
diff --git a/arch/powerpc/boot/dts/mpc8308rdb.dts b/arch/powerpc/boot/dts/mpc8308rdb.dts
index a97eb2db5a18..d3db02f98ddd 100644
--- a/arch/powerpc/boot/dts/mpc8308rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8308rdb.dts
@@ -265,6 +265,14 @@
265 interrupt-parent = < &ipic >; 265 interrupt-parent = < &ipic >;
266 }; 266 };
267 267
268 dma@2c000 {
269 compatible = "fsl,mpc8308-dma", "fsl,mpc5121-dma";
270 reg = <0x2c000 0x1800>;
271 interrupts = <3 0x8
272 94 0x8>;
273 interrupt-parent = < &ipic >;
274 };
275
268 }; 276 };
269 277
270 pci0: pcie@e0009000 { 278 pci0: pcie@e0009000 {
diff --git a/arch/powerpc/configs/40x/kilauea_defconfig b/arch/powerpc/configs/40x/kilauea_defconfig
index 4e19ee7ce4ee..34b8c1a1e752 100644
--- a/arch/powerpc/configs/40x/kilauea_defconfig
+++ b/arch/powerpc/configs/40x/kilauea_defconfig
@@ -12,6 +12,8 @@ CONFIG_MODULES=y
12CONFIG_MODULE_UNLOAD=y 12CONFIG_MODULE_UNLOAD=y
13# CONFIG_BLK_DEV_BSG is not set 13# CONFIG_BLK_DEV_BSG is not set
14CONFIG_KILAUEA=y 14CONFIG_KILAUEA=y
15CONFIG_NO_HZ=y
16CONFIG_HIGH_RES_TIMERS=y
15# CONFIG_WALNUT is not set 17# CONFIG_WALNUT is not set
16CONFIG_SPARSE_IRQ=y 18CONFIG_SPARSE_IRQ=y
17CONFIG_PCI=y 19CONFIG_PCI=y
@@ -42,6 +44,9 @@ CONFIG_MTD_PHYSMAP_OF=y
42CONFIG_MTD_NAND=y 44CONFIG_MTD_NAND=y
43CONFIG_MTD_NAND_NDFC=y 45CONFIG_MTD_NAND_NDFC=y
44CONFIG_PROC_DEVICETREE=y 46CONFIG_PROC_DEVICETREE=y
47CONFIG_PM=y
48CONFIG_SUSPEND=y
49CONFIG_PPC4xx_CPM=y
45CONFIG_BLK_DEV_RAM=y 50CONFIG_BLK_DEV_RAM=y
46CONFIG_BLK_DEV_RAM_SIZE=35000 51CONFIG_BLK_DEV_RAM_SIZE=35000
47# CONFIG_MISC_DEVICES is not set 52# CONFIG_MISC_DEVICES is not set
diff --git a/arch/powerpc/configs/44x/canyonlands_defconfig b/arch/powerpc/configs/44x/canyonlands_defconfig
index 45c64d818b2a..17e4dd98eed7 100644
--- a/arch/powerpc/configs/44x/canyonlands_defconfig
+++ b/arch/powerpc/configs/44x/canyonlands_defconfig
@@ -42,6 +42,9 @@ CONFIG_MTD_PHYSMAP_OF=y
42CONFIG_MTD_NAND=y 42CONFIG_MTD_NAND=y
43CONFIG_MTD_NAND_NDFC=y 43CONFIG_MTD_NAND_NDFC=y
44CONFIG_PROC_DEVICETREE=y 44CONFIG_PROC_DEVICETREE=y
45CONFIG_PM=y
46CONFIG_SUSPEND=y
47CONFIG_PPC4xx_CPM=y
45CONFIG_BLK_DEV_RAM=y 48CONFIG_BLK_DEV_RAM=y
46CONFIG_BLK_DEV_RAM_SIZE=35000 49CONFIG_BLK_DEV_RAM_SIZE=35000
47# CONFIG_MISC_DEVICES is not set 50# CONFIG_MISC_DEVICES is not set
diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h
index 30964ae2d096..8a7e9314c68a 100644
--- a/arch/powerpc/include/asm/bitops.h
+++ b/arch/powerpc/include/asm/bitops.h
@@ -267,7 +267,16 @@ static __inline__ int fls64(__u64 x)
267#include <asm-generic/bitops/fls64.h> 267#include <asm-generic/bitops/fls64.h>
268#endif /* __powerpc64__ */ 268#endif /* __powerpc64__ */
269 269
270#ifdef CONFIG_PPC64
271unsigned int __arch_hweight8(unsigned int w);
272unsigned int __arch_hweight16(unsigned int w);
273unsigned int __arch_hweight32(unsigned int w);
274unsigned long __arch_hweight64(__u64 w);
275#include <asm-generic/bitops/const_hweight.h>
276#else
270#include <asm-generic/bitops/hweight.h> 277#include <asm-generic/bitops/hweight.h>
278#endif
279
271#include <asm-generic/bitops/find.h> 280#include <asm-generic/bitops/find.h>
272 281
273/* Little-endian versions */ 282/* Little-endian versions */
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index f3a1fdd9cf08..f0a211d96923 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -199,6 +199,8 @@ extern const char *powerpc_base_platform;
199#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0080000000000000) 199#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0080000000000000)
200#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0100000000000000) 200#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0100000000000000)
201#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0200000000000000) 201#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0200000000000000)
202#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0400000000000000)
203#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0800000000000000)
202 204
203#ifndef __ASSEMBLY__ 205#ifndef __ASSEMBLY__
204 206
@@ -403,21 +405,22 @@ extern const char *powerpc_base_platform;
403 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 405 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
404 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 406 CPU_FTR_MMCRA | CPU_FTR_SMT | \
405 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ 407 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
406 CPU_FTR_PURR | CPU_FTR_STCX_CHECKS_ADDRESS) 408 CPU_FTR_PURR | CPU_FTR_STCX_CHECKS_ADDRESS | \
409 CPU_FTR_POPCNTB)
407#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 410#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
408 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 411 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
409 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 412 CPU_FTR_MMCRA | CPU_FTR_SMT | \
410 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ 413 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
411 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 414 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
412 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \ 415 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
413 CPU_FTR_STCX_CHECKS_ADDRESS) 416 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
414#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 417#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
415 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 418 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
416 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 419 CPU_FTR_MMCRA | CPU_FTR_SMT | \
417 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ 420 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
418 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 421 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
419 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \ 422 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
420 CPU_FTR_STCX_CHECKS_ADDRESS) 423 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD)
421#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 424#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
422 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 425 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
423 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ 426 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
diff --git a/arch/powerpc/include/asm/cputhreads.h b/arch/powerpc/include/asm/cputhreads.h
index a8e18447c62b..f71bb4c118b4 100644
--- a/arch/powerpc/include/asm/cputhreads.h
+++ b/arch/powerpc/include/asm/cputhreads.h
@@ -61,22 +61,25 @@ static inline cpumask_t cpu_online_cores_map(void)
61 return cpu_thread_mask_to_cores(cpu_online_map); 61 return cpu_thread_mask_to_cores(cpu_online_map);
62} 62}
63 63
64static inline int cpu_thread_to_core(int cpu) 64#ifdef CONFIG_SMP
65{ 65int cpu_core_index_of_thread(int cpu);
66 return cpu >> threads_shift; 66int cpu_first_thread_of_core(int core);
67} 67#else
68static inline int cpu_core_index_of_thread(int cpu) { return cpu; }
69static inline int cpu_first_thread_of_core(int core) { return core; }
70#endif
68 71
69static inline int cpu_thread_in_core(int cpu) 72static inline int cpu_thread_in_core(int cpu)
70{ 73{
71 return cpu & (threads_per_core - 1); 74 return cpu & (threads_per_core - 1);
72} 75}
73 76
74static inline int cpu_first_thread_in_core(int cpu) 77static inline int cpu_first_thread_sibling(int cpu)
75{ 78{
76 return cpu & ~(threads_per_core - 1); 79 return cpu & ~(threads_per_core - 1);
77} 80}
78 81
79static inline int cpu_last_thread_in_core(int cpu) 82static inline int cpu_last_thread_sibling(int cpu)
80{ 83{
81 return cpu | (threads_per_core - 1); 84 return cpu | (threads_per_core - 1);
82} 85}
diff --git a/arch/powerpc/include/asm/device.h b/arch/powerpc/include/asm/device.h
index a3954e4fcbe2..16d25c0974be 100644
--- a/arch/powerpc/include/asm/device.h
+++ b/arch/powerpc/include/asm/device.h
@@ -9,6 +9,12 @@
9struct dma_map_ops; 9struct dma_map_ops;
10struct device_node; 10struct device_node;
11 11
12/*
13 * Arch extensions to struct device.
14 *
15 * When adding fields, consider macio_add_one_device in
16 * drivers/macintosh/macio_asic.c
17 */
12struct dev_archdata { 18struct dev_archdata {
13 /* DMA operations on that device */ 19 /* DMA operations on that device */
14 struct dma_map_ops *dma_ops; 20 struct dma_map_ops *dma_ops;
diff --git a/arch/powerpc/include/asm/firmware.h b/arch/powerpc/include/asm/firmware.h
index 20778a405d7a..4ef662e4a31d 100644
--- a/arch/powerpc/include/asm/firmware.h
+++ b/arch/powerpc/include/asm/firmware.h
@@ -46,6 +46,7 @@
46#define FW_FEATURE_PS3_LV1 ASM_CONST(0x0000000000800000) 46#define FW_FEATURE_PS3_LV1 ASM_CONST(0x0000000000800000)
47#define FW_FEATURE_BEAT ASM_CONST(0x0000000001000000) 47#define FW_FEATURE_BEAT ASM_CONST(0x0000000001000000)
48#define FW_FEATURE_CMO ASM_CONST(0x0000000002000000) 48#define FW_FEATURE_CMO ASM_CONST(0x0000000002000000)
49#define FW_FEATURE_VPHN ASM_CONST(0x0000000004000000)
49 50
50#ifndef __ASSEMBLY__ 51#ifndef __ASSEMBLY__
51 52
@@ -59,7 +60,7 @@ enum {
59 FW_FEATURE_VIO | FW_FEATURE_RDMA | FW_FEATURE_LLAN | 60 FW_FEATURE_VIO | FW_FEATURE_RDMA | FW_FEATURE_LLAN |
60 FW_FEATURE_BULK_REMOVE | FW_FEATURE_XDABR | 61 FW_FEATURE_BULK_REMOVE | FW_FEATURE_XDABR |
61 FW_FEATURE_MULTITCE | FW_FEATURE_SPLPAR | FW_FEATURE_LPAR | 62 FW_FEATURE_MULTITCE | FW_FEATURE_SPLPAR | FW_FEATURE_LPAR |
62 FW_FEATURE_CMO, 63 FW_FEATURE_CMO | FW_FEATURE_VPHN,
63 FW_FEATURE_PSERIES_ALWAYS = 0, 64 FW_FEATURE_PSERIES_ALWAYS = 0,
64 FW_FEATURE_ISERIES_POSSIBLE = FW_FEATURE_ISERIES | FW_FEATURE_LPAR, 65 FW_FEATURE_ISERIES_POSSIBLE = FW_FEATURE_ISERIES | FW_FEATURE_LPAR,
65 FW_FEATURE_ISERIES_ALWAYS = FW_FEATURE_ISERIES | FW_FEATURE_LPAR, 66 FW_FEATURE_ISERIES_ALWAYS = FW_FEATURE_ISERIES | FW_FEATURE_LPAR,
diff --git a/arch/powerpc/include/asm/hvcall.h b/arch/powerpc/include/asm/hvcall.h
index de03ca58db5d..ec089acfa56b 100644
--- a/arch/powerpc/include/asm/hvcall.h
+++ b/arch/powerpc/include/asm/hvcall.h
@@ -232,7 +232,9 @@
232#define H_GET_EM_PARMS 0x2B8 232#define H_GET_EM_PARMS 0x2B8
233#define H_SET_MPP 0x2D0 233#define H_SET_MPP 0x2D0
234#define H_GET_MPP 0x2D4 234#define H_GET_MPP 0x2D4
235#define MAX_HCALL_OPCODE H_GET_MPP 235#define H_HOME_NODE_ASSOCIATIVITY 0x2EC
236#define H_BEST_ENERGY 0x2F4
237#define MAX_HCALL_OPCODE H_BEST_ENERGY
236 238
237#ifndef __ASSEMBLY__ 239#ifndef __ASSEMBLY__
238 240
diff --git a/arch/powerpc/include/asm/lppaca.h b/arch/powerpc/include/asm/lppaca.h
index 7f5e0fefebb0..380d48bacd16 100644
--- a/arch/powerpc/include/asm/lppaca.h
+++ b/arch/powerpc/include/asm/lppaca.h
@@ -62,7 +62,10 @@ struct lppaca {
62 volatile u32 dyn_pir; // Dynamic ProcIdReg value x20-x23 62 volatile u32 dyn_pir; // Dynamic ProcIdReg value x20-x23
63 u32 dsei_data; // DSEI data x24-x27 63 u32 dsei_data; // DSEI data x24-x27
64 u64 sprg3; // SPRG3 value x28-x2F 64 u64 sprg3; // SPRG3 value x28-x2F
65 u8 reserved3[80]; // Reserved x30-x7F 65 u8 reserved3[40]; // Reserved x30-x57
66 volatile u8 vphn_assoc_counts[8]; // Virtual processor home node
67 // associativity change counters x58-x5F
68 u8 reserved4[32]; // Reserved x60-x7F
66 69
67//============================================================================= 70//=============================================================================
68// CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data 71// CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index d045b0145537..8433d36619a1 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -27,9 +27,7 @@ struct iommu_table;
27struct rtc_time; 27struct rtc_time;
28struct file; 28struct file;
29struct pci_controller; 29struct pci_controller;
30#ifdef CONFIG_KEXEC
31struct kimage; 30struct kimage;
32#endif
33 31
34#ifdef CONFIG_SMP 32#ifdef CONFIG_SMP
35struct smp_ops_t { 33struct smp_ops_t {
@@ -72,7 +70,7 @@ struct machdep_calls {
72 int psize, int ssize); 70 int psize, int ssize);
73 void (*flush_hash_range)(unsigned long number, int local); 71 void (*flush_hash_range)(unsigned long number, int local);
74 72
75 /* special for kexec, to be called in real mode, linar mapping is 73 /* special for kexec, to be called in real mode, linear mapping is
76 * destroyed as well */ 74 * destroyed as well */
77 void (*hpte_clear_all)(void); 75 void (*hpte_clear_all)(void);
78 76
@@ -324,8 +322,6 @@ extern sys_ctrler_t sys_ctrler;
324 322
325#endif /* CONFIG_PPC_PMAC */ 323#endif /* CONFIG_PPC_PMAC */
326 324
327extern void setup_pci_ptrs(void);
328
329#ifdef CONFIG_SMP 325#ifdef CONFIG_SMP
330/* Poor default implementations */ 326/* Poor default implementations */
331extern void __devinit smp_generic_give_timebase(void); 327extern void __devinit smp_generic_give_timebase(void);
diff --git a/arch/powerpc/include/asm/mmzone.h b/arch/powerpc/include/asm/mmzone.h
index aac87cbceb57..fd3fd58bad84 100644
--- a/arch/powerpc/include/asm/mmzone.h
+++ b/arch/powerpc/include/asm/mmzone.h
@@ -33,6 +33,9 @@ extern int numa_cpu_lookup_table[];
33extern cpumask_var_t node_to_cpumask_map[]; 33extern cpumask_var_t node_to_cpumask_map[];
34#ifdef CONFIG_MEMORY_HOTPLUG 34#ifdef CONFIG_MEMORY_HOTPLUG
35extern unsigned long max_pfn; 35extern unsigned long max_pfn;
36u64 memory_hotplug_max(void);
37#else
38#define memory_hotplug_max() memblock_end_of_DRAM()
36#endif 39#endif
37 40
38/* 41/*
@@ -42,6 +45,8 @@ extern unsigned long max_pfn;
42#define node_start_pfn(nid) (NODE_DATA(nid)->node_start_pfn) 45#define node_start_pfn(nid) (NODE_DATA(nid)->node_start_pfn)
43#define node_end_pfn(nid) (NODE_DATA(nid)->node_end_pfn) 46#define node_end_pfn(nid) (NODE_DATA(nid)->node_end_pfn)
44 47
48#else
49#define memory_hotplug_max() memblock_end_of_DRAM()
45#endif /* CONFIG_NEED_MULTIPLE_NODES */ 50#endif /* CONFIG_NEED_MULTIPLE_NODES */
46 51
47#endif /* __KERNEL__ */ 52#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/nvram.h b/arch/powerpc/include/asm/nvram.h
index 850b72f27445..92efe67d1c57 100644
--- a/arch/powerpc/include/asm/nvram.h
+++ b/arch/powerpc/include/asm/nvram.h
@@ -10,31 +10,7 @@
10#ifndef _ASM_POWERPC_NVRAM_H 10#ifndef _ASM_POWERPC_NVRAM_H
11#define _ASM_POWERPC_NVRAM_H 11#define _ASM_POWERPC_NVRAM_H
12 12
13#include <linux/errno.h> 13/* Signatures for nvram partitions */
14
15#define NVRW_CNT 0x20
16#define NVRAM_HEADER_LEN 16 /* sizeof(struct nvram_header) */
17#define NVRAM_BLOCK_LEN 16
18#define NVRAM_MAX_REQ (2080/NVRAM_BLOCK_LEN)
19#define NVRAM_MIN_REQ (1056/NVRAM_BLOCK_LEN)
20
21#define NVRAM_AS0 0x74
22#define NVRAM_AS1 0x75
23#define NVRAM_DATA 0x77
24
25
26/* RTC Offsets */
27
28#define MOTO_RTC_SECONDS 0x1FF9
29#define MOTO_RTC_MINUTES 0x1FFA
30#define MOTO_RTC_HOURS 0x1FFB
31#define MOTO_RTC_DAY_OF_WEEK 0x1FFC
32#define MOTO_RTC_DAY_OF_MONTH 0x1FFD
33#define MOTO_RTC_MONTH 0x1FFE
34#define MOTO_RTC_YEAR 0x1FFF
35#define MOTO_RTC_CONTROLA 0x1FF8
36#define MOTO_RTC_CONTROLB 0x1FF9
37
38#define NVRAM_SIG_SP 0x02 /* support processor */ 14#define NVRAM_SIG_SP 0x02 /* support processor */
39#define NVRAM_SIG_OF 0x50 /* open firmware config */ 15#define NVRAM_SIG_OF 0x50 /* open firmware config */
40#define NVRAM_SIG_FW 0x51 /* general firmware */ 16#define NVRAM_SIG_FW 0x51 /* general firmware */
@@ -49,32 +25,19 @@
49#define NVRAM_SIG_OS 0xa0 /* OS defined */ 25#define NVRAM_SIG_OS 0xa0 /* OS defined */
50#define NVRAM_SIG_PANIC 0xa1 /* Apple OSX "panic" */ 26#define NVRAM_SIG_PANIC 0xa1 /* Apple OSX "panic" */
51 27
52/* If change this size, then change the size of NVNAME_LEN */
53struct nvram_header {
54 unsigned char signature;
55 unsigned char checksum;
56 unsigned short length;
57 char name[12];
58};
59
60#ifdef __KERNEL__ 28#ifdef __KERNEL__
61 29
30#include <linux/errno.h>
62#include <linux/list.h> 31#include <linux/list.h>
63 32
64struct nvram_partition { 33#ifdef CONFIG_PPC_PSERIES
65 struct list_head partition;
66 struct nvram_header header;
67 unsigned int index;
68};
69
70
71extern int nvram_write_error_log(char * buff, int length, 34extern int nvram_write_error_log(char * buff, int length,
72 unsigned int err_type, unsigned int err_seq); 35 unsigned int err_type, unsigned int err_seq);
73extern int nvram_read_error_log(char * buff, int length, 36extern int nvram_read_error_log(char * buff, int length,
74 unsigned int * err_type, unsigned int *err_seq); 37 unsigned int * err_type, unsigned int *err_seq);
75extern int nvram_clear_error_log(void); 38extern int nvram_clear_error_log(void);
76
77extern int pSeries_nvram_init(void); 39extern int pSeries_nvram_init(void);
40#endif /* CONFIG_PPC_PSERIES */
78 41
79#ifdef CONFIG_MMIO_NVRAM 42#ifdef CONFIG_MMIO_NVRAM
80extern int mmio_nvram_init(void); 43extern int mmio_nvram_init(void);
@@ -85,6 +48,13 @@ static inline int mmio_nvram_init(void)
85} 48}
86#endif 49#endif
87 50
51extern int __init nvram_scan_partitions(void);
52extern loff_t nvram_create_partition(const char *name, int sig,
53 int req_size, int min_size);
54extern int nvram_remove_partition(const char *name, int sig);
55extern int nvram_get_partition_size(loff_t data_index);
56extern loff_t nvram_find_partition(const char *name, int sig, int *out_size);
57
88#endif /* __KERNEL__ */ 58#endif /* __KERNEL__ */
89 59
90/* PowerMac specific nvram stuffs */ 60/* PowerMac specific nvram stuffs */
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index 43adc8b819ed..1255569387b6 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -36,6 +36,8 @@
36#define PPC_INST_NOP 0x60000000 36#define PPC_INST_NOP 0x60000000
37#define PPC_INST_POPCNTB 0x7c0000f4 37#define PPC_INST_POPCNTB 0x7c0000f4
38#define PPC_INST_POPCNTB_MASK 0xfc0007fe 38#define PPC_INST_POPCNTB_MASK 0xfc0007fe
39#define PPC_INST_POPCNTD 0x7c0003f4
40#define PPC_INST_POPCNTW 0x7c0002f4
39#define PPC_INST_RFCI 0x4c000066 41#define PPC_INST_RFCI 0x4c000066
40#define PPC_INST_RFDI 0x4c00004e 42#define PPC_INST_RFDI 0x4c00004e
41#define PPC_INST_RFMCI 0x4c00004c 43#define PPC_INST_RFMCI 0x4c00004c
@@ -88,6 +90,12 @@
88 __PPC_RB(b) | __PPC_EH(eh)) 90 __PPC_RB(b) | __PPC_EH(eh))
89#define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND | \ 91#define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND | \
90 __PPC_RB(b)) 92 __PPC_RB(b))
93#define PPC_POPCNTB(a, s) stringify_in_c(.long PPC_INST_POPCNTB | \
94 __PPC_RA(a) | __PPC_RS(s))
95#define PPC_POPCNTD(a, s) stringify_in_c(.long PPC_INST_POPCNTD | \
96 __PPC_RA(a) | __PPC_RS(s))
97#define PPC_POPCNTW(a, s) stringify_in_c(.long PPC_INST_POPCNTW | \
98 __PPC_RA(a) | __PPC_RS(s))
91#define PPC_RFCI stringify_in_c(.long PPC_INST_RFCI) 99#define PPC_RFCI stringify_in_c(.long PPC_INST_RFCI)
92#define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI) 100#define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI)
93#define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI) 101#define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI)
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 4c14187ba02d..de1967a1ff57 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -122,7 +122,6 @@ extern struct task_struct *last_task_used_spe;
122 TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 ) 122 TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
123#endif 123#endif
124 124
125#ifdef __KERNEL__
126#ifdef __powerpc64__ 125#ifdef __powerpc64__
127 126
128#define STACK_TOP_USER64 TASK_SIZE_USER64 127#define STACK_TOP_USER64 TASK_SIZE_USER64
@@ -139,7 +138,6 @@ extern struct task_struct *last_task_used_spe;
139#define STACK_TOP_MAX STACK_TOP 138#define STACK_TOP_MAX STACK_TOP
140 139
141#endif /* __powerpc64__ */ 140#endif /* __powerpc64__ */
142#endif /* __KERNEL__ */
143 141
144typedef struct { 142typedef struct {
145 unsigned long seg; 143 unsigned long seg;
diff --git a/arch/powerpc/include/asm/topology.h b/arch/powerpc/include/asm/topology.h
index afe4aaa65c3b..7ef0d90defc8 100644
--- a/arch/powerpc/include/asm/topology.h
+++ b/arch/powerpc/include/asm/topology.h
@@ -106,9 +106,22 @@ static inline void sysfs_remove_device_from_node(struct sys_device *dev,
106 int nid) 106 int nid)
107{ 107{
108} 108}
109
110#endif /* CONFIG_NUMA */ 109#endif /* CONFIG_NUMA */
111 110
111#if defined(CONFIG_NUMA) && defined(CONFIG_PPC_SPLPAR)
112extern int start_topology_update(void);
113extern int stop_topology_update(void);
114#else
115static inline int start_topology_update(void)
116{
117 return 0;
118}
119static inline int stop_topology_update(void)
120{
121 return 0;
122}
123#endif /* CONFIG_NUMA && CONFIG_PPC_SPLPAR */
124
112#include <asm-generic/topology.h> 125#include <asm-generic/topology.h>
113 126
114#ifdef CONFIG_SMP 127#ifdef CONFIG_SMP
diff --git a/arch/powerpc/include/asm/vdso_datapage.h b/arch/powerpc/include/asm/vdso_datapage.h
index 08679c5319b8..25e39220e89c 100644
--- a/arch/powerpc/include/asm/vdso_datapage.h
+++ b/arch/powerpc/include/asm/vdso_datapage.h
@@ -116,9 +116,7 @@ struct vdso_data {
116 116
117#endif /* CONFIG_PPC64 */ 117#endif /* CONFIG_PPC64 */
118 118
119#ifdef __KERNEL__
120extern struct vdso_data *vdso_data; 119extern struct vdso_data *vdso_data;
121#endif
122 120
123#endif /* __ASSEMBLY__ */ 121#endif /* __ASSEMBLY__ */
124 122
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 36c30f31ec93..3bb2a3e6a337 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -29,8 +29,10 @@ endif
29obj-y := cputable.o ptrace.o syscalls.o \ 29obj-y := cputable.o ptrace.o syscalls.o \
30 irq.o align.o signal_32.o pmc.o vdso.o \ 30 irq.o align.o signal_32.o pmc.o vdso.o \
31 init_task.o process.o systbl.o idle.o \ 31 init_task.o process.o systbl.o idle.o \
32 signal.o sysfs.o cacheinfo.o 32 signal.o sysfs.o cacheinfo.o time.o \
33obj-y += vdso32/ 33 prom.o traps.o setup-common.o \
34 udbg.o misc.o io.o dma.o \
35 misc_$(CONFIG_WORD_SIZE).o vdso32/
34obj-$(CONFIG_PPC64) += setup_64.o sys_ppc32.o \ 36obj-$(CONFIG_PPC64) += setup_64.o sys_ppc32.o \
35 signal_64.o ptrace32.o \ 37 signal_64.o ptrace32.o \
36 paca.o nvram_64.o firmware.o 38 paca.o nvram_64.o firmware.o
@@ -80,9 +82,6 @@ extra-$(CONFIG_FSL_BOOKE) := head_fsl_booke.o
80extra-$(CONFIG_8xx) := head_8xx.o 82extra-$(CONFIG_8xx) := head_8xx.o
81extra-y += vmlinux.lds 83extra-y += vmlinux.lds
82 84
83obj-y += time.o prom.o traps.o setup-common.o \
84 udbg.o misc.o io.o dma.o \
85 misc_$(CONFIG_WORD_SIZE).o
86obj-$(CONFIG_PPC32) += entry_32.o setup_32.o 85obj-$(CONFIG_PPC32) += entry_32.o setup_32.o
87obj-$(CONFIG_PPC64) += dma-iommu.o iommu.o 86obj-$(CONFIG_PPC64) += dma-iommu.o iommu.o
88obj-$(CONFIG_KGDB) += kgdb.o 87obj-$(CONFIG_KGDB) += kgdb.o
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index bd0df2e6aa8f..23e6a93145ab 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -209,7 +209,6 @@ int main(void)
209 DEFINE(RTASENTRY, offsetof(struct rtas_t, entry)); 209 DEFINE(RTASENTRY, offsetof(struct rtas_t, entry));
210 210
211 /* Interrupt register frame */ 211 /* Interrupt register frame */
212 DEFINE(STACK_FRAME_OVERHEAD, STACK_FRAME_OVERHEAD);
213 DEFINE(INT_FRAME_SIZE, STACK_INT_FRAME_SIZE); 212 DEFINE(INT_FRAME_SIZE, STACK_INT_FRAME_SIZE);
214 DEFINE(SWITCH_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs)); 213 DEFINE(SWITCH_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs));
215#ifdef CONFIG_PPC64 214#ifdef CONFIG_PPC64
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 96a908f1cd87..be5ab18b03b5 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -457,16 +457,26 @@ static struct cpu_spec __initdata cpu_specs[] = {
457 .dcache_bsize = 128, 457 .dcache_bsize = 128,
458 .num_pmcs = 6, 458 .num_pmcs = 6,
459 .pmc_type = PPC_PMC_IBM, 459 .pmc_type = PPC_PMC_IBM,
460 .cpu_setup = __setup_cpu_power7,
461 .cpu_restore = __restore_cpu_power7,
462 .oprofile_cpu_type = "ppc64/power7", 460 .oprofile_cpu_type = "ppc64/power7",
463 .oprofile_type = PPC_OPROFILE_POWER4, 461 .oprofile_type = PPC_OPROFILE_POWER4,
464 .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
465 .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR,
466 .oprofile_mmcra_clear = POWER6_MMCRA_THRM |
467 POWER6_MMCRA_OTHER,
468 .platform = "power7", 462 .platform = "power7",
469 }, 463 },
464 { /* Power7+ */
465 .pvr_mask = 0xffff0000,
466 .pvr_value = 0x004A0000,
467 .cpu_name = "POWER7+ (raw)",
468 .cpu_features = CPU_FTRS_POWER7,
469 .cpu_user_features = COMMON_USER_POWER7,
470 .mmu_features = MMU_FTR_HPTE_TABLE |
471 MMU_FTR_TLBIE_206,
472 .icache_bsize = 128,
473 .dcache_bsize = 128,
474 .num_pmcs = 6,
475 .pmc_type = PPC_PMC_IBM,
476 .oprofile_cpu_type = "ppc64/power7",
477 .oprofile_type = PPC_OPROFILE_POWER4,
478 .platform = "power7+",
479 },
470 { /* Cell Broadband Engine */ 480 { /* Cell Broadband Engine */
471 .pvr_mask = 0xffff0000, 481 .pvr_mask = 0xffff0000,
472 .pvr_value = 0x00700000, 482 .pvr_value = 0x00700000,
diff --git a/arch/powerpc/kernel/crash_dump.c b/arch/powerpc/kernel/crash_dump.c
index 8e05c16344e4..0a2af50243cb 100644
--- a/arch/powerpc/kernel/crash_dump.c
+++ b/arch/powerpc/kernel/crash_dump.c
@@ -19,6 +19,7 @@
19#include <asm/prom.h> 19#include <asm/prom.h>
20#include <asm/firmware.h> 20#include <asm/firmware.h>
21#include <asm/uaccess.h> 21#include <asm/uaccess.h>
22#include <asm/rtas.h>
22 23
23#ifdef DEBUG 24#ifdef DEBUG
24#include <asm/udbg.h> 25#include <asm/udbg.h>
@@ -141,3 +142,35 @@ ssize_t copy_oldmem_page(unsigned long pfn, char *buf,
141 142
142 return csize; 143 return csize;
143} 144}
145
146#ifdef CONFIG_PPC_RTAS
147/*
148 * The crashkernel region will almost always overlap the RTAS region, so
149 * we have to be careful when shrinking the crashkernel region.
150 */
151void crash_free_reserved_phys_range(unsigned long begin, unsigned long end)
152{
153 unsigned long addr;
154 const u32 *basep, *sizep;
155 unsigned int rtas_start = 0, rtas_end = 0;
156
157 basep = of_get_property(rtas.dev, "linux,rtas-base", NULL);
158 sizep = of_get_property(rtas.dev, "rtas-size", NULL);
159
160 if (basep && sizep) {
161 rtas_start = *basep;
162 rtas_end = *basep + *sizep;
163 }
164
165 for (addr = begin; addr < end; addr += PAGE_SIZE) {
166 /* Does this page overlap with the RTAS region? */
167 if (addr <= rtas_end && ((addr + PAGE_SIZE) > rtas_start))
168 continue;
169
170 ClearPageReserved(pfn_to_page(addr >> PAGE_SHIFT));
171 init_page_count(pfn_to_page(addr >> PAGE_SHIFT));
172 free_page((unsigned long)__va(addr));
173 totalram_pages++;
174 }
175}
176#endif
diff --git a/arch/powerpc/kernel/dma-iommu.c b/arch/powerpc/kernel/dma-iommu.c
index 6e54a0fd31aa..e7554154a6de 100644
--- a/arch/powerpc/kernel/dma-iommu.c
+++ b/arch/powerpc/kernel/dma-iommu.c
@@ -19,7 +19,7 @@ static void *dma_iommu_alloc_coherent(struct device *dev, size_t size,
19 dma_addr_t *dma_handle, gfp_t flag) 19 dma_addr_t *dma_handle, gfp_t flag)
20{ 20{
21 return iommu_alloc_coherent(dev, get_iommu_table_base(dev), size, 21 return iommu_alloc_coherent(dev, get_iommu_table_base(dev), size,
22 dma_handle, device_to_mask(dev), flag, 22 dma_handle, dev->coherent_dma_mask, flag,
23 dev_to_node(dev)); 23 dev_to_node(dev));
24} 24}
25 25
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index ed4aeb96398b..c22dc1ec1c94 100644
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -31,6 +31,7 @@
31#include <asm/asm-offsets.h> 31#include <asm/asm-offsets.h>
32#include <asm/unistd.h> 32#include <asm/unistd.h>
33#include <asm/ftrace.h> 33#include <asm/ftrace.h>
34#include <asm/ptrace.h>
34 35
35#undef SHOW_SYSCALLS 36#undef SHOW_SYSCALLS
36#undef SHOW_SYSCALLS_TASK 37#undef SHOW_SYSCALLS_TASK
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 9f8b01d6466f..8a817995b4cd 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -13,6 +13,7 @@
13 */ 13 */
14 14
15#include <asm/exception-64s.h> 15#include <asm/exception-64s.h>
16#include <asm/ptrace.h>
16 17
17/* 18/*
18 * We layout physical memory as follows: 19 * We layout physical memory as follows:
diff --git a/arch/powerpc/kernel/fpu.S b/arch/powerpc/kernel/fpu.S
index e86c040ae585..de369558bf0a 100644
--- a/arch/powerpc/kernel/fpu.S
+++ b/arch/powerpc/kernel/fpu.S
@@ -23,6 +23,7 @@
23#include <asm/thread_info.h> 23#include <asm/thread_info.h>
24#include <asm/ppc_asm.h> 24#include <asm/ppc_asm.h>
25#include <asm/asm-offsets.h> 25#include <asm/asm-offsets.h>
26#include <asm/ptrace.h>
26 27
27#ifdef CONFIG_VSX 28#ifdef CONFIG_VSX
28#define REST_32FPVSRS(n,c,base) \ 29#define REST_32FPVSRS(n,c,base) \
diff --git a/arch/powerpc/kernel/head_40x.S b/arch/powerpc/kernel/head_40x.S
index 8278e8bad5a0..9dd21a8c4d52 100644
--- a/arch/powerpc/kernel/head_40x.S
+++ b/arch/powerpc/kernel/head_40x.S
@@ -40,6 +40,7 @@
40#include <asm/thread_info.h> 40#include <asm/thread_info.h>
41#include <asm/ppc_asm.h> 41#include <asm/ppc_asm.h>
42#include <asm/asm-offsets.h> 42#include <asm/asm-offsets.h>
43#include <asm/ptrace.h>
43 44
44/* As with the other PowerPC ports, it is expected that when code 45/* As with the other PowerPC ports, it is expected that when code
45 * execution begins here, the following registers contain valid, yet 46 * execution begins here, the following registers contain valid, yet
diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S
index 562305b40a8e..cbb3436b592d 100644
--- a/arch/powerpc/kernel/head_44x.S
+++ b/arch/powerpc/kernel/head_44x.S
@@ -37,6 +37,7 @@
37#include <asm/thread_info.h> 37#include <asm/thread_info.h>
38#include <asm/ppc_asm.h> 38#include <asm/ppc_asm.h>
39#include <asm/asm-offsets.h> 39#include <asm/asm-offsets.h>
40#include <asm/ptrace.h>
40#include <asm/synch.h> 41#include <asm/synch.h>
41#include "head_booke.h" 42#include "head_booke.h"
42 43
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index f0dd577e4a5b..782f23df7c85 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -38,6 +38,7 @@
38#include <asm/page_64.h> 38#include <asm/page_64.h>
39#include <asm/irqflags.h> 39#include <asm/irqflags.h>
40#include <asm/kvm_book3s_asm.h> 40#include <asm/kvm_book3s_asm.h>
41#include <asm/ptrace.h>
41 42
42/* The physical memory is layed out such that the secondary processor 43/* The physical memory is layed out such that the secondary processor
43 * spin code sits at 0x0000...0x00ff. On server, the vectors follow 44 * spin code sits at 0x0000...0x00ff. On server, the vectors follow
@@ -96,7 +97,7 @@ __secondary_hold_acknowledge:
96 .llong hvReleaseData-KERNELBASE 97 .llong hvReleaseData-KERNELBASE
97#endif /* CONFIG_PPC_ISERIES */ 98#endif /* CONFIG_PPC_ISERIES */
98 99
99#ifdef CONFIG_CRASH_DUMP 100#ifdef CONFIG_RELOCATABLE
100 /* This flag is set to 1 by a loader if the kernel should run 101 /* This flag is set to 1 by a loader if the kernel should run
101 * at the loaded address instead of the linked address. This 102 * at the loaded address instead of the linked address. This
102 * is used by kexec-tools to keep the the kdump kernel in the 103 * is used by kexec-tools to keep the the kdump kernel in the
@@ -384,12 +385,10 @@ _STATIC(__after_prom_start)
384 /* process relocations for the final address of the kernel */ 385 /* process relocations for the final address of the kernel */
385 lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */ 386 lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */
386 sldi r25,r25,32 387 sldi r25,r25,32
387#ifdef CONFIG_CRASH_DUMP
388 lwz r7,__run_at_load-_stext(r26) 388 lwz r7,__run_at_load-_stext(r26)
389 cmplwi cr0,r7,1 /* kdump kernel ? - stay where we are */ 389 cmplwi cr0,r7,1 /* flagged to stay where we are ? */
390 bne 1f 390 bne 1f
391 add r25,r25,r26 391 add r25,r25,r26
392#endif
3931: mr r3,r25 3921: mr r3,r25
394 bl .relocate 393 bl .relocate
395#endif 394#endif
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 1f1a04b5c2a4..1cbf64e6b416 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -29,6 +29,7 @@
29#include <asm/thread_info.h> 29#include <asm/thread_info.h>
30#include <asm/ppc_asm.h> 30#include <asm/ppc_asm.h>
31#include <asm/asm-offsets.h> 31#include <asm/asm-offsets.h>
32#include <asm/ptrace.h>
32 33
33/* Macro to make the code more readable. */ 34/* Macro to make the code more readable. */
34#ifdef CONFIG_8xx_CPU6 35#ifdef CONFIG_8xx_CPU6
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 529b817f473b..3e02710d9562 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -41,6 +41,7 @@
41#include <asm/ppc_asm.h> 41#include <asm/ppc_asm.h>
42#include <asm/asm-offsets.h> 42#include <asm/asm-offsets.h>
43#include <asm/cache.h> 43#include <asm/cache.h>
44#include <asm/ptrace.h>
44#include "head_booke.h" 45#include "head_booke.h"
45 46
46/* As with the other PowerPC ports, it is expected that when code 47/* As with the other PowerPC ports, it is expected that when code
diff --git a/arch/powerpc/kernel/iommu.c b/arch/powerpc/kernel/iommu.c
index d5839179ec77..961bb03413f3 100644
--- a/arch/powerpc/kernel/iommu.c
+++ b/arch/powerpc/kernel/iommu.c
@@ -311,8 +311,9 @@ int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
311 /* Handle failure */ 311 /* Handle failure */
312 if (unlikely(entry == DMA_ERROR_CODE)) { 312 if (unlikely(entry == DMA_ERROR_CODE)) {
313 if (printk_ratelimit()) 313 if (printk_ratelimit())
314 printk(KERN_INFO "iommu_alloc failed, tbl %p vaddr %lx" 314 dev_info(dev, "iommu_alloc failed, tbl %p "
315 " npages %lx\n", tbl, vaddr, npages); 315 "vaddr %lx npages %lu\n", tbl, vaddr,
316 npages);
316 goto failure; 317 goto failure;
317 } 318 }
318 319
@@ -579,9 +580,9 @@ dma_addr_t iommu_map_page(struct device *dev, struct iommu_table *tbl,
579 attrs); 580 attrs);
580 if (dma_handle == DMA_ERROR_CODE) { 581 if (dma_handle == DMA_ERROR_CODE) {
581 if (printk_ratelimit()) { 582 if (printk_ratelimit()) {
582 printk(KERN_INFO "iommu_alloc failed, " 583 dev_info(dev, "iommu_alloc failed, tbl %p "
583 "tbl %p vaddr %p npages %d\n", 584 "vaddr %p npages %d\n", tbl, vaddr,
584 tbl, vaddr, npages); 585 npages);
585 } 586 }
586 } else 587 } else
587 dma_handle |= (uaddr & ~IOMMU_PAGE_MASK); 588 dma_handle |= (uaddr & ~IOMMU_PAGE_MASK);
@@ -627,7 +628,8 @@ void *iommu_alloc_coherent(struct device *dev, struct iommu_table *tbl,
627 * the tce tables. 628 * the tce tables.
628 */ 629 */
629 if (order >= IOMAP_MAX_ORDER) { 630 if (order >= IOMAP_MAX_ORDER) {
630 printk("iommu_alloc_consistent size too large: 0x%lx\n", size); 631 dev_info(dev, "iommu_alloc_consistent size too large: 0x%lx\n",
632 size);
631 return NULL; 633 return NULL;
632 } 634 }
633 635
diff --git a/arch/powerpc/kernel/misc.S b/arch/powerpc/kernel/misc.S
index 2d29752cbe16..b69463ec2010 100644
--- a/arch/powerpc/kernel/misc.S
+++ b/arch/powerpc/kernel/misc.S
@@ -122,8 +122,3 @@ _GLOBAL(longjmp)
122 mtlr r0 122 mtlr r0
123 mr r3,r4 123 mr r3,r4
124 blr 124 blr
125
126_GLOBAL(__setup_cpu_power7)
127_GLOBAL(__restore_cpu_power7)
128 /* place holder */
129 blr
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index a7a570dcdd57..094bd9821ad4 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -30,6 +30,7 @@
30#include <asm/processor.h> 30#include <asm/processor.h>
31#include <asm/kexec.h> 31#include <asm/kexec.h>
32#include <asm/bug.h> 32#include <asm/bug.h>
33#include <asm/ptrace.h>
33 34
34 .text 35 .text
35 36
diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
index e5144906a56d..206a321a71d3 100644
--- a/arch/powerpc/kernel/misc_64.S
+++ b/arch/powerpc/kernel/misc_64.S
@@ -25,6 +25,7 @@
25#include <asm/cputable.h> 25#include <asm/cputable.h>
26#include <asm/thread_info.h> 26#include <asm/thread_info.h>
27#include <asm/kexec.h> 27#include <asm/kexec.h>
28#include <asm/ptrace.h>
28 29
29 .text 30 .text
30 31
diff --git a/arch/powerpc/kernel/nvram_64.c b/arch/powerpc/kernel/nvram_64.c
index 9cf197f01e94..bb12b3248f13 100644
--- a/arch/powerpc/kernel/nvram_64.c
+++ b/arch/powerpc/kernel/nvram_64.c
@@ -34,15 +34,26 @@
34 34
35#undef DEBUG_NVRAM 35#undef DEBUG_NVRAM
36 36
37static struct nvram_partition * nvram_part; 37#define NVRAM_HEADER_LEN sizeof(struct nvram_header)
38static long nvram_error_log_index = -1; 38#define NVRAM_BLOCK_LEN NVRAM_HEADER_LEN
39static long nvram_error_log_size = 0; 39
40/* If change this size, then change the size of NVNAME_LEN */
41struct nvram_header {
42 unsigned char signature;
43 unsigned char checksum;
44 unsigned short length;
45 /* Terminating null required only for names < 12 chars. */
46 char name[12];
47};
40 48
41struct err_log_info { 49struct nvram_partition {
42 int error_type; 50 struct list_head partition;
43 unsigned int seq_num; 51 struct nvram_header header;
52 unsigned int index;
44}; 53};
45 54
55static LIST_HEAD(nvram_partitions);
56
46static loff_t dev_nvram_llseek(struct file *file, loff_t offset, int origin) 57static loff_t dev_nvram_llseek(struct file *file, loff_t offset, int origin)
47{ 58{
48 int size; 59 int size;
@@ -186,14 +197,12 @@ static struct miscdevice nvram_dev = {
186#ifdef DEBUG_NVRAM 197#ifdef DEBUG_NVRAM
187static void __init nvram_print_partitions(char * label) 198static void __init nvram_print_partitions(char * label)
188{ 199{
189 struct list_head * p;
190 struct nvram_partition * tmp_part; 200 struct nvram_partition * tmp_part;
191 201
192 printk(KERN_WARNING "--------%s---------\n", label); 202 printk(KERN_WARNING "--------%s---------\n", label);
193 printk(KERN_WARNING "indx\t\tsig\tchks\tlen\tname\n"); 203 printk(KERN_WARNING "indx\t\tsig\tchks\tlen\tname\n");
194 list_for_each(p, &nvram_part->partition) { 204 list_for_each_entry(tmp_part, &nvram_partitions, partition) {
195 tmp_part = list_entry(p, struct nvram_partition, partition); 205 printk(KERN_WARNING "%4d \t%02x\t%02x\t%d\t%12s\n",
196 printk(KERN_WARNING "%4d \t%02x\t%02x\t%d\t%s\n",
197 tmp_part->index, tmp_part->header.signature, 206 tmp_part->index, tmp_part->header.signature,
198 tmp_part->header.checksum, tmp_part->header.length, 207 tmp_part->header.checksum, tmp_part->header.length,
199 tmp_part->header.name); 208 tmp_part->header.name);
@@ -228,95 +237,113 @@ static unsigned char __init nvram_checksum(struct nvram_header *p)
228 return c_sum; 237 return c_sum;
229} 238}
230 239
231static int __init nvram_remove_os_partition(void) 240/**
241 * nvram_remove_partition - Remove one or more partitions in nvram
242 * @name: name of the partition to remove, or NULL for a
243 * signature only match
244 * @sig: signature of the partition(s) to remove
245 */
246
247int __init nvram_remove_partition(const char *name, int sig)
232{ 248{
233 struct list_head *i; 249 struct nvram_partition *part, *prev, *tmp;
234 struct list_head *j;
235 struct nvram_partition * part;
236 struct nvram_partition * cur_part;
237 int rc; 250 int rc;
238 251
239 list_for_each(i, &nvram_part->partition) { 252 list_for_each_entry(part, &nvram_partitions, partition) {
240 part = list_entry(i, struct nvram_partition, partition); 253 if (part->header.signature != sig)
241 if (part->header.signature != NVRAM_SIG_OS)
242 continue; 254 continue;
243 255 if (name && strncmp(name, part->header.name, 12))
244 /* Make os partition a free partition */ 256 continue;
257
258 /* Make partition a free partition */
245 part->header.signature = NVRAM_SIG_FREE; 259 part->header.signature = NVRAM_SIG_FREE;
246 sprintf(part->header.name, "wwwwwwwwwwww"); 260 strncpy(part->header.name, "wwwwwwwwwwww", 12);
247 part->header.checksum = nvram_checksum(&part->header); 261 part->header.checksum = nvram_checksum(&part->header);
248
249 /* Merge contiguous free partitions backwards */
250 list_for_each_prev(j, &part->partition) {
251 cur_part = list_entry(j, struct nvram_partition, partition);
252 if (cur_part == nvram_part || cur_part->header.signature != NVRAM_SIG_FREE) {
253 break;
254 }
255
256 part->header.length += cur_part->header.length;
257 part->header.checksum = nvram_checksum(&part->header);
258 part->index = cur_part->index;
259
260 list_del(&cur_part->partition);
261 kfree(cur_part);
262 j = &part->partition; /* fixup our loop */
263 }
264
265 /* Merge contiguous free partitions forwards */
266 list_for_each(j, &part->partition) {
267 cur_part = list_entry(j, struct nvram_partition, partition);
268 if (cur_part == nvram_part || cur_part->header.signature != NVRAM_SIG_FREE) {
269 break;
270 }
271
272 part->header.length += cur_part->header.length;
273 part->header.checksum = nvram_checksum(&part->header);
274
275 list_del(&cur_part->partition);
276 kfree(cur_part);
277 j = &part->partition; /* fixup our loop */
278 }
279
280 rc = nvram_write_header(part); 262 rc = nvram_write_header(part);
281 if (rc <= 0) { 263 if (rc <= 0) {
282 printk(KERN_ERR "nvram_remove_os_partition: nvram_write failed (%d)\n", rc); 264 printk(KERN_ERR "nvram_remove_partition: nvram_write failed (%d)\n", rc);
283 return rc; 265 return rc;
284 } 266 }
267 }
285 268
269 /* Merge contiguous ones */
270 prev = NULL;
271 list_for_each_entry_safe(part, tmp, &nvram_partitions, partition) {
272 if (part->header.signature != NVRAM_SIG_FREE) {
273 prev = NULL;
274 continue;
275 }
276 if (prev) {
277 prev->header.length += part->header.length;
278 prev->header.checksum = nvram_checksum(&part->header);
279 rc = nvram_write_header(part);
280 if (rc <= 0) {
281 printk(KERN_ERR "nvram_remove_partition: nvram_write failed (%d)\n", rc);
282 return rc;
283 }
284 list_del(&part->partition);
285 kfree(part);
286 } else
287 prev = part;
286 } 288 }
287 289
288 return 0; 290 return 0;
289} 291}
290 292
291/* nvram_create_os_partition 293/**
294 * nvram_create_partition - Create a partition in nvram
295 * @name: name of the partition to create
296 * @sig: signature of the partition to create
297 * @req_size: size of data to allocate in bytes
298 * @min_size: minimum acceptable size (0 means req_size)
292 * 299 *
293 * Create a OS linux partition to buffer error logs. 300 * Returns a negative error code or a positive nvram index
294 * Will create a partition starting at the first free 301 * of the beginning of the data area of the newly created
295 * space found if space has enough room. 302 * partition. If you provided a min_size smaller than req_size
303 * you need to query for the actual size yourself after the
304 * call using nvram_partition_get_size().
296 */ 305 */
297static int __init nvram_create_os_partition(void) 306loff_t __init nvram_create_partition(const char *name, int sig,
307 int req_size, int min_size)
298{ 308{
299 struct nvram_partition *part; 309 struct nvram_partition *part;
300 struct nvram_partition *new_part; 310 struct nvram_partition *new_part;
301 struct nvram_partition *free_part = NULL; 311 struct nvram_partition *free_part = NULL;
302 int seq_init[2] = { 0, 0 }; 312 static char nv_init_vals[16];
303 loff_t tmp_index; 313 loff_t tmp_index;
304 long size = 0; 314 long size = 0;
305 int rc; 315 int rc;
306 316
317 /* Convert sizes from bytes to blocks */
318 req_size = _ALIGN_UP(req_size, NVRAM_BLOCK_LEN) / NVRAM_BLOCK_LEN;
319 min_size = _ALIGN_UP(min_size, NVRAM_BLOCK_LEN) / NVRAM_BLOCK_LEN;
320
321 /* If no minimum size specified, make it the same as the
322 * requested size
323 */
324 if (min_size == 0)
325 min_size = req_size;
326 if (min_size > req_size)
327 return -EINVAL;
328
329 /* Now add one block to each for the header */
330 req_size += 1;
331 min_size += 1;
332
307 /* Find a free partition that will give us the maximum needed size 333 /* Find a free partition that will give us the maximum needed size
308 If can't find one that will give us the minimum size needed */ 334 If can't find one that will give us the minimum size needed */
309 list_for_each_entry(part, &nvram_part->partition, partition) { 335 list_for_each_entry(part, &nvram_partitions, partition) {
310 if (part->header.signature != NVRAM_SIG_FREE) 336 if (part->header.signature != NVRAM_SIG_FREE)
311 continue; 337 continue;
312 338
313 if (part->header.length >= NVRAM_MAX_REQ) { 339 if (part->header.length >= req_size) {
314 size = NVRAM_MAX_REQ; 340 size = req_size;
315 free_part = part; 341 free_part = part;
316 break; 342 break;
317 } 343 }
318 if (!size && part->header.length >= NVRAM_MIN_REQ) { 344 if (part->header.length > size &&
319 size = NVRAM_MIN_REQ; 345 part->header.length >= min_size) {
346 size = part->header.length;
320 free_part = part; 347 free_part = part;
321 } 348 }
322 } 349 }
@@ -326,136 +353,95 @@ static int __init nvram_create_os_partition(void)
326 /* Create our OS partition */ 353 /* Create our OS partition */
327 new_part = kmalloc(sizeof(*new_part), GFP_KERNEL); 354 new_part = kmalloc(sizeof(*new_part), GFP_KERNEL);
328 if (!new_part) { 355 if (!new_part) {
329 printk(KERN_ERR "nvram_create_os_partition: kmalloc failed\n"); 356 pr_err("nvram_create_os_partition: kmalloc failed\n");
330 return -ENOMEM; 357 return -ENOMEM;
331 } 358 }
332 359
333 new_part->index = free_part->index; 360 new_part->index = free_part->index;
334 new_part->header.signature = NVRAM_SIG_OS; 361 new_part->header.signature = sig;
335 new_part->header.length = size; 362 new_part->header.length = size;
336 strcpy(new_part->header.name, "ppc64,linux"); 363 strncpy(new_part->header.name, name, 12);
337 new_part->header.checksum = nvram_checksum(&new_part->header); 364 new_part->header.checksum = nvram_checksum(&new_part->header);
338 365
339 rc = nvram_write_header(new_part); 366 rc = nvram_write_header(new_part);
340 if (rc <= 0) { 367 if (rc <= 0) {
341 printk(KERN_ERR "nvram_create_os_partition: nvram_write_header " 368 pr_err("nvram_create_os_partition: nvram_write_header "
342 "failed (%d)\n", rc);
343 return rc;
344 }
345
346 /* make sure and initialize to zero the sequence number and the error
347 type logged */
348 tmp_index = new_part->index + NVRAM_HEADER_LEN;
349 rc = ppc_md.nvram_write((char *)&seq_init, sizeof(seq_init), &tmp_index);
350 if (rc <= 0) {
351 printk(KERN_ERR "nvram_create_os_partition: nvram_write "
352 "failed (%d)\n", rc); 369 "failed (%d)\n", rc);
353 return rc; 370 return rc;
354 } 371 }
355
356 nvram_error_log_index = new_part->index + NVRAM_HEADER_LEN;
357 nvram_error_log_size = ((part->header.length - 1) *
358 NVRAM_BLOCK_LEN) - sizeof(struct err_log_info);
359
360 list_add_tail(&new_part->partition, &free_part->partition); 372 list_add_tail(&new_part->partition, &free_part->partition);
361 373
362 if (free_part->header.length <= size) { 374 /* Adjust or remove the partition we stole the space from */
375 if (free_part->header.length > size) {
376 free_part->index += size * NVRAM_BLOCK_LEN;
377 free_part->header.length -= size;
378 free_part->header.checksum = nvram_checksum(&free_part->header);
379 rc = nvram_write_header(free_part);
380 if (rc <= 0) {
381 pr_err("nvram_create_os_partition: nvram_write_header "
382 "failed (%d)\n", rc);
383 return rc;
384 }
385 } else {
363 list_del(&free_part->partition); 386 list_del(&free_part->partition);
364 kfree(free_part); 387 kfree(free_part);
365 return 0;
366 } 388 }
367 389
368 /* Adjust the partition we stole the space from */ 390 /* Clear the new partition */
369 free_part->index += size * NVRAM_BLOCK_LEN; 391 for (tmp_index = new_part->index + NVRAM_HEADER_LEN;
370 free_part->header.length -= size; 392 tmp_index < ((size - 1) * NVRAM_BLOCK_LEN);
371 free_part->header.checksum = nvram_checksum(&free_part->header); 393 tmp_index += NVRAM_BLOCK_LEN) {
372 394 rc = ppc_md.nvram_write(nv_init_vals, NVRAM_BLOCK_LEN, &tmp_index);
373 rc = nvram_write_header(free_part); 395 if (rc <= 0) {
374 if (rc <= 0) { 396 pr_err("nvram_create_partition: nvram_write failed (%d)\n", rc);
375 printk(KERN_ERR "nvram_create_os_partition: nvram_write_header " 397 return rc;
376 "failed (%d)\n", rc); 398 }
377 return rc;
378 } 399 }
379 400
380 return 0; 401 return new_part->index + NVRAM_HEADER_LEN;
381} 402}
382 403
383 404/**
384/* nvram_setup_partition 405 * nvram_get_partition_size - Get the data size of an nvram partition
385 * 406 * @data_index: This is the offset of the start of the data of
386 * This will setup the partition we need for buffering the 407 * the partition. The same value that is returned by
387 * error logs and cleanup partitions if needed. 408 * nvram_create_partition().
388 *
389 * The general strategy is the following:
390 * 1.) If there is ppc64,linux partition large enough then use it.
391 * 2.) If there is not a ppc64,linux partition large enough, search
392 * for a free partition that is large enough.
393 * 3.) If there is not a free partition large enough remove
394 * _all_ OS partitions and consolidate the space.
395 * 4.) Will first try getting a chunk that will satisfy the maximum
396 * error log size (NVRAM_MAX_REQ).
397 * 5.) If the max chunk cannot be allocated then try finding a chunk
398 * that will satisfy the minum needed (NVRAM_MIN_REQ).
399 */ 409 */
400static int __init nvram_setup_partition(void) 410int nvram_get_partition_size(loff_t data_index)
401{ 411{
402 struct list_head * p; 412 struct nvram_partition *part;
403 struct nvram_partition * part; 413
404 int rc; 414 list_for_each_entry(part, &nvram_partitions, partition) {
405 415 if (part->index + NVRAM_HEADER_LEN == data_index)
406 /* For now, we don't do any of this on pmac, until I 416 return (part->header.length - 1) * NVRAM_BLOCK_LEN;
407 * have figured out if it's worth killing some unused stuffs 417 }
408 * in our nvram, as Apple defined partitions use pretty much 418 return -1;
409 * all of the space 419}
410 */
411 if (machine_is(powermac))
412 return -ENOSPC;
413
414 /* see if we have an OS partition that meets our needs.
415 will try getting the max we need. If not we'll delete
416 partitions and try again. */
417 list_for_each(p, &nvram_part->partition) {
418 part = list_entry(p, struct nvram_partition, partition);
419 if (part->header.signature != NVRAM_SIG_OS)
420 continue;
421 420
422 if (strcmp(part->header.name, "ppc64,linux"))
423 continue;
424 421
425 if (part->header.length >= NVRAM_MIN_REQ) { 422/**
426 /* found our partition */ 423 * nvram_find_partition - Find an nvram partition by signature and name
427 nvram_error_log_index = part->index + NVRAM_HEADER_LEN; 424 * @name: Name of the partition or NULL for any name
428 nvram_error_log_size = ((part->header.length - 1) * 425 * @sig: Signature to test against
429 NVRAM_BLOCK_LEN) - sizeof(struct err_log_info); 426 * @out_size: if non-NULL, returns the size of the data part of the partition
430 return 0; 427 */
428loff_t nvram_find_partition(const char *name, int sig, int *out_size)
429{
430 struct nvram_partition *p;
431
432 list_for_each_entry(p, &nvram_partitions, partition) {
433 if (p->header.signature == sig &&
434 (!name || !strncmp(p->header.name, name, 12))) {
435 if (out_size)
436 *out_size = (p->header.length - 1) *
437 NVRAM_BLOCK_LEN;
438 return p->index + NVRAM_HEADER_LEN;
431 } 439 }
432 } 440 }
433
434 /* try creating a partition with the free space we have */
435 rc = nvram_create_os_partition();
436 if (!rc) {
437 return 0;
438 }
439
440 /* need to free up some space */
441 rc = nvram_remove_os_partition();
442 if (rc) {
443 return rc;
444 }
445
446 /* create a partition in this new space */
447 rc = nvram_create_os_partition();
448 if (rc) {
449 printk(KERN_ERR "nvram_create_os_partition: Could not find a "
450 "NVRAM partition large enough\n");
451 return rc;
452 }
453
454 return 0; 441 return 0;
455} 442}
456 443
457 444int __init nvram_scan_partitions(void)
458static int __init nvram_scan_partitions(void)
459{ 445{
460 loff_t cur_index = 0; 446 loff_t cur_index = 0;
461 struct nvram_header phead; 447 struct nvram_header phead;
@@ -465,7 +451,7 @@ static int __init nvram_scan_partitions(void)
465 int total_size; 451 int total_size;
466 int err; 452 int err;
467 453
468 if (ppc_md.nvram_size == NULL) 454 if (ppc_md.nvram_size == NULL || ppc_md.nvram_size() <= 0)
469 return -ENODEV; 455 return -ENODEV;
470 total_size = ppc_md.nvram_size(); 456 total_size = ppc_md.nvram_size();
471 457
@@ -512,12 +498,16 @@ static int __init nvram_scan_partitions(void)
512 498
513 memcpy(&tmp_part->header, &phead, NVRAM_HEADER_LEN); 499 memcpy(&tmp_part->header, &phead, NVRAM_HEADER_LEN);
514 tmp_part->index = cur_index; 500 tmp_part->index = cur_index;
515 list_add_tail(&tmp_part->partition, &nvram_part->partition); 501 list_add_tail(&tmp_part->partition, &nvram_partitions);
516 502
517 cur_index += phead.length * NVRAM_BLOCK_LEN; 503 cur_index += phead.length * NVRAM_BLOCK_LEN;
518 } 504 }
519 err = 0; 505 err = 0;
520 506
507#ifdef DEBUG_NVRAM
508 nvram_print_partitions("NVRAM Partitions");
509#endif
510
521 out: 511 out:
522 kfree(header); 512 kfree(header);
523 return err; 513 return err;
@@ -525,9 +515,10 @@ static int __init nvram_scan_partitions(void)
525 515
526static int __init nvram_init(void) 516static int __init nvram_init(void)
527{ 517{
528 int error;
529 int rc; 518 int rc;
530 519
520 BUILD_BUG_ON(NVRAM_BLOCK_LEN != 16);
521
531 if (ppc_md.nvram_size == NULL || ppc_md.nvram_size() <= 0) 522 if (ppc_md.nvram_size == NULL || ppc_md.nvram_size() <= 0)
532 return -ENODEV; 523 return -ENODEV;
533 524
@@ -537,29 +528,6 @@ static int __init nvram_init(void)
537 return rc; 528 return rc;
538 } 529 }
539 530
540 /* initialize our anchor for the nvram partition list */
541 nvram_part = kmalloc(sizeof(struct nvram_partition), GFP_KERNEL);
542 if (!nvram_part) {
543 printk(KERN_ERR "nvram_init: Failed kmalloc\n");
544 return -ENOMEM;
545 }
546 INIT_LIST_HEAD(&nvram_part->partition);
547
548 /* Get all the NVRAM partitions */
549 error = nvram_scan_partitions();
550 if (error) {
551 printk(KERN_ERR "nvram_init: Failed nvram_scan_partitions\n");
552 return error;
553 }
554
555 if(nvram_setup_partition())
556 printk(KERN_WARNING "nvram_init: Could not find nvram partition"
557 " for nvram buffered error logging.\n");
558
559#ifdef DEBUG_NVRAM
560 nvram_print_partitions("NVRAM Partitions");
561#endif
562
563 return rc; 531 return rc;
564} 532}
565 533
@@ -568,135 +536,6 @@ void __exit nvram_cleanup(void)
568 misc_deregister( &nvram_dev ); 536 misc_deregister( &nvram_dev );
569} 537}
570 538
571
572#ifdef CONFIG_PPC_PSERIES
573
574/* nvram_write_error_log
575 *
576 * We need to buffer the error logs into nvram to ensure that we have
577 * the failure information to decode. If we have a severe error there
578 * is no way to guarantee that the OS or the machine is in a state to
579 * get back to user land and write the error to disk. For example if
580 * the SCSI device driver causes a Machine Check by writing to a bad
581 * IO address, there is no way of guaranteeing that the device driver
582 * is in any state that is would also be able to write the error data
583 * captured to disk, thus we buffer it in NVRAM for analysis on the
584 * next boot.
585 *
586 * In NVRAM the partition containing the error log buffer will looks like:
587 * Header (in bytes):
588 * +-----------+----------+--------+------------+------------------+
589 * | signature | checksum | length | name | data |
590 * |0 |1 |2 3|4 15|16 length-1|
591 * +-----------+----------+--------+------------+------------------+
592 *
593 * The 'data' section would look like (in bytes):
594 * +--------------+------------+-----------------------------------+
595 * | event_logged | sequence # | error log |
596 * |0 3|4 7|8 nvram_error_log_size-1|
597 * +--------------+------------+-----------------------------------+
598 *
599 * event_logged: 0 if event has not been logged to syslog, 1 if it has
600 * sequence #: The unique sequence # for each event. (until it wraps)
601 * error log: The error log from event_scan
602 */
603int nvram_write_error_log(char * buff, int length,
604 unsigned int err_type, unsigned int error_log_cnt)
605{
606 int rc;
607 loff_t tmp_index;
608 struct err_log_info info;
609
610 if (nvram_error_log_index == -1) {
611 return -ESPIPE;
612 }
613
614 if (length > nvram_error_log_size) {
615 length = nvram_error_log_size;
616 }
617
618 info.error_type = err_type;
619 info.seq_num = error_log_cnt;
620
621 tmp_index = nvram_error_log_index;
622
623 rc = ppc_md.nvram_write((char *)&info, sizeof(struct err_log_info), &tmp_index);
624 if (rc <= 0) {
625 printk(KERN_ERR "nvram_write_error_log: Failed nvram_write (%d)\n", rc);
626 return rc;
627 }
628
629 rc = ppc_md.nvram_write(buff, length, &tmp_index);
630 if (rc <= 0) {
631 printk(KERN_ERR "nvram_write_error_log: Failed nvram_write (%d)\n", rc);
632 return rc;
633 }
634
635 return 0;
636}
637
638/* nvram_read_error_log
639 *
640 * Reads nvram for error log for at most 'length'
641 */
642int nvram_read_error_log(char * buff, int length,
643 unsigned int * err_type, unsigned int * error_log_cnt)
644{
645 int rc;
646 loff_t tmp_index;
647 struct err_log_info info;
648
649 if (nvram_error_log_index == -1)
650 return -1;
651
652 if (length > nvram_error_log_size)
653 length = nvram_error_log_size;
654
655 tmp_index = nvram_error_log_index;
656
657 rc = ppc_md.nvram_read((char *)&info, sizeof(struct err_log_info), &tmp_index);
658 if (rc <= 0) {
659 printk(KERN_ERR "nvram_read_error_log: Failed nvram_read (%d)\n", rc);
660 return rc;
661 }
662
663 rc = ppc_md.nvram_read(buff, length, &tmp_index);
664 if (rc <= 0) {
665 printk(KERN_ERR "nvram_read_error_log: Failed nvram_read (%d)\n", rc);
666 return rc;
667 }
668
669 *error_log_cnt = info.seq_num;
670 *err_type = info.error_type;
671
672 return 0;
673}
674
675/* This doesn't actually zero anything, but it sets the event_logged
676 * word to tell that this event is safely in syslog.
677 */
678int nvram_clear_error_log(void)
679{
680 loff_t tmp_index;
681 int clear_word = ERR_FLAG_ALREADY_LOGGED;
682 int rc;
683
684 if (nvram_error_log_index == -1)
685 return -1;
686
687 tmp_index = nvram_error_log_index;
688
689 rc = ppc_md.nvram_write((char *)&clear_word, sizeof(int), &tmp_index);
690 if (rc <= 0) {
691 printk(KERN_ERR "nvram_clear_error_log: Failed nvram_write (%d)\n", rc);
692 return rc;
693 }
694
695 return 0;
696}
697
698#endif /* CONFIG_PPC_PSERIES */
699
700module_init(nvram_init); 539module_init(nvram_init);
701module_exit(nvram_cleanup); 540module_exit(nvram_cleanup);
702MODULE_LICENSE("GPL"); 541MODULE_LICENSE("GPL");
diff --git a/arch/powerpc/kernel/pci_64.c b/arch/powerpc/kernel/pci_64.c
index d43fc65749c1..851577608a78 100644
--- a/arch/powerpc/kernel/pci_64.c
+++ b/arch/powerpc/kernel/pci_64.c
@@ -193,8 +193,7 @@ int __devinit pcibios_map_io_space(struct pci_bus *bus)
193 hose->io_resource.start += io_virt_offset; 193 hose->io_resource.start += io_virt_offset;
194 hose->io_resource.end += io_virt_offset; 194 hose->io_resource.end += io_virt_offset;
195 195
196 pr_debug(" hose->io_resource=0x%016llx...0x%016llx\n", 196 pr_debug(" hose->io_resource=%pR\n", &hose->io_resource);
197 hose->io_resource.start, hose->io_resource.end);
198 197
199 return 0; 198 return 0;
200} 199}
diff --git a/arch/powerpc/kernel/ppc_ksyms.c b/arch/powerpc/kernel/ppc_ksyms.c
index ab3e392ac63c..ef3ef566235e 100644
--- a/arch/powerpc/kernel/ppc_ksyms.c
+++ b/arch/powerpc/kernel/ppc_ksyms.c
@@ -186,3 +186,10 @@ EXPORT_SYMBOL(__mtdcr);
186EXPORT_SYMBOL(__mfdcr); 186EXPORT_SYMBOL(__mfdcr);
187#endif 187#endif
188EXPORT_SYMBOL(empty_zero_page); 188EXPORT_SYMBOL(empty_zero_page);
189
190#ifdef CONFIG_PPC64
191EXPORT_SYMBOL(__arch_hweight8);
192EXPORT_SYMBOL(__arch_hweight16);
193EXPORT_SYMBOL(__arch_hweight32);
194EXPORT_SYMBOL(__arch_hweight64);
195#endif
diff --git a/arch/powerpc/kernel/ppc_save_regs.S b/arch/powerpc/kernel/ppc_save_regs.S
index 5113bd2285e1..e83ba3f078e4 100644
--- a/arch/powerpc/kernel/ppc_save_regs.S
+++ b/arch/powerpc/kernel/ppc_save_regs.S
@@ -11,6 +11,7 @@
11#include <asm/processor.h> 11#include <asm/processor.h>
12#include <asm/ppc_asm.h> 12#include <asm/ppc_asm.h>
13#include <asm/asm-offsets.h> 13#include <asm/asm-offsets.h>
14#include <asm/ptrace.h>
14 15
15/* 16/*
16 * Grab the register values as they are now. 17 * Grab the register values as they are now.
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index a9b32967cff6..906536998291 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -1316,6 +1316,10 @@ static int set_dac_range(struct task_struct *child,
1316static long ppc_set_hwdebug(struct task_struct *child, 1316static long ppc_set_hwdebug(struct task_struct *child,
1317 struct ppc_hw_breakpoint *bp_info) 1317 struct ppc_hw_breakpoint *bp_info)
1318{ 1318{
1319#ifndef CONFIG_PPC_ADV_DEBUG_REGS
1320 unsigned long dabr;
1321#endif
1322
1319 if (bp_info->version != 1) 1323 if (bp_info->version != 1)
1320 return -ENOTSUPP; 1324 return -ENOTSUPP;
1321#ifdef CONFIG_PPC_ADV_DEBUG_REGS 1325#ifdef CONFIG_PPC_ADV_DEBUG_REGS
@@ -1353,11 +1357,10 @@ static long ppc_set_hwdebug(struct task_struct *child,
1353 /* 1357 /*
1354 * We only support one data breakpoint 1358 * We only support one data breakpoint
1355 */ 1359 */
1356 if (((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0) || 1360 if ((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0 ||
1357 ((bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0) || 1361 (bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0 ||
1358 (bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_WRITE) || 1362 bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT ||
1359 (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) || 1363 bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)
1360 (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE))
1361 return -EINVAL; 1364 return -EINVAL;
1362 1365
1363 if (child->thread.dabr) 1366 if (child->thread.dabr)
@@ -1366,7 +1369,14 @@ static long ppc_set_hwdebug(struct task_struct *child,
1366 if ((unsigned long)bp_info->addr >= TASK_SIZE) 1369 if ((unsigned long)bp_info->addr >= TASK_SIZE)
1367 return -EIO; 1370 return -EIO;
1368 1371
1369 child->thread.dabr = (unsigned long)bp_info->addr; 1372 dabr = (unsigned long)bp_info->addr & ~7UL;
1373 dabr |= DABR_TRANSLATION;
1374 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
1375 dabr |= DABR_DATA_READ;
1376 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
1377 dabr |= DABR_DATA_WRITE;
1378
1379 child->thread.dabr = dabr;
1370 1380
1371 return 1; 1381 return 1;
1372#endif /* !CONFIG_PPC_ADV_DEBUG_DVCS */ 1382#endif /* !CONFIG_PPC_ADV_DEBUG_DVCS */
diff --git a/arch/powerpc/kernel/ptrace32.c b/arch/powerpc/kernel/ptrace32.c
index 8a6daf4129f6..69c4be917d07 100644
--- a/arch/powerpc/kernel/ptrace32.c
+++ b/arch/powerpc/kernel/ptrace32.c
@@ -280,7 +280,11 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
280 /* We only support one DABR and no IABRS at the moment */ 280 /* We only support one DABR and no IABRS at the moment */
281 if (addr > 0) 281 if (addr > 0)
282 break; 282 break;
283#ifdef CONFIG_PPC_ADV_DEBUG_REGS
284 ret = put_user(child->thread.dac1, (u32 __user *)data);
285#else
283 ret = put_user(child->thread.dabr, (u32 __user *)data); 286 ret = put_user(child->thread.dabr, (u32 __user *)data);
287#endif
284 break; 288 break;
285 } 289 }
286 290
@@ -312,6 +316,9 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
312 case PTRACE_SET_DEBUGREG: 316 case PTRACE_SET_DEBUGREG:
313 case PTRACE_SYSCALL: 317 case PTRACE_SYSCALL:
314 case PTRACE_CONT: 318 case PTRACE_CONT:
319 case PPC_PTRACE_GETHWDBGINFO:
320 case PPC_PTRACE_SETHWDEBUG:
321 case PPC_PTRACE_DELHWDEBUG:
315 ret = arch_ptrace(child, request, addr, data); 322 ret = arch_ptrace(child, request, addr, data);
316 break; 323 break;
317 324
diff --git a/arch/powerpc/kernel/rtas.c b/arch/powerpc/kernel/rtas.c
index 8fe8bc61c10a..2097f2b3cba8 100644
--- a/arch/powerpc/kernel/rtas.c
+++ b/arch/powerpc/kernel/rtas.c
@@ -41,6 +41,7 @@
41#include <asm/atomic.h> 41#include <asm/atomic.h>
42#include <asm/time.h> 42#include <asm/time.h>
43#include <asm/mmu.h> 43#include <asm/mmu.h>
44#include <asm/topology.h>
44 45
45struct rtas_t rtas = { 46struct rtas_t rtas = {
46 .lock = __ARCH_SPIN_LOCK_UNLOCKED 47 .lock = __ARCH_SPIN_LOCK_UNLOCKED
@@ -713,6 +714,7 @@ static int __rtas_suspend_last_cpu(struct rtas_suspend_me_data *data, int wake_w
713 int cpu; 714 int cpu;
714 715
715 slb_set_size(SLB_MIN_SIZE); 716 slb_set_size(SLB_MIN_SIZE);
717 stop_topology_update();
716 printk(KERN_DEBUG "calling ibm,suspend-me on cpu %i\n", smp_processor_id()); 718 printk(KERN_DEBUG "calling ibm,suspend-me on cpu %i\n", smp_processor_id());
717 719
718 while (rc == H_MULTI_THREADS_ACTIVE && !atomic_read(&data->done) && 720 while (rc == H_MULTI_THREADS_ACTIVE && !atomic_read(&data->done) &&
@@ -728,6 +730,7 @@ static int __rtas_suspend_last_cpu(struct rtas_suspend_me_data *data, int wake_w
728 rc = atomic_read(&data->error); 730 rc = atomic_read(&data->error);
729 731
730 atomic_set(&data->error, rc); 732 atomic_set(&data->error, rc);
733 start_topology_update();
731 734
732 if (wake_when_done) { 735 if (wake_when_done) {
733 atomic_set(&data->done, 1); 736 atomic_set(&data->done, 1);
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index ce6f61c6f871..5a0401fcaebd 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -437,8 +437,8 @@ static void __init irqstack_early_init(void)
437 unsigned int i; 437 unsigned int i;
438 438
439 /* 439 /*
440 * interrupt stacks must be under 256MB, we cannot afford to take 440 * Interrupt stacks must be in the first segment since we
441 * SLB misses on them. 441 * cannot afford to take SLB misses on them.
442 */ 442 */
443 for_each_possible_cpu(i) { 443 for_each_possible_cpu(i) {
444 softirq_ctx[i] = (struct thread_info *) 444 softirq_ctx[i] = (struct thread_info *)
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 68034bbf2e4f..981360509172 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -466,7 +466,20 @@ out:
466 return id; 466 return id;
467} 467}
468 468
469/* Must be called when no change can occur to cpu_present_mask, 469/* Helper routines for cpu to core mapping */
470int cpu_core_index_of_thread(int cpu)
471{
472 return cpu >> threads_shift;
473}
474EXPORT_SYMBOL_GPL(cpu_core_index_of_thread);
475
476int cpu_first_thread_of_core(int core)
477{
478 return core << threads_shift;
479}
480EXPORT_SYMBOL_GPL(cpu_first_thread_of_core);
481
482/* Must be called when no change can occur to cpu_present_map,
470 * i.e. during cpu online or offline. 483 * i.e. during cpu online or offline.
471 */ 484 */
472static struct device_node *cpu_to_l2cache(int cpu) 485static struct device_node *cpu_to_l2cache(int cpu)
@@ -514,7 +527,7 @@ int __devinit start_secondary(void *unused)
514 notify_cpu_starting(cpu); 527 notify_cpu_starting(cpu);
515 set_cpu_online(cpu, true); 528 set_cpu_online(cpu, true);
516 /* Update sibling maps */ 529 /* Update sibling maps */
517 base = cpu_first_thread_in_core(cpu); 530 base = cpu_first_thread_sibling(cpu);
518 for (i = 0; i < threads_per_core; i++) { 531 for (i = 0; i < threads_per_core; i++) {
519 if (cpu_is_offline(base + i)) 532 if (cpu_is_offline(base + i))
520 continue; 533 continue;
@@ -600,7 +613,7 @@ int __cpu_disable(void)
600 return err; 613 return err;
601 614
602 /* Update sibling maps */ 615 /* Update sibling maps */
603 base = cpu_first_thread_in_core(cpu); 616 base = cpu_first_thread_sibling(cpu);
604 for (i = 0; i < threads_per_core; i++) { 617 for (i = 0; i < threads_per_core; i++) {
605 cpumask_clear_cpu(cpu, cpu_sibling_mask(base + i)); 618 cpumask_clear_cpu(cpu, cpu_sibling_mask(base + i));
606 cpumask_clear_cpu(base + i, cpu_sibling_mask(cpu)); 619 cpumask_clear_cpu(base + i, cpu_sibling_mask(cpu));
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index 010406958d97..09e4dea4a85a 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -155,7 +155,7 @@ EXPORT_SYMBOL_GPL(rtc_lock);
155 155
156static u64 tb_to_ns_scale __read_mostly; 156static u64 tb_to_ns_scale __read_mostly;
157static unsigned tb_to_ns_shift __read_mostly; 157static unsigned tb_to_ns_shift __read_mostly;
158static unsigned long boot_tb __read_mostly; 158static u64 boot_tb __read_mostly;
159 159
160extern struct timezone sys_tz; 160extern struct timezone sys_tz;
161static long timezone_offset; 161static long timezone_offset;
diff --git a/arch/powerpc/kernel/vector.S b/arch/powerpc/kernel/vector.S
index fe460482fa68..9de6f396cf85 100644
--- a/arch/powerpc/kernel/vector.S
+++ b/arch/powerpc/kernel/vector.S
@@ -5,6 +5,7 @@
5#include <asm/cputable.h> 5#include <asm/cputable.h>
6#include <asm/thread_info.h> 6#include <asm/thread_info.h>
7#include <asm/page.h> 7#include <asm/page.h>
8#include <asm/ptrace.h>
8 9
9/* 10/*
10 * load_up_altivec(unused, unused, tsk) 11 * load_up_altivec(unused, unused, tsk)
diff --git a/arch/powerpc/kernel/vio.c b/arch/powerpc/kernel/vio.c
index 441d2a722f06..1b695fdc362b 100644
--- a/arch/powerpc/kernel/vio.c
+++ b/arch/powerpc/kernel/vio.c
@@ -600,6 +600,11 @@ static void vio_dma_iommu_unmap_sg(struct device *dev,
600 vio_cmo_dealloc(viodev, alloc_size); 600 vio_cmo_dealloc(viodev, alloc_size);
601} 601}
602 602
603static int vio_dma_iommu_dma_supported(struct device *dev, u64 mask)
604{
605 return dma_iommu_ops.dma_supported(dev, mask);
606}
607
603struct dma_map_ops vio_dma_mapping_ops = { 608struct dma_map_ops vio_dma_mapping_ops = {
604 .alloc_coherent = vio_dma_iommu_alloc_coherent, 609 .alloc_coherent = vio_dma_iommu_alloc_coherent,
605 .free_coherent = vio_dma_iommu_free_coherent, 610 .free_coherent = vio_dma_iommu_free_coherent,
@@ -607,6 +612,7 @@ struct dma_map_ops vio_dma_mapping_ops = {
607 .unmap_sg = vio_dma_iommu_unmap_sg, 612 .unmap_sg = vio_dma_iommu_unmap_sg,
608 .map_page = vio_dma_iommu_map_page, 613 .map_page = vio_dma_iommu_map_page,
609 .unmap_page = vio_dma_iommu_unmap_page, 614 .unmap_page = vio_dma_iommu_unmap_page,
615 .dma_supported = vio_dma_iommu_dma_supported,
610 616
611}; 617};
612 618
@@ -858,8 +864,7 @@ static void vio_cmo_bus_remove(struct vio_dev *viodev)
858 864
859static void vio_cmo_set_dma_ops(struct vio_dev *viodev) 865static void vio_cmo_set_dma_ops(struct vio_dev *viodev)
860{ 866{
861 vio_dma_mapping_ops.dma_supported = dma_iommu_ops.dma_supported; 867 set_dma_ops(&viodev->dev, &vio_dma_mapping_ops);
862 viodev->dev.archdata.dma_ops = &vio_dma_mapping_ops;
863} 868}
864 869
865/** 870/**
@@ -1244,7 +1249,7 @@ struct vio_dev *vio_register_device_node(struct device_node *of_node)
1244 if (firmware_has_feature(FW_FEATURE_CMO)) 1249 if (firmware_has_feature(FW_FEATURE_CMO))
1245 vio_cmo_set_dma_ops(viodev); 1250 vio_cmo_set_dma_ops(viodev);
1246 else 1251 else
1247 viodev->dev.archdata.dma_ops = &dma_iommu_ops; 1252 set_dma_ops(&viodev->dev, &dma_iommu_ops);
1248 set_iommu_table_base(&viodev->dev, vio_build_iommu_table(viodev)); 1253 set_iommu_table_base(&viodev->dev, vio_build_iommu_table(viodev));
1249 set_dev_node(&viodev->dev, of_node_to_nid(of_node)); 1254 set_dev_node(&viodev->dev, of_node_to_nid(of_node));
1250 1255
@@ -1252,6 +1257,10 @@ struct vio_dev *vio_register_device_node(struct device_node *of_node)
1252 viodev->dev.parent = &vio_bus_device.dev; 1257 viodev->dev.parent = &vio_bus_device.dev;
1253 viodev->dev.bus = &vio_bus_type; 1258 viodev->dev.bus = &vio_bus_type;
1254 viodev->dev.release = vio_dev_release; 1259 viodev->dev.release = vio_dev_release;
1260 /* needed to ensure proper operation of coherent allocations
1261 * later, in case driver doesn't set it explicitly */
1262 dma_set_mask(&viodev->dev, DMA_BIT_MASK(64));
1263 dma_set_coherent_mask(&viodev->dev, DMA_BIT_MASK(64));
1255 1264
1256 /* register with generic device framework */ 1265 /* register with generic device framework */
1257 if (device_register(&viodev->dev)) { 1266 if (device_register(&viodev->dev)) {
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 889f2bc106dd..166a6a0ad544 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -16,7 +16,7 @@ obj-$(CONFIG_HAS_IOMEM) += devres.o
16 16
17obj-$(CONFIG_PPC64) += copypage_64.o copyuser_64.o \ 17obj-$(CONFIG_PPC64) += copypage_64.o copyuser_64.o \
18 memcpy_64.o usercopy_64.o mem_64.o string.o \ 18 memcpy_64.o usercopy_64.o mem_64.o string.o \
19 checksum_wrappers_64.o 19 checksum_wrappers_64.o hweight_64.o
20obj-$(CONFIG_XMON) += sstep.o ldstfp.o 20obj-$(CONFIG_XMON) += sstep.o ldstfp.o
21obj-$(CONFIG_KPROBES) += sstep.o ldstfp.o 21obj-$(CONFIG_KPROBES) += sstep.o ldstfp.o
22obj-$(CONFIG_HAVE_HW_BREAKPOINT) += sstep.o ldstfp.o 22obj-$(CONFIG_HAVE_HW_BREAKPOINT) += sstep.o ldstfp.o
diff --git a/arch/powerpc/lib/hweight_64.S b/arch/powerpc/lib/hweight_64.S
new file mode 100644
index 000000000000..fda27868cf8c
--- /dev/null
+++ b/arch/powerpc/lib/hweight_64.S
@@ -0,0 +1,110 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
15 *
16 * Copyright (C) IBM Corporation, 2010
17 *
18 * Author: Anton Blanchard <anton@au.ibm.com>
19 */
20#include <asm/processor.h>
21#include <asm/ppc_asm.h>
22
23/* Note: This code relies on -mminimal-toc */
24
25_GLOBAL(__arch_hweight8)
26BEGIN_FTR_SECTION
27 b .__sw_hweight8
28 nop
29 nop
30FTR_SECTION_ELSE
31 PPC_POPCNTB(r3,r3)
32 clrldi r3,r3,64-8
33 blr
34ALT_FTR_SECTION_END_IFCLR(CPU_FTR_POPCNTB)
35
36_GLOBAL(__arch_hweight16)
37BEGIN_FTR_SECTION
38 b .__sw_hweight16
39 nop
40 nop
41 nop
42 nop
43FTR_SECTION_ELSE
44 BEGIN_FTR_SECTION_NESTED(50)
45 PPC_POPCNTB(r3,r3)
46 srdi r4,r3,8
47 add r3,r4,r3
48 clrldi r3,r3,64-8
49 blr
50 FTR_SECTION_ELSE_NESTED(50)
51 clrlwi r3,r3,16
52 PPC_POPCNTW(r3,r3)
53 clrldi r3,r3,64-8
54 blr
55 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_POPCNTD, 50)
56ALT_FTR_SECTION_END_IFCLR(CPU_FTR_POPCNTB)
57
58_GLOBAL(__arch_hweight32)
59BEGIN_FTR_SECTION
60 b .__sw_hweight32
61 nop
62 nop
63 nop
64 nop
65 nop
66 nop
67FTR_SECTION_ELSE
68 BEGIN_FTR_SECTION_NESTED(51)
69 PPC_POPCNTB(r3,r3)
70 srdi r4,r3,16
71 add r3,r4,r3
72 srdi r4,r3,8
73 add r3,r4,r3
74 clrldi r3,r3,64-8
75 blr
76 FTR_SECTION_ELSE_NESTED(51)
77 PPC_POPCNTW(r3,r3)
78 clrldi r3,r3,64-8
79 blr
80 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_POPCNTD, 51)
81ALT_FTR_SECTION_END_IFCLR(CPU_FTR_POPCNTB)
82
83_GLOBAL(__arch_hweight64)
84BEGIN_FTR_SECTION
85 b .__sw_hweight64
86 nop
87 nop
88 nop
89 nop
90 nop
91 nop
92 nop
93 nop
94FTR_SECTION_ELSE
95 BEGIN_FTR_SECTION_NESTED(52)
96 PPC_POPCNTB(r3,r3)
97 srdi r4,r3,32
98 add r3,r4,r3
99 srdi r4,r3,16
100 add r3,r4,r3
101 srdi r4,r3,8
102 add r3,r4,r3
103 clrldi r3,r3,64-8
104 blr
105 FTR_SECTION_ELSE_NESTED(52)
106 PPC_POPCNTD(r3,r3)
107 clrldi r3,r3,64-8
108 blr
109 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_POPCNTD, 52)
110ALT_FTR_SECTION_END_IFCLR(CPU_FTR_POPCNTB)
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index 5e9584405c45..a5991facddce 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -1070,7 +1070,7 @@ void hash_preload(struct mm_struct *mm, unsigned long ea,
1070 unsigned long access, unsigned long trap) 1070 unsigned long access, unsigned long trap)
1071{ 1071{
1072 unsigned long vsid; 1072 unsigned long vsid;
1073 void *pgdir; 1073 pgd_t *pgdir;
1074 pte_t *ptep; 1074 pte_t *ptep;
1075 unsigned long flags; 1075 unsigned long flags;
1076 int rc, ssize, local = 0; 1076 int rc, ssize, local = 0;
diff --git a/arch/powerpc/mm/mmu_context_nohash.c b/arch/powerpc/mm/mmu_context_nohash.c
index 5ce99848d91e..c0aab52da3a5 100644
--- a/arch/powerpc/mm/mmu_context_nohash.c
+++ b/arch/powerpc/mm/mmu_context_nohash.c
@@ -111,8 +111,8 @@ static unsigned int steal_context_smp(unsigned int id)
111 * a core map instead but this will do for now. 111 * a core map instead but this will do for now.
112 */ 112 */
113 for_each_cpu(cpu, mm_cpumask(mm)) { 113 for_each_cpu(cpu, mm_cpumask(mm)) {
114 for (i = cpu_first_thread_in_core(cpu); 114 for (i = cpu_first_thread_sibling(cpu);
115 i <= cpu_last_thread_in_core(cpu); i++) 115 i <= cpu_last_thread_sibling(cpu); i++)
116 __set_bit(id, stale_map[i]); 116 __set_bit(id, stale_map[i]);
117 cpu = i - 1; 117 cpu = i - 1;
118 } 118 }
@@ -264,14 +264,14 @@ void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next)
264 */ 264 */
265 if (test_bit(id, stale_map[cpu])) { 265 if (test_bit(id, stale_map[cpu])) {
266 pr_hardcont(" | stale flush %d [%d..%d]", 266 pr_hardcont(" | stale flush %d [%d..%d]",
267 id, cpu_first_thread_in_core(cpu), 267 id, cpu_first_thread_sibling(cpu),
268 cpu_last_thread_in_core(cpu)); 268 cpu_last_thread_sibling(cpu));
269 269
270 local_flush_tlb_mm(next); 270 local_flush_tlb_mm(next);
271 271
272 /* XXX This clear should ultimately be part of local_flush_tlb_mm */ 272 /* XXX This clear should ultimately be part of local_flush_tlb_mm */
273 for (i = cpu_first_thread_in_core(cpu); 273 for (i = cpu_first_thread_sibling(cpu);
274 i <= cpu_last_thread_in_core(cpu); i++) { 274 i <= cpu_last_thread_sibling(cpu); i++) {
275 __clear_bit(id, stale_map[i]); 275 __clear_bit(id, stale_map[i]);
276 } 276 }
277 } 277 }
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index 74505b245374..bf5cb91f07de 100644
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
@@ -20,10 +20,15 @@
20#include <linux/memblock.h> 20#include <linux/memblock.h>
21#include <linux/of.h> 21#include <linux/of.h>
22#include <linux/pfn.h> 22#include <linux/pfn.h>
23#include <linux/cpuset.h>
24#include <linux/node.h>
23#include <asm/sparsemem.h> 25#include <asm/sparsemem.h>
24#include <asm/prom.h> 26#include <asm/prom.h>
25#include <asm/system.h> 27#include <asm/system.h>
26#include <asm/smp.h> 28#include <asm/smp.h>
29#include <asm/firmware.h>
30#include <asm/paca.h>
31#include <asm/hvcall.h>
27 32
28static int numa_enabled = 1; 33static int numa_enabled = 1;
29 34
@@ -163,7 +168,7 @@ static void __init get_node_active_region(unsigned long start_pfn,
163 work_with_active_regions(nid, get_active_region_work_fn, node_ar); 168 work_with_active_regions(nid, get_active_region_work_fn, node_ar);
164} 169}
165 170
166static void __cpuinit map_cpu_to_node(int cpu, int node) 171static void map_cpu_to_node(int cpu, int node)
167{ 172{
168 numa_cpu_lookup_table[cpu] = node; 173 numa_cpu_lookup_table[cpu] = node;
169 174
@@ -173,7 +178,7 @@ static void __cpuinit map_cpu_to_node(int cpu, int node)
173 cpumask_set_cpu(cpu, node_to_cpumask_map[node]); 178 cpumask_set_cpu(cpu, node_to_cpumask_map[node]);
174} 179}
175 180
176#ifdef CONFIG_HOTPLUG_CPU 181#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PPC_SPLPAR)
177static void unmap_cpu_from_node(unsigned long cpu) 182static void unmap_cpu_from_node(unsigned long cpu)
178{ 183{
179 int node = numa_cpu_lookup_table[cpu]; 184 int node = numa_cpu_lookup_table[cpu];
@@ -187,7 +192,7 @@ static void unmap_cpu_from_node(unsigned long cpu)
187 cpu, node); 192 cpu, node);
188 } 193 }
189} 194}
190#endif /* CONFIG_HOTPLUG_CPU */ 195#endif /* CONFIG_HOTPLUG_CPU || CONFIG_PPC_SPLPAR */
191 196
192/* must hold reference to node during call */ 197/* must hold reference to node during call */
193static const int *of_get_associativity(struct device_node *dev) 198static const int *of_get_associativity(struct device_node *dev)
@@ -246,32 +251,41 @@ static void initialize_distance_lookup_table(int nid,
246/* Returns nid in the range [0..MAX_NUMNODES-1], or -1 if no useful numa 251/* Returns nid in the range [0..MAX_NUMNODES-1], or -1 if no useful numa
247 * info is found. 252 * info is found.
248 */ 253 */
249static int of_node_to_nid_single(struct device_node *device) 254static int associativity_to_nid(const unsigned int *associativity)
250{ 255{
251 int nid = -1; 256 int nid = -1;
252 const unsigned int *tmp;
253 257
254 if (min_common_depth == -1) 258 if (min_common_depth == -1)
255 goto out; 259 goto out;
256 260
257 tmp = of_get_associativity(device); 261 if (associativity[0] >= min_common_depth)
258 if (!tmp) 262 nid = associativity[min_common_depth];
259 goto out;
260
261 if (tmp[0] >= min_common_depth)
262 nid = tmp[min_common_depth];
263 263
264 /* POWER4 LPAR uses 0xffff as invalid node */ 264 /* POWER4 LPAR uses 0xffff as invalid node */
265 if (nid == 0xffff || nid >= MAX_NUMNODES) 265 if (nid == 0xffff || nid >= MAX_NUMNODES)
266 nid = -1; 266 nid = -1;
267 267
268 if (nid > 0 && tmp[0] >= distance_ref_points_depth) 268 if (nid > 0 && associativity[0] >= distance_ref_points_depth)
269 initialize_distance_lookup_table(nid, tmp); 269 initialize_distance_lookup_table(nid, associativity);
270 270
271out: 271out:
272 return nid; 272 return nid;
273} 273}
274 274
275/* Returns the nid associated with the given device tree node,
276 * or -1 if not found.
277 */
278static int of_node_to_nid_single(struct device_node *device)
279{
280 int nid = -1;
281 const unsigned int *tmp;
282
283 tmp = of_get_associativity(device);
284 if (tmp)
285 nid = associativity_to_nid(tmp);
286 return nid;
287}
288
275/* Walk the device tree upwards, looking for an associativity id */ 289/* Walk the device tree upwards, looking for an associativity id */
276int of_node_to_nid(struct device_node *device) 290int of_node_to_nid(struct device_node *device)
277{ 291{
@@ -1247,4 +1261,275 @@ int hot_add_scn_to_nid(unsigned long scn_addr)
1247 return nid; 1261 return nid;
1248} 1262}
1249 1263
1264static u64 hot_add_drconf_memory_max(void)
1265{
1266 struct device_node *memory = NULL;
1267 unsigned int drconf_cell_cnt = 0;
1268 u64 lmb_size = 0;
1269 const u32 *dm = 0;
1270
1271 memory = of_find_node_by_path("/ibm,dynamic-reconfiguration-memory");
1272 if (memory) {
1273 drconf_cell_cnt = of_get_drconf_memory(memory, &dm);
1274 lmb_size = of_get_lmb_size(memory);
1275 of_node_put(memory);
1276 }
1277 return lmb_size * drconf_cell_cnt;
1278}
1279
1280/*
1281 * memory_hotplug_max - return max address of memory that may be added
1282 *
1283 * This is currently only used on systems that support drconfig memory
1284 * hotplug.
1285 */
1286u64 memory_hotplug_max(void)
1287{
1288 return max(hot_add_drconf_memory_max(), memblock_end_of_DRAM());
1289}
1250#endif /* CONFIG_MEMORY_HOTPLUG */ 1290#endif /* CONFIG_MEMORY_HOTPLUG */
1291
1292/* Vrtual Processor Home Node (VPHN) support */
1293#ifdef CONFIG_PPC_SPLPAR
1294#define VPHN_NR_CHANGE_CTRS (8)
1295static u8 vphn_cpu_change_counts[NR_CPUS][VPHN_NR_CHANGE_CTRS];
1296static cpumask_t cpu_associativity_changes_mask;
1297static int vphn_enabled;
1298static void set_topology_timer(void);
1299
1300/*
1301 * Store the current values of the associativity change counters in the
1302 * hypervisor.
1303 */
1304static void setup_cpu_associativity_change_counters(void)
1305{
1306 int cpu = 0;
1307
1308 for_each_possible_cpu(cpu) {
1309 int i = 0;
1310 u8 *counts = vphn_cpu_change_counts[cpu];
1311 volatile u8 *hypervisor_counts = lppaca[cpu].vphn_assoc_counts;
1312
1313 for (i = 0; i < VPHN_NR_CHANGE_CTRS; i++) {
1314 counts[i] = hypervisor_counts[i];
1315 }
1316 }
1317}
1318
1319/*
1320 * The hypervisor maintains a set of 8 associativity change counters in
1321 * the VPA of each cpu that correspond to the associativity levels in the
1322 * ibm,associativity-reference-points property. When an associativity
1323 * level changes, the corresponding counter is incremented.
1324 *
1325 * Set a bit in cpu_associativity_changes_mask for each cpu whose home
1326 * node associativity levels have changed.
1327 *
1328 * Returns the number of cpus with unhandled associativity changes.
1329 */
1330static int update_cpu_associativity_changes_mask(void)
1331{
1332 int cpu = 0, nr_cpus = 0;
1333 cpumask_t *changes = &cpu_associativity_changes_mask;
1334
1335 cpumask_clear(changes);
1336
1337 for_each_possible_cpu(cpu) {
1338 int i, changed = 0;
1339 u8 *counts = vphn_cpu_change_counts[cpu];
1340 volatile u8 *hypervisor_counts = lppaca[cpu].vphn_assoc_counts;
1341
1342 for (i = 0; i < VPHN_NR_CHANGE_CTRS; i++) {
1343 if (hypervisor_counts[i] > counts[i]) {
1344 counts[i] = hypervisor_counts[i];
1345 changed = 1;
1346 }
1347 }
1348 if (changed) {
1349 cpumask_set_cpu(cpu, changes);
1350 nr_cpus++;
1351 }
1352 }
1353
1354 return nr_cpus;
1355}
1356
1357/* 6 64-bit registers unpacked into 12 32-bit associativity values */
1358#define VPHN_ASSOC_BUFSIZE (6*sizeof(u64)/sizeof(u32))
1359
1360/*
1361 * Convert the associativity domain numbers returned from the hypervisor
1362 * to the sequence they would appear in the ibm,associativity property.
1363 */
1364static int vphn_unpack_associativity(const long *packed, unsigned int *unpacked)
1365{
1366 int i = 0;
1367 int nr_assoc_doms = 0;
1368 const u16 *field = (const u16*) packed;
1369
1370#define VPHN_FIELD_UNUSED (0xffff)
1371#define VPHN_FIELD_MSB (0x8000)
1372#define VPHN_FIELD_MASK (~VPHN_FIELD_MSB)
1373
1374 for (i = 0; i < VPHN_ASSOC_BUFSIZE; i++) {
1375 if (*field == VPHN_FIELD_UNUSED) {
1376 /* All significant fields processed, and remaining
1377 * fields contain the reserved value of all 1's.
1378 * Just store them.
1379 */
1380 unpacked[i] = *((u32*)field);
1381 field += 2;
1382 }
1383 else if (*field & VPHN_FIELD_MSB) {
1384 /* Data is in the lower 15 bits of this field */
1385 unpacked[i] = *field & VPHN_FIELD_MASK;
1386 field++;
1387 nr_assoc_doms++;
1388 }
1389 else {
1390 /* Data is in the lower 15 bits of this field
1391 * concatenated with the next 16 bit field
1392 */
1393 unpacked[i] = *((u32*)field);
1394 field += 2;
1395 nr_assoc_doms++;
1396 }
1397 }
1398
1399 return nr_assoc_doms;
1400}
1401
1402/*
1403 * Retrieve the new associativity information for a virtual processor's
1404 * home node.
1405 */
1406static long hcall_vphn(unsigned long cpu, unsigned int *associativity)
1407{
1408 long rc = 0;
1409 long retbuf[PLPAR_HCALL9_BUFSIZE] = {0};
1410 u64 flags = 1;
1411 int hwcpu = get_hard_smp_processor_id(cpu);
1412
1413 rc = plpar_hcall9(H_HOME_NODE_ASSOCIATIVITY, retbuf, flags, hwcpu);
1414 vphn_unpack_associativity(retbuf, associativity);
1415
1416 return rc;
1417}
1418
1419static long vphn_get_associativity(unsigned long cpu,
1420 unsigned int *associativity)
1421{
1422 long rc = 0;
1423
1424 rc = hcall_vphn(cpu, associativity);
1425
1426 switch (rc) {
1427 case H_FUNCTION:
1428 printk(KERN_INFO
1429 "VPHN is not supported. Disabling polling...\n");
1430 stop_topology_update();
1431 break;
1432 case H_HARDWARE:
1433 printk(KERN_ERR
1434 "hcall_vphn() experienced a hardware fault "
1435 "preventing VPHN. Disabling polling...\n");
1436 stop_topology_update();
1437 }
1438
1439 return rc;
1440}
1441
1442/*
1443 * Update the node maps and sysfs entries for each cpu whose home node
1444 * has changed.
1445 */
1446int arch_update_cpu_topology(void)
1447{
1448 int cpu = 0, nid = 0, old_nid = 0;
1449 unsigned int associativity[VPHN_ASSOC_BUFSIZE] = {0};
1450 struct sys_device *sysdev = NULL;
1451
1452 for_each_cpu_mask(cpu, cpu_associativity_changes_mask) {
1453 vphn_get_associativity(cpu, associativity);
1454 nid = associativity_to_nid(associativity);
1455
1456 if (nid < 0 || !node_online(nid))
1457 nid = first_online_node;
1458
1459 old_nid = numa_cpu_lookup_table[cpu];
1460
1461 /* Disable hotplug while we update the cpu
1462 * masks and sysfs.
1463 */
1464 get_online_cpus();
1465 unregister_cpu_under_node(cpu, old_nid);
1466 unmap_cpu_from_node(cpu);
1467 map_cpu_to_node(cpu, nid);
1468 register_cpu_under_node(cpu, nid);
1469 put_online_cpus();
1470
1471 sysdev = get_cpu_sysdev(cpu);
1472 if (sysdev)
1473 kobject_uevent(&sysdev->kobj, KOBJ_CHANGE);
1474 }
1475
1476 return 1;
1477}
1478
1479static void topology_work_fn(struct work_struct *work)
1480{
1481 rebuild_sched_domains();
1482}
1483static DECLARE_WORK(topology_work, topology_work_fn);
1484
1485void topology_schedule_update(void)
1486{
1487 schedule_work(&topology_work);
1488}
1489
1490static void topology_timer_fn(unsigned long ignored)
1491{
1492 if (!vphn_enabled)
1493 return;
1494 if (update_cpu_associativity_changes_mask() > 0)
1495 topology_schedule_update();
1496 set_topology_timer();
1497}
1498static struct timer_list topology_timer =
1499 TIMER_INITIALIZER(topology_timer_fn, 0, 0);
1500
1501static void set_topology_timer(void)
1502{
1503 topology_timer.data = 0;
1504 topology_timer.expires = jiffies + 60 * HZ;
1505 add_timer(&topology_timer);
1506}
1507
1508/*
1509 * Start polling for VPHN associativity changes.
1510 */
1511int start_topology_update(void)
1512{
1513 int rc = 0;
1514
1515 if (firmware_has_feature(FW_FEATURE_VPHN)) {
1516 vphn_enabled = 1;
1517 setup_cpu_associativity_change_counters();
1518 init_timer_deferrable(&topology_timer);
1519 set_topology_timer();
1520 rc = 1;
1521 }
1522
1523 return rc;
1524}
1525__initcall(start_topology_update);
1526
1527/*
1528 * Disable polling for VPHN associativity changes.
1529 */
1530int stop_topology_update(void)
1531{
1532 vphn_enabled = 0;
1533 return del_timer_sync(&topology_timer);
1534}
1535#endif /* CONFIG_PPC_SPLPAR */
diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c
index a87ead0138b4..8dc41c0157fe 100644
--- a/arch/powerpc/mm/pgtable_32.c
+++ b/arch/powerpc/mm/pgtable_32.c
@@ -78,7 +78,7 @@ pgd_t *pgd_alloc(struct mm_struct *mm)
78 78
79 /* pgdir take page or two with 4K pages and a page fraction otherwise */ 79 /* pgdir take page or two with 4K pages and a page fraction otherwise */
80#ifndef CONFIG_PPC_4K_PAGES 80#ifndef CONFIG_PPC_4K_PAGES
81 ret = (pgd_t *)kzalloc(1 << PGDIR_ORDER, GFP_KERNEL); 81 ret = kzalloc(1 << PGDIR_ORDER, GFP_KERNEL);
82#else 82#else
83 ret = (pgd_t *)__get_free_pages(GFP_KERNEL|__GFP_ZERO, 83 ret = (pgd_t *)__get_free_pages(GFP_KERNEL|__GFP_ZERO,
84 PGDIR_ORDER - PAGE_SHIFT); 84 PGDIR_ORDER - PAGE_SHIFT);
@@ -230,6 +230,7 @@ __ioremap_caller(phys_addr_t addr, unsigned long size, unsigned long flags,
230 area = get_vm_area_caller(size, VM_IOREMAP, caller); 230 area = get_vm_area_caller(size, VM_IOREMAP, caller);
231 if (area == 0) 231 if (area == 0)
232 return NULL; 232 return NULL;
233 area->phys_addr = p;
233 v = (unsigned long) area->addr; 234 v = (unsigned long) area->addr;
234 } else { 235 } else {
235 v = (ioremap_bot -= size); 236 v = (ioremap_bot -= size);
diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c
index 21d6dfab7942..88927a05cdc2 100644
--- a/arch/powerpc/mm/pgtable_64.c
+++ b/arch/powerpc/mm/pgtable_64.c
@@ -223,6 +223,8 @@ void __iomem * __ioremap_caller(phys_addr_t addr, unsigned long size,
223 caller); 223 caller);
224 if (area == NULL) 224 if (area == NULL)
225 return NULL; 225 return NULL;
226
227 area->phys_addr = paligned;
226 ret = __ioremap_at(paligned, area->addr, size, flags); 228 ret = __ioremap_at(paligned, area->addr, size, flags);
227 if (!ret) 229 if (!ret)
228 vunmap(area->addr); 230 vunmap(area->addr);
diff --git a/arch/powerpc/platforms/44x/Makefile b/arch/powerpc/platforms/44x/Makefile
index 82ff326e0795..c04d16df8488 100644
--- a/arch/powerpc/platforms/44x/Makefile
+++ b/arch/powerpc/platforms/44x/Makefile
@@ -1,4 +1,7 @@
1obj-$(CONFIG_44x) := misc_44x.o idle.o 1obj-$(CONFIG_44x) += misc_44x.o
2ifneq ($(CONFIG_PPC4xx_CPM),y)
3obj-$(CONFIG_44x) += idle.o
4endif
2obj-$(CONFIG_PPC44x_SIMPLE) += ppc44x_simple.o 5obj-$(CONFIG_PPC44x_SIMPLE) += ppc44x_simple.o
3obj-$(CONFIG_EBONY) += ebony.o 6obj-$(CONFIG_EBONY) += ebony.o
4obj-$(CONFIG_SAM440EP) += sam440ep.o 7obj-$(CONFIG_SAM440EP) += sam440ep.o
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 956154f32cfe..20576829eca5 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -313,13 +313,14 @@ config OF_RTC
313source "arch/powerpc/sysdev/bestcomm/Kconfig" 313source "arch/powerpc/sysdev/bestcomm/Kconfig"
314 314
315config MPC8xxx_GPIO 315config MPC8xxx_GPIO
316 bool "MPC8xxx GPIO support" 316 bool "MPC512x/MPC8xxx GPIO support"
317 depends on PPC_MPC831x || PPC_MPC834x || PPC_MPC837x || FSL_SOC_BOOKE || PPC_86xx 317 depends on PPC_MPC512x || PPC_MPC831x || PPC_MPC834x || PPC_MPC837x || \
318 FSL_SOC_BOOKE || PPC_86xx
318 select GENERIC_GPIO 319 select GENERIC_GPIO
319 select ARCH_REQUIRE_GPIOLIB 320 select ARCH_REQUIRE_GPIOLIB
320 help 321 help
321 Say Y here if you're going to use hardware that connects to the 322 Say Y here if you're going to use hardware that connects to the
322 MPC831x/834x/837x/8572/8610 GPIOs. 323 MPC512x/831x/834x/837x/8572/8610 GPIOs.
323 324
324config SIMPLE_GPIO 325config SIMPLE_GPIO
325 bool "Support for simple, memory-mapped GPIO controllers" 326 bool "Support for simple, memory-mapped GPIO controllers"
diff --git a/arch/powerpc/platforms/cell/beat_iommu.c b/arch/powerpc/platforms/cell/beat_iommu.c
index beec405eb6f8..3ce685568935 100644
--- a/arch/powerpc/platforms/cell/beat_iommu.c
+++ b/arch/powerpc/platforms/cell/beat_iommu.c
@@ -76,7 +76,7 @@ static void __init celleb_init_direct_mapping(void)
76 76
77static void celleb_dma_dev_setup(struct device *dev) 77static void celleb_dma_dev_setup(struct device *dev)
78{ 78{
79 dev->archdata.dma_ops = get_pci_dma_ops(); 79 set_dma_ops(dev, &dma_direct_ops);
80 set_dma_offset(dev, celleb_dma_direct_offset); 80 set_dma_offset(dev, celleb_dma_direct_offset);
81} 81}
82 82
@@ -106,7 +106,6 @@ static struct notifier_block celleb_of_bus_notifier = {
106static int __init celleb_init_iommu(void) 106static int __init celleb_init_iommu(void)
107{ 107{
108 celleb_init_direct_mapping(); 108 celleb_init_direct_mapping();
109 set_pci_dma_ops(&dma_direct_ops);
110 ppc_md.pci_dma_dev_setup = celleb_pci_dma_dev_setup; 109 ppc_md.pci_dma_dev_setup = celleb_pci_dma_dev_setup;
111 bus_register_notifier(&platform_bus_type, &celleb_of_bus_notifier); 110 bus_register_notifier(&platform_bus_type, &celleb_of_bus_notifier);
112 111
diff --git a/arch/powerpc/platforms/cell/spufs/lscsa_alloc.c b/arch/powerpc/platforms/cell/spufs/lscsa_alloc.c
index a101abf17504..3b894f585280 100644
--- a/arch/powerpc/platforms/cell/spufs/lscsa_alloc.c
+++ b/arch/powerpc/platforms/cell/spufs/lscsa_alloc.c
@@ -36,10 +36,9 @@ static int spu_alloc_lscsa_std(struct spu_state *csa)
36 struct spu_lscsa *lscsa; 36 struct spu_lscsa *lscsa;
37 unsigned char *p; 37 unsigned char *p;
38 38
39 lscsa = vmalloc(sizeof(struct spu_lscsa)); 39 lscsa = vzalloc(sizeof(struct spu_lscsa));
40 if (!lscsa) 40 if (!lscsa)
41 return -ENOMEM; 41 return -ENOMEM;
42 memset(lscsa, 0, sizeof(struct spu_lscsa));
43 csa->lscsa = lscsa; 42 csa->lscsa = lscsa;
44 43
45 /* Set LS pages reserved to allow for user-space mapping. */ 44 /* Set LS pages reserved to allow for user-space mapping. */
diff --git a/arch/powerpc/platforms/chrp/time.c b/arch/powerpc/platforms/chrp/time.c
index 054dfe5b8e77..f803f4b8ab6f 100644
--- a/arch/powerpc/platforms/chrp/time.c
+++ b/arch/powerpc/platforms/chrp/time.c
@@ -29,6 +29,10 @@
29 29
30extern spinlock_t rtc_lock; 30extern spinlock_t rtc_lock;
31 31
32#define NVRAM_AS0 0x74
33#define NVRAM_AS1 0x75
34#define NVRAM_DATA 0x77
35
32static int nvram_as1 = NVRAM_AS1; 36static int nvram_as1 = NVRAM_AS1;
33static int nvram_as0 = NVRAM_AS0; 37static int nvram_as0 = NVRAM_AS0;
34static int nvram_data = NVRAM_DATA; 38static int nvram_data = NVRAM_DATA;
diff --git a/arch/powerpc/platforms/iseries/mf.c b/arch/powerpc/platforms/iseries/mf.c
index 42d0a886de05..b5e026bdca21 100644
--- a/arch/powerpc/platforms/iseries/mf.c
+++ b/arch/powerpc/platforms/iseries/mf.c
@@ -1045,71 +1045,9 @@ static const struct file_operations mf_side_proc_fops = {
1045 .write = mf_side_proc_write, 1045 .write = mf_side_proc_write,
1046}; 1046};
1047 1047
1048#if 0
1049static void mf_getSrcHistory(char *buffer, int size)
1050{
1051 struct IplTypeReturnStuff return_stuff;
1052 struct pending_event *ev = new_pending_event();
1053 int rc = 0;
1054 char *pages[4];
1055
1056 pages[0] = kmalloc(4096, GFP_ATOMIC);
1057 pages[1] = kmalloc(4096, GFP_ATOMIC);
1058 pages[2] = kmalloc(4096, GFP_ATOMIC);
1059 pages[3] = kmalloc(4096, GFP_ATOMIC);
1060 if ((ev == NULL) || (pages[0] == NULL) || (pages[1] == NULL)
1061 || (pages[2] == NULL) || (pages[3] == NULL))
1062 return -ENOMEM;
1063
1064 return_stuff.xType = 0;
1065 return_stuff.xRc = 0;
1066 return_stuff.xDone = 0;
1067 ev->event.hp_lp_event.xSubtype = 6;
1068 ev->event.hp_lp_event.x.xSubtypeData =
1069 subtype_data('M', 'F', 'V', 'I');
1070 ev->event.data.vsp_cmd.xEvent = &return_stuff;
1071 ev->event.data.vsp_cmd.cmd = 4;
1072 ev->event.data.vsp_cmd.lp_index = HvLpConfig_getLpIndex();
1073 ev->event.data.vsp_cmd.result_code = 0xFF;
1074 ev->event.data.vsp_cmd.reserved = 0;
1075 ev->event.data.vsp_cmd.sub_data.page[0] = iseries_hv_addr(pages[0]);
1076 ev->event.data.vsp_cmd.sub_data.page[1] = iseries_hv_addr(pages[1]);
1077 ev->event.data.vsp_cmd.sub_data.page[2] = iseries_hv_addr(pages[2]);
1078 ev->event.data.vsp_cmd.sub_data.page[3] = iseries_hv_addr(pages[3]);
1079 mb();
1080 if (signal_event(ev) != 0)
1081 return;
1082
1083 while (return_stuff.xDone != 1)
1084 udelay(10);
1085 if (return_stuff.xRc == 0)
1086 memcpy(buffer, pages[0], size);
1087 kfree(pages[0]);
1088 kfree(pages[1]);
1089 kfree(pages[2]);
1090 kfree(pages[3]);
1091}
1092#endif
1093
1094static int mf_src_proc_show(struct seq_file *m, void *v) 1048static int mf_src_proc_show(struct seq_file *m, void *v)
1095{ 1049{
1096#if 0
1097 int len;
1098
1099 mf_getSrcHistory(page, count);
1100 len = count;
1101 len -= off;
1102 if (len < count) {
1103 *eof = 1;
1104 if (len <= 0)
1105 return 0;
1106 } else
1107 len = count;
1108 *start = page + off;
1109 return len;
1110#else
1111 return 0; 1050 return 0;
1112#endif
1113} 1051}
1114 1052
1115static int mf_src_proc_open(struct inode *inode, struct file *file) 1053static int mf_src_proc_open(struct inode *inode, struct file *file)
diff --git a/arch/powerpc/platforms/pasemi/iommu.c b/arch/powerpc/platforms/pasemi/iommu.c
index 1f9fb2c57761..14943ef01918 100644
--- a/arch/powerpc/platforms/pasemi/iommu.c
+++ b/arch/powerpc/platforms/pasemi/iommu.c
@@ -156,20 +156,12 @@ static void iommu_table_iobmap_setup(void)
156 156
157static void pci_dma_bus_setup_pasemi(struct pci_bus *bus) 157static void pci_dma_bus_setup_pasemi(struct pci_bus *bus)
158{ 158{
159 struct device_node *dn;
160
161 pr_debug("pci_dma_bus_setup, bus %p, bus->self %p\n", bus, bus->self); 159 pr_debug("pci_dma_bus_setup, bus %p, bus->self %p\n", bus, bus->self);
162 160
163 if (!iommu_table_iobmap_inited) { 161 if (!iommu_table_iobmap_inited) {
164 iommu_table_iobmap_inited = 1; 162 iommu_table_iobmap_inited = 1;
165 iommu_table_iobmap_setup(); 163 iommu_table_iobmap_setup();
166 } 164 }
167
168 dn = pci_bus_to_OF_node(bus);
169
170 if (dn)
171 PCI_DN(dn)->iommu_table = &iommu_table_iobmap;
172
173} 165}
174 166
175 167
@@ -192,9 +184,6 @@ static void pci_dma_dev_setup_pasemi(struct pci_dev *dev)
192 set_iommu_table_base(&dev->dev, &iommu_table_iobmap); 184 set_iommu_table_base(&dev->dev, &iommu_table_iobmap);
193} 185}
194 186
195static void pci_dma_bus_setup_null(struct pci_bus *b) { }
196static void pci_dma_dev_setup_null(struct pci_dev *d) { }
197
198int __init iob_init(struct device_node *dn) 187int __init iob_init(struct device_node *dn)
199{ 188{
200 unsigned long tmp; 189 unsigned long tmp;
@@ -251,14 +240,8 @@ void __init iommu_init_early_pasemi(void)
251 iommu_off = of_chosen && 240 iommu_off = of_chosen &&
252 of_get_property(of_chosen, "linux,iommu-off", NULL); 241 of_get_property(of_chosen, "linux,iommu-off", NULL);
253#endif 242#endif
254 if (iommu_off) { 243 if (iommu_off)
255 /* Direct I/O, IOMMU off */
256 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_null;
257 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_null;
258 set_pci_dma_ops(&dma_direct_ops);
259
260 return; 244 return;
261 }
262 245
263 iob_init(NULL); 246 iob_init(NULL);
264 247
diff --git a/arch/powerpc/platforms/powermac/setup.c b/arch/powerpc/platforms/powermac/setup.c
index 9deb274841f1..d5aceb7fb125 100644
--- a/arch/powerpc/platforms/powermac/setup.c
+++ b/arch/powerpc/platforms/powermac/setup.c
@@ -506,6 +506,15 @@ static int __init pmac_declare_of_platform_devices(void)
506 of_platform_device_create(np, "smu", NULL); 506 of_platform_device_create(np, "smu", NULL);
507 of_node_put(np); 507 of_node_put(np);
508 } 508 }
509 np = of_find_node_by_type(NULL, "fcu");
510 if (np == NULL) {
511 /* Some machines have strangely broken device-tree */
512 np = of_find_node_by_path("/u3@0,f8000000/i2c@f8001000/fan@15e");
513 }
514 if (np) {
515 of_platform_device_create(np, "temperature", NULL);
516 of_node_put(np);
517 }
509 518
510 return 0; 519 return 0;
511} 520}
diff --git a/arch/powerpc/platforms/pseries/Kconfig b/arch/powerpc/platforms/pseries/Kconfig
index 3139814f6439..5d1b743dbe7e 100644
--- a/arch/powerpc/platforms/pseries/Kconfig
+++ b/arch/powerpc/platforms/pseries/Kconfig
@@ -33,6 +33,16 @@ config PSERIES_MSI
33 depends on PCI_MSI && EEH 33 depends on PCI_MSI && EEH
34 default y 34 default y
35 35
36config PSERIES_ENERGY
37 tristate "pSeries energy management capabilities driver"
38 depends on PPC_PSERIES
39 default y
40 help
41 Provides interface to platform energy management capabilities
42 on supported PSERIES platforms.
43 Provides: /sys/devices/system/cpu/pseries_(de)activation_hint_list
44 and /sys/devices/system/cpu/cpuN/pseries_(de)activation_hint
45
36config SCANLOG 46config SCANLOG
37 tristate "Scanlog dump interface" 47 tristate "Scanlog dump interface"
38 depends on RTAS_PROC && PPC_PSERIES 48 depends on RTAS_PROC && PPC_PSERIES
diff --git a/arch/powerpc/platforms/pseries/Makefile b/arch/powerpc/platforms/pseries/Makefile
index 59eb8bdaa79d..fc5237810ece 100644
--- a/arch/powerpc/platforms/pseries/Makefile
+++ b/arch/powerpc/platforms/pseries/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_EEH) += eeh.o eeh_cache.o eeh_driver.o eeh_event.o eeh_sysfs.o
11obj-$(CONFIG_KEXEC) += kexec.o 11obj-$(CONFIG_KEXEC) += kexec.o
12obj-$(CONFIG_PCI) += pci.o pci_dlpar.o 12obj-$(CONFIG_PCI) += pci.o pci_dlpar.o
13obj-$(CONFIG_PSERIES_MSI) += msi.o 13obj-$(CONFIG_PSERIES_MSI) += msi.o
14obj-$(CONFIG_PSERIES_ENERGY) += pseries_energy.o
14 15
15obj-$(CONFIG_HOTPLUG_CPU) += hotplug-cpu.o 16obj-$(CONFIG_HOTPLUG_CPU) += hotplug-cpu.o
16obj-$(CONFIG_MEMORY_HOTPLUG) += hotplug-memory.o 17obj-$(CONFIG_MEMORY_HOTPLUG) += hotplug-memory.o
diff --git a/arch/powerpc/platforms/pseries/firmware.c b/arch/powerpc/platforms/pseries/firmware.c
index 0a14d8cd314f..0b0eff0cce35 100644
--- a/arch/powerpc/platforms/pseries/firmware.c
+++ b/arch/powerpc/platforms/pseries/firmware.c
@@ -55,6 +55,7 @@ firmware_features_table[FIRMWARE_MAX_FEATURES] = {
55 {FW_FEATURE_XDABR, "hcall-xdabr"}, 55 {FW_FEATURE_XDABR, "hcall-xdabr"},
56 {FW_FEATURE_MULTITCE, "hcall-multi-tce"}, 56 {FW_FEATURE_MULTITCE, "hcall-multi-tce"},
57 {FW_FEATURE_SPLPAR, "hcall-splpar"}, 57 {FW_FEATURE_SPLPAR, "hcall-splpar"},
58 {FW_FEATURE_VPHN, "hcall-vphn"},
58}; 59};
59 60
60/* Build up the firmware features bitmask using the contents of 61/* Build up the firmware features bitmask using the contents of
diff --git a/arch/powerpc/platforms/pseries/hvCall.S b/arch/powerpc/platforms/pseries/hvCall.S
index 48d20573e4de..fd05fdee576a 100644
--- a/arch/powerpc/platforms/pseries/hvCall.S
+++ b/arch/powerpc/platforms/pseries/hvCall.S
@@ -11,6 +11,7 @@
11#include <asm/processor.h> 11#include <asm/processor.h>
12#include <asm/ppc_asm.h> 12#include <asm/ppc_asm.h>
13#include <asm/asm-offsets.h> 13#include <asm/asm-offsets.h>
14#include <asm/ptrace.h>
14 15
15#define STK_PARM(i) (48 + ((i)-3)*8) 16#define STK_PARM(i) (48 + ((i)-3)*8)
16 17
diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/platforms/pseries/iommu.c
index a77bcaed80af..edea60b7ee90 100644
--- a/arch/powerpc/platforms/pseries/iommu.c
+++ b/arch/powerpc/platforms/pseries/iommu.c
@@ -140,7 +140,7 @@ static int tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum,
140 return ret; 140 return ret;
141} 141}
142 142
143static DEFINE_PER_CPU(u64 *, tce_page) = NULL; 143static DEFINE_PER_CPU(u64 *, tce_page);
144 144
145static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum, 145static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
146 long npages, unsigned long uaddr, 146 long npages, unsigned long uaddr,
@@ -323,14 +323,13 @@ static void iommu_table_setparms(struct pci_controller *phb,
323static void iommu_table_setparms_lpar(struct pci_controller *phb, 323static void iommu_table_setparms_lpar(struct pci_controller *phb,
324 struct device_node *dn, 324 struct device_node *dn,
325 struct iommu_table *tbl, 325 struct iommu_table *tbl,
326 const void *dma_window, 326 const void *dma_window)
327 int bussubno)
328{ 327{
329 unsigned long offset, size; 328 unsigned long offset, size;
330 329
331 tbl->it_busno = bussubno;
332 of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size); 330 of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size);
333 331
332 tbl->it_busno = phb->bus->number;
334 tbl->it_base = 0; 333 tbl->it_base = 0;
335 tbl->it_blocksize = 16; 334 tbl->it_blocksize = 16;
336 tbl->it_type = TCE_PCI; 335 tbl->it_type = TCE_PCI;
@@ -450,14 +449,10 @@ static void pci_dma_bus_setup_pSeriesLP(struct pci_bus *bus)
450 if (!ppci->iommu_table) { 449 if (!ppci->iommu_table) {
451 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, 450 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
452 ppci->phb->node); 451 ppci->phb->node);
453 iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window, 452 iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window);
454 bus->number);
455 ppci->iommu_table = iommu_init_table(tbl, ppci->phb->node); 453 ppci->iommu_table = iommu_init_table(tbl, ppci->phb->node);
456 pr_debug(" created table: %p\n", ppci->iommu_table); 454 pr_debug(" created table: %p\n", ppci->iommu_table);
457 } 455 }
458
459 if (pdn != dn)
460 PCI_DN(dn)->iommu_table = ppci->iommu_table;
461} 456}
462 457
463 458
@@ -533,21 +528,11 @@ static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev)
533 } 528 }
534 pr_debug(" parent is %s\n", pdn->full_name); 529 pr_debug(" parent is %s\n", pdn->full_name);
535 530
536 /* Check for parent == NULL so we don't try to setup the empty EADS
537 * slots on POWER4 machines.
538 */
539 if (dma_window == NULL || pdn->parent == NULL) {
540 pr_debug(" no dma window for device, linking to parent\n");
541 set_iommu_table_base(&dev->dev, PCI_DN(pdn)->iommu_table);
542 return;
543 }
544
545 pci = PCI_DN(pdn); 531 pci = PCI_DN(pdn);
546 if (!pci->iommu_table) { 532 if (!pci->iommu_table) {
547 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, 533 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
548 pci->phb->node); 534 pci->phb->node);
549 iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window, 535 iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window);
550 pci->phb->bus->number);
551 pci->iommu_table = iommu_init_table(tbl, pci->phb->node); 536 pci->iommu_table = iommu_init_table(tbl, pci->phb->node);
552 pr_debug(" created table: %p\n", pci->iommu_table); 537 pr_debug(" created table: %p\n", pci->iommu_table);
553 } else { 538 } else {
@@ -571,8 +556,7 @@ static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long acti
571 556
572 switch (action) { 557 switch (action) {
573 case PSERIES_RECONFIG_REMOVE: 558 case PSERIES_RECONFIG_REMOVE:
574 if (pci && pci->iommu_table && 559 if (pci && pci->iommu_table)
575 of_get_property(np, "ibm,dma-window", NULL))
576 iommu_free_table(pci->iommu_table, np->full_name); 560 iommu_free_table(pci->iommu_table, np->full_name);
577 break; 561 break;
578 default: 562 default:
@@ -589,13 +573,8 @@ static struct notifier_block iommu_reconfig_nb = {
589/* These are called very early. */ 573/* These are called very early. */
590void iommu_init_early_pSeries(void) 574void iommu_init_early_pSeries(void)
591{ 575{
592 if (of_chosen && of_get_property(of_chosen, "linux,iommu-off", NULL)) { 576 if (of_chosen && of_get_property(of_chosen, "linux,iommu-off", NULL))
593 /* Direct I/O, IOMMU off */
594 ppc_md.pci_dma_dev_setup = NULL;
595 ppc_md.pci_dma_bus_setup = NULL;
596 set_pci_dma_ops(&dma_direct_ops);
597 return; 577 return;
598 }
599 578
600 if (firmware_has_feature(FW_FEATURE_LPAR)) { 579 if (firmware_has_feature(FW_FEATURE_LPAR)) {
601 if (firmware_has_feature(FW_FEATURE_MULTITCE)) { 580 if (firmware_has_feature(FW_FEATURE_MULTITCE)) {
@@ -622,3 +601,17 @@ void iommu_init_early_pSeries(void)
622 set_pci_dma_ops(&dma_iommu_ops); 601 set_pci_dma_ops(&dma_iommu_ops);
623} 602}
624 603
604static int __init disable_multitce(char *str)
605{
606 if (strcmp(str, "off") == 0 &&
607 firmware_has_feature(FW_FEATURE_LPAR) &&
608 firmware_has_feature(FW_FEATURE_MULTITCE)) {
609 printk(KERN_INFO "Disabling MULTITCE firmware feature\n");
610 ppc_md.tce_build = tce_build_pSeriesLP;
611 ppc_md.tce_free = tce_free_pSeriesLP;
612 powerpc_firmware_features &= ~FW_FEATURE_MULTITCE;
613 }
614 return 1;
615}
616
617__setup("multitce=", disable_multitce);
diff --git a/arch/powerpc/platforms/pseries/lpar.c b/arch/powerpc/platforms/pseries/lpar.c
index f129040d974c..5d3ea9f60dd7 100644
--- a/arch/powerpc/platforms/pseries/lpar.c
+++ b/arch/powerpc/platforms/pseries/lpar.c
@@ -627,6 +627,18 @@ static void pSeries_lpar_flush_hash_range(unsigned long number, int local)
627 spin_unlock_irqrestore(&pSeries_lpar_tlbie_lock, flags); 627 spin_unlock_irqrestore(&pSeries_lpar_tlbie_lock, flags);
628} 628}
629 629
630static int __init disable_bulk_remove(char *str)
631{
632 if (strcmp(str, "off") == 0 &&
633 firmware_has_feature(FW_FEATURE_BULK_REMOVE)) {
634 printk(KERN_INFO "Disabling BULK_REMOVE firmware feature");
635 powerpc_firmware_features &= ~FW_FEATURE_BULK_REMOVE;
636 }
637 return 1;
638}
639
640__setup("bulk_remove=", disable_bulk_remove);
641
630void __init hpte_init_lpar(void) 642void __init hpte_init_lpar(void)
631{ 643{
632 ppc_md.hpte_invalidate = pSeries_lpar_hpte_invalidate; 644 ppc_md.hpte_invalidate = pSeries_lpar_hpte_invalidate;
diff --git a/arch/powerpc/platforms/pseries/nvram.c b/arch/powerpc/platforms/pseries/nvram.c
index bc3c7f2abd79..7e828ba29bc3 100644
--- a/arch/powerpc/platforms/pseries/nvram.c
+++ b/arch/powerpc/platforms/pseries/nvram.c
@@ -22,11 +22,25 @@
22#include <asm/prom.h> 22#include <asm/prom.h>
23#include <asm/machdep.h> 23#include <asm/machdep.h>
24 24
25/* Max bytes to read/write in one go */
26#define NVRW_CNT 0x20
27
25static unsigned int nvram_size; 28static unsigned int nvram_size;
26static int nvram_fetch, nvram_store; 29static int nvram_fetch, nvram_store;
27static char nvram_buf[NVRW_CNT]; /* assume this is in the first 4GB */ 30static char nvram_buf[NVRW_CNT]; /* assume this is in the first 4GB */
28static DEFINE_SPINLOCK(nvram_lock); 31static DEFINE_SPINLOCK(nvram_lock);
29 32
33static long nvram_error_log_index = -1;
34static long nvram_error_log_size = 0;
35
36struct err_log_info {
37 int error_type;
38 unsigned int seq_num;
39};
40#define NVRAM_MAX_REQ 2079
41#define NVRAM_MIN_REQ 1055
42
43#define NVRAM_LOG_PART_NAME "ibm,rtas-log"
30 44
31static ssize_t pSeries_nvram_read(char *buf, size_t count, loff_t *index) 45static ssize_t pSeries_nvram_read(char *buf, size_t count, loff_t *index)
32{ 46{
@@ -119,6 +133,197 @@ static ssize_t pSeries_nvram_get_size(void)
119 return nvram_size ? nvram_size : -ENODEV; 133 return nvram_size ? nvram_size : -ENODEV;
120} 134}
121 135
136
137/* nvram_write_error_log
138 *
139 * We need to buffer the error logs into nvram to ensure that we have
140 * the failure information to decode. If we have a severe error there
141 * is no way to guarantee that the OS or the machine is in a state to
142 * get back to user land and write the error to disk. For example if
143 * the SCSI device driver causes a Machine Check by writing to a bad
144 * IO address, there is no way of guaranteeing that the device driver
145 * is in any state that is would also be able to write the error data
146 * captured to disk, thus we buffer it in NVRAM for analysis on the
147 * next boot.
148 *
149 * In NVRAM the partition containing the error log buffer will looks like:
150 * Header (in bytes):
151 * +-----------+----------+--------+------------+------------------+
152 * | signature | checksum | length | name | data |
153 * |0 |1 |2 3|4 15|16 length-1|
154 * +-----------+----------+--------+------------+------------------+
155 *
156 * The 'data' section would look like (in bytes):
157 * +--------------+------------+-----------------------------------+
158 * | event_logged | sequence # | error log |
159 * |0 3|4 7|8 nvram_error_log_size-1|
160 * +--------------+------------+-----------------------------------+
161 *
162 * event_logged: 0 if event has not been logged to syslog, 1 if it has
163 * sequence #: The unique sequence # for each event. (until it wraps)
164 * error log: The error log from event_scan
165 */
166int nvram_write_error_log(char * buff, int length,
167 unsigned int err_type, unsigned int error_log_cnt)
168{
169 int rc;
170 loff_t tmp_index;
171 struct err_log_info info;
172
173 if (nvram_error_log_index == -1) {
174 return -ESPIPE;
175 }
176
177 if (length > nvram_error_log_size) {
178 length = nvram_error_log_size;
179 }
180
181 info.error_type = err_type;
182 info.seq_num = error_log_cnt;
183
184 tmp_index = nvram_error_log_index;
185
186 rc = ppc_md.nvram_write((char *)&info, sizeof(struct err_log_info), &tmp_index);
187 if (rc <= 0) {
188 printk(KERN_ERR "nvram_write_error_log: Failed nvram_write (%d)\n", rc);
189 return rc;
190 }
191
192 rc = ppc_md.nvram_write(buff, length, &tmp_index);
193 if (rc <= 0) {
194 printk(KERN_ERR "nvram_write_error_log: Failed nvram_write (%d)\n", rc);
195 return rc;
196 }
197
198 return 0;
199}
200
201/* nvram_read_error_log
202 *
203 * Reads nvram for error log for at most 'length'
204 */
205int nvram_read_error_log(char * buff, int length,
206 unsigned int * err_type, unsigned int * error_log_cnt)
207{
208 int rc;
209 loff_t tmp_index;
210 struct err_log_info info;
211
212 if (nvram_error_log_index == -1)
213 return -1;
214
215 if (length > nvram_error_log_size)
216 length = nvram_error_log_size;
217
218 tmp_index = nvram_error_log_index;
219
220 rc = ppc_md.nvram_read((char *)&info, sizeof(struct err_log_info), &tmp_index);
221 if (rc <= 0) {
222 printk(KERN_ERR "nvram_read_error_log: Failed nvram_read (%d)\n", rc);
223 return rc;
224 }
225
226 rc = ppc_md.nvram_read(buff, length, &tmp_index);
227 if (rc <= 0) {
228 printk(KERN_ERR "nvram_read_error_log: Failed nvram_read (%d)\n", rc);
229 return rc;
230 }
231
232 *error_log_cnt = info.seq_num;
233 *err_type = info.error_type;
234
235 return 0;
236}
237
238/* This doesn't actually zero anything, but it sets the event_logged
239 * word to tell that this event is safely in syslog.
240 */
241int nvram_clear_error_log(void)
242{
243 loff_t tmp_index;
244 int clear_word = ERR_FLAG_ALREADY_LOGGED;
245 int rc;
246
247 if (nvram_error_log_index == -1)
248 return -1;
249
250 tmp_index = nvram_error_log_index;
251
252 rc = ppc_md.nvram_write((char *)&clear_word, sizeof(int), &tmp_index);
253 if (rc <= 0) {
254 printk(KERN_ERR "nvram_clear_error_log: Failed nvram_write (%d)\n", rc);
255 return rc;
256 }
257
258 return 0;
259}
260
261/* pseries_nvram_init_log_partition
262 *
263 * This will setup the partition we need for buffering the
264 * error logs and cleanup partitions if needed.
265 *
266 * The general strategy is the following:
267 * 1.) If there is log partition large enough then use it.
268 * 2.) If there is none large enough, search
269 * for a free partition that is large enough.
270 * 3.) If there is not a free partition large enough remove
271 * _all_ OS partitions and consolidate the space.
272 * 4.) Will first try getting a chunk that will satisfy the maximum
273 * error log size (NVRAM_MAX_REQ).
274 * 5.) If the max chunk cannot be allocated then try finding a chunk
275 * that will satisfy the minum needed (NVRAM_MIN_REQ).
276 */
277static int __init pseries_nvram_init_log_partition(void)
278{
279 loff_t p;
280 int size;
281
282 /* Scan nvram for partitions */
283 nvram_scan_partitions();
284
285 /* Lookg for ours */
286 p = nvram_find_partition(NVRAM_LOG_PART_NAME, NVRAM_SIG_OS, &size);
287
288 /* Found one but too small, remove it */
289 if (p && size < NVRAM_MIN_REQ) {
290 pr_info("nvram: Found too small "NVRAM_LOG_PART_NAME" partition"
291 ",removing it...");
292 nvram_remove_partition(NVRAM_LOG_PART_NAME, NVRAM_SIG_OS);
293 p = 0;
294 }
295
296 /* Create one if we didn't find */
297 if (!p) {
298 p = nvram_create_partition(NVRAM_LOG_PART_NAME, NVRAM_SIG_OS,
299 NVRAM_MAX_REQ, NVRAM_MIN_REQ);
300 /* No room for it, try to get rid of any OS partition
301 * and try again
302 */
303 if (p == -ENOSPC) {
304 pr_info("nvram: No room to create "NVRAM_LOG_PART_NAME
305 " partition, deleting all OS partitions...");
306 nvram_remove_partition(NULL, NVRAM_SIG_OS);
307 p = nvram_create_partition(NVRAM_LOG_PART_NAME,
308 NVRAM_SIG_OS, NVRAM_MAX_REQ,
309 NVRAM_MIN_REQ);
310 }
311 }
312
313 if (p <= 0) {
314 pr_err("nvram: Failed to find or create "NVRAM_LOG_PART_NAME
315 " partition, err %d\n", (int)p);
316 return 0;
317 }
318
319 nvram_error_log_index = p;
320 nvram_error_log_size = nvram_get_partition_size(p) -
321 sizeof(struct err_log_info);
322
323 return 0;
324}
325machine_arch_initcall(pseries, pseries_nvram_init_log_partition);
326
122int __init pSeries_nvram_init(void) 327int __init pSeries_nvram_init(void)
123{ 328{
124 struct device_node *nvram; 329 struct device_node *nvram;
diff --git a/arch/powerpc/platforms/pseries/pseries_energy.c b/arch/powerpc/platforms/pseries/pseries_energy.c
new file mode 100644
index 000000000000..c8b3c69fe891
--- /dev/null
+++ b/arch/powerpc/platforms/pseries/pseries_energy.c
@@ -0,0 +1,326 @@
1/*
2 * POWER platform energy management driver
3 * Copyright (C) 2010 IBM Corporation
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 * This pseries platform device driver provides access to
10 * platform energy management capabilities.
11 */
12
13#include <linux/module.h>
14#include <linux/types.h>
15#include <linux/errno.h>
16#include <linux/init.h>
17#include <linux/seq_file.h>
18#include <linux/sysdev.h>
19#include <linux/cpu.h>
20#include <linux/of.h>
21#include <asm/cputhreads.h>
22#include <asm/page.h>
23#include <asm/hvcall.h>
24
25
26#define MODULE_VERS "1.0"
27#define MODULE_NAME "pseries_energy"
28
29/* Driver flags */
30
31static int sysfs_entries;
32
33/* Helper routines */
34
35/*
36 * Routine to detect firmware support for hcall
37 * return 1 if H_BEST_ENERGY is supported
38 * else return 0
39 */
40
41static int check_for_h_best_energy(void)
42{
43 struct device_node *rtas = NULL;
44 const char *hypertas, *s;
45 int length;
46 int rc = 0;
47
48 rtas = of_find_node_by_path("/rtas");
49 if (!rtas)
50 return 0;
51
52 hypertas = of_get_property(rtas, "ibm,hypertas-functions", &length);
53 if (!hypertas) {
54 of_node_put(rtas);
55 return 0;
56 }
57
58 /* hypertas will have list of strings with hcall names */
59 for (s = hypertas; s < hypertas + length; s += strlen(s) + 1) {
60 if (!strncmp("hcall-best-energy-1", s, 19)) {
61 rc = 1; /* Found the string */
62 break;
63 }
64 }
65 of_node_put(rtas);
66 return rc;
67}
68
69/* Helper Routines to convert between drc_index to cpu numbers */
70
71static u32 cpu_to_drc_index(int cpu)
72{
73 struct device_node *dn = NULL;
74 const int *indexes;
75 int i;
76 int rc = 1;
77 u32 ret = 0;
78
79 dn = of_find_node_by_path("/cpus");
80 if (dn == NULL)
81 goto err;
82 indexes = of_get_property(dn, "ibm,drc-indexes", NULL);
83 if (indexes == NULL)
84 goto err_of_node_put;
85 /* Convert logical cpu number to core number */
86 i = cpu_core_index_of_thread(cpu);
87 /*
88 * The first element indexes[0] is the number of drc_indexes
89 * returned in the list. Hence i+1 will get the drc_index
90 * corresponding to core number i.
91 */
92 WARN_ON(i > indexes[0]);
93 ret = indexes[i + 1];
94 rc = 0;
95
96err_of_node_put:
97 of_node_put(dn);
98err:
99 if (rc)
100 printk(KERN_WARNING "cpu_to_drc_index(%d) failed", cpu);
101 return ret;
102}
103
104static int drc_index_to_cpu(u32 drc_index)
105{
106 struct device_node *dn = NULL;
107 const int *indexes;
108 int i, cpu = 0;
109 int rc = 1;
110
111 dn = of_find_node_by_path("/cpus");
112 if (dn == NULL)
113 goto err;
114 indexes = of_get_property(dn, "ibm,drc-indexes", NULL);
115 if (indexes == NULL)
116 goto err_of_node_put;
117 /*
118 * First element in the array is the number of drc_indexes
119 * returned. Search through the list to find the matching
120 * drc_index and get the core number
121 */
122 for (i = 0; i < indexes[0]; i++) {
123 if (indexes[i + 1] == drc_index)
124 break;
125 }
126 /* Convert core number to logical cpu number */
127 cpu = cpu_first_thread_of_core(i);
128 rc = 0;
129
130err_of_node_put:
131 of_node_put(dn);
132err:
133 if (rc)
134 printk(KERN_WARNING "drc_index_to_cpu(%d) failed", drc_index);
135 return cpu;
136}
137
138/*
139 * pseries hypervisor call H_BEST_ENERGY provides hints to OS on
140 * preferred logical cpus to activate or deactivate for optimized
141 * energy consumption.
142 */
143
144#define FLAGS_MODE1 0x004E200000080E01
145#define FLAGS_MODE2 0x004E200000080401
146#define FLAGS_ACTIVATE 0x100
147
148static ssize_t get_best_energy_list(char *page, int activate)
149{
150 int rc, cnt, i, cpu;
151 unsigned long retbuf[PLPAR_HCALL9_BUFSIZE];
152 unsigned long flags = 0;
153 u32 *buf_page;
154 char *s = page;
155
156 buf_page = (u32 *) get_zeroed_page(GFP_KERNEL);
157 if (!buf_page)
158 return -ENOMEM;
159
160 flags = FLAGS_MODE1;
161 if (activate)
162 flags |= FLAGS_ACTIVATE;
163
164 rc = plpar_hcall9(H_BEST_ENERGY, retbuf, flags, 0, __pa(buf_page),
165 0, 0, 0, 0, 0, 0);
166 if (rc != H_SUCCESS) {
167 free_page((unsigned long) buf_page);
168 return -EINVAL;
169 }
170
171 cnt = retbuf[0];
172 for (i = 0; i < cnt; i++) {
173 cpu = drc_index_to_cpu(buf_page[2*i+1]);
174 if ((cpu_online(cpu) && !activate) ||
175 (!cpu_online(cpu) && activate))
176 s += sprintf(s, "%d,", cpu);
177 }
178 if (s > page) { /* Something to show */
179 s--; /* Suppress last comma */
180 s += sprintf(s, "\n");
181 }
182
183 free_page((unsigned long) buf_page);
184 return s-page;
185}
186
187static ssize_t get_best_energy_data(struct sys_device *dev,
188 char *page, int activate)
189{
190 int rc;
191 unsigned long retbuf[PLPAR_HCALL9_BUFSIZE];
192 unsigned long flags = 0;
193
194 flags = FLAGS_MODE2;
195 if (activate)
196 flags |= FLAGS_ACTIVATE;
197
198 rc = plpar_hcall9(H_BEST_ENERGY, retbuf, flags,
199 cpu_to_drc_index(dev->id),
200 0, 0, 0, 0, 0, 0, 0);
201
202 if (rc != H_SUCCESS)
203 return -EINVAL;
204
205 return sprintf(page, "%lu\n", retbuf[1] >> 32);
206}
207
208/* Wrapper functions */
209
210static ssize_t cpu_activate_hint_list_show(struct sysdev_class *class,
211 struct sysdev_class_attribute *attr, char *page)
212{
213 return get_best_energy_list(page, 1);
214}
215
216static ssize_t cpu_deactivate_hint_list_show(struct sysdev_class *class,
217 struct sysdev_class_attribute *attr, char *page)
218{
219 return get_best_energy_list(page, 0);
220}
221
222static ssize_t percpu_activate_hint_show(struct sys_device *dev,
223 struct sysdev_attribute *attr, char *page)
224{
225 return get_best_energy_data(dev, page, 1);
226}
227
228static ssize_t percpu_deactivate_hint_show(struct sys_device *dev,
229 struct sysdev_attribute *attr, char *page)
230{
231 return get_best_energy_data(dev, page, 0);
232}
233
234/*
235 * Create sysfs interface:
236 * /sys/devices/system/cpu/pseries_activate_hint_list
237 * /sys/devices/system/cpu/pseries_deactivate_hint_list
238 * Comma separated list of cpus to activate or deactivate
239 * /sys/devices/system/cpu/cpuN/pseries_activate_hint
240 * /sys/devices/system/cpu/cpuN/pseries_deactivate_hint
241 * Per-cpu value of the hint
242 */
243
244struct sysdev_class_attribute attr_cpu_activate_hint_list =
245 _SYSDEV_CLASS_ATTR(pseries_activate_hint_list, 0444,
246 cpu_activate_hint_list_show, NULL);
247
248struct sysdev_class_attribute attr_cpu_deactivate_hint_list =
249 _SYSDEV_CLASS_ATTR(pseries_deactivate_hint_list, 0444,
250 cpu_deactivate_hint_list_show, NULL);
251
252struct sysdev_attribute attr_percpu_activate_hint =
253 _SYSDEV_ATTR(pseries_activate_hint, 0444,
254 percpu_activate_hint_show, NULL);
255
256struct sysdev_attribute attr_percpu_deactivate_hint =
257 _SYSDEV_ATTR(pseries_deactivate_hint, 0444,
258 percpu_deactivate_hint_show, NULL);
259
260static int __init pseries_energy_init(void)
261{
262 int cpu, err;
263 struct sys_device *cpu_sys_dev;
264
265 if (!check_for_h_best_energy()) {
266 printk(KERN_INFO "Hypercall H_BEST_ENERGY not supported\n");
267 return 0;
268 }
269 /* Create the sysfs files */
270 err = sysfs_create_file(&cpu_sysdev_class.kset.kobj,
271 &attr_cpu_activate_hint_list.attr);
272 if (!err)
273 err = sysfs_create_file(&cpu_sysdev_class.kset.kobj,
274 &attr_cpu_deactivate_hint_list.attr);
275
276 if (err)
277 return err;
278 for_each_possible_cpu(cpu) {
279 cpu_sys_dev = get_cpu_sysdev(cpu);
280 err = sysfs_create_file(&cpu_sys_dev->kobj,
281 &attr_percpu_activate_hint.attr);
282 if (err)
283 break;
284 err = sysfs_create_file(&cpu_sys_dev->kobj,
285 &attr_percpu_deactivate_hint.attr);
286 if (err)
287 break;
288 }
289
290 if (err)
291 return err;
292
293 sysfs_entries = 1; /* Removed entries on cleanup */
294 return 0;
295
296}
297
298static void __exit pseries_energy_cleanup(void)
299{
300 int cpu;
301 struct sys_device *cpu_sys_dev;
302
303 if (!sysfs_entries)
304 return;
305
306 /* Remove the sysfs files */
307 sysfs_remove_file(&cpu_sysdev_class.kset.kobj,
308 &attr_cpu_activate_hint_list.attr);
309
310 sysfs_remove_file(&cpu_sysdev_class.kset.kobj,
311 &attr_cpu_deactivate_hint_list.attr);
312
313 for_each_possible_cpu(cpu) {
314 cpu_sys_dev = get_cpu_sysdev(cpu);
315 sysfs_remove_file(&cpu_sys_dev->kobj,
316 &attr_percpu_activate_hint.attr);
317 sysfs_remove_file(&cpu_sys_dev->kobj,
318 &attr_percpu_deactivate_hint.attr);
319 }
320}
321
322module_init(pseries_energy_init);
323module_exit(pseries_energy_cleanup);
324MODULE_DESCRIPTION("Driver for pSeries platform energy management");
325MODULE_AUTHOR("Vaidyanathan Srinivasan");
326MODULE_LICENSE("GPL");
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 0bef9dacb64e..9c2973479142 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_OF_RTC) += of_rtc.o
41ifeq ($(CONFIG_PCI),y) 41ifeq ($(CONFIG_PCI),y)
42obj-$(CONFIG_4xx) += ppc4xx_pci.o 42obj-$(CONFIG_4xx) += ppc4xx_pci.o
43endif 43endif
44obj-$(CONFIG_PPC4xx_CPM) += ppc4xx_cpm.o
44obj-$(CONFIG_PPC4xx_GPIO) += ppc4xx_gpio.o 45obj-$(CONFIG_PPC4xx_GPIO) += ppc4xx_gpio.o
45 46
46obj-$(CONFIG_CPM) += cpm_common.o 47obj-$(CONFIG_CPM) += cpm_common.o
diff --git a/arch/powerpc/sysdev/dart_iommu.c b/arch/powerpc/sysdev/dart_iommu.c
index 17cf15ec38be..8e9e06a7ca59 100644
--- a/arch/powerpc/sysdev/dart_iommu.c
+++ b/arch/powerpc/sysdev/dart_iommu.c
@@ -312,17 +312,10 @@ static void pci_dma_dev_setup_dart(struct pci_dev *dev)
312 312
313static void pci_dma_bus_setup_dart(struct pci_bus *bus) 313static void pci_dma_bus_setup_dart(struct pci_bus *bus)
314{ 314{
315 struct device_node *dn;
316
317 if (!iommu_table_dart_inited) { 315 if (!iommu_table_dart_inited) {
318 iommu_table_dart_inited = 1; 316 iommu_table_dart_inited = 1;
319 iommu_table_dart_setup(); 317 iommu_table_dart_setup();
320 } 318 }
321
322 dn = pci_bus_to_OF_node(bus);
323
324 if (dn)
325 PCI_DN(dn)->iommu_table = &iommu_table_dart;
326} 319}
327 320
328static bool dart_device_on_pcie(struct device *dev) 321static bool dart_device_on_pcie(struct device *dev)
@@ -373,7 +366,7 @@ void __init iommu_init_early_dart(void)
373 if (dn == NULL) { 366 if (dn == NULL) {
374 dn = of_find_compatible_node(NULL, "dart", "u4-dart"); 367 dn = of_find_compatible_node(NULL, "dart", "u4-dart");
375 if (dn == NULL) 368 if (dn == NULL)
376 goto bail; 369 return; /* use default direct_dma_ops */
377 dart_is_u4 = 1; 370 dart_is_u4 = 1;
378 } 371 }
379 372
diff --git a/arch/powerpc/sysdev/mpc8xxx_gpio.c b/arch/powerpc/sysdev/mpc8xxx_gpio.c
index c0ea05e87f1d..c48cd8178079 100644
--- a/arch/powerpc/sysdev/mpc8xxx_gpio.c
+++ b/arch/powerpc/sysdev/mpc8xxx_gpio.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * GPIOs on MPC8349/8572/8610 and compatible 2 * GPIOs on MPC512x/8349/8572/8610 and compatible
3 * 3 *
4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk> 4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
5 * 5 *
@@ -26,6 +26,7 @@
26#define GPIO_IER 0x0c 26#define GPIO_IER 0x0c
27#define GPIO_IMR 0x10 27#define GPIO_IMR 0x10
28#define GPIO_ICR 0x14 28#define GPIO_ICR 0x14
29#define GPIO_ICR2 0x18
29 30
30struct mpc8xxx_gpio_chip { 31struct mpc8xxx_gpio_chip {
31 struct of_mm_gpio_chip mm_gc; 32 struct of_mm_gpio_chip mm_gc;
@@ -37,6 +38,7 @@ struct mpc8xxx_gpio_chip {
37 */ 38 */
38 u32 data; 39 u32 data;
39 struct irq_host *irq; 40 struct irq_host *irq;
41 void *of_dev_id_data;
40}; 42};
41 43
42static inline u32 mpc8xxx_gpio2mask(unsigned int gpio) 44static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
@@ -215,6 +217,51 @@ static int mpc8xxx_irq_set_type(unsigned int virq, unsigned int flow_type)
215 return 0; 217 return 0;
216} 218}
217 219
220static int mpc512x_irq_set_type(unsigned int virq, unsigned int flow_type)
221{
222 struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq);
223 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
224 unsigned long gpio = virq_to_hw(virq);
225 void __iomem *reg;
226 unsigned int shift;
227 unsigned long flags;
228
229 if (gpio < 16) {
230 reg = mm->regs + GPIO_ICR;
231 shift = (15 - gpio) * 2;
232 } else {
233 reg = mm->regs + GPIO_ICR2;
234 shift = (15 - (gpio % 16)) * 2;
235 }
236
237 switch (flow_type) {
238 case IRQ_TYPE_EDGE_FALLING:
239 case IRQ_TYPE_LEVEL_LOW:
240 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
241 clrsetbits_be32(reg, 3 << shift, 2 << shift);
242 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
243 break;
244
245 case IRQ_TYPE_EDGE_RISING:
246 case IRQ_TYPE_LEVEL_HIGH:
247 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
248 clrsetbits_be32(reg, 3 << shift, 1 << shift);
249 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
250 break;
251
252 case IRQ_TYPE_EDGE_BOTH:
253 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
254 clrbits32(reg, 3 << shift);
255 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
256 break;
257
258 default:
259 return -EINVAL;
260 }
261
262 return 0;
263}
264
218static struct irq_chip mpc8xxx_irq_chip = { 265static struct irq_chip mpc8xxx_irq_chip = {
219 .name = "mpc8xxx-gpio", 266 .name = "mpc8xxx-gpio",
220 .unmask = mpc8xxx_irq_unmask, 267 .unmask = mpc8xxx_irq_unmask,
@@ -226,6 +273,11 @@ static struct irq_chip mpc8xxx_irq_chip = {
226static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq, 273static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq,
227 irq_hw_number_t hw) 274 irq_hw_number_t hw)
228{ 275{
276 struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data;
277
278 if (mpc8xxx_gc->of_dev_id_data)
279 mpc8xxx_irq_chip.set_type = mpc8xxx_gc->of_dev_id_data;
280
229 set_irq_chip_data(virq, h->host_data); 281 set_irq_chip_data(virq, h->host_data);
230 set_irq_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq); 282 set_irq_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq);
231 set_irq_type(virq, IRQ_TYPE_NONE); 283 set_irq_type(virq, IRQ_TYPE_NONE);
@@ -253,11 +305,20 @@ static struct irq_host_ops mpc8xxx_gpio_irq_ops = {
253 .xlate = mpc8xxx_gpio_irq_xlate, 305 .xlate = mpc8xxx_gpio_irq_xlate,
254}; 306};
255 307
308static struct of_device_id mpc8xxx_gpio_ids[] __initdata = {
309 { .compatible = "fsl,mpc8349-gpio", },
310 { .compatible = "fsl,mpc8572-gpio", },
311 { .compatible = "fsl,mpc8610-gpio", },
312 { .compatible = "fsl,mpc5121-gpio", .data = mpc512x_irq_set_type, },
313 {}
314};
315
256static void __init mpc8xxx_add_controller(struct device_node *np) 316static void __init mpc8xxx_add_controller(struct device_node *np)
257{ 317{
258 struct mpc8xxx_gpio_chip *mpc8xxx_gc; 318 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
259 struct of_mm_gpio_chip *mm_gc; 319 struct of_mm_gpio_chip *mm_gc;
260 struct gpio_chip *gc; 320 struct gpio_chip *gc;
321 const struct of_device_id *id;
261 unsigned hwirq; 322 unsigned hwirq;
262 int ret; 323 int ret;
263 324
@@ -297,6 +358,10 @@ static void __init mpc8xxx_add_controller(struct device_node *np)
297 if (!mpc8xxx_gc->irq) 358 if (!mpc8xxx_gc->irq)
298 goto skip_irq; 359 goto skip_irq;
299 360
361 id = of_match_node(mpc8xxx_gpio_ids, np);
362 if (id)
363 mpc8xxx_gc->of_dev_id_data = id->data;
364
300 mpc8xxx_gc->irq->host_data = mpc8xxx_gc; 365 mpc8xxx_gc->irq->host_data = mpc8xxx_gc;
301 366
302 /* ack and mask all irqs */ 367 /* ack and mask all irqs */
@@ -321,13 +386,7 @@ static int __init mpc8xxx_add_gpiochips(void)
321{ 386{
322 struct device_node *np; 387 struct device_node *np;
323 388
324 for_each_compatible_node(np, NULL, "fsl,mpc8349-gpio") 389 for_each_matching_node(np, mpc8xxx_gpio_ids)
325 mpc8xxx_add_controller(np);
326
327 for_each_compatible_node(np, NULL, "fsl,mpc8572-gpio")
328 mpc8xxx_add_controller(np);
329
330 for_each_compatible_node(np, NULL, "fsl,mpc8610-gpio")
331 mpc8xxx_add_controller(np); 390 mpc8xxx_add_controller(np);
332 391
333 for_each_compatible_node(np, NULL, "fsl,qoriq-gpio") 392 for_each_compatible_node(np, NULL, "fsl,qoriq-gpio")
diff --git a/arch/powerpc/sysdev/ppc4xx_cpm.c b/arch/powerpc/sysdev/ppc4xx_cpm.c
new file mode 100644
index 000000000000..73b86cc5ea74
--- /dev/null
+++ b/arch/powerpc/sysdev/ppc4xx_cpm.c
@@ -0,0 +1,346 @@
1/*
2 * PowerPC 4xx Clock and Power Management
3 *
4 * Copyright (C) 2010, Applied Micro Circuits Corporation
5 * Victor Gallardo (vgallardo@apm.com)
6 *
7 * Based on arch/powerpc/platforms/44x/idle.c:
8 * Jerone Young <jyoung5@us.ibm.com>
9 * Copyright 2008 IBM Corp.
10 *
11 * Based on arch/powerpc/sysdev/fsl_pmc.c:
12 * Anton Vorontsov <avorontsov@ru.mvista.com>
13 * Copyright 2009 MontaVista Software, Inc.
14 *
15 * See file CREDITS for list of people who contributed to this
16 * project.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA
32 */
33
34#include <linux/kernel.h>
35#include <linux/of_platform.h>
36#include <linux/sysfs.h>
37#include <linux/cpu.h>
38#include <linux/suspend.h>
39#include <asm/dcr.h>
40#include <asm/dcr-native.h>
41#include <asm/machdep.h>
42
43#define CPM_ER 0
44#define CPM_FR 1
45#define CPM_SR 2
46
47#define CPM_IDLE_WAIT 0
48#define CPM_IDLE_DOZE 1
49
50struct cpm {
51 dcr_host_t dcr_host;
52 unsigned int dcr_offset[3];
53 unsigned int powersave_off;
54 unsigned int unused;
55 unsigned int idle_doze;
56 unsigned int standby;
57 unsigned int suspend;
58};
59
60static struct cpm cpm;
61
62struct cpm_idle_mode {
63 unsigned int enabled;
64 const char *name;
65};
66
67static struct cpm_idle_mode idle_mode[] = {
68 [CPM_IDLE_WAIT] = { 1, "wait" }, /* default */
69 [CPM_IDLE_DOZE] = { 0, "doze" },
70};
71
72static unsigned int cpm_set(unsigned int cpm_reg, unsigned int mask)
73{
74 unsigned int value;
75
76 /* CPM controller supports 3 different types of sleep interface
77 * known as class 1, 2 and 3. For class 1 units, they are
78 * unconditionally put to sleep when the corresponding CPM bit is
79 * set. For class 2 and 3 units this is not case; if they can be
80 * put to to sleep, they will. Here we do not verify, we just
81 * set them and expect them to eventually go off when they can.
82 */
83 value = dcr_read(cpm.dcr_host, cpm.dcr_offset[cpm_reg]);
84 dcr_write(cpm.dcr_host, cpm.dcr_offset[cpm_reg], value | mask);
85
86 /* return old state, to restore later if needed */
87 return value;
88}
89
90static void cpm_idle_wait(void)
91{
92 unsigned long msr_save;
93
94 /* save off initial state */
95 msr_save = mfmsr();
96 /* sync required when CPM0_ER[CPU] is set */
97 mb();
98 /* set wait state MSR */
99 mtmsr(msr_save|MSR_WE|MSR_EE|MSR_CE|MSR_DE);
100 isync();
101 /* return to initial state */
102 mtmsr(msr_save);
103 isync();
104}
105
106static void cpm_idle_sleep(unsigned int mask)
107{
108 unsigned int er_save;
109
110 /* update CPM_ER state */
111 er_save = cpm_set(CPM_ER, mask);
112
113 /* go to wait state so that CPM0_ER[CPU] can take effect */
114 cpm_idle_wait();
115
116 /* restore CPM_ER state */
117 dcr_write(cpm.dcr_host, cpm.dcr_offset[CPM_ER], er_save);
118}
119
120static void cpm_idle_doze(void)
121{
122 cpm_idle_sleep(cpm.idle_doze);
123}
124
125static void cpm_idle_config(int mode)
126{
127 int i;
128
129 if (idle_mode[mode].enabled)
130 return;
131
132 for (i = 0; i < ARRAY_SIZE(idle_mode); i++)
133 idle_mode[i].enabled = 0;
134
135 idle_mode[mode].enabled = 1;
136}
137
138static ssize_t cpm_idle_show(struct kobject *kobj,
139 struct kobj_attribute *attr, char *buf)
140{
141 char *s = buf;
142 int i;
143
144 for (i = 0; i < ARRAY_SIZE(idle_mode); i++) {
145 if (idle_mode[i].enabled)
146 s += sprintf(s, "[%s] ", idle_mode[i].name);
147 else
148 s += sprintf(s, "%s ", idle_mode[i].name);
149 }
150
151 *(s-1) = '\n'; /* convert the last space to a newline */
152
153 return s - buf;
154}
155
156static ssize_t cpm_idle_store(struct kobject *kobj,
157 struct kobj_attribute *attr,
158 const char *buf, size_t n)
159{
160 int i;
161 char *p;
162 int len;
163
164 p = memchr(buf, '\n', n);
165 len = p ? p - buf : n;
166
167 for (i = 0; i < ARRAY_SIZE(idle_mode); i++) {
168 if (strncmp(buf, idle_mode[i].name, len) == 0) {
169 cpm_idle_config(i);
170 return n;
171 }
172 }
173
174 return -EINVAL;
175}
176
177static struct kobj_attribute cpm_idle_attr =
178 __ATTR(idle, 0644, cpm_idle_show, cpm_idle_store);
179
180static void cpm_idle_config_sysfs(void)
181{
182 struct sys_device *sys_dev;
183 unsigned long ret;
184
185 sys_dev = get_cpu_sysdev(0);
186
187 ret = sysfs_create_file(&sys_dev->kobj,
188 &cpm_idle_attr.attr);
189 if (ret)
190 printk(KERN_WARNING
191 "cpm: failed to create idle sysfs entry\n");
192}
193
194static void cpm_idle(void)
195{
196 if (idle_mode[CPM_IDLE_DOZE].enabled)
197 cpm_idle_doze();
198 else
199 cpm_idle_wait();
200}
201
202static int cpm_suspend_valid(suspend_state_t state)
203{
204 switch (state) {
205 case PM_SUSPEND_STANDBY:
206 return !!cpm.standby;
207 case PM_SUSPEND_MEM:
208 return !!cpm.suspend;
209 default:
210 return 0;
211 }
212}
213
214static void cpm_suspend_standby(unsigned int mask)
215{
216 unsigned long tcr_save;
217
218 /* disable decrement interrupt */
219 tcr_save = mfspr(SPRN_TCR);
220 mtspr(SPRN_TCR, tcr_save & ~TCR_DIE);
221
222 /* go to sleep state */
223 cpm_idle_sleep(mask);
224
225 /* restore decrement interrupt */
226 mtspr(SPRN_TCR, tcr_save);
227}
228
229static int cpm_suspend_enter(suspend_state_t state)
230{
231 switch (state) {
232 case PM_SUSPEND_STANDBY:
233 cpm_suspend_standby(cpm.standby);
234 break;
235 case PM_SUSPEND_MEM:
236 cpm_suspend_standby(cpm.suspend);
237 break;
238 }
239
240 return 0;
241}
242
243static struct platform_suspend_ops cpm_suspend_ops = {
244 .valid = cpm_suspend_valid,
245 .enter = cpm_suspend_enter,
246};
247
248static int cpm_get_uint_property(struct device_node *np,
249 const char *name)
250{
251 int len;
252 const unsigned int *prop = of_get_property(np, name, &len);
253
254 if (prop == NULL || len < sizeof(u32))
255 return 0;
256
257 return *prop;
258}
259
260static int __init cpm_init(void)
261{
262 struct device_node *np;
263 int dcr_base, dcr_len;
264 int ret = 0;
265
266 if (!cpm.powersave_off) {
267 cpm_idle_config(CPM_IDLE_WAIT);
268 ppc_md.power_save = &cpm_idle;
269 }
270
271 np = of_find_compatible_node(NULL, NULL, "ibm,cpm");
272 if (!np) {
273 ret = -EINVAL;
274 goto out;
275 }
276
277 dcr_base = dcr_resource_start(np, 0);
278 dcr_len = dcr_resource_len(np, 0);
279
280 if (dcr_base == 0 || dcr_len == 0) {
281 printk(KERN_ERR "cpm: could not parse dcr property for %s\n",
282 np->full_name);
283 ret = -EINVAL;
284 goto out;
285 }
286
287 cpm.dcr_host = dcr_map(np, dcr_base, dcr_len);
288
289 if (!DCR_MAP_OK(cpm.dcr_host)) {
290 printk(KERN_ERR "cpm: failed to map dcr property for %s\n",
291 np->full_name);
292 ret = -EINVAL;
293 goto out;
294 }
295
296 /* All 4xx SoCs with a CPM controller have one of two
297 * different order for the CPM registers. Some have the
298 * CPM registers in the following order (ER,FR,SR). The
299 * others have them in the following order (SR,ER,FR).
300 */
301
302 if (cpm_get_uint_property(np, "er-offset") == 0) {
303 cpm.dcr_offset[CPM_ER] = 0;
304 cpm.dcr_offset[CPM_FR] = 1;
305 cpm.dcr_offset[CPM_SR] = 2;
306 } else {
307 cpm.dcr_offset[CPM_ER] = 1;
308 cpm.dcr_offset[CPM_FR] = 2;
309 cpm.dcr_offset[CPM_SR] = 0;
310 }
311
312 /* Now let's see what IPs to turn off for the following modes */
313
314 cpm.unused = cpm_get_uint_property(np, "unused-units");
315 cpm.idle_doze = cpm_get_uint_property(np, "idle-doze");
316 cpm.standby = cpm_get_uint_property(np, "standby");
317 cpm.suspend = cpm_get_uint_property(np, "suspend");
318
319 /* If some IPs are unused let's turn them off now */
320
321 if (cpm.unused) {
322 cpm_set(CPM_ER, cpm.unused);
323 cpm_set(CPM_FR, cpm.unused);
324 }
325
326 /* Now let's export interfaces */
327
328 if (!cpm.powersave_off && cpm.idle_doze)
329 cpm_idle_config_sysfs();
330
331 if (cpm.standby || cpm.suspend)
332 suspend_set_ops(&cpm_suspend_ops);
333out:
334 if (np)
335 of_node_put(np);
336 return ret;
337}
338
339late_initcall(cpm_init);
340
341static int __init cpm_powersave_off(char *arg)
342{
343 cpm.powersave_off = 1;
344 return 0;
345}
346__setup("powersave=off", cpm_powersave_off);
diff --git a/arch/powerpc/sysdev/tsi108_dev.c b/arch/powerpc/sysdev/tsi108_dev.c
index c2d675b6392c..ee056807b52c 100644
--- a/arch/powerpc/sysdev/tsi108_dev.c
+++ b/arch/powerpc/sysdev/tsi108_dev.c
@@ -84,8 +84,8 @@ static int __init tsi108_eth_of_init(void)
84 memset(&tsi_eth_data, 0, sizeof(tsi_eth_data)); 84 memset(&tsi_eth_data, 0, sizeof(tsi_eth_data));
85 85
86 ret = of_address_to_resource(np, 0, &r[0]); 86 ret = of_address_to_resource(np, 0, &r[0]);
87 DBG("%s: name:start->end = %s:0x%lx-> 0x%lx\n", 87 DBG("%s: name:start->end = %s:%pR\n",
88 __func__,r[0].name, r[0].start, r[0].end); 88 __func__, r[0].name, &r[0]);
89 if (ret) 89 if (ret)
90 goto err; 90 goto err;
91 91
@@ -93,8 +93,8 @@ static int __init tsi108_eth_of_init(void)
93 r[1].start = irq_of_parse_and_map(np, 0); 93 r[1].start = irq_of_parse_and_map(np, 0);
94 r[1].end = irq_of_parse_and_map(np, 0); 94 r[1].end = irq_of_parse_and_map(np, 0);
95 r[1].flags = IORESOURCE_IRQ; 95 r[1].flags = IORESOURCE_IRQ;
96 DBG("%s: name:start->end = %s:0x%lx-> 0x%lx\n", 96 DBG("%s: name:start->end = %s:%pR\n",
97 __func__,r[1].name, r[1].start, r[1].end); 97 __func__, r[1].name, &r[1]);
98 98
99 tsi_eth_dev = 99 tsi_eth_dev =
100 platform_device_register_simple("tsi-ethernet", i++, &r[0], 100 platform_device_register_simple("tsi-ethernet", i++, &r[0],
diff --git a/arch/sparc/kernel/cpu.c b/arch/sparc/kernel/cpu.c
index e447938d39cf..0dc714fa23d8 100644
--- a/arch/sparc/kernel/cpu.c
+++ b/arch/sparc/kernel/cpu.c
@@ -375,5 +375,5 @@ static int __init cpu_type_probe(void)
375 return 0; 375 return 0;
376} 376}
377 377
378arch_initcall(cpu_type_probe); 378early_initcall(cpu_type_probe);
379#endif 379#endif
diff --git a/arch/sparc/kernel/pcr.c b/arch/sparc/kernel/pcr.c
index b87873c0e8ea..ae96cf52a955 100644
--- a/arch/sparc/kernel/pcr.c
+++ b/arch/sparc/kernel/pcr.c
@@ -168,4 +168,4 @@ out_unregister:
168 return err; 168 return err;
169} 169}
170 170
171arch_initcall(pcr_arch_init); 171early_initcall(pcr_arch_init);
diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h
index 55d106b5e31b..211ca3f7fd16 100644
--- a/arch/x86/include/asm/acpi.h
+++ b/arch/x86/include/asm/acpi.h
@@ -185,17 +185,16 @@ struct bootnode;
185 185
186#ifdef CONFIG_ACPI_NUMA 186#ifdef CONFIG_ACPI_NUMA
187extern int acpi_numa; 187extern int acpi_numa;
188extern int acpi_get_nodes(struct bootnode *physnodes); 188extern void acpi_get_nodes(struct bootnode *physnodes, unsigned long start,
189 unsigned long end);
189extern int acpi_scan_nodes(unsigned long start, unsigned long end); 190extern int acpi_scan_nodes(unsigned long start, unsigned long end);
190#define NR_NODE_MEMBLKS (MAX_NUMNODES*2) 191#define NR_NODE_MEMBLKS (MAX_NUMNODES*2)
192
193#ifdef CONFIG_NUMA_EMU
191extern void acpi_fake_nodes(const struct bootnode *fake_nodes, 194extern void acpi_fake_nodes(const struct bootnode *fake_nodes,
192 int num_nodes); 195 int num_nodes);
193#else
194static inline void acpi_fake_nodes(const struct bootnode *fake_nodes,
195 int num_nodes)
196{
197}
198#endif 196#endif
197#endif /* CONFIG_ACPI_NUMA */
199 198
200#define acpi_unlazy_tlb(x) leave_mm(x) 199#define acpi_unlazy_tlb(x) leave_mm(x)
201 200
diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h
index 6aee50d655d1..64dc82ee19f0 100644
--- a/arch/x86/include/asm/amd_nb.h
+++ b/arch/x86/include/asm/amd_nb.h
@@ -3,16 +3,27 @@
3 3
4#include <linux/pci.h> 4#include <linux/pci.h>
5 5
6struct amd_nb_bus_dev_range {
7 u8 bus;
8 u8 dev_base;
9 u8 dev_limit;
10};
11
6extern struct pci_device_id amd_nb_misc_ids[]; 12extern struct pci_device_id amd_nb_misc_ids[];
13extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[];
7struct bootnode; 14struct bootnode;
8 15
9extern int early_is_amd_nb(u32 value); 16extern int early_is_amd_nb(u32 value);
10extern int amd_cache_northbridges(void); 17extern int amd_cache_northbridges(void);
11extern void amd_flush_garts(void); 18extern void amd_flush_garts(void);
12extern int amd_get_nodes(struct bootnode *nodes);
13extern int amd_numa_init(unsigned long start_pfn, unsigned long end_pfn); 19extern int amd_numa_init(unsigned long start_pfn, unsigned long end_pfn);
14extern int amd_scan_nodes(void); 20extern int amd_scan_nodes(void);
15 21
22#ifdef CONFIG_NUMA_EMU
23extern void amd_fake_nodes(const struct bootnode *nodes, int nr_nodes);
24extern void amd_get_nodes(struct bootnode *nodes);
25#endif
26
16struct amd_northbridge { 27struct amd_northbridge {
17 struct pci_dev *misc; 28 struct pci_dev *misc;
18}; 29};
diff --git a/arch/x86/include/asm/fixmap.h b/arch/x86/include/asm/fixmap.h
index 0141b234406f..4729b2b63117 100644
--- a/arch/x86/include/asm/fixmap.h
+++ b/arch/x86/include/asm/fixmap.h
@@ -116,11 +116,11 @@ enum fixed_addresses {
116#endif 116#endif
117 FIX_TEXT_POKE1, /* reserve 2 pages for text_poke() */ 117 FIX_TEXT_POKE1, /* reserve 2 pages for text_poke() */
118 FIX_TEXT_POKE0, /* first page is last, because allocation is backward */ 118 FIX_TEXT_POKE0, /* first page is last, because allocation is backward */
119 __end_of_permanent_fixed_addresses,
120
121#ifdef CONFIG_X86_MRST 119#ifdef CONFIG_X86_MRST
122 FIX_LNW_VRTC, 120 FIX_LNW_VRTC,
123#endif 121#endif
122 __end_of_permanent_fixed_addresses,
123
124 /* 124 /*
125 * 256 temporary boot-time mappings, used by early_ioremap(), 125 * 256 temporary boot-time mappings, used by early_ioremap(),
126 * before ioremap() is functional. 126 * before ioremap() is functional.
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 49dbfdfa50f9..91d915a65259 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -38,12 +38,9 @@ static inline int gpio_cansleep(unsigned int gpio)
38 return __gpio_cansleep(gpio); 38 return __gpio_cansleep(gpio);
39} 39}
40 40
41/*
42 * Not implemented, yet.
43 */
44static inline int gpio_to_irq(unsigned int gpio) 41static inline int gpio_to_irq(unsigned int gpio)
45{ 42{
46 return -ENOSYS; 43 return __gpio_to_irq(gpio);
47} 44}
48 45
49static inline int irq_to_gpio(unsigned int irq) 46static inline int irq_to_gpio(unsigned int irq)
diff --git a/arch/x86/include/asm/kdebug.h b/arch/x86/include/asm/kdebug.h
index f23eb2528464..ca242d35e873 100644
--- a/arch/x86/include/asm/kdebug.h
+++ b/arch/x86/include/asm/kdebug.h
@@ -18,7 +18,6 @@ enum die_val {
18 DIE_TRAP, 18 DIE_TRAP,
19 DIE_GPF, 19 DIE_GPF,
20 DIE_CALL, 20 DIE_CALL,
21 DIE_NMI_IPI,
22 DIE_PAGE_FAULT, 21 DIE_PAGE_FAULT,
23 DIE_NMIUNKNOWN, 22 DIE_NMIUNKNOWN,
24}; 23};
diff --git a/arch/x86/include/asm/mach_traps.h b/arch/x86/include/asm/mach_traps.h
index f7920601e472..72a8b52e7dfd 100644
--- a/arch/x86/include/asm/mach_traps.h
+++ b/arch/x86/include/asm/mach_traps.h
@@ -7,9 +7,19 @@
7 7
8#include <asm/mc146818rtc.h> 8#include <asm/mc146818rtc.h>
9 9
10#define NMI_REASON_PORT 0x61
11
12#define NMI_REASON_SERR 0x80
13#define NMI_REASON_IOCHK 0x40
14#define NMI_REASON_MASK (NMI_REASON_SERR | NMI_REASON_IOCHK)
15
16#define NMI_REASON_CLEAR_SERR 0x04
17#define NMI_REASON_CLEAR_IOCHK 0x08
18#define NMI_REASON_CLEAR_MASK 0x0f
19
10static inline unsigned char get_nmi_reason(void) 20static inline unsigned char get_nmi_reason(void)
11{ 21{
12 return inb(0x61); 22 return inb(NMI_REASON_PORT);
13} 23}
14 24
15static inline void reassert_nmi(void) 25static inline void reassert_nmi(void)
diff --git a/arch/x86/include/asm/nmi.h b/arch/x86/include/asm/nmi.h
index c4021b953510..c76f5b92b840 100644
--- a/arch/x86/include/asm/nmi.h
+++ b/arch/x86/include/asm/nmi.h
@@ -23,6 +23,26 @@ void arch_trigger_all_cpu_backtrace(void);
23#define arch_trigger_all_cpu_backtrace arch_trigger_all_cpu_backtrace 23#define arch_trigger_all_cpu_backtrace arch_trigger_all_cpu_backtrace
24#endif 24#endif
25 25
26/*
27 * Define some priorities for the nmi notifier call chain.
28 *
29 * Create a local nmi bit that has a higher priority than
30 * external nmis, because the local ones are more frequent.
31 *
32 * Also setup some default high/normal/low settings for
33 * subsystems to registers with. Using 4 bits to seperate
34 * the priorities. This can go alot higher if needed be.
35 */
36
37#define NMI_LOCAL_SHIFT 16 /* randomly picked */
38#define NMI_LOCAL_BIT (1ULL << NMI_LOCAL_SHIFT)
39#define NMI_HIGH_PRIOR (1ULL << 8)
40#define NMI_NORMAL_PRIOR (1ULL << 4)
41#define NMI_LOW_PRIOR (1ULL << 0)
42#define NMI_LOCAL_HIGH_PRIOR (NMI_LOCAL_BIT | NMI_HIGH_PRIOR)
43#define NMI_LOCAL_NORMAL_PRIOR (NMI_LOCAL_BIT | NMI_NORMAL_PRIOR)
44#define NMI_LOCAL_LOW_PRIOR (NMI_LOCAL_BIT | NMI_LOW_PRIOR)
45
26void stop_nmi(void); 46void stop_nmi(void);
27void restart_nmi(void); 47void restart_nmi(void);
28 48
diff --git a/arch/x86/include/asm/numa_64.h b/arch/x86/include/asm/numa_64.h
index 823e070e7c26..5ae87285a502 100644
--- a/arch/x86/include/asm/numa_64.h
+++ b/arch/x86/include/asm/numa_64.h
@@ -38,7 +38,7 @@ extern void __cpuinit numa_add_cpu(int cpu);
38extern void __cpuinit numa_remove_cpu(int cpu); 38extern void __cpuinit numa_remove_cpu(int cpu);
39 39
40#ifdef CONFIG_NUMA_EMU 40#ifdef CONFIG_NUMA_EMU
41#define FAKE_NODE_MIN_SIZE ((u64)64 << 20) 41#define FAKE_NODE_MIN_SIZE ((u64)32 << 20)
42#define FAKE_NODE_MIN_HASH_MASK (~(FAKE_NODE_MIN_SIZE - 1UL)) 42#define FAKE_NODE_MIN_HASH_MASK (~(FAKE_NODE_MIN_SIZE - 1UL))
43#endif /* CONFIG_NUMA_EMU */ 43#endif /* CONFIG_NUMA_EMU */
44#else 44#else
diff --git a/arch/x86/include/asm/perf_event_p4.h b/arch/x86/include/asm/perf_event_p4.h
index 295e2ff18a6a..e2f6a99f14ab 100644
--- a/arch/x86/include/asm/perf_event_p4.h
+++ b/arch/x86/include/asm/perf_event_p4.h
@@ -20,6 +20,9 @@
20#define ARCH_P4_MAX_ESCR (ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR) 20#define ARCH_P4_MAX_ESCR (ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR)
21#define ARCH_P4_MAX_CCCR (18) 21#define ARCH_P4_MAX_CCCR (18)
22 22
23#define ARCH_P4_CNTRVAL_BITS (40)
24#define ARCH_P4_CNTRVAL_MASK ((1ULL << ARCH_P4_CNTRVAL_BITS) - 1)
25
23#define P4_ESCR_EVENT_MASK 0x7e000000U 26#define P4_ESCR_EVENT_MASK 0x7e000000U
24#define P4_ESCR_EVENT_SHIFT 25 27#define P4_ESCR_EVENT_SHIFT 25
25#define P4_ESCR_EVENTMASK_MASK 0x01fffe00U 28#define P4_ESCR_EVENTMASK_MASK 0x01fffe00U
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index affacb5e0065..0a99f7198bc3 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -20,6 +20,13 @@ struct pci_device_id amd_nb_misc_ids[] = {
20}; 20};
21EXPORT_SYMBOL(amd_nb_misc_ids); 21EXPORT_SYMBOL(amd_nb_misc_ids);
22 22
23const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
24 { 0x00, 0x18, 0x20 },
25 { 0xff, 0x00, 0x20 },
26 { 0xfe, 0x00, 0x20 },
27 { }
28};
29
23struct amd_northbridge_info amd_northbridges; 30struct amd_northbridge_info amd_northbridges;
24EXPORT_SYMBOL(amd_northbridges); 31EXPORT_SYMBOL(amd_northbridges);
25 32
diff --git a/arch/x86/kernel/aperture_64.c b/arch/x86/kernel/aperture_64.c
index dcd7c83e1659..5955a7800a96 100644
--- a/arch/x86/kernel/aperture_64.c
+++ b/arch/x86/kernel/aperture_64.c
@@ -39,18 +39,6 @@ int fallback_aper_force __initdata;
39 39
40int fix_aperture __initdata = 1; 40int fix_aperture __initdata = 1;
41 41
42struct bus_dev_range {
43 int bus;
44 int dev_base;
45 int dev_limit;
46};
47
48static struct bus_dev_range bus_dev_ranges[] __initdata = {
49 { 0x00, 0x18, 0x20},
50 { 0xff, 0x00, 0x20},
51 { 0xfe, 0x00, 0x20}
52};
53
54static struct resource gart_resource = { 42static struct resource gart_resource = {
55 .name = "GART", 43 .name = "GART",
56 .flags = IORESOURCE_MEM, 44 .flags = IORESOURCE_MEM,
@@ -294,13 +282,13 @@ void __init early_gart_iommu_check(void)
294 search_agp_bridge(&agp_aper_order, &valid_agp); 282 search_agp_bridge(&agp_aper_order, &valid_agp);
295 283
296 fix = 0; 284 fix = 0;
297 for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) { 285 for (i = 0; amd_nb_bus_dev_ranges[i].dev_limit; i++) {
298 int bus; 286 int bus;
299 int dev_base, dev_limit; 287 int dev_base, dev_limit;
300 288
301 bus = bus_dev_ranges[i].bus; 289 bus = amd_nb_bus_dev_ranges[i].bus;
302 dev_base = bus_dev_ranges[i].dev_base; 290 dev_base = amd_nb_bus_dev_ranges[i].dev_base;
303 dev_limit = bus_dev_ranges[i].dev_limit; 291 dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
304 292
305 for (slot = dev_base; slot < dev_limit; slot++) { 293 for (slot = dev_base; slot < dev_limit; slot++) {
306 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00))) 294 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
@@ -349,13 +337,13 @@ void __init early_gart_iommu_check(void)
349 return; 337 return;
350 338
351 /* disable them all at first */ 339 /* disable them all at first */
352 for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) { 340 for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
353 int bus; 341 int bus;
354 int dev_base, dev_limit; 342 int dev_base, dev_limit;
355 343
356 bus = bus_dev_ranges[i].bus; 344 bus = amd_nb_bus_dev_ranges[i].bus;
357 dev_base = bus_dev_ranges[i].dev_base; 345 dev_base = amd_nb_bus_dev_ranges[i].dev_base;
358 dev_limit = bus_dev_ranges[i].dev_limit; 346 dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
359 347
360 for (slot = dev_base; slot < dev_limit; slot++) { 348 for (slot = dev_base; slot < dev_limit; slot++) {
361 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00))) 349 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
@@ -390,14 +378,14 @@ int __init gart_iommu_hole_init(void)
390 378
391 fix = 0; 379 fix = 0;
392 node = 0; 380 node = 0;
393 for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) { 381 for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
394 int bus; 382 int bus;
395 int dev_base, dev_limit; 383 int dev_base, dev_limit;
396 u32 ctl; 384 u32 ctl;
397 385
398 bus = bus_dev_ranges[i].bus; 386 bus = amd_nb_bus_dev_ranges[i].bus;
399 dev_base = bus_dev_ranges[i].dev_base; 387 dev_base = amd_nb_bus_dev_ranges[i].dev_base;
400 dev_limit = bus_dev_ranges[i].dev_limit; 388 dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
401 389
402 for (slot = dev_base; slot < dev_limit; slot++) { 390 for (slot = dev_base; slot < dev_limit; slot++) {
403 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00))) 391 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
@@ -505,7 +493,7 @@ out:
505 } 493 }
506 494
507 /* Fix up the north bridges */ 495 /* Fix up the north bridges */
508 for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) { 496 for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
509 int bus, dev_base, dev_limit; 497 int bus, dev_base, dev_limit;
510 498
511 /* 499 /*
@@ -514,9 +502,9 @@ out:
514 */ 502 */
515 u32 ctl = DISTLBWALKPRB | aper_order << 1; 503 u32 ctl = DISTLBWALKPRB | aper_order << 1;
516 504
517 bus = bus_dev_ranges[i].bus; 505 bus = amd_nb_bus_dev_ranges[i].bus;
518 dev_base = bus_dev_ranges[i].dev_base; 506 dev_base = amd_nb_bus_dev_ranges[i].dev_base;
519 dev_limit = bus_dev_ranges[i].dev_limit; 507 dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
520 for (slot = dev_base; slot < dev_limit; slot++) { 508 for (slot = dev_base; slot < dev_limit; slot++) {
521 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00))) 509 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
522 continue; 510 continue;
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index a51345ba449e..06c196d7e59c 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -684,7 +684,7 @@ static int __init calibrate_APIC_clock(void)
684 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 684 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
685 lapic_clockevent.shift); 685 lapic_clockevent.shift);
686 lapic_clockevent.max_delta_ns = 686 lapic_clockevent.max_delta_ns =
687 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); 687 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
688 lapic_clockevent.min_delta_ns = 688 lapic_clockevent.min_delta_ns =
689 clockevent_delta2ns(0xF, &lapic_clockevent); 689 clockevent_delta2ns(0xF, &lapic_clockevent);
690 690
diff --git a/arch/x86/kernel/apic/hw_nmi.c b/arch/x86/kernel/apic/hw_nmi.c
index 72ec29e1ae06..79fd43ca6f96 100644
--- a/arch/x86/kernel/apic/hw_nmi.c
+++ b/arch/x86/kernel/apic/hw_nmi.c
@@ -68,7 +68,6 @@ arch_trigger_all_cpu_backtrace_handler(struct notifier_block *self,
68 68
69 switch (cmd) { 69 switch (cmd) {
70 case DIE_NMI: 70 case DIE_NMI:
71 case DIE_NMI_IPI:
72 break; 71 break;
73 72
74 default: 73 default:
@@ -96,7 +95,7 @@ arch_trigger_all_cpu_backtrace_handler(struct notifier_block *self,
96static __read_mostly struct notifier_block backtrace_notifier = { 95static __read_mostly struct notifier_block backtrace_notifier = {
97 .notifier_call = arch_trigger_all_cpu_backtrace_handler, 96 .notifier_call = arch_trigger_all_cpu_backtrace_handler,
98 .next = NULL, 97 .next = NULL,
99 .priority = 1 98 .priority = NMI_LOCAL_LOW_PRIOR,
100}; 99};
101 100
102static int __init register_trigger_all_cpu_backtrace(void) 101static int __init register_trigger_all_cpu_backtrace(void)
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index ecca5f41ad2c..bd16b58b8850 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -378,7 +378,7 @@ struct apic __refdata apic_x2apic_uv_x = {
378 378
379static __cpuinit void set_x2apic_extra_bits(int pnode) 379static __cpuinit void set_x2apic_extra_bits(int pnode)
380{ 380{
381 __this_cpu_write(x2apic_extra_bits, (pnode << 6)); 381 __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
382} 382}
383 383
384/* 384/*
@@ -641,7 +641,7 @@ void __cpuinit uv_cpu_init(void)
641 */ 641 */
642int uv_handle_nmi(struct notifier_block *self, unsigned long reason, void *data) 642int uv_handle_nmi(struct notifier_block *self, unsigned long reason, void *data)
643{ 643{
644 if (reason != DIE_NMI_IPI) 644 if (reason != DIE_NMIUNKNOWN)
645 return NOTIFY_OK; 645 return NOTIFY_OK;
646 646
647 if (in_crash_kexec) 647 if (in_crash_kexec)
diff --git a/arch/x86/kernel/cpu/mcheck/mce-inject.c b/arch/x86/kernel/cpu/mcheck/mce-inject.c
index e7dbde7bfedb..a77971979564 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-inject.c
+++ b/arch/x86/kernel/cpu/mcheck/mce-inject.c
@@ -25,6 +25,7 @@
25#include <linux/gfp.h> 25#include <linux/gfp.h>
26#include <asm/mce.h> 26#include <asm/mce.h>
27#include <asm/apic.h> 27#include <asm/apic.h>
28#include <asm/nmi.h>
28 29
29/* Update fake mce registers on current CPU. */ 30/* Update fake mce registers on current CPU. */
30static void inject_mce(struct mce *m) 31static void inject_mce(struct mce *m)
@@ -83,7 +84,7 @@ static int mce_raise_notify(struct notifier_block *self,
83 struct die_args *args = (struct die_args *)data; 84 struct die_args *args = (struct die_args *)data;
84 int cpu = smp_processor_id(); 85 int cpu = smp_processor_id();
85 struct mce *m = &__get_cpu_var(injectm); 86 struct mce *m = &__get_cpu_var(injectm);
86 if (val != DIE_NMI_IPI || !cpumask_test_cpu(cpu, mce_inject_cpumask)) 87 if (val != DIE_NMI || !cpumask_test_cpu(cpu, mce_inject_cpumask))
87 return NOTIFY_DONE; 88 return NOTIFY_DONE;
88 cpumask_clear_cpu(cpu, mce_inject_cpumask); 89 cpumask_clear_cpu(cpu, mce_inject_cpumask);
89 if (m->inject_flags & MCJ_EXCEPTION) 90 if (m->inject_flags & MCJ_EXCEPTION)
@@ -95,7 +96,7 @@ static int mce_raise_notify(struct notifier_block *self,
95 96
96static struct notifier_block mce_raise_nb = { 97static struct notifier_block mce_raise_nb = {
97 .notifier_call = mce_raise_notify, 98 .notifier_call = mce_raise_notify,
98 .priority = 1000, 99 .priority = NMI_LOCAL_NORMAL_PRIOR,
99}; 100};
100 101
101/* Inject mce on current CPU */ 102/* Inject mce on current CPU */
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index 04921017abe0..9d977a2ea693 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -1267,7 +1267,6 @@ perf_event_nmi_handler(struct notifier_block *self,
1267 1267
1268 switch (cmd) { 1268 switch (cmd) {
1269 case DIE_NMI: 1269 case DIE_NMI:
1270 case DIE_NMI_IPI:
1271 break; 1270 break;
1272 case DIE_NMIUNKNOWN: 1271 case DIE_NMIUNKNOWN:
1273 this_nmi = percpu_read(irq_stat.__nmi_count); 1272 this_nmi = percpu_read(irq_stat.__nmi_count);
@@ -1317,7 +1316,7 @@ perf_event_nmi_handler(struct notifier_block *self,
1317static __read_mostly struct notifier_block perf_event_nmi_notifier = { 1316static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1318 .notifier_call = perf_event_nmi_handler, 1317 .notifier_call = perf_event_nmi_handler,
1319 .next = NULL, 1318 .next = NULL,
1320 .priority = 1 1319 .priority = NMI_LOCAL_LOW_PRIOR,
1321}; 1320};
1322 1321
1323static struct event_constraint unconstrained; 1322static struct event_constraint unconstrained;
diff --git a/arch/x86/kernel/cpu/perf_event_p4.c b/arch/x86/kernel/cpu/perf_event_p4.c
index 81400b93e694..e56b9bfbabd1 100644
--- a/arch/x86/kernel/cpu/perf_event_p4.c
+++ b/arch/x86/kernel/cpu/perf_event_p4.c
@@ -753,19 +753,21 @@ out:
753 753
754static inline int p4_pmu_clear_cccr_ovf(struct hw_perf_event *hwc) 754static inline int p4_pmu_clear_cccr_ovf(struct hw_perf_event *hwc)
755{ 755{
756 int overflow = 0; 756 u64 v;
757 u32 low, high;
758 757
759 rdmsr(hwc->config_base + hwc->idx, low, high); 758 /* an official way for overflow indication */
760 759 rdmsrl(hwc->config_base + hwc->idx, v);
761 /* we need to check high bit for unflagged overflows */ 760 if (v & P4_CCCR_OVF) {
762 if ((low & P4_CCCR_OVF) || !(high & (1 << 31))) { 761 wrmsrl(hwc->config_base + hwc->idx, v & ~P4_CCCR_OVF);
763 overflow = 1; 762 return 1;
764 (void)checking_wrmsrl(hwc->config_base + hwc->idx,
765 ((u64)low) & ~P4_CCCR_OVF);
766 } 763 }
767 764
768 return overflow; 765 /* it might be unflagged overflow */
766 rdmsrl(hwc->event_base + hwc->idx, v);
767 if (!(v & ARCH_P4_CNTRVAL_MASK))
768 return 1;
769
770 return 0;
769} 771}
770 772
771static void p4_pmu_disable_pebs(void) 773static void p4_pmu_disable_pebs(void)
@@ -1152,9 +1154,9 @@ static __initconst const struct x86_pmu p4_pmu = {
1152 */ 1154 */
1153 .num_counters = ARCH_P4_MAX_CCCR, 1155 .num_counters = ARCH_P4_MAX_CCCR,
1154 .apic = 1, 1156 .apic = 1,
1155 .cntval_bits = 40, 1157 .cntval_bits = ARCH_P4_CNTRVAL_BITS,
1156 .cntval_mask = (1ULL << 40) - 1, 1158 .cntval_mask = ARCH_P4_CNTRVAL_MASK,
1157 .max_period = (1ULL << 39) - 1, 1159 .max_period = (1ULL << (ARCH_P4_CNTRVAL_BITS - 1)) - 1,
1158 .hw_config = p4_hw_config, 1160 .hw_config = p4_hw_config,
1159 .schedule_events = p4_pmu_schedule_events, 1161 .schedule_events = p4_pmu_schedule_events,
1160 /* 1162 /*
diff --git a/arch/x86/kernel/dumpstack.c b/arch/x86/kernel/dumpstack.c
index 8474c998cbd4..d6fb146c0d8b 100644
--- a/arch/x86/kernel/dumpstack.c
+++ b/arch/x86/kernel/dumpstack.c
@@ -197,14 +197,8 @@ void show_stack(struct task_struct *task, unsigned long *sp)
197 */ 197 */
198void dump_stack(void) 198void dump_stack(void)
199{ 199{
200 unsigned long bp = 0;
201 unsigned long stack; 200 unsigned long stack;
202 201
203#ifdef CONFIG_FRAME_POINTER
204 if (!bp)
205 get_bp(bp);
206#endif
207
208 printk("Pid: %d, comm: %.20s %s %s %.*s\n", 202 printk("Pid: %d, comm: %.20s %s %s %.*s\n",
209 current->pid, current->comm, print_tainted(), 203 current->pid, current->comm, print_tainted(),
210 init_utsname()->release, 204 init_utsname()->release,
diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S
index e3ba417e8697..d3b895f375d3 100644
--- a/arch/x86/kernel/entry_64.S
+++ b/arch/x86/kernel/entry_64.S
@@ -299,17 +299,21 @@ ENDPROC(native_usergs_sysret64)
299ENTRY(save_args) 299ENTRY(save_args)
300 XCPT_FRAME 300 XCPT_FRAME
301 cld 301 cld
302 movq_cfi rdi, RDI+16-ARGOFFSET 302 /*
303 movq_cfi rsi, RSI+16-ARGOFFSET 303 * start from rbp in pt_regs and jump over
304 movq_cfi rdx, RDX+16-ARGOFFSET 304 * return address.
305 movq_cfi rcx, RCX+16-ARGOFFSET 305 */
306 movq_cfi rax, RAX+16-ARGOFFSET 306 movq_cfi rdi, RDI+8-RBP
307 movq_cfi r8, R8+16-ARGOFFSET 307 movq_cfi rsi, RSI+8-RBP
308 movq_cfi r9, R9+16-ARGOFFSET 308 movq_cfi rdx, RDX+8-RBP
309 movq_cfi r10, R10+16-ARGOFFSET 309 movq_cfi rcx, RCX+8-RBP
310 movq_cfi r11, R11+16-ARGOFFSET 310 movq_cfi rax, RAX+8-RBP
311 311 movq_cfi r8, R8+8-RBP
312 leaq -ARGOFFSET+16(%rsp),%rdi /* arg1 for handler */ 312 movq_cfi r9, R9+8-RBP
313 movq_cfi r10, R10+8-RBP
314 movq_cfi r11, R11+8-RBP
315
316 leaq -RBP+8(%rsp),%rdi /* arg1 for handler */
313 movq_cfi rbp, 8 /* push %rbp */ 317 movq_cfi rbp, 8 /* push %rbp */
314 leaq 8(%rsp), %rbp /* mov %rsp, %ebp */ 318 leaq 8(%rsp), %rbp /* mov %rsp, %ebp */
315 testl $3, CS(%rdi) 319 testl $3, CS(%rdi)
@@ -782,8 +786,9 @@ END(interrupt)
782 786
783/* 0(%rsp): ~(interrupt number) */ 787/* 0(%rsp): ~(interrupt number) */
784 .macro interrupt func 788 .macro interrupt func
785 subq $ORIG_RAX-ARGOFFSET+8, %rsp 789 /* reserve pt_regs for scratch regs and rbp */
786 CFI_ADJUST_CFA_OFFSET ORIG_RAX-ARGOFFSET+8 790 subq $ORIG_RAX-RBP, %rsp
791 CFI_ADJUST_CFA_OFFSET ORIG_RAX-RBP
787 call save_args 792 call save_args
788 PARTIAL_FRAME 0 793 PARTIAL_FRAME 0
789 call \func 794 call \func
@@ -808,9 +813,14 @@ ret_from_intr:
808 TRACE_IRQS_OFF 813 TRACE_IRQS_OFF
809 decl PER_CPU_VAR(irq_count) 814 decl PER_CPU_VAR(irq_count)
810 leaveq 815 leaveq
816
811 CFI_RESTORE rbp 817 CFI_RESTORE rbp
812 CFI_DEF_CFA_REGISTER rsp 818 CFI_DEF_CFA_REGISTER rsp
813 CFI_ADJUST_CFA_OFFSET -8 819 CFI_ADJUST_CFA_OFFSET -8
820
821 /* we did not save rbx, restore only from ARGOFFSET */
822 addq $8, %rsp
823 CFI_ADJUST_CFA_OFFSET -8
814exit_intr: 824exit_intr:
815 GET_THREAD_INFO(%rcx) 825 GET_THREAD_INFO(%rcx)
816 testl $3,CS-ARGOFFSET(%rsp) 826 testl $3,CS-ARGOFFSET(%rsp)
diff --git a/arch/x86/kernel/kgdb.c b/arch/x86/kernel/kgdb.c
index cd21b654dec6..a4130005028a 100644
--- a/arch/x86/kernel/kgdb.c
+++ b/arch/x86/kernel/kgdb.c
@@ -48,6 +48,7 @@
48#include <asm/apicdef.h> 48#include <asm/apicdef.h>
49#include <asm/system.h> 49#include <asm/system.h>
50#include <asm/apic.h> 50#include <asm/apic.h>
51#include <asm/nmi.h>
51 52
52struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] = 53struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] =
53{ 54{
@@ -525,10 +526,6 @@ static int __kgdb_notify(struct die_args *args, unsigned long cmd)
525 } 526 }
526 return NOTIFY_DONE; 527 return NOTIFY_DONE;
527 528
528 case DIE_NMI_IPI:
529 /* Just ignore, we will handle the roundup on DIE_NMI. */
530 return NOTIFY_DONE;
531
532 case DIE_NMIUNKNOWN: 529 case DIE_NMIUNKNOWN:
533 if (was_in_debug_nmi[raw_smp_processor_id()]) { 530 if (was_in_debug_nmi[raw_smp_processor_id()]) {
534 was_in_debug_nmi[raw_smp_processor_id()] = 0; 531 was_in_debug_nmi[raw_smp_processor_id()] = 0;
@@ -606,7 +603,7 @@ static struct notifier_block kgdb_notifier = {
606 /* 603 /*
607 * Lowest-prio notifier priority, we want to be notified last: 604 * Lowest-prio notifier priority, we want to be notified last:
608 */ 605 */
609 .priority = -INT_MAX, 606 .priority = NMI_LOCAL_LOW_PRIOR,
610}; 607};
611 608
612/** 609/**
diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c
index c495aa8d4815..fc7aae1e2bc7 100644
--- a/arch/x86/kernel/reboot.c
+++ b/arch/x86/kernel/reboot.c
@@ -18,6 +18,7 @@
18#include <asm/pci_x86.h> 18#include <asm/pci_x86.h>
19#include <asm/virtext.h> 19#include <asm/virtext.h>
20#include <asm/cpu.h> 20#include <asm/cpu.h>
21#include <asm/nmi.h>
21 22
22#ifdef CONFIG_X86_32 23#ifdef CONFIG_X86_32
23# include <linux/ctype.h> 24# include <linux/ctype.h>
@@ -747,7 +748,7 @@ static int crash_nmi_callback(struct notifier_block *self,
747{ 748{
748 int cpu; 749 int cpu;
749 750
750 if (val != DIE_NMI_IPI) 751 if (val != DIE_NMI)
751 return NOTIFY_OK; 752 return NOTIFY_OK;
752 753
753 cpu = raw_smp_processor_id(); 754 cpu = raw_smp_processor_id();
@@ -778,6 +779,8 @@ static void smp_send_nmi_allbutself(void)
778 779
779static struct notifier_block crash_nmi_nb = { 780static struct notifier_block crash_nmi_nb = {
780 .notifier_call = crash_nmi_callback, 781 .notifier_call = crash_nmi_callback,
782 /* we want to be the first one called */
783 .priority = NMI_LOCAL_HIGH_PRIOR+1,
781}; 784};
782 785
783/* Halt all other CPUs, calling the specified function on each of them 786/* Halt all other CPUs, calling the specified function on each of them
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index c7149c96d079..763df77343dd 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -97,12 +97,12 @@ static DEFINE_PER_CPU(struct task_struct *, idle_thread_array);
97 */ 97 */
98static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex); 98static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex);
99 99
100void cpu_hotplug_driver_lock() 100void cpu_hotplug_driver_lock(void)
101{ 101{
102 mutex_lock(&x86_cpu_hotplug_driver_mutex); 102 mutex_lock(&x86_cpu_hotplug_driver_mutex);
103} 103}
104 104
105void cpu_hotplug_driver_unlock() 105void cpu_hotplug_driver_unlock(void)
106{ 106{
107 mutex_unlock(&x86_cpu_hotplug_driver_mutex); 107 mutex_unlock(&x86_cpu_hotplug_driver_mutex);
108} 108}
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
index c76aaca5694d..b9b67166f9de 100644
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -84,6 +84,11 @@ EXPORT_SYMBOL_GPL(used_vectors);
84static int ignore_nmis; 84static int ignore_nmis;
85 85
86int unknown_nmi_panic; 86int unknown_nmi_panic;
87/*
88 * Prevent NMI reason port (0x61) being accessed simultaneously, can
89 * only be used in NMI handler.
90 */
91static DEFINE_RAW_SPINLOCK(nmi_reason_lock);
87 92
88static inline void conditional_sti(struct pt_regs *regs) 93static inline void conditional_sti(struct pt_regs *regs)
89{ 94{
@@ -310,15 +315,15 @@ static int __init setup_unknown_nmi_panic(char *str)
310__setup("unknown_nmi_panic", setup_unknown_nmi_panic); 315__setup("unknown_nmi_panic", setup_unknown_nmi_panic);
311 316
312static notrace __kprobes void 317static notrace __kprobes void
313mem_parity_error(unsigned char reason, struct pt_regs *regs) 318pci_serr_error(unsigned char reason, struct pt_regs *regs)
314{ 319{
315 printk(KERN_EMERG 320 pr_emerg("NMI: PCI system error (SERR) for reason %02x on CPU %d.\n",
316 "Uhhuh. NMI received for unknown reason %02x on CPU %d.\n", 321 reason, smp_processor_id());
317 reason, smp_processor_id());
318
319 printk(KERN_EMERG
320 "You have some hardware problem, likely on the PCI bus.\n");
321 322
323 /*
324 * On some machines, PCI SERR line is used to report memory
325 * errors. EDAC makes use of it.
326 */
322#if defined(CONFIG_EDAC) 327#if defined(CONFIG_EDAC)
323 if (edac_handler_set()) { 328 if (edac_handler_set()) {
324 edac_atomic_assert_error(); 329 edac_atomic_assert_error();
@@ -329,11 +334,11 @@ mem_parity_error(unsigned char reason, struct pt_regs *regs)
329 if (panic_on_unrecovered_nmi) 334 if (panic_on_unrecovered_nmi)
330 panic("NMI: Not continuing"); 335 panic("NMI: Not continuing");
331 336
332 printk(KERN_EMERG "Dazed and confused, but trying to continue\n"); 337 pr_emerg("Dazed and confused, but trying to continue\n");
333 338
334 /* Clear and disable the memory parity error line. */ 339 /* Clear and disable the PCI SERR error line. */
335 reason = (reason & 0xf) | 4; 340 reason = (reason & NMI_REASON_CLEAR_MASK) | NMI_REASON_CLEAR_SERR;
336 outb(reason, 0x61); 341 outb(reason, NMI_REASON_PORT);
337} 342}
338 343
339static notrace __kprobes void 344static notrace __kprobes void
@@ -341,15 +346,17 @@ io_check_error(unsigned char reason, struct pt_regs *regs)
341{ 346{
342 unsigned long i; 347 unsigned long i;
343 348
344 printk(KERN_EMERG "NMI: IOCK error (debug interrupt?)\n"); 349 pr_emerg(
350 "NMI: IOCK error (debug interrupt?) for reason %02x on CPU %d.\n",
351 reason, smp_processor_id());
345 show_registers(regs); 352 show_registers(regs);
346 353
347 if (panic_on_io_nmi) 354 if (panic_on_io_nmi)
348 panic("NMI IOCK error: Not continuing"); 355 panic("NMI IOCK error: Not continuing");
349 356
350 /* Re-enable the IOCK line, wait for a few seconds */ 357 /* Re-enable the IOCK line, wait for a few seconds */
351 reason = (reason & 0xf) | 8; 358 reason = (reason & NMI_REASON_CLEAR_MASK) | NMI_REASON_CLEAR_IOCHK;
352 outb(reason, 0x61); 359 outb(reason, NMI_REASON_PORT);
353 360
354 i = 20000; 361 i = 20000;
355 while (--i) { 362 while (--i) {
@@ -357,8 +364,8 @@ io_check_error(unsigned char reason, struct pt_regs *regs)
357 udelay(100); 364 udelay(100);
358 } 365 }
359 366
360 reason &= ~8; 367 reason &= ~NMI_REASON_CLEAR_IOCHK;
361 outb(reason, 0x61); 368 outb(reason, NMI_REASON_PORT);
362} 369}
363 370
364static notrace __kprobes void 371static notrace __kprobes void
@@ -377,57 +384,50 @@ unknown_nmi_error(unsigned char reason, struct pt_regs *regs)
377 return; 384 return;
378 } 385 }
379#endif 386#endif
380 printk(KERN_EMERG 387 pr_emerg("Uhhuh. NMI received for unknown reason %02x on CPU %d.\n",
381 "Uhhuh. NMI received for unknown reason %02x on CPU %d.\n", 388 reason, smp_processor_id());
382 reason, smp_processor_id());
383 389
384 printk(KERN_EMERG "Do you have a strange power saving mode enabled?\n"); 390 pr_emerg("Do you have a strange power saving mode enabled?\n");
385 if (unknown_nmi_panic || panic_on_unrecovered_nmi) 391 if (unknown_nmi_panic || panic_on_unrecovered_nmi)
386 panic("NMI: Not continuing"); 392 panic("NMI: Not continuing");
387 393
388 printk(KERN_EMERG "Dazed and confused, but trying to continue\n"); 394 pr_emerg("Dazed and confused, but trying to continue\n");
389} 395}
390 396
391static notrace __kprobes void default_do_nmi(struct pt_regs *regs) 397static notrace __kprobes void default_do_nmi(struct pt_regs *regs)
392{ 398{
393 unsigned char reason = 0; 399 unsigned char reason = 0;
394 int cpu;
395 400
396 cpu = smp_processor_id(); 401 /*
397 402 * CPU-specific NMI must be processed before non-CPU-specific
398 /* Only the BSP gets external NMIs from the system. */ 403 * NMI, otherwise we may lose it, because the CPU-specific
399 if (!cpu) 404 * NMI can not be detected/processed on other CPUs.
400 reason = get_nmi_reason(); 405 */
406 if (notify_die(DIE_NMI, "nmi", regs, 0, 2, SIGINT) == NOTIFY_STOP)
407 return;
401 408
402 if (!(reason & 0xc0)) { 409 /* Non-CPU-specific NMI: NMI sources can be processed on any CPU */
403 if (notify_die(DIE_NMI_IPI, "nmi_ipi", regs, reason, 2, SIGINT) 410 raw_spin_lock(&nmi_reason_lock);
404 == NOTIFY_STOP) 411 reason = get_nmi_reason();
405 return;
406 412
407#ifdef CONFIG_X86_LOCAL_APIC 413 if (reason & NMI_REASON_MASK) {
408 if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT) 414 if (reason & NMI_REASON_SERR)
409 == NOTIFY_STOP) 415 pci_serr_error(reason, regs);
410 return; 416 else if (reason & NMI_REASON_IOCHK)
417 io_check_error(reason, regs);
418#ifdef CONFIG_X86_32
419 /*
420 * Reassert NMI in case it became active
421 * meanwhile as it's edge-triggered:
422 */
423 reassert_nmi();
411#endif 424#endif
412 unknown_nmi_error(reason, regs); 425 raw_spin_unlock(&nmi_reason_lock);
413
414 return; 426 return;
415 } 427 }
416 if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT) == NOTIFY_STOP) 428 raw_spin_unlock(&nmi_reason_lock);
417 return;
418 429
419 /* AK: following checks seem to be broken on modern chipsets. FIXME */ 430 unknown_nmi_error(reason, regs);
420 if (reason & 0x80)
421 mem_parity_error(reason, regs);
422 if (reason & 0x40)
423 io_check_error(reason, regs);
424#ifdef CONFIG_X86_32
425 /*
426 * Reassert NMI in case it became active meanwhile
427 * as it's edge-triggered:
428 */
429 reassert_nmi();
430#endif
431} 431}
432 432
433dotraplinkage notrace __kprobes void 433dotraplinkage notrace __kprobes void
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 03d2ea82f35a..823f79a17ad1 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -965,7 +965,7 @@ out:
965 965
966static int __init init_tsc_clocksource(void) 966static int __init init_tsc_clocksource(void)
967{ 967{
968 if (!cpu_has_tsc || tsc_disabled > 0) 968 if (!cpu_has_tsc || tsc_disabled > 0 || !tsc_khz)
969 return 0; 969 return 0;
970 970
971 if (tsc_clocksource_reliable) 971 if (tsc_clocksource_reliable)
diff --git a/arch/x86/mm/amdtopology_64.c b/arch/x86/mm/amdtopology_64.c
index 08a0069b87a5..f21962c435ed 100644
--- a/arch/x86/mm/amdtopology_64.c
+++ b/arch/x86/mm/amdtopology_64.c
@@ -27,6 +27,7 @@
27#include <asm/amd_nb.h> 27#include <asm/amd_nb.h>
28 28
29static struct bootnode __initdata nodes[8]; 29static struct bootnode __initdata nodes[8];
30static unsigned char __initdata nodeids[8];
30static nodemask_t __initdata nodes_parsed = NODE_MASK_NONE; 31static nodemask_t __initdata nodes_parsed = NODE_MASK_NONE;
31 32
32static __init int find_northbridge(void) 33static __init int find_northbridge(void)
@@ -68,19 +69,6 @@ static __init void early_get_boot_cpu_id(void)
68#endif 69#endif
69} 70}
70 71
71int __init amd_get_nodes(struct bootnode *physnodes)
72{
73 int i;
74 int ret = 0;
75
76 for_each_node_mask(i, nodes_parsed) {
77 physnodes[ret].start = nodes[i].start;
78 physnodes[ret].end = nodes[i].end;
79 ret++;
80 }
81 return ret;
82}
83
84int __init amd_numa_init(unsigned long start_pfn, unsigned long end_pfn) 72int __init amd_numa_init(unsigned long start_pfn, unsigned long end_pfn)
85{ 73{
86 unsigned long start = PFN_PHYS(start_pfn); 74 unsigned long start = PFN_PHYS(start_pfn);
@@ -113,7 +101,7 @@ int __init amd_numa_init(unsigned long start_pfn, unsigned long end_pfn)
113 base = read_pci_config(0, nb, 1, 0x40 + i*8); 101 base = read_pci_config(0, nb, 1, 0x40 + i*8);
114 limit = read_pci_config(0, nb, 1, 0x44 + i*8); 102 limit = read_pci_config(0, nb, 1, 0x44 + i*8);
115 103
116 nodeid = limit & 7; 104 nodeids[i] = nodeid = limit & 7;
117 if ((base & 3) == 0) { 105 if ((base & 3) == 0) {
118 if (i < numnodes) 106 if (i < numnodes)
119 pr_info("Skipping disabled node %d\n", i); 107 pr_info("Skipping disabled node %d\n", i);
@@ -193,6 +181,76 @@ int __init amd_numa_init(unsigned long start_pfn, unsigned long end_pfn)
193 return 0; 181 return 0;
194} 182}
195 183
184#ifdef CONFIG_NUMA_EMU
185static s16 fake_apicid_to_node[MAX_LOCAL_APIC] __initdata = {
186 [0 ... MAX_LOCAL_APIC-1] = NUMA_NO_NODE
187};
188
189void __init amd_get_nodes(struct bootnode *physnodes)
190{
191 int i;
192
193 for_each_node_mask(i, nodes_parsed) {
194 physnodes[i].start = nodes[i].start;
195 physnodes[i].end = nodes[i].end;
196 }
197}
198
199static int __init find_node_by_addr(unsigned long addr)
200{
201 int ret = NUMA_NO_NODE;
202 int i;
203
204 for (i = 0; i < 8; i++)
205 if (addr >= nodes[i].start && addr < nodes[i].end) {
206 ret = i;
207 break;
208 }
209 return ret;
210}
211
212/*
213 * For NUMA emulation, fake proximity domain (_PXM) to node id mappings must be
214 * setup to represent the physical topology but reflect the emulated
215 * environment. For each emulated node, the real node which it appears on is
216 * found and a fake pxm to nid mapping is created which mirrors the actual
217 * locality. node_distance() then represents the correct distances between
218 * emulated nodes by using the fake acpi mappings to pxms.
219 */
220void __init amd_fake_nodes(const struct bootnode *nodes, int nr_nodes)
221{
222 unsigned int bits;
223 unsigned int cores;
224 unsigned int apicid_base = 0;
225 int i;
226
227 bits = boot_cpu_data.x86_coreid_bits;
228 cores = 1 << bits;
229 early_get_boot_cpu_id();
230 if (boot_cpu_physical_apicid > 0)
231 apicid_base = boot_cpu_physical_apicid;
232
233 for (i = 0; i < nr_nodes; i++) {
234 int index;
235 int nid;
236 int j;
237
238 nid = find_node_by_addr(nodes[i].start);
239 if (nid == NUMA_NO_NODE)
240 continue;
241
242 index = nodeids[nid] << bits;
243 if (fake_apicid_to_node[index + apicid_base] == NUMA_NO_NODE)
244 for (j = apicid_base; j < cores + apicid_base; j++)
245 fake_apicid_to_node[index + j] = i;
246#ifdef CONFIG_ACPI_NUMA
247 __acpi_map_pxm_to_node(nid, i);
248#endif
249 }
250 memcpy(apicid_to_node, fake_apicid_to_node, sizeof(apicid_to_node));
251}
252#endif /* CONFIG_NUMA_EMU */
253
196int __init amd_scan_nodes(void) 254int __init amd_scan_nodes(void)
197{ 255{
198 unsigned int bits; 256 unsigned int bits;
diff --git a/arch/x86/mm/numa_64.c b/arch/x86/mm/numa_64.c
index 7762a517d69d..1e72102e80c9 100644
--- a/arch/x86/mm/numa_64.c
+++ b/arch/x86/mm/numa_64.c
@@ -260,30 +260,30 @@ void __init numa_init_array(void)
260#ifdef CONFIG_NUMA_EMU 260#ifdef CONFIG_NUMA_EMU
261/* Numa emulation */ 261/* Numa emulation */
262static struct bootnode nodes[MAX_NUMNODES] __initdata; 262static struct bootnode nodes[MAX_NUMNODES] __initdata;
263static struct bootnode physnodes[MAX_NUMNODES] __initdata; 263static struct bootnode physnodes[MAX_NUMNODES] __cpuinitdata;
264static char *cmdline __initdata; 264static char *cmdline __initdata;
265 265
266static int __init setup_physnodes(unsigned long start, unsigned long end, 266static int __init setup_physnodes(unsigned long start, unsigned long end,
267 int acpi, int amd) 267 int acpi, int amd)
268{ 268{
269 int nr_nodes = 0;
270 int ret = 0; 269 int ret = 0;
271 int i; 270 int i;
272 271
272 memset(physnodes, 0, sizeof(physnodes));
273#ifdef CONFIG_ACPI_NUMA 273#ifdef CONFIG_ACPI_NUMA
274 if (acpi) 274 if (acpi)
275 nr_nodes = acpi_get_nodes(physnodes); 275 acpi_get_nodes(physnodes, start, end);
276#endif 276#endif
277#ifdef CONFIG_AMD_NUMA 277#ifdef CONFIG_AMD_NUMA
278 if (amd) 278 if (amd)
279 nr_nodes = amd_get_nodes(physnodes); 279 amd_get_nodes(physnodes);
280#endif 280#endif
281 /* 281 /*
282 * Basic sanity checking on the physical node map: there may be errors 282 * Basic sanity checking on the physical node map: there may be errors
283 * if the SRAT or AMD code incorrectly reported the topology or the mem= 283 * if the SRAT or AMD code incorrectly reported the topology or the mem=
284 * kernel parameter is used. 284 * kernel parameter is used.
285 */ 285 */
286 for (i = 0; i < nr_nodes; i++) { 286 for (i = 0; i < MAX_NUMNODES; i++) {
287 if (physnodes[i].start == physnodes[i].end) 287 if (physnodes[i].start == physnodes[i].end)
288 continue; 288 continue;
289 if (physnodes[i].start > end) { 289 if (physnodes[i].start > end) {
@@ -298,17 +298,6 @@ static int __init setup_physnodes(unsigned long start, unsigned long end,
298 physnodes[i].start = start; 298 physnodes[i].start = start;
299 if (physnodes[i].end > end) 299 if (physnodes[i].end > end)
300 physnodes[i].end = end; 300 physnodes[i].end = end;
301 }
302
303 /*
304 * Remove all nodes that have no memory or were truncated because of the
305 * limited address range.
306 */
307 for (i = 0; i < nr_nodes; i++) {
308 if (physnodes[i].start == physnodes[i].end)
309 continue;
310 physnodes[ret].start = physnodes[i].start;
311 physnodes[ret].end = physnodes[i].end;
312 ret++; 301 ret++;
313 } 302 }
314 303
@@ -324,6 +313,24 @@ static int __init setup_physnodes(unsigned long start, unsigned long end,
324 return ret; 313 return ret;
325} 314}
326 315
316static void __init fake_physnodes(int acpi, int amd, int nr_nodes)
317{
318 int i;
319
320 BUG_ON(acpi && amd);
321#ifdef CONFIG_ACPI_NUMA
322 if (acpi)
323 acpi_fake_nodes(nodes, nr_nodes);
324#endif
325#ifdef CONFIG_AMD_NUMA
326 if (amd)
327 amd_fake_nodes(nodes, nr_nodes);
328#endif
329 if (!acpi && !amd)
330 for (i = 0; i < nr_cpu_ids; i++)
331 numa_set_node(i, 0);
332}
333
327/* 334/*
328 * Setups up nid to range from addr to addr + size. If the end 335 * Setups up nid to range from addr to addr + size. If the end
329 * boundary is greater than max_addr, then max_addr is used instead. 336 * boundary is greater than max_addr, then max_addr is used instead.
@@ -352,8 +359,7 @@ static int __init setup_node_range(int nid, u64 *addr, u64 size, u64 max_addr)
352 * Sets up nr_nodes fake nodes interleaved over physical nodes ranging from addr 359 * Sets up nr_nodes fake nodes interleaved over physical nodes ranging from addr
353 * to max_addr. The return value is the number of nodes allocated. 360 * to max_addr. The return value is the number of nodes allocated.
354 */ 361 */
355static int __init split_nodes_interleave(u64 addr, u64 max_addr, 362static int __init split_nodes_interleave(u64 addr, u64 max_addr, int nr_nodes)
356 int nr_phys_nodes, int nr_nodes)
357{ 363{
358 nodemask_t physnode_mask = NODE_MASK_NONE; 364 nodemask_t physnode_mask = NODE_MASK_NONE;
359 u64 size; 365 u64 size;
@@ -384,7 +390,7 @@ static int __init split_nodes_interleave(u64 addr, u64 max_addr,
384 return -1; 390 return -1;
385 } 391 }
386 392
387 for (i = 0; i < nr_phys_nodes; i++) 393 for (i = 0; i < MAX_NUMNODES; i++)
388 if (physnodes[i].start != physnodes[i].end) 394 if (physnodes[i].start != physnodes[i].end)
389 node_set(i, physnode_mask); 395 node_set(i, physnode_mask);
390 396
@@ -553,11 +559,9 @@ static int __init numa_emulation(unsigned long start_pfn,
553{ 559{
554 u64 addr = start_pfn << PAGE_SHIFT; 560 u64 addr = start_pfn << PAGE_SHIFT;
555 u64 max_addr = last_pfn << PAGE_SHIFT; 561 u64 max_addr = last_pfn << PAGE_SHIFT;
556 int num_phys_nodes;
557 int num_nodes; 562 int num_nodes;
558 int i; 563 int i;
559 564
560 num_phys_nodes = setup_physnodes(addr, max_addr, acpi, amd);
561 /* 565 /*
562 * If the numa=fake command-line contains a 'M' or 'G', it represents 566 * If the numa=fake command-line contains a 'M' or 'G', it represents
563 * the fixed node size. Otherwise, if it is just a single number N, 567 * the fixed node size. Otherwise, if it is just a single number N,
@@ -572,7 +576,7 @@ static int __init numa_emulation(unsigned long start_pfn,
572 unsigned long n; 576 unsigned long n;
573 577
574 n = simple_strtoul(cmdline, NULL, 0); 578 n = simple_strtoul(cmdline, NULL, 0);
575 num_nodes = split_nodes_interleave(addr, max_addr, num_phys_nodes, n); 579 num_nodes = split_nodes_interleave(addr, max_addr, n);
576 } 580 }
577 581
578 if (num_nodes < 0) 582 if (num_nodes < 0)
@@ -595,7 +599,8 @@ static int __init numa_emulation(unsigned long start_pfn,
595 nodes[i].end >> PAGE_SHIFT); 599 nodes[i].end >> PAGE_SHIFT);
596 setup_node_bootmem(i, nodes[i].start, nodes[i].end); 600 setup_node_bootmem(i, nodes[i].start, nodes[i].end);
597 } 601 }
598 acpi_fake_nodes(nodes, num_nodes); 602 setup_physnodes(addr, max_addr, acpi, amd);
603 fake_physnodes(acpi, amd, num_nodes);
599 numa_init_array(); 604 numa_init_array();
600 return 0; 605 return 0;
601} 606}
@@ -610,8 +615,12 @@ void __init initmem_init(unsigned long start_pfn, unsigned long last_pfn,
610 nodes_clear(node_online_map); 615 nodes_clear(node_online_map);
611 616
612#ifdef CONFIG_NUMA_EMU 617#ifdef CONFIG_NUMA_EMU
618 setup_physnodes(start_pfn << PAGE_SHIFT, last_pfn << PAGE_SHIFT,
619 acpi, amd);
613 if (cmdline && !numa_emulation(start_pfn, last_pfn, acpi, amd)) 620 if (cmdline && !numa_emulation(start_pfn, last_pfn, acpi, amd))
614 return; 621 return;
622 setup_physnodes(start_pfn << PAGE_SHIFT, last_pfn << PAGE_SHIFT,
623 acpi, amd);
615 nodes_clear(node_possible_map); 624 nodes_clear(node_possible_map);
616 nodes_clear(node_online_map); 625 nodes_clear(node_online_map);
617#endif 626#endif
@@ -767,6 +776,7 @@ void __cpuinit numa_clear_node(int cpu)
767 776
768#ifndef CONFIG_DEBUG_PER_CPU_MAPS 777#ifndef CONFIG_DEBUG_PER_CPU_MAPS
769 778
779#ifndef CONFIG_NUMA_EMU
770void __cpuinit numa_add_cpu(int cpu) 780void __cpuinit numa_add_cpu(int cpu)
771{ 781{
772 cpumask_set_cpu(cpu, node_to_cpumask_map[early_cpu_to_node(cpu)]); 782 cpumask_set_cpu(cpu, node_to_cpumask_map[early_cpu_to_node(cpu)]);
@@ -776,34 +786,115 @@ void __cpuinit numa_remove_cpu(int cpu)
776{ 786{
777 cpumask_clear_cpu(cpu, node_to_cpumask_map[early_cpu_to_node(cpu)]); 787 cpumask_clear_cpu(cpu, node_to_cpumask_map[early_cpu_to_node(cpu)]);
778} 788}
789#else
790void __cpuinit numa_add_cpu(int cpu)
791{
792 unsigned long addr;
793 u16 apicid;
794 int physnid;
795 int nid = NUMA_NO_NODE;
796
797 apicid = early_per_cpu(x86_cpu_to_apicid, cpu);
798 if (apicid != BAD_APICID)
799 nid = apicid_to_node[apicid];
800 if (nid == NUMA_NO_NODE)
801 nid = early_cpu_to_node(cpu);
802 BUG_ON(nid == NUMA_NO_NODE || !node_online(nid));
803
804 /*
805 * Use the starting address of the emulated node to find which physical
806 * node it is allocated on.
807 */
808 addr = node_start_pfn(nid) << PAGE_SHIFT;
809 for (physnid = 0; physnid < MAX_NUMNODES; physnid++)
810 if (addr >= physnodes[physnid].start &&
811 addr < physnodes[physnid].end)
812 break;
813
814 /*
815 * Map the cpu to each emulated node that is allocated on the physical
816 * node of the cpu's apic id.
817 */
818 for_each_online_node(nid) {
819 addr = node_start_pfn(nid) << PAGE_SHIFT;
820 if (addr >= physnodes[physnid].start &&
821 addr < physnodes[physnid].end)
822 cpumask_set_cpu(cpu, node_to_cpumask_map[nid]);
823 }
824}
825
826void __cpuinit numa_remove_cpu(int cpu)
827{
828 int i;
829
830 for_each_online_node(i)
831 cpumask_clear_cpu(cpu, node_to_cpumask_map[i]);
832}
833#endif /* !CONFIG_NUMA_EMU */
779 834
780#else /* CONFIG_DEBUG_PER_CPU_MAPS */ 835#else /* CONFIG_DEBUG_PER_CPU_MAPS */
836static struct cpumask __cpuinit *debug_cpumask_set_cpu(int cpu, int enable)
837{
838 int node = early_cpu_to_node(cpu);
839 struct cpumask *mask;
840 char buf[64];
841
842 mask = node_to_cpumask_map[node];
843 if (!mask) {
844 pr_err("node_to_cpumask_map[%i] NULL\n", node);
845 dump_stack();
846 return NULL;
847 }
848
849 cpulist_scnprintf(buf, sizeof(buf), mask);
850 printk(KERN_DEBUG "%s cpu %d node %d: mask now %s\n",
851 enable ? "numa_add_cpu" : "numa_remove_cpu",
852 cpu, node, buf);
853 return mask;
854}
781 855
782/* 856/*
783 * --------- debug versions of the numa functions --------- 857 * --------- debug versions of the numa functions ---------
784 */ 858 */
859#ifndef CONFIG_NUMA_EMU
785static void __cpuinit numa_set_cpumask(int cpu, int enable) 860static void __cpuinit numa_set_cpumask(int cpu, int enable)
786{ 861{
787 int node = early_cpu_to_node(cpu);
788 struct cpumask *mask; 862 struct cpumask *mask;
789 char buf[64];
790 863
791 mask = node_to_cpumask_map[node]; 864 mask = debug_cpumask_set_cpu(cpu, enable);
792 if (mask == NULL) { 865 if (!mask)
793 printk(KERN_ERR "node_to_cpumask_map[%i] NULL\n", node);
794 dump_stack();
795 return; 866 return;
796 }
797 867
798 if (enable) 868 if (enable)
799 cpumask_set_cpu(cpu, mask); 869 cpumask_set_cpu(cpu, mask);
800 else 870 else
801 cpumask_clear_cpu(cpu, mask); 871 cpumask_clear_cpu(cpu, mask);
872}
873#else
874static void __cpuinit numa_set_cpumask(int cpu, int enable)
875{
876 int node = early_cpu_to_node(cpu);
877 struct cpumask *mask;
878 int i;
802 879
803 cpulist_scnprintf(buf, sizeof(buf), mask); 880 for_each_online_node(i) {
804 printk(KERN_DEBUG "%s cpu %d node %d: mask now %s\n", 881 unsigned long addr;
805 enable ? "numa_add_cpu" : "numa_remove_cpu", cpu, node, buf); 882
883 addr = node_start_pfn(i) << PAGE_SHIFT;
884 if (addr < physnodes[node].start ||
885 addr >= physnodes[node].end)
886 continue;
887 mask = debug_cpumask_set_cpu(cpu, enable);
888 if (!mask)
889 return;
890
891 if (enable)
892 cpumask_set_cpu(cpu, mask);
893 else
894 cpumask_clear_cpu(cpu, mask);
895 }
806} 896}
897#endif /* CONFIG_NUMA_EMU */
807 898
808void __cpuinit numa_add_cpu(int cpu) 899void __cpuinit numa_add_cpu(int cpu)
809{ 900{
diff --git a/arch/x86/mm/srat_64.c b/arch/x86/mm/srat_64.c
index 171a0aacb99a..603d285d1daa 100644
--- a/arch/x86/mm/srat_64.c
+++ b/arch/x86/mm/srat_64.c
@@ -349,18 +349,19 @@ static int __init nodes_cover_memory(const struct bootnode *nodes)
349 349
350void __init acpi_numa_arch_fixup(void) {} 350void __init acpi_numa_arch_fixup(void) {}
351 351
352int __init acpi_get_nodes(struct bootnode *physnodes) 352#ifdef CONFIG_NUMA_EMU
353void __init acpi_get_nodes(struct bootnode *physnodes, unsigned long start,
354 unsigned long end)
353{ 355{
354 int i; 356 int i;
355 int ret = 0;
356 357
357 for_each_node_mask(i, nodes_parsed) { 358 for_each_node_mask(i, nodes_parsed) {
358 physnodes[ret].start = nodes[i].start; 359 cutoff_node(i, start, end);
359 physnodes[ret].end = nodes[i].end; 360 physnodes[i].start = nodes[i].start;
360 ret++; 361 physnodes[i].end = nodes[i].end;
361 } 362 }
362 return ret;
363} 363}
364#endif /* CONFIG_NUMA_EMU */
364 365
365/* Use the information discovered above to actually set up the nodes. */ 366/* Use the information discovered above to actually set up the nodes. */
366int __init acpi_scan_nodes(unsigned long start, unsigned long end) 367int __init acpi_scan_nodes(unsigned long start, unsigned long end)
@@ -505,8 +506,6 @@ void __init acpi_fake_nodes(const struct bootnode *fake_nodes, int num_nodes)
505{ 506{
506 int i, j; 507 int i, j;
507 508
508 printk(KERN_INFO "Faking PXM affinity for fake nodes on real "
509 "topology.\n");
510 for (i = 0; i < num_nodes; i++) { 509 for (i = 0; i < num_nodes; i++) {
511 int nid, pxm; 510 int nid, pxm;
512 511
@@ -526,6 +525,17 @@ void __init acpi_fake_nodes(const struct bootnode *fake_nodes, int num_nodes)
526 fake_apicid_to_node[j] == NUMA_NO_NODE) 525 fake_apicid_to_node[j] == NUMA_NO_NODE)
527 fake_apicid_to_node[j] = i; 526 fake_apicid_to_node[j] = i;
528 } 527 }
528
529 /*
530 * If there are apicid-to-node mappings for physical nodes that do not
531 * have a corresponding emulated node, it should default to a guaranteed
532 * value.
533 */
534 for (i = 0; i < MAX_LOCAL_APIC; i++)
535 if (apicid_to_node[i] != NUMA_NO_NODE &&
536 fake_apicid_to_node[i] == NUMA_NO_NODE)
537 fake_apicid_to_node[i] = 0;
538
529 for (i = 0; i < num_nodes; i++) 539 for (i = 0; i < num_nodes; i++)
530 __acpi_map_pxm_to_node(fake_node_to_pxm_map[i], i); 540 __acpi_map_pxm_to_node(fake_node_to_pxm_map[i], i);
531 memcpy(apicid_to_node, fake_apicid_to_node, sizeof(apicid_to_node)); 541 memcpy(apicid_to_node, fake_apicid_to_node, sizeof(apicid_to_node));
diff --git a/arch/x86/oprofile/nmi_int.c b/arch/x86/oprofile/nmi_int.c
index f24a8533bcdf..e2b7b0c06cdf 100644
--- a/arch/x86/oprofile/nmi_int.c
+++ b/arch/x86/oprofile/nmi_int.c
@@ -65,7 +65,6 @@ static int profile_exceptions_notify(struct notifier_block *self,
65 65
66 switch (val) { 66 switch (val) {
67 case DIE_NMI: 67 case DIE_NMI:
68 case DIE_NMI_IPI:
69 if (ctr_running) 68 if (ctr_running)
70 model->check_ctrs(args->regs, &__get_cpu_var(cpu_msrs)); 69 model->check_ctrs(args->regs, &__get_cpu_var(cpu_msrs));
71 else if (!nmi_enabled) 70 else if (!nmi_enabled)
@@ -361,7 +360,7 @@ static void nmi_cpu_setup(void *dummy)
361static struct notifier_block profile_exceptions_nb = { 360static struct notifier_block profile_exceptions_nb = {
362 .notifier_call = profile_exceptions_notify, 361 .notifier_call = profile_exceptions_notify,
363 .next = NULL, 362 .next = NULL,
364 .priority = 2 363 .priority = NMI_LOCAL_LOW_PRIOR,
365}; 364};
366 365
367static void nmi_cpu_restore_registers(struct op_msrs *msrs) 366static void nmi_cpu_restore_registers(struct op_msrs *msrs)
diff --git a/arch/x86/oprofile/nmi_timer_int.c b/arch/x86/oprofile/nmi_timer_int.c
index 0636dd93cef8..720bf5a53c51 100644
--- a/arch/x86/oprofile/nmi_timer_int.c
+++ b/arch/x86/oprofile/nmi_timer_int.c
@@ -38,7 +38,7 @@ static int profile_timer_exceptions_notify(struct notifier_block *self,
38static struct notifier_block profile_timer_exceptions_nb = { 38static struct notifier_block profile_timer_exceptions_nb = {
39 .notifier_call = profile_timer_exceptions_notify, 39 .notifier_call = profile_timer_exceptions_notify,
40 .next = NULL, 40 .next = NULL,
41 .priority = 0 41 .priority = NMI_LOW_PRIOR,
42}; 42};
43 43
44static int timer_start(void) 44static int timer_start(void)
diff --git a/arch/x86/pci/amd_bus.c b/arch/x86/pci/amd_bus.c
index fc1e8fe07e5c..e27dffbbb1a7 100644
--- a/arch/x86/pci/amd_bus.c
+++ b/arch/x86/pci/amd_bus.c
@@ -4,6 +4,7 @@
4#include <linux/cpu.h> 4#include <linux/cpu.h>
5#include <linux/range.h> 5#include <linux/range.h>
6 6
7#include <asm/amd_nb.h>
7#include <asm/pci_x86.h> 8#include <asm/pci_x86.h>
8 9
9#include <asm/pci-direct.h> 10#include <asm/pci-direct.h>
@@ -378,6 +379,34 @@ static struct notifier_block __cpuinitdata amd_cpu_notifier = {
378 .notifier_call = amd_cpu_notify, 379 .notifier_call = amd_cpu_notify,
379}; 380};
380 381
382static void __init pci_enable_pci_io_ecs(void)
383{
384#ifdef CONFIG_AMD_NB
385 unsigned int i, n;
386
387 for (n = i = 0; !n && amd_nb_bus_dev_ranges[i].dev_limit; ++i) {
388 u8 bus = amd_nb_bus_dev_ranges[i].bus;
389 u8 slot = amd_nb_bus_dev_ranges[i].dev_base;
390 u8 limit = amd_nb_bus_dev_ranges[i].dev_limit;
391
392 for (; slot < limit; ++slot) {
393 u32 val = read_pci_config(bus, slot, 3, 0);
394
395 if (!early_is_amd_nb(val))
396 continue;
397
398 val = read_pci_config(bus, slot, 3, 0x8c);
399 if (!(val & (ENABLE_CF8_EXT_CFG >> 32))) {
400 val |= ENABLE_CF8_EXT_CFG >> 32;
401 write_pci_config(bus, slot, 3, 0x8c, val);
402 }
403 ++n;
404 }
405 }
406 pr_info("Extended Config Space enabled on %u nodes\n", n);
407#endif
408}
409
381static int __init pci_io_ecs_init(void) 410static int __init pci_io_ecs_init(void)
382{ 411{
383 int cpu; 412 int cpu;
@@ -386,6 +415,10 @@ static int __init pci_io_ecs_init(void)
386 if (boot_cpu_data.x86 < 0x10) 415 if (boot_cpu_data.x86 < 0x10)
387 return 0; 416 return 0;
388 417
418 /* Try the PCI method first. */
419 if (early_pci_allowed())
420 pci_enable_pci_io_ecs();
421
389 register_cpu_notifier(&amd_cpu_notifier); 422 register_cpu_notifier(&amd_cpu_notifier);
390 for_each_online_cpu(cpu) 423 for_each_online_cpu(cpu)
391 amd_cpu_notify(&amd_cpu_notifier, (unsigned long)CPU_ONLINE, 424 amd_cpu_notify(&amd_cpu_notifier, (unsigned long)CPU_ONLINE,