diff options
author | David Daney <ddaney@caviumnetworks.com> | 2010-01-22 17:41:14 -0500 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2010-02-27 06:53:12 -0500 |
commit | 2a880986d899f556f5a327bc77cc8760d5bb9c64 (patch) | |
tree | 179032b7895ca3594c3fec96a194178ffecf4ad6 /arch | |
parent | f868ba29723be46e0981226d7455090d515b08ef (diff) |
MIPS: Remove probe_tlb().
The function probe_tlb() only does anything for processors that are
not PRID_COMP_LEGACY. This is precisely the set of processors for
which decode_configs() is called to do identical tlbsize probing
calculations. Therefore probe_tlb() is completely redundant and may
be removed.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/865/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/mips/mm/tlb-r4k.c | 31 |
1 files changed, 0 insertions, 31 deletions
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index d73428b18b0a..45b7c35950c4 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c | |||
@@ -447,34 +447,6 @@ out: | |||
447 | return ret; | 447 | return ret; |
448 | } | 448 | } |
449 | 449 | ||
450 | static void __cpuinit probe_tlb(unsigned long config) | ||
451 | { | ||
452 | struct cpuinfo_mips *c = ¤t_cpu_data; | ||
453 | unsigned int reg; | ||
454 | |||
455 | /* | ||
456 | * If this isn't a MIPS32 / MIPS64 compliant CPU. Config 1 register | ||
457 | * is not supported, we assume R4k style. Cpu probing already figured | ||
458 | * out the number of tlb entries. | ||
459 | */ | ||
460 | if ((c->processor_id & 0xff0000) == PRID_COMP_LEGACY) | ||
461 | return; | ||
462 | #ifdef CONFIG_MIPS_MT_SMTC | ||
463 | /* | ||
464 | * If TLB is shared in SMTC system, total size already | ||
465 | * has been calculated and written into cpu_data tlbsize | ||
466 | */ | ||
467 | if((smtc_status & SMTC_TLB_SHARED) == SMTC_TLB_SHARED) | ||
468 | return; | ||
469 | #endif /* CONFIG_MIPS_MT_SMTC */ | ||
470 | |||
471 | reg = read_c0_config1(); | ||
472 | if (!((config >> 7) & 3)) | ||
473 | panic("No TLB present"); | ||
474 | |||
475 | c->tlbsize = ((reg >> 25) & 0x3f) + 1; | ||
476 | } | ||
477 | |||
478 | static int __cpuinitdata ntlb; | 450 | static int __cpuinitdata ntlb; |
479 | static int __init set_ntlb(char *str) | 451 | static int __init set_ntlb(char *str) |
480 | { | 452 | { |
@@ -486,8 +458,6 @@ __setup("ntlb=", set_ntlb); | |||
486 | 458 | ||
487 | void __cpuinit tlb_init(void) | 459 | void __cpuinit tlb_init(void) |
488 | { | 460 | { |
489 | unsigned int config = read_c0_config(); | ||
490 | |||
491 | /* | 461 | /* |
492 | * You should never change this register: | 462 | * You should never change this register: |
493 | * - On R4600 1.7 the tlbp never hits for pages smaller than | 463 | * - On R4600 1.7 the tlbp never hits for pages smaller than |
@@ -495,7 +465,6 @@ void __cpuinit tlb_init(void) | |||
495 | * - The entire mm handling assumes the c0_pagemask register to | 465 | * - The entire mm handling assumes the c0_pagemask register to |
496 | * be set to fixed-size pages. | 466 | * be set to fixed-size pages. |
497 | */ | 467 | */ |
498 | probe_tlb(config); | ||
499 | write_c0_pagemask(PM_DEFAULT_MASK); | 468 | write_c0_pagemask(PM_DEFAULT_MASK); |
500 | write_c0_wired(0); | 469 | write_c0_wired(0); |
501 | if (current_cpu_type() == CPU_R10000 || | 470 | if (current_cpu_type() == CPU_R10000 || |