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authorDavid Daney <ddaney@caviumnetworks.com>2010-01-22 17:41:15 -0500
committerRalf Baechle <ralf@linux-mips.org>2010-02-27 06:53:13 -0500
commit1b362e3e350f72c6cb4b3346f6ba92a529082a09 (patch)
treede172b4853b1aaa6684e5b7afed679c88d8ab655 /arch
parent2a880986d899f556f5a327bc77cc8760d5bb9c64 (diff)
MIPS: Decode c0_config4 for large TLBs.
For processors that have more than 64 TLBs, we need to decode both config1 and config4 to determine the total number TLBs. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/866/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/include/asm/mipsregs.h4
-rw-r--r--arch/mips/kernel/cpu-probe.c15
2 files changed, 19 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index f4ab3139d737..edda1daf742f 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -576,6 +576,10 @@
576#define MIPS_CONF3_DSP (_ULCAST_(1) << 10) 576#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
577#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) 577#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
578 578
579#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
580#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
581#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
582
579#define MIPS_CONF7_WII (_ULCAST_(1) << 31) 583#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
580 584
581#define MIPS_CONF7_RPS (_ULCAST_(1) << 2) 585#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 758ad426c57f..323395081b2a 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -700,6 +700,19 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
700 return config3 & MIPS_CONF_M; 700 return config3 & MIPS_CONF_M;
701} 701}
702 702
703static inline unsigned int decode_config4(struct cpuinfo_mips *c)
704{
705 unsigned int config4;
706
707 config4 = read_c0_config4();
708
709 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
710 && cpu_has_tlb)
711 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
712
713 return config4 & MIPS_CONF_M;
714}
715
703static void __cpuinit decode_configs(struct cpuinfo_mips *c) 716static void __cpuinit decode_configs(struct cpuinfo_mips *c)
704{ 717{
705 int ok; 718 int ok;
@@ -718,6 +731,8 @@ static void __cpuinit decode_configs(struct cpuinfo_mips *c)
718 ok = decode_config2(c); 731 ok = decode_config2(c);
719 if (ok) 732 if (ok)
720 ok = decode_config3(c); 733 ok = decode_config3(c);
734 if (ok)
735 ok = decode_config4(c);
721 736
722 mips_probe_watch_registers(c); 737 mips_probe_watch_registers(c);
723} 738}