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authorLinus Torvalds <torvalds@g5.osdl.org>2005-09-27 16:33:25 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2005-09-27 16:33:25 -0400
commit95001ee9256df846e374f116c92ca8e0beec1527 (patch)
treeef682e01be51423592d19c5c9425363ef3881ca7 /arch
parent63906e41fe70fe8a376c5887429448272a0ee7d4 (diff)
parent0dc461069879b45a2d5333bd16990f8080a318fd (diff)
Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6
Diffstat (limited to 'arch')
-rw-r--r--arch/sparc64/Kconfig.debug8
-rw-r--r--arch/sparc64/kernel/devices.c22
-rw-r--r--arch/sparc64/kernel/dtlb_backend.S13
-rw-r--r--arch/sparc64/kernel/dtlb_base.S8
-rw-r--r--arch/sparc64/kernel/entry.S180
-rw-r--r--arch/sparc64/kernel/head.S556
-rw-r--r--arch/sparc64/kernel/ktlb.S198
-rw-r--r--arch/sparc64/kernel/pci_schizo.c2
-rw-r--r--arch/sparc64/kernel/setup.c31
-rw-r--r--arch/sparc64/kernel/smp.c21
-rw-r--r--arch/sparc64/kernel/trampoline.S16
-rw-r--r--arch/sparc64/kernel/traps.c40
-rw-r--r--arch/sparc64/kernel/vmlinux.lds.S3
-rw-r--r--arch/sparc64/mm/init.c664
-rw-r--r--arch/sparc64/mm/ultra.S96
-rw-r--r--arch/sparc64/prom/Makefile2
-rw-r--r--arch/sparc64/prom/console.c2
-rw-r--r--arch/sparc64/prom/devops.c2
-rw-r--r--arch/sparc64/prom/init.c2
-rw-r--r--arch/sparc64/prom/map.S72
-rw-r--r--arch/sparc64/prom/misc.c34
-rw-r--r--arch/sparc64/prom/p1275.c2
-rw-r--r--arch/sparc64/prom/printf.c2
-rw-r--r--arch/sparc64/prom/tree.c50
24 files changed, 856 insertions, 1170 deletions
diff --git a/arch/sparc64/Kconfig.debug b/arch/sparc64/Kconfig.debug
index af0e9411b83e..fa06ea04837b 100644
--- a/arch/sparc64/Kconfig.debug
+++ b/arch/sparc64/Kconfig.debug
@@ -33,6 +33,14 @@ config DEBUG_BOOTMEM
33 depends on DEBUG_KERNEL 33 depends on DEBUG_KERNEL
34 bool "Debug BOOTMEM initialization" 34 bool "Debug BOOTMEM initialization"
35 35
36config DEBUG_PAGEALLOC
37 bool "Page alloc debugging"
38 depends on DEBUG_KERNEL && !SOFTWARE_SUSPEND
39 help
40 Unmap pages from the kernel linear mapping after free_pages().
41 This results in a large slowdown, but helps to find certain types
42 of memory corruptions.
43
36config MCOUNT 44config MCOUNT
37 bool 45 bool
38 depends on STACK_DEBUG 46 depends on STACK_DEBUG
diff --git a/arch/sparc64/kernel/devices.c b/arch/sparc64/kernel/devices.c
index d710274e516b..df9a1ca8fd77 100644
--- a/arch/sparc64/kernel/devices.c
+++ b/arch/sparc64/kernel/devices.c
@@ -135,6 +135,28 @@ void __init device_scan(void)
135 cpu_data(0).clock_tick = prom_getintdefault(cpu_node, 135 cpu_data(0).clock_tick = prom_getintdefault(cpu_node,
136 "clock-frequency", 136 "clock-frequency",
137 0); 137 0);
138 cpu_data(0).dcache_size = prom_getintdefault(cpu_node,
139 "dcache-size",
140 16 * 1024);
141 cpu_data(0).dcache_line_size =
142 prom_getintdefault(cpu_node, "dcache-line-size", 32);
143 cpu_data(0).icache_size = prom_getintdefault(cpu_node,
144 "icache-size",
145 16 * 1024);
146 cpu_data(0).icache_line_size =
147 prom_getintdefault(cpu_node, "icache-line-size", 32);
148 cpu_data(0).ecache_size = prom_getintdefault(cpu_node,
149 "ecache-size",
150 4 * 1024 * 1024);
151 cpu_data(0).ecache_line_size =
152 prom_getintdefault(cpu_node, "ecache-line-size", 64);
153 printk("CPU[0]: Caches "
154 "D[sz(%d):line_sz(%d)] "
155 "I[sz(%d):line_sz(%d)] "
156 "E[sz(%d):line_sz(%d)]\n",
157 cpu_data(0).dcache_size, cpu_data(0).dcache_line_size,
158 cpu_data(0).icache_size, cpu_data(0).icache_line_size,
159 cpu_data(0).ecache_size, cpu_data(0).ecache_line_size);
138 } 160 }
139#endif 161#endif
140 162
diff --git a/arch/sparc64/kernel/dtlb_backend.S b/arch/sparc64/kernel/dtlb_backend.S
index 538522848ad4..acc889a7f9c1 100644
--- a/arch/sparc64/kernel/dtlb_backend.S
+++ b/arch/sparc64/kernel/dtlb_backend.S
@@ -9,17 +9,7 @@
9#include <asm/pgtable.h> 9#include <asm/pgtable.h>
10#include <asm/mmu.h> 10#include <asm/mmu.h>
11 11
12#if PAGE_SHIFT == 13 12#define VALID_SZ_BITS (_PAGE_VALID | _PAGE_SZBITS)
13#define SZ_BITS _PAGE_SZ8K
14#elif PAGE_SHIFT == 16
15#define SZ_BITS _PAGE_SZ64K
16#elif PAGE_SHIFT == 19
17#define SZ_BITS _PAGE_SZ512K
18#elif PAGE_SHIFT == 22
19#define SZ_BITS _PAGE_SZ4MB
20#endif
21
22#define VALID_SZ_BITS (_PAGE_VALID | SZ_BITS)
23 13
24#define VPTE_BITS (_PAGE_CP | _PAGE_CV | _PAGE_P ) 14#define VPTE_BITS (_PAGE_CP | _PAGE_CV | _PAGE_P )
25#define VPTE_SHIFT (PAGE_SHIFT - 3) 15#define VPTE_SHIFT (PAGE_SHIFT - 3)
@@ -163,7 +153,6 @@ sparc64_vpte_continue:
163 stxa %g4, [%g1 + %g1] ASI_DMMU ! Restore previous TAG_ACCESS 153 stxa %g4, [%g1 + %g1] ASI_DMMU ! Restore previous TAG_ACCESS
164 retry ! Load PTE once again 154 retry ! Load PTE once again
165 155
166#undef SZ_BITS
167#undef VALID_SZ_BITS 156#undef VALID_SZ_BITS
168#undef VPTE_SHIFT 157#undef VPTE_SHIFT
169#undef VPTE_BITS 158#undef VPTE_BITS
diff --git a/arch/sparc64/kernel/dtlb_base.S b/arch/sparc64/kernel/dtlb_base.S
index ded2fed23fcc..702d349c1e88 100644
--- a/arch/sparc64/kernel/dtlb_base.S
+++ b/arch/sparc64/kernel/dtlb_base.S
@@ -71,7 +71,7 @@
71from_tl1_trap: 71from_tl1_trap:
72 rdpr %tl, %g5 ! For TL==3 test 72 rdpr %tl, %g5 ! For TL==3 test
73 CREATE_VPTE_OFFSET1(%g4, %g6) ! Create VPTE offset 73 CREATE_VPTE_OFFSET1(%g4, %g6) ! Create VPTE offset
74 be,pn %xcc, 3f ! Yep, special processing 74 be,pn %xcc, kvmap ! Yep, special processing
75 CREATE_VPTE_OFFSET2(%g4, %g6) ! Create VPTE offset 75 CREATE_VPTE_OFFSET2(%g4, %g6) ! Create VPTE offset
76 cmp %g5, 4 ! Last trap level? 76 cmp %g5, 4 ! Last trap level?
77 be,pn %xcc, longpath ! Yep, cannot risk VPTE miss 77 be,pn %xcc, longpath ! Yep, cannot risk VPTE miss
@@ -83,9 +83,9 @@ from_tl1_trap:
83 nop ! Delay-slot 83 nop ! Delay-slot
849: stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB 849: stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB
85 retry ! Trap return 85 retry ! Trap return
863: brlz,pt %g4, 9b ! Kernel virtual map? 86 nop
87 xor %g2, %g4, %g5 ! Finish bit twiddles 87 nop
88 ba,a,pt %xcc, kvmap ! Yep, go check for obp/vmalloc 88 nop
89 89
90/* DTLB ** ICACHE line 3: winfixups+real_faults */ 90/* DTLB ** ICACHE line 3: winfixups+real_faults */
91longpath: 91longpath:
diff --git a/arch/sparc64/kernel/entry.S b/arch/sparc64/kernel/entry.S
index b48349527853..2879b1072921 100644
--- a/arch/sparc64/kernel/entry.S
+++ b/arch/sparc64/kernel/entry.S
@@ -30,159 +30,6 @@
30 .text 30 .text
31 .align 32 31 .align 32
32 32
33 .globl sparc64_vpte_patchme1
34 .globl sparc64_vpte_patchme2
35/*
36 * On a second level vpte miss, check whether the original fault is to the OBP
37 * range (note that this is only possible for instruction miss, data misses to
38 * obp range do not use vpte). If so, go back directly to the faulting address.
39 * This is because we want to read the tpc, otherwise we have no way of knowing
40 * the 8k aligned faulting address if we are using >8k kernel pagesize. This
41 * also ensures no vpte range addresses are dropped into tlb while obp is
42 * executing (see inherit_locked_prom_mappings() rant).
43 */
44sparc64_vpte_nucleus:
45 /* Note that kvmap below has verified that the address is
46 * in the range MODULES_VADDR --> VMALLOC_END already. So
47 * here we need only check if it is an OBP address or not.
48 */
49 sethi %hi(LOW_OBP_ADDRESS), %g5
50 cmp %g4, %g5
51 blu,pn %xcc, sparc64_vpte_patchme1
52 mov 0x1, %g5
53 sllx %g5, 32, %g5
54 cmp %g4, %g5
55 blu,pn %xcc, obp_iaddr_patch
56 nop
57
58 /* These two instructions are patched by paginig_init(). */
59sparc64_vpte_patchme1:
60 sethi %hi(0), %g5
61sparc64_vpte_patchme2:
62 or %g5, %lo(0), %g5
63
64 /* With kernel PGD in %g5, branch back into dtlb_backend. */
65 ba,pt %xcc, sparc64_kpte_continue
66 andn %g1, 0x3, %g1 /* Finish PMD offset adjustment. */
67
68vpte_noent:
69 /* Restore previous TAG_ACCESS, %g5 is zero, and we will
70 * skip over the trap instruction so that the top level
71 * TLB miss handler will thing this %g5 value is just an
72 * invalid PTE, thus branching to full fault processing.
73 */
74 mov TLB_SFSR, %g1
75 stxa %g4, [%g1 + %g1] ASI_DMMU
76 done
77
78 .globl obp_iaddr_patch
79obp_iaddr_patch:
80 /* These two instructions patched by inherit_prom_mappings(). */
81 sethi %hi(0), %g5
82 or %g5, %lo(0), %g5
83
84 /* Behave as if we are at TL0. */
85 wrpr %g0, 1, %tl
86 rdpr %tpc, %g4 /* Find original faulting iaddr */
87 srlx %g4, 13, %g4 /* Throw out context bits */
88 sllx %g4, 13, %g4 /* g4 has vpn + ctx0 now */
89
90 /* Restore previous TAG_ACCESS. */
91 mov TLB_SFSR, %g1
92 stxa %g4, [%g1 + %g1] ASI_IMMU
93
94 /* Get PMD offset. */
95 srlx %g4, 23, %g6
96 and %g6, 0x7ff, %g6
97 sllx %g6, 2, %g6
98
99 /* Load PMD, is it valid? */
100 lduwa [%g5 + %g6] ASI_PHYS_USE_EC, %g5
101 brz,pn %g5, longpath
102 sllx %g5, 11, %g5
103
104 /* Get PTE offset. */
105 srlx %g4, 13, %g6
106 and %g6, 0x3ff, %g6
107 sllx %g6, 3, %g6
108
109 /* Load PTE. */
110 ldxa [%g5 + %g6] ASI_PHYS_USE_EC, %g5
111 brgez,pn %g5, longpath
112 nop
113
114 /* TLB load and return from trap. */
115 stxa %g5, [%g0] ASI_ITLB_DATA_IN
116 retry
117
118 .globl obp_daddr_patch
119obp_daddr_patch:
120 /* These two instructions patched by inherit_prom_mappings(). */
121 sethi %hi(0), %g5
122 or %g5, %lo(0), %g5
123
124 /* Get PMD offset. */
125 srlx %g4, 23, %g6
126 and %g6, 0x7ff, %g6
127 sllx %g6, 2, %g6
128
129 /* Load PMD, is it valid? */
130 lduwa [%g5 + %g6] ASI_PHYS_USE_EC, %g5
131 brz,pn %g5, longpath
132 sllx %g5, 11, %g5
133
134 /* Get PTE offset. */
135 srlx %g4, 13, %g6
136 and %g6, 0x3ff, %g6
137 sllx %g6, 3, %g6
138
139 /* Load PTE. */
140 ldxa [%g5 + %g6] ASI_PHYS_USE_EC, %g5
141 brgez,pn %g5, longpath
142 nop
143
144 /* TLB load and return from trap. */
145 stxa %g5, [%g0] ASI_DTLB_DATA_IN
146 retry
147
148/*
149 * On a first level data miss, check whether this is to the OBP range (note
150 * that such accesses can be made by prom, as well as by kernel using
151 * prom_getproperty on "address"), and if so, do not use vpte access ...
152 * rather, use information saved during inherit_prom_mappings() using 8k
153 * pagesize.
154 */
155 .align 32
156kvmap:
157 sethi %hi(MODULES_VADDR), %g5
158 cmp %g4, %g5
159 blu,pn %xcc, longpath
160 mov (VMALLOC_END >> 24), %g5
161 sllx %g5, 24, %g5
162 cmp %g4, %g5
163 bgeu,pn %xcc, longpath
164 nop
165
166kvmap_check_obp:
167 sethi %hi(LOW_OBP_ADDRESS), %g5
168 cmp %g4, %g5
169 blu,pn %xcc, kvmap_vmalloc_addr
170 mov 0x1, %g5
171 sllx %g5, 32, %g5
172 cmp %g4, %g5
173 blu,pn %xcc, obp_daddr_patch
174 nop
175
176kvmap_vmalloc_addr:
177 /* If we get here, a vmalloc addr was accessed, load kernel VPTE. */
178 ldxa [%g3 + %g6] ASI_N, %g5
179 brgez,pn %g5, longpath
180 nop
181
182 /* PTE is valid, load into TLB and return from trap. */
183 stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB
184 retry
185
186 /* This is trivial with the new code... */ 33 /* This is trivial with the new code... */
187 .globl do_fpdis 34 .globl do_fpdis
188do_fpdis: 35do_fpdis:
@@ -525,14 +372,13 @@ cheetah_plus_patch_fpdis:
525 * 372 *
526 * DATA 0: [low 32-bits] Address of function to call, jmp to this 373 * DATA 0: [low 32-bits] Address of function to call, jmp to this
527 * [high 32-bits] MMU Context Argument 0, place in %g5 374 * [high 32-bits] MMU Context Argument 0, place in %g5
528 * DATA 1: Address Argument 1, place in %g6 375 * DATA 1: Address Argument 1, place in %g1
529 * DATA 2: Address Argument 2, place in %g7 376 * DATA 2: Address Argument 2, place in %g7
530 * 377 *
531 * With this method we can do most of the cross-call tlb/cache 378 * With this method we can do most of the cross-call tlb/cache
532 * flushing very quickly. 379 * flushing very quickly.
533 * 380 *
534 * Current CPU's IRQ worklist table is locked into %g1, 381 * Current CPU's IRQ worklist table is locked into %g6, don't touch.
535 * don't touch.
536 */ 382 */
537 .text 383 .text
538 .align 32 384 .align 32
@@ -1006,13 +852,14 @@ cheetah_plus_dcpe_trap_vector:
1006 nop 852 nop
1007 853
1008do_cheetah_plus_data_parity: 854do_cheetah_plus_data_parity:
1009 ba,pt %xcc, etrap 855 rdpr %pil, %g2
856 wrpr %g0, 15, %pil
857 ba,pt %xcc, etrap_irq
1010 rd %pc, %g7 858 rd %pc, %g7
1011 mov 0x0, %o0 859 mov 0x0, %o0
1012 call cheetah_plus_parity_error 860 call cheetah_plus_parity_error
1013 add %sp, PTREGS_OFF, %o1 861 add %sp, PTREGS_OFF, %o1
1014 ba,pt %xcc, rtrap 862 ba,a,pt %xcc, rtrap_irq
1015 clr %l6
1016 863
1017cheetah_plus_dcpe_trap_vector_tl1: 864cheetah_plus_dcpe_trap_vector_tl1:
1018 membar #Sync 865 membar #Sync
@@ -1036,13 +883,14 @@ cheetah_plus_icpe_trap_vector:
1036 nop 883 nop
1037 884
1038do_cheetah_plus_insn_parity: 885do_cheetah_plus_insn_parity:
1039 ba,pt %xcc, etrap 886 rdpr %pil, %g2
887 wrpr %g0, 15, %pil
888 ba,pt %xcc, etrap_irq
1040 rd %pc, %g7 889 rd %pc, %g7
1041 mov 0x1, %o0 890 mov 0x1, %o0
1042 call cheetah_plus_parity_error 891 call cheetah_plus_parity_error
1043 add %sp, PTREGS_OFF, %o1 892 add %sp, PTREGS_OFF, %o1
1044 ba,pt %xcc, rtrap 893 ba,a,pt %xcc, rtrap_irq
1045 clr %l6
1046 894
1047cheetah_plus_icpe_trap_vector_tl1: 895cheetah_plus_icpe_trap_vector_tl1:
1048 membar #Sync 896 membar #Sync
@@ -1075,6 +923,10 @@ do_dcpe_tl1:
1075 nop 923 nop
1076 wrpr %g1, %tl ! Restore original trap level 924 wrpr %g1, %tl ! Restore original trap level
1077do_dcpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */ 925do_dcpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
926 sethi %hi(dcache_parity_tl1_occurred), %g2
927 lduw [%g2 + %lo(dcache_parity_tl1_occurred)], %g1
928 add %g1, 1, %g1
929 stw %g1, [%g2 + %lo(dcache_parity_tl1_occurred)]
1078 /* Reset D-cache parity */ 930 /* Reset D-cache parity */
1079 sethi %hi(1 << 16), %g1 ! D-cache size 931 sethi %hi(1 << 16), %g1 ! D-cache size
1080 mov (1 << 5), %g2 ! D-cache line size 932 mov (1 << 5), %g2 ! D-cache line size
@@ -1121,6 +973,10 @@ do_icpe_tl1:
1121 nop 973 nop
1122 wrpr %g1, %tl ! Restore original trap level 974 wrpr %g1, %tl ! Restore original trap level
1123do_icpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */ 975do_icpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
976 sethi %hi(icache_parity_tl1_occurred), %g2
977 lduw [%g2 + %lo(icache_parity_tl1_occurred)], %g1
978 add %g1, 1, %g1
979 stw %g1, [%g2 + %lo(icache_parity_tl1_occurred)]
1124 /* Flush I-cache */ 980 /* Flush I-cache */
1125 sethi %hi(1 << 15), %g1 ! I-cache size 981 sethi %hi(1 << 15), %g1 ! I-cache size
1126 mov (1 << 5), %g2 ! I-cache line size 982 mov (1 << 5), %g2 ! I-cache line size
diff --git a/arch/sparc64/kernel/head.S b/arch/sparc64/kernel/head.S
index 1fa06c4e3bdb..ecc748fb9ad7 100644
--- a/arch/sparc64/kernel/head.S
+++ b/arch/sparc64/kernel/head.S
@@ -80,15 +80,165 @@ sparc_ramdisk_image64:
80 .xword 0 80 .xword 0
81 .word _end 81 .word _end
82 82
83 /* We must be careful, 32-bit OpenBOOT will get confused if it 83 /* PROM cif handler code address is in %o4. */
84 * tries to save away a register window to a 64-bit kernel 84sparc64_boot:
85 * stack address. Flush all windows, disable interrupts, 851: rd %pc, %g7
86 * remap if necessary, jump onto kernel trap table, then kernel 86 set 1b, %g1
87 * stack, or else we die. 87 cmp %g1, %g7
88 be,pn %xcc, sparc64_boot_after_remap
89 mov %o4, %l7
90
91 /* We need to remap the kernel. Use position independant
92 * code to remap us to KERNBASE.
88 * 93 *
89 * PROM entry point is on %o4 94 * SILO can invoke us with 32-bit address masking enabled,
95 * so make sure that's clear.
90 */ 96 */
91sparc64_boot: 97 rdpr %pstate, %g1
98 andn %g1, PSTATE_AM, %g1
99 wrpr %g1, 0x0, %pstate
100 ba,a,pt %xcc, 1f
101
102 .globl prom_finddev_name, prom_chosen_path
103 .globl prom_getprop_name, prom_mmu_name
104 .globl prom_callmethod_name, prom_translate_name
105 .globl prom_map_name, prom_unmap_name, prom_mmu_ihandle_cache
106 .globl prom_boot_mapped_pc, prom_boot_mapping_mode
107 .globl prom_boot_mapping_phys_high, prom_boot_mapping_phys_low
108prom_finddev_name:
109 .asciz "finddevice"
110prom_chosen_path:
111 .asciz "/chosen"
112prom_getprop_name:
113 .asciz "getprop"
114prom_mmu_name:
115 .asciz "mmu"
116prom_callmethod_name:
117 .asciz "call-method"
118prom_translate_name:
119 .asciz "translate"
120prom_map_name:
121 .asciz "map"
122prom_unmap_name:
123 .asciz "unmap"
124 .align 4
125prom_mmu_ihandle_cache:
126 .word 0
127prom_boot_mapped_pc:
128 .word 0
129prom_boot_mapping_mode:
130 .word 0
131 .align 8
132prom_boot_mapping_phys_high:
133 .xword 0
134prom_boot_mapping_phys_low:
135 .xword 0
1361:
137 rd %pc, %l0
138 mov (1b - prom_finddev_name), %l1
139 mov (1b - prom_chosen_path), %l2
140 mov (1b - prom_boot_mapped_pc), %l3
141 sub %l0, %l1, %l1
142 sub %l0, %l2, %l2
143 sub %l0, %l3, %l3
144 stw %l0, [%l3]
145 sub %sp, (192 + 128), %sp
146
147 /* chosen_node = prom_finddevice("/chosen") */
148 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "finddevice"
149 mov 1, %l3
150 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
151 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
152 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/chosen"
153 stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
154 call %l7
155 add %sp, (2047 + 128), %o0 ! argument array
156
157 ldx [%sp + 2047 + 128 + 0x20], %l4 ! chosen device node
158
159 mov (1b - prom_getprop_name), %l1
160 mov (1b - prom_mmu_name), %l2
161 mov (1b - prom_mmu_ihandle_cache), %l5
162 sub %l0, %l1, %l1
163 sub %l0, %l2, %l2
164 sub %l0, %l5, %l5
165
166 /* prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu") */
167 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
168 mov 4, %l3
169 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
170 mov 1, %l3
171 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
172 stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, chosen_node
173 stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "mmu"
174 stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_mmu_ihandle_cache
175 mov 4, %l3
176 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, sizeof(arg3)
177 stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
178 call %l7
179 add %sp, (2047 + 128), %o0 ! argument array
180
181 mov (1b - prom_callmethod_name), %l1
182 mov (1b - prom_translate_name), %l2
183 sub %l0, %l1, %l1
184 sub %l0, %l2, %l2
185 lduw [%l5], %l5 ! prom_mmu_ihandle_cache
186
187 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "call-method"
188 mov 3, %l3
189 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 3
190 mov 5, %l3
191 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 5
192 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1: "translate"
193 stx %l5, [%sp + 2047 + 128 + 0x20] ! arg2: prom_mmu_ihandle_cache
194 srlx %l0, 22, %l3
195 sllx %l3, 22, %l3
196 stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: vaddr, our PC
197 stx %g0, [%sp + 2047 + 128 + 0x30] ! res1
198 stx %g0, [%sp + 2047 + 128 + 0x38] ! res2
199 stx %g0, [%sp + 2047 + 128 + 0x40] ! res3
200 stx %g0, [%sp + 2047 + 128 + 0x48] ! res4
201 stx %g0, [%sp + 2047 + 128 + 0x50] ! res5
202 call %l7
203 add %sp, (2047 + 128), %o0 ! argument array
204
205 ldx [%sp + 2047 + 128 + 0x40], %l1 ! translation mode
206 mov (1b - prom_boot_mapping_mode), %l4
207 sub %l0, %l4, %l4
208 stw %l1, [%l4]
209 mov (1b - prom_boot_mapping_phys_high), %l4
210 sub %l0, %l4, %l4
211 ldx [%sp + 2047 + 128 + 0x48], %l2 ! physaddr high
212 stx %l2, [%l4 + 0x0]
213 ldx [%sp + 2047 + 128 + 0x50], %l3 ! physaddr low
214 stx %l3, [%l4 + 0x8]
215
216 /* Leave service as-is, "call-method" */
217 mov 7, %l3
218 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 7
219 mov 1, %l3
220 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
221 mov (1b - prom_map_name), %l3
222 sub %l0, %l3, %l3
223 stx %l3, [%sp + 2047 + 128 + 0x18] ! arg1: "map"
224 /* Leave arg2 as-is, prom_mmu_ihandle_cache */
225 mov -1, %l3
226 stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: mode (-1 default)
227 sethi %hi(8 * 1024 * 1024), %l3
228 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4: size (8MB)
229 sethi %hi(KERNBASE), %l3
230 stx %l3, [%sp + 2047 + 128 + 0x38] ! arg5: vaddr (KERNBASE)
231 stx %g0, [%sp + 2047 + 128 + 0x40] ! arg6: empty
232 mov (1b - prom_boot_mapping_phys_low), %l3
233 sub %l0, %l3, %l3
234 ldx [%l3], %l3
235 stx %l3, [%sp + 2047 + 128 + 0x48] ! arg7: phys addr
236 call %l7
237 add %sp, (2047 + 128), %o0 ! argument array
238
239 add %sp, (192 + 128), %sp
240
241sparc64_boot_after_remap:
92 BRANCH_IF_CHEETAH_BASE(g1,g7,cheetah_boot) 242 BRANCH_IF_CHEETAH_BASE(g1,g7,cheetah_boot)
93 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,cheetah_plus_boot) 243 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,cheetah_plus_boot)
94 ba,pt %xcc, spitfire_boot 244 ba,pt %xcc, spitfire_boot
@@ -125,185 +275,7 @@ cheetah_generic_boot:
125 stxa %g0, [%g3] ASI_IMMU 275 stxa %g0, [%g3] ASI_IMMU
126 membar #Sync 276 membar #Sync
127 277
128 wrpr %g0, (PSTATE_PRIV|PSTATE_PEF|PSTATE_IE), %pstate 278 ba,a,pt %xcc, jump_to_sun4u_init
129 wr %g0, 0, %fprs
130
131 /* Just like for Spitfire, we probe itlb-2 for a mapping which
132 * matches our current %pc. We take the physical address in
133 * that mapping and use it to make our own.
134 */
135
136 /* %g5 holds the tlb data */
137 sethi %uhi(_PAGE_VALID | _PAGE_SZ4MB), %g5
138 sllx %g5, 32, %g5
139 or %g5, (_PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W | _PAGE_G), %g5
140
141 /* Put PADDR tlb data mask into %g3. */
142 sethi %uhi(_PAGE_PADDR), %g3
143 or %g3, %ulo(_PAGE_PADDR), %g3
144 sllx %g3, 32, %g3
145 sethi %hi(_PAGE_PADDR), %g7
146 or %g7, %lo(_PAGE_PADDR), %g7
147 or %g3, %g7, %g3
148
149 set 2 << 16, %l0 /* TLB entry walker. */
150 set 0x1fff, %l2 /* Page mask. */
151 rd %pc, %l3
152 andn %l3, %l2, %g2 /* vaddr comparator */
153
1541: ldxa [%l0] ASI_ITLB_TAG_READ, %g1
155 membar #Sync
156 andn %g1, %l2, %g1
157 cmp %g1, %g2
158 be,pn %xcc, cheetah_got_tlbentry
159 nop
160 and %l0, (127 << 3), %g1
161 cmp %g1, (127 << 3)
162 blu,pt %xcc, 1b
163 add %l0, (1 << 3), %l0
164
165 /* Search the small TLB. OBP never maps us like that but
166 * newer SILO can.
167 */
168 clr %l0
169
1701: ldxa [%l0] ASI_ITLB_TAG_READ, %g1
171 membar #Sync
172 andn %g1, %l2, %g1
173 cmp %g1, %g2
174 be,pn %xcc, cheetah_got_tlbentry
175 nop
176 cmp %l0, (15 << 3)
177 blu,pt %xcc, 1b
178 add %l0, (1 << 3), %l0
179
180 /* BUG() if we get here... */
181 ta 0x5
182
183cheetah_got_tlbentry:
184 ldxa [%l0] ASI_ITLB_DATA_ACCESS, %g0
185 ldxa [%l0] ASI_ITLB_DATA_ACCESS, %g1
186 membar #Sync
187 and %g1, %g3, %g1
188 set 0x5fff, %l0
189 andn %g1, %l0, %g1
190 or %g5, %g1, %g5
191
192 /* Clear out any KERNBASE area entries. */
193 set 2 << 16, %l0
194 sethi %hi(KERNBASE), %g3
195 sethi %hi(KERNBASE<<1), %g7
196 mov TLB_TAG_ACCESS, %l7
197
198 /* First, check ITLB */
1991: ldxa [%l0] ASI_ITLB_TAG_READ, %g1
200 membar #Sync
201 andn %g1, %l2, %g1
202 cmp %g1, %g3
203 blu,pn %xcc, 2f
204 cmp %g1, %g7
205 bgeu,pn %xcc, 2f
206 nop
207 stxa %g0, [%l7] ASI_IMMU
208 membar #Sync
209 stxa %g0, [%l0] ASI_ITLB_DATA_ACCESS
210 membar #Sync
211
2122: and %l0, (127 << 3), %g1
213 cmp %g1, (127 << 3)
214 blu,pt %xcc, 1b
215 add %l0, (1 << 3), %l0
216
217 /* Next, check DTLB */
218 set 2 << 16, %l0
2191: ldxa [%l0] ASI_DTLB_TAG_READ, %g1
220 membar #Sync
221 andn %g1, %l2, %g1
222 cmp %g1, %g3
223 blu,pn %xcc, 2f
224 cmp %g1, %g7
225 bgeu,pn %xcc, 2f
226 nop
227 stxa %g0, [%l7] ASI_DMMU
228 membar #Sync
229 stxa %g0, [%l0] ASI_DTLB_DATA_ACCESS
230 membar #Sync
231
2322: and %l0, (511 << 3), %g1
233 cmp %g1, (511 << 3)
234 blu,pt %xcc, 1b
235 add %l0, (1 << 3), %l0
236
237 /* On Cheetah+, have to check second DTLB. */
238 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,l0,2f)
239 ba,pt %xcc, 9f
240 nop
241
2422: set 3 << 16, %l0
2431: ldxa [%l0] ASI_DTLB_TAG_READ, %g1
244 membar #Sync
245 andn %g1, %l2, %g1
246 cmp %g1, %g3
247 blu,pn %xcc, 2f
248 cmp %g1, %g7
249 bgeu,pn %xcc, 2f
250 nop
251 stxa %g0, [%l7] ASI_DMMU
252 membar #Sync
253 stxa %g0, [%l0] ASI_DTLB_DATA_ACCESS
254 membar #Sync
255
2562: and %l0, (511 << 3), %g1
257 cmp %g1, (511 << 3)
258 blu,pt %xcc, 1b
259 add %l0, (1 << 3), %l0
260
2619:
262
263 /* Now lock the TTE we created into ITLB-0 and DTLB-0,
264 * entry 15 (and maybe 14 too).
265 */
266 sethi %hi(KERNBASE), %g3
267 set (0 << 16) | (15 << 3), %g7
268 stxa %g3, [%l7] ASI_DMMU
269 membar #Sync
270 stxa %g5, [%g7] ASI_DTLB_DATA_ACCESS
271 membar #Sync
272 stxa %g3, [%l7] ASI_IMMU
273 membar #Sync
274 stxa %g5, [%g7] ASI_ITLB_DATA_ACCESS
275 membar #Sync
276 flush %g3
277 membar #Sync
278 sethi %hi(_end), %g3 /* Check for bigkernel case */
279 or %g3, %lo(_end), %g3
280 srl %g3, 23, %g3 /* Check if _end > 8M */
281 brz,pt %g3, 1f
282 sethi %hi(KERNBASE), %g3 /* Restore for fixup code below */
283 sethi %hi(0x400000), %g3
284 or %g3, %lo(0x400000), %g3
285 add %g5, %g3, %g5 /* New tte data */
286 andn %g5, (_PAGE_G), %g5
287 sethi %hi(KERNBASE+0x400000), %g3
288 or %g3, %lo(KERNBASE+0x400000), %g3
289 set (0 << 16) | (14 << 3), %g7
290 stxa %g3, [%l7] ASI_DMMU
291 membar #Sync
292 stxa %g5, [%g7] ASI_DTLB_DATA_ACCESS
293 membar #Sync
294 stxa %g3, [%l7] ASI_IMMU
295 membar #Sync
296 stxa %g5, [%g7] ASI_ITLB_DATA_ACCESS
297 membar #Sync
298 flush %g3
299 membar #Sync
300 sethi %hi(KERNBASE), %g3 /* Restore for fixup code below */
301 ba,pt %xcc, 1f
302 nop
303
3041: set sun4u_init, %g2
305 jmpl %g2 + %g0, %g0
306 nop
307 279
308spitfire_boot: 280spitfire_boot:
309 /* Typically PROM has already enabled both MMU's and both on-chip 281 /* Typically PROM has already enabled both MMU's and both on-chip
@@ -313,6 +285,7 @@ spitfire_boot:
313 stxa %g1, [%g0] ASI_LSU_CONTROL 285 stxa %g1, [%g0] ASI_LSU_CONTROL
314 membar #Sync 286 membar #Sync
315 287
288jump_to_sun4u_init:
316 /* 289 /*
317 * Make sure we are in privileged mode, have address masking, 290 * Make sure we are in privileged mode, have address masking,
318 * using the ordinary globals and have enabled floating 291 * using the ordinary globals and have enabled floating
@@ -324,151 +297,6 @@ spitfire_boot:
324 wrpr %g0, (PSTATE_PRIV|PSTATE_PEF|PSTATE_IE), %pstate 297 wrpr %g0, (PSTATE_PRIV|PSTATE_PEF|PSTATE_IE), %pstate
325 wr %g0, 0, %fprs 298 wr %g0, 0, %fprs
326 299
327spitfire_create_mappings:
328 /* %g5 holds the tlb data */
329 sethi %uhi(_PAGE_VALID | _PAGE_SZ4MB), %g5
330 sllx %g5, 32, %g5
331 or %g5, (_PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W | _PAGE_G), %g5
332
333 /* Base of physical memory cannot reliably be assumed to be
334 * at 0x0! Figure out where it happens to be. -DaveM
335 */
336
337 /* Put PADDR tlb data mask into %g3. */
338 sethi %uhi(_PAGE_PADDR_SF), %g3
339 or %g3, %ulo(_PAGE_PADDR_SF), %g3
340 sllx %g3, 32, %g3
341 sethi %hi(_PAGE_PADDR_SF), %g7
342 or %g7, %lo(_PAGE_PADDR_SF), %g7
343 or %g3, %g7, %g3
344
345 /* Walk through entire ITLB, looking for entry which maps
346 * our %pc currently, stick PADDR from there into %g5 tlb data.
347 */
348 clr %l0 /* TLB entry walker. */
349 set 0x1fff, %l2 /* Page mask. */
350 rd %pc, %l3
351 andn %l3, %l2, %g2 /* vaddr comparator */
3521:
353 /* Yes, the nops seem to be necessary for now, don't ask me why. -DaveM */
354 ldxa [%l0] ASI_ITLB_TAG_READ, %g1
355 nop
356 nop
357 nop
358 andn %g1, %l2, %g1 /* Get vaddr */
359 cmp %g1, %g2
360 be,a,pn %xcc, spitfire_got_tlbentry
361 ldxa [%l0] ASI_ITLB_DATA_ACCESS, %g1
362 cmp %l0, (63 << 3)
363 blu,pt %xcc, 1b
364 add %l0, (1 << 3), %l0
365
366 /* BUG() if we get here... */
367 ta 0x5
368
369spitfire_got_tlbentry:
370 /* Nops here again, perhaps Cheetah/Blackbird are better behaved... */
371 nop
372 nop
373 nop
374 and %g1, %g3, %g1 /* Mask to just get paddr bits. */
375 set 0x5fff, %l3 /* Mask offset to get phys base. */
376 andn %g1, %l3, %g1
377
378 /* NOTE: We hold on to %g1 paddr base as we need it below to lock
379 * NOTE: the PROM cif code into the TLB.
380 */
381
382 or %g5, %g1, %g5 /* Or it into TAG being built. */
383
384 clr %l0 /* TLB entry walker. */
385 sethi %hi(KERNBASE), %g3 /* 4M lower limit */
386 sethi %hi(KERNBASE<<1), %g7 /* 8M upper limit */
387 mov TLB_TAG_ACCESS, %l7
3881:
389 /* Yes, the nops seem to be necessary for now, don't ask me why. -DaveM */
390 ldxa [%l0] ASI_ITLB_TAG_READ, %g1
391 nop
392 nop
393 nop
394 andn %g1, %l2, %g1 /* Get vaddr */
395 cmp %g1, %g3
396 blu,pn %xcc, 2f
397 cmp %g1, %g7
398 bgeu,pn %xcc, 2f
399 nop
400 stxa %g0, [%l7] ASI_IMMU
401 stxa %g0, [%l0] ASI_ITLB_DATA_ACCESS
402 membar #Sync
4032:
404 cmp %l0, (63 << 3)
405 blu,pt %xcc, 1b
406 add %l0, (1 << 3), %l0
407
408 nop; nop; nop
409
410 clr %l0 /* TLB entry walker. */
4111:
412 /* Yes, the nops seem to be necessary for now, don't ask me why. -DaveM */
413 ldxa [%l0] ASI_DTLB_TAG_READ, %g1
414 nop
415 nop
416 nop
417 andn %g1, %l2, %g1 /* Get vaddr */
418 cmp %g1, %g3
419 blu,pn %xcc, 2f
420 cmp %g1, %g7
421 bgeu,pn %xcc, 2f
422 nop
423 stxa %g0, [%l7] ASI_DMMU
424 stxa %g0, [%l0] ASI_DTLB_DATA_ACCESS
425 membar #Sync
4262:
427 cmp %l0, (63 << 3)
428 blu,pt %xcc, 1b
429 add %l0, (1 << 3), %l0
430
431 nop; nop; nop
432
433
434 /* PROM never puts any TLB entries into the MMU with the lock bit
435 * set. So we gladly use tlb entry 63 for KERNBASE. And maybe 62 too.
436 */
437
438 sethi %hi(KERNBASE), %g3
439 mov (63 << 3), %g7
440 stxa %g3, [%l7] ASI_DMMU /* KERNBASE into TLB TAG */
441 stxa %g5, [%g7] ASI_DTLB_DATA_ACCESS /* TTE into TLB DATA */
442 membar #Sync
443 stxa %g3, [%l7] ASI_IMMU /* KERNBASE into TLB TAG */
444 stxa %g5, [%g7] ASI_ITLB_DATA_ACCESS /* TTE into TLB DATA */
445 membar #Sync
446 flush %g3
447 membar #Sync
448 sethi %hi(_end), %g3 /* Check for bigkernel case */
449 or %g3, %lo(_end), %g3
450 srl %g3, 23, %g3 /* Check if _end > 8M */
451 brz,pt %g3, 2f
452 sethi %hi(KERNBASE), %g3 /* Restore for fixup code below */
453 sethi %hi(0x400000), %g3
454 or %g3, %lo(0x400000), %g3
455 add %g5, %g3, %g5 /* New tte data */
456 andn %g5, (_PAGE_G), %g5
457 sethi %hi(KERNBASE+0x400000), %g3
458 or %g3, %lo(KERNBASE+0x400000), %g3
459 mov (62 << 3), %g7
460 stxa %g3, [%l7] ASI_DMMU
461 stxa %g5, [%g7] ASI_DTLB_DATA_ACCESS
462 membar #Sync
463 stxa %g3, [%l7] ASI_IMMU
464 stxa %g5, [%g7] ASI_ITLB_DATA_ACCESS
465 membar #Sync
466 flush %g3
467 membar #Sync
468 sethi %hi(KERNBASE), %g3 /* Restore for fixup code below */
4692: ba,pt %xcc, 1f
470 nop
4711:
472 set sun4u_init, %g2 300 set sun4u_init, %g2
473 jmpl %g2 + %g0, %g0 301 jmpl %g2 + %g0, %g0
474 nop 302 nop
@@ -483,38 +311,12 @@ sun4u_init:
483 stxa %g0, [%g7] ASI_DMMU 311 stxa %g0, [%g7] ASI_DMMU
484 membar #Sync 312 membar #Sync
485 313
486 /* We are now safely (we hope) in Nucleus context (0), rewrite
487 * the KERNBASE TTE's so they no longer have the global bit set.
488 * Don't forget to setup TAG_ACCESS first 8-)
489 */
490 mov TLB_TAG_ACCESS, %g2
491 stxa %g3, [%g2] ASI_IMMU
492 stxa %g3, [%g2] ASI_DMMU
493 membar #Sync
494
495 BRANCH_IF_ANY_CHEETAH(g1,g7,cheetah_tlb_fixup) 314 BRANCH_IF_ANY_CHEETAH(g1,g7,cheetah_tlb_fixup)
496 315
497 ba,pt %xcc, spitfire_tlb_fixup 316 ba,pt %xcc, spitfire_tlb_fixup
498 nop 317 nop
499 318
500cheetah_tlb_fixup: 319cheetah_tlb_fixup:
501 set (0 << 16) | (15 << 3), %g7
502 ldxa [%g7] ASI_ITLB_DATA_ACCESS, %g0
503 ldxa [%g7] ASI_ITLB_DATA_ACCESS, %g1
504 andn %g1, (_PAGE_G), %g1
505 stxa %g1, [%g7] ASI_ITLB_DATA_ACCESS
506 membar #Sync
507
508 ldxa [%g7] ASI_DTLB_DATA_ACCESS, %g0
509 ldxa [%g7] ASI_DTLB_DATA_ACCESS, %g1
510 andn %g1, (_PAGE_G), %g1
511 stxa %g1, [%g7] ASI_DTLB_DATA_ACCESS
512 membar #Sync
513
514 /* Kill instruction prefetch queues. */
515 flush %g3
516 membar #Sync
517
518 mov 2, %g2 /* Set TLB type to cheetah+. */ 320 mov 2, %g2 /* Set TLB type to cheetah+. */
519 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f) 321 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f)
520 322
@@ -551,21 +353,6 @@ cheetah_tlb_fixup:
551 nop 353 nop
552 354
553spitfire_tlb_fixup: 355spitfire_tlb_fixup:
554 mov (63 << 3), %g7
555 ldxa [%g7] ASI_ITLB_DATA_ACCESS, %g1
556 andn %g1, (_PAGE_G), %g1
557 stxa %g1, [%g7] ASI_ITLB_DATA_ACCESS
558 membar #Sync
559
560 ldxa [%g7] ASI_DTLB_DATA_ACCESS, %g1
561 andn %g1, (_PAGE_G), %g1
562 stxa %g1, [%g7] ASI_DTLB_DATA_ACCESS
563 membar #Sync
564
565 /* Kill instruction prefetch queues. */
566 flush %g3
567 membar #Sync
568
569 /* Set TLB type to spitfire. */ 356 /* Set TLB type to spitfire. */
570 mov 0, %g2 357 mov 0, %g2
571 sethi %hi(tlb_type), %g1 358 sethi %hi(tlb_type), %g1
@@ -578,24 +365,6 @@ tlb_fixup_done:
578 mov %sp, %l6 365 mov %sp, %l6
579 mov %o4, %l7 366 mov %o4, %l7
580 367
581#if 0 /* We don't do it like this anymore, but for historical hack value
582 * I leave this snippet here to show how crazy we can be sometimes. 8-)
583 */
584
585 /* Setup "Linux Current Register", thanks Sun 8-) */
586 wr %g0, 0x1, %pcr
587
588 /* Blackbird errata workaround. See commentary in
589 * smp.c:smp_percpu_timer_interrupt() for more
590 * information.
591 */
592 ba,pt %xcc, 99f
593 nop
594 .align 64
59599: wr %g6, %g0, %pic
596 rd %pic, %g0
597#endif
598
599 wr %g0, ASI_P, %asi 368 wr %g0, ASI_P, %asi
600 mov 1, %g1 369 mov 1, %g1
601 sllx %g1, THREAD_SHIFT, %g1 370 sllx %g1, THREAD_SHIFT, %g1
@@ -756,12 +525,7 @@ bootup_user_stack_end:
756 525
757#include "ttable.S" 526#include "ttable.S"
758#include "systbls.S" 527#include "systbls.S"
759 528#include "ktlb.S"
760 .align 1024
761 .globl swapper_pg_dir
762swapper_pg_dir:
763 .word 0
764
765#include "etrap.S" 529#include "etrap.S"
766#include "rtrap.S" 530#include "rtrap.S"
767#include "winfixup.S" 531#include "winfixup.S"
diff --git a/arch/sparc64/kernel/ktlb.S b/arch/sparc64/kernel/ktlb.S
new file mode 100644
index 000000000000..7796b37f478c
--- /dev/null
+++ b/arch/sparc64/kernel/ktlb.S
@@ -0,0 +1,198 @@
1/* arch/sparc64/kernel/ktlb.S: Kernel mapping TLB miss handling.
2 *
3 * Copyright (C) 1995, 1997, 2005 David S. Miller <davem@davemloft.net>
4 * Copyright (C) 1996 Eddie C. Dost (ecd@brainaid.de)
5 * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
6 * Copyright (C) 1996,98,99 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
7*/
8
9#include <linux/config.h>
10#include <asm/head.h>
11#include <asm/asi.h>
12#include <asm/page.h>
13#include <asm/pgtable.h>
14
15 .text
16 .align 32
17
18/*
19 * On a second level vpte miss, check whether the original fault is to the OBP
20 * range (note that this is only possible for instruction miss, data misses to
21 * obp range do not use vpte). If so, go back directly to the faulting address.
22 * This is because we want to read the tpc, otherwise we have no way of knowing
23 * the 8k aligned faulting address if we are using >8k kernel pagesize. This
24 * also ensures no vpte range addresses are dropped into tlb while obp is
25 * executing (see inherit_locked_prom_mappings() rant).
26 */
27sparc64_vpte_nucleus:
28 /* Note that kvmap below has verified that the address is
29 * in the range MODULES_VADDR --> VMALLOC_END already. So
30 * here we need only check if it is an OBP address or not.
31 */
32 sethi %hi(LOW_OBP_ADDRESS), %g5
33 cmp %g4, %g5
34 blu,pn %xcc, kern_vpte
35 mov 0x1, %g5
36 sllx %g5, 32, %g5
37 cmp %g4, %g5
38 blu,pn %xcc, vpte_insn_obp
39 nop
40
41 /* These two instructions are patched by paginig_init(). */
42kern_vpte:
43 sethi %hi(swapper_pgd_zero), %g5
44 lduw [%g5 + %lo(swapper_pgd_zero)], %g5
45
46 /* With kernel PGD in %g5, branch back into dtlb_backend. */
47 ba,pt %xcc, sparc64_kpte_continue
48 andn %g1, 0x3, %g1 /* Finish PMD offset adjustment. */
49
50vpte_noent:
51 /* Restore previous TAG_ACCESS, %g5 is zero, and we will
52 * skip over the trap instruction so that the top level
53 * TLB miss handler will thing this %g5 value is just an
54 * invalid PTE, thus branching to full fault processing.
55 */
56 mov TLB_SFSR, %g1
57 stxa %g4, [%g1 + %g1] ASI_DMMU
58 done
59
60vpte_insn_obp:
61 sethi %hi(prom_pmd_phys), %g5
62 ldx [%g5 + %lo(prom_pmd_phys)], %g5
63
64 /* Behave as if we are at TL0. */
65 wrpr %g0, 1, %tl
66 rdpr %tpc, %g4 /* Find original faulting iaddr */
67 srlx %g4, 13, %g4 /* Throw out context bits */
68 sllx %g4, 13, %g4 /* g4 has vpn + ctx0 now */
69
70 /* Restore previous TAG_ACCESS. */
71 mov TLB_SFSR, %g1
72 stxa %g4, [%g1 + %g1] ASI_IMMU
73
74 /* Get PMD offset. */
75 srlx %g4, 23, %g6
76 and %g6, 0x7ff, %g6
77 sllx %g6, 2, %g6
78
79 /* Load PMD, is it valid? */
80 lduwa [%g5 + %g6] ASI_PHYS_USE_EC, %g5
81 brz,pn %g5, longpath
82 sllx %g5, 11, %g5
83
84 /* Get PTE offset. */
85 srlx %g4, 13, %g6
86 and %g6, 0x3ff, %g6
87 sllx %g6, 3, %g6
88
89 /* Load PTE. */
90 ldxa [%g5 + %g6] ASI_PHYS_USE_EC, %g5
91 brgez,pn %g5, longpath
92 nop
93
94 /* TLB load and return from trap. */
95 stxa %g5, [%g0] ASI_ITLB_DATA_IN
96 retry
97
98kvmap_do_obp:
99 sethi %hi(prom_pmd_phys), %g5
100 ldx [%g5 + %lo(prom_pmd_phys)], %g5
101
102 /* Get PMD offset. */
103 srlx %g4, 23, %g6
104 and %g6, 0x7ff, %g6
105 sllx %g6, 2, %g6
106
107 /* Load PMD, is it valid? */
108 lduwa [%g5 + %g6] ASI_PHYS_USE_EC, %g5
109 brz,pn %g5, longpath
110 sllx %g5, 11, %g5
111
112 /* Get PTE offset. */
113 srlx %g4, 13, %g6
114 and %g6, 0x3ff, %g6
115 sllx %g6, 3, %g6
116
117 /* Load PTE. */
118 ldxa [%g5 + %g6] ASI_PHYS_USE_EC, %g5
119 brgez,pn %g5, longpath
120 nop
121
122 /* TLB load and return from trap. */
123 stxa %g5, [%g0] ASI_DTLB_DATA_IN
124 retry
125
126/*
127 * On a first level data miss, check whether this is to the OBP range (note
128 * that such accesses can be made by prom, as well as by kernel using
129 * prom_getproperty on "address"), and if so, do not use vpte access ...
130 * rather, use information saved during inherit_prom_mappings() using 8k
131 * pagesize.
132 */
133 .align 32
134kvmap:
135 brgez,pn %g4, kvmap_nonlinear
136 nop
137
138#ifdef CONFIG_DEBUG_PAGEALLOC
139 .globl kvmap_linear_patch
140kvmap_linear_patch:
141#endif
142 ba,pt %xcc, kvmap_load
143 xor %g2, %g4, %g5
144
145#ifdef CONFIG_DEBUG_PAGEALLOC
146 sethi %hi(swapper_pg_dir), %g5
147 or %g5, %lo(swapper_pg_dir), %g5
148 sllx %g4, 64 - (PGDIR_SHIFT + PGDIR_BITS), %g6
149 srlx %g6, 64 - PAGE_SHIFT, %g6
150 andn %g6, 0x3, %g6
151 lduw [%g5 + %g6], %g5
152 brz,pn %g5, longpath
153 sllx %g4, 64 - (PMD_SHIFT + PMD_BITS), %g6
154 srlx %g6, 64 - PAGE_SHIFT, %g6
155 sllx %g5, 11, %g5
156 andn %g6, 0x3, %g6
157 lduwa [%g5 + %g6] ASI_PHYS_USE_EC, %g5
158 brz,pn %g5, longpath
159 sllx %g4, 64 - PMD_SHIFT, %g6
160 srlx %g6, 64 - PAGE_SHIFT, %g6
161 sllx %g5, 11, %g5
162 andn %g6, 0x7, %g6
163 ldxa [%g5 + %g6] ASI_PHYS_USE_EC, %g5
164 brz,pn %g5, longpath
165 nop
166 ba,a,pt %xcc, kvmap_load
167#endif
168
169kvmap_nonlinear:
170 sethi %hi(MODULES_VADDR), %g5
171 cmp %g4, %g5
172 blu,pn %xcc, longpath
173 mov (VMALLOC_END >> 24), %g5
174 sllx %g5, 24, %g5
175 cmp %g4, %g5
176 bgeu,pn %xcc, longpath
177 nop
178
179kvmap_check_obp:
180 sethi %hi(LOW_OBP_ADDRESS), %g5
181 cmp %g4, %g5
182 blu,pn %xcc, kvmap_vmalloc_addr
183 mov 0x1, %g5
184 sllx %g5, 32, %g5
185 cmp %g4, %g5
186 blu,pn %xcc, kvmap_do_obp
187 nop
188
189kvmap_vmalloc_addr:
190 /* If we get here, a vmalloc addr was accessed, load kernel VPTE. */
191 ldxa [%g3 + %g6] ASI_N, %g5
192 brgez,pn %g5, longpath
193 nop
194
195kvmap_load:
196 /* PTE is valid, load into TLB and return from trap. */
197 stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB
198 retry
diff --git a/arch/sparc64/kernel/pci_schizo.c b/arch/sparc64/kernel/pci_schizo.c
index 331382e1a75d..cae5b61fe2f0 100644
--- a/arch/sparc64/kernel/pci_schizo.c
+++ b/arch/sparc64/kernel/pci_schizo.c
@@ -330,7 +330,7 @@ static int schizo_ino_to_pil(struct pci_dev *pdev, unsigned int ino)
330static void tomatillo_wsync_handler(struct ino_bucket *bucket, void *_arg1, void *_arg2) 330static void tomatillo_wsync_handler(struct ino_bucket *bucket, void *_arg1, void *_arg2)
331{ 331{
332 unsigned long sync_reg = (unsigned long) _arg2; 332 unsigned long sync_reg = (unsigned long) _arg2;
333 u64 mask = 1 << (__irq_ino(__irq(bucket)) & IMAP_INO); 333 u64 mask = 1UL << (__irq_ino(__irq(bucket)) & IMAP_INO);
334 u64 val; 334 u64 val;
335 int limit; 335 int limit;
336 336
diff --git a/arch/sparc64/kernel/setup.c b/arch/sparc64/kernel/setup.c
index ddbed3341a23..8e8baf2354df 100644
--- a/arch/sparc64/kernel/setup.c
+++ b/arch/sparc64/kernel/setup.c
@@ -496,7 +496,6 @@ extern void paging_init(void);
496 496
497void __init setup_arch(char **cmdline_p) 497void __init setup_arch(char **cmdline_p)
498{ 498{
499 unsigned long highest_paddr;
500 int i; 499 int i;
501 500
502 /* Initialize PROM console and command line. */ 501 /* Initialize PROM console and command line. */
@@ -519,11 +518,7 @@ void __init setup_arch(char **cmdline_p)
519 idprom_init(); 518 idprom_init();
520 (void) prom_probe_memory(); 519 (void) prom_probe_memory();
521 520
522 /* In paging_init() we tip off this value to see if we need
523 * to change init_mm.pgd to point to the real alias mapping.
524 */
525 phys_base = 0xffffffffffffffffUL; 521 phys_base = 0xffffffffffffffffUL;
526 highest_paddr = 0UL;
527 for (i = 0; sp_banks[i].num_bytes != 0; i++) { 522 for (i = 0; sp_banks[i].num_bytes != 0; i++) {
528 unsigned long top; 523 unsigned long top;
529 524
@@ -531,25 +526,10 @@ void __init setup_arch(char **cmdline_p)
531 phys_base = sp_banks[i].base_addr; 526 phys_base = sp_banks[i].base_addr;
532 top = sp_banks[i].base_addr + 527 top = sp_banks[i].base_addr +
533 sp_banks[i].num_bytes; 528 sp_banks[i].num_bytes;
534 if (highest_paddr < top)
535 highest_paddr = top;
536 } 529 }
537 pfn_base = phys_base >> PAGE_SHIFT; 530 pfn_base = phys_base >> PAGE_SHIFT;
538 531
539 switch (tlb_type) { 532 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
540 default:
541 case spitfire:
542 kern_base = spitfire_get_itlb_data(sparc64_highest_locked_tlbent());
543 kern_base &= _PAGE_PADDR_SF;
544 break;
545
546 case cheetah:
547 case cheetah_plus:
548 kern_base = cheetah_get_litlb_data(sparc64_highest_locked_tlbent());
549 kern_base &= _PAGE_PADDR;
550 break;
551 };
552
553 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE; 533 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
554 534
555 if (!root_flags) 535 if (!root_flags)
@@ -625,6 +605,9 @@ extern void smp_info(struct seq_file *);
625extern void smp_bogo(struct seq_file *); 605extern void smp_bogo(struct seq_file *);
626extern void mmu_info(struct seq_file *); 606extern void mmu_info(struct seq_file *);
627 607
608unsigned int dcache_parity_tl1_occurred;
609unsigned int icache_parity_tl1_occurred;
610
628static int show_cpuinfo(struct seq_file *m, void *__unused) 611static int show_cpuinfo(struct seq_file *m, void *__unused)
629{ 612{
630 seq_printf(m, 613 seq_printf(m,
@@ -635,6 +618,8 @@ static int show_cpuinfo(struct seq_file *m, void *__unused)
635 "type\t\t: sun4u\n" 618 "type\t\t: sun4u\n"
636 "ncpus probed\t: %ld\n" 619 "ncpus probed\t: %ld\n"
637 "ncpus active\t: %ld\n" 620 "ncpus active\t: %ld\n"
621 "D$ parity tl1\t: %u\n"
622 "I$ parity tl1\t: %u\n"
638#ifndef CONFIG_SMP 623#ifndef CONFIG_SMP
639 "Cpu0Bogo\t: %lu.%02lu\n" 624 "Cpu0Bogo\t: %lu.%02lu\n"
640 "Cpu0ClkTck\t: %016lx\n" 625 "Cpu0ClkTck\t: %016lx\n"
@@ -647,7 +632,9 @@ static int show_cpuinfo(struct seq_file *m, void *__unused)
647 (prom_prev >> 8) & 0xff, 632 (prom_prev >> 8) & 0xff,
648 prom_prev & 0xff, 633 prom_prev & 0xff,
649 (long)num_possible_cpus(), 634 (long)num_possible_cpus(),
650 (long)num_online_cpus() 635 (long)num_online_cpus(),
636 dcache_parity_tl1_occurred,
637 icache_parity_tl1_occurred
651#ifndef CONFIG_SMP 638#ifndef CONFIG_SMP
652 , cpu_data(0).udelay_val/(500000/HZ), 639 , cpu_data(0).udelay_val/(500000/HZ),
653 (cpu_data(0).udelay_val/(5000/HZ)) % 100, 640 (cpu_data(0).udelay_val/(5000/HZ)) % 100,
diff --git a/arch/sparc64/kernel/smp.c b/arch/sparc64/kernel/smp.c
index b4fc6a5462b2..590df5a16f5a 100644
--- a/arch/sparc64/kernel/smp.c
+++ b/arch/sparc64/kernel/smp.c
@@ -93,6 +93,27 @@ void __init smp_store_cpu_info(int id)
93 cpu_data(id).pte_cache[1] = NULL; 93 cpu_data(id).pte_cache[1] = NULL;
94 cpu_data(id).pgd_cache = NULL; 94 cpu_data(id).pgd_cache = NULL;
95 cpu_data(id).idle_volume = 1; 95 cpu_data(id).idle_volume = 1;
96
97 cpu_data(id).dcache_size = prom_getintdefault(cpu_node, "dcache-size",
98 16 * 1024);
99 cpu_data(id).dcache_line_size =
100 prom_getintdefault(cpu_node, "dcache-line-size", 32);
101 cpu_data(id).icache_size = prom_getintdefault(cpu_node, "icache-size",
102 16 * 1024);
103 cpu_data(id).icache_line_size =
104 prom_getintdefault(cpu_node, "icache-line-size", 32);
105 cpu_data(id).ecache_size = prom_getintdefault(cpu_node, "ecache-size",
106 4 * 1024 * 1024);
107 cpu_data(id).ecache_line_size =
108 prom_getintdefault(cpu_node, "ecache-line-size", 64);
109 printk("CPU[%d]: Caches "
110 "D[sz(%d):line_sz(%d)] "
111 "I[sz(%d):line_sz(%d)] "
112 "E[sz(%d):line_sz(%d)]\n",
113 id,
114 cpu_data(id).dcache_size, cpu_data(id).dcache_line_size,
115 cpu_data(id).icache_size, cpu_data(id).icache_line_size,
116 cpu_data(id).ecache_size, cpu_data(id).ecache_line_size);
96} 117}
97 118
98static void smp_setup_percpu_timer(void); 119static void smp_setup_percpu_timer(void);
diff --git a/arch/sparc64/kernel/trampoline.S b/arch/sparc64/kernel/trampoline.S
index 3a145fc39cf2..89f2fcfcd662 100644
--- a/arch/sparc64/kernel/trampoline.S
+++ b/arch/sparc64/kernel/trampoline.S
@@ -119,8 +119,8 @@ startup_continue:
119 sethi %hi(itlb_load), %g2 119 sethi %hi(itlb_load), %g2
120 or %g2, %lo(itlb_load), %g2 120 or %g2, %lo(itlb_load), %g2
121 stx %g2, [%sp + 2047 + 128 + 0x18] 121 stx %g2, [%sp + 2047 + 128 + 0x18]
122 sethi %hi(mmu_ihandle_cache), %g2 122 sethi %hi(prom_mmu_ihandle_cache), %g2
123 lduw [%g2 + %lo(mmu_ihandle_cache)], %g2 123 lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
124 stx %g2, [%sp + 2047 + 128 + 0x20] 124 stx %g2, [%sp + 2047 + 128 + 0x20]
125 sethi %hi(KERNBASE), %g2 125 sethi %hi(KERNBASE), %g2
126 stx %g2, [%sp + 2047 + 128 + 0x28] 126 stx %g2, [%sp + 2047 + 128 + 0x28]
@@ -156,8 +156,8 @@ startup_continue:
156 sethi %hi(itlb_load), %g2 156 sethi %hi(itlb_load), %g2
157 or %g2, %lo(itlb_load), %g2 157 or %g2, %lo(itlb_load), %g2
158 stx %g2, [%sp + 2047 + 128 + 0x18] 158 stx %g2, [%sp + 2047 + 128 + 0x18]
159 sethi %hi(mmu_ihandle_cache), %g2 159 sethi %hi(prom_mmu_ihandle_cache), %g2
160 lduw [%g2 + %lo(mmu_ihandle_cache)], %g2 160 lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
161 stx %g2, [%sp + 2047 + 128 + 0x20] 161 stx %g2, [%sp + 2047 + 128 + 0x20]
162 sethi %hi(KERNBASE + 0x400000), %g2 162 sethi %hi(KERNBASE + 0x400000), %g2
163 stx %g2, [%sp + 2047 + 128 + 0x28] 163 stx %g2, [%sp + 2047 + 128 + 0x28]
@@ -190,8 +190,8 @@ do_dtlb:
190 sethi %hi(dtlb_load), %g2 190 sethi %hi(dtlb_load), %g2
191 or %g2, %lo(dtlb_load), %g2 191 or %g2, %lo(dtlb_load), %g2
192 stx %g2, [%sp + 2047 + 128 + 0x18] 192 stx %g2, [%sp + 2047 + 128 + 0x18]
193 sethi %hi(mmu_ihandle_cache), %g2 193 sethi %hi(prom_mmu_ihandle_cache), %g2
194 lduw [%g2 + %lo(mmu_ihandle_cache)], %g2 194 lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
195 stx %g2, [%sp + 2047 + 128 + 0x20] 195 stx %g2, [%sp + 2047 + 128 + 0x20]
196 sethi %hi(KERNBASE), %g2 196 sethi %hi(KERNBASE), %g2
197 stx %g2, [%sp + 2047 + 128 + 0x28] 197 stx %g2, [%sp + 2047 + 128 + 0x28]
@@ -228,8 +228,8 @@ do_dtlb:
228 sethi %hi(dtlb_load), %g2 228 sethi %hi(dtlb_load), %g2
229 or %g2, %lo(dtlb_load), %g2 229 or %g2, %lo(dtlb_load), %g2
230 stx %g2, [%sp + 2047 + 128 + 0x18] 230 stx %g2, [%sp + 2047 + 128 + 0x18]
231 sethi %hi(mmu_ihandle_cache), %g2 231 sethi %hi(prom_mmu_ihandle_cache), %g2
232 lduw [%g2 + %lo(mmu_ihandle_cache)], %g2 232 lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
233 stx %g2, [%sp + 2047 + 128 + 0x20] 233 stx %g2, [%sp + 2047 + 128 + 0x20]
234 sethi %hi(KERNBASE + 0x400000), %g2 234 sethi %hi(KERNBASE + 0x400000), %g2
235 stx %g2, [%sp + 2047 + 128 + 0x28] 235 stx %g2, [%sp + 2047 + 128 + 0x28]
diff --git a/arch/sparc64/kernel/traps.c b/arch/sparc64/kernel/traps.c
index b280b2ef674f..f8e7005fede9 100644
--- a/arch/sparc64/kernel/traps.c
+++ b/arch/sparc64/kernel/traps.c
@@ -869,14 +869,19 @@ static void cheetah_flush_ecache_line(unsigned long physaddr)
869 */ 869 */
870static void __cheetah_flush_icache(void) 870static void __cheetah_flush_icache(void)
871{ 871{
872 unsigned long i; 872 unsigned int icache_size, icache_line_size;
873 unsigned long addr;
874
875 icache_size = local_cpu_data().icache_size;
876 icache_line_size = local_cpu_data().icache_line_size;
873 877
874 /* Clear the valid bits in all the tags. */ 878 /* Clear the valid bits in all the tags. */
875 for (i = 0; i < (1 << 15); i += (1 << 5)) { 879 for (addr = 0; addr < icache_size; addr += icache_line_size) {
876 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" 880 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
877 "membar #Sync" 881 "membar #Sync"
878 : /* no outputs */ 882 : /* no outputs */
879 : "r" (i | (2 << 3)), "i" (ASI_IC_TAG)); 883 : "r" (addr | (2 << 3)),
884 "i" (ASI_IC_TAG));
880 } 885 }
881} 886}
882 887
@@ -904,13 +909,17 @@ static void cheetah_flush_icache(void)
904 909
905static void cheetah_flush_dcache(void) 910static void cheetah_flush_dcache(void)
906{ 911{
907 unsigned long i; 912 unsigned int dcache_size, dcache_line_size;
913 unsigned long addr;
914
915 dcache_size = local_cpu_data().dcache_size;
916 dcache_line_size = local_cpu_data().dcache_line_size;
908 917
909 for (i = 0; i < (1 << 16); i += (1 << 5)) { 918 for (addr = 0; addr < dcache_size; addr += dcache_line_size) {
910 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" 919 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
911 "membar #Sync" 920 "membar #Sync"
912 : /* no outputs */ 921 : /* no outputs */
913 : "r" (i), "i" (ASI_DCACHE_TAG)); 922 : "r" (addr), "i" (ASI_DCACHE_TAG));
914 } 923 }
915} 924}
916 925
@@ -921,24 +930,29 @@ static void cheetah_flush_dcache(void)
921 */ 930 */
922static void cheetah_plus_zap_dcache_parity(void) 931static void cheetah_plus_zap_dcache_parity(void)
923{ 932{
924 unsigned long i; 933 unsigned int dcache_size, dcache_line_size;
934 unsigned long addr;
935
936 dcache_size = local_cpu_data().dcache_size;
937 dcache_line_size = local_cpu_data().dcache_line_size;
925 938
926 for (i = 0; i < (1 << 16); i += (1 << 5)) { 939 for (addr = 0; addr < dcache_size; addr += dcache_line_size) {
927 unsigned long tag = (i >> 14); 940 unsigned long tag = (addr >> 14);
928 unsigned long j; 941 unsigned long line;
929 942
930 __asm__ __volatile__("membar #Sync\n\t" 943 __asm__ __volatile__("membar #Sync\n\t"
931 "stxa %0, [%1] %2\n\t" 944 "stxa %0, [%1] %2\n\t"
932 "membar #Sync" 945 "membar #Sync"
933 : /* no outputs */ 946 : /* no outputs */
934 : "r" (tag), "r" (i), 947 : "r" (tag), "r" (addr),
935 "i" (ASI_DCACHE_UTAG)); 948 "i" (ASI_DCACHE_UTAG));
936 for (j = i; j < i + (1 << 5); j += (1 << 3)) 949 for (line = addr; line < addr + dcache_line_size; line += 8)
937 __asm__ __volatile__("membar #Sync\n\t" 950 __asm__ __volatile__("membar #Sync\n\t"
938 "stxa %%g0, [%0] %1\n\t" 951 "stxa %%g0, [%0] %1\n\t"
939 "membar #Sync" 952 "membar #Sync"
940 : /* no outputs */ 953 : /* no outputs */
941 : "r" (j), "i" (ASI_DCACHE_DATA)); 954 : "r" (line),
955 "i" (ASI_DCACHE_DATA));
942 } 956 }
943} 957}
944 958
diff --git a/arch/sparc64/kernel/vmlinux.lds.S b/arch/sparc64/kernel/vmlinux.lds.S
index f47d0be39378..2af0cf0a8640 100644
--- a/arch/sparc64/kernel/vmlinux.lds.S
+++ b/arch/sparc64/kernel/vmlinux.lds.S
@@ -9,8 +9,7 @@ ENTRY(_start)
9jiffies = jiffies_64; 9jiffies = jiffies_64;
10SECTIONS 10SECTIONS
11{ 11{
12 swapper_pmd_dir = 0x0000000000402000; 12 swapper_low_pmd_dir = 0x0000000000402000;
13 empty_pg_dir = 0x0000000000403000;
14 . = 0x4000; 13 . = 0x4000;
15 .text 0x0000000000404000 : 14 .text 0x0000000000404000 :
16 { 15 {
diff --git a/arch/sparc64/mm/init.c b/arch/sparc64/mm/init.c
index fdb1ebb308c9..9f6ca624892d 100644
--- a/arch/sparc64/mm/init.c
+++ b/arch/sparc64/mm/init.c
@@ -20,6 +20,7 @@
20#include <linux/fs.h> 20#include <linux/fs.h>
21#include <linux/seq_file.h> 21#include <linux/seq_file.h>
22#include <linux/kprobes.h> 22#include <linux/kprobes.h>
23#include <linux/cache.h>
23 24
24#include <asm/head.h> 25#include <asm/head.h>
25#include <asm/system.h> 26#include <asm/system.h>
@@ -42,22 +43,13 @@ extern void device_scan(void);
42 43
43struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS]; 44struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS];
44 45
45unsigned long *sparc64_valid_addr_bitmap; 46unsigned long *sparc64_valid_addr_bitmap __read_mostly;
46 47
47/* Ugly, but necessary... -DaveM */ 48/* Ugly, but necessary... -DaveM */
48unsigned long phys_base; 49unsigned long phys_base __read_mostly;
49unsigned long kern_base; 50unsigned long kern_base __read_mostly;
50unsigned long kern_size; 51unsigned long kern_size __read_mostly;
51unsigned long pfn_base; 52unsigned long pfn_base __read_mostly;
52
53/* This is even uglier. We have a problem where the kernel may not be
54 * located at phys_base. However, initial __alloc_bootmem() calls need to
55 * be adjusted to be within the 4-8Megs that the kernel is mapped to, else
56 * those page mappings wont work. Things are ok after inherit_prom_mappings
57 * is called though. Dave says he'll clean this up some other time.
58 * -- BenC
59 */
60static unsigned long bootmap_base;
61 53
62/* get_new_mmu_context() uses "cache + 1". */ 54/* get_new_mmu_context() uses "cache + 1". */
63DEFINE_SPINLOCK(ctx_alloc_lock); 55DEFINE_SPINLOCK(ctx_alloc_lock);
@@ -73,7 +65,7 @@ extern unsigned long sparc_ramdisk_image64;
73extern unsigned int sparc_ramdisk_image; 65extern unsigned int sparc_ramdisk_image;
74extern unsigned int sparc_ramdisk_size; 66extern unsigned int sparc_ramdisk_size;
75 67
76struct page *mem_map_zero; 68struct page *mem_map_zero __read_mostly;
77 69
78int bigkernel = 0; 70int bigkernel = 0;
79 71
@@ -179,8 +171,6 @@ static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long c
179 : "g1", "g7"); 171 : "g1", "g7");
180} 172}
181 173
182extern void __update_mmu_cache(unsigned long mmu_context_hw, unsigned long address, pte_t pte, int code);
183
184void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte) 174void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
185{ 175{
186 struct page *page; 176 struct page *page;
@@ -207,10 +197,6 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t p
207 197
208 put_cpu(); 198 put_cpu();
209 } 199 }
210
211 if (get_thread_fault_code())
212 __update_mmu_cache(CTX_NRBITS(vma->vm_mm->context),
213 address, pte, get_thread_fault_code());
214} 200}
215 201
216void flush_dcache_page(struct page *page) 202void flush_dcache_page(struct page *page)
@@ -309,6 +295,7 @@ struct linux_prom_translation {
309 unsigned long size; 295 unsigned long size;
310 unsigned long data; 296 unsigned long data;
311}; 297};
298static struct linux_prom_translation prom_trans[512] __initdata;
312 299
313extern unsigned long prom_boot_page; 300extern unsigned long prom_boot_page;
314extern void prom_remap(unsigned long physpage, unsigned long virtpage, int mmu_ihandle); 301extern void prom_remap(unsigned long physpage, unsigned long virtpage, int mmu_ihandle);
@@ -318,14 +305,63 @@ extern void register_prom_callbacks(void);
318/* Exported for SMP bootup purposes. */ 305/* Exported for SMP bootup purposes. */
319unsigned long kern_locked_tte_data; 306unsigned long kern_locked_tte_data;
320 307
321void __init early_pgtable_allocfail(char *type) 308/* Exported for kernel TLB miss handling in ktlb.S */
309unsigned long prom_pmd_phys __read_mostly;
310unsigned int swapper_pgd_zero __read_mostly;
311
312/* Allocate power-of-2 aligned chunks from the end of the
313 * kernel image. Return physical address.
314 */
315static inline unsigned long early_alloc_phys(unsigned long size)
316{
317 unsigned long base;
318
319 BUILD_BUG_ON(size & (size - 1));
320
321 kern_size = (kern_size + (size - 1)) & ~(size - 1);
322 base = kern_base + kern_size;
323 kern_size += size;
324
325 return base;
326}
327
328static inline unsigned long load_phys32(unsigned long pa)
329{
330 unsigned long val;
331
332 __asm__ __volatile__("lduwa [%1] %2, %0"
333 : "=&r" (val)
334 : "r" (pa), "i" (ASI_PHYS_USE_EC));
335
336 return val;
337}
338
339static inline unsigned long load_phys64(unsigned long pa)
340{
341 unsigned long val;
342
343 __asm__ __volatile__("ldxa [%1] %2, %0"
344 : "=&r" (val)
345 : "r" (pa), "i" (ASI_PHYS_USE_EC));
346
347 return val;
348}
349
350static inline void store_phys32(unsigned long pa, unsigned long val)
351{
352 __asm__ __volatile__("stwa %0, [%1] %2"
353 : /* no outputs */
354 : "r" (val), "r" (pa), "i" (ASI_PHYS_USE_EC));
355}
356
357static inline void store_phys64(unsigned long pa, unsigned long val)
322{ 358{
323 prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type); 359 __asm__ __volatile__("stxa %0, [%1] %2"
324 prom_halt(); 360 : /* no outputs */
361 : "r" (val), "r" (pa), "i" (ASI_PHYS_USE_EC));
325} 362}
326 363
327#define BASE_PAGE_SIZE 8192 364#define BASE_PAGE_SIZE 8192
328static pmd_t *prompmd;
329 365
330/* 366/*
331 * Translate PROM's mapping we capture at boot time into physical address. 367 * Translate PROM's mapping we capture at boot time into physical address.
@@ -333,278 +369,172 @@ static pmd_t *prompmd;
333 */ 369 */
334unsigned long prom_virt_to_phys(unsigned long promva, int *error) 370unsigned long prom_virt_to_phys(unsigned long promva, int *error)
335{ 371{
336 pmd_t *pmdp = prompmd + ((promva >> 23) & 0x7ff); 372 unsigned long pmd_phys = (prom_pmd_phys +
337 pte_t *ptep; 373 ((promva >> 23) & 0x7ff) * sizeof(pmd_t));
374 unsigned long pte_phys;
375 pmd_t pmd_ent;
376 pte_t pte_ent;
338 unsigned long base; 377 unsigned long base;
339 378
340 if (pmd_none(*pmdp)) { 379 pmd_val(pmd_ent) = load_phys32(pmd_phys);
380 if (pmd_none(pmd_ent)) {
341 if (error) 381 if (error)
342 *error = 1; 382 *error = 1;
343 return(0); 383 return 0;
344 } 384 }
345 ptep = (pte_t *)__pmd_page(*pmdp) + ((promva >> 13) & 0x3ff); 385
346 if (!pte_present(*ptep)) { 386 pte_phys = (unsigned long)pmd_val(pmd_ent) << 11UL;
387 pte_phys += ((promva >> 13) & 0x3ff) * sizeof(pte_t);
388 pte_val(pte_ent) = load_phys64(pte_phys);
389 if (!pte_present(pte_ent)) {
347 if (error) 390 if (error)
348 *error = 1; 391 *error = 1;
349 return(0); 392 return 0;
350 } 393 }
351 if (error) { 394 if (error) {
352 *error = 0; 395 *error = 0;
353 return(pte_val(*ptep)); 396 return pte_val(pte_ent);
354 } 397 }
355 base = pte_val(*ptep) & _PAGE_PADDR; 398 base = pte_val(pte_ent) & _PAGE_PADDR;
356 return(base + (promva & (BASE_PAGE_SIZE - 1))); 399 return (base + (promva & (BASE_PAGE_SIZE - 1)));
357} 400}
358 401
359static void inherit_prom_mappings(void) 402/* The obp translations are saved based on 8k pagesize, since obp can
403 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
404 * HI_OBP_ADDRESS range are handled in entry.S and do not use the vpte
405 * scheme (also, see rant in inherit_locked_prom_mappings()).
406 */
407static void __init build_obp_range(unsigned long start, unsigned long end, unsigned long data)
360{ 408{
361 struct linux_prom_translation *trans; 409 unsigned long vaddr;
362 unsigned long phys_page, tte_vaddr, tte_data;
363 void (*remap_func)(unsigned long, unsigned long, int);
364 pmd_t *pmdp;
365 pte_t *ptep;
366 int node, n, i, tsz;
367 extern unsigned int obp_iaddr_patch[2], obp_daddr_patch[2];
368 410
369 node = prom_finddevice("/virtual-memory"); 411 for (vaddr = start; vaddr < end; vaddr += BASE_PAGE_SIZE) {
370 n = prom_getproplen(node, "translations"); 412 unsigned long val, pte_phys, pmd_phys;
371 if (n == 0 || n == -1) { 413 pmd_t pmd_ent;
372 prom_printf("Couldn't get translation property\n"); 414 int i;
373 prom_halt();
374 }
375 n += 5 * sizeof(struct linux_prom_translation);
376 for (tsz = 1; tsz < n; tsz <<= 1)
377 /* empty */;
378 trans = __alloc_bootmem(tsz, SMP_CACHE_BYTES, bootmap_base);
379 if (trans == NULL) {
380 prom_printf("inherit_prom_mappings: Cannot alloc translations.\n");
381 prom_halt();
382 }
383 memset(trans, 0, tsz);
384 415
385 if ((n = prom_getproperty(node, "translations", (char *)trans, tsz)) == -1) { 416 pmd_phys = (prom_pmd_phys +
386 prom_printf("Couldn't get translation property\n"); 417 (((vaddr >> 23) & 0x7ff) * sizeof(pmd_t)));
387 prom_halt(); 418 pmd_val(pmd_ent) = load_phys32(pmd_phys);
388 } 419 if (pmd_none(pmd_ent)) {
389 n = n / sizeof(*trans); 420 pte_phys = early_alloc_phys(BASE_PAGE_SIZE);
390 421
391 /* 422 for (i = 0; i < BASE_PAGE_SIZE / sizeof(pte_t); i++)
392 * The obp translations are saved based on 8k pagesize, since obp can 423 store_phys64(pte_phys+i*sizeof(pte_t),0);
393 * use a mixture of pagesizes. Misses to the 0xf0000000 - 0x100000000,
394 * ie obp range, are handled in entry.S and do not use the vpte scheme
395 * (see rant in inherit_locked_prom_mappings()).
396 */
397#define OBP_PMD_SIZE 2048
398 prompmd = __alloc_bootmem(OBP_PMD_SIZE, OBP_PMD_SIZE, bootmap_base);
399 if (prompmd == NULL)
400 early_pgtable_allocfail("pmd");
401 memset(prompmd, 0, OBP_PMD_SIZE);
402 for (i = 0; i < n; i++) {
403 unsigned long vaddr;
404
405 if (trans[i].virt >= LOW_OBP_ADDRESS && trans[i].virt < HI_OBP_ADDRESS) {
406 for (vaddr = trans[i].virt;
407 ((vaddr < trans[i].virt + trans[i].size) &&
408 (vaddr < HI_OBP_ADDRESS));
409 vaddr += BASE_PAGE_SIZE) {
410 unsigned long val;
411
412 pmdp = prompmd + ((vaddr >> 23) & 0x7ff);
413 if (pmd_none(*pmdp)) {
414 ptep = __alloc_bootmem(BASE_PAGE_SIZE,
415 BASE_PAGE_SIZE,
416 bootmap_base);
417 if (ptep == NULL)
418 early_pgtable_allocfail("pte");
419 memset(ptep, 0, BASE_PAGE_SIZE);
420 pmd_set(pmdp, ptep);
421 }
422 ptep = (pte_t *)__pmd_page(*pmdp) +
423 ((vaddr >> 13) & 0x3ff);
424 424
425 val = trans[i].data; 425 pmd_val(pmd_ent) = pte_phys >> 11UL;
426 store_phys32(pmd_phys, pmd_val(pmd_ent));
427 }
426 428
427 /* Clear diag TTE bits. */ 429 pte_phys = (unsigned long)pmd_val(pmd_ent) << 11UL;
428 if (tlb_type == spitfire) 430 pte_phys += (((vaddr >> 13) & 0x3ff) * sizeof(pte_t));
429 val &= ~0x0003fe0000000000UL;
430 431
431 set_pte_at(&init_mm, vaddr, 432 val = data;
432 ptep, __pte(val | _PAGE_MODIFIED));
433 trans[i].data += BASE_PAGE_SIZE;
434 }
435 }
436 }
437 phys_page = __pa(prompmd);
438 obp_iaddr_patch[0] |= (phys_page >> 10);
439 obp_iaddr_patch[1] |= (phys_page & 0x3ff);
440 flushi((long)&obp_iaddr_patch[0]);
441 obp_daddr_patch[0] |= (phys_page >> 10);
442 obp_daddr_patch[1] |= (phys_page & 0x3ff);
443 flushi((long)&obp_daddr_patch[0]);
444 433
445 /* Now fixup OBP's idea about where we really are mapped. */ 434 /* Clear diag TTE bits. */
446 prom_printf("Remapping the kernel... "); 435 if (tlb_type == spitfire)
436 val &= ~0x0003fe0000000000UL;
447 437
448 /* Spitfire Errata #32 workaround */ 438 store_phys64(pte_phys, val | _PAGE_MODIFIED);
449 /* NOTE: Using plain zero for the context value is
450 * correct here, we are not using the Linux trap
451 * tables yet so we should not use the special
452 * UltraSPARC-III+ page size encodings yet.
453 */
454 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
455 "flush %%g6"
456 : /* No outputs */
457 : "r" (0), "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
458
459 switch (tlb_type) {
460 default:
461 case spitfire:
462 phys_page = spitfire_get_dtlb_data(sparc64_highest_locked_tlbent());
463 break;
464
465 case cheetah:
466 case cheetah_plus:
467 phys_page = cheetah_get_litlb_data(sparc64_highest_locked_tlbent());
468 break;
469 };
470
471 phys_page &= _PAGE_PADDR;
472 phys_page += ((unsigned long)&prom_boot_page -
473 (unsigned long)KERNBASE);
474 439
475 if (tlb_type == spitfire) { 440 data += BASE_PAGE_SIZE;
476 /* Lock this into i/d tlb entry 59 */
477 __asm__ __volatile__(
478 "stxa %%g0, [%2] %3\n\t"
479 "stxa %0, [%1] %4\n\t"
480 "membar #Sync\n\t"
481 "flush %%g6\n\t"
482 "stxa %%g0, [%2] %5\n\t"
483 "stxa %0, [%1] %6\n\t"
484 "membar #Sync\n\t"
485 "flush %%g6"
486 : : "r" (phys_page | _PAGE_VALID | _PAGE_SZ8K | _PAGE_CP |
487 _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W),
488 "r" (59 << 3), "r" (TLB_TAG_ACCESS),
489 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS),
490 "i" (ASI_IMMU), "i" (ASI_ITLB_DATA_ACCESS)
491 : "memory");
492 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
493 /* Lock this into i/d tlb-0 entry 11 */
494 __asm__ __volatile__(
495 "stxa %%g0, [%2] %3\n\t"
496 "stxa %0, [%1] %4\n\t"
497 "membar #Sync\n\t"
498 "flush %%g6\n\t"
499 "stxa %%g0, [%2] %5\n\t"
500 "stxa %0, [%1] %6\n\t"
501 "membar #Sync\n\t"
502 "flush %%g6"
503 : : "r" (phys_page | _PAGE_VALID | _PAGE_SZ8K | _PAGE_CP |
504 _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W),
505 "r" ((0 << 16) | (11 << 3)), "r" (TLB_TAG_ACCESS),
506 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS),
507 "i" (ASI_IMMU), "i" (ASI_ITLB_DATA_ACCESS)
508 : "memory");
509 } else {
510 /* Implement me :-) */
511 BUG();
512 } 441 }
442}
513 443
514 tte_vaddr = (unsigned long) KERNBASE; 444static inline int in_obp_range(unsigned long vaddr)
445{
446 return (vaddr >= LOW_OBP_ADDRESS &&
447 vaddr < HI_OBP_ADDRESS);
448}
515 449
516 /* Spitfire Errata #32 workaround */ 450#define OBP_PMD_SIZE 2048
517 /* NOTE: Using plain zero for the context value is 451static void __init build_obp_pgtable(int prom_trans_ents)
518 * correct here, we are not using the Linux trap 452{
519 * tables yet so we should not use the special 453 unsigned long i;
520 * UltraSPARC-III+ page size encodings yet.
521 */
522 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
523 "flush %%g6"
524 : /* No outputs */
525 : "r" (0),
526 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
527
528 if (tlb_type == spitfire)
529 tte_data = spitfire_get_dtlb_data(sparc64_highest_locked_tlbent());
530 else
531 tte_data = cheetah_get_ldtlb_data(sparc64_highest_locked_tlbent());
532 454
533 kern_locked_tte_data = tte_data; 455 prom_pmd_phys = early_alloc_phys(OBP_PMD_SIZE);
456 for (i = 0; i < OBP_PMD_SIZE; i += 4)
457 store_phys32(prom_pmd_phys + i, 0);
458
459 for (i = 0; i < prom_trans_ents; i++) {
460 unsigned long start, end;
534 461
535 remap_func = (void *) ((unsigned long) &prom_remap - 462 if (!in_obp_range(prom_trans[i].virt))
536 (unsigned long) &prom_boot_page); 463 continue;
537 464
465 start = prom_trans[i].virt;
466 end = start + prom_trans[i].size;
467 if (end > HI_OBP_ADDRESS)
468 end = HI_OBP_ADDRESS;
538 469
539 /* Spitfire Errata #32 workaround */ 470 build_obp_range(start, end, prom_trans[i].data);
540 /* NOTE: Using plain zero for the context value is
541 * correct here, we are not using the Linux trap
542 * tables yet so we should not use the special
543 * UltraSPARC-III+ page size encodings yet.
544 */
545 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
546 "flush %%g6"
547 : /* No outputs */
548 : "r" (0),
549 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
550
551 remap_func((tlb_type == spitfire ?
552 (spitfire_get_dtlb_data(sparc64_highest_locked_tlbent()) & _PAGE_PADDR) :
553 (cheetah_get_litlb_data(sparc64_highest_locked_tlbent()) & _PAGE_PADDR)),
554 (unsigned long) KERNBASE,
555 prom_get_mmu_ihandle());
556
557 if (bigkernel)
558 remap_func(((tte_data + 0x400000) & _PAGE_PADDR),
559 (unsigned long) KERNBASE + 0x400000, prom_get_mmu_ihandle());
560
561 /* Flush out that temporary mapping. */
562 spitfire_flush_dtlb_nucleus_page(0x0);
563 spitfire_flush_itlb_nucleus_page(0x0);
564
565 /* Now lock us back into the TLBs via OBP. */
566 prom_dtlb_load(sparc64_highest_locked_tlbent(), tte_data, tte_vaddr);
567 prom_itlb_load(sparc64_highest_locked_tlbent(), tte_data, tte_vaddr);
568 if (bigkernel) {
569 prom_dtlb_load(sparc64_highest_locked_tlbent()-1, tte_data + 0x400000,
570 tte_vaddr + 0x400000);
571 prom_itlb_load(sparc64_highest_locked_tlbent()-1, tte_data + 0x400000,
572 tte_vaddr + 0x400000);
573 } 471 }
472}
574 473
575 /* Re-read translations property. */ 474/* Read OBP translations property into 'prom_trans[]'.
576 if ((n = prom_getproperty(node, "translations", (char *)trans, tsz)) == -1) { 475 * Return the number of entries.
577 prom_printf("Couldn't get translation property\n"); 476 */
477static int __init read_obp_translations(void)
478{
479 int n, node;
480
481 node = prom_finddevice("/virtual-memory");
482 n = prom_getproplen(node, "translations");
483 if (unlikely(n == 0 || n == -1)) {
484 prom_printf("prom_mappings: Couldn't get size.\n");
485 prom_halt();
486 }
487 if (unlikely(n > sizeof(prom_trans))) {
488 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
578 prom_halt(); 489 prom_halt();
579 } 490 }
580 n = n / sizeof(*trans);
581 491
582 for (i = 0; i < n; i++) { 492 if ((n = prom_getproperty(node, "translations",
583 unsigned long vaddr = trans[i].virt; 493 (char *)&prom_trans[0],
584 unsigned long size = trans[i].size; 494 sizeof(prom_trans))) == -1) {
495 prom_printf("prom_mappings: Couldn't get property.\n");
496 prom_halt();
497 }
498 n = n / sizeof(struct linux_prom_translation);
499 return n;
500}
585 501
586 if (vaddr < 0xf0000000UL) { 502static void __init remap_kernel(void)
587 unsigned long avoid_start = (unsigned long) KERNBASE; 503{
588 unsigned long avoid_end = avoid_start + (4 * 1024 * 1024); 504 unsigned long phys_page, tte_vaddr, tte_data;
505 int tlb_ent = sparc64_highest_locked_tlbent();
589 506
590 if (bigkernel) 507 tte_vaddr = (unsigned long) KERNBASE;
591 avoid_end += (4 * 1024 * 1024); 508 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
592 if (vaddr < avoid_start) { 509 tte_data = (phys_page | (_PAGE_VALID | _PAGE_SZ4MB |
593 unsigned long top = vaddr + size; 510 _PAGE_CP | _PAGE_CV | _PAGE_P |
511 _PAGE_L | _PAGE_W));
594 512
595 if (top > avoid_start) 513 kern_locked_tte_data = tte_data;
596 top = avoid_start;
597 prom_unmap(top - vaddr, vaddr);
598 }
599 if ((vaddr + size) > avoid_end) {
600 unsigned long bottom = vaddr;
601 514
602 if (bottom < avoid_end) 515 /* Now lock us into the TLBs via OBP. */
603 bottom = avoid_end; 516 prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
604 prom_unmap((vaddr + size) - bottom, bottom); 517 prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
605 } 518 if (bigkernel) {
606 } 519 prom_dtlb_load(tlb_ent - 1,
520 tte_data + 0x400000,
521 tte_vaddr + 0x400000);
522 prom_itlb_load(tlb_ent - 1,
523 tte_data + 0x400000,
524 tte_vaddr + 0x400000);
607 } 525 }
526}
527
528static void __init inherit_prom_mappings(void)
529{
530 int n;
531
532 n = read_obp_translations();
533 build_obp_pgtable(n);
534
535 /* Now fixup OBP's idea about where we really are mapped. */
536 prom_printf("Remapping the kernel... ");
537 remap_kernel();
608 538
609 prom_printf("done.\n"); 539 prom_printf("done.\n");
610 540
@@ -1347,8 +1277,6 @@ unsigned long __init bootmem_init(unsigned long *pages_avail)
1347#endif 1277#endif
1348 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn); 1278 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
1349 1279
1350 bootmap_base = bootmap_pfn << PAGE_SHIFT;
1351
1352 /* Now register the available physical memory with the 1280 /* Now register the available physical memory with the
1353 * allocator. 1281 * allocator.
1354 */ 1282 */
@@ -1398,120 +1326,142 @@ unsigned long __init bootmem_init(unsigned long *pages_avail)
1398 return end_pfn; 1326 return end_pfn;
1399} 1327}
1400 1328
1329#ifdef CONFIG_DEBUG_PAGEALLOC
1330static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
1331{
1332 unsigned long vstart = PAGE_OFFSET + pstart;
1333 unsigned long vend = PAGE_OFFSET + pend;
1334 unsigned long alloc_bytes = 0UL;
1335
1336 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1337 prom_printf("kernel_map: Unaligned sp_banks[%lx:%lx]\n",
1338 vstart, vend);
1339 prom_halt();
1340 }
1341
1342 while (vstart < vend) {
1343 unsigned long this_end, paddr = __pa(vstart);
1344 pgd_t *pgd = pgd_offset_k(vstart);
1345 pud_t *pud;
1346 pmd_t *pmd;
1347 pte_t *pte;
1348
1349 pud = pud_offset(pgd, vstart);
1350 if (pud_none(*pud)) {
1351 pmd_t *new;
1352
1353 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1354 alloc_bytes += PAGE_SIZE;
1355 pud_populate(&init_mm, pud, new);
1356 }
1357
1358 pmd = pmd_offset(pud, vstart);
1359 if (!pmd_present(*pmd)) {
1360 pte_t *new;
1361
1362 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1363 alloc_bytes += PAGE_SIZE;
1364 pmd_populate_kernel(&init_mm, pmd, new);
1365 }
1366
1367 pte = pte_offset_kernel(pmd, vstart);
1368 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1369 if (this_end > vend)
1370 this_end = vend;
1371
1372 while (vstart < this_end) {
1373 pte_val(*pte) = (paddr | pgprot_val(prot));
1374
1375 vstart += PAGE_SIZE;
1376 paddr += PAGE_SIZE;
1377 pte++;
1378 }
1379 }
1380
1381 return alloc_bytes;
1382}
1383
1384extern struct linux_mlist_p1275 *prom_ptot_ptr;
1385extern unsigned int kvmap_linear_patch[1];
1386
1387static void __init kernel_physical_mapping_init(void)
1388{
1389 struct linux_mlist_p1275 *p = prom_ptot_ptr;
1390 unsigned long mem_alloced = 0UL;
1391
1392 while (p) {
1393 unsigned long phys_start, phys_end;
1394
1395 phys_start = p->start_adr;
1396 phys_end = phys_start + p->num_bytes;
1397 mem_alloced += kernel_map_range(phys_start, phys_end,
1398 PAGE_KERNEL);
1399
1400 p = p->theres_more;
1401 }
1402
1403 printk("Allocated %ld bytes for kernel page tables.\n",
1404 mem_alloced);
1405
1406 kvmap_linear_patch[0] = 0x01000000; /* nop */
1407 flushi(&kvmap_linear_patch[0]);
1408
1409 __flush_tlb_all();
1410}
1411
1412void kernel_map_pages(struct page *page, int numpages, int enable)
1413{
1414 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1415 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1416
1417 kernel_map_range(phys_start, phys_end,
1418 (enable ? PAGE_KERNEL : __pgprot(0)));
1419
1420 /* we should perform an IPI and flush all tlbs,
1421 * but that can deadlock->flush only current cpu.
1422 */
1423 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1424 PAGE_OFFSET + phys_end);
1425}
1426#endif
1427
1401/* paging_init() sets up the page tables */ 1428/* paging_init() sets up the page tables */
1402 1429
1403extern void cheetah_ecache_flush_init(void); 1430extern void cheetah_ecache_flush_init(void);
1404 1431
1405static unsigned long last_valid_pfn; 1432static unsigned long last_valid_pfn;
1433pgd_t swapper_pg_dir[2048];
1406 1434
1407void __init paging_init(void) 1435void __init paging_init(void)
1408{ 1436{
1409 extern pmd_t swapper_pmd_dir[1024]; 1437 unsigned long end_pfn, pages_avail, shift;
1410 extern unsigned int sparc64_vpte_patchme1[1];
1411 extern unsigned int sparc64_vpte_patchme2[1];
1412 unsigned long alias_base = kern_base + PAGE_OFFSET;
1413 unsigned long second_alias_page = 0;
1414 unsigned long pt, flags, end_pfn, pages_avail;
1415 unsigned long shift = alias_base - ((unsigned long)KERNBASE);
1416 unsigned long real_end; 1438 unsigned long real_end;
1417 1439
1418 set_bit(0, mmu_context_bmap); 1440 set_bit(0, mmu_context_bmap);
1419 1441
1442 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1443
1420 real_end = (unsigned long)_end; 1444 real_end = (unsigned long)_end;
1421 if ((real_end > ((unsigned long)KERNBASE + 0x400000))) 1445 if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1422 bigkernel = 1; 1446 bigkernel = 1;
1423#ifdef CONFIG_BLK_DEV_INITRD 1447 if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1424 if (sparc_ramdisk_image || sparc_ramdisk_image64) 1448 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1425 real_end = (PAGE_ALIGN(real_end) + PAGE_ALIGN(sparc_ramdisk_size)); 1449 prom_halt();
1426#endif
1427
1428 /* We assume physical memory starts at some 4mb multiple,
1429 * if this were not true we wouldn't boot up to this point
1430 * anyways.
1431 */
1432 pt = kern_base | _PAGE_VALID | _PAGE_SZ4MB;
1433 pt |= _PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W;
1434 local_irq_save(flags);
1435 if (tlb_type == spitfire) {
1436 __asm__ __volatile__(
1437 " stxa %1, [%0] %3\n"
1438 " stxa %2, [%5] %4\n"
1439 " membar #Sync\n"
1440 " flush %%g6\n"
1441 " nop\n"
1442 " nop\n"
1443 " nop\n"
1444 : /* No outputs */
1445 : "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt),
1446 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (61 << 3)
1447 : "memory");
1448 if (real_end >= KERNBASE + 0x340000) {
1449 second_alias_page = alias_base + 0x400000;
1450 __asm__ __volatile__(
1451 " stxa %1, [%0] %3\n"
1452 " stxa %2, [%5] %4\n"
1453 " membar #Sync\n"
1454 " flush %%g6\n"
1455 " nop\n"
1456 " nop\n"
1457 " nop\n"
1458 : /* No outputs */
1459 : "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000),
1460 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (60 << 3)
1461 : "memory");
1462 }
1463 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1464 __asm__ __volatile__(
1465 " stxa %1, [%0] %3\n"
1466 " stxa %2, [%5] %4\n"
1467 " membar #Sync\n"
1468 " flush %%g6\n"
1469 " nop\n"
1470 " nop\n"
1471 " nop\n"
1472 : /* No outputs */
1473 : "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt),
1474 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" ((0<<16) | (13<<3))
1475 : "memory");
1476 if (real_end >= KERNBASE + 0x340000) {
1477 second_alias_page = alias_base + 0x400000;
1478 __asm__ __volatile__(
1479 " stxa %1, [%0] %3\n"
1480 " stxa %2, [%5] %4\n"
1481 " membar #Sync\n"
1482 " flush %%g6\n"
1483 " nop\n"
1484 " nop\n"
1485 " nop\n"
1486 : /* No outputs */
1487 : "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000),
1488 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" ((0<<16) | (12<<3))
1489 : "memory");
1490 }
1491 } 1450 }
1492 local_irq_restore(flags); 1451
1493 1452 /* Set kernel pgd to upper alias so physical page computations
1494 /* Now set kernel pgd to upper alias so physical page computations
1495 * work. 1453 * work.
1496 */ 1454 */
1497 init_mm.pgd += ((shift) / (sizeof(pgd_t))); 1455 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1498 1456
1499 memset(swapper_pmd_dir, 0, sizeof(swapper_pmd_dir)); 1457 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1500 1458
1501 /* Now can init the kernel/bad page tables. */ 1459 /* Now can init the kernel/bad page tables. */
1502 pud_set(pud_offset(&swapper_pg_dir[0], 0), 1460 pud_set(pud_offset(&swapper_pg_dir[0], 0),
1503 swapper_pmd_dir + (shift / sizeof(pgd_t))); 1461 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1504 1462
1505 sparc64_vpte_patchme1[0] |= 1463 swapper_pgd_zero = pgd_val(swapper_pg_dir[0]);
1506 (((unsigned long)pgd_val(init_mm.pgd[0])) >> 10);
1507 sparc64_vpte_patchme2[0] |=
1508 (((unsigned long)pgd_val(init_mm.pgd[0])) & 0x3ff);
1509 flushi((long)&sparc64_vpte_patchme1[0]);
1510 1464
1511 /* Setup bootmem... */
1512 pages_avail = 0;
1513 last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1514
1515 /* Inherit non-locked OBP mappings. */ 1465 /* Inherit non-locked OBP mappings. */
1516 inherit_prom_mappings(); 1466 inherit_prom_mappings();
1517 1467
@@ -1527,13 +1477,16 @@ void __init paging_init(void)
1527 1477
1528 inherit_locked_prom_mappings(1); 1478 inherit_locked_prom_mappings(1);
1529 1479
1530 /* We only created DTLB mapping of this stuff. */
1531 spitfire_flush_dtlb_nucleus_page(alias_base);
1532 if (second_alias_page)
1533 spitfire_flush_dtlb_nucleus_page(second_alias_page);
1534
1535 __flush_tlb_all(); 1480 __flush_tlb_all();
1536 1481
1482 /* Setup bootmem... */
1483 pages_avail = 0;
1484 last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1485
1486#ifdef CONFIG_DEBUG_PAGEALLOC
1487 kernel_physical_mapping_init();
1488#endif
1489
1537 { 1490 {
1538 unsigned long zones_size[MAX_NR_ZONES]; 1491 unsigned long zones_size[MAX_NR_ZONES];
1539 unsigned long zholes_size[MAX_NR_ZONES]; 1492 unsigned long zholes_size[MAX_NR_ZONES];
@@ -1695,8 +1648,7 @@ void __init mem_init(void)
1695 1648
1696 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6); 1649 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1697 i += 1; 1650 i += 1;
1698 sparc64_valid_addr_bitmap = (unsigned long *) 1651 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1699 __alloc_bootmem(i << 3, SMP_CACHE_BYTES, bootmap_base);
1700 if (sparc64_valid_addr_bitmap == NULL) { 1652 if (sparc64_valid_addr_bitmap == NULL) {
1701 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n"); 1653 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1702 prom_halt(); 1654 prom_halt();
@@ -1749,7 +1701,7 @@ void __init mem_init(void)
1749 cheetah_ecache_flush_init(); 1701 cheetah_ecache_flush_init();
1750} 1702}
1751 1703
1752void free_initmem (void) 1704void free_initmem(void)
1753{ 1705{
1754 unsigned long addr, initend; 1706 unsigned long addr, initend;
1755 1707
diff --git a/arch/sparc64/mm/ultra.S b/arch/sparc64/mm/ultra.S
index b2ee9b53227f..058b8126c1a7 100644
--- a/arch/sparc64/mm/ultra.S
+++ b/arch/sparc64/mm/ultra.S
@@ -144,42 +144,29 @@ __flush_icache_page: /* %o0 = phys_page */
144 144
145#define DTAG_MASK 0x3 145#define DTAG_MASK 0x3
146 146
147 /* This routine is Spitfire specific so the hardcoded
148 * D-cache size and line-size are OK.
149 */
147 .align 64 150 .align 64
148 .globl __flush_dcache_page 151 .globl __flush_dcache_page
149__flush_dcache_page: /* %o0=kaddr, %o1=flush_icache */ 152__flush_dcache_page: /* %o0=kaddr, %o1=flush_icache */
150 sethi %uhi(PAGE_OFFSET), %g1 153 sethi %uhi(PAGE_OFFSET), %g1
151 sllx %g1, 32, %g1 154 sllx %g1, 32, %g1
152 sub %o0, %g1, %o0 155 sub %o0, %g1, %o0 ! physical address
153 clr %o4 156 srlx %o0, 11, %o0 ! make D-cache TAG
154 srlx %o0, 11, %o0 157 sethi %hi(1 << 14), %o2 ! D-cache size
155 sethi %hi(1 << 14), %o2 158 sub %o2, (1 << 5), %o2 ! D-cache line size
1561: ldxa [%o4] ASI_DCACHE_TAG, %o3 ! LSU Group 1591: ldxa [%o2] ASI_DCACHE_TAG, %o3 ! load D-cache TAG
157 add %o4, (1 << 5), %o4 ! IEU0 160 andcc %o3, DTAG_MASK, %g0 ! Valid?
158 ldxa [%o4] ASI_DCACHE_TAG, %g1 ! LSU Group 161 be,pn %xcc, 2f ! Nope, branch
159 add %o4, (1 << 5), %o4 ! IEU0 162 andn %o3, DTAG_MASK, %o3 ! Clear valid bits
160 ldxa [%o4] ASI_DCACHE_TAG, %g2 ! LSU Group o3 available 163 cmp %o3, %o0 ! TAG match?
161 add %o4, (1 << 5), %o4 ! IEU0 164 bne,pt %xcc, 2f ! Nope, branch
162 andn %o3, DTAG_MASK, %o3 ! IEU1 165 nop
163 ldxa [%o4] ASI_DCACHE_TAG, %g3 ! LSU Group 166 stxa %g0, [%o2] ASI_DCACHE_TAG ! Invalidate TAG
164 add %o4, (1 << 5), %o4 ! IEU0 167 membar #Sync
165 andn %g1, DTAG_MASK, %g1 ! IEU1 1682: brnz,pt %o2, 1b
166 cmp %o0, %o3 ! IEU1 Group 169 sub %o2, (1 << 5), %o2 ! D-cache line size
167 be,a,pn %xcc, dflush1 ! CTI
168 sub %o4, (4 << 5), %o4 ! IEU0 (Group)
169 cmp %o0, %g1 ! IEU1 Group
170 andn %g2, DTAG_MASK, %g2 ! IEU0
171 be,a,pn %xcc, dflush2 ! CTI
172 sub %o4, (3 << 5), %o4 ! IEU0 (Group)
173 cmp %o0, %g2 ! IEU1 Group
174 andn %g3, DTAG_MASK, %g3 ! IEU0
175 be,a,pn %xcc, dflush3 ! CTI
176 sub %o4, (2 << 5), %o4 ! IEU0 (Group)
177 cmp %o0, %g3 ! IEU1 Group
178 be,a,pn %xcc, dflush4 ! CTI
179 sub %o4, (1 << 5), %o4 ! IEU0
1802: cmp %o4, %o2 ! IEU1 Group
181 bne,pt %xcc, 1b ! CTI
182 nop ! IEU0
183 170
184 /* The I-cache does not snoop local stores so we 171 /* The I-cache does not snoop local stores so we
185 * better flush that too when necessary. 172 * better flush that too when necessary.
@@ -189,48 +176,9 @@ __flush_dcache_page: /* %o0=kaddr, %o1=flush_icache */
189 retl 176 retl
190 nop 177 nop
191 178
192dflush1:stxa %g0, [%o4] ASI_DCACHE_TAG
193 add %o4, (1 << 5), %o4
194dflush2:stxa %g0, [%o4] ASI_DCACHE_TAG
195 add %o4, (1 << 5), %o4
196dflush3:stxa %g0, [%o4] ASI_DCACHE_TAG
197 add %o4, (1 << 5), %o4
198dflush4:stxa %g0, [%o4] ASI_DCACHE_TAG
199 add %o4, (1 << 5), %o4
200 membar #Sync
201 ba,pt %xcc, 2b
202 nop
203#endif /* DCACHE_ALIASING_POSSIBLE */ 179#endif /* DCACHE_ALIASING_POSSIBLE */
204 180
205 .previous .text 181 .previous
206 .align 32
207__prefill_dtlb:
208 rdpr %pstate, %g7
209 wrpr %g7, PSTATE_IE, %pstate
210 mov TLB_TAG_ACCESS, %g1
211 stxa %o5, [%g1] ASI_DMMU
212 stxa %o2, [%g0] ASI_DTLB_DATA_IN
213 flush %g6
214 retl
215 wrpr %g7, %pstate
216__prefill_itlb:
217 rdpr %pstate, %g7
218 wrpr %g7, PSTATE_IE, %pstate
219 mov TLB_TAG_ACCESS, %g1
220 stxa %o5, [%g1] ASI_IMMU
221 stxa %o2, [%g0] ASI_ITLB_DATA_IN
222 flush %g6
223 retl
224 wrpr %g7, %pstate
225
226 .globl __update_mmu_cache
227__update_mmu_cache: /* %o0=hw_context, %o1=address, %o2=pte, %o3=fault_code */
228 srlx %o1, PAGE_SHIFT, %o1
229 andcc %o3, FAULT_CODE_DTLB, %g0
230 sllx %o1, PAGE_SHIFT, %o5
231 bne,pt %xcc, __prefill_dtlb
232 or %o5, %o0, %o5
233 ba,a,pt %xcc, __prefill_itlb
234 182
235 /* Cheetah specific versions, patched at boot time. */ 183 /* Cheetah specific versions, patched at boot time. */
236__cheetah_flush_tlb_mm: /* 18 insns */ 184__cheetah_flush_tlb_mm: /* 18 insns */
@@ -283,7 +231,7 @@ __cheetah_flush_tlb_pending: /* 26 insns */
283 wrpr %g7, 0x0, %pstate 231 wrpr %g7, 0x0, %pstate
284 232
285#ifdef DCACHE_ALIASING_POSSIBLE 233#ifdef DCACHE_ALIASING_POSSIBLE
286flush_dcpage_cheetah: /* 11 insns */ 234__cheetah_flush_dcache_page: /* 11 insns */
287 sethi %uhi(PAGE_OFFSET), %g1 235 sethi %uhi(PAGE_OFFSET), %g1
288 sllx %g1, 32, %g1 236 sllx %g1, 32, %g1
289 sub %o0, %g1, %o0 237 sub %o0, %g1, %o0
@@ -329,8 +277,8 @@ cheetah_patch_cachetlbops:
329#ifdef DCACHE_ALIASING_POSSIBLE 277#ifdef DCACHE_ALIASING_POSSIBLE
330 sethi %hi(__flush_dcache_page), %o0 278 sethi %hi(__flush_dcache_page), %o0
331 or %o0, %lo(__flush_dcache_page), %o0 279 or %o0, %lo(__flush_dcache_page), %o0
332 sethi %hi(flush_dcpage_cheetah), %o1 280 sethi %hi(__cheetah_flush_dcache_page), %o1
333 or %o1, %lo(flush_dcpage_cheetah), %o1 281 or %o1, %lo(__cheetah_flush_dcache_page), %o1
334 call cheetah_patch_one 282 call cheetah_patch_one
335 mov 11, %o2 283 mov 11, %o2
336#endif /* DCACHE_ALIASING_POSSIBLE */ 284#endif /* DCACHE_ALIASING_POSSIBLE */
diff --git a/arch/sparc64/prom/Makefile b/arch/sparc64/prom/Makefile
index 8f2420d9e9e6..c7898a5ee456 100644
--- a/arch/sparc64/prom/Makefile
+++ b/arch/sparc64/prom/Makefile
@@ -7,4 +7,4 @@ EXTRA_AFLAGS := -ansi
7EXTRA_CFLAGS := -Werror 7EXTRA_CFLAGS := -Werror
8 8
9lib-y := bootstr.o devops.o init.o memory.o misc.o \ 9lib-y := bootstr.o devops.o init.o memory.o misc.o \
10 tree.o console.o printf.o p1275.o map.o cif.o 10 tree.o console.o printf.o p1275.o cif.o
diff --git a/arch/sparc64/prom/console.c b/arch/sparc64/prom/console.c
index 028a53fcb1ec..eae5db8dda56 100644
--- a/arch/sparc64/prom/console.c
+++ b/arch/sparc64/prom/console.c
@@ -67,7 +67,7 @@ prom_putchar(char c)
67} 67}
68 68
69void 69void
70prom_puts(char *s, int len) 70prom_puts(const char *s, int len)
71{ 71{
72 p1275_cmd("write", P1275_ARG(1,P1275_ARG_IN_BUF)| 72 p1275_cmd("write", P1275_ARG(1,P1275_ARG_IN_BUF)|
73 P1275_INOUT(3,1), 73 P1275_INOUT(3,1),
diff --git a/arch/sparc64/prom/devops.c b/arch/sparc64/prom/devops.c
index 2c99b21b6981..4641839eb39a 100644
--- a/arch/sparc64/prom/devops.c
+++ b/arch/sparc64/prom/devops.c
@@ -16,7 +16,7 @@
16 * Returns 0 on failure. 16 * Returns 0 on failure.
17 */ 17 */
18int 18int
19prom_devopen(char *dstr) 19prom_devopen(const char *dstr)
20{ 20{
21 return p1275_cmd ("open", P1275_ARG(0,P1275_ARG_IN_STRING)| 21 return p1275_cmd ("open", P1275_ARG(0,P1275_ARG_IN_STRING)|
22 P1275_INOUT(1,1), 22 P1275_INOUT(1,1),
diff --git a/arch/sparc64/prom/init.c b/arch/sparc64/prom/init.c
index 817faae058cd..8b4b622d0909 100644
--- a/arch/sparc64/prom/init.c
+++ b/arch/sparc64/prom/init.c
@@ -46,7 +46,7 @@ void __init prom_init(void *cif_handler, void *cif_stack)
46 if((prom_root_node == 0) || (prom_root_node == -1)) 46 if((prom_root_node == 0) || (prom_root_node == -1))
47 prom_halt(); 47 prom_halt();
48 48
49 prom_chosen_node = prom_finddevice("/chosen"); 49 prom_chosen_node = prom_finddevice(prom_chosen_path);
50 if (!prom_chosen_node || prom_chosen_node == -1) 50 if (!prom_chosen_node || prom_chosen_node == -1)
51 prom_halt(); 51 prom_halt();
52 52
diff --git a/arch/sparc64/prom/map.S b/arch/sparc64/prom/map.S
deleted file mode 100644
index 21b3f9c99ea7..000000000000
--- a/arch/sparc64/prom/map.S
+++ /dev/null
@@ -1,72 +0,0 @@
1/* $Id: map.S,v 1.2 1999/11/19 05:53:02 davem Exp $
2 * map.S: Tricky coding required to fixup the kernel OBP maps
3 * properly.
4 *
5 * Copyright (C) 1999 David S. Miller (davem@redhat.com)
6 */
7
8 .text
9 .align 8192
10 .globl prom_boot_page
11prom_boot_page:
12call_method:
13 .asciz "call-method"
14 .align 8
15map:
16 .asciz "map"
17 .align 8
18
19 /* When we are invoked, our caller has remapped us to
20 * page zero, therefore we must use PC relative addressing
21 * for everything after we begin performing the unmap/map
22 * calls.
23 */
24 .globl prom_remap
25prom_remap: /* %o0 = physpage, %o1 = virtpage, %o2 = mmu_ihandle */
26 rd %pc, %g1
27 srl %o2, 0, %o2 ! kill sign extension
28 sethi %hi(p1275buf), %g2
29 or %g2, %lo(p1275buf), %g2
30 ldx [%g2 + 0x10], %g3 ! prom_cif_stack
31 save %g3, -(192 + 128), %sp
32 ldx [%g2 + 0x08], %l0 ! prom_cif_handler
33 mov %g6, %i3
34 mov %g4, %i4
35 mov %g5, %i5
36 flushw
37
38 sethi %hi(prom_remap - call_method), %g7
39 or %g7, %lo(prom_remap - call_method), %g7
40 sub %g1, %g7, %l2 ! call-method string
41 sethi %hi(prom_remap - map), %g7
42 or %g7, %lo(prom_remap - map), %g7
43 sub %g1, %g7, %l4 ! map string
44
45 /* OK, map the 4MB region we really live at. */
46 stx %l2, [%sp + 2047 + 128 + 0x00] ! call-method
47 mov 7, %l5
48 stx %l5, [%sp + 2047 + 128 + 0x08] ! num_args
49 mov 1, %l5
50 stx %l5, [%sp + 2047 + 128 + 0x10] ! num_rets
51 stx %l4, [%sp + 2047 + 128 + 0x18] ! map
52 stx %i2, [%sp + 2047 + 128 + 0x20] ! mmu_ihandle
53 mov -1, %l5
54 stx %l5, [%sp + 2047 + 128 + 0x28] ! mode == default
55 sethi %hi(4 * 1024 * 1024), %l5
56 stx %l5, [%sp + 2047 + 128 + 0x30] ! size
57 stx %i1, [%sp + 2047 + 128 + 0x38] ! vaddr
58 stx %g0, [%sp + 2047 + 128 + 0x40] ! filler
59 stx %i0, [%sp + 2047 + 128 + 0x48] ! paddr
60 call %l0
61 add %sp, (2047 + 128), %o0 ! argument array
62
63 /* Restore hard-coded globals. */
64 mov %i3, %g6
65 mov %i4, %g4
66 mov %i5, %g5
67
68 /* Wheee.... we are done. */
69 ret
70 restore
71
72 .align 8192
diff --git a/arch/sparc64/prom/misc.c b/arch/sparc64/prom/misc.c
index 19c44e97e9ee..9b895faf077b 100644
--- a/arch/sparc64/prom/misc.c
+++ b/arch/sparc64/prom/misc.c
@@ -17,14 +17,14 @@
17#include <asm/system.h> 17#include <asm/system.h>
18 18
19/* Reset and reboot the machine with the command 'bcommand'. */ 19/* Reset and reboot the machine with the command 'bcommand'. */
20void prom_reboot(char *bcommand) 20void prom_reboot(const char *bcommand)
21{ 21{
22 p1275_cmd("boot", P1275_ARG(0, P1275_ARG_IN_STRING) | 22 p1275_cmd("boot", P1275_ARG(0, P1275_ARG_IN_STRING) |
23 P1275_INOUT(1, 0), bcommand); 23 P1275_INOUT(1, 0), bcommand);
24} 24}
25 25
26/* Forth evaluate the expression contained in 'fstring'. */ 26/* Forth evaluate the expression contained in 'fstring'. */
27void prom_feval(char *fstring) 27void prom_feval(const char *fstring)
28{ 28{
29 if (!fstring || fstring[0] == 0) 29 if (!fstring || fstring[0] == 0)
30 return; 30 return;
@@ -148,21 +148,19 @@ void prom_set_trap_table(unsigned long tba)
148 p1275_cmd("SUNW,set-trap-table", P1275_INOUT(1, 0), tba); 148 p1275_cmd("SUNW,set-trap-table", P1275_INOUT(1, 0), tba);
149} 149}
150 150
151int mmu_ihandle_cache = 0;
152
153int prom_get_mmu_ihandle(void) 151int prom_get_mmu_ihandle(void)
154{ 152{
155 int node, ret; 153 int node, ret;
156 154
157 if (mmu_ihandle_cache != 0) 155 if (prom_mmu_ihandle_cache != 0)
158 return mmu_ihandle_cache; 156 return prom_mmu_ihandle_cache;
159 157
160 node = prom_finddevice("/chosen"); 158 node = prom_finddevice(prom_chosen_path);
161 ret = prom_getint(node, "mmu"); 159 ret = prom_getint(node, prom_mmu_name);
162 if (ret == -1 || ret == 0) 160 if (ret == -1 || ret == 0)
163 mmu_ihandle_cache = -1; 161 prom_mmu_ihandle_cache = -1;
164 else 162 else
165 mmu_ihandle_cache = ret; 163 prom_mmu_ihandle_cache = ret;
166 164
167 return ret; 165 return ret;
168} 166}
@@ -190,7 +188,7 @@ long prom_itlb_load(unsigned long index,
190 unsigned long tte_data, 188 unsigned long tte_data,
191 unsigned long vaddr) 189 unsigned long vaddr)
192{ 190{
193 return p1275_cmd("call-method", 191 return p1275_cmd(prom_callmethod_name,
194 (P1275_ARG(0, P1275_ARG_IN_STRING) | 192 (P1275_ARG(0, P1275_ARG_IN_STRING) |
195 P1275_ARG(2, P1275_ARG_IN_64B) | 193 P1275_ARG(2, P1275_ARG_IN_64B) |
196 P1275_ARG(3, P1275_ARG_IN_64B) | 194 P1275_ARG(3, P1275_ARG_IN_64B) |
@@ -207,7 +205,7 @@ long prom_dtlb_load(unsigned long index,
207 unsigned long tte_data, 205 unsigned long tte_data,
208 unsigned long vaddr) 206 unsigned long vaddr)
209{ 207{
210 return p1275_cmd("call-method", 208 return p1275_cmd(prom_callmethod_name,
211 (P1275_ARG(0, P1275_ARG_IN_STRING) | 209 (P1275_ARG(0, P1275_ARG_IN_STRING) |
212 P1275_ARG(2, P1275_ARG_IN_64B) | 210 P1275_ARG(2, P1275_ARG_IN_64B) |
213 P1275_ARG(3, P1275_ARG_IN_64B) | 211 P1275_ARG(3, P1275_ARG_IN_64B) |
@@ -223,13 +221,13 @@ long prom_dtlb_load(unsigned long index,
223int prom_map(int mode, unsigned long size, 221int prom_map(int mode, unsigned long size,
224 unsigned long vaddr, unsigned long paddr) 222 unsigned long vaddr, unsigned long paddr)
225{ 223{
226 int ret = p1275_cmd("call-method", 224 int ret = p1275_cmd(prom_callmethod_name,
227 (P1275_ARG(0, P1275_ARG_IN_STRING) | 225 (P1275_ARG(0, P1275_ARG_IN_STRING) |
228 P1275_ARG(3, P1275_ARG_IN_64B) | 226 P1275_ARG(3, P1275_ARG_IN_64B) |
229 P1275_ARG(4, P1275_ARG_IN_64B) | 227 P1275_ARG(4, P1275_ARG_IN_64B) |
230 P1275_ARG(6, P1275_ARG_IN_64B) | 228 P1275_ARG(6, P1275_ARG_IN_64B) |
231 P1275_INOUT(7, 1)), 229 P1275_INOUT(7, 1)),
232 "map", 230 prom_map_name,
233 prom_get_mmu_ihandle(), 231 prom_get_mmu_ihandle(),
234 mode, 232 mode,
235 size, 233 size,
@@ -244,12 +242,12 @@ int prom_map(int mode, unsigned long size,
244 242
245void prom_unmap(unsigned long size, unsigned long vaddr) 243void prom_unmap(unsigned long size, unsigned long vaddr)
246{ 244{
247 p1275_cmd("call-method", 245 p1275_cmd(prom_callmethod_name,
248 (P1275_ARG(0, P1275_ARG_IN_STRING) | 246 (P1275_ARG(0, P1275_ARG_IN_STRING) |
249 P1275_ARG(2, P1275_ARG_IN_64B) | 247 P1275_ARG(2, P1275_ARG_IN_64B) |
250 P1275_ARG(3, P1275_ARG_IN_64B) | 248 P1275_ARG(3, P1275_ARG_IN_64B) |
251 P1275_INOUT(4, 0)), 249 P1275_INOUT(4, 0)),
252 "unmap", 250 prom_unmap_name,
253 prom_get_mmu_ihandle(), 251 prom_get_mmu_ihandle(),
254 size, 252 size,
255 vaddr); 253 vaddr);
@@ -258,7 +256,7 @@ void prom_unmap(unsigned long size, unsigned long vaddr)
258/* Set aside physical memory which is not touched or modified 256/* Set aside physical memory which is not touched or modified
259 * across soft resets. 257 * across soft resets.
260 */ 258 */
261unsigned long prom_retain(char *name, 259unsigned long prom_retain(const char *name,
262 unsigned long pa_low, unsigned long pa_high, 260 unsigned long pa_low, unsigned long pa_high,
263 long size, long align) 261 long size, long align)
264{ 262{
@@ -290,7 +288,7 @@ int prom_getunumber(int syndrome_code,
290 unsigned long phys_addr, 288 unsigned long phys_addr,
291 char *buf, int buflen) 289 char *buf, int buflen)
292{ 290{
293 return p1275_cmd("call-method", 291 return p1275_cmd(prom_callmethod_name,
294 (P1275_ARG(0, P1275_ARG_IN_STRING) | 292 (P1275_ARG(0, P1275_ARG_IN_STRING) |
295 P1275_ARG(3, P1275_ARG_OUT_BUF) | 293 P1275_ARG(3, P1275_ARG_OUT_BUF) |
296 P1275_ARG(6, P1275_ARG_IN_64B) | 294 P1275_ARG(6, P1275_ARG_IN_64B) |
diff --git a/arch/sparc64/prom/p1275.c b/arch/sparc64/prom/p1275.c
index 59fe38bba39e..a5a7c5712028 100644
--- a/arch/sparc64/prom/p1275.c
+++ b/arch/sparc64/prom/p1275.c
@@ -46,7 +46,7 @@ static inline unsigned long spitfire_get_primary_context(void)
46 */ 46 */
47DEFINE_SPINLOCK(prom_entry_lock); 47DEFINE_SPINLOCK(prom_entry_lock);
48 48
49long p1275_cmd (char *service, long fmt, ...) 49long p1275_cmd(const char *service, long fmt, ...)
50{ 50{
51 char *p, *q; 51 char *p, *q;
52 unsigned long flags; 52 unsigned long flags;
diff --git a/arch/sparc64/prom/printf.c b/arch/sparc64/prom/printf.c
index a6df82cafa0d..660943ee4c2a 100644
--- a/arch/sparc64/prom/printf.c
+++ b/arch/sparc64/prom/printf.c
@@ -34,7 +34,7 @@ prom_write(const char *buf, unsigned int n)
34} 34}
35 35
36void 36void
37prom_printf(char *fmt, ...) 37prom_printf(const char *fmt, ...)
38{ 38{
39 va_list args; 39 va_list args;
40 int i; 40 int i;
diff --git a/arch/sparc64/prom/tree.c b/arch/sparc64/prom/tree.c
index ccf73258ebf7..b1ff9e87dcc6 100644
--- a/arch/sparc64/prom/tree.c
+++ b/arch/sparc64/prom/tree.c
@@ -69,7 +69,7 @@ prom_getsibling(int node)
69 * Return -1 on error. 69 * Return -1 on error.
70 */ 70 */
71__inline__ int 71__inline__ int
72prom_getproplen(int node, char *prop) 72prom_getproplen(int node, const char *prop)
73{ 73{
74 if((!node) || (!prop)) return -1; 74 if((!node) || (!prop)) return -1;
75 return p1275_cmd ("getproplen", 75 return p1275_cmd ("getproplen",
@@ -83,20 +83,20 @@ prom_getproplen(int node, char *prop)
83 * was successful the length will be returned, else -1 is returned. 83 * was successful the length will be returned, else -1 is returned.
84 */ 84 */
85__inline__ int 85__inline__ int
86prom_getproperty(int node, char *prop, char *buffer, int bufsize) 86prom_getproperty(int node, const char *prop, char *buffer, int bufsize)
87{ 87{
88 int plen; 88 int plen;
89 89
90 plen = prom_getproplen(node, prop); 90 plen = prom_getproplen(node, prop);
91 if((plen > bufsize) || (plen == 0) || (plen == -1)) 91 if ((plen > bufsize) || (plen == 0) || (plen == -1)) {
92 return -1; 92 return -1;
93 else { 93 } else {
94 /* Ok, things seem all right. */ 94 /* Ok, things seem all right. */
95 return p1275_cmd ("getprop", 95 return p1275_cmd(prom_getprop_name,
96 P1275_ARG(1,P1275_ARG_IN_STRING)| 96 P1275_ARG(1,P1275_ARG_IN_STRING)|
97 P1275_ARG(2,P1275_ARG_OUT_BUF)| 97 P1275_ARG(2,P1275_ARG_OUT_BUF)|
98 P1275_INOUT(4, 1), 98 P1275_INOUT(4, 1),
99 node, prop, buffer, P1275_SIZE(plen)); 99 node, prop, buffer, P1275_SIZE(plen));
100 } 100 }
101} 101}
102 102
@@ -104,7 +104,7 @@ prom_getproperty(int node, char *prop, char *buffer, int bufsize)
104 * on failure. 104 * on failure.
105 */ 105 */
106__inline__ int 106__inline__ int
107prom_getint(int node, char *prop) 107prom_getint(int node, const char *prop)
108{ 108{
109 int intprop; 109 int intprop;
110 110
@@ -119,7 +119,7 @@ prom_getint(int node, char *prop)
119 */ 119 */
120 120
121int 121int
122prom_getintdefault(int node, char *property, int deflt) 122prom_getintdefault(int node, const char *property, int deflt)
123{ 123{
124 int retval; 124 int retval;
125 125
@@ -131,7 +131,7 @@ prom_getintdefault(int node, char *property, int deflt)
131 131
132/* Acquire a boolean property, 1=TRUE 0=FALSE. */ 132/* Acquire a boolean property, 1=TRUE 0=FALSE. */
133int 133int
134prom_getbool(int node, char *prop) 134prom_getbool(int node, const char *prop)
135{ 135{
136 int retval; 136 int retval;
137 137
@@ -145,7 +145,7 @@ prom_getbool(int node, char *prop)
145 * buffer. 145 * buffer.
146 */ 146 */
147void 147void
148prom_getstring(int node, char *prop, char *user_buf, int ubuf_size) 148prom_getstring(int node, const char *prop, char *user_buf, int ubuf_size)
149{ 149{
150 int len; 150 int len;
151 151
@@ -160,7 +160,7 @@ prom_getstring(int node, char *prop, char *user_buf, int ubuf_size)
160 * YES = 1 NO = 0 160 * YES = 1 NO = 0
161 */ 161 */
162int 162int
163prom_nodematch(int node, char *name) 163prom_nodematch(int node, const char *name)
164{ 164{
165 char namebuf[128]; 165 char namebuf[128];
166 prom_getproperty(node, "name", namebuf, sizeof(namebuf)); 166 prom_getproperty(node, "name", namebuf, sizeof(namebuf));
@@ -172,7 +172,7 @@ prom_nodematch(int node, char *name)
172 * 'nodename'. Return node if successful, zero if not. 172 * 'nodename'. Return node if successful, zero if not.
173 */ 173 */
174int 174int
175prom_searchsiblings(int node_start, char *nodename) 175prom_searchsiblings(int node_start, const char *nodename)
176{ 176{
177 177
178 int thisnode, error; 178 int thisnode, error;
@@ -294,7 +294,7 @@ prom_firstprop(int node, char *buffer)
294 * property types for this node. 294 * property types for this node.
295 */ 295 */
296__inline__ char * 296__inline__ char *
297prom_nextprop(int node, char *oprop, char *buffer) 297prom_nextprop(int node, const char *oprop, char *buffer)
298{ 298{
299 char buf[32]; 299 char buf[32];
300 300
@@ -314,15 +314,17 @@ prom_nextprop(int node, char *oprop, char *buffer)
314} 314}
315 315
316int 316int
317prom_finddevice(char *name) 317prom_finddevice(const char *name)
318{ 318{
319 if(!name) return 0; 319 if (!name)
320 return p1275_cmd ("finddevice", P1275_ARG(0,P1275_ARG_IN_STRING)| 320 return 0;
321 P1275_INOUT(1, 1), 321 return p1275_cmd(prom_finddev_name,
322 name); 322 P1275_ARG(0,P1275_ARG_IN_STRING)|
323 P1275_INOUT(1, 1),
324 name);
323} 325}
324 326
325int prom_node_has_property(int node, char *prop) 327int prom_node_has_property(int node, const char *prop)
326{ 328{
327 char buf [32]; 329 char buf [32];
328 330
@@ -339,7 +341,7 @@ int prom_node_has_property(int node, char *prop)
339 * of 'size' bytes. Return the number of bytes the prom accepted. 341 * of 'size' bytes. Return the number of bytes the prom accepted.
340 */ 342 */
341int 343int
342prom_setprop(int node, char *pname, char *value, int size) 344prom_setprop(int node, const char *pname, char *value, int size)
343{ 345{
344 if(size == 0) return 0; 346 if(size == 0) return 0;
345 if((pname == 0) || (value == 0)) return 0; 347 if((pname == 0) || (value == 0)) return 0;
@@ -364,7 +366,7 @@ prom_inst2pkg(int inst)
364 * FIXME: Should work for v0 as well 366 * FIXME: Should work for v0 as well
365 */ 367 */
366int 368int
367prom_pathtoinode(char *path) 369prom_pathtoinode(const char *path)
368{ 370{
369 int node, inst; 371 int node, inst;
370 372
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-15 16:59:30 -0500