aboutsummaryrefslogtreecommitdiffstats
path: root/arch
diff options
context:
space:
mode:
authorGrant Likely <grant.likely@secretlab.ca>2009-02-03 14:30:26 -0500
committerGrant Likely <grant.likely@secretlab.ca>2009-02-03 14:30:26 -0500
commitb8842451079a3034363320b932205d9cea791e9d (patch)
tree0b8b0e2f2b2a244501dd9956803635136ba60ab0 /arch
parent3b5ebf8e1ac88babf60772d54bc81b180b5f53b0 (diff)
powerpc/5200: Trim cruft from device trees
Trim out obsolete/extraneous properties and tighten up some usage conventions. Changes include: - removal of device_type properties - removal of cell-index properties - Addition of gpio-controller and #gpio-cells properties to gpio nodes - Move common interrupt-parent property out of device nodes and into top level parent node. This patch also include what looks to be just trivial editorial whitespace/format changes, but there is real method in this madness. Editorial changes were made to keep the all the mpc5200 board device trees as similar as possible so that diffs between them only show the real differences between the boards. The pcm030 device tree was most affected by this because many of the comments had been changed from // to /* */ style and some cell values where changed from decimal to hex format when it was cloned from one of the other 5200 device trees. Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Reviewed-by: Wolfram Sang <w.sang@pengutronix.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/boot/dts/cm5200.dts49
-rw-r--r--arch/powerpc/boot/dts/lite5200.dts52
-rw-r--r--arch/powerpc/boot/dts/lite5200b.dts63
-rw-r--r--arch/powerpc/boot/dts/motionpro.dts42
-rw-r--r--arch/powerpc/boot/dts/pcm030.dts182
-rw-r--r--arch/powerpc/boot/dts/tqm5200.dts32
6 files changed, 106 insertions, 314 deletions
diff --git a/arch/powerpc/boot/dts/cm5200.dts b/arch/powerpc/boot/dts/cm5200.dts
index 2f74cc4e093e..cee8080aa245 100644
--- a/arch/powerpc/boot/dts/cm5200.dts
+++ b/arch/powerpc/boot/dts/cm5200.dts
@@ -17,6 +17,7 @@
17 compatible = "schindler,cm5200"; 17 compatible = "schindler,cm5200";
18 #address-cells = <1>; 18 #address-cells = <1>;
19 #size-cells = <1>; 19 #size-cells = <1>;
20 interrupt-parent = <&mpc5200_pic>;
20 21
21 cpus { 22 cpus {
22 #address-cells = <1>; 23 #address-cells = <1>;
@@ -66,7 +67,6 @@
66 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 67 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
67 reg = <0x600 0x10>; 68 reg = <0x600 0x10>;
68 interrupts = <1 9 0>; 69 interrupts = <1 9 0>;
69 interrupt-parent = <&mpc5200_pic>;
70 fsl,has-wdt; 70 fsl,has-wdt;
71 }; 71 };
72 72
@@ -74,84 +74,76 @@
74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
75 reg = <0x610 0x10>; 75 reg = <0x610 0x10>;
76 interrupts = <1 10 0>; 76 interrupts = <1 10 0>;
77 interrupt-parent = <&mpc5200_pic>;
78 }; 77 };
79 78
80 timer@620 { // General Purpose Timer 79 timer@620 { // General Purpose Timer
81 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 80 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
82 reg = <0x620 0x10>; 81 reg = <0x620 0x10>;
83 interrupts = <1 11 0>; 82 interrupts = <1 11 0>;
84 interrupt-parent = <&mpc5200_pic>;
85 }; 83 };
86 84
87 timer@630 { // General Purpose Timer 85 timer@630 { // General Purpose Timer
88 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
89 reg = <0x630 0x10>; 87 reg = <0x630 0x10>;
90 interrupts = <1 12 0>; 88 interrupts = <1 12 0>;
91 interrupt-parent = <&mpc5200_pic>;
92 }; 89 };
93 90
94 timer@640 { // General Purpose Timer 91 timer@640 { // General Purpose Timer
95 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
96 reg = <0x640 0x10>; 93 reg = <0x640 0x10>;
97 interrupts = <1 13 0>; 94 interrupts = <1 13 0>;
98 interrupt-parent = <&mpc5200_pic>;
99 }; 95 };
100 96
101 timer@650 { // General Purpose Timer 97 timer@650 { // General Purpose Timer
102 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 98 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
103 reg = <0x650 0x10>; 99 reg = <0x650 0x10>;
104 interrupts = <1 14 0>; 100 interrupts = <1 14 0>;
105 interrupt-parent = <&mpc5200_pic>;
106 }; 101 };
107 102
108 timer@660 { // General Purpose Timer 103 timer@660 { // General Purpose Timer
109 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 104 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
110 reg = <0x660 0x10>; 105 reg = <0x660 0x10>;
111 interrupts = <1 15 0>; 106 interrupts = <1 15 0>;
112 interrupt-parent = <&mpc5200_pic>;
113 }; 107 };
114 108
115 timer@670 { // General Purpose Timer 109 timer@670 { // General Purpose Timer
116 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 110 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
117 reg = <0x670 0x10>; 111 reg = <0x670 0x10>;
118 interrupts = <1 16 0>; 112 interrupts = <1 16 0>;
119 interrupt-parent = <&mpc5200_pic>;
120 }; 113 };
121 114
122 rtc@800 { // Real time clock 115 rtc@800 { // Real time clock
123 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; 116 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
124 reg = <0x800 0x100>; 117 reg = <0x800 0x100>;
125 interrupts = <1 5 0 1 6 0>; 118 interrupts = <1 5 0 1 6 0>;
126 interrupt-parent = <&mpc5200_pic>;
127 }; 119 };
128 120
129 gpio@b00 { 121 gpio_simple: gpio@b00 {
130 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 122 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
131 reg = <0xb00 0x40>; 123 reg = <0xb00 0x40>;
132 interrupts = <1 7 0>; 124 interrupts = <1 7 0>;
133 interrupt-parent = <&mpc5200_pic>; 125 gpio-controller;
126 #gpio-cells = <2>;
134 }; 127 };
135 128
136 gpio@c00 { 129 gpio_wkup: gpio@c00 {
137 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 130 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
138 reg = <0xc00 0x40>; 131 reg = <0xc00 0x40>;
139 interrupts = <1 8 0 0 3 0>; 132 interrupts = <1 8 0 0 3 0>;
140 interrupt-parent = <&mpc5200_pic>; 133 gpio-controller;
134 #gpio-cells = <2>;
141 }; 135 };
142 136
143 spi@f00 { 137 spi@f00 {
144 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 138 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
145 reg = <0xf00 0x20>; 139 reg = <0xf00 0x20>;
146 interrupts = <2 13 0 2 14 0>; 140 interrupts = <2 13 0 2 14 0>;
147 interrupt-parent = <&mpc5200_pic>;
148 }; 141 };
149 142
150 usb@1000 { 143 usb@1000 {
151 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; 144 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
152 reg = <0x1000 0xff>; 145 reg = <0x1000 0xff>;
153 interrupts = <2 6 0>; 146 interrupts = <2 6 0>;
154 interrupt-parent = <&mpc5200_pic>;
155 }; 147 };
156 148
157 dma-controller@1200 { 149 dma-controller@1200 {
@@ -161,7 +153,6 @@
161 3 4 0 3 5 0 3 6 0 3 7 0 153 3 4 0 3 5 0 3 6 0 3 7 0
162 3 8 0 3 9 0 3 10 0 3 11 0 154 3 8 0 3 9 0 3 10 0 3 11 0
163 3 12 0 3 13 0 3 14 0 3 15 0>; 155 3 12 0 3 13 0 3 14 0 3 15 0>;
164 interrupt-parent = <&mpc5200_pic>;
165 }; 156 };
166 157
167 xlb@1f00 { 158 xlb@1f00 {
@@ -170,48 +161,34 @@
170 }; 161 };
171 162
172 serial@2000 { // PSC1 163 serial@2000 { // PSC1
173 device_type = "serial";
174 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 164 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
175 port-number = <0>; // Logical port assignment
176 reg = <0x2000 0x100>; 165 reg = <0x2000 0x100>;
177 interrupts = <2 1 0>; 166 interrupts = <2 1 0>;
178 interrupt-parent = <&mpc5200_pic>;
179 }; 167 };
180 168
181 serial@2200 { // PSC2 169 serial@2200 { // PSC2
182 device_type = "serial"; 170 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
183 compatible = "fsl,mpc5200-psc-uart";
184 port-number = <1>; // Logical port assignment
185 reg = <0x2200 0x100>; 171 reg = <0x2200 0x100>;
186 interrupts = <2 2 0>; 172 interrupts = <2 2 0>;
187 interrupt-parent = <&mpc5200_pic>;
188 }; 173 };
189 174
190 serial@2400 { // PSC3 175 serial@2400 { // PSC3
191 device_type = "serial"; 176 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
192 compatible = "fsl,mpc5200-psc-uart";
193 port-number = <2>; // Logical port assignment
194 reg = <0x2400 0x100>; 177 reg = <0x2400 0x100>;
195 interrupts = <2 3 0>; 178 interrupts = <2 3 0>;
196 interrupt-parent = <&mpc5200_pic>;
197 }; 179 };
198 180
199 serial@2c00 { // PSC6 181 serial@2c00 { // PSC6
200 device_type = "serial";
201 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 182 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
202 port-number = <5>; // Logical port assignment
203 reg = <0x2c00 0x100>; 183 reg = <0x2c00 0x100>;
204 interrupts = <2 4 0>; 184 interrupts = <2 4 0>;
205 interrupt-parent = <&mpc5200_pic>;
206 }; 185 };
207 186
208 ethernet@3000 { 187 ethernet@3000 {
209 device_type = "network";
210 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; 188 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
211 reg = <0x3000 0x400>; 189 reg = <0x3000 0x400>;
212 local-mac-address = [ 00 00 00 00 00 00 ]; 190 local-mac-address = [ 00 00 00 00 00 00 ];
213 interrupts = <2 5 0>; 191 interrupts = <2 5 0>;
214 interrupt-parent = <&mpc5200_pic>;
215 phy-handle = <&phy0>; 192 phy-handle = <&phy0>;
216 }; 193 };
217 194
@@ -221,10 +198,8 @@
221 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; 198 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
222 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts 199 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
223 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 200 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
224 interrupt-parent = <&mpc5200_pic>;
225 201
226 phy0: ethernet-phy@0 { 202 phy0: ethernet-phy@0 {
227 device_type = "ethernet-phy";
228 reg = <0>; 203 reg = <0>;
229 }; 204 };
230 }; 205 };
@@ -235,7 +210,6 @@
235 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 210 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
236 reg = <0x3d40 0x40>; 211 reg = <0x3d40 0x40>;
237 interrupts = <2 16 0>; 212 interrupts = <2 16 0>;
238 interrupt-parent = <&mpc5200_pic>;
239 fsl5200-clocking; 213 fsl5200-clocking;
240 }; 214 };
241 215
@@ -245,9 +219,8 @@
245 }; 219 };
246 }; 220 };
247 221
248 lpb { 222 localbus {
249 model = "fsl,lpb"; 223 compatible = "fsl,mpc5200b-lpb","simple-bus";
250 compatible = "fsl,lpb";
251 #address-cells = <2>; 224 #address-cells = <2>;
252 #size-cells = <1>; 225 #size-cells = <1>;
253 ranges = <0 0 0xfc000000 0x2000000>; 226 ranges = <0 0 0xfc000000 0x2000000>;
diff --git a/arch/powerpc/boot/dts/lite5200.dts b/arch/powerpc/boot/dts/lite5200.dts
index 3f7a5dce8de0..de30b3f9eb26 100644
--- a/arch/powerpc/boot/dts/lite5200.dts
+++ b/arch/powerpc/boot/dts/lite5200.dts
@@ -17,6 +17,7 @@
17 compatible = "fsl,lite5200"; 17 compatible = "fsl,lite5200";
18 #address-cells = <1>; 18 #address-cells = <1>;
19 #size-cells = <1>; 19 #size-cells = <1>;
20 interrupt-parent = <&mpc5200_pic>;
20 21
21 cpus { 22 cpus {
22 #address-cells = <1>; 23 #address-cells = <1>;
@@ -58,96 +59,74 @@
58 // 5200 interrupts are encoded into two levels; 59 // 5200 interrupts are encoded into two levels;
59 interrupt-controller; 60 interrupt-controller;
60 #interrupt-cells = <3>; 61 #interrupt-cells = <3>;
61 device_type = "interrupt-controller";
62 compatible = "fsl,mpc5200-pic"; 62 compatible = "fsl,mpc5200-pic";
63 reg = <0x500 0x80>; 63 reg = <0x500 0x80>;
64 }; 64 };
65 65
66 timer@600 { // General Purpose Timer 66 timer@600 { // General Purpose Timer
67 compatible = "fsl,mpc5200-gpt"; 67 compatible = "fsl,mpc5200-gpt";
68 cell-index = <0>;
69 reg = <0x600 0x10>; 68 reg = <0x600 0x10>;
70 interrupts = <1 9 0>; 69 interrupts = <1 9 0>;
71 interrupt-parent = <&mpc5200_pic>;
72 fsl,has-wdt; 70 fsl,has-wdt;
73 }; 71 };
74 72
75 timer@610 { // General Purpose Timer 73 timer@610 { // General Purpose Timer
76 compatible = "fsl,mpc5200-gpt"; 74 compatible = "fsl,mpc5200-gpt";
77 cell-index = <1>;
78 reg = <0x610 0x10>; 75 reg = <0x610 0x10>;
79 interrupts = <1 10 0>; 76 interrupts = <1 10 0>;
80 interrupt-parent = <&mpc5200_pic>;
81 }; 77 };
82 78
83 timer@620 { // General Purpose Timer 79 timer@620 { // General Purpose Timer
84 compatible = "fsl,mpc5200-gpt"; 80 compatible = "fsl,mpc5200-gpt";
85 cell-index = <2>;
86 reg = <0x620 0x10>; 81 reg = <0x620 0x10>;
87 interrupts = <1 11 0>; 82 interrupts = <1 11 0>;
88 interrupt-parent = <&mpc5200_pic>;
89 }; 83 };
90 84
91 timer@630 { // General Purpose Timer 85 timer@630 { // General Purpose Timer
92 compatible = "fsl,mpc5200-gpt"; 86 compatible = "fsl,mpc5200-gpt";
93 cell-index = <3>;
94 reg = <0x630 0x10>; 87 reg = <0x630 0x10>;
95 interrupts = <1 12 0>; 88 interrupts = <1 12 0>;
96 interrupt-parent = <&mpc5200_pic>;
97 }; 89 };
98 90
99 timer@640 { // General Purpose Timer 91 timer@640 { // General Purpose Timer
100 compatible = "fsl,mpc5200-gpt"; 92 compatible = "fsl,mpc5200-gpt";
101 cell-index = <4>;
102 reg = <0x640 0x10>; 93 reg = <0x640 0x10>;
103 interrupts = <1 13 0>; 94 interrupts = <1 13 0>;
104 interrupt-parent = <&mpc5200_pic>;
105 }; 95 };
106 96
107 timer@650 { // General Purpose Timer 97 timer@650 { // General Purpose Timer
108 compatible = "fsl,mpc5200-gpt"; 98 compatible = "fsl,mpc5200-gpt";
109 cell-index = <5>;
110 reg = <0x650 0x10>; 99 reg = <0x650 0x10>;
111 interrupts = <1 14 0>; 100 interrupts = <1 14 0>;
112 interrupt-parent = <&mpc5200_pic>;
113 }; 101 };
114 102
115 timer@660 { // General Purpose Timer 103 timer@660 { // General Purpose Timer
116 compatible = "fsl,mpc5200-gpt"; 104 compatible = "fsl,mpc5200-gpt";
117 cell-index = <6>;
118 reg = <0x660 0x10>; 105 reg = <0x660 0x10>;
119 interrupts = <1 15 0>; 106 interrupts = <1 15 0>;
120 interrupt-parent = <&mpc5200_pic>;
121 }; 107 };
122 108
123 timer@670 { // General Purpose Timer 109 timer@670 { // General Purpose Timer
124 compatible = "fsl,mpc5200-gpt"; 110 compatible = "fsl,mpc5200-gpt";
125 cell-index = <7>;
126 reg = <0x670 0x10>; 111 reg = <0x670 0x10>;
127 interrupts = <1 16 0>; 112 interrupts = <1 16 0>;
128 interrupt-parent = <&mpc5200_pic>;
129 }; 113 };
130 114
131 rtc@800 { // Real time clock 115 rtc@800 { // Real time clock
132 compatible = "fsl,mpc5200-rtc"; 116 compatible = "fsl,mpc5200-rtc";
133 reg = <0x800 0x100>; 117 reg = <0x800 0x100>;
134 interrupts = <1 5 0 1 6 0>; 118 interrupts = <1 5 0 1 6 0>;
135 interrupt-parent = <&mpc5200_pic>;
136 }; 119 };
137 120
138 can@900 { 121 can@900 {
139 compatible = "fsl,mpc5200-mscan"; 122 compatible = "fsl,mpc5200-mscan";
140 cell-index = <0>;
141 interrupts = <2 17 0>; 123 interrupts = <2 17 0>;
142 interrupt-parent = <&mpc5200_pic>;
143 reg = <0x900 0x80>; 124 reg = <0x900 0x80>;
144 }; 125 };
145 126
146 can@980 { 127 can@980 {
147 compatible = "fsl,mpc5200-mscan"; 128 compatible = "fsl,mpc5200-mscan";
148 cell-index = <1>;
149 interrupts = <2 18 0>; 129 interrupts = <2 18 0>;
150 interrupt-parent = <&mpc5200_pic>;
151 reg = <0x980 0x80>; 130 reg = <0x980 0x80>;
152 }; 131 };
153 132
@@ -155,39 +134,33 @@
155 compatible = "fsl,mpc5200-gpio"; 134 compatible = "fsl,mpc5200-gpio";
156 reg = <0xb00 0x40>; 135 reg = <0xb00 0x40>;
157 interrupts = <1 7 0>; 136 interrupts = <1 7 0>;
158 interrupt-parent = <&mpc5200_pic>;
159 }; 137 };
160 138
161 gpio@c00 { 139 gpio@c00 {
162 compatible = "fsl,mpc5200-gpio-wkup"; 140 compatible = "fsl,mpc5200-gpio-wkup";
163 reg = <0xc00 0x40>; 141 reg = <0xc00 0x40>;
164 interrupts = <1 8 0 0 3 0>; 142 interrupts = <1 8 0 0 3 0>;
165 interrupt-parent = <&mpc5200_pic>;
166 }; 143 };
167 144
168 spi@f00 { 145 spi@f00 {
169 compatible = "fsl,mpc5200-spi"; 146 compatible = "fsl,mpc5200-spi";
170 reg = <0xf00 0x20>; 147 reg = <0xf00 0x20>;
171 interrupts = <2 13 0 2 14 0>; 148 interrupts = <2 13 0 2 14 0>;
172 interrupt-parent = <&mpc5200_pic>;
173 }; 149 };
174 150
175 usb@1000 { 151 usb@1000 {
176 compatible = "fsl,mpc5200-ohci","ohci-be"; 152 compatible = "fsl,mpc5200-ohci","ohci-be";
177 reg = <0x1000 0xff>; 153 reg = <0x1000 0xff>;
178 interrupts = <2 6 0>; 154 interrupts = <2 6 0>;
179 interrupt-parent = <&mpc5200_pic>;
180 }; 155 };
181 156
182 dma-controller@1200 { 157 dma-controller@1200 {
183 device_type = "dma-controller";
184 compatible = "fsl,mpc5200-bestcomm"; 158 compatible = "fsl,mpc5200-bestcomm";
185 reg = <0x1200 0x80>; 159 reg = <0x1200 0x80>;
186 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 160 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
187 3 4 0 3 5 0 3 6 0 3 7 0 161 3 4 0 3 5 0 3 6 0 3 7 0
188 3 8 0 3 9 0 3 10 0 3 11 0 162 3 8 0 3 9 0 3 10 0 3 11 0
189 3 12 0 3 13 0 3 14 0 3 15 0>; 163 3 12 0 3 13 0 3 14 0 3 15 0>;
190 interrupt-parent = <&mpc5200_pic>;
191 }; 164 };
192 165
193 xlb@1f00 { 166 xlb@1f00 {
@@ -196,13 +169,10 @@
196 }; 169 };
197 170
198 serial@2000 { // PSC1 171 serial@2000 { // PSC1
199 device_type = "serial";
200 compatible = "fsl,mpc5200-psc-uart"; 172 compatible = "fsl,mpc5200-psc-uart";
201 port-number = <0>; // Logical port assignment
202 cell-index = <0>; 173 cell-index = <0>;
203 reg = <0x2000 0x100>; 174 reg = <0x2000 0x100>;
204 interrupts = <2 1 0>; 175 interrupts = <2 1 0>;
205 interrupt-parent = <&mpc5200_pic>;
206 }; 176 };
207 177
208 // PSC2 in ac97 mode example 178 // PSC2 in ac97 mode example
@@ -211,7 +181,6 @@
211 // cell-index = <1>; 181 // cell-index = <1>;
212 // reg = <0x2200 0x100>; 182 // reg = <0x2200 0x100>;
213 // interrupts = <2 2 0>; 183 // interrupts = <2 2 0>;
214 // interrupt-parent = <&mpc5200_pic>;
215 //}; 184 //};
216 185
217 // PSC3 in CODEC mode example 186 // PSC3 in CODEC mode example
@@ -220,27 +189,22 @@
220 // cell-index = <2>; 189 // cell-index = <2>;
221 // reg = <0x2400 0x100>; 190 // reg = <0x2400 0x100>;
222 // interrupts = <2 3 0>; 191 // interrupts = <2 3 0>;
223 // interrupt-parent = <&mpc5200_pic>;
224 //}; 192 //};
225 193
226 // PSC4 in uart mode example 194 // PSC4 in uart mode example
227 //serial@2600 { // PSC4 195 //serial@2600 { // PSC4
228 // device_type = "serial";
229 // compatible = "fsl,mpc5200-psc-uart"; 196 // compatible = "fsl,mpc5200-psc-uart";
230 // cell-index = <3>; 197 // cell-index = <3>;
231 // reg = <0x2600 0x100>; 198 // reg = <0x2600 0x100>;
232 // interrupts = <2 11 0>; 199 // interrupts = <2 11 0>;
233 // interrupt-parent = <&mpc5200_pic>;
234 //}; 200 //};
235 201
236 // PSC5 in uart mode example 202 // PSC5 in uart mode example
237 //serial@2800 { // PSC5 203 //serial@2800 { // PSC5
238 // device_type = "serial";
239 // compatible = "fsl,mpc5200-psc-uart"; 204 // compatible = "fsl,mpc5200-psc-uart";
240 // cell-index = <4>; 205 // cell-index = <4>;
241 // reg = <0x2800 0x100>; 206 // reg = <0x2800 0x100>;
242 // interrupts = <2 12 0>; 207 // interrupts = <2 12 0>;
243 // interrupt-parent = <&mpc5200_pic>;
244 //}; 208 //};
245 209
246 // PSC6 in spi mode example 210 // PSC6 in spi mode example
@@ -249,16 +213,13 @@
249 // cell-index = <5>; 213 // cell-index = <5>;
250 // reg = <0x2c00 0x100>; 214 // reg = <0x2c00 0x100>;
251 // interrupts = <2 4 0>; 215 // interrupts = <2 4 0>;
252 // interrupt-parent = <&mpc5200_pic>;
253 //}; 216 //};
254 217
255 ethernet@3000 { 218 ethernet@3000 {
256 device_type = "network";
257 compatible = "fsl,mpc5200-fec"; 219 compatible = "fsl,mpc5200-fec";
258 reg = <0x3000 0x400>; 220 reg = <0x3000 0x400>;
259 local-mac-address = [ 00 00 00 00 00 00 ]; 221 local-mac-address = [ 00 00 00 00 00 00 ];
260 interrupts = <2 5 0>; 222 interrupts = <2 5 0>;
261 interrupt-parent = <&mpc5200_pic>;
262 phy-handle = <&phy0>; 223 phy-handle = <&phy0>;
263 }; 224 };
264 225
@@ -268,30 +229,24 @@
268 compatible = "fsl,mpc5200-mdio"; 229 compatible = "fsl,mpc5200-mdio";
269 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts 230 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
270 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 231 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
271 interrupt-parent = <&mpc5200_pic>;
272 232
273 phy0: ethernet-phy@1 { 233 phy0: ethernet-phy@1 {
274 device_type = "ethernet-phy";
275 reg = <1>; 234 reg = <1>;
276 }; 235 };
277 }; 236 };
278 237
279 ata@3a00 { 238 ata@3a00 {
280 device_type = "ata";
281 compatible = "fsl,mpc5200-ata"; 239 compatible = "fsl,mpc5200-ata";
282 reg = <0x3a00 0x100>; 240 reg = <0x3a00 0x100>;
283 interrupts = <2 7 0>; 241 interrupts = <2 7 0>;
284 interrupt-parent = <&mpc5200_pic>;
285 }; 242 };
286 243
287 i2c@3d00 { 244 i2c@3d00 {
288 #address-cells = <1>; 245 #address-cells = <1>;
289 #size-cells = <0>; 246 #size-cells = <0>;
290 compatible = "fsl,mpc5200-i2c","fsl-i2c"; 247 compatible = "fsl,mpc5200-i2c","fsl-i2c";
291 cell-index = <0>;
292 reg = <0x3d00 0x40>; 248 reg = <0x3d00 0x40>;
293 interrupts = <2 15 0>; 249 interrupts = <2 15 0>;
294 interrupt-parent = <&mpc5200_pic>;
295 fsl5200-clocking; 250 fsl5200-clocking;
296 }; 251 };
297 252
@@ -299,14 +254,12 @@
299 #address-cells = <1>; 254 #address-cells = <1>;
300 #size-cells = <0>; 255 #size-cells = <0>;
301 compatible = "fsl,mpc5200-i2c","fsl-i2c"; 256 compatible = "fsl,mpc5200-i2c","fsl-i2c";
302 cell-index = <1>;
303 reg = <0x3d40 0x40>; 257 reg = <0x3d40 0x40>;
304 interrupts = <2 16 0>; 258 interrupts = <2 16 0>;
305 interrupt-parent = <&mpc5200_pic>;
306 fsl5200-clocking; 259 fsl5200-clocking;
307 }; 260 };
308 sram@8000 { 261 sram@8000 {
309 compatible = "fsl,mpc5200-sram","sram"; 262 compatible = "fsl,mpc5200-sram";
310 reg = <0x8000 0x4000>; 263 reg = <0x8000 0x4000>;
311 }; 264 };
312 }; 265 };
@@ -325,7 +278,6 @@
325 0xc000 0 0 4 &mpc5200_pic 0 0 3>; 278 0xc000 0 0 4 &mpc5200_pic 0 0 3>;
326 clock-frequency = <0>; // From boot loader 279 clock-frequency = <0>; // From boot loader
327 interrupts = <2 8 0 2 9 0 2 10 0>; 280 interrupts = <2 8 0 2 9 0 2 10 0>;
328 interrupt-parent = <&mpc5200_pic>;
329 bus-range = <0 0>; 281 bus-range = <0 0>;
330 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 282 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
331 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 283 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts
index 63e3bb48e843..c63e3566479e 100644
--- a/arch/powerpc/boot/dts/lite5200b.dts
+++ b/arch/powerpc/boot/dts/lite5200b.dts
@@ -17,6 +17,7 @@
17 compatible = "fsl,lite5200b"; 17 compatible = "fsl,lite5200b";
18 #address-cells = <1>; 18 #address-cells = <1>;
19 #size-cells = <1>; 19 #size-cells = <1>;
20 interrupt-parent = <&mpc5200_pic>;
20 21
21 cpus { 22 cpus {
22 #address-cells = <1>; 23 #address-cells = <1>;
@@ -58,136 +59,112 @@
58 // 5200 interrupts are encoded into two levels; 59 // 5200 interrupts are encoded into two levels;
59 interrupt-controller; 60 interrupt-controller;
60 #interrupt-cells = <3>; 61 #interrupt-cells = <3>;
61 device_type = "interrupt-controller";
62 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; 62 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
63 reg = <0x500 0x80>; 63 reg = <0x500 0x80>;
64 }; 64 };
65 65
66 timer@600 { // General Purpose Timer 66 timer@600 { // General Purpose Timer
67 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 67 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
68 cell-index = <0>;
69 reg = <0x600 0x10>; 68 reg = <0x600 0x10>;
70 interrupts = <1 9 0>; 69 interrupts = <1 9 0>;
71 interrupt-parent = <&mpc5200_pic>;
72 fsl,has-wdt; 70 fsl,has-wdt;
73 }; 71 };
74 72
75 timer@610 { // General Purpose Timer 73 timer@610 { // General Purpose Timer
76 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
77 cell-index = <1>;
78 reg = <0x610 0x10>; 75 reg = <0x610 0x10>;
79 interrupts = <1 10 0>; 76 interrupts = <1 10 0>;
80 interrupt-parent = <&mpc5200_pic>;
81 }; 77 };
82 78
83 timer@620 { // General Purpose Timer 79 timer@620 { // General Purpose Timer
84 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 80 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
85 cell-index = <2>;
86 reg = <0x620 0x10>; 81 reg = <0x620 0x10>;
87 interrupts = <1 11 0>; 82 interrupts = <1 11 0>;
88 interrupt-parent = <&mpc5200_pic>;
89 }; 83 };
90 84
91 timer@630 { // General Purpose Timer 85 timer@630 { // General Purpose Timer
92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
93 cell-index = <3>;
94 reg = <0x630 0x10>; 87 reg = <0x630 0x10>;
95 interrupts = <1 12 0>; 88 interrupts = <1 12 0>;
96 interrupt-parent = <&mpc5200_pic>;
97 }; 89 };
98 90
99 timer@640 { // General Purpose Timer 91 timer@640 { // General Purpose Timer
100 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
101 cell-index = <4>;
102 reg = <0x640 0x10>; 93 reg = <0x640 0x10>;
103 interrupts = <1 13 0>; 94 interrupts = <1 13 0>;
104 interrupt-parent = <&mpc5200_pic>;
105 }; 95 };
106 96
107 timer@650 { // General Purpose Timer 97 timer@650 { // General Purpose Timer
108 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 98 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
109 cell-index = <5>;
110 reg = <0x650 0x10>; 99 reg = <0x650 0x10>;
111 interrupts = <1 14 0>; 100 interrupts = <1 14 0>;
112 interrupt-parent = <&mpc5200_pic>;
113 }; 101 };
114 102
115 timer@660 { // General Purpose Timer 103 timer@660 { // General Purpose Timer
116 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 104 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
117 cell-index = <6>;
118 reg = <0x660 0x10>; 105 reg = <0x660 0x10>;
119 interrupts = <1 15 0>; 106 interrupts = <1 15 0>;
120 interrupt-parent = <&mpc5200_pic>;
121 }; 107 };
122 108
123 timer@670 { // General Purpose Timer 109 timer@670 { // General Purpose Timer
124 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 110 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
125 cell-index = <7>;
126 reg = <0x670 0x10>; 111 reg = <0x670 0x10>;
127 interrupts = <1 16 0>; 112 interrupts = <1 16 0>;
128 interrupt-parent = <&mpc5200_pic>;
129 }; 113 };
130 114
131 rtc@800 { // Real time clock 115 rtc@800 { // Real time clock
132 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; 116 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
133 reg = <0x800 0x100>; 117 reg = <0x800 0x100>;
134 interrupts = <1 5 0 1 6 0>; 118 interrupts = <1 5 0 1 6 0>;
135 interrupt-parent = <&mpc5200_pic>;
136 }; 119 };
137 120
138 can@900 { 121 can@900 {
139 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 122 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
140 cell-index = <0>;
141 interrupts = <2 17 0>; 123 interrupts = <2 17 0>;
142 interrupt-parent = <&mpc5200_pic>;
143 reg = <0x900 0x80>; 124 reg = <0x900 0x80>;
144 }; 125 };
145 126
146 can@980 { 127 can@980 {
147 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 128 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
148 cell-index = <1>;
149 interrupts = <2 18 0>; 129 interrupts = <2 18 0>;
150 interrupt-parent = <&mpc5200_pic>;
151 reg = <0x980 0x80>; 130 reg = <0x980 0x80>;
152 }; 131 };
153 132
154 gpio@b00 { 133 gpio_simple: gpio@b00 {
155 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 134 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
156 reg = <0xb00 0x40>; 135 reg = <0xb00 0x40>;
157 interrupts = <1 7 0>; 136 interrupts = <1 7 0>;
158 interrupt-parent = <&mpc5200_pic>; 137 gpio-controller;
138 #gpio-cells = <2>;
159 }; 139 };
160 140
161 gpio@c00 { 141 gpio_wkup: gpio@c00 {
162 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 142 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
163 reg = <0xc00 0x40>; 143 reg = <0xc00 0x40>;
164 interrupts = <1 8 0 0 3 0>; 144 interrupts = <1 8 0 0 3 0>;
165 interrupt-parent = <&mpc5200_pic>; 145 gpio-controller;
146 #gpio-cells = <2>;
166 }; 147 };
167 148
168 spi@f00 { 149 spi@f00 {
169 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 150 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
170 reg = <0xf00 0x20>; 151 reg = <0xf00 0x20>;
171 interrupts = <2 13 0 2 14 0>; 152 interrupts = <2 13 0 2 14 0>;
172 interrupt-parent = <&mpc5200_pic>;
173 }; 153 };
174 154
175 usb@1000 { 155 usb@1000 {
176 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; 156 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
177 reg = <0x1000 0xff>; 157 reg = <0x1000 0xff>;
178 interrupts = <2 6 0>; 158 interrupts = <2 6 0>;
179 interrupt-parent = <&mpc5200_pic>;
180 }; 159 };
181 160
182 dma-controller@1200 { 161 dma-controller@1200 {
183 device_type = "dma-controller";
184 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; 162 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
185 reg = <0x1200 0x80>; 163 reg = <0x1200 0x80>;
186 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 164 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
187 3 4 0 3 5 0 3 6 0 3 7 0 165 3 4 0 3 5 0 3 6 0 3 7 0
188 3 8 0 3 9 0 3 10 0 3 11 0 166 3 8 0 3 9 0 3 10 0 3 11 0
189 3 12 0 3 13 0 3 14 0 3 15 0>; 167 3 12 0 3 13 0 3 14 0 3 15 0>;
190 interrupt-parent = <&mpc5200_pic>;
191 }; 168 };
192 169
193 xlb@1f00 { 170 xlb@1f00 {
@@ -196,13 +173,10 @@
196 }; 173 };
197 174
198 serial@2000 { // PSC1 175 serial@2000 { // PSC1
199 device_type = "serial";
200 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 176 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
201 port-number = <0>; // Logical port assignment
202 cell-index = <0>; 177 cell-index = <0>;
203 reg = <0x2000 0x100>; 178 reg = <0x2000 0x100>;
204 interrupts = <2 1 0>; 179 interrupts = <2 1 0>;
205 interrupt-parent = <&mpc5200_pic>;
206 }; 180 };
207 181
208 // PSC2 in ac97 mode example 182 // PSC2 in ac97 mode example
@@ -211,7 +185,6 @@
211 // cell-index = <1>; 185 // cell-index = <1>;
212 // reg = <0x2200 0x100>; 186 // reg = <0x2200 0x100>;
213 // interrupts = <2 2 0>; 187 // interrupts = <2 2 0>;
214 // interrupt-parent = <&mpc5200_pic>;
215 //}; 188 //};
216 189
217 // PSC3 in CODEC mode example 190 // PSC3 in CODEC mode example
@@ -220,27 +193,22 @@
220 // cell-index = <2>; 193 // cell-index = <2>;
221 // reg = <0x2400 0x100>; 194 // reg = <0x2400 0x100>;
222 // interrupts = <2 3 0>; 195 // interrupts = <2 3 0>;
223 // interrupt-parent = <&mpc5200_pic>;
224 //}; 196 //};
225 197
226 // PSC4 in uart mode example 198 // PSC4 in uart mode example
227 //serial@2600 { // PSC4 199 //serial@2600 { // PSC4
228 // device_type = "serial";
229 // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 200 // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
230 // cell-index = <3>; 201 // cell-index = <3>;
231 // reg = <0x2600 0x100>; 202 // reg = <0x2600 0x100>;
232 // interrupts = <2 11 0>; 203 // interrupts = <2 11 0>;
233 // interrupt-parent = <&mpc5200_pic>;
234 //}; 204 //};
235 205
236 // PSC5 in uart mode example 206 // PSC5 in uart mode example
237 //serial@2800 { // PSC5 207 //serial@2800 { // PSC5
238 // device_type = "serial";
239 // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 208 // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
240 // cell-index = <4>; 209 // cell-index = <4>;
241 // reg = <0x2800 0x100>; 210 // reg = <0x2800 0x100>;
242 // interrupts = <2 12 0>; 211 // interrupts = <2 12 0>;
243 // interrupt-parent = <&mpc5200_pic>;
244 //}; 212 //};
245 213
246 // PSC6 in spi mode example 214 // PSC6 in spi mode example
@@ -249,49 +217,40 @@
249 // cell-index = <5>; 217 // cell-index = <5>;
250 // reg = <0x2c00 0x100>; 218 // reg = <0x2c00 0x100>;
251 // interrupts = <2 4 0>; 219 // interrupts = <2 4 0>;
252 // interrupt-parent = <&mpc5200_pic>;
253 //}; 220 //};
254 221
255 ethernet@3000 { 222 ethernet@3000 {
256 device_type = "network";
257 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; 223 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
258 reg = <0x3000 0x400>; 224 reg = <0x3000 0x400>;
259 local-mac-address = [ 00 00 00 00 00 00 ]; 225 local-mac-address = [ 00 00 00 00 00 00 ];
260 interrupts = <2 5 0>; 226 interrupts = <2 5 0>;
261 interrupt-parent = <&mpc5200_pic>;
262 phy-handle = <&phy0>; 227 phy-handle = <&phy0>;
263 }; 228 };
264 229
265 mdio@3000 { 230 mdio@3000 {
266 #address-cells = <1>; 231 #address-cells = <1>;
267 #size-cells = <0>; 232 #size-cells = <0>;
268 compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio"; 233 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
269 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts 234 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
270 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 235 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
271 interrupt-parent = <&mpc5200_pic>;
272 236
273 phy0: ethernet-phy@0 { 237 phy0: ethernet-phy@0 {
274 device_type = "ethernet-phy";
275 reg = <0>; 238 reg = <0>;
276 }; 239 };
277 }; 240 };
278 241
279 ata@3a00 { 242 ata@3a00 {
280 device_type = "ata";
281 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; 243 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
282 reg = <0x3a00 0x100>; 244 reg = <0x3a00 0x100>;
283 interrupts = <2 7 0>; 245 interrupts = <2 7 0>;
284 interrupt-parent = <&mpc5200_pic>;
285 }; 246 };
286 247
287 i2c@3d00 { 248 i2c@3d00 {
288 #address-cells = <1>; 249 #address-cells = <1>;
289 #size-cells = <0>; 250 #size-cells = <0>;
290 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 251 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
291 cell-index = <0>;
292 reg = <0x3d00 0x40>; 252 reg = <0x3d00 0x40>;
293 interrupts = <2 15 0>; 253 interrupts = <2 15 0>;
294 interrupt-parent = <&mpc5200_pic>;
295 fsl5200-clocking; 254 fsl5200-clocking;
296 }; 255 };
297 256
@@ -299,14 +258,13 @@
299 #address-cells = <1>; 258 #address-cells = <1>;
300 #size-cells = <0>; 259 #size-cells = <0>;
301 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 260 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
302 cell-index = <1>;
303 reg = <0x3d40 0x40>; 261 reg = <0x3d40 0x40>;
304 interrupts = <2 16 0>; 262 interrupts = <2 16 0>;
305 interrupt-parent = <&mpc5200_pic>;
306 fsl5200-clocking; 263 fsl5200-clocking;
307 }; 264 };
265
308 sram@8000 { 266 sram@8000 {
309 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram"; 267 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
310 reg = <0x8000 0x4000>; 268 reg = <0x8000 0x4000>;
311 }; 269 };
312 }; 270 };
@@ -330,7 +288,6 @@
330 0xc800 0 0 4 &mpc5200_pic 0 0 3>; 288 0xc800 0 0 4 &mpc5200_pic 0 0 3>;
331 clock-frequency = <0>; // From boot loader 289 clock-frequency = <0>; // From boot loader
332 interrupts = <2 8 0 2 9 0 2 10 0>; 290 interrupts = <2 8 0 2 9 0 2 10 0>;
333 interrupt-parent = <&mpc5200_pic>;
334 bus-range = <0 0>; 291 bus-range = <0 0>;
335 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 292 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
336 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 293 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
diff --git a/arch/powerpc/boot/dts/motionpro.dts b/arch/powerpc/boot/dts/motionpro.dts
index 52ba6f98b273..7be8ca038676 100644
--- a/arch/powerpc/boot/dts/motionpro.dts
+++ b/arch/powerpc/boot/dts/motionpro.dts
@@ -17,6 +17,7 @@
17 compatible = "promess,motionpro"; 17 compatible = "promess,motionpro";
18 #address-cells = <1>; 18 #address-cells = <1>;
19 #size-cells = <1>; 19 #size-cells = <1>;
20 interrupt-parent = <&mpc5200_pic>;
20 21
21 cpus { 22 cpus {
22 #address-cells = <1>; 23 #address-cells = <1>;
@@ -66,7 +67,6 @@
66 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 67 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
67 reg = <0x600 0x10>; 68 reg = <0x600 0x10>;
68 interrupts = <1 9 0>; 69 interrupts = <1 9 0>;
69 interrupt-parent = <&mpc5200_pic>;
70 fsl,has-wdt; 70 fsl,has-wdt;
71 }; 71 };
72 72
@@ -74,35 +74,30 @@
74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
75 reg = <0x610 0x10>; 75 reg = <0x610 0x10>;
76 interrupts = <1 10 0>; 76 interrupts = <1 10 0>;
77 interrupt-parent = <&mpc5200_pic>;
78 }; 77 };
79 78
80 timer@620 { // General Purpose Timer 79 timer@620 { // General Purpose Timer
81 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 80 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
82 reg = <0x620 0x10>; 81 reg = <0x620 0x10>;
83 interrupts = <1 11 0>; 82 interrupts = <1 11 0>;
84 interrupt-parent = <&mpc5200_pic>;
85 }; 83 };
86 84
87 timer@630 { // General Purpose Timer 85 timer@630 { // General Purpose Timer
88 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
89 reg = <0x630 0x10>; 87 reg = <0x630 0x10>;
90 interrupts = <1 12 0>; 88 interrupts = <1 12 0>;
91 interrupt-parent = <&mpc5200_pic>;
92 }; 89 };
93 90
94 timer@640 { // General Purpose Timer 91 timer@640 { // General Purpose Timer
95 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
96 reg = <0x640 0x10>; 93 reg = <0x640 0x10>;
97 interrupts = <1 13 0>; 94 interrupts = <1 13 0>;
98 interrupt-parent = <&mpc5200_pic>;
99 }; 95 };
100 96
101 timer@650 { // General Purpose Timer 97 timer@650 { // General Purpose Timer
102 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 98 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
103 reg = <0x650 0x10>; 99 reg = <0x650 0x10>;
104 interrupts = <1 14 0>; 100 interrupts = <1 14 0>;
105 interrupt-parent = <&mpc5200_pic>;
106 }; 101 };
107 102
108 motionpro-led@660 { // Motion-PRO status LED 103 motionpro-led@660 { // Motion-PRO status LED
@@ -110,7 +105,6 @@
110 label = "motionpro-statusled"; 105 label = "motionpro-statusled";
111 reg = <0x660 0x10>; 106 reg = <0x660 0x10>;
112 interrupts = <1 15 0>; 107 interrupts = <1 15 0>;
113 interrupt-parent = <&mpc5200_pic>;
114 blink-delay = <100>; // 100 msec 108 blink-delay = <100>; // 100 msec
115 }; 109 };
116 110
@@ -119,49 +113,46 @@
119 label = "motionpro-readyled"; 113 label = "motionpro-readyled";
120 reg = <0x670 0x10>; 114 reg = <0x670 0x10>;
121 interrupts = <1 16 0>; 115 interrupts = <1 16 0>;
122 interrupt-parent = <&mpc5200_pic>;
123 }; 116 };
124 117
125 rtc@800 { // Real time clock 118 rtc@800 { // Real time clock
126 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; 119 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
127 reg = <0x800 0x100>; 120 reg = <0x800 0x100>;
128 interrupts = <1 5 0 1 6 0>; 121 interrupts = <1 5 0 1 6 0>;
129 interrupt-parent = <&mpc5200_pic>;
130 }; 122 };
131 123
132 can@980 { 124 can@980 {
133 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 125 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
134 interrupts = <2 18 0>; 126 interrupts = <2 18 0>;
135 interrupt-parent = <&mpc5200_pic>;
136 reg = <0x980 0x80>; 127 reg = <0x980 0x80>;
137 }; 128 };
138 129
139 gpio@b00 { 130 gpio_simple: gpio@b00 {
140 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 131 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
141 reg = <0xb00 0x40>; 132 reg = <0xb00 0x40>;
142 interrupts = <1 7 0>; 133 interrupts = <1 7 0>;
143 interrupt-parent = <&mpc5200_pic>; 134 gpio-controller;
135 #gpio-cells = <2>;
144 }; 136 };
145 137
146 gpio@c00 { 138 gpio_wkup: gpio@c00 {
147 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 139 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
148 reg = <0xc00 0x40>; 140 reg = <0xc00 0x40>;
149 interrupts = <1 8 0 0 3 0>; 141 interrupts = <1 8 0 0 3 0>;
150 interrupt-parent = <&mpc5200_pic>; 142 gpio-controller;
143 #gpio-cells = <2>;
151 }; 144 };
152 145
153 spi@f00 { 146 spi@f00 {
154 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 147 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
155 reg = <0xf00 0x20>; 148 reg = <0xf00 0x20>;
156 interrupts = <2 13 0 2 14 0>; 149 interrupts = <2 13 0 2 14 0>;
157 interrupt-parent = <&mpc5200_pic>;
158 }; 150 };
159 151
160 usb@1000 { 152 usb@1000 {
161 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; 153 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
162 reg = <0x1000 0xff>; 154 reg = <0x1000 0xff>;
163 interrupts = <2 6 0>; 155 interrupts = <2 6 0>;
164 interrupt-parent = <&mpc5200_pic>;
165 }; 156 };
166 157
167 dma-controller@1200 { 158 dma-controller@1200 {
@@ -171,7 +162,6 @@
171 3 4 0 3 5 0 3 6 0 3 7 0 162 3 4 0 3 5 0 3 6 0 3 7 0
172 3 8 0 3 9 0 3 10 0 3 11 0 163 3 8 0 3 9 0 3 10 0 3 11 0
173 3 12 0 3 13 0 3 14 0 3 15 0>; 164 3 12 0 3 13 0 3 14 0 3 15 0>;
174 interrupt-parent = <&mpc5200_pic>;
175 }; 165 };
176 166
177 xlb@1f00 { 167 xlb@1f00 {
@@ -180,12 +170,9 @@
180 }; 170 };
181 171
182 serial@2000 { // PSC1 172 serial@2000 { // PSC1
183 device_type = "serial";
184 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 173 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
185 port-number = <0>; // Logical port assignment
186 reg = <0x2000 0x100>; 174 reg = <0x2000 0x100>;
187 interrupts = <2 1 0>; 175 interrupts = <2 1 0>;
188 interrupt-parent = <&mpc5200_pic>;
189 }; 176 };
190 177
191 // PSC2 in spi master mode 178 // PSC2 in spi master mode
@@ -194,26 +181,20 @@
194 cell-index = <1>; 181 cell-index = <1>;
195 reg = <0x2200 0x100>; 182 reg = <0x2200 0x100>;
196 interrupts = <2 2 0>; 183 interrupts = <2 2 0>;
197 interrupt-parent = <&mpc5200_pic>;
198 }; 184 };
199 185
200 // PSC5 in uart mode 186 // PSC5 in uart mode
201 serial@2800 { // PSC5 187 serial@2800 { // PSC5
202 device_type = "serial";
203 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 188 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
204 port-number = <4>; // Logical port assignment
205 reg = <0x2800 0x100>; 189 reg = <0x2800 0x100>;
206 interrupts = <2 12 0>; 190 interrupts = <2 12 0>;
207 interrupt-parent = <&mpc5200_pic>;
208 }; 191 };
209 192
210 ethernet@3000 { 193 ethernet@3000 {
211 device_type = "network";
212 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; 194 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
213 reg = <0x3000 0x400>; 195 reg = <0x3000 0x400>;
214 local-mac-address = [ 00 00 00 00 00 00 ]; 196 local-mac-address = [ 00 00 00 00 00 00 ];
215 interrupts = <2 5 0>; 197 interrupts = <2 5 0>;
216 interrupt-parent = <&mpc5200_pic>;
217 phy-handle = <&phy0>; 198 phy-handle = <&phy0>;
218 }; 199 };
219 200
@@ -223,10 +204,8 @@
223 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; 204 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
224 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts 205 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
225 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 206 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
226 interrupt-parent = <&mpc5200_pic>;
227 207
228 phy0: ethernet-phy@2 { 208 phy0: ethernet-phy@2 {
229 device_type = "ethernet-phy";
230 reg = <2>; 209 reg = <2>;
231 }; 210 };
232 }; 211 };
@@ -235,7 +214,6 @@
235 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; 214 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
236 reg = <0x3a00 0x100>; 215 reg = <0x3a00 0x100>;
237 interrupts = <2 7 0>; 216 interrupts = <2 7 0>;
238 interrupt-parent = <&mpc5200_pic>;
239 }; 217 };
240 218
241 i2c@3d40 { 219 i2c@3d40 {
@@ -244,7 +222,6 @@
244 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 222 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
245 reg = <0x3d40 0x40>; 223 reg = <0x3d40 0x40>;
246 interrupts = <2 16 0>; 224 interrupts = <2 16 0>;
247 interrupt-parent = <&mpc5200_pic>;
248 fsl5200-clocking; 225 fsl5200-clocking;
249 226
250 rtc@68 { 227 rtc@68 {
@@ -259,8 +236,8 @@
259 }; 236 };
260 }; 237 };
261 238
262 lpb { 239 localbus {
263 compatible = "fsl,lpb"; 240 compatible = "fsl,mpc5200b-lpb","simple-bus";
264 #address-cells = <2>; 241 #address-cells = <2>;
265 #size-cells = <1>; 242 #size-cells = <1>;
266 ranges = <0 0 0xff000000 0x01000000 243 ranges = <0 0 0xff000000 0x01000000
@@ -273,7 +250,6 @@
273 compatible = "promess,motionpro-kollmorgen"; 250 compatible = "promess,motionpro-kollmorgen";
274 reg = <1 0 0x10000>; 251 reg = <1 0 0x10000>;
275 interrupts = <1 1 0>; 252 interrupts = <1 1 0>;
276 interrupt-parent = <&mpc5200_pic>;
277 }; 253 };
278 254
279 // 8-bit board CPLD on LocalPlus Bus CS2 255 // 8-bit board CPLD on LocalPlus Bus CS2
diff --git a/arch/powerpc/boot/dts/pcm030.dts b/arch/powerpc/boot/dts/pcm030.dts
index be2c11ca0594..895834713894 100644
--- a/arch/powerpc/boot/dts/pcm030.dts
+++ b/arch/powerpc/boot/dts/pcm030.dts
@@ -19,6 +19,7 @@
19 compatible = "phytec,pcm030"; 19 compatible = "phytec,pcm030";
20 #address-cells = <1>; 20 #address-cells = <1>;
21 #size-cells = <1>; 21 #size-cells = <1>;
22 interrupt-parent = <&mpc5200_pic>;
22 23
23 cpus { 24 cpus {
24 #address-cells = <1>; 25 #address-cells = <1>;
@@ -29,26 +30,26 @@
29 reg = <0>; 30 reg = <0>;
30 d-cache-line-size = <32>; 31 d-cache-line-size = <32>;
31 i-cache-line-size = <32>; 32 i-cache-line-size = <32>;
32 d-cache-size = <0x4000>; /* L1, 16K */ 33 d-cache-size = <0x4000>; // L1, 16K
33 i-cache-size = <0x4000>; /* L1, 16K */ 34 i-cache-size = <0x4000>; // L1, 16K
34 timebase-frequency = <0>; /* From Bootloader */ 35 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; /* From Bootloader */ 36 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; /* From Bootloader */ 37 clock-frequency = <0>; // from bootloader
37 }; 38 };
38 }; 39 };
39 40
40 memory { 41 memory {
41 device_type = "memory"; 42 device_type = "memory";
42 reg = <0x00000000 0x04000000>; /* 64MB */ 43 reg = <0x00000000 0x04000000>; // 64MB
43 }; 44 };
44 45
45 soc5200@f0000000 { 46 soc5200@f0000000 {
46 #address-cells = <1>; 47 #address-cells = <1>;
47 #size-cells = <1>; 48 #size-cells = <1>;
48 compatible = "fsl,mpc5200b-immr"; 49 compatible = "fsl,mpc5200b-immr";
49 ranges = <0x0 0xf0000000 0x0000c000>; 50 ranges = <0 0xf0000000 0x0000c000>;
50 bus-frequency = <0>; /* From bootloader */ 51 bus-frequency = <0>; // from bootloader
51 system-frequency = <0>; /* From bootloader */ 52 system-frequency = <0>; // from bootloader
52 53
53 cdm@200 { 54 cdm@200 {
54 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; 55 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
@@ -56,87 +57,70 @@
56 }; 57 };
57 58
58 mpc5200_pic: interrupt-controller@500 { 59 mpc5200_pic: interrupt-controller@500 {
59 /* 5200 interrupts are encoded into two levels; */ 60 // 5200 interrupts are encoded into two levels;
60 interrupt-controller; 61 interrupt-controller;
61 #interrupt-cells = <3>; 62 #interrupt-cells = <3>;
62 device_type = "interrupt-controller";
63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; 63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
64 reg = <0x500 0x80>; 64 reg = <0x500 0x80>;
65 }; 65 };
66 66
67 timer@600 { /* General Purpose Timer */ 67 timer@600 { // General Purpose Timer
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69 cell-index = <0>;
70 reg = <0x600 0x10>; 69 reg = <0x600 0x10>;
71 interrupts = <0x1 0x9 0x0>; 70 interrupts = <1 9 0>;
72 interrupt-parent = <&mpc5200_pic>;
73 fsl,has-wdt; 71 fsl,has-wdt;
74 }; 72 };
75 73
76 timer@610 { /* General Purpose Timer */ 74 timer@610 { // General Purpose Timer
77 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 75 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
78 cell-index = <1>;
79 reg = <0x610 0x10>; 76 reg = <0x610 0x10>;
80 interrupts = <0x1 0xa 0x0>; 77 interrupts = <1 10 0>;
81 interrupt-parent = <&mpc5200_pic>;
82 }; 78 };
83 79
84 gpt2: timer@620 { /* General Purpose Timer in GPIO mode */ 80 gpt2: timer@620 { // General Purpose Timer in GPIO mode
85 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 81 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
86 cell-index = <2>;
87 reg = <0x620 0x10>; 82 reg = <0x620 0x10>;
88 interrupts = <0x1 0xb 0x0>; 83 interrupts = <1 11 0>;
89 interrupt-parent = <&mpc5200_pic>;
90 gpio-controller; 84 gpio-controller;
91 #gpio-cells = <2>; 85 #gpio-cells = <2>;
92 }; 86 };
93 87
94 gpt3: timer@630 { /* General Purpose Timer in GPIO mode */ 88 gpt3: timer@630 { // General Purpose Timer in GPIO mode
95 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 89 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
96 cell-index = <3>;
97 reg = <0x630 0x10>; 90 reg = <0x630 0x10>;
98 interrupts = <0x1 0xc 0x0>; 91 interrupts = <1 12 0>;
99 interrupt-parent = <&mpc5200_pic>;
100 gpio-controller; 92 gpio-controller;
101 #gpio-cells = <2>; 93 #gpio-cells = <2>;
102 }; 94 };
103 95
104 gpt4: timer@640 { /* General Purpose Timer in GPIO mode */ 96 gpt4: timer@640 { // General Purpose Timer in GPIO mode
105 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 97 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
106 cell-index = <4>;
107 reg = <0x640 0x10>; 98 reg = <0x640 0x10>;
108 interrupts = <0x1 0xd 0x0>; 99 interrupts = <1 13 0>;
109 interrupt-parent = <&mpc5200_pic>;
110 gpio-controller; 100 gpio-controller;
111 #gpio-cells = <2>; 101 #gpio-cells = <2>;
112 }; 102 };
113 103
114 gpt5: timer@650 { /* General Purpose Timer in GPIO mode */ 104 gpt5: timer@650 { // General Purpose Timer in GPIO mode
115 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 105 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
116 cell-index = <5>;
117 reg = <0x650 0x10>; 106 reg = <0x650 0x10>;
118 interrupts = <0x1 0xe 0x0>; 107 interrupts = <1 14 0>;
119 interrupt-parent = <&mpc5200_pic>;
120 gpio-controller; 108 gpio-controller;
121 #gpio-cells = <2>; 109 #gpio-cells = <2>;
122 }; 110 };
123 111
124 gpt6: timer@660 { /* General Purpose Timer in GPIO mode */ 112 gpt6: timer@660 { // General Purpose Timer in GPIO mode
125 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 113 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
126 cell-index = <6>;
127 reg = <0x660 0x10>; 114 reg = <0x660 0x10>;
128 interrupts = <0x1 0xf 0x0>; 115 interrupts = <1 15 0>;
129 interrupt-parent = <&mpc5200_pic>;
130 gpio-controller; 116 gpio-controller;
131 #gpio-cells = <2>; 117 #gpio-cells = <2>;
132 }; 118 };
133 119
134 gpt7: timer@670 { /* General Purpose Timer in GPIO mode */ 120 gpt7: timer@670 { // General Purpose Timer in GPIO mode
135 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 121 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
136 cell-index = <7>;
137 reg = <0x670 0x10>; 122 reg = <0x670 0x10>;
138 interrupts = <0x1 0x10 0x0>; 123 interrupts = <1 16 0>;
139 interrupt-parent = <&mpc5200_pic>;
140 gpio-controller; 124 gpio-controller;
141 #gpio-cells = <2>; 125 #gpio-cells = <2>;
142 }; 126 };
@@ -144,40 +128,33 @@
144 rtc@800 { // Real time clock 128 rtc@800 { // Real time clock
145 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; 129 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
146 reg = <0x800 0x100>; 130 reg = <0x800 0x100>;
147 interrupts = <0x1 0x5 0x0 0x1 0x6 0x0>; 131 interrupts = <1 5 0 1 6 0>;
148 interrupt-parent = <&mpc5200_pic>;
149 }; 132 };
150 133
151 can@900 { 134 can@900 {
152 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 135 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
153 cell-index = <0>; 136 interrupts = <2 17 0>;
154 interrupts = <0x2 0x11 0x0>;
155 interrupt-parent = <&mpc5200_pic>;
156 reg = <0x900 0x80>; 137 reg = <0x900 0x80>;
157 }; 138 };
158 139
159 can@980 { 140 can@980 {
160 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 141 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
161 cell-index = <1>; 142 interrupts = <2 18 0>;
162 interrupts = <0x2 0x12 0x0>;
163 interrupt-parent = <&mpc5200_pic>;
164 reg = <0x980 0x80>; 143 reg = <0x980 0x80>;
165 }; 144 };
166 145
167 gpio_simple: gpio@b00 { 146 gpio_simple: gpio@b00 {
168 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 147 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
169 reg = <0xb00 0x40>; 148 reg = <0xb00 0x40>;
170 interrupts = <0x1 0x7 0x0>; 149 interrupts = <1 7 0>;
171 interrupt-parent = <&mpc5200_pic>;
172 gpio-controller; 150 gpio-controller;
173 #gpio-cells = <2>; 151 #gpio-cells = <2>;
174 }; 152 };
175 153
176 gpio_wkup: gpio-wkup@c00 { 154 gpio_wkup: gpio@c00 {
177 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 155 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
178 reg = <0xc00 0x40>; 156 reg = <0xc00 0x40>;
179 interrupts = <0x1 0x8 0x0 0x0 0x3 0x0>; 157 interrupts = <1 8 0 0 3 0>;
180 interrupt-parent = <&mpc5200_pic>;
181 gpio-controller; 158 gpio-controller;
182 #gpio-cells = <2>; 159 #gpio-cells = <2>;
183 }; 160 };
@@ -185,26 +162,22 @@
185 spi@f00 { 162 spi@f00 {
186 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 163 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
187 reg = <0xf00 0x20>; 164 reg = <0xf00 0x20>;
188 interrupts = <0x2 0xd 0x0 0x2 0xe 0x0>; 165 interrupts = <2 13 0 2 14 0>;
189 interrupt-parent = <&mpc5200_pic>;
190 }; 166 };
191 167
192 usb@1000 { 168 usb@1000 {
193 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; 169 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
194 reg = <0x1000 0xff>; 170 reg = <0x1000 0xff>;
195 interrupts = <0x2 0x6 0x0>; 171 interrupts = <2 6 0>;
196 interrupt-parent = <&mpc5200_pic>;
197 }; 172 };
198 173
199 dma-controller@1200 { 174 dma-controller@1200 {
200 device_type = "dma-controller";
201 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; 175 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
202 reg = <0x1200 0x80>; 176 reg = <0x1200 0x80>;
203 interrupts = <0x3 0x0 0x0 0x3 0x1 0x0 0x3 0x2 0x0 0x3 0x3 0x0 177 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
204 0x3 0x4 0x0 0x3 0x5 0x0 0x3 0x6 0x0 0x3 0x7 0x0 178 3 4 0 3 5 0 3 6 0 3 7 0
205 0x3 0x8 0x0 0x3 0x9 0x0 0x3 0xa 0x0 0x3 0xb 0x0 179 3 8 0 3 9 0 3 10 0 3 11 0
206 0x3 0xc 0x0 0x3 0xd 0x0 0x3 0xe 0x0 0x3 0xf 0x0>; 180 3 12 0 3 13 0 3 14 0 3 15 0>;
207 interrupt-parent = <&mpc5200_pic>;
208 }; 181 };
209 182
210 xlb@1f00 { 183 xlb@1f00 {
@@ -213,24 +186,19 @@
213 }; 186 };
214 187
215 ac97@2000 { /* PSC1 in ac97 mode */ 188 ac97@2000 { /* PSC1 in ac97 mode */
216 device_type = "sound";
217 compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97"; 189 compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97";
218 cell-index = <0>; 190 cell-index = <0>;
219 reg = <0x2000 0x100>; 191 reg = <0x2000 0x100>;
220 interrupts = <0x2 0x2 0x0>; 192 interrupts = <2 1 0>;
221 interrupt-parent = <&mpc5200_pic>;
222 }; 193 };
223 194
224 /* PSC2 port is used by CAN1/2 */ 195 /* PSC2 port is used by CAN1/2 */
225 196
226 serial@2400 { /* PSC3 in UART mode */ 197 serial@2400 { /* PSC3 in UART mode */
227 device_type = "serial";
228 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 198 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
229 port-number = <0>;
230 cell-index = <2>; 199 cell-index = <2>;
231 reg = <0x2400 0x100>; 200 reg = <0x2400 0x100>;
232 interrupts = <0x2 0x3 0x0>; 201 interrupts = <2 3 0>;
233 interrupt-parent = <&mpc5200_pic>;
234 }; 202 };
235 203
236 /* PSC4 is ??? */ 204 /* PSC4 is ??? */
@@ -238,55 +206,44 @@
238 /* PSC5 is ??? */ 206 /* PSC5 is ??? */
239 207
240 serial@2c00 { /* PSC6 in UART mode */ 208 serial@2c00 { /* PSC6 in UART mode */
241 device_type = "serial";
242 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 209 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
243 port-number = <1>;
244 cell-index = <5>; 210 cell-index = <5>;
245 reg = <0x2c00 0x100>; 211 reg = <0x2c00 0x100>;
246 interrupts = <0x2 0x4 0x0>; 212 interrupts = <2 4 0>;
247 interrupt-parent = <&mpc5200_pic>;
248 }; 213 };
249 214
250 ethernet@3000 { 215 ethernet@3000 {
251 device_type = "network";
252 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; 216 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
253 reg = <0x3000 0x400>; 217 reg = <0x3000 0x400>;
254 local-mac-address = [00 00 00 00 00 00]; 218 local-mac-address = [ 00 00 00 00 00 00 ];
255 interrupts = <0x2 0x5 0x0>; 219 interrupts = <2 5 0>;
256 interrupt-parent = <&mpc5200_pic>;
257 phy-handle = <&phy0>; 220 phy-handle = <&phy0>;
258 }; 221 };
259 222
260 mdio@3000 { 223 mdio@3000 {
261 #address-cells = <1>; 224 #address-cells = <1>;
262 #size-cells = <0>; 225 #size-cells = <0>;
263 compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio"; 226 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
264 reg = <0x3000 0x400>; /* fec range, since we need to setup fec interrupts */ 227 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
265 interrupts = <0x2 0x5 0x0>; /* these are for "mii command finished", not link changes & co. */ 228 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
266 interrupt-parent = <&mpc5200_pic>; 229
267 230 phy0: ethernet-phy@0 {
268 phy0:ethernet-phy@0 { 231 reg = <0>;
269 device_type = "ethernet-phy";
270 reg = <0x0>;
271 }; 232 };
272 }; 233 };
273 234
274 ata@3a00 { 235 ata@3a00 {
275 device_type = "ata";
276 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; 236 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
277 reg = <0x3a00 0x100>; 237 reg = <0x3a00 0x100>;
278 interrupts = <0x2 0x7 0x0>; 238 interrupts = <2 7 0>;
279 interrupt-parent = <&mpc5200_pic>;
280 }; 239 };
281 240
282 i2c@3d00 { 241 i2c@3d00 {
283 #address-cells = <1>; 242 #address-cells = <1>;
284 #size-cells = <0>; 243 #size-cells = <0>;
285 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 244 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
286 cell-index = <0>;
287 reg = <0x3d00 0x40>; 245 reg = <0x3d00 0x40>;
288 interrupts = <0x2 0xf 0x0>; 246 interrupts = <2 15 0>;
289 interrupt-parent = <&mpc5200_pic>;
290 fsl5200-clocking; 247 fsl5200-clocking;
291 }; 248 };
292 249
@@ -294,10 +251,8 @@
294 #address-cells = <1>; 251 #address-cells = <1>;
295 #size-cells = <0>; 252 #size-cells = <0>;
296 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 253 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
297 cell-index = <1>;
298 reg = <0x3d40 0x40>; 254 reg = <0x3d40 0x40>;
299 interrupts = <0x2 0x10 0x0>; 255 interrupts = <2 16 0>;
300 interrupt-parent = <&mpc5200_pic>;
301 fsl5200-clocking; 256 fsl5200-clocking;
302 rtc@51 { 257 rtc@51 {
303 compatible = "nxp,pcf8563"; 258 compatible = "nxp,pcf8563";
@@ -307,7 +262,7 @@
307 }; 262 };
308 263
309 sram@8000 { 264 sram@8000 {
310 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram"; 265 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
311 reg = <0x8000 0x4000>; 266 reg = <0x8000 0x4000>;
312 }; 267 };
313 268
@@ -340,22 +295,21 @@
340 device_type = "pci"; 295 device_type = "pci";
341 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci"; 296 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
342 reg = <0xf0000d00 0x100>; 297 reg = <0xf0000d00 0x100>;
343 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 298 interrupt-map-mask = <0xf800 0 0 7>;
344 interrupt-map = <0xc000 0x0 0x0 0x1 &mpc5200_pic 0x0 0x0 0x3 /* 1st slot */ 299 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
345 0xc000 0x0 0x0 0x2 &mpc5200_pic 0x1 0x1 0x3 300 0xc000 0 0 2 &mpc5200_pic 1 1 3
346 0xc000 0x0 0x0 0x3 &mpc5200_pic 0x1 0x2 0x3 301 0xc000 0 0 3 &mpc5200_pic 1 2 3
347 0xc000 0x0 0x0 0x4 &mpc5200_pic 0x1 0x3 0x3 302 0xc000 0 0 4 &mpc5200_pic 1 3 3
348 303
349 0xc800 0x0 0x0 0x1 &mpc5200_pic 0x1 0x1 0x3 /* 2nd slot */ 304 0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
350 0xc800 0x0 0x0 0x2 &mpc5200_pic 0x1 0x2 0x3 305 0xc800 0 0 2 &mpc5200_pic 1 2 3
351 0xc800 0x0 0x0 0x3 &mpc5200_pic 0x1 0x3 0x3 306 0xc800 0 0 3 &mpc5200_pic 1 3 3
352 0xc800 0x0 0x0 0x4 &mpc5200_pic 0x0 0x0 0x3>; 307 0xc800 0 0 4 &mpc5200_pic 0 0 3>;
353 clock-frequency = <0>; // From boot loader 308 clock-frequency = <0>; // From boot loader
354 interrupts = <0x2 0x8 0x0 0x2 0x9 0x0 0x2 0xa 0x0>; 309 interrupts = <2 8 0 2 9 0 2 10 0>;
355 interrupt-parent = <&mpc5200_pic>;
356 bus-range = <0 0>; 310 bus-range = <0 0>;
357 ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000 311 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
358 0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 312 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
359 0x01000000 0x0 0x00000000 0xb0000000 0x0 0x01000000>; 313 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
360 }; 314 };
361}; 315};
diff --git a/arch/powerpc/boot/dts/tqm5200.dts b/arch/powerpc/boot/dts/tqm5200.dts
index 906302e26a62..c9590b58b7b0 100644
--- a/arch/powerpc/boot/dts/tqm5200.dts
+++ b/arch/powerpc/boot/dts/tqm5200.dts
@@ -17,6 +17,7 @@
17 compatible = "tqc,tqm5200"; 17 compatible = "tqc,tqm5200";
18 #address-cells = <1>; 18 #address-cells = <1>;
19 #size-cells = <1>; 19 #size-cells = <1>;
20 interrupt-parent = <&mpc5200_pic>;
20 21
21 cpus { 22 cpus {
22 #address-cells = <1>; 23 #address-cells = <1>;
@@ -66,36 +67,33 @@
66 compatible = "fsl,mpc5200-gpt"; 67 compatible = "fsl,mpc5200-gpt";
67 reg = <0x600 0x10>; 68 reg = <0x600 0x10>;
68 interrupts = <1 9 0>; 69 interrupts = <1 9 0>;
69 interrupt-parent = <&mpc5200_pic>;
70 fsl,has-wdt; 70 fsl,has-wdt;
71 }; 71 };
72 72
73 can@900 { 73 can@900 {
74 compatible = "fsl,mpc5200-mscan"; 74 compatible = "fsl,mpc5200-mscan";
75 interrupts = <2 17 0>; 75 interrupts = <2 17 0>;
76 interrupt-parent = <&mpc5200_pic>;
77 reg = <0x900 0x80>; 76 reg = <0x900 0x80>;
78 }; 77 };
79 78
80 can@980 { 79 can@980 {
81 compatible = "fsl,mpc5200-mscan"; 80 compatible = "fsl,mpc5200-mscan";
82 interrupts = <2 18 0>; 81 interrupts = <2 18 0>;
83 interrupt-parent = <&mpc5200_pic>;
84 reg = <0x980 0x80>; 82 reg = <0x980 0x80>;
85 }; 83 };
86 84
87 gpio@b00 { 85 gpio_simple: gpio@b00 {
88 compatible = "fsl,mpc5200-gpio"; 86 compatible = "fsl,mpc5200-gpio";
89 reg = <0xb00 0x40>; 87 reg = <0xb00 0x40>;
90 interrupts = <1 7 0>; 88 interrupts = <1 7 0>;
91 interrupt-parent = <&mpc5200_pic>; 89 gpio-controller;
90 #gpio-cells = <2>;
92 }; 91 };
93 92
94 usb@1000 { 93 usb@1000 {
95 compatible = "fsl,mpc5200-ohci","ohci-be"; 94 compatible = "fsl,mpc5200-ohci","ohci-be";
96 reg = <0x1000 0xff>; 95 reg = <0x1000 0xff>;
97 interrupts = <2 6 0>; 96 interrupts = <2 6 0>;
98 interrupt-parent = <&mpc5200_pic>;
99 }; 97 };
100 98
101 dma-controller@1200 { 99 dma-controller@1200 {
@@ -105,7 +103,6 @@
105 3 4 0 3 5 0 3 6 0 3 7 0 103 3 4 0 3 5 0 3 6 0 3 7 0
106 3 8 0 3 9 0 3 10 0 3 11 0 104 3 8 0 3 9 0 3 10 0 3 11 0
107 3 12 0 3 13 0 3 14 0 3 15 0>; 105 3 12 0 3 13 0 3 14 0 3 15 0>;
108 interrupt-parent = <&mpc5200_pic>;
109 }; 106 };
110 107
111 xlb@1f00 { 108 xlb@1f00 {
@@ -114,39 +111,28 @@
114 }; 111 };
115 112
116 serial@2000 { // PSC1 113 serial@2000 { // PSC1
117 device_type = "serial";
118 compatible = "fsl,mpc5200-psc-uart"; 114 compatible = "fsl,mpc5200-psc-uart";
119 port-number = <0>; // Logical port assignment
120 reg = <0x2000 0x100>; 115 reg = <0x2000 0x100>;
121 interrupts = <2 1 0>; 116 interrupts = <2 1 0>;
122 interrupt-parent = <&mpc5200_pic>;
123 }; 117 };
124 118
125 serial@2200 { // PSC2 119 serial@2200 { // PSC2
126 device_type = "serial";
127 compatible = "fsl,mpc5200-psc-uart"; 120 compatible = "fsl,mpc5200-psc-uart";
128 port-number = <1>; // Logical port assignment
129 reg = <0x2200 0x100>; 121 reg = <0x2200 0x100>;
130 interrupts = <2 2 0>; 122 interrupts = <2 2 0>;
131 interrupt-parent = <&mpc5200_pic>;
132 }; 123 };
133 124
134 serial@2400 { // PSC3 125 serial@2400 { // PSC3
135 device_type = "serial";
136 compatible = "fsl,mpc5200-psc-uart"; 126 compatible = "fsl,mpc5200-psc-uart";
137 port-number = <2>; // Logical port assignment
138 reg = <0x2400 0x100>; 127 reg = <0x2400 0x100>;
139 interrupts = <2 3 0>; 128 interrupts = <2 3 0>;
140 interrupt-parent = <&mpc5200_pic>;
141 }; 129 };
142 130
143 ethernet@3000 { 131 ethernet@3000 {
144 device_type = "network";
145 compatible = "fsl,mpc5200-fec"; 132 compatible = "fsl,mpc5200-fec";
146 reg = <0x3000 0x400>; 133 reg = <0x3000 0x400>;
147 local-mac-address = [ 00 00 00 00 00 00 ]; 134 local-mac-address = [ 00 00 00 00 00 00 ];
148 interrupts = <2 5 0>; 135 interrupts = <2 5 0>;
149 interrupt-parent = <&mpc5200_pic>;
150 phy-handle = <&phy0>; 136 phy-handle = <&phy0>;
151 }; 137 };
152 138
@@ -156,10 +142,8 @@
156 compatible = "fsl,mpc5200-mdio"; 142 compatible = "fsl,mpc5200-mdio";
157 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts 143 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
158 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 144 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
159 interrupt-parent = <&mpc5200_pic>;
160 145
161 phy0: ethernet-phy@0 { 146 phy0: ethernet-phy@0 {
162 device_type = "ethernet-phy";
163 reg = <0>; 147 reg = <0>;
164 }; 148 };
165 }; 149 };
@@ -168,7 +152,6 @@
168 compatible = "fsl,mpc5200-ata"; 152 compatible = "fsl,mpc5200-ata";
169 reg = <0x3a00 0x100>; 153 reg = <0x3a00 0x100>;
170 interrupts = <2 7 0>; 154 interrupts = <2 7 0>;
171 interrupt-parent = <&mpc5200_pic>;
172 }; 155 };
173 156
174 i2c@3d40 { 157 i2c@3d40 {
@@ -177,7 +160,6 @@
177 compatible = "fsl,mpc5200-i2c","fsl-i2c"; 160 compatible = "fsl,mpc5200-i2c","fsl-i2c";
178 reg = <0x3d40 0x40>; 161 reg = <0x3d40 0x40>;
179 interrupts = <2 16 0>; 162 interrupts = <2 16 0>;
180 interrupt-parent = <&mpc5200_pic>;
181 fsl5200-clocking; 163 fsl5200-clocking;
182 164
183 rtc@68 { 165 rtc@68 {
@@ -192,9 +174,8 @@
192 }; 174 };
193 }; 175 };
194 176
195 lpb { 177 localbus {
196 model = "fsl,lpb"; 178 compatible = "fsl,mpc5200-lpb","simple-bus";
197 compatible = "fsl,lpb";
198 #address-cells = <2>; 179 #address-cells = <2>;
199 #size-cells = <1>; 180 #size-cells = <1>;
200 ranges = <0 0 0xfc000000 0x02000000>; 181 ranges = <0 0 0xfc000000 0x02000000>;
@@ -223,7 +204,6 @@
223 0xc000 0 0 4 &mpc5200_pic 0 0 3>; 204 0xc000 0 0 4 &mpc5200_pic 0 0 3>;
224 clock-frequency = <0>; // From boot loader 205 clock-frequency = <0>; // From boot loader
225 interrupts = <2 8 0 2 9 0 2 10 0>; 206 interrupts = <2 8 0 2 9 0 2 10 0>;
226 interrupt-parent = <&mpc5200_pic>;
227 bus-range = <0 0>; 207 bus-range = <0 0>;
228 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000 208 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000
229 0x02000000 0 0x90000000 0x90000000 0 0x10000000 209 0x02000000 0 0x90000000 0x90000000 0 0x10000000
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-05 21:10:28 -0500