aboutsummaryrefslogtreecommitdiffstats
path: root/arch
diff options
context:
space:
mode:
authorPaul Mackerras <paulus@samba.org>2006-01-13 18:11:39 -0500
committerPaul Mackerras <paulus@samba.org>2006-01-13 18:11:39 -0500
commit80f15dc703b3677d0b025bafd215f1f3664c8978 (patch)
treefa60781edcedefe4eb6baa6d213a62bbc6d7803a /arch
parent25cd6aa0aa059b48cdcef2a00981b14fafd5161a (diff)
powerpc: Provide a suitable AT_PLATFORM value
The glibc folks want to use AT_PLATFORM to select between possible alternative versions of shared libraries. This commit makes the kernel supply an AT_PLATFORM string that indicates what class of processor we are running on. Processors with the same set of user-level instructions and roughly the same instruction scheduling characteristics are given the same AT_PLATFORM value; for example, 821, 823 and 860 are all reported as "ppc823", and 7447, 7447A, 7448, 7450, 7451, 7455 are all called "ppc7450". The intention is that the AT_PLATFORM values match the values that gcc accepts for the -mcpu= option. For values which are numeric (e.g. -mcpu=750), "ppc" has been prepended. This also adds a PPC_FEATURE_BOOKE bit to the AT_HWCAP value and sets it for the 440 family and the Freescale 85xx family. Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/kernel/cputable.c172
1 files changed, 128 insertions, 44 deletions
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 43c74a6b07b1..cf1eea1a2299 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -55,7 +55,8 @@ extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
55#define COMMON_USER_POWER4 (COMMON_USER_PPC64 | PPC_FEATURE_POWER4) 55#define COMMON_USER_POWER4 (COMMON_USER_PPC64 | PPC_FEATURE_POWER4)
56#define COMMON_USER_POWER5 (COMMON_USER_PPC64 | PPC_FEATURE_POWER5) 56#define COMMON_USER_POWER5 (COMMON_USER_PPC64 | PPC_FEATURE_POWER5)
57#define COMMON_USER_POWER5_PLUS (COMMON_USER_PPC64 | PPC_FEATURE_POWER5_PLUS) 57#define COMMON_USER_POWER5_PLUS (COMMON_USER_PPC64 | PPC_FEATURE_POWER5_PLUS)
58 58#define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \
59 PPC_FEATURE_BOOKE)
59 60
60/* We only set the spe features if the kernel was compiled with 61/* We only set the spe features if the kernel was compiled with
61 * spe support 62 * spe support
@@ -80,6 +81,7 @@ struct cpu_spec cpu_specs[] = {
80 .cpu_setup = __setup_cpu_power3, 81 .cpu_setup = __setup_cpu_power3,
81 .oprofile_cpu_type = "ppc64/power3", 82 .oprofile_cpu_type = "ppc64/power3",
82 .oprofile_type = RS64, 83 .oprofile_type = RS64,
84 .platform = "power3",
83 }, 85 },
84 { /* Power3+ */ 86 { /* Power3+ */
85 .pvr_mask = 0xffff0000, 87 .pvr_mask = 0xffff0000,
@@ -93,6 +95,7 @@ struct cpu_spec cpu_specs[] = {
93 .cpu_setup = __setup_cpu_power3, 95 .cpu_setup = __setup_cpu_power3,
94 .oprofile_cpu_type = "ppc64/power3", 96 .oprofile_cpu_type = "ppc64/power3",
95 .oprofile_type = RS64, 97 .oprofile_type = RS64,
98 .platform = "power3",
96 }, 99 },
97 { /* Northstar */ 100 { /* Northstar */
98 .pvr_mask = 0xffff0000, 101 .pvr_mask = 0xffff0000,
@@ -106,6 +109,7 @@ struct cpu_spec cpu_specs[] = {
106 .cpu_setup = __setup_cpu_power3, 109 .cpu_setup = __setup_cpu_power3,
107 .oprofile_cpu_type = "ppc64/rs64", 110 .oprofile_cpu_type = "ppc64/rs64",
108 .oprofile_type = RS64, 111 .oprofile_type = RS64,
112 .platform = "rs64",
109 }, 113 },
110 { /* Pulsar */ 114 { /* Pulsar */
111 .pvr_mask = 0xffff0000, 115 .pvr_mask = 0xffff0000,
@@ -119,6 +123,7 @@ struct cpu_spec cpu_specs[] = {
119 .cpu_setup = __setup_cpu_power3, 123 .cpu_setup = __setup_cpu_power3,
120 .oprofile_cpu_type = "ppc64/rs64", 124 .oprofile_cpu_type = "ppc64/rs64",
121 .oprofile_type = RS64, 125 .oprofile_type = RS64,
126 .platform = "rs64",
122 }, 127 },
123 { /* I-star */ 128 { /* I-star */
124 .pvr_mask = 0xffff0000, 129 .pvr_mask = 0xffff0000,
@@ -132,6 +137,7 @@ struct cpu_spec cpu_specs[] = {
132 .cpu_setup = __setup_cpu_power3, 137 .cpu_setup = __setup_cpu_power3,
133 .oprofile_cpu_type = "ppc64/rs64", 138 .oprofile_cpu_type = "ppc64/rs64",
134 .oprofile_type = RS64, 139 .oprofile_type = RS64,
140 .platform = "rs64",
135 }, 141 },
136 { /* S-star */ 142 { /* S-star */
137 .pvr_mask = 0xffff0000, 143 .pvr_mask = 0xffff0000,
@@ -145,6 +151,7 @@ struct cpu_spec cpu_specs[] = {
145 .cpu_setup = __setup_cpu_power3, 151 .cpu_setup = __setup_cpu_power3,
146 .oprofile_cpu_type = "ppc64/rs64", 152 .oprofile_cpu_type = "ppc64/rs64",
147 .oprofile_type = RS64, 153 .oprofile_type = RS64,
154 .platform = "rs64",
148 }, 155 },
149 { /* Power4 */ 156 { /* Power4 */
150 .pvr_mask = 0xffff0000, 157 .pvr_mask = 0xffff0000,
@@ -158,6 +165,7 @@ struct cpu_spec cpu_specs[] = {
158 .cpu_setup = __setup_cpu_power4, 165 .cpu_setup = __setup_cpu_power4,
159 .oprofile_cpu_type = "ppc64/power4", 166 .oprofile_cpu_type = "ppc64/power4",
160 .oprofile_type = POWER4, 167 .oprofile_type = POWER4,
168 .platform = "power4",
161 }, 169 },
162 { /* Power4+ */ 170 { /* Power4+ */
163 .pvr_mask = 0xffff0000, 171 .pvr_mask = 0xffff0000,
@@ -171,6 +179,7 @@ struct cpu_spec cpu_specs[] = {
171 .cpu_setup = __setup_cpu_power4, 179 .cpu_setup = __setup_cpu_power4,
172 .oprofile_cpu_type = "ppc64/power4", 180 .oprofile_cpu_type = "ppc64/power4",
173 .oprofile_type = POWER4, 181 .oprofile_type = POWER4,
182 .platform = "power4",
174 }, 183 },
175 { /* PPC970 */ 184 { /* PPC970 */
176 .pvr_mask = 0xffff0000, 185 .pvr_mask = 0xffff0000,
@@ -185,6 +194,7 @@ struct cpu_spec cpu_specs[] = {
185 .cpu_setup = __setup_cpu_ppc970, 194 .cpu_setup = __setup_cpu_ppc970,
186 .oprofile_cpu_type = "ppc64/970", 195 .oprofile_cpu_type = "ppc64/970",
187 .oprofile_type = POWER4, 196 .oprofile_type = POWER4,
197 .platform = "ppc970",
188 }, 198 },
189#endif /* CONFIG_PPC64 */ 199#endif /* CONFIG_PPC64 */
190#if defined(CONFIG_PPC64) || defined(CONFIG_POWER4) 200#if defined(CONFIG_PPC64) || defined(CONFIG_POWER4)
@@ -205,6 +215,7 @@ struct cpu_spec cpu_specs[] = {
205 .cpu_setup = __setup_cpu_ppc970, 215 .cpu_setup = __setup_cpu_ppc970,
206 .oprofile_cpu_type = "ppc64/970", 216 .oprofile_cpu_type = "ppc64/970",
207 .oprofile_type = POWER4, 217 .oprofile_type = POWER4,
218 .platform = "ppc970",
208 }, 219 },
209#endif /* defined(CONFIG_PPC64) || defined(CONFIG_POWER4) */ 220#endif /* defined(CONFIG_PPC64) || defined(CONFIG_POWER4) */
210#ifdef CONFIG_PPC64 221#ifdef CONFIG_PPC64
@@ -220,6 +231,7 @@ struct cpu_spec cpu_specs[] = {
220 .cpu_setup = __setup_cpu_ppc970, 231 .cpu_setup = __setup_cpu_ppc970,
221 .oprofile_cpu_type = "ppc64/970", 232 .oprofile_cpu_type = "ppc64/970",
222 .oprofile_type = POWER4, 233 .oprofile_type = POWER4,
234 .platform = "ppc970",
223 }, 235 },
224 { /* Power5 GR */ 236 { /* Power5 GR */
225 .pvr_mask = 0xffff0000, 237 .pvr_mask = 0xffff0000,
@@ -233,6 +245,7 @@ struct cpu_spec cpu_specs[] = {
233 .cpu_setup = __setup_cpu_power4, 245 .cpu_setup = __setup_cpu_power4,
234 .oprofile_cpu_type = "ppc64/power5", 246 .oprofile_cpu_type = "ppc64/power5",
235 .oprofile_type = POWER4, 247 .oprofile_type = POWER4,
248 .platform = "power5",
236 }, 249 },
237 { /* Power5 GS */ 250 { /* Power5 GS */
238 .pvr_mask = 0xffff0000, 251 .pvr_mask = 0xffff0000,
@@ -246,6 +259,7 @@ struct cpu_spec cpu_specs[] = {
246 .cpu_setup = __setup_cpu_power4, 259 .cpu_setup = __setup_cpu_power4,
247 .oprofile_cpu_type = "ppc64/power5+", 260 .oprofile_cpu_type = "ppc64/power5+",
248 .oprofile_type = POWER4, 261 .oprofile_type = POWER4,
262 .platform = "power5+",
249 }, 263 },
250 { /* Cell Broadband Engine */ 264 { /* Cell Broadband Engine */
251 .pvr_mask = 0xffff0000, 265 .pvr_mask = 0xffff0000,
@@ -257,6 +271,7 @@ struct cpu_spec cpu_specs[] = {
257 .icache_bsize = 128, 271 .icache_bsize = 128,
258 .dcache_bsize = 128, 272 .dcache_bsize = 128,
259 .cpu_setup = __setup_cpu_be, 273 .cpu_setup = __setup_cpu_be,
274 .platform = "ppc-cell-be",
260 }, 275 },
261 { /* default match */ 276 { /* default match */
262 .pvr_mask = 0x00000000, 277 .pvr_mask = 0x00000000,
@@ -268,6 +283,7 @@ struct cpu_spec cpu_specs[] = {
268 .dcache_bsize = 128, 283 .dcache_bsize = 128,
269 .num_pmcs = 6, 284 .num_pmcs = 6,
270 .cpu_setup = __setup_cpu_power4, 285 .cpu_setup = __setup_cpu_power4,
286 .platform = "power4",
271 } 287 }
272#endif /* CONFIG_PPC64 */ 288#endif /* CONFIG_PPC64 */
273#ifdef CONFIG_PPC32 289#ifdef CONFIG_PPC32
@@ -281,6 +297,7 @@ struct cpu_spec cpu_specs[] = {
281 PPC_FEATURE_UNIFIED_CACHE | PPC_FEATURE_NO_TB, 297 PPC_FEATURE_UNIFIED_CACHE | PPC_FEATURE_NO_TB,
282 .icache_bsize = 32, 298 .icache_bsize = 32,
283 .dcache_bsize = 32, 299 .dcache_bsize = 32,
300 .platform = "ppc601",
284 }, 301 },
285 { /* 603 */ 302 { /* 603 */
286 .pvr_mask = 0xffff0000, 303 .pvr_mask = 0xffff0000,
@@ -290,7 +307,8 @@ struct cpu_spec cpu_specs[] = {
290 .cpu_user_features = COMMON_USER, 307 .cpu_user_features = COMMON_USER,
291 .icache_bsize = 32, 308 .icache_bsize = 32,
292 .dcache_bsize = 32, 309 .dcache_bsize = 32,
293 .cpu_setup = __setup_cpu_603 310 .cpu_setup = __setup_cpu_603,
311 .platform = "ppc603",
294 }, 312 },
295 { /* 603e */ 313 { /* 603e */
296 .pvr_mask = 0xffff0000, 314 .pvr_mask = 0xffff0000,
@@ -300,7 +318,8 @@ struct cpu_spec cpu_specs[] = {
300 .cpu_user_features = COMMON_USER, 318 .cpu_user_features = COMMON_USER,
301 .icache_bsize = 32, 319 .icache_bsize = 32,
302 .dcache_bsize = 32, 320 .dcache_bsize = 32,
303 .cpu_setup = __setup_cpu_603 321 .cpu_setup = __setup_cpu_603,
322 .platform = "ppc603",
304 }, 323 },
305 { /* 603ev */ 324 { /* 603ev */
306 .pvr_mask = 0xffff0000, 325 .pvr_mask = 0xffff0000,
@@ -310,7 +329,8 @@ struct cpu_spec cpu_specs[] = {
310 .cpu_user_features = COMMON_USER, 329 .cpu_user_features = COMMON_USER,
311 .icache_bsize = 32, 330 .icache_bsize = 32,
312 .dcache_bsize = 32, 331 .dcache_bsize = 32,
313 .cpu_setup = __setup_cpu_603 332 .cpu_setup = __setup_cpu_603,
333 .platform = "ppc603",
314 }, 334 },
315 { /* 604 */ 335 { /* 604 */
316 .pvr_mask = 0xffff0000, 336 .pvr_mask = 0xffff0000,
@@ -321,7 +341,8 @@ struct cpu_spec cpu_specs[] = {
321 .icache_bsize = 32, 341 .icache_bsize = 32,
322 .dcache_bsize = 32, 342 .dcache_bsize = 32,
323 .num_pmcs = 2, 343 .num_pmcs = 2,
324 .cpu_setup = __setup_cpu_604 344 .cpu_setup = __setup_cpu_604,
345 .platform = "ppc604",
325 }, 346 },
326 { /* 604e */ 347 { /* 604e */
327 .pvr_mask = 0xfffff000, 348 .pvr_mask = 0xfffff000,
@@ -332,7 +353,8 @@ struct cpu_spec cpu_specs[] = {
332 .icache_bsize = 32, 353 .icache_bsize = 32,
333 .dcache_bsize = 32, 354 .dcache_bsize = 32,
334 .num_pmcs = 4, 355 .num_pmcs = 4,
335 .cpu_setup = __setup_cpu_604 356 .cpu_setup = __setup_cpu_604,
357 .platform = "ppc604",
336 }, 358 },
337 { /* 604r */ 359 { /* 604r */
338 .pvr_mask = 0xffff0000, 360 .pvr_mask = 0xffff0000,
@@ -343,7 +365,8 @@ struct cpu_spec cpu_specs[] = {
343 .icache_bsize = 32, 365 .icache_bsize = 32,
344 .dcache_bsize = 32, 366 .dcache_bsize = 32,
345 .num_pmcs = 4, 367 .num_pmcs = 4,
346 .cpu_setup = __setup_cpu_604 368 .cpu_setup = __setup_cpu_604,
369 .platform = "ppc604",
347 }, 370 },
348 { /* 604ev */ 371 { /* 604ev */
349 .pvr_mask = 0xffff0000, 372 .pvr_mask = 0xffff0000,
@@ -354,7 +377,8 @@ struct cpu_spec cpu_specs[] = {
354 .icache_bsize = 32, 377 .icache_bsize = 32,
355 .dcache_bsize = 32, 378 .dcache_bsize = 32,
356 .num_pmcs = 4, 379 .num_pmcs = 4,
357 .cpu_setup = __setup_cpu_604 380 .cpu_setup = __setup_cpu_604,
381 .platform = "ppc604",
358 }, 382 },
359 { /* 740/750 (0x4202, don't support TAU ?) */ 383 { /* 740/750 (0x4202, don't support TAU ?) */
360 .pvr_mask = 0xffffffff, 384 .pvr_mask = 0xffffffff,
@@ -365,7 +389,8 @@ struct cpu_spec cpu_specs[] = {
365 .icache_bsize = 32, 389 .icache_bsize = 32,
366 .dcache_bsize = 32, 390 .dcache_bsize = 32,
367 .num_pmcs = 4, 391 .num_pmcs = 4,
368 .cpu_setup = __setup_cpu_750 392 .cpu_setup = __setup_cpu_750,
393 .platform = "ppc750",
369 }, 394 },
370 { /* 750CX (80100 and 8010x?) */ 395 { /* 750CX (80100 and 8010x?) */
371 .pvr_mask = 0xfffffff0, 396 .pvr_mask = 0xfffffff0,
@@ -376,7 +401,8 @@ struct cpu_spec cpu_specs[] = {
376 .icache_bsize = 32, 401 .icache_bsize = 32,
377 .dcache_bsize = 32, 402 .dcache_bsize = 32,
378 .num_pmcs = 4, 403 .num_pmcs = 4,
379 .cpu_setup = __setup_cpu_750cx 404 .cpu_setup = __setup_cpu_750cx,
405 .platform = "ppc750",
380 }, 406 },
381 { /* 750CX (82201 and 82202) */ 407 { /* 750CX (82201 and 82202) */
382 .pvr_mask = 0xfffffff0, 408 .pvr_mask = 0xfffffff0,
@@ -387,7 +413,8 @@ struct cpu_spec cpu_specs[] = {
387 .icache_bsize = 32, 413 .icache_bsize = 32,
388 .dcache_bsize = 32, 414 .dcache_bsize = 32,
389 .num_pmcs = 4, 415 .num_pmcs = 4,
390 .cpu_setup = __setup_cpu_750cx 416 .cpu_setup = __setup_cpu_750cx,
417 .platform = "ppc750",
391 }, 418 },
392 { /* 750CXe (82214) */ 419 { /* 750CXe (82214) */
393 .pvr_mask = 0xfffffff0, 420 .pvr_mask = 0xfffffff0,
@@ -398,7 +425,8 @@ struct cpu_spec cpu_specs[] = {
398 .icache_bsize = 32, 425 .icache_bsize = 32,
399 .dcache_bsize = 32, 426 .dcache_bsize = 32,
400 .num_pmcs = 4, 427 .num_pmcs = 4,
401 .cpu_setup = __setup_cpu_750cx 428 .cpu_setup = __setup_cpu_750cx,
429 .platform = "ppc750",
402 }, 430 },
403 { /* 750CXe "Gekko" (83214) */ 431 { /* 750CXe "Gekko" (83214) */
404 .pvr_mask = 0xffffffff, 432 .pvr_mask = 0xffffffff,
@@ -409,7 +437,8 @@ struct cpu_spec cpu_specs[] = {
409 .icache_bsize = 32, 437 .icache_bsize = 32,
410 .dcache_bsize = 32, 438 .dcache_bsize = 32,
411 .num_pmcs = 4, 439 .num_pmcs = 4,
412 .cpu_setup = __setup_cpu_750cx 440 .cpu_setup = __setup_cpu_750cx,
441 .platform = "ppc750",
413 }, 442 },
414 { /* 745/755 */ 443 { /* 745/755 */
415 .pvr_mask = 0xfffff000, 444 .pvr_mask = 0xfffff000,
@@ -420,7 +449,8 @@ struct cpu_spec cpu_specs[] = {
420 .icache_bsize = 32, 449 .icache_bsize = 32,
421 .dcache_bsize = 32, 450 .dcache_bsize = 32,
422 .num_pmcs = 4, 451 .num_pmcs = 4,
423 .cpu_setup = __setup_cpu_750 452 .cpu_setup = __setup_cpu_750,
453 .platform = "ppc750",
424 }, 454 },
425 { /* 750FX rev 1.x */ 455 { /* 750FX rev 1.x */
426 .pvr_mask = 0xffffff00, 456 .pvr_mask = 0xffffff00,
@@ -431,7 +461,8 @@ struct cpu_spec cpu_specs[] = {
431 .icache_bsize = 32, 461 .icache_bsize = 32,
432 .dcache_bsize = 32, 462 .dcache_bsize = 32,
433 .num_pmcs = 4, 463 .num_pmcs = 4,
434 .cpu_setup = __setup_cpu_750 464 .cpu_setup = __setup_cpu_750,
465 .platform = "ppc750",
435 }, 466 },
436 { /* 750FX rev 2.0 must disable HID0[DPM] */ 467 { /* 750FX rev 2.0 must disable HID0[DPM] */
437 .pvr_mask = 0xffffffff, 468 .pvr_mask = 0xffffffff,
@@ -442,7 +473,8 @@ struct cpu_spec cpu_specs[] = {
442 .icache_bsize = 32, 473 .icache_bsize = 32,
443 .dcache_bsize = 32, 474 .dcache_bsize = 32,
444 .num_pmcs = 4, 475 .num_pmcs = 4,
445 .cpu_setup = __setup_cpu_750 476 .cpu_setup = __setup_cpu_750,
477 .platform = "ppc750",
446 }, 478 },
447 { /* 750FX (All revs except 2.0) */ 479 { /* 750FX (All revs except 2.0) */
448 .pvr_mask = 0xffff0000, 480 .pvr_mask = 0xffff0000,
@@ -453,7 +485,8 @@ struct cpu_spec cpu_specs[] = {
453 .icache_bsize = 32, 485 .icache_bsize = 32,
454 .dcache_bsize = 32, 486 .dcache_bsize = 32,
455 .num_pmcs = 4, 487 .num_pmcs = 4,
456 .cpu_setup = __setup_cpu_750fx 488 .cpu_setup = __setup_cpu_750fx,
489 .platform = "ppc750",
457 }, 490 },
458 { /* 750GX */ 491 { /* 750GX */
459 .pvr_mask = 0xffff0000, 492 .pvr_mask = 0xffff0000,
@@ -464,7 +497,8 @@ struct cpu_spec cpu_specs[] = {
464 .icache_bsize = 32, 497 .icache_bsize = 32,
465 .dcache_bsize = 32, 498 .dcache_bsize = 32,
466 .num_pmcs = 4, 499 .num_pmcs = 4,
467 .cpu_setup = __setup_cpu_750fx 500 .cpu_setup = __setup_cpu_750fx,
501 .platform = "ppc750",
468 }, 502 },
469 { /* 740/750 (L2CR bit need fixup for 740) */ 503 { /* 740/750 (L2CR bit need fixup for 740) */
470 .pvr_mask = 0xffff0000, 504 .pvr_mask = 0xffff0000,
@@ -475,7 +509,8 @@ struct cpu_spec cpu_specs[] = {
475 .icache_bsize = 32, 509 .icache_bsize = 32,
476 .dcache_bsize = 32, 510 .dcache_bsize = 32,
477 .num_pmcs = 4, 511 .num_pmcs = 4,
478 .cpu_setup = __setup_cpu_750 512 .cpu_setup = __setup_cpu_750,
513 .platform = "ppc750",
479 }, 514 },
480 { /* 7400 rev 1.1 ? (no TAU) */ 515 { /* 7400 rev 1.1 ? (no TAU) */
481 .pvr_mask = 0xffffffff, 516 .pvr_mask = 0xffffffff,
@@ -486,7 +521,8 @@ struct cpu_spec cpu_specs[] = {
486 .icache_bsize = 32, 521 .icache_bsize = 32,
487 .dcache_bsize = 32, 522 .dcache_bsize = 32,
488 .num_pmcs = 4, 523 .num_pmcs = 4,
489 .cpu_setup = __setup_cpu_7400 524 .cpu_setup = __setup_cpu_7400,
525 .platform = "ppc7400",
490 }, 526 },
491 { /* 7400 */ 527 { /* 7400 */
492 .pvr_mask = 0xffff0000, 528 .pvr_mask = 0xffff0000,
@@ -497,7 +533,8 @@ struct cpu_spec cpu_specs[] = {
497 .icache_bsize = 32, 533 .icache_bsize = 32,
498 .dcache_bsize = 32, 534 .dcache_bsize = 32,
499 .num_pmcs = 4, 535 .num_pmcs = 4,
500 .cpu_setup = __setup_cpu_7400 536 .cpu_setup = __setup_cpu_7400,
537 .platform = "ppc7400",
501 }, 538 },
502 { /* 7410 */ 539 { /* 7410 */
503 .pvr_mask = 0xffff0000, 540 .pvr_mask = 0xffff0000,
@@ -508,7 +545,8 @@ struct cpu_spec cpu_specs[] = {
508 .icache_bsize = 32, 545 .icache_bsize = 32,
509 .dcache_bsize = 32, 546 .dcache_bsize = 32,
510 .num_pmcs = 4, 547 .num_pmcs = 4,
511 .cpu_setup = __setup_cpu_7410 548 .cpu_setup = __setup_cpu_7410,
549 .platform = "ppc7400",
512 }, 550 },
513 { /* 7450 2.0 - no doze/nap */ 551 { /* 7450 2.0 - no doze/nap */
514 .pvr_mask = 0xffffffff, 552 .pvr_mask = 0xffffffff,
@@ -522,6 +560,7 @@ struct cpu_spec cpu_specs[] = {
522 .cpu_setup = __setup_cpu_745x, 560 .cpu_setup = __setup_cpu_745x,
523 .oprofile_cpu_type = "ppc/7450", 561 .oprofile_cpu_type = "ppc/7450",
524 .oprofile_type = G4, 562 .oprofile_type = G4,
563 .platform = "ppc7450",
525 }, 564 },
526 { /* 7450 2.1 */ 565 { /* 7450 2.1 */
527 .pvr_mask = 0xffffffff, 566 .pvr_mask = 0xffffffff,
@@ -535,6 +574,7 @@ struct cpu_spec cpu_specs[] = {
535 .cpu_setup = __setup_cpu_745x, 574 .cpu_setup = __setup_cpu_745x,
536 .oprofile_cpu_type = "ppc/7450", 575 .oprofile_cpu_type = "ppc/7450",
537 .oprofile_type = G4, 576 .oprofile_type = G4,
577 .platform = "ppc7450",
538 }, 578 },
539 { /* 7450 2.3 and newer */ 579 { /* 7450 2.3 and newer */
540 .pvr_mask = 0xffff0000, 580 .pvr_mask = 0xffff0000,
@@ -548,6 +588,7 @@ struct cpu_spec cpu_specs[] = {
548 .cpu_setup = __setup_cpu_745x, 588 .cpu_setup = __setup_cpu_745x,
549 .oprofile_cpu_type = "ppc/7450", 589 .oprofile_cpu_type = "ppc/7450",
550 .oprofile_type = G4, 590 .oprofile_type = G4,
591 .platform = "ppc7450",
551 }, 592 },
552 { /* 7455 rev 1.x */ 593 { /* 7455 rev 1.x */
553 .pvr_mask = 0xffffff00, 594 .pvr_mask = 0xffffff00,
@@ -561,6 +602,7 @@ struct cpu_spec cpu_specs[] = {
561 .cpu_setup = __setup_cpu_745x, 602 .cpu_setup = __setup_cpu_745x,
562 .oprofile_cpu_type = "ppc/7450", 603 .oprofile_cpu_type = "ppc/7450",
563 .oprofile_type = G4, 604 .oprofile_type = G4,
605 .platform = "ppc7450",
564 }, 606 },
565 { /* 7455 rev 2.0 */ 607 { /* 7455 rev 2.0 */
566 .pvr_mask = 0xffffffff, 608 .pvr_mask = 0xffffffff,
@@ -574,6 +616,7 @@ struct cpu_spec cpu_specs[] = {
574 .cpu_setup = __setup_cpu_745x, 616 .cpu_setup = __setup_cpu_745x,
575 .oprofile_cpu_type = "ppc/7450", 617 .oprofile_cpu_type = "ppc/7450",
576 .oprofile_type = G4, 618 .oprofile_type = G4,
619 .platform = "ppc7450",
577 }, 620 },
578 { /* 7455 others */ 621 { /* 7455 others */
579 .pvr_mask = 0xffff0000, 622 .pvr_mask = 0xffff0000,
@@ -587,6 +630,7 @@ struct cpu_spec cpu_specs[] = {
587 .cpu_setup = __setup_cpu_745x, 630 .cpu_setup = __setup_cpu_745x,
588 .oprofile_cpu_type = "ppc/7450", 631 .oprofile_cpu_type = "ppc/7450",
589 .oprofile_type = G4, 632 .oprofile_type = G4,
633 .platform = "ppc7450",
590 }, 634 },
591 { /* 7447/7457 Rev 1.0 */ 635 { /* 7447/7457 Rev 1.0 */
592 .pvr_mask = 0xffffffff, 636 .pvr_mask = 0xffffffff,
@@ -600,6 +644,7 @@ struct cpu_spec cpu_specs[] = {
600 .cpu_setup = __setup_cpu_745x, 644 .cpu_setup = __setup_cpu_745x,
601 .oprofile_cpu_type = "ppc/7450", 645 .oprofile_cpu_type = "ppc/7450",
602 .oprofile_type = G4, 646 .oprofile_type = G4,
647 .platform = "ppc7450",
603 }, 648 },
604 { /* 7447/7457 Rev 1.1 */ 649 { /* 7447/7457 Rev 1.1 */
605 .pvr_mask = 0xffffffff, 650 .pvr_mask = 0xffffffff,
@@ -613,6 +658,7 @@ struct cpu_spec cpu_specs[] = {
613 .cpu_setup = __setup_cpu_745x, 658 .cpu_setup = __setup_cpu_745x,
614 .oprofile_cpu_type = "ppc/7450", 659 .oprofile_cpu_type = "ppc/7450",
615 .oprofile_type = G4, 660 .oprofile_type = G4,
661 .platform = "ppc7450",
616 }, 662 },
617 { /* 7447/7457 Rev 1.2 and later */ 663 { /* 7447/7457 Rev 1.2 and later */
618 .pvr_mask = 0xffff0000, 664 .pvr_mask = 0xffff0000,
@@ -626,6 +672,7 @@ struct cpu_spec cpu_specs[] = {
626 .cpu_setup = __setup_cpu_745x, 672 .cpu_setup = __setup_cpu_745x,
627 .oprofile_cpu_type = "ppc/7450", 673 .oprofile_cpu_type = "ppc/7450",
628 .oprofile_type = G4, 674 .oprofile_type = G4,
675 .platform = "ppc7450",
629 }, 676 },
630 { /* 7447A */ 677 { /* 7447A */
631 .pvr_mask = 0xffff0000, 678 .pvr_mask = 0xffff0000,
@@ -639,6 +686,7 @@ struct cpu_spec cpu_specs[] = {
639 .cpu_setup = __setup_cpu_745x, 686 .cpu_setup = __setup_cpu_745x,
640 .oprofile_cpu_type = "ppc/7450", 687 .oprofile_cpu_type = "ppc/7450",
641 .oprofile_type = G4, 688 .oprofile_type = G4,
689 .platform = "ppc7450",
642 }, 690 },
643 { /* 7448 */ 691 { /* 7448 */
644 .pvr_mask = 0xffff0000, 692 .pvr_mask = 0xffff0000,
@@ -652,6 +700,7 @@ struct cpu_spec cpu_specs[] = {
652 .cpu_setup = __setup_cpu_745x, 700 .cpu_setup = __setup_cpu_745x,
653 .oprofile_cpu_type = "ppc/7450", 701 .oprofile_cpu_type = "ppc/7450",
654 .oprofile_type = G4, 702 .oprofile_type = G4,
703 .platform = "ppc7450",
655 }, 704 },
656 { /* 82xx (8240, 8245, 8260 are all 603e cores) */ 705 { /* 82xx (8240, 8245, 8260 are all 603e cores) */
657 .pvr_mask = 0x7fff0000, 706 .pvr_mask = 0x7fff0000,
@@ -661,7 +710,8 @@ struct cpu_spec cpu_specs[] = {
661 .cpu_user_features = COMMON_USER, 710 .cpu_user_features = COMMON_USER,
662 .icache_bsize = 32, 711 .icache_bsize = 32,
663 .dcache_bsize = 32, 712 .dcache_bsize = 32,
664 .cpu_setup = __setup_cpu_603 713 .cpu_setup = __setup_cpu_603,
714 .platform = "ppc603",
665 }, 715 },
666 { /* All G2_LE (603e core, plus some) have the same pvr */ 716 { /* All G2_LE (603e core, plus some) have the same pvr */
667 .pvr_mask = 0x7fff0000, 717 .pvr_mask = 0x7fff0000,
@@ -671,7 +721,8 @@ struct cpu_spec cpu_specs[] = {
671 .cpu_user_features = COMMON_USER, 721 .cpu_user_features = COMMON_USER,
672 .icache_bsize = 32, 722 .icache_bsize = 32,
673 .dcache_bsize = 32, 723 .dcache_bsize = 32,
674 .cpu_setup = __setup_cpu_603 724 .cpu_setup = __setup_cpu_603,
725 .platform = "ppc603",
675 }, 726 },
676 { /* e300 (a 603e core, plus some) on 83xx */ 727 { /* e300 (a 603e core, plus some) on 83xx */
677 .pvr_mask = 0x7fff0000, 728 .pvr_mask = 0x7fff0000,
@@ -681,7 +732,8 @@ struct cpu_spec cpu_specs[] = {
681 .cpu_user_features = COMMON_USER, 732 .cpu_user_features = COMMON_USER,
682 .icache_bsize = 32, 733 .icache_bsize = 32,
683 .dcache_bsize = 32, 734 .dcache_bsize = 32,
684 .cpu_setup = __setup_cpu_603 735 .cpu_setup = __setup_cpu_603,
736 .platform = "ppc603",
685 }, 737 },
686 { /* default match, we assume split I/D cache & TB (non-601)... */ 738 { /* default match, we assume split I/D cache & TB (non-601)... */
687 .pvr_mask = 0x00000000, 739 .pvr_mask = 0x00000000,
@@ -691,6 +743,7 @@ struct cpu_spec cpu_specs[] = {
691 .cpu_user_features = COMMON_USER, 743 .cpu_user_features = COMMON_USER,
692 .icache_bsize = 32, 744 .icache_bsize = 32,
693 .dcache_bsize = 32, 745 .dcache_bsize = 32,
746 .platform = "ppc603",
694 }, 747 },
695#endif /* CLASSIC_PPC */ 748#endif /* CLASSIC_PPC */
696#ifdef CONFIG_8xx 749#ifdef CONFIG_8xx
@@ -704,6 +757,7 @@ struct cpu_spec cpu_specs[] = {
704 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 757 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
705 .icache_bsize = 16, 758 .icache_bsize = 16,
706 .dcache_bsize = 16, 759 .dcache_bsize = 16,
760 .platform = "ppc823",
707 }, 761 },
708#endif /* CONFIG_8xx */ 762#endif /* CONFIG_8xx */
709#ifdef CONFIG_40x 763#ifdef CONFIG_40x
@@ -715,6 +769,7 @@ struct cpu_spec cpu_specs[] = {
715 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 769 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
716 .icache_bsize = 16, 770 .icache_bsize = 16,
717 .dcache_bsize = 16, 771 .dcache_bsize = 16,
772 .platform = "ppc403",
718 }, 773 },
719 { /* 403GCX */ 774 { /* 403GCX */
720 .pvr_mask = 0xffffff00, 775 .pvr_mask = 0xffffff00,
@@ -725,6 +780,7 @@ struct cpu_spec cpu_specs[] = {
725 PPC_FEATURE_HAS_MMU | PPC_FEATURE_NO_TB, 780 PPC_FEATURE_HAS_MMU | PPC_FEATURE_NO_TB,
726 .icache_bsize = 16, 781 .icache_bsize = 16,
727 .dcache_bsize = 16, 782 .dcache_bsize = 16,
783 .platform = "ppc403",
728 }, 784 },
729 { /* 403G ?? */ 785 { /* 403G ?? */
730 .pvr_mask = 0xffff0000, 786 .pvr_mask = 0xffff0000,
@@ -734,6 +790,7 @@ struct cpu_spec cpu_specs[] = {
734 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 790 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
735 .icache_bsize = 16, 791 .icache_bsize = 16,
736 .dcache_bsize = 16, 792 .dcache_bsize = 16,
793 .platform = "ppc403",
737 }, 794 },
738 { /* 405GP */ 795 { /* 405GP */
739 .pvr_mask = 0xffff0000, 796 .pvr_mask = 0xffff0000,
@@ -744,6 +801,7 @@ struct cpu_spec cpu_specs[] = {
744 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 801 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
745 .icache_bsize = 32, 802 .icache_bsize = 32,
746 .dcache_bsize = 32, 803 .dcache_bsize = 32,
804 .platform = "ppc405",
747 }, 805 },
748 { /* STB 03xxx */ 806 { /* STB 03xxx */
749 .pvr_mask = 0xffff0000, 807 .pvr_mask = 0xffff0000,
@@ -754,6 +812,7 @@ struct cpu_spec cpu_specs[] = {
754 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 812 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
755 .icache_bsize = 32, 813 .icache_bsize = 32,
756 .dcache_bsize = 32, 814 .dcache_bsize = 32,
815 .platform = "ppc405",
757 }, 816 },
758 { /* STB 04xxx */ 817 { /* STB 04xxx */
759 .pvr_mask = 0xffff0000, 818 .pvr_mask = 0xffff0000,
@@ -764,6 +823,7 @@ struct cpu_spec cpu_specs[] = {
764 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 823 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
765 .icache_bsize = 32, 824 .icache_bsize = 32,
766 .dcache_bsize = 32, 825 .dcache_bsize = 32,
826 .platform = "ppc405",
767 }, 827 },
768 { /* NP405L */ 828 { /* NP405L */
769 .pvr_mask = 0xffff0000, 829 .pvr_mask = 0xffff0000,
@@ -774,6 +834,7 @@ struct cpu_spec cpu_specs[] = {
774 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 834 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
775 .icache_bsize = 32, 835 .icache_bsize = 32,
776 .dcache_bsize = 32, 836 .dcache_bsize = 32,
837 .platform = "ppc405",
777 }, 838 },
778 { /* NP4GS3 */ 839 { /* NP4GS3 */
779 .pvr_mask = 0xffff0000, 840 .pvr_mask = 0xffff0000,
@@ -784,6 +845,7 @@ struct cpu_spec cpu_specs[] = {
784 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 845 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
785 .icache_bsize = 32, 846 .icache_bsize = 32,
786 .dcache_bsize = 32, 847 .dcache_bsize = 32,
848 .platform = "ppc405",
787 }, 849 },
788 { /* NP405H */ 850 { /* NP405H */
789 .pvr_mask = 0xffff0000, 851 .pvr_mask = 0xffff0000,
@@ -794,6 +856,7 @@ struct cpu_spec cpu_specs[] = {
794 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 856 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
795 .icache_bsize = 32, 857 .icache_bsize = 32,
796 .dcache_bsize = 32, 858 .dcache_bsize = 32,
859 .platform = "ppc405",
797 }, 860 },
798 { /* 405GPr */ 861 { /* 405GPr */
799 .pvr_mask = 0xffff0000, 862 .pvr_mask = 0xffff0000,
@@ -804,6 +867,7 @@ struct cpu_spec cpu_specs[] = {
804 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 867 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
805 .icache_bsize = 32, 868 .icache_bsize = 32,
806 .dcache_bsize = 32, 869 .dcache_bsize = 32,
870 .platform = "ppc405",
807 }, 871 },
808 { /* STBx25xx */ 872 { /* STBx25xx */
809 .pvr_mask = 0xffff0000, 873 .pvr_mask = 0xffff0000,
@@ -814,6 +878,7 @@ struct cpu_spec cpu_specs[] = {
814 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 878 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
815 .icache_bsize = 32, 879 .icache_bsize = 32,
816 .dcache_bsize = 32, 880 .dcache_bsize = 32,
881 .platform = "ppc405",
817 }, 882 },
818 { /* 405LP */ 883 { /* 405LP */
819 .pvr_mask = 0xffff0000, 884 .pvr_mask = 0xffff0000,
@@ -823,6 +888,7 @@ struct cpu_spec cpu_specs[] = {
823 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 888 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
824 .icache_bsize = 32, 889 .icache_bsize = 32,
825 .dcache_bsize = 32, 890 .dcache_bsize = 32,
891 .platform = "ppc405",
826 }, 892 },
827 { /* Xilinx Virtex-II Pro */ 893 { /* Xilinx Virtex-II Pro */
828 .pvr_mask = 0xffff0000, 894 .pvr_mask = 0xffff0000,
@@ -833,6 +899,7 @@ struct cpu_spec cpu_specs[] = {
833 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 899 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
834 .icache_bsize = 32, 900 .icache_bsize = 32,
835 .dcache_bsize = 32, 901 .dcache_bsize = 32,
902 .platform = "ppc405",
836 }, 903 },
837 { /* 405EP */ 904 { /* 405EP */
838 .pvr_mask = 0xffff0000, 905 .pvr_mask = 0xffff0000,
@@ -843,6 +910,7 @@ struct cpu_spec cpu_specs[] = {
843 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 910 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
844 .icache_bsize = 32, 911 .icache_bsize = 32,
845 .dcache_bsize = 32, 912 .dcache_bsize = 32,
913 .platform = "ppc405",
846 }, 914 },
847 915
848#endif /* CONFIG_40x */ 916#endif /* CONFIG_40x */
@@ -852,81 +920,90 @@ struct cpu_spec cpu_specs[] = {
852 .pvr_value = 0x40000850, 920 .pvr_value = 0x40000850,
853 .cpu_name = "440EP Rev. A", 921 .cpu_name = "440EP Rev. A",
854 .cpu_features = CPU_FTRS_44X, 922 .cpu_features = CPU_FTRS_44X,
855 .cpu_user_features = COMMON_USER, /* 440EP has an FPU */ 923 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
856 .icache_bsize = 32, 924 .icache_bsize = 32,
857 .dcache_bsize = 32, 925 .dcache_bsize = 32,
926 .platform = "ppc440",
858 }, 927 },
859 { 928 {
860 .pvr_mask = 0xf0000fff, 929 .pvr_mask = 0xf0000fff,
861 .pvr_value = 0x400008d3, 930 .pvr_value = 0x400008d3,
862 .cpu_name = "440EP Rev. B", 931 .cpu_name = "440EP Rev. B",
863 .cpu_features = CPU_FTRS_44X, 932 .cpu_features = CPU_FTRS_44X,
864 .cpu_user_features = COMMON_USER, /* 440EP has an FPU */ 933 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
865 .icache_bsize = 32, 934 .icache_bsize = 32,
866 .dcache_bsize = 32, 935 .dcache_bsize = 32,
936 .platform = "ppc440",
867 }, 937 },
868 { /* 440GP Rev. B */ 938 { /* 440GP Rev. B */
869 .pvr_mask = 0xf0000fff, 939 .pvr_mask = 0xf0000fff,
870 .pvr_value = 0x40000440, 940 .pvr_value = 0x40000440,
871 .cpu_name = "440GP Rev. B", 941 .cpu_name = "440GP Rev. B",
872 .cpu_features = CPU_FTRS_44X, 942 .cpu_features = CPU_FTRS_44X,
873 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 943 .cpu_user_features = COMMON_USER_BOOKE,
874 .icache_bsize = 32, 944 .icache_bsize = 32,
875 .dcache_bsize = 32, 945 .dcache_bsize = 32,
946 .platform = "ppc440gp",
876 }, 947 },
877 { /* 440GP Rev. C */ 948 { /* 440GP Rev. C */
878 .pvr_mask = 0xf0000fff, 949 .pvr_mask = 0xf0000fff,
879 .pvr_value = 0x40000481, 950 .pvr_value = 0x40000481,
880 .cpu_name = "440GP Rev. C", 951 .cpu_name = "440GP Rev. C",
881 .cpu_features = CPU_FTRS_44X, 952 .cpu_features = CPU_FTRS_44X,
882 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 953 .cpu_user_features = COMMON_USER_BOOKE,
883 .icache_bsize = 32, 954 .icache_bsize = 32,
884 .dcache_bsize = 32, 955 .dcache_bsize = 32,
956 .platform = "ppc440gp",
885 }, 957 },
886 { /* 440GX Rev. A */ 958 { /* 440GX Rev. A */
887 .pvr_mask = 0xf0000fff, 959 .pvr_mask = 0xf0000fff,
888 .pvr_value = 0x50000850, 960 .pvr_value = 0x50000850,
889 .cpu_name = "440GX Rev. A", 961 .cpu_name = "440GX Rev. A",
890 .cpu_features = CPU_FTRS_44X, 962 .cpu_features = CPU_FTRS_44X,
891 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 963 .cpu_user_features = COMMON_USER_BOOKE,
892 .icache_bsize = 32, 964 .icache_bsize = 32,
893 .dcache_bsize = 32, 965 .dcache_bsize = 32,
966 .platform = "ppc440",
894 }, 967 },
895 { /* 440GX Rev. B */ 968 { /* 440GX Rev. B */
896 .pvr_mask = 0xf0000fff, 969 .pvr_mask = 0xf0000fff,
897 .pvr_value = 0x50000851, 970 .pvr_value = 0x50000851,
898 .cpu_name = "440GX Rev. B", 971 .cpu_name = "440GX Rev. B",
899 .cpu_features = CPU_FTRS_44X, 972 .cpu_features = CPU_FTRS_44X,
900 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 973 .cpu_user_features = COMMON_USER_BOOKE,
901 .icache_bsize = 32, 974 .icache_bsize = 32,
902 .dcache_bsize = 32, 975 .dcache_bsize = 32,
976 .platform = "ppc440",
903 }, 977 },
904 { /* 440GX Rev. C */ 978 { /* 440GX Rev. C */
905 .pvr_mask = 0xf0000fff, 979 .pvr_mask = 0xf0000fff,
906 .pvr_value = 0x50000892, 980 .pvr_value = 0x50000892,
907 .cpu_name = "440GX Rev. C", 981 .cpu_name = "440GX Rev. C",
908 .cpu_features = CPU_FTRS_44X, 982 .cpu_features = CPU_FTRS_44X,
909 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 983 .cpu_user_features = COMMON_USER_BOOKE,
910 .icache_bsize = 32, 984 .icache_bsize = 32,
911 .dcache_bsize = 32, 985 .dcache_bsize = 32,
986 .platform = "ppc440",
912 }, 987 },
913 { /* 440GX Rev. F */ 988 { /* 440GX Rev. F */
914 .pvr_mask = 0xf0000fff, 989 .pvr_mask = 0xf0000fff,
915 .pvr_value = 0x50000894, 990 .pvr_value = 0x50000894,
916 .cpu_name = "440GX Rev. F", 991 .cpu_name = "440GX Rev. F",
917 .cpu_features = CPU_FTRS_44X, 992 .cpu_features = CPU_FTRS_44X,
918 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 993 .cpu_user_features = COMMON_USER_BOOKE,
919 .icache_bsize = 32, 994 .icache_bsize = 32,
920 .dcache_bsize = 32, 995 .dcache_bsize = 32,
996 .platform = "ppc440",
921 }, 997 },
922 { /* 440SP Rev. A */ 998 { /* 440SP Rev. A */
923 .pvr_mask = 0xff000fff, 999 .pvr_mask = 0xff000fff,
924 .pvr_value = 0x53000891, 1000 .pvr_value = 0x53000891,
925 .cpu_name = "440SP Rev. A", 1001 .cpu_name = "440SP Rev. A",
926 .cpu_features = CPU_FTRS_44X, 1002 .cpu_features = CPU_FTRS_44X,
927 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 1003 .cpu_user_features = COMMON_USER_BOOKE,
928 .icache_bsize = 32, 1004 .icache_bsize = 32,
929 .dcache_bsize = 32, 1005 .dcache_bsize = 32,
1006 .platform = "ppc440",
930 }, 1007 },
931 { /* 440SPe Rev. A */ 1008 { /* 440SPe Rev. A */
932 .pvr_mask = 0xff000fff, 1009 .pvr_mask = 0xff000fff,
@@ -934,9 +1011,10 @@ struct cpu_spec cpu_specs[] = {
934 .cpu_name = "440SPe Rev. A", 1011 .cpu_name = "440SPe Rev. A",
935 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 1012 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
936 CPU_FTR_USE_TB, 1013 CPU_FTR_USE_TB,
937 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 1014 .cpu_user_features = COMMON_USER_BOOKE,
938 .icache_bsize = 32, 1015 .icache_bsize = 32,
939 .dcache_bsize = 32, 1016 .dcache_bsize = 32,
1017 .platform = "ppc440",
940 }, 1018 },
941#endif /* CONFIG_44x */ 1019#endif /* CONFIG_44x */
942#ifdef CONFIG_FSL_BOOKE 1020#ifdef CONFIG_FSL_BOOKE
@@ -946,10 +1024,11 @@ struct cpu_spec cpu_specs[] = {
946 .cpu_name = "e200z5", 1024 .cpu_name = "e200z5",
947 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */ 1025 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
948 .cpu_features = CPU_FTRS_E200, 1026 .cpu_features = CPU_FTRS_E200,
949 .cpu_user_features = PPC_FEATURE_32 | 1027 .cpu_user_features = COMMON_USER_BOOKE |
950 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_EFP_SINGLE | 1028 PPC_FEATURE_HAS_EFP_SINGLE |
951 PPC_FEATURE_UNIFIED_CACHE, 1029 PPC_FEATURE_UNIFIED_CACHE,
952 .dcache_bsize = 32, 1030 .dcache_bsize = 32,
1031 .platform = "ppc5554",
953 }, 1032 },
954 { /* e200z6 */ 1033 { /* e200z6 */
955 .pvr_mask = 0xfff00000, 1034 .pvr_mask = 0xfff00000,
@@ -957,11 +1036,12 @@ struct cpu_spec cpu_specs[] = {
957 .cpu_name = "e200z6", 1036 .cpu_name = "e200z6",
958 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */ 1037 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
959 .cpu_features = CPU_FTRS_E200, 1038 .cpu_features = CPU_FTRS_E200,
960 .cpu_user_features = PPC_FEATURE_32 | 1039 .cpu_user_features = COMMON_USER_BOOKE |
961 PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP | 1040 PPC_FEATURE_SPE_COMP |
962 PPC_FEATURE_HAS_EFP_SINGLE | 1041 PPC_FEATURE_HAS_EFP_SINGLE |
963 PPC_FEATURE_UNIFIED_CACHE, 1042 PPC_FEATURE_UNIFIED_CACHE,
964 .dcache_bsize = 32, 1043 .dcache_bsize = 32,
1044 .platform = "ppc5554",
965 }, 1045 },
966 { /* e500 */ 1046 { /* e500 */
967 .pvr_mask = 0xffff0000, 1047 .pvr_mask = 0xffff0000,
@@ -969,14 +1049,15 @@ struct cpu_spec cpu_specs[] = {
969 .cpu_name = "e500", 1049 .cpu_name = "e500",
970 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */ 1050 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
971 .cpu_features = CPU_FTRS_E500, 1051 .cpu_features = CPU_FTRS_E500,
972 .cpu_user_features = PPC_FEATURE_32 | 1052 .cpu_user_features = COMMON_USER_BOOKE |
973 PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP | 1053 PPC_FEATURE_SPE_COMP |
974 PPC_FEATURE_HAS_EFP_SINGLE, 1054 PPC_FEATURE_HAS_EFP_SINGLE,
975 .icache_bsize = 32, 1055 .icache_bsize = 32,
976 .dcache_bsize = 32, 1056 .dcache_bsize = 32,
977 .num_pmcs = 4, 1057 .num_pmcs = 4,
978 .oprofile_cpu_type = "ppc/e500", 1058 .oprofile_cpu_type = "ppc/e500",
979 .oprofile_type = BOOKE, 1059 .oprofile_type = BOOKE,
1060 .platform = "ppc8540",
980 }, 1061 },
981 { /* e500v2 */ 1062 { /* e500v2 */
982 .pvr_mask = 0xffff0000, 1063 .pvr_mask = 0xffff0000,
@@ -984,14 +1065,16 @@ struct cpu_spec cpu_specs[] = {
984 .cpu_name = "e500v2", 1065 .cpu_name = "e500v2",
985 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */ 1066 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
986 .cpu_features = CPU_FTRS_E500_2, 1067 .cpu_features = CPU_FTRS_E500_2,
987 .cpu_user_features = PPC_FEATURE_32 | 1068 .cpu_user_features = COMMON_USER_BOOKE |
988 PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP | 1069 PPC_FEATURE_SPE_COMP |
989 PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_HAS_EFP_DOUBLE, 1070 PPC_FEATURE_HAS_EFP_SINGLE |
1071 PPC_FEATURE_HAS_EFP_DOUBLE,
990 .icache_bsize = 32, 1072 .icache_bsize = 32,
991 .dcache_bsize = 32, 1073 .dcache_bsize = 32,
992 .num_pmcs = 4, 1074 .num_pmcs = 4,
993 .oprofile_cpu_type = "ppc/e500", 1075 .oprofile_cpu_type = "ppc/e500",
994 .oprofile_type = BOOKE, 1076 .oprofile_type = BOOKE,
1077 .platform = "ppc8548",
995 }, 1078 },
996#endif 1079#endif
997#if !CLASSIC_PPC 1080#if !CLASSIC_PPC
@@ -1003,6 +1086,7 @@ struct cpu_spec cpu_specs[] = {
1003 .cpu_user_features = PPC_FEATURE_32, 1086 .cpu_user_features = PPC_FEATURE_32,
1004 .icache_bsize = 32, 1087 .icache_bsize = 32,
1005 .dcache_bsize = 32, 1088 .dcache_bsize = 32,
1089 .platform = "powerpc",
1006 } 1090 }
1007#endif /* !CLASSIC_PPC */ 1091#endif /* !CLASSIC_PPC */
1008#endif /* CONFIG_PPC32 */ 1092#endif /* CONFIG_PPC32 */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-20 07:54:51 -0500