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authorJassi Brar <jassi.brar@samsung.com>2009-11-04 23:44:45 -0500
committerBen Dooks <ben-linux@fluff.org>2009-11-09 18:50:42 -0500
commit7507f39c57d4a285aea11c379fbc65c2b3f375ef (patch)
treebbc206d771b2f43f9cabe5f9bfd8dc47d8b6eb46 /arch
parent6d0b8627d545aed7d4bcaad2156b6cb95e105715 (diff)
ARM: S3C64XX: DMA: Make src and dst transfer size same
Some devices don't seem to work if the source and desitnation transfer widths are not same. For example, SPI dma xfers, with 8bits/word, don't work without this patch. Signed-off-by: Jassi Brar <jassi.brar@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/plat-s3c64xx/dma.c6
1 files changed, 2 insertions, 4 deletions
diff --git a/arch/arm/plat-s3c64xx/dma.c b/arch/arm/plat-s3c64xx/dma.c
index 5a08a86419dd..a94281bb84d6 100644
--- a/arch/arm/plat-s3c64xx/dma.c
+++ b/arch/arm/plat-s3c64xx/dma.c
@@ -151,8 +151,6 @@ static void s3c64xx_dma_fill_lli(struct s3c2410_dma_chan *chan,
151 src = chan->dev_addr; 151 src = chan->dev_addr;
152 dst = data; 152 dst = data;
153 control0 = PL080_CONTROL_SRC_AHB2; 153 control0 = PL080_CONTROL_SRC_AHB2;
154 control0 |= (u32)chan->hw_width << PL080_CONTROL_SWIDTH_SHIFT;
155 control0 |= 2 << PL080_CONTROL_DWIDTH_SHIFT;
156 control0 |= PL080_CONTROL_DST_INCR; 154 control0 |= PL080_CONTROL_DST_INCR;
157 break; 155 break;
158 156
@@ -160,8 +158,6 @@ static void s3c64xx_dma_fill_lli(struct s3c2410_dma_chan *chan,
160 src = data; 158 src = data;
161 dst = chan->dev_addr; 159 dst = chan->dev_addr;
162 control0 = PL080_CONTROL_DST_AHB2; 160 control0 = PL080_CONTROL_DST_AHB2;
163 control0 |= (u32)chan->hw_width << PL080_CONTROL_DWIDTH_SHIFT;
164 control0 |= 2 << PL080_CONTROL_SWIDTH_SHIFT;
165 control0 |= PL080_CONTROL_SRC_INCR; 161 control0 |= PL080_CONTROL_SRC_INCR;
166 break; 162 break;
167 default: 163 default:
@@ -173,6 +169,8 @@ static void s3c64xx_dma_fill_lli(struct s3c2410_dma_chan *chan,
173 control1 = size >> chan->hw_width; /* size in no of xfers */ 169 control1 = size >> chan->hw_width; /* size in no of xfers */
174 control0 |= PL080_CONTROL_PROT_SYS; /* always in priv. mode */ 170 control0 |= PL080_CONTROL_PROT_SYS; /* always in priv. mode */
175 control0 |= PL080_CONTROL_TC_IRQ_EN; /* always fire IRQ */ 171 control0 |= PL080_CONTROL_TC_IRQ_EN; /* always fire IRQ */
172 control0 |= (u32)chan->hw_width << PL080_CONTROL_DWIDTH_SHIFT;
173 control0 |= (u32)chan->hw_width << PL080_CONTROL_SWIDTH_SHIFT;
176 174
177 lli->src_addr = src; 175 lli->src_addr = src;
178 lli->dst_addr = dst; 176 lli->dst_addr = dst;